Bug Summary

File:dev/pci/drm/amd/amdgpu/dce_v11_0.c
Warning:line 3093, column 3
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dce_v11_0.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/dce_v11_0.c
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fourcc.h>
25#include <drm/drm_vblank.h>
26
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_i2c.h"
30#include "vid.h"
31#include "atom.h"
32#include "amdgpu_atombios.h"
33#include "atombios_crtc.h"
34#include "atombios_encoders.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37#include "amdgpu_display.h"
38#include "dce_v11_0.h"
39
40#include "dce/dce_11_0_d.h"
41#include "dce/dce_11_0_sh_mask.h"
42#include "dce/dce_11_0_enum.h"
43#include "oss/oss_3_0_d.h"
44#include "oss/oss_3_0_sh_mask.h"
45#include "gmc/gmc_8_1_d.h"
46#include "gmc/gmc_8_1_sh_mask.h"
47
48#include "ivsrcid/ivsrcid_vislands30.h"
49
50static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
51static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
52
53static const u32 crtc_offsets[] =
54{
55 CRTC0_REGISTER_OFFSET(0x1b9c - 0x1b9c),
56 CRTC1_REGISTER_OFFSET(0x1d9c - 0x1b9c),
57 CRTC2_REGISTER_OFFSET(0x1f9c - 0x1b9c),
58 CRTC3_REGISTER_OFFSET(0x419c - 0x1b9c),
59 CRTC4_REGISTER_OFFSET(0x439c - 0x1b9c),
60 CRTC5_REGISTER_OFFSET(0x459c - 0x1b9c),
61 CRTC6_REGISTER_OFFSET(0x479c - 0x1b9c)
62};
63
64static const u32 hpd_offsets[] =
65{
66 HPD0_REGISTER_OFFSET(0x1898 - 0x1898),
67 HPD1_REGISTER_OFFSET(0x18a0 - 0x1898),
68 HPD2_REGISTER_OFFSET(0x18a8 - 0x1898),
69 HPD3_REGISTER_OFFSET(0x18b0 - 0x1898),
70 HPD4_REGISTER_OFFSET(0x18b8 - 0x1898),
71 HPD5_REGISTER_OFFSET(0x18c0 - 0x1898)
72};
73
74static const uint32_t dig_offsets[] = {
75 DIG0_REGISTER_OFFSET(0x4a00 - 0x4a00),
76 DIG1_REGISTER_OFFSET(0x4b00 - 0x4a00),
77 DIG2_REGISTER_OFFSET(0x4c00 - 0x4a00),
78 DIG3_REGISTER_OFFSET(0x4d00 - 0x4a00),
79 DIG4_REGISTER_OFFSET(0x4e00 - 0x4a00),
80 DIG5_REGISTER_OFFSET(0x4f00 - 0x4a00),
81 DIG6_REGISTER_OFFSET(0x5400 - 0x4a00),
82 DIG7_REGISTER_OFFSET(0x5600 - 0x4a00),
83 DIG8_REGISTER_OFFSET(0x5700 - 0x4a00)
84};
85
86static const struct {
87 uint32_t reg;
88 uint32_t vblank;
89 uint32_t vline;
90 uint32_t hpd;
91
92} interrupt_status_offsets[] = { {
93 .reg = mmDISP_INTERRUPT_STATUS0x1857,
94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK0x8,
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK0x4,
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK0x20000
97}, {
98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE0x1858,
99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK0x8,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK0x4,
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK0x20000
102}, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE20x1859,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK0x8,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK0x4,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK0x20000
107}, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE30x185a,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK0x8,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK0x4,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK0x20000
112}, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE40x185b,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK0x8,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK0x4,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK0x20000
117}, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE50x185c,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK0x8,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK0x4,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK0x20000
122} };
123
124static const u32 cz_golden_settings_a11[] =
125{
126 mmCRTC_DOUBLE_BUFFER_CONTROL0x1bb6, 0x00010101, 0x00010000,
127 mmFBC_MISC0x2a2, 0x1f311fff, 0x14300000,
128};
129
130static const u32 cz_mgcg_cgcg_init[] =
131{
132 mmXDMA_CLOCK_GATING_CNTL0x3e4, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL0x3e6, 0x00000101, 0x00000000,
134};
135
136static const u32 stoney_golden_settings_a11[] =
137{
138 mmCRTC_DOUBLE_BUFFER_CONTROL0x1bb6, 0x00010101, 0x00010000,
139 mmFBC_MISC0x2a2, 0x1f311fff, 0x14302000,
140};
141
142static const u32 polaris11_golden_settings_a11[] =
143{
144 mmDCI_CLK_CNTL0x319, 0x00000080, 0x00000000,
145 mmFBC_DEBUG_COMP0x29c, 0x000000f0, 0x00000070,
146 mmFBC_DEBUG10x287, 0xffffffff, 0x00000008,
147 mmFBC_MISC0x2a2, 0x9f313fff, 0x14302008,
148 mmHDMI_CONTROL0x4a09, 0x313f031f, 0x00000011,
149};
150
151static const u32 polaris10_golden_settings_a11[] =
152{
153 mmDCI_CLK_CNTL0x319, 0x00000080, 0x00000000,
154 mmFBC_DEBUG_COMP0x29c, 0x000000f0, 0x00000070,
155 mmFBC_MISC0x2a2, 0x9f313fff, 0x14302008,
156 mmHDMI_CONTROL0x4a09, 0x313f031f, 0x00000011,
157};
158
159static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
160{
161 switch (adev->asic_type) {
162 case CHIP_CARRIZO:
163 amdgpu_device_program_register_sequence(adev,
164 cz_mgcg_cgcg_init,
165 ARRAY_SIZE(cz_mgcg_cgcg_init)(sizeof((cz_mgcg_cgcg_init)) / sizeof((cz_mgcg_cgcg_init)[0])
));
166 amdgpu_device_program_register_sequence(adev,
167 cz_golden_settings_a11,
168 ARRAY_SIZE(cz_golden_settings_a11)(sizeof((cz_golden_settings_a11)) / sizeof((cz_golden_settings_a11
)[0])));
169 break;
170 case CHIP_STONEY:
171 amdgpu_device_program_register_sequence(adev,
172 stoney_golden_settings_a11,
173 ARRAY_SIZE(stoney_golden_settings_a11)(sizeof((stoney_golden_settings_a11)) / sizeof((stoney_golden_settings_a11
)[0])));
174 break;
175 case CHIP_POLARIS11:
176 case CHIP_POLARIS12:
177 amdgpu_device_program_register_sequence(adev,
178 polaris11_golden_settings_a11,
179 ARRAY_SIZE(polaris11_golden_settings_a11)(sizeof((polaris11_golden_settings_a11)) / sizeof((polaris11_golden_settings_a11
)[0])));
180 break;
181 case CHIP_POLARIS10:
182 case CHIP_VEGAM:
183 amdgpu_device_program_register_sequence(adev,
184 polaris10_golden_settings_a11,
185 ARRAY_SIZE(polaris10_golden_settings_a11)(sizeof((polaris10_golden_settings_a11)) / sizeof((polaris10_golden_settings_a11
)[0])));
186 break;
187 default:
188 break;
189 }
190}
191
192static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
193 u32 block_offset, u32 reg)
194{
195 unsigned long flags;
196 u32 r;
197
198 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags)do { flags = 0; mtx_enter(&adev->audio_endpt_idx_lock)
; } while (0);
199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg)amdgpu_device_wreg(adev, (0x17a8 + block_offset), (reg), 0);
200 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset)amdgpu_device_rreg(adev, (0x17a9 + block_offset), 0);
201 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->audio_endpt_idx_lock
); } while (0);
202
203 return r;
204}
205
206static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
207 u32 block_offset, u32 reg, u32 v)
208{
209 unsigned long flags;
210
211 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags)do { flags = 0; mtx_enter(&adev->audio_endpt_idx_lock)
; } while (0);
212 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg)amdgpu_device_wreg(adev, (0x17a8 + block_offset), (reg), 0);
213 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v)amdgpu_device_wreg(adev, (0x17a9 + block_offset), (v), 0);
214 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags)do { (void)(flags); mtx_leave(&adev->audio_endpt_idx_lock
); } while (0);
215}
216
217static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
218{
219 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
220 return 0;
221 else
222 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ba6 + crtc_offsets[crtc]), 0);
223}
224
225static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
226{
227 unsigned i;
228
229 /* Enable pflip interrupts */
230 for (i = 0; i < adev->mode_info.num_crtc; i++)
231 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
232}
233
234static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
235{
236 unsigned i;
237
238 /* Disable pflip interrupts */
239 for (i = 0; i < adev->mode_info.num_crtc; i++)
240 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
241}
242
243/**
244 * dce_v11_0_page_flip - pageflip callback.
245 *
246 * @adev: amdgpu_device pointer
247 * @crtc_id: crtc to cleanup pageflip on
248 * @crtc_base: new address of the crtc (GPU MC address)
249 *
250 * Triggers the actual pageflip by updating the primary
251 * surface base address.
252 */
253static void dce_v11_0_page_flip(struct amdgpu_device *adev,
254 int crtc_id, u64 crtc_base, bool_Bool async)
255{
256 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
257 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
258 u32 tmp;
259
260 /* flip immediate for async, default is vsync */
261 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), 0);
262 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,(((tmp) & ~0x10) | (0x10 & ((async ? 1 : 0) << 0x4
)))
263 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0)(((tmp) & ~0x10) | (0x10 & ((async ? 1 : 0) << 0x4
)));
264 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), (tmp), 0);
265 /* update pitch */
266 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset
), (fb->pitches[0] / fb->format->cpp[0]), 0)
267 fb->pitches[0] / fb->format->cpp[0])amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset
), (fb->pitches[0] / fb->format->cpp[0]), 0);
268 /* update the scanout addresses */
269 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((crtc_base) >> 16) >> 16))), 0)
270 upper_32_bits(crtc_base))amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((crtc_base) >> 16) >> 16))), 0);
271 /* writing to the low address triggers the update */
272 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), (((u32)(crtc_base))), 0)
273 lower_32_bits(crtc_base))amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), (((u32)(crtc_base))), 0);
274 /* post the write */
275 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), 0);
276}
277
278static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
279 u32 *vbl, u32 *position)
280{
281 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
282 return -EINVAL22;
283
284 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1b8d + crtc_offsets[crtc]), 0);
285 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ba4 + crtc_offsets[crtc]), 0);
286
287 return 0;
288}
289
290/**
291 * dce_v11_0_hpd_sense - hpd sense callback.
292 *
293 * @adev: amdgpu_device pointer
294 * @hpd: hpd (hotplug detect) pin
295 *
296 * Checks if a digital monitor is connected (evergreen+).
297 * Returns true if connected, false if not connected.
298 */
299static bool_Bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
300 enum amdgpu_hpd_id hpd)
301{
302 bool_Bool connected = false0;
303
304 if (hpd >= adev->mode_info.num_hpd)
305 return connected;
306
307 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1898 + hpd_offsets[hpd]), 0) &
308 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK0x2)
309 connected = true1;
310
311 return connected;
312}
313
314/**
315 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
316 *
317 * @adev: amdgpu_device pointer
318 * @hpd: hpd (hotplug detect) pin
319 *
320 * Set the polarity of the hpd pin (evergreen+).
321 */
322static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
323 enum amdgpu_hpd_id hpd)
324{
325 u32 tmp;
326 bool_Bool connected = dce_v11_0_hpd_sense(adev, hpd);
327
328 if (hpd >= adev->mode_info.num_hpd)
329 return;
330
331 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
332 if (connected)
333 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8)));
334 else
335 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
336 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
);
337}
338
339/**
340 * dce_v11_0_hpd_init - hpd setup callback.
341 *
342 * @adev: amdgpu_device pointer
343 *
344 * Setup the hpd pins used by the card (evergreen+).
345 * Enable the pin, set the polarity, and enable the hpd interrupts.
346 */
347static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
348{
349 struct drm_device *dev = adev_to_drm(adev);
350 struct drm_connector *connector;
351 struct drm_connector_list_iter iter;
352 u32 tmp;
353
354 drm_connector_list_iter_begin(dev, &iter);
355 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
356 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
357
358 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
359 continue;
360
361 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14 ||
362 connector->connector_type == DRM_MODE_CONNECTOR_LVDS7) {
363 /* don't try to enable hpd on eDP or LVDS avoid breaking the
364 * aux dp channel on imac and help (but not completely fix)
365 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
366 * also avoid interrupt storms during dpms.
367 */
368 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0);
369 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0)(((tmp) & ~0x10000) | (0x10000 & ((0) << 0x10))
);
370 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0);
371 continue;
372 }
373
374 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0);
375 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1)(((tmp) & ~0x10000000) | (0x10000000 & ((1) << 0x1c
)));
376 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0);
377
378 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189c + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0);
379 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,(((tmp) & ~0xff) | (0xff & ((50) << 0x0)))
380 DC_HPD_CONNECT_INT_DELAY,(((tmp) & ~0xff) | (0xff & ((50) << 0x0)))
381 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS)(((tmp) & ~0xff) | (0xff & ((50) << 0x0)));
382 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14
)))
383 DC_HPD_DISCONNECT_INT_DELAY,(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14
)))
384 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS)(((tmp) & ~0xff00000) | (0xff00000 & ((10) << 0x14
)));
385 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189c + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0);
386
387 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
388 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
389 }
390 drm_connector_list_iter_end(&iter);
391}
392
393/**
394 * dce_v11_0_hpd_fini - hpd tear down callback.
395 *
396 * @adev: amdgpu_device pointer
397 *
398 * Tear down the hpd pins used by the card (evergreen+).
399 * Disable the hpd interrupts.
400 */
401static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
402{
403 struct drm_device *dev = adev_to_drm(adev);
404 struct drm_connector *connector;
405 struct drm_connector_list_iter iter;
406 u32 tmp;
407
408 drm_connector_list_iter_begin(dev, &iter);
409 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
410 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
411
412 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
413 continue;
414
415 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd])amdgpu_device_rreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), 0);
416 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0)(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c
)));
417 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp)amdgpu_device_wreg(adev, (0x189a + hpd_offsets[amdgpu_connector
->hpd.hpd]), (tmp), 0);
418
419 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
420 }
421 drm_connector_list_iter_end(&iter);
422}
423
424static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
425{
426 return mmDC_GPIO_HPD_A0x488d;
427}
428
429static bool_Bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
430{
431 u32 crtc_hung = 0;
432 u32 crtc_status[6];
433 u32 i, j, tmp;
434
435 for (i = 0; i < adev->mode_info.num_crtc; i++) {
436 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0);
437 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)(((tmp) & 0x1) >> 0x0)) {
438 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1ba8 + crtc_offsets[i]), 0);
439 crtc_hung |= (1 << i);
440 }
441 }
442
443 for (j = 0; j < 10; j++) {
444 for (i = 0; i < adev->mode_info.num_crtc; i++) {
445 if (crtc_hung & (1 << i)) {
446 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1ba8 + crtc_offsets[i]), 0);
447 if (tmp != crtc_status[i])
448 crtc_hung &= ~(1 << i);
449 }
450 }
451 if (crtc_hung == 0)
452 return false0;
453 udelay(100);
454 }
455
456 return true1;
457}
458
459static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
460 bool_Bool render)
461{
462 u32 tmp;
463
464 /* Lockout access through VGA aperture*/
465 tmp = RREG32(mmVGA_HDP_CONTROL)amdgpu_device_rreg(adev, (0xca), 0);
466 if (render)
467 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0)(((tmp) & ~0x10) | (0x10 & ((0) << 0x4)));
468 else
469 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
470 WREG32(mmVGA_HDP_CONTROL, tmp)amdgpu_device_wreg(adev, (0xca), (tmp), 0);
471
472 /* disable VGA render */
473 tmp = RREG32(mmVGA_RENDER_CONTROL)amdgpu_device_rreg(adev, (0xc0), 0);
474 if (render)
475 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1)(((tmp) & ~0x30000) | (0x30000 & ((1) << 0x10))
);
476 else
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0)(((tmp) & ~0x30000) | (0x30000 & ((0) << 0x10))
);
478 WREG32(mmVGA_RENDER_CONTROL, tmp)amdgpu_device_wreg(adev, (0xc0), (tmp), 0);
479}
480
481static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
482{
483 int num_crtc = 0;
484
485 switch (adev->asic_type) {
486 case CHIP_CARRIZO:
487 num_crtc = 3;
488 break;
489 case CHIP_STONEY:
490 num_crtc = 2;
491 break;
492 case CHIP_POLARIS10:
493 case CHIP_VEGAM:
494 num_crtc = 6;
495 break;
496 case CHIP_POLARIS11:
497 case CHIP_POLARIS12:
498 num_crtc = 5;
499 break;
500 default:
501 num_crtc = 0;
502 }
503 return num_crtc;
504}
505
506void dce_v11_0_disable_dce(struct amdgpu_device *adev)
507{
508 /*Disable VGA render and enabled crtc, if has DCE engine*/
509 if (amdgpu_atombios_has_dce_engine_info(adev)) {
510 u32 tmp;
511 int crtc_enabled, i;
512
513 dce_v11_0_set_vga_render_state(adev, false0);
514
515 /*Disable crtc*/
516 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
517 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),(((amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0)) &
0x1) >> 0x0)
518 CRTC_CONTROL, CRTC_MASTER_EN)(((amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0)) &
0x1) >> 0x0);
519 if (crtc_enabled) {
520 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1)amdgpu_device_wreg(adev, (0x1bb5 + crtc_offsets[i]), (1), 0);
521 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i])amdgpu_device_rreg(adev, (0x1b9c + crtc_offsets[i]), 0);
522 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
523 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp)amdgpu_device_wreg(adev, (0x1b9c + crtc_offsets[i]), (tmp), 0
);
524 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0)amdgpu_device_wreg(adev, (0x1bb5 + crtc_offsets[i]), (0), 0);
525 }
526 }
527 }
528}
529
530static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
531{
532 struct drm_device *dev = encoder->dev;
533 struct amdgpu_device *adev = drm_to_adev(dev);
534 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
535 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_crtc, base) );});
536 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
537 int bpc = 0;
538 u32 tmp = 0;
539 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
540
541 if (connector) {
542 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
543 bpc = amdgpu_connector_get_monitor_bpc(connector);
544 dither = amdgpu_connector->dither;
545 }
546
547 /* LVDS/eDP FMT is set up by atom */
548 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))
549 return;
550
551 /* not needed for analog */
552 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15) ||
553 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16))
554 return;
555
556 if (bpc == 0)
557 return;
558
559 switch (bpc) {
560 case 6:
561 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
562 /* XXX sort out optimal dither settings */
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd)));
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf)));
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0)(((tmp) & ~0x1800) | (0x1800 & ((0) << 0xb)));
567 } else {
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0)(((tmp) & ~0x30) | (0x30 & ((0) << 0x4)));
570 }
571 break;
572 case 8:
573 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
574 /* XXX sort out optimal dither settings */
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd)));
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf)));
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1)(((tmp) & ~0x4000) | (0x4000 & ((1) << 0xe)));
578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1)(((tmp) & ~0x1800) | (0x1800 & ((1) << 0xb)));
580 } else {
581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1)(((tmp) & ~0x30) | (0x30 & ((1) << 0x4)));
583 }
584 break;
585 case 10:
586 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
587 /* XXX sort out optimal dither settings */
588 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1)(((tmp) & ~0x2000) | (0x2000 & ((1) << 0xd)));
589 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1)(((tmp) & ~0x8000) | (0x8000 & ((1) << 0xf)));
590 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1)(((tmp) & ~0x4000) | (0x4000 & ((1) << 0xe)));
591 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
592 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2)(((tmp) & ~0x1800) | (0x1800 & ((2) << 0xb)));
593 } else {
594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2)(((tmp) & ~0x30) | (0x30 & ((2) << 0x4)));
596 }
597 break;
598 default:
599 /* not needed */
600 break;
601 }
602
603 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1bf2 + amdgpu_crtc->crtc_offset
), (tmp), 0);
604}
605
606
607/* display watermark setup */
608/**
609 * dce_v11_0_line_buffer_adjust - Set up the line buffer
610 *
611 * @adev: amdgpu_device pointer
612 * @amdgpu_crtc: the selected display controller
613 * @mode: the current display mode on the selected display
614 * controller
615 *
616 * Setup up the line buffer allocation for
617 * the selected display controller (CIK).
618 * Returns the line buffer size in pixels.
619 */
620static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
621 struct amdgpu_crtc *amdgpu_crtc,
622 struct drm_display_mode *mode)
623{
624 u32 tmp, buffer_alloc, i, mem_cfg;
625 u32 pipe_offset = amdgpu_crtc->crtc_id;
626 /*
627 * Line Buffer Setup
628 * There are 6 line buffers, one for each display controllers.
629 * There are 3 partitions per LB. Select the number of partitions
630 * to enable based on the display width. For display widths larger
631 * than 4096, you need use to use 2 display controllers and combine
632 * them using the stereo blender.
633 */
634 if (amdgpu_crtc->base.enabled && mode) {
635 if (mode->crtc_hdisplay < 1920) {
636 mem_cfg = 1;
637 buffer_alloc = 2;
638 } else if (mode->crtc_hdisplay < 2560) {
639 mem_cfg = 2;
640 buffer_alloc = 2;
641 } else if (mode->crtc_hdisplay < 4096) {
642 mem_cfg = 0;
643 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
644 } else {
645 DRM_DEBUG_KMS("Mode too big for LB!\n")__drm_dbg(DRM_UT_KMS, "Mode too big for LB!\n");
646 mem_cfg = 0;
647 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
648 }
649 } else {
650 mem_cfg = 1;
651 buffer_alloc = 0;
652 }
653
654 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1ac1 + amdgpu_crtc->crtc_offset
), 0);
655 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg)(((tmp) & ~0x300000) | (0x300000 & ((mem_cfg) <<
0x14)));
656 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1ac1 + amdgpu_crtc->crtc_offset
), (tmp), 0);
657
658 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset)amdgpu_device_rreg(adev, (0x321 + pipe_offset), 0);
659 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc)(((tmp) & ~0x7) | (0x7 & ((buffer_alloc) << 0x0
)));
660 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp)amdgpu_device_wreg(adev, (0x321 + pipe_offset), (tmp), 0);
661
662 for (i = 0; i < adev->usec_timeout; i++) {
663 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset)amdgpu_device_rreg(adev, (0x321 + pipe_offset), 0);
664 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)(((tmp) & 0x10) >> 0x4))
665 break;
666 udelay(1);
667 }
668
669 if (amdgpu_crtc->base.enabled && mode) {
670 switch (mem_cfg) {
671 case 0:
672 default:
673 return 4096 * 2;
674 case 1:
675 return 1920 * 2;
676 case 2:
677 return 2560 * 2;
678 }
679 }
680
681 /* controller not enabled, so no lb used */
682 return 0;
683}
684
685/**
686 * cik_get_number_of_dram_channels - get the number of dram channels
687 *
688 * @adev: amdgpu_device pointer
689 *
690 * Look up the number of video ram channels (CIK).
691 * Used for display watermark bandwidth calculations
692 * Returns the number of dram channels
693 */
694static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
695{
696 u32 tmp = RREG32(mmMC_SHARED_CHMAP)amdgpu_device_rreg(adev, (0x801), 0);
697
698 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)(((tmp) & 0xf000) >> 0xc)) {
699 case 0:
700 default:
701 return 1;
702 case 1:
703 return 2;
704 case 2:
705 return 4;
706 case 3:
707 return 8;
708 case 4:
709 return 3;
710 case 5:
711 return 6;
712 case 6:
713 return 10;
714 case 7:
715 return 12;
716 case 8:
717 return 16;
718 }
719}
720
721struct dce10_wm_params {
722 u32 dram_channels; /* number of dram channels */
723 u32 yclk; /* bandwidth per dram data pin in kHz */
724 u32 sclk; /* engine clock in kHz */
725 u32 disp_clk; /* display clock in kHz */
726 u32 src_width; /* viewport width */
727 u32 active_time; /* active display time in ns */
728 u32 blank_time; /* blank time in ns */
729 bool_Bool interlaced; /* mode is interlaced */
730 fixed20_12 vsc; /* vertical scale ratio */
731 u32 num_heads; /* number of active crtcs */
732 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
733 u32 lb_size; /* line buffer allocated to pipe */
734 u32 vtaps; /* vertical scaler taps */
735};
736
737/**
738 * dce_v11_0_dram_bandwidth - get the dram bandwidth
739 *
740 * @wm: watermark calculation data
741 *
742 * Calculate the raw dram bandwidth (CIK).
743 * Used for display watermark bandwidth calculations
744 * Returns the dram bandwidth in MBytes/s
745 */
746static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
747{
748 /* Calculate raw DRAM Bandwidth */
749 fixed20_12 dram_efficiency; /* 0.7 */
750 fixed20_12 yclk, dram_channels, bandwidth;
751 fixed20_12 a;
752
753 a.full = dfixed_const(1000)(u32)(((1000) << 12));
754 yclk.full = dfixed_const(wm->yclk)(u32)(((wm->yclk) << 12));
755 yclk.full = dfixed_div(yclk, a);
756 dram_channels.full = dfixed_const(wm->dram_channels * 4)(u32)(((wm->dram_channels * 4) << 12));
757 a.full = dfixed_const(10)(u32)(((10) << 12));
758 dram_efficiency.full = dfixed_const(7)(u32)(((7) << 12));
759 dram_efficiency.full = dfixed_div(dram_efficiency, a);
760 bandwidth.full = dfixed_mul(dram_channels, yclk)((u64)((u64)(dram_channels).full * (yclk).full + 2048) >>
12);
761 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency)((u64)((u64)(bandwidth).full * (dram_efficiency).full + 2048)
>> 12);
762
763 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
764}
765
766/**
767 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
768 *
769 * @wm: watermark calculation data
770 *
771 * Calculate the dram bandwidth used for display (CIK).
772 * Used for display watermark bandwidth calculations
773 * Returns the dram bandwidth for display in MBytes/s
774 */
775static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
776{
777 /* Calculate DRAM Bandwidth and the part allocated to display. */
778 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
779 fixed20_12 yclk, dram_channels, bandwidth;
780 fixed20_12 a;
781
782 a.full = dfixed_const(1000)(u32)(((1000) << 12));
783 yclk.full = dfixed_const(wm->yclk)(u32)(((wm->yclk) << 12));
784 yclk.full = dfixed_div(yclk, a);
785 dram_channels.full = dfixed_const(wm->dram_channels * 4)(u32)(((wm->dram_channels * 4) << 12));
786 a.full = dfixed_const(10)(u32)(((10) << 12));
787 disp_dram_allocation.full = dfixed_const(3)(u32)(((3) << 12)); /* XXX worse case value 0.3 */
788 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
789 bandwidth.full = dfixed_mul(dram_channels, yclk)((u64)((u64)(dram_channels).full * (yclk).full + 2048) >>
12);
790 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation)((u64)((u64)(bandwidth).full * (disp_dram_allocation).full + 2048
) >> 12);
791
792 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
793}
794
795/**
796 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
797 *
798 * @wm: watermark calculation data
799 *
800 * Calculate the data return bandwidth used for display (CIK).
801 * Used for display watermark bandwidth calculations
802 * Returns the data return bandwidth in MBytes/s
803 */
804static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
805{
806 /* Calculate the display Data return Bandwidth */
807 fixed20_12 return_efficiency; /* 0.8 */
808 fixed20_12 sclk, bandwidth;
809 fixed20_12 a;
810
811 a.full = dfixed_const(1000)(u32)(((1000) << 12));
812 sclk.full = dfixed_const(wm->sclk)(u32)(((wm->sclk) << 12));
813 sclk.full = dfixed_div(sclk, a);
814 a.full = dfixed_const(10)(u32)(((10) << 12));
815 return_efficiency.full = dfixed_const(8)(u32)(((8) << 12));
816 return_efficiency.full = dfixed_div(return_efficiency, a);
817 a.full = dfixed_const(32)(u32)(((32) << 12));
818 bandwidth.full = dfixed_mul(a, sclk)((u64)((u64)(a).full * (sclk).full + 2048) >> 12);
819 bandwidth.full = dfixed_mul(bandwidth, return_efficiency)((u64)((u64)(bandwidth).full * (return_efficiency).full + 2048
) >> 12);
820
821 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
822}
823
824/**
825 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
826 *
827 * @wm: watermark calculation data
828 *
829 * Calculate the dmif bandwidth used for display (CIK).
830 * Used for display watermark bandwidth calculations
831 * Returns the dmif bandwidth in MBytes/s
832 */
833static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
834{
835 /* Calculate the DMIF Request Bandwidth */
836 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
837 fixed20_12 disp_clk, bandwidth;
838 fixed20_12 a, b;
839
840 a.full = dfixed_const(1000)(u32)(((1000) << 12));
841 disp_clk.full = dfixed_const(wm->disp_clk)(u32)(((wm->disp_clk) << 12));
842 disp_clk.full = dfixed_div(disp_clk, a);
843 a.full = dfixed_const(32)(u32)(((32) << 12));
844 b.full = dfixed_mul(a, disp_clk)((u64)((u64)(a).full * (disp_clk).full + 2048) >> 12);
845
846 a.full = dfixed_const(10)(u32)(((10) << 12));
847 disp_clk_request_efficiency.full = dfixed_const(8)(u32)(((8) << 12));
848 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
849
850 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency)((u64)((u64)(b).full * (disp_clk_request_efficiency).full + 2048
) >> 12);
851
852 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
853}
854
855/**
856 * dce_v11_0_available_bandwidth - get the min available bandwidth
857 *
858 * @wm: watermark calculation data
859 *
860 * Calculate the min available bandwidth used for display (CIK).
861 * Used for display watermark bandwidth calculations
862 * Returns the min available bandwidth in MBytes/s
863 */
864static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
865{
866 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
867 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
868 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
869 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
870
871 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth))(((dram_bandwidth)<((((data_return_bandwidth)<(dmif_req_bandwidth
))?(data_return_bandwidth):(dmif_req_bandwidth))))?(dram_bandwidth
):((((data_return_bandwidth)<(dmif_req_bandwidth))?(data_return_bandwidth
):(dmif_req_bandwidth))));
872}
873
874/**
875 * dce_v11_0_average_bandwidth - get the average available bandwidth
876 *
877 * @wm: watermark calculation data
878 *
879 * Calculate the average available bandwidth used for display (CIK).
880 * Used for display watermark bandwidth calculations
881 * Returns the average available bandwidth in MBytes/s
882 */
883static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
884{
885 /* Calculate the display mode Average Bandwidth
886 * DisplayMode should contain the source and destination dimensions,
887 * timing, etc.
888 */
889 fixed20_12 bpp;
890 fixed20_12 line_time;
891 fixed20_12 src_width;
892 fixed20_12 bandwidth;
893 fixed20_12 a;
894
895 a.full = dfixed_const(1000)(u32)(((1000) << 12));
896 line_time.full = dfixed_const(wm->active_time + wm->blank_time)(u32)(((wm->active_time + wm->blank_time) << 12));
897 line_time.full = dfixed_div(line_time, a);
898 bpp.full = dfixed_const(wm->bytes_per_pixel)(u32)(((wm->bytes_per_pixel) << 12));
899 src_width.full = dfixed_const(wm->src_width)(u32)(((wm->src_width) << 12));
900 bandwidth.full = dfixed_mul(src_width, bpp)((u64)((u64)(src_width).full * (bpp).full + 2048) >> 12
);
901 bandwidth.full = dfixed_mul(bandwidth, wm->vsc)((u64)((u64)(bandwidth).full * (wm->vsc).full + 2048) >>
12);
902 bandwidth.full = dfixed_div(bandwidth, line_time);
903
904 return dfixed_trunc(bandwidth)((bandwidth).full >> 12);
905}
906
907/**
908 * dce_v11_0_latency_watermark - get the latency watermark
909 *
910 * @wm: watermark calculation data
911 *
912 * Calculate the latency watermark (CIK).
913 * Used for display watermark bandwidth calculations
914 * Returns the latency watermark in ns
915 */
916static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
917{
918 /* First calculate the latency in ns */
919 u32 mc_latency = 2000; /* 2000 ns. */
920 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
921 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
922 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
923 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
924 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
925 (wm->num_heads * cursor_line_pair_return_time);
926 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
927 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
928 u32 tmp, dmif_size = 12288;
929 fixed20_12 a, b, c;
930
931 if (wm->num_heads == 0)
932 return 0;
933
934 a.full = dfixed_const(2)(u32)(((2) << 12));
935 b.full = dfixed_const(1)(u32)(((1) << 12));
936 if ((wm->vsc.full > a.full) ||
937 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
938 (wm->vtaps >= 5) ||
939 ((wm->vsc.full >= a.full) && wm->interlaced))
940 max_src_lines_per_dst_line = 4;
941 else
942 max_src_lines_per_dst_line = 2;
943
944 a.full = dfixed_const(available_bandwidth)(u32)(((available_bandwidth) << 12));
945 b.full = dfixed_const(wm->num_heads)(u32)(((wm->num_heads) << 12));
946 a.full = dfixed_div(a, b);
947 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
948 tmp = min(dfixed_trunc(a), tmp)(((((a).full >> 12))<(tmp))?(((a).full >> 12))
:(tmp));
949
950 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000)(((tmp)<(wm->disp_clk * wm->bytes_per_pixel / 1000))
?(tmp):(wm->disp_clk * wm->bytes_per_pixel / 1000));
951
952 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel)(u32)(((max_src_lines_per_dst_line * wm->src_width * wm->
bytes_per_pixel) << 12));
953 b.full = dfixed_const(1000)(u32)(((1000) << 12));
954 c.full = dfixed_const(lb_fill_bw)(u32)(((lb_fill_bw) << 12));
955 b.full = dfixed_div(c, b);
956 a.full = dfixed_div(a, b);
957 line_fill_time = dfixed_trunc(a)((a).full >> 12);
958
959 if (line_fill_time < wm->active_time)
960 return latency;
961 else
962 return latency + (line_fill_time - wm->active_time);
963
964}
965
966/**
967 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
968 * average and available dram bandwidth
969 *
970 * @wm: watermark calculation data
971 *
972 * Check if the display average bandwidth fits in the display
973 * dram bandwidth (CIK).
974 * Used for display watermark bandwidth calculations
975 * Returns true if the display fits, false if not.
976 */
977static bool_Bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
978{
979 if (dce_v11_0_average_bandwidth(wm) <=
980 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
981 return true1;
982 else
983 return false0;
984}
985
986/**
987 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
988 * average and available bandwidth
989 *
990 * @wm: watermark calculation data
991 *
992 * Check if the display average bandwidth fits in the display
993 * available bandwidth (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns true if the display fits, false if not.
996 */
997static bool_Bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
998{
999 if (dce_v11_0_average_bandwidth(wm) <=
1000 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1001 return true1;
1002 else
1003 return false0;
1004}
1005
1006/**
1007 * dce_v11_0_check_latency_hiding - check latency hiding
1008 *
1009 * @wm: watermark calculation data
1010 *
1011 * Check latency hiding (CIK).
1012 * Used for display watermark bandwidth calculations
1013 * Returns true if the display fits, false if not.
1014 */
1015static bool_Bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1016{
1017 u32 lb_partitions = wm->lb_size / wm->src_width;
1018 u32 line_time = wm->active_time + wm->blank_time;
1019 u32 latency_tolerant_lines;
1020 u32 latency_hiding;
1021 fixed20_12 a;
1022
1023 a.full = dfixed_const(1)(u32)(((1) << 12));
1024 if (wm->vsc.full > a.full)
1025 latency_tolerant_lines = 1;
1026 else {
1027 if (lb_partitions <= (wm->vtaps + 1))
1028 latency_tolerant_lines = 1;
1029 else
1030 latency_tolerant_lines = 2;
1031 }
1032
1033 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1034
1035 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1036 return true1;
1037 else
1038 return false0;
1039}
1040
1041/**
1042 * dce_v11_0_program_watermarks - program display watermarks
1043 *
1044 * @adev: amdgpu_device pointer
1045 * @amdgpu_crtc: the selected display controller
1046 * @lb_size: line buffer size
1047 * @num_heads: number of display controllers in use
1048 *
1049 * Calculate and program the display watermarks for the
1050 * selected display controller (CIK).
1051 */
1052static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1053 struct amdgpu_crtc *amdgpu_crtc,
1054 u32 lb_size, u32 num_heads)
1055{
1056 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1057 struct dce10_wm_params wm_low, wm_high;
1058 u32 active_time;
1059 u32 line_time = 0;
1060 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1061 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1062
1063 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1064 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1065 (u32)mode->clock);
1066 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1067 (u32)mode->clock);
1068 line_time = min(line_time, (u32)65535)(((line_time)<((u32)65535))?(line_time):((u32)65535));
1069
1070 /* watermark for high clocks */
1071 if (adev->pm.dpm_enabled) {
1072 wm_high.yclk =
1073 amdgpu_dpm_get_mclk(adev, false0) * 10;
1074 wm_high.sclk =
1075 amdgpu_dpm_get_sclk(adev, false0) * 10;
1076 } else {
1077 wm_high.yclk = adev->pm.current_mclk * 10;
1078 wm_high.sclk = adev->pm.current_sclk * 10;
1079 }
1080
1081 wm_high.disp_clk = mode->clock;
1082 wm_high.src_width = mode->crtc_hdisplay;
1083 wm_high.active_time = active_time;
1084 wm_high.blank_time = line_time - wm_high.active_time;
1085 wm_high.interlaced = false0;
1086 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
1087 wm_high.interlaced = true1;
1088 wm_high.vsc = amdgpu_crtc->vsc;
1089 wm_high.vtaps = 1;
1090 if (amdgpu_crtc->rmx_type != RMX_OFF)
1091 wm_high.vtaps = 2;
1092 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1093 wm_high.lb_size = lb_size;
1094 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1095 wm_high.num_heads = num_heads;
1096
1097 /* set for high clocks */
1098 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535)(((dce_v11_0_latency_watermark(&wm_high))<((u32)65535)
)?(dce_v11_0_latency_watermark(&wm_high)):((u32)65535));
1099
1100 /* possibly force display priority to high */
1101 /* should really do this at mode validation time... */
1102 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1103 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1104 !dce_v11_0_check_latency_hiding(&wm_high) ||
1105 (adev->mode_info.disp_priority == 2)) {
1106 DRM_DEBUG_KMS("force priority to high\n")__drm_dbg(DRM_UT_KMS, "force priority to high\n");
1107 }
1108
1109 /* watermark for low clocks */
1110 if (adev->pm.dpm_enabled) {
1111 wm_low.yclk =
1112 amdgpu_dpm_get_mclk(adev, true1) * 10;
1113 wm_low.sclk =
1114 amdgpu_dpm_get_sclk(adev, true1) * 10;
1115 } else {
1116 wm_low.yclk = adev->pm.current_mclk * 10;
1117 wm_low.sclk = adev->pm.current_sclk * 10;
1118 }
1119
1120 wm_low.disp_clk = mode->clock;
1121 wm_low.src_width = mode->crtc_hdisplay;
1122 wm_low.active_time = active_time;
1123 wm_low.blank_time = line_time - wm_low.active_time;
1124 wm_low.interlaced = false0;
1125 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
1126 wm_low.interlaced = true1;
1127 wm_low.vsc = amdgpu_crtc->vsc;
1128 wm_low.vtaps = 1;
1129 if (amdgpu_crtc->rmx_type != RMX_OFF)
1130 wm_low.vtaps = 2;
1131 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1132 wm_low.lb_size = lb_size;
1133 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1134 wm_low.num_heads = num_heads;
1135
1136 /* set for low clocks */
1137 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535)(((dce_v11_0_latency_watermark(&wm_low))<((u32)65535))
?(dce_v11_0_latency_watermark(&wm_low)):((u32)65535));
1138
1139 /* possibly force display priority to high */
1140 /* should really do this at mode validation time... */
1141 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1142 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1143 !dce_v11_0_check_latency_hiding(&wm_low) ||
1144 (adev->mode_info.disp_priority == 2)) {
1145 DRM_DEBUG_KMS("force priority to high\n")__drm_dbg(DRM_UT_KMS, "force priority to high\n");
1146 }
1147 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay)(((lb_size) + ((mode->crtc_hdisplay) - 1)) / (mode->crtc_hdisplay
));
1148 }
1149
1150 /* select wm A */
1151 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), 0);
1152 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1)(((wm_mask) & ~0x300) | (0x300 & ((1) << 0x8)));
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), (tmp), 0);
1154 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), 0);
1155 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a)(((tmp) & ~0xffff) | (0xffff & ((latency_watermark_a)
<< 0x0)));
1156 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time)(((tmp) & ~0xffff0000) | (0xffff0000 & ((line_time) <<
0x10)));
1157 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), (tmp), 0);
1158 /* select wm B */
1159 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2)(((wm_mask) & ~0x300) | (0x300 & ((2) << 0x8)));
1160 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), (tmp), 0);
1161 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), 0);
1162 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b)(((tmp) & ~0xffff) | (0xffff & ((latency_watermark_b)
<< 0x0)));
1163 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time)(((tmp) & ~0xffff0000) | (0xffff0000 & ((line_time) <<
0x10)));
1164 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1b33 + amdgpu_crtc->crtc_offset
), (tmp), 0);
1165 /* restore original selection */
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask)amdgpu_device_wreg(adev, (0x1b32 + amdgpu_crtc->crtc_offset
), (wm_mask), 0);
1167
1168 /* save values for DPM */
1169 amdgpu_crtc->line_time = line_time;
1170 amdgpu_crtc->wm_high = latency_watermark_a;
1171 amdgpu_crtc->wm_low = latency_watermark_b;
1172 /* Save number of lines the linebuffer leads before the scanout */
1173 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1174}
1175
1176/**
1177 * dce_v11_0_bandwidth_update - program display watermarks
1178 *
1179 * @adev: amdgpu_device pointer
1180 *
1181 * Calculate and program the display watermarks and line
1182 * buffer allocation (CIK).
1183 */
1184static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1185{
1186 struct drm_display_mode *mode = NULL((void *)0);
1187 u32 num_heads = 0, lb_size;
1188 int i;
1189
1190 amdgpu_display_update_priority(adev);
1191
1192 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1193 if (adev->mode_info.crtcs[i]->base.enabled)
1194 num_heads++;
1195 }
1196 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1197 mode = &adev->mode_info.crtcs[i]->base.mode;
1198 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1199 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1200 lb_size, num_heads);
1201 }
1202}
1203
1204static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1205{
1206 int i;
1207 u32 offset, tmp;
1208
1209 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1210 offset = adev->mode_info.audio.pin[i].offset;
1211 tmp = RREG32_AUDIO_ENDPT(offset,adev->audio_endpt_rreg(adev, (offset), (0x56))
1212 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT)adev->audio_endpt_rreg(adev, (offset), (0x56));
1213 if (((tmp &
1214 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK0xc0000000) >>
1215 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT0x1e) == 1)
1216 adev->mode_info.audio.pin[i].connected = false0;
1217 else
1218 adev->mode_info.audio.pin[i].connected = true1;
1219 }
1220}
1221
1222static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1223{
1224 int i;
1225
1226 dce_v11_0_audio_get_connected_pins(adev);
1227
1228 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1229 if (adev->mode_info.audio.pin[i].connected)
1230 return &adev->mode_info.audio.pin[i];
1231 }
1232 DRM_ERROR("No connected audio pins found!\n")__drm_err("No connected audio pins found!\n");
1233 return NULL((void *)0);
1234}
1235
1236static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1237{
1238 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1239 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1240 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1241 u32 tmp;
1242
1243 if (!dig || !dig->afmt || !dig->afmt->pin)
1244 return;
1245
1246 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a45 + dig->afmt->offset), 0
);
1247 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id)(((tmp) & ~0x7) | (0x7 & ((dig->afmt->pin->id
) << 0x0)));
1248 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a45 + dig->afmt->offset), (
tmp), 0);
1249}
1250
1251static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1252 struct drm_display_mode *mode)
1253{
1254 struct drm_device *dev = encoder->dev;
1255 struct amdgpu_device *adev = drm_to_adev(dev);
1256 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1257 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1258 struct drm_connector *connector;
1259 struct drm_connector_list_iter iter;
1260 struct amdgpu_connector *amdgpu_connector = NULL((void *)0);
1261 u32 tmp;
1262 int interlace = 0;
1263
1264 if (!dig || !dig->afmt || !dig->afmt->pin)
1265 return;
1266
1267 drm_connector_list_iter_begin(dev, &iter);
1268 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
1269 if (connector->encoder == encoder) {
1270 amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
1271 break;
1272 }
1273 }
1274 drm_connector_list_iter_end(&iter);
1275
1276 if (!amdgpu_connector) {
1277 DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n");
1278 return;
1279 }
1280
1281 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
1282 interlace = 1;
1283 if (connector->latency_present[interlace]) {
1284 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff) | (0xff & ((connector->video_latency
[interlace]) << 0x0)))
1285 VIDEO_LIPSYNC, connector->video_latency[interlace])(((0) & ~0xff) | (0xff & ((connector->video_latency
[interlace]) << 0x0)));
1286 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff00) | (0xff00 & ((connector->audio_latency
[interlace]) << 0x8)))
1287 AUDIO_LIPSYNC, connector->audio_latency[interlace])(((0) & ~0xff00) | (0xff00 & ((connector->audio_latency
[interlace]) << 0x8)));
1288 } else {
1289 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff) | (0xff & ((0) << 0x0)))
1290 VIDEO_LIPSYNC, 0)(((0) & ~0xff) | (0xff & ((0) << 0x0)));
1291 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,(((0) & ~0xff00) | (0xff00 & ((0) << 0x8)))
1292 AUDIO_LIPSYNC, 0)(((0) & ~0xff00) | (0xff00 & ((0) << 0x8)));
1293 }
1294 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x37), (tmp))
1295 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x37), (tmp));
1296}
1297
1298static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1299{
1300 struct drm_device *dev = encoder->dev;
1301 struct amdgpu_device *adev = drm_to_adev(dev);
1302 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1303 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1304 struct drm_connector *connector;
1305 struct drm_connector_list_iter iter;
1306 struct amdgpu_connector *amdgpu_connector = NULL((void *)0);
1307 u32 tmp;
1308 u8 *sadb = NULL((void *)0);
1309 int sad_count;
1310
1311 if (!dig || !dig->afmt || !dig->afmt->pin)
1312 return;
1313
1314 drm_connector_list_iter_begin(dev, &iter);
1315 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
1316 if (connector->encoder == encoder) {
1317 amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
1318 break;
1319 }
1320 }
1321 drm_connector_list_iter_end(&iter);
1322
1323 if (!amdgpu_connector) {
1324 DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n");
1325 return;
1326 }
1327
1328 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1329 if (sad_count < 0) {
1330 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count)__drm_err("Couldn't read Speaker Allocation Data Block: %d\n"
, sad_count);
1331 sad_count = 0;
1332 }
1333
1334 /* program the speaker allocation */
1335 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_rreg(adev, (dig->afmt->pin->offset
), (0x25))
1336 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER)adev->audio_endpt_rreg(adev, (dig->afmt->pin->offset
), (0x25));
1337 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x20000) | (0x20000 & ((0) << 0x11))
)
1338 DP_CONNECTION, 0)(((tmp) & ~0x20000) | (0x20000 & ((0) << 0x11))
);
1339 /* set HDMI mode */
1340 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10))
)
1341 HDMI_CONNECTION, 1)(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10))
);
1342 if (sad_count)
1343 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x7f) | (0x7f & ((sadb[0]) << 0x0)))
1344 SPEAKER_ALLOCATION, sadb[0])(((tmp) & ~0x7f) | (0x7f & ((sadb[0]) << 0x0)));
1345 else
1346 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,(((tmp) & ~0x7f) | (0x7f & ((5) << 0x0)))
1347 SPEAKER_ALLOCATION, 5)(((tmp) & ~0x7f) | (0x7f & ((5) << 0x0))); /* stereo */
1348 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x25), (tmp))
1349 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (0x25), (tmp));
1350
1351 kfree(sadb);
1352}
1353
1354static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1355{
1356 struct drm_device *dev = encoder->dev;
1357 struct amdgpu_device *adev = drm_to_adev(dev);
1358 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1359 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1360 struct drm_connector *connector;
1361 struct drm_connector_list_iter iter;
1362 struct amdgpu_connector *amdgpu_connector = NULL((void *)0);
1363 struct cea_sad *sads;
1364 int i, sad_count;
1365
1366 static const u16 eld_reg_to_type[][2] = {
1367 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR00x28, HDMI_AUDIO_CODING_TYPE_PCM },
1368 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10x29, HDMI_AUDIO_CODING_TYPE_AC3 },
1369 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR20x2a, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1370 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR30x2b, HDMI_AUDIO_CODING_TYPE_MP3 },
1371 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR40x2c, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR50x2d, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR60x2e, HDMI_AUDIO_CODING_TYPE_DTS },
1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR70x2f, HDMI_AUDIO_CODING_TYPE_ATRAC },
1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR90x31, HDMI_AUDIO_CODING_TYPE_EAC3 },
1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR100x32, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR110x33, HDMI_AUDIO_CODING_TYPE_MLP },
1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR130x35, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1379 };
1380
1381 if (!dig || !dig->afmt || !dig->afmt->pin)
1382 return;
1383
1384 drm_connector_list_iter_begin(dev, &iter);
1385 drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
1386 if (connector->encoder == encoder) {
1387 amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
1388 break;
1389 }
1390 }
1391 drm_connector_list_iter_end(&iter);
1392
1393 if (!amdgpu_connector) {
1394 DRM_ERROR("Couldn't find encoder's connector\n")__drm_err("Couldn't find encoder's connector\n");
1395 return;
1396 }
1397
1398 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1399 if (sad_count < 0)
1400 DRM_ERROR("Couldn't read SADs: %d\n", sad_count)__drm_err("Couldn't read SADs: %d\n", sad_count);
1401 if (sad_count <= 0)
1402 return;
1403 BUG_ON(!sads)((!(!sads)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/dce_v11_0.c"
, 1403, "!(!sads)"));
1404
1405 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type)(sizeof((eld_reg_to_type)) / sizeof((eld_reg_to_type)[0])); i++) {
1406 u32 tmp = 0;
1407 u8 stereo_freqs = 0;
1408 int max_channels = -1;
1409 int j;
1410
1411 for (j = 0; j < sad_count; j++) {
1412 struct cea_sad *sad = &sads[j];
1413
1414 if (sad->format == eld_reg_to_type[i][1]) {
1415 if (sad->channels > max_channels) {
1416 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0x7) | (0x7 & ((sad->channels) <<
0x0)))
1417 MAX_CHANNELS, sad->channels)(((tmp) & ~0x7) | (0x7 & ((sad->channels) <<
0x0)));
1418 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff0000) | (0xff0000 & ((sad->byte2) <<
0x10)))
1419 DESCRIPTOR_BYTE_2, sad->byte2)(((tmp) & ~0xff0000) | (0xff0000 & ((sad->byte2) <<
0x10)));
1420 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff00) | (0xff00 & ((sad->freq) <<
0x8)))
1421 SUPPORTED_FREQUENCIES, sad->freq)(((tmp) & ~0xff00) | (0xff00 & ((sad->freq) <<
0x8)));
1422 max_channels = sad->channels;
1423 }
1424
1425 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1426 stereo_freqs |= sad->freq;
1427 else
1428 break;
1429 }
1430 }
1431
1432 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,(((tmp) & ~0xff000000) | (0xff000000 & ((stereo_freqs
) << 0x18)))
1433 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs)(((tmp) & ~0xff000000) | (0xff000000 & ((stereo_freqs
) << 0x18)));
1434 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp)adev->audio_endpt_wreg(adev, (dig->afmt->pin->offset
), (eld_reg_to_type[i][0]), (tmp));
1435 }
1436
1437 kfree(sads);
1438}
1439
1440static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1441 struct amdgpu_audio_pin *pin,
1442 bool_Bool enable)
1443{
1444 if (!pin)
1445 return;
1446
1447 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,adev->audio_endpt_wreg(adev, (pin->offset), (0x54), (enable
? 0x80000000 : 0))
1448 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0)adev->audio_endpt_wreg(adev, (pin->offset), (0x54), (enable
? 0x80000000 : 0));
1449}
1450
1451static const u32 pin_offsets[] =
1452{
1453 AUD0_REGISTER_OFFSET(0x17a8 - 0x17a8),
1454 AUD1_REGISTER_OFFSET(0x17ac - 0x17a8),
1455 AUD2_REGISTER_OFFSET(0x17b0 - 0x17a8),
1456 AUD3_REGISTER_OFFSET(0x17b4 - 0x17a8),
1457 AUD4_REGISTER_OFFSET(0x17b8 - 0x17a8),
1458 AUD5_REGISTER_OFFSET(0x17bc - 0x17a8),
1459 AUD6_REGISTER_OFFSET(0x17c0 - 0x17a8),
1460 AUD7_REGISTER_OFFSET(0x17c4 - 0x17a8),
1461};
1462
1463static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1464{
1465 int i;
1466
1467 if (!amdgpu_audio)
1468 return 0;
1469
1470 adev->mode_info.audio.enabled = true1;
1471
1472 switch (adev->asic_type) {
1473 case CHIP_CARRIZO:
1474 case CHIP_STONEY:
1475 adev->mode_info.audio.num_pins = 7;
1476 break;
1477 case CHIP_POLARIS10:
1478 case CHIP_VEGAM:
1479 adev->mode_info.audio.num_pins = 8;
1480 break;
1481 case CHIP_POLARIS11:
1482 case CHIP_POLARIS12:
1483 adev->mode_info.audio.num_pins = 6;
1484 break;
1485 default:
1486 return -EINVAL22;
1487 }
1488
1489 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1490 adev->mode_info.audio.pin[i].channels = -1;
1491 adev->mode_info.audio.pin[i].rate = -1;
1492 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1493 adev->mode_info.audio.pin[i].status_bits = 0;
1494 adev->mode_info.audio.pin[i].category_code = 0;
1495 adev->mode_info.audio.pin[i].connected = false0;
1496 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1497 adev->mode_info.audio.pin[i].id = i;
1498 /* disable audio. it will be set up later */
1499 /* XXX remove once we switch to ip funcs */
1500 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
1501 }
1502
1503 return 0;
1504}
1505
1506static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1507{
1508 int i;
1509
1510 if (!amdgpu_audio)
1511 return;
1512
1513 if (!adev->mode_info.audio.enabled)
1514 return;
1515
1516 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1517 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
1518
1519 adev->mode_info.audio.enabled = false0;
1520}
1521
1522/*
1523 * update the N and CTS parameters for a given pixel clock rate
1524 */
1525static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1526{
1527 struct drm_device *dev = encoder->dev;
1528 struct amdgpu_device *adev = drm_to_adev(dev);
1529 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1530 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1531 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1532 u32 tmp;
1533
1534 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a2e + dig->afmt->offset), 0
);
1535 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_32khz
) << 0xc)));
1536 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a2e + dig->afmt->offset), (
tmp), 0);
1537 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a2f + dig->afmt->offset), 0
);
1538 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_32khz) <<
0x0)));
1539 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a2f + dig->afmt->offset), (
tmp), 0);
1540
1541 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a30 + dig->afmt->offset), 0
);
1542 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_44_1khz
) << 0xc)));
1543 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a30 + dig->afmt->offset), (
tmp), 0);
1544 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a31 + dig->afmt->offset), 0
);
1545 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_44_1khz) <<
0x0)));
1546 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a31 + dig->afmt->offset), (
tmp), 0);
1547
1548 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a32 + dig->afmt->offset), 0
);
1549 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz)(((tmp) & ~0xfffff000) | (0xfffff000 & ((acr.cts_48khz
) << 0xc)));
1550 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a32 + dig->afmt->offset), (
tmp), 0);
1551 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a33 + dig->afmt->offset), 0
);
1552 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz)(((tmp) & ~0xfffff) | (0xfffff & ((acr.n_48khz) <<
0x0)));
1553 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a33 + dig->afmt->offset), (
tmp), 0);
1554
1555}
1556
1557/*
1558 * build a HDMI Video Info Frame
1559 */
1560static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1561 void *buffer, size_t size)
1562{
1563 struct drm_device *dev = encoder->dev;
1564 struct amdgpu_device *adev = drm_to_adev(dev);
1565 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1566 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1567 uint8_t *frame = buffer + 3;
1568 uint8_t *header = buffer;
1569
1570 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a1e + dig->afmt->offset), (
frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16
) | (frame[0x3] << 24)), 0)
1571 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24))amdgpu_device_wreg(adev, (0x4a1e + dig->afmt->offset), (
frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16
) | (frame[0x3] << 24)), 0);
1572 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a1f + dig->afmt->offset), (
frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16
) | (frame[0x7] << 24)), 0)
1573 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24))amdgpu_device_wreg(adev, (0x4a1f + dig->afmt->offset), (
frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16
) | (frame[0x7] << 24)), 0);
1574 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a20 + dig->afmt->offset), (
frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16
) | (frame[0xB] << 24)), 0)
1575 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24))amdgpu_device_wreg(adev, (0x4a20 + dig->afmt->offset), (
frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16
) | (frame[0xB] << 24)), 0);
1576 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a21 + dig->afmt->offset), (
frame[0xC] | (frame[0xD] << 8) | (header[1] << 24
)), 0)
1577 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24))amdgpu_device_wreg(adev, (0x4a21 + dig->afmt->offset), (
frame[0xC] | (frame[0xD] << 8) | (header[1] << 24
)), 0);
1578}
1579
1580static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1581{
1582 struct drm_device *dev = encoder->dev;
1583 struct amdgpu_device *adev = drm_to_adev(dev);
1584 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1585 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_crtc, base) );});
1587 u32 dto_phase = 24 * 1000;
1588 u32 dto_modulo = clock;
1589 u32 tmp;
1590
1591 if (!dig || !dig->afmt)
1592 return;
1593
1594 /* XXX two dtos; generally use dto0 for hdmi */
1595 /* Express [24MHz / target pixel clock] as an exact rational
1596 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1597 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1598 */
1599 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE)amdgpu_device_rreg(adev, (0x16b), 0);
1600 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,(((tmp) & ~0x7) | (0x7 & ((amdgpu_crtc->crtc_id) <<
0x0)))
1601 amdgpu_crtc->crtc_id)(((tmp) & ~0x7) | (0x7 & ((amdgpu_crtc->crtc_id) <<
0x0)));
1602 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp)amdgpu_device_wreg(adev, (0x16b), (tmp), 0);
1603 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase)amdgpu_device_wreg(adev, (0x16c), (dto_phase), 0);
1604 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo)amdgpu_device_wreg(adev, (0x16d), (dto_modulo), 0);
1605}
1606
1607/*
1608 * update the info frames with the data from the current display mode
1609 */
1610static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1611 struct drm_display_mode *mode)
1612{
1613 struct drm_device *dev = encoder->dev;
1614 struct amdgpu_device *adev = drm_to_adev(dev);
1615 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1616 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1617 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1618 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE4 + HDMI_AVI_INFOFRAME_SIZE13];
1619 struct hdmi_avi_infoframe frame;
1620 ssize_t err;
1621 u32 tmp;
1622 int bpc = 8;
1623
1624 if (!dig || !dig->afmt)
1625 return;
1626
1627 /* Silent, r600_hdmi_enable will raise WARN for us */
1628 if (!dig->afmt->enabled)
1629 return;
1630
1631 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1632 if (encoder->crtc) {
1633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (encoder->crtc); (struct amdgpu_crtc *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_crtc, base) );});
1634 bpc = amdgpu_crtc->bpc;
1635 }
1636
1637 /* disable audio prior to setting up hw */
1638 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1639 dce_v11_0_audio_enable(adev, dig->afmt->pin, false0);
1640
1641 dce_v11_0_audio_set_dto(encoder, mode->clock);
1642
1643 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0d + dig->afmt->offset), 0
);
1644 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
1645 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0d + dig->afmt->offset), (
tmp), 0); /* send null packets when required */
1646
1647 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000)amdgpu_device_wreg(adev, (0x4a3a + dig->afmt->offset), (
0x1000), 0);
1648
1649 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a09 + dig->afmt->offset), 0
);
1650 switch (bpc) {
1651 case 0:
1652 case 6:
1653 case 8:
1654 case 16:
1655 default:
1656 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0)(((tmp) & ~0x1000000) | (0x1000000 & ((0) << 0x18
)));
1657 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0)(((tmp) & ~0x30000000) | (0x30000000 & ((0) << 0x1c
)));
1658 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",__drm_dbg(DRM_UT_CORE, "%s: Disabling hdmi deep color for %d bpc.\n"
, connector->name, bpc)
1659 connector->name, bpc)__drm_dbg(DRM_UT_CORE, "%s: Disabling hdmi deep color for %d bpc.\n"
, connector->name, bpc);
1660 break;
1661 case 10:
1662 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18
)));
1663 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1)(((tmp) & ~0x30000000) | (0x30000000 & ((1) << 0x1c
)));
1664 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",__drm_dbg(DRM_UT_CORE, "%s: Enabling hdmi deep color 30 for 10 bpc.\n"
, connector->name)
1665 connector->name)__drm_dbg(DRM_UT_CORE, "%s: Enabling hdmi deep color 30 for 10 bpc.\n"
, connector->name);
1666 break;
1667 case 12:
1668 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18
)));
1669 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2)(((tmp) & ~0x30000000) | (0x30000000 & ((2) << 0x1c
)));
1670 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",__drm_dbg(DRM_UT_CORE, "%s: Enabling hdmi deep color 36 for 12 bpc.\n"
, connector->name)
1671 connector->name)__drm_dbg(DRM_UT_CORE, "%s: Enabling hdmi deep color 36 for 12 bpc.\n"
, connector->name);
1672 break;
1673 }
1674 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a09 + dig->afmt->offset), (
tmp), 0);
1675
1676 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0d + dig->afmt->offset), 0
);
1677 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); /* send null packets when required */
1678 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4))); /* send general control packets */
1679 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1)(((tmp) & ~0x20) | (0x20 & ((1) << 0x5))); /* send general control packets every frame */
1680 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0d + dig->afmt->offset), (
tmp), 0);
1681
1682 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0e + dig->afmt->offset), 0
);
1683 /* enable audio info frames (frames won't be set until audio is enabled) */
1684 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
1685 /* required for audio info values to be updated */
1686 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1)(((tmp) & ~0x20) | (0x20 & ((1) << 0x5)));
1687 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0e + dig->afmt->offset), (
tmp), 0);
1688
1689 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a44 + dig->afmt->offset), 0
);
1690 /* required for audio info values to be updated */
1691 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1)(((tmp) & ~0x80) | (0x80 & ((1) << 0x7)));
1692 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a44 + dig->afmt->offset), (
tmp), 0);
1693
1694 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0f + dig->afmt->offset), 0
);
1695 /* anything other than 0 */
1696 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2)(((tmp) & ~0x3f00) | (0x3f00 & ((2) << 0x8)));
1697 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0f + dig->afmt->offset), (
tmp), 0);
1698
1699 WREG32(mmHDMI_GC + dig->afmt->offset, 0)amdgpu_device_wreg(adev, (0x4a13 + dig->afmt->offset), (
0), 0); /* unset HDMI_GC_AVMUTE */
1700
1701 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0b + dig->afmt->offset), 0
);
1702 /* set the default audio delay */
1703 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1)(((tmp) & ~0x30) | (0x30 & ((1) << 0x4)));
1704 /* should be suffient for all audio modes and small enough for all hblanks */
1705 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3)(((tmp) & ~0x1f0000) | (0x1f0000 & ((3) << 0x10
)));
1706 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0b + dig->afmt->offset), (
tmp), 0);
1707
1708 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a42 + dig->afmt->offset), 0
);
1709 /* allow 60958 channel status fields to be updated */
1710 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1)(((tmp) & ~0x4000000) | (0x4000000 & ((1) << 0x1a
)));
1711 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a42 + dig->afmt->offset), (
tmp), 0);
1712
1713 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0c + dig->afmt->offset), 0
);
1714 if (bpc > 8)
1715 /* clear SW CTS value */
1716 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8)));
1717 else
1718 /* select SW CTS value */
1719 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
1720 /* allow hw to sent ACR packets when required */
1721 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1)(((tmp) & ~0x1000) | (0x1000 & ((1) << 0xc)));
1722 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0c + dig->afmt->offset), (
tmp), 0);
1723
1724 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1725
1726 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a38 + dig->afmt->offset), 0
);
1727 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1)(((tmp) & ~0xf00000) | (0xf00000 & ((1) << 0x14
)));
1728 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a38 + dig->afmt->offset), (
tmp), 0);
1729
1730 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a39 + dig->afmt->offset), 0
);
1731 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2)(((tmp) & ~0xf00000) | (0xf00000 & ((2) << 0x14
)));
1732 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a39 + dig->afmt->offset), (
tmp), 0);
1733
1734 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a3f + dig->afmt->offset), 0
);
1735 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3)(((tmp) & ~0xf) | (0xf & ((3) << 0x0)));
1736 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4)(((tmp) & ~0xf0) | (0xf0 & ((4) << 0x4)));
1737 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5)(((tmp) & ~0xf00) | (0xf00 & ((5) << 0x8)));
1738 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6)(((tmp) & ~0xf000) | (0xf000 & ((6) << 0xc)));
1739 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7)(((tmp) & ~0xf0000) | (0xf0000 & ((7) << 0x10))
);
1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8)(((tmp) & ~0xf00000) | (0xf00000 & ((8) << 0x14
)));
1741 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a3f + dig->afmt->offset), (
tmp), 0);
1742
1743 dce_v11_0_audio_write_speaker_allocation(encoder);
1744
1745 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,amdgpu_device_wreg(adev, (0x4a14 + dig->afmt->offset), (
(0xff << 0x8)), 0)
1746 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT))amdgpu_device_wreg(adev, (0x4a14 + dig->afmt->offset), (
(0xff << 0x8)), 0);
1747
1748 dce_v11_0_afmt_audio_select_pin(encoder);
1749 dce_v11_0_audio_write_sad_regs(encoder);
1750 dce_v11_0_audio_write_latency_fields(encoder, mode);
1751
1752 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1753 if (err < 0) {
1754 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err)__drm_err("failed to setup AVI infoframe: %zd\n", err);
1755 return;
1756 }
1757
1758 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1759 if (err < 0) {
1760 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err)__drm_err("failed to pack AVI infoframe: %zd\n", err);
1761 return;
1762 }
1763
1764 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1765
1766 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0e + dig->afmt->offset), 0
);
1767 /* enable AVI info frames */
1768 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
1769 /* required for audio info values to be updated */
1770 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1)));
1771 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0e + dig->afmt->offset), (
tmp), 0);
1772
1773 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a0f + dig->afmt->offset), 0
);
1774 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2)(((tmp) & ~0x3f) | (0x3f & ((2) << 0x0)));
1775 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a0f + dig->afmt->offset), (
tmp), 0);
1776
1777 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset)amdgpu_device_rreg(adev, (0x4a42 + dig->afmt->offset), 0
);
1778 /* send audio packets */
1779 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
1780 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp)amdgpu_device_wreg(adev, (0x4a42 + dig->afmt->offset), (
tmp), 0);
1781
1782 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF)amdgpu_device_wreg(adev, (0x4a3b + dig->afmt->offset), (
0x00FFFFFF), 0);
1783 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF)amdgpu_device_wreg(adev, (0x4a3c + dig->afmt->offset), (
0x007FFFFF), 0);
1784 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001)amdgpu_device_wreg(adev, (0x4a3d + dig->afmt->offset), (
0x00000001), 0);
1785 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001)amdgpu_device_wreg(adev, (0x4a3e + dig->afmt->offset), (
0x00000001), 0);
1786
1787 /* enable audio after to setting up hw */
1788 dce_v11_0_audio_enable(adev, dig->afmt->pin, true1);
1789}
1790
1791static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool_Bool enable)
1792{
1793 struct drm_device *dev = encoder->dev;
1794 struct amdgpu_device *adev = drm_to_adev(dev);
1795 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
1796 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1797
1798 if (!dig || !dig->afmt)
1799 return;
1800
1801 /* Silent, r600_hdmi_enable will raise WARN for us */
1802 if (enable && dig->afmt->enabled)
1803 return;
1804 if (!enable && !dig->afmt->enabled)
1805 return;
1806
1807 if (!enable && dig->afmt->pin) {
1808 dce_v11_0_audio_enable(adev, dig->afmt->pin, false0);
1809 dig->afmt->pin = NULL((void *)0);
1810 }
1811
1812 dig->afmt->enabled = enable;
1813
1814 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",__drm_dbg(DRM_UT_CORE, "%sabling AFMT interface @ 0x%04X for encoder 0x%x\n"
, enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder
->encoder_id)
1815 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id)__drm_dbg(DRM_UT_CORE, "%sabling AFMT interface @ 0x%04X for encoder 0x%x\n"
, enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder
->encoder_id);
1816}
1817
1818static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1819{
1820 int i;
1821
1822 for (i = 0; i < adev->mode_info.num_dig; i++)
1823 adev->mode_info.afmt[i] = NULL((void *)0);
1824
1825 /* DCE11 has audio blocks tied to DIG encoders */
1826 for (i = 0; i < adev->mode_info.num_dig; i++) {
1827 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL(0x0001 | 0x0004));
1828 if (adev->mode_info.afmt[i]) {
1829 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1830 adev->mode_info.afmt[i]->id = i;
1831 } else {
1832 int j;
1833 for (j = 0; j < i; j++) {
1834 kfree(adev->mode_info.afmt[j]);
1835 adev->mode_info.afmt[j] = NULL((void *)0);
1836 }
1837 return -ENOMEM12;
1838 }
1839 }
1840 return 0;
1841}
1842
1843static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1844{
1845 int i;
1846
1847 for (i = 0; i < adev->mode_info.num_dig; i++) {
1848 kfree(adev->mode_info.afmt[i]);
1849 adev->mode_info.afmt[i] = NULL((void *)0);
1850 }
1851}
1852
1853static const u32 vga_control_regs[6] =
1854{
1855 mmD1VGA_CONTROL0xcc,
1856 mmD2VGA_CONTROL0xce,
1857 mmD3VGA_CONTROL0xf8,
1858 mmD4VGA_CONTROL0xf9,
1859 mmD5VGA_CONTROL0xfa,
1860 mmD6VGA_CONTROL0xfb,
1861};
1862
1863static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool_Bool enable)
1864{
1865 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
1866 struct drm_device *dev = crtc->dev;
1867 struct amdgpu_device *adev = drm_to_adev(dev);
1868 u32 vga_control;
1869
1870 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id])amdgpu_device_rreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id
]), 0) & ~1;
1871 if (enable)
1872 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1)amdgpu_device_wreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id
]), (vga_control | 1), 0);
1873 else
1874 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control)amdgpu_device_wreg(adev, (vga_control_regs[amdgpu_crtc->crtc_id
]), (vga_control), 0);
1875}
1876
1877static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool_Bool enable)
1878{
1879 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
1880 struct drm_device *dev = crtc->dev;
1881 struct amdgpu_device *adev = drm_to_adev(dev);
1882
1883 if (enable)
1884 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1)amdgpu_device_wreg(adev, (0x1a00 + amdgpu_crtc->crtc_offset
), (1), 0);
1885 else
1886 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a00 + amdgpu_crtc->crtc_offset
), (0), 0);
1887}
1888
1889static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1890 struct drm_framebuffer *fb,
1891 int x, int y, int atomic)
1892{
1893 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
1894 struct drm_device *dev = crtc->dev;
1895 struct amdgpu_device *adev = drm_to_adev(dev);
1896 struct drm_framebuffer *target_fb;
1897 struct drm_gem_object *obj;
1898 struct amdgpu_bo *abo;
1899 uint64_t fb_location, tiling_flags;
1900 uint32_t fb_format, fb_pitch_pixels;
1901 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE)(((0) & ~0x3) | (0x3 & ((ENDIAN_NONE) << 0x0)));
1902 u32 pipe_config;
1903 u32 tmp, viewport_w, viewport_h;
1904 int r;
1905 bool_Bool bypass_lut = false0;
1906 struct drm_format_name_buf format_name;
1907
1908 /* no fb bound */
1909 if (!atomic && !crtc->primary->fb) {
1910 DRM_DEBUG_KMS("No FB bound\n")__drm_dbg(DRM_UT_KMS, "No FB bound\n");
1911 return 0;
1912 }
1913
1914 if (atomic)
1915 target_fb = fb;
1916 else
1917 target_fb = crtc->primary->fb;
1918
1919 /* If atomic, assume fb object is pinned & idle & fenced and
1920 * just update base pointers
1921 */
1922 obj = target_fb->obj[0];
1923 abo = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );});
1924 r = amdgpu_bo_reserve(abo, false0);
1925 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
1926 return r;
1927
1928 if (!atomic) {
1929 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM0x4);
1930 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
1931 amdgpu_bo_unreserve(abo);
1932 return -EINVAL22;
1933 }
1934 }
1935 fb_location = amdgpu_bo_gpu_offset(abo);
1936
1937 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1938 amdgpu_bo_unreserve(abo);
1939
1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG)(((__u64)(tiling_flags) >> 4) & 0x1f);
1941
1942 switch (target_fb->format->format) {
1943 case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24)):
1944 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0)(((0) & ~0x3) | (0x3 & ((0) << 0x0)));
1945 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
));
1946 break;
1947 case DRM_FORMAT_XRGB4444((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24)):
1948 case DRM_FORMAT_ARGB4444((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24)):
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2)(((fb_format) & ~0x700) | (0x700 & ((2) << 0x8)
));
1951#ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1953 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)));
1954#endif
1955 break;
1956 case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24)):
1957 case DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24)):
1958 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
));
1960#ifdef __BIG_ENDIAN
1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1962 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)));
1963#endif
1964 break;
1965 case DRM_FORMAT_BGRX5551((__u32)('B') | ((__u32)('X') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24)):
1966 case DRM_FORMAT_BGRA5551((__u32)('B') | ((__u32)('A') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24)):
1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5)(((fb_format) & ~0x700) | (0x700 & ((5) << 0x8)
));
1969#ifdef __BIG_ENDIAN
1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1971 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)));
1972#endif
1973 break;
1974 case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24)):
1975 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1)(((0) & ~0x3) | (0x3 & ((1) << 0x0)));
1976 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1)(((fb_format) & ~0x700) | (0x700 & ((1) << 0x8)
));
1977#ifdef __BIG_ENDIAN
1978 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)))
1979 ENDIAN_8IN16)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN16) <<
0x0)));
1980#endif
1981 break;
1982 case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24)):
1983 case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24)):
1984 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
1985 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
));
1986#ifdef __BIG_ENDIAN
1987 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
1988 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)));
1989#endif
1990 break;
1991 case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24)):
1992 case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24)):
1993 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
1994 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1)(((fb_format) & ~0x700) | (0x700 & ((1) << 0x8)
));
1995#ifdef __BIG_ENDIAN
1996 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
1997 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)));
1998#endif
1999 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2000 bypass_lut = true1;
2001 break;
2002 case DRM_FORMAT_BGRX1010102((__u32)('B') | ((__u32)('X') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24)):
2003 case DRM_FORMAT_BGRA1010102((__u32)('B') | ((__u32)('A') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24)):
2004 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4)(((fb_format) & ~0x700) | (0x700 & ((4) << 0x8)
));
2006#ifdef __BIG_ENDIAN
2007 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
2008 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)));
2009#endif
2010 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2011 bypass_lut = true1;
2012 break;
2013 case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24)):
2014 case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24)):
2015 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2)(((0) & ~0x3) | (0x3 & ((2) << 0x0)));
2016 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0)(((fb_format) & ~0x700) | (0x700 & ((0) << 0x8)
));
2017 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2)(((fb_swap) & ~0x30) | (0x30 & ((2) << 0x4)));
2018 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2)(((fb_swap) & ~0x300) | (0x300 & ((2) << 0x8)));
2019#ifdef __BIG_ENDIAN
2020 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)))
2021 ENDIAN_8IN32)(((fb_swap) & ~0x3) | (0x3 & ((ENDIAN_8IN32) <<
0x0)));
2022#endif
2023 break;
2024 default:
2025 DRM_ERROR("Unsupported screen format %s\n",__drm_err("Unsupported screen format %s\n", drm_get_format_name
(target_fb->format->format, &format_name))
2026 drm_get_format_name(target_fb->format->format, &format_name))__drm_err("Unsupported screen format %s\n", drm_get_format_name
(target_fb->format->format, &format_name));
2027 return -EINVAL22;
2028 }
2029
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == ARRAY_2D_TILED_THIN1) {
2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2032
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH)(((__u64)(tiling_flags) >> 15) & 0x3);
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT)(((__u64)(tiling_flags) >> 17) & 0x3);
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT)(((__u64)(tiling_flags) >> 19) & 0x3);
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)(((__u64)(tiling_flags) >> 9) & 0x7);
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS)(((__u64)(tiling_flags) >> 21) & 0x3);
2038
2039 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks)(((fb_format) & ~0xc) | (0xc & ((num_banks) << 0x2
)));
2040 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_2D_TILED_THIN1
) << 0x14)))
2041 ARRAY_2D_TILED_THIN1)(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_2D_TILED_THIN1
) << 0x14)));
2042 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,(((fb_format) & ~0xe000) | (0xe000 & ((tile_split) <<
0xd)))
2043 tile_split)(((fb_format) & ~0xe000) | (0xe000 & ((tile_split) <<
0xd)));
2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw)(((fb_format) & ~0xc0) | (0xc0 & ((bankw) << 0x6
)));
2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh)(((fb_format) & ~0x1800) | (0x1800 & ((bankh) <<
0xb)));
2046 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,(((fb_format) & ~0xc0000) | (0xc0000 & ((mtaspect) <<
0x12)))
2047 mtaspect)(((fb_format) & ~0xc0000) | (0xc0000 & ((mtaspect) <<
0x12)));
2048 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,(((fb_format) & ~0x60000000) | (0x60000000 & ((ADDR_SURF_MICRO_TILING_DISPLAY
) << 0x1d)))
2049 ADDR_SURF_MICRO_TILING_DISPLAY)(((fb_format) & ~0x60000000) | (0x60000000 & ((ADDR_SURF_MICRO_TILING_DISPLAY
) << 0x1d)));
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)(((__u64)(tiling_flags) >> 0) & 0xf) == ARRAY_1D_TILED_THIN1) {
2051 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_1D_TILED_THIN1
) << 0x14)))
2052 ARRAY_1D_TILED_THIN1)(((fb_format) & ~0xf00000) | (0xf00000 & ((ARRAY_1D_TILED_THIN1
) << 0x14)));
2053 }
2054
2055 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,(((fb_format) & ~0x1f000000) | (0x1f000000 & ((pipe_config
) << 0x18)))
2056 pipe_config)(((fb_format) & ~0x1f000000) | (0x1f000000 & ((pipe_config
) << 0x18)));
2057
2058 dce_v11_0_vga_enable(crtc, false0);
2059
2060 /* Make sure surface address is updated at vertical blank rather than
2061 * horizontal blank
2062 */
2063 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), 0);
2064 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)))
2065 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
2066 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a12 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2067
2068 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0)
2069 upper_32_bits(fb_location))amdgpu_device_wreg(adev, (0x1a07 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0);
2070 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a08 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0)
2071 upper_32_bits(fb_location))amdgpu_device_wreg(adev, (0x1a08 + amdgpu_crtc->crtc_offset
), (((u32)(((fb_location) >> 16) >> 16))), 0);
2072 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), ((u32)fb_location & 0xffffff00), 0)
2073 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK)amdgpu_device_wreg(adev, (0x1a04 + amdgpu_crtc->crtc_offset
), ((u32)fb_location & 0xffffff00), 0);
2074 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a05 + amdgpu_crtc->crtc_offset
), ((u32) fb_location & 0xffffff00), 0)
2075 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK)amdgpu_device_wreg(adev, (0x1a05 + amdgpu_crtc->crtc_offset
), ((u32) fb_location & 0xffffff00), 0);
2076 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format)amdgpu_device_wreg(adev, (0x1a01 + amdgpu_crtc->crtc_offset
), (fb_format), 0);
2077 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap)amdgpu_device_wreg(adev, (0x1a03 + amdgpu_crtc->crtc_offset
), (fb_swap), 0);
2078
2079 /*
2080 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2081 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2082 * retain the full precision throughout the pipeline.
2083 */
2084 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a02 + amdgpu_crtc->crtc_offset
), 0);
2085 if (bypass_lut)
2086 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1)(((tmp) & ~0x100) | (0x100 & ((1) << 0x8)));
2087 else
2088 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0)(((tmp) & ~0x100) | (0x100 & ((0) << 0x8)));
2089 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a02 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2090
2091 if (bypass_lut)
2092 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n")__drm_dbg(DRM_UT_KMS, "Bypassing hardware LUT due to 10 bit fb scanout.\n"
);
2093
2094 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a09 + amdgpu_crtc->crtc_offset
), (0), 0);
2095 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0a + amdgpu_crtc->crtc_offset
), (0), 0);
2096 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0b + amdgpu_crtc->crtc_offset
), (0), 0);
2097 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a0c + amdgpu_crtc->crtc_offset
), (0), 0);
2098 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width)amdgpu_device_wreg(adev, (0x1a0d + amdgpu_crtc->crtc_offset
), (target_fb->width), 0);
2099 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height)amdgpu_device_wreg(adev, (0x1a0e + amdgpu_crtc->crtc_offset
), (target_fb->height), 0);
2100
2101 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2102 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels)amdgpu_device_wreg(adev, (0x1a06 + amdgpu_crtc->crtc_offset
), (fb_pitch_pixels), 0);
2103
2104 dce_v11_0_grph_enable(crtc, true1);
2105
2106 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1ac3 + amdgpu_crtc->crtc_offset
), (target_fb->height), 0)
2107 target_fb->height)amdgpu_device_wreg(adev, (0x1ac3 + amdgpu_crtc->crtc_offset
), (target_fb->height), 0);
2108
2109 x &= ~3;
2110 y &= ~1;
2111 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1b5c + amdgpu_crtc->crtc_offset
), ((x << 16) | y), 0)
2112 (x << 16) | y)amdgpu_device_wreg(adev, (0x1b5c + amdgpu_crtc->crtc_offset
), ((x << 16) | y), 0);
2113 viewport_w = crtc->mode.hdisplay;
2114 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2115 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1b5d + amdgpu_crtc->crtc_offset
), ((viewport_w << 16) | viewport_h), 0)
2116 (viewport_w << 16) | viewport_h)amdgpu_device_wreg(adev, (0x1b5d + amdgpu_crtc->crtc_offset
), ((viewport_w << 16) | viewport_h), 0);
2117
2118 /* set pageflip to happen anywhere in vblank interval */
2119 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1bbe + amdgpu_crtc->crtc_offset
), (0), 0);
2120
2121 if (!atomic && fb && fb != crtc->primary->fb) {
2122 abo = gem_to_amdgpu_bo(fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((fb->obj[0])); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );});
2123 r = amdgpu_bo_reserve(abo, true1);
2124 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
2125 return r;
2126 amdgpu_bo_unpin(abo);
2127 amdgpu_bo_unreserve(abo);
2128 }
2129
2130 /* Bytes per pixel may have changed */
2131 dce_v11_0_bandwidth_update(adev);
2132
2133 return 0;
2134}
2135
2136static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2137 struct drm_display_mode *mode)
2138{
2139 struct drm_device *dev = crtc->dev;
2140 struct amdgpu_device *adev = drm_to_adev(dev);
2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2142 u32 tmp;
2143
2144 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1ac0 + amdgpu_crtc->crtc_offset
), 0);
2145 if (mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
2146 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1)(((tmp) & ~0x8) | (0x8 & ((1) << 0x3)));
2147 else
2148 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0)(((tmp) & ~0x8) | (0x8 & ((0) << 0x3)));
2149 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1ac0 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2150}
2151
2152static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2153{
2154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2155 struct drm_device *dev = crtc->dev;
2156 struct amdgpu_device *adev = drm_to_adev(dev);
2157 u16 *r, *g, *b;
2158 int i;
2159 u32 tmp;
2160
2161 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id)__drm_dbg(DRM_UT_KMS, "%d\n", amdgpu_crtc->crtc_id);
2162
2163 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a35 + amdgpu_crtc->crtc_offset
), 0);
2164 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0)));
2165 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a35 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2166
2167 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a2d + amdgpu_crtc->crtc_offset
), 0);
2168 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
2169 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a2d + amdgpu_crtc->crtc_offset
), (tmp), 0);
2170
2171 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a10 + amdgpu_crtc->crtc_offset
), 0);
2172 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
2173 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a10 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2174
2175 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a80 + amdgpu_crtc->crtc_offset
), (0), 0);
2176
2177 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a81 + amdgpu_crtc->crtc_offset
), (0), 0);
2178 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a82 + amdgpu_crtc->crtc_offset
), (0), 0);
2179 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a83 + amdgpu_crtc->crtc_offset
), (0), 0);
2180
2181 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a84 + amdgpu_crtc->crtc_offset
), (0xffff), 0);
2182 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a85 + amdgpu_crtc->crtc_offset
), (0xffff), 0);
2183 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff)amdgpu_device_wreg(adev, (0x1a86 + amdgpu_crtc->crtc_offset
), (0xffff), 0);
2184
2185 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a78 + amdgpu_crtc->crtc_offset
), (0), 0);
2186 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007)amdgpu_device_wreg(adev, (0x1a7e + amdgpu_crtc->crtc_offset
), (0x00000007), 0);
2187
2188 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a79 + amdgpu_crtc->crtc_offset
), (0), 0);
2189 r = crtc->gamma_store;
2190 g = r + crtc->gamma_size;
2191 b = g + crtc->gamma_size;
2192 for (i = 0; i < 256; i++) {
2193 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
2194 ((*r++ & 0xffc0) << 14) |amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
2195 ((*g++ & 0xffc0) << 4) |amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0)
2196 (*b++ >> 6))amdgpu_device_wreg(adev, (0x1a7c + amdgpu_crtc->crtc_offset
), (((*r++ & 0xffc0) << 14) | ((*g++ & 0xffc0) <<
4) | (*b++ >> 6)), 0);
2197 }
2198
2199 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a58 + amdgpu_crtc->crtc_offset
), 0);
2200 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0)));
2201 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0)(((tmp) & ~0x3000) | (0x3000 & ((0) << 0xc)));
2202 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0)(((tmp) & ~0x300) | (0x300 & ((0) << 0x8)));
2203 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a58 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2204
2205 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a59 + amdgpu_crtc->crtc_offset
), 0);
2206 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0)(((tmp) & ~0x3) | (0x3 & ((0) << 0x0)));
2207 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a59 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2208
2209 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1aa0 + amdgpu_crtc->crtc_offset
), 0);
2210 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0)));
2211 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1aa0 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2212
2213 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a3c + amdgpu_crtc->crtc_offset
), 0);
2214 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0)(((tmp) & ~0x7) | (0x7 & ((0) << 0x0)));
2215 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a3c + amdgpu_crtc->crtc_offset
), (tmp), 0);
2216
2217 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2218 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0)amdgpu_device_wreg(adev, (0x1a50 + amdgpu_crtc->crtc_offset
), (0), 0);
2219 /* XXX this only needs to be programmed once per crtc at startup,
2220 * not sure where the best place for it is
2221 */
2222 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1abc + amdgpu_crtc->crtc_offset
), 0);
2223 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1)));
2224 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1abc + amdgpu_crtc->crtc_offset
), (tmp), 0);
2225}
2226
2227static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2228{
2229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
2230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2231
2232 switch (amdgpu_encoder->encoder_id) {
2233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
2234 if (dig->linkb)
2235 return 1;
2236 else
2237 return 0;
2238 break;
2239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
2240 if (dig->linkb)
2241 return 3;
2242 else
2243 return 2;
2244 break;
2245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
2246 if (dig->linkb)
2247 return 5;
2248 else
2249 return 4;
2250 break;
2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
2252 return 6;
2253 break;
2254 default:
2255 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id)__drm_err("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id
);
2256 return 0;
2257 }
2258}
2259
2260/**
2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2262 *
2263 * @crtc: drm crtc
2264 *
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2268 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2269 * as there is no need to program the PLL itself. If we are not able to
2270 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2271 * avoid messing up an existing monitor.
2272 *
2273 * Asic specific PLL information
2274 *
2275 * DCE 10.x
2276 * Tonga
2277 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2278 * CI
2279 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2280 *
2281 */
2282static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2283{
2284 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2285 struct drm_device *dev = crtc->dev;
2286 struct amdgpu_device *adev = drm_to_adev(dev);
2287 u32 pll_in_use;
2288 int pll;
2289
2290 if ((adev->asic_type == CHIP_POLARIS10) ||
2291 (adev->asic_type == CHIP_POLARIS11) ||
2292 (adev->asic_type == CHIP_POLARIS12) ||
2293 (adev->asic_type == CHIP_VEGAM)) {
2294 struct amdgpu_encoder *amdgpu_encoder =
2295 to_amdgpu_encoder(amdgpu_crtc->encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (amdgpu_crtc->encoder); (struct amdgpu_encoder *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_encoder, base) )
;});
2296 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2297
2298 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder
)) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder)) == 5)))
2299 return ATOM_DP_DTO11;
2300
2301 switch (amdgpu_encoder->encoder_id) {
2302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
2303 if (dig->linkb)
2304 return ATOM_COMBOPHY_PLL121;
2305 else
2306 return ATOM_COMBOPHY_PLL020;
2307 break;
2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
2309 if (dig->linkb)
2310 return ATOM_COMBOPHY_PLL323;
2311 else
2312 return ATOM_COMBOPHY_PLL222;
2313 break;
2314 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
2315 if (dig->linkb)
2316 return ATOM_COMBOPHY_PLL525;
2317 else
2318 return ATOM_COMBOPHY_PLL424;
2319 break;
2320 default:
2321 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id)__drm_err("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id
);
2322 return ATOM_PPLL_INVALID0xFF;
2323 }
2324 }
2325
2326 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder
)) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder)) == 5))) {
2327 if (adev->clock.dp_extclk)
2328 /* skip PPLL programming if using ext clock */
2329 return ATOM_PPLL_INVALID0xFF;
2330 else {
2331 /* use the same PPLL for all DP monitors */
2332 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2333 if (pll != ATOM_PPLL_INVALID0xFF)
2334 return pll;
2335 }
2336 } else {
2337 /* use the same PPLL for all monitors with the same clock */
2338 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2339 if (pll != ATOM_PPLL_INVALID0xFF)
2340 return pll;
2341 }
2342
2343 /* XXX need to determine what plls are available on each DCE11 part */
2344 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2345 if (adev->flags & AMD_IS_APU) {
2346 if (!(pll_in_use & (1 << ATOM_PPLL10)))
2347 return ATOM_PPLL10;
2348 if (!(pll_in_use & (1 << ATOM_PPLL02)))
2349 return ATOM_PPLL02;
2350 DRM_ERROR("unable to allocate a PPLL\n")__drm_err("unable to allocate a PPLL\n");
2351 return ATOM_PPLL_INVALID0xFF;
2352 } else {
2353 if (!(pll_in_use & (1 << ATOM_PPLL21)))
2354 return ATOM_PPLL21;
2355 if (!(pll_in_use & (1 << ATOM_PPLL10)))
2356 return ATOM_PPLL10;
2357 if (!(pll_in_use & (1 << ATOM_PPLL02)))
2358 return ATOM_PPLL02;
2359 DRM_ERROR("unable to allocate a PPLL\n")__drm_err("unable to allocate a PPLL\n");
2360 return ATOM_PPLL_INVALID0xFF;
2361 }
2362 return ATOM_PPLL_INVALID0xFF;
2363}
2364
2365static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool_Bool lock)
2366{
2367 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2368 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2369 uint32_t cur_lock;
2370
2371 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a6e + amdgpu_crtc->crtc_offset
), 0);
2372 if (lock)
2373 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1)(((cur_lock) & ~0x10000) | (0x10000 & ((1) << 0x10
)));
2374 else
2375 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0)(((cur_lock) & ~0x10000) | (0x10000 & ((0) << 0x10
)));
2376 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock)amdgpu_device_wreg(adev, (0x1a6e + amdgpu_crtc->crtc_offset
), (cur_lock), 0);
2377}
2378
2379static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2380{
2381 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2382 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2383 u32 tmp;
2384
2385 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), 0);
2386 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0)));
2387 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2388}
2389
2390static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2391{
2392 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2393 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2394 u32 tmp;
2395
2396 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a69 + amdgpu_crtc->crtc_offset
), (((u32)(((amdgpu_crtc->cursor_addr) >> 16) >>
16))), 0)
2397 upper_32_bits(amdgpu_crtc->cursor_addr))amdgpu_device_wreg(adev, (0x1a69 + amdgpu_crtc->crtc_offset
), (((u32)(((amdgpu_crtc->cursor_addr) >> 16) >>
16))), 0);
2398 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a67 + amdgpu_crtc->crtc_offset
), (((u32)(amdgpu_crtc->cursor_addr))), 0)
2399 lower_32_bits(amdgpu_crtc->cursor_addr))amdgpu_device_wreg(adev, (0x1a67 + amdgpu_crtc->crtc_offset
), (((u32)(amdgpu_crtc->cursor_addr))), 0);
2400
2401 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset)amdgpu_device_rreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), 0);
2402 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
2403 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2)(((tmp) & ~0x300) | (0x300 & ((2) << 0x8)));
2404 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp)amdgpu_device_wreg(adev, (0x1a66 + amdgpu_crtc->crtc_offset
), (tmp), 0);
2405}
2406
2407static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2408 int x, int y)
2409{
2410 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2411 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2412 int xorigin = 0, yorigin = 0;
2413
2414 amdgpu_crtc->cursor_x = x;
2415 amdgpu_crtc->cursor_y = y;
2416
2417 /* avivo cursor are offset into the total surface */
2418 x += crtc->x;
2419 y += crtc->y;
2420 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y)__drm_dbg(DRM_UT_CORE, "x %d y %d c->x %d c->y %d\n", x
, y, crtc->x, crtc->y);
2421
2422 if (x < 0) {
2423 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1)(((-x)<(amdgpu_crtc->max_cursor_width - 1))?(-x):(amdgpu_crtc
->max_cursor_width - 1));
2424 x = 0;
2425 }
2426 if (y < 0) {
2427 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1)(((-y)<(amdgpu_crtc->max_cursor_height - 1))?(-y):(amdgpu_crtc
->max_cursor_height - 1));
2428 y = 0;
2429 }
2430
2431 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y)amdgpu_device_wreg(adev, (0x1a6a + amdgpu_crtc->crtc_offset
), ((x << 16) | y), 0);
2432 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin)amdgpu_device_wreg(adev, (0x1a6b + amdgpu_crtc->crtc_offset
), ((xorigin << 16) | yorigin), 0);
2433 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,amdgpu_device_wreg(adev, (0x1a68 + amdgpu_crtc->crtc_offset
), (((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc
->cursor_height - 1)), 0)
2434 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1))amdgpu_device_wreg(adev, (0x1a68 + amdgpu_crtc->crtc_offset
), (((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc
->cursor_height - 1)), 0);
2435
2436 return 0;
2437}
2438
2439static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2440 int x, int y)
2441{
2442 int ret;
2443
2444 dce_v11_0_lock_cursor(crtc, true1);
2445 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2446 dce_v11_0_lock_cursor(crtc, false0);
2447
2448 return ret;
2449}
2450
2451static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2452 struct drm_file *file_priv,
2453 uint32_t handle,
2454 uint32_t width,
2455 uint32_t height,
2456 int32_t hot_x,
2457 int32_t hot_y)
2458{
2459 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2460 struct drm_gem_object *obj;
2461 struct amdgpu_bo *aobj;
2462 int ret;
2463
2464 if (!handle) {
2465 /* turn off cursor */
2466 dce_v11_0_hide_cursor(crtc);
2467 obj = NULL((void *)0);
2468 goto unpin;
2469 }
2470
2471 if ((width > amdgpu_crtc->max_cursor_width) ||
2472 (height > amdgpu_crtc->max_cursor_height)) {
2473 DRM_ERROR("bad cursor width or height %d x %d\n", width, height)__drm_err("bad cursor width or height %d x %d\n", width, height
);
2474 return -EINVAL22;
2475 }
2476
2477 obj = drm_gem_object_lookup(file_priv, handle);
2478 if (!obj) {
2479 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id)__drm_err("Cannot find cursor object %x for crtc %d\n", handle
, amdgpu_crtc->crtc_id);
2480 return -ENOENT2;
2481 }
2482
2483 aobj = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );});
2484 ret = amdgpu_bo_reserve(aobj, false0);
2485 if (ret != 0) {
2486 drm_gem_object_put(obj);
2487 return ret;
2488 }
2489
2490 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM0x4);
2491 amdgpu_bo_unreserve(aobj);
2492 if (ret) {
2493 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret)__drm_err("Failed to pin new cursor BO (%d)\n", ret);
2494 drm_gem_object_put(obj);
2495 return ret;
2496 }
2497 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2498
2499 dce_v11_0_lock_cursor(crtc, true1);
2500
2501 if (width != amdgpu_crtc->cursor_width ||
2502 height != amdgpu_crtc->cursor_height ||
2503 hot_x != amdgpu_crtc->cursor_hot_x ||
2504 hot_y != amdgpu_crtc->cursor_hot_y) {
2505 int x, y;
2506
2507 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2508 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2509
2510 dce_v11_0_cursor_move_locked(crtc, x, y);
2511
2512 amdgpu_crtc->cursor_width = width;
2513 amdgpu_crtc->cursor_height = height;
2514 amdgpu_crtc->cursor_hot_x = hot_x;
2515 amdgpu_crtc->cursor_hot_y = hot_y;
2516 }
2517
2518 dce_v11_0_show_cursor(crtc);
2519 dce_v11_0_lock_cursor(crtc, false0);
2520
2521unpin:
2522 if (amdgpu_crtc->cursor_bo) {
2523 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((amdgpu_crtc->cursor_bo)); (struct amdgpu_bo *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.base) );
});
2524 ret = amdgpu_bo_reserve(aobj, true1);
2525 if (likely(ret == 0)__builtin_expect(!!(ret == 0), 1)) {
2526 amdgpu_bo_unpin(aobj);
2527 amdgpu_bo_unreserve(aobj);
2528 }
2529 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2530 }
2531
2532 amdgpu_crtc->cursor_bo = obj;
2533 return 0;
2534}
2535
2536static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2537{
2538 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2539
2540 if (amdgpu_crtc->cursor_bo) {
2541 dce_v11_0_lock_cursor(crtc, true1);
2542
2543 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2544 amdgpu_crtc->cursor_y);
2545
2546 dce_v11_0_show_cursor(crtc);
2547
2548 dce_v11_0_lock_cursor(crtc, false0);
2549 }
2550}
2551
2552static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2553 u16 *blue, uint32_t size,
2554 struct drm_modeset_acquire_ctx *ctx)
2555{
2556 dce_v11_0_crtc_load_lut(crtc);
2557
2558 return 0;
2559}
2560
2561static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2562{
2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2564
2565 drm_crtc_cleanup(crtc);
2566 kfree(amdgpu_crtc);
2567}
2568
2569static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2570 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2571 .cursor_move = dce_v11_0_crtc_cursor_move,
2572 .gamma_set = dce_v11_0_crtc_gamma_set,
2573 .set_config = amdgpu_display_crtc_set_config,
2574 .destroy = dce_v11_0_crtc_destroy,
2575 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2576 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2577 .enable_vblank = amdgpu_enable_vblank_kms,
2578 .disable_vblank = amdgpu_disable_vblank_kms,
2579 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2580};
2581
2582static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2583{
2584 struct drm_device *dev = crtc->dev;
2585 struct amdgpu_device *adev = drm_to_adev(dev);
2586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2587 unsigned type;
2588
2589 switch (mode) {
2590 case DRM_MODE_DPMS_ON0:
2591 amdgpu_crtc->enabled = true1;
2592 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE1);
2593 dce_v11_0_vga_enable(crtc, true1);
2594 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE0);
2595 dce_v11_0_vga_enable(crtc, false0);
2596 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2597 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2598 amdgpu_crtc->crtc_id);
2599 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2600 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2601 drm_crtc_vblank_on(crtc);
2602 dce_v11_0_crtc_load_lut(crtc);
2603 break;
2604 case DRM_MODE_DPMS_STANDBY1:
2605 case DRM_MODE_DPMS_SUSPEND2:
2606 case DRM_MODE_DPMS_OFF3:
2607 drm_crtc_vblank_off(crtc);
2608 if (amdgpu_crtc->enabled) {
2609 dce_v11_0_vga_enable(crtc, true1);
2610 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE1);
2611 dce_v11_0_vga_enable(crtc, false0);
2612 }
2613 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE0);
2614 amdgpu_crtc->enabled = false0;
2615 break;
2616 }
2617 /* adjust pm to dpms */
2618 amdgpu_pm_compute_clocks(adev);
2619}
2620
2621static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2622{
2623 /* disable crtc pair power gating before programming */
2624 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE0);
2625 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE1);
2626 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF3);
2627}
2628
2629static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2630{
2631 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON0);
2632 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE0);
2633}
2634
2635static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2636{
2637 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2638 struct drm_device *dev = crtc->dev;
2639 struct amdgpu_device *adev = drm_to_adev(dev);
2640 struct amdgpu_atom_ss ss;
2641 int i;
2642
2643 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF3);
2644 if (crtc->primary->fb) {
2645 int r;
2646 struct amdgpu_bo *abo;
2647
2648 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
= ((crtc->primary->fb->obj[0])); (struct amdgpu_bo *
)( (char *)__mptr - __builtin_offsetof(struct amdgpu_bo, tbo.
base) );});
2649 r = amdgpu_bo_reserve(abo, true1);
2650 if (unlikely(r)__builtin_expect(!!(r), 0))
2651 DRM_ERROR("failed to reserve abo before unpin\n")__drm_err("failed to reserve abo before unpin\n");
2652 else {
2653 amdgpu_bo_unpin(abo);
2654 amdgpu_bo_unreserve(abo);
2655 }
2656 }
2657 /* disable the GRPH */
2658 dce_v11_0_grph_enable(crtc, false0);
2659
2660 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE1);
2661
2662 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2663 if (adev->mode_info.crtcs[i] &&
2664 adev->mode_info.crtcs[i]->enabled &&
2665 i != amdgpu_crtc->crtc_id &&
2666 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2667 /* one other crtc is using this pll don't turn
2668 * off the pll
2669 */
2670 goto done;
2671 }
2672 }
2673
2674 switch (amdgpu_crtc->pll_id) {
2675 case ATOM_PPLL02:
2676 case ATOM_PPLL10:
2677 case ATOM_PPLL21:
2678 /* disable the ppll */
2679 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2680 0, 0, ATOM_DISABLE0, 0, 0, 0, 0, 0, false0, &ss);
2681 break;
2682 case ATOM_COMBOPHY_PLL020:
2683 case ATOM_COMBOPHY_PLL121:
2684 case ATOM_COMBOPHY_PLL222:
2685 case ATOM_COMBOPHY_PLL323:
2686 case ATOM_COMBOPHY_PLL424:
2687 case ATOM_COMBOPHY_PLL525:
2688 /* disable the ppll */
2689 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID0xFF, amdgpu_crtc->pll_id,
2690 0, 0, ATOM_DISABLE0, 0, 0, 0, 0, 0, false0, &ss);
2691 break;
2692 default:
2693 break;
2694 }
2695done:
2696 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID0xFF;
2697 amdgpu_crtc->adjusted_clock = 0;
2698 amdgpu_crtc->encoder = NULL((void *)0);
2699 amdgpu_crtc->connector = NULL((void *)0);
2700}
2701
2702static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2703 struct drm_display_mode *mode,
2704 struct drm_display_mode *adjusted_mode,
2705 int x, int y, struct drm_framebuffer *old_fb)
2706{
2707 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2708 struct drm_device *dev = crtc->dev;
2709 struct amdgpu_device *adev = drm_to_adev(dev);
2710
2711 if (!amdgpu_crtc->adjusted_clock)
2712 return -EINVAL22;
2713
2714 if ((adev->asic_type == CHIP_POLARIS10) ||
2715 (adev->asic_type == CHIP_POLARIS11) ||
2716 (adev->asic_type == CHIP_POLARIS12) ||
2717 (adev->asic_type == CHIP_VEGAM)) {
2718 struct amdgpu_encoder *amdgpu_encoder =
2719 to_amdgpu_encoder(amdgpu_crtc->encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (amdgpu_crtc->encoder); (struct amdgpu_encoder *)( (char
*)__mptr - __builtin_offsetof(struct amdgpu_encoder, base) )
;});
2720 int encoder_mode =
2721 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2722
2723 /* SetPixelClock calculates the plls and ss values now */
2724 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2725 amdgpu_crtc->pll_id,
2726 encoder_mode, amdgpu_encoder->encoder_id,
2727 adjusted_mode->clock, 0, 0, 0, 0,
2728 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2729 } else {
2730 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2731 }
2732 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2733 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2734 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2735 amdgpu_atombios_crtc_scaler_setup(crtc);
2736 dce_v11_0_cursor_reset(crtc);
2737 /* update the hw version fpr dpm */
2738 amdgpu_crtc->hw_mode = *adjusted_mode;
2739
2740 return 0;
2741}
2742
2743static bool_Bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2744 const struct drm_display_mode *mode,
2745 struct drm_display_mode *adjusted_mode)
2746{
2747 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
= (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_encoder *encoder;
2750
2751 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );})) {
2753 if (encoder->crtc == crtc) {
2754 amdgpu_crtc->encoder = encoder;
2755 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2756 break;
2757 }
2758 }
2759 if ((amdgpu_crtc->encoder == NULL((void *)0)) || (amdgpu_crtc->connector == NULL((void *)0))) {
2760 amdgpu_crtc->encoder = NULL((void *)0);
2761 amdgpu_crtc->connector = NULL((void *)0);
2762 return false0;
2763 }
2764 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2765 return false0;
2766 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2767 return false0;
2768 /* pick pll */
2769 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2770 /* if we can't get a PPLL for a non-DP encoder, fail */
2771 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID0xFF) &&
2772 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))(((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder
)) == 0) || ((amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc
->encoder)) == 5)))
2773 return false0;
2774
2775 return true1;
2776}
2777
2778static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2779 struct drm_framebuffer *old_fb)
2780{
2781 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2782}
2783
2784static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2785 struct drm_framebuffer *fb,
2786 int x, int y, enum mode_set_atomic state)
2787{
2788 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2789}
2790
2791static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2792 .dpms = dce_v11_0_crtc_dpms,
2793 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2794 .mode_set = dce_v11_0_crtc_mode_set,
2795 .mode_set_base = dce_v11_0_crtc_set_base,
2796 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2797 .prepare = dce_v11_0_crtc_prepare,
2798 .commit = dce_v11_0_crtc_commit,
2799 .disable = dce_v11_0_crtc_disable,
2800 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2801};
2802
2803static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2804{
2805 struct amdgpu_crtc *amdgpu_crtc;
2806
2807 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2808 (AMDGPUFB_CONN_LIMIT4 * sizeof(struct drm_connector *)), GFP_KERNEL(0x0001 | 0x0004));
2809 if (amdgpu_crtc == NULL((void *)0))
2810 return -ENOMEM12;
2811
2812 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2813
2814 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2815 amdgpu_crtc->crtc_id = index;
2816 adev->mode_info.crtcs[index] = amdgpu_crtc;
2817
2818 amdgpu_crtc->max_cursor_width = 128;
2819 amdgpu_crtc->max_cursor_height = 128;
2820 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2821 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2822
2823 switch (amdgpu_crtc->crtc_id) {
2824 case 0:
2825 default:
2826 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET(0x1b9c - 0x1b9c);
2827 break;
2828 case 1:
2829 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET(0x1d9c - 0x1b9c);
2830 break;
2831 case 2:
2832 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET(0x1f9c - 0x1b9c);
2833 break;
2834 case 3:
2835 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET(0x419c - 0x1b9c);
2836 break;
2837 case 4:
2838 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET(0x439c - 0x1b9c);
2839 break;
2840 case 5:
2841 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET(0x459c - 0x1b9c);
2842 break;
2843 }
2844
2845 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID0xFF;
2846 amdgpu_crtc->adjusted_clock = 0;
2847 amdgpu_crtc->encoder = NULL((void *)0);
2848 amdgpu_crtc->connector = NULL((void *)0);
2849 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2850
2851 return 0;
2852}
2853
2854static int dce_v11_0_early_init(void *handle)
2855{
2856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2857
2858 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2859 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2860
2861 dce_v11_0_set_display_funcs(adev);
2862
2863 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2864
2865 switch (adev->asic_type) {
2866 case CHIP_CARRIZO:
2867 adev->mode_info.num_hpd = 6;
2868 adev->mode_info.num_dig = 9;
2869 break;
2870 case CHIP_STONEY:
2871 adev->mode_info.num_hpd = 6;
2872 adev->mode_info.num_dig = 9;
2873 break;
2874 case CHIP_POLARIS10:
2875 case CHIP_VEGAM:
2876 adev->mode_info.num_hpd = 6;
2877 adev->mode_info.num_dig = 6;
2878 break;
2879 case CHIP_POLARIS11:
2880 case CHIP_POLARIS12:
2881 adev->mode_info.num_hpd = 5;
2882 adev->mode_info.num_dig = 5;
2883 break;
2884 default:
2885 /* FIXME: not supported yet */
2886 return -EINVAL22;
2887 }
2888
2889 dce_v11_0_set_irq_funcs(adev);
2890
2891 return 0;
2892}
2893
2894static int dce_v11_0_sw_init(void *handle)
2895{
2896 int r, i;
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
2899 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2900 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, i + 1, &adev->crtc_irq);
2901 if (r)
2902 return r;
2903 }
2904
2905 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8; i < 20; i += 2) {
2906 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, i, &adev->pageflip_irq);
2907 if (r)
2908 return r;
2909 }
2910
2911 /* HPD hotplug */
2912 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq);
2913 if (r)
2914 return r;
2915
2916 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2917
2918 adev_to_drm(adev)->mode_config.async_page_flip = true1;
2919
2920 adev_to_drm(adev)->mode_config.max_width = 16384;
2921 adev_to_drm(adev)->mode_config.max_height = 16384;
2922
2923 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2924 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2925
2926 adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;
2927
2928 r = amdgpu_display_modeset_create_props(adev);
2929 if (r)
2930 return r;
2931
2932 adev_to_drm(adev)->mode_config.max_width = 16384;
2933 adev_to_drm(adev)->mode_config.max_height = 16384;
2934
2935
2936 /* allocate crtcs */
2937 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2938 r = dce_v11_0_crtc_init(adev, i);
2939 if (r)
2940 return r;
2941 }
2942
2943 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2944 amdgpu_display_print_display_setup(adev_to_drm(adev));
2945 else
2946 return -EINVAL22;
2947
2948 /* setup afmt */
2949 r = dce_v11_0_afmt_init(adev);
2950 if (r)
2951 return r;
2952
2953 r = dce_v11_0_audio_init(adev);
2954 if (r)
2955 return r;
2956
2957 drm_kms_helper_poll_init(adev_to_drm(adev));
2958
2959 adev->mode_info.mode_config_initialized = true1;
2960 return 0;
2961}
2962
2963static int dce_v11_0_sw_fini(void *handle)
2964{
2965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2966
2967 kfree(adev->mode_info.bios_hardcoded_edid);
2968
2969 drm_kms_helper_poll_fini(adev_to_drm(adev));
2970
2971 dce_v11_0_audio_fini(adev);
2972
2973 dce_v11_0_afmt_fini(adev);
2974
2975 drm_mode_config_cleanup(adev_to_drm(adev));
2976 adev->mode_info.mode_config_initialized = false0;
2977
2978 return 0;
2979}
2980
2981static int dce_v11_0_hw_init(void *handle)
2982{
2983 int i;
2984 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2985
2986 dce_v11_0_init_golden_registers(adev);
2987
2988 /* disable vga render */
2989 dce_v11_0_set_vga_render_state(adev, false0);
2990 /* init dig PHYs, disp eng pll */
2991 amdgpu_atombios_crtc_powergate_init(adev);
2992 amdgpu_atombios_encoder_init_dig(adev);
2993 if ((adev->asic_type == CHIP_POLARIS10) ||
2994 (adev->asic_type == CHIP_POLARIS11) ||
2995 (adev->asic_type == CHIP_POLARIS12) ||
2996 (adev->asic_type == CHIP_VEGAM)) {
2997 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2998 DCE_CLOCK_TYPE_DISPCLK0, ATOM_GCK_DFS8);
2999 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3000 DCE_CLOCK_TYPE_DPREFCLK1, ATOM_GCK_DFS8);
3001 } else {
3002 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3003 }
3004
3005 /* initialize hpd */
3006 dce_v11_0_hpd_init(adev);
3007
3008 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3009 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
3010 }
3011
3012 dce_v11_0_pageflip_interrupt_init(adev);
3013
3014 return 0;
3015}
3016
3017static int dce_v11_0_hw_fini(void *handle)
3018{
3019 int i;
3020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021
3022 dce_v11_0_hpd_fini(adev);
3023
3024 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3025 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false0);
3026 }
3027
3028 dce_v11_0_pageflip_interrupt_fini(adev);
3029
3030 return 0;
3031}
3032
3033static int dce_v11_0_suspend(void *handle)
3034{
3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3036
3037 adev->mode_info.bl_level =
3038 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3039
3040 return dce_v11_0_hw_fini(handle);
3041}
3042
3043static int dce_v11_0_resume(void *handle)
3044{
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046 int ret;
3047
3048 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3049 adev->mode_info.bl_level);
3050
3051 ret = dce_v11_0_hw_init(handle);
3052
3053 /* turn on the BL */
3054 if (adev->mode_info.bl_encoder) {
3055 u8 bl_level = amdgpu_display_backlight_get_level(adev,(adev)->mode_info.funcs->backlight_get_level((adev->
mode_info.bl_encoder))
3056 adev->mode_info.bl_encoder)(adev)->mode_info.funcs->backlight_get_level((adev->
mode_info.bl_encoder));
3057 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,(adev)->mode_info.funcs->backlight_set_level((adev->
mode_info.bl_encoder), (bl_level))
3058 bl_level)(adev)->mode_info.funcs->backlight_set_level((adev->
mode_info.bl_encoder), (bl_level));
3059 }
3060
3061 return ret;
3062}
3063
3064static bool_Bool dce_v11_0_is_idle(void *handle)
3065{
3066 return true1;
3067}
3068
3069static int dce_v11_0_wait_for_idle(void *handle)
3070{
3071 return 0;
3072}
3073
3074static int dce_v11_0_soft_reset(void *handle)
3075{
3076 u32 srbm_soft_reset = 0, tmp;
3077 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078
3079 if (dce_v11_0_is_display_hung(adev))
3080 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK0x20;
3081
3082 if (srbm_soft_reset) {
3083 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
3084 tmp |= srbm_soft_reset;
3085 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
3086 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
3087 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
3088
3089 udelay(50);
3090
3091 tmp &= ~srbm_soft_reset;
3092 WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0);
3093 tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0);
Value stored to 'tmp' is never read
3094
3095 /* Wait a little for things to settle down */
3096 udelay(50);
3097 }
3098 return 0;
3099}
3100
3101static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3102 int crtc,
3103 enum amdgpu_interrupt_state state)
3104{
3105 u32 lb_interrupt_mask;
3106
3107 if (crtc >= adev->mode_info.num_crtc) {
3108 DRM_DEBUG("invalid crtc %d\n", crtc)__drm_dbg(DRM_UT_CORE, "invalid crtc %d\n", crtc);
3109 return;
3110 }
3111
3112 switch (state) {
3113 case AMDGPU_IRQ_STATE_DISABLE:
3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3115 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x1) | (0x1 & ((0) << 0x0
)))
3116 VBLANK_INTERRUPT_MASK, 0)(((lb_interrupt_mask) & ~0x1) | (0x1 & ((0) << 0x0
)));
3117 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0);
3118 break;
3119 case AMDGPU_IRQ_STATE_ENABLE:
3120 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3121 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x1) | (0x1 & ((1) << 0x0
)))
3122 VBLANK_INTERRUPT_MASK, 1)(((lb_interrupt_mask) & ~0x1) | (0x1 & ((1) << 0x0
)));
3123 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0);
3124 break;
3125 default:
3126 break;
3127 }
3128}
3129
3130static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3131 int crtc,
3132 enum amdgpu_interrupt_state state)
3133{
3134 u32 lb_interrupt_mask;
3135
3136 if (crtc >= adev->mode_info.num_crtc) {
3137 DRM_DEBUG("invalid crtc %d\n", crtc)__drm_dbg(DRM_UT_CORE, "invalid crtc %d\n", crtc);
3138 return;
3139 }
3140
3141 switch (state) {
3142 case AMDGPU_IRQ_STATE_DISABLE:
3143 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3144 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x10) | (0x10 & ((0) <<
0x4)))
3145 VLINE_INTERRUPT_MASK, 0)(((lb_interrupt_mask) & ~0x10) | (0x10 & ((0) <<
0x4)));
3146 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0);
3147 break;
3148 case AMDGPU_IRQ_STATE_ENABLE:
3149 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac8 + crtc_offsets[crtc]), 0);
3150 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,(((lb_interrupt_mask) & ~0x10) | (0x10 & ((1) <<
0x4)))
3151 VLINE_INTERRUPT_MASK, 1)(((lb_interrupt_mask) & ~0x10) | (0x10 & ((1) <<
0x4)));
3152 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask)amdgpu_device_wreg(adev, (0x1ac8 + crtc_offsets[crtc]), (lb_interrupt_mask
), 0);
3153 break;
3154 default:
3155 break;
3156 }
3157}
3158
3159static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3160 struct amdgpu_irq_src *source,
3161 unsigned hpd,
3162 enum amdgpu_interrupt_state state)
3163{
3164 u32 tmp;
3165
3166 if (hpd >= adev->mode_info.num_hpd) {
3167 DRM_DEBUG("invalid hdp %d\n", hpd)__drm_dbg(DRM_UT_CORE, "invalid hdp %d\n", hpd);
3168 return 0;
3169 }
3170
3171 switch (state) {
3172 case AMDGPU_IRQ_STATE_DISABLE:
3173 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
3174 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0)(((tmp) & ~0x10000) | (0x10000 & ((0) << 0x10))
);
3175 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
);
3176 break;
3177 case AMDGPU_IRQ_STATE_ENABLE:
3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
3179 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1)(((tmp) & ~0x10000) | (0x10000 & ((1) << 0x10))
);
3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
);
3181 break;
3182 default:
3183 break;
3184 }
3185
3186 return 0;
3187}
3188
3189static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3190 struct amdgpu_irq_src *source,
3191 unsigned type,
3192 enum amdgpu_interrupt_state state)
3193{
3194 switch (type) {
3195 case AMDGPU_CRTC_IRQ_VBLANK1:
3196 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3197 break;
3198 case AMDGPU_CRTC_IRQ_VBLANK2:
3199 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3200 break;
3201 case AMDGPU_CRTC_IRQ_VBLANK3:
3202 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3203 break;
3204 case AMDGPU_CRTC_IRQ_VBLANK4:
3205 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3206 break;
3207 case AMDGPU_CRTC_IRQ_VBLANK5:
3208 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3209 break;
3210 case AMDGPU_CRTC_IRQ_VBLANK6:
3211 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3212 break;
3213 case AMDGPU_CRTC_IRQ_VLINE1:
3214 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3215 break;
3216 case AMDGPU_CRTC_IRQ_VLINE2:
3217 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3218 break;
3219 case AMDGPU_CRTC_IRQ_VLINE3:
3220 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3221 break;
3222 case AMDGPU_CRTC_IRQ_VLINE4:
3223 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3224 break;
3225 case AMDGPU_CRTC_IRQ_VLINE5:
3226 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3227 break;
3228 case AMDGPU_CRTC_IRQ_VLINE6:
3229 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3230 break;
3231 default:
3232 break;
3233 }
3234 return 0;
3235}
3236
3237static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3238 struct amdgpu_irq_src *src,
3239 unsigned type,
3240 enum amdgpu_interrupt_state state)
3241{
3242 u32 reg;
3243
3244 if (type >= adev->mode_info.num_crtc) {
3245 DRM_ERROR("invalid pageflip crtc %d\n", type)__drm_err("invalid pageflip crtc %d\n", type);
3246 return -EINVAL22;
3247 }
3248
3249 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type])amdgpu_device_rreg(adev, (0x1a17 + crtc_offsets[type]), 0);
3250 if (state == AMDGPU_IRQ_STATE_DISABLE)
3251 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg &
~0x1), 0)
3252 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK)amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg &
~0x1), 0);
3253 else
3254 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg |
0x1), 0)
3255 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK)amdgpu_device_wreg(adev, (0x1a17 + crtc_offsets[type]), (reg |
0x1), 0);
3256
3257 return 0;
3258}
3259
3260static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *source,
3262 struct amdgpu_iv_entry *entry)
3263{
3264 unsigned long flags;
3265 unsigned crtc_id;
3266 struct amdgpu_crtc *amdgpu_crtc;
3267 struct amdgpu_flip_work *works;
3268
3269 crtc_id = (entry->src_id - 8) >> 1;
3270 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3271
3272 if (crtc_id >= adev->mode_info.num_crtc) {
3273 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id)__drm_err("invalid pageflip crtc %d\n", crtc_id);
3274 return -EINVAL22;
3275 }
3276
3277 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id])amdgpu_device_rreg(adev, (0x1a16 + crtc_offsets[crtc_id]), 0) &
3278 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK0x1)
3279 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],amdgpu_device_wreg(adev, (0x1a16 + crtc_offsets[crtc_id]), (0x100
), 0)
3280 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK)amdgpu_device_wreg(adev, (0x1a16 + crtc_offsets[crtc_id]), (0x100
), 0);
3281
3282 /* IRQ could occur when in initial stage */
3283 if(amdgpu_crtc == NULL((void *)0))
3284 return 0;
3285
3286 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
3287 works = amdgpu_crtc->pflip_works;
3288 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3289 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
3290 "AMDGPU_FLIP_SUBMITTED(%d)\n",__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
3291 amdgpu_crtc->pflip_status,__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED)
3292 AMDGPU_FLIP_SUBMITTED)__drm_dbg(DRM_UT_DRIVER, "amdgpu_crtc->pflip_status = %d != "
"AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status,
AMDGPU_FLIP_SUBMITTED);
3293 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
3294 return 0;
3295 }
3296
3297 /* page flip completed. clean up */
3298 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3299 amdgpu_crtc->pflip_works = NULL((void *)0);
3300
3301 /* wakeup usersapce */
3302 if(works->event)
3303 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3304
3305 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
3306
3307 drm_crtc_vblank_put(&amdgpu_crtc->base);
3308 schedule_work(&works->unpin_work);
3309
3310 return 0;
3311}
3312
3313static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3314 int hpd)
3315{
3316 u32 tmp;
3317
3318 if (hpd >= adev->mode_info.num_hpd) {
3319 DRM_DEBUG("invalid hdp %d\n", hpd)__drm_dbg(DRM_UT_CORE, "invalid hdp %d\n", hpd);
3320 return;
3321 }
3322
3323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd])amdgpu_device_rreg(adev, (0x1899 + hpd_offsets[hpd]), 0);
3324 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0)));
3325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp)amdgpu_device_wreg(adev, (0x1899 + hpd_offsets[hpd]), (tmp), 0
);
3326}
3327
3328static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3329 int crtc)
3330{
3331 u32 tmp;
3332
3333 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3334 DRM_DEBUG("invalid crtc %d\n", crtc)__drm_dbg(DRM_UT_CORE, "invalid crtc %d\n", crtc);
3335 return;
3336 }
3337
3338 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1acb + crtc_offsets[crtc]), 0);
3339 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
3340 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp)amdgpu_device_wreg(adev, (0x1acb + crtc_offsets[crtc]), (tmp)
, 0);
3341}
3342
3343static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3344 int crtc)
3345{
3346 u32 tmp;
3347
3348 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3349 DRM_DEBUG("invalid crtc %d\n", crtc)__drm_dbg(DRM_UT_CORE, "invalid crtc %d\n", crtc);
3350 return;
3351 }
3352
3353 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc])amdgpu_device_rreg(adev, (0x1ac9 + crtc_offsets[crtc]), 0);
3354 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1)(((tmp) & ~0x10) | (0x10 & ((1) << 0x4)));
3355 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp)amdgpu_device_wreg(adev, (0x1ac9 + crtc_offsets[crtc]), (tmp)
, 0);
3356}
3357
3358static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361{
3362 unsigned crtc = entry->src_id - 1;
3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg)amdgpu_device_rreg(adev, (interrupt_status_offsets[crtc].reg)
, 0);
3364 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3365 crtc);
3366
3367 switch (entry->src_data[0]) {
3368 case 0: /* vblank */
3369 if (disp_int & interrupt_status_offsets[crtc].vblank)
3370 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3371 else
3372 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: IH event w/o asserted irq bit?\n"
);
3373
3374 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3375 drm_handle_vblank(adev_to_drm(adev), crtc);
3376 }
3377 DRM_DEBUG("IH: D%d vblank\n", crtc + 1)__drm_dbg(DRM_UT_CORE, "IH: D%d vblank\n", crtc + 1);
3378
3379 break;
3380 case 1: /* vline */
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3382 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3383 else
3384 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n")__drm_dbg(DRM_UT_CORE, "IH: IH event w/o asserted irq bit?\n"
);
3385
3386 DRM_DEBUG("IH: D%d vline\n", crtc + 1)__drm_dbg(DRM_UT_CORE, "IH: D%d vline\n", crtc + 1);
3387
3388 break;
3389 default:
3390 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0])__drm_dbg(DRM_UT_CORE, "Unhandled interrupt: %d %d\n", entry->
src_id, entry->src_data[0]);
3391 break;
3392 }
3393
3394 return 0;
3395}
3396
3397static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3398 struct amdgpu_irq_src *source,
3399 struct amdgpu_iv_entry *entry)
3400{
3401 uint32_t disp_int, mask;
3402 unsigned hpd;
3403
3404 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3405 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0])__drm_dbg(DRM_UT_CORE, "Unhandled interrupt: %d %d\n", entry->
src_id, entry->src_data[0]);
3406 return 0;
3407 }
3408
3409 hpd = entry->src_data[0];
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg)amdgpu_device_rreg(adev, (interrupt_status_offsets[hpd].reg),
0);
3411 mask = interrupt_status_offsets[hpd].hpd;
3412
3413 if (disp_int & mask) {
3414 dce_v11_0_hpd_int_ack(adev, hpd);
3415 schedule_work(&adev->hotplug_work);
3416 DRM_DEBUG("IH: HPD%d\n", hpd + 1)__drm_dbg(DRM_UT_CORE, "IH: HPD%d\n", hpd + 1);
3417 }
3418
3419 return 0;
3420}
3421
3422static int dce_v11_0_set_clockgating_state(void *handle,
3423 enum amd_clockgating_state state)
3424{
3425 return 0;
3426}
3427
3428static int dce_v11_0_set_powergating_state(void *handle,
3429 enum amd_powergating_state state)
3430{
3431 return 0;
3432}
3433
3434static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3435 .name = "dce_v11_0",
3436 .early_init = dce_v11_0_early_init,
3437 .late_init = NULL((void *)0),
3438 .sw_init = dce_v11_0_sw_init,
3439 .sw_fini = dce_v11_0_sw_fini,
3440 .hw_init = dce_v11_0_hw_init,
3441 .hw_fini = dce_v11_0_hw_fini,
3442 .suspend = dce_v11_0_suspend,
3443 .resume = dce_v11_0_resume,
3444 .is_idle = dce_v11_0_is_idle,
3445 .wait_for_idle = dce_v11_0_wait_for_idle,
3446 .soft_reset = dce_v11_0_soft_reset,
3447 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3448 .set_powergating_state = dce_v11_0_set_powergating_state,
3449};
3450
3451static void
3452dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3453 struct drm_display_mode *mode,
3454 struct drm_display_mode *adjusted_mode)
3455{
3456 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
3457
3458 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3459
3460 /* need to call this here rather than in prepare() since we need some crtc info */
3461 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3);
3462
3463 /* set scaler clears this on some chips */
3464 dce_v11_0_set_interleave(encoder->crtc, mode);
3465
3466 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3) {
3467 dce_v11_0_afmt_enable(encoder, true1);
3468 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3469 }
3470}
3471
3472static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3473{
3474 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
3476 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3477
3478 if ((amdgpu_encoder->active_device &
3479 (ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
<< 0x0000000B ) | (0x1L << 0x00000006 )) | ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) ||
3480 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3481 ENCODER_OBJECT_ID_NONE0x00)) {
3482 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3483 if (dig) {
3484 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3485 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT((0x1L << 0x00000003 ) | (0x1L << 0x00000007 ) | (
0x1L << 0x00000009 ) | (0x1L << 0x0000000A ) | (0x1L
<< 0x0000000B ) | (0x1L << 0x00000006 )))
3486 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3487 }
3488 }
3489
3490 amdgpu_atombios_scratch_regs_lock(adev, true1);
3491
3492 if (connector) {
3493 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector)({ const __typeof( ((struct amdgpu_connector *)0)->base ) *
__mptr = (connector); (struct amdgpu_connector *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_connector, base) );});
3494
3495 /* select the clock/data port if it uses a router */
3496 if (amdgpu_connector->router.cd_valid)
3497 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3498
3499 /* turn eDP panel on for mode set */
3500 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)
3501 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3502 ATOM_TRANSMITTER_ACTION_POWER_ON12);
3503 }
3504
3505 /* this is needed for the pll/ss setup to work correctly in some cases */
3506 amdgpu_atombios_encoder_set_crtc_source(encoder);
3507 /* set up the FMT blocks */
3508 dce_v11_0_program_fmt(encoder);
3509}
3510
3511static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3512{
3513 struct drm_device *dev = encoder->dev;
3514 struct amdgpu_device *adev = drm_to_adev(dev);
3515
3516 /* need to call this here as we need the crtc set up */
3517 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON0);
3518 amdgpu_atombios_scratch_regs_lock(adev, false0);
3519}
3520
3521static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3522{
3523 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
3524 struct amdgpu_encoder_atom_dig *dig;
3525
3526 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF3);
3527
3528 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3529 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI3)
3530 dce_v11_0_afmt_enable(encoder, false0);
3531 dig = amdgpu_encoder->enc_priv;
3532 dig->dig_encoder = -1;
3533 }
3534 amdgpu_encoder->active_device = 0;
3535}
3536
3537/* these are handled by the primary encoders */
3538static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3539{
3540
3541}
3542
3543static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3544{
3545
3546}
3547
3548static void
3549dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3550 struct drm_display_mode *mode,
3551 struct drm_display_mode *adjusted_mode)
3552{
3553
3554}
3555
3556static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3557{
3558
3559}
3560
3561static void
3562dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3563{
3564
3565}
3566
3567static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3568 .dpms = dce_v11_0_ext_dpms,
3569 .prepare = dce_v11_0_ext_prepare,
3570 .mode_set = dce_v11_0_ext_mode_set,
3571 .commit = dce_v11_0_ext_commit,
3572 .disable = dce_v11_0_ext_disable,
3573 /* no detect for TMDS/LVDS yet */
3574};
3575
3576static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3577 .dpms = amdgpu_atombios_encoder_dpms,
3578 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3579 .prepare = dce_v11_0_encoder_prepare,
3580 .mode_set = dce_v11_0_encoder_mode_set,
3581 .commit = dce_v11_0_encoder_commit,
3582 .disable = dce_v11_0_encoder_disable,
3583 .detect = amdgpu_atombios_encoder_dig_detect,
3584};
3585
3586static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3587 .dpms = amdgpu_atombios_encoder_dpms,
3588 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3589 .prepare = dce_v11_0_encoder_prepare,
3590 .mode_set = dce_v11_0_encoder_mode_set,
3591 .commit = dce_v11_0_encoder_commit,
3592 .detect = amdgpu_atombios_encoder_dac_detect,
3593};
3594
3595static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3596{
3597 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
3598 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
3599 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3600 kfree(amdgpu_encoder->enc_priv);
3601 drm_encoder_cleanup(encoder);
3602 kfree(amdgpu_encoder);
3603}
3604
3605static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3606 .destroy = dce_v11_0_encoder_destroy,
3607};
3608
3609static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3610 uint32_t encoder_enum,
3611 uint32_t supported_device,
3612 u16 caps)
3613{
3614 struct drm_device *dev = adev_to_drm(adev);
3615 struct drm_encoder *encoder;
3616 struct amdgpu_encoder *amdgpu_encoder;
3617
3618 /* see if we already added it */
3619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
head ) *__mptr = ((&dev->mode_config.encoder_list)->
next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );}); &encoder->head != (&
dev->mode_config.encoder_list); encoder = ({ const __typeof
( ((__typeof(*encoder) *)0)->head ) *__mptr = (encoder->
head.next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), head) );})) {
3620 amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
= (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
3621 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3622 amdgpu_encoder->devices |= supported_device;
3623 return;
3624 }
3625
3626 }
3627
3628 /* add a new one */
3629 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL(0x0001 | 0x0004));
3630 if (!amdgpu_encoder)
3631 return;
3632
3633 encoder = &amdgpu_encoder->base;
3634 switch (adev->mode_info.num_crtc) {
3635 case 1:
3636 encoder->possible_crtcs = 0x1;
3637 break;
3638 case 2:
3639 default:
3640 encoder->possible_crtcs = 0x3;
3641 break;
3642 case 3:
3643 encoder->possible_crtcs = 0x7;
3644 break;
3645 case 4:
3646 encoder->possible_crtcs = 0xf;
3647 break;
3648 case 5:
3649 encoder->possible_crtcs = 0x1f;
3650 break;
3651 case 6:
3652 encoder->possible_crtcs = 0x3f;
3653 break;
3654 }
3655
3656 amdgpu_encoder->enc_priv = NULL((void *)0);
3657
3658 amdgpu_encoder->encoder_enum = encoder_enum;
3659 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK0x00FF) >> OBJECT_ID_SHIFT0x00;
3660 amdgpu_encoder->devices = supported_device;
3661 amdgpu_encoder->rmx_type = RMX_OFF;
3662 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3663 amdgpu_encoder->is_ext_encoder = false0;
3664 amdgpu_encoder->caps = caps;
3665
3666 switch (amdgpu_encoder->encoder_id) {
3667 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC10x15:
3668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC20x16:
3669 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3670 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
3671 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3672 break;
3673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO10x14:
3674 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY0x1E:
3675 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY10x20:
3676 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY20x21:
3677 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY30x25:
3678 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 )))) {
3679 amdgpu_encoder->rmx_type = RMX_FULL;
3680 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3681 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
3682 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3683 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 )))) {
3684 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3685 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
3686 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3687 } else {
3688 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3689 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
3690 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3691 }
3692 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3693 break;
3694 case ENCODER_OBJECT_ID_SI170B0x08:
3695 case ENCODER_OBJECT_ID_CH73030x09:
3696 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA0x0C:
3697 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB0x0D:
3698 case ENCODER_OBJECT_ID_TITFP5130x0E:
3699 case ENCODER_OBJECT_ID_VT16230x10:
3700 case ENCODER_OBJECT_ID_HDMI_SI19300x11:
3701 case ENCODER_OBJECT_ID_TRAVIS0x23:
3702 case ENCODER_OBJECT_ID_NUTMEG0x22:
3703 /* these are handled by the primary encoders */
3704 amdgpu_encoder->is_ext_encoder = true1;
3705 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT((0x1L << 0x00000001 ) | (0x1L << 0x00000005 ))))
3706 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3707 DRM_MODE_ENCODER_LVDS3, NULL((void *)0));
3708 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT((0x1L << 0x00000000 ) | (0x1L << 0x00000004 ))))
3709 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3710 DRM_MODE_ENCODER_DAC1, NULL((void *)0));
3711 else
3712 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3713 DRM_MODE_ENCODER_TMDS2, NULL((void *)0));
3714 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3715 break;
3716 }
3717}
3718
3719static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3720 .bandwidth_update = &dce_v11_0_bandwidth_update,
3721 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3722 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3723 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3724 .hpd_sense = &dce_v11_0_hpd_sense,
3725 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3726 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3727 .page_flip = &dce_v11_0_page_flip,
3728 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3729 .add_encoder = &dce_v11_0_encoder_add,
3730 .add_connector = &amdgpu_connector_add,
3731};
3732
3733static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3734{
3735 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3736}
3737
3738static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3739 .set = dce_v11_0_set_crtc_irq_state,
3740 .process = dce_v11_0_crtc_irq,
3741};
3742
3743static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3744 .set = dce_v11_0_set_pageflip_irq_state,
3745 .process = dce_v11_0_pageflip_irq,
3746};
3747
3748static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3749 .set = dce_v11_0_set_hpd_irq_state,
3750 .process = dce_v11_0_hpd_irq,
3751};
3752
3753static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3754{
3755 if (adev->mode_info.num_crtc > 0)
3756 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3757 else
3758 adev->crtc_irq.num_types = 0;
3759 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3760
3761 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3762 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3763
3764 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3765 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3766}
3767
3768const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3769{
3770 .type = AMD_IP_BLOCK_TYPE_DCE,
3771 .major = 11,
3772 .minor = 0,
3773 .rev = 0,
3774 .funcs = &dce_v11_0_ip_funcs,
3775};
3776
3777const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3778{
3779 .type = AMD_IP_BLOCK_TYPE_DCE,
3780 .major = 11,
3781 .minor = 2,
3782 .rev = 0,
3783 .funcs = &dce_v11_0_ip_funcs,
3784};