Bug Summary

File:dev/pci/drm/radeon/rv515.c
Warning:line 1179, column 7
The left operand of '>>' is a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name rv515.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/radeon/rv515.c
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31
32#include <drm/drm_debugfs.h>
33#include <drm/drm_device.h>
34#include <drm/drm_file.h>
35
36#include "atom.h"
37#include "radeon.h"
38#include "radeon_asic.h"
39#include "rv515_reg_safe.h"
40#include "rv515d.h"
41
42/* This files gather functions specifics to: rv515 */
43static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
44static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
45static void rv515_gpu_init(struct radeon_device *rdev);
46int rv515_mc_wait_for_idle(struct radeon_device *rdev);
47
48static const u32 crtc_offsets[2] =
49{
50 0,
51 AVIVO_D2CRTC_H_TOTAL0x6800 - AVIVO_D1CRTC_H_TOTAL0x6000
52};
53
54void rv515_debugfs(struct radeon_device *rdev)
55{
56 if (r100_debugfs_rbbm_init(rdev)) {
57 DRM_ERROR("Failed to register debugfs file for RBBM !\n")__drm_err("Failed to register debugfs file for RBBM !\n");
58 }
59 if (rv515_debugfs_pipes_info_init(rdev)) {
60 DRM_ERROR("Failed to register debugfs file for pipes !\n")__drm_err("Failed to register debugfs file for pipes !\n");
61 }
62 if (rv515_debugfs_ga_info_init(rdev)) {
63 DRM_ERROR("Failed to register debugfs file for pipes !\n")__drm_err("Failed to register debugfs file for pipes !\n");
64 }
65}
66
67void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
68{
69 int r;
70
71 r = radeon_ring_lock(rdev, ring, 64);
72 if (r) {
73 return;
74 }
75 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0)(0x00000000 | ((((0x1724) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
76 radeon_ring_write(ring,
77 ISYNC_ANY2D_IDLE3D(1 << 0) |
78 ISYNC_ANY3D_IDLE2D(1 << 1) |
79 ISYNC_WAIT_IDLEGUI(1 << 4) |
80 ISYNC_CPSCRATCH_IDLEGUI(1 << 5));
81 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)(0x00000000 | ((((0x1720) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
82 radeon_ring_write(ring, WAIT_2D_IDLECLEAN(1 << 16) | WAIT_3D_IDLECLEAN(1 << 17));
83 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0)(0x00000000 | ((((0x170c) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
84 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG(1 << 31));
85 radeon_ring_write(ring, PACKET0(GB_SELECT, 0)(0x00000000 | ((((0x401C) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
86 radeon_ring_write(ring, 0);
87 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0)(0x00000000 | ((((0x4008) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
88 radeon_ring_write(ring, 0);
89 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0)(0x00000000 | ((((0x42c8) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
90 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
91 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0)(0x00000000 | ((((0x208C) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
92 radeon_ring_write(ring, 0);
93 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)(0x00000000 | ((((0x4E4C) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
94 radeon_ring_write(ring, RB3D_DC_FLUSH(2 << 0) | RB3D_DC_FREE(2 << 2));
95 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)(0x00000000 | ((((0x4F18) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
96 radeon_ring_write(ring, ZC_FLUSH(1 << 0) | ZC_FREE(1 << 1));
97 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0)(0x00000000 | ((((0x1720) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
98 radeon_ring_write(ring, WAIT_2D_IDLECLEAN(1 << 16) | WAIT_3D_IDLECLEAN(1 << 17));
99 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0)(0x00000000 | ((((0x4020) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
100 radeon_ring_write(ring, 0);
101 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)(0x00000000 | ((((0x4E4C) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
102 radeon_ring_write(ring, RB3D_DC_FLUSH(2 << 0) | RB3D_DC_FREE(2 << 2));
103 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0)(0x00000000 | ((((0x4F18) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
104 radeon_ring_write(ring, ZC_FLUSH(1 << 0) | ZC_FREE(1 << 1));
105 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0)(0x00000000 | ((((0x4010) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
106 radeon_ring_write(ring,
107 ((6 << MS_X0_SHIFT0) |
108 (6 << MS_Y0_SHIFT4) |
109 (6 << MS_X1_SHIFT8) |
110 (6 << MS_Y1_SHIFT12) |
111 (6 << MS_X2_SHIFT16) |
112 (6 << MS_Y2_SHIFT20) |
113 (6 << MSBD0_Y_SHIFT24) |
114 (6 << MSBD0_X_SHIFT28)));
115 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0)(0x00000000 | ((((0x4014) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
116 radeon_ring_write(ring,
117 ((6 << MS_X3_SHIFT0) |
118 (6 << MS_Y3_SHIFT4) |
119 (6 << MS_X4_SHIFT8) |
120 (6 << MS_Y4_SHIFT12) |
121 (6 << MS_X5_SHIFT16) |
122 (6 << MS_Y5_SHIFT20) |
123 (6 << MSBD1_SHIFT24)));
124 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0)(0x00000000 | ((((0x4274) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
125 radeon_ring_write(ring, GA_DEADLOCK_CNTL(1 << 0) | GA_FASTSYNC_CNTL(1 << 1));
126 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0)(0x00000000 | ((((0x4288) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
127 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE(2 << 4) | BACK_PTYPE_TRIANGE(2 << 7));
128 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0)(0x00000000 | ((((0x428C) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
129 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST(1 << 0) | COLOR_ROUND_NEAREST(1 << 2));
130 radeon_ring_write(ring, PACKET0(0x20C8, 0)(0x00000000 | ((((0x20C8) >> 2) << 0) & (0x1ffff
<< 0)) | ((((0)) << 16) & (0x3fff << 16
)))
);
131 radeon_ring_write(ring, 0);
132 radeon_ring_unlock_commit(rdev, ring, false0);
133}
134
135int rv515_mc_wait_for_idle(struct radeon_device *rdev)
136{
137 unsigned i;
138 uint32_t tmp;
139
140 for (i = 0; i < rdev->usec_timeout; i++) {
141 /* read MC_STATUS */
142 tmp = RREG32_MC(MC_STATUS)rdev->mc_rreg(rdev, (0x08));
143 if (tmp & MC_STATUS_IDLE(1 << 4)) {
144 return 0;
145 }
146 udelay(1);
147 }
148 return -1;
149}
150
151void rv515_vga_render_disable(struct radeon_device *rdev)
152{
153 WREG32(R_000300_VGA_RENDER_CONTROL,r100_mm_wreg(rdev, (0x000300), (r100_mm_rreg(rdev, (0x000300)
, 0) & 0xFFFCFFFF), 0)
154 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL)r100_mm_wreg(rdev, (0x000300), (r100_mm_rreg(rdev, (0x000300)
, 0) & 0xFFFCFFFF), 0)
;
155}
156
157static void rv515_gpu_init(struct radeon_device *rdev)
158{
159 unsigned pipe_select_current, gb_pipe_select, tmp;
160
161 if (r100_gui_wait_for_idle(rdev)) {
162 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"
)
;
163 }
164 rv515_vga_render_disable(rdev);
165 r420_pipes_init(rdev);
166 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT)r100_mm_rreg(rdev, (0x402c), 0);
167 tmp = RREG32(R300_DST_PIPE_CONFIG)r100_mm_rreg(rdev, (0x170c), 0);
168 pipe_select_current = (tmp >> 2) & 3;
169 tmp = (1 << pipe_select_current) |
170 (((gb_pipe_select >> 8) & 0xF) << 4);
171 WREG32_PLL(0x000D, tmp)rdev->pll_wreg(rdev, (0x000D), (tmp));
172 if (r100_gui_wait_for_idle(rdev)) {
173 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while resetting GPU. Bad things might happen.\n"
)
;
174 }
175 if (rv515_mc_wait_for_idle(rdev)) {
176 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n")printk("\0014" "Failed to wait MC idle while programming pipes. Bad things might happen.\n"
)
;
177 }
178}
179
180static void rv515_vram_get_type(struct radeon_device *rdev)
181{
182 uint32_t tmp;
183
184 rdev->mc.vram_width = 128;
185 rdev->mc.vram_is_ddr = true1;
186 tmp = RREG32_MC(RV515_MC_CNTL)rdev->mc_rreg(rdev, (0x5)) & MEM_NUM_CHANNELS_MASK0x00000003;
187 switch (tmp) {
188 case 0:
189 rdev->mc.vram_width = 64;
190 break;
191 case 1:
192 rdev->mc.vram_width = 128;
193 break;
194 default:
195 rdev->mc.vram_width = 128;
196 break;
197 }
198}
199
200static void rv515_mc_init(struct radeon_device *rdev)
201{
202
203 rv515_vram_get_type(rdev);
204 r100_vram_init_sizes(rdev);
205 radeon_vram_location(rdev, &rdev->mc, 0);
206 rdev->mc.gtt_base_align = 0;
207 if (!(rdev->flags & RADEON_IS_AGP))
208 radeon_gtt_location(rdev, &rdev->mc);
209 radeon_update_bandwidth_info(rdev);
210}
211
212uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
213{
214 unsigned long flags;
215 uint32_t r;
216
217 spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while
(0)
;
218 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff))r100_mm_wreg(rdev, (0x0070), (0x7f0000 | (reg & 0xffff)),
0)
;
219 r = RREG32(MC_IND_DATA)r100_mm_rreg(rdev, (0x0074), 0);
220 WREG32(MC_IND_INDEX, 0)r100_mm_wreg(rdev, (0x0070), (0), 0);
221 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while
(0)
;
222
223 return r;
224}
225
226void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
227{
228 unsigned long flags;
229
230 spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while
(0)
;
231 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff))r100_mm_wreg(rdev, (0x0070), (0xff0000 | ((reg) & 0xffff)
), 0)
;
232 WREG32(MC_IND_DATA, (v))r100_mm_wreg(rdev, (0x0074), ((v)), 0);
233 WREG32(MC_IND_INDEX, 0)r100_mm_wreg(rdev, (0x0070), (0), 0);
234 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while
(0)
;
235}
236
237#if defined(CONFIG_DEBUG_FS)
238static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
239{
240 struct drm_info_node *node = (struct drm_info_node *) m->private;
241 struct drm_device *dev = node->minor->dev;
242 struct radeon_device *rdev = dev->dev_private;
243 uint32_t tmp;
244
245 tmp = RREG32(GB_PIPE_SELECT)r100_mm_rreg(rdev, (0x402C), 0);
246 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
247 tmp = RREG32(SU_REG_DEST)r100_mm_rreg(rdev, (0x42C8), 0);
248 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
249 tmp = RREG32(GB_TILE_CONFIG)r100_mm_rreg(rdev, (0x4018), 0);
250 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
251 tmp = RREG32(DST_PIPE_CONFIG)r100_mm_rreg(rdev, (0x170C), 0);
252 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
253 return 0;
254}
255
256static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
257{
258 struct drm_info_node *node = (struct drm_info_node *) m->private;
259 struct drm_device *dev = node->minor->dev;
260 struct radeon_device *rdev = dev->dev_private;
261 uint32_t tmp;
262
263 tmp = RREG32(0x2140)r100_mm_rreg(rdev, (0x2140), 0);
264 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
265 radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0);
266 tmp = RREG32(0x425C)r100_mm_rreg(rdev, (0x425C), 0);
267 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
268 return 0;
269}
270
271static struct drm_info_list rv515_pipes_info_list[] = {
272 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL((void *)0)},
273};
274
275static struct drm_info_list rv515_ga_info_list[] = {
276 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL((void *)0)},
277};
278#endif
279
280static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
281{
282#if defined(CONFIG_DEBUG_FS)
283 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
284#else
285 return 0;
286#endif
287}
288
289static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
290{
291#if defined(CONFIG_DEBUG_FS)
292 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
293#else
294 return 0;
295#endif
296}
297
298void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
299{
300 u32 crtc_enabled, tmp, frame_count, blackout;
301 int i, j;
302
303 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL)r100_mm_rreg(rdev, (0x000300), 0);
304 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL)r100_mm_rreg(rdev, (0x000328), 0);
305
306 /* disable VGA render */
307 WREG32(R_000300_VGA_RENDER_CONTROL, 0)r100_mm_wreg(rdev, (0x000300), (0), 0);
308 /* blank the display controllers */
309 for (i = 0; i < rdev->num_crtc; i++) {
310 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i])r100_mm_rreg(rdev, (0x6080 + crtc_offsets[i]), 0) & AVIVO_CRTC_EN(1 << 0);
311 if (crtc_enabled) {
312 save->crtc_enabled[i] = true1;
313 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i])r100_mm_rreg(rdev, (0x6080 + crtc_offsets[i]), 0);
314 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE(1 << 24))) {
315 radeon_wait_for_vblank(rdev, i)(rdev)->asic->display.wait_for_vblank((rdev), (i));
316 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1)r100_mm_wreg(rdev, (0x60e8 + crtc_offsets[i]), (1), 0);
317 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE(1 << 24);
318 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x6080 + crtc_offsets[i]), (tmp), 0);
319 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0)r100_mm_wreg(rdev, (0x60e8 + crtc_offsets[i]), (0), 0);
320 }
321 /* wait for the next frame */
322 frame_count = radeon_get_vblank_counter(rdev, i)(rdev)->asic->display.get_vblank_counter((rdev), (i));
323 for (j = 0; j < rdev->usec_timeout; j++) {
324 if (radeon_get_vblank_counter(rdev, i)(rdev)->asic->display.get_vblank_counter((rdev), (i)) != frame_count)
325 break;
326 udelay(1);
327 }
328
329 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
330 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1)r100_mm_wreg(rdev, (0x60e8 + crtc_offsets[i]), (1), 0);
331 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i])r100_mm_rreg(rdev, (0x6080 + crtc_offsets[i]), 0);
332 tmp &= ~AVIVO_CRTC_EN(1 << 0);
333 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x6080 + crtc_offsets[i]), (tmp), 0);
334 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0)r100_mm_wreg(rdev, (0x60e8 + crtc_offsets[i]), (0), 0);
335 save->crtc_enabled[i] = false0;
336 /* ***** */
337 } else {
338 save->crtc_enabled[i] = false0;
339 }
340 }
341
342 radeon_mc_wait_for_idle(rdev)(rdev)->asic->mc_wait_for_idle((rdev));
343
344 if (rdev->family >= CHIP_R600) {
345 if (rdev->family >= CHIP_RV770)
346 blackout = RREG32(R700_MC_CITF_CNTL)r100_mm_rreg(rdev, (0x25c0), 0);
347 else
348 blackout = RREG32(R600_CITF_CNTL)r100_mm_rreg(rdev, (0x200c), 0);
349 if ((blackout & R600_BLACKOUT_MASK0x00000003) != R600_BLACKOUT_MASK0x00000003) {
350 /* Block CPU access */
351 WREG32(R600_BIF_FB_EN, 0)r100_mm_wreg(rdev, (0x5490), (0), 0);
352 /* blackout the MC */
353 blackout |= R600_BLACKOUT_MASK0x00000003;
354 if (rdev->family >= CHIP_RV770)
355 WREG32(R700_MC_CITF_CNTL, blackout)r100_mm_wreg(rdev, (0x25c0), (blackout), 0);
356 else
357 WREG32(R600_CITF_CNTL, blackout)r100_mm_wreg(rdev, (0x200c), (blackout), 0);
358 }
359 }
360 /* wait for the MC to settle */
361 udelay(100);
362
363 /* lock double buffered regs */
364 for (i = 0; i < rdev->num_crtc; i++) {
365 if (save->crtc_enabled[i]) {
366 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i])r100_mm_rreg(rdev, (0x6144 + crtc_offsets[i]), 0);
367 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK(1 << 16))) {
368 tmp |= AVIVO_D1GRPH_UPDATE_LOCK(1 << 16);
369 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x6144 + crtc_offsets[i]), (tmp), 0);
370 }
371 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i])r100_mm_rreg(rdev, (0x60e0 + crtc_offsets[i]), 0);
372 if (!(tmp & 1)) {
373 tmp |= 1;
374 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x60e0 + crtc_offsets[i]), (tmp), 0);
375 }
376 }
377 }
378}
379
380void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
381{
382 u32 tmp, frame_count;
383 int i, j;
384
385 /* update crtc base addresses */
386 for (i = 0; i < rdev->num_crtc; i++) {
387 if (rdev->family >= CHIP_RV770) {
388 if (i == 0) {
389 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,r100_mm_wreg(rdev, (0x6914), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
390 upper_32_bits(rdev->mc.vram_start))r100_mm_wreg(rdev, (0x6914), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
;
391 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,r100_mm_wreg(rdev, (0x691c), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
392 upper_32_bits(rdev->mc.vram_start))r100_mm_wreg(rdev, (0x691c), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
;
393 } else {
394 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,r100_mm_wreg(rdev, (0x6114), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
395 upper_32_bits(rdev->mc.vram_start))r100_mm_wreg(rdev, (0x6114), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
;
396 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,r100_mm_wreg(rdev, (0x611c), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
397 upper_32_bits(rdev->mc.vram_start))r100_mm_wreg(rdev, (0x611c), (((u32)(((rdev->mc.vram_start
) >> 16) >> 16))), 0)
;
398 }
399 }
400 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],r100_mm_wreg(rdev, (0x006110 + crtc_offsets[i]), ((u32)rdev->
mc.vram_start), 0)
401 (u32)rdev->mc.vram_start)r100_mm_wreg(rdev, (0x006110 + crtc_offsets[i]), ((u32)rdev->
mc.vram_start), 0)
;
402 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],r100_mm_wreg(rdev, (0x006118 + crtc_offsets[i]), ((u32)rdev->
mc.vram_start), 0)
403 (u32)rdev->mc.vram_start)r100_mm_wreg(rdev, (0x006118 + crtc_offsets[i]), ((u32)rdev->
mc.vram_start), 0)
;
404 }
405 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start)r100_mm_wreg(rdev, (0x000310), ((u32)rdev->mc.vram_start),
0)
;
406
407 /* unlock regs and wait for update */
408 for (i = 0; i < rdev->num_crtc; i++) {
409 if (save->crtc_enabled[i]) {
410 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i])r100_mm_rreg(rdev, (0x60e4 + crtc_offsets[i]), 0);
411 if ((tmp & 0x7) != 3) {
412 tmp &= ~0x7;
413 tmp |= 0x3;
414 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x60e4 + crtc_offsets[i]), (tmp), 0);
415 }
416 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i])r100_mm_rreg(rdev, (0x6144 + crtc_offsets[i]), 0);
417 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK(1 << 16)) {
418 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK(1 << 16);
419 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x6144 + crtc_offsets[i]), (tmp), 0);
420 }
421 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i])r100_mm_rreg(rdev, (0x60e0 + crtc_offsets[i]), 0);
422 if (tmp & 1) {
423 tmp &= ~1;
424 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x60e0 + crtc_offsets[i]), (tmp), 0);
425 }
426 for (j = 0; j < rdev->usec_timeout; j++) {
427 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i])r100_mm_rreg(rdev, (0x6144 + crtc_offsets[i]), 0);
428 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING(1 << 2)) == 0)
429 break;
430 udelay(1);
431 }
432 }
433 }
434
435 if (rdev->family >= CHIP_R600) {
436 /* unblackout the MC */
437 if (rdev->family >= CHIP_RV770)
438 tmp = RREG32(R700_MC_CITF_CNTL)r100_mm_rreg(rdev, (0x25c0), 0);
439 else
440 tmp = RREG32(R600_CITF_CNTL)r100_mm_rreg(rdev, (0x200c), 0);
441 tmp &= ~R600_BLACKOUT_MASK0x00000003;
442 if (rdev->family >= CHIP_RV770)
443 WREG32(R700_MC_CITF_CNTL, tmp)r100_mm_wreg(rdev, (0x25c0), (tmp), 0);
444 else
445 WREG32(R600_CITF_CNTL, tmp)r100_mm_wreg(rdev, (0x200c), (tmp), 0);
446 /* allow CPU access */
447 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN)r100_mm_wreg(rdev, (0x5490), ((1 << 0) | (1 << 1)
), 0)
;
448 }
449
450 for (i = 0; i < rdev->num_crtc; i++) {
451 if (save->crtc_enabled[i]) {
452 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i])r100_mm_rreg(rdev, (0x6080 + crtc_offsets[i]), 0);
453 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE(1 << 24);
454 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp)r100_mm_wreg(rdev, (0x6080 + crtc_offsets[i]), (tmp), 0);
455 /* wait for the next frame */
456 frame_count = radeon_get_vblank_counter(rdev, i)(rdev)->asic->display.get_vblank_counter((rdev), (i));
457 for (j = 0; j < rdev->usec_timeout; j++) {
458 if (radeon_get_vblank_counter(rdev, i)(rdev)->asic->display.get_vblank_counter((rdev), (i)) != frame_count)
459 break;
460 udelay(1);
461 }
462 }
463 }
464 /* Unlock vga access */
465 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control)r100_mm_wreg(rdev, (0x000328), (save->vga_hdp_control), 0);
466 mdelay(1);
467 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control)r100_mm_wreg(rdev, (0x000300), (save->vga_render_control),
0)
;
468}
469
470static void rv515_mc_program(struct radeon_device *rdev)
471{
472 struct rv515_mc_save save;
473
474 /* Stops all mc clients */
475 rv515_mc_stop(rdev, &save);
476
477 /* Wait for mc idle */
478 if (rv515_mc_wait_for_idle(rdev))
479 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n")printf("drm:pid%d:%s *WARNING* " "Wait MC idle timeout before updating MC.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
480 /* Write VRAM size in case we are limiting it */
481 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size)r100_mm_wreg(rdev, (0x0000F8), (rdev->mc.real_vram_size), 0
)
;
482 /* Program MC, should be a 32bits limited address space */
483 WREG32_MC(R_000001_MC_FB_LOCATION,rdev->mc_wreg(rdev, (0x000001), ((((rdev->mc.vram_start
>> 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end
>> 16) & 0xFFFF) << 16)))
484 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |rdev->mc_wreg(rdev, (0x000001), ((((rdev->mc.vram_start
>> 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end
>> 16) & 0xFFFF) << 16)))
485 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16))rdev->mc_wreg(rdev, (0x000001), ((((rdev->mc.vram_start
>> 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end
>> 16) & 0xFFFF) << 16)))
;
486 WREG32(R_000134_HDP_FB_LOCATION,r100_mm_wreg(rdev, (0x000134), ((((rdev->mc.vram_start >>
16) & 0xFFFF) << 0)), 0)
487 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16))r100_mm_wreg(rdev, (0x000134), ((((rdev->mc.vram_start >>
16) & 0xFFFF) << 0)), 0)
;
488 if (rdev->flags & RADEON_IS_AGP) {
489 WREG32_MC(R_000002_MC_AGP_LOCATION,rdev->mc_wreg(rdev, (0x000002), ((((rdev->mc.gtt_start >>
16) & 0xFFFF) << 0) | (((rdev->mc.gtt_end >>
16) & 0xFFFF) << 16)))
490 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |rdev->mc_wreg(rdev, (0x000002), ((((rdev->mc.gtt_start >>
16) & 0xFFFF) << 0) | (((rdev->mc.gtt_end >>
16) & 0xFFFF) << 16)))
491 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16))rdev->mc_wreg(rdev, (0x000002), ((((rdev->mc.gtt_start >>
16) & 0xFFFF) << 0) | (((rdev->mc.gtt_end >>
16) & 0xFFFF) << 16)))
;
492 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base))rdev->mc_wreg(rdev, (0x000003), (((u32)(rdev->mc.agp_base
))))
;
493 WREG32_MC(R_000004_MC_AGP_BASE_2,rdev->mc_wreg(rdev, (0x000004), ((((((u32)(((rdev->mc.agp_base
) >> 16) >> 16))) & 0xF) << 0)))
494 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)))rdev->mc_wreg(rdev, (0x000004), ((((((u32)(((rdev->mc.agp_base
) >> 16) >> 16))) & 0xF) << 0)))
;
495 } else {
496 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF)rdev->mc_wreg(rdev, (0x000002), (0xFFFFFFFF));
497 WREG32_MC(R_000003_MC_AGP_BASE, 0)rdev->mc_wreg(rdev, (0x000003), (0));
498 WREG32_MC(R_000004_MC_AGP_BASE_2, 0)rdev->mc_wreg(rdev, (0x000004), (0));
499 }
500
501 rv515_mc_resume(rdev, &save);
502}
503
504void rv515_clock_startup(struct radeon_device *rdev)
505{
506 if (radeon_dynclks != -1 && radeon_dynclks)
507 radeon_atom_set_clock_gating(rdev, 1);
508 /* We need to force on some of the block */
509 WREG32_PLL(R_00000F_CP_DYN_CNTL,rdev->pll_wreg(rdev, (0x00000F), (rdev->pll_rreg(rdev, (
0x00000F)) | (((1) & 0x1) << 0)))
510 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1))rdev->pll_wreg(rdev, (0x00000F), (rdev->pll_rreg(rdev, (
0x00000F)) | (((1) & 0x1) << 0)))
;
511 WREG32_PLL(R_000011_E2_DYN_CNTL,rdev->pll_wreg(rdev, (0x000011), (rdev->pll_rreg(rdev, (
0x000011)) | (((1) & 0x1) << 0)))
512 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1))rdev->pll_wreg(rdev, (0x000011), (rdev->pll_rreg(rdev, (
0x000011)) | (((1) & 0x1) << 0)))
;
513 WREG32_PLL(R_000013_IDCT_DYN_CNTL,rdev->pll_wreg(rdev, (0x000013), (rdev->pll_rreg(rdev, (
0x000013)) | (((1) & 0x1) << 0)))
514 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1))rdev->pll_wreg(rdev, (0x000013), (rdev->pll_rreg(rdev, (
0x000013)) | (((1) & 0x1) << 0)))
;
515}
516
517static int rv515_startup(struct radeon_device *rdev)
518{
519 int r;
520
521 rv515_mc_program(rdev);
522 /* Resume clock */
523 rv515_clock_startup(rdev);
524 /* Initialize GPU configuration (# pipes, ...) */
525 rv515_gpu_init(rdev);
526 /* Initialize GART (initialize after TTM so we can allocate
527 * memory through TTM but finalize after TTM) */
528 if (rdev->flags & RADEON_IS_PCIE) {
529 r = rv370_pcie_gart_enable(rdev);
530 if (r)
531 return r;
532 }
533
534 /* allocate wb buffer */
535 r = radeon_wb_init(rdev);
536 if (r)
537 return r;
538
539 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX0);
540 if (r) {
541 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r)
;
542 return r;
543 }
544
545 /* Enable IRQ */
546 if (!rdev->irq.installed) {
547 r = radeon_irq_kms_init(rdev);
548 if (r)
549 return r;
550 }
551
552 rs600_irq_set(rdev);
553 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x0130), 0);
554 /* 1M ring buffer */
555 r = r100_cp_init(rdev, 1024 * 1024);
556 if (r) {
557 dev_err(rdev->dev, "failed initializing CP (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r)
;
558 return r;
559 }
560
561 r = radeon_ib_pool_init(rdev);
562 if (r) {
563 dev_err(rdev->dev, "IB initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "IB initialization failed (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r)
;
564 return r;
565 }
566
567 return 0;
568}
569
570int rv515_resume(struct radeon_device *rdev)
571{
572 int r;
573
574 /* Make sur GART are not working */
575 if (rdev->flags & RADEON_IS_PCIE)
576 rv370_pcie_gart_disable(rdev);
577 /* Resume clock before doing reset */
578 rv515_clock_startup(rdev);
579 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
580 if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) {
581 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
582 RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
583 RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
;
584 }
585 /* post */
586 atom_asic_init(rdev->mode_info.atom_context);
587 /* Resume clock after posting */
588 rv515_clock_startup(rdev);
589 /* Initialize surface registers */
590 radeon_surface_init(rdev);
591
592 rdev->accel_working = true1;
593 r = rv515_startup(rdev);
594 if (r) {
595 rdev->accel_working = false0;
596 }
597 return r;
598}
599
600int rv515_suspend(struct radeon_device *rdev)
601{
602 radeon_pm_suspend(rdev);
603 r100_cp_disable(rdev);
604 radeon_wb_disable(rdev);
605 rs600_irq_disable(rdev);
606 if (rdev->flags & RADEON_IS_PCIE)
607 rv370_pcie_gart_disable(rdev);
608 return 0;
609}
610
611void rv515_set_safe_registers(struct radeon_device *rdev)
612{
613 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
614 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm)(sizeof((rv515_reg_safe_bm)) / sizeof((rv515_reg_safe_bm)[0])
)
;
615}
616
617void rv515_fini(struct radeon_device *rdev)
618{
619 radeon_pm_fini(rdev);
620 r100_cp_fini(rdev);
621 radeon_wb_fini(rdev);
622 radeon_ib_pool_fini(rdev);
623 radeon_gem_fini(rdev);
624 rv370_pcie_gart_fini(rdev);
625 radeon_agp_fini(rdev);
626 radeon_irq_kms_fini(rdev);
627 radeon_fence_driver_fini(rdev);
628 radeon_bo_fini(rdev);
629 radeon_atombios_fini(rdev);
630 kfree(rdev->bios);
631 rdev->bios = NULL((void *)0);
632}
633
634int rv515_init(struct radeon_device *rdev)
635{
636 int r;
637
638 /* Initialize scratch registers */
639 radeon_scratch_init(rdev);
640 /* Initialize surface registers */
641 radeon_surface_init(rdev);
642 /* TODO: disable VGA need to use VGA request */
643 /* restore some register to sane defaults */
644 r100_restore_sanity(rdev);
645 /* BIOS*/
646 if (!radeon_get_bios(rdev)) {
647 if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
648 return -EINVAL22;
649 }
650 if (rdev->is_atom_bios) {
651 r = radeon_atombios_init(rdev);
652 if (r)
653 return r;
654 } else {
655 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n")printf("drm:pid%d:%s *ERROR* " "Expecting atombios for RV515 GPU\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
656 return -EINVAL22;
657 }
658 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
659 if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) {
660 dev_warn(rdev->dev,printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
661 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
662 RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
663 RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
;
664 }
665 /* check if cards are posted or not */
666 if (radeon_boot_test_post_card(rdev) == false0)
667 return -EINVAL22;
668 /* Initialize clocks */
669 radeon_get_clock_info(rdev->ddev);
670 /* initialize AGP */
671 if (rdev->flags & RADEON_IS_AGP) {
672 r = radeon_agp_init(rdev);
673 if (r) {
674 radeon_agp_disable(rdev);
675 }
676 }
677 /* initialize memory controller */
678 rv515_mc_init(rdev);
679 rv515_debugfs(rdev);
680 /* Fence driver */
681 r = radeon_fence_driver_init(rdev);
682 if (r)
683 return r;
684 /* Memory manager */
685 r = radeon_bo_init(rdev);
686 if (r)
687 return r;
688 r = rv370_pcie_gart_init(rdev);
689 if (r)
690 return r;
691 rv515_set_safe_registers(rdev);
692
693 /* Initialize power management */
694 radeon_pm_init(rdev);
695
696 rdev->accel_working = true1;
697 r = rv515_startup(rdev);
698 if (r) {
699 /* Somethings want wront with the accel init stop accel */
700 dev_err(rdev->dev, "Disabling GPU acceleration\n")printf("drm:pid%d:%s *ERROR* " "Disabling GPU acceleration\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
701 r100_cp_fini(rdev);
702 radeon_wb_fini(rdev);
703 radeon_ib_pool_fini(rdev);
704 radeon_irq_kms_fini(rdev);
705 rv370_pcie_gart_fini(rdev);
706 radeon_agp_fini(rdev);
707 rdev->accel_working = false0;
708 }
709 return 0;
710}
711
712void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
713{
714 int index_reg = 0x6578 + crtc->crtc_offset;
715 int data_reg = 0x657c + crtc->crtc_offset;
716
717 WREG32(0x659C + crtc->crtc_offset, 0x0)r100_mm_wreg(rdev, (0x659C + crtc->crtc_offset), (0x0), 0);
718 WREG32(0x6594 + crtc->crtc_offset, 0x705)r100_mm_wreg(rdev, (0x6594 + crtc->crtc_offset), (0x705), 0
)
;
719 WREG32(0x65A4 + crtc->crtc_offset, 0x10001)r100_mm_wreg(rdev, (0x65A4 + crtc->crtc_offset), (0x10001)
, 0)
;
720 WREG32(0x65D8 + crtc->crtc_offset, 0x0)r100_mm_wreg(rdev, (0x65D8 + crtc->crtc_offset), (0x0), 0);
721 WREG32(0x65B0 + crtc->crtc_offset, 0x0)r100_mm_wreg(rdev, (0x65B0 + crtc->crtc_offset), (0x0), 0);
722 WREG32(0x65C0 + crtc->crtc_offset, 0x0)r100_mm_wreg(rdev, (0x65C0 + crtc->crtc_offset), (0x0), 0);
723 WREG32(0x65D4 + crtc->crtc_offset, 0x0)r100_mm_wreg(rdev, (0x65D4 + crtc->crtc_offset), (0x0), 0);
724 WREG32(index_reg, 0x0)r100_mm_wreg(rdev, (index_reg), (0x0), 0);
725 WREG32(data_reg, 0x841880A8)r100_mm_wreg(rdev, (data_reg), (0x841880A8), 0);
726 WREG32(index_reg, 0x1)r100_mm_wreg(rdev, (index_reg), (0x1), 0);
727 WREG32(data_reg, 0x84208680)r100_mm_wreg(rdev, (data_reg), (0x84208680), 0);
728 WREG32(index_reg, 0x2)r100_mm_wreg(rdev, (index_reg), (0x2), 0);
729 WREG32(data_reg, 0xBFF880B0)r100_mm_wreg(rdev, (data_reg), (0xBFF880B0), 0);
730 WREG32(index_reg, 0x100)r100_mm_wreg(rdev, (index_reg), (0x100), 0);
731 WREG32(data_reg, 0x83D88088)r100_mm_wreg(rdev, (data_reg), (0x83D88088), 0);
732 WREG32(index_reg, 0x101)r100_mm_wreg(rdev, (index_reg), (0x101), 0);
733 WREG32(data_reg, 0x84608680)r100_mm_wreg(rdev, (data_reg), (0x84608680), 0);
734 WREG32(index_reg, 0x102)r100_mm_wreg(rdev, (index_reg), (0x102), 0);
735 WREG32(data_reg, 0xBFF080D0)r100_mm_wreg(rdev, (data_reg), (0xBFF080D0), 0);
736 WREG32(index_reg, 0x200)r100_mm_wreg(rdev, (index_reg), (0x200), 0);
737 WREG32(data_reg, 0x83988068)r100_mm_wreg(rdev, (data_reg), (0x83988068), 0);
738 WREG32(index_reg, 0x201)r100_mm_wreg(rdev, (index_reg), (0x201), 0);
739 WREG32(data_reg, 0x84A08680)r100_mm_wreg(rdev, (data_reg), (0x84A08680), 0);
740 WREG32(index_reg, 0x202)r100_mm_wreg(rdev, (index_reg), (0x202), 0);
741 WREG32(data_reg, 0xBFF080F8)r100_mm_wreg(rdev, (data_reg), (0xBFF080F8), 0);
742 WREG32(index_reg, 0x300)r100_mm_wreg(rdev, (index_reg), (0x300), 0);
743 WREG32(data_reg, 0x83588058)r100_mm_wreg(rdev, (data_reg), (0x83588058), 0);
744 WREG32(index_reg, 0x301)r100_mm_wreg(rdev, (index_reg), (0x301), 0);
745 WREG32(data_reg, 0x84E08660)r100_mm_wreg(rdev, (data_reg), (0x84E08660), 0);
746 WREG32(index_reg, 0x302)r100_mm_wreg(rdev, (index_reg), (0x302), 0);
747 WREG32(data_reg, 0xBFF88120)r100_mm_wreg(rdev, (data_reg), (0xBFF88120), 0);
748 WREG32(index_reg, 0x400)r100_mm_wreg(rdev, (index_reg), (0x400), 0);
749 WREG32(data_reg, 0x83188040)r100_mm_wreg(rdev, (data_reg), (0x83188040), 0);
750 WREG32(index_reg, 0x401)r100_mm_wreg(rdev, (index_reg), (0x401), 0);
751 WREG32(data_reg, 0x85008660)r100_mm_wreg(rdev, (data_reg), (0x85008660), 0);
752 WREG32(index_reg, 0x402)r100_mm_wreg(rdev, (index_reg), (0x402), 0);
753 WREG32(data_reg, 0xBFF88150)r100_mm_wreg(rdev, (data_reg), (0xBFF88150), 0);
754 WREG32(index_reg, 0x500)r100_mm_wreg(rdev, (index_reg), (0x500), 0);
755 WREG32(data_reg, 0x82D88030)r100_mm_wreg(rdev, (data_reg), (0x82D88030), 0);
756 WREG32(index_reg, 0x501)r100_mm_wreg(rdev, (index_reg), (0x501), 0);
757 WREG32(data_reg, 0x85408640)r100_mm_wreg(rdev, (data_reg), (0x85408640), 0);
758 WREG32(index_reg, 0x502)r100_mm_wreg(rdev, (index_reg), (0x502), 0);
759 WREG32(data_reg, 0xBFF88180)r100_mm_wreg(rdev, (data_reg), (0xBFF88180), 0);
760 WREG32(index_reg, 0x600)r100_mm_wreg(rdev, (index_reg), (0x600), 0);
761 WREG32(data_reg, 0x82A08018)r100_mm_wreg(rdev, (data_reg), (0x82A08018), 0);
762 WREG32(index_reg, 0x601)r100_mm_wreg(rdev, (index_reg), (0x601), 0);
763 WREG32(data_reg, 0x85808620)r100_mm_wreg(rdev, (data_reg), (0x85808620), 0);
764 WREG32(index_reg, 0x602)r100_mm_wreg(rdev, (index_reg), (0x602), 0);
765 WREG32(data_reg, 0xBFF081B8)r100_mm_wreg(rdev, (data_reg), (0xBFF081B8), 0);
766 WREG32(index_reg, 0x700)r100_mm_wreg(rdev, (index_reg), (0x700), 0);
767 WREG32(data_reg, 0x82608010)r100_mm_wreg(rdev, (data_reg), (0x82608010), 0);
768 WREG32(index_reg, 0x701)r100_mm_wreg(rdev, (index_reg), (0x701), 0);
769 WREG32(data_reg, 0x85A08600)r100_mm_wreg(rdev, (data_reg), (0x85A08600), 0);
770 WREG32(index_reg, 0x702)r100_mm_wreg(rdev, (index_reg), (0x702), 0);
771 WREG32(data_reg, 0x800081F0)r100_mm_wreg(rdev, (data_reg), (0x800081F0), 0);
772 WREG32(index_reg, 0x800)r100_mm_wreg(rdev, (index_reg), (0x800), 0);
773 WREG32(data_reg, 0x8228BFF8)r100_mm_wreg(rdev, (data_reg), (0x8228BFF8), 0);
774 WREG32(index_reg, 0x801)r100_mm_wreg(rdev, (index_reg), (0x801), 0);
775 WREG32(data_reg, 0x85E085E0)r100_mm_wreg(rdev, (data_reg), (0x85E085E0), 0);
776 WREG32(index_reg, 0x802)r100_mm_wreg(rdev, (index_reg), (0x802), 0);
777 WREG32(data_reg, 0xBFF88228)r100_mm_wreg(rdev, (data_reg), (0xBFF88228), 0);
778 WREG32(index_reg, 0x10000)r100_mm_wreg(rdev, (index_reg), (0x10000), 0);
779 WREG32(data_reg, 0x82A8BF00)r100_mm_wreg(rdev, (data_reg), (0x82A8BF00), 0);
780 WREG32(index_reg, 0x10001)r100_mm_wreg(rdev, (index_reg), (0x10001), 0);
781 WREG32(data_reg, 0x82A08CC0)r100_mm_wreg(rdev, (data_reg), (0x82A08CC0), 0);
782 WREG32(index_reg, 0x10002)r100_mm_wreg(rdev, (index_reg), (0x10002), 0);
783 WREG32(data_reg, 0x8008BEF8)r100_mm_wreg(rdev, (data_reg), (0x8008BEF8), 0);
784 WREG32(index_reg, 0x10100)r100_mm_wreg(rdev, (index_reg), (0x10100), 0);
785 WREG32(data_reg, 0x81F0BF28)r100_mm_wreg(rdev, (data_reg), (0x81F0BF28), 0);
786 WREG32(index_reg, 0x10101)r100_mm_wreg(rdev, (index_reg), (0x10101), 0);
787 WREG32(data_reg, 0x83608CA0)r100_mm_wreg(rdev, (data_reg), (0x83608CA0), 0);
788 WREG32(index_reg, 0x10102)r100_mm_wreg(rdev, (index_reg), (0x10102), 0);
789 WREG32(data_reg, 0x8018BED0)r100_mm_wreg(rdev, (data_reg), (0x8018BED0), 0);
790 WREG32(index_reg, 0x10200)r100_mm_wreg(rdev, (index_reg), (0x10200), 0);
791 WREG32(data_reg, 0x8148BF38)r100_mm_wreg(rdev, (data_reg), (0x8148BF38), 0);
792 WREG32(index_reg, 0x10201)r100_mm_wreg(rdev, (index_reg), (0x10201), 0);
793 WREG32(data_reg, 0x84408C80)r100_mm_wreg(rdev, (data_reg), (0x84408C80), 0);
794 WREG32(index_reg, 0x10202)r100_mm_wreg(rdev, (index_reg), (0x10202), 0);
795 WREG32(data_reg, 0x8008BEB8)r100_mm_wreg(rdev, (data_reg), (0x8008BEB8), 0);
796 WREG32(index_reg, 0x10300)r100_mm_wreg(rdev, (index_reg), (0x10300), 0);
797 WREG32(data_reg, 0x80B0BF78)r100_mm_wreg(rdev, (data_reg), (0x80B0BF78), 0);
798 WREG32(index_reg, 0x10301)r100_mm_wreg(rdev, (index_reg), (0x10301), 0);
799 WREG32(data_reg, 0x85008C20)r100_mm_wreg(rdev, (data_reg), (0x85008C20), 0);
800 WREG32(index_reg, 0x10302)r100_mm_wreg(rdev, (index_reg), (0x10302), 0);
801 WREG32(data_reg, 0x8020BEA0)r100_mm_wreg(rdev, (data_reg), (0x8020BEA0), 0);
802 WREG32(index_reg, 0x10400)r100_mm_wreg(rdev, (index_reg), (0x10400), 0);
803 WREG32(data_reg, 0x8028BF90)r100_mm_wreg(rdev, (data_reg), (0x8028BF90), 0);
804 WREG32(index_reg, 0x10401)r100_mm_wreg(rdev, (index_reg), (0x10401), 0);
805 WREG32(data_reg, 0x85E08BC0)r100_mm_wreg(rdev, (data_reg), (0x85E08BC0), 0);
806 WREG32(index_reg, 0x10402)r100_mm_wreg(rdev, (index_reg), (0x10402), 0);
807 WREG32(data_reg, 0x8018BE90)r100_mm_wreg(rdev, (data_reg), (0x8018BE90), 0);
808 WREG32(index_reg, 0x10500)r100_mm_wreg(rdev, (index_reg), (0x10500), 0);
809 WREG32(data_reg, 0xBFB8BFB0)r100_mm_wreg(rdev, (data_reg), (0xBFB8BFB0), 0);
810 WREG32(index_reg, 0x10501)r100_mm_wreg(rdev, (index_reg), (0x10501), 0);
811 WREG32(data_reg, 0x86C08B40)r100_mm_wreg(rdev, (data_reg), (0x86C08B40), 0);
812 WREG32(index_reg, 0x10502)r100_mm_wreg(rdev, (index_reg), (0x10502), 0);
813 WREG32(data_reg, 0x8010BE90)r100_mm_wreg(rdev, (data_reg), (0x8010BE90), 0);
814 WREG32(index_reg, 0x10600)r100_mm_wreg(rdev, (index_reg), (0x10600), 0);
815 WREG32(data_reg, 0xBF58BFC8)r100_mm_wreg(rdev, (data_reg), (0xBF58BFC8), 0);
816 WREG32(index_reg, 0x10601)r100_mm_wreg(rdev, (index_reg), (0x10601), 0);
817 WREG32(data_reg, 0x87A08AA0)r100_mm_wreg(rdev, (data_reg), (0x87A08AA0), 0);
818 WREG32(index_reg, 0x10602)r100_mm_wreg(rdev, (index_reg), (0x10602), 0);
819 WREG32(data_reg, 0x8010BE98)r100_mm_wreg(rdev, (data_reg), (0x8010BE98), 0);
820 WREG32(index_reg, 0x10700)r100_mm_wreg(rdev, (index_reg), (0x10700), 0);
821 WREG32(data_reg, 0xBF10BFF0)r100_mm_wreg(rdev, (data_reg), (0xBF10BFF0), 0);
822 WREG32(index_reg, 0x10701)r100_mm_wreg(rdev, (index_reg), (0x10701), 0);
823 WREG32(data_reg, 0x886089E0)r100_mm_wreg(rdev, (data_reg), (0x886089E0), 0);
824 WREG32(index_reg, 0x10702)r100_mm_wreg(rdev, (index_reg), (0x10702), 0);
825 WREG32(data_reg, 0x8018BEB0)r100_mm_wreg(rdev, (data_reg), (0x8018BEB0), 0);
826 WREG32(index_reg, 0x10800)r100_mm_wreg(rdev, (index_reg), (0x10800), 0);
827 WREG32(data_reg, 0xBED8BFE8)r100_mm_wreg(rdev, (data_reg), (0xBED8BFE8), 0);
828 WREG32(index_reg, 0x10801)r100_mm_wreg(rdev, (index_reg), (0x10801), 0);
829 WREG32(data_reg, 0x89408940)r100_mm_wreg(rdev, (data_reg), (0x89408940), 0);
830 WREG32(index_reg, 0x10802)r100_mm_wreg(rdev, (index_reg), (0x10802), 0);
831 WREG32(data_reg, 0xBFE8BED8)r100_mm_wreg(rdev, (data_reg), (0xBFE8BED8), 0);
832 WREG32(index_reg, 0x20000)r100_mm_wreg(rdev, (index_reg), (0x20000), 0);
833 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
834 WREG32(index_reg, 0x20001)r100_mm_wreg(rdev, (index_reg), (0x20001), 0);
835 WREG32(data_reg, 0x90008000)r100_mm_wreg(rdev, (data_reg), (0x90008000), 0);
836 WREG32(index_reg, 0x20002)r100_mm_wreg(rdev, (index_reg), (0x20002), 0);
837 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
838 WREG32(index_reg, 0x20003)r100_mm_wreg(rdev, (index_reg), (0x20003), 0);
839 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
840 WREG32(index_reg, 0x20100)r100_mm_wreg(rdev, (index_reg), (0x20100), 0);
841 WREG32(data_reg, 0x80108000)r100_mm_wreg(rdev, (data_reg), (0x80108000), 0);
842 WREG32(index_reg, 0x20101)r100_mm_wreg(rdev, (index_reg), (0x20101), 0);
843 WREG32(data_reg, 0x8FE0BF70)r100_mm_wreg(rdev, (data_reg), (0x8FE0BF70), 0);
844 WREG32(index_reg, 0x20102)r100_mm_wreg(rdev, (index_reg), (0x20102), 0);
845 WREG32(data_reg, 0xBFE880C0)r100_mm_wreg(rdev, (data_reg), (0xBFE880C0), 0);
846 WREG32(index_reg, 0x20103)r100_mm_wreg(rdev, (index_reg), (0x20103), 0);
847 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
848 WREG32(index_reg, 0x20200)r100_mm_wreg(rdev, (index_reg), (0x20200), 0);
849 WREG32(data_reg, 0x8018BFF8)r100_mm_wreg(rdev, (data_reg), (0x8018BFF8), 0);
850 WREG32(index_reg, 0x20201)r100_mm_wreg(rdev, (index_reg), (0x20201), 0);
851 WREG32(data_reg, 0x8F80BF08)r100_mm_wreg(rdev, (data_reg), (0x8F80BF08), 0);
852 WREG32(index_reg, 0x20202)r100_mm_wreg(rdev, (index_reg), (0x20202), 0);
853 WREG32(data_reg, 0xBFD081A0)r100_mm_wreg(rdev, (data_reg), (0xBFD081A0), 0);
854 WREG32(index_reg, 0x20203)r100_mm_wreg(rdev, (index_reg), (0x20203), 0);
855 WREG32(data_reg, 0xBFF88000)r100_mm_wreg(rdev, (data_reg), (0xBFF88000), 0);
856 WREG32(index_reg, 0x20300)r100_mm_wreg(rdev, (index_reg), (0x20300), 0);
857 WREG32(data_reg, 0x80188000)r100_mm_wreg(rdev, (data_reg), (0x80188000), 0);
858 WREG32(index_reg, 0x20301)r100_mm_wreg(rdev, (index_reg), (0x20301), 0);
859 WREG32(data_reg, 0x8EE0BEC0)r100_mm_wreg(rdev, (data_reg), (0x8EE0BEC0), 0);
860 WREG32(index_reg, 0x20302)r100_mm_wreg(rdev, (index_reg), (0x20302), 0);
861 WREG32(data_reg, 0xBFB082A0)r100_mm_wreg(rdev, (data_reg), (0xBFB082A0), 0);
862 WREG32(index_reg, 0x20303)r100_mm_wreg(rdev, (index_reg), (0x20303), 0);
863 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
864 WREG32(index_reg, 0x20400)r100_mm_wreg(rdev, (index_reg), (0x20400), 0);
865 WREG32(data_reg, 0x80188000)r100_mm_wreg(rdev, (data_reg), (0x80188000), 0);
866 WREG32(index_reg, 0x20401)r100_mm_wreg(rdev, (index_reg), (0x20401), 0);
867 WREG32(data_reg, 0x8E00BEA0)r100_mm_wreg(rdev, (data_reg), (0x8E00BEA0), 0);
868 WREG32(index_reg, 0x20402)r100_mm_wreg(rdev, (index_reg), (0x20402), 0);
869 WREG32(data_reg, 0xBF8883C0)r100_mm_wreg(rdev, (data_reg), (0xBF8883C0), 0);
870 WREG32(index_reg, 0x20403)r100_mm_wreg(rdev, (index_reg), (0x20403), 0);
871 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
872 WREG32(index_reg, 0x20500)r100_mm_wreg(rdev, (index_reg), (0x20500), 0);
873 WREG32(data_reg, 0x80188000)r100_mm_wreg(rdev, (data_reg), (0x80188000), 0);
874 WREG32(index_reg, 0x20501)r100_mm_wreg(rdev, (index_reg), (0x20501), 0);
875 WREG32(data_reg, 0x8D00BE90)r100_mm_wreg(rdev, (data_reg), (0x8D00BE90), 0);
876 WREG32(index_reg, 0x20502)r100_mm_wreg(rdev, (index_reg), (0x20502), 0);
877 WREG32(data_reg, 0xBF588500)r100_mm_wreg(rdev, (data_reg), (0xBF588500), 0);
878 WREG32(index_reg, 0x20503)r100_mm_wreg(rdev, (index_reg), (0x20503), 0);
879 WREG32(data_reg, 0x80008008)r100_mm_wreg(rdev, (data_reg), (0x80008008), 0);
880 WREG32(index_reg, 0x20600)r100_mm_wreg(rdev, (index_reg), (0x20600), 0);
881 WREG32(data_reg, 0x80188000)r100_mm_wreg(rdev, (data_reg), (0x80188000), 0);
882 WREG32(index_reg, 0x20601)r100_mm_wreg(rdev, (index_reg), (0x20601), 0);
883 WREG32(data_reg, 0x8BC0BE98)r100_mm_wreg(rdev, (data_reg), (0x8BC0BE98), 0);
884 WREG32(index_reg, 0x20602)r100_mm_wreg(rdev, (index_reg), (0x20602), 0);
885 WREG32(data_reg, 0xBF308660)r100_mm_wreg(rdev, (data_reg), (0xBF308660), 0);
886 WREG32(index_reg, 0x20603)r100_mm_wreg(rdev, (index_reg), (0x20603), 0);
887 WREG32(data_reg, 0x80008008)r100_mm_wreg(rdev, (data_reg), (0x80008008), 0);
888 WREG32(index_reg, 0x20700)r100_mm_wreg(rdev, (index_reg), (0x20700), 0);
889 WREG32(data_reg, 0x80108000)r100_mm_wreg(rdev, (data_reg), (0x80108000), 0);
890 WREG32(index_reg, 0x20701)r100_mm_wreg(rdev, (index_reg), (0x20701), 0);
891 WREG32(data_reg, 0x8A80BEB0)r100_mm_wreg(rdev, (data_reg), (0x8A80BEB0), 0);
892 WREG32(index_reg, 0x20702)r100_mm_wreg(rdev, (index_reg), (0x20702), 0);
893 WREG32(data_reg, 0xBF0087C0)r100_mm_wreg(rdev, (data_reg), (0xBF0087C0), 0);
894 WREG32(index_reg, 0x20703)r100_mm_wreg(rdev, (index_reg), (0x20703), 0);
895 WREG32(data_reg, 0x80008008)r100_mm_wreg(rdev, (data_reg), (0x80008008), 0);
896 WREG32(index_reg, 0x20800)r100_mm_wreg(rdev, (index_reg), (0x20800), 0);
897 WREG32(data_reg, 0x80108000)r100_mm_wreg(rdev, (data_reg), (0x80108000), 0);
898 WREG32(index_reg, 0x20801)r100_mm_wreg(rdev, (index_reg), (0x20801), 0);
899 WREG32(data_reg, 0x8920BED0)r100_mm_wreg(rdev, (data_reg), (0x8920BED0), 0);
900 WREG32(index_reg, 0x20802)r100_mm_wreg(rdev, (index_reg), (0x20802), 0);
901 WREG32(data_reg, 0xBED08920)r100_mm_wreg(rdev, (data_reg), (0xBED08920), 0);
902 WREG32(index_reg, 0x20803)r100_mm_wreg(rdev, (index_reg), (0x20803), 0);
903 WREG32(data_reg, 0x80008010)r100_mm_wreg(rdev, (data_reg), (0x80008010), 0);
904 WREG32(index_reg, 0x30000)r100_mm_wreg(rdev, (index_reg), (0x30000), 0);
905 WREG32(data_reg, 0x90008000)r100_mm_wreg(rdev, (data_reg), (0x90008000), 0);
906 WREG32(index_reg, 0x30001)r100_mm_wreg(rdev, (index_reg), (0x30001), 0);
907 WREG32(data_reg, 0x80008000)r100_mm_wreg(rdev, (data_reg), (0x80008000), 0);
908 WREG32(index_reg, 0x30100)r100_mm_wreg(rdev, (index_reg), (0x30100), 0);
909 WREG32(data_reg, 0x8FE0BF90)r100_mm_wreg(rdev, (data_reg), (0x8FE0BF90), 0);
910 WREG32(index_reg, 0x30101)r100_mm_wreg(rdev, (index_reg), (0x30101), 0);
911 WREG32(data_reg, 0xBFF880A0)r100_mm_wreg(rdev, (data_reg), (0xBFF880A0), 0);
912 WREG32(index_reg, 0x30200)r100_mm_wreg(rdev, (index_reg), (0x30200), 0);
913 WREG32(data_reg, 0x8F60BF40)r100_mm_wreg(rdev, (data_reg), (0x8F60BF40), 0);
914 WREG32(index_reg, 0x30201)r100_mm_wreg(rdev, (index_reg), (0x30201), 0);
915 WREG32(data_reg, 0xBFE88180)r100_mm_wreg(rdev, (data_reg), (0xBFE88180), 0);
916 WREG32(index_reg, 0x30300)r100_mm_wreg(rdev, (index_reg), (0x30300), 0);
917 WREG32(data_reg, 0x8EC0BF00)r100_mm_wreg(rdev, (data_reg), (0x8EC0BF00), 0);
918 WREG32(index_reg, 0x30301)r100_mm_wreg(rdev, (index_reg), (0x30301), 0);
919 WREG32(data_reg, 0xBFC88280)r100_mm_wreg(rdev, (data_reg), (0xBFC88280), 0);
920 WREG32(index_reg, 0x30400)r100_mm_wreg(rdev, (index_reg), (0x30400), 0);
921 WREG32(data_reg, 0x8DE0BEE0)r100_mm_wreg(rdev, (data_reg), (0x8DE0BEE0), 0);
922 WREG32(index_reg, 0x30401)r100_mm_wreg(rdev, (index_reg), (0x30401), 0);
923 WREG32(data_reg, 0xBFA083A0)r100_mm_wreg(rdev, (data_reg), (0xBFA083A0), 0);
924 WREG32(index_reg, 0x30500)r100_mm_wreg(rdev, (index_reg), (0x30500), 0);
925 WREG32(data_reg, 0x8CE0BED0)r100_mm_wreg(rdev, (data_reg), (0x8CE0BED0), 0);
926 WREG32(index_reg, 0x30501)r100_mm_wreg(rdev, (index_reg), (0x30501), 0);
927 WREG32(data_reg, 0xBF7884E0)r100_mm_wreg(rdev, (data_reg), (0xBF7884E0), 0);
928 WREG32(index_reg, 0x30600)r100_mm_wreg(rdev, (index_reg), (0x30600), 0);
929 WREG32(data_reg, 0x8BA0BED8)r100_mm_wreg(rdev, (data_reg), (0x8BA0BED8), 0);
930 WREG32(index_reg, 0x30601)r100_mm_wreg(rdev, (index_reg), (0x30601), 0);
931 WREG32(data_reg, 0xBF508640)r100_mm_wreg(rdev, (data_reg), (0xBF508640), 0);
932 WREG32(index_reg, 0x30700)r100_mm_wreg(rdev, (index_reg), (0x30700), 0);
933 WREG32(data_reg, 0x8A60BEE8)r100_mm_wreg(rdev, (data_reg), (0x8A60BEE8), 0);
934 WREG32(index_reg, 0x30701)r100_mm_wreg(rdev, (index_reg), (0x30701), 0);
935 WREG32(data_reg, 0xBF2087A0)r100_mm_wreg(rdev, (data_reg), (0xBF2087A0), 0);
936 WREG32(index_reg, 0x30800)r100_mm_wreg(rdev, (index_reg), (0x30800), 0);
937 WREG32(data_reg, 0x8900BF00)r100_mm_wreg(rdev, (data_reg), (0x8900BF00), 0);
938 WREG32(index_reg, 0x30801)r100_mm_wreg(rdev, (index_reg), (0x30801), 0);
939 WREG32(data_reg, 0xBF008900)r100_mm_wreg(rdev, (data_reg), (0xBF008900), 0);
940}
941
942struct rv515_watermark {
943 u32 lb_request_fifo_depth;
944 fixed20_12 num_line_pair;
945 fixed20_12 estimated_width;
946 fixed20_12 worst_case_latency;
947 fixed20_12 consumption_rate;
948 fixed20_12 active_time;
949 fixed20_12 dbpp;
950 fixed20_12 priority_mark_max;
951 fixed20_12 priority_mark;
952 fixed20_12 sclk;
953};
954
955static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
956 struct radeon_crtc *crtc,
957 struct rv515_watermark *wm,
958 bool_Bool low)
959{
960 struct drm_display_mode *mode = &crtc->base.mode;
961 fixed20_12 a, b, c;
962 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
963 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
964 fixed20_12 sclk;
965 u32 selected_sclk;
966
967 if (!crtc->base.enabled) {
18
Assuming field 'enabled' is false
19
Taking true branch
968 /* FIXME: wouldn't it better to set priority mark to maximum */
969 wm->lb_request_fifo_depth = 4;
970 return;
20
Returning without writing to 'wm->dbpp.full'
971 }
972
973 /* rv6xx, rv7xx */
974 if ((rdev->family >= CHIP_RV610) &&
975 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
976 selected_sclk = radeon_dpm_get_sclk(rdev, low)rdev->asic->dpm.get_sclk((rdev), (low));
977 else
978 selected_sclk = rdev->pm.current_sclk;
979
980 /* sclk in Mhz */
981 a.full = dfixed_const(100)(u32)(((100) << 12));
982 sclk.full = dfixed_const(selected_sclk)(u32)(((selected_sclk) << 12));
983 sclk.full = dfixed_div(sclk, a);
984
985 if (crtc->vsc.full > dfixed_const(2)(u32)(((2) << 12)))
986 wm->num_line_pair.full = dfixed_const(2)(u32)(((2) << 12));
987 else
988 wm->num_line_pair.full = dfixed_const(1)(u32)(((1) << 12));
989
990 b.full = dfixed_const(mode->crtc_hdisplay)(u32)(((mode->crtc_hdisplay) << 12));
991 c.full = dfixed_const(256)(u32)(((256) << 12));
992 a.full = dfixed_div(b, c);
993 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair)((u64)((u64)(a).full * (wm->num_line_pair).full + 2048) >>
12)
;
994 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
995 if (a.full < dfixed_const(4)(u32)(((4) << 12))) {
996 wm->lb_request_fifo_depth = 4;
997 } else {
998 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth)((request_fifo_depth).full >> 12);
999 }
1000
1001 /* Determine consumption rate
1002 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
1003 * vtaps = number of vertical taps,
1004 * vsc = vertical scaling ratio, defined as source/destination
1005 * hsc = horizontal scaling ration, defined as source/destination
1006 */
1007 a.full = dfixed_const(mode->clock)(u32)(((mode->clock) << 12));
1008 b.full = dfixed_const(1000)(u32)(((1000) << 12));
1009 a.full = dfixed_div(a, b);
1010 pclk.full = dfixed_div(b, a);
1011 if (crtc->rmx_type != RMX_OFF) {
1012 b.full = dfixed_const(2)(u32)(((2) << 12));
1013 if (crtc->vsc.full > b.full)
1014 b.full = crtc->vsc.full;
1015 b.full = dfixed_mul(b, crtc->hsc)((u64)((u64)(b).full * (crtc->hsc).full + 2048) >> 12
)
;
1016 c.full = dfixed_const(2)(u32)(((2) << 12));
1017 b.full = dfixed_div(b, c);
1018 consumption_time.full = dfixed_div(pclk, b);
1019 } else {
1020 consumption_time.full = pclk.full;
1021 }
1022 a.full = dfixed_const(1)(u32)(((1) << 12));
1023 wm->consumption_rate.full = dfixed_div(a, consumption_time);
1024
1025
1026 /* Determine line time
1027 * LineTime = total time for one line of displayhtotal
1028 * LineTime = total number of horizontal pixels
1029 * pclk = pixel clock period(ns)
1030 */
1031 a.full = dfixed_const(crtc->base.mode.crtc_htotal)(u32)(((crtc->base.mode.crtc_htotal) << 12));
1032 line_time.full = dfixed_mul(a, pclk)((u64)((u64)(a).full * (pclk).full + 2048) >> 12);
1033
1034 /* Determine active time
1035 * ActiveTime = time of active region of display within one line,
1036 * hactive = total number of horizontal active pixels
1037 * htotal = total number of horizontal pixels
1038 */
1039 a.full = dfixed_const(crtc->base.mode.crtc_htotal)(u32)(((crtc->base.mode.crtc_htotal) << 12));
1040 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay)(u32)(((crtc->base.mode.crtc_hdisplay) << 12));
1041 wm->active_time.full = dfixed_mul(line_time, b)((u64)((u64)(line_time).full * (b).full + 2048) >> 12);
1042 wm->active_time.full = dfixed_div(wm->active_time, a);
1043
1044 /* Determine chunk time
1045 * ChunkTime = the time it takes the DCP to send one chunk of data
1046 * to the LB which consists of pipeline delay and inter chunk gap
1047 * sclk = system clock(Mhz)
1048 */
1049 a.full = dfixed_const(600 * 1000)(u32)(((600 * 1000) << 12));
1050 chunk_time.full = dfixed_div(a, sclk);
1051 read_delay_latency.full = dfixed_const(1000)(u32)(((1000) << 12));
1052
1053 /* Determine the worst case latency
1054 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1055 * WorstCaseLatency = worst case time from urgent to when the MC starts
1056 * to return data
1057 * READ_DELAY_IDLE_MAX = constant of 1us
1058 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1059 * which consists of pipeline delay and inter chunk gap
1060 */
1061 if (dfixed_trunc(wm->num_line_pair)((wm->num_line_pair).full >> 12) > 1) {
1062 a.full = dfixed_const(3)(u32)(((3) << 12));
1063 wm->worst_case_latency.full = dfixed_mul(a, chunk_time)((u64)((u64)(a).full * (chunk_time).full + 2048) >> 12);
1064 wm->worst_case_latency.full += read_delay_latency.full;
1065 } else {
1066 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1067 }
1068
1069 /* Determine the tolerable latency
1070 * TolerableLatency = Any given request has only 1 line time
1071 * for the data to be returned
1072 * LBRequestFifoDepth = Number of chunk requests the LB can
1073 * put into the request FIFO for a display
1074 * LineTime = total time for one line of display
1075 * ChunkTime = the time it takes the DCP to send one chunk
1076 * of data to the LB which consists of
1077 * pipeline delay and inter chunk gap
1078 */
1079 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)((request_fifo_depth).full >> 12)) {
1080 tolerable_latency.full = line_time.full;
1081 } else {
1082 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2)(u32)(((wm->lb_request_fifo_depth - 2) << 12));
1083 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1084 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time)((u64)((u64)(tolerable_latency).full * (chunk_time).full + 2048
) >> 12)
;
1085 tolerable_latency.full = line_time.full - tolerable_latency.full;
1086 }
1087 /* We assume worst case 32bits (4 bytes) */
1088 wm->dbpp.full = dfixed_const(2 * 16)(u32)(((2 * 16) << 12));
1089
1090 /* Determine the maximum priority mark
1091 * width = viewport width in pixels
1092 */
1093 a.full = dfixed_const(16)(u32)(((16) << 12));
1094 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay)(u32)(((crtc->base.mode.crtc_hdisplay) << 12));
1095 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1096 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1097
1098 /* Determine estimated width */
1099 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1100 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1101 if (dfixed_trunc(estimated_width)((estimated_width).full >> 12) > crtc->base.mode.crtc_hdisplay) {
1102 wm->priority_mark.full = wm->priority_mark_max.full;
1103 } else {
1104 a.full = dfixed_const(16)(u32)(((16) << 12));
1105 wm->priority_mark.full = dfixed_div(estimated_width, a);
1106 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1107 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1108 }
1109}
1110
1111static void rv515_compute_mode_priority(struct radeon_device *rdev,
1112 struct rv515_watermark *wm0,
1113 struct rv515_watermark *wm1,
1114 struct drm_display_mode *mode0,
1115 struct drm_display_mode *mode1,
1116 u32 *d1mode_priority_a_cnt,
1117 u32 *d2mode_priority_a_cnt)
1118{
1119 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1120 fixed20_12 a, b;
1121
1122 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF(1 << 16);
1123 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF(1 << 16);
1124
1125 if (mode0
22.1
'mode0' is non-null
&& mode1
22.2
'mode1' is null
) {
23
Taking false branch
1126 if (dfixed_trunc(wm0->dbpp)((wm0->dbpp).full >> 12) > 64)
1127 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1128 else
1129 a.full = wm0->num_line_pair.full;
1130 if (dfixed_trunc(wm1->dbpp)((wm1->dbpp).full >> 12) > 64)
1131 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1132 else
1133 b.full = wm1->num_line_pair.full;
1134 a.full += b.full;
1135 fill_rate.full = dfixed_div(wm0->sclk, a);
1136 if (wm0->consumption_rate.full > fill_rate.full) {
1137 b.full = wm0->consumption_rate.full - fill_rate.full;
1138 b.full = dfixed_mul(b, wm0->active_time)((u64)((u64)(b).full * (wm0->active_time).full + 2048) >>
12)
;
1139 a.full = dfixed_const(16)(u32)(((16) << 12));
1140 b.full = dfixed_div(b, a);
1141 a.full = dfixed_mul(wm0->worst_case_latency,((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
1142 wm0->consumption_rate)((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
;
1143 priority_mark02.full = a.full + b.full;
1144 } else {
1145 a.full = dfixed_mul(wm0->worst_case_latency,((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
1146 wm0->consumption_rate)((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
;
1147 b.full = dfixed_const(16 * 1000)(u32)(((16 * 1000) << 12));
1148 priority_mark02.full = dfixed_div(a, b);
1149 }
1150 if (wm1->consumption_rate.full > fill_rate.full) {
1151 b.full = wm1->consumption_rate.full - fill_rate.full;
1152 b.full = dfixed_mul(b, wm1->active_time)((u64)((u64)(b).full * (wm1->active_time).full + 2048) >>
12)
;
1153 a.full = dfixed_const(16)(u32)(((16) << 12));
1154 b.full = dfixed_div(b, a);
1155 a.full = dfixed_mul(wm1->worst_case_latency,((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
1156 wm1->consumption_rate)((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
;
1157 priority_mark12.full = a.full + b.full;
1158 } else {
1159 a.full = dfixed_mul(wm1->worst_case_latency,((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
1160 wm1->consumption_rate)((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
;
1161 b.full = dfixed_const(16 * 1000)(u32)(((16 * 1000) << 12));
1162 priority_mark12.full = dfixed_div(a, b);
1163 }
1164 if (wm0->priority_mark.full > priority_mark02.full)
1165 priority_mark02.full = wm0->priority_mark.full;
1166 if (wm0->priority_mark_max.full > priority_mark02.full)
1167 priority_mark02.full = wm0->priority_mark_max.full;
1168 if (wm1->priority_mark.full > priority_mark12.full)
1169 priority_mark12.full = wm1->priority_mark.full;
1170 if (wm1->priority_mark_max.full > priority_mark12.full)
1171 priority_mark12.full = wm1->priority_mark_max.full;
1172 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02)((priority_mark02).full >> 12);
1173 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12)((priority_mark12).full >> 12);
1174 if (rdev->disp_priority == 2) {
1175 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON(1 << 20);
1176 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON(1 << 20);
1177 }
1178 } else if (mode0
23.1
'mode0' is non-null
) {
24
Taking true branch
1179 if (dfixed_trunc(wm0->dbpp)((wm0->dbpp).full >> 12) > 64)
25
The left operand of '>>' is a garbage value
1180 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1181 else
1182 a.full = wm0->num_line_pair.full;
1183 fill_rate.full = dfixed_div(wm0->sclk, a);
1184 if (wm0->consumption_rate.full > fill_rate.full) {
1185 b.full = wm0->consumption_rate.full - fill_rate.full;
1186 b.full = dfixed_mul(b, wm0->active_time)((u64)((u64)(b).full * (wm0->active_time).full + 2048) >>
12)
;
1187 a.full = dfixed_const(16)(u32)(((16) << 12));
1188 b.full = dfixed_div(b, a);
1189 a.full = dfixed_mul(wm0->worst_case_latency,((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
1190 wm0->consumption_rate)((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
;
1191 priority_mark02.full = a.full + b.full;
1192 } else {
1193 a.full = dfixed_mul(wm0->worst_case_latency,((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
1194 wm0->consumption_rate)((u64)((u64)(wm0->worst_case_latency).full * (wm0->consumption_rate
).full + 2048) >> 12)
;
1195 b.full = dfixed_const(16)(u32)(((16) << 12));
1196 priority_mark02.full = dfixed_div(a, b);
1197 }
1198 if (wm0->priority_mark.full > priority_mark02.full)
1199 priority_mark02.full = wm0->priority_mark.full;
1200 if (wm0->priority_mark_max.full > priority_mark02.full)
1201 priority_mark02.full = wm0->priority_mark_max.full;
1202 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02)((priority_mark02).full >> 12);
1203 if (rdev->disp_priority == 2)
1204 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON(1 << 20);
1205 } else if (mode1) {
1206 if (dfixed_trunc(wm1->dbpp)((wm1->dbpp).full >> 12) > 64)
1207 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1208 else
1209 a.full = wm1->num_line_pair.full;
1210 fill_rate.full = dfixed_div(wm1->sclk, a);
1211 if (wm1->consumption_rate.full > fill_rate.full) {
1212 b.full = wm1->consumption_rate.full - fill_rate.full;
1213 b.full = dfixed_mul(b, wm1->active_time)((u64)((u64)(b).full * (wm1->active_time).full + 2048) >>
12)
;
1214 a.full = dfixed_const(16)(u32)(((16) << 12));
1215 b.full = dfixed_div(b, a);
1216 a.full = dfixed_mul(wm1->worst_case_latency,((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
1217 wm1->consumption_rate)((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
;
1218 priority_mark12.full = a.full + b.full;
1219 } else {
1220 a.full = dfixed_mul(wm1->worst_case_latency,((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
1221 wm1->consumption_rate)((u64)((u64)(wm1->worst_case_latency).full * (wm1->consumption_rate
).full + 2048) >> 12)
;
1222 b.full = dfixed_const(16 * 1000)(u32)(((16 * 1000) << 12));
1223 priority_mark12.full = dfixed_div(a, b);
1224 }
1225 if (wm1->priority_mark.full > priority_mark12.full)
1226 priority_mark12.full = wm1->priority_mark.full;
1227 if (wm1->priority_mark_max.full > priority_mark12.full)
1228 priority_mark12.full = wm1->priority_mark_max.full;
1229 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12)((priority_mark12).full >> 12);
1230 if (rdev->disp_priority == 2)
1231 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON(1 << 20);
1232 }
1233}
1234
1235void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1236{
1237 struct drm_display_mode *mode0 = NULL((void *)0);
1238 struct drm_display_mode *mode1 = NULL((void *)0);
1239 struct rv515_watermark wm0_high, wm0_low;
1240 struct rv515_watermark wm1_high, wm1_low;
1241 u32 tmp;
1242 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1243 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1244
1245 if (rdev->mode_info.crtcs[0]->base.enabled)
13
Assuming field 'enabled' is true
14
Taking true branch
1246 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1247 if (rdev->mode_info.crtcs[1]->base.enabled)
15
Assuming field 'enabled' is false
16
Taking false branch
1248 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1249 rs690_line_buffer_adjust(rdev, mode0, mode1);
1250
1251 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false0);
17
Calling 'rv515_crtc_bandwidth_compute'
21
Returning from 'rv515_crtc_bandwidth_compute'
1252 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false0);
1253
1254 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false0);
1255 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false0);
1256
1257 tmp = wm0_high.lb_request_fifo_depth;
1258 tmp |= wm1_high.lb_request_fifo_depth << 16;
1259 WREG32(LB_MAX_REQ_OUTSTANDING, tmp)r100_mm_wreg(rdev, (0x6D58), (tmp), 0);
1260
1261 rv515_compute_mode_priority(rdev,
22
Calling 'rv515_compute_mode_priority'
1262 &wm0_high, &wm1_high,
1263 mode0, mode1,
1264 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1265 rv515_compute_mode_priority(rdev,
1266 &wm0_low, &wm1_low,
1267 mode0, mode1,
1268 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1269
1270 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt)r100_mm_wreg(rdev, (0x6548), (d1mode_priority_a_cnt), 0);
1271 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt)r100_mm_wreg(rdev, (0x654C), (d1mode_priority_b_cnt), 0);
1272 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt)r100_mm_wreg(rdev, (0x6D48), (d2mode_priority_a_cnt), 0);
1273 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt)r100_mm_wreg(rdev, (0x6D4C), (d2mode_priority_b_cnt), 0);
1274}
1275
1276void rv515_bandwidth_update(struct radeon_device *rdev)
1277{
1278 uint32_t tmp;
1279 struct drm_display_mode *mode0 = NULL((void *)0);
1280 struct drm_display_mode *mode1 = NULL((void *)0);
1281
1282 if (!rdev->mode_info.mode_config_initialized)
1
Assuming field 'mode_config_initialized' is true
2
Taking false branch
1283 return;
1284
1285 radeon_update_display_priority(rdev);
1286
1287 if (rdev->mode_info.crtcs[0]->base.enabled)
3
Assuming field 'enabled' is false
4
Taking false branch
1288 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1289 if (rdev->mode_info.crtcs[1]->base.enabled)
5
Assuming field 'enabled' is false
6
Taking false branch
1290 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1291 /*
1292 * Set display0/1 priority up in the memory controller for
1293 * modes if the user specifies HIGH for displaypriority
1294 * option.
1295 */
1296 if ((rdev->disp_priority == 2) &&
7
Assuming field 'disp_priority' is equal to 2
9
Taking true branch
1297 (rdev->family == CHIP_RV515)) {
8
Assuming field 'family' is equal to CHIP_RV515
1298 tmp = RREG32_MC(MC_MISC_LAT_TIMER)rdev->mc_rreg(rdev, (0x09));
1299 tmp &= ~MC_DISP1R_INIT_LAT_MASK0x0000F000;
1300 tmp &= ~MC_DISP0R_INIT_LAT_MASK0x00000F00;
1301 if (mode1
9.1
'mode1' is null
)
10
Taking false branch
1302 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT12);
1303 if (mode0
10.1
'mode0' is null
)
11
Taking false branch
1304 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT8);
1305 WREG32_MC(MC_MISC_LAT_TIMER, tmp)rdev->mc_wreg(rdev, (0x09), (tmp));
1306 }
1307 rv515_bandwidth_avivo_update(rdev);
12
Calling 'rv515_bandwidth_avivo_update'
1308}