Bug Summary

File:dev/pci/drm/i915/display/intel_display.c
Warning:line 9221, column 27
Value stored to 'i915' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name intel_display.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_display.c
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/i2c.h>
28#include <linux/input.h>
29#include <linux/intel-iommu.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/dma-resv.h>
33#include <linux/slab.h>
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_atomic_uapi.h>
38#include <drm/drm_damage_helper.h>
39#include <drm/drm_dp_helper.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_fourcc.h>
42#include <drm/drm_plane_helper.h>
43#include <drm/drm_probe_helper.h>
44#include <drm/drm_rect.h>
45
46#include "display/intel_crt.h"
47#include "display/intel_ddi.h"
48#include "display/intel_dp.h"
49#include "display/intel_dp_mst.h"
50#include "display/intel_dpll_mgr.h"
51#include "display/intel_dsi.h"
52#include "display/intel_dvo.h"
53#include "display/intel_gmbus.h"
54#include "display/intel_hdmi.h"
55#include "display/intel_lvds.h"
56#include "display/intel_sdvo.h"
57#include "display/intel_tv.h"
58#include "display/intel_vdsc.h"
59
60#include "gt/intel_rps.h"
61
62#include "i915_drv.h"
63#include "i915_trace.h"
64#include "intel_acpi.h"
65#include "intel_atomic.h"
66#include "intel_atomic_plane.h"
67#include "intel_bw.h"
68#include "intel_cdclk.h"
69#include "intel_color.h"
70#include "intel_csr.h"
71#include "intel_display_types.h"
72#include "intel_dp_link_training.h"
73#include "intel_fbc.h"
74#include "intel_fbdev.h"
75#include "intel_fifo_underrun.h"
76#include "intel_frontbuffer.h"
77#include "intel_hdcp.h"
78#include "intel_hotplug.h"
79#include "intel_overlay.h"
80#include "intel_pipe_crc.h"
81#include "intel_pm.h"
82#include "intel_psr.h"
83#include "intel_quirks.h"
84#include "intel_sideband.h"
85#include "intel_sprite.h"
86#include "intel_tc.h"
87#include "intel_vga.h"
88
89/* Primary plane formats for gen <= 3 */
90static const u32 i8xx_primary_formats[] = {
91 DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
,
92 DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
,
93 DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
,
94 DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
95};
96
97/* Primary plane formats for ivb (no fp16 due to hw issue) */
98static const u32 ivb_primary_formats[] = {
99 DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
,
100 DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
,
101 DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
102 DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
103 DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
104 DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
105};
106
107/* Primary plane formats for gen >= 4, except ivb */
108static const u32 i965_primary_formats[] = {
109 DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
,
110 DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
,
111 DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
112 DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
113 DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
114 DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
115 DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
,
116};
117
118/* Primary plane formats for vlv/chv */
119static const u32 vlv_primary_formats[] = {
120 DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
,
121 DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
,
122 DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
123 DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
124 DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
125 DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
126 DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
127 DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
128 DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
129 DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
,
130 DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
,
131};
132
133static const u64 i9xx_format_modifiers[] = {
134 I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
,
135 DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
,
136 DRM_FORMAT_MOD_INVALID((((__u64)0) << 56) | ((((1ULL << 56) - 1)) &
0x00ffffffffffffffULL))
137};
138
139/* Cursor formats */
140static const u32 intel_cursor_formats[] = {
141 DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
,
142};
143
144static const u64 cursor_format_modifiers[] = {
145 DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
,
146 DRM_FORMAT_MOD_INVALID((((__u64)0) << 56) | ((((1ULL << 56) - 1)) &
0x00ffffffffffffffULL))
147};
148
149static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
150 struct intel_crtc_state *pipe_config);
151static void ilk_pch_clock_get(struct intel_crtc *crtc,
152 struct intel_crtc_state *pipe_config);
153
154static int intel_framebuffer_init(struct intel_framebuffer *ifb,
155 struct drm_i915_gem_object *obj,
156 struct drm_mode_fb_cmd2 *mode_cmd);
157static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state);
158static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
159static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,
160 const struct intel_link_m_n *m_n,
161 const struct intel_link_m_n *m2_n2);
162static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
163static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
164static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state);
165static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
166static void vlv_prepare_pll(struct intel_crtc *crtc,
167 const struct intel_crtc_state *pipe_config);
168static void chv_prepare_pll(struct intel_crtc *crtc,
169 const struct intel_crtc_state *pipe_config);
170static void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
171static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
172static void intel_modeset_setup_hw_state(struct drm_device *dev,
173 struct drm_modeset_acquire_ctx *ctx);
174static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc);
175
176struct intel_limit {
177 struct {
178 int min, max;
179 } dot, vco, n, m, m1, m2, p, p1;
180
181 struct {
182 int dot_limit;
183 int p2_slow, p2_fast;
184 } p2;
185};
186
187/* returns HPLL frequency in kHz */
188int vlv_get_hpll_vco(struct drm_i915_privateinteldrm_softc *dev_priv)
189{
190 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
191
192 /* Obtain SKU information */
193 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG0x8) &
194 CCK_FUSE_HPLL_FREQ_MASK0x3;
195
196 return vco_freq[hpll_freq] * 1000;
197}
198
199int vlv_get_cck_clock(struct drm_i915_privateinteldrm_softc *dev_priv,
200 const char *name, u32 reg, int ref_freq)
201{
202 u32 val;
203 int divider;
204
205 val = vlv_cck_read(dev_priv, reg);
206 divider = val & CCK_FREQUENCY_VALUES(0x1f << 0);
207
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=({ int __ret = !!((val & (0x1f << 8)) != (divider <<
8)); if (__ret) printf("%s %s: " "%s change in progress\n", dev_driver_string
((&dev_priv->drm)->dev), "", name); __builtin_expect
(!!(__ret), 0); })
209 (divider << CCK_FREQUENCY_STATUS_SHIFT),({ int __ret = !!((val & (0x1f << 8)) != (divider <<
8)); if (__ret) printf("%s %s: " "%s change in progress\n", dev_driver_string
((&dev_priv->drm)->dev), "", name); __builtin_expect
(!!(__ret), 0); })
210 "%s change in progress\n", name)({ int __ret = !!((val & (0x1f << 8)) != (divider <<
8)); if (__ret) printf("%s %s: " "%s change in progress\n", dev_driver_string
((&dev_priv->drm)->dev), "", name); __builtin_expect
(!!(__ret), 0); })
;
211
212 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1)(((ref_freq << 1) + ((divider + 1) / 2)) / (divider + 1
))
;
213}
214
215int vlv_get_cck_clock_hpll(struct drm_i915_privateinteldrm_softc *dev_priv,
216 const char *name, u32 reg)
217{
218 int hpll;
219
220 vlv_cck_get(dev_priv);
221
222 if (dev_priv->hpll_freq == 0)
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
224
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
226
227 vlv_cck_put(dev_priv);
228
229 return hpll;
230}
231
232static void intel_update_czclk(struct drm_i915_privateinteldrm_softc *dev_priv)
233{
234 if (!(IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)))
235 return;
236
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
238 CCK_CZ_CLOCK_CONTROL0x62);
239
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "CZ clock rate: %d kHz\n"
, dev_priv->czclk_freq)
241 dev_priv->czclk_freq)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "CZ clock rate: %d kHz\n"
, dev_priv->czclk_freq)
;
242}
243
244/* units of 100MHz */
245static u32 intel_fdi_link_freq(struct drm_i915_privateinteldrm_softc *dev_priv,
246 const struct intel_crtc_state *pipe_config)
247{
248 if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi))
249 return pipe_config->port_clock; /* SPLL */
250 else
251 return dev_priv->fdi_pll_freq;
252}
253
254static const struct intel_limit intel_limits_i8xx_dac = {
255 .dot = { .min = 25000, .max = 350000 },
256 .vco = { .min = 908000, .max = 1512000 },
257 .n = { .min = 2, .max = 16 },
258 .m = { .min = 96, .max = 140 },
259 .m1 = { .min = 18, .max = 26 },
260 .m2 = { .min = 6, .max = 16 },
261 .p = { .min = 4, .max = 128 },
262 .p1 = { .min = 2, .max = 33 },
263 .p2 = { .dot_limit = 165000,
264 .p2_slow = 4, .p2_fast = 2 },
265};
266
267static const struct intel_limit intel_limits_i8xx_dvo = {
268 .dot = { .min = 25000, .max = 350000 },
269 .vco = { .min = 908000, .max = 1512000 },
270 .n = { .min = 2, .max = 16 },
271 .m = { .min = 96, .max = 140 },
272 .m1 = { .min = 18, .max = 26 },
273 .m2 = { .min = 6, .max = 16 },
274 .p = { .min = 4, .max = 128 },
275 .p1 = { .min = 2, .max = 33 },
276 .p2 = { .dot_limit = 165000,
277 .p2_slow = 4, .p2_fast = 4 },
278};
279
280static const struct intel_limit intel_limits_i8xx_lvds = {
281 .dot = { .min = 25000, .max = 350000 },
282 .vco = { .min = 908000, .max = 1512000 },
283 .n = { .min = 2, .max = 16 },
284 .m = { .min = 96, .max = 140 },
285 .m1 = { .min = 18, .max = 26 },
286 .m2 = { .min = 6, .max = 16 },
287 .p = { .min = 4, .max = 128 },
288 .p1 = { .min = 1, .max = 6 },
289 .p2 = { .dot_limit = 165000,
290 .p2_slow = 14, .p2_fast = 7 },
291};
292
293static const struct intel_limit intel_limits_i9xx_sdvo = {
294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1400000, .max = 2800000 },
296 .n = { .min = 1, .max = 6 },
297 .m = { .min = 70, .max = 120 },
298 .m1 = { .min = 8, .max = 18 },
299 .m2 = { .min = 3, .max = 7 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 200000,
303 .p2_slow = 10, .p2_fast = 5 },
304};
305
306static const struct intel_limit intel_limits_i9xx_lvds = {
307 .dot = { .min = 20000, .max = 400000 },
308 .vco = { .min = 1400000, .max = 2800000 },
309 .n = { .min = 1, .max = 6 },
310 .m = { .min = 70, .max = 120 },
311 .m1 = { .min = 8, .max = 18 },
312 .m2 = { .min = 3, .max = 7 },
313 .p = { .min = 7, .max = 98 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 112000,
316 .p2_slow = 14, .p2_fast = 7 },
317};
318
319
320static const struct intel_limit intel_limits_g4x_sdvo = {
321 .dot = { .min = 25000, .max = 270000 },
322 .vco = { .min = 1750000, .max = 3500000},
323 .n = { .min = 1, .max = 4 },
324 .m = { .min = 104, .max = 138 },
325 .m1 = { .min = 17, .max = 23 },
326 .m2 = { .min = 5, .max = 11 },
327 .p = { .min = 10, .max = 30 },
328 .p1 = { .min = 1, .max = 3},
329 .p2 = { .dot_limit = 270000,
330 .p2_slow = 10,
331 .p2_fast = 10
332 },
333};
334
335static const struct intel_limit intel_limits_g4x_hdmi = {
336 .dot = { .min = 22000, .max = 400000 },
337 .vco = { .min = 1750000, .max = 3500000},
338 .n = { .min = 1, .max = 4 },
339 .m = { .min = 104, .max = 138 },
340 .m1 = { .min = 16, .max = 23 },
341 .m2 = { .min = 5, .max = 11 },
342 .p = { .min = 5, .max = 80 },
343 .p1 = { .min = 1, .max = 8},
344 .p2 = { .dot_limit = 165000,
345 .p2_slow = 10, .p2_fast = 5 },
346};
347
348static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
349 .dot = { .min = 20000, .max = 115000 },
350 .vco = { .min = 1750000, .max = 3500000 },
351 .n = { .min = 1, .max = 3 },
352 .m = { .min = 104, .max = 138 },
353 .m1 = { .min = 17, .max = 23 },
354 .m2 = { .min = 5, .max = 11 },
355 .p = { .min = 28, .max = 112 },
356 .p1 = { .min = 2, .max = 8 },
357 .p2 = { .dot_limit = 0,
358 .p2_slow = 14, .p2_fast = 14
359 },
360};
361
362static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
363 .dot = { .min = 80000, .max = 224000 },
364 .vco = { .min = 1750000, .max = 3500000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 104, .max = 138 },
367 .m1 = { .min = 17, .max = 23 },
368 .m2 = { .min = 5, .max = 11 },
369 .p = { .min = 14, .max = 42 },
370 .p1 = { .min = 2, .max = 6 },
371 .p2 = { .dot_limit = 0,
372 .p2_slow = 7, .p2_fast = 7
373 },
374};
375
376static const struct intel_limit pnv_limits_sdvo = {
377 .dot = { .min = 20000, .max = 400000},
378 .vco = { .min = 1700000, .max = 3500000 },
379 /* Pineview's Ncounter is a ring counter */
380 .n = { .min = 3, .max = 6 },
381 .m = { .min = 2, .max = 256 },
382 /* Pineview only has one combined m divider, which we treat as m2. */
383 .m1 = { .min = 0, .max = 0 },
384 .m2 = { .min = 0, .max = 254 },
385 .p = { .min = 5, .max = 80 },
386 .p1 = { .min = 1, .max = 8 },
387 .p2 = { .dot_limit = 200000,
388 .p2_slow = 10, .p2_fast = 5 },
389};
390
391static const struct intel_limit pnv_limits_lvds = {
392 .dot = { .min = 20000, .max = 400000 },
393 .vco = { .min = 1700000, .max = 3500000 },
394 .n = { .min = 3, .max = 6 },
395 .m = { .min = 2, .max = 256 },
396 .m1 = { .min = 0, .max = 0 },
397 .m2 = { .min = 0, .max = 254 },
398 .p = { .min = 7, .max = 112 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 112000,
401 .p2_slow = 14, .p2_fast = 14 },
402};
403
404/* Ironlake / Sandybridge
405 *
406 * We calculate clock using (register_value + 2) for N/M1/M2, so here
407 * the range value for them is (actual_value - 2).
408 */
409static const struct intel_limit ilk_limits_dac = {
410 .dot = { .min = 25000, .max = 350000 },
411 .vco = { .min = 1760000, .max = 3510000 },
412 .n = { .min = 1, .max = 5 },
413 .m = { .min = 79, .max = 127 },
414 .m1 = { .min = 12, .max = 22 },
415 .m2 = { .min = 5, .max = 9 },
416 .p = { .min = 5, .max = 80 },
417 .p1 = { .min = 1, .max = 8 },
418 .p2 = { .dot_limit = 225000,
419 .p2_slow = 10, .p2_fast = 5 },
420};
421
422static const struct intel_limit ilk_limits_single_lvds = {
423 .dot = { .min = 25000, .max = 350000 },
424 .vco = { .min = 1760000, .max = 3510000 },
425 .n = { .min = 1, .max = 3 },
426 .m = { .min = 79, .max = 118 },
427 .m1 = { .min = 12, .max = 22 },
428 .m2 = { .min = 5, .max = 9 },
429 .p = { .min = 28, .max = 112 },
430 .p1 = { .min = 2, .max = 8 },
431 .p2 = { .dot_limit = 225000,
432 .p2_slow = 14, .p2_fast = 14 },
433};
434
435static const struct intel_limit ilk_limits_dual_lvds = {
436 .dot = { .min = 25000, .max = 350000 },
437 .vco = { .min = 1760000, .max = 3510000 },
438 .n = { .min = 1, .max = 3 },
439 .m = { .min = 79, .max = 127 },
440 .m1 = { .min = 12, .max = 22 },
441 .m2 = { .min = 5, .max = 9 },
442 .p = { .min = 14, .max = 56 },
443 .p1 = { .min = 2, .max = 8 },
444 .p2 = { .dot_limit = 225000,
445 .p2_slow = 7, .p2_fast = 7 },
446};
447
448/* LVDS 100mhz refclk limits. */
449static const struct intel_limit ilk_limits_single_lvds_100m = {
450 .dot = { .min = 25000, .max = 350000 },
451 .vco = { .min = 1760000, .max = 3510000 },
452 .n = { .min = 1, .max = 2 },
453 .m = { .min = 79, .max = 126 },
454 .m1 = { .min = 12, .max = 22 },
455 .m2 = { .min = 5, .max = 9 },
456 .p = { .min = 28, .max = 112 },
457 .p1 = { .min = 2, .max = 8 },
458 .p2 = { .dot_limit = 225000,
459 .p2_slow = 14, .p2_fast = 14 },
460};
461
462static const struct intel_limit ilk_limits_dual_lvds_100m = {
463 .dot = { .min = 25000, .max = 350000 },
464 .vco = { .min = 1760000, .max = 3510000 },
465 .n = { .min = 1, .max = 3 },
466 .m = { .min = 79, .max = 126 },
467 .m1 = { .min = 12, .max = 22 },
468 .m2 = { .min = 5, .max = 9 },
469 .p = { .min = 14, .max = 42 },
470 .p1 = { .min = 2, .max = 6 },
471 .p2 = { .dot_limit = 225000,
472 .p2_slow = 7, .p2_fast = 7 },
473};
474
475static const struct intel_limit intel_limits_vlv = {
476 /*
477 * These are the data rate limits (measured in fast clocks)
478 * since those are the strictest limits we have. The fast
479 * clock and actual rate limits are more relaxed, so checking
480 * them would make no difference.
481 */
482 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
483 .vco = { .min = 4000000, .max = 6000000 },
484 .n = { .min = 1, .max = 7 },
485 .m1 = { .min = 2, .max = 3 },
486 .m2 = { .min = 11, .max = 156 },
487 .p1 = { .min = 2, .max = 3 },
488 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
489};
490
491static const struct intel_limit intel_limits_chv = {
492 /*
493 * These are the data rate limits (measured in fast clocks)
494 * since those are the strictest limits we have. The fast
495 * clock and actual rate limits are more relaxed, so checking
496 * them would make no difference.
497 */
498 .dot = { .min = 25000 * 5, .max = 540000 * 5},
499 .vco = { .min = 4800000, .max = 6480000 },
500 .n = { .min = 1, .max = 1 },
501 .m1 = { .min = 2, .max = 2 },
502 .m2 = { .min = 24 << 22, .max = 175 << 22 },
503 .p1 = { .min = 2, .max = 4 },
504 .p2 = { .p2_slow = 1, .p2_fast = 14 },
505};
506
507static const struct intel_limit intel_limits_bxt = {
508 /* FIXME: find real dot limits */
509 .dot = { .min = 0, .max = INT_MAX0x7fffffff },
510 .vco = { .min = 4800000, .max = 6700000 },
511 .n = { .min = 1, .max = 1 },
512 .m1 = { .min = 2, .max = 2 },
513 /* FIXME: find real m2 limits */
514 .m2 = { .min = 2 << 22, .max = 255 << 22 },
515 .p1 = { .min = 2, .max = 4 },
516 .p2 = { .p2_slow = 1, .p2_fast = 20 },
517};
518
519/* WA Display #0827: Gen9:all */
520static void
521skl_wa_827(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe, bool_Bool enable)
522{
523 if (enable)
524 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
,
525 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
) | DUPS1_GATING_DIS(1 << 15) | DUPS2_GATING_DIS(1 << 19));
526 else
527 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
,
528 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
) & ~(DUPS1_GATING_DIS(1 << 15) | DUPS2_GATING_DIS(1 << 19)));
529}
530
531/* Wa_2006604312:icl,ehl */
532static void
533icl_wa_scalerclkgating(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe,
534 bool_Bool enable)
535{
536 if (enable)
537 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
,
538 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
) | DPFR_GATING_DIS(1 << 8));
539 else
540 intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
,
541 intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524)
- (0x46520)))) })
) & ~DPFR_GATING_DIS(1 << 8));
542}
543
544static bool_Bool
545needs_modeset(const struct intel_crtc_state *state)
546{
547 return drm_atomic_crtc_needs_modeset(&state->uapi);
548}
549
550static bool_Bool
551is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
552{
553 return crtc_state->master_transcoder != INVALID_TRANSCODER;
554}
555
556static bool_Bool
557is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
558{
559 return crtc_state->sync_mode_slaves_mask != 0;
560}
561
562bool_Bool
563is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
564{
565 return is_trans_port_sync_master(crtc_state) ||
566 is_trans_port_sync_slave(crtc_state);
567}
568
569/*
570 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
571 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
572 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
573 * The helpers' return value is the rate of the clock that is fed to the
574 * display engine's pipe which can be the above fast dot clock rate or a
575 * divided-down version of it.
576 */
577/* m1 is reserved as 0 in Pineview, n is a ring counter */
578static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
579{
580 clock->m = clock->m2 + 2;
581 clock->p = clock->p1 * clock->p2;
582 if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!((clock->n == 0 || clock->p == 0)); if
(__ret) printf("%s", "WARN_ON(" "clock->n == 0 || clock->p == 0"
")"); __builtin_expect(!!(__ret), 0); })
)
583 return 0;
584 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n)(((refclk * clock->m) + ((clock->n) / 2)) / (clock->
n))
;
585 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p));
586
587 return clock->dot;
588}
589
590static u32 i9xx_dpll_compute_m(struct dpll *dpll)
591{
592 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
593}
594
595static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
596{
597 clock->m = i9xx_dpll_compute_m(clock);
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)({ int __ret = !!((clock->n + 2 == 0 || clock->p == 0))
; if (__ret) printf("%s", "WARN_ON(" "clock->n + 2 == 0 || clock->p == 0"
")"); __builtin_expect(!!(__ret), 0); })
)
600 return 0;
601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2)(((refclk * clock->m) + ((clock->n + 2) / 2)) / (clock->
n + 2))
;
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p));
603
604 return clock->dot;
605}
606
607static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
608{
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!((clock->n == 0 || clock->p == 0)); if
(__ret) printf("%s", "WARN_ON(" "clock->n == 0 || clock->p == 0"
")"); __builtin_expect(!!(__ret), 0); })
)
612 return 0;
613 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n)(((refclk * clock->m) + ((clock->n) / 2)) / (clock->
n))
;
614 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p));
615
616 return clock->dot / 5;
617}
618
619int chv_calc_dpll_params(int refclk, struct dpll *clock)
620{
621 clock->m = clock->m1 * clock->m2;
622 clock->p = clock->p1 * clock->p2;
623 if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!((clock->n == 0 || clock->p == 0)); if
(__ret) printf("%s", "WARN_ON(" "clock->n == 0 || clock->p == 0"
")"); __builtin_expect(!!(__ret), 0); })
)
624 return 0;
625 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),(((mul_u32_u32(refclk, clock->m)) + ((clock->n <<
22) / 2)) / (clock->n << 22))
626 clock->n << 22)(((mul_u32_u32(refclk, clock->m)) + ((clock->n <<
22) / 2)) / (clock->n << 22))
;
627 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p));
628
629 return clock->dot / 5;
630}
631
632/*
633 * Returns whether the given set of divisors are valid for a given refclk with
634 * the given connectors.
635 */
636static bool_Bool intel_pll_is_valid(struct drm_i915_privateinteldrm_softc *dev_priv,
637 const struct intel_limit *limit,
638 const struct dpll *clock)
639{
640 if (clock->n < limit->n.min || limit->n.max < clock->n)
641 return false0;
642 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
643 return false0;
644 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
645 return false0;
646 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
647 return false0;
648
649 if (!IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) && !IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) &&
650 !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && !IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) &&
((&(dev_priv)->__info)->is_lp))
)
651 if (clock->m1 <= clock->m2)
652 return false0;
653
654 if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) &&
655 !IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) &&
((&(dev_priv)->__info)->is_lp))
) {
656 if (clock->p < limit->p.min || limit->p.max < clock->p)
657 return false0;
658 if (clock->m < limit->m.min || limit->m.max < clock->m)
659 return false0;
660 }
661
662 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
663 return false0;
664 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
665 * connector, etc., rather than just a single range.
666 */
667 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
668 return false0;
669
670 return true1;
671}
672
673static int
674i9xx_select_p2_div(const struct intel_limit *limit,
675 const struct intel_crtc_state *crtc_state,
676 int target)
677{
678 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
679
680 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
681 /*
682 * For LVDS just rely on its current settings for dual-channel.
683 * We haven't figured out how to reliably set up different
684 * single/dual channel state, if we even can.
685 */
686 if (intel_is_dual_link_lvds(dev_priv))
687 return limit->p2.p2_fast;
688 else
689 return limit->p2.p2_slow;
690 } else {
691 if (target < limit->p2.dot_limit)
692 return limit->p2.p2_slow;
693 else
694 return limit->p2.p2_fast;
695 }
696}
697
698/*
699 * Returns a set of divisors for the desired target clock with the given
700 * refclk, or FALSE. The returned values represent the clock equation:
701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
702 *
703 * Target and reference clocks are specified in kHz.
704 *
705 * If match_clock is provided, then best_clock P divider must match the P
706 * divider from @match_clock used for LVDS downclocking.
707 */
708static bool_Bool
709i9xx_find_best_dpll(const struct intel_limit *limit,
710 struct intel_crtc_state *crtc_state,
711 int target, int refclk, struct dpll *match_clock,
712 struct dpll *best_clock)
713{
714 struct drm_device *dev = crtc_state->uapi.crtc->dev;
715 struct dpll clock;
716 int err = target;
717
718 memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock)));
719
720 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
721
722 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
723 clock.m1++) {
724 for (clock.m2 = limit->m2.min;
725 clock.m2 <= limit->m2.max; clock.m2++) {
726 if (clock.m2 >= clock.m1)
727 break;
728 for (clock.n = limit->n.min;
729 clock.n <= limit->n.max; clock.n++) {
730 for (clock.p1 = limit->p1.min;
731 clock.p1 <= limit->p1.max; clock.p1++) {
732 int this_err;
733
734 i9xx_calc_dpll_params(refclk, &clock);
735 if (!intel_pll_is_valid(to_i915(dev),
736 limit,
737 &clock))
738 continue;
739 if (match_clock &&
740 clock.p != match_clock->p)
741 continue;
742
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
745 *best_clock = clock;
746 err = this_err;
747 }
748 }
749 }
750 }
751 }
752
753 return (err != target);
754}
755
756/*
757 * Returns a set of divisors for the desired target clock with the given
758 * refclk, or FALSE. The returned values represent the clock equation:
759 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
760 *
761 * Target and reference clocks are specified in kHz.
762 *
763 * If match_clock is provided, then best_clock P divider must match the P
764 * divider from @match_clock used for LVDS downclocking.
765 */
766static bool_Bool
767pnv_find_best_dpll(const struct intel_limit *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, struct dpll *match_clock,
770 struct dpll *best_clock)
771{
772 struct drm_device *dev = crtc_state->uapi.crtc->dev;
773 struct dpll clock;
774 int err = target;
775
776 memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock)));
777
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
779
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
781 clock.m1++) {
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 pnv_calc_dpll_params(refclk, &clock);
791 if (!intel_pll_is_valid(to_i915(dev),
792 limit,
793 &clock))
794 continue;
795 if (match_clock &&
796 clock.p != match_clock->p)
797 continue;
798
799 this_err = abs(clock.dot - target);
800 if (this_err < err) {
801 *best_clock = clock;
802 err = this_err;
803 }
804 }
805 }
806 }
807 }
808
809 return (err != target);
810}
811
812/*
813 * Returns a set of divisors for the desired target clock with the given
814 * refclk, or FALSE. The returned values represent the clock equation:
815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
816 *
817 * Target and reference clocks are specified in kHz.
818 *
819 * If match_clock is provided, then best_clock P divider must match the P
820 * divider from @match_clock used for LVDS downclocking.
821 */
822static bool_Bool
823g4x_find_best_dpll(const struct intel_limit *limit,
824 struct intel_crtc_state *crtc_state,
825 int target, int refclk, struct dpll *match_clock,
826 struct dpll *best_clock)
827{
828 struct drm_device *dev = crtc_state->uapi.crtc->dev;
829 struct dpll clock;
830 int max_n;
831 bool_Bool found = false0;
832 /* approximately equals target * 0.00585 */
833 int err_most = (target >> 8) + (target >> 9);
834
835 memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock)));
836
837 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
838
839 max_n = limit->n.max;
840 /* based on hardware requirement, prefer smaller n to precision */
841 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
842 /* based on hardware requirement, prefere larger m1,m2 */
843 for (clock.m1 = limit->m1.max;
844 clock.m1 >= limit->m1.min; clock.m1--) {
845 for (clock.m2 = limit->m2.max;
846 clock.m2 >= limit->m2.min; clock.m2--) {
847 for (clock.p1 = limit->p1.max;
848 clock.p1 >= limit->p1.min; clock.p1--) {
849 int this_err;
850
851 i9xx_calc_dpll_params(refclk, &clock);
852 if (!intel_pll_is_valid(to_i915(dev),
853 limit,
854 &clock))
855 continue;
856
857 this_err = abs(clock.dot - target);
858 if (this_err < err_most) {
859 *best_clock = clock;
860 err_most = this_err;
861 max_n = clock.n;
862 found = true1;
863 }
864 }
865 }
866 }
867 }
868 return found;
869}
870
871/*
872 * Check if the calculated PLL configuration is more optimal compared to the
873 * best configuration and error found so far. Return the calculated error.
874 */
875static bool_Bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
876 const struct dpll *calculated_clock,
877 const struct dpll *best_clock,
878 unsigned int best_error_ppm,
879 unsigned int *error_ppm)
880{
881 /*
882 * For CHV ignore the error and consider only the P value.
883 * Prefer a bigger P value based on HW requirements.
884 */
885 if (IS_CHERRYVIEW(to_i915(dev))IS_PLATFORM(to_i915(dev), INTEL_CHERRYVIEW)) {
886 *error_ppm = 0;
887
888 return calculated_clock->p > best_clock->p;
889 }
890
891 if (drm_WARN_ON_ONCE(dev, !target_freq)({ static int __warned; int __ret = !!((!target_freq)); if (__ret
&& !__warned) { printf("%s %s: " "%s", dev_driver_string
(((dev))->dev), "", "drm_WARN_ON_ONCE(" "!target_freq" ")"
); __warned = 1; } __builtin_expect(!!(__ret), 0); })
)
892 return false0;
893
894 *error_ppm = div_u64(1000000ULL *
895 abs(target_freq - calculated_clock->dot),
896 target_freq);
897 /*
898 * Prefer a better P value over a better (smaller) error if the error
899 * is small. Ensure this preference for future configurations too by
900 * setting the error to 0.
901 */
902 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
903 *error_ppm = 0;
904
905 return true1;
906 }
907
908 return *error_ppm + 10 < best_error_ppm;
909}
910
911/*
912 * Returns a set of divisors for the desired target clock with the given
913 * refclk, or FALSE. The returned values represent the clock equation:
914 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
915 */
916static bool_Bool
917vlv_find_best_dpll(const struct intel_limit *limit,
918 struct intel_crtc_state *crtc_state,
919 int target, int refclk, struct dpll *match_clock,
920 struct dpll *best_clock)
921{
922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
923 struct drm_device *dev = crtc->base.dev;
924 struct dpll clock;
925 unsigned int bestppm = 1000000;
926 /* min update 19.2 MHz */
927 int max_n = min(limit->n.max, refclk / 19200)(((limit->n.max)<(refclk / 19200))?(limit->n.max):(refclk
/ 19200))
;
928 bool_Bool found = false0;
929
930 target *= 5; /* fast clock */
931
932 memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock)));
933
934 /* based on hardware requirement, prefer smaller n to precision */
935 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
936 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
937 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
939 clock.p = clock.p1 * clock.p2;
940 /* based on hardware requirement, prefer bigger m1,m2 values */
941 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
942 unsigned int ppm;
943
944 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,(((target * clock.p * clock.n) + ((refclk * clock.m1) / 2)) /
(refclk * clock.m1))
945 refclk * clock.m1)(((target * clock.p * clock.n) + ((refclk * clock.m1) / 2)) /
(refclk * clock.m1))
;
946
947 vlv_calc_dpll_params(refclk, &clock);
948
949 if (!intel_pll_is_valid(to_i915(dev),
950 limit,
951 &clock))
952 continue;
953
954 if (!vlv_PLL_is_optimal(dev, target,
955 &clock,
956 best_clock,
957 bestppm, &ppm))
958 continue;
959
960 *best_clock = clock;
961 bestppm = ppm;
962 found = true1;
963 }
964 }
965 }
966 }
967
968 return found;
969}
970
971/*
972 * Returns a set of divisors for the desired target clock with the given
973 * refclk, or FALSE. The returned values represent the clock equation:
974 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
975 */
976static bool_Bool
977chv_find_best_dpll(const struct intel_limit *limit,
978 struct intel_crtc_state *crtc_state,
979 int target, int refclk, struct dpll *match_clock,
980 struct dpll *best_clock)
981{
982 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
983 struct drm_device *dev = crtc->base.dev;
984 unsigned int best_error_ppm;
985 struct dpll clock;
986 u64 m2;
987 int found = false0;
988
989 memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock)));
990 best_error_ppm = 1000000;
991
992 /*
993 * Based on hardware doc, the n always set to 1, and m1 always
994 * set to 2. If requires to support 200Mhz refclk, we need to
995 * revisit this because n may not 1 anymore.
996 */
997 clock.n = 1, clock.m1 = 2;
998 target *= 5; /* fast clock */
999
1000 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1001 for (clock.p2 = limit->p2.p2_fast;
1002 clock.p2 >= limit->p2.p2_slow;
1003 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1004 unsigned int error_ppm;
1005
1006 clock.p = clock.p1 * clock.p2;
1007
1008 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,(((mul_u32_u32(target, clock.p * clock.n) << 22) + ((refclk
* clock.m1) / 2)) / (refclk * clock.m1))
1009 refclk * clock.m1)(((mul_u32_u32(target, clock.p * clock.n) << 22) + ((refclk
* clock.m1) / 2)) / (refclk * clock.m1))
;
1010
1011 if (m2 > INT_MAX0x7fffffff/clock.m1)
1012 continue;
1013
1014 clock.m2 = m2;
1015
1016 chv_calc_dpll_params(refclk, &clock);
1017
1018 if (!intel_pll_is_valid(to_i915(dev), limit, &clock))
1019 continue;
1020
1021 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1022 best_error_ppm, &error_ppm))
1023 continue;
1024
1025 *best_clock = clock;
1026 best_error_ppm = error_ppm;
1027 found = true1;
1028 }
1029 }
1030
1031 return found;
1032}
1033
1034bool_Bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state,
1035 struct dpll *best_clock)
1036{
1037 int refclk = 100000;
1038 const struct intel_limit *limit = &intel_limits_bxt;
1039
1040 return chv_find_best_dpll(limit, crtc_state,
1041 crtc_state->port_clock, refclk,
1042 NULL((void *)0), best_clock);
1043}
1044
1045static bool_Bool pipe_scanline_is_moving(struct drm_i915_privateinteldrm_softc *dev_priv,
1046 enum pipe pipe)
1047{
1048 i915_reg_t reg = PIPEDSL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70000) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
;
1049 u32 line1, line2;
1050 u32 line_mask;
1051
1052 if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)))
1053 line_mask = DSL_LINEMASK_GEN20x00000fff;
1054 else
1055 line_mask = DSL_LINEMASK_GEN30x00001fff;
1056
1057 line1 = intel_de_read(dev_priv, reg) & line_mask;
1058 drm_msleep(5)mdelay(5);
1059 line2 = intel_de_read(dev_priv, reg) & line_mask;
1060
1061 return line1 != line2;
1062}
1063
1064static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool_Bool state)
1065{
1066 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1067 enum pipe pipe = crtc->pipe;
1068
1069 /* Wait for the display line to settle/start moving */
1070 if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll
* (((100) * 1000))); long wait__ = ((10)); int ret__; assertwaitok
(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw
(), end__); ; __asm volatile("" : : : "memory"); if (((pipe_scanline_is_moving
(dev_priv, pipe) == state))) { ret__ = 0; break; } if (expired__
) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if
(wait__ < ((1000))) wait__ <<= 1; } ret__; })
)
1071 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "pipe %c scanline %s wait timed out\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'), onoff(state))
1072 "pipe %c scanline %s wait timed out\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "pipe %c scanline %s wait timed out\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'), onoff(state))
1073 pipe_name(pipe), onoff(state))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "pipe %c scanline %s wait timed out\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'), onoff(state))
;
1074}
1075
1076static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc)
1077{
1078 wait_for_pipe_scanline_moving(crtc, false0);
1079}
1080
1081static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc)
1082{
1083 wait_for_pipe_scanline_moving(crtc, true1);
1084}
1085
1086static void
1087intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
1088{
1089 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
*)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1090 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1091
1092 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) {
1093 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1094 i915_reg_t reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)->
pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info
)->display_mmio_offset)) })
;
1095
1096 /* Wait for the Pipe State to go off */
1097 if (intel_de_wait_for_clear(dev_priv, reg,
1098 I965_PIPECONF_ACTIVE(1 << 30), 100))
1099 drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "pipe_off wait timed out\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect
(!!(__ret), 0); })
1100 "pipe_off wait timed out\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "pipe_off wait timed out\n"
, dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect
(!!(__ret), 0); })
;
1101 } else {
1102 intel_wait_for_pipe_scanline_stopped(crtc);
1103 }
1104}
1105
1106/* Only for pre-ILK configs */
1107void assert_pll(struct drm_i915_privateinteldrm_softc *dev_priv,
1108 enum pipe pipe, bool_Bool state)
1109{
1110 u32 val;
1111 bool_Bool cur_state;
1112
1113 val = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
);
1114 cur_state = !!(val & DPLL_VCO_ENABLE(1 << 31));
1115 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1116 "PLL state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1117 onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1118}
1119
1120/* XXX: the dsi pll is shared between MIPI DSI ports */
1121void assert_dsi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, bool_Bool state)
1122{
1123 u32 val;
1124 bool_Bool cur_state;
1125
1126 vlv_cck_get(dev_priv);
1127 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL0x48);
1128 vlv_cck_put(dev_priv);
1129
1130 cur_state = val & DSI_PLL_VCO_EN(1 << 31);
1131 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("DSI PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("DSI PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1132 "DSI PLL state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("DSI PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("DSI PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1133 onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("DSI PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("DSI PLL state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1134}
1135
1136static void assert_fdi_tx(struct drm_i915_privateinteldrm_softc *dev_priv,
1137 enum pipe pipe, bool_Bool state)
1138{
1139 bool_Bool cur_state;
1140
1141 if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) {
1142 /*
1143 * DDI does not have a specific FDI_TX register.
1144 *
1145 * FDI is never fed from EDP transcoder
1146 * so pipe->transcoder cast is fine here.
1147 */
1148 enum transcoder cpu_transcoder = (enum transcoder)pipe;
1149 u32 val = intel_de_read(dev_priv,
1150 TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info
)->trans_offsets[TRANSCODER_A] + (0x60400) + ((&(dev_priv
)->__info)->display_mmio_offset))) })
);
1151 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE(1 << 31));
1152 } else {
1153 u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
);
1154 cur_state = !!(val & FDI_TX_ENABLE(1 << 31));
1155 }
1156 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI TX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI TX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1157 "FDI TX state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI TX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI TX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1158 onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI TX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI TX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1159}
1160#define assert_fdi_tx_enabled(d, p)assert_fdi_tx(d, p, 1) assert_fdi_tx(d, p, true1)
1161#define assert_fdi_tx_disabled(d, p)assert_fdi_tx(d, p, 0) assert_fdi_tx(d, p, false0)
1162
1163static void assert_fdi_rx(struct drm_i915_privateinteldrm_softc *dev_priv,
1164 enum pipe pipe, bool_Bool state)
1165{
1166 u32 val;
1167 bool_Bool cur_state;
1168
1169 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
);
1170 cur_state = !!(val & FDI_RX_ENABLE(1 << 31));
1171 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI RX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI RX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1172 "FDI RX state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI RX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI RX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1173 onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI RX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI RX state assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1174}
1175#define assert_fdi_rx_enabled(d, p)assert_fdi_rx(d, p, 1) assert_fdi_rx(d, p, true1)
1176#define assert_fdi_rx_disabled(d, p)assert_fdi_rx(d, p, 0) assert_fdi_rx(d, p, false0)
1177
1178static void assert_fdi_tx_pll_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1179 enum pipe pipe)
1180{
1181 u32 val;
1182
1183 /* ILK FDI PLL is always enabled */
1184 if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5)))
1185 return;
1186
1187 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1188 if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi))
1189 return;
1190
1191 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
);
1192 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n")({ int __ret_warn_on = !!(!(val & (1 << 14))); if (
__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !
!(i915_modparams.verbose_state_checks); if (__ret) printf("FDI TX PLL assertion failure, should be active but is disabled\n"
); __builtin_expect(!!(__ret), 0); })) __drm_err("FDI TX PLL assertion failure, should be active but is disabled\n"
); __builtin_expect(!!(__ret_warn_on), 0); })
;
1193}
1194
1195void assert_fdi_rx_pll(struct drm_i915_privateinteldrm_softc *dev_priv,
1196 enum pipe pipe, bool_Bool state)
1197{
1198 u32 val;
1199 bool_Bool cur_state;
1200
1201 val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
);
1202 cur_state = !!(val & FDI_RX_PLL_ENABLE(1 << 13));
1203 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI RX PLL assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI RX PLL assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1204 "FDI RX PLL assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI RX PLL assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI RX PLL assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
1205 onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("FDI RX PLL assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret)
, 0); })) __drm_err("FDI RX PLL assertion failure (expected %s, current %s)\n"
, onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1206}
1207
1208void assert_panel_unlocked(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe)
1209{
1210 i915_reg_t pp_reg;
1211 u32 val;
1212 enum pipe panel_pipe = INVALID_PIPE;
1213 bool_Bool locked = true1;
1214
1215 if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))({ int __ret = !!((((&(dev_priv)->__info)->display.
has_ddi))); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__info)->display.has_ddi)"
")"); __builtin_expect(!!(__ret), 0); })
)
1216 return;
1217
1218 if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) {
1219 u32 port_sel;
1220
1221 pp_reg = PP_CONTROL(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61204) + (0) * 0x100) })
;
1222 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61208) + (0) * 0x100) })
) & PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))
;
1223
1224 switch (port_sel) {
1225 case PANEL_PORT_SELECT_LVDS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
:
1226 intel_lvds_port_enabled(dev_priv, PCH_LVDS((const i915_reg_t){ .reg = (0xe1180) }), &panel_pipe);
1227 break;
1228 case PANEL_PORT_SELECT_DPA((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(1) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
:
1229 intel_dp_port_enabled(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), PORT_A, &panel_pipe);
1230 break;
1231 case PANEL_PORT_SELECT_DPC((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(2) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
:
1232 intel_dp_port_enabled(dev_priv, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) }), PORT_C, &panel_pipe);
1233 break;
1234 case PANEL_PORT_SELECT_DPD((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (30))) + 0))))(3) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0
))
:
1235 intel_dp_port_enabled(dev_priv, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) }), PORT_D, &panel_pipe);
1236 break;
1237 default:
1238 MISSING_CASE(port_sel)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "port_sel", (long)(port_sel)); __builtin_expect(!!(__ret), 0
); })
;
1239 break;
1240 }
1241 } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) {
1242 /* presumably write lock depends on pipe, not port select */
1243 pp_reg = PP_CONTROL(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61204) + (pipe) * 0x100) })
;
1244 panel_pipe = pipe;
1245 } else {
1246 u32 port_sel;
1247
1248 pp_reg = PP_CONTROL(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61204) + (0) * 0x100) })
;
1249 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200
+ (0x61208) + (0) * 0x100) })
) & PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0))
;
1250
1251 drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((port_sel != ((u32)((((typeof(((u32)((((~0UL
) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0
))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64
- (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) &
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0)))) + 0 + 0 + 0 + 0)))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "port_sel != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0))"
")"); __builtin_expect(!!(__ret), 0); })
1252 port_sel != PANEL_PORT_SELECT_LVDS)({ int __ret = !!((port_sel != ((u32)((((typeof(((u32)((((~0UL
) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0
))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64
- (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) &
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(30))) + 0)))) + 0 + 0 + 0 + 0)))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "port_sel != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0))"
")"); __builtin_expect(!!(__ret), 0); })
;
1253 intel_lvds_port_enabled(dev_priv, LVDS((const i915_reg_t){ .reg = (0x61180) }), &panel_pipe);
1254 }
1255
1256 val = intel_de_read(dev_priv, pp_reg);
1257 if (!(val & PANEL_POWER_ON((u32)((1UL << (0)) + 0))) ||
1258 ((val & PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0))
) == PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) &
((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll
(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) <<
(16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31
) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0
))
))
1259 locked = false0;
1260
1261 I915_STATE_WARN(panel_pipe == pipe && locked,({ int __ret_warn_on = !!(panel_pipe == pipe && locked
); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A'
)); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1262 "panel assertion failure, pipe %c regs locked\n",({ int __ret_warn_on = !!(panel_pipe == pipe && locked
); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A'
)); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1263 pipe_name(pipe))({ int __ret_warn_on = !!(panel_pipe == pipe && locked
); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A'
)); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
;
1264}
1265
1266void assert_pipe(struct drm_i915_privateinteldrm_softc *dev_priv,
1267 enum transcoder cpu_transcoder, bool_Bool state)
1268{
1269 bool_Bool cur_state;
1270 enum intel_display_power_domain power_domain;
1271 intel_wakeref_t wakeref;
1272
1273 /* we keep both pipes enabled on 830 */
1274 if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830))
1275 state = true1;
1276
1277 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP
: (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A)
;
1278 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
1279 if (wakeref) {
1280 u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)->
pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info
)->display_mmio_offset)) })
);
1281 cur_state = !!(val & PIPECONF_ENABLE(1 << 31));
1282
1283 intel_display_power_put(dev_priv, power_domain, wakeref);
1284 } else {
1285 cur_state = false0;
1286 }
1287
1288 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret_warn_on), 0); })
1289 "transcoder %s assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret_warn_on), 0); })
1290 transcoder_name(cpu_transcoder),({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret_warn_on), 0); })
1291 onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n"
, transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state
)); __builtin_expect(!!(__ret_warn_on), 0); })
;
1292}
1293
1294static void assert_plane(struct intel_plane *plane, bool_Bool state)
1295{
1296 enum pipe pipe;
1297 bool_Bool cur_state;
1298
1299 cur_state = plane->get_hw_state(plane, &pipe);
1300
1301 I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n"
, plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n"
, plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret_warn_on), 0); })
1302 "%s assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n"
, plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n"
, plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret_warn_on), 0); })
1303 plane->base.name, onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n"
, plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n"
, plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect
(!!(__ret_warn_on), 0); })
;
1304}
1305
1306#define assert_plane_enabled(p)assert_plane(p, 1) assert_plane(p, true1)
1307#define assert_plane_disabled(p)assert_plane(p, 0) assert_plane(p, false0)
1308
1309static void assert_planes_disabled(struct intel_crtc *crtc)
1310{
1311 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1312 struct intel_plane *plane;
1313
1314 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base
.head ) *__mptr = ((&(&dev_priv->drm)->mode_config
.plane_list)->next); (__typeof(*plane) *)( (char *)__mptr -
__builtin_offsetof(__typeof(*plane), base.head) );}); &plane
->base.head != (&(&dev_priv->drm)->mode_config
.plane_list); plane = ({ const __typeof( ((__typeof(*plane) *
)0)->base.head ) *__mptr = (plane->base.head.next); (__typeof
(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane
), base.head) );})) if (!((plane)->pipe == (crtc)->pipe
)) {} else
1315 assert_plane_disabled(plane)assert_plane(plane, 0);
1316}
1317
1318static void assert_vblank_disabled(struct drm_crtc *crtc)
1319{
1320 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)({ int __ret_warn_on = !!((drm_crtc_vblank_get(crtc) == 0)); if
(__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret =
!!(i915_modparams.verbose_state_checks); if (__ret) printf("%s"
, "WARN_ON(" "drm_crtc_vblank_get(crtc) == 0" ")"); __builtin_expect
(!!(__ret), 0); })) __drm_err("%s", "WARN_ON(" "drm_crtc_vblank_get(crtc) == 0"
")"); __builtin_expect(!!(__ret_warn_on), 0); })
)
1321 drm_crtc_vblank_put(crtc);
1322}
1323
1324void assert_pch_transcoder_disabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1325 enum pipe pipe)
1326{
1327 u32 val;
1328 bool_Bool enabled;
1329
1330 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008)
- (0xf0008)))) })
);
1331 enabled = !!(val & TRANS_ENABLE(1 << 31));
1332 I915_STATE_WARN(enabled,({ int __ret_warn_on = !!(enabled); if (__builtin_expect(!!(__ret_warn_on
), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("transcoder assertion failed, should be off on pipe %c but is still active\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("transcoder assertion failed, should be off on pipe %c but is still active\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1333 "transcoder assertion failed, should be off on pipe %c but is still active\n",({ int __ret_warn_on = !!(enabled); if (__builtin_expect(!!(__ret_warn_on
), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("transcoder assertion failed, should be off on pipe %c but is still active\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("transcoder assertion failed, should be off on pipe %c but is still active\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1334 pipe_name(pipe))({ int __ret_warn_on = !!(enabled); if (__builtin_expect(!!(__ret_warn_on
), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("transcoder assertion failed, should be off on pipe %c but is still active\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("transcoder assertion failed, should be off on pipe %c but is still active\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
;
1335}
1336
1337static void assert_pch_dp_disabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1338 enum pipe pipe, enum port port,
1339 i915_reg_t dp_reg)
1340{
1341 enum pipe port_pipe;
1342 bool_Bool state;
1343
1344 state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe);
1345
1346 I915_STATE_WARN(state && port_pipe == pipe,({ int __ret_warn_on = !!(state && port_pipe == pipe)
; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("PCH DP %c enabled on transcoder %c, should be disabled\n", (
(port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret), 0
); })) __drm_err("PCH DP %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on
), 0); })
1347 "PCH DP %c enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(state && port_pipe == pipe)
; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("PCH DP %c enabled on transcoder %c, should be disabled\n", (
(port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret), 0
); })) __drm_err("PCH DP %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on
), 0); })
1348 port_name(port), pipe_name(pipe))({ int __ret_warn_on = !!(state && port_pipe == pipe)
; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("PCH DP %c enabled on transcoder %c, should be disabled\n", (
(port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret), 0
); })) __drm_err("PCH DP %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1349
1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX
) && !state && port_pipe == PIPE_B); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("IBX PCH DP %c still using transcoder B\n"
, ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("IBX PCH DP %c still using transcoder B\n", ((port) + 'A'));
__builtin_expect(!!(__ret_warn_on), 0); })
1351 "IBX PCH DP %c still using transcoder B\n",({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX
) && !state && port_pipe == PIPE_B); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("IBX PCH DP %c still using transcoder B\n"
, ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("IBX PCH DP %c still using transcoder B\n", ((port) + 'A'));
__builtin_expect(!!(__ret_warn_on), 0); })
1352 port_name(port))({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX
) && !state && port_pipe == PIPE_B); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("IBX PCH DP %c still using transcoder B\n"
, ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("IBX PCH DP %c still using transcoder B\n", ((port) + 'A'));
__builtin_expect(!!(__ret_warn_on), 0); })
;
1353}
1354
1355static void assert_pch_hdmi_disabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1356 enum pipe pipe, enum port port,
1357 i915_reg_t hdmi_reg)
1358{
1359 enum pipe port_pipe;
1360 bool_Bool state;
1361
1362 state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe);
1363
1364 I915_STATE_WARN(state && port_pipe == pipe,({ int __ret_warn_on = !!(state && port_pipe == pipe)
; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("PCH HDMI %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret)
, 0); })) __drm_err("PCH HDMI %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on
), 0); })
1365 "PCH HDMI %c enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(state && port_pipe == pipe)
; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("PCH HDMI %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret)
, 0); })) __drm_err("PCH HDMI %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on
), 0); })
1366 port_name(port), pipe_name(pipe))({ int __ret_warn_on = !!(state && port_pipe == pipe)
; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret
= !!(i915_modparams.verbose_state_checks); if (__ret) printf
("PCH HDMI %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret)
, 0); })) __drm_err("PCH HDMI %c enabled on transcoder %c, should be disabled\n"
, ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on
), 0); })
;
1367
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX
) && !state && port_pipe == PIPE_B); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("IBX PCH HDMI %c still using transcoder B\n"
, ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("IBX PCH HDMI %c still using transcoder B\n", ((port) + 'A')
); __builtin_expect(!!(__ret_warn_on), 0); })
1369 "IBX PCH HDMI %c still using transcoder B\n",({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX
) && !state && port_pipe == PIPE_B); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("IBX PCH HDMI %c still using transcoder B\n"
, ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("IBX PCH HDMI %c still using transcoder B\n", ((port) + 'A')
); __builtin_expect(!!(__ret_warn_on), 0); })
1370 port_name(port))({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX
) && !state && port_pipe == PIPE_B); if (__builtin_expect
(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams
.verbose_state_checks); if (__ret) printf("IBX PCH HDMI %c still using transcoder B\n"
, ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("IBX PCH HDMI %c still using transcoder B\n", ((port) + 'A')
); __builtin_expect(!!(__ret_warn_on), 0); })
;
1371}
1372
1373static void assert_pch_ports_disabled(struct drm_i915_privateinteldrm_softc *dev_priv,
1374 enum pipe pipe)
1375{
1376 enum pipe port_pipe;
1377
1378 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B((const i915_reg_t){ .reg = (0xe4100) }));
1379 assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) }));
1380 assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) }));
1381
1382 I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, ((
const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH VGA enabled on transcoder %c, should be disabled\n", ((
pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1383 port_pipe == pipe,({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, ((
const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH VGA enabled on transcoder %c, should be disabled\n", ((
pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1384 "PCH VGA enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, ((
const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH VGA enabled on transcoder %c, should be disabled\n", ((
pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1385 pipe_name(pipe))({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, ((
const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH VGA enabled on transcoder %c, should be disabled\n", ((
pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
;
1386
1387 I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, (
(const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH LVDS enabled on transcoder %c, should be disabled\n", (
(pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1388 port_pipe == pipe,({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, (
(const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH LVDS enabled on transcoder %c, should be disabled\n", (
(pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1389 "PCH LVDS enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, (
(const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH LVDS enabled on transcoder %c, should be disabled\n", (
(pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
1390 pipe_name(pipe))({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, (
(const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) &&
port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0
)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks
); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n"
, ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err
("PCH LVDS enabled on transcoder %c, should be disabled\n", (
(pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); })
;
1391
1392 /* PCH SDVOB multiplex with HDMIB */
1393 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB((const i915_reg_t){ .reg = (0xe1140) }));
1394 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC((const i915_reg_t){ .reg = (0xe1150) }));
1395 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID((const i915_reg_t){ .reg = (0xe1160) }));
1396}
1397
1398static void _vlv_enable_pll(struct intel_crtc *crtc,
1399 const struct intel_crtc_state *pipe_config)
1400{
1401 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1402 enum pipe pipe = crtc->pipe;
1403
1404 intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, pipe_config->dpll_hw_state.dpll);
1405 intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
);
1406 udelay(150);
1407
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, DPLL_LOCK_VLV(1 << 15), 1))
1409 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DPLL %d failed to lock\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , pipe)
;
1410}
1411
1412static void vlv_enable_pll(struct intel_crtc *crtc,
1413 const struct intel_crtc_state *pipe_config)
1414{
1415 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1416 enum pipe pipe = crtc->pipe;
1417
1418 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)assert_pipe(dev_priv, pipe_config->cpu_transcoder, 0);
1419
1420 /* PLL is protected by panel, make sure we can write it */
1421 assert_panel_unlocked(dev_priv, pipe);
1422
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31))
1424 _vlv_enable_pll(crtc, pipe_config);
1425
1426 intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(pipe)]))
})
,
1427 pipe_config->dpll_hw_state.dpll_md);
1428 intel_de_posting_read(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(pipe)]))
})
);
1429}
1430
1431
1432static void _chv_enable_pll(struct intel_crtc *crtc,
1433 const struct intel_crtc_state *pipe_config)
1434{
1435 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1436 enum pipe pipe = crtc->pipe;
1437 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1438 u32 tmp;
1439
1440 vlv_dpio_get(dev_priv);
1441
1442 /* Enable back the 10bit clock to display controller */
1443 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))));
1444 tmp |= DPIO_DCLKP_EN(1 << 13);
1445 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), tmp);
1446
1447 vlv_dpio_put(dev_priv);
1448
1449 /*
1450 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1451 */
1452 udelay(1);
1453
1454 /* Enable PLL */
1455 intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, pipe_config->dpll_hw_state.dpll);
1456
1457 /* Check PLL is locked */
1458 if (intel_de_wait_for_set(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, DPLL_LOCK_VLV(1 << 15), 1))
1459 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d failed to lock\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , pipe)
;
1460}
1461
1462static void chv_enable_pll(struct intel_crtc *crtc,
1463 const struct intel_crtc_state *pipe_config)
1464{
1465 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1466 enum pipe pipe = crtc->pipe;
1467
1468 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)assert_pipe(dev_priv, pipe_config->cpu_transcoder, 0);
1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 assert_panel_unlocked(dev_priv, pipe);
1472
1473 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31))
1474 _chv_enable_pll(crtc, pipe_config);
1475
1476 if (pipe != PIPE_A) {
1477 /*
1478 * WaPixelRepeatModeFixForC0:chv
1479 *
1480 * DPLLCMD is AWOL. Use chicken bits to propagate
1481 * the value from DPLLBMD to either pipe B or C.
1482 */
1483 intel_de_write(dev_priv, CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }), CBR_DPLLBMD_PIPE(pipe)(1 << (7 + (pipe) * 11)));
1484 intel_de_write(dev_priv, DPLL_MD(PIPE_B)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(PIPE_B)]
)) })
,
1485 pipe_config->dpll_hw_state.dpll_md);
1486 intel_de_write(dev_priv, CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }), 0);
1487 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1488
1489 /*
1490 * DPLLB VGA mode also seems to cause problems.
1491 * We should always have it disabled.
1492 */
1493 drm_WARN_ON(&dev_priv->drm,({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->
display_mmio_offset) + 0x6014), (((&(dev_priv)->__info
)->display_mmio_offset) + 0x6018), (((&(dev_priv)->
__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) }))
& (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
"(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0"
")"); __builtin_expect(!!(__ret), 0); })
1494 (intel_de_read(dev_priv, DPLL(PIPE_B)) &({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->
display_mmio_offset) + 0x6014), (((&(dev_priv)->__info
)->display_mmio_offset) + 0x6018), (((&(dev_priv)->
__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) }))
& (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
"(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0"
")"); __builtin_expect(!!(__ret), 0); })
1495 DPLL_VGA_MODE_DIS) == 0)({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t
){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->
display_mmio_offset) + 0x6014), (((&(dev_priv)->__info
)->display_mmio_offset) + 0x6018), (((&(dev_priv)->
__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) }))
& (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
"(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0"
")"); __builtin_expect(!!(__ret), 0); })
;
1496 } else {
1497 intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(pipe)]))
})
,
1498 pipe_config->dpll_hw_state.dpll_md);
1499 intel_de_posting_read(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(pipe)]))
})
);
1500 }
1501}
1502
1503static bool_Bool i9xx_has_pps(struct drm_i915_privateinteldrm_softc *dev_priv)
1504{
1505 if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830))
1506 return false0;
1507
1508 return IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) || IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile);
1509}
1510
1511static void i9xx_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *crtc_state)
1513{
1514 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1515 i915_reg_t reg = DPLL(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(crtc->
pipe)])) })
;
1516 u32 dpll = crtc_state->dpll_hw_state.dpll;
1517 int i;
1518
1519 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 0);
1520
1521 /* PLL is protected by panel, make sure we can write it */
1522 if (i9xx_has_pps(dev_priv))
1523 assert_panel_unlocked(dev_priv, crtc->pipe);
1524
1525 /*
1526 * Apparently we need to have VGA mode enabled prior to changing
1527 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1528 * dividers, even though the register value does change.
1529 */
1530 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS(1 << 28));
1531 intel_de_write(dev_priv, reg, dpll);
1532
1533 /* Wait for the clocks to stabilize. */
1534 intel_de_posting_read(dev_priv, reg);
1535 udelay(150);
1536
1537 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) {
1538 intel_de_write(dev_priv, DPLL_MD(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x603c) })[(crtc->
pipe)])) })
,
1539 crtc_state->dpll_hw_state.dpll_md);
1540 } else {
1541 /* The pixel multiplier can only be updated once the
1542 * DPLL is enabled and the clocks are stable.
1543 *
1544 * So write it again.
1545 */
1546 intel_de_write(dev_priv, reg, dpll);
1547 }
1548
1549 /* We do this three times for luck */
1550 for (i = 0; i < 3; i++) {
1551 intel_de_write(dev_priv, reg, dpll);
1552 intel_de_posting_read(dev_priv, reg);
1553 udelay(150); /* wait for warmup */
1554 }
1555}
1556
1557static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state)
1558{
1559 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1560 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1561 enum pipe pipe = crtc->pipe;
1562
1563 /* Don't disable pipe or pipe PLLs if needed */
1564 if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830))
1565 return;
1566
1567 /* Make sure the pipe isn't still relying on us */
1568 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 0);
1569
1570 intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, DPLL_VGA_MODE_DIS(1 << 28));
1571 intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
);
1572}
1573
1574static void vlv_disable_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe)
1575{
1576 u32 val;
1577
1578 /* Make sure the pipe isn't still relying on us */
1579 assert_pipe_disabled(dev_priv, (enum transcoder)pipe)assert_pipe(dev_priv, (enum transcoder)pipe, 0);
1580
1581 val = DPLL_INTEGRATED_REF_CLK_VLV(1 << 13) |
1582 DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28);
1583 if (pipe != PIPE_A)
1584 val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14);
1585
1586 intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, val);
1587 intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
);
1588}
1589
1590static void chv_disable_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe)
1591{
1592 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1593 u32 val;
1594
1595 /* Make sure the pipe isn't still relying on us */
1596 assert_pipe_disabled(dev_priv, (enum transcoder)pipe)assert_pipe(dev_priv, (enum transcoder)pipe, 0);
1597
1598 val = DPLL_SSC_REF_CLK_CHV(1 << 13) |
1599 DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28);
1600 if (pipe != PIPE_A)
1601 val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14);
1602
1603 intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
, val);
1604 intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(pipe)]))
})
);
1605
1606 vlv_dpio_get(dev_priv);
1607
1608 /* Disable 10bit clock to display controller */
1609 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))));
1610 val &= ~DPIO_DCLKP_EN(1 << 13);
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), val);
1612
1613 vlv_dpio_put(dev_priv);
1614}
1615
1616void vlv_wait_port_ready(struct drm_i915_privateinteldrm_softc *dev_priv,
1617 struct intel_digital_port *dig_port,
1618 unsigned int expected_mask)
1619{
1620 u32 port_mask;
1621 i915_reg_t dpll_reg;
1622
1623 switch (dig_port->base.port) {
1624 case PORT_B:
1625 port_mask = DPLL_PORTB_READY_MASK(0xf);
1626 dpll_reg = DPLL(0)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(0)])) })
;
1627 break;
1628 case PORT_C:
1629 port_mask = DPLL_PORTC_READY_MASK(0xf << 4);
1630 dpll_reg = DPLL(0)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv
)->__info)->display_mmio_offset) + 0x6030) })[(0)])) })
;
1631 expected_mask <<= 4;
1632 break;
1633 case PORT_D:
1634 port_mask = DPLL_PORTD_READY_MASK(0xf);
1635 dpll_reg = DPIO_PHY_STATUS((const i915_reg_t){ .reg = (0x180000 + 0x6240) });
1636 break;
1637 default:
1638 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c"
, 1638); } while (0)
;
1639 }
1640
1641 if (intel_de_wait_for_register(dev_priv, dpll_reg,
1642 port_mask, expected_mask, 1000))
1643 drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n"
, dev_driver_string((&dev_priv->drm)->dev), "", dig_port
->base.base.base.id, dig_port->base.base.name, intel_de_read
(dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect
(!!(__ret), 0); })
1644 "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n"
, dev_driver_string((&dev_priv->drm)->dev), "", dig_port
->base.base.base.id, dig_port->base.base.name, intel_de_read
(dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect
(!!(__ret), 0); })
1645 dig_port->base.base.base.id, dig_port->base.base.name,({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n"
, dev_driver_string((&dev_priv->drm)->dev), "", dig_port
->base.base.base.id, dig_port->base.base.name, intel_de_read
(dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect
(!!(__ret), 0); })
1646 intel_de_read(dev_priv, dpll_reg) & port_mask,({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n"
, dev_driver_string((&dev_priv->drm)->dev), "", dig_port
->base.base.base.id, dig_port->base.base.name, intel_de_read
(dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect
(!!(__ret), 0); })
1647 expected_mask)({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n"
, dev_driver_string((&dev_priv->drm)->dev), "", dig_port
->base.base.base.id, dig_port->base.base.name, intel_de_read
(dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect
(!!(__ret), 0); })
;
1648}
1649
1650static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
1651{
1652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1653 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1654 enum pipe pipe = crtc->pipe;
1655 i915_reg_t reg;
1656 u32 val, pipeconf_val;
1657
1658 /* Make sure PCH DPLL is enabled */
1659 assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll)assert_shared_dpll(dev_priv, crtc_state->shared_dpll, 1);
1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe)assert_fdi_tx(dev_priv, pipe, 1);
1663 assert_fdi_rx_enabled(dev_priv, pipe)assert_fdi_rx(dev_priv, pipe, 1);
1664
1665 if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) {
1666 reg = TRANS_CHICKEN2(pipe)((const i915_reg_t){ .reg = (((0xf0064) + (pipe) * ((0xf1064)
- (0xf0064)))) })
;
1667 val = intel_de_read(dev_priv, reg);
1668 /*
1669 * Workaround: Set the timing override bit
1670 * before enabling the pch transcoder.
1671 */
1672 val |= TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31);
1673 /* Configure frame start delay to match the CPU */
1674 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK(3 << 27);
1675 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0)((0) << 27);
1676 intel_de_write(dev_priv, reg, val);
1677 }
1678
1679 reg = PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008)
- (0xf0008)))) })
;
1680 val = intel_de_read(dev_priv, reg);
1681 pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
);
1682
1683 if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) {
1684 /* Configure frame start delay to match the CPU */
1685 val &= ~TRANS_FRAME_START_DELAY_MASK(3 << 27);
1686 val |= TRANS_FRAME_START_DELAY(0)((0) << 27);
1687
1688 /*
1689 * Make the BPC in transcoder be consistent with
1690 * that in pipeconf reg. For HDMI we must use 8bpc
1691 * here for both 8bpc and 12bpc.
1692 */
1693 val &= ~PIPECONF_BPC_MASK(0x7 << 5);
1694 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1695 val |= PIPECONF_8BPC(0 << 5);
1696 else
1697 val |= pipeconf_val & PIPECONF_BPC_MASK(0x7 << 5);
1698 }
1699
1700 val &= ~TRANS_INTERLACE_MASK(7 << 21);
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK(7 << 21)) == PIPECONF_INTERLACED_ILK(3 << 21)) {
1702 if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) &&
1703 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK(2 << 21);
1705 else
1706 val |= TRANS_INTERLACED(3 << 21);
1707 } else {
1708 val |= TRANS_PROGRESSIVE(0 << 21);
1709 }
1710
1711 intel_de_write(dev_priv, reg, val | TRANS_ENABLE(1 << 31));
1712 if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE(1 << 30), 100))
1713 drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to enable transcoder %c\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'))
1714 pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to enable transcoder %c\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'))
;
1715}
1716
1717static void lpt_enable_pch_transcoder(struct drm_i915_privateinteldrm_softc *dev_priv,
1718 enum transcoder cpu_transcoder)
1719{
1720 u32 val, pipeconf_val;
1721
1722 /* FDI must be feeding us bits for PCH ports */
1723 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder)assert_fdi_tx(dev_priv, (enum pipe) cpu_transcoder, 1);
1724 assert_fdi_rx_enabled(dev_priv, PIPE_A)assert_fdi_rx(dev_priv, PIPE_A, 1);
1725
1726 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064
) - (0xf0064)))) })
);
1727 /* Workaround: set timing override bit. */
1728 val |= TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31);
1729 /* Configure frame start delay to match the CPU */
1730 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK(3 << 27);
1731 val |= TRANS_CHICKEN2_FRAME_START_DELAY(0)((0) << 27);
1732 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064
) - (0xf0064)))) })
, val);
1733
1734 val = TRANS_ENABLE(1 << 31);
1735 pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)->
pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info
)->display_mmio_offset)) })
);
1736
1737 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW(3 << 21)) ==
1738 PIPECONF_INTERLACED_ILK(3 << 21))
1739 val |= TRANS_INTERLACED(3 << 21);
1740 else
1741 val |= TRANS_PROGRESSIVE(0 << 21);
1742
1743 intel_de_write(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) })
, val);
1744 if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) })
,
1745 TRANS_STATE_ENABLE(1 << 30), 100))
1746 drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to enable PCH transcoder\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1747}
1748
1749static void ilk_disable_pch_transcoder(struct drm_i915_privateinteldrm_softc *dev_priv,
1750 enum pipe pipe)
1751{
1752 i915_reg_t reg;
1753 u32 val;
1754
1755 /* FDI relies on the transcoder */
1756 assert_fdi_tx_disabled(dev_priv, pipe)assert_fdi_tx(dev_priv, pipe, 0);
1757 assert_fdi_rx_disabled(dev_priv, pipe)assert_fdi_rx(dev_priv, pipe, 0);
1758
1759 /* Ports must be off as well */
1760 assert_pch_ports_disabled(dev_priv, pipe);
1761
1762 reg = PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008)
- (0xf0008)))) })
;
1763 val = intel_de_read(dev_priv, reg);
1764 val &= ~TRANS_ENABLE(1 << 31);
1765 intel_de_write(dev_priv, reg, val);
1766 /* wait for PCH transcoder off, transcoder state */
1767 if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE(1 << 30), 50))
1768 drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to disable transcoder %c\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'))
1769 pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to disable transcoder %c\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe
) + 'A'))
;
1770
1771 if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) {
1772 /* Workaround: Clear the timing override chicken bit again. */
1773 reg = TRANS_CHICKEN2(pipe)((const i915_reg_t){ .reg = (((0xf0064) + (pipe) * ((0xf1064)
- (0xf0064)))) })
;
1774 val = intel_de_read(dev_priv, reg);
1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31);
1776 intel_de_write(dev_priv, reg, val);
1777 }
1778}
1779
1780void lpt_disable_pch_transcoder(struct drm_i915_privateinteldrm_softc *dev_priv)
1781{
1782 u32 val;
1783
1784 val = intel_de_read(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) })
);
1785 val &= ~TRANS_ENABLE(1 << 31);
1786 intel_de_write(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) })
, val);
1787 /* wait for PCH transcoder off, transcoder state */
1788 if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008
) - (0xf0008)))) })
,
1789 TRANS_STATE_ENABLE(1 << 30), 50))
1790 drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to disable PCH transcoder\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1791
1792 /* Workaround: clear timing override bit. */
1793 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064
) - (0xf0064)))) })
);
1794 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31);
1795 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064
) - (0xf0064)))) })
, val);
1796}
1797
1798enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1799{
1800 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1801
1802 if (HAS_PCH_LPT(dev_priv)(((dev_priv)->pch_type) == PCH_LPT))
1803 return PIPE_A;
1804 else
1805 return crtc->pipe;
1806}
1807
1808static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state)
1809{
1810 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1811
1812 /*
1813 * On i965gm the hardware frame counter reads
1814 * zero when the TV encoder is enabled :(
1815 */
1816 if (IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) &&
1817 (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)(1UL << (INTEL_OUTPUT_TVOUT))))
1818 return 0;
1819
1820 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45
))
)
1821 return 0xffffffff; /* full 32 bit counter */
1822 else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 3)
1823 return 0xffffff; /* only 24 bits of frame count */
1824 else
1825 return 0; /* Gen2 doesn't have a hardware frame counter */
1826}
1827
1828void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
1829{
1830 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1831
1832 assert_vblank_disabled(&crtc->base);
1833 drm_crtc_set_max_vblank_count(&crtc->base,
1834 intel_crtc_max_vblank_count(crtc_state));
1835 drm_crtc_vblank_on(&crtc->base);
1836}
1837
1838void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state)
1839{
1840 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1841
1842 drm_crtc_vblank_off(&crtc->base);
1843 assert_vblank_disabled(&crtc->base);
1844}
1845
1846void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
1847{
1848 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
*)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1849 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1850 enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1851 enum pipe pipe = crtc->pipe;
1852 i915_reg_t reg;
1853 u32 val;
1854
1855 drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling pipe %c\n"
, ((pipe) + 'A'))
;
1856
1857 assert_planes_disabled(crtc);
1858
1859 /*
1860 * A pipe without a PLL won't actually be able to drive bits from
1861 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1862 * need the check.
1863 */
1864 if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) {
1865 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
1866 assert_dsi_pll_enabled(dev_priv)assert_dsi_pll(dev_priv, 1);
1867 else
1868 assert_pll_enabled(dev_priv, pipe)assert_pll(dev_priv, pipe, 1);
1869 } else {
1870 if (new_crtc_state->has_pch_encoder) {
1871 /* if driving the PCH, we need FDI enabled */
1872 assert_fdi_rx_pll_enabled(dev_priv,assert_fdi_rx_pll(dev_priv, intel_crtc_pch_transcoder(crtc), 1
)
1873 intel_crtc_pch_transcoder(crtc))assert_fdi_rx_pll(dev_priv, intel_crtc_pch_transcoder(crtc), 1
)
;
1874 assert_fdi_tx_pll_enabled(dev_priv,
1875 (enum pipe) cpu_transcoder);
1876 }
1877 /* FIXME: assert CPU port conditions for SNB+ */
1878 }
1879
1880 trace_intel_pipe_enable(crtc);
1881
1882 reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)->
pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info
)->display_mmio_offset)) })
;
1883 val = intel_de_read(dev_priv, reg);
1884 if (val & PIPECONF_ENABLE(1 << 31)) {
1885 /* we keep both pipes enabled on 830 */
1886 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv))({ int __ret = !!((!IS_PLATFORM(dev_priv, INTEL_I830))); if (
__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "!IS_PLATFORM(dev_priv, INTEL_I830)"
")"); __builtin_expect(!!(__ret), 0); })
;
1887 return;
1888 }
1889
1890 intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE(1 << 31));
1891 intel_de_posting_read(dev_priv, reg);
1892
1893 /*
1894 * Until the pipe starts PIPEDSL reads will return a stale value,
1895 * which causes an apparent vblank timestamp jump when PIPEDSL
1896 * resets to its proper value. That also messes up the frame count
1897 * when it's derived from the timestamps. So let's wait for the
1898 * pipe to start properly before we call drm_crtc_vblank_on()
1899 */
1900 if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
1901 intel_wait_for_pipe_scanline_moving(crtc);
1902}
1903
1904void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state)
1905{
1906 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
*)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1907 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
1908 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
1909 enum pipe pipe = crtc->pipe;
1910 i915_reg_t reg;
1911 u32 val;
1912
1913 drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling pipe %c\n"
, ((pipe) + 'A'))
;
1914
1915 /*
1916 * Make sure planes won't keep trying to pump pixels to us,
1917 * or we might hang the display.
1918 */
1919 assert_planes_disabled(crtc);
1920
1921 trace_intel_pipe_disable(crtc);
1922
1923 reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)->
pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info
)->display_mmio_offset)) })
;
1924 val = intel_de_read(dev_priv, reg);
1925 if ((val & PIPECONF_ENABLE(1 << 31)) == 0)
1926 return;
1927
1928 /*
1929 * Double wide has implications for planes
1930 * so best keep it disabled when not needed.
1931 */
1932 if (old_crtc_state->double_wide)
1933 val &= ~PIPECONF_DOUBLE_WIDE(1 << 30);
1934
1935 /* Don't disable pipe or pipe PLLs if needed */
1936 if (!IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830))
1937 val &= ~PIPECONF_ENABLE(1 << 31);
1938
1939 intel_de_write(dev_priv, reg, val);
1940 if ((val & PIPECONF_ENABLE(1 << 31)) == 0)
1941 intel_wait_for_pipe_off(old_crtc_state);
1942}
1943
1944static unsigned int intel_tile_size(const struct drm_i915_privateinteldrm_softc *dev_priv)
1945{
1946 return IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) ? 2048 : 4096;
1947}
1948
1949static bool_Bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
1950{
1951 if (!is_ccs_modifier(fb->modifier))
1952 return false0;
1953
1954 return plane >= fb->format->num_planes / 2;
1955}
1956
1957static bool_Bool is_gen12_ccs_modifier(u64 modifier)
1958{
1959 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
||
1960 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
;
1961
1962}
1963
1964static bool_Bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane)
1965{
1966 return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane);
1967}
1968
1969static bool_Bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
1970{
1971 if (is_ccs_modifier(fb->modifier))
1972 return is_ccs_plane(fb, plane);
1973
1974 return plane == 1;
1975}
1976
1977static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
1978{
1979 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||({ int __ret = !!((!is_ccs_modifier(fb->modifier) || (main_plane
&& main_plane >= fb->format->num_planes / 2
))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb
->dev))->dev), "", "drm_WARN_ON(" "!is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)"
")"); __builtin_expect(!!(__ret), 0); })
1980 (main_plane && main_plane >= fb->format->num_planes / 2))({ int __ret = !!((!is_ccs_modifier(fb->modifier) || (main_plane
&& main_plane >= fb->format->num_planes / 2
))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb
->dev))->dev), "", "drm_WARN_ON(" "!is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)"
")"); __builtin_expect(!!(__ret), 0); })
;
1981
1982 return fb->format->num_planes / 2 + main_plane;
1983}
1984
1985static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane)
1986{
1987 drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||({ int __ret = !!((!is_ccs_modifier(fb->modifier) || ccs_plane
< fb->format->num_planes / 2)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON("
"!is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2"
")"); __builtin_expect(!!(__ret), 0); })
1988 ccs_plane < fb->format->num_planes / 2)({ int __ret = !!((!is_ccs_modifier(fb->modifier) || ccs_plane
< fb->format->num_planes / 2)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON("
"!is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2"
")"); __builtin_expect(!!(__ret), 0); })
;
1989
1990 return ccs_plane - fb->format->num_planes / 2;
1991}
1992
1993/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
1994int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
1995{
1996 if (is_ccs_modifier(fb->modifier))
1997 return main_to_ccs_plane(fb, main_plane);
1998
1999 return 1;
2000}
2001
2002bool_Bool
2003intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
2004 uint64_t modifier)
2005{
2006 return info->is_yuv &&
2007 info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2);
2008}
2009
2010static bool_Bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb,
2011 int color_plane)
2012{
2013 return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
2014 color_plane == 1;
2015}
2016
2017static unsigned int
2018intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
2019{
2020 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev);
2021 unsigned int cpp = fb->format->cpp[color_plane];
2022
2023 switch (fb->modifier) {
2024 case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
:
2025 return intel_tile_size(dev_priv);
2026 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
2027 if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)))
2028 return 128;
2029 else
2030 return 512;
2031 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
2032 if (is_ccs_plane(fb, color_plane))
2033 return 128;
2034 fallthroughdo {} while (0);
2035 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
:
2036 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
:
2037 if (is_ccs_plane(fb, color_plane))
2038 return 64;
2039 fallthroughdo {} while (0);
2040 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
2041 if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) || HAS_128_BYTE_Y_TILING(dev_priv)(!(0 + (&(dev_priv)->__info)->gen == (2)) &&
!(IS_PLATFORM(dev_priv, INTEL_I915G) || IS_PLATFORM(dev_priv
, INTEL_I915GM)))
)
2042 return 128;
2043 else
2044 return 512;
2045 case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
:
2046 if (is_ccs_plane(fb, color_plane))
2047 return 128;
2048 fallthroughdo {} while (0);
2049 case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL
))
:
2050 switch (cpp) {
2051 case 1:
2052 return 64;
2053 case 2:
2054 case 4:
2055 return 128;
2056 case 8:
2057 case 16:
2058 return 256;
2059 default:
2060 MISSING_CASE(cpp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "cpp", (long)(cpp)); __builtin_expect(!!(__ret), 0); })
;
2061 return cpp;
2062 }
2063 break;
2064 default:
2065 MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fb->modifier", (long)(fb->modifier)); __builtin_expect
(!!(__ret), 0); })
;
2066 return cpp;
2067 }
2068}
2069
2070static unsigned int
2071intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
2072{
2073 if (is_gen12_ccs_plane(fb, color_plane))
2074 return 1;
2075
2076 return intel_tile_size(to_i915(fb->dev)) /
2077 intel_tile_width_bytes(fb, color_plane);
2078}
2079
2080/* Return the tile dimensions in pixel units */
2081static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
2082 unsigned int *tile_width,
2083 unsigned int *tile_height)
2084{
2085 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
2086 unsigned int cpp = fb->format->cpp[color_plane];
2087
2088 *tile_width = tile_width_bytes / cpp;
2089 *tile_height = intel_tile_height(fb, color_plane);
2090}
2091
2092static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb,
2093 int color_plane)
2094{
2095 unsigned int tile_width, tile_height;
2096
2097 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2098
2099 return fb->pitches[color_plane] * tile_height;
2100}
2101
2102unsigned int
2103intel_fb_align_height(const struct drm_framebuffer *fb,
2104 int color_plane, unsigned int height)
2105{
2106 unsigned int tile_height = intel_tile_height(fb, color_plane);
2107
2108 return roundup2(height, tile_height)(((height) + ((tile_height) - 1)) & (~((__typeof(height))
(tile_height) - 1)))
;
2109}
2110
2111unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2112{
2113 unsigned int size = 0;
2114 int i;
2115
2116 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane)(sizeof((rot_info->plane)) / sizeof((rot_info->plane)[0
]))
; i++)
2117 size += rot_info->plane[i].width * rot_info->plane[i].height;
2118
2119 return size;
2120}
2121
2122unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
2123{
2124 unsigned int size = 0;
2125 int i;
2126
2127 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane)(sizeof((rem_info->plane)) / sizeof((rem_info->plane)[0
]))
; i++)
2128 size += rem_info->plane[i].width * rem_info->plane[i].height;
2129
2130 return size;
2131}
2132
2133static void
2134intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2135 const struct drm_framebuffer *fb,
2136 unsigned int rotation)
2137{
2138 view->type = I915_GGTT_VIEW_NORMAL;
2139 if (drm_rotation_90_or_270(rotation)) {
2140 view->type = I915_GGTT_VIEW_ROTATED;
2141 view->rotated = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
->rot_info;
2142 }
2143}
2144
2145static unsigned int intel_cursor_alignment(const struct drm_i915_privateinteldrm_softc *dev_priv)
2146{
2147 if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830))
2148 return 16 * 1024;
2149 else if (IS_I85X(dev_priv)IS_PLATFORM(dev_priv, INTEL_I85X))
2150 return 256;
2151 else if (IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G) || IS_I865G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I865G))
2152 return 32;
2153 else
2154 return 4 * 1024;
2155}
2156
2157static unsigned int intel_linear_alignment(const struct drm_i915_privateinteldrm_softc *dev_priv)
2158{
2159 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9)
2160 return 256 * 1024;
2161 else if (IS_I965G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965G) || IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) ||
2162 IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
2163 return 128 * 1024;
2164 else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
2165 return 4 * 1024;
2166 else
2167 return 0;
2168}
2169
2170static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2171 int color_plane)
2172{
2173 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev);
2174
2175 /* AUX_DIST needs only 4K alignment */
2176 if ((INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 12 && is_aux_plane(fb, color_plane)) ||
2177 is_ccs_plane(fb, color_plane))
2178 return 4096;
2179
2180 switch (fb->modifier) {
2181 case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
:
2182 return intel_linear_alignment(dev_priv);
2183 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
2184 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9)
2185 return 256 * 1024;
2186 return 0;
2187 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
:
2188 if (is_semiplanar_uv_plane(fb, color_plane))
2189 return intel_tile_row_size(fb, color_plane);
2190 fallthroughdo {} while (0);
2191 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
:
2192 return 16 * 1024;
2193 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
2194 case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
:
2195 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
2196 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 &&
2197 is_semiplanar_uv_plane(fb, color_plane))
2198 return intel_tile_row_size(fb, color_plane);
2199 fallthroughdo {} while (0);
2200 case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL
))
:
2201 return 1 * 1024 * 1024;
2202 default:
2203 MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fb->modifier", (long)(fb->modifier)); __builtin_expect
(!!(__ret), 0); })
;
2204 return 0;
2205 }
2206}
2207
2208static bool_Bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
2209{
2210 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (plane_state->uapi.plane); (struct intel_plane *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane, base) );})
;
2211 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
2212
2213 return INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4 ||
2214 (plane->has_fbc &&
2215 plane_state->view.type == I915_GGTT_VIEW_NORMAL);
2216}
2217
2218struct i915_vma *
2219intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2220 const struct i915_ggtt_view *view,
2221 bool_Bool uses_fence,
2222 unsigned long *out_flags)
2223{
2224 struct drm_device *dev = fb->dev;
2225 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
2226 struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0));
2227 intel_wakeref_t wakeref;
2228 struct i915_vma *vma;
2229 unsigned int pinctl;
2230 u32 alignment;
2231
2232 if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))({ int __ret = !!((!i915_gem_object_is_framebuffer(obj))); if
(__ret) printf("%s %s: " "%s", dev_driver_string(((dev))->
dev), "", "drm_WARN_ON(" "!i915_gem_object_is_framebuffer(obj)"
")"); __builtin_expect(!!(__ret), 0); })
)
2233 return ERR_PTR(-EINVAL22);
2234
2235 alignment = intel_surf_alignment(fb, 0);
2236 if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))({ int __ret = !!((alignment && !(((alignment) != 0) &&
(((alignment) - 1) & (alignment)) == 0))); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON("
"alignment && !(((alignment) != 0) && (((alignment) - 1) & (alignment)) == 0)"
")"); __builtin_expect(!!(__ret), 0); })
)
2237 return ERR_PTR(-EINVAL22);
2238
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2242 * the VT-d warning.
2243 */
2244 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2246
2247 /*
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2253 */
2254 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
2255
2256 atomic_inc(&dev_priv->gpu_error.pending_fb_pin)__sync_fetch_and_add(&dev_priv->gpu_error.pending_fb_pin
, 1)
;
2257
2258 /*
2259 * Valleyview is definitely limited to scanning out the first
2260 * 512MiB. Lets presume this behaviour was inherited from the
2261 * g4x display engine and that all earlier gen are similarly
2262 * limited. Testing suggests that it is a little more
2263 * complicated than this. For example, Cherryview appears quite
2264 * happy to scanout from anywhere within its global aperture.
2265 */
2266 pinctl = 0;
2267 if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch))
2268 pinctl |= PIN_MAPPABLE(1ULL << (3));
2269
2270 vma = i915_gem_object_pin_to_display_plane(obj,
2271 alignment, view, pinctl);
2272 if (IS_ERR(vma))
2273 goto err;
2274
2275 if (uses_fence && i915_vma_is_map_and_fenceable(vma)) {
2276 int ret;
2277
2278 /*
2279 * Install a fence for tiled scan-out. Pre-i965 always needs a
2280 * fence, whereas 965+ only requires a fence if using
2281 * framebuffer compression. For simplicity, we always, when
2282 * possible, install a fence as the cost is not that onerous.
2283 *
2284 * If we fail to fence the tiled scanout, then either the
2285 * modeset will reject the change (which is highly unlikely as
2286 * the affected systems, all but one, do not have unmappable
2287 * space) or we will not be able to enable full powersaving
2288 * techniques (also likely not to apply due to various limits
2289 * FBC and the like impose on the size of the buffer, which
2290 * presumably we violated anyway with this unmappable buffer).
2291 * Anyway, it is presumably better to stumble onwards with
2292 * something and try to run the system in a "less than optimal"
2293 * mode that matches the user configuration.
2294 */
2295 ret = i915_vma_pin_fence(vma);
2296 if (ret != 0 && INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) {
2297 i915_vma_unpin(vma);
2298 vma = ERR_PTR(ret);
2299 goto err;
2300 }
2301
2302 if (ret == 0 && vma->fence)
2303 *out_flags |= PLANE_HAS_FENCE(1UL << (0));
2304 }
2305
2306 i915_vma_get(vma);
2307err:
2308 atomic_dec(&dev_priv->gpu_error.pending_fb_pin)__sync_fetch_and_sub(&dev_priv->gpu_error.pending_fb_pin
, 1)
;
2309 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
2310 return vma;
2311}
2312
2313void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
2314{
2315 if (flags & PLANE_HAS_FENCE(1UL << (0)))
2316 i915_vma_unpin_fence(vma);
2317 i915_vma_unpin(vma);
2318 i915_vma_put(vma);
2319}
2320
2321static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
2322 unsigned int rotation)
2323{
2324 if (drm_rotation_90_or_270(rotation))
2325 return to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
->rotated[color_plane].pitch;
2326 else
2327 return fb->pitches[color_plane];
2328}
2329
2330/*
2331 * Convert the x/y offsets into a linear offset.
2332 * Only valid with 0/180 degree rotation, which is fine since linear
2333 * offset is only used with linear buffers on pre-hsw and tiled buffers
2334 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2335 */
2336u32 intel_fb_xy_to_linear(int x, int y,
2337 const struct intel_plane_state *state,
2338 int color_plane)
2339{
2340 const struct drm_framebuffer *fb = state->hw.fb;
2341 unsigned int cpp = fb->format->cpp[color_plane];
2342 unsigned int pitch = state->color_plane[color_plane].stride;
2343
2344 return y * pitch + x * cpp;
2345}
2346
2347/*
2348 * Add the x/y offsets derived from fb->offsets[] to the user
2349 * specified plane src x/y offsets. The resulting x/y offsets
2350 * specify the start of scanout from the beginning of the gtt mapping.
2351 */
2352void intel_add_fb_offsets(int *x, int *y,
2353 const struct intel_plane_state *state,
2354 int color_plane)
2355
2356{
2357 *x += state->color_plane[color_plane].x;
2358 *y += state->color_plane[color_plane].y;
2359}
2360
2361static u32 intel_adjust_tile_offset(int *x, int *y,
2362 unsigned int tile_width,
2363 unsigned int tile_height,
2364 unsigned int tile_size,
2365 unsigned int pitch_tiles,
2366 u32 old_offset,
2367 u32 new_offset)
2368{
2369 unsigned int pitch_pixels = pitch_tiles * tile_width;
2370 unsigned int tiles;
2371
2372 WARN_ON(old_offset & (tile_size - 1))({ int __ret = !!((old_offset & (tile_size - 1))); if (__ret
) printf("%s", "WARN_ON(" "old_offset & (tile_size - 1)" ")"
); __builtin_expect(!!(__ret), 0); })
;
2373 WARN_ON(new_offset & (tile_size - 1))({ int __ret = !!((new_offset & (tile_size - 1))); if (__ret
) printf("%s", "WARN_ON(" "new_offset & (tile_size - 1)" ")"
); __builtin_expect(!!(__ret), 0); })
;
2374 WARN_ON(new_offset > old_offset)({ int __ret = !!((new_offset > old_offset)); if (__ret) printf
("%s", "WARN_ON(" "new_offset > old_offset" ")"); __builtin_expect
(!!(__ret), 0); })
;
2375
2376 tiles = (old_offset - new_offset) / tile_size;
2377
2378 *y += tiles / pitch_tiles * tile_height;
2379 *x += tiles % pitch_tiles * tile_width;
2380
2381 /* minimize x in case it got needlessly big */
2382 *y += *x / pitch_pixels * tile_height;
2383 *x %= pitch_pixels;
2384
2385 return new_offset;
2386}
2387
2388static bool_Bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane)
2389{
2390 return fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
||
2391 is_gen12_ccs_plane(fb, color_plane);
2392}
2393
2394static u32 intel_adjust_aligned_offset(int *x, int *y,
2395 const struct drm_framebuffer *fb,
2396 int color_plane,
2397 unsigned int rotation,
2398 unsigned int pitch,
2399 u32 old_offset, u32 new_offset)
2400{
2401 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev);
2402 unsigned int cpp = fb->format->cpp[color_plane];
2403
2404 drm_WARN_ON(&dev_priv->drm, new_offset > old_offset)({ int __ret = !!((new_offset > old_offset)); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "new_offset > old_offset" ")"); __builtin_expect
(!!(__ret), 0); })
;
2405
2406 if (!is_surface_linear(fb, color_plane)) {
2407 unsigned int tile_size, tile_width, tile_height;
2408 unsigned int pitch_tiles;
2409
2410 tile_size = intel_tile_size(dev_priv);
2411 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2412
2413 if (drm_rotation_90_or_270(rotation)) {
2414 pitch_tiles = pitch / tile_height;
2415 swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) =
(tile_height); (tile_height) = __tmp; } while(0)
;
2416 } else {
2417 pitch_tiles = pitch / (tile_width * cpp);
2418 }
2419
2420 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2421 tile_size, pitch_tiles,
2422 old_offset, new_offset);
2423 } else {
2424 old_offset += *y * pitch + *x * cpp;
2425
2426 *y = (old_offset - new_offset) / pitch;
2427 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2428 }
2429
2430 return new_offset;
2431}
2432
2433/*
2434 * Adjust the tile offset by moving the difference into
2435 * the x/y offsets.
2436 */
2437static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
2438 const struct intel_plane_state *state,
2439 int color_plane,
2440 u32 old_offset, u32 new_offset)
2441{
2442 return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane,
2443 state->hw.rotation,
2444 state->color_plane[color_plane].stride,
2445 old_offset, new_offset);
2446}
2447
2448/*
2449 * Computes the aligned offset to the base tile and adjusts
2450 * x, y. bytes per pixel is assumed to be a power-of-two.
2451 *
2452 * In the 90/270 rotated case, x and y are assumed
2453 * to be already rotated to match the rotated GTT view, and
2454 * pitch is the tile_height aligned framebuffer height.
2455 *
2456 * This function is used when computing the derived information
2457 * under intel_framebuffer, so using any of that information
2458 * here is not allowed. Anything under drm_framebuffer can be
2459 * used. This is why the user has to pass in the pitch since it
2460 * is specified in the rotated orientation.
2461 */
2462static u32 intel_compute_aligned_offset(struct drm_i915_privateinteldrm_softc *dev_priv,
2463 int *x, int *y,
2464 const struct drm_framebuffer *fb,
2465 int color_plane,
2466 unsigned int pitch,
2467 unsigned int rotation,
2468 u32 alignment)
2469{
2470 unsigned int cpp = fb->format->cpp[color_plane];
2471 u32 offset, offset_aligned;
2472
2473 if (!is_surface_linear(fb, color_plane)) {
2474 unsigned int tile_size, tile_width, tile_height;
2475 unsigned int tile_rows, tiles, pitch_tiles;
2476
2477 tile_size = intel_tile_size(dev_priv);
2478 intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
2479
2480 if (drm_rotation_90_or_270(rotation)) {
2481 pitch_tiles = pitch / tile_height;
2482 swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) =
(tile_height); (tile_height) = __tmp; } while(0)
;
2483 } else {
2484 pitch_tiles = pitch / (tile_width * cpp);
2485 }
2486
2487 tile_rows = *y / tile_height;
2488 *y %= tile_height;
2489
2490 tiles = *x / tile_width;
2491 *x %= tile_width;
2492
2493 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2494
2495 offset_aligned = offset;
2496 if (alignment)
2497 offset_aligned = rounddown(offset_aligned, alignment)(((offset_aligned) / (alignment)) * (alignment));
2498
2499 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2500 tile_size, pitch_tiles,
2501 offset, offset_aligned);
2502 } else {
2503 offset = *y * pitch + *x * cpp;
2504 offset_aligned = offset;
2505 if (alignment) {
2506 offset_aligned = rounddown(offset_aligned, alignment)(((offset_aligned) / (alignment)) * (alignment));
2507 *y = (offset % alignment) / pitch;
2508 *x = ((offset % alignment) - *y * pitch) / cpp;
2509 } else {
2510 *y = *x = 0;
2511 }
2512 }
2513
2514 return offset_aligned;
2515}
2516
2517static u32 intel_plane_compute_aligned_offset(int *x, int *y,
2518 const struct intel_plane_state *state,
2519 int color_plane)
2520{
2521 struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (state->uapi.plane); (struct intel_plane *)( (char *)__mptr
- __builtin_offsetof(struct intel_plane, base) );})
;
2522 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_plane->base.dev);
2523 const struct drm_framebuffer *fb = state->hw.fb;
2524 unsigned int rotation = state->hw.rotation;
2525 int pitch = state->color_plane[color_plane].stride;
2526 u32 alignment;
2527
2528 if (intel_plane->id == PLANE_CURSOR)
2529 alignment = intel_cursor_alignment(dev_priv);
2530 else
2531 alignment = intel_surf_alignment(fb, color_plane);
2532
2533 return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
2534 pitch, rotation, alignment);
2535}
2536
2537/* Convert the fb->offset[] into x/y offsets */
2538static int intel_fb_offset_to_xy(int *x, int *y,
2539 const struct drm_framebuffer *fb,
2540 int color_plane)
2541{
2542 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev);
2543 unsigned int height;
2544 u32 alignment;
2545
2546 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 &&
2547 is_semiplanar_uv_plane(fb, color_plane))
2548 alignment = intel_tile_row_size(fb, color_plane);
2549 else if (fb->modifier != DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
)
2550 alignment = intel_tile_size(dev_priv);
2551 else
2552 alignment = 0;
2553
2554 if (alignment != 0 && fb->offsets[color_plane] % alignment) {
2555 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n"
, fb->offsets[color_plane], color_plane)
2556 "Misaligned offset 0x%08x for color plane %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n"
, fb->offsets[color_plane], color_plane)
2557 fb->offsets[color_plane], color_plane)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n"
, fb->offsets[color_plane], color_plane)
;
2558 return -EINVAL22;
2559 }
2560
2561 height = drm_framebuffer_plane_height(fb->height, fb, color_plane);
2562 height = roundup2(height, intel_tile_height(fb, color_plane))(((height) + ((intel_tile_height(fb, color_plane)) - 1)) &
(~((__typeof(height))(intel_tile_height(fb, color_plane)) - 1
)))
;
2563
2564 /* Catch potential overflows early */
2565 if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),({ typeof(mul_u32_u32(height, fb->pitches[color_plane])) a
= (mul_u32_u32(height, fb->pitches[color_plane])); typeof
(fb->offsets[color_plane]) b = (fb->offsets[color_plane
]); (u32)(a + b) < a; })
2566 fb->offsets[color_plane])({ typeof(mul_u32_u32(height, fb->pitches[color_plane])) a
= (mul_u32_u32(height, fb->pitches[color_plane])); typeof
(fb->offsets[color_plane]) b = (fb->offsets[color_plane
]); (u32)(a + b) < a; })
) {
2567 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n"
, fb->offsets[color_plane], fb->pitches[color_plane], color_plane
)
2568 "Bad offset 0x%08x or pitch %d for color plane %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n"
, fb->offsets[color_plane], fb->pitches[color_plane], color_plane
)
2569 fb->offsets[color_plane], fb->pitches[color_plane],drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n"
, fb->offsets[color_plane], fb->pitches[color_plane], color_plane
)
2570 color_plane)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n"
, fb->offsets[color_plane], fb->pitches[color_plane], color_plane
)
;
2571 return -ERANGE34;
2572 }
2573
2574 *x = 0;
2575 *y = 0;
2576
2577 intel_adjust_aligned_offset(x, y,
2578 fb, color_plane, DRM_MODE_ROTATE_0(1<<0),
2579 fb->pitches[color_plane],
2580 fb->offsets[color_plane], 0);
2581
2582 return 0;
2583}
2584
2585static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
2586{
2587 switch (fb_modifier) {
2588 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
2589 return I915_TILING_X1;
2590 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
2591 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
2592 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
:
2593 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
:
2594 return I915_TILING_Y2;
2595 default:
2596 return I915_TILING_NONE0;
2597 }
2598}
2599
2600/*
2601 * From the Sky Lake PRM:
2602 * "The Color Control Surface (CCS) contains the compression status of
2603 * the cache-line pairs. The compression state of the cache-line pair
2604 * is specified by 2 bits in the CCS. Each CCS cache-line represents
2605 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
2606 * cache-line-pairs. CCS is always Y tiled."
2607 *
2608 * Since cache line pairs refers to horizontally adjacent cache lines,
2609 * each cache line in the CCS corresponds to an area of 32x16 cache
2610 * lines on the main surface. Since each pixel is 4 bytes, this gives
2611 * us a ratio of one byte in the CCS for each 8x16 pixels in the
2612 * main surface.
2613 */
2614static const struct drm_format_info skl_ccs_formats[] = {
2615 { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 24, .num_planes = 2,
2616 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2617 { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 24, .num_planes = 2,
2618 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
2619 { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 32, .num_planes = 2,
2620 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true1, },
2621 { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 32, .num_planes = 2,
2622 .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true1, },
2623};
2624
2625/*
2626 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
2627 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
2628 * in the main surface. With 4 byte pixels and each Y-tile having dimensions of
2629 * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
2630 * the main surface.
2631 */
2632static const struct drm_format_info gen12_ccs_formats[] = {
2633 { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 24, .num_planes = 2,
2634 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2635 .hsub = 1, .vsub = 1, },
2636 { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 24, .num_planes = 2,
2637 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2638 .hsub = 1, .vsub = 1, },
2639 { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 32, .num_planes = 2,
2640 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2641 .hsub = 1, .vsub = 1, .has_alpha = true1 },
2642 { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
, .depth = 32, .num_planes = 2,
2643 .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2644 .hsub = 1, .vsub = 1, .has_alpha = true1 },
2645 { .format = DRM_FORMAT_YUYV((__u32)('Y') | ((__u32)('U') << 8) | ((__u32)('Y') <<
16) | ((__u32)('V') << 24))
, .num_planes = 2,
2646 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2647 .hsub = 2, .vsub = 1, .is_yuv = true1 },
2648 { .format = DRM_FORMAT_YVYU((__u32)('Y') | ((__u32)('V') << 8) | ((__u32)('Y') <<
16) | ((__u32)('U') << 24))
, .num_planes = 2,
2649 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2650 .hsub = 2, .vsub = 1, .is_yuv = true1 },
2651 { .format = DRM_FORMAT_UYVY((__u32)('U') | ((__u32)('Y') << 8) | ((__u32)('V') <<
16) | ((__u32)('Y') << 24))
, .num_planes = 2,
2652 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2653 .hsub = 2, .vsub = 1, .is_yuv = true1 },
2654 { .format = DRM_FORMAT_VYUY((__u32)('V') | ((__u32)('Y') << 8) | ((__u32)('U') <<
16) | ((__u32)('Y') << 24))
, .num_planes = 2,
2655 .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
2656 .hsub = 2, .vsub = 1, .is_yuv = true1 },
2657 { .format = DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
, .num_planes = 4,
2658 .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 },
2659 .hsub = 2, .vsub = 2, .is_yuv = true1 },
2660 { .format = DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('0') << 24))
, .num_planes = 4,
2661 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2662 .hsub = 2, .vsub = 2, .is_yuv = true1 },
2663 { .format = DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
, .num_planes = 4,
2664 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2665 .hsub = 2, .vsub = 2, .is_yuv = true1 },
2666 { .format = DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
, .num_planes = 4,
2667 .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 },
2668 .hsub = 2, .vsub = 2, .is_yuv = true1 },
2669};
2670
2671static const struct drm_format_info *
2672lookup_format_info(const struct drm_format_info formats[],
2673 int num_formats, u32 format)
2674{
2675 int i;
2676
2677 for (i = 0; i < num_formats; i++) {
2678 if (formats[i].format == format)
2679 return &formats[i];
2680 }
2681
2682 return NULL((void *)0);
2683}
2684
2685static const struct drm_format_info *
2686intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
2687{
2688 switch (cmd->modifier[0]) {
2689 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
2690 case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
:
2691 return lookup_format_info(skl_ccs_formats,
2692 ARRAY_SIZE(skl_ccs_formats)(sizeof((skl_ccs_formats)) / sizeof((skl_ccs_formats)[0])),
2693 cmd->pixel_format);
2694 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
:
2695 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
:
2696 return lookup_format_info(gen12_ccs_formats,
2697 ARRAY_SIZE(gen12_ccs_formats)(sizeof((gen12_ccs_formats)) / sizeof((gen12_ccs_formats)[0])
)
,
2698 cmd->pixel_format);
2699 default:
2700 return NULL((void *)0);
2701 }
2702}
2703
2704bool_Bool is_ccs_modifier(u64 modifier)
2705{
2706 return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
||
2707 modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
||
2708 modifier == I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
||
2709 modifier == I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
;
2710}
2711
2712static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
2713{
2714 return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],(((fb->pitches[ccs_to_main_plane(fb, ccs_plane)]) + ((512)
- 1)) / (512))
2715 512)(((fb->pitches[ccs_to_main_plane(fb, ccs_plane)]) + ((512)
- 1)) / (512))
* 64;
2716}
2717
2718u32 intel_plane_fb_max_stride(struct drm_i915_privateinteldrm_softc *dev_priv,
2719 u32 pixel_format, u64 modifier)
2720{
2721 struct intel_crtc *crtc;
2722 struct intel_plane *plane;
2723
2724 /*
2725 * We assume the primary plane for pipe A has
2726 * the highest stride limits of them all,
2727 * if in case pipe A is disabled, use the first pipe from pipe_mask.
2728 */
2729 crtc = intel_get_first_crtc(dev_priv);
2730 if (!crtc)
2731 return 0;
2732
2733 plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (crtc->base.primary); (struct intel_plane *)( (char *)__mptr
- __builtin_offsetof(struct intel_plane, base) );})
;
2734
2735 return plane->max_stride(plane, pixel_format, modifier,
2736 DRM_MODE_ROTATE_0(1<<0));
2737}
2738
2739static
2740u32 intel_fb_max_stride(struct drm_i915_privateinteldrm_softc *dev_priv,
2741 u32 pixel_format, u64 modifier)
2742{
2743 /*
2744 * Arbitrary limit for gen4+ chosen to match the
2745 * render engine max stride.
2746 *
2747 * The new CCS hash mode makes remapping impossible
2748 */
2749 if (!is_ccs_modifier(modifier)) {
2750 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 7)
2751 return 256*1024;
2752 else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
2753 return 128*1024;
2754 }
2755
2756 return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
2757}
2758
2759static u32
2760intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
2761{
2762 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev);
2763 u32 tile_width;
2764
2765 if (is_surface_linear(fb, color_plane)) {
2766 u32 max_stride = intel_plane_fb_max_stride(dev_priv,
2767 fb->format->format,
2768 fb->modifier);
2769
2770 /*
2771 * To make remapping with linear generally feasible
2772 * we need the stride to be page aligned.
2773 */
2774 if (fb->pitches[color_plane] > max_stride &&
2775 !is_ccs_modifier(fb->modifier))
2776 return intel_tile_size(dev_priv);
2777 else
2778 return 64;
2779 }
2780
2781 tile_width = intel_tile_width_bytes(fb, color_plane);
2782 if (is_ccs_modifier(fb->modifier)) {
2783 /*
2784 * Display WA #0531: skl,bxt,kbl,glk
2785 *
2786 * Render decompression and plane width > 3840
2787 * combined with horizontal panning requires the
2788 * plane stride to be a multiple of 4. We'll just
2789 * require the entire fb to accommodate that to avoid
2790 * potential runtime errors at plane configuration time.
2791 */
2792 if (IS_GEN(dev_priv, 9)(0 + (&(dev_priv)->__info)->gen == (9)) && color_plane == 0 && fb->width > 3840)
2793 tile_width *= 4;
2794 /*
2795 * The main surface pitch must be padded to a multiple of four
2796 * tile widths.
2797 */
2798 else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12)
2799 tile_width *= 4;
2800 }
2801 return tile_width;
2802}
2803
2804bool_Bool intel_plane_can_remap(const struct intel_plane_state *plane_state)
2805{
2806 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (plane_state->uapi.plane); (struct intel_plane *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane, base) );})
;
2807 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
2808 const struct drm_framebuffer *fb = plane_state->hw.fb;
2809 int i;
2810
2811 /* We don't want to deal with remapping with cursors */
2812 if (plane->id == PLANE_CURSOR)
2813 return false0;
2814
2815 /*
2816 * The display engine limits already match/exceed the
2817 * render engine limits, so not much point in remapping.
2818 * Would also need to deal with the fence POT alignment
2819 * and gen2 2KiB GTT tile size.
2820 */
2821 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4)
2822 return false0;
2823
2824 /*
2825 * The new CCS hash mode isn't compatible with remapping as
2826 * the virtual address of the pages affects the compressed data.
2827 */
2828 if (is_ccs_modifier(fb->modifier))
2829 return false0;
2830
2831 /* Linear needs a page aligned stride for remapping */
2832 if (fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
) {
2833 unsigned int alignment = intel_tile_size(dev_priv) - 1;
2834
2835 for (i = 0; i < fb->format->num_planes; i++) {
2836 if (fb->pitches[i] & alignment)
2837 return false0;
2838 }
2839 }
2840
2841 return true1;
2842}
2843
2844static bool_Bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
2845{
2846 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (plane_state->uapi.plane); (struct intel_plane *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane, base) );})
;
2847 const struct drm_framebuffer *fb = plane_state->hw.fb;
2848 unsigned int rotation = plane_state->hw.rotation;
2849 u32 stride, max_stride;
2850
2851 /*
2852 * No remapping for invisible planes since we don't have
2853 * an actual source viewport to remap.
2854 */
2855 if (!plane_state->uapi.visible)
2856 return false0;
2857
2858 if (!intel_plane_can_remap(plane_state))
2859 return false0;
2860
2861 /*
2862 * FIXME: aux plane limits on gen9+ are
2863 * unclear in Bspec, for now no checking.
2864 */
2865 stride = intel_fb_pitch(fb, 0, rotation);
2866 max_stride = plane->max_stride(plane, fb->format->format,
2867 fb->modifier, rotation);
2868
2869 return stride > max_stride;
2870}
2871
2872static void
2873intel_fb_plane_get_subsampling(int *hsub, int *vsub,
2874 const struct drm_framebuffer *fb,
2875 int color_plane)
2876{
2877 int main_plane;
2878
2879 if (color_plane == 0) {
2880 *hsub = 1;
2881 *vsub = 1;
2882
2883 return;
2884 }
2885
2886 /*
2887 * TODO: Deduct the subsampling from the char block for all CCS
2888 * formats and planes.
2889 */
2890 if (!is_gen12_ccs_plane(fb, color_plane)) {
2891 *hsub = fb->format->hsub;
2892 *vsub = fb->format->vsub;
2893
2894 return;
2895 }
2896
2897 main_plane = ccs_to_main_plane(fb, color_plane);
2898 *hsub = drm_format_info_block_width(fb->format, color_plane) /
2899 drm_format_info_block_width(fb->format, main_plane);
2900
2901 /*
2902 * The min stride check in the core framebuffer_check() function
2903 * assumes that format->hsub applies to every plane except for the
2904 * first plane. That's incorrect for the CCS AUX plane of the first
2905 * plane, but for the above check to pass we must define the block
2906 * width with that subsampling applied to it. Adjust the width here
2907 * accordingly, so we can calculate the actual subsampling factor.
2908 */
2909 if (main_plane == 0)
2910 *hsub *= fb->format->hsub;
2911
2912 *vsub = 32;
2913}
2914static int
2915intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y)
2916{
2917 struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->dev);
2918 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
;
2919 int main_plane;
2920 int hsub, vsub;
2921 int tile_width, tile_height;
2922 int ccs_x, ccs_y;
2923 int main_x, main_y;
2924
2925 if (!is_ccs_plane(fb, ccs_plane))
2926 return 0;
2927
2928 intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height);
2929 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
2930
2931 tile_width *= hsub;
2932 tile_height *= vsub;
2933
2934 ccs_x = (x * hsub) % tile_width;
2935 ccs_y = (y * vsub) % tile_height;
2936
2937 main_plane = ccs_to_main_plane(fb, ccs_plane);
2938 main_x = intel_fb->normal[main_plane].x % tile_width;
2939 main_y = intel_fb->normal[main_plane].y % tile_height;
2940
2941 /*
2942 * CCS doesn't have its own x/y offset register, so the intra CCS tile
2943 * x/y offsets must match between CCS and the main surface.
2944 */
2945 if (main_x != ccs_x || main_y != ccs_y) {
2946 drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
2947 "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
2948 main_x, main_y,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
2949 ccs_x, ccs_y,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
2950 intel_fb->normal[main_plane].x,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
2951 intel_fb->normal[main_plane].y,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
2952 x, y)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n"
, main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane
].x, intel_fb->normal[main_plane].y, x, y)
;
2953 return -EINVAL22;
2954 }
2955
2956 return 0;
2957}
2958
2959static void
2960intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane)
2961{
2962 int main_plane = is_ccs_plane(fb, color_plane) ?
2963 ccs_to_main_plane(fb, color_plane) : 0;
2964 int main_hsub, main_vsub;
2965 int hsub, vsub;
2966
2967 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane);
2968 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane);
2969 *w = fb->width / main_hsub / hsub;
2970 *h = fb->height / main_vsub / vsub;
2971}
2972
2973/*
2974 * Setup the rotated view for an FB plane and return the size the GTT mapping
2975 * requires for this view.
2976 */
2977static u32
2978setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info,
2979 u32 gtt_offset_rotated, int x, int y,
2980 unsigned int width, unsigned int height,
2981 unsigned int tile_size,
2982 unsigned int tile_width, unsigned int tile_height,
2983 struct drm_framebuffer *fb)
2984{
2985 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
;
2986 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2987 unsigned int pitch_tiles;
2988 struct drm_rect r;
2989
2990 /* Y or Yf modifiers required for 90/270 rotation */
2991 if (fb->modifier != I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
&&
2992 fb->modifier != I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL
))
)
2993 return 0;
2994
2995 if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane))({ int __ret = !!((plane >= (sizeof((rot_info->plane)) /
sizeof((rot_info->plane)[0])))); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON("
"plane >= (sizeof((rot_info->plane)) / sizeof((rot_info->plane)[0]))"
")"); __builtin_expect(!!(__ret), 0); })
)
2996 return 0;
2997
2998 rot_info->plane[plane] = *plane_info;
2999
3000 intel_fb->rotated[plane].pitch = plane_info->height * tile_height;
3001
3002 /* rotate the x/y offsets to match the GTT view */
3003 drm_rect_init(&r, x, y, width, height);
3004 drm_rect_rotate(&r,
3005 plane_info->width * tile_width,
3006 plane_info->height * tile_height,
3007 DRM_MODE_ROTATE_270(1<<3));
3008 x = r.x1;
3009 y = r.y1;
3010
3011 /* rotate the tile dimensions to match the GTT view */
3012 pitch_tiles = intel_fb->rotated[plane].pitch / tile_height;
3013 swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) =
(tile_height); (tile_height) = __tmp; } while(0)
;
3014
3015 /*
3016 * We only keep the x/y offsets, so push all of the
3017 * gtt offset into the x/y offsets.
3018 */
3019 intel_adjust_tile_offset(&x, &y,
3020 tile_width, tile_height,
3021 tile_size, pitch_tiles,
3022 gtt_offset_rotated * tile_size, 0);
3023
3024 /*
3025 * First pixel of the framebuffer from
3026 * the start of the rotated gtt mapping.
3027 */
3028 intel_fb->rotated[plane].x = x;
3029 intel_fb->rotated[plane].y = y;
3030
3031 return plane_info->width * plane_info->height;
3032}
3033
3034static int
3035intel_fill_fb_info(struct drm_i915_privateinteldrm_softc *dev_priv,
3036 struct drm_framebuffer *fb)
3037{
3038 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
;
3039 struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0));
3040 u32 gtt_offset_rotated = 0;
3041 unsigned int max_size = 0;
3042 int i, num_planes = fb->format->num_planes;
3043 unsigned int tile_size = intel_tile_size(dev_priv);
3044
3045 for (i = 0; i < num_planes; i++) {
3046 unsigned int width, height;
3047 unsigned int cpp, size;
3048 u32 offset;
3049 int x, y;
3050 int ret;
3051
3052 cpp = fb->format->cpp[i];
3053 intel_fb_plane_dims(&width, &height, fb, i);
3054
3055 ret = intel_fb_offset_to_xy(&x, &y, fb, i);
3056 if (ret) {
3057 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n"
, i, fb->offsets[i])
3058 "bad fb plane %d offset: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n"
, i, fb->offsets[i])
3059 i, fb->offsets[i])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n"
, i, fb->offsets[i])
;
3060 return ret;
3061 }
3062
3063 ret = intel_fb_check_ccs_xy(fb, i, x, y);
3064 if (ret)
3065 return ret;
3066
3067 /*
3068 * The fence (if used) is aligned to the start of the object
3069 * so having the framebuffer wrap around across the edge of the
3070 * fenced region doesn't really work. We have no API to configure
3071 * the fence start offset within the object (nor could we probably
3072 * on gen2/3). So it's just easier if we just require that the
3073 * fb layout agrees with the fence layout. We already check that the
3074 * fb stride matches the fence stride elsewhere.
3075 */
3076 if (i == 0 && i915_gem_object_is_tiled(obj) &&
3077 (x + width) * cpp > fb->pitches[i]) {
3078 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n"
, i, fb->offsets[i])
3079 "bad fb plane %d offset: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n"
, i, fb->offsets[i])
3080 i, fb->offsets[i])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n"
, i, fb->offsets[i])
;
3081 return -EINVAL22;
3082 }
3083
3084 /*
3085 * First pixel of the framebuffer from
3086 * the start of the normal gtt mapping.
3087 */
3088 intel_fb->normal[i].x = x;
3089 intel_fb->normal[i].y = y;
3090
3091 offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
3092 fb->pitches[i],
3093 DRM_MODE_ROTATE_0(1<<0),
3094 tile_size);
3095 offset /= tile_size;
3096
3097 if (!is_surface_linear(fb, i)) {
3098 struct intel_remapped_plane_info plane_info;
3099 unsigned int tile_width, tile_height;
3100
3101 intel_tile_dims(fb, i, &tile_width, &tile_height);
3102
3103 plane_info.offset = offset;
3104 plane_info.stride = DIV_ROUND_UP(fb->pitches[i],(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width
* cpp))
3105 tile_width * cpp)(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width
* cpp))
;
3106 plane_info.width = DIV_ROUND_UP(x + width, tile_width)(((x + width) + ((tile_width) - 1)) / (tile_width));
3107 plane_info.height = DIV_ROUND_UP(y + height,(((y + height) + ((tile_height) - 1)) / (tile_height))
3108 tile_height)(((y + height) + ((tile_height) - 1)) / (tile_height));
3109
3110 /* how many tiles does this plane need */
3111 size = plane_info.stride * plane_info.height;
3112 /*
3113 * If the plane isn't horizontally tile aligned,
3114 * we need one more tile.
3115 */
3116 if (x != 0)
3117 size++;
3118
3119 gtt_offset_rotated +=
3120 setup_fb_rotation(i, &plane_info,
3121 gtt_offset_rotated,
3122 x, y, width, height,
3123 tile_size,
3124 tile_width, tile_height,
3125 fb);
3126 } else {
3127 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +((((y + height) * fb->pitches[i] + x * cpp) + ((tile_size)
- 1)) / (tile_size))
3128 x * cpp, tile_size)((((y + height) * fb->pitches[i] + x * cpp) + ((tile_size)
- 1)) / (tile_size))
;
3129 }
3130
3131 /* how many tiles in total needed in the bo */
3132 max_size = max(max_size, offset + size)(((max_size)>(offset + size))?(max_size):(offset + size));
3133 }
3134
3135 if (mul_u32_u32(max_size, tile_size) > obj->base.size) {
3136 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n"
, mul_u32_u32(max_size, tile_size), obj->base.size)
3137 "fb too big for bo (need %llu bytes, have %zu bytes)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n"
, mul_u32_u32(max_size, tile_size), obj->base.size)
3138 mul_u32_u32(max_size, tile_size), obj->base.size)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n"
, mul_u32_u32(max_size, tile_size), obj->base.size)
;
3139 return -EINVAL22;
3140 }
3141
3142 return 0;
3143}
3144
3145static void
3146intel_plane_remap_gtt(struct intel_plane_state *plane_state)
3147{
3148 struct drm_i915_privateinteldrm_softc *dev_priv =
3149 to_i915(plane_state->uapi.plane->dev);
3150 struct drm_framebuffer *fb = plane_state->hw.fb;
3151 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
;
3152 struct intel_rotation_info *info = &plane_state->view.rotated;
3153 unsigned int rotation = plane_state->hw.rotation;
3154 int i, num_planes = fb->format->num_planes;
3155 unsigned int tile_size = intel_tile_size(dev_priv);
3156 unsigned int src_x, src_y;
3157 unsigned int src_w, src_h;
3158 u32 gtt_offset = 0;
3159
3160 memset(&plane_state->view, 0, sizeof(plane_state->view))__builtin_memset((&plane_state->view), (0), (sizeof(plane_state
->view)))
;
3161 plane_state->view.type = drm_rotation_90_or_270(rotation) ?
3162 I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
3163
3164 src_x = plane_state->uapi.src.x1 >> 16;
3165 src_y = plane_state->uapi.src.y1 >> 16;
3166 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
3167 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
3168
3169 drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier))({ int __ret = !!((is_ccs_modifier(fb->modifier))); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON(" "is_ccs_modifier(fb->modifier)"
")"); __builtin_expect(!!(__ret), 0); })
;
3170
3171 /* Make src coordinates relative to the viewport */
3172 drm_rect_translate(&plane_state->uapi.src,
3173 -(src_x << 16), -(src_y << 16));
3174
3175 /* Rotate src coordinates to match rotated GTT view */
3176 if (drm_rotation_90_or_270(rotation))
3177 drm_rect_rotate(&plane_state->uapi.src,
3178 src_w << 16, src_h << 16,
3179 DRM_MODE_ROTATE_270(1<<3));
3180
3181 for (i = 0; i < num_planes; i++) {
3182 unsigned int hsub = i ? fb->format->hsub : 1;
3183 unsigned int vsub = i ? fb->format->vsub : 1;
3184 unsigned int cpp = fb->format->cpp[i];
3185 unsigned int tile_width, tile_height;
3186 unsigned int width, height;
3187 unsigned int pitch_tiles;
3188 unsigned int x, y;
3189 u32 offset;
3190
3191 intel_tile_dims(fb, i, &tile_width, &tile_height);
3192
3193 x = src_x / hsub;
3194 y = src_y / vsub;
3195 width = src_w / hsub;
3196 height = src_h / vsub;
3197
3198 /*
3199 * First pixel of the src viewport from the
3200 * start of the normal gtt mapping.
3201 */
3202 x += intel_fb->normal[i].x;
3203 y += intel_fb->normal[i].y;
3204
3205 offset = intel_compute_aligned_offset(dev_priv, &x, &y,
3206 fb, i, fb->pitches[i],
3207 DRM_MODE_ROTATE_0(1<<0), tile_size);
3208 offset /= tile_size;
3209
3210 drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane))({ int __ret = !!((i >= (sizeof((info->plane)) / sizeof
((info->plane)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string
(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "i >= (sizeof((info->plane)) / sizeof((info->plane)[0]))"
")"); __builtin_expect(!!(__ret), 0); })
;
3211 info->plane[i].offset = offset;
3212 info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width
* cpp))
3213 tile_width * cpp)(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width
* cpp))
;
3214 info->plane[i].width = DIV_ROUND_UP(x + width, tile_width)(((x + width) + ((tile_width) - 1)) / (tile_width));
3215 info->plane[i].height = DIV_ROUND_UP(y + height, tile_height)(((y + height) + ((tile_height) - 1)) / (tile_height));
3216
3217 if (drm_rotation_90_or_270(rotation)) {
3218 struct drm_rect r;
3219
3220 /* rotate the x/y offsets to match the GTT view */
3221 drm_rect_init(&r, x, y, width, height);
3222 drm_rect_rotate(&r,
3223 info->plane[i].width * tile_width,
3224 info->plane[i].height * tile_height,
3225 DRM_MODE_ROTATE_270(1<<3));
3226 x = r.x1;
3227 y = r.y1;
3228
3229 pitch_tiles = info->plane[i].height;
3230 plane_state->color_plane[i].stride = pitch_tiles * tile_height;
3231
3232 /* rotate the tile dimensions to match the GTT view */
3233 swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) =
(tile_height); (tile_height) = __tmp; } while(0)
;
3234 } else {
3235 pitch_tiles = info->plane[i].width;
3236 plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
3237 }
3238
3239 /*
3240 * We only keep the x/y offsets, so push all of the
3241 * gtt offset into the x/y offsets.
3242 */
3243 intel_adjust_tile_offset(&x, &y,
3244 tile_width, tile_height,
3245 tile_size, pitch_tiles,
3246 gtt_offset * tile_size, 0);
3247
3248 gtt_offset += info->plane[i].width * info->plane[i].height;
3249
3250 plane_state->color_plane[i].offset = 0;
3251 plane_state->color_plane[i].x = x;
3252 plane_state->color_plane[i].y = y;
3253 }
3254}
3255
3256static int
3257intel_plane_compute_gtt(struct intel_plane_state *plane_state)
3258{
3259 const struct intel_framebuffer *fb =
3260 to_intel_framebuffer(plane_state->hw.fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (plane_state->hw.fb); (struct intel_framebuffer
*)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer
, base) );})
;
3261 unsigned int rotation = plane_state->hw.rotation;
3262 int i, num_planes;
3263
3264 if (!fb)
3265 return 0;
3266
3267 num_planes = fb->base.format->num_planes;
3268
3269 if (intel_plane_needs_remap(plane_state)) {
3270 intel_plane_remap_gtt(plane_state);
3271
3272 /*
3273 * Sometimes even remapping can't overcome
3274 * the stride limitations :( Can happen with
3275 * big plane sizes and suitably misaligned
3276 * offsets.
3277 */
3278 return intel_plane_check_stride(plane_state);
3279 }
3280
3281 intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
3282
3283 for (i = 0; i < num_planes; i++) {
3284 plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
3285 plane_state->color_plane[i].offset = 0;
3286
3287 if (drm_rotation_90_or_270(rotation)) {
3288 plane_state->color_plane[i].x = fb->rotated[i].x;
3289 plane_state->color_plane[i].y = fb->rotated[i].y;
3290 } else {
3291 plane_state->color_plane[i].x = fb->normal[i].x;
3292 plane_state->color_plane[i].y = fb->normal[i].y;
3293 }
3294 }
3295
3296 /* Rotate src coordinates to match rotated GTT view */
3297 if (drm_rotation_90_or_270(rotation))
3298 drm_rect_rotate(&plane_state->uapi.src,
3299 fb->base.width << 16, fb->base.height << 16,
3300 DRM_MODE_ROTATE_270(1<<3));
3301
3302 return intel_plane_check_stride(plane_state);
3303}
3304
3305static int i9xx_format_to_fourcc(int format)
3306{
3307 switch (format) {
3308 case DISPPLANE_8BPP(0x2 << 26):
3309 return DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
;
3310 case DISPPLANE_BGRA555(0x3 << 26):
3311 return DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
;
3312 case DISPPLANE_BGRX555(0x4 << 26):
3313 return DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
;
3314 case DISPPLANE_BGRX565(0x5 << 26):
3315 return DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
;
3316 default:
3317 case DISPPLANE_BGRX888(0x6 << 26):
3318 return DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3319 case DISPPLANE_RGBX888(0xe << 26):
3320 return DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3321 case DISPPLANE_BGRA888(0x7 << 26):
3322 return DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3323 case DISPPLANE_RGBA888(0xf << 26):
3324 return DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3325 case DISPPLANE_BGRX101010(0xa << 26):
3326 return DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3327 case DISPPLANE_RGBX101010(0x8 << 26):
3328 return DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3329 case DISPPLANE_BGRA101010(0xb << 26):
3330 return DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3331 case DISPPLANE_RGBA101010(0x9 << 26):
3332 return DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3333 case DISPPLANE_RGBX161616(0xc << 26):
3334 return DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
;
3335 }
3336}
3337
3338int skl_format_to_fourcc(int format, bool_Bool rgb_order, bool_Bool alpha)
3339{
3340 switch (format) {
3341 case PLANE_CTL_FORMAT_RGB_565(14 << 24):
3342 return DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
;
3343 case PLANE_CTL_FORMAT_NV12(1 << 24):
3344 return DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
;
3345 case PLANE_CTL_FORMAT_XYUV(8 << 24):
3346 return DRM_FORMAT_XYUV8888((__u32)('X') | ((__u32)('Y') << 8) | ((__u32)('U') <<
16) | ((__u32)('V') << 24))
;
3347 case PLANE_CTL_FORMAT_P010(3 << 24):
3348 return DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('0') << 24))
;
3349 case PLANE_CTL_FORMAT_P012(5 << 24):
3350 return DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
;
3351 case PLANE_CTL_FORMAT_P016(7 << 24):
3352 return DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
;
3353 case PLANE_CTL_FORMAT_Y210(1 << 23):
3354 return DRM_FORMAT_Y210((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('0') << 24))
;
3355 case PLANE_CTL_FORMAT_Y212(3 << 23):
3356 return DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
;
3357 case PLANE_CTL_FORMAT_Y216(5 << 23):
3358 return DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
;
3359 case PLANE_CTL_FORMAT_Y410(7 << 23):
3360 return DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3361 case PLANE_CTL_FORMAT_Y412(9 << 23):
3362 return DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') <<
16) | ((__u32)('6') << 24))
;
3363 case PLANE_CTL_FORMAT_Y416(0xb << 23):
3364 return DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') <<
16) | ((__u32)('8') << 24))
;
3365 default:
3366 case PLANE_CTL_FORMAT_XRGB_8888(4 << 24):
3367 if (rgb_order) {
3368 if (alpha)
3369 return DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3370 else
3371 return DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3372 } else {
3373 if (alpha)
3374 return DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3375 else
3376 return DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
;
3377 }
3378 case PLANE_CTL_FORMAT_XRGB_2101010(2 << 24):
3379 if (rgb_order) {
3380 if (alpha)
3381 return DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3382 else
3383 return DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3384 } else {
3385 if (alpha)
3386 return DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3387 else
3388 return DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
;
3389 }
3390 case PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24):
3391 if (rgb_order) {
3392 if (alpha)
3393 return DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
;
3394 else
3395 return DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
;
3396 } else {
3397 if (alpha)
3398 return DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
;
3399 else
3400 return DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
;
3401 }
3402 }
3403}
3404
3405static struct i915_vma *
3406initial_plane_vma(struct drm_i915_privateinteldrm_softc *i915,
3407 struct intel_initial_plane_config *plane_config)
3408{
3409 struct drm_i915_gem_object *obj;
3410 struct i915_vma *vma;
3411 u32 base, size;
3412
3413 if (plane_config->size == 0)
3414 return NULL((void *)0);
3415
3416 base = round_down(plane_config->base,(((plane_config->base) / ((1ULL << (12)))) * ((1ULL <<
(12))))
3417 I915_GTT_MIN_ALIGNMENT)(((plane_config->base) / ((1ULL << (12)))) * ((1ULL <<
(12))))
;
3418 size = round_up(plane_config->base + plane_config->size,((((plane_config->base + plane_config->size) + (((1ULL <<
(12))) - 1)) / ((1ULL << (12)))) * ((1ULL << (12
))))
3419 I915_GTT_MIN_ALIGNMENT)((((plane_config->base + plane_config->size) + (((1ULL <<
(12))) - 1)) / ((1ULL << (12)))) * ((1ULL << (12
))))
;
3420 size -= base;
3421
3422 /*
3423 * If the FB is too big, just don't use it since fbdev is not very
3424 * important and we should probably use that space with FBC or other
3425 * features.
3426 */
3427 if (size * 2 > i915->stolen_usable_size)
3428 return NULL((void *)0);
3429
3430 obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
3431 if (IS_ERR(obj))
3432 return NULL((void *)0);
3433
3434 /*
3435 * Mark it WT ahead of time to avoid changing the
3436 * cache_level during fbdev initialization. The
3437 * unbind there would get stuck waiting for rcu.
3438 */
3439 i915_gem_object_set_cache_coherency(obj, HAS_WT(i915)((IS_PLATFORM(i915, INTEL_HASWELL) || IS_PLATFORM(i915, INTEL_BROADWELL
)) && ((i915)->edram_size_mb))
?
3440 I915_CACHE_WT : I915_CACHE_NONE);
3441
3442 switch (plane_config->tiling) {
3443 case I915_TILING_NONE0:
3444 break;
3445 case I915_TILING_X1:
3446 case I915_TILING_Y2:
3447 obj->tiling_and_stride =
3448 plane_config->fb->base.pitches[0] |
3449 plane_config->tiling;
3450 break;
3451 default:
3452 MISSING_CASE(plane_config->tiling)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "plane_config->tiling", (long)(plane_config->tiling))
; __builtin_expect(!!(__ret), 0); })
;
3453 goto err_obj;
3454 }
3455
3456 vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL((void *)0));
3457 if (IS_ERR(vma))
3458 goto err_obj;
3459
3460 if (i915_ggtt_pin(vma, NULL((void *)0), 0, PIN_MAPPABLE(1ULL << (3)) | PIN_OFFSET_FIXED(1ULL << (7)) | base))
3461 goto err_obj;
3462
3463 if (i915_gem_object_is_tiled(obj) &&
3464 !i915_vma_is_map_and_fenceable(vma))
3465 goto err_obj;
3466
3467 return vma;
3468
3469err_obj:
3470 i915_gem_object_put(obj);
3471 return NULL((void *)0);
3472}
3473
3474static bool_Bool
3475intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
3476 struct intel_initial_plane_config *plane_config)
3477{
3478 struct drm_device *dev = crtc->base.dev;
3479 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
3480 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
3481 struct drm_framebuffer *fb = &plane_config->fb->base;
3482 struct i915_vma *vma;
3483
3484 switch (fb->modifier) {
3485 case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
:
3486 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
3487 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
3488 break;
3489 default:
3490 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unsupported modifier for initial FB: 0x%llx\n"
, fb->modifier)
3491 "Unsupported modifier for initial FB: 0x%llx\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unsupported modifier for initial FB: 0x%llx\n"
, fb->modifier)
3492 fb->modifier)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unsupported modifier for initial FB: 0x%llx\n"
, fb->modifier)
;
3493 return false0;
3494 }
3495
3496 vma = initial_plane_vma(dev_priv, plane_config);
3497 if (!vma)
3498 return false0;
3499
3500 mode_cmd.pixel_format = fb->format->format;
3501 mode_cmd.width = fb->width;
3502 mode_cmd.height = fb->height;
3503 mode_cmd.pitches[0] = fb->pitches[0];
3504 mode_cmd.modifier[0] = fb->modifier;
3505 mode_cmd.flags = DRM_MODE_FB_MODIFIERS(1<<1);
3506
3507 if (intel_framebuffer_init(to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
,
3508 vma->obj, &mode_cmd)) {
3509 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "intel fb init failed\n"
)
;
3510 goto err_vma;
3511 }
3512
3513 plane_config->vma = vma;
3514 return true1;
3515
3516err_vma:
3517 i915_vma_put(vma);
3518 return false0;
3519}
3520
3521static void
3522intel_set_plane_visible(struct intel_crtc_state *crtc_state,
3523 struct intel_plane_state *plane_state,
3524 bool_Bool visible)
3525{
3526 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (plane_state->uapi.plane); (struct intel_plane *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane, base) );})
;
3527
3528 plane_state->uapi.visible = visible;
3529
3530 if (visible)
3531 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
3532 else
3533 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
3534}
3535
3536static void fixup_active_planes(struct intel_crtc_state *crtc_state)
3537{
3538 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3539 struct drm_plane *plane;
3540
3541 /*
3542 * Active_planes aliases if multiple "primary" or cursor planes
3543 * have been used on the same (or wrong) pipe. plane_mask uses
3544 * unique ids, hence we can use that to reconstruct active_planes.
3545 */
3546 crtc_state->active_planes = 0;
3547
3548 drm_for_each_plane_mask(plane, &dev_priv->drm,for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((&(&dev_priv->drm)->mode_config
.plane_list)->next); (__typeof(*(plane)) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*(plane)), head) );}); &(plane
)->head != (&(&dev_priv->drm)->mode_config.plane_list
); (plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((plane)->head.next); (__typeof(*(plane))
*)( (char *)__mptr - __builtin_offsetof(__typeof(*(plane)), head
) );})) if (!((crtc_state->uapi.plane_mask) & drm_plane_mask
(plane))) {} else
3549 crtc_state->uapi.plane_mask)for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((&(&dev_priv->drm)->mode_config
.plane_list)->next); (__typeof(*(plane)) *)( (char *)__mptr
- __builtin_offsetof(__typeof(*(plane)), head) );}); &(plane
)->head != (&(&dev_priv->drm)->mode_config.plane_list
); (plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((plane)->head.next); (__typeof(*(plane))
*)( (char *)__mptr - __builtin_offsetof(__typeof(*(plane)), head
) );})) if (!((crtc_state->uapi.plane_mask) & drm_plane_mask
(plane))) {} else
3550 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id)(1UL << (({ const __typeof( ((struct intel_plane *)0)->
base ) *__mptr = (plane); (struct intel_plane *)( (char *)__mptr
- __builtin_offsetof(struct intel_plane, base) );})->id))
;
3551}
3552
3553static void intel_plane_disable_noatomic(struct intel_crtc *crtc,
3554 struct intel_plane *plane)
3555{
3556 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
3557 struct intel_crtc_state *crtc_state =
3558 to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *
__mptr = (crtc->base.state); (struct intel_crtc_state *)( (
char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi
) );})
;
3559 struct intel_plane_state *plane_state =
3560 to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi )
*__mptr = (plane->base.state); (struct intel_plane_state *
)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state
, uapi) );})
;
3561
3562 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n"
, plane->base.base.id, plane->base.name, crtc->base.
base.id, crtc->base.name)
3563 "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n"
, plane->base.base.id, plane->base.name, crtc->base.
base.id, crtc->base.name)
3564 plane->base.base.id, plane->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n"
, plane->base.base.id, plane->base.name, crtc->base.
base.id, crtc->base.name)
3565 crtc->base.base.id, crtc->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n"
, plane->base.base.id, plane->base.name, crtc->base.
base.id, crtc->base.name)
;
3566
3567 intel_set_plane_visible(crtc_state, plane_state, false0);
3568 fixup_active_planes(crtc_state);
3569 crtc_state->data_rate[plane->id] = 0;
3570 crtc_state->min_cdclk[plane->id] = 0;
3571
3572 if (plane->id == PLANE_PRIMARY)
3573 hsw_disable_ips(crtc_state);
3574
3575 /*
3576 * Vblank time updates from the shadow to live plane control register
3577 * are blocked if the memory self-refresh mode is active at that
3578 * moment. So to make sure the plane gets truly disabled, disable
3579 * first the self-refresh mode. The self-refresh enable bit in turn
3580 * will be checked/applied by the HW only at the next frame start
3581 * event which is after the vblank start event, so we need to have a
3582 * wait-for-vblank between disabling the plane and the pipe.
3583 */
3584 if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) &&
3585 intel_set_memory_cxsr(dev_priv, false0))
3586 intel_wait_for_vblank(dev_priv, crtc->pipe);
3587
3588 /*
3589 * Gen2 reports pipe underruns whenever all planes are disabled.
3590 * So disable underrun reporting before all the planes get disabled.
3591 */
3592 if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) && !crtc_state->active_planes)
3593 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false0);
3594
3595 intel_disable_plane(plane, crtc_state);
3596}
3597
3598static struct intel_frontbuffer *
3599to_intel_frontbuffer(struct drm_framebuffer *fb)
3600{
3601 return fb ? to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base )
*__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr
- __builtin_offsetof(struct intel_framebuffer, base) );})
->frontbuffer : NULL((void *)0);
3602}
3603
3604static void
3605intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
3606 struct intel_initial_plane_config *plane_config)
3607{
3608 struct drm_device *dev = intel_crtc->base.dev;
3609 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
3610 struct drm_crtc *c;
3611 struct drm_plane *primary = intel_crtc->base.primary;
3612 struct drm_plane_state *plane_state = primary->state;
3613 struct intel_plane *intel_plane = to_intel_plane(primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof
(struct intel_plane, base) );})
;
3614 struct intel_plane_state *intel_state =
3615 to_intel_plane_state(plane_state)({ const __typeof( ((struct intel_plane_state *)0)->uapi )
*__mptr = (plane_state); (struct intel_plane_state *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane_state, uapi
) );})
;
3616 struct drm_framebuffer *fb;
3617 struct i915_vma *vma;
3618
3619 if (!plane_config->fb)
3620 return;
3621
3622 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
3623 fb = &plane_config->fb->base;
3624 vma = plane_config->vma;
3625 goto valid_fb;
3626 }
3627
3628 /*
3629 * Failed to alloc the obj, check to see if we should share
3630 * an fb with another CRTC instead
3631 */
3632 for_each_crtc(dev, c)for (c = ({ const __typeof( ((__typeof(*c) *)0)->head ) *__mptr
= ((&(dev)->mode_config.crtc_list)->next); (__typeof
(*c) *)( (char *)__mptr - __builtin_offsetof(__typeof(*c), head
) );}); &c->head != (&(dev)->mode_config.crtc_list
); c = ({ const __typeof( ((__typeof(*c) *)0)->head ) *__mptr
= (c->head.next); (__typeof(*c) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*c), head) );}))
{
3633 struct intel_plane_state *state;
3634
3635 if (c == &intel_crtc->base)
3636 continue;
3637
3638 if (!to_intel_crtc(c)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (c); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof
(struct intel_crtc, base) );})
->active)
3639 continue;
3640
3641 state = to_intel_plane_state(c->primary->state)({ const __typeof( ((struct intel_plane_state *)0)->uapi )
*__mptr = (c->primary->state); (struct intel_plane_state
*)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state
, uapi) );})
;
3642 if (!state->vma)
3643 continue;
3644
3645 if (intel_plane_ggtt_offset(state) == plane_config->base) {
3646 fb = state->hw.fb;
3647 vma = state->vma;
3648 goto valid_fb;
3649 }
3650 }
3651
3652 /*
3653 * We've failed to reconstruct the BIOS FB. Current display state
3654 * indicates that the primary plane is visible, but has a NULL FB,
3655 * which will lead to problems later if we don't fix it up. The
3656 * simplest solution is to just disable the primary plane now and
3657 * pretend the BIOS never had it enabled.
3658 */
3659 intel_plane_disable_noatomic(intel_crtc, intel_plane);
3660
3661 return;
3662
3663valid_fb:
3664 intel_state->hw.rotation = plane_config->rotation;
3665 intel_fill_fb_ggtt_view(&intel_state->view, fb,
3666 intel_state->hw.rotation);
3667 intel_state->color_plane[0].stride =
3668 intel_fb_pitch(fb, 0, intel_state->hw.rotation);
3669
3670 __i915_vma_pin(vma);
3671 intel_state->vma = i915_vma_get(vma);
3672 if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0)
3673 if (vma->fence)
3674 intel_state->flags |= PLANE_HAS_FENCE(1UL << (0));
3675
3676 plane_state->src_x = 0;
3677 plane_state->src_y = 0;
3678 plane_state->src_w = fb->width << 16;
3679 plane_state->src_h = fb->height << 16;
3680
3681 plane_state->crtc_x = 0;
3682 plane_state->crtc_y = 0;
3683 plane_state->crtc_w = fb->width;
3684 plane_state->crtc_h = fb->height;
3685
3686 intel_state->uapi.src = drm_plane_state_src(plane_state);
3687 intel_state->uapi.dst = drm_plane_state_dest(plane_state);
3688
3689 if (plane_config->tiling)
3690 dev_priv->preserve_bios_swizzle = true1;
3691
3692 plane_state->fb = fb;
3693 drm_framebuffer_get(fb);
3694
3695 plane_state->crtc = &intel_crtc->base;
3696 intel_plane_copy_uapi_to_hw_state(intel_state, intel_state);
3697
3698 intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB);
3699
3700 atomic_or(to_intel_plane(primary)->frontbuffer_bit,x86_atomic_setbits_u32(&to_intel_frontbuffer(fb)->bits
, ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof
(struct intel_plane, base) );})->frontbuffer_bit)
3701 &to_intel_frontbuffer(fb)->bits)x86_atomic_setbits_u32(&to_intel_frontbuffer(fb)->bits
, ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof
(struct intel_plane, base) );})->frontbuffer_bit)
;
3702}
3703
3704static int skl_max_plane_width(const struct drm_framebuffer *fb,
3705 int color_plane,
3706 unsigned int rotation)
3707{
3708 int cpp = fb->format->cpp[color_plane];
3709
3710 switch (fb->modifier) {
3711 case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
:
3712 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
3713 /*
3714 * Validated limit is 4k, but has 5k should
3715 * work apart from the following features:
3716 * - Ytile (already limited to 4k)
3717 * - FP16 (already limited to 4k)
3718 * - render compression (already limited to 4k)
3719 * - KVMR sprite and cursor (don't care)
3720 * - horizontal panning (TODO verify this)
3721 * - pipe and plane scaling (TODO verify this)
3722 */
3723 if (cpp == 8)
3724 return 4096;
3725 else
3726 return 5120;
3727 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
3728 case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
:
3729 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
:
3730 /* FIXME AUX plane? */
3731 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
3732 case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL
))
:
3733 if (cpp == 8)
3734 return 2048;
3735 else
3736 return 4096;
3737 default:
3738 MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fb->modifier", (long)(fb->modifier)); __builtin_expect
(!!(__ret), 0); })
;
3739 return 2048;
3740 }
3741}
3742
3743static int glk_max_plane_width(const struct drm_framebuffer *fb,
3744 int color_plane,
3745 unsigned int rotation)
3746{
3747 int cpp = fb->format->cpp[color_plane];
3748
3749 switch (fb->modifier) {
3750 case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
:
3751 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
3752 if (cpp == 8)
3753 return 4096;
3754 else
3755 return 5120;
3756 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
3757 case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
:
3758 /* FIXME AUX plane? */
3759 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
3760 case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL
))
:
3761 if (cpp == 8)
3762 return 2048;
3763 else
3764 return 5120;
3765 default:
3766 MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fb->modifier", (long)(fb->modifier)); __builtin_expect
(!!(__ret), 0); })
;
3767 return 2048;
3768 }
3769}
3770
3771static int icl_min_plane_width(const struct drm_framebuffer *fb)
3772{
3773 /* Wa_14011264657, Wa_14011050563: gen11+ */
3774 switch (fb->format->format) {
3775 case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
:
3776 return 18;
3777 case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
3778 return 10;
3779 case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
3780 case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
3781 case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
3782 case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
3783 case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
3784 case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
3785 case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
3786 case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
3787 case DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
3788 case DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
3789 case DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
3790 return 6;
3791 case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
3792 return 20;
3793 case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('0') << 24))
:
3794 case DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
3795 case DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
3796 return 12;
3797 case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
3798 case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
3799 case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
3800 case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
3801 case DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') <<
16) | ((__u32)('6') << 24))
:
3802 case DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') <<
16) | ((__u32)('8') << 24))
:
3803 return 4;
3804 default:
3805 return 1;
3806 }
3807}
3808
3809static int icl_max_plane_width(const struct drm_framebuffer *fb,
3810 int color_plane,
3811 unsigned int rotation)
3812{
3813 return 5120;
3814}
3815
3816static int skl_max_plane_height(void)
3817{
3818 return 4096;
3819}
3820
3821static int icl_max_plane_height(void)
3822{
3823 return 4320;
3824}
3825
3826static bool_Bool
3827skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
3828 int main_x, int main_y, u32 main_offset,
3829 int ccs_plane)
3830{
3831 const struct drm_framebuffer *fb = plane_state->hw.fb;
3832 int aux_x = plane_state->color_plane[ccs_plane].x;
3833 int aux_y = plane_state->color_plane[ccs_plane].y;
3834 u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
3835 u32 alignment = intel_surf_alignment(fb, ccs_plane);
3836 int hsub;
3837 int vsub;
3838
3839 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
3840 while (aux_offset >= main_offset && aux_y <= main_y) {
3841 int x, y;
3842
3843 if (aux_x == main_x && aux_y == main_y)
3844 break;
3845
3846 if (aux_offset == 0)
3847 break;
3848
3849 x = aux_x / hsub;
3850 y = aux_y / vsub;
3851 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
3852 plane_state,
3853 ccs_plane,
3854 aux_offset,
3855 aux_offset -
3856 alignment);
3857 aux_x = x * hsub + aux_x % hsub;
3858 aux_y = y * vsub + aux_y % vsub;
3859 }
3860
3861 if (aux_x != main_x || aux_y != main_y)
3862 return false0;
3863
3864 plane_state->color_plane[ccs_plane].offset = aux_offset;
3865 plane_state->color_plane[ccs_plane].x = aux_x;
3866 plane_state->color_plane[ccs_plane].y = aux_y;
3867
3868 return true1;
3869}
3870
3871unsigned int
3872intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
3873{
3874 int x = 0, y = 0;
3875
3876 intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3877 plane_state->color_plane[0].offset, 0);
3878
3879 return y;
3880}
3881
3882static int skl_check_main_surface(struct intel_plane_state *plane_state)
3883{
3884 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane_state->uapi.plane->dev);
3885 const struct drm_framebuffer *fb = plane_state->hw.fb;
3886 unsigned int rotation = plane_state->hw.rotation;
3887 int x = plane_state->uapi.src.x1 >> 16;
3888 int y = plane_state->uapi.src.y1 >> 16;
3889 int w = drm_rect_width(&plane_state->uapi.src) >> 16;
3890 int h = drm_rect_height(&plane_state->uapi.src) >> 16;
3891 int max_width, min_width, max_height;
3892 u32 alignment, offset;
3893 int aux_plane = intel_main_to_aux_plane(fb, 0);
3894 u32 aux_offset = plane_state->color_plane[aux_plane].offset;
3895
3896 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) {
3897 max_width = icl_max_plane_width(fb, 0, rotation);
3898 min_width = icl_min_plane_width(fb);
3899 } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
3900 max_width = glk_max_plane_width(fb, 0, rotation);
3901 min_width = 1;
3902 } else {
3903 max_width = skl_max_plane_width(fb, 0, rotation);
3904 min_width = 1;
3905 }
3906
3907 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11)
3908 max_height = icl_max_plane_height();
3909 else
3910 max_height = skl_max_plane_height();
3911
3912 if (w > max_width || w < min_width || h > max_height) {
3913 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n"
, w, h, min_width, max_width, max_height)
3914 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n"
, w, h, min_width, max_width, max_height)
3915 w, h, min_width, max_width, max_height)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n"
, w, h, min_width, max_width, max_height)
;
3916 return -EINVAL22;
3917 }
3918
3919 intel_add_fb_offsets(&x, &y, plane_state, 0);
3920 offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
3921 alignment = intel_surf_alignment(fb, 0);
3922 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))({ int __ret = !!((alignment && !(((alignment) != 0) &&
(((alignment) - 1) & (alignment)) == 0))); if (__ret) printf
("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->
dev), "", "drm_WARN_ON(" "alignment && !(((alignment) != 0) && (((alignment) - 1) & (alignment)) == 0)"
")"); __builtin_expect(!!(__ret), 0); })
)
3923 return -EINVAL22;
3924
3925 /*
3926 * AUX surface offset is specified as the distance from the
3927 * main surface offset, and it must be non-negative. Make
3928 * sure that is what we will get.
3929 */
3930 if (offset > aux_offset)
3931 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3932 offset, aux_offset & ~(alignment - 1));
3933
3934 /*
3935 * When using an X-tiled surface, the plane blows up
3936 * if the x offset + width exceed the stride.
3937 *
3938 * TODO: linear and Y-tiled seem fine, Yf untested,
3939 */
3940 if (fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
) {
3941 int cpp = fb->format->cpp[0];
3942
3943 while ((x + w) * cpp > plane_state->color_plane[0].stride) {
3944 if (offset == 0) {
3945 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to X-tiling\n"
)
3946 "Unable to find suitable display surface offset due to X-tiling\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to X-tiling\n"
)
;
3947 return -EINVAL22;
3948 }
3949
3950 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3951 offset, offset - alignment);
3952 }
3953 }
3954
3955 /*
3956 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
3957 * they match with the main surface x/y offsets.
3958 */
3959 if (is_ccs_modifier(fb->modifier)) {
3960 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
3961 offset, aux_plane)) {
3962 if (offset == 0)
3963 break;
3964
3965 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
3966 offset, offset - alignment);
3967 }
3968
3969 if (x != plane_state->color_plane[aux_plane].x ||
3970 y != plane_state->color_plane[aux_plane].y) {
3971 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n"
)
3972 "Unable to find suitable display surface offset due to CCS\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n"
)
;
3973 return -EINVAL22;
3974 }
3975 }
3976
3977 plane_state->color_plane[0].offset = offset;
3978 plane_state->color_plane[0].x = x;
3979 plane_state->color_plane[0].y = y;
3980
3981 /*
3982 * Put the final coordinates back so that the src
3983 * coordinate checks will see the right values.
3984 */
3985 drm_rect_translate_to(&plane_state->uapi.src,
3986 x << 16, y << 16);
3987
3988 return 0;
3989}
3990
3991static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
3992{
3993 struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane_state->uapi.plane->dev);
3994 const struct drm_framebuffer *fb = plane_state->hw.fb;
3995 unsigned int rotation = plane_state->hw.rotation;
3996 int uv_plane = 1;
3997 int max_width = skl_max_plane_width(fb, uv_plane, rotation);
3998 int max_height = 4096;
3999 int x = plane_state->uapi.src.x1 >> 17;
4000 int y = plane_state->uapi.src.y1 >> 17;
4001 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
4002 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
4003 u32 offset;
4004
4005 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
4006 offset = intel_plane_compute_aligned_offset(&x, &y,
4007 plane_state, uv_plane);
4008
4009 /* FIXME not quite sure how/if these apply to the chroma plane */
4010 if (w > max_width || h > max_height) {
4011 drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CbCr source size %dx%d too big (limit %dx%d)\n"
, w, h, max_width, max_height)
4012 "CbCr source size %dx%d too big (limit %dx%d)\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CbCr source size %dx%d too big (limit %dx%d)\n"
, w, h, max_width, max_height)
4013 w, h, max_width, max_height)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CbCr source size %dx%d too big (limit %dx%d)\n"
, w, h, max_width, max_height)
;
4014 return -EINVAL22;
4015 }
4016
4017 if (is_ccs_modifier(fb->modifier)) {
4018 int ccs_plane = main_to_ccs_plane(fb, uv_plane);
4019 int aux_offset = plane_state->color_plane[ccs_plane].offset;
4020 int alignment = intel_surf_alignment(fb, uv_plane);
4021
4022 if (offset > aux_offset)
4023 offset = intel_plane_adjust_aligned_offset(&x, &y,
4024 plane_state,
4025 uv_plane,
4026 offset,
4027 aux_offset & ~(alignment - 1));
4028
4029 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
4030 offset, ccs_plane)) {
4031 if (offset == 0)
4032 break;
4033
4034 offset = intel_plane_adjust_aligned_offset(&x, &y,
4035 plane_state,
4036 uv_plane,
4037 offset, offset - alignment);
4038 }
4039
4040 if (x != plane_state->color_plane[ccs_plane].x ||
4041 y != plane_state->color_plane[ccs_plane].y) {
4042 drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n"
)
4043 "Unable to find suitable display surface offset due to CCS\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n"
)
;
4044 return -EINVAL22;
4045 }
4046 }
4047
4048 plane_state->color_plane[uv_plane].offset = offset;
4049 plane_state->color_plane[uv_plane].x = x;
4050 plane_state->color_plane[uv_plane].y = y;
4051
4052 return 0;
4053}
4054
4055static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
4056{
4057 const struct drm_framebuffer *fb = plane_state->hw.fb;
4058 int src_x = plane_state->uapi.src.x1 >> 16;
4059 int src_y = plane_state->uapi.src.y1 >> 16;
4060 u32 offset;
4061 int ccs_plane;
4062
4063 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
4064 int main_hsub, main_vsub;
4065 int hsub, vsub;
4066 int x, y;
4067
4068 if (!is_ccs_plane(fb, ccs_plane))
4069 continue;
4070
4071 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
4072 ccs_to_main_plane(fb, ccs_plane));
4073 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
4074
4075 hsub *= main_hsub;
4076 vsub *= main_vsub;
4077 x = src_x / hsub;
4078 y = src_y / vsub;
4079
4080 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
4081
4082 offset = intel_plane_compute_aligned_offset(&x, &y,
4083 plane_state,
4084 ccs_plane);
4085
4086 plane_state->color_plane[ccs_plane].offset = offset;
4087 plane_state->color_plane[ccs_plane].x = (x * hsub +
4088 src_x % hsub) /
4089 main_hsub;
4090 plane_state->color_plane[ccs_plane].y = (y * vsub +
4091 src_y % vsub) /
4092 main_vsub;
4093 }
4094
4095 return 0;
4096}
4097
4098int skl_check_plane_surface(struct intel_plane_state *plane_state)
4099{
4100 const struct drm_framebuffer *fb = plane_state->hw.fb;
4101 int ret, i;
4102
4103 ret = intel_plane_compute_gtt(plane_state);
4104 if (ret)
4105 return ret;
4106
4107 if (!plane_state->uapi.visible)
4108 return 0;
4109
4110 /*
4111 * Handle the AUX surface first since the main surface setup depends on
4112 * it.
4113 */
4114 if (is_ccs_modifier(fb->modifier)) {
4115 ret = skl_check_ccs_aux_surface(plane_state);
4116 if (ret)
4117 return ret;
4118 }
4119
4120 if (intel_format_info_is_yuv_semiplanar(fb->format,
4121 fb->modifier)) {
4122 ret = skl_check_nv12_aux_surface(plane_state);
4123 if (ret)
4124 return ret;
4125 }
4126
4127 for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane)(sizeof((plane_state->color_plane)) / sizeof((plane_state->
color_plane)[0]))
; i++) {
4128 plane_state->color_plane[i].offset = ~0xfff;
4129 plane_state->color_plane[i].x = 0;
4130 plane_state->color_plane[i].y = 0;
4131 }
4132
4133 ret = skl_check_main_surface(plane_state);
4134 if (ret)
4135 return ret;
4136
4137 return 0;
4138}
4139
4140static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state,
4141 const struct intel_plane_state *plane_state,
4142 unsigned int *num, unsigned int *den)
4143{
4144 const struct drm_framebuffer *fb = plane_state->hw.fb;
4145 unsigned int cpp = fb->format->cpp[0];
4146
4147 /*
4148 * g4x bspec says 64bpp pixel rate can't exceed 80%
4149 * of cdclk when the sprite plane is enabled on the
4150 * same pipe. ilk/snb bspec says 64bpp pixel rate is
4151 * never allowed to exceed 80% of cdclk. Let's just go
4152 * with the ilk/snb limit always.
4153 */
4154 if (cpp == 8) {
4155 *num = 10;
4156 *den = 8;
4157 } else {
4158 *num = 1;
4159 *den = 1;
4160 }
4161}
4162
4163static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
4164 const struct intel_plane_state *plane_state)
4165{
4166 unsigned int pixel_rate;
4167 unsigned int num, den;
4168
4169 /*
4170 * Note that crtc_state->pixel_rate accounts for both
4171 * horizontal and vertical panel fitter downscaling factors.
4172 * Pre-HSW bspec tells us to only consider the horizontal
4173 * downscaling factor here. We ignore that and just consider
4174 * both for simplicity.
4175 */
4176 pixel_rate = crtc_state->pixel_rate;
4177
4178 i9xx_plane_ratio(crtc_state, plane_state, &num, &den);
4179
4180 /* two pixels per clock with double wide pipe */
4181 if (crtc_state->double_wide)
4182 den *= 2;
4183
4184 return DIV_ROUND_UP(pixel_rate * num, den)(((pixel_rate * num) + ((den) - 1)) / (den));
4185}
4186
4187unsigned int
4188i9xx_plane_max_stride(struct intel_plane *plane,
4189 u32 pixel_format, u64 modifier,
4190 unsigned int rotation)
4191{
4192 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
4193
4194 if (!HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) {
4195 return 32*1024;
4196 } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) {
4197 if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
)
4198 return 16*1024;
4199 else
4200 return 32*1024;
4201 } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 3) {
4202 if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
)
4203 return 8*1024;
4204 else
4205 return 16*1024;
4206 } else {
4207 if (plane->i9xx_plane == PLANE_C)
4208 return 4*1024;
4209 else
4210 return 8*1024;
4211 }
4212}
4213
4214static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4215{
4216 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
4217 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
4218 u32 dspcntr = 0;
4219
4220 if (crtc_state->gamma_enable)
4221 dspcntr |= DISPPLANE_GAMMA_ENABLE(1 << 30);
4222
4223 if (crtc_state->csc_enable)
4224 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE(1 << 24);
4225
4226 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5)
4227 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe)((crtc->pipe) << 24);
4228
4229 return dspcntr;
4230}
4231
4232static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
4233 const struct intel_plane_state *plane_state)
4234{
4235 struct drm_i915_privateinteldrm_softc *dev_priv =
4236 to_i915(plane_state->uapi.plane->dev);
4237 const struct drm_framebuffer *fb = plane_state->hw.fb;
4238 unsigned int rotation = plane_state->hw.rotation;
4239 u32 dspcntr;
4240
4241 dspcntr = DISPLAY_PLANE_ENABLE(1 << 31);
4242
4243 if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45
))
|| IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5)) ||
4244 IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6)) || IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE))
4245 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE(1 << 14);
4246
4247 switch (fb->format->format) {
4248 case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
:
4249 dspcntr |= DISPPLANE_8BPP(0x2 << 26);
4250 break;
4251 case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
:
4252 dspcntr |= DISPPLANE_BGRX555(0x4 << 26);
4253 break;
4254 case DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') <<
16) | ((__u32)('5') << 24))
:
4255 dspcntr |= DISPPLANE_BGRA555(0x3 << 26);
4256 break;
4257 case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
4258 dspcntr |= DISPPLANE_BGRX565(0x5 << 26);
4259 break;
4260 case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4261 dspcntr |= DISPPLANE_BGRX888(0x6 << 26);
4262 break;
4263 case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4264 dspcntr |= DISPPLANE_RGBX888(0xe << 26);
4265 break;
4266 case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4267 dspcntr |= DISPPLANE_BGRA888(0x7 << 26);
4268 break;
4269 case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4270 dspcntr |= DISPPLANE_RGBA888(0xf << 26);
4271 break;
4272 case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4273 dspcntr |= DISPPLANE_BGRX101010(0xa << 26);
4274 break;
4275 case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4276 dspcntr |= DISPPLANE_RGBX101010(0x8 << 26);
4277 break;
4278 case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4279 dspcntr |= DISPPLANE_BGRA101010(0xb << 26);
4280 break;
4281 case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4282 dspcntr |= DISPPLANE_RGBA101010(0x9 << 26);
4283 break;
4284 case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
4285 dspcntr |= DISPPLANE_RGBX161616(0xc << 26);
4286 break;
4287 default:
4288 MISSING_CASE(fb->format->format)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fb->format->format", (long)(fb->format->format
)); __builtin_expect(!!(__ret), 0); })
;
4289 return 0;
4290 }
4291
4292 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4 &&
4293 fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
)
4294 dspcntr |= DISPPLANE_TILED(1 << 10);
4295
4296 if (rotation & DRM_MODE_ROTATE_180(1<<2))
4297 dspcntr |= DISPPLANE_ROTATE_180(1 << 15);
4298
4299 if (rotation & DRM_MODE_REFLECT_X(1<<4))
4300 dspcntr |= DISPPLANE_MIRROR(1 << 8);
4301
4302 return dspcntr;
4303}
4304
4305int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
4306{
4307 struct drm_i915_privateinteldrm_softc *dev_priv =
4308 to_i915(plane_state->uapi.plane->dev);
4309 const struct drm_framebuffer *fb = plane_state->hw.fb;
4310 int src_x, src_y, src_w;
4311 u32 offset;
4312 int ret;
4313
4314 ret = intel_plane_compute_gtt(plane_state);
4315 if (ret)
4316 return ret;
4317
4318 if (!plane_state->uapi.visible)
4319 return 0;
4320
4321 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4322 src_x = plane_state->uapi.src.x1 >> 16;
4323 src_y = plane_state->uapi.src.y1 >> 16;
4324
4325 /* Undocumented hardware limit on i965/g4x/vlv/chv */
4326 if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && fb->format->cpp[0] == 8 && src_w > 2048)
4327 return -EINVAL22;
4328
4329 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
4330
4331 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
4332 offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
4333 plane_state, 0);
4334 else
4335 offset = 0;
4336
4337 /*
4338 * Put the final coordinates back so that the src
4339 * coordinate checks will see the right values.
4340 */
4341 drm_rect_translate_to(&plane_state->uapi.src,
4342 src_x << 16, src_y << 16);
4343
4344 /* HSW/BDW do this automagically in hardware */
4345 if (!IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && !IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) {
4346 unsigned int rotation = plane_state->hw.rotation;
4347 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
4348 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
4349
4350 if (rotation & DRM_MODE_ROTATE_180(1<<2)) {
4351 src_x += src_w - 1;
4352 src_y += src_h - 1;
4353 } else if (rotation & DRM_MODE_REFLECT_X(1<<4)) {
4354 src_x += src_w - 1;
4355 }
4356 }
4357
4358 plane_state->color_plane[0].offset = offset;
4359 plane_state->color_plane[0].x = src_x;
4360 plane_state->color_plane[0].y = src_y;
4361
4362 return 0;
4363}
4364
4365static bool_Bool i9xx_plane_has_windowing(struct intel_plane *plane)
4366{
4367 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
4368 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4369
4370 if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
4371 return i9xx_plane == PLANE_B;
4372 else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45
))
)
4373 return false0;
4374 else if (IS_GEN(dev_priv, 4)(0 + (&(dev_priv)->__info)->gen == (4)))
4375 return i9xx_plane == PLANE_C;
4376 else
4377 return i9xx_plane == PLANE_B ||
4378 i9xx_plane == PLANE_C;
4379}
4380
4381static int
4382i9xx_plane_check(struct intel_crtc_state *crtc_state,
4383 struct intel_plane_state *plane_state)
4384{
4385 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (plane_state->uapi.plane); (struct intel_plane *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane, base) );})
;
4386 int ret;
4387
4388 ret = chv_plane_check_rotation(plane_state);
4389 if (ret)
4390 return ret;
4391
4392 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi,
4393 &crtc_state->uapi,
4394 DRM_PLANE_HELPER_NO_SCALING(1<<16),
4395 DRM_PLANE_HELPER_NO_SCALING(1<<16),
4396 i9xx_plane_has_windowing(plane),
4397 true1);
4398 if (ret)
4399 return ret;
4400
4401 ret = i9xx_check_plane_surface(plane_state);
4402 if (ret)
4403 return ret;
4404
4405 if (!plane_state->uapi.visible)
4406 return 0;
4407
4408 ret = intel_plane_check_src_coordinates(plane_state);
4409 if (ret)
4410 return ret;
4411
4412 plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
4413
4414 return 0;
4415}
4416
4417static void i9xx_update_plane(struct intel_plane *plane,
4418 const struct intel_crtc_state *crtc_state,
4419 const struct intel_plane_state *plane_state)
4420{
4421 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
4422 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4423 u32 linear_offset;
4424 int x = plane_state->color_plane[0].x;
4425 int y = plane_state->color_plane[0].y;
4426 int crtc_x = plane_state->uapi.dst.x1;
4427 int crtc_y = plane_state->uapi.dst.y1;
4428 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
4429 int crtc_h = drm_rect_height(&plane_state->uapi.dst);
4430 unsigned long irqflags;
4431 u32 dspaddr_offset;
4432 u32 dspcntr;
4433
4434 dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state);
4435
4436 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
4437
4438 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
4439 dspaddr_offset = plane_state->color_plane[0].offset;
4440 else
4441 dspaddr_offset = linear_offset;
4442
4443 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); }
while (0)
;
4444
4445 intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70188) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4446 plane_state->color_plane[0].stride);
4447
4448 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) {
4449 /*
4450 * PLANE_A doesn't actually have a full window
4451 * generator but let's assume we still need to
4452 * program whatever is there.
4453 */
4454 intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7018C) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4455 (crtc_y << 16) | crtc_x);
4456 intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70190) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4457 ((crtc_h - 1) << 16) | (crtc_w - 1));
4458 } else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && i9xx_plane == PLANE_B) {
4459 intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info)->
trans_offsets[TRANSCODER_A] + (0x60a08) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
,
4460 (crtc_y << 16) | crtc_x);
4461 intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info)->
trans_offsets[TRANSCODER_A] + (0x60a0c) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
,
4462 ((crtc_h - 1) << 16) | (crtc_w - 1));
4463 intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info)->
trans_offsets[TRANSCODER_A] + (0x60a10) + ((&(dev_priv)->
__info)->display_mmio_offset))) })
, 0);
4464 }
4465
4466 if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) {
4467 intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4468 (y << 16) | x);
4469 } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) {
4470 intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4471 linear_offset);
4472 intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4473 (y << 16) | x);
4474 }
4475
4476 /*
4477 * The control register self-arms if the plane was previously
4478 * disabled. Try to make the plane enable atomic by writing
4479 * the control register just before the surface register.
4480 */
4481 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
, dspcntr);
4482 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
4483 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4484 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4485 else
4486 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
,
4487 intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
4488
4489 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock
); } while (0)
;
4490}
4491
4492static void i9xx_disable_plane(struct intel_plane *plane,
4493 const struct intel_crtc_state *crtc_state)
4494{
4495 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
4496 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4497 unsigned long irqflags;
4498 u32 dspcntr;
4499
4500 /*
4501 * DSPCNTR pipe gamma enable on g4x+ and pipe csc
4502 * enable on ilk+ affect the pipe bottom color as
4503 * well, so we must configure them even if the plane
4504 * is disabled.
4505 *
4506 * On pre-g4x there is no way to gamma correct the
4507 * pipe bottom color but we'll keep on doing this
4508 * anyway so that the crtc state readout works correctly.
4509 */
4510 dspcntr = i9xx_plane_ctl_crtc(crtc_state);
4511
4512 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); }
while (0)
;
4513
4514 intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
, dspcntr);
4515 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
4516 intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
, 0);
4517 else
4518 intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
, 0);
4519
4520 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock
); } while (0)
;
4521}
4522
4523static bool_Bool i9xx_plane_get_hw_state(struct intel_plane *plane,
4524 enum pipe *pipe)
4525{
4526 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev);
4527 enum intel_display_power_domain power_domain;
4528 enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
4529 intel_wakeref_t wakeref;
4530 bool_Bool ret;
4531 u32 val;
4532
4533 /*
4534 * Not 100% correct for planes that can move between pipes,
4535 * but that's only the case for gen2-4 which don't have any
4536 * display power wells.
4537 */
4538 power_domain = POWER_DOMAIN_PIPE(plane->pipe)((plane->pipe) + POWER_DOMAIN_PIPE_A);
4539 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
4540 if (!wakeref)
4541 return false0;
4542
4543 val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets
[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset
)) })
);
4544
4545 ret = val & DISPLAY_PLANE_ENABLE(1 << 31);
4546
4547 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5)
4548 *pipe = plane->pipe;
4549 else
4550 *pipe = (val & DISPPLANE_SEL_PIPE_MASK(3 << 24)) >>
4551 DISPPLANE_SEL_PIPE_SHIFT24;
4552
4553 intel_display_power_put(dev_priv, power_domain, wakeref);
4554
4555 return ret;
4556}
4557
4558static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
4559{
4560 struct drm_device *dev = intel_crtc->base.dev;
4561 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
4562 unsigned long irqflags;
4563
4564 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); }
while (0)
;
4565
4566 intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id)((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280)
- (0x68180)))) + (intel_crtc->pipe) * ((((0x68980) + (id)
* ((0x68A80) - (0x68980)))) - (((0x68180) + (id) * ((0x68280
) - (0x68180))))))) })
, 0);
4567 intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id)((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270)
- (0x68170)))) + (intel_crtc->pipe) * ((((0x68970) + (id)
* ((0x68A70) - (0x68970)))) - (((0x68170) + (id) * ((0x68270
) - (0x68170))))))) })
, 0);
4568 intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id)((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274)
- (0x68174)))) + (intel_crtc->pipe) * ((((0x68974) + (id)
* ((0x68A74) - (0x68974)))) - (((0x68174) + (id) * ((0x68274
) - (0x68174))))))) })
, 0);
4569
4570 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock
); } while (0)
;
4571}
4572
4573/*
4574 * This function detaches (aka. unbinds) unused scalers in hardware
4575 */
4576static void skl_detach_scalers(const struct intel_crtc_state *crtc_state)
4577{
4578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
4579 const struct intel_crtc_scaler_state *scaler_state =
4580 &crtc_state->scaler_state;
4581 int i;
4582
4583 /* loop through and disable scalers that aren't in use */
4584 for (i = 0; i < intel_crtc->num_scalers; i++) {
4585 if (!scaler_state->scalers[i].in_use)
4586 skl_detach_scaler(intel_crtc, i);
4587 }
4588}
4589
4590static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
4591 int color_plane, unsigned int rotation)
4592{
4593 /*
4594 * The stride is either expressed as a multiple of 64 bytes chunks for
4595 * linear buffers or in number of tiles for tiled buffers.
4596 */
4597 if (is_surface_linear(fb, color_plane))
4598 return 64;
4599 else if (drm_rotation_90_or_270(rotation))
4600 return intel_tile_height(fb, color_plane);
4601 else
4602 return intel_tile_width_bytes(fb, color_plane);
4603}
4604
4605u32 skl_plane_stride(const struct intel_plane_state *plane_state,
4606 int color_plane)
4607{
4608 const struct drm_framebuffer *fb = plane_state->hw.fb;
4609 unsigned int rotation = plane_state->hw.rotation;
4610 u32 stride = plane_state->color_plane[color_plane].stride;
4611
4612 if (color_plane >= fb->format->num_planes)
4613 return 0;
4614
4615 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
4616}
4617
4618static u32 skl_plane_ctl_format(u32 pixel_format)
4619{
4620 switch (pixel_format) {
4621 case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
16) | ((__u32)(' ') << 24))
:
4622 return PLANE_CTL_FORMAT_INDEXED(12 << 24);
4623 case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
4624 return PLANE_CTL_FORMAT_RGB_565(14 << 24);
4625 case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4626 case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4627 return PLANE_CTL_FORMAT_XRGB_8888(4 << 24) | PLANE_CTL_ORDER_RGBX(1 << 20);
4628 case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4629 case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
16) | ((__u32)('4') << 24))
:
4630 return PLANE_CTL_FORMAT_XRGB_8888(4 << 24);
4631 case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4632 case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4633 return PLANE_CTL_FORMAT_XRGB_2101010(2 << 24) | PLANE_CTL_ORDER_RGBX(1 << 20);
4634 case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4635 case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4636 return PLANE_CTL_FORMAT_XRGB_2101010(2 << 24);
4637 case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
4638 case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
4639 return PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24) | PLANE_CTL_ORDER_RGBX(1 << 20);
4640 case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
4641 case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
16) | ((__u32)('H') << 24))
:
4642 return PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24);
4643 case DRM_FORMAT_XYUV8888((__u32)('X') | ((__u32)('Y') << 8) | ((__u32)('U') <<
16) | ((__u32)('V') << 24))
:
4644 return PLANE_CTL_FORMAT_XYUV(8 << 24);
4645 case DRM_FORMAT_YUYV((__u32)('Y') | ((__u32)('U') << 8) | ((__u32)('Y') <<
16) | ((__u32)('V') << 24))
:
4646 return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_YUYV(0 << 16);
4647 case DRM_FORMAT_YVYU((__u32)('Y') | ((__u32)('V') << 8) | ((__u32)('Y') <<
16) | ((__u32)('U') << 24))
:
4648 return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_YVYU(2 << 16);
4649 case DRM_FORMAT_UYVY((__u32)('U') | ((__u32)('Y') << 8) | ((__u32)('V') <<
16) | ((__u32)('Y') << 24))
:
4650 return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_UYVY(1 << 16);
4651 case DRM_FORMAT_VYUY((__u32)('V') | ((__u32)('Y') << 8) | ((__u32)('U') <<
16) | ((__u32)('Y') << 24))
:
4652 return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_VYUY(3 << 16);
4653 case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
4654 return PLANE_CTL_FORMAT_NV12(1 << 24);
4655 case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('0') << 24))
:
4656 return PLANE_CTL_FORMAT_P010(3 << 24);
4657 case DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
4658 return PLANE_CTL_FORMAT_P012(5 << 24);
4659 case DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
4660 return PLANE_CTL_FORMAT_P016(7 << 24);
4661 case DRM_FORMAT_Y210((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('0') << 24))
:
4662 return PLANE_CTL_FORMAT_Y210(1 << 23);
4663 case DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('2') << 24))
:
4664 return PLANE_CTL_FORMAT_Y212(3 << 23);
4665 case DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') <<
16) | ((__u32)('6') << 24))
:
4666 return PLANE_CTL_FORMAT_Y216(5 << 23);
4667 case DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') <<
16) | ((__u32)('0') << 24))
:
4668 return PLANE_CTL_FORMAT_Y410(7 << 23);
4669 case DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') <<
16) | ((__u32)('6') << 24))
:
4670 return PLANE_CTL_FORMAT_Y412(9 << 23);
4671 case DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') <<
16) | ((__u32)('8') << 24))
:
4672 return PLANE_CTL_FORMAT_Y416(0xb << 23);
4673 default:
4674 MISSING_CASE(pixel_format)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "pixel_format", (long)(pixel_format)); __builtin_expect(!!(
__ret), 0); })
;
4675 }
4676
4677 return 0;
4678}
4679
4680static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
4681{
4682 if (!plane_state->hw.fb->format->has_alpha)
4683 return PLANE_CTL_ALPHA_DISABLE(0 << 4);
4684
4685 switch (plane_state->hw.pixel_blend_mode) {
4686 case DRM_MODE_BLEND_PIXEL_NONE2:
4687 return PLANE_CTL_ALPHA_DISABLE(0 << 4);
4688 case DRM_MODE_BLEND_PREMULTI0:
4689 return PLANE_CTL_ALPHA_SW_PREMULTIPLY(2 << 4);
4690 case DRM_MODE_BLEND_COVERAGE1:
4691 return PLANE_CTL_ALPHA_HW_PREMULTIPLY(3 << 4);
4692 default:
4693 MISSING_CASE(plane_state->hw.pixel_blend_mode)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "plane_state->hw.pixel_blend_mode", (long)(plane_state->
hw.pixel_blend_mode)); __builtin_expect(!!(__ret), 0); })
;
4694 return PLANE_CTL_ALPHA_DISABLE(0 << 4);
4695 }
4696}
4697
4698static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
4699{
4700 if (!plane_state->hw.fb->format->has_alpha)
4701 return PLANE_COLOR_ALPHA_DISABLE(0 << 4);
4702
4703 switch (plane_state->hw.pixel_blend_mode) {
4704 case DRM_MODE_BLEND_PIXEL_NONE2:
4705 return PLANE_COLOR_ALPHA_DISABLE(0 << 4);
4706 case DRM_MODE_BLEND_PREMULTI0:
4707 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY(2 << 4);
4708 case DRM_MODE_BLEND_COVERAGE1:
4709 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY(3 << 4);
4710 default:
4711 MISSING_CASE(plane_state->hw.pixel_blend_mode)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "plane_state->hw.pixel_blend_mode", (long)(plane_state->
hw.pixel_blend_mode)); __builtin_expect(!!(__ret), 0); })
;
4712 return PLANE_COLOR_ALPHA_DISABLE(0 << 4);
4713 }
4714}
4715
4716static u32 skl_plane_ctl_tiling(u64 fb_modifier)
4717{
4718 switch (fb_modifier) {
4719 case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL)
)
:
4720 break;
4721 case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL
))
:
4722 return PLANE_CTL_TILED_X(1 << 10);
4723 case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL
))
:
4724 return PLANE_CTL_TILED_Y(4 << 10);
4725 case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL
))
:
4726 return PLANE_CTL_TILED_Y(4 << 10) | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15);
4727 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL
))
:
4728 return PLANE_CTL_TILED_Y(4 << 10) |
4729 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15) |
4730 PLANE_CTL_CLEAR_COLOR_DISABLE(1 << 13);
4731 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL
))
:
4732 return PLANE_CTL_TILED_Y(4 << 10) | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE(1 << 4);
4733 case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL
))
:
4734 return PLANE_CTL_TILED_YF(5 << 10);
4735 case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL
))
:
4736 return PLANE_CTL_TILED_YF(5 << 10) | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15);
4737 default:
4738 MISSING_CASE(fb_modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fb_modifier", (long)(fb_modifier)); __builtin_expect(!!(__ret
), 0); })
;
4739 }
4740
4741 return 0;
4742}
4743
4744static u32 skl_plane_ctl_rotate(unsigned int rotate)
4745{
4746 switch (rotate) {
4747 case DRM_MODE_ROTATE_0(1<<0):
4748 break;
4749 /*
4750 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
4751 * while i915 HW rotation is clockwise, thats why this swapping.
4752 */
4753 case DRM_MODE_ROTATE_90(1<<1):
4754 return PLANE_CTL_ROTATE_2700x3;
4755 case DRM_MODE_ROTATE_180(1<<2):
4756 return PLANE_CTL_ROTATE_1800x2;
4757 case DRM_MODE_ROTATE_270(1<<3):
4758 return PLANE_CTL_ROTATE_900x1;
4759 default:
4760 MISSING_CASE(rotate)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "rotate", (long)(rotate)); __builtin_expect(!!(__ret), 0); }
)
;
4761 }
4762
4763 return 0;
4764}
4765
4766static u32 cnl_plane_ctl_flip(unsigned int reflect)
4767{
4768 switch (reflect) {
4769 case 0:
4770 break;
4771 case DRM_MODE_REFLECT_X(1<<4):
4772 return PLANE_CTL_FLIP_HORIZONTAL(1 << 8);
4773 case DRM_MODE_REFLECT_Y(1<<5):
4774 default:
4775 MISSING_CASE(reflect)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "reflect", (long)(reflect)); __builtin_expect(!!(__ret), 0)
; })
;
4776 }
4777
4778 return 0;
4779}
4780
4781u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
4782{
4783 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4784 u32 plane_ctl = 0;
4785
4786 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))
4787 return plane_ctl;
4788
4789 if (crtc_state->gamma_enable)
4790 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30);
4791
4792 if (crtc_state->csc_enable)
4793 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE(1 << 23);
4794
4795 return plane_ctl;
4796}
4797
4798u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
4799 const struct intel_plane_state *plane_state)
4800{
4801 struct drm_i915_privateinteldrm_softc *dev_priv =
4802 to_i915(plane_state->uapi.plane->dev);
4803 const struct drm_framebuffer *fb = plane_state->hw.fb;
4804 unsigned int rotation = plane_state->hw.rotation;
4805 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
4806 u32 plane_ctl;
4807
4808 plane_ctl = PLANE_CTL_ENABLE(1 << 31);
4809
4810 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 10 && !IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
4811 plane_ctl |= skl_plane_ctl_alpha(plane_state);
4812 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13);
4813
4814 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
4815 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18);
4816
4817 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4818 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE(1 << 28);
4819 }
4820
4821 plane_ctl |= skl_plane_ctl_format(fb->format->format);
4822 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
4823 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK( (1<<0) | (1<<1) | (1<<2) | (1<<3)));
4824
4825 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10)
4826 plane_ctl |= cnl_plane_ctl_flip(rotation &
4827 DRM_MODE_REFLECT_MASK( (1<<4) | (1<<5)));
4828
4829 if (key->flags & I915_SET_COLORKEY_DESTINATION(1<<1))
4830 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21);
4831 else if (key->flags & I915_SET_COLORKEY_SOURCE(1<<2))
4832 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE(1 << 21);
4833
4834 return plane_ctl;
4835}
4836
4837u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
4838{
4839 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4840 u32 plane_color_ctl = 0;
4841
4842 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11)
4843 return plane_color_ctl;
4844
4845 if (crtc_state->gamma_enable)
4846 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30);
4847
4848 if (crtc_state->csc_enable)
4849 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23);
4850
4851 return plane_color_ctl;
4852}
4853
4854u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
4855 const struct intel_plane_state *plane_state)
4856{
4857 struct drm_i915_privateinteldrm_softc *dev_priv =
4858 to_i915(plane_state->uapi.plane->dev);
4859 const struct drm_framebuffer *fb = plane_state->hw.fb;
4860 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr
= (plane_state->uapi.plane); (struct intel_plane *)( (char
*)__mptr - __builtin_offsetof(struct intel_plane, base) );})
;
4861 u32 plane_color_ctl = 0;
4862
4863 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE(1 << 13);
4864 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
4865
4866 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
4867 switch (plane_state->hw.color_encoding) {
4868 case DRM_COLOR_YCBCR_BT709:
4869 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709(2 << 17);
4870 break;
4871 case DRM_COLOR_YCBCR_BT2020:
4872 plane_color_ctl |=
4873 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020(3 << 17);
4874 break;
4875 default:
4876 plane_color_ctl |=
4877 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601(1 << 17);
4878 }
4879 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4880 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE(1 << 28);
4881 } else if (fb->format->is_yuv) {
4882 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE(1 << 20);
4883 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
4884 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE(1 << 28);
4885 }
4886
4887 return plane_color_ctl;
4888}
4889
4890static int
4891__intel_display_resume(struct drm_device *dev,
4892 struct drm_atomic_state *state,
4893 struct drm_modeset_acquire_ctx *ctx)
4894{
4895 struct drm_crtc_state *crtc_state;
4896 struct drm_crtc *crtc;
4897 int i, ret;
4898
4899 intel_modeset_setup_hw_state(dev, ctx);
4900 intel_vga_redisable(to_i915(dev));
4901
4902 if (!state)
4903 return 0;
4904
4905 /*
4906 * We've duplicated the state, pointers to the old state are invalid.
4907 *
4908 * Don't attempt to use the old state until we commit the duplicated state.
4909 */
4910 for_each_new_crtc_in_state(state, crtc, crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (crtc_state) = (state
)->crtcs[i].new_state, (void)(crtc_state) , 1))) {} else
{
4911 /*
4912 * Force recalculation even if we restore
4913 * current state. With fast modeset this may not result
4914 * in a modeset when the state is compatible.
4915 */
4916 crtc_state->mode_changed = true1;
4917 }
4918
4919 /* ignore any reset values/BIOS leftovers in the WM registers */
4920 if (!HAS_GMCH(to_i915(dev))((&(to_i915(dev))->__info)->display.has_gmch))
4921 to_intel_atomic_state(state)({ const __typeof( ((struct intel_atomic_state *)0)->base )
*__mptr = (state); (struct intel_atomic_state *)( (char *)__mptr
- __builtin_offsetof(struct intel_atomic_state, base) );})
->skip_intermediate_wm = true1;
4922
4923 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
4924
4925 drm_WARN_ON(dev, ret == -EDEADLK)({ int __ret = !!((ret == -11)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "ret == -11"
")"); __builtin_expect(!!(__ret), 0); })
;
4926 return ret;
4927}
4928
4929static bool_Bool gpu_reset_clobbers_display(struct drm_i915_privateinteldrm_softc *dev_priv)
4930{
4931 return (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gpu_reset_clobbers_display &&
4932 intel_has_gpu_reset(&dev_priv->gt));
4933}
4934
4935void intel_prepare_reset(struct drm_i915_privateinteldrm_softc *dev_priv)
4936{
4937 struct drm_device *dev = &dev_priv->drm;
4938 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4939 struct drm_atomic_state *state;
4940 int ret;
4941
4942 /* reset doesn't touch the display */
4943 if (!dev_priv->params.force_reset_modeset_test &&
4944 !gpu_reset_clobbers_display(dev_priv))
4945 return;
4946
4947 /* We have a modeset vs reset deadlock, defensively unbreak it. */
4948 set_bit(I915_RESET_MODESET1, &dev_priv->gt.reset.flags);
4949 smp_mb__after_atomic()do { } while (0);
4950 wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET1);
4951
4952 if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)({ typeof(*(&dev_priv->gpu_error.pending_fb_pin)) __tmp
= *(volatile typeof(*(&dev_priv->gpu_error.pending_fb_pin
)) *)&(*(&dev_priv->gpu_error.pending_fb_pin)); membar_datadep_consumer
(); __tmp; })
) {
4953 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Modeset potentially stuck, unbreaking through wedging\n"
)
4954 "Modeset potentially stuck, unbreaking through wedging\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Modeset potentially stuck, unbreaking through wedging\n"
)
;
4955 intel_gt_set_wedged(&dev_priv->gt);
4956 }
4957
4958 /*
4959 * Need mode_config.mutex so that we don't
4960 * trample ongoing ->detect() and whatnot.
4961 */
4962 mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex);
4963 drm_modeset_acquire_init(ctx, 0);
4964 while (1) {
4965 ret = drm_modeset_lock_all_ctx(dev, ctx);
4966 if (ret != -EDEADLK11)
4967 break;
4968
4969 drm_modeset_backoff(ctx);
4970 }
4971 /*
4972 * Disabling the crtcs gracefully seems nicer. Also the
4973 * g33 docs say we should at least disable all the planes.
4974 */
4975 state = drm_atomic_helper_duplicate_state(dev, ctx);
4976 if (IS_ERR(state)) {
4977 ret = PTR_ERR(state);
4978 drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Duplicating state failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
4979 ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Duplicating state failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
4980 return;
4981 }
4982
4983 ret = drm_atomic_helper_disable_all(dev, ctx);
4984 if (ret) {
4985 drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspending crtc's failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
4986 ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspending crtc's failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
4987 drm_atomic_state_put(state);
4988 return;
4989 }
4990
4991 dev_priv->modeset_restore_state = state;
4992 state->acquire_ctx = ctx;
4993}
4994
4995void intel_finish_reset(struct drm_i915_privateinteldrm_softc *dev_priv)
4996{
4997 struct drm_device *dev = &dev_priv->drm;
4998 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
4999 struct drm_atomic_state *state;
5000 int ret;
5001
5002 /* reset doesn't touch the display */
5003 if (!test_bit(I915_RESET_MODESET1, &dev_priv->gt.reset.flags))
5004 return;
5005
5006 state = fetch_and_zero(&dev_priv->modeset_restore_state)({ typeof(*&dev_priv->modeset_restore_state) __T = *(&
dev_priv->modeset_restore_state); *(&dev_priv->modeset_restore_state
) = (typeof(*&dev_priv->modeset_restore_state))0; __T;
})
;
5007 if (!state)
5008 goto unlock;
5009
5010 /* reset doesn't touch the display */
5011 if (!gpu_reset_clobbers_display(dev_priv)) {
5012 /* for testing only restore the display */
5013 ret = __intel_display_resume(dev, state, ctx);
5014 if (ret)
5015 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
5016 "Restoring old state failed with %i\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
5017 } else {
5018 /*
5019 * The display has been reset as well,
5020 * so need a full re-initialization.
5021 */
5022 intel_pps_unlock_regs_wa(dev_priv);
5023 intel_modeset_init_hw(dev_priv);
5024 intel_init_clock_gating(dev_priv);
5025
5026 spin_lock_irq(&dev_priv->irq_lock)mtx_enter(&dev_priv->irq_lock);
5027 if (dev_priv->display.hpd_irq_setup)
5028 dev_priv->display.hpd_irq_setup(dev_priv);
5029 spin_unlock_irq(&dev_priv->irq_lock)mtx_leave(&dev_priv->irq_lock);
5030
5031 ret = __intel_display_resume(dev, state, ctx);
5032 if (ret)
5033 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
5034 "Restoring old state failed with %i\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
5035
5036 intel_hpd_init(dev_priv);
5037 }
5038
5039 drm_atomic_state_put(state);
5040unlock:
5041 drm_modeset_drop_locks(ctx);
5042 drm_modeset_acquire_fini(ctx);
5043 mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex);
5044
5045 clear_bit_unlock(I915_RESET_MODESET1, &dev_priv->gt.reset.flags);
5046}
5047
5048static void icl_set_pipe_chicken(struct intel_crtc *crtc)
5049{
5050 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
5051 enum pipe pipe = crtc->pipe;
5052 u32 tmp;
5053
5054 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038)
- (0x70038)))) })
);
5055
5056 /*
5057 * Display WA #1153: icl
5058 * enable hardware to bypass the alpha math
5059 * and rounding for per-pixel values 00 and 0xff
5060 */
5061 tmp |= PER_PIXEL_ALPHA_BYPASS_EN(1 << 7);
5062 /*
5063 * Display WA # 1605353570: icl
5064 * Set the pixel rounding bit to 1 for allowing
5065 * passthrough of Frame buffer pixels unmodified
5066 * across pipe
5067 */
5068 tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU(1 << 15);
5069 intel_de_write(dev_priv, PIPE_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038)
- (0x70038)))) })
, tmp);
5070}
5071
5072static void intel_fdi_normal_train(struct intel_crtc *crtc)
5073{
5074 struct drm_device *dev = crtc->base.dev;
5075 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
5076 enum pipe pipe = crtc->pipe;
5077 i915_reg_t reg;
5078 u32 temp;
5079
5080 /* enable normal train */
5081 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5082 temp = intel_de_read(dev_priv, reg);
5083 if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) {
5084 temp &= ~FDI_LINK_TRAIN_NONE_IVB(3 << 8);
5085 temp |= FDI_LINK_TRAIN_NONE_IVB(3 << 8) | FDI_TX_ENHANCE_FRAME_ENABLE(1 << 18);
5086 } else {
5087 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5088 temp |= FDI_LINK_TRAIN_NONE(3 << 28) | FDI_TX_ENHANCE_FRAME_ENABLE(1 << 18);
5089 }
5090 intel_de_write(dev_priv, reg, temp);
5091
5092 reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
;
5093 temp = intel_de_read(dev_priv, reg);
5094 if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) {
5095 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8);
5096 temp |= FDI_LINK_TRAIN_NORMAL_CPT(3 << 8);
5097 } else {
5098 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5099 temp |= FDI_LINK_TRAIN_NONE(3 << 28);
5100 }
5101 intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE(1 << 6));
5102
5103 /* wait one idle pattern time */
5104 intel_de_posting_read(dev_priv, reg);
5105 udelay(1000);
5106
5107 /* IVB wants error correction enabled */
5108 if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE))
5109 intel_de_write(dev_priv, reg,
5110 intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE(1 << 27) | FDI_FE_ERRC_ENABLE(1 << 26));
5111}
5112
5113/* The FDI link training functions for ILK/Ibexpeak. */
5114static void ilk_fdi_link_train(struct intel_crtc *crtc,
5115 const struct intel_crtc_state *crtc_state)
5116{
5117 struct drm_device *dev = crtc->base.dev;
5118 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
5119 enum pipe pipe = crtc->pipe;
5120 i915_reg_t reg;
5121 u32 temp, tries;
5122
5123 /* FDI needs bits from pipe first */
5124 assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 1);
5125
5126 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5127 for train result */
5128 reg = FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018)
- (0xf0018)))) })
;
5129 temp = intel_de_read(dev_priv, reg);
5130 temp &= ~FDI_RX_SYMBOL_LOCK(1 << 9);
5131 temp &= ~FDI_RX_BIT_LOCK(1 << 8);
5132 intel_de_write(dev_priv, reg, temp);
5133 intel_de_read(dev_priv, reg);
5134 udelay(150);
5135
5136 /* enable CPU FDI TX and PCH FDI RX */
5137 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5138 temp = intel_de_read(dev_priv, reg);
5139 temp &= ~FDI_DP_PORT_WIDTH_MASK(7 << 19);
5140 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes)(((crtc_state->fdi_lanes) - 1) << 19);
5141 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5142 temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28);
5143 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE(1 << 31));
5144
5145 reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
;
5146 temp = intel_de_read(dev_priv, reg);
5147 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5148 temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28);
5149 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE(1 << 31));
5150
5151 intel_de_posting_read(dev_priv, reg);
5152 udelay(150);
5153
5154 /* Ironlake workaround, enable clock pointer after FDI enable*/
5155 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010)
- (0xc200c)))) })
,
5156 FDI_RX_PHASE_SYNC_POINTER_OVR(1 << 1));
5157 intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010)
- (0xc200c)))) })
,
5158 FDI_RX_PHASE_SYNC_POINTER_OVR(1 << 1) | FDI_RX_PHASE_SYNC_POINTER_EN(1 << 0));
5159
5160 reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014)
- (0xf0014)))) })
;
5161 for (tries = 0; tries < 5; tries++) {
5162 temp = intel_de_read(dev_priv, reg);
5163 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n"
, temp)
;
5164
5165 if ((temp & FDI_RX_BIT_LOCK(1 << 8))) {
5166 drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done.\n"
)
;
5167 intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK(1 << 8));
5168 break;
5169 }
5170 }
5171 if (tries == 5)
5172 drm_err(&dev_priv->drm, "FDI train 1 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 1 fail!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
5173
5174 /* Train 2 */
5175 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5176 temp = intel_de_read(dev_priv, reg);
5177 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5178 temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28);
5179 intel_de_write(dev_priv, reg, temp);
5180
5181 reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
;
5182 temp = intel_de_read(dev_priv, reg);
5183 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5184 temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28);
5185 intel_de_write(dev_priv, reg, temp);
5186
5187 intel_de_posting_read(dev_priv, reg);
5188 udelay(150);
5189
5190 reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014)
- (0xf0014)))) })
;
5191 for (tries = 0; tries < 5; tries++) {
5192 temp = intel_de_read(dev_priv, reg);
5193 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n"
, temp)
;
5194
5195 if (temp & FDI_RX_SYMBOL_LOCK(1 << 9)) {
5196 intel_de_write(dev_priv, reg,
5197 temp | FDI_RX_SYMBOL_LOCK(1 << 9));
5198 drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done.\n"
)
;
5199 break;
5200 }
5201 }
5202 if (tries == 5)
5203 drm_err(&dev_priv->drm, "FDI train 2 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 2 fail!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
5204
5205 drm_dbg_kms(&dev_priv->drm, "FDI train done\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train done\n"
)
;
5206
5207}
5208
5209static const int snb_b_fdi_train_param[] = {
5210 FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22),
5211 FDI_LINK_TRAIN_400MV_6DB_SNB_B(0x3a << 22),
5212 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B(0x39 << 22),
5213 FDI_LINK_TRAIN_800MV_0DB_SNB_B(0x38 << 22),
5214};
5215
5216/* The FDI link training functions for SNB/Cougarpoint. */
5217static void gen6_fdi_link_train(struct intel_crtc *crtc,
5218 const struct intel_crtc_state *crtc_state)
5219{
5220 struct drm_device *dev = crtc->base.dev;
5221 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
5222 enum pipe pipe = crtc->pipe;
5223 i915_reg_t reg;
5224 u32 temp, i, retry;
5225
5226 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5227 for train result */
5228 reg = FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018)
- (0xf0018)))) })
;
5229 temp = intel_de_read(dev_priv, reg);
5230 temp &= ~FDI_RX_SYMBOL_LOCK(1 << 9);
5231 temp &= ~FDI_RX_BIT_LOCK(1 << 8);
5232 intel_de_write(dev_priv, reg, temp);
5233
5234 intel_de_posting_read(dev_priv, reg);
5235 udelay(150);
5236
5237 /* enable CPU FDI TX and PCH FDI RX */
5238 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5239 temp = intel_de_read(dev_priv, reg);
5240 temp &= ~FDI_DP_PORT_WIDTH_MASK(7 << 19);
5241 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes)(((crtc_state->fdi_lanes) - 1) << 19);
5242 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5243 temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28);
5244 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22);
5245 /* SNB-B */
5246 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22);
5247 intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE(1 << 31));
5248
5249 intel_de_write(dev_priv, FDI_RX_MISC(pipe)((const i915_reg_t){ .reg = (((0xf0010) + (pipe) * ((0xf1010)
- (0xf0010)))) })
,
5250 FDI_RX_TP1_TO_TP2_48(2 << 20) | FDI_RX_FDI_DELAY_90(0x90 << 0));
5251
5252 reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
;
5253 temp = intel_de_read(dev_priv, reg);
5254 if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) {
5255 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8);
5256 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT(0 << 8);
5257 } else {
5258 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5259 temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28);
5260 }
5261 intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE(1 << 31));
5262
5263 intel_de_posting_read(dev_priv, reg);
5264 udelay(150);
5265
5266 for (i = 0; i < 4; i++) {
5267 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5268 temp = intel_de_read(dev_priv, reg);
5269 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22);
5270 temp |= snb_b_fdi_train_param[i];
5271 intel_de_write(dev_priv, reg, temp);
5272
5273 intel_de_posting_read(dev_priv, reg);
5274 udelay(500);
5275
5276 for (retry = 0; retry < 5; retry++) {
5277 reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014)
- (0xf0014)))) })
;
5278 temp = intel_de_read(dev_priv, reg);
5279 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n"
, temp)
;
5280 if (temp & FDI_RX_BIT_LOCK(1 << 8)) {
5281 intel_de_write(dev_priv, reg,
5282 temp | FDI_RX_BIT_LOCK(1 << 8));
5283 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done.\n"
)
5284 "FDI train 1 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done.\n"
)
;
5285 break;
5286 }
5287 udelay(50);
5288 }
5289 if (retry < 5)
5290 break;
5291 }
5292 if (i == 4)
5293 drm_err(&dev_priv->drm, "FDI train 1 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 1 fail!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
5294
5295 /* Train 2 */
5296 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5297 temp = intel_de_read(dev_priv, reg);
5298 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5299 temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28);
5300 if (IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6))) {
5301 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22);
5302 /* SNB-B */
5303 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22);
5304 }
5305 intel_de_write(dev_priv, reg, temp);
5306
5307 reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c)
- (0xf000c)))) })
;
5308 temp = intel_de_read(dev_priv, reg);
5309 if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) {
5310 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8);
5311 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT(1 << 8);
5312 } else {
5313 temp &= ~FDI_LINK_TRAIN_NONE(3 << 28);
5314 temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28);
5315 }
5316 intel_de_write(dev_priv, reg, temp);
5317
5318 intel_de_posting_read(dev_priv, reg);
5319 udelay(150);
5320
5321 for (i = 0; i < 4; i++) {
5322 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5323 temp = intel_de_read(dev_priv, reg);
5324 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22);
5325 temp |= snb_b_fdi_train_param[i];
5326 intel_de_write(dev_priv, reg, temp);
5327
5328 intel_de_posting_read(dev_priv, reg);
5329 udelay(500);
5330
5331 for (retry = 0; retry < 5; retry++) {
5332 reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014)
- (0xf0014)))) })
;
5333 temp = intel_de_read(dev_priv, reg);
5334 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n"
, temp)
;
5335 if (temp & FDI_RX_SYMBOL_LOCK(1 << 9)) {
5336 intel_de_write(dev_priv, reg,
5337 temp | FDI_RX_SYMBOL_LOCK(1 << 9));
5338 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done.\n"
)
5339 "FDI train 2 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done.\n"
)
;
5340 break;
5341 }
5342 udelay(50);
5343 }
5344 if (retry < 5)
5345 break;
5346 }
5347 if (i == 4)
5348 drm_err(&dev_priv->drm, "FDI train 2 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 2 fail!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
5349
5350 drm_dbg_kms(&dev_priv->drm, "FDI train done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train done.\n"
)
;
5351}
5352
5353/* Manual link training for Ivy Bridge A0 parts */
5354static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
5355 const struct intel_crtc_state *crtc_state)
5356{
5357 struct drm_device *dev = crtc->base.dev;
5358 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
5359 enum pipe pipe = crtc->pipe;
5360 i915_reg_t reg;
5361 u32 temp, i, j;
5362
5363 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
5364 for train result */
5365 reg = FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018)
- (0xf0018)))) })
;
5366 temp = intel_de_read(dev_priv, reg);
5367 temp &= ~FDI_RX_SYMBOL_LOCK(1 << 9);
5368 temp &= ~FDI_RX_BIT_LOCK(1 << 8);
5369 intel_de_write(dev_priv, reg, temp);
5370
5371 intel_de_posting_read(dev_priv, reg);
5372 udelay(150);
5373
5374 drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR before link train 0x%x\n"
, intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf0014
) + (pipe) * ((0xf1014) - (0xf0014)))) })))
5375 intel_de_read(dev_priv, FDI_RX_IIR(pipe)))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR before link train 0x%x\n"
, intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf0014
) + (pipe) * ((0xf1014) - (0xf0014)))) })))
;
5376
5377 /* Try each vswing and preemphasis setting twice before moving on */
5378 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param)(sizeof((snb_b_fdi_train_param)) / sizeof((snb_b_fdi_train_param
)[0]))
* 2; j++) {
5379 /* disable first in case we need to retry */
5380 reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100)
- (0x60100)))) })
;
5381 temp = intel_de_read(dev_priv, reg);
5382 temp &= ~(FDI_LINK_TRAIN_AUTO(1 << 10)