File: | dev/pci/drm/drm_edid.c |
Warning: | line 1885, column 28 Potential leak of memory pointed to by 'override' |
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1 | /* | ||||
2 | * Copyright (c) 2006 Luc Verhaegen (quirks list) | ||||
3 | * Copyright (c) 2007-2008 Intel Corporation | ||||
4 | * Jesse Barnes <jesse.barnes@intel.com> | ||||
5 | * Copyright 2010 Red Hat, Inc. | ||||
6 | * | ||||
7 | * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from | ||||
8 | * FB layer. | ||||
9 | * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> | ||||
10 | * | ||||
11 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||
12 | * copy of this software and associated documentation files (the "Software"), | ||||
13 | * to deal in the Software without restriction, including without limitation | ||||
14 | * the rights to use, copy, modify, merge, publish, distribute, sub license, | ||||
15 | * and/or sell copies of the Software, and to permit persons to whom the | ||||
16 | * Software is furnished to do so, subject to the following conditions: | ||||
17 | * | ||||
18 | * The above copyright notice and this permission notice (including the | ||||
19 | * next paragraph) shall be included in all copies or substantial portions | ||||
20 | * of the Software. | ||||
21 | * | ||||
22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||
23 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||
24 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||||
25 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||||
26 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||||
27 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||||
28 | * DEALINGS IN THE SOFTWARE. | ||||
29 | */ | ||||
30 | |||||
31 | #include <linux/hdmi.h> | ||||
32 | #include <linux/i2c.h> | ||||
33 | #include <linux/kernel.h> | ||||
34 | #include <linux/module.h> | ||||
35 | #include <linux/slab.h> | ||||
36 | #include <linux/vga_switcheroo.h> | ||||
37 | |||||
38 | #include <drm/drm_displayid.h> | ||||
39 | #include <drm/drm_drv.h> | ||||
40 | #include <drm/drm_edid.h> | ||||
41 | #include <drm/drm_encoder.h> | ||||
42 | #include <drm/drm_print.h> | ||||
43 | #include <drm/drm_scdc_helper.h> | ||||
44 | |||||
45 | #include "drm_crtc_internal.h" | ||||
46 | |||||
47 | #define version_greater(edid, maj, min)(((edid)->version > (maj)) || ((edid)->version == (maj ) && (edid)->revision > (min))) \ | ||||
48 | (((edid)->version > (maj)) || \ | ||||
49 | ((edid)->version == (maj) && (edid)->revision > (min))) | ||||
50 | |||||
51 | #define EDID_EST_TIMINGS16 16 | ||||
52 | #define EDID_STD_TIMINGS8 8 | ||||
53 | #define EDID_DETAILED_TIMINGS4 4 | ||||
54 | |||||
55 | /* | ||||
56 | * EDID blocks out in the wild have a variety of bugs, try to collect | ||||
57 | * them here (note that userspace may work around broken monitors first, | ||||
58 | * but fixes should make their way here so that the kernel "just works" | ||||
59 | * on as many displays as possible). | ||||
60 | */ | ||||
61 | |||||
62 | /* First detailed mode wrong, use largest 60Hz mode */ | ||||
63 | #define EDID_QUIRK_PREFER_LARGE_60(1 << 0) (1 << 0) | ||||
64 | /* Reported 135MHz pixel clock is too high, needs adjustment */ | ||||
65 | #define EDID_QUIRK_135_CLOCK_TOO_HIGH(1 << 1) (1 << 1) | ||||
66 | /* Prefer the largest mode at 75 Hz */ | ||||
67 | #define EDID_QUIRK_PREFER_LARGE_75(1 << 2) (1 << 2) | ||||
68 | /* Detail timing is in cm not mm */ | ||||
69 | #define EDID_QUIRK_DETAILED_IN_CM(1 << 3) (1 << 3) | ||||
70 | /* Detailed timing descriptors have bogus size values, so just take the | ||||
71 | * maximum size and use that. | ||||
72 | */ | ||||
73 | #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE(1 << 4) (1 << 4) | ||||
74 | /* use +hsync +vsync for detailed mode */ | ||||
75 | #define EDID_QUIRK_DETAILED_SYNC_PP(1 << 6) (1 << 6) | ||||
76 | /* Force reduced-blanking timings for detailed modes */ | ||||
77 | #define EDID_QUIRK_FORCE_REDUCED_BLANKING(1 << 7) (1 << 7) | ||||
78 | /* Force 8bpc */ | ||||
79 | #define EDID_QUIRK_FORCE_8BPC(1 << 8) (1 << 8) | ||||
80 | /* Force 12bpc */ | ||||
81 | #define EDID_QUIRK_FORCE_12BPC(1 << 9) (1 << 9) | ||||
82 | /* Force 6bpc */ | ||||
83 | #define EDID_QUIRK_FORCE_6BPC(1 << 10) (1 << 10) | ||||
84 | /* Force 10bpc */ | ||||
85 | #define EDID_QUIRK_FORCE_10BPC(1 << 11) (1 << 11) | ||||
86 | /* Non desktop display (i.e. HMD) */ | ||||
87 | #define EDID_QUIRK_NON_DESKTOP(1 << 12) (1 << 12) | ||||
88 | |||||
89 | struct detailed_mode_closure { | ||||
90 | struct drm_connector *connector; | ||||
91 | struct edid *edid; | ||||
92 | bool_Bool preferred; | ||||
93 | u32 quirks; | ||||
94 | int modes; | ||||
95 | }; | ||||
96 | |||||
97 | #define LEVEL_DMT0 0 | ||||
98 | #define LEVEL_GTF1 1 | ||||
99 | #define LEVEL_GTF22 2 | ||||
100 | #define LEVEL_CVT3 3 | ||||
101 | |||||
102 | static const struct edid_quirk { | ||||
103 | char vendor[4]; | ||||
104 | int product_id; | ||||
105 | u32 quirks; | ||||
106 | } edid_quirk_list[] = { | ||||
107 | /* Acer AL1706 */ | ||||
108 | { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
109 | /* Acer F51 */ | ||||
110 | { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
111 | |||||
112 | /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ | ||||
113 | { "AEO", 0, EDID_QUIRK_FORCE_6BPC(1 << 10) }, | ||||
114 | |||||
115 | /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ | ||||
116 | { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC(1 << 10) }, | ||||
117 | |||||
118 | /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ | ||||
119 | { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC(1 << 10) }, | ||||
120 | |||||
121 | /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ | ||||
122 | { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC(1 << 10) }, | ||||
123 | |||||
124 | /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ | ||||
125 | { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC(1 << 10) }, | ||||
126 | |||||
127 | /* Belinea 10 15 55 */ | ||||
128 | { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
129 | { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
130 | |||||
131 | /* Envision Peripherals, Inc. EN-7100e */ | ||||
132 | { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH(1 << 1) }, | ||||
133 | /* Envision EN2028 */ | ||||
134 | { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
135 | |||||
136 | /* Funai Electronics PM36B */ | ||||
137 | { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75(1 << 2) | | ||||
138 | EDID_QUIRK_DETAILED_IN_CM(1 << 3) }, | ||||
139 | |||||
140 | /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ | ||||
141 | { "LGD", 764, EDID_QUIRK_FORCE_10BPC(1 << 11) }, | ||||
142 | |||||
143 | /* LG Philips LCD LP154W01-A5 */ | ||||
144 | { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE(1 << 4) }, | ||||
145 | { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE(1 << 4) }, | ||||
146 | |||||
147 | /* Samsung SyncMaster 205BW. Note: irony */ | ||||
148 | { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP(1 << 6) }, | ||||
149 | /* Samsung SyncMaster 22[5-6]BW */ | ||||
150 | { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
151 | { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60(1 << 0) }, | ||||
152 | |||||
153 | /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ | ||||
154 | { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC(1 << 9) }, | ||||
155 | |||||
156 | /* ViewSonic VA2026w */ | ||||
157 | { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING(1 << 7) }, | ||||
158 | |||||
159 | /* Medion MD 30217 PG */ | ||||
160 | { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75(1 << 2) }, | ||||
161 | |||||
162 | /* Lenovo G50 */ | ||||
163 | { "SDC", 18514, EDID_QUIRK_FORCE_6BPC(1 << 10) }, | ||||
164 | |||||
165 | /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ | ||||
166 | { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC(1 << 8) }, | ||||
167 | |||||
168 | /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ | ||||
169 | { "ETR", 13896, EDID_QUIRK_FORCE_8BPC(1 << 8) }, | ||||
170 | |||||
171 | /* Valve Index Headset */ | ||||
172 | { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
173 | { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
174 | { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
175 | { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
176 | { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
177 | { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
178 | { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
179 | { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
180 | { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
181 | { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
182 | { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
183 | { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
184 | { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
185 | { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
186 | { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
187 | { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
188 | { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
189 | |||||
190 | /* HTC Vive and Vive Pro VR Headsets */ | ||||
191 | { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
192 | { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
193 | |||||
194 | /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ | ||||
195 | { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
196 | { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
197 | { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
198 | { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
199 | |||||
200 | /* Windows Mixed Reality Headsets */ | ||||
201 | { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
202 | { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
203 | { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
204 | { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
205 | { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
206 | { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
207 | { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
208 | { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
209 | |||||
210 | /* Sony PlayStation VR Headset */ | ||||
211 | { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
212 | |||||
213 | /* Sensics VR Headsets */ | ||||
214 | { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
215 | |||||
216 | /* OSVR HDK and HDK2 VR Headsets */ | ||||
217 | { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP(1 << 12) }, | ||||
218 | }; | ||||
219 | |||||
220 | /* | ||||
221 | * Autogenerated from the DMT spec. | ||||
222 | * This table is copied from xfree86/modes/xf86EdidModes.c. | ||||
223 | */ | ||||
224 | static const struct drm_display_mode drm_dmt_modes[] = { | ||||
225 | /* 0x01 - 640x350@85Hz */ | ||||
226 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,.name = "640x350", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (350), . vsync_start = (382), .vsync_end = (385), .vtotal = (445), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
227 | 736, 832, 0, 350, 382, 385, 445, 0,.name = "640x350", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (350), . vsync_start = (382), .vsync_end = (385), .vtotal = (445), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
228 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x350", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (350), . vsync_start = (382), .vsync_end = (385), .vtotal = (445), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
229 | /* 0x02 - 640x400@85Hz */ | ||||
230 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,.name = "640x400", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (445), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
231 | 736, 832, 0, 400, 401, 404, 445, 0,.name = "640x400", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (445), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
232 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "640x400", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (672), .hsync_end = (736), .htotal = (832), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (445), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
233 | /* 0x03 - 720x400@85Hz */ | ||||
234 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (756), .hsync_end = (828), .htotal = (936), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (446), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
235 | 828, 936, 0, 400, 401, 404, 446, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (756), .hsync_end = (828), .htotal = (936), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (446), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
236 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (756), .hsync_end = (828), .htotal = (936), .hskew = (0), .vdisplay = (400), . vsync_start = (401), .vsync_end = (404), .vtotal = (446), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
237 | /* 0x04 - 640x480@60Hz */ | ||||
238 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
239 | 752, 800, 0, 480, 490, 492, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
240 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
241 | /* 0x05 - 640x480@72Hz */ | ||||
242 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
243 | 704, 832, 0, 480, 489, 492, 520, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
244 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
245 | /* 0x06 - 640x480@75Hz */ | ||||
246 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
247 | 720, 840, 0, 480, 481, 484, 500, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
248 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
249 | /* 0x07 - 640x480@85Hz */ | ||||
250 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (640), .hsync_start = (696), .hsync_end = (752), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (509), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
251 | 752, 832, 0, 480, 481, 484, 509, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (640), .hsync_start = (696), .hsync_end = (752), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (509), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
252 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (640), .hsync_start = (696), .hsync_end = (752), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (509), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
253 | /* 0x08 - 800x600@56Hz */ | ||||
254 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
255 | 896, 1024, 0, 600, 601, 603, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
256 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
257 | /* 0x09 - 800x600@60Hz */ | ||||
258 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
259 | 968, 1056, 0, 600, 601, 605, 628, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
260 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
261 | /* 0x0a - 800x600@72Hz */ | ||||
262 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
263 | 976, 1040, 0, 600, 637, 643, 666, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
264 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
265 | /* 0x0b - 800x600@75Hz */ | ||||
266 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
267 | 896, 1056, 0, 600, 601, 604, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
268 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
269 | /* 0x0c - 800x600@85Hz */ | ||||
270 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (56250), .hdisplay = (800), .hsync_start = (832), .hsync_end = (896), .htotal = (1048), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (631), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
271 | 896, 1048, 0, 600, 601, 604, 631, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (56250), .hdisplay = (800), .hsync_start = (832), .hsync_end = (896), .htotal = (1048), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (631), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
272 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (56250), .hdisplay = (800), .hsync_start = (832), .hsync_end = (896), .htotal = (1048), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (631), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
273 | /* 0x0d - 800x600@120Hz RB */ | ||||
274 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (73250), .hdisplay = (800), .hsync_start = (848), .hsync_end = (880), .htotal = (960), .hskew = (0), .vdisplay = (600), . vsync_start = (603), .vsync_end = (607), .vtotal = (636), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
275 | 880, 960, 0, 600, 603, 607, 636, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (73250), .hdisplay = (800), .hsync_start = (848), .hsync_end = (880), .htotal = (960), .hskew = (0), .vdisplay = (600), . vsync_start = (603), .vsync_end = (607), .vtotal = (636), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
276 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (73250), .hdisplay = (800), .hsync_start = (848), .hsync_end = (880), .htotal = (960), .hskew = (0), .vdisplay = (600), . vsync_start = (603), .vsync_end = (607), .vtotal = (636), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
277 | /* 0x0e - 848x480@60Hz */ | ||||
278 | { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,.name = "848x480", .status = 0, .type = ((1<<6)), .clock = (33750), .hdisplay = (848), .hsync_start = (864), .hsync_end = (976), .htotal = (1088), .hskew = (0), .vdisplay = (480), . vsync_start = (486), .vsync_end = (494), .vtotal = (517), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
279 | 976, 1088, 0, 480, 486, 494, 517, 0,.name = "848x480", .status = 0, .type = ((1<<6)), .clock = (33750), .hdisplay = (848), .hsync_start = (864), .hsync_end = (976), .htotal = (1088), .hskew = (0), .vdisplay = (480), . vsync_start = (486), .vsync_end = (494), .vtotal = (517), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
280 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "848x480", .status = 0, .type = ((1<<6)), .clock = (33750), .hdisplay = (848), .hsync_start = (864), .hsync_end = (976), .htotal = (1088), .hskew = (0), .vdisplay = (480), . vsync_start = (486), .vsync_end = (494), .vtotal = (517), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
281 | /* 0x0f - 1024x768@43Hz, interlace */ | ||||
282 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
283 | 1208, 1264, 0, 768, 768, 776, 817, 0,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
284 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
285 | DRM_MODE_FLAG_INTERLACE).name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) }, | ||||
286 | /* 0x10 - 1024x768@60Hz */ | ||||
287 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
288 | 1184, 1344, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
289 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
290 | /* 0x11 - 1024x768@70Hz */ | ||||
291 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
292 | 1184, 1328, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
293 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
294 | /* 0x12 - 1024x768@75Hz */ | ||||
295 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
296 | 1136, 1312, 0, 768, 769, 772, 800, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
297 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
298 | /* 0x13 - 1024x768@85Hz */ | ||||
299 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (94500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1168), .htotal = (1376), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (808), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
300 | 1168, 1376, 0, 768, 769, 772, 808, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (94500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1168), .htotal = (1376), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (808), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
301 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (94500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1168), .htotal = (1376), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (808), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
302 | /* 0x14 - 1024x768@120Hz RB */ | ||||
303 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (115500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1104), .htotal = (1184), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (775), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
304 | 1104, 1184, 0, 768, 771, 775, 813, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (115500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1104), .htotal = (1184), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (775), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
305 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (115500), .hdisplay = (1024), .hsync_start = (1072), .hsync_end = (1104), .htotal = (1184), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (775), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
306 | /* 0x15 - 1152x864@75Hz */ | ||||
307 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
308 | 1344, 1600, 0, 864, 865, 868, 900, 0,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
309 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
310 | /* 0x55 - 1280x720@60Hz */ | ||||
311 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
312 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
313 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
314 | /* 0x16 - 1280x768@60Hz RB */ | ||||
315 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (68250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (790), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
316 | 1360, 1440, 0, 768, 771, 778, 790, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (68250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (790), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
317 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (68250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (790), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
318 | /* 0x17 - 1280x768@60Hz */ | ||||
319 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (79500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1472), .htotal = (1664), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (798), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
320 | 1472, 1664, 0, 768, 771, 778, 798, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (79500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1472), .htotal = (1664), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (798), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
321 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (79500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1472), .htotal = (1664), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (798), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
322 | /* 0x18 - 1280x768@75Hz */ | ||||
323 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (102250), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (805), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
324 | 1488, 1696, 0, 768, 771, 778, 805, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (102250), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (805), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
325 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (102250), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (805), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
326 | /* 0x19 - 1280x768@85Hz */ | ||||
327 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (117500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (809), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
328 | 1496, 1712, 0, 768, 771, 778, 809, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (117500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (809), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
329 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (117500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (809), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
330 | /* 0x1a - 1280x768@120Hz RB */ | ||||
331 | { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (140250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
332 | 1360, 1440, 0, 768, 771, 778, 813, 0,.name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (140250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
333 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x768", .status = 0, .type = ((1<<6)), .clock = (140250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (778), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
334 | /* 0x1b - 1280x800@60Hz RB */ | ||||
335 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (71000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (823), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
336 | 1360, 1440, 0, 800, 803, 809, 823, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (71000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (823), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
337 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (71000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (823), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
338 | /* 0x1c - 1280x800@60Hz */ | ||||
339 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (83500), .hdisplay = (1280), .hsync_start = (1352), .hsync_end = (1480), .htotal = (1680), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (831), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
340 | 1480, 1680, 0, 800, 803, 809, 831, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (83500), .hdisplay = (1280), .hsync_start = (1352), .hsync_end = (1480), .htotal = (1680), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (831), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
341 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (83500), .hdisplay = (1280), .hsync_start = (1352), .hsync_end = (1480), .htotal = (1680), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (831), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
342 | /* 0x1d - 1280x800@75Hz */ | ||||
343 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (838), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
344 | 1488, 1696, 0, 800, 803, 809, 838, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (838), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
345 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1488), .htotal = (1696), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (838), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
346 | /* 0x1e - 1280x800@85Hz */ | ||||
347 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (122500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (843), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
348 | 1496, 1712, 0, 800, 803, 809, 843, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (122500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (843), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
349 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (122500), .hdisplay = (1280), .hsync_start = (1360), .hsync_end = (1496), .htotal = (1712), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (843), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
350 | /* 0x1f - 1280x800@120Hz RB */ | ||||
351 | { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (847), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
352 | 1360, 1440, 0, 800, 803, 809, 847, 0,.name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (847), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
353 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x800", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (800), .vsync_start = (803), .vsync_end = (809), .vtotal = (847), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
354 | /* 0x20 - 1280x960@60Hz */ | ||||
355 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1376), .hsync_end = (1488), .htotal = (1800), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
356 | 1488, 1800, 0, 960, 961, 964, 1000, 0,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1376), .hsync_end = (1488), .htotal = (1800), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
357 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1376), .hsync_end = (1488), .htotal = (1800), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
358 | /* 0x21 - 1280x960@85Hz */ | ||||
359 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1011), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
360 | 1504, 1728, 0, 960, 961, 964, 1011, 0,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1011), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
361 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (960), .vsync_start = (961), .vsync_end = (964), .vtotal = (1011), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
362 | /* 0x22 - 1280x960@120Hz RB */ | ||||
363 | { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (960), .vsync_start = (963), .vsync_end = (967), .vtotal = (1017), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
364 | 1360, 1440, 0, 960, 963, 967, 1017, 0,.name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (960), .vsync_start = (963), .vsync_end = (967), .vtotal = (1017), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
365 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x960", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (960), .vsync_start = (963), .vsync_end = (967), .vtotal = (1017), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
366 | /* 0x23 - 1280x1024@60Hz */ | ||||
367 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
368 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
369 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
370 | /* 0x24 - 1280x1024@75Hz */ | ||||
371 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
372 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
373 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
374 | /* 0x25 - 1280x1024@85Hz */ | ||||
375 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (157500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1072 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
376 | 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (157500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1072 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
377 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (157500), .hdisplay = (1280), .hsync_start = (1344), .hsync_end = (1504), .htotal = (1728), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1072 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
378 | /* 0x26 - 1280x1024@120Hz RB */ | ||||
379 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (187250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1027), .vsync_end = (1034), .vtotal = (1084 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
380 | 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (187250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1027), .vsync_end = (1034), .vtotal = (1084 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
381 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (187250), .hdisplay = (1280), .hsync_start = (1328), .hsync_end = (1360), .htotal = (1440), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1027), .vsync_end = (1034), .vtotal = (1084 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
382 | /* 0x27 - 1360x768@60Hz */ | ||||
383 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1360), .hsync_start = (1424), .hsync_end = (1536), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (795), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
384 | 1536, 1792, 0, 768, 771, 777, 795, 0,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1360), .hsync_start = (1424), .hsync_end = (1536), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (795), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
385 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1360), .hsync_start = (1424), .hsync_end = (1536), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (795), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
386 | /* 0x28 - 1360x768@120Hz RB */ | ||||
387 | { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (148250), .hdisplay = (1360), .hsync_start = (1408), .hsync_end = (1440), .htotal = (1520), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (776), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
388 | 1440, 1520, 0, 768, 771, 776, 813, 0,.name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (148250), .hdisplay = (1360), .hsync_start = (1408), .hsync_end = (1440), .htotal = (1520), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (776), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
389 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1360x768", .status = 0, .type = ((1<<6)), .clock = (148250), .hdisplay = (1360), .hsync_start = (1408), .hsync_end = (1440), .htotal = (1520), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (776), .vtotal = (813), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
390 | /* 0x51 - 1366x768@60Hz */ | ||||
391 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1366), .hsync_start = (1436), .hsync_end = (1579), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (774), .vtotal = (798), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
392 | 1579, 1792, 0, 768, 771, 774, 798, 0,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1366), .hsync_start = (1436), .hsync_end = (1579), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (774), .vtotal = (798), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
393 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (85500), .hdisplay = (1366), .hsync_start = (1436), .hsync_end = (1579), .htotal = (1792), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (774), .vtotal = (798), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
394 | /* 0x56 - 1366x768@60Hz */ | ||||
395 | { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1366), .hsync_start = (1380), .hsync_end = (1436), .htotal = (1500), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
396 | 1436, 1500, 0, 768, 769, 772, 800, 0,.name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1366), .hsync_start = (1380), .hsync_end = (1436), .htotal = (1500), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
397 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1366x768", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1366), .hsync_start = (1380), .hsync_end = (1436), .htotal = (1500), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
398 | /* 0x29 - 1400x1050@60Hz RB */ | ||||
399 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (101000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
400 | 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (101000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
401 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (101000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
402 | /* 0x2a - 1400x1050@60Hz */ | ||||
403 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (121750), .hdisplay = (1400), .hsync_start = (1488), .hsync_end = (1632), .htotal = (1864), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
404 | 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (121750), .hdisplay = (1400), .hsync_start = (1488), .hsync_end = (1632), .htotal = (1864), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
405 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (121750), .hdisplay = (1400), .hsync_start = (1488), .hsync_end = (1632), .htotal = (1864), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
406 | /* 0x2b - 1400x1050@75Hz */ | ||||
407 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (156000), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1648), .htotal = (1896), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
408 | 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (156000), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1648), .htotal = (1896), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
409 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (156000), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1648), .htotal = (1896), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
410 | /* 0x2c - 1400x1050@85Hz */ | ||||
411 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (179500), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1656), .htotal = (1912), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
412 | 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (179500), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1656), .htotal = (1912), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
413 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (179500), .hdisplay = (1400), .hsync_start = (1504), .hsync_end = (1656), .htotal = (1912), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
414 | /* 0x2d - 1400x1050@120Hz RB */ | ||||
415 | { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (208000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
416 | 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,.name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (208000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
417 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1400x1050", .status = 0, .type = ((1<<6)), .clock = (208000), .hdisplay = (1400), .hsync_start = (1448), .hsync_end = (1480), .htotal = (1560), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1057), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
418 | /* 0x2e - 1440x900@60Hz RB */ | ||||
419 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (88750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (926), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
420 | 1520, 1600, 0, 900, 903, 909, 926, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (88750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (926), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
421 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (88750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (926), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
422 | /* 0x2f - 1440x900@60Hz */ | ||||
423 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1440), .hsync_start = (1520), .hsync_end = (1672), .htotal = (1904), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (934), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
424 | 1672, 1904, 0, 900, 903, 909, 934, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1440), .hsync_start = (1520), .hsync_end = (1672), .htotal = (1904), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (934), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
425 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (106500), .hdisplay = (1440), .hsync_start = (1520), .hsync_end = (1672), .htotal = (1904), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (934), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
426 | /* 0x30 - 1440x900@75Hz */ | ||||
427 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (136750), .hdisplay = (1440), .hsync_start = (1536), .hsync_end = (1688), .htotal = (1936), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (942), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
428 | 1688, 1936, 0, 900, 903, 909, 942, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (136750), .hdisplay = (1440), .hsync_start = (1536), .hsync_end = (1688), .htotal = (1936), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (942), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
429 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (136750), .hdisplay = (1440), .hsync_start = (1536), .hsync_end = (1688), .htotal = (1936), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (942), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
430 | /* 0x31 - 1440x900@85Hz */ | ||||
431 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (157000), .hdisplay = (1440), .hsync_start = (1544), .hsync_end = (1696), .htotal = (1952), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (948), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
432 | 1696, 1952, 0, 900, 903, 909, 948, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (157000), .hdisplay = (1440), .hsync_start = (1544), .hsync_end = (1696), .htotal = (1952), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (948), . vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
433 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (157000), .hdisplay = (1440), .hsync_start = (1544), .hsync_end = (1696), .htotal = (1952), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (948), . vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
434 | /* 0x32 - 1440x900@120Hz RB */ | ||||
435 | { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (182750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (953), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
436 | 1520, 1600, 0, 900, 903, 909, 953, 0,.name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (182750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (953), . vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
437 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x900", .status = 0, .type = ((1<<6)), .clock = (182750), .hdisplay = (1440), .hsync_start = (1488), .hsync_end = (1520), .htotal = (1600), .hskew = (0), .vdisplay = (900), .vsync_start = (903), .vsync_end = (909), .vtotal = (953), . vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
438 | /* 0x53 - 1600x900@60Hz */ | ||||
439 | { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,.name = "1600x900", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1600), .hsync_start = (1624), .hsync_end = (1704), .htotal = (1800), .hskew = (0), .vdisplay = (900), .vsync_start = (901), .vsync_end = (904), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
440 | 1704, 1800, 0, 900, 901, 904, 1000, 0,.name = "1600x900", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1600), .hsync_start = (1624), .hsync_end = (1704), .htotal = (1800), .hskew = (0), .vdisplay = (900), .vsync_start = (901), .vsync_end = (904), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
441 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x900", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1600), .hsync_start = (1624), .hsync_end = (1704), .htotal = (1800), .hskew = (0), .vdisplay = (900), .vsync_start = (901), .vsync_end = (904), .vtotal = (1000), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
442 | /* 0x33 - 1600x1200@60Hz */ | ||||
443 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
444 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
445 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
446 | /* 0x34 - 1600x1200@65Hz */ | ||||
447 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
448 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
449 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (175500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
450 | /* 0x35 - 1600x1200@70Hz */ | ||||
451 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (189000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
452 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (189000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
453 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (189000), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
454 | /* 0x36 - 1600x1200@75Hz */ | ||||
455 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (202500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
456 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (202500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
457 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (202500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
458 | /* 0x37 - 1600x1200@85Hz */ | ||||
459 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (229500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
460 | 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (229500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
461 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (229500), .hdisplay = (1600), .hsync_start = (1664), .hsync_end = (1856), .htotal = (2160), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1201), .vsync_end = (1204), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
462 | /* 0x38 - 1600x1200@120Hz RB */ | ||||
463 | { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (268250), .hdisplay = (1600), .hsync_start = (1648), .hsync_end = (1680), .htotal = (1760), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1207), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
464 | 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,.name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (268250), .hdisplay = (1600), .hsync_start = (1648), .hsync_end = (1680), .htotal = (1760), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1207), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
465 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1600x1200", .status = 0, .type = ((1<<6)), .clock = (268250), .hdisplay = (1600), .hsync_start = (1648), .hsync_end = (1680), .htotal = (1760), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1207), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
466 | /* 0x39 - 1680x1050@60Hz RB */ | ||||
467 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (119000), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
468 | 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (119000), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
469 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (119000), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1080 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
470 | /* 0x3a - 1680x1050@60Hz */ | ||||
471 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1680), .hsync_start = (1784), .hsync_end = (1960), .htotal = (2240), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
472 | 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1680), .hsync_start = (1784), .hsync_end = (1960), .htotal = (2240), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
473 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (146250), .hdisplay = (1680), .hsync_start = (1784), .hsync_end = (1960), .htotal = (2240), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1089 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
474 | /* 0x3b - 1680x1050@75Hz */ | ||||
475 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (187000), .hdisplay = (1680), .hsync_start = (1800), .hsync_end = (1976), .htotal = (2272), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
476 | 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (187000), .hdisplay = (1680), .hsync_start = (1800), .hsync_end = (1976), .htotal = (2272), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
477 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (187000), .hdisplay = (1680), .hsync_start = (1800), .hsync_end = (1976), .htotal = (2272), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1099 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
478 | /* 0x3c - 1680x1050@85Hz */ | ||||
479 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (214750), .hdisplay = (1680), .hsync_start = (1808), .hsync_end = (1984), .htotal = (2288), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
480 | 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (214750), .hdisplay = (1680), .hsync_start = (1808), .hsync_end = (1984), .htotal = (2288), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
481 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (214750), .hdisplay = (1680), .hsync_start = (1808), .hsync_end = (1984), .htotal = (2288), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1105 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
482 | /* 0x3d - 1680x1050@120Hz RB */ | ||||
483 | { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (245500), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
484 | 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,.name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (245500), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
485 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1680x1050", .status = 0, .type = ((1<<6)), .clock = (245500), .hdisplay = (1680), .hsync_start = (1728), .hsync_end = (1760), .htotal = (1840), .hskew = (0), .vdisplay = (1050) , .vsync_start = (1053), .vsync_end = (1059), .vtotal = (1112 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
486 | /* 0x3e - 1792x1344@60Hz */ | ||||
487 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (204750), .hdisplay = (1792), .hsync_start = (1920), .hsync_end = (2120), .htotal = (2448), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1394 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
488 | 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (204750), .hdisplay = (1792), .hsync_start = (1920), .hsync_end = (2120), .htotal = (2448), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1394 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
489 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (204750), .hdisplay = (1792), .hsync_start = (1920), .hsync_end = (2120), .htotal = (2448), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1394 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
490 | /* 0x3f - 1792x1344@75Hz */ | ||||
491 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (261000), .hdisplay = (1792), .hsync_start = (1888), .hsync_end = (2104), .htotal = (2456), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1417 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
492 | 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (261000), .hdisplay = (1792), .hsync_start = (1888), .hsync_end = (2104), .htotal = (2456), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1417 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
493 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (261000), .hdisplay = (1792), .hsync_start = (1888), .hsync_end = (2104), .htotal = (2456), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1345), .vsync_end = (1348), .vtotal = (1417 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
494 | /* 0x40 - 1792x1344@120Hz RB */ | ||||
495 | { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (333250), .hdisplay = (1792), .hsync_start = (1840), .hsync_end = (1872), .htotal = (1952), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1347), .vsync_end = (1351), .vtotal = (1423 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
496 | 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,.name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (333250), .hdisplay = (1792), .hsync_start = (1840), .hsync_end = (1872), .htotal = (1952), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1347), .vsync_end = (1351), .vtotal = (1423 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
497 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1792x1344", .status = 0, .type = ((1<<6)), .clock = (333250), .hdisplay = (1792), .hsync_start = (1840), .hsync_end = (1872), .htotal = (1952), .hskew = (0), .vdisplay = (1344) , .vsync_start = (1347), .vsync_end = (1351), .vtotal = (1423 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
498 | /* 0x41 - 1856x1392@60Hz */ | ||||
499 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (218250), .hdisplay = (1856), .hsync_start = (1952), .hsync_end = (2176), .htotal = (2528), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1439 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
500 | 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (218250), .hdisplay = (1856), .hsync_start = (1952), .hsync_end = (2176), .htotal = (2528), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1439 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
501 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (218250), .hdisplay = (1856), .hsync_start = (1952), .hsync_end = (2176), .htotal = (2528), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1439 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
502 | /* 0x42 - 1856x1392@75Hz */ | ||||
503 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (288000), .hdisplay = (1856), .hsync_start = (1984), .hsync_end = (2208), .htotal = (2560), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
504 | 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (288000), .hdisplay = (1856), .hsync_start = (1984), .hsync_end = (2208), .htotal = (2560), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
505 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (288000), .hdisplay = (1856), .hsync_start = (1984), .hsync_end = (2208), .htotal = (2560), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1393), .vsync_end = (1396), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
506 | /* 0x43 - 1856x1392@120Hz RB */ | ||||
507 | { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (356500), .hdisplay = (1856), .hsync_start = (1904), .hsync_end = (1936), .htotal = (2016), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1395), .vsync_end = (1399), .vtotal = (1474 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
508 | 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,.name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (356500), .hdisplay = (1856), .hsync_start = (1904), .hsync_end = (1936), .htotal = (2016), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1395), .vsync_end = (1399), .vtotal = (1474 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
509 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1856x1392", .status = 0, .type = ((1<<6)), .clock = (356500), .hdisplay = (1856), .hsync_start = (1904), .hsync_end = (1936), .htotal = (2016), .hskew = (0), .vdisplay = (1392) , .vsync_start = (1395), .vsync_end = (1399), .vtotal = (1474 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
510 | /* 0x52 - 1920x1080@60Hz */ | ||||
511 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
512 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
513 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, | ||||
514 | /* 0x44 - 1920x1200@60Hz RB */ | ||||
515 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (154000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1235 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
516 | 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (154000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1235 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
517 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (154000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1235 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
518 | /* 0x45 - 1920x1200@60Hz */ | ||||
519 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (193250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2256), .htotal = (2592), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1245 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
520 | 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (193250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2256), .htotal = (2592), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1245 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
521 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (193250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2256), .htotal = (2592), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1245 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
522 | /* 0x46 - 1920x1200@75Hz */ | ||||
523 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (245250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2264), .htotal = (2608), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1255 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
524 | 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (245250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2264), .htotal = (2608), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1255 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
525 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (245250), .hdisplay = (1920), .hsync_start = (2056), .hsync_end = (2264), .htotal = (2608), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1255 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
526 | /* 0x47 - 1920x1200@85Hz */ | ||||
527 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (281250), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2272), .htotal = (2624), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1262 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
528 | 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (281250), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2272), .htotal = (2624), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1262 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
529 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (281250), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2272), .htotal = (2624), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1262 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
530 | /* 0x48 - 1920x1200@120Hz RB */ | ||||
531 | { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (317000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
532 | 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,.name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (317000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
533 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1200", .status = 0, .type = ((1<<6)), .clock = (317000), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1200) , .vsync_start = (1203), .vsync_end = (1209), .vtotal = (1271 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
534 | /* 0x49 - 1920x1440@60Hz */ | ||||
535 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (234000), .hdisplay = (1920), .hsync_start = (2048), .hsync_end = (2256), .htotal = (2600), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
536 | 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (234000), .hdisplay = (1920), .hsync_start = (2048), .hsync_end = (2256), .htotal = (2600), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
537 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (234000), .hdisplay = (1920), .hsync_start = (2048), .hsync_end = (2256), .htotal = (2600), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
538 | /* 0x4a - 1920x1440@75Hz */ | ||||
539 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2288), .htotal = (2640), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
540 | 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2288), .htotal = (2640), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
541 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2064), .hsync_end = (2288), .htotal = (2640), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1441), .vsync_end = (1444), .vtotal = (1500 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
542 | /* 0x4b - 1920x1440@120Hz RB */ | ||||
543 | { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (380500), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1443), .vsync_end = (1447), .vtotal = (1525 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
544 | 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,.name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (380500), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1443), .vsync_end = (1447), .vtotal = (1525 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
545 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1920x1440", .status = 0, .type = ((1<<6)), .clock = (380500), .hdisplay = (1920), .hsync_start = (1968), .hsync_end = (2000), .htotal = (2080), .hskew = (0), .vdisplay = (1440) , .vsync_start = (1443), .vsync_end = (1447), .vtotal = (1525 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
546 | /* 0x54 - 2048x1152@60Hz */ | ||||
547 | { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,.name = "2048x1152", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (2048), .hsync_start = (2074), .hsync_end = (2154), .htotal = (2250), .hskew = (0), .vdisplay = (1152) , .vsync_start = (1153), .vsync_end = (1156), .vtotal = (1200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
548 | 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,.name = "2048x1152", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (2048), .hsync_start = (2074), .hsync_end = (2154), .htotal = (2250), .hskew = (0), .vdisplay = (1152) , .vsync_start = (1153), .vsync_end = (1156), .vtotal = (1200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
549 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2048x1152", .status = 0, .type = ((1<<6)), .clock = (162000), .hdisplay = (2048), .hsync_start = (2074), .hsync_end = (2154), .htotal = (2250), .hskew = (0), .vdisplay = (1152) , .vsync_start = (1153), .vsync_end = (1156), .vtotal = (1200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, | ||||
550 | /* 0x4c - 2560x1600@60Hz RB */ | ||||
551 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (268500), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1646 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
552 | 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (268500), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1646 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
553 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (268500), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1646 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
554 | /* 0x4d - 2560x1600@60Hz */ | ||||
555 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (348500), .hdisplay = (2560), .hsync_start = (2752), .hsync_end = (3032), .htotal = (3504), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1658 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
556 | 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (348500), .hdisplay = (2560), .hsync_start = (2752), .hsync_end = (3032), .htotal = (3504), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1658 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
557 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (348500), .hdisplay = (2560), .hsync_start = (2752), .hsync_end = (3032), .htotal = (3504), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1658 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
558 | /* 0x4e - 2560x1600@75Hz */ | ||||
559 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (443250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1672 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
560 | 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (443250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1672 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
561 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (443250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1672 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
562 | /* 0x4f - 2560x1600@85Hz */ | ||||
563 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (505250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1682 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
564 | 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (505250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1682 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
565 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (505250), .hdisplay = (2560), .hsync_start = (2768), .hsync_end = (3048), .htotal = (3536), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1682 ), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, | ||||
566 | /* 0x50 - 2560x1600@120Hz RB */ | ||||
567 | { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (552750), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1694 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
568 | 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,.name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (552750), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1694 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
569 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2560x1600", .status = 0, .type = ((1<<6)), .clock = (552750), .hdisplay = (2560), .hsync_start = (2608), .hsync_end = (2640), .htotal = (2720), .hskew = (0), .vdisplay = (1600) , .vsync_start = (1603), .vsync_end = (1609), .vtotal = (1694 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
570 | /* 0x57 - 4096x2160@60Hz RB */ | ||||
571 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556744), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
572 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556744), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
573 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556744), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
574 | /* 0x58 - 4096x2160@59.94Hz RB */ | ||||
575 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556188), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
576 | 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556188), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) | ||||
577 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (556188), .hdisplay = (4096), .hsync_start = (4104), .hsync_end = (4136), .htotal = (4176), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2208), .vsync_end = (2216), .vtotal = (2222 ), .vscan = (0), .flags = ((1<<0) | (1<<3)) }, | ||||
578 | }; | ||||
579 | |||||
580 | /* | ||||
581 | * These more or less come from the DMT spec. The 720x400 modes are | ||||
582 | * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 | ||||
583 | * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode | ||||
584 | * should be 1152x870, again for the Mac, but instead we use the x864 DMT | ||||
585 | * mode. | ||||
586 | * | ||||
587 | * The DMT modes have been fact-checked; the rest are mild guesses. | ||||
588 | */ | ||||
589 | static const struct drm_display_mode edid_est_modes[] = { | ||||
590 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
591 | 968, 1056, 0, 600, 601, 605, 628, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
592 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (40000), .hdisplay = (800), .hsync_start = (840), .hsync_end = (968), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (605), .vtotal = (628), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@60Hz */ | ||||
593 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
594 | 896, 1024, 0, 600, 601, 603, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
595 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (36000), .hdisplay = (800), .hsync_start = (824), .hsync_end = (896), .htotal = (1024), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (603), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@56Hz */ | ||||
596 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
597 | 720, 840, 0, 480, 481, 484, 500, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
598 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (656), .hsync_end = (720), .htotal = (840), .hskew = (0), .vdisplay = (480), . vsync_start = (481), .vsync_end = (484), .vtotal = (500), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@75Hz */ | ||||
599 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
600 | 704, 832, 0, 480, 489, 492, 520, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
601 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (492), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@72Hz */ | ||||
602 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (30240), .hdisplay = (640), .hsync_start = (704), .hsync_end = (768), .htotal = (864), .hskew = (0), .vdisplay = (480), . vsync_start = (483), .vsync_end = (486), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
603 | 768, 864, 0, 480, 483, 486, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (30240), .hdisplay = (640), .hsync_start = (704), .hsync_end = (768), .htotal = (864), .hskew = (0), .vdisplay = (480), . vsync_start = (483), .vsync_end = (486), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
604 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (30240), .hdisplay = (640), .hsync_start = (704), .hsync_end = (768), .htotal = (864), .hskew = (0), .vdisplay = (480), . vsync_start = (483), .vsync_end = (486), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@67Hz */ | ||||
605 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
606 | 752, 800, 0, 480, 490, 492, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
607 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 640x480@60Hz */ | ||||
608 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (421), .vsync_end = (423), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
609 | 846, 900, 0, 400, 421, 423, 449, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (421), .vsync_end = (423), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
610 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (35500), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (421), .vsync_end = (423), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 720x400@88Hz */ | ||||
611 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (28320), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (412), .vsync_end = (414), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
612 | 846, 900, 0, 400, 412, 414, 449, 0,.name = "720x400", .status = 0, .type = ((1<<6)), .clock = (28320), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (412), .vsync_end = (414), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<2)) | ||||
613 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC).name = "720x400", .status = 0, .type = ((1<<6)), .clock = (28320), .hdisplay = (720), .hsync_start = (738), .hsync_end = (846), .htotal = (900), .hskew = (0), .vdisplay = (400), . vsync_start = (412), .vsync_end = (414), .vtotal = (449), .vscan = (0), .flags = ((1<<1) | (1<<2)) }, /* 720x400@70Hz */ | ||||
614 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
615 | 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,.name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
616 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x1024", .status = 0, .type = ((1<<6)), .clock = (135000), .hdisplay = (1280), .hsync_start = (1296), .hsync_end = (1440), .htotal = (1688), .hskew = (0), .vdisplay = (1024) , .vsync_start = (1025), .vsync_end = (1028), .vtotal = (1066 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 1280x1024@75Hz */ | ||||
617 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
618 | 1136, 1312, 0, 768, 769, 772, 800, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
619 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (78750), .hdisplay = (1024), .hsync_start = (1040), .hsync_end = (1136), .htotal = (1312), .hskew = (0), .vdisplay = (768), .vsync_start = (769), .vsync_end = (772), .vtotal = (800), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 1024x768@75Hz */ | ||||
620 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
621 | 1184, 1328, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
622 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (75000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1328), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 1024x768@70Hz */ | ||||
623 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
624 | 1184, 1344, 0, 768, 771, 777, 806, 0,.name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
625 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1024x768", .status = 0, .type = ((1<<6)), .clock = (65000), .hdisplay = (1024), .hsync_start = (1048), .hsync_end = (1184), .htotal = (1344), .hskew = (0), .vdisplay = (768), .vsync_start = (771), .vsync_end = (777), .vtotal = (806), . vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 1024x768@60Hz */ | ||||
626 | { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
627 | 1208, 1264, 0, 768, 768, 776, 817, 0,.name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
628 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE).name = "1024x768i", .status = 0, .type = ((1<<6)), .clock = (44900), .hdisplay = (1024), .hsync_start = (1032), .hsync_end = (1208), .htotal = (1264), .hskew = (0), .vdisplay = (768), .vsync_start = (768), .vsync_end = (776), .vtotal = (817), . vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) }, /* 1024x768@43Hz */ | ||||
629 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,.name = "832x624", .status = 0, .type = ((1<<6)), .clock = (57284), .hdisplay = (832), .hsync_start = (864), .hsync_end = (928), .htotal = (1152), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (628), .vtotal = (667), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
630 | 928, 1152, 0, 624, 625, 628, 667, 0,.name = "832x624", .status = 0, .type = ((1<<6)), .clock = (57284), .hdisplay = (832), .hsync_start = (864), .hsync_end = (928), .htotal = (1152), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (628), .vtotal = (667), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
631 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "832x624", .status = 0, .type = ((1<<6)), .clock = (57284), .hdisplay = (832), .hsync_start = (864), .hsync_end = (928), .htotal = (1152), .hskew = (0), .vdisplay = (624), . vsync_start = (625), .vsync_end = (628), .vtotal = (667), .vscan = (0), .flags = ((1<<1) | (1<<3)) }, /* 832x624@75Hz */ | ||||
632 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
633 | 896, 1056, 0, 600, 601, 604, 625, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
634 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (49500), .hdisplay = (800), .hsync_start = (816), .hsync_end = (896), .htotal = (1056), .hskew = (0), .vdisplay = (600), . vsync_start = (601), .vsync_end = (604), .vtotal = (625), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@75Hz */ | ||||
635 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
636 | 976, 1040, 0, 600, 637, 643, 666, 0,.name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
637 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "800x600", .status = 0, .type = ((1<<6)), .clock = (50000), .hdisplay = (800), .hsync_start = (856), .hsync_end = (976), .htotal = (1040), .hskew = (0), .vdisplay = (600), . vsync_start = (637), .vsync_end = (643), .vtotal = (666), .vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 800x600@72Hz */ | ||||
638 | { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
639 | 1344, 1600, 0, 864, 865, 868, 900, 0,.name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
640 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1152x864", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (1152), .hsync_start = (1216), .hsync_end = (1344), .htotal = (1600), .hskew = (0), .vdisplay = (864), .vsync_start = (865), .vsync_end = (868), .vtotal = (900), . vscan = (0), .flags = ((1<<0) | (1<<2)) }, /* 1152x864@75Hz */ | ||||
641 | }; | ||||
642 | |||||
643 | struct minimode { | ||||
644 | short w; | ||||
645 | short h; | ||||
646 | short r; | ||||
647 | short rb; | ||||
648 | }; | ||||
649 | |||||
650 | static const struct minimode est3_modes[] = { | ||||
651 | /* byte 6 */ | ||||
652 | { 640, 350, 85, 0 }, | ||||
653 | { 640, 400, 85, 0 }, | ||||
654 | { 720, 400, 85, 0 }, | ||||
655 | { 640, 480, 85, 0 }, | ||||
656 | { 848, 480, 60, 0 }, | ||||
657 | { 800, 600, 85, 0 }, | ||||
658 | { 1024, 768, 85, 0 }, | ||||
659 | { 1152, 864, 75, 0 }, | ||||
660 | /* byte 7 */ | ||||
661 | { 1280, 768, 60, 1 }, | ||||
662 | { 1280, 768, 60, 0 }, | ||||
663 | { 1280, 768, 75, 0 }, | ||||
664 | { 1280, 768, 85, 0 }, | ||||
665 | { 1280, 960, 60, 0 }, | ||||
666 | { 1280, 960, 85, 0 }, | ||||
667 | { 1280, 1024, 60, 0 }, | ||||
668 | { 1280, 1024, 85, 0 }, | ||||
669 | /* byte 8 */ | ||||
670 | { 1360, 768, 60, 0 }, | ||||
671 | { 1440, 900, 60, 1 }, | ||||
672 | { 1440, 900, 60, 0 }, | ||||
673 | { 1440, 900, 75, 0 }, | ||||
674 | { 1440, 900, 85, 0 }, | ||||
675 | { 1400, 1050, 60, 1 }, | ||||
676 | { 1400, 1050, 60, 0 }, | ||||
677 | { 1400, 1050, 75, 0 }, | ||||
678 | /* byte 9 */ | ||||
679 | { 1400, 1050, 85, 0 }, | ||||
680 | { 1680, 1050, 60, 1 }, | ||||
681 | { 1680, 1050, 60, 0 }, | ||||
682 | { 1680, 1050, 75, 0 }, | ||||
683 | { 1680, 1050, 85, 0 }, | ||||
684 | { 1600, 1200, 60, 0 }, | ||||
685 | { 1600, 1200, 65, 0 }, | ||||
686 | { 1600, 1200, 70, 0 }, | ||||
687 | /* byte 10 */ | ||||
688 | { 1600, 1200, 75, 0 }, | ||||
689 | { 1600, 1200, 85, 0 }, | ||||
690 | { 1792, 1344, 60, 0 }, | ||||
691 | { 1792, 1344, 75, 0 }, | ||||
692 | { 1856, 1392, 60, 0 }, | ||||
693 | { 1856, 1392, 75, 0 }, | ||||
694 | { 1920, 1200, 60, 1 }, | ||||
695 | { 1920, 1200, 60, 0 }, | ||||
696 | /* byte 11 */ | ||||
697 | { 1920, 1200, 75, 0 }, | ||||
698 | { 1920, 1200, 85, 0 }, | ||||
699 | { 1920, 1440, 60, 0 }, | ||||
700 | { 1920, 1440, 75, 0 }, | ||||
701 | }; | ||||
702 | |||||
703 | static const struct minimode extra_modes[] = { | ||||
704 | { 1024, 576, 60, 0 }, | ||||
705 | { 1366, 768, 60, 0 }, | ||||
706 | { 1600, 900, 60, 0 }, | ||||
707 | { 1680, 945, 60, 0 }, | ||||
708 | { 1920, 1080, 60, 0 }, | ||||
709 | { 2048, 1152, 60, 0 }, | ||||
710 | { 2048, 1536, 60, 0 }, | ||||
711 | }; | ||||
712 | |||||
713 | /* | ||||
714 | * From CEA/CTA-861 spec. | ||||
715 | * | ||||
716 | * Do not access directly, instead always use cea_mode_for_vic(). | ||||
717 | */ | ||||
718 | static const struct drm_display_mode edid_cea_modes_1[] = { | ||||
719 | /* 1 - 640x480@60Hz 4:3 */ | ||||
720 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
721 | 752, 800, 0, 480, 490, 492, 525, 0,.name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
722 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<6)), .clock = (25175), .hdisplay = (640), .hsync_start = (656), .hsync_end = (752), .htotal = (800), .hskew = (0), .vdisplay = (480), . vsync_start = (490), .vsync_end = (492), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
723 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
724 | /* 2 - 720x480@60Hz 4:3 */ | ||||
725 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
726 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
727 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
728 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
729 | /* 3 - 720x480@60Hz 16:9 */ | ||||
730 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
731 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
732 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
733 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
734 | /* 4 - 1280x720@60Hz 16:9 */ | ||||
735 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
736 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
737 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
738 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
739 | /* 5 - 1920x1080i@60Hz 16:9 */ | ||||
740 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
741 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
742 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
743 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
744 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
745 | /* 6 - 720(1440)x480i@60Hz 4:3 */ | ||||
746 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
747 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
748 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
749 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
750 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
751 | /* 7 - 720(1440)x480i@60Hz 16:9 */ | ||||
752 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
753 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
754 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
755 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
756 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
757 | /* 8 - 720(1440)x240@60Hz 4:3 */ | ||||
758 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
759 | 801, 858, 0, 240, 244, 247, 262, 0,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
760 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
761 | DRM_MODE_FLAG_DBLCLK).name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
762 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
763 | /* 9 - 720(1440)x240@60Hz 16:9 */ | ||||
764 | { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
765 | 801, 858, 0, 240, 244, 247, 262, 0,.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
766 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
767 | DRM_MODE_FLAG_DBLCLK).name = "720x240", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (240), . vsync_start = (244), .vsync_end = (247), .vtotal = (262), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
768 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
769 | /* 10 - 2880x480i@60Hz 4:3 */ | ||||
770 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
771 | 3204, 3432, 0, 480, 488, 494, 525, 0,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
772 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
773 | DRM_MODE_FLAG_INTERLACE).name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
774 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
775 | /* 11 - 2880x480i@60Hz 16:9 */ | ||||
776 | { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
777 | 3204, 3432, 0, 480, 488, 494, 525, 0,.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
778 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
779 | DRM_MODE_FLAG_INTERLACE).name = "2880x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (488), .vsync_end = (494), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
780 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
781 | /* 12 - 2880x240@60Hz 4:3 */ | ||||
782 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
783 | 3204, 3432, 0, 240, 244, 247, 262, 0,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
784 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
785 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
786 | /* 13 - 2880x240@60Hz 16:9 */ | ||||
787 | { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
788 | 3204, 3432, 0, 240, 244, 247, 262, 0,.name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
789 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x240", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2956), .hsync_end = (3204), .htotal = (3432), .hskew = (0), .vdisplay = (240), .vsync_start = (244), .vsync_end = (247), .vtotal = (262), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
790 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
791 | /* 14 - 1440x480@60Hz 4:3 */ | ||||
792 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
793 | 1596, 1716, 0, 480, 489, 495, 525, 0,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
794 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
795 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
796 | /* 15 - 1440x480@60Hz 16:9 */ | ||||
797 | { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
798 | 1596, 1716, 0, 480, 489, 495, 525, 0,.name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
799 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1472), .hsync_end = (1596), .htotal = (1716), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
800 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
801 | /* 16 - 1920x1080@60Hz 16:9 */ | ||||
802 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
803 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
804 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
805 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
806 | /* 17 - 720x576@50Hz 4:3 */ | ||||
807 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
808 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
809 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
810 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
811 | /* 18 - 720x576@50Hz 16:9 */ | ||||
812 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
813 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
814 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
815 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
816 | /* 19 - 1280x720@50Hz 16:9 */ | ||||
817 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
818 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
819 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
820 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
821 | /* 20 - 1920x1080i@50Hz 16:9 */ | ||||
822 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
823 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
824 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
825 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
826 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
827 | /* 21 - 720(1440)x576i@50Hz 4:3 */ | ||||
828 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
829 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
830 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
831 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
832 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
833 | /* 22 - 720(1440)x576i@50Hz 16:9 */ | ||||
834 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
835 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
836 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
837 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
838 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
839 | /* 23 - 720(1440)x288@50Hz 4:3 */ | ||||
840 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
841 | 795, 864, 0, 288, 290, 293, 312, 0,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
842 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
843 | DRM_MODE_FLAG_DBLCLK).name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
844 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
845 | /* 24 - 720(1440)x288@50Hz 16:9 */ | ||||
846 | { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
847 | 795, 864, 0, 288, 290, 293, 312, 0,.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
848 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ) | ||||
849 | DRM_MODE_FLAG_DBLCLK).name = "720x288", .status = 0, .type = ((1<<6)), .clock = (13500), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (288), . vsync_start = (290), .vsync_end = (293), .vtotal = (312), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<12) ), | ||||
850 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
851 | /* 25 - 2880x576i@50Hz 4:3 */ | ||||
852 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
853 | 3180, 3456, 0, 576, 580, 586, 625, 0,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
854 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
855 | DRM_MODE_FLAG_INTERLACE).name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
856 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
857 | /* 26 - 2880x576i@50Hz 16:9 */ | ||||
858 | { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
859 | 3180, 3456, 0, 576, 580, 586, 625, 0,.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
860 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)) | ||||
861 | DRM_MODE_FLAG_INTERLACE).name = "2880x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (580), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3) | (1<< 4)), | ||||
862 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
863 | /* 27 - 2880x288@50Hz 4:3 */ | ||||
864 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
865 | 3180, 3456, 0, 288, 290, 293, 312, 0,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
866 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
867 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
868 | /* 28 - 2880x288@50Hz 16:9 */ | ||||
869 | { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
870 | 3180, 3456, 0, 288, 290, 293, 312, 0,.name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
871 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x288", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3180), .htotal = (3456), .hskew = (0), .vdisplay = (288), .vsync_start = (290), .vsync_end = (293), .vtotal = (312), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
872 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
873 | /* 29 - 1440x576@50Hz 4:3 */ | ||||
874 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
875 | 1592, 1728, 0, 576, 581, 586, 625, 0,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
876 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
877 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
878 | /* 30 - 1440x576@50Hz 16:9 */ | ||||
879 | { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
880 | 1592, 1728, 0, 576, 581, 586, 625, 0,.name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
881 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "1440x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (1440), .hsync_start = (1464), .hsync_end = (1592), .htotal = (1728), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
882 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
883 | /* 31 - 1920x1080@50Hz 16:9 */ | ||||
884 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
885 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
886 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
887 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
888 | /* 32 - 1920x1080@24Hz 16:9 */ | ||||
889 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
890 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
891 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
892 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
893 | /* 33 - 1920x1080@25Hz 16:9 */ | ||||
894 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
895 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
896 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
897 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
898 | /* 34 - 1920x1080@30Hz 16:9 */ | ||||
899 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
900 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
901 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
902 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
903 | /* 35 - 2880x480@60Hz 4:3 */ | ||||
904 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
905 | 3192, 3432, 0, 480, 489, 495, 525, 0,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
906 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
907 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
908 | /* 36 - 2880x480@60Hz 16:9 */ | ||||
909 | { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
910 | 3192, 3432, 0, 480, 489, 495, 525, 0,.name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
911 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2944), .hsync_end = (3192), .htotal = (3432), .hskew = (0), .vdisplay = (480), .vsync_start = (489), .vsync_end = (495), .vtotal = (525), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
912 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
913 | /* 37 - 2880x576@50Hz 4:3 */ | ||||
914 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
915 | 3184, 3456, 0, 576, 581, 586, 625, 0,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
916 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
917 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
918 | /* 38 - 2880x576@50Hz 16:9 */ | ||||
919 | { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
920 | 3184, 3456, 0, 576, 581, 586, 625, 0,.name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
921 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "2880x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (2880), .hsync_start = (2928), .hsync_end = (3184), .htotal = (3456), .hskew = (0), .vdisplay = (576), .vsync_start = (581), .vsync_end = (586), .vtotal = (625), . vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
922 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
923 | /* 39 - 1920x1080i@50Hz 16:9 */ | ||||
924 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)) | ||||
925 | 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)) | ||||
926 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)) | ||||
927 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (72000), .hdisplay = (1920), .hsync_start = (1952), .hsync_end = (2120), .htotal = (2304), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1126), .vsync_end = (1136), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<3) | (1<< 4)), | ||||
928 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
929 | /* 40 - 1920x1080i@100Hz 16:9 */ | ||||
930 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
931 | 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
932 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
933 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
934 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
935 | /* 41 - 1280x720@100Hz 16:9 */ | ||||
936 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
937 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
938 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
939 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
940 | /* 42 - 720x576@100Hz 4:3 */ | ||||
941 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
942 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
943 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
944 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
945 | /* 43 - 720x576@100Hz 16:9 */ | ||||
946 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
947 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
948 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
949 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
950 | /* 44 - 720(1440)x576i@100Hz 4:3 */ | ||||
951 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
952 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
953 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
954 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
955 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
956 | /* 45 - 720(1440)x576i@100Hz 16:9 */ | ||||
957 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
958 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
959 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
960 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
961 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
962 | /* 46 - 1920x1080i@120Hz 16:9 */ | ||||
963 | { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
964 | 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
965 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |.name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)) | ||||
966 | DRM_MODE_FLAG_INTERLACE).name = "1920x1080i", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1094), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2) | (1<< 4)), | ||||
967 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
968 | /* 47 - 1280x720@120Hz 16:9 */ | ||||
969 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
970 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
971 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
972 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
973 | /* 48 - 720x480@120Hz 4:3 */ | ||||
974 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
975 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
976 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
977 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
978 | /* 49 - 720x480@120Hz 16:9 */ | ||||
979 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
980 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
981 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
982 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
983 | /* 50 - 720(1440)x480i@120Hz 4:3 */ | ||||
984 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
985 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
986 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
987 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
988 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
989 | /* 51 - 720(1440)x480i@120Hz 16:9 */ | ||||
990 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
991 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
992 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
993 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (27000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
994 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
995 | /* 52 - 720x576@200Hz 4:3 */ | ||||
996 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
997 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
998 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
999 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1000 | /* 53 - 720x576@200Hz 16:9 */ | ||||
1001 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1002 | 796, 864, 0, 576, 581, 586, 625, 0,.name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1003 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x576", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (796), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (581), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1004 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1005 | /* 54 - 720(1440)x576i@200Hz 4:3 */ | ||||
1006 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1007 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1008 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1009 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1010 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1011 | /* 55 - 720(1440)x576i@200Hz 16:9 */ | ||||
1012 | { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1013 | 795, 864, 0, 576, 580, 586, 625, 0,.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1014 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1015 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x576i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (732), .hsync_end = (795), .htotal = (864), .hskew = (0), .vdisplay = (576), . vsync_start = (580), .vsync_end = (586), .vtotal = (625), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1016 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1017 | /* 56 - 720x480@240Hz 4:3 */ | ||||
1018 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1019 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1020 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1021 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1022 | /* 57 - 720x480@240Hz 16:9 */ | ||||
1023 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1024 | 798, 858, 0, 480, 489, 495, 525, 0,.name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)) | ||||
1025 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "720x480", .status = 0, .type = ((1<<6)), .clock = (108000), .hdisplay = (720), .hsync_start = (736), .hsync_end = (798), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (495), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3)), | ||||
1026 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1027 | /* 58 - 720(1440)x480i@240Hz 4:3 */ | ||||
1028 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1029 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1030 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1031 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1032 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, | ||||
1033 | /* 59 - 720(1440)x480i@240Hz 16:9 */ | ||||
1034 | { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1035 | 801, 858, 0, 480, 488, 494, 525, 0,.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1036 | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |.name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)) | ||||
1037 | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK).name = "720x480i", .status = 0, .type = ((1<<6)), .clock = (54000), .hdisplay = (720), .hsync_start = (739), .hsync_end = (801), .htotal = (858), .hskew = (0), .vdisplay = (480), . vsync_start = (488), .vsync_end = (494), .vtotal = (525), .vscan = (0), .flags = ((1<<1) | (1<<3) | (1<<4) | (1<<12)), | ||||
1038 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1039 | /* 60 - 1280x720@24Hz 16:9 */ | ||||
1040 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1041 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1042 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1043 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1044 | /* 61 - 1280x720@25Hz 16:9 */ | ||||
1045 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1046 | 3740, 3960, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1047 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1048 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1049 | /* 62 - 1280x720@30Hz 16:9 */ | ||||
1050 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1051 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1052 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1053 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1054 | /* 63 - 1920x1080@120Hz 16:9 */ | ||||
1055 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1056 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1057 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1058 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1059 | /* 64 - 1920x1080@100Hz 16:9 */ | ||||
1060 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1061 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1062 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1063 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1064 | /* 65 - 1280x720@24Hz 64:27 */ | ||||
1065 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1066 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1067 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1068 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1069 | /* 66 - 1280x720@25Hz 64:27 */ | ||||
1070 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1071 | 3740, 3960, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1072 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3700), .hsync_end = (3740), .htotal = (3960), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1073 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1074 | /* 67 - 1280x720@30Hz 64:27 */ | ||||
1075 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1076 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1077 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1078 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1079 | /* 68 - 1280x720@50Hz 64:27 */ | ||||
1080 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1081 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1082 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1083 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1084 | /* 69 - 1280x720@60Hz 64:27 */ | ||||
1085 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1086 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1087 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1088 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1089 | /* 70 - 1280x720@100Hz 64:27 */ | ||||
1090 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1091 | 1760, 1980, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1092 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1720), .hsync_end = (1760), .htotal = (1980), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1093 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1094 | /* 71 - 1280x720@120Hz 64:27 */ | ||||
1095 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1096 | 1430, 1650, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1097 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1280), .hsync_start = (1390), .hsync_end = (1430), .htotal = (1650), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1098 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1099 | /* 72 - 1920x1080@24Hz 64:27 */ | ||||
1100 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1101 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1102 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1103 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1104 | /* 73 - 1920x1080@25Hz 64:27 */ | ||||
1105 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1106 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1107 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1108 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1109 | /* 74 - 1920x1080@30Hz 64:27 */ | ||||
1110 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1111 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1112 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (74250), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1113 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1114 | /* 75 - 1920x1080@50Hz 64:27 */ | ||||
1115 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1116 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1117 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1118 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1119 | /* 76 - 1920x1080@60Hz 64:27 */ | ||||
1120 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1121 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1122 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1123 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1124 | /* 77 - 1920x1080@100Hz 64:27 */ | ||||
1125 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1126 | 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1127 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2448), .hsync_end = (2492), .htotal = (2640), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1128 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1129 | /* 78 - 1920x1080@120Hz 64:27 */ | ||||
1130 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1131 | 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1132 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (1920), .hsync_start = (2008), .hsync_end = (2052), .htotal = (2200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1133 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1134 | /* 79 - 1680x720@24Hz 64:27 */ | ||||
1135 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1136 | 3080, 3300, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1137 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (3040), .hsync_end = (3080), .htotal = (3300), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1138 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1139 | /* 80 - 1680x720@25Hz 64:27 */ | ||||
1140 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2908), .hsync_end = (2948), .htotal = (3168), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1141 | 2948, 3168, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2908), .hsync_end = (2948), .htotal = (3168), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1142 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2908), .hsync_end = (2948), .htotal = (3168), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1143 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1144 | /* 81 - 1680x720@30Hz 64:27 */ | ||||
1145 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2380), .hsync_end = (2420), .htotal = (2640), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1146 | 2420, 2640, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2380), .hsync_end = (2420), .htotal = (2640), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1147 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (59400), .hdisplay = (1680), .hsync_start = (2380), .hsync_end = (2420), .htotal = (2640), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1148 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1149 | /* 82 - 1680x720@50Hz 64:27 */ | ||||
1150 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (82500), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1151 | 1980, 2200, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (82500), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1152 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (82500), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1153 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1154 | /* 83 - 1680x720@60Hz 64:27 */ | ||||
1155 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1156 | 1980, 2200, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1157 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (1940), .hsync_end = (1980), .htotal = (2200), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1158 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1159 | /* 84 - 1680x720@100Hz 64:27 */ | ||||
1160 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (165000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1161 | 1780, 2000, 0, 720, 725, 730, 825, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (165000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1162 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (165000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1163 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1164 | /* 85 - 1680x720@120Hz 64:27 */ | ||||
1165 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1166 | 1780, 2000, 0, 720, 725, 730, 825, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1167 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (1680), .hsync_start = (1740), .hsync_end = (1780), .htotal = (2000), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (825), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1168 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1169 | /* 86 - 2560x1080@24Hz 64:27 */ | ||||
1170 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1171 | 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1172 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1173 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1174 | /* 87 - 2560x1080@25Hz 64:27 */ | ||||
1175 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (2560), .hsync_start = (3008), .hsync_end = (3052), .htotal = (3200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1176 | 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (2560), .hsync_start = (3008), .hsync_end = (3052), .htotal = (3200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1177 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (2560), .hsync_start = (3008), .hsync_end = (3052), .htotal = (3200), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1178 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1179 | /* 88 - 2560x1080@30Hz 64:27 */ | ||||
1180 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (118800), .hdisplay = (2560), .hsync_start = (3328), .hsync_end = (3372), .htotal = (3520), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1181 | 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (118800), .hdisplay = (2560), .hsync_start = (3328), .hsync_end = (3372), .htotal = (3520), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1182 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (118800), .hdisplay = (2560), .hsync_start = (3328), .hsync_end = (3372), .htotal = (3520), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1183 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1184 | /* 89 - 2560x1080@50Hz 64:27 */ | ||||
1185 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (185625), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1186 | 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (185625), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1187 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (185625), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1188 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1189 | /* 90 - 2560x1080@60Hz 64:27 */ | ||||
1190 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (2808), .hsync_end = (2852), .htotal = (3000), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1191 | 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (2808), .hsync_end = (2852), .htotal = (3000), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1192 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (2808), .hsync_end = (2852), .htotal = (3000), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1193 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1194 | /* 91 - 2560x1080@100Hz 64:27 */ | ||||
1195 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (371250), .hdisplay = (2560), .hsync_start = (2778), .hsync_end = (2822), .htotal = (2970), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1196 | 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (371250), .hdisplay = (2560), .hsync_start = (2778), .hsync_end = (2822), .htotal = (2970), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1197 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (371250), .hdisplay = (2560), .hsync_start = (2778), .hsync_end = (2822), .htotal = (2970), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1198 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1199 | /* 92 - 2560x1080@120Hz 64:27 */ | ||||
1200 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (495000), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1201 | 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (495000), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1202 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (495000), .hdisplay = (2560), .hsync_start = (3108), .hsync_end = (3152), .htotal = (3300), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1203 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1204 | /* 93 - 3840x2160@24Hz 16:9 */ | ||||
1205 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1206 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1207 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1208 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1209 | /* 94 - 3840x2160@25Hz 16:9 */ | ||||
1210 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1211 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1212 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1213 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1214 | /* 95 - 3840x2160@30Hz 16:9 */ | ||||
1215 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1216 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1217 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1218 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1219 | /* 96 - 3840x2160@50Hz 16:9 */ | ||||
1220 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1221 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1222 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1223 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1224 | /* 97 - 3840x2160@60Hz 16:9 */ | ||||
1225 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1226 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1227 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1228 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1229 | /* 98 - 4096x2160@24Hz 256:135 */ | ||||
1230 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1231 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1232 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1233 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1234 | /* 99 - 4096x2160@25Hz 256:135 */ | ||||
1235 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1236 | 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1237 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1238 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1239 | /* 100 - 4096x2160@30Hz 256:135 */ | ||||
1240 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1241 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1242 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1243 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1244 | /* 101 - 4096x2160@50Hz 256:135 */ | ||||
1245 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1246 | 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1247 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5064), .hsync_end = (5152), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1248 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1249 | /* 102 - 4096x2160@60Hz 256:135 */ | ||||
1250 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1251 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1252 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1253 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1254 | /* 103 - 3840x2160@24Hz 64:27 */ | ||||
1255 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1256 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1257 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1258 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1259 | /* 104 - 3840x2160@25Hz 64:27 */ | ||||
1260 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1261 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1262 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1263 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1264 | /* 105 - 3840x2160@30Hz 64:27 */ | ||||
1265 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1266 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1267 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1268 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1269 | /* 106 - 3840x2160@50Hz 64:27 */ | ||||
1270 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1271 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1272 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1273 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1274 | /* 107 - 3840x2160@60Hz 64:27 */ | ||||
1275 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1276 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1277 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1278 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1279 | /* 108 - 1280x720@48Hz 16:9 */ | ||||
1280 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1281 | 2280, 2500, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1282 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1283 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1284 | /* 109 - 1280x720@48Hz 64:27 */ | ||||
1285 | { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1286 | 2280, 2500, 0, 720, 725, 730, 750, 0,.name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1287 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1280x720", .status = 0, .type = ((1<<6)), .clock = (90000), .hdisplay = (1280), .hsync_start = (2240), .hsync_end = (2280), .htotal = (2500), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1288 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1289 | /* 110 - 1680x720@48Hz 64:27 */ | ||||
1290 | { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (2490), .hsync_end = (2530), .htotal = (2750), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1291 | 2530, 2750, 0, 720, 725, 730, 750, 0,.name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (2490), .hsync_end = (2530), .htotal = (2750), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1292 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1680x720", .status = 0, .type = ((1<<6)), .clock = (99000), .hdisplay = (1680), .hsync_start = (2490), .hsync_end = (2530), .htotal = (2750), .hskew = (0), .vdisplay = (720), .vsync_start = (725), .vsync_end = (730), .vtotal = (750), . vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1293 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1294 | /* 111 - 1920x1080@48Hz 16:9 */ | ||||
1295 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1296 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1297 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1298 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1299 | /* 112 - 1920x1080@48Hz 64:27 */ | ||||
1300 | { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1301 | 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,.name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1302 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "1920x1080", .status = 0, .type = ((1<<6)), .clock = (148500), .hdisplay = (1920), .hsync_start = (2558), .hsync_end = (2602), .htotal = (2750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1125 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1303 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1304 | /* 113 - 2560x1080@48Hz 64:27 */ | ||||
1305 | { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1306 | 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,.name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1307 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "2560x1080", .status = 0, .type = ((1<<6)), .clock = (198000), .hdisplay = (2560), .hsync_start = (3558), .hsync_end = (3602), .htotal = (3750), .hskew = (0), .vdisplay = (1080) , .vsync_start = (1084), .vsync_end = (1089), .vtotal = (1100 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1308 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1309 | /* 114 - 3840x2160@48Hz 16:9 */ | ||||
1310 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1311 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1312 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1313 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1314 | /* 115 - 4096x2160@48Hz 256:135 */ | ||||
1315 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1316 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1317 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1318 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1319 | /* 116 - 3840x2160@48Hz 64:27 */ | ||||
1320 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1321 | 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1322 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (594000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1323 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1324 | /* 117 - 3840x2160@100Hz 16:9 */ | ||||
1325 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1326 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1327 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1328 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1329 | /* 118 - 3840x2160@120Hz 16:9 */ | ||||
1330 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1331 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1332 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1333 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1334 | /* 119 - 3840x2160@100Hz 64:27 */ | ||||
1335 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1336 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1337 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1338 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1339 | /* 120 - 3840x2160@120Hz 64:27 */ | ||||
1340 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1341 | 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1342 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1343 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1344 | /* 121 - 5120x2160@24Hz 64:27 */ | ||||
1345 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (7116), .hsync_end = (7204), .htotal = (7500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1346 | 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (7116), .hsync_end = (7204), .htotal = (7500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1347 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (7116), .hsync_end = (7204), .htotal = (7500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1348 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1349 | /* 122 - 5120x2160@25Hz 64:27 */ | ||||
1350 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (6816), .hsync_end = (6904), .htotal = (7200), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1351 | 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (6816), .hsync_end = (6904), .htotal = (7200), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1352 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (6816), .hsync_end = (6904), .htotal = (7200), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1353 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1354 | /* 123 - 5120x2160@30Hz 64:27 */ | ||||
1355 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (5784), .hsync_end = (5872), .htotal = (6000), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1356 | 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (5784), .hsync_end = (5872), .htotal = (6000), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1357 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (396000), .hdisplay = (5120), .hsync_start = (5784), .hsync_end = (5872), .htotal = (6000), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2200 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1358 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1359 | /* 124 - 5120x2160@48Hz 64:27 */ | ||||
1360 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5866), .hsync_end = (5954), .htotal = (6250), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2475 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1361 | 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5866), .hsync_end = (5954), .htotal = (6250), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2475 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1362 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5866), .hsync_end = (5954), .htotal = (6250), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2475 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1363 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1364 | /* 125 - 5120x2160@50Hz 64:27 */ | ||||
1365 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1366 | 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1367 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1368 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1369 | /* 126 - 5120x2160@60Hz 64:27 */ | ||||
1370 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1371 | 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1372 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (742500), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1373 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1374 | /* 127 - 5120x2160@100Hz 64:27 */ | ||||
1375 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1376 | 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1377 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (6216), .hsync_end = (6304), .htotal = (6600), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1378 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1379 | }; | ||||
1380 | |||||
1381 | /* | ||||
1382 | * From CEA/CTA-861 spec. | ||||
1383 | * | ||||
1384 | * Do not access directly, instead always use cea_mode_for_vic(). | ||||
1385 | */ | ||||
1386 | static const struct drm_display_mode edid_cea_modes_193[] = { | ||||
1387 | /* 193 - 5120x2160@120Hz 64:27 */ | ||||
1388 | { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1389 | 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,.name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1390 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "5120x2160", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (5120), .hsync_start = (5284), .hsync_end = (5372), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1391 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1392 | /* 194 - 7680x4320@24Hz 16:9 */ | ||||
1393 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1394 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1395 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1396 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1397 | /* 195 - 7680x4320@25Hz 16:9 */ | ||||
1398 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1399 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1400 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1401 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1402 | /* 196 - 7680x4320@30Hz 16:9 */ | ||||
1403 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1404 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1405 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1406 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1407 | /* 197 - 7680x4320@48Hz 16:9 */ | ||||
1408 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1409 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1410 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1411 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1412 | /* 198 - 7680x4320@50Hz 16:9 */ | ||||
1413 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1414 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1415 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1416 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1417 | /* 199 - 7680x4320@60Hz 16:9 */ | ||||
1418 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1419 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1420 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1421 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1422 | /* 200 - 7680x4320@100Hz 16:9 */ | ||||
1423 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1424 | 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1425 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1426 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1427 | /* 201 - 7680x4320@120Hz 16:9 */ | ||||
1428 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1429 | 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1430 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1431 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1432 | /* 202 - 7680x4320@24Hz 64:27 */ | ||||
1433 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1434 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1435 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1436 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1437 | /* 203 - 7680x4320@25Hz 64:27 */ | ||||
1438 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1439 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1440 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1441 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1442 | /* 204 - 7680x4320@30Hz 64:27 */ | ||||
1443 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1444 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1445 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1446 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1447 | /* 205 - 7680x4320@48Hz 64:27 */ | ||||
1448 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1449 | 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1450 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10232), .hsync_end = (10408), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1451 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1452 | /* 206 - 7680x4320@50Hz 64:27 */ | ||||
1453 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1454 | 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1455 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (10032), .hsync_end = (10208), .htotal = (10800), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1456 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1457 | /* 207 - 7680x4320@60Hz 64:27 */ | ||||
1458 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1459 | 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1460 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (2376000), .hdisplay = (7680), .hsync_start = (8232), .hsync_end = (8408), .htotal = (9000), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1461 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1462 | /* 208 - 7680x4320@100Hz 64:27 */ | ||||
1463 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1464 | 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1465 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (9792), .hsync_end = (9968), .htotal = (10560), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1466 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1467 | /* 209 - 7680x4320@120Hz 64:27 */ | ||||
1468 | { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1469 | 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,.name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1470 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "7680x4320", .status = 0, .type = ((1<<6)), .clock = (4752000), .hdisplay = (7680), .hsync_start = (8032), .hsync_end = (8208), .htotal = (8800), .hskew = (0), .vdisplay = (4320) , .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1471 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1472 | /* 210 - 10240x4320@24Hz 64:27 */ | ||||
1473 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1474 | 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1475 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1476 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1477 | /* 211 - 10240x4320@25Hz 64:27 */ | ||||
1478 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1479 | 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1480 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1481 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1482 | /* 212 - 10240x4320@30Hz 64:27 */ | ||||
1483 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1484 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1485 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (1485000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1486 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1487 | /* 213 - 10240x4320@48Hz 64:27 */ | ||||
1488 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1489 | 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1490 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (11732), .hsync_end = (11908), .htotal = (12500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4950 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1491 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1492 | /* 214 - 10240x4320@50Hz 64:27 */ | ||||
1493 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1494 | 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1495 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (12732), .hsync_end = (12908), .htotal = (13500), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4400 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1496 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1497 | /* 215 - 10240x4320@60Hz 64:27 */ | ||||
1498 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1499 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1500 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (2970000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1501 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1502 | /* 216 - 10240x4320@100Hz 64:27 */ | ||||
1503 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (12432), .hsync_end = (12608), .htotal = (13200), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1504 | 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (12432), .hsync_end = (12608), .htotal = (13200), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1505 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (12432), .hsync_end = (12608), .htotal = (13200), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1506 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1507 | /* 217 - 10240x4320@120Hz 64:27 */ | ||||
1508 | { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1509 | 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,.name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1510 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "10240x4320", .status = 0, .type = ((1<<6)), .clock = (5940000), .hdisplay = (10240), .hsync_start = (10528), .hsync_end = (10704), .htotal = (11000), .hskew = (0), .vdisplay = (4320 ), .vsync_start = (4336), .vsync_end = (4356), .vtotal = (4500 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1511 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, | ||||
1512 | /* 218 - 4096x2160@100Hz 256:135 */ | ||||
1513 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1514 | 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1515 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1516 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1517 | /* 219 - 4096x2160@120Hz 256:135 */ | ||||
1518 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1519 | 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1520 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (1188000), .hdisplay = (4096), .hsync_start = (4184), .hsync_end = (4272), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1521 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1522 | }; | ||||
1523 | |||||
1524 | /* | ||||
1525 | * HDMI 1.4 4k modes. Index using the VIC. | ||||
1526 | */ | ||||
1527 | static const struct drm_display_mode edid_4k_modes[] = { | ||||
1528 | /* 0 - dummy, VICs start at 1 */ | ||||
1529 | { }, | ||||
1530 | /* 1 - 3840x2160@30Hz */ | ||||
1531 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1532 | 3840, 4016, 4104, 4400, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1533 | 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1534 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4016), .hsync_end = (4104), .htotal = (4400), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1535 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1536 | /* 2 - 3840x2160@25Hz */ | ||||
1537 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1538 | 3840, 4896, 4984, 5280, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1539 | 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1540 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (4896), .hsync_end = (4984), .htotal = (5280), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1541 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1542 | /* 3 - 3840x2160@24Hz */ | ||||
1543 | { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1544 | 3840, 5116, 5204, 5500, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1545 | 2160, 2168, 2178, 2250, 0,.name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1546 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "3840x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (3840), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1547 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, | ||||
1548 | /* 4 - 4096x2160@24Hz (SMPTE) */ | ||||
1549 | { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1550 | 4096, 5116, 5204, 5500, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1551 | 2160, 2168, 2178, 2250, 0,.name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)) | ||||
1552 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC).name = "4096x2160", .status = 0, .type = ((1<<6)), .clock = (297000), .hdisplay = (4096), .hsync_start = (5116), .hsync_end = (5204), .htotal = (5500), .hskew = (0), .vdisplay = (2160) , .vsync_start = (2168), .vsync_end = (2178), .vtotal = (2250 ), .vscan = (0), .flags = ((1<<0) | (1<<2)), | ||||
1553 | .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, | ||||
1554 | }; | ||||
1555 | |||||
1556 | /*** DDC fetch and block validation ***/ | ||||
1557 | |||||
1558 | static const u8 edid_header[] = { | ||||
1559 | 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 | ||||
1560 | }; | ||||
1561 | |||||
1562 | /** | ||||
1563 | * drm_edid_header_is_valid - sanity check the header of the base EDID block | ||||
1564 | * @raw_edid: pointer to raw base EDID block | ||||
1565 | * | ||||
1566 | * Sanity check the header of the base EDID block. | ||||
1567 | * | ||||
1568 | * Return: 8 if the header is perfect, down to 0 if it's totally wrong. | ||||
1569 | */ | ||||
1570 | int drm_edid_header_is_valid(const u8 *raw_edid) | ||||
1571 | { | ||||
1572 | int i, score = 0; | ||||
1573 | |||||
1574 | for (i = 0; i < sizeof(edid_header); i++) | ||||
1575 | if (raw_edid[i] == edid_header[i]) | ||||
1576 | score++; | ||||
1577 | |||||
1578 | return score; | ||||
1579 | } | ||||
1580 | EXPORT_SYMBOL(drm_edid_header_is_valid); | ||||
1581 | |||||
1582 | static int edid_fixup __read_mostly = 6; | ||||
1583 | module_param_named(edid_fixup, edid_fixup, int, 0400); | ||||
1584 | MODULE_PARM_DESC(edid_fixup, | ||||
1585 | "Minimum number of valid EDID header bytes (0-8, default 6)"); | ||||
1586 | |||||
1587 | static int validate_displayid(u8 *displayid, int length, int idx); | ||||
1588 | |||||
1589 | static int drm_edid_block_checksum(const u8 *raw_edid) | ||||
1590 | { | ||||
1591 | int i; | ||||
1592 | u8 csum = 0, crc = 0; | ||||
1593 | |||||
1594 | for (i = 0; i < EDID_LENGTH128 - 1; i++) | ||||
1595 | csum += raw_edid[i]; | ||||
1596 | |||||
1597 | crc = 0x100 - csum; | ||||
1598 | |||||
1599 | return crc; | ||||
1600 | } | ||||
1601 | |||||
1602 | static bool_Bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum) | ||||
1603 | { | ||||
1604 | if (raw_edid[EDID_LENGTH128 - 1] != real_checksum) | ||||
1605 | return true1; | ||||
1606 | else | ||||
1607 | return false0; | ||||
1608 | } | ||||
1609 | |||||
1610 | static bool_Bool drm_edid_is_zero(const u8 *in_edid, int length) | ||||
1611 | { | ||||
1612 | if (memchr_inv(in_edid, 0, length)) | ||||
1613 | return false0; | ||||
1614 | |||||
1615 | return true1; | ||||
1616 | } | ||||
1617 | |||||
1618 | /** | ||||
1619 | * drm_edid_are_equal - compare two edid blobs. | ||||
1620 | * @edid1: pointer to first blob | ||||
1621 | * @edid2: pointer to second blob | ||||
1622 | * This helper can be used during probing to determine if | ||||
1623 | * edid had changed. | ||||
1624 | */ | ||||
1625 | bool_Bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2) | ||||
1626 | { | ||||
1627 | int edid1_len, edid2_len; | ||||
1628 | bool_Bool edid1_present = edid1 != NULL((void *)0); | ||||
1629 | bool_Bool edid2_present = edid2 != NULL((void *)0); | ||||
1630 | |||||
1631 | if (edid1_present != edid2_present) | ||||
1632 | return false0; | ||||
1633 | |||||
1634 | if (edid1) { | ||||
1635 | edid1_len = EDID_LENGTH128 * (1 + edid1->extensions); | ||||
1636 | edid2_len = EDID_LENGTH128 * (1 + edid2->extensions); | ||||
1637 | |||||
1638 | if (edid1_len != edid2_len) | ||||
1639 | return false0; | ||||
1640 | |||||
1641 | if (memcmp(edid1, edid2, edid1_len)__builtin_memcmp((edid1), (edid2), (edid1_len))) | ||||
1642 | return false0; | ||||
1643 | } | ||||
1644 | |||||
1645 | return true1; | ||||
1646 | } | ||||
1647 | EXPORT_SYMBOL(drm_edid_are_equal); | ||||
1648 | |||||
1649 | /** | ||||
1650 | * drm_edid_block_valid - Sanity check the EDID block (base or extension) | ||||
1651 | * @raw_edid: pointer to raw EDID block | ||||
1652 | * @block: type of block to validate (0 for base, extension otherwise) | ||||
1653 | * @print_bad_edid: if true, dump bad EDID blocks to the console | ||||
1654 | * @edid_corrupt: if true, the header or checksum is invalid | ||||
1655 | * | ||||
1656 | * Validate a base or extension EDID block and optionally dump bad blocks to | ||||
1657 | * the console. | ||||
1658 | * | ||||
1659 | * Return: True if the block is valid, false otherwise. | ||||
1660 | */ | ||||
1661 | bool_Bool drm_edid_block_valid(u8 *raw_edid, int block, bool_Bool print_bad_edid, | ||||
1662 | bool_Bool *edid_corrupt) | ||||
1663 | { | ||||
1664 | u8 csum; | ||||
1665 | struct edid *edid = (struct edid *)raw_edid; | ||||
1666 | |||||
1667 | if (WARN_ON(!raw_edid)({ int __ret = !!(!raw_edid); if (__ret) printf("WARNING %s failed at %s:%d\n" , "!raw_edid", "/usr/src/sys/dev/pci/drm/drm_edid.c", 1667); __builtin_expect (!!(__ret), 0); })) | ||||
1668 | return false0; | ||||
1669 | |||||
1670 | if (edid_fixup > 8 || edid_fixup < 0) | ||||
1671 | edid_fixup = 6; | ||||
1672 | |||||
1673 | if (block == 0) { | ||||
1674 | int score = drm_edid_header_is_valid(raw_edid); | ||||
1675 | |||||
1676 | if (score == 8) { | ||||
1677 | if (edid_corrupt) | ||||
1678 | *edid_corrupt = false0; | ||||
1679 | } else if (score >= edid_fixup) { | ||||
1680 | /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 | ||||
1681 | * The corrupt flag needs to be set here otherwise, the | ||||
1682 | * fix-up code here will correct the problem, the | ||||
1683 | * checksum is correct and the test fails | ||||
1684 | */ | ||||
1685 | if (edid_corrupt) | ||||
1686 | *edid_corrupt = true1; | ||||
1687 | DRM_DEBUG("Fixing EDID header, your hardware may be failing\n")__drm_dbg(DRM_UT_CORE, "Fixing EDID header, your hardware may be failing\n" ); | ||||
1688 | memcpy(raw_edid, edid_header, sizeof(edid_header))__builtin_memcpy((raw_edid), (edid_header), (sizeof(edid_header ))); | ||||
1689 | } else { | ||||
1690 | if (edid_corrupt) | ||||
1691 | *edid_corrupt = true1; | ||||
1692 | goto bad; | ||||
1693 | } | ||||
1694 | } | ||||
1695 | |||||
1696 | csum = drm_edid_block_checksum(raw_edid); | ||||
1697 | if (drm_edid_block_checksum_diff(raw_edid, csum)) { | ||||
1698 | if (edid_corrupt) | ||||
1699 | *edid_corrupt = true1; | ||||
1700 | |||||
1701 | /* allow CEA to slide through, switches mangle this */ | ||||
1702 | if (raw_edid[0] == CEA_EXT0x02) { | ||||
1703 | DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum)__drm_dbg(DRM_UT_CORE, "EDID checksum is invalid, remainder is %d\n" , csum); | ||||
1704 | DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n")__drm_dbg(DRM_UT_CORE, "Assuming a KVM switch modified the CEA block but left the original checksum\n" ); | ||||
1705 | } else { | ||||
1706 | if (print_bad_edid) | ||||
1707 | DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum)printk("\0015" "[" "drm" "] " "EDID checksum is invalid, remainder is %d\n" , csum); | ||||
1708 | |||||
1709 | goto bad; | ||||
1710 | } | ||||
1711 | } | ||||
1712 | |||||
1713 | /* per-block-type checks */ | ||||
1714 | switch (raw_edid[0]) { | ||||
1715 | case 0: /* base */ | ||||
1716 | if (edid->version != 1) { | ||||
1717 | DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version)printk("\0015" "[" "drm" "] " "EDID has major version %d, instead of 1\n" , edid->version); | ||||
1718 | goto bad; | ||||
1719 | } | ||||
1720 | |||||
1721 | if (edid->revision > 4) | ||||
1722 | DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n")__drm_dbg(DRM_UT_CORE, "EDID minor > 4, assuming backward compatibility\n" ); | ||||
1723 | break; | ||||
1724 | |||||
1725 | default: | ||||
1726 | break; | ||||
1727 | } | ||||
1728 | |||||
1729 | return true1; | ||||
1730 | |||||
1731 | bad: | ||||
1732 | if (print_bad_edid) { | ||||
1733 | if (drm_edid_is_zero(raw_edid, EDID_LENGTH128)) { | ||||
1734 | pr_notice("EDID block is all zeroes\n")printk("\0015" "EDID block is all zeroes\n"); | ||||
1735 | } else { | ||||
1736 | pr_notice("Raw EDID:\n")printk("\0015" "Raw EDID:\n"); | ||||
1737 | print_hex_dump(KERN_NOTICE"\0015", | ||||
1738 | " \t", DUMP_PREFIX_NONE, 16, 1, | ||||
1739 | raw_edid, EDID_LENGTH128, false0); | ||||
1740 | } | ||||
1741 | } | ||||
1742 | return false0; | ||||
1743 | } | ||||
1744 | EXPORT_SYMBOL(drm_edid_block_valid); | ||||
1745 | |||||
1746 | /** | ||||
1747 | * drm_edid_is_valid - sanity check EDID data | ||||
1748 | * @edid: EDID data | ||||
1749 | * | ||||
1750 | * Sanity-check an entire EDID record (including extensions) | ||||
1751 | * | ||||
1752 | * Return: True if the EDID data is valid, false otherwise. | ||||
1753 | */ | ||||
1754 | bool_Bool drm_edid_is_valid(struct edid *edid) | ||||
1755 | { | ||||
1756 | int i; | ||||
1757 | u8 *raw = (u8 *)edid; | ||||
1758 | |||||
1759 | if (!edid) | ||||
1760 | return false0; | ||||
1761 | |||||
1762 | for (i = 0; i <= edid->extensions; i++) | ||||
1763 | if (!drm_edid_block_valid(raw + i * EDID_LENGTH128, i, true1, NULL((void *)0))) | ||||
1764 | return false0; | ||||
1765 | |||||
1766 | return true1; | ||||
1767 | } | ||||
1768 | EXPORT_SYMBOL(drm_edid_is_valid); | ||||
1769 | |||||
1770 | #define DDC_SEGMENT_ADDR0x30 0x30 | ||||
1771 | /** | ||||
1772 | * drm_do_probe_ddc_edid() - get EDID information via I2C | ||||
1773 | * @data: I2C device adapter | ||||
1774 | * @buf: EDID data buffer to be filled | ||||
1775 | * @block: 128 byte EDID block to start fetching from | ||||
1776 | * @len: EDID data buffer length to fetch | ||||
1777 | * | ||||
1778 | * Try to fetch EDID information by calling I2C driver functions. | ||||
1779 | * | ||||
1780 | * Return: 0 on success or -1 on failure. | ||||
1781 | */ | ||||
1782 | static int | ||||
1783 | drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) | ||||
1784 | { | ||||
1785 | struct i2c_adapter *adapter = data; | ||||
1786 | unsigned char start = block * EDID_LENGTH128; | ||||
1787 | unsigned char segment = block >> 1; | ||||
1788 | unsigned char xfers = segment ? 3 : 2; | ||||
1789 | int ret, retries = 5; | ||||
1790 | |||||
1791 | /* | ||||
1792 | * The core I2C driver will automatically retry the transfer if the | ||||
1793 | * adapter reports EAGAIN. However, we find that bit-banging transfers | ||||
1794 | * are susceptible to errors under a heavily loaded machine and | ||||
1795 | * generate spurious NAKs and timeouts. Retrying the transfer | ||||
1796 | * of the individual block a few times seems to overcome this. | ||||
1797 | */ | ||||
1798 | do { | ||||
1799 | struct i2c_msg msgs[] = { | ||||
1800 | { | ||||
1801 | .addr = DDC_SEGMENT_ADDR0x30, | ||||
1802 | .flags = 0, | ||||
1803 | .len = 1, | ||||
1804 | .buf = &segment, | ||||
1805 | }, { | ||||
1806 | .addr = DDC_ADDR0x50, | ||||
1807 | .flags = 0, | ||||
1808 | .len = 1, | ||||
1809 | .buf = &start, | ||||
1810 | }, { | ||||
1811 | .addr = DDC_ADDR0x50, | ||||
1812 | .flags = I2C_M_RD0x0001, | ||||
1813 | .len = len, | ||||
1814 | .buf = buf, | ||||
1815 | } | ||||
1816 | }; | ||||
1817 | |||||
1818 | /* | ||||
1819 | * Avoid sending the segment addr to not upset non-compliant | ||||
1820 | * DDC monitors. | ||||
1821 | */ | ||||
1822 | ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); | ||||
1823 | |||||
1824 | if (ret == -ENXIO6) { | ||||
1825 | DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",__drm_dbg(DRM_UT_KMS, "drm: skipping non-existent adapter %s\n" , adapter->name) | ||||
1826 | adapter->name)__drm_dbg(DRM_UT_KMS, "drm: skipping non-existent adapter %s\n" , adapter->name); | ||||
1827 | break; | ||||
1828 | } | ||||
1829 | } while (ret != xfers && --retries); | ||||
1830 | |||||
1831 | return ret == xfers ? 0 : -1; | ||||
1832 | } | ||||
1833 | |||||
1834 | static void connector_bad_edid(struct drm_connector *connector, | ||||
1835 | u8 *edid, int num_blocks) | ||||
1836 | { | ||||
1837 | int i; | ||||
1838 | u8 last_block; | ||||
1839 | |||||
1840 | /* | ||||
1841 | * 0x7e in the EDID is the number of extension blocks. The EDID | ||||
1842 | * is 1 (base block) + num_ext_blocks big. That means we can think | ||||
1843 | * of 0x7e in the EDID of the _index_ of the last block in the | ||||
1844 | * combined chunk of memory. | ||||
1845 | */ | ||||
1846 | last_block = edid[0x7e]; | ||||
1847 | |||||
1848 | /* Calculate real checksum for the last edid extension block data */ | ||||
1849 | if (last_block < num_blocks) | ||||
1850 | connector->real_edid_checksum = | ||||
1851 | drm_edid_block_checksum(edid + last_block * EDID_LENGTH128); | ||||
1852 | |||||
1853 | if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) | ||||
1854 | return; | ||||
1855 | |||||
1856 | drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name)printf("drm:pid%d:%s *WARNING* " "[drm] " "%s: EDID is invalid:\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , connector ->name); | ||||
1857 | for (i = 0; i < num_blocks; i++) { | ||||
1858 | u8 *block = edid + i * EDID_LENGTH128; | ||||
1859 | char prefix[20]; | ||||
1860 | |||||
1861 | if (drm_edid_is_zero(block, EDID_LENGTH128)) | ||||
1862 | snprintf(prefix, sizeof(prefix), "\t[%02x] ZERO ", i); | ||||
1863 | else if (!drm_edid_block_valid(block, i, false0, NULL((void *)0))) | ||||
1864 | snprintf(prefix, sizeof(prefix), "\t[%02x] BAD ", i); | ||||
1865 | else | ||||
1866 | snprintf(prefix, sizeof(prefix), "\t[%02x] GOOD ", i); | ||||
1867 | |||||
1868 | print_hex_dump(KERN_WARNING"\0014", | ||||
1869 | prefix, DUMP_PREFIX_NONE, 16, 1, | ||||
1870 | block, EDID_LENGTH128, false0); | ||||
1871 | } | ||||
1872 | } | ||||
1873 | |||||
1874 | /* Get override or firmware EDID */ | ||||
1875 | static struct edid *drm_get_override_edid(struct drm_connector *connector) | ||||
1876 | { | ||||
1877 | struct edid *override = NULL((void *)0); | ||||
1878 | |||||
1879 | if (connector->override_edid) | ||||
1880 | override = drm_edid_duplicate(connector->edid_blob_ptr->data); | ||||
1881 | |||||
1882 | if (!override
| ||||
1883 | override = drm_load_edid_firmware(connector); | ||||
1884 | |||||
1885 | return IS_ERR(override) ? NULL((void *)0) : override; | ||||
| |||||
1886 | } | ||||
1887 | |||||
1888 | /** | ||||
1889 | * drm_add_override_edid_modes - add modes from override/firmware EDID | ||||
1890 | * @connector: connector we're probing | ||||
1891 | * | ||||
1892 | * Add modes from the override/firmware EDID, if available. Only to be used from | ||||
1893 | * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe | ||||
1894 | * failed during drm_get_edid() and caused the override/firmware EDID to be | ||||
1895 | * skipped. | ||||
1896 | * | ||||
1897 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
1898 | */ | ||||
1899 | int drm_add_override_edid_modes(struct drm_connector *connector) | ||||
1900 | { | ||||
1901 | struct edid *override; | ||||
1902 | int num_modes = 0; | ||||
1903 | |||||
1904 | override = drm_get_override_edid(connector); | ||||
| |||||
1905 | if (override) { | ||||
1906 | drm_connector_update_edid_property(connector, override); | ||||
1907 | num_modes = drm_add_edid_modes(connector, override); | ||||
1908 | kfree(override); | ||||
1909 | |||||
1910 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",__drm_dbg(DRM_UT_KMS, "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n" , connector->base.id, connector->name, num_modes) | ||||
1911 | connector->base.id, connector->name, num_modes)__drm_dbg(DRM_UT_KMS, "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n" , connector->base.id, connector->name, num_modes); | ||||
1912 | } | ||||
1913 | |||||
1914 | return num_modes; | ||||
1915 | } | ||||
1916 | EXPORT_SYMBOL(drm_add_override_edid_modes); | ||||
1917 | |||||
1918 | /** | ||||
1919 | * drm_do_get_edid - get EDID data using a custom EDID block read function | ||||
1920 | * @connector: connector we're probing | ||||
1921 | * @get_edid_block: EDID block read function | ||||
1922 | * @data: private data passed to the block read function | ||||
1923 | * | ||||
1924 | * When the I2C adapter connected to the DDC bus is hidden behind a device that | ||||
1925 | * exposes a different interface to read EDID blocks this function can be used | ||||
1926 | * to get EDID data using a custom block read function. | ||||
1927 | * | ||||
1928 | * As in the general case the DDC bus is accessible by the kernel at the I2C | ||||
1929 | * level, drivers must make all reasonable efforts to expose it as an I2C | ||||
1930 | * adapter and use drm_get_edid() instead of abusing this function. | ||||
1931 | * | ||||
1932 | * The EDID may be overridden using debugfs override_edid or firmare EDID | ||||
1933 | * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority | ||||
1934 | * order. Having either of them bypasses actual EDID reads. | ||||
1935 | * | ||||
1936 | * Return: Pointer to valid EDID or NULL if we couldn't find any. | ||||
1937 | */ | ||||
1938 | struct edid *drm_do_get_edid(struct drm_connector *connector, | ||||
1939 | int (*get_edid_block)(void *data, u8 *buf, unsigned int block, | ||||
1940 | size_t len), | ||||
1941 | void *data) | ||||
1942 | { | ||||
1943 | int i, j = 0, valid_extensions = 0; | ||||
1944 | u8 *edid, *new; | ||||
1945 | struct edid *override; | ||||
1946 | |||||
1947 | override = drm_get_override_edid(connector); | ||||
1948 | if (override) | ||||
1949 | return override; | ||||
1950 | |||||
1951 | if ((edid = kmalloc(EDID_LENGTH128, GFP_KERNEL(0x0001 | 0x0004))) == NULL((void *)0)) | ||||
1952 | return NULL((void *)0); | ||||
1953 | |||||
1954 | /* base block fetch */ | ||||
1955 | for (i = 0; i < 4; i++) { | ||||
1956 | if (get_edid_block(data, edid, 0, EDID_LENGTH128)) | ||||
1957 | goto out; | ||||
1958 | if (drm_edid_block_valid(edid, 0, false0, | ||||
1959 | &connector->edid_corrupt)) | ||||
1960 | break; | ||||
1961 | if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH128)) { | ||||
1962 | connector->null_edid_counter++; | ||||
1963 | goto carp; | ||||
1964 | } | ||||
1965 | } | ||||
1966 | if (i == 4) | ||||
1967 | goto carp; | ||||
1968 | |||||
1969 | /* if there's no extensions, we're done */ | ||||
1970 | valid_extensions = edid[0x7e]; | ||||
1971 | if (valid_extensions == 0) | ||||
1972 | return (struct edid *)edid; | ||||
1973 | |||||
1974 | #ifdef __linux__ | ||||
1975 | new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH128, GFP_KERNEL(0x0001 | 0x0004)); | ||||
1976 | if (!new) | ||||
1977 | goto out; | ||||
1978 | #else | ||||
1979 | new = kmalloc((valid_extensions + 1) * EDID_LENGTH128, GFP_KERNEL(0x0001 | 0x0004)); | ||||
1980 | if (!new) | ||||
1981 | goto out; | ||||
1982 | memcpy(new, edid, EDID_LENGTH)__builtin_memcpy((new), (edid), (128)); | ||||
1983 | kfree(edid); | ||||
1984 | #endif | ||||
1985 | edid = new; | ||||
1986 | |||||
1987 | for (j = 1; j <= edid[0x7e]; j++) { | ||||
1988 | u8 *block = edid + j * EDID_LENGTH128; | ||||
1989 | |||||
1990 | for (i = 0; i < 4; i++) { | ||||
1991 | if (get_edid_block(data, block, j, EDID_LENGTH128)) | ||||
1992 | goto out; | ||||
1993 | if (drm_edid_block_valid(block, j, false0, NULL((void *)0))) | ||||
1994 | break; | ||||
1995 | } | ||||
1996 | |||||
1997 | if (i == 4) | ||||
1998 | valid_extensions--; | ||||
1999 | } | ||||
2000 | |||||
2001 | if (valid_extensions != edid[0x7e]) { | ||||
2002 | u8 *base; | ||||
2003 | |||||
2004 | connector_bad_edid(connector, edid, edid[0x7e] + 1); | ||||
2005 | |||||
2006 | edid[EDID_LENGTH128-1] += edid[0x7e] - valid_extensions; | ||||
2007 | edid[0x7e] = valid_extensions; | ||||
2008 | |||||
2009 | new = kmalloc_array(valid_extensions + 1, EDID_LENGTH128, | ||||
2010 | GFP_KERNEL(0x0001 | 0x0004)); | ||||
2011 | if (!new) | ||||
2012 | goto out; | ||||
2013 | |||||
2014 | base = new; | ||||
2015 | for (i = 0; i <= edid[0x7e]; i++) { | ||||
2016 | u8 *block = edid + i * EDID_LENGTH128; | ||||
2017 | |||||
2018 | if (!drm_edid_block_valid(block, i, false0, NULL((void *)0))) | ||||
2019 | continue; | ||||
2020 | |||||
2021 | memcpy(base, block, EDID_LENGTH)__builtin_memcpy((base), (block), (128)); | ||||
2022 | base += EDID_LENGTH128; | ||||
2023 | } | ||||
2024 | |||||
2025 | kfree(edid); | ||||
2026 | edid = new; | ||||
2027 | } | ||||
2028 | |||||
2029 | return (struct edid *)edid; | ||||
2030 | |||||
2031 | carp: | ||||
2032 | connector_bad_edid(connector, edid, 1); | ||||
2033 | out: | ||||
2034 | kfree(edid); | ||||
2035 | return NULL((void *)0); | ||||
2036 | } | ||||
2037 | EXPORT_SYMBOL_GPL(drm_do_get_edid); | ||||
2038 | |||||
2039 | /** | ||||
2040 | * drm_probe_ddc() - probe DDC presence | ||||
2041 | * @adapter: I2C adapter to probe | ||||
2042 | * | ||||
2043 | * Return: True on success, false on failure. | ||||
2044 | */ | ||||
2045 | bool_Bool | ||||
2046 | drm_probe_ddc(struct i2c_adapter *adapter) | ||||
2047 | { | ||||
2048 | unsigned char out; | ||||
2049 | |||||
2050 | return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); | ||||
2051 | } | ||||
2052 | EXPORT_SYMBOL(drm_probe_ddc); | ||||
2053 | |||||
2054 | /** | ||||
2055 | * drm_get_edid - get EDID data, if available | ||||
2056 | * @connector: connector we're probing | ||||
2057 | * @adapter: I2C adapter to use for DDC | ||||
2058 | * | ||||
2059 | * Poke the given I2C channel to grab EDID data if possible. If found, | ||||
2060 | * attach it to the connector. | ||||
2061 | * | ||||
2062 | * Return: Pointer to valid EDID or NULL if we couldn't find any. | ||||
2063 | */ | ||||
2064 | struct edid *drm_get_edid(struct drm_connector *connector, | ||||
2065 | struct i2c_adapter *adapter) | ||||
2066 | { | ||||
2067 | struct edid *edid; | ||||
2068 | |||||
2069 | if (connector->force == DRM_FORCE_OFF) | ||||
2070 | return NULL((void *)0); | ||||
2071 | |||||
2072 | if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) | ||||
2073 | return NULL((void *)0); | ||||
2074 | |||||
2075 | edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); | ||||
2076 | drm_connector_update_edid_property(connector, edid); | ||||
2077 | return edid; | ||||
2078 | } | ||||
2079 | EXPORT_SYMBOL(drm_get_edid); | ||||
2080 | |||||
2081 | /** | ||||
2082 | * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output | ||||
2083 | * @connector: connector we're probing | ||||
2084 | * @adapter: I2C adapter to use for DDC | ||||
2085 | * | ||||
2086 | * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of | ||||
2087 | * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily | ||||
2088 | * switch DDC to the GPU which is retrieving EDID. | ||||
2089 | * | ||||
2090 | * Return: Pointer to valid EDID or %NULL if we couldn't find any. | ||||
2091 | */ | ||||
2092 | struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, | ||||
2093 | struct i2c_adapter *adapter) | ||||
2094 | { | ||||
2095 | struct pci_dev *pdev = connector->dev->pdev; | ||||
2096 | struct edid *edid; | ||||
2097 | |||||
2098 | vga_switcheroo_lock_ddc(pdev); | ||||
2099 | edid = drm_get_edid(connector, adapter); | ||||
2100 | vga_switcheroo_unlock_ddc(pdev); | ||||
2101 | |||||
2102 | return edid; | ||||
2103 | } | ||||
2104 | EXPORT_SYMBOL(drm_get_edid_switcheroo); | ||||
2105 | |||||
2106 | /** | ||||
2107 | * drm_edid_duplicate - duplicate an EDID and the extensions | ||||
2108 | * @edid: EDID to duplicate | ||||
2109 | * | ||||
2110 | * Return: Pointer to duplicated EDID or NULL on allocation failure. | ||||
2111 | */ | ||||
2112 | struct edid *drm_edid_duplicate(const struct edid *edid) | ||||
2113 | { | ||||
2114 | return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH128, GFP_KERNEL(0x0001 | 0x0004)); | ||||
2115 | } | ||||
2116 | EXPORT_SYMBOL(drm_edid_duplicate); | ||||
2117 | |||||
2118 | /*** EDID parsing ***/ | ||||
2119 | |||||
2120 | /** | ||||
2121 | * edid_vendor - match a string against EDID's obfuscated vendor field | ||||
2122 | * @edid: EDID to match | ||||
2123 | * @vendor: vendor string | ||||
2124 | * | ||||
2125 | * Returns true if @vendor is in @edid, false otherwise | ||||
2126 | */ | ||||
2127 | static bool_Bool edid_vendor(const struct edid *edid, const char *vendor) | ||||
2128 | { | ||||
2129 | char edid_vendor[3]; | ||||
2130 | |||||
2131 | edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; | ||||
2132 | edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | | ||||
2133 | ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; | ||||
2134 | edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; | ||||
2135 | |||||
2136 | return !strncmp(edid_vendor, vendor, 3); | ||||
2137 | } | ||||
2138 | |||||
2139 | /** | ||||
2140 | * edid_get_quirks - return quirk flags for a given EDID | ||||
2141 | * @edid: EDID to process | ||||
2142 | * | ||||
2143 | * This tells subsequent routines what fixes they need to apply. | ||||
2144 | */ | ||||
2145 | static u32 edid_get_quirks(const struct edid *edid) | ||||
2146 | { | ||||
2147 | const struct edid_quirk *quirk; | ||||
2148 | int i; | ||||
2149 | |||||
2150 | for (i = 0; i < ARRAY_SIZE(edid_quirk_list)(sizeof((edid_quirk_list)) / sizeof((edid_quirk_list)[0])); i++) { | ||||
2151 | quirk = &edid_quirk_list[i]; | ||||
2152 | |||||
2153 | if (edid_vendor(edid, quirk->vendor) && | ||||
2154 | (EDID_PRODUCT_ID(edid)((edid)->prod_code[0] | ((edid)->prod_code[1] << 8 )) == quirk->product_id)) | ||||
2155 | return quirk->quirks; | ||||
2156 | } | ||||
2157 | |||||
2158 | return 0; | ||||
2159 | } | ||||
2160 | |||||
2161 | #define MODE_SIZE(m)((m)->hdisplay * (m)->vdisplay) ((m)->hdisplay * (m)->vdisplay) | ||||
2162 | #define MODE_REFRESH_DIFF(c,t)(abs((c) - (t))) (abs((c) - (t))) | ||||
2163 | |||||
2164 | /** | ||||
2165 | * edid_fixup_preferred - set preferred modes based on quirk list | ||||
2166 | * @connector: has mode list to fix up | ||||
2167 | * @quirks: quirks list | ||||
2168 | * | ||||
2169 | * Walk the mode list for @connector, clearing the preferred status | ||||
2170 | * on existing modes and setting it anew for the right mode ala @quirks. | ||||
2171 | */ | ||||
2172 | static void edid_fixup_preferred(struct drm_connector *connector, | ||||
2173 | u32 quirks) | ||||
2174 | { | ||||
2175 | struct drm_display_mode *t, *cur_mode, *preferred_mode; | ||||
2176 | int target_refresh = 0; | ||||
2177 | int cur_vrefresh, preferred_vrefresh; | ||||
2178 | |||||
2179 | if (list_empty(&connector->probed_modes)) | ||||
2180 | return; | ||||
2181 | |||||
2182 | if (quirks & EDID_QUIRK_PREFER_LARGE_60(1 << 0)) | ||||
2183 | target_refresh = 60; | ||||
2184 | if (quirks & EDID_QUIRK_PREFER_LARGE_75(1 << 2)) | ||||
2185 | target_refresh = 75; | ||||
2186 | |||||
2187 | preferred_mode = list_first_entry(&connector->probed_modes,({ const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&connector->probed_modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );}) | ||||
2188 | struct drm_display_mode, head)({ const __typeof( ((struct drm_display_mode *)0)->head ) * __mptr = ((&connector->probed_modes)->next); (struct drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct drm_display_mode, head) );}); | ||||
2189 | |||||
2190 | list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head)for (cur_mode = ({ const __typeof( ((__typeof(*cur_mode) *)0) ->head ) *__mptr = ((&connector->probed_modes)-> next); (__typeof(*cur_mode) *)( (char *)__mptr - __builtin_offsetof (__typeof(*cur_mode), head) );}), t = ({ const __typeof( ((__typeof (*cur_mode) *)0)->head ) *__mptr = (cur_mode->head.next ); (__typeof(*cur_mode) *)( (char *)__mptr - __builtin_offsetof (__typeof(*cur_mode), head) );}); &cur_mode->head != ( &connector->probed_modes); cur_mode = t, t = ({ const __typeof ( ((__typeof(*t) *)0)->head ) *__mptr = (t->head.next); (__typeof(*t) *)( (char *)__mptr - __builtin_offsetof(__typeof (*t), head) );})) { | ||||
2191 | cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
2192 | |||||
2193 | if (cur_mode == preferred_mode) | ||||
2194 | continue; | ||||
2195 | |||||
2196 | /* Largest mode is preferred */ | ||||
2197 | if (MODE_SIZE(cur_mode)((cur_mode)->hdisplay * (cur_mode)->vdisplay) > MODE_SIZE(preferred_mode)((preferred_mode)->hdisplay * (preferred_mode)->vdisplay )) | ||||
2198 | preferred_mode = cur_mode; | ||||
2199 | |||||
2200 | cur_vrefresh = drm_mode_vrefresh(cur_mode); | ||||
2201 | preferred_vrefresh = drm_mode_vrefresh(preferred_mode); | ||||
2202 | /* At a given size, try to get closest to target refresh */ | ||||
2203 | if ((MODE_SIZE(cur_mode)((cur_mode)->hdisplay * (cur_mode)->vdisplay) == MODE_SIZE(preferred_mode)((preferred_mode)->hdisplay * (preferred_mode)->vdisplay )) && | ||||
2204 | MODE_REFRESH_DIFF(cur_vrefresh, target_refresh)(abs((cur_vrefresh) - (target_refresh))) < | ||||
2205 | MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)(abs((preferred_vrefresh) - (target_refresh)))) { | ||||
2206 | preferred_mode = cur_mode; | ||||
2207 | } | ||||
2208 | } | ||||
2209 | |||||
2210 | preferred_mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
2211 | } | ||||
2212 | |||||
2213 | static bool_Bool | ||||
2214 | mode_is_rb(const struct drm_display_mode *mode) | ||||
2215 | { | ||||
2216 | return (mode->htotal - mode->hdisplay == 160) && | ||||
2217 | (mode->hsync_end - mode->hdisplay == 80) && | ||||
2218 | (mode->hsync_end - mode->hsync_start == 32) && | ||||
2219 | (mode->vsync_start - mode->vdisplay == 3); | ||||
2220 | } | ||||
2221 | |||||
2222 | /* | ||||
2223 | * drm_mode_find_dmt - Create a copy of a mode if present in DMT | ||||
2224 | * @dev: Device to duplicate against | ||||
2225 | * @hsize: Mode width | ||||
2226 | * @vsize: Mode height | ||||
2227 | * @fresh: Mode refresh rate | ||||
2228 | * @rb: Mode reduced-blanking-ness | ||||
2229 | * | ||||
2230 | * Walk the DMT mode list looking for a match for the given parameters. | ||||
2231 | * | ||||
2232 | * Return: A newly allocated copy of the mode, or NULL if not found. | ||||
2233 | */ | ||||
2234 | struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, | ||||
2235 | int hsize, int vsize, int fresh, | ||||
2236 | bool_Bool rb) | ||||
2237 | { | ||||
2238 | int i; | ||||
2239 | |||||
2240 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes)(sizeof((drm_dmt_modes)) / sizeof((drm_dmt_modes)[0])); i++) { | ||||
2241 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; | ||||
2242 | |||||
2243 | if (hsize != ptr->hdisplay) | ||||
2244 | continue; | ||||
2245 | if (vsize != ptr->vdisplay) | ||||
2246 | continue; | ||||
2247 | if (fresh != drm_mode_vrefresh(ptr)) | ||||
2248 | continue; | ||||
2249 | if (rb != mode_is_rb(ptr)) | ||||
2250 | continue; | ||||
2251 | |||||
2252 | return drm_mode_duplicate(dev, ptr); | ||||
2253 | } | ||||
2254 | |||||
2255 | return NULL((void *)0); | ||||
2256 | } | ||||
2257 | EXPORT_SYMBOL(drm_mode_find_dmt); | ||||
2258 | |||||
2259 | static bool_Bool is_display_descriptor(const u8 d[18], u8 tag) | ||||
2260 | { | ||||
2261 | return d[0] == 0x00 && d[1] == 0x00 && | ||||
2262 | d[2] == 0x00 && d[3] == tag; | ||||
2263 | } | ||||
2264 | |||||
2265 | static bool_Bool is_detailed_timing_descriptor(const u8 d[18]) | ||||
2266 | { | ||||
2267 | return d[0] != 0x00 || d[1] != 0x00; | ||||
2268 | } | ||||
2269 | |||||
2270 | typedef void detailed_cb(struct detailed_timing *timing, void *closure); | ||||
2271 | |||||
2272 | static void | ||||
2273 | cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | ||||
2274 | { | ||||
2275 | int i, n; | ||||
2276 | u8 d = ext[0x02]; | ||||
2277 | u8 *det_base = ext + d; | ||||
2278 | |||||
2279 | if (d < 4 || d > 127) | ||||
2280 | return; | ||||
2281 | |||||
2282 | n = (127 - d) / 18; | ||||
2283 | for (i = 0; i < n; i++) | ||||
2284 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | ||||
2285 | } | ||||
2286 | |||||
2287 | static void | ||||
2288 | vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) | ||||
2289 | { | ||||
2290 | unsigned int i, n = min((int)ext[0x02], 6)((((int)ext[0x02])<(6))?((int)ext[0x02]):(6)); | ||||
2291 | u8 *det_base = ext + 5; | ||||
2292 | |||||
2293 | if (ext[0x01] != 1) | ||||
2294 | return; /* unknown version */ | ||||
2295 | |||||
2296 | for (i = 0; i < n; i++) | ||||
2297 | cb((struct detailed_timing *)(det_base + 18 * i), closure); | ||||
2298 | } | ||||
2299 | |||||
2300 | static void | ||||
2301 | drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) | ||||
2302 | { | ||||
2303 | int i; | ||||
2304 | struct edid *edid = (struct edid *)raw_edid; | ||||
2305 | |||||
2306 | if (edid == NULL((void *)0)) | ||||
2307 | return; | ||||
2308 | |||||
2309 | for (i = 0; i < EDID_DETAILED_TIMINGS4; i++) | ||||
2310 | cb(&(edid->detailed_timings[i]), closure); | ||||
2311 | |||||
2312 | for (i = 1; i <= raw_edid[0x7e]; i++) { | ||||
2313 | u8 *ext = raw_edid + (i * EDID_LENGTH128); | ||||
2314 | |||||
2315 | switch (*ext) { | ||||
2316 | case CEA_EXT0x02: | ||||
2317 | cea_for_each_detailed_block(ext, cb, closure); | ||||
2318 | break; | ||||
2319 | case VTB_EXT0x10: | ||||
2320 | vtb_for_each_detailed_block(ext, cb, closure); | ||||
2321 | break; | ||||
2322 | default: | ||||
2323 | break; | ||||
2324 | } | ||||
2325 | } | ||||
2326 | } | ||||
2327 | |||||
2328 | static void | ||||
2329 | is_rb(struct detailed_timing *t, void *data) | ||||
2330 | { | ||||
2331 | u8 *r = (u8 *)t; | ||||
2332 | |||||
2333 | if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
2334 | return; | ||||
2335 | |||||
2336 | if (r[15] & 0x10) | ||||
2337 | *(bool_Bool *)data = true1; | ||||
2338 | } | ||||
2339 | |||||
2340 | /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ | ||||
2341 | static bool_Bool | ||||
2342 | drm_monitor_supports_rb(struct edid *edid) | ||||
2343 | { | ||||
2344 | if (edid->revision >= 4) { | ||||
2345 | bool_Bool ret = false0; | ||||
2346 | |||||
2347 | drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); | ||||
2348 | return ret; | ||||
2349 | } | ||||
2350 | |||||
2351 | return ((edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7)) != 0); | ||||
2352 | } | ||||
2353 | |||||
2354 | static void | ||||
2355 | find_gtf2(struct detailed_timing *t, void *data) | ||||
2356 | { | ||||
2357 | u8 *r = (u8 *)t; | ||||
2358 | |||||
2359 | if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
2360 | return; | ||||
2361 | |||||
2362 | if (r[10] == 0x02) | ||||
2363 | *(u8 **)data = r; | ||||
2364 | } | ||||
2365 | |||||
2366 | /* Secondary GTF curve kicks in above some break frequency */ | ||||
2367 | static int | ||||
2368 | drm_gtf2_hbreak(struct edid *edid) | ||||
2369 | { | ||||
2370 | u8 *r = NULL((void *)0); | ||||
2371 | |||||
2372 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | ||||
2373 | return r ? (r[12] * 2) : 0; | ||||
2374 | } | ||||
2375 | |||||
2376 | static int | ||||
2377 | drm_gtf2_2c(struct edid *edid) | ||||
2378 | { | ||||
2379 | u8 *r = NULL((void *)0); | ||||
2380 | |||||
2381 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | ||||
2382 | return r ? r[13] : 0; | ||||
2383 | } | ||||
2384 | |||||
2385 | static int | ||||
2386 | drm_gtf2_m(struct edid *edid) | ||||
2387 | { | ||||
2388 | u8 *r = NULL((void *)0); | ||||
2389 | |||||
2390 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | ||||
2391 | return r ? (r[15] << 8) + r[14] : 0; | ||||
2392 | } | ||||
2393 | |||||
2394 | static int | ||||
2395 | drm_gtf2_k(struct edid *edid) | ||||
2396 | { | ||||
2397 | u8 *r = NULL((void *)0); | ||||
2398 | |||||
2399 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | ||||
2400 | return r ? r[16] : 0; | ||||
2401 | } | ||||
2402 | |||||
2403 | static int | ||||
2404 | drm_gtf2_2j(struct edid *edid) | ||||
2405 | { | ||||
2406 | u8 *r = NULL((void *)0); | ||||
2407 | |||||
2408 | drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); | ||||
2409 | return r ? r[17] : 0; | ||||
2410 | } | ||||
2411 | |||||
2412 | /** | ||||
2413 | * standard_timing_level - get std. timing level(CVT/GTF/DMT) | ||||
2414 | * @edid: EDID block to scan | ||||
2415 | */ | ||||
2416 | static int standard_timing_level(struct edid *edid) | ||||
2417 | { | ||||
2418 | if (edid->revision >= 2) { | ||||
2419 | if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF(1 << 0))) | ||||
2420 | return LEVEL_CVT3; | ||||
2421 | if (drm_gtf2_hbreak(edid)) | ||||
2422 | return LEVEL_GTF22; | ||||
2423 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF(1 << 0)) | ||||
2424 | return LEVEL_GTF1; | ||||
2425 | } | ||||
2426 | return LEVEL_DMT0; | ||||
2427 | } | ||||
2428 | |||||
2429 | /* | ||||
2430 | * 0 is reserved. The spec says 0x01 fill for unused timings. Some old | ||||
2431 | * monitors fill with ascii space (0x20) instead. | ||||
2432 | */ | ||||
2433 | static int | ||||
2434 | bad_std_timing(u8 a, u8 b) | ||||
2435 | { | ||||
2436 | return (a == 0x00 && b == 0x00) || | ||||
2437 | (a == 0x01 && b == 0x01) || | ||||
2438 | (a == 0x20 && b == 0x20); | ||||
2439 | } | ||||
2440 | |||||
2441 | static int drm_mode_hsync(const struct drm_display_mode *mode) | ||||
2442 | { | ||||
2443 | if (mode->htotal <= 0) | ||||
2444 | return 0; | ||||
2445 | |||||
2446 | return DIV_ROUND_CLOSEST(mode->clock, mode->htotal)(((mode->clock) + ((mode->htotal) / 2)) / (mode->htotal )); | ||||
2447 | } | ||||
2448 | |||||
2449 | /** | ||||
2450 | * drm_mode_std - convert standard mode info (width, height, refresh) into mode | ||||
2451 | * @connector: connector of for the EDID block | ||||
2452 | * @edid: EDID block to scan | ||||
2453 | * @t: standard timing params | ||||
2454 | * | ||||
2455 | * Take the standard timing params (in this case width, aspect, and refresh) | ||||
2456 | * and convert them into a real mode using CVT/GTF/DMT. | ||||
2457 | */ | ||||
2458 | static struct drm_display_mode * | ||||
2459 | drm_mode_std(struct drm_connector *connector, struct edid *edid, | ||||
2460 | struct std_timing *t) | ||||
2461 | { | ||||
2462 | struct drm_device *dev = connector->dev; | ||||
2463 | struct drm_display_mode *m, *mode = NULL((void *)0); | ||||
2464 | int hsize, vsize; | ||||
2465 | int vrefresh_rate; | ||||
2466 | unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK(0x3 << 6)) | ||||
2467 | >> EDID_TIMING_ASPECT_SHIFT6; | ||||
2468 | unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK(0x3f << 0)) | ||||
2469 | >> EDID_TIMING_VFREQ_SHIFT0; | ||||
2470 | int timing_level = standard_timing_level(edid); | ||||
2471 | |||||
2472 | if (bad_std_timing(t->hsize, t->vfreq_aspect)) | ||||
2473 | return NULL((void *)0); | ||||
2474 | |||||
2475 | /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ | ||||
2476 | hsize = t->hsize * 8 + 248; | ||||
2477 | /* vrefresh_rate = vfreq + 60 */ | ||||
2478 | vrefresh_rate = vfreq + 60; | ||||
2479 | /* the vdisplay is calculated based on the aspect ratio */ | ||||
2480 | if (aspect_ratio == 0) { | ||||
2481 | if (edid->revision < 3) | ||||
2482 | vsize = hsize; | ||||
2483 | else | ||||
2484 | vsize = (hsize * 10) / 16; | ||||
2485 | } else if (aspect_ratio == 1) | ||||
2486 | vsize = (hsize * 3) / 4; | ||||
2487 | else if (aspect_ratio == 2) | ||||
2488 | vsize = (hsize * 4) / 5; | ||||
2489 | else | ||||
2490 | vsize = (hsize * 9) / 16; | ||||
2491 | |||||
2492 | /* HDTV hack, part 1 */ | ||||
2493 | if (vrefresh_rate == 60 && | ||||
2494 | ((hsize == 1360 && vsize == 765) || | ||||
2495 | (hsize == 1368 && vsize == 769))) { | ||||
2496 | hsize = 1366; | ||||
2497 | vsize = 768; | ||||
2498 | } | ||||
2499 | |||||
2500 | /* | ||||
2501 | * If this connector already has a mode for this size and refresh | ||||
2502 | * rate (because it came from detailed or CVT info), use that | ||||
2503 | * instead. This way we don't have to guess at interlace or | ||||
2504 | * reduced blanking. | ||||
2505 | */ | ||||
2506 | list_for_each_entry(m, &connector->probed_modes, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof(*m ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head) );}); &m->head != (&connector->probed_modes); m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof (__typeof(*m), head) );})) | ||||
2507 | if (m->hdisplay == hsize && m->vdisplay == vsize && | ||||
2508 | drm_mode_vrefresh(m) == vrefresh_rate) | ||||
2509 | return NULL((void *)0); | ||||
2510 | |||||
2511 | /* HDTV hack, part 2 */ | ||||
2512 | if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { | ||||
2513 | mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, | ||||
2514 | false0); | ||||
2515 | if (!mode) | ||||
2516 | return NULL((void *)0); | ||||
2517 | mode->hdisplay = 1366; | ||||
2518 | mode->hsync_start = mode->hsync_start - 1; | ||||
2519 | mode->hsync_end = mode->hsync_end - 1; | ||||
2520 | return mode; | ||||
2521 | } | ||||
2522 | |||||
2523 | /* check whether it can be found in default mode table */ | ||||
2524 | if (drm_monitor_supports_rb(edid)) { | ||||
2525 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, | ||||
2526 | true1); | ||||
2527 | if (mode) | ||||
2528 | return mode; | ||||
2529 | } | ||||
2530 | mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false0); | ||||
2531 | if (mode) | ||||
2532 | return mode; | ||||
2533 | |||||
2534 | /* okay, generate it */ | ||||
2535 | switch (timing_level) { | ||||
2536 | case LEVEL_DMT0: | ||||
2537 | break; | ||||
2538 | case LEVEL_GTF1: | ||||
2539 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | ||||
2540 | break; | ||||
2541 | case LEVEL_GTF22: | ||||
2542 | /* | ||||
2543 | * This is potentially wrong if there's ever a monitor with | ||||
2544 | * more than one ranges section, each claiming a different | ||||
2545 | * secondary GTF curve. Please don't do that. | ||||
2546 | */ | ||||
2547 | mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); | ||||
2548 | if (!mode) | ||||
2549 | return NULL((void *)0); | ||||
2550 | if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { | ||||
2551 | drm_mode_destroy(dev, mode); | ||||
2552 | mode = drm_gtf_mode_complex(dev, hsize, vsize, | ||||
2553 | vrefresh_rate, 0, 0, | ||||
2554 | drm_gtf2_m(edid), | ||||
2555 | drm_gtf2_2c(edid), | ||||
2556 | drm_gtf2_k(edid), | ||||
2557 | drm_gtf2_2j(edid)); | ||||
2558 | } | ||||
2559 | break; | ||||
2560 | case LEVEL_CVT3: | ||||
2561 | mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, | ||||
2562 | false0); | ||||
2563 | break; | ||||
2564 | } | ||||
2565 | return mode; | ||||
2566 | } | ||||
2567 | |||||
2568 | /* | ||||
2569 | * EDID is delightfully ambiguous about how interlaced modes are to be | ||||
2570 | * encoded. Our internal representation is of frame height, but some | ||||
2571 | * HDTV detailed timings are encoded as field height. | ||||
2572 | * | ||||
2573 | * The format list here is from CEA, in frame size. Technically we | ||||
2574 | * should be checking refresh rate too. Whatever. | ||||
2575 | */ | ||||
2576 | static void | ||||
2577 | drm_mode_do_interlace_quirk(struct drm_display_mode *mode, | ||||
2578 | struct detailed_pixel_timing *pt) | ||||
2579 | { | ||||
2580 | int i; | ||||
2581 | static const struct { | ||||
2582 | int w, h; | ||||
2583 | } cea_interlaced[] = { | ||||
2584 | { 1920, 1080 }, | ||||
2585 | { 720, 480 }, | ||||
2586 | { 1440, 480 }, | ||||
2587 | { 2880, 480 }, | ||||
2588 | { 720, 576 }, | ||||
2589 | { 1440, 576 }, | ||||
2590 | { 2880, 576 }, | ||||
2591 | }; | ||||
2592 | |||||
2593 | if (!(pt->misc & DRM_EDID_PT_INTERLACED(1 << 7))) | ||||
2594 | return; | ||||
2595 | |||||
2596 | for (i = 0; i < ARRAY_SIZE(cea_interlaced)(sizeof((cea_interlaced)) / sizeof((cea_interlaced)[0])); i++) { | ||||
2597 | if ((mode->hdisplay == cea_interlaced[i].w) && | ||||
2598 | (mode->vdisplay == cea_interlaced[i].h / 2)) { | ||||
2599 | mode->vdisplay *= 2; | ||||
2600 | mode->vsync_start *= 2; | ||||
2601 | mode->vsync_end *= 2; | ||||
2602 | mode->vtotal *= 2; | ||||
2603 | mode->vtotal |= 1; | ||||
2604 | } | ||||
2605 | } | ||||
2606 | |||||
2607 | mode->flags |= DRM_MODE_FLAG_INTERLACE(1<<4); | ||||
2608 | } | ||||
2609 | |||||
2610 | /** | ||||
2611 | * drm_mode_detailed - create a new mode from an EDID detailed timing section | ||||
2612 | * @dev: DRM device (needed to create new mode) | ||||
2613 | * @edid: EDID block | ||||
2614 | * @timing: EDID detailed timing info | ||||
2615 | * @quirks: quirks to apply | ||||
2616 | * | ||||
2617 | * An EDID detailed timing block contains enough info for us to create and | ||||
2618 | * return a new struct drm_display_mode. | ||||
2619 | */ | ||||
2620 | static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, | ||||
2621 | struct edid *edid, | ||||
2622 | struct detailed_timing *timing, | ||||
2623 | u32 quirks) | ||||
2624 | { | ||||
2625 | struct drm_display_mode *mode; | ||||
2626 | struct detailed_pixel_timing *pt = &timing->data.pixel_data; | ||||
2627 | unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; | ||||
2628 | unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; | ||||
2629 | unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; | ||||
2630 | unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; | ||||
2631 | unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; | ||||
2632 | unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; | ||||
2633 | unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; | ||||
2634 | unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); | ||||
2635 | |||||
2636 | /* ignore tiny modes */ | ||||
2637 | if (hactive < 64 || vactive < 64) | ||||
2638 | return NULL((void *)0); | ||||
2639 | |||||
2640 | if (pt->misc & DRM_EDID_PT_STEREO(1 << 5)) { | ||||
2641 | DRM_DEBUG_KMS("stereo mode not supported\n")__drm_dbg(DRM_UT_KMS, "stereo mode not supported\n"); | ||||
2642 | return NULL((void *)0); | ||||
2643 | } | ||||
2644 | if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC(3 << 3))) { | ||||
2645 | DRM_DEBUG_KMS("composite sync not supported\n")__drm_dbg(DRM_UT_KMS, "composite sync not supported\n"); | ||||
2646 | } | ||||
2647 | |||||
2648 | /* it is incorrect if hsync/vsync width is zero */ | ||||
2649 | if (!hsync_pulse_width || !vsync_pulse_width) { | ||||
2650 | DRM_DEBUG_KMS("Incorrect Detailed timing. "__drm_dbg(DRM_UT_KMS, "Incorrect Detailed timing. " "Wrong Hsync/Vsync pulse width\n" ) | ||||
2651 | "Wrong Hsync/Vsync pulse width\n")__drm_dbg(DRM_UT_KMS, "Incorrect Detailed timing. " "Wrong Hsync/Vsync pulse width\n" ); | ||||
2652 | return NULL((void *)0); | ||||
2653 | } | ||||
2654 | |||||
2655 | if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING(1 << 7)) { | ||||
2656 | mode = drm_cvt_mode(dev, hactive, vactive, 60, true1, false0, false0); | ||||
2657 | if (!mode) | ||||
2658 | return NULL((void *)0); | ||||
2659 | |||||
2660 | goto set_size; | ||||
2661 | } | ||||
2662 | |||||
2663 | mode = drm_mode_create(dev); | ||||
2664 | if (!mode) | ||||
2665 | return NULL((void *)0); | ||||
2666 | |||||
2667 | if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH(1 << 1)) | ||||
2668 | timing->pixel_clock = cpu_to_le16(1088)((__uint16_t)(1088)); | ||||
2669 | |||||
2670 | mode->clock = le16_to_cpu(timing->pixel_clock)((__uint16_t)(timing->pixel_clock)) * 10; | ||||
2671 | |||||
2672 | mode->hdisplay = hactive; | ||||
2673 | mode->hsync_start = mode->hdisplay + hsync_offset; | ||||
2674 | mode->hsync_end = mode->hsync_start + hsync_pulse_width; | ||||
2675 | mode->htotal = mode->hdisplay + hblank; | ||||
2676 | |||||
2677 | mode->vdisplay = vactive; | ||||
2678 | mode->vsync_start = mode->vdisplay + vsync_offset; | ||||
2679 | mode->vsync_end = mode->vsync_start + vsync_pulse_width; | ||||
2680 | mode->vtotal = mode->vdisplay + vblank; | ||||
2681 | |||||
2682 | /* Some EDIDs have bogus h/vtotal values */ | ||||
2683 | if (mode->hsync_end > mode->htotal) | ||||
2684 | mode->htotal = mode->hsync_end + 1; | ||||
2685 | if (mode->vsync_end > mode->vtotal) | ||||
2686 | mode->vtotal = mode->vsync_end + 1; | ||||
2687 | |||||
2688 | drm_mode_do_interlace_quirk(mode, pt); | ||||
2689 | |||||
2690 | if (quirks & EDID_QUIRK_DETAILED_SYNC_PP(1 << 6)) { | ||||
2691 | pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE(1 << 1) | DRM_EDID_PT_VSYNC_POSITIVE(1 << 2); | ||||
2692 | } | ||||
2693 | |||||
2694 | mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE(1 << 1)) ? | ||||
2695 | DRM_MODE_FLAG_PHSYNC(1<<0) : DRM_MODE_FLAG_NHSYNC(1<<1); | ||||
2696 | mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE(1 << 2)) ? | ||||
2697 | DRM_MODE_FLAG_PVSYNC(1<<2) : DRM_MODE_FLAG_NVSYNC(1<<3); | ||||
2698 | |||||
2699 | set_size: | ||||
2700 | mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; | ||||
2701 | mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; | ||||
2702 | |||||
2703 | if (quirks & EDID_QUIRK_DETAILED_IN_CM(1 << 3)) { | ||||
2704 | mode->width_mm *= 10; | ||||
2705 | mode->height_mm *= 10; | ||||
2706 | } | ||||
2707 | |||||
2708 | if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE(1 << 4)) { | ||||
2709 | mode->width_mm = edid->width_cm * 10; | ||||
2710 | mode->height_mm = edid->height_cm * 10; | ||||
2711 | } | ||||
2712 | |||||
2713 | mode->type = DRM_MODE_TYPE_DRIVER(1<<6); | ||||
2714 | drm_mode_set_name(mode); | ||||
2715 | |||||
2716 | return mode; | ||||
2717 | } | ||||
2718 | |||||
2719 | static bool_Bool | ||||
2720 | mode_in_hsync_range(const struct drm_display_mode *mode, | ||||
2721 | struct edid *edid, u8 *t) | ||||
2722 | { | ||||
2723 | int hsync, hmin, hmax; | ||||
2724 | |||||
2725 | hmin = t[7]; | ||||
2726 | if (edid->revision >= 4) | ||||
2727 | hmin += ((t[4] & 0x04) ? 255 : 0); | ||||
2728 | hmax = t[8]; | ||||
2729 | if (edid->revision >= 4) | ||||
2730 | hmax += ((t[4] & 0x08) ? 255 : 0); | ||||
2731 | hsync = drm_mode_hsync(mode); | ||||
2732 | |||||
2733 | return (hsync <= hmax && hsync >= hmin); | ||||
2734 | } | ||||
2735 | |||||
2736 | static bool_Bool | ||||
2737 | mode_in_vsync_range(const struct drm_display_mode *mode, | ||||
2738 | struct edid *edid, u8 *t) | ||||
2739 | { | ||||
2740 | int vsync, vmin, vmax; | ||||
2741 | |||||
2742 | vmin = t[5]; | ||||
2743 | if (edid->revision >= 4) | ||||
2744 | vmin += ((t[4] & 0x01) ? 255 : 0); | ||||
2745 | vmax = t[6]; | ||||
2746 | if (edid->revision >= 4) | ||||
2747 | vmax += ((t[4] & 0x02) ? 255 : 0); | ||||
2748 | vsync = drm_mode_vrefresh(mode); | ||||
2749 | |||||
2750 | return (vsync <= vmax && vsync >= vmin); | ||||
2751 | } | ||||
2752 | |||||
2753 | static u32 | ||||
2754 | range_pixel_clock(struct edid *edid, u8 *t) | ||||
2755 | { | ||||
2756 | /* unspecified */ | ||||
2757 | if (t[9] == 0 || t[9] == 255) | ||||
2758 | return 0; | ||||
2759 | |||||
2760 | /* 1.4 with CVT support gives us real precision, yay */ | ||||
2761 | if (edid->revision >= 4 && t[10] == 0x04) | ||||
2762 | return (t[9] * 10000) - ((t[12] >> 2) * 250); | ||||
2763 | |||||
2764 | /* 1.3 is pathetic, so fuzz up a bit */ | ||||
2765 | return t[9] * 10000 + 5001; | ||||
2766 | } | ||||
2767 | |||||
2768 | static bool_Bool | ||||
2769 | mode_in_range(const struct drm_display_mode *mode, struct edid *edid, | ||||
2770 | struct detailed_timing *timing) | ||||
2771 | { | ||||
2772 | u32 max_clock; | ||||
2773 | u8 *t = (u8 *)timing; | ||||
2774 | |||||
2775 | if (!mode_in_hsync_range(mode, edid, t)) | ||||
2776 | return false0; | ||||
2777 | |||||
2778 | if (!mode_in_vsync_range(mode, edid, t)) | ||||
2779 | return false0; | ||||
2780 | |||||
2781 | if ((max_clock = range_pixel_clock(edid, t))) | ||||
2782 | if (mode->clock > max_clock) | ||||
2783 | return false0; | ||||
2784 | |||||
2785 | /* 1.4 max horizontal check */ | ||||
2786 | if (edid->revision >= 4 && t[10] == 0x04) | ||||
2787 | if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) | ||||
2788 | return false0; | ||||
2789 | |||||
2790 | if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) | ||||
2791 | return false0; | ||||
2792 | |||||
2793 | return true1; | ||||
2794 | } | ||||
2795 | |||||
2796 | static bool_Bool valid_inferred_mode(const struct drm_connector *connector, | ||||
2797 | const struct drm_display_mode *mode) | ||||
2798 | { | ||||
2799 | const struct drm_display_mode *m; | ||||
2800 | bool_Bool ok = false0; | ||||
2801 | |||||
2802 | list_for_each_entry(m, &connector->probed_modes, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof(*m ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head) );}); &m->head != (&connector->probed_modes); m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof (__typeof(*m), head) );})) { | ||||
2803 | if (mode->hdisplay == m->hdisplay && | ||||
2804 | mode->vdisplay == m->vdisplay && | ||||
2805 | drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) | ||||
2806 | return false0; /* duplicated */ | ||||
2807 | if (mode->hdisplay <= m->hdisplay && | ||||
2808 | mode->vdisplay <= m->vdisplay) | ||||
2809 | ok = true1; | ||||
2810 | } | ||||
2811 | return ok; | ||||
2812 | } | ||||
2813 | |||||
2814 | static int | ||||
2815 | drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, | ||||
2816 | struct detailed_timing *timing) | ||||
2817 | { | ||||
2818 | int i, modes = 0; | ||||
2819 | struct drm_display_mode *newmode; | ||||
2820 | struct drm_device *dev = connector->dev; | ||||
2821 | |||||
2822 | for (i = 0; i < ARRAY_SIZE(drm_dmt_modes)(sizeof((drm_dmt_modes)) / sizeof((drm_dmt_modes)[0])); i++) { | ||||
2823 | if (mode_in_range(drm_dmt_modes + i, edid, timing) && | ||||
2824 | valid_inferred_mode(connector, drm_dmt_modes + i)) { | ||||
2825 | newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); | ||||
2826 | if (newmode) { | ||||
2827 | drm_mode_probed_add(connector, newmode); | ||||
2828 | modes++; | ||||
2829 | } | ||||
2830 | } | ||||
2831 | } | ||||
2832 | |||||
2833 | return modes; | ||||
2834 | } | ||||
2835 | |||||
2836 | /* fix up 1366x768 mode from 1368x768; | ||||
2837 | * GFT/CVT can't express 1366 width which isn't dividable by 8 | ||||
2838 | */ | ||||
2839 | void drm_mode_fixup_1366x768(struct drm_display_mode *mode) | ||||
2840 | { | ||||
2841 | if (mode->hdisplay == 1368 && mode->vdisplay == 768) { | ||||
2842 | mode->hdisplay = 1366; | ||||
2843 | mode->hsync_start--; | ||||
2844 | mode->hsync_end--; | ||||
2845 | drm_mode_set_name(mode); | ||||
2846 | } | ||||
2847 | } | ||||
2848 | |||||
2849 | static int | ||||
2850 | drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, | ||||
2851 | struct detailed_timing *timing) | ||||
2852 | { | ||||
2853 | int i, modes = 0; | ||||
2854 | struct drm_display_mode *newmode; | ||||
2855 | struct drm_device *dev = connector->dev; | ||||
2856 | |||||
2857 | for (i = 0; i < ARRAY_SIZE(extra_modes)(sizeof((extra_modes)) / sizeof((extra_modes)[0])); i++) { | ||||
2858 | const struct minimode *m = &extra_modes[i]; | ||||
2859 | |||||
2860 | newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); | ||||
2861 | if (!newmode) | ||||
2862 | return modes; | ||||
2863 | |||||
2864 | drm_mode_fixup_1366x768(newmode); | ||||
2865 | if (!mode_in_range(newmode, edid, timing) || | ||||
2866 | !valid_inferred_mode(connector, newmode)) { | ||||
2867 | drm_mode_destroy(dev, newmode); | ||||
2868 | continue; | ||||
2869 | } | ||||
2870 | |||||
2871 | drm_mode_probed_add(connector, newmode); | ||||
2872 | modes++; | ||||
2873 | } | ||||
2874 | |||||
2875 | return modes; | ||||
2876 | } | ||||
2877 | |||||
2878 | static int | ||||
2879 | drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, | ||||
2880 | struct detailed_timing *timing) | ||||
2881 | { | ||||
2882 | int i, modes = 0; | ||||
2883 | struct drm_display_mode *newmode; | ||||
2884 | struct drm_device *dev = connector->dev; | ||||
2885 | bool_Bool rb = drm_monitor_supports_rb(edid); | ||||
2886 | |||||
2887 | for (i = 0; i < ARRAY_SIZE(extra_modes)(sizeof((extra_modes)) / sizeof((extra_modes)[0])); i++) { | ||||
2888 | const struct minimode *m = &extra_modes[i]; | ||||
2889 | |||||
2890 | newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); | ||||
2891 | if (!newmode) | ||||
2892 | return modes; | ||||
2893 | |||||
2894 | drm_mode_fixup_1366x768(newmode); | ||||
2895 | if (!mode_in_range(newmode, edid, timing) || | ||||
2896 | !valid_inferred_mode(connector, newmode)) { | ||||
2897 | drm_mode_destroy(dev, newmode); | ||||
2898 | continue; | ||||
2899 | } | ||||
2900 | |||||
2901 | drm_mode_probed_add(connector, newmode); | ||||
2902 | modes++; | ||||
2903 | } | ||||
2904 | |||||
2905 | return modes; | ||||
2906 | } | ||||
2907 | |||||
2908 | static void | ||||
2909 | do_inferred_modes(struct detailed_timing *timing, void *c) | ||||
2910 | { | ||||
2911 | struct detailed_mode_closure *closure = c; | ||||
2912 | struct detailed_non_pixel *data = &timing->data.other_data; | ||||
2913 | struct detailed_data_monitor_range *range = &data->data.range; | ||||
2914 | |||||
2915 | if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
2916 | return; | ||||
2917 | |||||
2918 | closure->modes += drm_dmt_modes_for_range(closure->connector, | ||||
2919 | closure->edid, | ||||
2920 | timing); | ||||
2921 | |||||
2922 | if (!version_greater(closure->edid, 1, 1)(((closure->edid)->version > (1)) || ((closure->edid )->version == (1) && (closure->edid)->revision > (1)))) | ||||
2923 | return; /* GTF not defined yet */ | ||||
2924 | |||||
2925 | switch (range->flags) { | ||||
2926 | case 0x02: /* secondary gtf, XXX could do more */ | ||||
2927 | case 0x00: /* default gtf */ | ||||
2928 | closure->modes += drm_gtf_modes_for_range(closure->connector, | ||||
2929 | closure->edid, | ||||
2930 | timing); | ||||
2931 | break; | ||||
2932 | case 0x04: /* cvt, only in 1.4+ */ | ||||
2933 | if (!version_greater(closure->edid, 1, 3)(((closure->edid)->version > (1)) || ((closure->edid )->version == (1) && (closure->edid)->revision > (3)))) | ||||
2934 | break; | ||||
2935 | |||||
2936 | closure->modes += drm_cvt_modes_for_range(closure->connector, | ||||
2937 | closure->edid, | ||||
2938 | timing); | ||||
2939 | break; | ||||
2940 | case 0x01: /* just the ranges, no formula */ | ||||
2941 | default: | ||||
2942 | break; | ||||
2943 | } | ||||
2944 | } | ||||
2945 | |||||
2946 | static int | ||||
2947 | add_inferred_modes(struct drm_connector *connector, struct edid *edid) | ||||
2948 | { | ||||
2949 | struct detailed_mode_closure closure = { | ||||
2950 | .connector = connector, | ||||
2951 | .edid = edid, | ||||
2952 | }; | ||||
2953 | |||||
2954 | if (version_greater(edid, 1, 0)(((edid)->version > (1)) || ((edid)->version == (1) && (edid)->revision > (0)))) | ||||
2955 | drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, | ||||
2956 | &closure); | ||||
2957 | |||||
2958 | return closure.modes; | ||||
2959 | } | ||||
2960 | |||||
2961 | static int | ||||
2962 | drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) | ||||
2963 | { | ||||
2964 | int i, j, m, modes = 0; | ||||
2965 | struct drm_display_mode *mode; | ||||
2966 | u8 *est = ((u8 *)timing) + 6; | ||||
2967 | |||||
2968 | for (i = 0; i < 6; i++) { | ||||
2969 | for (j = 7; j >= 0; j--) { | ||||
2970 | m = (i * 8) + (7 - j); | ||||
2971 | if (m >= ARRAY_SIZE(est3_modes)(sizeof((est3_modes)) / sizeof((est3_modes)[0]))) | ||||
2972 | break; | ||||
2973 | if (est[i] & (1 << j)) { | ||||
2974 | mode = drm_mode_find_dmt(connector->dev, | ||||
2975 | est3_modes[m].w, | ||||
2976 | est3_modes[m].h, | ||||
2977 | est3_modes[m].r, | ||||
2978 | est3_modes[m].rb); | ||||
2979 | if (mode) { | ||||
2980 | drm_mode_probed_add(connector, mode); | ||||
2981 | modes++; | ||||
2982 | } | ||||
2983 | } | ||||
2984 | } | ||||
2985 | } | ||||
2986 | |||||
2987 | return modes; | ||||
2988 | } | ||||
2989 | |||||
2990 | static void | ||||
2991 | do_established_modes(struct detailed_timing *timing, void *c) | ||||
2992 | { | ||||
2993 | struct detailed_mode_closure *closure = c; | ||||
2994 | |||||
2995 | if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS0xf7)) | ||||
2996 | return; | ||||
2997 | |||||
2998 | closure->modes += drm_est3_modes(closure->connector, timing); | ||||
2999 | } | ||||
3000 | |||||
3001 | /** | ||||
3002 | * add_established_modes - get est. modes from EDID and add them | ||||
3003 | * @connector: connector to add mode(s) to | ||||
3004 | * @edid: EDID block to scan | ||||
3005 | * | ||||
3006 | * Each EDID block contains a bitmap of the supported "established modes" list | ||||
3007 | * (defined above). Tease them out and add them to the global modes list. | ||||
3008 | */ | ||||
3009 | static int | ||||
3010 | add_established_modes(struct drm_connector *connector, struct edid *edid) | ||||
3011 | { | ||||
3012 | struct drm_device *dev = connector->dev; | ||||
3013 | unsigned long est_bits = edid->established_timings.t1 | | ||||
3014 | (edid->established_timings.t2 << 8) | | ||||
3015 | ((edid->established_timings.mfg_rsvd & 0x80) << 9); | ||||
3016 | int i, modes = 0; | ||||
3017 | struct detailed_mode_closure closure = { | ||||
3018 | .connector = connector, | ||||
3019 | .edid = edid, | ||||
3020 | }; | ||||
3021 | |||||
3022 | for (i = 0; i <= EDID_EST_TIMINGS16; i++) { | ||||
3023 | if (est_bits & (1<<i)) { | ||||
3024 | struct drm_display_mode *newmode; | ||||
3025 | |||||
3026 | newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); | ||||
3027 | if (newmode) { | ||||
3028 | drm_mode_probed_add(connector, newmode); | ||||
3029 | modes++; | ||||
3030 | } | ||||
3031 | } | ||||
3032 | } | ||||
3033 | |||||
3034 | if (version_greater(edid, 1, 0)(((edid)->version > (1)) || ((edid)->version == (1) && (edid)->revision > (0)))) | ||||
3035 | drm_for_each_detailed_block((u8 *)edid, | ||||
3036 | do_established_modes, &closure); | ||||
3037 | |||||
3038 | return modes + closure.modes; | ||||
3039 | } | ||||
3040 | |||||
3041 | static void | ||||
3042 | do_standard_modes(struct detailed_timing *timing, void *c) | ||||
3043 | { | ||||
3044 | struct detailed_mode_closure *closure = c; | ||||
3045 | struct detailed_non_pixel *data = &timing->data.other_data; | ||||
3046 | struct drm_connector *connector = closure->connector; | ||||
3047 | struct edid *edid = closure->edid; | ||||
3048 | int i; | ||||
3049 | |||||
3050 | if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES0xfa)) | ||||
3051 | return; | ||||
3052 | |||||
3053 | for (i = 0; i < 6; i++) { | ||||
3054 | struct std_timing *std = &data->data.timings[i]; | ||||
3055 | struct drm_display_mode *newmode; | ||||
3056 | |||||
3057 | newmode = drm_mode_std(connector, edid, std); | ||||
3058 | if (newmode) { | ||||
3059 | drm_mode_probed_add(connector, newmode); | ||||
3060 | closure->modes++; | ||||
3061 | } | ||||
3062 | } | ||||
3063 | } | ||||
3064 | |||||
3065 | /** | ||||
3066 | * add_standard_modes - get std. modes from EDID and add them | ||||
3067 | * @connector: connector to add mode(s) to | ||||
3068 | * @edid: EDID block to scan | ||||
3069 | * | ||||
3070 | * Standard modes can be calculated using the appropriate standard (DMT, | ||||
3071 | * GTF or CVT. Grab them from @edid and add them to the list. | ||||
3072 | */ | ||||
3073 | static int | ||||
3074 | add_standard_modes(struct drm_connector *connector, struct edid *edid) | ||||
3075 | { | ||||
3076 | int i, modes = 0; | ||||
3077 | struct detailed_mode_closure closure = { | ||||
3078 | .connector = connector, | ||||
3079 | .edid = edid, | ||||
3080 | }; | ||||
3081 | |||||
3082 | for (i = 0; i < EDID_STD_TIMINGS8; i++) { | ||||
3083 | struct drm_display_mode *newmode; | ||||
3084 | |||||
3085 | newmode = drm_mode_std(connector, edid, | ||||
3086 | &edid->standard_timings[i]); | ||||
3087 | if (newmode) { | ||||
3088 | drm_mode_probed_add(connector, newmode); | ||||
3089 | modes++; | ||||
3090 | } | ||||
3091 | } | ||||
3092 | |||||
3093 | if (version_greater(edid, 1, 0)(((edid)->version > (1)) || ((edid)->version == (1) && (edid)->revision > (0)))) | ||||
3094 | drm_for_each_detailed_block((u8 *)edid, do_standard_modes, | ||||
3095 | &closure); | ||||
3096 | |||||
3097 | /* XXX should also look for standard codes in VTB blocks */ | ||||
3098 | |||||
3099 | return modes + closure.modes; | ||||
3100 | } | ||||
3101 | |||||
3102 | static int drm_cvt_modes(struct drm_connector *connector, | ||||
3103 | struct detailed_timing *timing) | ||||
3104 | { | ||||
3105 | int i, j, modes = 0; | ||||
3106 | struct drm_display_mode *newmode; | ||||
3107 | struct drm_device *dev = connector->dev; | ||||
3108 | struct cvt_timing *cvt; | ||||
3109 | const int rates[] = { 60, 85, 75, 60, 50 }; | ||||
3110 | const u8 empty[3] = { 0, 0, 0 }; | ||||
3111 | |||||
3112 | for (i = 0; i < 4; i++) { | ||||
3113 | int width, height; | ||||
3114 | |||||
3115 | cvt = &(timing->data.other_data.data.cvt[i]); | ||||
3116 | |||||
3117 | if (!memcmp(cvt->code, empty, 3)__builtin_memcmp((cvt->code), (empty), (3))) | ||||
3118 | continue; | ||||
3119 | |||||
3120 | height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; | ||||
3121 | switch (cvt->code[1] & 0x0c) { | ||||
3122 | /* default - because compiler doesn't see that we've enumerated all cases */ | ||||
3123 | default: | ||||
3124 | case 0x00: | ||||
3125 | width = height * 4 / 3; | ||||
3126 | break; | ||||
3127 | case 0x04: | ||||
3128 | width = height * 16 / 9; | ||||
3129 | break; | ||||
3130 | case 0x08: | ||||
3131 | width = height * 16 / 10; | ||||
3132 | break; | ||||
3133 | case 0x0c: | ||||
3134 | width = height * 15 / 9; | ||||
3135 | break; | ||||
3136 | } | ||||
3137 | |||||
3138 | for (j = 1; j < 5; j++) { | ||||
3139 | if (cvt->code[2] & (1 << j)) { | ||||
3140 | newmode = drm_cvt_mode(dev, width, height, | ||||
3141 | rates[j], j == 0, | ||||
3142 | false0, false0); | ||||
3143 | if (newmode) { | ||||
3144 | drm_mode_probed_add(connector, newmode); | ||||
3145 | modes++; | ||||
3146 | } | ||||
3147 | } | ||||
3148 | } | ||||
3149 | } | ||||
3150 | |||||
3151 | return modes; | ||||
3152 | } | ||||
3153 | |||||
3154 | static void | ||||
3155 | do_cvt_mode(struct detailed_timing *timing, void *c) | ||||
3156 | { | ||||
3157 | struct detailed_mode_closure *closure = c; | ||||
3158 | |||||
3159 | if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE0xf8)) | ||||
3160 | return; | ||||
3161 | |||||
3162 | closure->modes += drm_cvt_modes(closure->connector, timing); | ||||
3163 | } | ||||
3164 | |||||
3165 | static int | ||||
3166 | add_cvt_modes(struct drm_connector *connector, struct edid *edid) | ||||
3167 | { | ||||
3168 | struct detailed_mode_closure closure = { | ||||
3169 | .connector = connector, | ||||
3170 | .edid = edid, | ||||
3171 | }; | ||||
3172 | |||||
3173 | if (version_greater(edid, 1, 2)(((edid)->version > (1)) || ((edid)->version == (1) && (edid)->revision > (2)))) | ||||
3174 | drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); | ||||
3175 | |||||
3176 | /* XXX should also look for CVT codes in VTB blocks */ | ||||
3177 | |||||
3178 | return closure.modes; | ||||
3179 | } | ||||
3180 | |||||
3181 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); | ||||
3182 | |||||
3183 | static void | ||||
3184 | do_detailed_mode(struct detailed_timing *timing, void *c) | ||||
3185 | { | ||||
3186 | struct detailed_mode_closure *closure = c; | ||||
3187 | struct drm_display_mode *newmode; | ||||
3188 | |||||
3189 | if (!is_detailed_timing_descriptor((const u8 *)timing)) | ||||
3190 | return; | ||||
3191 | |||||
3192 | newmode = drm_mode_detailed(closure->connector->dev, | ||||
3193 | closure->edid, timing, | ||||
3194 | closure->quirks); | ||||
3195 | if (!newmode) | ||||
3196 | return; | ||||
3197 | |||||
3198 | if (closure->preferred) | ||||
3199 | newmode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
3200 | |||||
3201 | /* | ||||
3202 | * Detailed modes are limited to 10kHz pixel clock resolution, | ||||
3203 | * so fix up anything that looks like CEA/HDMI mode, but the clock | ||||
3204 | * is just slightly off. | ||||
3205 | */ | ||||
3206 | fixup_detailed_cea_mode_clock(newmode); | ||||
3207 | |||||
3208 | drm_mode_probed_add(closure->connector, newmode); | ||||
3209 | closure->modes++; | ||||
3210 | closure->preferred = false0; | ||||
3211 | } | ||||
3212 | |||||
3213 | /* | ||||
3214 | * add_detailed_modes - Add modes from detailed timings | ||||
3215 | * @connector: attached connector | ||||
3216 | * @edid: EDID block to scan | ||||
3217 | * @quirks: quirks to apply | ||||
3218 | */ | ||||
3219 | static int | ||||
3220 | add_detailed_modes(struct drm_connector *connector, struct edid *edid, | ||||
3221 | u32 quirks) | ||||
3222 | { | ||||
3223 | struct detailed_mode_closure closure = { | ||||
3224 | .connector = connector, | ||||
3225 | .edid = edid, | ||||
3226 | .preferred = true1, | ||||
3227 | .quirks = quirks, | ||||
3228 | }; | ||||
3229 | |||||
3230 | if (closure.preferred && !version_greater(edid, 1, 3)(((edid)->version > (1)) || ((edid)->version == (1) && (edid)->revision > (3)))) | ||||
3231 | closure.preferred = | ||||
3232 | (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING(1 << 1)); | ||||
3233 | |||||
3234 | drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); | ||||
3235 | |||||
3236 | return closure.modes; | ||||
3237 | } | ||||
3238 | |||||
3239 | #define AUDIO_BLOCK0x01 0x01 | ||||
3240 | #define VIDEO_BLOCK0x02 0x02 | ||||
3241 | #define VENDOR_BLOCK0x03 0x03 | ||||
3242 | #define SPEAKER_BLOCK0x04 0x04 | ||||
3243 | #define HDR_STATIC_METADATA_BLOCK0x6 0x6 | ||||
3244 | #define USE_EXTENDED_TAG0x07 0x07 | ||||
3245 | #define EXT_VIDEO_CAPABILITY_BLOCK0x00 0x00 | ||||
3246 | #define EXT_VIDEO_DATA_BLOCK_4200x0E 0x0E | ||||
3247 | #define EXT_VIDEO_CAP_BLOCK_Y420CMDB0x0F 0x0F | ||||
3248 | #define EDID_BASIC_AUDIO(1 << 6) (1 << 6) | ||||
3249 | #define EDID_CEA_YCRCB444(1 << 5) (1 << 5) | ||||
3250 | #define EDID_CEA_YCRCB422(1 << 4) (1 << 4) | ||||
3251 | #define EDID_CEA_VCDB_QS(1 << 6) (1 << 6) | ||||
3252 | |||||
3253 | /* | ||||
3254 | * Search EDID for CEA extension block. | ||||
3255 | */ | ||||
3256 | static u8 *drm_find_edid_extension(const struct edid *edid, | ||||
3257 | int ext_id, int *ext_index) | ||||
3258 | { | ||||
3259 | u8 *edid_ext = NULL((void *)0); | ||||
3260 | int i; | ||||
3261 | |||||
3262 | /* No EDID or EDID extensions */ | ||||
3263 | if (edid == NULL((void *)0) || edid->extensions == 0) | ||||
3264 | return NULL((void *)0); | ||||
3265 | |||||
3266 | /* Find CEA extension */ | ||||
3267 | for (i = *ext_index; i < edid->extensions; i++) { | ||||
3268 | edid_ext = (u8 *)edid + EDID_LENGTH128 * (i + 1); | ||||
3269 | if (edid_ext[0] == ext_id) | ||||
3270 | break; | ||||
3271 | } | ||||
3272 | |||||
3273 | if (i >= edid->extensions) | ||||
3274 | return NULL((void *)0); | ||||
3275 | |||||
3276 | *ext_index = i + 1; | ||||
3277 | |||||
3278 | return edid_ext; | ||||
3279 | } | ||||
3280 | |||||
3281 | |||||
3282 | static u8 *drm_find_displayid_extension(const struct edid *edid, | ||||
3283 | int *length, int *idx, | ||||
3284 | int *ext_index) | ||||
3285 | { | ||||
3286 | u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT0x70, ext_index); | ||||
3287 | struct displayid_hdr *base; | ||||
3288 | int ret; | ||||
3289 | |||||
3290 | if (!displayid) | ||||
3291 | return NULL((void *)0); | ||||
3292 | |||||
3293 | /* EDID extensions block checksum isn't for us */ | ||||
3294 | *length = EDID_LENGTH128 - 1; | ||||
3295 | *idx = 1; | ||||
3296 | |||||
3297 | ret = validate_displayid(displayid, *length, *idx); | ||||
3298 | if (ret) | ||||
3299 | return NULL((void *)0); | ||||
3300 | |||||
3301 | base = (struct displayid_hdr *)&displayid[*idx]; | ||||
3302 | *length = *idx + sizeof(*base) + base->bytes; | ||||
3303 | |||||
3304 | return displayid; | ||||
3305 | } | ||||
3306 | |||||
3307 | static u8 *drm_find_cea_extension(const struct edid *edid) | ||||
3308 | { | ||||
3309 | int length, idx; | ||||
3310 | struct displayid_block *block; | ||||
3311 | u8 *cea; | ||||
3312 | u8 *displayid; | ||||
3313 | int ext_index; | ||||
3314 | |||||
3315 | /* Look for a top level CEA extension block */ | ||||
3316 | /* FIXME: make callers iterate through multiple CEA ext blocks? */ | ||||
3317 | ext_index = 0; | ||||
3318 | cea = drm_find_edid_extension(edid, CEA_EXT0x02, &ext_index); | ||||
3319 | if (cea) | ||||
3320 | return cea; | ||||
3321 | |||||
3322 | /* CEA blocks can also be found embedded in a DisplayID block */ | ||||
3323 | ext_index = 0; | ||||
3324 | for (;;) { | ||||
3325 | displayid = drm_find_displayid_extension(edid, &length, &idx, | ||||
3326 | &ext_index); | ||||
3327 | if (!displayid) | ||||
3328 | return NULL((void *)0); | ||||
3329 | |||||
3330 | idx += sizeof(struct displayid_hdr); | ||||
3331 | for_each_displayid_db(displayid, block, idx, length)for ((block) = (struct displayid_block *)&(displayid)[idx ]; (idx) + sizeof(struct displayid_block) <= (length) && (idx) + sizeof(struct displayid_block) + (block)->num_bytes <= (length) && (block)->num_bytes > 0; (idx ) += sizeof(struct displayid_block) + (block)->num_bytes, ( block) = (struct displayid_block *)&(displayid)[idx]) { | ||||
3332 | if (block->tag == DATA_BLOCK_CTA0x81) | ||||
3333 | return (u8 *)block; | ||||
3334 | } | ||||
3335 | } | ||||
3336 | |||||
3337 | return NULL((void *)0); | ||||
3338 | } | ||||
3339 | |||||
3340 | static __always_inline__attribute__((__always_inline__)) const struct drm_display_mode *cea_mode_for_vic(u8 vic) | ||||
3341 | { | ||||
3342 | BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127)extern char _ctassert[(!(1 + (sizeof((edid_cea_modes_1)) / sizeof ((edid_cea_modes_1)[0])) - 1 != 127)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
3343 | BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219)extern char _ctassert[(!(193 + (sizeof((edid_cea_modes_193)) / sizeof((edid_cea_modes_193)[0])) - 1 != 219)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
3344 | |||||
3345 | if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)(sizeof((edid_cea_modes_1)) / sizeof((edid_cea_modes_1)[0]))) | ||||
3346 | return &edid_cea_modes_1[vic - 1]; | ||||
3347 | if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)(sizeof((edid_cea_modes_193)) / sizeof((edid_cea_modes_193)[0 ]))) | ||||
3348 | return &edid_cea_modes_193[vic - 193]; | ||||
3349 | return NULL((void *)0); | ||||
3350 | } | ||||
3351 | |||||
3352 | static u8 cea_num_vics(void) | ||||
3353 | { | ||||
3354 | return 193 + ARRAY_SIZE(edid_cea_modes_193)(sizeof((edid_cea_modes_193)) / sizeof((edid_cea_modes_193)[0 ])); | ||||
3355 | } | ||||
3356 | |||||
3357 | static u8 cea_next_vic(u8 vic) | ||||
3358 | { | ||||
3359 | if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)(sizeof((edid_cea_modes_1)) / sizeof((edid_cea_modes_1)[0]))) | ||||
3360 | vic = 193; | ||||
3361 | return vic; | ||||
3362 | } | ||||
3363 | |||||
3364 | /* | ||||
3365 | * Calculate the alternate clock for the CEA mode | ||||
3366 | * (60Hz vs. 59.94Hz etc.) | ||||
3367 | */ | ||||
3368 | static unsigned int | ||||
3369 | cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) | ||||
3370 | { | ||||
3371 | unsigned int clock = cea_mode->clock; | ||||
3372 | |||||
3373 | if (drm_mode_vrefresh(cea_mode) % 6 != 0) | ||||
3374 | return clock; | ||||
3375 | |||||
3376 | /* | ||||
3377 | * edid_cea_modes contains the 59.94Hz | ||||
3378 | * variant for 240 and 480 line modes, | ||||
3379 | * and the 60Hz variant otherwise. | ||||
3380 | */ | ||||
3381 | if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) | ||||
3382 | clock = DIV_ROUND_CLOSEST(clock * 1001, 1000)(((clock * 1001) + ((1000) / 2)) / (1000)); | ||||
3383 | else | ||||
3384 | clock = DIV_ROUND_CLOSEST(clock * 1000, 1001)(((clock * 1000) + ((1001) / 2)) / (1001)); | ||||
3385 | |||||
3386 | return clock; | ||||
3387 | } | ||||
3388 | |||||
3389 | static bool_Bool | ||||
3390 | cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) | ||||
3391 | { | ||||
3392 | /* | ||||
3393 | * For certain VICs the spec allows the vertical | ||||
3394 | * front porch to vary by one or two lines. | ||||
3395 | * | ||||
3396 | * cea_modes[] stores the variant with the shortest | ||||
3397 | * vertical front porch. We can adjust the mode to | ||||
3398 | * get the other variants by simply increasing the | ||||
3399 | * vertical front porch length. | ||||
3400 | */ | ||||
3401 | #ifdef notyet | ||||
3402 | BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3403 | cea_mode_for_vic(9)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3404 | cea_mode_for_vic(12)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3405 | cea_mode_for_vic(13)->vtotal != 262 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3406 | cea_mode_for_vic(23)->vtotal != 312 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3407 | cea_mode_for_vic(24)->vtotal != 312 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3408 | cea_mode_for_vic(27)->vtotal != 312 ||extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)) | ||||
3409 | cea_mode_for_vic(28)->vtotal != 312)extern char _ctassert[(!(cea_mode_for_vic(8)->vtotal != 262 || cea_mode_for_vic(9)->vtotal != 262 || cea_mode_for_vic (12)->vtotal != 262 || cea_mode_for_vic(13)->vtotal != 262 || cea_mode_for_vic(23)->vtotal != 312 || cea_mode_for_vic (24)->vtotal != 312 || cea_mode_for_vic(27)->vtotal != 312 || cea_mode_for_vic(28)->vtotal != 312)) ? 1 : -1 ] __attribute__ ((__unused__)); | ||||
3410 | #endif | ||||
3411 | |||||
3412 | if (((vic == 8 || vic == 9 || | ||||
3413 | vic == 12 || vic == 13) && mode->vtotal < 263) || | ||||
3414 | ((vic == 23 || vic == 24 || | ||||
3415 | vic == 27 || vic == 28) && mode->vtotal < 314)) { | ||||
3416 | mode->vsync_start++; | ||||
3417 | mode->vsync_end++; | ||||
3418 | mode->vtotal++; | ||||
3419 | |||||
3420 | return true1; | ||||
3421 | } | ||||
3422 | |||||
3423 | return false0; | ||||
3424 | } | ||||
3425 | |||||
3426 | static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, | ||||
3427 | unsigned int clock_tolerance) | ||||
3428 | { | ||||
3429 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
3430 | u8 vic; | ||||
3431 | |||||
3432 | if (!to_match->clock) | ||||
3433 | return 0; | ||||
3434 | |||||
3435 | if (to_match->picture_aspect_ratio) | ||||
3436 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
3437 | |||||
3438 | for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { | ||||
3439 | struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); | ||||
3440 | unsigned int clock1, clock2; | ||||
3441 | |||||
3442 | /* Check both 60Hz and 59.94Hz */ | ||||
3443 | clock1 = cea_mode.clock; | ||||
3444 | clock2 = cea_mode_alternate_clock(&cea_mode); | ||||
3445 | |||||
3446 | if (abs(to_match->clock - clock1) > clock_tolerance && | ||||
3447 | abs(to_match->clock - clock2) > clock_tolerance) | ||||
3448 | continue; | ||||
3449 | |||||
3450 | do { | ||||
3451 | if (drm_mode_match(to_match, &cea_mode, match_flags)) | ||||
3452 | return vic; | ||||
3453 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | ||||
3454 | } | ||||
3455 | |||||
3456 | return 0; | ||||
3457 | } | ||||
3458 | |||||
3459 | /** | ||||
3460 | * drm_match_cea_mode - look for a CEA mode matching given mode | ||||
3461 | * @to_match: display mode | ||||
3462 | * | ||||
3463 | * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 | ||||
3464 | * mode. | ||||
3465 | */ | ||||
3466 | u8 drm_match_cea_mode(const struct drm_display_mode *to_match) | ||||
3467 | { | ||||
3468 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
3469 | u8 vic; | ||||
3470 | |||||
3471 | if (!to_match->clock) | ||||
3472 | return 0; | ||||
3473 | |||||
3474 | if (to_match->picture_aspect_ratio) | ||||
3475 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
3476 | |||||
3477 | for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { | ||||
3478 | struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); | ||||
3479 | unsigned int clock1, clock2; | ||||
3480 | |||||
3481 | /* Check both 60Hz and 59.94Hz */ | ||||
3482 | clock1 = cea_mode.clock; | ||||
3483 | clock2 = cea_mode_alternate_clock(&cea_mode); | ||||
3484 | |||||
3485 | if (KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) != KHZ2PICOS(clock1)(1000000000UL/(clock1)) && | ||||
3486 | KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) != KHZ2PICOS(clock2)(1000000000UL/(clock2))) | ||||
3487 | continue; | ||||
3488 | |||||
3489 | do { | ||||
3490 | if (drm_mode_match(to_match, &cea_mode, match_flags)) | ||||
3491 | return vic; | ||||
3492 | } while (cea_mode_alternate_timings(vic, &cea_mode)); | ||||
3493 | } | ||||
3494 | |||||
3495 | return 0; | ||||
3496 | } | ||||
3497 | EXPORT_SYMBOL(drm_match_cea_mode); | ||||
3498 | |||||
3499 | static bool_Bool drm_valid_cea_vic(u8 vic) | ||||
3500 | { | ||||
3501 | return cea_mode_for_vic(vic) != NULL((void *)0); | ||||
3502 | } | ||||
3503 | |||||
3504 | static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) | ||||
3505 | { | ||||
3506 | const struct drm_display_mode *mode = cea_mode_for_vic(video_code); | ||||
3507 | |||||
3508 | if (mode) | ||||
3509 | return mode->picture_aspect_ratio; | ||||
3510 | |||||
3511 | return HDMI_PICTURE_ASPECT_NONE; | ||||
3512 | } | ||||
3513 | |||||
3514 | static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) | ||||
3515 | { | ||||
3516 | return edid_4k_modes[video_code].picture_aspect_ratio; | ||||
3517 | } | ||||
3518 | |||||
3519 | /* | ||||
3520 | * Calculate the alternate clock for HDMI modes (those from the HDMI vendor | ||||
3521 | * specific block). | ||||
3522 | */ | ||||
3523 | static unsigned int | ||||
3524 | hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) | ||||
3525 | { | ||||
3526 | return cea_mode_alternate_clock(hdmi_mode); | ||||
3527 | } | ||||
3528 | |||||
3529 | static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, | ||||
3530 | unsigned int clock_tolerance) | ||||
3531 | { | ||||
3532 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
3533 | u8 vic; | ||||
3534 | |||||
3535 | if (!to_match->clock) | ||||
3536 | return 0; | ||||
3537 | |||||
3538 | if (to_match->picture_aspect_ratio) | ||||
3539 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
3540 | |||||
3541 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes)(sizeof((edid_4k_modes)) / sizeof((edid_4k_modes)[0])); vic++) { | ||||
3542 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | ||||
3543 | unsigned int clock1, clock2; | ||||
3544 | |||||
3545 | /* Make sure to also match alternate clocks */ | ||||
3546 | clock1 = hdmi_mode->clock; | ||||
3547 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | ||||
3548 | |||||
3549 | if (abs(to_match->clock - clock1) > clock_tolerance && | ||||
3550 | abs(to_match->clock - clock2) > clock_tolerance) | ||||
3551 | continue; | ||||
3552 | |||||
3553 | if (drm_mode_match(to_match, hdmi_mode, match_flags)) | ||||
3554 | return vic; | ||||
3555 | } | ||||
3556 | |||||
3557 | return 0; | ||||
3558 | } | ||||
3559 | |||||
3560 | /* | ||||
3561 | * drm_match_hdmi_mode - look for a HDMI mode matching given mode | ||||
3562 | * @to_match: display mode | ||||
3563 | * | ||||
3564 | * An HDMI mode is one defined in the HDMI vendor specific block. | ||||
3565 | * | ||||
3566 | * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. | ||||
3567 | */ | ||||
3568 | static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) | ||||
3569 | { | ||||
3570 | unsigned int match_flags = DRM_MODE_MATCH_TIMINGS(1 << 0) | DRM_MODE_MATCH_FLAGS(1 << 2); | ||||
3571 | u8 vic; | ||||
3572 | |||||
3573 | if (!to_match->clock) | ||||
3574 | return 0; | ||||
3575 | |||||
3576 | if (to_match->picture_aspect_ratio) | ||||
3577 | match_flags |= DRM_MODE_MATCH_ASPECT_RATIO(1 << 4); | ||||
3578 | |||||
3579 | for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes)(sizeof((edid_4k_modes)) / sizeof((edid_4k_modes)[0])); vic++) { | ||||
3580 | const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; | ||||
3581 | unsigned int clock1, clock2; | ||||
3582 | |||||
3583 | /* Make sure to also match alternate clocks */ | ||||
3584 | clock1 = hdmi_mode->clock; | ||||
3585 | clock2 = hdmi_mode_alternate_clock(hdmi_mode); | ||||
3586 | |||||
3587 | if ((KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) == KHZ2PICOS(clock1)(1000000000UL/(clock1)) || | ||||
3588 | KHZ2PICOS(to_match->clock)(1000000000UL/(to_match->clock)) == KHZ2PICOS(clock2)(1000000000UL/(clock2))) && | ||||
3589 | drm_mode_match(to_match, hdmi_mode, match_flags)) | ||||
3590 | return vic; | ||||
3591 | } | ||||
3592 | return 0; | ||||
3593 | } | ||||
3594 | |||||
3595 | static bool_Bool drm_valid_hdmi_vic(u8 vic) | ||||
3596 | { | ||||
3597 | return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes)(sizeof((edid_4k_modes)) / sizeof((edid_4k_modes)[0])); | ||||
3598 | } | ||||
3599 | |||||
3600 | static int | ||||
3601 | add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) | ||||
3602 | { | ||||
3603 | struct drm_device *dev = connector->dev; | ||||
3604 | struct drm_display_mode *mode, *tmp; | ||||
3605 | DRM_LIST_HEAD(list)struct list_head list = { &(list), &(list) }; | ||||
3606 | int modes = 0; | ||||
3607 | |||||
3608 | /* Don't add CEA modes if the CEA extension block is missing */ | ||||
3609 | if (!drm_find_cea_extension(edid)) | ||||
3610 | return 0; | ||||
3611 | |||||
3612 | /* | ||||
3613 | * Go through all probed modes and create a new mode | ||||
3614 | * with the alternate clock for certain CEA modes. | ||||
3615 | */ | ||||
3616 | list_for_each_entry(mode, &connector->probed_modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->probed_modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { | ||||
3617 | const struct drm_display_mode *cea_mode = NULL((void *)0); | ||||
3618 | struct drm_display_mode *newmode; | ||||
3619 | u8 vic = drm_match_cea_mode(mode); | ||||
3620 | unsigned int clock1, clock2; | ||||
3621 | |||||
3622 | if (drm_valid_cea_vic(vic)) { | ||||
3623 | cea_mode = cea_mode_for_vic(vic); | ||||
3624 | clock2 = cea_mode_alternate_clock(cea_mode); | ||||
3625 | } else { | ||||
3626 | vic = drm_match_hdmi_mode(mode); | ||||
3627 | if (drm_valid_hdmi_vic(vic)) { | ||||
3628 | cea_mode = &edid_4k_modes[vic]; | ||||
3629 | clock2 = hdmi_mode_alternate_clock(cea_mode); | ||||
3630 | } | ||||
3631 | } | ||||
3632 | |||||
3633 | if (!cea_mode) | ||||
3634 | continue; | ||||
3635 | |||||
3636 | clock1 = cea_mode->clock; | ||||
3637 | |||||
3638 | if (clock1 == clock2) | ||||
3639 | continue; | ||||
3640 | |||||
3641 | if (mode->clock != clock1 && mode->clock != clock2) | ||||
3642 | continue; | ||||
3643 | |||||
3644 | newmode = drm_mode_duplicate(dev, cea_mode); | ||||
3645 | if (!newmode) | ||||
3646 | continue; | ||||
3647 | |||||
3648 | /* Carry over the stereo flags */ | ||||
3649 | newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK(0x1f<<14); | ||||
3650 | |||||
3651 | /* | ||||
3652 | * The current mode could be either variant. Make | ||||
3653 | * sure to pick the "other" clock for the new mode. | ||||
3654 | */ | ||||
3655 | if (mode->clock != clock1) | ||||
3656 | newmode->clock = clock1; | ||||
3657 | else | ||||
3658 | newmode->clock = clock2; | ||||
3659 | |||||
3660 | list_add_tail(&newmode->head, &list); | ||||
3661 | } | ||||
3662 | |||||
3663 | list_for_each_entry_safe(mode, tmp, &list, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&list)->next); (__typeof(*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode), head) );}), tmp = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode), head) );}); &mode-> head != (&list); mode = tmp, tmp = ({ const __typeof( ((__typeof (*tmp) *)0)->head ) *__mptr = (tmp->head.next); (__typeof (*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof(*tmp) , head) );})) { | ||||
3664 | list_del(&mode->head); | ||||
3665 | drm_mode_probed_add(connector, mode); | ||||
3666 | modes++; | ||||
3667 | } | ||||
3668 | |||||
3669 | return modes; | ||||
3670 | } | ||||
3671 | |||||
3672 | static u8 svd_to_vic(u8 svd) | ||||
3673 | { | ||||
3674 | /* 0-6 bit vic, 7th bit native mode indicator */ | ||||
3675 | if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) | ||||
3676 | return svd & 127; | ||||
3677 | |||||
3678 | return svd; | ||||
3679 | } | ||||
3680 | |||||
3681 | static struct drm_display_mode * | ||||
3682 | drm_display_mode_from_vic_index(struct drm_connector *connector, | ||||
3683 | const u8 *video_db, u8 video_len, | ||||
3684 | u8 video_index) | ||||
3685 | { | ||||
3686 | struct drm_device *dev = connector->dev; | ||||
3687 | struct drm_display_mode *newmode; | ||||
3688 | u8 vic; | ||||
3689 | |||||
3690 | if (video_db == NULL((void *)0) || video_index >= video_len) | ||||
3691 | return NULL((void *)0); | ||||
3692 | |||||
3693 | /* CEA modes are numbered 1..127 */ | ||||
3694 | vic = svd_to_vic(video_db[video_index]); | ||||
3695 | if (!drm_valid_cea_vic(vic)) | ||||
3696 | return NULL((void *)0); | ||||
3697 | |||||
3698 | newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); | ||||
3699 | if (!newmode) | ||||
3700 | return NULL((void *)0); | ||||
3701 | |||||
3702 | return newmode; | ||||
3703 | } | ||||
3704 | |||||
3705 | /* | ||||
3706 | * do_y420vdb_modes - Parse YCBCR 420 only modes | ||||
3707 | * @connector: connector corresponding to the HDMI sink | ||||
3708 | * @svds: start of the data block of CEA YCBCR 420 VDB | ||||
3709 | * @len: length of the CEA YCBCR 420 VDB | ||||
3710 | * | ||||
3711 | * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) | ||||
3712 | * which contains modes which can be supported in YCBCR 420 | ||||
3713 | * output format only. | ||||
3714 | */ | ||||
3715 | static int do_y420vdb_modes(struct drm_connector *connector, | ||||
3716 | const u8 *svds, u8 svds_len) | ||||
3717 | { | ||||
3718 | int modes = 0, i; | ||||
3719 | struct drm_device *dev = connector->dev; | ||||
3720 | struct drm_display_info *info = &connector->display_info; | ||||
3721 | struct drm_hdmi_info *hdmi = &info->hdmi; | ||||
3722 | |||||
3723 | for (i = 0; i < svds_len; i++) { | ||||
3724 | u8 vic = svd_to_vic(svds[i]); | ||||
3725 | struct drm_display_mode *newmode; | ||||
3726 | |||||
3727 | if (!drm_valid_cea_vic(vic)) | ||||
3728 | continue; | ||||
3729 | |||||
3730 | newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); | ||||
3731 | if (!newmode) | ||||
3732 | break; | ||||
3733 | bitmap_set(hdmi->y420_vdb_modes, vic, 1); | ||||
3734 | drm_mode_probed_add(connector, newmode); | ||||
3735 | modes++; | ||||
3736 | } | ||||
3737 | |||||
3738 | if (modes > 0) | ||||
3739 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB420(1<<3); | ||||
3740 | return modes; | ||||
3741 | } | ||||
3742 | |||||
3743 | /* | ||||
3744 | * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap | ||||
3745 | * @connector: connector corresponding to the HDMI sink | ||||
3746 | * @vic: CEA vic for the video mode to be added in the map | ||||
3747 | * | ||||
3748 | * Makes an entry for a videomode in the YCBCR 420 bitmap | ||||
3749 | */ | ||||
3750 | static void | ||||
3751 | drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) | ||||
3752 | { | ||||
3753 | u8 vic = svd_to_vic(svd); | ||||
3754 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | ||||
3755 | |||||
3756 | if (!drm_valid_cea_vic(vic)) | ||||
3757 | return; | ||||
3758 | |||||
3759 | bitmap_set(hdmi->y420_cmdb_modes, vic, 1); | ||||
3760 | } | ||||
3761 | |||||
3762 | /** | ||||
3763 | * drm_display_mode_from_cea_vic() - return a mode for CEA VIC | ||||
3764 | * @dev: DRM device | ||||
3765 | * @video_code: CEA VIC of the mode | ||||
3766 | * | ||||
3767 | * Creates a new mode matching the specified CEA VIC. | ||||
3768 | * | ||||
3769 | * Returns: A new drm_display_mode on success or NULL on failure | ||||
3770 | */ | ||||
3771 | struct drm_display_mode * | ||||
3772 | drm_display_mode_from_cea_vic(struct drm_device *dev, | ||||
3773 | u8 video_code) | ||||
3774 | { | ||||
3775 | const struct drm_display_mode *cea_mode; | ||||
3776 | struct drm_display_mode *newmode; | ||||
3777 | |||||
3778 | cea_mode = cea_mode_for_vic(video_code); | ||||
3779 | if (!cea_mode) | ||||
3780 | return NULL((void *)0); | ||||
3781 | |||||
3782 | newmode = drm_mode_duplicate(dev, cea_mode); | ||||
3783 | if (!newmode) | ||||
3784 | return NULL((void *)0); | ||||
3785 | |||||
3786 | return newmode; | ||||
3787 | } | ||||
3788 | EXPORT_SYMBOL(drm_display_mode_from_cea_vic); | ||||
3789 | |||||
3790 | static int | ||||
3791 | do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) | ||||
3792 | { | ||||
3793 | int i, modes = 0; | ||||
3794 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | ||||
3795 | |||||
3796 | for (i = 0; i < len; i++) { | ||||
3797 | struct drm_display_mode *mode; | ||||
3798 | |||||
3799 | mode = drm_display_mode_from_vic_index(connector, db, len, i); | ||||
3800 | if (mode) { | ||||
3801 | /* | ||||
3802 | * YCBCR420 capability block contains a bitmap which | ||||
3803 | * gives the index of CEA modes from CEA VDB, which | ||||
3804 | * can support YCBCR 420 sampling output also (apart | ||||
3805 | * from RGB/YCBCR444 etc). | ||||
3806 | * For example, if the bit 0 in bitmap is set, | ||||
3807 | * first mode in VDB can support YCBCR420 output too. | ||||
3808 | * Add YCBCR420 modes only if sink is HDMI 2.0 capable. | ||||
3809 | */ | ||||
3810 | if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) | ||||
3811 | drm_add_cmdb_modes(connector, db[i]); | ||||
3812 | |||||
3813 | drm_mode_probed_add(connector, mode); | ||||
3814 | modes++; | ||||
3815 | } | ||||
3816 | } | ||||
3817 | |||||
3818 | return modes; | ||||
3819 | } | ||||
3820 | |||||
3821 | struct stereo_mandatory_mode { | ||||
3822 | int width, height, vrefresh; | ||||
3823 | unsigned int flags; | ||||
3824 | }; | ||||
3825 | |||||
3826 | static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { | ||||
3827 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14) }, | ||||
3828 | { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14) }, | ||||
3829 | { 1920, 1080, 50, | ||||
3830 | DRM_MODE_FLAG_INTERLACE(1<<4) | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14) }, | ||||
3831 | { 1920, 1080, 60, | ||||
3832 | DRM_MODE_FLAG_INTERLACE(1<<4) | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14) }, | ||||
3833 | { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14) }, | ||||
3834 | { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14) }, | ||||
3835 | { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14) }, | ||||
3836 | { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14) } | ||||
3837 | }; | ||||
3838 | |||||
3839 | static bool_Bool | ||||
3840 | stereo_match_mandatory(const struct drm_display_mode *mode, | ||||
3841 | const struct stereo_mandatory_mode *stereo_mode) | ||||
3842 | { | ||||
3843 | unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4); | ||||
3844 | |||||
3845 | return mode->hdisplay == stereo_mode->width && | ||||
3846 | mode->vdisplay == stereo_mode->height && | ||||
3847 | interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) && | ||||
3848 | drm_mode_vrefresh(mode) == stereo_mode->vrefresh; | ||||
3849 | } | ||||
3850 | |||||
3851 | static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) | ||||
3852 | { | ||||
3853 | struct drm_device *dev = connector->dev; | ||||
3854 | const struct drm_display_mode *mode; | ||||
3855 | struct list_head stereo_modes; | ||||
3856 | int modes = 0, i; | ||||
3857 | |||||
3858 | INIT_LIST_HEAD(&stereo_modes); | ||||
3859 | |||||
3860 | list_for_each_entry(mode, &connector->probed_modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->probed_modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { | ||||
3861 | for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes)(sizeof((stereo_mandatory_modes)) / sizeof((stereo_mandatory_modes )[0])); i++) { | ||||
3862 | const struct stereo_mandatory_mode *mandatory; | ||||
3863 | struct drm_display_mode *new_mode; | ||||
3864 | |||||
3865 | if (!stereo_match_mandatory(mode, | ||||
3866 | &stereo_mandatory_modes[i])) | ||||
3867 | continue; | ||||
3868 | |||||
3869 | mandatory = &stereo_mandatory_modes[i]; | ||||
3870 | new_mode = drm_mode_duplicate(dev, mode); | ||||
3871 | if (!new_mode) | ||||
3872 | continue; | ||||
3873 | |||||
3874 | new_mode->flags |= mandatory->flags; | ||||
3875 | list_add_tail(&new_mode->head, &stereo_modes); | ||||
3876 | modes++; | ||||
3877 | } | ||||
3878 | } | ||||
3879 | |||||
3880 | list_splice_tail(&stereo_modes, &connector->probed_modes); | ||||
3881 | |||||
3882 | return modes; | ||||
3883 | } | ||||
3884 | |||||
3885 | static int add_hdmi_mode(struct drm_connector *connector, u8 vic) | ||||
3886 | { | ||||
3887 | struct drm_device *dev = connector->dev; | ||||
3888 | struct drm_display_mode *newmode; | ||||
3889 | |||||
3890 | if (!drm_valid_hdmi_vic(vic)) { | ||||
3891 | DRM_ERROR("Unknown HDMI VIC: %d\n", vic)__drm_err("Unknown HDMI VIC: %d\n", vic); | ||||
3892 | return 0; | ||||
3893 | } | ||||
3894 | |||||
3895 | newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); | ||||
3896 | if (!newmode) | ||||
3897 | return 0; | ||||
3898 | |||||
3899 | drm_mode_probed_add(connector, newmode); | ||||
3900 | |||||
3901 | return 1; | ||||
3902 | } | ||||
3903 | |||||
3904 | static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, | ||||
3905 | const u8 *video_db, u8 video_len, u8 video_index) | ||||
3906 | { | ||||
3907 | struct drm_display_mode *newmode; | ||||
3908 | int modes = 0; | ||||
3909 | |||||
3910 | if (structure & (1 << 0)) { | ||||
3911 | newmode = drm_display_mode_from_vic_index(connector, video_db, | ||||
3912 | video_len, | ||||
3913 | video_index); | ||||
3914 | if (newmode) { | ||||
3915 | newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14); | ||||
3916 | drm_mode_probed_add(connector, newmode); | ||||
3917 | modes++; | ||||
3918 | } | ||||
3919 | } | ||||
3920 | if (structure & (1 << 6)) { | ||||
3921 | newmode = drm_display_mode_from_vic_index(connector, video_db, | ||||
3922 | video_len, | ||||
3923 | video_index); | ||||
3924 | if (newmode) { | ||||
3925 | newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14); | ||||
3926 | drm_mode_probed_add(connector, newmode); | ||||
3927 | modes++; | ||||
3928 | } | ||||
3929 | } | ||||
3930 | if (structure & (1 << 8)) { | ||||
3931 | newmode = drm_display_mode_from_vic_index(connector, video_db, | ||||
3932 | video_len, | ||||
3933 | video_index); | ||||
3934 | if (newmode) { | ||||
3935 | newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14); | ||||
3936 | drm_mode_probed_add(connector, newmode); | ||||
3937 | modes++; | ||||
3938 | } | ||||
3939 | } | ||||
3940 | |||||
3941 | return modes; | ||||
3942 | } | ||||
3943 | |||||
3944 | /* | ||||
3945 | * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block | ||||
3946 | * @connector: connector corresponding to the HDMI sink | ||||
3947 | * @db: start of the CEA vendor specific block | ||||
3948 | * @len: length of the CEA block payload, ie. one can access up to db[len] | ||||
3949 | * | ||||
3950 | * Parses the HDMI VSDB looking for modes to add to @connector. This function | ||||
3951 | * also adds the stereo 3d modes when applicable. | ||||
3952 | */ | ||||
3953 | static int | ||||
3954 | do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, | ||||
3955 | const u8 *video_db, u8 video_len) | ||||
3956 | { | ||||
3957 | struct drm_display_info *info = &connector->display_info; | ||||
3958 | int modes = 0, offset = 0, i, multi_present = 0, multi_len; | ||||
3959 | u8 vic_len, hdmi_3d_len = 0; | ||||
3960 | u16 mask; | ||||
3961 | u16 structure_all; | ||||
3962 | |||||
3963 | if (len < 8) | ||||
3964 | goto out; | ||||
3965 | |||||
3966 | /* no HDMI_Video_Present */ | ||||
3967 | if (!(db[8] & (1 << 5))) | ||||
3968 | goto out; | ||||
3969 | |||||
3970 | /* Latency_Fields_Present */ | ||||
3971 | if (db[8] & (1 << 7)) | ||||
3972 | offset += 2; | ||||
3973 | |||||
3974 | /* I_Latency_Fields_Present */ | ||||
3975 | if (db[8] & (1 << 6)) | ||||
3976 | offset += 2; | ||||
3977 | |||||
3978 | /* the declared length is not long enough for the 2 first bytes | ||||
3979 | * of additional video format capabilities */ | ||||
3980 | if (len < (8 + offset + 2)) | ||||
3981 | goto out; | ||||
3982 | |||||
3983 | /* 3D_Present */ | ||||
3984 | offset++; | ||||
3985 | if (db[8 + offset] & (1 << 7)) { | ||||
3986 | modes += add_hdmi_mandatory_stereo_modes(connector); | ||||
3987 | |||||
3988 | /* 3D_Multi_present */ | ||||
3989 | multi_present = (db[8 + offset] & 0x60) >> 5; | ||||
3990 | } | ||||
3991 | |||||
3992 | offset++; | ||||
3993 | vic_len = db[8 + offset] >> 5; | ||||
3994 | hdmi_3d_len = db[8 + offset] & 0x1f; | ||||
3995 | |||||
3996 | for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { | ||||
3997 | u8 vic; | ||||
3998 | |||||
3999 | vic = db[9 + offset + i]; | ||||
4000 | modes += add_hdmi_mode(connector, vic); | ||||
4001 | } | ||||
4002 | offset += 1 + vic_len; | ||||
4003 | |||||
4004 | if (multi_present == 1) | ||||
4005 | multi_len = 2; | ||||
4006 | else if (multi_present == 2) | ||||
4007 | multi_len = 4; | ||||
4008 | else | ||||
4009 | multi_len = 0; | ||||
4010 | |||||
4011 | if (len < (8 + offset + hdmi_3d_len - 1)) | ||||
4012 | goto out; | ||||
4013 | |||||
4014 | if (hdmi_3d_len < multi_len) | ||||
4015 | goto out; | ||||
4016 | |||||
4017 | if (multi_present == 1 || multi_present == 2) { | ||||
4018 | /* 3D_Structure_ALL */ | ||||
4019 | structure_all = (db[8 + offset] << 8) | db[9 + offset]; | ||||
4020 | |||||
4021 | /* check if 3D_MASK is present */ | ||||
4022 | if (multi_present == 2) | ||||
4023 | mask = (db[10 + offset] << 8) | db[11 + offset]; | ||||
4024 | else | ||||
4025 | mask = 0xffff; | ||||
4026 | |||||
4027 | for (i = 0; i < 16; i++) { | ||||
4028 | if (mask & (1 << i)) | ||||
4029 | modes += add_3d_struct_modes(connector, | ||||
4030 | structure_all, | ||||
4031 | video_db, | ||||
4032 | video_len, i); | ||||
4033 | } | ||||
4034 | } | ||||
4035 | |||||
4036 | offset += multi_len; | ||||
4037 | |||||
4038 | for (i = 0; i < (hdmi_3d_len - multi_len); i++) { | ||||
4039 | int vic_index; | ||||
4040 | struct drm_display_mode *newmode = NULL((void *)0); | ||||
4041 | unsigned int newflag = 0; | ||||
4042 | bool_Bool detail_present; | ||||
4043 | |||||
4044 | detail_present = ((db[8 + offset + i] & 0x0f) > 7); | ||||
4045 | |||||
4046 | if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) | ||||
4047 | break; | ||||
4048 | |||||
4049 | /* 2D_VIC_order_X */ | ||||
4050 | vic_index = db[8 + offset + i] >> 4; | ||||
4051 | |||||
4052 | /* 3D_Structure_X */ | ||||
4053 | switch (db[8 + offset + i] & 0x0f) { | ||||
4054 | case 0: | ||||
4055 | newflag = DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14); | ||||
4056 | break; | ||||
4057 | case 6: | ||||
4058 | newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14); | ||||
4059 | break; | ||||
4060 | case 8: | ||||
4061 | /* 3D_Detail_X */ | ||||
4062 | if ((db[9 + offset + i] >> 4) == 1) | ||||
4063 | newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14); | ||||
4064 | break; | ||||
4065 | } | ||||
4066 | |||||
4067 | if (newflag != 0) { | ||||
4068 | newmode = drm_display_mode_from_vic_index(connector, | ||||
4069 | video_db, | ||||
4070 | video_len, | ||||
4071 | vic_index); | ||||
4072 | |||||
4073 | if (newmode) { | ||||
4074 | newmode->flags |= newflag; | ||||
4075 | drm_mode_probed_add(connector, newmode); | ||||
4076 | modes++; | ||||
4077 | } | ||||
4078 | } | ||||
4079 | |||||
4080 | if (detail_present) | ||||
4081 | i++; | ||||
4082 | } | ||||
4083 | |||||
4084 | out: | ||||
4085 | if (modes > 0) | ||||
4086 | info->has_hdmi_infoframe = true1; | ||||
4087 | return modes; | ||||
4088 | } | ||||
4089 | |||||
4090 | static int | ||||
4091 | cea_db_payload_len(const u8 *db) | ||||
4092 | { | ||||
4093 | return db[0] & 0x1f; | ||||
4094 | } | ||||
4095 | |||||
4096 | static int | ||||
4097 | cea_db_extended_tag(const u8 *db) | ||||
4098 | { | ||||
4099 | return db[1]; | ||||
4100 | } | ||||
4101 | |||||
4102 | static int | ||||
4103 | cea_db_tag(const u8 *db) | ||||
4104 | { | ||||
4105 | return db[0] >> 5; | ||||
4106 | } | ||||
4107 | |||||
4108 | static int | ||||
4109 | cea_revision(const u8 *cea) | ||||
4110 | { | ||||
4111 | /* | ||||
4112 | * FIXME is this correct for the DispID variant? | ||||
4113 | * The DispID spec doesn't really specify whether | ||||
4114 | * this is the revision of the CEA extension or | ||||
4115 | * the DispID CEA data block. And the only value | ||||
4116 | * given as an example is 0. | ||||
4117 | */ | ||||
4118 | return cea[1]; | ||||
4119 | } | ||||
4120 | |||||
4121 | static int | ||||
4122 | cea_db_offsets(const u8 *cea, int *start, int *end) | ||||
4123 | { | ||||
4124 | /* DisplayID CTA extension blocks and top-level CEA EDID | ||||
4125 | * block header definitions differ in the following bytes: | ||||
4126 | * 1) Byte 2 of the header specifies length differently, | ||||
4127 | * 2) Byte 3 is only present in the CEA top level block. | ||||
4128 | * | ||||
4129 | * The different definitions for byte 2 follow. | ||||
4130 | * | ||||
4131 | * DisplayID CTA extension block defines byte 2 as: | ||||
4132 | * Number of payload bytes | ||||
4133 | * | ||||
4134 | * CEA EDID block defines byte 2 as: | ||||
4135 | * Byte number (decimal) within this block where the 18-byte | ||||
4136 | * DTDs begin. If no non-DTD data is present in this extension | ||||
4137 | * block, the value should be set to 04h (the byte after next). | ||||
4138 | * If set to 00h, there are no DTDs present in this block and | ||||
4139 | * no non-DTD data. | ||||
4140 | */ | ||||
4141 | if (cea[0] == DATA_BLOCK_CTA0x81) { | ||||
4142 | /* | ||||
4143 | * for_each_displayid_db() has already verified | ||||
4144 | * that these stay within expected bounds. | ||||
4145 | */ | ||||
4146 | *start = 3; | ||||
4147 | *end = *start + cea[2]; | ||||
4148 | } else if (cea[0] == CEA_EXT0x02) { | ||||
4149 | /* Data block offset in CEA extension block */ | ||||
4150 | *start = 4; | ||||
4151 | *end = cea[2]; | ||||
4152 | if (*end == 0) | ||||
4153 | *end = 127; | ||||
4154 | if (*end < 4 || *end > 127) | ||||
4155 | return -ERANGE34; | ||||
4156 | } else { | ||||
4157 | return -EOPNOTSUPP45; | ||||
4158 | } | ||||
4159 | |||||
4160 | return 0; | ||||
4161 | } | ||||
4162 | |||||
4163 | static bool_Bool cea_db_is_hdmi_vsdb(const u8 *db) | ||||
4164 | { | ||||
4165 | int hdmi_id; | ||||
4166 | |||||
4167 | if (cea_db_tag(db) != VENDOR_BLOCK0x03) | ||||
4168 | return false0; | ||||
4169 | |||||
4170 | if (cea_db_payload_len(db) < 5) | ||||
4171 | return false0; | ||||
4172 | |||||
4173 | hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); | ||||
4174 | |||||
4175 | return hdmi_id == HDMI_IEEE_OUI0x000c03; | ||||
4176 | } | ||||
4177 | |||||
4178 | static bool_Bool cea_db_is_hdmi_forum_vsdb(const u8 *db) | ||||
4179 | { | ||||
4180 | unsigned int oui; | ||||
4181 | |||||
4182 | if (cea_db_tag(db) != VENDOR_BLOCK0x03) | ||||
4183 | return false0; | ||||
4184 | |||||
4185 | if (cea_db_payload_len(db) < 7) | ||||
4186 | return false0; | ||||
4187 | |||||
4188 | oui = db[3] << 16 | db[2] << 8 | db[1]; | ||||
4189 | |||||
4190 | return oui == HDMI_FORUM_IEEE_OUI0xc45dd8; | ||||
4191 | } | ||||
4192 | |||||
4193 | static bool_Bool cea_db_is_vcdb(const u8 *db) | ||||
4194 | { | ||||
4195 | if (cea_db_tag(db) != USE_EXTENDED_TAG0x07) | ||||
4196 | return false0; | ||||
4197 | |||||
4198 | if (cea_db_payload_len(db) != 2) | ||||
4199 | return false0; | ||||
4200 | |||||
4201 | if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK0x00) | ||||
4202 | return false0; | ||||
4203 | |||||
4204 | return true1; | ||||
4205 | } | ||||
4206 | |||||
4207 | static bool_Bool cea_db_is_y420cmdb(const u8 *db) | ||||
4208 | { | ||||
4209 | if (cea_db_tag(db) != USE_EXTENDED_TAG0x07) | ||||
4210 | return false0; | ||||
4211 | |||||
4212 | if (!cea_db_payload_len(db)) | ||||
4213 | return false0; | ||||
4214 | |||||
4215 | if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB0x0F) | ||||
4216 | return false0; | ||||
4217 | |||||
4218 | return true1; | ||||
4219 | } | ||||
4220 | |||||
4221 | static bool_Bool cea_db_is_y420vdb(const u8 *db) | ||||
4222 | { | ||||
4223 | if (cea_db_tag(db) != USE_EXTENDED_TAG0x07) | ||||
4224 | return false0; | ||||
4225 | |||||
4226 | if (!cea_db_payload_len(db)) | ||||
4227 | return false0; | ||||
4228 | |||||
4229 | if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_4200x0E) | ||||
4230 | return false0; | ||||
4231 | |||||
4232 | return true1; | ||||
4233 | } | ||||
4234 | |||||
4235 | #define for_each_cea_db(cea, i, start, end)for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len (&(cea)[(i)]) < (end); (i) += cea_db_payload_len(& (cea)[(i)]) + 1) \ | ||||
4236 | for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) | ||||
4237 | |||||
4238 | static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, | ||||
4239 | const u8 *db) | ||||
4240 | { | ||||
4241 | struct drm_display_info *info = &connector->display_info; | ||||
4242 | struct drm_hdmi_info *hdmi = &info->hdmi; | ||||
4243 | u8 map_len = cea_db_payload_len(db) - 1; | ||||
4244 | u8 count; | ||||
4245 | u64 map = 0; | ||||
4246 | |||||
4247 | if (map_len == 0) { | ||||
4248 | /* All CEA modes support ycbcr420 sampling also.*/ | ||||
4249 | hdmi->y420_cmdb_map = U64_MAX0xffffffffffffffffULL; | ||||
4250 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB420(1<<3); | ||||
4251 | return; | ||||
4252 | } | ||||
4253 | |||||
4254 | /* | ||||
4255 | * This map indicates which of the existing CEA block modes | ||||
4256 | * from VDB can support YCBCR420 output too. So if bit=0 is | ||||
4257 | * set, first mode from VDB can support YCBCR420 output too. | ||||
4258 | * We will parse and keep this map, before parsing VDB itself | ||||
4259 | * to avoid going through the same block again and again. | ||||
4260 | * | ||||
4261 | * Spec is not clear about max possible size of this block. | ||||
4262 | * Clamping max bitmap block size at 8 bytes. Every byte can | ||||
4263 | * address 8 CEA modes, in this way this map can address | ||||
4264 | * 8*8 = first 64 SVDs. | ||||
4265 | */ | ||||
4266 | if (WARN_ON_ONCE(map_len > 8)({ static int __warned; int __ret = !!(map_len > 8); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "map_len > 8", "/usr/src/sys/dev/pci/drm/drm_edid.c", 4266 ); __warned = 1; } __builtin_expect(!!(__ret), 0); })) | ||||
4267 | map_len = 8; | ||||
4268 | |||||
4269 | for (count = 0; count < map_len; count++) | ||||
4270 | map |= (u64)db[2 + count] << (8 * count); | ||||
4271 | |||||
4272 | if (map) | ||||
4273 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB420(1<<3); | ||||
4274 | |||||
4275 | hdmi->y420_cmdb_map = map; | ||||
4276 | } | ||||
4277 | |||||
4278 | static int | ||||
4279 | add_cea_modes(struct drm_connector *connector, struct edid *edid) | ||||
4280 | { | ||||
4281 | const u8 *cea = drm_find_cea_extension(edid); | ||||
4282 | const u8 *db, *hdmi = NULL((void *)0), *video = NULL((void *)0); | ||||
4283 | u8 dbl, hdmi_len, video_len = 0; | ||||
4284 | int modes = 0; | ||||
4285 | |||||
4286 | if (cea && cea_revision(cea) >= 3) { | ||||
4287 | int i, start, end; | ||||
4288 | |||||
4289 | if (cea_db_offsets(cea, &start, &end)) | ||||
4290 | return 0; | ||||
4291 | |||||
4292 | for_each_cea_db(cea, i, start, end)for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len (&(cea)[(i)]) < (end); (i) += cea_db_payload_len(& (cea)[(i)]) + 1) { | ||||
4293 | db = &cea[i]; | ||||
4294 | dbl = cea_db_payload_len(db); | ||||
4295 | |||||
4296 | if (cea_db_tag(db) == VIDEO_BLOCK0x02) { | ||||
4297 | video = db + 1; | ||||
4298 | video_len = dbl; | ||||
4299 | modes += do_cea_modes(connector, video, dbl); | ||||
4300 | } else if (cea_db_is_hdmi_vsdb(db)) { | ||||
4301 | hdmi = db; | ||||
4302 | hdmi_len = dbl; | ||||
4303 | } else if (cea_db_is_y420vdb(db)) { | ||||
4304 | const u8 *vdb420 = &db[2]; | ||||
4305 | |||||
4306 | /* Add 4:2:0(only) modes present in EDID */ | ||||
4307 | modes += do_y420vdb_modes(connector, | ||||
4308 | vdb420, | ||||
4309 | dbl - 1); | ||||
4310 | } | ||||
4311 | } | ||||
4312 | } | ||||
4313 | |||||
4314 | /* | ||||
4315 | * We parse the HDMI VSDB after having added the cea modes as we will | ||||
4316 | * be patching their flags when the sink supports stereo 3D. | ||||
4317 | */ | ||||
4318 | if (hdmi) | ||||
4319 | modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, | ||||
4320 | video_len); | ||||
4321 | |||||
4322 | return modes; | ||||
4323 | } | ||||
4324 | |||||
4325 | static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) | ||||
4326 | { | ||||
4327 | const struct drm_display_mode *cea_mode; | ||||
4328 | int clock1, clock2, clock; | ||||
4329 | u8 vic; | ||||
4330 | const char *type; | ||||
4331 | |||||
4332 | /* | ||||
4333 | * allow 5kHz clock difference either way to account for | ||||
4334 | * the 10kHz clock resolution limit of detailed timings. | ||||
4335 | */ | ||||
4336 | vic = drm_match_cea_mode_clock_tolerance(mode, 5); | ||||
4337 | if (drm_valid_cea_vic(vic)) { | ||||
4338 | type = "CEA"; | ||||
4339 | cea_mode = cea_mode_for_vic(vic); | ||||
4340 | clock1 = cea_mode->clock; | ||||
4341 | clock2 = cea_mode_alternate_clock(cea_mode); | ||||
4342 | } else { | ||||
4343 | vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); | ||||
4344 | if (drm_valid_hdmi_vic(vic)) { | ||||
4345 | type = "HDMI"; | ||||
4346 | cea_mode = &edid_4k_modes[vic]; | ||||
4347 | clock1 = cea_mode->clock; | ||||
4348 | clock2 = hdmi_mode_alternate_clock(cea_mode); | ||||
4349 | } else { | ||||
4350 | return; | ||||
4351 | } | ||||
4352 | } | ||||
4353 | |||||
4354 | /* pick whichever is closest */ | ||||
4355 | if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) | ||||
4356 | clock = clock1; | ||||
4357 | else | ||||
4358 | clock = clock2; | ||||
4359 | |||||
4360 | if (mode->clock == clock) | ||||
4361 | return; | ||||
4362 | |||||
4363 | DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",__drm_dbg(DRM_UT_CORE, "detailed mode matches %s VIC %d, adjusting clock %d -> %d\n" , type, vic, mode->clock, clock) | ||||
4364 | type, vic, mode->clock, clock)__drm_dbg(DRM_UT_CORE, "detailed mode matches %s VIC %d, adjusting clock %d -> %d\n" , type, vic, mode->clock, clock); | ||||
4365 | mode->clock = clock; | ||||
4366 | } | ||||
4367 | |||||
4368 | static bool_Bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) | ||||
4369 | { | ||||
4370 | if (cea_db_tag(db) != USE_EXTENDED_TAG0x07) | ||||
4371 | return false0; | ||||
4372 | |||||
4373 | if (db[1] != HDR_STATIC_METADATA_BLOCK0x6) | ||||
4374 | return false0; | ||||
4375 | |||||
4376 | if (cea_db_payload_len(db) < 3) | ||||
4377 | return false0; | ||||
4378 | |||||
4379 | return true1; | ||||
4380 | } | ||||
4381 | |||||
4382 | static uint8_t eotf_supported(const u8 *edid_ext) | ||||
4383 | { | ||||
4384 | return edid_ext[2] & | ||||
4385 | (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR)(1UL << (HDMI_EOTF_TRADITIONAL_GAMMA_SDR)) | | ||||
4386 | BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR)(1UL << (HDMI_EOTF_TRADITIONAL_GAMMA_HDR)) | | ||||
4387 | BIT(HDMI_EOTF_SMPTE_ST2084)(1UL << (HDMI_EOTF_SMPTE_ST2084)) | | ||||
4388 | BIT(HDMI_EOTF_BT_2100_HLG)(1UL << (HDMI_EOTF_BT_2100_HLG))); | ||||
4389 | } | ||||
4390 | |||||
4391 | static uint8_t hdr_metadata_type(const u8 *edid_ext) | ||||
4392 | { | ||||
4393 | return edid_ext[3] & | ||||
4394 | BIT(HDMI_STATIC_METADATA_TYPE1)(1UL << (HDMI_STATIC_METADATA_TYPE1)); | ||||
4395 | } | ||||
4396 | |||||
4397 | static void | ||||
4398 | drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) | ||||
4399 | { | ||||
4400 | u16 len; | ||||
4401 | |||||
4402 | len = cea_db_payload_len(db); | ||||
4403 | |||||
4404 | connector->hdr_sink_metadata.hdmi_type1.eotf = | ||||
4405 | eotf_supported(db); | ||||
4406 | connector->hdr_sink_metadata.hdmi_type1.metadata_type = | ||||
4407 | hdr_metadata_type(db); | ||||
4408 | |||||
4409 | if (len >= 4) | ||||
4410 | connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; | ||||
4411 | if (len >= 5) | ||||
4412 | connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; | ||||
4413 | if (len >= 6) | ||||
4414 | connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; | ||||
4415 | } | ||||
4416 | |||||
4417 | static void | ||||
4418 | drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) | ||||
4419 | { | ||||
4420 | u8 len = cea_db_payload_len(db); | ||||
4421 | |||||
4422 | if (len >= 6 && (db[6] & (1 << 7))) | ||||
4423 | connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= DRM_ELD_SUPPORTS_AI(1 << 1); | ||||
4424 | if (len >= 8) { | ||||
4425 | connector->latency_present[0] = db[8] >> 7; | ||||
4426 | connector->latency_present[1] = (db[8] >> 6) & 1; | ||||
4427 | } | ||||
4428 | if (len >= 9) | ||||
4429 | connector->video_latency[0] = db[9]; | ||||
4430 | if (len >= 10) | ||||
4431 | connector->audio_latency[0] = db[10]; | ||||
4432 | if (len >= 11) | ||||
4433 | connector->video_latency[1] = db[11]; | ||||
4434 | if (len >= 12) | ||||
4435 | connector->audio_latency[1] = db[12]; | ||||
4436 | |||||
4437 | DRM_DEBUG_KMS("HDMI: latency present %d %d, "__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4438 | "video latency %d %d, "__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4439 | "audio latency %d %d\n",__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4440 | connector->latency_present[0],__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4441 | connector->latency_present[1],__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4442 | connector->video_latency[0],__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4443 | connector->video_latency[1],__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4444 | connector->audio_latency[0],__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]) | ||||
4445 | connector->audio_latency[1])__drm_dbg(DRM_UT_KMS, "HDMI: latency present %d %d, " "video latency %d %d, " "audio latency %d %d\n", connector->latency_present[0], connector ->latency_present[1], connector->video_latency[0], connector ->video_latency[1], connector->audio_latency[0], connector ->audio_latency[1]); | ||||
4446 | } | ||||
4447 | |||||
4448 | static void | ||||
4449 | monitor_name(struct detailed_timing *t, void *data) | ||||
4450 | { | ||||
4451 | if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME0xfc)) | ||||
4452 | return; | ||||
4453 | |||||
4454 | *(u8 **)data = t->data.other_data.data.str.str; | ||||
4455 | } | ||||
4456 | |||||
4457 | static int get_monitor_name(struct edid *edid, char name[13]) | ||||
4458 | { | ||||
4459 | char *edid_name = NULL((void *)0); | ||||
4460 | int mnl; | ||||
4461 | |||||
4462 | if (!edid || !name) | ||||
4463 | return 0; | ||||
4464 | |||||
4465 | drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); | ||||
4466 | for (mnl = 0; edid_name && mnl < 13; mnl++) { | ||||
4467 | if (edid_name[mnl] == 0x0a) | ||||
4468 | break; | ||||
4469 | |||||
4470 | name[mnl] = edid_name[mnl]; | ||||
4471 | } | ||||
4472 | |||||
4473 | return mnl; | ||||
4474 | } | ||||
4475 | |||||
4476 | /** | ||||
4477 | * drm_edid_get_monitor_name - fetch the monitor name from the edid | ||||
4478 | * @edid: monitor EDID information | ||||
4479 | * @name: pointer to a character array to hold the name of the monitor | ||||
4480 | * @bufsize: The size of the name buffer (should be at least 14 chars.) | ||||
4481 | * | ||||
4482 | */ | ||||
4483 | void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) | ||||
4484 | { | ||||
4485 | int name_length; | ||||
4486 | char buf[13]; | ||||
4487 | |||||
4488 | if (bufsize <= 0) | ||||
4489 | return; | ||||
4490 | |||||
4491 | name_length = min(get_monitor_name(edid, buf), bufsize - 1)(((get_monitor_name(edid, buf))<(bufsize - 1))?(get_monitor_name (edid, buf)):(bufsize - 1)); | ||||
4492 | memcpy(name, buf, name_length)__builtin_memcpy((name), (buf), (name_length)); | ||||
4493 | name[name_length] = '\0'; | ||||
4494 | } | ||||
4495 | EXPORT_SYMBOL(drm_edid_get_monitor_name); | ||||
4496 | |||||
4497 | static void clear_eld(struct drm_connector *connector) | ||||
4498 | { | ||||
4499 | memset(connector->eld, 0, sizeof(connector->eld))__builtin_memset((connector->eld), (0), (sizeof(connector-> eld))); | ||||
4500 | |||||
4501 | connector->latency_present[0] = false0; | ||||
4502 | connector->latency_present[1] = false0; | ||||
4503 | connector->video_latency[0] = 0; | ||||
4504 | connector->audio_latency[0] = 0; | ||||
4505 | connector->video_latency[1] = 0; | ||||
4506 | connector->audio_latency[1] = 0; | ||||
4507 | } | ||||
4508 | |||||
4509 | /* | ||||
4510 | * drm_edid_to_eld - build ELD from EDID | ||||
4511 | * @connector: connector corresponding to the HDMI/DP sink | ||||
4512 | * @edid: EDID to parse | ||||
4513 | * | ||||
4514 | * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The | ||||
4515 | * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. | ||||
4516 | */ | ||||
4517 | static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) | ||||
4518 | { | ||||
4519 | uint8_t *eld = connector->eld; | ||||
4520 | u8 *cea; | ||||
4521 | u8 *db; | ||||
4522 | int total_sad_count = 0; | ||||
4523 | int mnl; | ||||
4524 | int dbl; | ||||
4525 | |||||
4526 | clear_eld(connector); | ||||
4527 | |||||
4528 | if (!edid) | ||||
4529 | return; | ||||
4530 | |||||
4531 | cea = drm_find_cea_extension(edid); | ||||
4532 | if (!cea) { | ||||
4533 | DRM_DEBUG_KMS("ELD: no CEA Extension found\n")__drm_dbg(DRM_UT_KMS, "ELD: no CEA Extension found\n"); | ||||
4534 | return; | ||||
4535 | } | ||||
4536 | |||||
4537 | mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING20]); | ||||
4538 | DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING])__drm_dbg(DRM_UT_KMS, "ELD monitor %s\n", &eld[20]); | ||||
4539 | |||||
4540 | eld[DRM_ELD_CEA_EDID_VER_MNL4] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT5; | ||||
4541 | eld[DRM_ELD_CEA_EDID_VER_MNL4] |= mnl; | ||||
4542 | |||||
4543 | eld[DRM_ELD_VER0] = DRM_ELD_VER_CEA861D(2 << 3); | ||||
4544 | |||||
4545 | eld[DRM_ELD_MANUFACTURER_NAME016] = edid->mfg_id[0]; | ||||
4546 | eld[DRM_ELD_MANUFACTURER_NAME117] = edid->mfg_id[1]; | ||||
4547 | eld[DRM_ELD_PRODUCT_CODE018] = edid->prod_code[0]; | ||||
4548 | eld[DRM_ELD_PRODUCT_CODE119] = edid->prod_code[1]; | ||||
4549 | |||||
4550 | if (cea_revision(cea) >= 3) { | ||||
4551 | int i, start, end; | ||||
4552 | int sad_count; | ||||
4553 | |||||
4554 | if (cea_db_offsets(cea, &start, &end)) { | ||||
4555 | start = 0; | ||||
4556 | end = 0; | ||||
4557 | } | ||||
4558 | |||||
4559 | for_each_cea_db(cea, i, start, end)for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len (&(cea)[(i)]) < (end); (i) += cea_db_payload_len(& (cea)[(i)]) + 1) { | ||||
4560 | db = &cea[i]; | ||||
4561 | dbl = cea_db_payload_len(db); | ||||
4562 | |||||
4563 | switch (cea_db_tag(db)) { | ||||
4564 | case AUDIO_BLOCK0x01: | ||||
4565 | /* Audio Data Block, contains SADs */ | ||||
4566 | sad_count = min(dbl / 3, 15 - total_sad_count)(((dbl / 3)<(15 - total_sad_count))?(dbl / 3):(15 - total_sad_count )); | ||||
4567 | if (sad_count >= 1) | ||||
4568 | memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],__builtin_memcpy((&eld[(20 + (mnl) + 3 * (total_sad_count ))]), (&db[1]), (sad_count * 3)) | ||||
4569 | &db[1], sad_count * 3)__builtin_memcpy((&eld[(20 + (mnl) + 3 * (total_sad_count ))]), (&db[1]), (sad_count * 3)); | ||||
4570 | total_sad_count += sad_count; | ||||
4571 | break; | ||||
4572 | case SPEAKER_BLOCK0x04: | ||||
4573 | /* Speaker Allocation Data Block */ | ||||
4574 | if (dbl >= 1) | ||||
4575 | eld[DRM_ELD_SPEAKER7] = db[1]; | ||||
4576 | break; | ||||
4577 | case VENDOR_BLOCK0x03: | ||||
4578 | /* HDMI Vendor-Specific Data Block */ | ||||
4579 | if (cea_db_is_hdmi_vsdb(db)) | ||||
4580 | drm_parse_hdmi_vsdb_audio(connector, db); | ||||
4581 | break; | ||||
4582 | default: | ||||
4583 | break; | ||||
4584 | } | ||||
4585 | } | ||||
4586 | } | ||||
4587 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT4; | ||||
4588 | |||||
4589 | if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort10 || | ||||
4590 | connector->connector_type == DRM_MODE_CONNECTOR_eDP14) | ||||
4591 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= DRM_ELD_CONN_TYPE_DP(1 << 2); | ||||
4592 | else | ||||
4593 | eld[DRM_ELD_SAD_COUNT_CONN_TYPE5] |= DRM_ELD_CONN_TYPE_HDMI(0 << 2); | ||||
4594 | |||||
4595 | eld[DRM_ELD_BASELINE_ELD_LEN2] = | ||||
4596 | DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4)(((drm_eld_calc_baseline_block_size(eld)) + ((4) - 1)) / (4)); | ||||
4597 | |||||
4598 | DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",__drm_dbg(DRM_UT_KMS, "ELD size %d, SAD count %d\n", drm_eld_size (eld), total_sad_count) | ||||
4599 | drm_eld_size(eld), total_sad_count)__drm_dbg(DRM_UT_KMS, "ELD size %d, SAD count %d\n", drm_eld_size (eld), total_sad_count); | ||||
4600 | } | ||||
4601 | |||||
4602 | /** | ||||
4603 | * drm_edid_to_sad - extracts SADs from EDID | ||||
4604 | * @edid: EDID to parse | ||||
4605 | * @sads: pointer that will be set to the extracted SADs | ||||
4606 | * | ||||
4607 | * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. | ||||
4608 | * | ||||
4609 | * Note: The returned pointer needs to be freed using kfree(). | ||||
4610 | * | ||||
4611 | * Return: The number of found SADs or negative number on error. | ||||
4612 | */ | ||||
4613 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) | ||||
4614 | { | ||||
4615 | int count = 0; | ||||
4616 | int i, start, end, dbl; | ||||
4617 | u8 *cea; | ||||
4618 | |||||
4619 | cea = drm_find_cea_extension(edid); | ||||
4620 | if (!cea) { | ||||
4621 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n")__drm_dbg(DRM_UT_KMS, "SAD: no CEA Extension found\n"); | ||||
4622 | return 0; | ||||
4623 | } | ||||
4624 | |||||
4625 | if (cea_revision(cea) < 3) { | ||||
4626 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n")__drm_dbg(DRM_UT_KMS, "SAD: wrong CEA revision\n"); | ||||
4627 | return 0; | ||||
4628 | } | ||||
4629 | |||||
4630 | if (cea_db_offsets(cea, &start, &end)) { | ||||
4631 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n")__drm_dbg(DRM_UT_KMS, "SAD: invalid data block offsets\n"); | ||||
4632 | return -EPROTO95; | ||||
4633 | } | ||||
4634 | |||||
4635 | for_each_cea_db(cea, i, start, end)for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len (&(cea)[(i)]) < (end); (i) += cea_db_payload_len(& (cea)[(i)]) + 1) { | ||||
4636 | u8 *db = &cea[i]; | ||||
4637 | |||||
4638 | if (cea_db_tag(db) == AUDIO_BLOCK0x01) { | ||||
4639 | int j; | ||||
4640 | |||||
4641 | dbl = cea_db_payload_len(db); | ||||
4642 | |||||
4643 | count = dbl / 3; /* SAD is 3B */ | ||||
4644 | *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL(0x0001 | 0x0004)); | ||||
4645 | if (!*sads) | ||||
4646 | return -ENOMEM12; | ||||
4647 | for (j = 0; j < count; j++) { | ||||
4648 | u8 *sad = &db[1 + j * 3]; | ||||
4649 | |||||
4650 | (*sads)[j].format = (sad[0] & 0x78) >> 3; | ||||
4651 | (*sads)[j].channels = sad[0] & 0x7; | ||||
4652 | (*sads)[j].freq = sad[1] & 0x7F; | ||||
4653 | (*sads)[j].byte2 = sad[2]; | ||||
4654 | } | ||||
4655 | break; | ||||
4656 | } | ||||
4657 | } | ||||
4658 | |||||
4659 | return count; | ||||
4660 | } | ||||
4661 | EXPORT_SYMBOL(drm_edid_to_sad); | ||||
4662 | |||||
4663 | /** | ||||
4664 | * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID | ||||
4665 | * @edid: EDID to parse | ||||
4666 | * @sadb: pointer to the speaker block | ||||
4667 | * | ||||
4668 | * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. | ||||
4669 | * | ||||
4670 | * Note: The returned pointer needs to be freed using kfree(). | ||||
4671 | * | ||||
4672 | * Return: The number of found Speaker Allocation Blocks or negative number on | ||||
4673 | * error. | ||||
4674 | */ | ||||
4675 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) | ||||
4676 | { | ||||
4677 | int count = 0; | ||||
4678 | int i, start, end, dbl; | ||||
4679 | const u8 *cea; | ||||
4680 | |||||
4681 | cea = drm_find_cea_extension(edid); | ||||
4682 | if (!cea) { | ||||
4683 | DRM_DEBUG_KMS("SAD: no CEA Extension found\n")__drm_dbg(DRM_UT_KMS, "SAD: no CEA Extension found\n"); | ||||
4684 | return 0; | ||||
4685 | } | ||||
4686 | |||||
4687 | if (cea_revision(cea) < 3) { | ||||
4688 | DRM_DEBUG_KMS("SAD: wrong CEA revision\n")__drm_dbg(DRM_UT_KMS, "SAD: wrong CEA revision\n"); | ||||
4689 | return 0; | ||||
4690 | } | ||||
4691 | |||||
4692 | if (cea_db_offsets(cea, &start, &end)) { | ||||
4693 | DRM_DEBUG_KMS("SAD: invalid data block offsets\n")__drm_dbg(DRM_UT_KMS, "SAD: invalid data block offsets\n"); | ||||
4694 | return -EPROTO95; | ||||
4695 | } | ||||
4696 | |||||
4697 | for_each_cea_db(cea, i, start, end)for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len (&(cea)[(i)]) < (end); (i) += cea_db_payload_len(& (cea)[(i)]) + 1) { | ||||
4698 | const u8 *db = &cea[i]; | ||||
4699 | |||||
4700 | if (cea_db_tag(db) == SPEAKER_BLOCK0x04) { | ||||
4701 | dbl = cea_db_payload_len(db); | ||||
4702 | |||||
4703 | /* Speaker Allocation Data Block */ | ||||
4704 | if (dbl == 3) { | ||||
4705 | *sadb = kmemdup(&db[1], dbl, GFP_KERNEL(0x0001 | 0x0004)); | ||||
4706 | if (!*sadb) | ||||
4707 | return -ENOMEM12; | ||||
4708 | count = dbl; | ||||
4709 | break; | ||||
4710 | } | ||||
4711 | } | ||||
4712 | } | ||||
4713 | |||||
4714 | return count; | ||||
4715 | } | ||||
4716 | EXPORT_SYMBOL(drm_edid_to_speaker_allocation); | ||||
4717 | |||||
4718 | /** | ||||
4719 | * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay | ||||
4720 | * @connector: connector associated with the HDMI/DP sink | ||||
4721 | * @mode: the display mode | ||||
4722 | * | ||||
4723 | * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if | ||||
4724 | * the sink doesn't support audio or video. | ||||
4725 | */ | ||||
4726 | int drm_av_sync_delay(struct drm_connector *connector, | ||||
4727 | const struct drm_display_mode *mode) | ||||
4728 | { | ||||
4729 | int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)); | ||||
4730 | int a, v; | ||||
4731 | |||||
4732 | if (!connector->latency_present[0]) | ||||
4733 | return 0; | ||||
4734 | if (!connector->latency_present[1]) | ||||
4735 | i = 0; | ||||
4736 | |||||
4737 | a = connector->audio_latency[i]; | ||||
4738 | v = connector->video_latency[i]; | ||||
4739 | |||||
4740 | /* | ||||
4741 | * HDMI/DP sink doesn't support audio or video? | ||||
4742 | */ | ||||
4743 | if (a == 255 || v == 255) | ||||
4744 | return 0; | ||||
4745 | |||||
4746 | /* | ||||
4747 | * Convert raw EDID values to millisecond. | ||||
4748 | * Treat unknown latency as 0ms. | ||||
4749 | */ | ||||
4750 | if (a) | ||||
4751 | a = min(2 * (a - 1), 500)(((2 * (a - 1))<(500))?(2 * (a - 1)):(500)); | ||||
4752 | if (v) | ||||
4753 | v = min(2 * (v - 1), 500)(((2 * (v - 1))<(500))?(2 * (v - 1)):(500)); | ||||
4754 | |||||
4755 | return max(v - a, 0)(((v - a)>(0))?(v - a):(0)); | ||||
4756 | } | ||||
4757 | EXPORT_SYMBOL(drm_av_sync_delay); | ||||
4758 | |||||
4759 | /** | ||||
4760 | * drm_detect_hdmi_monitor - detect whether monitor is HDMI | ||||
4761 | * @edid: monitor EDID information | ||||
4762 | * | ||||
4763 | * Parse the CEA extension according to CEA-861-B. | ||||
4764 | * | ||||
4765 | * Drivers that have added the modes parsed from EDID to drm_display_info | ||||
4766 | * should use &drm_display_info.is_hdmi instead of calling this function. | ||||
4767 | * | ||||
4768 | * Return: True if the monitor is HDMI, false if not or unknown. | ||||
4769 | */ | ||||
4770 | bool_Bool drm_detect_hdmi_monitor(struct edid *edid) | ||||
4771 | { | ||||
4772 | u8 *edid_ext; | ||||
4773 | int i; | ||||
4774 | int start_offset, end_offset; | ||||
4775 | |||||
4776 | edid_ext = drm_find_cea_extension(edid); | ||||
4777 | if (!edid_ext) | ||||
4778 | return false0; | ||||
4779 | |||||
4780 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) | ||||
4781 | return false0; | ||||
4782 | |||||
4783 | /* | ||||
4784 | * Because HDMI identifier is in Vendor Specific Block, | ||||
4785 | * search it from all data blocks of CEA extension. | ||||
4786 | */ | ||||
4787 | for_each_cea_db(edid_ext, i, start_offset, end_offset)for ((i) = (start_offset); (i) < (end_offset) && ( i) + cea_db_payload_len(&(edid_ext)[(i)]) < (end_offset ); (i) += cea_db_payload_len(&(edid_ext)[(i)]) + 1) { | ||||
4788 | if (cea_db_is_hdmi_vsdb(&edid_ext[i])) | ||||
4789 | return true1; | ||||
4790 | } | ||||
4791 | |||||
4792 | return false0; | ||||
4793 | } | ||||
4794 | EXPORT_SYMBOL(drm_detect_hdmi_monitor); | ||||
4795 | |||||
4796 | /** | ||||
4797 | * drm_detect_monitor_audio - check monitor audio capability | ||||
4798 | * @edid: EDID block to scan | ||||
4799 | * | ||||
4800 | * Monitor should have CEA extension block. | ||||
4801 | * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic | ||||
4802 | * audio' only. If there is any audio extension block and supported | ||||
4803 | * audio format, assume at least 'basic audio' support, even if 'basic | ||||
4804 | * audio' is not defined in EDID. | ||||
4805 | * | ||||
4806 | * Return: True if the monitor supports audio, false otherwise. | ||||
4807 | */ | ||||
4808 | bool_Bool drm_detect_monitor_audio(struct edid *edid) | ||||
4809 | { | ||||
4810 | u8 *edid_ext; | ||||
4811 | int i, j; | ||||
4812 | bool_Bool has_audio = false0; | ||||
4813 | int start_offset, end_offset; | ||||
4814 | |||||
4815 | edid_ext = drm_find_cea_extension(edid); | ||||
4816 | if (!edid_ext) | ||||
4817 | goto end; | ||||
4818 | |||||
4819 | has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO(1 << 6)) != 0); | ||||
4820 | |||||
4821 | if (has_audio) { | ||||
4822 | DRM_DEBUG_KMS("Monitor has basic audio support\n")__drm_dbg(DRM_UT_KMS, "Monitor has basic audio support\n"); | ||||
4823 | goto end; | ||||
4824 | } | ||||
4825 | |||||
4826 | if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) | ||||
4827 | goto end; | ||||
4828 | |||||
4829 | for_each_cea_db(edid_ext, i, start_offset, end_offset)for ((i) = (start_offset); (i) < (end_offset) && ( i) + cea_db_payload_len(&(edid_ext)[(i)]) < (end_offset ); (i) += cea_db_payload_len(&(edid_ext)[(i)]) + 1) { | ||||
4830 | if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK0x01) { | ||||
4831 | has_audio = true1; | ||||
4832 | for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) | ||||
4833 | DRM_DEBUG_KMS("CEA audio format %d\n",__drm_dbg(DRM_UT_KMS, "CEA audio format %d\n", (edid_ext[i + j ] >> 3) & 0xf) | ||||
4834 | (edid_ext[i + j] >> 3) & 0xf)__drm_dbg(DRM_UT_KMS, "CEA audio format %d\n", (edid_ext[i + j ] >> 3) & 0xf); | ||||
4835 | goto end; | ||||
4836 | } | ||||
4837 | } | ||||
4838 | end: | ||||
4839 | return has_audio; | ||||
4840 | } | ||||
4841 | EXPORT_SYMBOL(drm_detect_monitor_audio); | ||||
4842 | |||||
4843 | |||||
4844 | /** | ||||
4845 | * drm_default_rgb_quant_range - default RGB quantization range | ||||
4846 | * @mode: display mode | ||||
4847 | * | ||||
4848 | * Determine the default RGB quantization range for the mode, | ||||
4849 | * as specified in CEA-861. | ||||
4850 | * | ||||
4851 | * Return: The default RGB quantization range for the mode | ||||
4852 | */ | ||||
4853 | enum hdmi_quantization_range | ||||
4854 | drm_default_rgb_quant_range(const struct drm_display_mode *mode) | ||||
4855 | { | ||||
4856 | /* All CEA modes other than VIC 1 use limited quantization range. */ | ||||
4857 | return drm_match_cea_mode(mode) > 1 ? | ||||
4858 | HDMI_QUANTIZATION_RANGE_LIMITED : | ||||
4859 | HDMI_QUANTIZATION_RANGE_FULL; | ||||
4860 | } | ||||
4861 | EXPORT_SYMBOL(drm_default_rgb_quant_range); | ||||
4862 | |||||
4863 | static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) | ||||
4864 | { | ||||
4865 | struct drm_display_info *info = &connector->display_info; | ||||
4866 | |||||
4867 | DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2])__drm_dbg(DRM_UT_KMS, "CEA VCDB 0x%02x\n", db[2]); | ||||
4868 | |||||
4869 | if (db[2] & EDID_CEA_VCDB_QS(1 << 6)) | ||||
4870 | info->rgb_quant_range_selectable = true1; | ||||
4871 | } | ||||
4872 | |||||
4873 | static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, | ||||
4874 | const u8 *db) | ||||
4875 | { | ||||
4876 | u8 dc_mask; | ||||
4877 | struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; | ||||
4878 | |||||
4879 | dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK((1 << 2) | (1 << 1) | (1 << 0)); | ||||
4880 | hdmi->y420_dc_modes = dc_mask; | ||||
4881 | } | ||||
4882 | |||||
4883 | static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, | ||||
4884 | const u8 *hf_vsdb) | ||||
4885 | { | ||||
4886 | struct drm_display_info *display = &connector->display_info; | ||||
4887 | struct drm_hdmi_info *hdmi = &display->hdmi; | ||||
4888 | |||||
4889 | display->has_hdmi_infoframe = true1; | ||||
4890 | |||||
4891 | if (hf_vsdb[6] & 0x80) { | ||||
4892 | hdmi->scdc.supported = true1; | ||||
4893 | if (hf_vsdb[6] & 0x40) | ||||
4894 | hdmi->scdc.read_request = true1; | ||||
4895 | } | ||||
4896 | |||||
4897 | /* | ||||
4898 | * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. | ||||
4899 | * And as per the spec, three factors confirm this: | ||||
4900 | * * Availability of a HF-VSDB block in EDID (check) | ||||
4901 | * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) | ||||
4902 | * * SCDC support available (let's check) | ||||
4903 | * Lets check it out. | ||||
4904 | */ | ||||
4905 | |||||
4906 | if (hf_vsdb[5]) { | ||||
4907 | /* max clock is 5000 KHz times block value */ | ||||
4908 | u32 max_tmds_clock = hf_vsdb[5] * 5000; | ||||
4909 | struct drm_scdc *scdc = &hdmi->scdc; | ||||
4910 | |||||
4911 | if (max_tmds_clock > 340000) { | ||||
4912 | display->max_tmds_clock = max_tmds_clock; | ||||
4913 | DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",__drm_dbg(DRM_UT_KMS, "HF-VSDB: max TMDS clock %d kHz\n", display ->max_tmds_clock) | ||||
4914 | display->max_tmds_clock)__drm_dbg(DRM_UT_KMS, "HF-VSDB: max TMDS clock %d kHz\n", display ->max_tmds_clock); | ||||
4915 | } | ||||
4916 | |||||
4917 | if (scdc->supported) { | ||||
4918 | scdc->scrambling.supported = true1; | ||||
4919 | |||||
4920 | /* Few sinks support scrambling for clocks < 340M */ | ||||
4921 | if ((hf_vsdb[6] & 0x8)) | ||||
4922 | scdc->scrambling.low_rates = true1; | ||||
4923 | } | ||||
4924 | } | ||||
4925 | |||||
4926 | drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); | ||||
4927 | } | ||||
4928 | |||||
4929 | static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, | ||||
4930 | const u8 *hdmi) | ||||
4931 | { | ||||
4932 | struct drm_display_info *info = &connector->display_info; | ||||
4933 | unsigned int dc_bpc = 0; | ||||
4934 | |||||
4935 | /* HDMI supports at least 8 bpc */ | ||||
4936 | info->bpc = 8; | ||||
4937 | |||||
4938 | if (cea_db_payload_len(hdmi) < 6) | ||||
4939 | return; | ||||
4940 | |||||
4941 | if (hdmi[6] & DRM_EDID_HDMI_DC_30(1 << 4)) { | ||||
4942 | dc_bpc = 10; | ||||
4943 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30(1 << 4); | ||||
4944 | DRM_DEBUG("%s: HDMI sink does deep color 30.\n",__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does deep color 30.\n", connector->name) | ||||
4945 | connector->name)__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does deep color 30.\n", connector->name); | ||||
4946 | } | ||||
4947 | |||||
4948 | if (hdmi[6] & DRM_EDID_HDMI_DC_36(1 << 5)) { | ||||
4949 | dc_bpc = 12; | ||||
4950 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36(1 << 5); | ||||
4951 | DRM_DEBUG("%s: HDMI sink does deep color 36.\n",__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does deep color 36.\n", connector->name) | ||||
4952 | connector->name)__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does deep color 36.\n", connector->name); | ||||
4953 | } | ||||
4954 | |||||
4955 | if (hdmi[6] & DRM_EDID_HDMI_DC_48(1 << 6)) { | ||||
4956 | dc_bpc = 16; | ||||
4957 | info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48(1 << 6); | ||||
4958 | DRM_DEBUG("%s: HDMI sink does deep color 48.\n",__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does deep color 48.\n", connector->name) | ||||
4959 | connector->name)__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does deep color 48.\n", connector->name); | ||||
4960 | } | ||||
4961 | |||||
4962 | if (dc_bpc == 0) { | ||||
4963 | DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",__drm_dbg(DRM_UT_CORE, "%s: No deep color support on this HDMI sink.\n" , connector->name) | ||||
4964 | connector->name)__drm_dbg(DRM_UT_CORE, "%s: No deep color support on this HDMI sink.\n" , connector->name); | ||||
4965 | return; | ||||
4966 | } | ||||
4967 | |||||
4968 | DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",__drm_dbg(DRM_UT_CORE, "%s: Assigning HDMI sink color depth as %d bpc.\n" , connector->name, dc_bpc) | ||||
4969 | connector->name, dc_bpc)__drm_dbg(DRM_UT_CORE, "%s: Assigning HDMI sink color depth as %d bpc.\n" , connector->name, dc_bpc); | ||||
4970 | info->bpc = dc_bpc; | ||||
4971 | |||||
4972 | /* | ||||
4973 | * Deep color support mandates RGB444 support for all video | ||||
4974 | * modes and forbids YCRCB422 support for all video modes per | ||||
4975 | * HDMI 1.3 spec. | ||||
4976 | */ | ||||
4977 | info->color_formats = DRM_COLOR_FORMAT_RGB444(1<<0); | ||||
4978 | |||||
4979 | /* YCRCB444 is optional according to spec. */ | ||||
4980 | if (hdmi[6] & DRM_EDID_HDMI_DC_Y444(1 << 3)) { | ||||
4981 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444(1<<1); | ||||
4982 | DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does YCRCB444 in deep color.\n" , connector->name) | ||||
4983 | connector->name)__drm_dbg(DRM_UT_CORE, "%s: HDMI sink does YCRCB444 in deep color.\n" , connector->name); | ||||
4984 | } | ||||
4985 | |||||
4986 | /* | ||||
4987 | * Spec says that if any deep color mode is supported at all, | ||||
4988 | * then deep color 36 bit must be supported. | ||||
4989 | */ | ||||
4990 | if (!(hdmi[6] & DRM_EDID_HDMI_DC_36(1 << 5))) { | ||||
4991 | DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",__drm_dbg(DRM_UT_CORE, "%s: HDMI sink should do DC_36, but does not!\n" , connector->name) | ||||
4992 | connector->name)__drm_dbg(DRM_UT_CORE, "%s: HDMI sink should do DC_36, but does not!\n" , connector->name); | ||||
4993 | } | ||||
4994 | } | ||||
4995 | |||||
4996 | static void | ||||
4997 | drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) | ||||
4998 | { | ||||
4999 | struct drm_display_info *info = &connector->display_info; | ||||
5000 | u8 len = cea_db_payload_len(db); | ||||
5001 | |||||
5002 | info->is_hdmi = true1; | ||||
5003 | |||||
5004 | if (len >= 6) | ||||
5005 | info->dvi_dual = db[6] & 1; | ||||
5006 | if (len >= 7) | ||||
5007 | info->max_tmds_clock = db[7] * 5000; | ||||
5008 | |||||
5009 | DRM_DEBUG_KMS("HDMI: DVI dual %d, "__drm_dbg(DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock) | ||||
5010 | "max TMDS clock %d kHz\n",__drm_dbg(DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock) | ||||
5011 | info->dvi_dual,__drm_dbg(DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock) | ||||
5012 | info->max_tmds_clock)__drm_dbg(DRM_UT_KMS, "HDMI: DVI dual %d, " "max TMDS clock %d kHz\n" , info->dvi_dual, info->max_tmds_clock); | ||||
5013 | |||||
5014 | drm_parse_hdmi_deep_color_info(connector, db); | ||||
5015 | } | ||||
5016 | |||||
5017 | static void drm_parse_cea_ext(struct drm_connector *connector, | ||||
5018 | const struct edid *edid) | ||||
5019 | { | ||||
5020 | struct drm_display_info *info = &connector->display_info; | ||||
5021 | const u8 *edid_ext; | ||||
5022 | int i, start, end; | ||||
5023 | |||||
5024 | edid_ext = drm_find_cea_extension(edid); | ||||
5025 | if (!edid_ext) | ||||
5026 | return; | ||||
5027 | |||||
5028 | info->cea_rev = edid_ext[1]; | ||||
5029 | |||||
5030 | /* The existence of a CEA block should imply RGB support */ | ||||
5031 | info->color_formats = DRM_COLOR_FORMAT_RGB444(1<<0); | ||||
5032 | if (edid_ext[3] & EDID_CEA_YCRCB444(1 << 5)) | ||||
5033 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444(1<<1); | ||||
5034 | if (edid_ext[3] & EDID_CEA_YCRCB422(1 << 4)) | ||||
5035 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422(1<<2); | ||||
5036 | |||||
5037 | if (cea_db_offsets(edid_ext, &start, &end)) | ||||
5038 | return; | ||||
5039 | |||||
5040 | for_each_cea_db(edid_ext, i, start, end)for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len (&(edid_ext)[(i)]) < (end); (i) += cea_db_payload_len( &(edid_ext)[(i)]) + 1) { | ||||
5041 | const u8 *db = &edid_ext[i]; | ||||
5042 | |||||
5043 | if (cea_db_is_hdmi_vsdb(db)) | ||||
5044 | drm_parse_hdmi_vsdb_video(connector, db); | ||||
5045 | if (cea_db_is_hdmi_forum_vsdb(db)) | ||||
5046 | drm_parse_hdmi_forum_vsdb(connector, db); | ||||
5047 | if (cea_db_is_y420cmdb(db)) | ||||
5048 | drm_parse_y420cmdb_bitmap(connector, db); | ||||
5049 | if (cea_db_is_vcdb(db)) | ||||
5050 | drm_parse_vcdb(connector, db); | ||||
5051 | if (cea_db_is_hdmi_hdr_metadata_block(db)) | ||||
5052 | drm_parse_hdr_metadata_block(connector, db); | ||||
5053 | } | ||||
5054 | } | ||||
5055 | |||||
5056 | static | ||||
5057 | void get_monitor_range(struct detailed_timing *timing, | ||||
5058 | void *info_monitor_range) | ||||
5059 | { | ||||
5060 | struct drm_monitor_range_info *monitor_range = info_monitor_range; | ||||
5061 | const struct detailed_non_pixel *data = &timing->data.other_data; | ||||
5062 | const struct detailed_data_monitor_range *range = &data->data.range; | ||||
5063 | |||||
5064 | if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE0xfd)) | ||||
5065 | return; | ||||
5066 | |||||
5067 | /* | ||||
5068 | * Check for flag range limits only. If flag == 1 then | ||||
5069 | * no additional timing information provided. | ||||
5070 | * Default GTF, GTF Secondary curve and CVT are not | ||||
5071 | * supported | ||||
5072 | */ | ||||
5073 | if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG0x01) | ||||
5074 | return; | ||||
5075 | |||||
5076 | monitor_range->min_vfreq = range->min_vfreq; | ||||
5077 | monitor_range->max_vfreq = range->max_vfreq; | ||||
5078 | } | ||||
5079 | |||||
5080 | static | ||||
5081 | void drm_get_monitor_range(struct drm_connector *connector, | ||||
5082 | const struct edid *edid) | ||||
5083 | { | ||||
5084 | struct drm_display_info *info = &connector->display_info; | ||||
5085 | |||||
5086 | if (!version_greater(edid, 1, 1)(((edid)->version > (1)) || ((edid)->version == (1) && (edid)->revision > (1)))) | ||||
5087 | return; | ||||
5088 | |||||
5089 | drm_for_each_detailed_block((u8 *)edid, get_monitor_range, | ||||
5090 | &info->monitor_range); | ||||
5091 | |||||
5092 | DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",__drm_dbg(DRM_UT_KMS, "Supported Monitor Refresh rate range is %d Hz - %d Hz\n" , info->monitor_range.min_vfreq, info->monitor_range.max_vfreq ) | ||||
5093 | info->monitor_range.min_vfreq,__drm_dbg(DRM_UT_KMS, "Supported Monitor Refresh rate range is %d Hz - %d Hz\n" , info->monitor_range.min_vfreq, info->monitor_range.max_vfreq ) | ||||
5094 | info->monitor_range.max_vfreq)__drm_dbg(DRM_UT_KMS, "Supported Monitor Refresh rate range is %d Hz - %d Hz\n" , info->monitor_range.min_vfreq, info->monitor_range.max_vfreq ); | ||||
5095 | } | ||||
5096 | |||||
5097 | /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset | ||||
5098 | * all of the values which would have been set from EDID | ||||
5099 | */ | ||||
5100 | void | ||||
5101 | drm_reset_display_info(struct drm_connector *connector) | ||||
5102 | { | ||||
5103 | struct drm_display_info *info = &connector->display_info; | ||||
5104 | |||||
5105 | info->width_mm = 0; | ||||
5106 | info->height_mm = 0; | ||||
5107 | |||||
5108 | info->bpc = 0; | ||||
5109 | info->color_formats = 0; | ||||
5110 | info->cea_rev = 0; | ||||
5111 | info->max_tmds_clock = 0; | ||||
5112 | info->dvi_dual = false0; | ||||
5113 | info->is_hdmi = false0; | ||||
5114 | info->has_hdmi_infoframe = false0; | ||||
5115 | info->rgb_quant_range_selectable = false0; | ||||
5116 | memset(&info->hdmi, 0, sizeof(info->hdmi))__builtin_memset((&info->hdmi), (0), (sizeof(info-> hdmi))); | ||||
5117 | |||||
5118 | info->non_desktop = 0; | ||||
5119 | memset(&info->monitor_range, 0, sizeof(info->monitor_range))__builtin_memset((&info->monitor_range), (0), (sizeof( info->monitor_range))); | ||||
5120 | } | ||||
5121 | |||||
5122 | u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) | ||||
5123 | { | ||||
5124 | struct drm_display_info *info = &connector->display_info; | ||||
5125 | |||||
5126 | u32 quirks = edid_get_quirks(edid); | ||||
5127 | |||||
5128 | drm_reset_display_info(connector); | ||||
5129 | |||||
5130 | info->width_mm = edid->width_cm * 10; | ||||
5131 | info->height_mm = edid->height_cm * 10; | ||||
5132 | |||||
5133 | info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP(1 << 12)); | ||||
5134 | |||||
5135 | drm_get_monitor_range(connector, edid); | ||||
5136 | |||||
5137 | DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop)__drm_dbg(DRM_UT_KMS, "non_desktop set to %d\n", info->non_desktop ); | ||||
5138 | |||||
5139 | if (edid->revision < 3) | ||||
5140 | return quirks; | ||||
5141 | |||||
5142 | if (!(edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7))) | ||||
5143 | return quirks; | ||||
5144 | |||||
5145 | drm_parse_cea_ext(connector, edid); | ||||
5146 | |||||
5147 | /* | ||||
5148 | * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? | ||||
5149 | * | ||||
5150 | * For such displays, the DFP spec 1.0, section 3.10 "EDID support" | ||||
5151 | * tells us to assume 8 bpc color depth if the EDID doesn't have | ||||
5152 | * extensions which tell otherwise. | ||||
5153 | */ | ||||
5154 | if (info->bpc == 0 && edid->revision == 3 && | ||||
5155 | edid->input & DRM_EDID_DIGITAL_DFP_1_X(1 << 0)) { | ||||
5156 | info->bpc = 8; | ||||
5157 | DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",__drm_dbg(DRM_UT_CORE, "%s: Assigning DFP sink color depth as %d bpc.\n" , connector->name, info->bpc) | ||||
5158 | connector->name, info->bpc)__drm_dbg(DRM_UT_CORE, "%s: Assigning DFP sink color depth as %d bpc.\n" , connector->name, info->bpc); | ||||
5159 | } | ||||
5160 | |||||
5161 | /* Only defined for 1.4 with digital displays */ | ||||
5162 | if (edid->revision < 4) | ||||
5163 | return quirks; | ||||
5164 | |||||
5165 | switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK(7 << 4)) { | ||||
5166 | case DRM_EDID_DIGITAL_DEPTH_6(1 << 4): | ||||
5167 | info->bpc = 6; | ||||
5168 | break; | ||||
5169 | case DRM_EDID_DIGITAL_DEPTH_8(2 << 4): | ||||
5170 | info->bpc = 8; | ||||
5171 | break; | ||||
5172 | case DRM_EDID_DIGITAL_DEPTH_10(3 << 4): | ||||
5173 | info->bpc = 10; | ||||
5174 | break; | ||||
5175 | case DRM_EDID_DIGITAL_DEPTH_12(4 << 4): | ||||
5176 | info->bpc = 12; | ||||
5177 | break; | ||||
5178 | case DRM_EDID_DIGITAL_DEPTH_14(5 << 4): | ||||
5179 | info->bpc = 14; | ||||
5180 | break; | ||||
5181 | case DRM_EDID_DIGITAL_DEPTH_16(6 << 4): | ||||
5182 | info->bpc = 16; | ||||
5183 | break; | ||||
5184 | case DRM_EDID_DIGITAL_DEPTH_UNDEF(0 << 4): | ||||
5185 | default: | ||||
5186 | info->bpc = 0; | ||||
5187 | break; | ||||
5188 | } | ||||
5189 | |||||
5190 | DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",__drm_dbg(DRM_UT_CORE, "%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n" , connector->name, info->bpc) | ||||
5191 | connector->name, info->bpc)__drm_dbg(DRM_UT_CORE, "%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n" , connector->name, info->bpc); | ||||
5192 | |||||
5193 | info->color_formats |= DRM_COLOR_FORMAT_RGB444(1<<0); | ||||
5194 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444(1 << 3)) | ||||
5195 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB444(1<<1); | ||||
5196 | if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422(2 << 3)) | ||||
5197 | info->color_formats |= DRM_COLOR_FORMAT_YCRCB422(1<<2); | ||||
5198 | return quirks; | ||||
5199 | } | ||||
5200 | |||||
5201 | static int validate_displayid(u8 *displayid, int length, int idx) | ||||
5202 | { | ||||
5203 | int i, dispid_length; | ||||
5204 | u8 csum = 0; | ||||
5205 | struct displayid_hdr *base; | ||||
5206 | |||||
5207 | base = (struct displayid_hdr *)&displayid[idx]; | ||||
5208 | |||||
5209 | DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",__drm_dbg(DRM_UT_KMS, "base revision 0x%x, length %d, %d %d\n" , base->rev, base->bytes, base->prod_id, base->ext_count ) | ||||
5210 | base->rev, base->bytes, base->prod_id, base->ext_count)__drm_dbg(DRM_UT_KMS, "base revision 0x%x, length %d, %d %d\n" , base->rev, base->bytes, base->prod_id, base->ext_count ); | ||||
5211 | |||||
5212 | /* +1 for DispID checksum */ | ||||
5213 | dispid_length = sizeof(*base) + base->bytes + 1; | ||||
5214 | if (dispid_length > length - idx) | ||||
5215 | return -EINVAL22; | ||||
5216 | |||||
5217 | for (i = 0; i < dispid_length; i++) | ||||
5218 | csum += displayid[idx + i]; | ||||
5219 | if (csum) { | ||||
5220 | DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum)printk("\0015" "[" "drm" "] " "DisplayID checksum invalid, remainder is %d\n" , csum); | ||||
5221 | return -EINVAL22; | ||||
5222 | } | ||||
5223 | |||||
5224 | return 0; | ||||
5225 | } | ||||
5226 | |||||
5227 | static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, | ||||
5228 | struct displayid_detailed_timings_1 *timings) | ||||
5229 | { | ||||
5230 | struct drm_display_mode *mode; | ||||
5231 | unsigned pixel_clock = (timings->pixel_clock[0] | | ||||
5232 | (timings->pixel_clock[1] << 8) | | ||||
5233 | (timings->pixel_clock[2] << 16)) + 1; | ||||
5234 | unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; | ||||
5235 | unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; | ||||
5236 | unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; | ||||
5237 | unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; | ||||
5238 | unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; | ||||
5239 | unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; | ||||
5240 | unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; | ||||
5241 | unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; | ||||
5242 | bool_Bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; | ||||
5243 | bool_Bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; | ||||
5244 | |||||
5245 | mode = drm_mode_create(dev); | ||||
5246 | if (!mode) | ||||
5247 | return NULL((void *)0); | ||||
5248 | |||||
5249 | mode->clock = pixel_clock * 10; | ||||
5250 | mode->hdisplay = hactive; | ||||
5251 | mode->hsync_start = mode->hdisplay + hsync; | ||||
5252 | mode->hsync_end = mode->hsync_start + hsync_width; | ||||
5253 | mode->htotal = mode->hdisplay + hblank; | ||||
5254 | |||||
5255 | mode->vdisplay = vactive; | ||||
5256 | mode->vsync_start = mode->vdisplay + vsync; | ||||
5257 | mode->vsync_end = mode->vsync_start + vsync_width; | ||||
5258 | mode->vtotal = mode->vdisplay + vblank; | ||||
5259 | |||||
5260 | mode->flags = 0; | ||||
5261 | mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC(1<<0) : DRM_MODE_FLAG_NHSYNC(1<<1); | ||||
5262 | mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC(1<<2) : DRM_MODE_FLAG_NVSYNC(1<<3); | ||||
5263 | mode->type = DRM_MODE_TYPE_DRIVER(1<<6); | ||||
5264 | |||||
5265 | if (timings->flags & 0x80) | ||||
5266 | mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
5267 | drm_mode_set_name(mode); | ||||
5268 | |||||
5269 | return mode; | ||||
5270 | } | ||||
5271 | |||||
5272 | static int add_displayid_detailed_1_modes(struct drm_connector *connector, | ||||
5273 | struct displayid_block *block) | ||||
5274 | { | ||||
5275 | struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; | ||||
5276 | int i; | ||||
5277 | int num_timings; | ||||
5278 | struct drm_display_mode *newmode; | ||||
5279 | int num_modes = 0; | ||||
5280 | /* blocks must be multiple of 20 bytes length */ | ||||
5281 | if (block->num_bytes % 20) | ||||
5282 | return 0; | ||||
5283 | |||||
5284 | num_timings = block->num_bytes / 20; | ||||
5285 | for (i = 0; i < num_timings; i++) { | ||||
5286 | struct displayid_detailed_timings_1 *timings = &det->timings[i]; | ||||
5287 | |||||
5288 | newmode = drm_mode_displayid_detailed(connector->dev, timings); | ||||
5289 | if (!newmode) | ||||
5290 | continue; | ||||
5291 | |||||
5292 | drm_mode_probed_add(connector, newmode); | ||||
5293 | num_modes++; | ||||
5294 | } | ||||
5295 | return num_modes; | ||||
5296 | } | ||||
5297 | |||||
5298 | static int add_displayid_detailed_modes(struct drm_connector *connector, | ||||
5299 | struct edid *edid) | ||||
5300 | { | ||||
5301 | u8 *displayid; | ||||
5302 | int length, idx; | ||||
5303 | struct displayid_block *block; | ||||
5304 | int num_modes = 0; | ||||
5305 | int ext_index = 0; | ||||
5306 | |||||
5307 | for (;;) { | ||||
5308 | displayid = drm_find_displayid_extension(edid, &length, &idx, | ||||
5309 | &ext_index); | ||||
5310 | if (!displayid) | ||||
5311 | break; | ||||
5312 | |||||
5313 | idx += sizeof(struct displayid_hdr); | ||||
5314 | for_each_displayid_db(displayid, block, idx, length)for ((block) = (struct displayid_block *)&(displayid)[idx ]; (idx) + sizeof(struct displayid_block) <= (length) && (idx) + sizeof(struct displayid_block) + (block)->num_bytes <= (length) && (block)->num_bytes > 0; (idx ) += sizeof(struct displayid_block) + (block)->num_bytes, ( block) = (struct displayid_block *)&(displayid)[idx]) { | ||||
5315 | switch (block->tag) { | ||||
5316 | case DATA_BLOCK_TYPE_1_DETAILED_TIMING0x03: | ||||
5317 | num_modes += add_displayid_detailed_1_modes(connector, block); | ||||
5318 | break; | ||||
5319 | } | ||||
5320 | } | ||||
5321 | } | ||||
5322 | |||||
5323 | return num_modes; | ||||
5324 | } | ||||
5325 | |||||
5326 | /** | ||||
5327 | * drm_add_edid_modes - add modes from EDID data, if available | ||||
5328 | * @connector: connector we're probing | ||||
5329 | * @edid: EDID data | ||||
5330 | * | ||||
5331 | * Add the specified modes to the connector's mode list. Also fills out the | ||||
5332 | * &drm_display_info structure and ELD in @connector with any information which | ||||
5333 | * can be derived from the edid. | ||||
5334 | * | ||||
5335 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
5336 | */ | ||||
5337 | int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) | ||||
5338 | { | ||||
5339 | int num_modes = 0; | ||||
5340 | u32 quirks; | ||||
5341 | |||||
5342 | if (edid == NULL((void *)0)) { | ||||
5343 | clear_eld(connector); | ||||
5344 | return 0; | ||||
5345 | } | ||||
5346 | if (!drm_edid_is_valid(edid)) { | ||||
5347 | clear_eld(connector); | ||||
5348 | drm_warn(connector->dev, "%s: EDID invalid.\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "%s: EDID invalid.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , connector ->name) | ||||
5349 | connector->name)printf("drm:pid%d:%s *WARNING* " "[drm] " "%s: EDID invalid.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , connector ->name); | ||||
5350 | return 0; | ||||
5351 | } | ||||
5352 | |||||
5353 | drm_edid_to_eld(connector, edid); | ||||
5354 | |||||
5355 | /* | ||||
5356 | * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. | ||||
5357 | * To avoid multiple parsing of same block, lets parse that map | ||||
5358 | * from sink info, before parsing CEA modes. | ||||
5359 | */ | ||||
5360 | quirks = drm_add_display_info(connector, edid); | ||||
5361 | |||||
5362 | /* | ||||
5363 | * EDID spec says modes should be preferred in this order: | ||||
5364 | * - preferred detailed mode | ||||
5365 | * - other detailed modes from base block | ||||
5366 | * - detailed modes from extension blocks | ||||
5367 | * - CVT 3-byte code modes | ||||
5368 | * - standard timing codes | ||||
5369 | * - established timing codes | ||||
5370 | * - modes inferred from GTF or CVT range information | ||||
5371 | * | ||||
5372 | * We get this pretty much right. | ||||
5373 | * | ||||
5374 | * XXX order for additional mode types in extension blocks? | ||||
5375 | */ | ||||
5376 | num_modes += add_detailed_modes(connector, edid, quirks); | ||||
5377 | num_modes += add_cvt_modes(connector, edid); | ||||
5378 | num_modes += add_standard_modes(connector, edid); | ||||
5379 | num_modes += add_established_modes(connector, edid); | ||||
5380 | num_modes += add_cea_modes(connector, edid); | ||||
5381 | num_modes += add_alternate_cea_modes(connector, edid); | ||||
5382 | num_modes += add_displayid_detailed_modes(connector, edid); | ||||
5383 | if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF(1 << 0)) | ||||
5384 | num_modes += add_inferred_modes(connector, edid); | ||||
5385 | |||||
5386 | if (quirks & (EDID_QUIRK_PREFER_LARGE_60(1 << 0) | EDID_QUIRK_PREFER_LARGE_75(1 << 2))) | ||||
5387 | edid_fixup_preferred(connector, quirks); | ||||
5388 | |||||
5389 | if (quirks & EDID_QUIRK_FORCE_6BPC(1 << 10)) | ||||
5390 | connector->display_info.bpc = 6; | ||||
5391 | |||||
5392 | if (quirks & EDID_QUIRK_FORCE_8BPC(1 << 8)) | ||||
5393 | connector->display_info.bpc = 8; | ||||
5394 | |||||
5395 | if (quirks & EDID_QUIRK_FORCE_10BPC(1 << 11)) | ||||
5396 | connector->display_info.bpc = 10; | ||||
5397 | |||||
5398 | if (quirks & EDID_QUIRK_FORCE_12BPC(1 << 9)) | ||||
5399 | connector->display_info.bpc = 12; | ||||
5400 | |||||
5401 | return num_modes; | ||||
5402 | } | ||||
5403 | EXPORT_SYMBOL(drm_add_edid_modes); | ||||
5404 | |||||
5405 | /** | ||||
5406 | * drm_add_modes_noedid - add modes for the connectors without EDID | ||||
5407 | * @connector: connector we're probing | ||||
5408 | * @hdisplay: the horizontal display limit | ||||
5409 | * @vdisplay: the vertical display limit | ||||
5410 | * | ||||
5411 | * Add the specified modes to the connector's mode list. Only when the | ||||
5412 | * hdisplay/vdisplay is not beyond the given limit, it will be added. | ||||
5413 | * | ||||
5414 | * Return: The number of modes added or 0 if we couldn't find any. | ||||
5415 | */ | ||||
5416 | int drm_add_modes_noedid(struct drm_connector *connector, | ||||
5417 | int hdisplay, int vdisplay) | ||||
5418 | { | ||||
5419 | int i, count, num_modes = 0; | ||||
5420 | struct drm_display_mode *mode; | ||||
5421 | struct drm_device *dev = connector->dev; | ||||
5422 | |||||
5423 | count = ARRAY_SIZE(drm_dmt_modes)(sizeof((drm_dmt_modes)) / sizeof((drm_dmt_modes)[0])); | ||||
5424 | if (hdisplay < 0) | ||||
5425 | hdisplay = 0; | ||||
5426 | if (vdisplay < 0) | ||||
5427 | vdisplay = 0; | ||||
5428 | |||||
5429 | for (i = 0; i < count; i++) { | ||||
5430 | const struct drm_display_mode *ptr = &drm_dmt_modes[i]; | ||||
5431 | |||||
5432 | if (hdisplay && vdisplay) { | ||||
5433 | /* | ||||
5434 | * Only when two are valid, they will be used to check | ||||
5435 | * whether the mode should be added to the mode list of | ||||
5436 | * the connector. | ||||
5437 | */ | ||||
5438 | if (ptr->hdisplay > hdisplay || | ||||
5439 | ptr->vdisplay > vdisplay) | ||||
5440 | continue; | ||||
5441 | } | ||||
5442 | if (drm_mode_vrefresh(ptr) > 61) | ||||
5443 | continue; | ||||
5444 | mode = drm_mode_duplicate(dev, ptr); | ||||
5445 | if (mode) { | ||||
5446 | drm_mode_probed_add(connector, mode); | ||||
5447 | num_modes++; | ||||
5448 | } | ||||
5449 | } | ||||
5450 | return num_modes; | ||||
5451 | } | ||||
5452 | EXPORT_SYMBOL(drm_add_modes_noedid); | ||||
5453 | |||||
5454 | /** | ||||
5455 | * drm_set_preferred_mode - Sets the preferred mode of a connector | ||||
5456 | * @connector: connector whose mode list should be processed | ||||
5457 | * @hpref: horizontal resolution of preferred mode | ||||
5458 | * @vpref: vertical resolution of preferred mode | ||||
5459 | * | ||||
5460 | * Marks a mode as preferred if it matches the resolution specified by @hpref | ||||
5461 | * and @vpref. | ||||
5462 | */ | ||||
5463 | void drm_set_preferred_mode(struct drm_connector *connector, | ||||
5464 | int hpref, int vpref) | ||||
5465 | { | ||||
5466 | struct drm_display_mode *mode; | ||||
5467 | |||||
5468 | list_for_each_entry(mode, &connector->probed_modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = ((&connector->probed_modes)->next); (__typeof (*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode ), head) );}); &mode->head != (&connector->probed_modes ); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head ) *__mptr = (mode->head.next); (__typeof(*mode) *)( (char * )__mptr - __builtin_offsetof(__typeof(*mode), head) );})) { | ||||
5469 | if (mode->hdisplay == hpref && | ||||
5470 | mode->vdisplay == vpref) | ||||
5471 | mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); | ||||
5472 | } | ||||
5473 | } | ||||
5474 | EXPORT_SYMBOL(drm_set_preferred_mode); | ||||
5475 | |||||
5476 | static bool_Bool is_hdmi2_sink(const struct drm_connector *connector) | ||||
5477 | { | ||||
5478 | /* | ||||
5479 | * FIXME: sil-sii8620 doesn't have a connector around when | ||||
5480 | * we need one, so we have to be prepared for a NULL connector. | ||||
5481 | */ | ||||
5482 | if (!connector) | ||||
5483 | return true1; | ||||
5484 | |||||
5485 | return connector->display_info.hdmi.scdc.supported || | ||||
5486 | connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420(1<<3); | ||||
5487 | } | ||||
5488 | |||||
5489 | static inline bool_Bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) | ||||
5490 | { | ||||
5491 | return sink_eotf & BIT(output_eotf)(1UL << (output_eotf)); | ||||
5492 | } | ||||
5493 | |||||
5494 | /** | ||||
5495 | * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with | ||||
5496 | * HDR metadata from userspace | ||||
5497 | * @frame: HDMI DRM infoframe | ||||
5498 | * @conn_state: Connector state containing HDR metadata | ||||
5499 | * | ||||
5500 | * Return: 0 on success or a negative error code on failure. | ||||
5501 | */ | ||||
5502 | int | ||||
5503 | drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, | ||||
5504 | const struct drm_connector_state *conn_state) | ||||
5505 | { | ||||
5506 | struct drm_connector *connector; | ||||
5507 | struct hdr_output_metadata *hdr_metadata; | ||||
5508 | int err; | ||||
5509 | |||||
5510 | if (!frame || !conn_state) | ||||
5511 | return -EINVAL22; | ||||
5512 | |||||
5513 | connector = conn_state->connector; | ||||
5514 | |||||
5515 | if (!conn_state->hdr_output_metadata) | ||||
5516 | return -EINVAL22; | ||||
5517 | |||||
5518 | hdr_metadata = conn_state->hdr_output_metadata->data; | ||||
5519 | |||||
5520 | if (!hdr_metadata || !connector) | ||||
5521 | return -EINVAL22; | ||||
5522 | |||||
5523 | /* Sink EOTF is Bit map while infoframe is absolute values */ | ||||
5524 | if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, | ||||
5525 | connector->hdr_sink_metadata.hdmi_type1.eotf)) { | ||||
5526 | DRM_DEBUG_KMS("EOTF Not Supported\n")__drm_dbg(DRM_UT_KMS, "EOTF Not Supported\n"); | ||||
5527 | return -EINVAL22; | ||||
5528 | } | ||||
5529 | |||||
5530 | err = hdmi_drm_infoframe_init(frame); | ||||
5531 | if (err < 0) | ||||
5532 | return err; | ||||
5533 | |||||
5534 | frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; | ||||
5535 | frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; | ||||
5536 | |||||
5537 | BUILD_BUG_ON(sizeof(frame->display_primaries) !=extern char _ctassert[(!(sizeof(frame->display_primaries) != sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries ))) ? 1 : -1 ] __attribute__((__unused__)) | ||||
5538 | sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries))extern char _ctassert[(!(sizeof(frame->display_primaries) != sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries ))) ? 1 : -1 ] __attribute__((__unused__)); | ||||
5539 | BUILD_BUG_ON(sizeof(frame->white_point) !=extern char _ctassert[(!(sizeof(frame->white_point) != sizeof (hdr_metadata->hdmi_metadata_type1.white_point))) ? 1 : -1 ] __attribute__((__unused__)) | ||||
5540 | sizeof(hdr_metadata->hdmi_metadata_type1.white_point))extern char _ctassert[(!(sizeof(frame->white_point) != sizeof (hdr_metadata->hdmi_metadata_type1.white_point))) ? 1 : -1 ] __attribute__((__unused__)); | ||||
5541 | |||||
5542 | memcpy(&frame->display_primaries,__builtin_memcpy((&frame->display_primaries), (&hdr_metadata ->hdmi_metadata_type1.display_primaries), (sizeof(frame-> display_primaries))) | ||||
5543 | &hdr_metadata->hdmi_metadata_type1.display_primaries,__builtin_memcpy((&frame->display_primaries), (&hdr_metadata ->hdmi_metadata_type1.display_primaries), (sizeof(frame-> display_primaries))) | ||||
5544 | sizeof(frame->display_primaries))__builtin_memcpy((&frame->display_primaries), (&hdr_metadata ->hdmi_metadata_type1.display_primaries), (sizeof(frame-> display_primaries))); | ||||
5545 | |||||
5546 | memcpy(&frame->white_point,__builtin_memcpy((&frame->white_point), (&hdr_metadata ->hdmi_metadata_type1.white_point), (sizeof(frame->white_point ))) | ||||
5547 | &hdr_metadata->hdmi_metadata_type1.white_point,__builtin_memcpy((&frame->white_point), (&hdr_metadata ->hdmi_metadata_type1.white_point), (sizeof(frame->white_point ))) | ||||
5548 | sizeof(frame->white_point))__builtin_memcpy((&frame->white_point), (&hdr_metadata ->hdmi_metadata_type1.white_point), (sizeof(frame->white_point ))); | ||||
5549 | |||||
5550 | frame->max_display_mastering_luminance = | ||||
5551 | hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; | ||||
5552 | frame->min_display_mastering_luminance = | ||||
5553 | hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; | ||||
5554 | frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; | ||||
5555 | frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; | ||||
5556 | |||||
5557 | return 0; | ||||
5558 | } | ||||
5559 | EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); | ||||
5560 | |||||
5561 | static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, | ||||
5562 | const struct drm_display_mode *mode) | ||||
5563 | { | ||||
5564 | bool_Bool has_hdmi_infoframe = connector ? | ||||
5565 | connector->display_info.has_hdmi_infoframe : false0; | ||||
5566 | |||||
5567 | if (!has_hdmi_infoframe) | ||||
5568 | return 0; | ||||
5569 | |||||
5570 | /* No HDMI VIC when signalling 3D video format */ | ||||
5571 | if (mode->flags & DRM_MODE_FLAG_3D_MASK(0x1f<<14)) | ||||
5572 | return 0; | ||||
5573 | |||||
5574 | return drm_match_hdmi_mode(mode); | ||||
5575 | } | ||||
5576 | |||||
5577 | static u8 drm_mode_cea_vic(const struct drm_connector *connector, | ||||
5578 | const struct drm_display_mode *mode) | ||||
5579 | { | ||||
5580 | u8 vic; | ||||
5581 | |||||
5582 | /* | ||||
5583 | * HDMI spec says if a mode is found in HDMI 1.4b 4K modes | ||||
5584 | * we should send its VIC in vendor infoframes, else send the | ||||
5585 | * VIC in AVI infoframes. Lets check if this mode is present in | ||||
5586 | * HDMI 1.4b 4K modes | ||||
5587 | */ | ||||
5588 | if (drm_mode_hdmi_vic(connector, mode)) | ||||
5589 | return 0; | ||||
5590 | |||||
5591 | vic = drm_match_cea_mode(mode); | ||||
5592 | |||||
5593 | /* | ||||
5594 | * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but | ||||
5595 | * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we | ||||
5596 | * have to make sure we dont break HDMI 1.4 sinks. | ||||
5597 | */ | ||||
5598 | if (!is_hdmi2_sink(connector) && vic > 64) | ||||
5599 | return 0; | ||||
5600 | |||||
5601 | return vic; | ||||
5602 | } | ||||
5603 | |||||
5604 | /** | ||||
5605 | * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with | ||||
5606 | * data from a DRM display mode | ||||
5607 | * @frame: HDMI AVI infoframe | ||||
5608 | * @connector: the connector | ||||
5609 | * @mode: DRM display mode | ||||
5610 | * | ||||
5611 | * Return: 0 on success or a negative error code on failure. | ||||
5612 | */ | ||||
5613 | int | ||||
5614 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, | ||||
5615 | const struct drm_connector *connector, | ||||
5616 | const struct drm_display_mode *mode) | ||||
5617 | { | ||||
5618 | enum hdmi_picture_aspect picture_aspect; | ||||
5619 | u8 vic, hdmi_vic; | ||||
5620 | |||||
5621 | if (!frame || !mode) | ||||
5622 | return -EINVAL22; | ||||
5623 | |||||
5624 | hdmi_avi_infoframe_init(frame); | ||||
5625 | |||||
5626 | if (mode->flags & DRM_MODE_FLAG_DBLCLK(1<<12)) | ||||
5627 | frame->pixel_repeat = 1; | ||||
5628 | |||||
5629 | vic = drm_mode_cea_vic(connector, mode); | ||||
5630 | hdmi_vic = drm_mode_hdmi_vic(connector, mode); | ||||
5631 | |||||
5632 | frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; | ||||
5633 | |||||
5634 | /* | ||||
5635 | * As some drivers don't support atomic, we can't use connector state. | ||||
5636 | * So just initialize the frame with default values, just the same way | ||||
5637 | * as it's done with other properties here. | ||||
5638 | */ | ||||
5639 | frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; | ||||
5640 | frame->itc = 0; | ||||
5641 | |||||
5642 | /* | ||||
5643 | * Populate picture aspect ratio from either | ||||
5644 | * user input (if specified) or from the CEA/HDMI mode lists. | ||||
5645 | */ | ||||
5646 | picture_aspect = mode->picture_aspect_ratio; | ||||
5647 | if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { | ||||
5648 | if (vic) | ||||
5649 | picture_aspect = drm_get_cea_aspect_ratio(vic); | ||||
5650 | else if (hdmi_vic) | ||||
5651 | picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); | ||||
5652 | } | ||||
5653 | |||||
5654 | /* | ||||
5655 | * The infoframe can't convey anything but none, 4:3 | ||||
5656 | * and 16:9, so if the user has asked for anything else | ||||
5657 | * we can only satisfy it by specifying the right VIC. | ||||
5658 | */ | ||||
5659 | if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { | ||||
5660 | if (vic) { | ||||
5661 | if (picture_aspect != drm_get_cea_aspect_ratio(vic)) | ||||
5662 | return -EINVAL22; | ||||
5663 | } else if (hdmi_vic) { | ||||
5664 | if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) | ||||
5665 | return -EINVAL22; | ||||
5666 | } else { | ||||
5667 | return -EINVAL22; | ||||
5668 | } | ||||
5669 | |||||
5670 | picture_aspect = HDMI_PICTURE_ASPECT_NONE; | ||||
5671 | } | ||||
5672 | |||||
5673 | frame->video_code = vic; | ||||
5674 | frame->picture_aspect = picture_aspect; | ||||
5675 | frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; | ||||
5676 | frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; | ||||
5677 | |||||
5678 | return 0; | ||||
5679 | } | ||||
5680 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); | ||||
5681 | |||||
5682 | /* HDMI Colorspace Spec Definitions */ | ||||
5683 | #define FULL_COLORIMETRY_MASK0x1FF 0x1FF | ||||
5684 | #define NORMAL_COLORIMETRY_MASK0x3 0x3 | ||||
5685 | #define EXTENDED_COLORIMETRY_MASK0x7 0x7 | ||||
5686 | #define EXTENDED_ACE_COLORIMETRY_MASK0xF 0xF | ||||
5687 | |||||
5688 | #define C(x) ((x) << 0) | ||||
5689 | #define EC(x) ((x) << 2) | ||||
5690 | #define ACE(x) ((x) << 5) | ||||
5691 | |||||
5692 | #define HDMI_COLORIMETRY_NO_DATA0x0 0x0 | ||||
5693 | #define HDMI_COLORIMETRY_SMPTE_170M_YCC(C(1) | EC(0) | ACE(0)) (C(1) | EC(0) | ACE(0)) | ||||
5694 | #define HDMI_COLORIMETRY_BT709_YCC(C(2) | EC(0) | ACE(0)) (C(2) | EC(0) | ACE(0)) | ||||
5695 | #define HDMI_COLORIMETRY_XVYCC_601(C(3) | EC(0) | ACE(0)) (C(3) | EC(0) | ACE(0)) | ||||
5696 | #define HDMI_COLORIMETRY_XVYCC_709(C(3) | EC(1) | ACE(0)) (C(3) | EC(1) | ACE(0)) | ||||
5697 | #define HDMI_COLORIMETRY_SYCC_601(C(3) | EC(2) | ACE(0)) (C(3) | EC(2) | ACE(0)) | ||||
5698 | #define HDMI_COLORIMETRY_OPYCC_601(C(3) | EC(3) | ACE(0)) (C(3) | EC(3) | ACE(0)) | ||||
5699 | #define HDMI_COLORIMETRY_OPRGB(C(3) | EC(4) | ACE(0)) (C(3) | EC(4) | ACE(0)) | ||||
5700 | #define HDMI_COLORIMETRY_BT2020_CYCC(C(3) | EC(5) | ACE(0)) (C(3) | EC(5) | ACE(0)) | ||||
5701 | #define HDMI_COLORIMETRY_BT2020_RGB(C(3) | EC(6) | ACE(0)) (C(3) | EC(6) | ACE(0)) | ||||
5702 | #define HDMI_COLORIMETRY_BT2020_YCC(C(3) | EC(6) | ACE(0)) (C(3) | EC(6) | ACE(0)) | ||||
5703 | #define HDMI_COLORIMETRY_DCI_P3_RGB_D65(C(3) | EC(7) | ACE(0)) (C(3) | EC(7) | ACE(0)) | ||||
5704 | #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER(C(3) | EC(7) | ACE(1)) (C(3) | EC(7) | ACE(1)) | ||||
5705 | |||||
5706 | static const u32 hdmi_colorimetry_val[] = { | ||||
5707 | [DRM_MODE_COLORIMETRY_NO_DATA0] = HDMI_COLORIMETRY_NO_DATA0x0, | ||||
5708 | [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC1] = HDMI_COLORIMETRY_SMPTE_170M_YCC(C(1) | EC(0) | ACE(0)), | ||||
5709 | [DRM_MODE_COLORIMETRY_BT709_YCC2] = HDMI_COLORIMETRY_BT709_YCC(C(2) | EC(0) | ACE(0)), | ||||
5710 | [DRM_MODE_COLORIMETRY_XVYCC_6013] = HDMI_COLORIMETRY_XVYCC_601(C(3) | EC(0) | ACE(0)), | ||||
5711 | [DRM_MODE_COLORIMETRY_XVYCC_7094] = HDMI_COLORIMETRY_XVYCC_709(C(3) | EC(1) | ACE(0)), | ||||
5712 | [DRM_MODE_COLORIMETRY_SYCC_6015] = HDMI_COLORIMETRY_SYCC_601(C(3) | EC(2) | ACE(0)), | ||||
5713 | [DRM_MODE_COLORIMETRY_OPYCC_6016] = HDMI_COLORIMETRY_OPYCC_601(C(3) | EC(3) | ACE(0)), | ||||
5714 | [DRM_MODE_COLORIMETRY_OPRGB7] = HDMI_COLORIMETRY_OPRGB(C(3) | EC(4) | ACE(0)), | ||||
5715 | [DRM_MODE_COLORIMETRY_BT2020_CYCC8] = HDMI_COLORIMETRY_BT2020_CYCC(C(3) | EC(5) | ACE(0)), | ||||
5716 | [DRM_MODE_COLORIMETRY_BT2020_RGB9] = HDMI_COLORIMETRY_BT2020_RGB(C(3) | EC(6) | ACE(0)), | ||||
5717 | [DRM_MODE_COLORIMETRY_BT2020_YCC10] = HDMI_COLORIMETRY_BT2020_YCC(C(3) | EC(6) | ACE(0)), | ||||
5718 | }; | ||||
5719 | |||||
5720 | #undef C | ||||
5721 | #undef EC | ||||
5722 | #undef ACE | ||||
5723 | |||||
5724 | /** | ||||
5725 | * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe | ||||
5726 | * colorspace information | ||||
5727 | * @frame: HDMI AVI infoframe | ||||
5728 | * @conn_state: connector state | ||||
5729 | */ | ||||
5730 | void | ||||
5731 | drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, | ||||
5732 | const struct drm_connector_state *conn_state) | ||||
5733 | { | ||||
5734 | u32 colorimetry_val; | ||||
5735 | u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK0x1FF; | ||||
5736 | |||||
5737 | if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)(sizeof((hdmi_colorimetry_val)) / sizeof((hdmi_colorimetry_val )[0]))) | ||||
5738 | colorimetry_val = HDMI_COLORIMETRY_NO_DATA0x0; | ||||
5739 | else | ||||
5740 | colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; | ||||
5741 | |||||
5742 | frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK0x3; | ||||
5743 | /* | ||||
5744 | * ToDo: Extend it for ACE formats as well. Modify the infoframe | ||||
5745 | * structure and extend it in drivers/video/hdmi | ||||
5746 | */ | ||||
5747 | frame->extended_colorimetry = (colorimetry_val >> 2) & | ||||
5748 | EXTENDED_COLORIMETRY_MASK0x7; | ||||
5749 | } | ||||
5750 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); | ||||
5751 | |||||
5752 | /** | ||||
5753 | * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe | ||||
5754 | * quantization range information | ||||
5755 | * @frame: HDMI AVI infoframe | ||||
5756 | * @connector: the connector | ||||
5757 | * @mode: DRM display mode | ||||
5758 | * @rgb_quant_range: RGB quantization range (Q) | ||||
5759 | */ | ||||
5760 | void | ||||
5761 | drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, | ||||
5762 | const struct drm_connector *connector, | ||||
5763 | const struct drm_display_mode *mode, | ||||
5764 | enum hdmi_quantization_range rgb_quant_range) | ||||
5765 | { | ||||
5766 | const struct drm_display_info *info = &connector->display_info; | ||||
5767 | |||||
5768 | /* | ||||
5769 | * CEA-861: | ||||
5770 | * "A Source shall not send a non-zero Q value that does not correspond | ||||
5771 | * to the default RGB Quantization Range for the transmitted Picture | ||||
5772 | * unless the Sink indicates support for the Q bit in a Video | ||||
5773 | * Capabilities Data Block." | ||||
5774 | * | ||||
5775 | * HDMI 2.0 recommends sending non-zero Q when it does match the | ||||
5776 | * default RGB quantization range for the mode, even when QS=0. | ||||
5777 | */ | ||||
5778 | if (info->rgb_quant_range_selectable || | ||||
5779 | rgb_quant_range == drm_default_rgb_quant_range(mode)) | ||||
5780 | frame->quantization_range = rgb_quant_range; | ||||
5781 | else | ||||
5782 | frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | ||||
5783 | |||||
5784 | /* | ||||
5785 | * CEA-861-F: | ||||
5786 | * "When transmitting any RGB colorimetry, the Source should set the | ||||
5787 | * YQ-field to match the RGB Quantization Range being transmitted | ||||
5788 | * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, | ||||
5789 | * set YQ=1) and the Sink shall ignore the YQ-field." | ||||
5790 | * | ||||
5791 | * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused | ||||
5792 | * by non-zero YQ when receiving RGB. There doesn't seem to be any | ||||
5793 | * good way to tell which version of CEA-861 the sink supports, so | ||||
5794 | * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based | ||||
5795 | * on on CEA-861-F. | ||||
5796 | */ | ||||
5797 | if (!is_hdmi2_sink(connector) || | ||||
5798 | rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) | ||||
5799 | frame->ycc_quantization_range = | ||||
5800 | HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | ||||
5801 | else | ||||
5802 | frame->ycc_quantization_range = | ||||
5803 | HDMI_YCC_QUANTIZATION_RANGE_FULL; | ||||
5804 | } | ||||
5805 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); | ||||
5806 | |||||
5807 | /** | ||||
5808 | * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe | ||||
5809 | * bar information | ||||
5810 | * @frame: HDMI AVI infoframe | ||||
5811 | * @conn_state: connector state | ||||
5812 | */ | ||||
5813 | void | ||||
5814 | drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, | ||||
5815 | const struct drm_connector_state *conn_state) | ||||
5816 | { | ||||
5817 | frame->right_bar = conn_state->tv.margins.right; | ||||
5818 | frame->left_bar = conn_state->tv.margins.left; | ||||
5819 | frame->top_bar = conn_state->tv.margins.top; | ||||
5820 | frame->bottom_bar = conn_state->tv.margins.bottom; | ||||
5821 | } | ||||
5822 | EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); | ||||
5823 | |||||
5824 | static enum hdmi_3d_structure | ||||
5825 | s3d_structure_from_display_mode(const struct drm_display_mode *mode) | ||||
5826 | { | ||||
5827 | u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK(0x1f<<14); | ||||
5828 | |||||
5829 | switch (layout) { | ||||
5830 | case DRM_MODE_FLAG_3D_FRAME_PACKING(1<<14): | ||||
5831 | return HDMI_3D_STRUCTURE_FRAME_PACKING; | ||||
5832 | case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE(2<<14): | ||||
5833 | return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; | ||||
5834 | case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE(3<<14): | ||||
5835 | return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; | ||||
5836 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL(4<<14): | ||||
5837 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; | ||||
5838 | case DRM_MODE_FLAG_3D_L_DEPTH(5<<14): | ||||
5839 | return HDMI_3D_STRUCTURE_L_DEPTH; | ||||
5840 | case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH(6<<14): | ||||
5841 | return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; | ||||
5842 | case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM(7<<14): | ||||
5843 | return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; | ||||
5844 | case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF(8<<14): | ||||
5845 | return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; | ||||
5846 | default: | ||||
5847 | return HDMI_3D_STRUCTURE_INVALID; | ||||
5848 | } | ||||
5849 | } | ||||
5850 | |||||
5851 | /** | ||||
5852 | * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with | ||||
5853 | * data from a DRM display mode | ||||
5854 | * @frame: HDMI vendor infoframe | ||||
5855 | * @connector: the connector | ||||
5856 | * @mode: DRM display mode | ||||
5857 | * | ||||
5858 | * Note that there's is a need to send HDMI vendor infoframes only when using a | ||||
5859 | * 4k or stereoscopic 3D mode. So when giving any other mode as input this | ||||
5860 | * function will return -EINVAL, error that can be safely ignored. | ||||
5861 | * | ||||
5862 | * Return: 0 on success or a negative error code on failure. | ||||
5863 | */ | ||||
5864 | int | ||||
5865 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, | ||||
5866 | const struct drm_connector *connector, | ||||
5867 | const struct drm_display_mode *mode) | ||||
5868 | { | ||||
5869 | /* | ||||
5870 | * FIXME: sil-sii8620 doesn't have a connector around when | ||||
5871 | * we need one, so we have to be prepared for a NULL connector. | ||||
5872 | */ | ||||
5873 | bool_Bool has_hdmi_infoframe = connector ? | ||||
5874 | connector->display_info.has_hdmi_infoframe : false0; | ||||
5875 | int err; | ||||
5876 | |||||
5877 | if (!frame || !mode) | ||||
5878 | return -EINVAL22; | ||||
5879 | |||||
5880 | if (!has_hdmi_infoframe) | ||||
5881 | return -EINVAL22; | ||||
5882 | |||||
5883 | err = hdmi_vendor_infoframe_init(frame); | ||||
5884 | if (err < 0) | ||||
5885 | return err; | ||||
5886 | |||||
5887 | /* | ||||
5888 | * Even if it's not absolutely necessary to send the infoframe | ||||
5889 | * (ie.vic==0 and s3d_struct==0) we will still send it if we | ||||
5890 | * know that the sink can handle it. This is based on a | ||||
5891 | * suggestion in HDMI 2.0 Appendix F. Apparently some sinks | ||||
5892 | * have trouble realizing that they shuld switch from 3D to 2D | ||||
5893 | * mode if the source simply stops sending the infoframe when | ||||
5894 | * it wants to switch from 3D to 2D. | ||||
5895 | */ | ||||
5896 | frame->vic = drm_mode_hdmi_vic(connector, mode); | ||||
5897 | frame->s3d_struct = s3d_structure_from_display_mode(mode); | ||||
5898 | |||||
5899 | return 0; | ||||
5900 | } | ||||
5901 | EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); | ||||
5902 | |||||
5903 | static void drm_parse_tiled_block(struct drm_connector *connector, | ||||
5904 | const struct displayid_block *block) | ||||
5905 | { | ||||
5906 | const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; | ||||
5907 | u16 w, h; | ||||
5908 | u8 tile_v_loc, tile_h_loc; | ||||
5909 | u8 num_v_tile, num_h_tile; | ||||
5910 | struct drm_tile_group *tg; | ||||
5911 | |||||
5912 | w = tile->tile_size[0] | tile->tile_size[1] << 8; | ||||
5913 | h = tile->tile_size[2] | tile->tile_size[3] << 8; | ||||
5914 | |||||
5915 | num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); | ||||
5916 | num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); | ||||
5917 | tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); | ||||
5918 | tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); | ||||
5919 | |||||
5920 | connector->has_tile = true1; | ||||
5921 | if (tile->tile_cap & 0x80) | ||||
5922 | connector->tile_is_single_monitor = true1; | ||||
5923 | |||||
5924 | connector->num_h_tile = num_h_tile + 1; | ||||
5925 | connector->num_v_tile = num_v_tile + 1; | ||||
5926 | connector->tile_h_loc = tile_h_loc; | ||||
5927 | connector->tile_v_loc = tile_v_loc; | ||||
5928 | connector->tile_h_size = w + 1; | ||||
5929 | connector->tile_v_size = h + 1; | ||||
5930 | |||||
5931 | DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap)__drm_dbg(DRM_UT_KMS, "tile cap 0x%x\n", tile->tile_cap); | ||||
5932 | DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1)__drm_dbg(DRM_UT_KMS, "tile_size %d x %d\n", w + 1, h + 1); | ||||
5933 | DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",__drm_dbg(DRM_UT_KMS, "topo num tiles %dx%d, location %dx%d\n" , num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc) | ||||
5934 | num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc)__drm_dbg(DRM_UT_KMS, "topo num tiles %dx%d, location %dx%d\n" , num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); | ||||
5935 | DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2])__drm_dbg(DRM_UT_KMS, "vend %c%c%c\n", tile->topology_id[0 ], tile->topology_id[1], tile->topology_id[2]); | ||||
5936 | |||||
5937 | tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); | ||||
5938 | if (!tg) | ||||
5939 | tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); | ||||
5940 | if (!tg) | ||||
5941 | return; | ||||
5942 | |||||
5943 | if (connector->tile_group != tg) { | ||||
5944 | /* if we haven't got a pointer, | ||||
5945 | take the reference, drop ref to old tile group */ | ||||
5946 | if (connector->tile_group) | ||||
5947 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | ||||
5948 | connector->tile_group = tg; | ||||
5949 | } else { | ||||
5950 | /* if same tile group, then release the ref we just took. */ | ||||
5951 | drm_mode_put_tile_group(connector->dev, tg); | ||||
5952 | } | ||||
5953 | } | ||||
5954 | |||||
5955 | static void drm_displayid_parse_tiled(struct drm_connector *connector, | ||||
5956 | const u8 *displayid, int length, int idx) | ||||
5957 | { | ||||
5958 | const struct displayid_block *block; | ||||
5959 | |||||
5960 | idx += sizeof(struct displayid_hdr); | ||||
5961 | for_each_displayid_db(displayid, block, idx, length)for ((block) = (struct displayid_block *)&(displayid)[idx ]; (idx) + sizeof(struct displayid_block) <= (length) && (idx) + sizeof(struct displayid_block) + (block)->num_bytes <= (length) && (block)->num_bytes > 0; (idx ) += sizeof(struct displayid_block) + (block)->num_bytes, ( block) = (struct displayid_block *)&(displayid)[idx]) { | ||||
5962 | DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",__drm_dbg(DRM_UT_KMS, "block id 0x%x, rev %d, len %d\n", block ->tag, block->rev, block->num_bytes) | ||||
5963 | block->tag, block->rev, block->num_bytes)__drm_dbg(DRM_UT_KMS, "block id 0x%x, rev %d, len %d\n", block ->tag, block->rev, block->num_bytes); | ||||
5964 | |||||
5965 | switch (block->tag) { | ||||
5966 | case DATA_BLOCK_TILED_DISPLAY0x12: | ||||
5967 | drm_parse_tiled_block(connector, block); | ||||
5968 | break; | ||||
5969 | default: | ||||
5970 | DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag)__drm_dbg(DRM_UT_KMS, "found DisplayID tag 0x%x, unhandled\n" , block->tag); | ||||
5971 | break; | ||||
5972 | } | ||||
5973 | } | ||||
5974 | } | ||||
5975 | |||||
5976 | void drm_update_tile_info(struct drm_connector *connector, | ||||
5977 | const struct edid *edid) | ||||
5978 | { | ||||
5979 | const void *displayid = NULL((void *)0); | ||||
5980 | int ext_index = 0; | ||||
5981 | int length, idx; | ||||
5982 | |||||
5983 | connector->has_tile = false0; | ||||
5984 | for (;;) { | ||||
5985 | displayid = drm_find_displayid_extension(edid, &length, &idx, | ||||
5986 | &ext_index); | ||||
5987 | if (!displayid) | ||||
5988 | break; | ||||
5989 | |||||
5990 | drm_displayid_parse_tiled(connector, displayid, length, idx); | ||||
5991 | } | ||||
5992 | |||||
5993 | if (!connector->has_tile && connector->tile_group) { | ||||
5994 | drm_mode_put_tile_group(connector->dev, connector->tile_group); | ||||
5995 | connector->tile_group = NULL((void *)0); | ||||
5996 | } | ||||
5997 | } |
1 | /* Public domain. */ |
2 | |
3 | #ifndef _LINUX_STRING_H |
4 | #define _LINUX_STRING_H |
5 | |
6 | #include <sys/types.h> |
7 | #include <sys/systm.h> |
8 | #include <sys/malloc.h> |
9 | #include <sys/stdint.h> |
10 | #include <sys/errno.h> |
11 | |
12 | void *memchr_inv(const void *, int, size_t); |
13 | |
14 | static inline void * |
15 | memset32(uint32_t *b, uint32_t c, size_t len) |
16 | { |
17 | uint32_t *dst = b; |
18 | while (len--) |
19 | *dst++ = c; |
20 | return b; |
21 | } |
22 | |
23 | static inline void * |
24 | memset64(uint64_t *b, uint64_t c, size_t len) |
25 | { |
26 | uint64_t *dst = b; |
27 | while (len--) |
28 | *dst++ = c; |
29 | return b; |
30 | } |
31 | |
32 | static inline void * |
33 | memset_p(void **p, void *v, size_t n) |
34 | { |
35 | #ifdef __LP64__1 |
36 | return memset64((uint64_t *)p, (uintptr_t)v, n); |
37 | #else |
38 | return memset32((uint32_t *)p, (uintptr_t)v, n); |
39 | #endif |
40 | } |
41 | |
42 | static inline void * |
43 | kmemdup(const void *src, size_t len, int flags) |
44 | { |
45 | void *p = malloc(len, M_DRM145, flags); |
46 | if (p) |
47 | memcpy(p, src, len)__builtin_memcpy((p), (src), (len)); |
48 | return (p); |
49 | } |
50 | |
51 | static inline void * |
52 | kstrdup(const char *str, int flags) |
53 | { |
54 | size_t len; |
55 | char *p; |
56 | |
57 | if (str == NULL((void *)0)) |
58 | return NULL((void *)0); |
59 | |
60 | len = strlen(str) + 1; |
61 | p = malloc(len, M_DRM145, flags); |
62 | if (p) |
63 | memcpy(p, str, len)__builtin_memcpy((p), (str), (len)); |
64 | return (p); |
65 | } |
66 | |
67 | static inline int |
68 | match_string(const char * const *array, size_t n, const char *str) |
69 | { |
70 | int i; |
71 | |
72 | for (i = 0; i < n; i++) { |
73 | if (array[i] == NULL((void *)0)) |
74 | break; |
75 | if (!strcmp(array[i], str)) |
76 | return i; |
77 | } |
78 | |
79 | return -EINVAL22; |
80 | } |
81 | |
82 | #endif |