| File: | dev/pci/drm/i915/display/intel_dp.c |
| Warning: | line 6507, column 27 Value stored to 'i915' during its initialization is never read |
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| 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/export.h> |
| 29 | #include <linux/i2c.h> |
| 30 | #include <linux/notifier.h> |
| 31 | #include <linux/reboot.h> |
| 32 | #include <linux/slab.h> |
| 33 | #include <linux/types.h> |
| 34 | |
| 35 | #include <asm/byteorder.h> |
| 36 | |
| 37 | #include <drm/drm_atomic_helper.h> |
| 38 | #include <drm/drm_crtc.h> |
| 39 | #include <drm/drm_dp_helper.h> |
| 40 | #include <drm/drm_edid.h> |
| 41 | #include <drm/drm_probe_helper.h> |
| 42 | |
| 43 | #include "i915_debugfs.h" |
| 44 | #include "i915_drv.h" |
| 45 | #include "i915_trace.h" |
| 46 | #include "intel_atomic.h" |
| 47 | #include "intel_audio.h" |
| 48 | #include "intel_connector.h" |
| 49 | #include "intel_ddi.h" |
| 50 | #include "intel_display_types.h" |
| 51 | #include "intel_dp.h" |
| 52 | #include "intel_dp_link_training.h" |
| 53 | #include "intel_dp_mst.h" |
| 54 | #include "intel_dpio_phy.h" |
| 55 | #include "intel_fifo_underrun.h" |
| 56 | #include "intel_hdcp.h" |
| 57 | #include "intel_hdmi.h" |
| 58 | #include "intel_hotplug.h" |
| 59 | #include "intel_lspcon.h" |
| 60 | #include "intel_lvds.h" |
| 61 | #include "intel_panel.h" |
| 62 | #include "intel_psr.h" |
| 63 | #include "intel_sideband.h" |
| 64 | #include "intel_tc.h" |
| 65 | #include "intel_vdsc.h" |
| 66 | |
| 67 | #define DP_DPRX_ESI_LEN14 14 |
| 68 | |
| 69 | /* DP DSC throughput values used for slice count calculations KPixels/s */ |
| 70 | #define DP_DSC_PEAK_PIXEL_RATE2720000 2720000 |
| 71 | #define DP_DSC_MAX_ENC_THROUGHPUT_0340000 340000 |
| 72 | #define DP_DSC_MAX_ENC_THROUGHPUT_1400000 400000 |
| 73 | |
| 74 | /* DP DSC FEC Overhead factor = 1/(0.972261) */ |
| 75 | #define DP_DSC_FEC_OVERHEAD_FACTOR972261 972261 |
| 76 | |
| 77 | /* Compliance test status bits */ |
| 78 | #define INTEL_DP_RESOLUTION_SHIFT_MASK0 0 |
| 79 | #define INTEL_DP_RESOLUTION_PREFERRED(1 << 0) (1 << INTEL_DP_RESOLUTION_SHIFT_MASK0) |
| 80 | #define INTEL_DP_RESOLUTION_STANDARD(2 << 0) (2 << INTEL_DP_RESOLUTION_SHIFT_MASK0) |
| 81 | #define INTEL_DP_RESOLUTION_FAILSAFE(3 << 0) (3 << INTEL_DP_RESOLUTION_SHIFT_MASK0) |
| 82 | |
| 83 | struct dp_link_dpll { |
| 84 | int clock; |
| 85 | struct dpll dpll; |
| 86 | }; |
| 87 | |
| 88 | static const struct dp_link_dpll g4x_dpll[] = { |
| 89 | { 162000, |
| 90 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
| 91 | { 270000, |
| 92 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 93 | }; |
| 94 | |
| 95 | static const struct dp_link_dpll pch_dpll[] = { |
| 96 | { 162000, |
| 97 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
| 98 | { 270000, |
| 99 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 100 | }; |
| 101 | |
| 102 | static const struct dp_link_dpll vlv_dpll[] = { |
| 103 | { 162000, |
| 104 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
| 105 | { 270000, |
| 106 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 107 | }; |
| 108 | |
| 109 | /* |
| 110 | * CHV supports eDP 1.4 that have more link rates. |
| 111 | * Below only provides the fixed rate but exclude variable rate. |
| 112 | */ |
| 113 | static const struct dp_link_dpll chv_dpll[] = { |
| 114 | /* |
| 115 | * CHV requires to program fractional division for m2. |
| 116 | * m2 is stored in fixed point format using formula below |
| 117 | * (m2_int << 22) | m2_fraction |
| 118 | */ |
| 119 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
| 120 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
| 121 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
| 122 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
| 123 | }; |
| 124 | |
| 125 | /* Constants for DP DSC configurations */ |
| 126 | static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; |
| 127 | |
| 128 | /* With Single pipe configuration, HW is capable of supporting maximum |
| 129 | * of 4 slices per line. |
| 130 | */ |
| 131 | static const u8 valid_dsc_slicecount[] = {1, 2, 4}; |
| 132 | |
| 133 | /** |
| 134 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 135 | * @intel_dp: DP struct |
| 136 | * |
| 137 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 138 | * will return true, and false otherwise. |
| 139 | */ |
| 140 | bool_Bool intel_dp_is_edp(struct intel_dp *intel_dp) |
| 141 | { |
| 142 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 143 | |
| 144 | return dig_port->base.type == INTEL_OUTPUT_EDP; |
| 145 | } |
| 146 | |
| 147 | static void intel_dp_link_down(struct intel_encoder *encoder, |
| 148 | const struct intel_crtc_state *old_crtc_state); |
| 149 | static bool_Bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
| 150 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool_Bool sync); |
| 151 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
| 152 | const struct intel_crtc_state *crtc_state); |
| 153 | static void vlv_steal_power_sequencer(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 154 | enum pipe pipe); |
| 155 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
| 156 | |
| 157 | static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) |
| 158 | { |
| 159 | intel_dp->sink_rates[0] = 162000; |
| 160 | intel_dp->num_sink_rates = 1; |
| 161 | } |
| 162 | |
| 163 | /* update sink rates from dpcd */ |
| 164 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) |
| 165 | { |
| 166 | static const int dp_rates[] = { |
| 167 | 162000, 270000, 540000, 810000 |
| 168 | }; |
| 169 | int i, max_rate; |
| 170 | |
| 171 | if (drm_dp_has_quirk(&intel_dp->desc, 0, |
| 172 | DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { |
| 173 | /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ |
| 174 | static const int quirk_rates[] = { 162000, 270000, 324000 }; |
| 175 | |
| 176 | memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates))__builtin_memcpy((intel_dp->sink_rates), (quirk_rates), (sizeof (quirk_rates))); |
| 177 | intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates)(sizeof((quirk_rates)) / sizeof((quirk_rates)[0])); |
| 178 | |
| 179 | return; |
| 180 | } |
| 181 | |
| 182 | max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE0x001]); |
| 183 | |
| 184 | for (i = 0; i < ARRAY_SIZE(dp_rates)(sizeof((dp_rates)) / sizeof((dp_rates)[0])); i++) { |
| 185 | if (dp_rates[i] > max_rate) |
| 186 | break; |
| 187 | intel_dp->sink_rates[i] = dp_rates[i]; |
| 188 | } |
| 189 | |
| 190 | intel_dp->num_sink_rates = i; |
| 191 | } |
| 192 | |
| 193 | /* Get length of rates array potentially limited by max_rate. */ |
| 194 | static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) |
| 195 | { |
| 196 | int i; |
| 197 | |
| 198 | /* Limit results by potentially reduced max rate */ |
| 199 | for (i = 0; i < len; i++) { |
| 200 | if (rates[len - i - 1] <= max_rate) |
| 201 | return len - i; |
| 202 | } |
| 203 | |
| 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | /* Get length of common rates array potentially limited by max_rate. */ |
| 208 | static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, |
| 209 | int max_rate) |
| 210 | { |
| 211 | return intel_dp_rate_limit_len(intel_dp->common_rates, |
| 212 | intel_dp->num_common_rates, max_rate); |
| 213 | } |
| 214 | |
| 215 | /* Theoretical max between source and sink */ |
| 216 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) |
| 217 | { |
| 218 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
| 219 | } |
| 220 | |
| 221 | /* Theoretical max between source and sink */ |
| 222 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) |
| 223 | { |
| 224 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 225 | int source_max = dig_port->max_lanes; |
| 226 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
| 227 | int fia_max = intel_tc_port_fia_max_lane_count(dig_port); |
| 228 | |
| 229 | return min3(source_max, sink_max, fia_max)(((source_max)<((((sink_max)<(fia_max))?(sink_max):(fia_max ))))?(source_max):((((sink_max)<(fia_max))?(sink_max):(fia_max )))); |
| 230 | } |
| 231 | |
| 232 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
| 233 | { |
| 234 | return intel_dp->max_link_lane_count; |
| 235 | } |
| 236 | |
| 237 | int |
| 238 | intel_dp_link_required(int pixel_clock, int bpp) |
| 239 | { |
| 240 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
| 241 | return DIV_ROUND_UP(pixel_clock * bpp, 8)(((pixel_clock * bpp) + ((8) - 1)) / (8)); |
| 242 | } |
| 243 | |
| 244 | int |
| 245 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 246 | { |
| 247 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
| 248 | * link rate that is generally expressed in Gbps. Since, 8 bits of data |
| 249 | * is transmitted every LS_Clk per lane, there is no need to account for |
| 250 | * the channel encoding that is done in the PHY layer here. |
| 251 | */ |
| 252 | |
| 253 | return max_link_clock * max_lanes; |
| 254 | } |
| 255 | |
| 256 | static int cnl_max_source_rate(struct intel_dp *intel_dp) |
| 257 | { |
| 258 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 259 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 260 | enum port port = dig_port->base.port; |
| 261 | |
| 262 | u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3((const i915_reg_t){ .reg = (0x16210c) })) & VOLTAGE_INFO_MASK(3 << 24); |
| 263 | |
| 264 | /* Low voltage SKUs are limited to max of 5.4G */ |
| 265 | if (voltage == VOLTAGE_INFO_0_85V(0 << 24)) |
| 266 | return 540000; |
| 267 | |
| 268 | /* For this SKU 8.1G is supported in all ports */ |
| 269 | if (IS_CNL_WITH_PORT_F(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, (0))) |
| 270 | return 810000; |
| 271 | |
| 272 | /* For other SKUs, max rate on ports A and D is 5.4G */ |
| 273 | if (port == PORT_A || port == PORT_D) |
| 274 | return 540000; |
| 275 | |
| 276 | return 810000; |
| 277 | } |
| 278 | |
| 279 | static int icl_max_source_rate(struct intel_dp *intel_dp) |
| 280 | { |
| 281 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 282 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 283 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
| 284 | |
| 285 | if (intel_phy_is_combo(dev_priv, phy) && |
| 286 | !IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) && |
| 287 | !intel_dp_is_edp(intel_dp)) |
| 288 | return 540000; |
| 289 | |
| 290 | return 810000; |
| 291 | } |
| 292 | |
| 293 | static void |
| 294 | intel_dp_set_source_rates(struct intel_dp *intel_dp) |
| 295 | { |
| 296 | /* The values must be in increasing order */ |
| 297 | static const int cnl_rates[] = { |
| 298 | 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 |
| 299 | }; |
| 300 | static const int bxt_rates[] = { |
| 301 | 162000, 216000, 243000, 270000, 324000, 432000, 540000 |
| 302 | }; |
| 303 | static const int skl_rates[] = { |
| 304 | 162000, 216000, 270000, 324000, 432000, 540000 |
| 305 | }; |
| 306 | static const int hsw_rates[] = { |
| 307 | 162000, 270000, 540000 |
| 308 | }; |
| 309 | static const int g4x_rates[] = { |
| 310 | 162000, 270000 |
| 311 | }; |
| 312 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 313 | struct intel_encoder *encoder = &dig_port->base; |
| 314 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 315 | const int *source_rates; |
| 316 | int size, max_rate = 0, vbt_max_rate; |
| 317 | |
| 318 | /* This should only be done once */ |
| 319 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->source_rates || intel_dp-> num_source_rates)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->source_rates || intel_dp->num_source_rates" ")"); __builtin_expect(!!(__ret), 0); }) |
| 320 | intel_dp->source_rates || intel_dp->num_source_rates)({ int __ret = !!((intel_dp->source_rates || intel_dp-> num_source_rates)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->source_rates || intel_dp->num_source_rates" ")"); __builtin_expect(!!(__ret), 0); }); |
| 321 | |
| 322 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10) { |
| 323 | source_rates = cnl_rates; |
| 324 | size = ARRAY_SIZE(cnl_rates)(sizeof((cnl_rates)) / sizeof((cnl_rates)[0])); |
| 325 | if (IS_GEN(dev_priv, 10)(0 + (&(dev_priv)->__info)->gen == (10))) |
| 326 | max_rate = cnl_max_source_rate(intel_dp); |
| 327 | else |
| 328 | max_rate = icl_max_source_rate(intel_dp); |
| 329 | } else if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) { |
| 330 | source_rates = bxt_rates; |
| 331 | size = ARRAY_SIZE(bxt_rates)(sizeof((bxt_rates)) / sizeof((bxt_rates)[0])); |
| 332 | } else if (IS_GEN9_BC(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && !((&(dev_priv)->__info)->is_lp))) { |
| 333 | source_rates = skl_rates; |
| 334 | size = ARRAY_SIZE(skl_rates)(sizeof((skl_rates)) / sizeof((skl_rates)[0])); |
| 335 | } else if ((IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && !IS_HSW_ULX(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (1))) || |
| 336 | IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 337 | source_rates = hsw_rates; |
| 338 | size = ARRAY_SIZE(hsw_rates)(sizeof((hsw_rates)) / sizeof((hsw_rates)[0])); |
| 339 | } else { |
| 340 | source_rates = g4x_rates; |
| 341 | size = ARRAY_SIZE(g4x_rates)(sizeof((g4x_rates)) / sizeof((g4x_rates)[0])); |
| 342 | } |
| 343 | |
| 344 | vbt_max_rate = intel_bios_dp_max_link_rate(encoder); |
| 345 | if (max_rate && vbt_max_rate) |
| 346 | max_rate = min(max_rate, vbt_max_rate)(((max_rate)<(vbt_max_rate))?(max_rate):(vbt_max_rate)); |
| 347 | else if (vbt_max_rate) |
| 348 | max_rate = vbt_max_rate; |
| 349 | |
| 350 | if (max_rate) |
| 351 | size = intel_dp_rate_limit_len(source_rates, size, max_rate); |
| 352 | |
| 353 | intel_dp->source_rates = source_rates; |
| 354 | intel_dp->num_source_rates = size; |
| 355 | } |
| 356 | |
| 357 | static int intersect_rates(const int *source_rates, int source_len, |
| 358 | const int *sink_rates, int sink_len, |
| 359 | int *common_rates) |
| 360 | { |
| 361 | int i = 0, j = 0, k = 0; |
| 362 | |
| 363 | while (i < source_len && j < sink_len) { |
| 364 | if (source_rates[i] == sink_rates[j]) { |
| 365 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)({ int __ret = !!((k >= 8)); if (__ret) printf("%s", "WARN_ON(" "k >= 8" ")"); __builtin_expect(!!(__ret), 0); })) |
| 366 | return k; |
| 367 | common_rates[k] = source_rates[i]; |
| 368 | ++k; |
| 369 | ++i; |
| 370 | ++j; |
| 371 | } else if (source_rates[i] < sink_rates[j]) { |
| 372 | ++i; |
| 373 | } else { |
| 374 | ++j; |
| 375 | } |
| 376 | } |
| 377 | return k; |
| 378 | } |
| 379 | |
| 380 | /* return index of rate in rates array, or -1 if not found */ |
| 381 | static int intel_dp_rate_index(const int *rates, int len, int rate) |
| 382 | { |
| 383 | int i; |
| 384 | |
| 385 | for (i = 0; i < len; i++) |
| 386 | if (rate == rates[i]) |
| 387 | return i; |
| 388 | |
| 389 | return -1; |
| 390 | } |
| 391 | |
| 392 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
| 393 | { |
| 394 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 395 | |
| 396 | drm_WARN_ON(&i915->drm,({ int __ret = !!((!intel_dp->num_source_rates || !intel_dp ->num_sink_rates)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!intel_dp->num_source_rates || !intel_dp->num_sink_rates" ")"); __builtin_expect(!!(__ret), 0); }) |
| 397 | !intel_dp->num_source_rates || !intel_dp->num_sink_rates)({ int __ret = !!((!intel_dp->num_source_rates || !intel_dp ->num_sink_rates)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!intel_dp->num_source_rates || !intel_dp->num_sink_rates" ")"); __builtin_expect(!!(__ret), 0); }); |
| 398 | |
| 399 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
| 400 | intel_dp->num_source_rates, |
| 401 | intel_dp->sink_rates, |
| 402 | intel_dp->num_sink_rates, |
| 403 | intel_dp->common_rates); |
| 404 | |
| 405 | /* Paranoia, there should always be something in common. */ |
| 406 | if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)({ int __ret = !!((intel_dp->num_common_rates == 0)); if ( __ret) printf("%s %s: " "%s", dev_driver_string(((&i915-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->num_common_rates == 0" ")"); __builtin_expect(!!(__ret), 0); })) { |
| 407 | intel_dp->common_rates[0] = 162000; |
| 408 | intel_dp->num_common_rates = 1; |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | static bool_Bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
| 413 | u8 lane_count) |
| 414 | { |
| 415 | /* |
| 416 | * FIXME: we need to synchronize the current link parameters with |
| 417 | * hardware readout. Currently fast link training doesn't work on |
| 418 | * boot-up. |
| 419 | */ |
| 420 | if (link_rate == 0 || |
| 421 | link_rate > intel_dp->max_link_rate) |
| 422 | return false0; |
| 423 | |
| 424 | if (lane_count == 0 || |
| 425 | lane_count > intel_dp_max_lane_count(intel_dp)) |
| 426 | return false0; |
| 427 | |
| 428 | return true1; |
| 429 | } |
| 430 | |
| 431 | static bool_Bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, |
| 432 | int link_rate, |
| 433 | u8 lane_count) |
| 434 | { |
| 435 | const struct drm_display_mode *fixed_mode = |
| 436 | intel_dp->attached_connector->panel.fixed_mode; |
| 437 | int mode_rate, max_rate; |
| 438 | |
| 439 | mode_rate = intel_dp_link_required(fixed_mode->clock, 18); |
| 440 | max_rate = intel_dp_max_data_rate(link_rate, lane_count); |
| 441 | if (mode_rate > max_rate) |
| 442 | return false0; |
| 443 | |
| 444 | return true1; |
| 445 | } |
| 446 | |
| 447 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
| 448 | int link_rate, u8 lane_count) |
| 449 | { |
| 450 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 451 | int index; |
| 452 | |
| 453 | /* |
| 454 | * TODO: Enable fallback on MST links once MST link compute can handle |
| 455 | * the fallback params. |
| 456 | */ |
| 457 | if (intel_dp->is_mst) { |
| 458 | drm_err(&i915->drm, "Link Training Unsuccessful\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Link Training Unsuccessful\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 459 | return -1; |
| 460 | } |
| 461 | |
| 462 | index = intel_dp_rate_index(intel_dp->common_rates, |
| 463 | intel_dp->num_common_rates, |
| 464 | link_rate); |
| 465 | if (index > 0) { |
| 466 | if (intel_dp_is_edp(intel_dp) && |
| 467 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, |
| 468 | intel_dp->common_rates[index - 1], |
| 469 | lane_count)) { |
| 470 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Retrying Link training for eDP with same parameters\n" ) |
| 471 | "Retrying Link training for eDP with same parameters\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Retrying Link training for eDP with same parameters\n" ); |
| 472 | return 0; |
| 473 | } |
| 474 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
| 475 | intel_dp->max_link_lane_count = lane_count; |
| 476 | } else if (lane_count > 1) { |
| 477 | if (intel_dp_is_edp(intel_dp) && |
| 478 | !intel_dp_can_link_train_fallback_for_edp(intel_dp, |
| 479 | intel_dp_max_common_rate(intel_dp), |
| 480 | lane_count >> 1)) { |
| 481 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Retrying Link training for eDP with same parameters\n" ) |
| 482 | "Retrying Link training for eDP with same parameters\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Retrying Link training for eDP with same parameters\n" ); |
| 483 | return 0; |
| 484 | } |
| 485 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
| 486 | intel_dp->max_link_lane_count = lane_count >> 1; |
| 487 | } else { |
| 488 | drm_err(&i915->drm, "Link Training Unsuccessful\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Link Training Unsuccessful\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 489 | return -1; |
| 490 | } |
| 491 | |
| 492 | return 0; |
| 493 | } |
| 494 | |
| 495 | u32 intel_dp_mode_to_fec_clock(u32 mode_clock) |
| 496 | { |
| 497 | return div_u64(mul_u32_u32(mode_clock, 1000000U), |
| 498 | DP_DSC_FEC_OVERHEAD_FACTOR972261); |
| 499 | } |
| 500 | |
| 501 | static int |
| 502 | small_joiner_ram_size_bits(struct drm_i915_privateinteldrm_softc *i915) |
| 503 | { |
| 504 | if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 11) |
| 505 | return 7680 * 8; |
| 506 | else |
| 507 | return 6144 * 8; |
| 508 | } |
| 509 | |
| 510 | static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_privateinteldrm_softc *i915, |
| 511 | u32 link_clock, u32 lane_count, |
| 512 | u32 mode_clock, u32 mode_hdisplay) |
| 513 | { |
| 514 | u32 bits_per_pixel, max_bpp_small_joiner_ram; |
| 515 | int i; |
| 516 | |
| 517 | /* |
| 518 | * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* |
| 519 | * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) |
| 520 | * for SST -> TimeSlotsPerMTP is 1, |
| 521 | * for MST -> TimeSlotsPerMTP has to be calculated |
| 522 | */ |
| 523 | bits_per_pixel = (link_clock * lane_count * 8) / |
| 524 | intel_dp_mode_to_fec_clock(mode_clock); |
| 525 | drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Max link bpp: %u\n" , bits_per_pixel); |
| 526 | |
| 527 | /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ |
| 528 | max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / |
| 529 | mode_hdisplay; |
| 530 | drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Max small joiner bpp: %u\n" , max_bpp_small_joiner_ram) |
| 531 | max_bpp_small_joiner_ram)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Max small joiner bpp: %u\n" , max_bpp_small_joiner_ram); |
| 532 | |
| 533 | /* |
| 534 | * Greatest allowed DSC BPP = MIN (output BPP from available Link BW |
| 535 | * check, output bpp from small joiner RAM check) |
| 536 | */ |
| 537 | bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram)(((bits_per_pixel)<(max_bpp_small_joiner_ram))?(bits_per_pixel ):(max_bpp_small_joiner_ram)); |
| 538 | |
| 539 | /* Error out if the max bpp is less than smallest allowed valid bpp */ |
| 540 | if (bits_per_pixel < valid_dsc_bpp[0]) { |
| 541 | drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported BPP %u, min %u\n" , bits_per_pixel, valid_dsc_bpp[0]) |
| 542 | bits_per_pixel, valid_dsc_bpp[0])drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported BPP %u, min %u\n" , bits_per_pixel, valid_dsc_bpp[0]); |
| 543 | return 0; |
| 544 | } |
| 545 | |
| 546 | /* Find the nearest match in the array of known BPPs from VESA */ |
| 547 | for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp)(sizeof((valid_dsc_bpp)) / sizeof((valid_dsc_bpp)[0])) - 1; i++) { |
| 548 | if (bits_per_pixel < valid_dsc_bpp[i + 1]) |
| 549 | break; |
| 550 | } |
| 551 | bits_per_pixel = valid_dsc_bpp[i]; |
| 552 | |
| 553 | /* |
| 554 | * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, |
| 555 | * fractional part is 0 |
| 556 | */ |
| 557 | return bits_per_pixel << 4; |
| 558 | } |
| 559 | |
| 560 | static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, |
| 561 | int mode_clock, int mode_hdisplay) |
| 562 | { |
| 563 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 564 | u8 min_slice_count, i; |
| 565 | int max_slice_width; |
| 566 | |
| 567 | if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE2720000) |
| 568 | min_slice_count = DIV_ROUND_UP(mode_clock,(((mode_clock) + ((340000) - 1)) / (340000)) |
| 569 | DP_DSC_MAX_ENC_THROUGHPUT_0)(((mode_clock) + ((340000) - 1)) / (340000)); |
| 570 | else |
| 571 | min_slice_count = DIV_ROUND_UP(mode_clock,(((mode_clock) + ((400000) - 1)) / (400000)) |
| 572 | DP_DSC_MAX_ENC_THROUGHPUT_1)(((mode_clock) + ((400000) - 1)) / (400000)); |
| 573 | |
| 574 | max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); |
| 575 | if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE2560) { |
| 576 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported slice width %d by DP DSC Sink device\n" , max_slice_width) |
| 577 | "Unsupported slice width %d by DP DSC Sink device\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported slice width %d by DP DSC Sink device\n" , max_slice_width) |
| 578 | max_slice_width)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported slice width %d by DP DSC Sink device\n" , max_slice_width); |
| 579 | return 0; |
| 580 | } |
| 581 | /* Also take into account max slice width */ |
| 582 | min_slice_count = max_t(u8, min_slice_count,({ u8 __max_a = (min_slice_count); u8 __max_b = ((((mode_hdisplay ) + ((max_slice_width) - 1)) / (max_slice_width))); __max_a > __max_b ? __max_a : __max_b; }) |
| 583 | DIV_ROUND_UP(mode_hdisplay,({ u8 __max_a = (min_slice_count); u8 __max_b = ((((mode_hdisplay ) + ((max_slice_width) - 1)) / (max_slice_width))); __max_a > __max_b ? __max_a : __max_b; }) |
| 584 | max_slice_width))({ u8 __max_a = (min_slice_count); u8 __max_b = ((((mode_hdisplay ) + ((max_slice_width) - 1)) / (max_slice_width))); __max_a > __max_b ? __max_a : __max_b; }); |
| 585 | |
| 586 | /* Find the closest match to the valid slice count values */ |
| 587 | for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount)(sizeof((valid_dsc_slicecount)) / sizeof((valid_dsc_slicecount )[0])); i++) { |
| 588 | if (valid_dsc_slicecount[i] > |
| 589 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
| 590 | false0)) |
| 591 | break; |
| 592 | if (min_slice_count <= valid_dsc_slicecount[i]) |
| 593 | return valid_dsc_slicecount[i]; |
| 594 | } |
| 595 | |
| 596 | drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported Slice Count %d\n" , min_slice_count) |
| 597 | min_slice_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unsupported Slice Count %d\n" , min_slice_count); |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static bool_Bool intel_dp_hdisplay_bad(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 602 | int hdisplay) |
| 603 | { |
| 604 | /* |
| 605 | * Older platforms don't like hdisplay==4096 with DP. |
| 606 | * |
| 607 | * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline |
| 608 | * and frame counter increment), but we don't get vblank interrupts, |
| 609 | * and the pipe underruns immediately. The link also doesn't seem |
| 610 | * to get trained properly. |
| 611 | * |
| 612 | * On CHV the vblank interrupts don't seem to disappear but |
| 613 | * otherwise the symptoms are similar. |
| 614 | * |
| 615 | * TODO: confirm the behaviour on HSW+ |
| 616 | */ |
| 617 | return hdisplay == 4096 && !HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi); |
| 618 | } |
| 619 | |
| 620 | static enum drm_mode_status |
| 621 | intel_dp_mode_valid_downstream(struct intel_connector *connector, |
| 622 | const struct drm_display_mode *mode, |
| 623 | int target_clock) |
| 624 | { |
| 625 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 626 | const struct drm_display_info *info = &connector->base.display_info; |
| 627 | int tmds_clock; |
| 628 | |
| 629 | if (intel_dp->dfp.max_dotclock && |
| 630 | target_clock > intel_dp->dfp.max_dotclock) |
| 631 | return MODE_CLOCK_HIGH; |
| 632 | |
| 633 | /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ |
| 634 | tmds_clock = target_clock; |
| 635 | if (drm_mode_is_420_only(info, mode)) |
| 636 | tmds_clock /= 2; |
| 637 | |
| 638 | if (intel_dp->dfp.min_tmds_clock && |
| 639 | tmds_clock < intel_dp->dfp.min_tmds_clock) |
| 640 | return MODE_CLOCK_LOW; |
| 641 | if (intel_dp->dfp.max_tmds_clock && |
| 642 | tmds_clock > intel_dp->dfp.max_tmds_clock) |
| 643 | return MODE_CLOCK_HIGH; |
| 644 | |
| 645 | return MODE_OK; |
| 646 | } |
| 647 | |
| 648 | static enum drm_mode_status |
| 649 | intel_dp_mode_valid(struct drm_connector *connector, |
| 650 | struct drm_display_mode *mode) |
| 651 | { |
| 652 | struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 653 | struct intel_connector *intel_connector = to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );}); |
| 654 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
| 655 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->dev); |
| 656 | int target_clock = mode->clock; |
| 657 | int max_rate, mode_rate, max_lanes, max_link_clock; |
| 658 | int max_dotclk = dev_priv->max_dotclk_freq; |
| 659 | u16 dsc_max_output_bpp = 0; |
| 660 | u8 dsc_slice_count = 0; |
| 661 | enum drm_mode_status status; |
| 662 | |
| 663 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)) |
| 664 | return MODE_NO_DBLESCAN; |
| 665 | |
| 666 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
| 667 | if (mode->hdisplay > fixed_mode->hdisplay) |
| 668 | return MODE_PANEL; |
| 669 | |
| 670 | if (mode->vdisplay > fixed_mode->vdisplay) |
| 671 | return MODE_PANEL; |
| 672 | |
| 673 | target_clock = fixed_mode->clock; |
| 674 | } |
| 675 | |
| 676 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
| 677 | max_lanes = intel_dp_max_lane_count(intel_dp); |
| 678 | |
| 679 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 680 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 681 | |
| 682 | if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) |
| 683 | return MODE_H_ILLEGAL; |
| 684 | |
| 685 | /* |
| 686 | * Output bpp is stored in 6.4 format so right shift by 4 to get the |
| 687 | * integer value since we support only integer values of bpp. |
| 688 | */ |
| 689 | if ((INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) && |
| 690 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { |
| 691 | if (intel_dp_is_edp(intel_dp)) { |
| 692 | dsc_max_output_bpp = |
| 693 | drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; |
| 694 | dsc_slice_count = |
| 695 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
| 696 | true1); |
| 697 | } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { |
| 698 | dsc_max_output_bpp = |
| 699 | intel_dp_dsc_get_output_bpp(dev_priv, |
| 700 | max_link_clock, |
| 701 | max_lanes, |
| 702 | target_clock, |
| 703 | mode->hdisplay) >> 4; |
| 704 | dsc_slice_count = |
| 705 | intel_dp_dsc_get_slice_count(intel_dp, |
| 706 | target_clock, |
| 707 | mode->hdisplay); |
| 708 | } |
| 709 | } |
| 710 | |
| 711 | if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || |
| 712 | target_clock > max_dotclk) |
| 713 | return MODE_CLOCK_HIGH; |
| 714 | |
| 715 | if (mode->clock < 10000) |
| 716 | return MODE_CLOCK_LOW; |
| 717 | |
| 718 | if (mode->flags & DRM_MODE_FLAG_DBLCLK(1<<12)) |
| 719 | return MODE_H_ILLEGAL; |
| 720 | |
| 721 | status = intel_dp_mode_valid_downstream(intel_connector, |
| 722 | mode, target_clock); |
| 723 | if (status != MODE_OK) |
| 724 | return status; |
| 725 | |
| 726 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
| 727 | } |
| 728 | |
| 729 | u32 intel_dp_pack_aux(const u8 *src, int src_bytes) |
| 730 | { |
| 731 | int i; |
| 732 | u32 v = 0; |
| 733 | |
| 734 | if (src_bytes > 4) |
| 735 | src_bytes = 4; |
| 736 | for (i = 0; i < src_bytes; i++) |
| 737 | v |= ((u32)src[i]) << ((3 - i) * 8); |
| 738 | return v; |
| 739 | } |
| 740 | |
| 741 | static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) |
| 742 | { |
| 743 | int i; |
| 744 | if (dst_bytes > 4) |
| 745 | dst_bytes = 4; |
| 746 | for (i = 0; i < dst_bytes; i++) |
| 747 | dst[i] = src >> ((3-i) * 8); |
| 748 | } |
| 749 | |
| 750 | static void |
| 751 | intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); |
| 752 | static void |
| 753 | intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, |
| 754 | bool_Bool force_disable_vdd); |
| 755 | static void |
| 756 | intel_dp_pps_init(struct intel_dp *intel_dp); |
| 757 | |
| 758 | static intel_wakeref_t |
| 759 | pps_lock(struct intel_dp *intel_dp) |
| 760 | { |
| 761 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 762 | intel_wakeref_t wakeref; |
| 763 | |
| 764 | /* |
| 765 | * See intel_power_sequencer_reset() why we need |
| 766 | * a power domain reference here. |
| 767 | */ |
| 768 | wakeref = intel_display_power_get(dev_priv, |
| 769 | intel_aux_power_domain(dp_to_dig_port(intel_dp))); |
| 770 | |
| 771 | mutex_lock(&dev_priv->pps_mutex)rw_enter_write(&dev_priv->pps_mutex); |
| 772 | |
| 773 | return wakeref; |
| 774 | } |
| 775 | |
| 776 | static intel_wakeref_t |
| 777 | pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) |
| 778 | { |
| 779 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 780 | |
| 781 | mutex_unlock(&dev_priv->pps_mutex)rw_exit_write(&dev_priv->pps_mutex); |
| 782 | intel_display_power_put(dev_priv, |
| 783 | intel_aux_power_domain(dp_to_dig_port(intel_dp)), |
| 784 | wakeref); |
| 785 | return 0; |
| 786 | } |
| 787 | |
| 788 | #define with_pps_lock(dp, wf)for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)) ) \ |
| 789 | for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) |
| 790 | |
| 791 | static void |
| 792 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
| 793 | { |
| 794 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 795 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 796 | enum pipe pipe = intel_dp->pps_pipe; |
| 797 | bool_Bool pll_enabled, release_cl_override = false0; |
| 798 | enum dpio_phy phy = DPIO_PHY(pipe)((pipe) >> 1); |
| 799 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
| 800 | u32 DP; |
| 801 | |
| 802 | if (drm_WARN(&dev_priv->drm,({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
| 803 | intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
| 804 | "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
| 805 | pipe_name(pipe), dig_port->base.base.base.id,({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
| 806 | dig_port->base.base.name)({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); })) |
| 807 | return; |
| 808 | |
| 809 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
| 810 | "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
| 811 | pipe_name(pipe), dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
| 812 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name); |
| 813 | |
| 814 | /* Preserve the BIOS-computed detected bit. This is |
| 815 | * supposed to be read-only. |
| 816 | */ |
| 817 | DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED(1 << 2); |
| 818 | DP |= DP_VOLTAGE_0_4(0 << 25) | DP_PRE_EMPHASIS_0(0 << 22); |
| 819 | DP |= DP_PORT_WIDTH(1)(((1) - 1) << 19); |
| 820 | DP |= DP_LINK_TRAIN_PAT_1(0 << 28); |
| 821 | |
| 822 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 823 | DP |= DP_PIPE_SEL_CHV(pipe)((pipe) << 16); |
| 824 | else |
| 825 | DP |= DP_PIPE_SEL(pipe)((pipe) << 30); |
| 826 | |
| 827 | pll_enabled = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })) & DPLL_VCO_ENABLE(1 << 31); |
| 828 | |
| 829 | /* |
| 830 | * The DPLL for the pipe must be enabled for this to work. |
| 831 | * So enable temporarily it if it's not already enabled. |
| 832 | */ |
| 833 | if (!pll_enabled) { |
| 834 | release_cl_override = IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && |
| 835 | !chv_phy_powergate_ch(dev_priv, phy, ch, true1); |
| 836 | |
| 837 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) ? |
| 838 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
| 839 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to force on pll for pipe %c!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
| 840 | "Failed to force on pll for pipe %c!\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to force on pll for pipe %c!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
| 841 | pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to force on pll for pipe %c!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')); |
| 842 | return; |
| 843 | } |
| 844 | } |
| 845 | |
| 846 | /* |
| 847 | * Similar magic as in intel_dp_enable_port(). |
| 848 | * We _must_ do this port enable + disable trick |
| 849 | * to make this power sequencer lock onto the port. |
| 850 | * Otherwise even VDD force bit won't work. |
| 851 | */ |
| 852 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
| 853 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 854 | |
| 855 | intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN(1 << 31)); |
| 856 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 857 | |
| 858 | intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN(1 << 31)); |
| 859 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 860 | |
| 861 | if (!pll_enabled) { |
| 862 | vlv_force_pll_off(dev_priv, pipe); |
| 863 | |
| 864 | if (release_cl_override) |
| 865 | chv_phy_powergate_ch(dev_priv, phy, ch, false0); |
| 866 | } |
| 867 | } |
| 868 | |
| 869 | static enum pipe vlv_find_free_pps(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 870 | { |
| 871 | struct intel_encoder *encoder; |
| 872 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
| 873 | |
| 874 | /* |
| 875 | * We don't have power sequencer currently. |
| 876 | * Pick one that's not used by other ports. |
| 877 | */ |
| 878 | for_each_intel_dp(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) if (!(intel_encoder_is_dp (encoder))) {} else { |
| 879 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 880 | |
| 881 | if (encoder->type == INTEL_OUTPUT_EDP) { |
| 882 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
| 883 | intel_dp->active_pipe != INVALID_PIPE &&({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
| 884 | intel_dp->active_pipe !=({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
| 885 | intel_dp->pps_pipe)({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }); |
| 886 | |
| 887 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 888 | pipes &= ~(1 << intel_dp->pps_pipe); |
| 889 | } else { |
| 890 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->pps_pipe != INVALID_PIPE)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }) |
| 891 | intel_dp->pps_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->pps_pipe != INVALID_PIPE)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
| 892 | |
| 893 | if (intel_dp->active_pipe != INVALID_PIPE) |
| 894 | pipes &= ~(1 << intel_dp->active_pipe); |
| 895 | } |
| 896 | } |
| 897 | |
| 898 | if (pipes == 0) |
| 899 | return INVALID_PIPE; |
| 900 | |
| 901 | return ffs(pipes) - 1; |
| 902 | } |
| 903 | |
| 904 | static enum pipe |
| 905 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 906 | { |
| 907 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 908 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 909 | enum pipe pipe; |
| 910 | |
| 911 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 912 | |
| 913 | /* We should never land here with regular DP ports */ |
| 914 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp))({ int __ret = !!((!intel_dp_is_edp(intel_dp))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!intel_dp_is_edp(intel_dp)" ")"); __builtin_expect (!!(__ret), 0); }); |
| 915 | |
| 916 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
| 917 | intel_dp->active_pipe != intel_dp->pps_pipe)({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE && intel_dp->active_pipe != intel_dp->pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }); |
| 918 | |
| 919 | if (intel_dp->pps_pipe != INVALID_PIPE) |
| 920 | return intel_dp->pps_pipe; |
| 921 | |
| 922 | pipe = vlv_find_free_pps(dev_priv); |
| 923 | |
| 924 | /* |
| 925 | * Didn't find one. This should not happen since there |
| 926 | * are two power sequencers and up to two eDP ports. |
| 927 | */ |
| 928 | if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)({ int __ret = !!((pipe == INVALID_PIPE)); if (__ret) printf( "%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "pipe == INVALID_PIPE" ")"); __builtin_expect (!!(__ret), 0); })) |
| 929 | pipe = PIPE_A; |
| 930 | |
| 931 | vlv_steal_power_sequencer(dev_priv, pipe); |
| 932 | intel_dp->pps_pipe = pipe; |
| 933 | |
| 934 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), dig_port->base.base.base .id, dig_port->base.base.name) |
| 935 | "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), dig_port->base.base.base .id, dig_port->base.base.name) |
| 936 | pipe_name(intel_dp->pps_pipe),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), dig_port->base.base.base .id, dig_port->base.base.name) |
| 937 | dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), dig_port->base.base.base .id, dig_port->base.base.name) |
| 938 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), dig_port->base.base.base .id, dig_port->base.base.name); |
| 939 | |
| 940 | /* init power sequencer on this pipe and port */ |
| 941 | intel_dp_init_panel_power_sequencer(intel_dp); |
| 942 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true1); |
| 943 | |
| 944 | /* |
| 945 | * Even vdd force doesn't work until we've made |
| 946 | * the power sequencer lock in on the port. |
| 947 | */ |
| 948 | vlv_power_sequencer_kick(intel_dp); |
| 949 | |
| 950 | return intel_dp->pps_pipe; |
| 951 | } |
| 952 | |
| 953 | static int |
| 954 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) |
| 955 | { |
| 956 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 957 | int backlight_controller = dev_priv->vbt.backlight.controller; |
| 958 | |
| 959 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 960 | |
| 961 | /* We should never land here with regular DP ports */ |
| 962 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp))({ int __ret = !!((!intel_dp_is_edp(intel_dp))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!intel_dp_is_edp(intel_dp)" ")"); __builtin_expect (!!(__ret), 0); }); |
| 963 | |
| 964 | if (!intel_dp->pps_reset) |
| 965 | return backlight_controller; |
| 966 | |
| 967 | intel_dp->pps_reset = false0; |
| 968 | |
| 969 | /* |
| 970 | * Only the HW needs to be reprogrammed, the SW state is fixed and |
| 971 | * has been setup during connector init. |
| 972 | */ |
| 973 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false0); |
| 974 | |
| 975 | return backlight_controller; |
| 976 | } |
| 977 | |
| 978 | typedef bool_Bool (*vlv_pipe_check)(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 979 | enum pipe pipe); |
| 980 | |
| 981 | static bool_Bool vlv_pipe_has_pp_on(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 982 | enum pipe pipe) |
| 983 | { |
| 984 | return intel_de_read(dev_priv, PP_STATUS(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61200) + (pipe) * 0x100) })) & PP_ON((u32)((1UL << (31)) + 0)); |
| 985 | } |
| 986 | |
| 987 | static bool_Bool vlv_pipe_has_vdd_on(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 988 | enum pipe pipe) |
| 989 | { |
| 990 | return intel_de_read(dev_priv, PP_CONTROL(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (pipe) * 0x100) })) & EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
| 991 | } |
| 992 | |
| 993 | static bool_Bool vlv_pipe_any(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 994 | enum pipe pipe) |
| 995 | { |
| 996 | return true1; |
| 997 | } |
| 998 | |
| 999 | static enum pipe |
| 1000 | vlv_initial_pps_pipe(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1001 | enum port port, |
| 1002 | vlv_pipe_check pipe_check) |
| 1003 | { |
| 1004 | enum pipe pipe; |
| 1005 | |
| 1006 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 1007 | u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61208) + (pipe) * 0x100) })) & |
| 1008 | PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)); |
| 1009 | |
| 1010 | if (port_sel != PANEL_PORT_SELECT_VLV(port)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(port) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 ))) |
| 1011 | continue; |
| 1012 | |
| 1013 | if (!pipe_check(dev_priv, pipe)) |
| 1014 | continue; |
| 1015 | |
| 1016 | return pipe; |
| 1017 | } |
| 1018 | |
| 1019 | return INVALID_PIPE; |
| 1020 | } |
| 1021 | |
| 1022 | static void |
| 1023 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
| 1024 | { |
| 1025 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1026 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1027 | enum port port = dig_port->base.port; |
| 1028 | |
| 1029 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 1030 | |
| 1031 | /* try to find a pipe with this port selected */ |
| 1032 | /* first pick one where the panel is on */ |
| 1033 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 1034 | vlv_pipe_has_pp_on); |
| 1035 | /* didn't find one? pick one where vdd is on */ |
| 1036 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 1037 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 1038 | vlv_pipe_has_vdd_on); |
| 1039 | /* didn't find one? pick one with just the correct port */ |
| 1040 | if (intel_dp->pps_pipe == INVALID_PIPE) |
| 1041 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
| 1042 | vlv_pipe_any); |
| 1043 | |
| 1044 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
| 1045 | if (intel_dp->pps_pipe == INVALID_PIPE) { |
| 1046 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 1047 | "no initial power sequencer for [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 1048 | dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 1049 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
| 1050 | return; |
| 1051 | } |
| 1052 | |
| 1053 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps_pipe) + 'A')) |
| 1054 | "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps_pipe) + 'A')) |
| 1055 | dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps_pipe) + 'A')) |
| 1056 | dig_port->base.base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps_pipe) + 'A')) |
| 1057 | pipe_name(intel_dp->pps_pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps_pipe) + 'A')); |
| 1058 | |
| 1059 | intel_dp_init_panel_power_sequencer(intel_dp); |
| 1060 | intel_dp_init_panel_power_sequencer_registers(intel_dp, false0); |
| 1061 | } |
| 1062 | |
| 1063 | void intel_power_sequencer_reset(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 1064 | { |
| 1065 | struct intel_encoder *encoder; |
| 1066 | |
| 1067 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv )->__info)->gen == (9)) && ((&(dev_priv)-> __info)->is_lp))))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1068 | !(IS_VALLEYVIEW(dev_priv) ||({ int __ret = !!((!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv )->__info)->gen == (9)) && ((&(dev_priv)-> __info)->is_lp))))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1069 | IS_CHERRYVIEW(dev_priv) ||({ int __ret = !!((!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv )->__info)->gen == (9)) && ((&(dev_priv)-> __info)->is_lp))))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1070 | IS_GEN9_LP(dev_priv)))({ int __ret = !!((!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv )->__info)->gen == (9)) && ((&(dev_priv)-> __info)->is_lp))))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "!(IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || ((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)))" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1071 | return; |
| 1072 | |
| 1073 | /* |
| 1074 | * We can't grab pps_mutex here due to deadlock with power_domain |
| 1075 | * mutex when power_domain functions are called while holding pps_mutex. |
| 1076 | * That also means that in order to use pps_pipe the code needs to |
| 1077 | * hold both a power domain reference and pps_mutex, and the power domain |
| 1078 | * reference get/put must be done while _not_ holding pps_mutex. |
| 1079 | * pps_{lock,unlock}() do these steps in the correct order, so one |
| 1080 | * should use them always. |
| 1081 | */ |
| 1082 | |
| 1083 | for_each_intel_dp(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) if (!(intel_encoder_is_dp (encoder))) {} else { |
| 1084 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 1085 | |
| 1086 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1087 | intel_dp->active_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1088 | |
| 1089 | if (encoder->type != INTEL_OUTPUT_EDP) |
| 1090 | continue; |
| 1091 | |
| 1092 | if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) |
| 1093 | intel_dp->pps_reset = true1; |
| 1094 | else |
| 1095 | intel_dp->pps_pipe = INVALID_PIPE; |
| 1096 | } |
| 1097 | } |
| 1098 | |
| 1099 | struct pps_registers { |
| 1100 | i915_reg_t pp_ctrl; |
| 1101 | i915_reg_t pp_stat; |
| 1102 | i915_reg_t pp_on; |
| 1103 | i915_reg_t pp_off; |
| 1104 | i915_reg_t pp_div; |
| 1105 | }; |
| 1106 | |
| 1107 | static void intel_pps_get_registers(struct intel_dp *intel_dp, |
| 1108 | struct pps_registers *regs) |
| 1109 | { |
| 1110 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1111 | int pps_idx = 0; |
| 1112 | |
| 1113 | memset(regs, 0, sizeof(*regs))__builtin_memset((regs), (0), (sizeof(*regs))); |
| 1114 | |
| 1115 | if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) |
| 1116 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
| 1117 | else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 1118 | pps_idx = vlv_power_sequencer_pipe(intel_dp); |
| 1119 | |
| 1120 | regs->pp_ctrl = PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (pps_idx) * 0x100) }); |
| 1121 | regs->pp_stat = PP_STATUS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61200) + (pps_idx) * 0x100) }); |
| 1122 | regs->pp_on = PP_ON_DELAYS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61208) + (pps_idx) * 0x100) }); |
| 1123 | regs->pp_off = PP_OFF_DELAYS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x6120C) + (pps_idx) * 0x100) }); |
| 1124 | |
| 1125 | /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ |
| 1126 | if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)) || INTEL_PCH_TYPE(dev_priv)((dev_priv)->pch_type) >= PCH_CNP) |
| 1127 | regs->pp_div = INVALID_MMIO_REG((const i915_reg_t){ .reg = (0) }); |
| 1128 | else |
| 1129 | regs->pp_div = PP_DIVISOR(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61210) + (pps_idx) * 0x100) }); |
| 1130 | } |
| 1131 | |
| 1132 | static i915_reg_t |
| 1133 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
| 1134 | { |
| 1135 | struct pps_registers regs; |
| 1136 | |
| 1137 | intel_pps_get_registers(intel_dp, ®s); |
| 1138 | |
| 1139 | return regs.pp_ctrl; |
| 1140 | } |
| 1141 | |
| 1142 | static i915_reg_t |
| 1143 | _pp_stat_reg(struct intel_dp *intel_dp) |
| 1144 | { |
| 1145 | struct pps_registers regs; |
| 1146 | |
| 1147 | intel_pps_get_registers(intel_dp, ®s); |
| 1148 | |
| 1149 | return regs.pp_stat; |
| 1150 | } |
| 1151 | |
| 1152 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
| 1153 | This function only applicable when panel PM state is not to be tracked */ |
| 1154 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, |
| 1155 | void *unused) |
| 1156 | { |
| 1157 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),({ const __typeof( ((typeof(* intel_dp) *)0)->edp_notifier ) *__mptr = (this); (typeof(* intel_dp) *)( (char *)__mptr - __builtin_offsetof(typeof(* intel_dp), edp_notifier) );}) |
| 1158 | edp_notifier)({ const __typeof( ((typeof(* intel_dp) *)0)->edp_notifier ) *__mptr = (this); (typeof(* intel_dp) *)( (char *)__mptr - __builtin_offsetof(typeof(* intel_dp), edp_notifier) );}); |
| 1159 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1160 | intel_wakeref_t wakeref; |
| 1161 | |
| 1162 | if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART0) |
| 1163 | return 0; |
| 1164 | |
| 1165 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) { |
| 1166 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 1167 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 1168 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
| 1169 | u32 pp_div; |
| 1170 | |
| 1171 | pp_ctrl_reg = PP_CONTROL(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (pipe) * 0x100) }); |
| 1172 | pp_div_reg = PP_DIVISOR(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61210) + (pipe) * 0x100) }); |
| 1173 | pp_div = intel_de_read(dev_priv, pp_div_reg); |
| 1174 | pp_div &= PP_REFERENCE_DIVIDER_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (8))) + 0)); |
| 1175 | |
| 1176 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ |
| 1177 | intel_de_write(dev_priv, pp_div_reg, pp_div | 0x1F); |
| 1178 | intel_de_write(dev_priv, pp_ctrl_reg, |
| 1179 | PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 ))); |
| 1180 | drm_msleep(intel_dp->panel_power_cycle_delay)mdelay(intel_dp->panel_power_cycle_delay); |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | return 0; |
| 1185 | } |
| 1186 | |
| 1187 | static bool_Bool edp_have_panel_power(struct intel_dp *intel_dp) |
| 1188 | { |
| 1189 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1190 | |
| 1191 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 1192 | |
| 1193 | if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) && |
| 1194 | intel_dp->pps_pipe == INVALID_PIPE) |
| 1195 | return false0; |
| 1196 | |
| 1197 | return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON((u32)((1UL << (31)) + 0))) != 0; |
| 1198 | } |
| 1199 | |
| 1200 | static bool_Bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
| 1201 | { |
| 1202 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1203 | |
| 1204 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 1205 | |
| 1206 | if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) && |
| 1207 | intel_dp->pps_pipe == INVALID_PIPE) |
| 1208 | return false0; |
| 1209 | |
| 1210 | return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
| 1211 | } |
| 1212 | |
| 1213 | static void |
| 1214 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 1215 | { |
| 1216 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1217 | |
| 1218 | if (!intel_dp_is_edp(intel_dp)) |
| 1219 | return; |
| 1220 | |
| 1221 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
| 1222 | drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "eDP powered off while attempting aux channel communication.\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }) |
| 1223 | "eDP powered off while attempting aux channel communication.\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "eDP powered off while attempting aux channel communication.\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }); |
| 1224 | drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Status 0x%08x Control 0x%08x\n" , intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read (dev_priv, _pp_ctrl_reg(intel_dp))) |
| 1225 | intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Status 0x%08x Control 0x%08x\n" , intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read (dev_priv, _pp_ctrl_reg(intel_dp))) |
| 1226 | intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Status 0x%08x Control 0x%08x\n" , intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read (dev_priv, _pp_ctrl_reg(intel_dp))); |
| 1227 | } |
| 1228 | } |
| 1229 | |
| 1230 | static u32 |
| 1231 | intel_dp_aux_wait_done(struct intel_dp *intel_dp) |
| 1232 | { |
| 1233 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 1234 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
| 1235 | const unsigned int timeout_ms = 10; |
| 1236 | u32 status; |
| 1237 | bool_Bool done; |
| 1238 | |
| 1239 | #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY(1 << 31)) == 0) |
| 1240 | done = wait_event_timeout(i915->gmbus_wait_queue, C,({ long __ret = msecs_to_jiffies_timeout(timeout_ms); if (!(C )) __ret = ({ long ret = msecs_to_jiffies_timeout(timeout_ms) ; do { int __error; unsigned long deadline; ((!cold) ? (void) 0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_dp.c" , 1241, "!cold")); mtx_enter(&sch_mtx); deadline = jiffies + ret; __error = msleep(&i915->gmbus_wait_queue, & sch_mtx, 0, "drmweti", ret); ret = deadline - jiffies; if (__error == -1 || __error == 4) { ret = -4; mtx_leave(&sch_mtx); break ; } if ((msecs_to_jiffies_timeout(timeout_ms)) > 0 && (ret <= 0 || __error == 35)) { mtx_leave(&sch_mtx); ret = ((C)) ? 1 : 0; break; } mtx_leave(&sch_mtx); } while ( ret > 0 && !(C)); ret; }); __ret; }) |
| 1241 | msecs_to_jiffies_timeout(timeout_ms))({ long __ret = msecs_to_jiffies_timeout(timeout_ms); if (!(C )) __ret = ({ long ret = msecs_to_jiffies_timeout(timeout_ms) ; do { int __error; unsigned long deadline; ((!cold) ? (void) 0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_dp.c" , 1241, "!cold")); mtx_enter(&sch_mtx); deadline = jiffies + ret; __error = msleep(&i915->gmbus_wait_queue, & sch_mtx, 0, "drmweti", ret); ret = deadline - jiffies; if (__error == -1 || __error == 4) { ret = -4; mtx_leave(&sch_mtx); break ; } if ((msecs_to_jiffies_timeout(timeout_ms)) > 0 && (ret <= 0 || __error == 35)) { mtx_leave(&sch_mtx); ret = ((C)) ? 1 : 0; break; } mtx_leave(&sch_mtx); } while ( ret > 0 && !(C)); ret; }); __ret; }); |
| 1242 | |
| 1243 | /* just trace the final value */ |
| 1244 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); |
| 1245 | |
| 1246 | if (!done) |
| 1247 | drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: did not complete or timeout within %ums (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, timeout_ms, status) |
| 1248 | "%s: did not complete or timeout within %ums (status 0x%08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: did not complete or timeout within %ums (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, timeout_ms, status) |
| 1249 | intel_dp->aux.name, timeout_ms, status)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: did not complete or timeout within %ums (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, timeout_ms, status); |
| 1250 | #undef C |
| 1251 | |
| 1252 | return status; |
| 1253 | } |
| 1254 | |
| 1255 | static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 1256 | { |
| 1257 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1258 | |
| 1259 | if (index) |
| 1260 | return 0; |
| 1261 | |
| 1262 | /* |
| 1263 | * The clock divider is based off the hrawclk, and would like to run at |
| 1264 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
| 1265 | */ |
| 1266 | return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000)((((&(dev_priv)->__runtime)->rawclk_freq) + ((2000) / 2)) / (2000)); |
| 1267 | } |
| 1268 | |
| 1269 | static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 1270 | { |
| 1271 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1272 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1273 | u32 freq; |
| 1274 | |
| 1275 | if (index) |
| 1276 | return 0; |
| 1277 | |
| 1278 | /* |
| 1279 | * The clock divider is based off the cdclk or PCH rawclk, and would |
| 1280 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and |
| 1281 | * divide by 2000 and use that |
| 1282 | */ |
| 1283 | if (dig_port->aux_ch == AUX_CH_A) |
| 1284 | freq = dev_priv->cdclk.hw.cdclk; |
| 1285 | else |
| 1286 | freq = RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->rawclk_freq; |
| 1287 | return DIV_ROUND_CLOSEST(freq, 2000)(((freq) + ((2000) / 2)) / (2000)); |
| 1288 | } |
| 1289 | |
| 1290 | static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 1291 | { |
| 1292 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1293 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1294 | |
| 1295 | if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)(((dev_priv)->pch_id) == 0x8c00 || ((dev_priv)->pch_id) == 0x8c80)) { |
| 1296 | /* Workaround for non-ULT HSW */ |
| 1297 | switch (index) { |
| 1298 | case 0: return 63; |
| 1299 | case 1: return 72; |
| 1300 | default: return 0; |
| 1301 | } |
| 1302 | } |
| 1303 | |
| 1304 | return ilk_get_aux_clock_divider(intel_dp, index); |
| 1305 | } |
| 1306 | |
| 1307 | static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 1308 | { |
| 1309 | /* |
| 1310 | * SKL doesn't need us to program the AUX clock divider (Hardware will |
| 1311 | * derive the clock from CDCLK automatically). We still implement the |
| 1312 | * get_aux_clock_divider vfunc to plug-in into the existing code. |
| 1313 | */ |
| 1314 | return index ? 0 : 1; |
| 1315 | } |
| 1316 | |
| 1317 | static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 1318 | int send_bytes, |
| 1319 | u32 aux_clock_divider) |
| 1320 | { |
| 1321 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1322 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 1323 | to_i915(dig_port->base.base.dev); |
| 1324 | u32 precharge, timeout; |
| 1325 | |
| 1326 | if (IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6))) |
| 1327 | precharge = 3; |
| 1328 | else |
| 1329 | precharge = 5; |
| 1330 | |
| 1331 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 1332 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us(1 << 26); |
| 1333 | else |
| 1334 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us(0 << 26); |
| 1335 | |
| 1336 | return DP_AUX_CH_CTL_SEND_BUSY(1 << 31) | |
| 1337 | DP_AUX_CH_CTL_DONE(1 << 30) | |
| 1338 | DP_AUX_CH_CTL_INTERRUPT(1 << 29) | |
| 1339 | DP_AUX_CH_CTL_TIME_OUT_ERROR(1 << 28) | |
| 1340 | timeout | |
| 1341 | DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25) | |
| 1342 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT20) | |
| 1343 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT16) | |
| 1344 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT0); |
| 1345 | } |
| 1346 | |
| 1347 | static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 1348 | int send_bytes, |
| 1349 | u32 unused) |
| 1350 | { |
| 1351 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1352 | struct drm_i915_privateinteldrm_softc *i915 = |
| 1353 | to_i915(dig_port->base.base.dev); |
| 1354 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); |
| 1355 | u32 ret; |
| 1356 | |
| 1357 | ret = DP_AUX_CH_CTL_SEND_BUSY(1 << 31) | |
| 1358 | DP_AUX_CH_CTL_DONE(1 << 30) | |
| 1359 | DP_AUX_CH_CTL_INTERRUPT(1 << 29) | |
| 1360 | DP_AUX_CH_CTL_TIME_OUT_ERROR(1 << 28) | |
| 1361 | DP_AUX_CH_CTL_TIME_OUT_MAX(3 << 26) | |
| 1362 | DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25) | |
| 1363 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT20) | |
| 1364 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32)(((32) - 1) << 5) | |
| 1365 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32)((32) - 1); |
| 1366 | |
| 1367 | if (intel_phy_is_tc(i915, phy) && |
| 1368 | dig_port->tc_mode == TC_PORT_TBT_ALT) |
| 1369 | ret |= DP_AUX_CH_CTL_TBT_IO(1 << 11); |
| 1370 | |
| 1371 | return ret; |
| 1372 | } |
| 1373 | |
| 1374 | static int |
| 1375 | intel_dp_aux_xfer(struct intel_dp *intel_dp, |
| 1376 | const u8 *send, int send_bytes, |
| 1377 | u8 *recv, int recv_size, |
| 1378 | u32 aux_send_ctl_flags) |
| 1379 | { |
| 1380 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1381 | struct drm_i915_privateinteldrm_softc *i915 = |
| 1382 | to_i915(dig_port->base.base.dev); |
| 1383 | struct intel_uncore *uncore = &i915->uncore; |
| 1384 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); |
| 1385 | bool_Bool is_tc_port = intel_phy_is_tc(i915, phy); |
| 1386 | i915_reg_t ch_ctl, ch_data[5]; |
| 1387 | u32 aux_clock_divider; |
| 1388 | enum intel_display_power_domain aux_domain; |
| 1389 | intel_wakeref_t aux_wakeref; |
| 1390 | intel_wakeref_t pps_wakeref; |
| 1391 | int i, ret, recv_bytes; |
| 1392 | int try, clock = 0; |
| 1393 | u32 status; |
| 1394 | bool_Bool vdd; |
| 1395 | |
| 1396 | ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); |
| 1397 | for (i = 0; i < ARRAY_SIZE(ch_data)(sizeof((ch_data)) / sizeof((ch_data)[0])); i++) |
| 1398 | ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); |
| 1399 | |
| 1400 | if (is_tc_port) |
| 1401 | intel_tc_port_lock(dig_port); |
| 1402 | |
| 1403 | aux_domain = intel_aux_power_domain(dig_port); |
| 1404 | |
| 1405 | aux_wakeref = intel_display_power_get(i915, aux_domain); |
| 1406 | pps_wakeref = pps_lock(intel_dp); |
| 1407 | |
| 1408 | /* |
| 1409 | * We will be called with VDD already enabled for dpcd/edid/oui reads. |
| 1410 | * In such cases we want to leave VDD enabled and it's up to upper layers |
| 1411 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off |
| 1412 | * ourselves. |
| 1413 | */ |
| 1414 | vdd = edp_panel_vdd_on(intel_dp); |
| 1415 | |
| 1416 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 1417 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 1418 | * deep sleep states. |
| 1419 | */ |
| 1420 | cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); |
| 1421 | |
| 1422 | intel_dp_check_edp(intel_dp); |
| 1423 | |
| 1424 | /* Try to wait for any previous AUX channel activity */ |
| 1425 | for (try = 0; try < 3; try++) { |
| 1426 | status = intel_uncore_read_notrace(uncore, ch_ctl); |
| 1427 | if ((status & DP_AUX_CH_CTL_SEND_BUSY(1 << 31)) == 0) |
| 1428 | break; |
| 1429 | drm_msleep(1)mdelay(1); |
| 1430 | } |
| 1431 | /* just trace the final value */ |
| 1432 | trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); |
| 1433 | |
| 1434 | if (try == 3) { |
| 1435 | const u32 status = intel_uncore_read(uncore, ch_ctl); |
| 1436 | |
| 1437 | if (status != intel_dp->aux_busy_last_status) { |
| 1438 | drm_WARN(&i915->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "%s: not started (status 0x%08x)\n" , dev_driver_string((&i915->drm)->dev), "", intel_dp ->aux.name, status); __builtin_expect(!!(__ret), 0); }) |
| 1439 | "%s: not started (status 0x%08x)\n",({ int __ret = !!(1); if (__ret) printf("%s %s: " "%s: not started (status 0x%08x)\n" , dev_driver_string((&i915->drm)->dev), "", intel_dp ->aux.name, status); __builtin_expect(!!(__ret), 0); }) |
| 1440 | intel_dp->aux.name, status)({ int __ret = !!(1); if (__ret) printf("%s %s: " "%s: not started (status 0x%08x)\n" , dev_driver_string((&i915->drm)->dev), "", intel_dp ->aux.name, status); __builtin_expect(!!(__ret), 0); }); |
| 1441 | intel_dp->aux_busy_last_status = status; |
| 1442 | } |
| 1443 | |
| 1444 | ret = -EBUSY16; |
| 1445 | goto out; |
| 1446 | } |
| 1447 | |
| 1448 | /* Only 5 data registers! */ |
| 1449 | if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)({ int __ret = !!((send_bytes > 20 || recv_size > 20)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915 ->drm))->dev), "", "drm_WARN_ON(" "send_bytes > 20 || recv_size > 20" ")"); __builtin_expect(!!(__ret), 0); })) { |
| 1450 | ret = -E2BIG7; |
| 1451 | goto out; |
| 1452 | } |
| 1453 | |
| 1454 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
| 1455 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 1456 | send_bytes, |
| 1457 | aux_clock_divider); |
| 1458 | |
| 1459 | send_ctl |= aux_send_ctl_flags; |
| 1460 | |
| 1461 | /* Must try at least 3 times according to DP spec */ |
| 1462 | for (try = 0; try < 5; try++) { |
| 1463 | /* Load the send data into the aux channel data registers */ |
| 1464 | for (i = 0; i < send_bytes; i += 4) |
| 1465 | intel_uncore_write(uncore, |
| 1466 | ch_data[i >> 2], |
| 1467 | intel_dp_pack_aux(send + i, |
| 1468 | send_bytes - i)); |
| 1469 | |
| 1470 | /* Send the command and wait for it to complete */ |
| 1471 | intel_uncore_write(uncore, ch_ctl, send_ctl); |
| 1472 | |
| 1473 | status = intel_dp_aux_wait_done(intel_dp); |
| 1474 | |
| 1475 | /* Clear done status and any errors */ |
| 1476 | intel_uncore_write(uncore, |
| 1477 | ch_ctl, |
| 1478 | status | |
| 1479 | DP_AUX_CH_CTL_DONE(1 << 30) | |
| 1480 | DP_AUX_CH_CTL_TIME_OUT_ERROR(1 << 28) | |
| 1481 | DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25)); |
| 1482 | |
| 1483 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 |
| 1484 | * 400us delay required for errors and timeouts |
| 1485 | * Timeout errors from the HW already meet this |
| 1486 | * requirement so skip to next iteration |
| 1487 | */ |
| 1488 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR(1 << 28)) |
| 1489 | continue; |
| 1490 | |
| 1491 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25)) { |
| 1492 | usleep_range(400, 500); |
| 1493 | continue; |
| 1494 | } |
| 1495 | if (status & DP_AUX_CH_CTL_DONE(1 << 30)) |
| 1496 | goto done; |
| 1497 | } |
| 1498 | } |
| 1499 | |
| 1500 | if ((status & DP_AUX_CH_CTL_DONE(1 << 30)) == 0) { |
| 1501 | drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: not done (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, status) |
| 1502 | intel_dp->aux.name, status)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: not done (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, status); |
| 1503 | ret = -EBUSY16; |
| 1504 | goto out; |
| 1505 | } |
| 1506 | |
| 1507 | done: |
| 1508 | /* Check for timeout or receive error. |
| 1509 | * Timeouts occur when the sink is not connected |
| 1510 | */ |
| 1511 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR(1 << 25)) { |
| 1512 | drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: receive error (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, status) |
| 1513 | intel_dp->aux.name, status)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: receive error (status 0x%08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_dp ->aux.name, status); |
| 1514 | ret = -EIO5; |
| 1515 | goto out; |
| 1516 | } |
| 1517 | |
| 1518 | /* Timeouts occur when the device isn't connected, so they're |
| 1519 | * "normal" -- don't fill the kernel log with these */ |
| 1520 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR(1 << 28)) { |
| 1521 | drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: timeout (status 0x%08x)\n" , intel_dp->aux.name, status) |
| 1522 | intel_dp->aux.name, status)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: timeout (status 0x%08x)\n" , intel_dp->aux.name, status); |
| 1523 | ret = -ETIMEDOUT60; |
| 1524 | goto out; |
| 1525 | } |
| 1526 | |
| 1527 | /* Unload any bytes sent back from the other side */ |
| 1528 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK(0x1f << 20)) >> |
| 1529 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT20); |
| 1530 | |
| 1531 | /* |
| 1532 | * By BSpec: "Message sizes of 0 or >20 are not allowed." |
| 1533 | * We have no idea of what happened so we return -EBUSY so |
| 1534 | * drm layer takes care for the necessary retries. |
| 1535 | */ |
| 1536 | if (recv_bytes == 0 || recv_bytes > 20) { |
| 1537 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: Forbidden recv_bytes = %d on aux transaction\n" , intel_dp->aux.name, recv_bytes) |
| 1538 | "%s: Forbidden recv_bytes = %d on aux transaction\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: Forbidden recv_bytes = %d on aux transaction\n" , intel_dp->aux.name, recv_bytes) |
| 1539 | intel_dp->aux.name, recv_bytes)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: Forbidden recv_bytes = %d on aux transaction\n" , intel_dp->aux.name, recv_bytes); |
| 1540 | ret = -EBUSY16; |
| 1541 | goto out; |
| 1542 | } |
| 1543 | |
| 1544 | if (recv_bytes > recv_size) |
| 1545 | recv_bytes = recv_size; |
| 1546 | |
| 1547 | for (i = 0; i < recv_bytes; i += 4) |
| 1548 | intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), |
| 1549 | recv + i, recv_bytes - i); |
| 1550 | |
| 1551 | ret = recv_bytes; |
| 1552 | out: |
| 1553 | cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 1554 | |
| 1555 | if (vdd) |
| 1556 | edp_panel_vdd_off(intel_dp, false0); |
| 1557 | |
| 1558 | pps_unlock(intel_dp, pps_wakeref); |
| 1559 | intel_display_power_put_async(i915, aux_domain, aux_wakeref); |
| 1560 | |
| 1561 | if (is_tc_port) |
| 1562 | intel_tc_port_unlock(dig_port); |
| 1563 | |
| 1564 | return ret; |
| 1565 | } |
| 1566 | |
| 1567 | #define BARE_ADDRESS_SIZE3 3 |
| 1568 | #define HEADER_SIZE(3 + 1) (BARE_ADDRESS_SIZE3 + 1) |
| 1569 | |
| 1570 | static void |
| 1571 | intel_dp_aux_header(u8 txbuf[HEADER_SIZE(3 + 1)], |
| 1572 | const struct drm_dp_aux_msg *msg) |
| 1573 | { |
| 1574 | txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); |
| 1575 | txbuf[1] = (msg->address >> 8) & 0xff; |
| 1576 | txbuf[2] = msg->address & 0xff; |
| 1577 | txbuf[3] = msg->size - 1; |
| 1578 | } |
| 1579 | |
| 1580 | static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) |
| 1581 | { |
| 1582 | /* |
| 1583 | * If we're trying to send the HDCP Aksv, we need to set a the Aksv |
| 1584 | * select bit to inform the hardware to send the Aksv after our header |
| 1585 | * since we can't access that data from software. |
| 1586 | */ |
| 1587 | if ((msg->request & ~DP_AUX_I2C_MOT0x4) == DP_AUX_NATIVE_WRITE0x8 && |
| 1588 | msg->address == DP_AUX_HDCP_AKSV0x68007) |
| 1589 | return DP_AUX_CH_CTL_AUX_AKSV_SELECT(1 << 15); |
| 1590 | |
| 1591 | return 0; |
| 1592 | } |
| 1593 | |
| 1594 | static ssize_t |
| 1595 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
| 1596 | { |
| 1597 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux)({ const __typeof( ((struct intel_dp *)0)->aux ) *__mptr = (aux); (struct intel_dp *)( (char *)__mptr - __builtin_offsetof (struct intel_dp, aux) );}); |
| 1598 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 1599 | u8 txbuf[20], rxbuf[20]; |
| 1600 | size_t txsize, rxsize; |
| 1601 | u32 flags = intel_dp_aux_xfer_flags(msg); |
| 1602 | int ret; |
| 1603 | |
| 1604 | intel_dp_aux_header(txbuf, msg); |
| 1605 | |
| 1606 | switch (msg->request & ~DP_AUX_I2C_MOT0x4) { |
| 1607 | case DP_AUX_NATIVE_WRITE0x8: |
| 1608 | case DP_AUX_I2C_WRITE0x0: |
| 1609 | case DP_AUX_I2C_WRITE_STATUS_UPDATE0x2: |
| 1610 | txsize = msg->size ? HEADER_SIZE(3 + 1) + msg->size : BARE_ADDRESS_SIZE3; |
| 1611 | rxsize = 2; /* 0 or 1 data bytes */ |
| 1612 | |
| 1613 | if (drm_WARN_ON(&i915->drm, txsize > 20)({ int __ret = !!((txsize > 20)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "txsize > 20" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1614 | return -E2BIG7; |
| 1615 | |
| 1616 | drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size)({ int __ret = !!((!msg->buffer != !msg->size)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&i915->drm ))->dev), "", "drm_WARN_ON(" "!msg->buffer != !msg->size" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1617 | |
| 1618 | if (msg->buffer) |
| 1619 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size)__builtin_memcpy((txbuf + (3 + 1)), (msg->buffer), (msg-> size)); |
| 1620 | |
| 1621 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
| 1622 | rxbuf, rxsize, flags); |
| 1623 | if (ret > 0) { |
| 1624 | msg->reply = rxbuf[0] >> 4; |
| 1625 | |
| 1626 | if (ret > 1) { |
| 1627 | /* Number of bytes written in a short write. */ |
| 1628 | ret = clamp_t(int, rxbuf[1], 0, msg->size)({ int __min_a = (({ int __max_a = (rxbuf[1]); int __max_b = ( 0); __max_a > __max_b ? __max_a : __max_b; })); int __min_b = (msg->size); __min_a < __min_b ? __min_a : __min_b; } ); |
| 1629 | } else { |
| 1630 | /* Return payload size. */ |
| 1631 | ret = msg->size; |
| 1632 | } |
| 1633 | } |
| 1634 | break; |
| 1635 | |
| 1636 | case DP_AUX_NATIVE_READ0x9: |
| 1637 | case DP_AUX_I2C_READ0x1: |
| 1638 | txsize = msg->size ? HEADER_SIZE(3 + 1) : BARE_ADDRESS_SIZE3; |
| 1639 | rxsize = msg->size + 1; |
| 1640 | |
| 1641 | if (drm_WARN_ON(&i915->drm, rxsize > 20)({ int __ret = !!((rxsize > 20)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "rxsize > 20" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1642 | return -E2BIG7; |
| 1643 | |
| 1644 | ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, |
| 1645 | rxbuf, rxsize, flags); |
| 1646 | if (ret > 0) { |
| 1647 | msg->reply = rxbuf[0] >> 4; |
| 1648 | /* |
| 1649 | * Assume happy day, and copy the data. The caller is |
| 1650 | * expected to check msg->reply before touching it. |
| 1651 | * |
| 1652 | * Return payload size. |
| 1653 | */ |
| 1654 | ret--; |
| 1655 | memcpy(msg->buffer, rxbuf + 1, ret)__builtin_memcpy((msg->buffer), (rxbuf + 1), (ret)); |
| 1656 | } |
| 1657 | break; |
| 1658 | |
| 1659 | default: |
| 1660 | ret = -EINVAL22; |
| 1661 | break; |
| 1662 | } |
| 1663 | |
| 1664 | return ret; |
| 1665 | } |
| 1666 | |
| 1667 | |
| 1668 | static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) |
| 1669 | { |
| 1670 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1671 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1672 | enum aux_ch aux_ch = dig_port->aux_ch; |
| 1673 | |
| 1674 | switch (aux_ch) { |
| 1675 | case AUX_CH_B: |
| 1676 | case AUX_CH_C: |
| 1677 | case AUX_CH_D: |
| 1678 | return DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64010)) + (aux_ch) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64110)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010 ))))) }); |
| 1679 | default: |
| 1680 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 1681 | return DP_AUX_CH_CTL(AUX_CH_B)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64010)) + (AUX_CH_B) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64110)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010 ))))) }); |
| 1682 | } |
| 1683 | } |
| 1684 | |
| 1685 | static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) |
| 1686 | { |
| 1687 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1688 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1689 | enum aux_ch aux_ch = dig_port->aux_ch; |
| 1690 | |
| 1691 | switch (aux_ch) { |
| 1692 | case AUX_CH_B: |
| 1693 | case AUX_CH_C: |
| 1694 | case AUX_CH_D: |
| 1695 | return DP_AUX_CH_DATA(aux_ch, index)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64014)) + (aux_ch) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64114)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014 )))) + (index) * 4) }); |
| 1696 | default: |
| 1697 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 1698 | return DP_AUX_CH_DATA(AUX_CH_B, index)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64014)) + (AUX_CH_B) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64114)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014 )))) + (index) * 4) }); |
| 1699 | } |
| 1700 | } |
| 1701 | |
| 1702 | static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) |
| 1703 | { |
| 1704 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1705 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1706 | enum aux_ch aux_ch = dig_port->aux_ch; |
| 1707 | |
| 1708 | switch (aux_ch) { |
| 1709 | case AUX_CH_A: |
| 1710 | return DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64010)) + (aux_ch) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64110)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010 ))))) }); |
| 1711 | case AUX_CH_B: |
| 1712 | case AUX_CH_C: |
| 1713 | case AUX_CH_D: |
| 1714 | return PCH_DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = (((0xe4110) + ((aux_ch) - AUX_CH_B ) * ((0xe4210) - (0xe4110)))) }); |
| 1715 | default: |
| 1716 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 1717 | return DP_AUX_CH_CTL(AUX_CH_A)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64010)) + (AUX_CH_A) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64110)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010 ))))) }); |
| 1718 | } |
| 1719 | } |
| 1720 | |
| 1721 | static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) |
| 1722 | { |
| 1723 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1724 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1725 | enum aux_ch aux_ch = dig_port->aux_ch; |
| 1726 | |
| 1727 | switch (aux_ch) { |
| 1728 | case AUX_CH_A: |
| 1729 | return DP_AUX_CH_DATA(aux_ch, index)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64014)) + (aux_ch) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64114)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014 )))) + (index) * 4) }); |
| 1730 | case AUX_CH_B: |
| 1731 | case AUX_CH_C: |
| 1732 | case AUX_CH_D: |
| 1733 | return PCH_DP_AUX_CH_DATA(aux_ch, index)((const i915_reg_t){ .reg = (((0xe4114) + ((aux_ch) - AUX_CH_B ) * ((0xe4214) - (0xe4114))) + (index) * 4) }); |
| 1734 | default: |
| 1735 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 1736 | return DP_AUX_CH_DATA(AUX_CH_A, index)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64014)) + (AUX_CH_A) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64114)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014 )))) + (index) * 4) }); |
| 1737 | } |
| 1738 | } |
| 1739 | |
| 1740 | static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) |
| 1741 | { |
| 1742 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1743 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1744 | enum aux_ch aux_ch = dig_port->aux_ch; |
| 1745 | |
| 1746 | switch (aux_ch) { |
| 1747 | case AUX_CH_A: |
| 1748 | case AUX_CH_B: |
| 1749 | case AUX_CH_C: |
| 1750 | case AUX_CH_D: |
| 1751 | case AUX_CH_E: |
| 1752 | case AUX_CH_F: |
| 1753 | case AUX_CH_G: |
| 1754 | return DP_AUX_CH_CTL(aux_ch)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64010)) + (aux_ch) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64110)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010 ))))) }); |
| 1755 | default: |
| 1756 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 1757 | return DP_AUX_CH_CTL(AUX_CH_A)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64010)) + (AUX_CH_A) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64110)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64010 ))))) }); |
| 1758 | } |
| 1759 | } |
| 1760 | |
| 1761 | static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) |
| 1762 | { |
| 1763 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1764 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1765 | enum aux_ch aux_ch = dig_port->aux_ch; |
| 1766 | |
| 1767 | switch (aux_ch) { |
| 1768 | case AUX_CH_A: |
| 1769 | case AUX_CH_B: |
| 1770 | case AUX_CH_C: |
| 1771 | case AUX_CH_D: |
| 1772 | case AUX_CH_E: |
| 1773 | case AUX_CH_F: |
| 1774 | case AUX_CH_G: |
| 1775 | return DP_AUX_CH_DATA(aux_ch, index)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64014)) + (aux_ch) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64114)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014 )))) + (index) * 4) }); |
| 1776 | default: |
| 1777 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 1778 | return DP_AUX_CH_DATA(AUX_CH_A, index)((const i915_reg_t){ .reg = ((((((&(dev_priv)->__info) ->display_mmio_offset) + 0x64014)) + (AUX_CH_A) * (((((& (dev_priv)->__info)->display_mmio_offset) + 0x64114)) - ((((&(dev_priv)->__info)->display_mmio_offset) + 0x64014 )))) + (index) * 4) }); |
| 1779 | } |
| 1780 | } |
| 1781 | |
| 1782 | static void |
| 1783 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
| 1784 | { |
| 1785 | if (cpu_latency_qos_request_active(&intel_dp->pm_qos)0) |
| 1786 | cpu_latency_qos_remove_request(&intel_dp->pm_qos); |
| 1787 | |
| 1788 | kfree(intel_dp->aux.name); |
| 1789 | } |
| 1790 | |
| 1791 | static void |
| 1792 | intel_dp_aux_init(struct intel_dp *intel_dp) |
| 1793 | { |
| 1794 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1795 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1796 | struct intel_encoder *encoder = &dig_port->base; |
| 1797 | |
| 1798 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) { |
| 1799 | intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; |
| 1800 | intel_dp->aux_ch_data_reg = skl_aux_data_reg; |
| 1801 | } else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 1802 | intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; |
| 1803 | intel_dp->aux_ch_data_reg = ilk_aux_data_reg; |
| 1804 | } else { |
| 1805 | intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; |
| 1806 | intel_dp->aux_ch_data_reg = g4x_aux_data_reg; |
| 1807 | } |
| 1808 | |
| 1809 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 1810 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
| 1811 | else if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 1812 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 1813 | else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) |
| 1814 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 1815 | else |
| 1816 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
| 1817 | |
| 1818 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 1819 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
| 1820 | else |
| 1821 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
| 1822 | |
| 1823 | drm_dp_aux_init(&intel_dp->aux); |
| 1824 | |
| 1825 | /* Failure to allocate our preferred name is not critical */ |
| 1826 | intel_dp->aux.name = kasprintf(GFP_KERNEL(0x0001 | 0x0004), "AUX %c/port %c", |
| 1827 | aux_ch_name(dig_port->aux_ch)((dig_port->aux_ch) + 'A'), |
| 1828 | port_name(encoder->port)((encoder->port) + 'A')); |
| 1829 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
| 1830 | cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); |
| 1831 | } |
| 1832 | |
| 1833 | bool_Bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
| 1834 | { |
| 1835 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
| 1836 | |
| 1837 | return max_rate >= 540000; |
| 1838 | } |
| 1839 | |
| 1840 | bool_Bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) |
| 1841 | { |
| 1842 | int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; |
| 1843 | |
| 1844 | return max_rate >= 810000; |
| 1845 | } |
| 1846 | |
| 1847 | static void |
| 1848 | intel_dp_set_clock(struct intel_encoder *encoder, |
| 1849 | struct intel_crtc_state *pipe_config) |
| 1850 | { |
| 1851 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 1852 | const struct dp_link_dpll *divisor = NULL((void *)0); |
| 1853 | int i, count = 0; |
| 1854 | |
| 1855 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
| 1856 | divisor = g4x_dpll; |
| 1857 | count = ARRAY_SIZE(g4x_dpll)(sizeof((g4x_dpll)) / sizeof((g4x_dpll)[0])); |
| 1858 | } else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 1859 | divisor = pch_dpll; |
| 1860 | count = ARRAY_SIZE(pch_dpll)(sizeof((pch_dpll)) / sizeof((pch_dpll)[0])); |
| 1861 | } else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 1862 | divisor = chv_dpll; |
| 1863 | count = ARRAY_SIZE(chv_dpll)(sizeof((chv_dpll)) / sizeof((chv_dpll)[0])); |
| 1864 | } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)) { |
| 1865 | divisor = vlv_dpll; |
| 1866 | count = ARRAY_SIZE(vlv_dpll)(sizeof((vlv_dpll)) / sizeof((vlv_dpll)[0])); |
| 1867 | } |
| 1868 | |
| 1869 | if (divisor && count) { |
| 1870 | for (i = 0; i < count; i++) { |
| 1871 | if (pipe_config->port_clock == divisor[i].clock) { |
| 1872 | pipe_config->dpll = divisor[i].dpll; |
| 1873 | pipe_config->clock_set = true1; |
| 1874 | break; |
| 1875 | } |
| 1876 | } |
| 1877 | } |
| 1878 | } |
| 1879 | |
| 1880 | static void snprintf_int_array(char *str, size_t len, |
| 1881 | const int *array, int nelem) |
| 1882 | { |
| 1883 | int i; |
| 1884 | |
| 1885 | str[0] = '\0'; |
| 1886 | |
| 1887 | for (i = 0; i < nelem; i++) { |
| 1888 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
| 1889 | if (r >= len) |
| 1890 | return; |
| 1891 | str += r; |
| 1892 | len -= r; |
| 1893 | } |
| 1894 | } |
| 1895 | |
| 1896 | static void intel_dp_print_rates(struct intel_dp *intel_dp) |
| 1897 | { |
| 1898 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 1899 | char str[128]; /* FIXME: too big for stack? */ |
| 1900 | |
| 1901 | if (!drm_debug_enabled(DRM_UT_KMS)) |
| 1902 | return; |
| 1903 | |
| 1904 | snprintf_int_array(str, sizeof(str), |
| 1905 | intel_dp->source_rates, intel_dp->num_source_rates); |
| 1906 | drm_dbg_kms(&i915->drm, "source rates: %s\n", str)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "source rates: %s\n" , str); |
| 1907 | |
| 1908 | snprintf_int_array(str, sizeof(str), |
| 1909 | intel_dp->sink_rates, intel_dp->num_sink_rates); |
| 1910 | drm_dbg_kms(&i915->drm, "sink rates: %s\n", str)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "sink rates: %s\n" , str); |
| 1911 | |
| 1912 | snprintf_int_array(str, sizeof(str), |
| 1913 | intel_dp->common_rates, intel_dp->num_common_rates); |
| 1914 | drm_dbg_kms(&i915->drm, "common rates: %s\n", str)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "common rates: %s\n" , str); |
| 1915 | } |
| 1916 | |
| 1917 | int |
| 1918 | intel_dp_max_link_rate(struct intel_dp *intel_dp) |
| 1919 | { |
| 1920 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 1921 | int len; |
| 1922 | |
| 1923 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
| 1924 | if (drm_WARN_ON(&i915->drm, len <= 0)({ int __ret = !!((len <= 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "len <= 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1925 | return 162000; |
| 1926 | |
| 1927 | return intel_dp->common_rates[len - 1]; |
| 1928 | } |
| 1929 | |
| 1930 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
| 1931 | { |
| 1932 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 1933 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
| 1934 | intel_dp->num_sink_rates, rate); |
| 1935 | |
| 1936 | if (drm_WARN_ON(&i915->drm, i < 0)({ int __ret = !!((i < 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "i < 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1937 | i = 0; |
| 1938 | |
| 1939 | return i; |
| 1940 | } |
| 1941 | |
| 1942 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 1943 | u8 *link_bw, u8 *rate_select) |
| 1944 | { |
| 1945 | /* eDP 1.4 rate select method. */ |
| 1946 | if (intel_dp->use_rate_select) { |
| 1947 | *link_bw = 0; |
| 1948 | *rate_select = |
| 1949 | intel_dp_rate_select(intel_dp, port_clock); |
| 1950 | } else { |
| 1951 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); |
| 1952 | *rate_select = 0; |
| 1953 | } |
| 1954 | } |
| 1955 | |
| 1956 | static bool_Bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, |
| 1957 | const struct intel_crtc_state *pipe_config) |
| 1958 | { |
| 1959 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 1960 | |
| 1961 | /* On TGL, FEC is supported on all Pipes */ |
| 1962 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 1963 | return true1; |
| 1964 | |
| 1965 | if (IS_GEN(dev_priv, 11)(0 + (&(dev_priv)->__info)->gen == (11)) && pipe_config->cpu_transcoder != TRANSCODER_A) |
| 1966 | return true1; |
| 1967 | |
| 1968 | return false0; |
| 1969 | } |
| 1970 | |
| 1971 | static bool_Bool intel_dp_supports_fec(struct intel_dp *intel_dp, |
| 1972 | const struct intel_crtc_state *pipe_config) |
| 1973 | { |
| 1974 | return intel_dp_source_supports_fec(intel_dp, pipe_config) && |
| 1975 | drm_dp_sink_supports_fec(intel_dp->fec_capable); |
| 1976 | } |
| 1977 | |
| 1978 | static bool_Bool intel_dp_supports_dsc(struct intel_dp *intel_dp, |
| 1979 | const struct intel_crtc_state *crtc_state) |
| 1980 | { |
| 1981 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 1982 | |
| 1983 | if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable) |
| 1984 | return false0; |
| 1985 | |
| 1986 | return intel_dsc_source_support(encoder, crtc_state) && |
| 1987 | drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); |
| 1988 | } |
| 1989 | |
| 1990 | static bool_Bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp, |
| 1991 | const struct intel_crtc_state *crtc_state) |
| 1992 | { |
| 1993 | return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
| 1994 | (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && |
| 1995 | intel_dp->dfp.ycbcr_444_to_420); |
| 1996 | } |
| 1997 | |
| 1998 | static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp, |
| 1999 | const struct intel_crtc_state *crtc_state, int bpc) |
| 2000 | { |
| 2001 | int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; |
| 2002 | |
| 2003 | if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) |
| 2004 | clock /= 2; |
| 2005 | |
| 2006 | return clock; |
| 2007 | } |
| 2008 | |
| 2009 | static bool_Bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, |
| 2010 | const struct intel_crtc_state *crtc_state, int bpc) |
| 2011 | { |
| 2012 | int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); |
| 2013 | |
| 2014 | if (intel_dp->dfp.min_tmds_clock && |
| 2015 | tmds_clock < intel_dp->dfp.min_tmds_clock) |
| 2016 | return false0; |
| 2017 | |
| 2018 | if (intel_dp->dfp.max_tmds_clock && |
| 2019 | tmds_clock > intel_dp->dfp.max_tmds_clock) |
| 2020 | return false0; |
| 2021 | |
| 2022 | return true1; |
| 2023 | } |
| 2024 | |
| 2025 | static bool_Bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp, |
| 2026 | const struct intel_crtc_state *crtc_state, |
| 2027 | int bpc) |
| 2028 | { |
| 2029 | |
| 2030 | return intel_hdmi_deep_color_possible(crtc_state, bpc, |
| 2031 | intel_dp->has_hdmi_sink, |
| 2032 | intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) && |
| 2033 | intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); |
| 2034 | } |
| 2035 | |
| 2036 | static int intel_dp_max_bpp(struct intel_dp *intel_dp, |
| 2037 | const struct intel_crtc_state *crtc_state) |
| 2038 | { |
| 2039 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 2040 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 2041 | int bpp, bpc; |
| 2042 | |
| 2043 | bpc = crtc_state->pipe_bpp / 3; |
| 2044 | |
| 2045 | if (intel_dp->dfp.max_bpc) |
| 2046 | bpc = min_t(int, bpc, intel_dp->dfp.max_bpc)({ int __min_a = (bpc); int __min_b = (intel_dp->dfp.max_bpc ); __min_a < __min_b ? __min_a : __min_b; }); |
| 2047 | |
| 2048 | if (intel_dp->dfp.min_tmds_clock) { |
| 2049 | for (; bpc >= 10; bpc -= 2) { |
| 2050 | if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc)) |
| 2051 | break; |
| 2052 | } |
| 2053 | } |
| 2054 | |
| 2055 | bpp = bpc * 3; |
| 2056 | if (intel_dp_is_edp(intel_dp)) { |
| 2057 | /* Get bpp from vbt only for panels that dont have bpp in edid */ |
| 2058 | if (intel_connector->base.display_info.bpc == 0 && |
| 2059 | dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { |
| 2060 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "clamping bpp for eDP panel to BIOS-provided %i\n" , dev_priv->vbt.edp.bpp) |
| 2061 | "clamping bpp for eDP panel to BIOS-provided %i\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "clamping bpp for eDP panel to BIOS-provided %i\n" , dev_priv->vbt.edp.bpp) |
| 2062 | dev_priv->vbt.edp.bpp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "clamping bpp for eDP panel to BIOS-provided %i\n" , dev_priv->vbt.edp.bpp); |
| 2063 | bpp = dev_priv->vbt.edp.bpp; |
| 2064 | } |
| 2065 | } |
| 2066 | |
| 2067 | return bpp; |
| 2068 | } |
| 2069 | |
| 2070 | /* Adjust link config limits based on compliance test requests. */ |
| 2071 | void |
| 2072 | intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, |
| 2073 | struct intel_crtc_state *pipe_config, |
| 2074 | struct link_config_limits *limits) |
| 2075 | { |
| 2076 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 2077 | |
| 2078 | /* For DP Compliance we override the computed bpp for the pipe */ |
| 2079 | if (intel_dp->compliance.test_data.bpc != 0) { |
| 2080 | int bpp = 3 * intel_dp->compliance.test_data.bpc; |
| 2081 | |
| 2082 | limits->min_bpp = limits->max_bpp = bpp; |
| 2083 | pipe_config->dither_force_disable = bpp == 6 * 3; |
| 2084 | |
| 2085 | drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Setting pipe_bpp to %d\n" , bpp); |
| 2086 | } |
| 2087 | |
| 2088 | /* Use values requested by Compliance Test Request */ |
| 2089 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING(1 << 0)) { |
| 2090 | int index; |
| 2091 | |
| 2092 | /* Validate the compliance test data since max values |
| 2093 | * might have changed due to link train fallback. |
| 2094 | */ |
| 2095 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, |
| 2096 | intel_dp->compliance.test_lane_count)) { |
| 2097 | index = intel_dp_rate_index(intel_dp->common_rates, |
| 2098 | intel_dp->num_common_rates, |
| 2099 | intel_dp->compliance.test_link_rate); |
| 2100 | if (index >= 0) |
| 2101 | limits->min_clock = limits->max_clock = index; |
| 2102 | limits->min_lane_count = limits->max_lane_count = |
| 2103 | intel_dp->compliance.test_lane_count; |
| 2104 | } |
| 2105 | } |
| 2106 | } |
| 2107 | |
| 2108 | static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) |
| 2109 | { |
| 2110 | /* |
| 2111 | * bpp value was assumed to RGB format. And YCbCr 4:2:0 output |
| 2112 | * format of the number of bytes per pixel will be half the number |
| 2113 | * of bytes of RGB pixel. |
| 2114 | */ |
| 2115 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
| 2116 | bpp /= 2; |
| 2117 | |
| 2118 | return bpp; |
| 2119 | } |
| 2120 | |
| 2121 | /* Optimize link config in order: max bpp, min clock, min lanes */ |
| 2122 | static int |
| 2123 | intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, |
| 2124 | struct intel_crtc_state *pipe_config, |
| 2125 | const struct link_config_limits *limits) |
| 2126 | { |
| 2127 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
| 2128 | int bpp, clock, lane_count; |
| 2129 | int mode_rate, link_clock, link_avail; |
| 2130 | |
| 2131 | for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { |
| 2132 | int output_bpp = intel_dp_output_bpp(pipe_config, bpp); |
| 2133 | |
| 2134 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 2135 | output_bpp); |
| 2136 | |
| 2137 | for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { |
| 2138 | for (lane_count = limits->min_lane_count; |
| 2139 | lane_count <= limits->max_lane_count; |
| 2140 | lane_count <<= 1) { |
| 2141 | link_clock = intel_dp->common_rates[clock]; |
| 2142 | link_avail = intel_dp_max_data_rate(link_clock, |
| 2143 | lane_count); |
| 2144 | |
| 2145 | if (mode_rate <= link_avail) { |
| 2146 | pipe_config->lane_count = lane_count; |
| 2147 | pipe_config->pipe_bpp = bpp; |
| 2148 | pipe_config->port_clock = link_clock; |
| 2149 | |
| 2150 | return 0; |
| 2151 | } |
| 2152 | } |
| 2153 | } |
| 2154 | } |
| 2155 | |
| 2156 | return -EINVAL22; |
| 2157 | } |
| 2158 | |
| 2159 | static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) |
| 2160 | { |
| 2161 | int i, num_bpc; |
| 2162 | u8 dsc_bpc[3] = {0}; |
| 2163 | |
| 2164 | num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, |
| 2165 | dsc_bpc); |
| 2166 | for (i = 0; i < num_bpc; i++) { |
| 2167 | if (dsc_max_bpc >= dsc_bpc[i]) |
| 2168 | return dsc_bpc[i] * 3; |
| 2169 | } |
| 2170 | |
| 2171 | return 0; |
| 2172 | } |
| 2173 | |
| 2174 | #define DSC_SUPPORTED_VERSION_MIN1 1 |
| 2175 | |
| 2176 | static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, |
| 2177 | struct intel_crtc_state *crtc_state) |
| 2178 | { |
| 2179 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
| 2180 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2181 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; |
| 2182 | u8 line_buf_depth; |
| 2183 | int ret; |
| 2184 | |
| 2185 | ret = intel_dsc_compute_params(encoder, crtc_state); |
| 2186 | if (ret) |
| 2187 | return ret; |
| 2188 | |
| 2189 | /* |
| 2190 | * Slice Height of 8 works for all currently available panels. So start |
| 2191 | * with that if pic_height is an integral multiple of 8. Eventually add |
| 2192 | * logic to try multiple slice heights. |
| 2193 | */ |
| 2194 | if (vdsc_cfg->pic_height % 8 == 0) |
| 2195 | vdsc_cfg->slice_height = 8; |
| 2196 | else if (vdsc_cfg->pic_height % 4 == 0) |
| 2197 | vdsc_cfg->slice_height = 4; |
| 2198 | else |
| 2199 | vdsc_cfg->slice_height = 2; |
| 2200 | |
| 2201 | vdsc_cfg->dsc_version_major = |
| 2202 | (intel_dp->dsc_dpcd[DP_DSC_REV0x061 - DP_DSC_SUPPORT0x060] & |
| 2203 | DP_DSC_MAJOR_MASK(0xf << 0)) >> DP_DSC_MAJOR_SHIFT0; |
| 2204 | vdsc_cfg->dsc_version_minor = |
| 2205 | min(DSC_SUPPORTED_VERSION_MIN,(((1)<((intel_dp->dsc_dpcd[0x061 - 0x060] & (0xf << 4)) >> 4))?(1):((intel_dp->dsc_dpcd[0x061 - 0x060] & (0xf << 4)) >> 4)) |
| 2206 | (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &(((1)<((intel_dp->dsc_dpcd[0x061 - 0x060] & (0xf << 4)) >> 4))?(1):((intel_dp->dsc_dpcd[0x061 - 0x060] & (0xf << 4)) >> 4)) |
| 2207 | DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT)(((1)<((intel_dp->dsc_dpcd[0x061 - 0x060] & (0xf << 4)) >> 4))?(1):((intel_dp->dsc_dpcd[0x061 - 0x060] & (0xf << 4)) >> 4)); |
| 2208 | |
| 2209 | vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP0x069 - DP_DSC_SUPPORT0x060] & |
| 2210 | DP_DSC_RGB(1 << 0); |
| 2211 | |
| 2212 | line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); |
| 2213 | if (!line_buf_depth) { |
| 2214 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DSC Sink Line Buffer Depth invalid\n" ) |
| 2215 | "DSC Sink Line Buffer Depth invalid\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DSC Sink Line Buffer Depth invalid\n" ); |
| 2216 | return -EINVAL22; |
| 2217 | } |
| 2218 | |
| 2219 | if (vdsc_cfg->dsc_version_minor == 2) |
| 2220 | vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS16) ? |
| 2221 | DSC_1_2_MAX_LINEBUF_DEPTH_VAL0 : line_buf_depth; |
| 2222 | else |
| 2223 | vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS13) ? |
| 2224 | DSC_1_1_MAX_LINEBUF_DEPTH_BITS13 : line_buf_depth; |
| 2225 | |
| 2226 | vdsc_cfg->block_pred_enable = |
| 2227 | intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT0x066 - DP_DSC_SUPPORT0x060] & |
| 2228 | DP_DSC_BLK_PREDICTION_IS_SUPPORTED(1 << 0); |
| 2229 | |
| 2230 | return drm_dsc_compute_rc_parameters(vdsc_cfg); |
| 2231 | } |
| 2232 | |
| 2233 | static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
| 2234 | struct intel_crtc_state *pipe_config, |
| 2235 | struct drm_connector_state *conn_state, |
| 2236 | struct link_config_limits *limits) |
| 2237 | { |
| 2238 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 2239 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 2240 | const struct drm_display_mode *adjusted_mode = |
| 2241 | &pipe_config->hw.adjusted_mode; |
| 2242 | u8 dsc_max_bpc; |
| 2243 | int pipe_bpp; |
| 2244 | int ret; |
| 2245 | |
| 2246 | pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && |
| 2247 | intel_dp_supports_fec(intel_dp, pipe_config); |
| 2248 | |
| 2249 | if (!intel_dp_supports_dsc(intel_dp, pipe_config)) |
| 2250 | return -EINVAL22; |
| 2251 | |
| 2252 | /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ |
| 2253 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 2254 | dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc)({ u8 __min_a = (12); u8 __min_b = (conn_state->max_requested_bpc ); __min_a < __min_b ? __min_a : __min_b; }); |
| 2255 | else |
| 2256 | dsc_max_bpc = min_t(u8, 10,({ u8 __min_a = (10); u8 __min_b = (conn_state->max_requested_bpc ); __min_a < __min_b ? __min_a : __min_b; }) |
| 2257 | conn_state->max_requested_bpc)({ u8 __min_a = (10); u8 __min_b = (conn_state->max_requested_bpc ); __min_a < __min_b ? __min_a : __min_b; }); |
| 2258 | |
| 2259 | pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); |
| 2260 | |
| 2261 | /* Min Input BPC for ICL+ is 8 */ |
| 2262 | if (pipe_bpp < 8 * 3) { |
| 2263 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No DSC support for less than 8bpc\n" ) |
| 2264 | "No DSC support for less than 8bpc\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No DSC support for less than 8bpc\n" ); |
| 2265 | return -EINVAL22; |
| 2266 | } |
| 2267 | |
| 2268 | /* |
| 2269 | * For now enable DSC for max bpp, max link rate, max lane count. |
| 2270 | * Optimize this later for the minimum possible link rate/lane count |
| 2271 | * with DSC enabled for the requested mode. |
| 2272 | */ |
| 2273 | pipe_config->pipe_bpp = pipe_bpp; |
| 2274 | pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; |
| 2275 | pipe_config->lane_count = limits->max_lane_count; |
| 2276 | |
| 2277 | if (intel_dp_is_edp(intel_dp)) { |
| 2278 | pipe_config->dsc.compressed_bpp = |
| 2279 | min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,({ u16 __min_a = (drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd ) >> 4); u16 __min_b = (pipe_config->pipe_bpp); __min_a < __min_b ? __min_a : __min_b; }) |
| 2280 | pipe_config->pipe_bpp)({ u16 __min_a = (drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd ) >> 4); u16 __min_b = (pipe_config->pipe_bpp); __min_a < __min_b ? __min_a : __min_b; }); |
| 2281 | pipe_config->dsc.slice_count = |
| 2282 | drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, |
| 2283 | true1); |
| 2284 | } else { |
| 2285 | u16 dsc_max_output_bpp; |
| 2286 | u8 dsc_dp_slice_count; |
| 2287 | |
| 2288 | dsc_max_output_bpp = |
| 2289 | intel_dp_dsc_get_output_bpp(dev_priv, |
| 2290 | pipe_config->port_clock, |
| 2291 | pipe_config->lane_count, |
| 2292 | adjusted_mode->crtc_clock, |
| 2293 | adjusted_mode->crtc_hdisplay); |
| 2294 | dsc_dp_slice_count = |
| 2295 | intel_dp_dsc_get_slice_count(intel_dp, |
| 2296 | adjusted_mode->crtc_clock, |
| 2297 | adjusted_mode->crtc_hdisplay); |
| 2298 | if (!dsc_max_output_bpp || !dsc_dp_slice_count) { |
| 2299 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Compressed BPP/Slice Count not supported\n" ) |
| 2300 | "Compressed BPP/Slice Count not supported\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Compressed BPP/Slice Count not supported\n" ); |
| 2301 | return -EINVAL22; |
| 2302 | } |
| 2303 | pipe_config->dsc.compressed_bpp = min_t(u16,({ u16 __min_a = (dsc_max_output_bpp >> 4); u16 __min_b = (pipe_config->pipe_bpp); __min_a < __min_b ? __min_a : __min_b; }) |
| 2304 | dsc_max_output_bpp >> 4,({ u16 __min_a = (dsc_max_output_bpp >> 4); u16 __min_b = (pipe_config->pipe_bpp); __min_a < __min_b ? __min_a : __min_b; }) |
| 2305 | pipe_config->pipe_bpp)({ u16 __min_a = (dsc_max_output_bpp >> 4); u16 __min_b = (pipe_config->pipe_bpp); __min_a < __min_b ? __min_a : __min_b; }); |
| 2306 | pipe_config->dsc.slice_count = dsc_dp_slice_count; |
| 2307 | } |
| 2308 | /* |
| 2309 | * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate |
| 2310 | * is greater than the maximum Cdclock and if slice count is even |
| 2311 | * then we need to use 2 VDSC instances. |
| 2312 | */ |
| 2313 | if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { |
| 2314 | if (pipe_config->dsc.slice_count > 1) { |
| 2315 | pipe_config->dsc.dsc_split = true1; |
| 2316 | } else { |
| 2317 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot split stream to use 2 VDSC instances\n" ) |
| 2318 | "Cannot split stream to use 2 VDSC instances\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot split stream to use 2 VDSC instances\n" ); |
| 2319 | return -EINVAL22; |
| 2320 | } |
| 2321 | } |
| 2322 | |
| 2323 | ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); |
| 2324 | if (ret < 0) { |
| 2325 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot compute valid DSC parameters for Input Bpp = %d " "Compressed BPP = %d\n", pipe_config->pipe_bpp, pipe_config ->dsc.compressed_bpp) |
| 2326 | "Cannot compute valid DSC parameters for Input Bpp = %d "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot compute valid DSC parameters for Input Bpp = %d " "Compressed BPP = %d\n", pipe_config->pipe_bpp, pipe_config ->dsc.compressed_bpp) |
| 2327 | "Compressed BPP = %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot compute valid DSC parameters for Input Bpp = %d " "Compressed BPP = %d\n", pipe_config->pipe_bpp, pipe_config ->dsc.compressed_bpp) |
| 2328 | pipe_config->pipe_bpp,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot compute valid DSC parameters for Input Bpp = %d " "Compressed BPP = %d\n", pipe_config->pipe_bpp, pipe_config ->dsc.compressed_bpp) |
| 2329 | pipe_config->dsc.compressed_bpp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Cannot compute valid DSC parameters for Input Bpp = %d " "Compressed BPP = %d\n", pipe_config->pipe_bpp, pipe_config ->dsc.compressed_bpp); |
| 2330 | return ret; |
| 2331 | } |
| 2332 | |
| 2333 | pipe_config->dsc.compression_enable = true1; |
| 2334 | drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", pipe_config->pipe_bpp , pipe_config->dsc.compressed_bpp, pipe_config->dsc.slice_count ) |
| 2335 | "Compressed Bpp = %d Slice Count = %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", pipe_config->pipe_bpp , pipe_config->dsc.compressed_bpp, pipe_config->dsc.slice_count ) |
| 2336 | pipe_config->pipe_bpp,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", pipe_config->pipe_bpp , pipe_config->dsc.compressed_bpp, pipe_config->dsc.slice_count ) |
| 2337 | pipe_config->dsc.compressed_bpp,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", pipe_config->pipe_bpp , pipe_config->dsc.compressed_bpp, pipe_config->dsc.slice_count ) |
| 2338 | pipe_config->dsc.slice_count)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "DP DSC computed with Input Bpp = %d " "Compressed Bpp = %d Slice Count = %d\n", pipe_config->pipe_bpp , pipe_config->dsc.compressed_bpp, pipe_config->dsc.slice_count ); |
| 2339 | |
| 2340 | return 0; |
| 2341 | } |
| 2342 | |
| 2343 | int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) |
| 2344 | { |
| 2345 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) |
| 2346 | return 6 * 3; |
| 2347 | else |
| 2348 | return 8 * 3; |
| 2349 | } |
| 2350 | |
| 2351 | static int |
| 2352 | intel_dp_compute_link_config(struct intel_encoder *encoder, |
| 2353 | struct intel_crtc_state *pipe_config, |
| 2354 | struct drm_connector_state *conn_state) |
| 2355 | { |
| 2356 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
| 2357 | const struct drm_display_mode *adjusted_mode = |
| 2358 | &pipe_config->hw.adjusted_mode; |
| 2359 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2360 | struct link_config_limits limits; |
| 2361 | int common_len; |
| 2362 | int ret; |
| 2363 | |
| 2364 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
| 2365 | intel_dp->max_link_rate); |
| 2366 | |
| 2367 | /* No common link rates between source and sink */ |
| 2368 | drm_WARN_ON(encoder->base.dev, common_len <= 0)({ int __ret = !!((common_len <= 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((encoder->base.dev))->dev), "" , "drm_WARN_ON(" "common_len <= 0" ")"); __builtin_expect( !!(__ret), 0); }); |
| 2369 | |
| 2370 | limits.min_clock = 0; |
| 2371 | limits.max_clock = common_len - 1; |
| 2372 | |
| 2373 | limits.min_lane_count = 1; |
| 2374 | limits.max_lane_count = intel_dp_max_lane_count(intel_dp); |
| 2375 | |
| 2376 | limits.min_bpp = intel_dp_min_bpp(pipe_config); |
| 2377 | limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); |
| 2378 | |
| 2379 | if (intel_dp_is_edp(intel_dp)) { |
| 2380 | /* |
| 2381 | * Use the maximum clock and number of lanes the eDP panel |
| 2382 | * advertizes being capable of. The panels are generally |
| 2383 | * designed to support only a single clock and lane |
| 2384 | * configuration, and typically these values correspond to the |
| 2385 | * native resolution of the panel. |
| 2386 | */ |
| 2387 | limits.min_lane_count = limits.max_lane_count; |
| 2388 | limits.min_clock = limits.max_clock; |
| 2389 | } |
| 2390 | |
| 2391 | intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); |
| 2392 | |
| 2393 | drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link computation with max lane count %i " "max rate %d max bpp %d pixel clock %iKHz\n", limits.max_lane_count , intel_dp->common_rates[limits.max_clock], limits.max_bpp , adjusted_mode->crtc_clock) |
| 2394 | "max rate %d max bpp %d pixel clock %iKHz\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link computation with max lane count %i " "max rate %d max bpp %d pixel clock %iKHz\n", limits.max_lane_count , intel_dp->common_rates[limits.max_clock], limits.max_bpp , adjusted_mode->crtc_clock) |
| 2395 | limits.max_lane_count,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link computation with max lane count %i " "max rate %d max bpp %d pixel clock %iKHz\n", limits.max_lane_count , intel_dp->common_rates[limits.max_clock], limits.max_bpp , adjusted_mode->crtc_clock) |
| 2396 | intel_dp->common_rates[limits.max_clock],drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link computation with max lane count %i " "max rate %d max bpp %d pixel clock %iKHz\n", limits.max_lane_count , intel_dp->common_rates[limits.max_clock], limits.max_bpp , adjusted_mode->crtc_clock) |
| 2397 | limits.max_bpp, adjusted_mode->crtc_clock)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link computation with max lane count %i " "max rate %d max bpp %d pixel clock %iKHz\n", limits.max_lane_count , intel_dp->common_rates[limits.max_clock], limits.max_bpp , adjusted_mode->crtc_clock); |
| 2398 | |
| 2399 | /* |
| 2400 | * Optimize for slow and wide. This is the place to add alternative |
| 2401 | * optimization policy. |
| 2402 | */ |
| 2403 | ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); |
| 2404 | |
| 2405 | /* enable compression if the mode doesn't fit available BW */ |
| 2406 | drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Force DSC en = %d\n" , intel_dp->force_dsc_en); |
| 2407 | if (ret || intel_dp->force_dsc_en) { |
| 2408 | ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, |
| 2409 | conn_state, &limits); |
| 2410 | if (ret < 0) |
| 2411 | return ret; |
| 2412 | } |
| 2413 | |
| 2414 | if (pipe_config->dsc.compression_enable) { |
| 2415 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp, pipe_config->dsc.compressed_bpp) |
| 2416 | "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp, pipe_config->dsc.compressed_bpp) |
| 2417 | pipe_config->lane_count, pipe_config->port_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp, pipe_config->dsc.compressed_bpp) |
| 2418 | pipe_config->pipe_bpp,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp, pipe_config->dsc.compressed_bpp) |
| 2419 | pipe_config->dsc.compressed_bpp)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp, pipe_config->dsc.compressed_bpp); |
| 2420 | |
| 2421 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->dsc.compressed_bpp), intel_dp_max_data_rate(pipe_config-> port_clock, pipe_config->lane_count)) |
| 2422 | "DP link rate required %i available %i\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->dsc.compressed_bpp), intel_dp_max_data_rate(pipe_config-> port_clock, pipe_config->lane_count)) |
| 2423 | intel_dp_link_required(adjusted_mode->crtc_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->dsc.compressed_bpp), intel_dp_max_data_rate(pipe_config-> port_clock, pipe_config->lane_count)) |
| 2424 | pipe_config->dsc.compressed_bpp),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->dsc.compressed_bpp), intel_dp_max_data_rate(pipe_config-> port_clock, pipe_config->lane_count)) |
| 2425 | intel_dp_max_data_rate(pipe_config->port_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->dsc.compressed_bpp), intel_dp_max_data_rate(pipe_config-> port_clock, pipe_config->lane_count)) |
| 2426 | pipe_config->lane_count))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->dsc.compressed_bpp), intel_dp_max_data_rate(pipe_config-> port_clock, pipe_config->lane_count)); |
| 2427 | } else { |
| 2428 | drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp) |
| 2429 | pipe_config->lane_count, pipe_config->port_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp) |
| 2430 | pipe_config->pipe_bpp)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP lane count %d clock %d bpp %d\n" , pipe_config->lane_count, pipe_config->port_clock, pipe_config ->pipe_bpp); |
| 2431 | |
| 2432 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->pipe_bpp), intel_dp_max_data_rate(pipe_config->port_clock , pipe_config->lane_count)) |
| 2433 | "DP link rate required %i available %i\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->pipe_bpp), intel_dp_max_data_rate(pipe_config->port_clock , pipe_config->lane_count)) |
| 2434 | intel_dp_link_required(adjusted_mode->crtc_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->pipe_bpp), intel_dp_max_data_rate(pipe_config->port_clock , pipe_config->lane_count)) |
| 2435 | pipe_config->pipe_bpp),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->pipe_bpp), intel_dp_max_data_rate(pipe_config->port_clock , pipe_config->lane_count)) |
| 2436 | intel_dp_max_data_rate(pipe_config->port_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->pipe_bpp), intel_dp_max_data_rate(pipe_config->port_clock , pipe_config->lane_count)) |
| 2437 | pipe_config->lane_count))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DP link rate required %i available %i\n" , intel_dp_link_required(adjusted_mode->crtc_clock, pipe_config ->pipe_bpp), intel_dp_max_data_rate(pipe_config->port_clock , pipe_config->lane_count)); |
| 2438 | } |
| 2439 | return 0; |
| 2440 | } |
| 2441 | |
| 2442 | static int |
| 2443 | intel_dp_ycbcr420_config(struct intel_dp *intel_dp, |
| 2444 | struct intel_crtc_state *crtc_state, |
| 2445 | const struct drm_connector_state *conn_state) |
| 2446 | { |
| 2447 | struct drm_connector *connector = conn_state->connector; |
| 2448 | const struct drm_display_info *info = &connector->display_info; |
| 2449 | const struct drm_display_mode *adjusted_mode = |
| 2450 | &crtc_state->hw.adjusted_mode; |
| 2451 | |
| 2452 | if (!connector->ycbcr_420_allowed) |
| 2453 | return 0; |
| 2454 | |
| 2455 | if (!drm_mode_is_420_only(info, adjusted_mode)) |
| 2456 | return 0; |
| 2457 | |
| 2458 | if (intel_dp->dfp.ycbcr_444_to_420) { |
| 2459 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; |
| 2460 | return 0; |
| 2461 | } |
| 2462 | |
| 2463 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
| 2464 | |
| 2465 | return intel_pch_panel_fitting(crtc_state, conn_state); |
| 2466 | } |
| 2467 | |
| 2468 | bool_Bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
| 2469 | const struct drm_connector_state *conn_state) |
| 2470 | { |
| 2471 | const struct intel_digital_connector_state *intel_conn_state = |
| 2472 | to_intel_digital_connector_state(conn_state)({ const __typeof( ((struct intel_digital_connector_state *)0 )->base ) *__mptr = (conn_state); (struct intel_digital_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_digital_connector_state , base) );}); |
| 2473 | const struct drm_display_mode *adjusted_mode = |
| 2474 | &crtc_state->hw.adjusted_mode; |
| 2475 | |
| 2476 | /* |
| 2477 | * Our YCbCr output is always limited range. |
| 2478 | * crtc_state->limited_color_range only applies to RGB, |
| 2479 | * and it must never be set for YCbCr or we risk setting |
| 2480 | * some conflicting bits in PIPECONF which will mess up |
| 2481 | * the colors on the monitor. |
| 2482 | */ |
| 2483 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) |
| 2484 | return false0; |
| 2485 | |
| 2486 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
| 2487 | /* |
| 2488 | * See: |
| 2489 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 2490 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 2491 | */ |
| 2492 | return crtc_state->pipe_bpp != 18 && |
| 2493 | drm_default_rgb_quant_range(adjusted_mode) == |
| 2494 | HDMI_QUANTIZATION_RANGE_LIMITED; |
| 2495 | } else { |
| 2496 | return intel_conn_state->broadcast_rgb == |
| 2497 | INTEL_BROADCAST_RGB_LIMITED; |
| 2498 | } |
| 2499 | } |
| 2500 | |
| 2501 | static bool_Bool intel_dp_port_has_audio(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2502 | enum port port) |
| 2503 | { |
| 2504 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 2505 | return false0; |
| 2506 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 12 && port == PORT_A) |
| 2507 | return false0; |
| 2508 | |
| 2509 | return true1; |
| 2510 | } |
| 2511 | |
| 2512 | static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, |
| 2513 | const struct drm_connector_state *conn_state, |
| 2514 | struct drm_dp_vsc_sdp *vsc) |
| 2515 | { |
| 2516 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 2517 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 2518 | |
| 2519 | /* |
| 2520 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 |
| 2521 | * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ |
| 2522 | * Colorimetry Format indication. |
| 2523 | */ |
| 2524 | vsc->revision = 0x5; |
| 2525 | vsc->length = 0x13; |
| 2526 | |
| 2527 | /* DP 1.4a spec, Table 2-120 */ |
| 2528 | switch (crtc_state->output_format) { |
| 2529 | case INTEL_OUTPUT_FORMAT_YCBCR444: |
| 2530 | vsc->pixelformat = DP_PIXELFORMAT_YUV444; |
| 2531 | break; |
| 2532 | case INTEL_OUTPUT_FORMAT_YCBCR420: |
| 2533 | vsc->pixelformat = DP_PIXELFORMAT_YUV420; |
| 2534 | break; |
| 2535 | case INTEL_OUTPUT_FORMAT_RGB: |
| 2536 | default: |
| 2537 | vsc->pixelformat = DP_PIXELFORMAT_RGB; |
| 2538 | } |
| 2539 | |
| 2540 | switch (conn_state->colorspace) { |
| 2541 | case DRM_MODE_COLORIMETRY_BT709_YCC2: |
| 2542 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; |
| 2543 | break; |
| 2544 | case DRM_MODE_COLORIMETRY_XVYCC_6013: |
| 2545 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; |
| 2546 | break; |
| 2547 | case DRM_MODE_COLORIMETRY_XVYCC_7094: |
| 2548 | vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; |
| 2549 | break; |
| 2550 | case DRM_MODE_COLORIMETRY_SYCC_6015: |
| 2551 | vsc->colorimetry = DP_COLORIMETRY_SYCC_601; |
| 2552 | break; |
| 2553 | case DRM_MODE_COLORIMETRY_OPYCC_6016: |
| 2554 | vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; |
| 2555 | break; |
| 2556 | case DRM_MODE_COLORIMETRY_BT2020_CYCC8: |
| 2557 | vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; |
| 2558 | break; |
| 2559 | case DRM_MODE_COLORIMETRY_BT2020_RGB9: |
| 2560 | vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; |
| 2561 | break; |
| 2562 | case DRM_MODE_COLORIMETRY_BT2020_YCC10: |
| 2563 | vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; |
| 2564 | break; |
| 2565 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D6511: |
| 2566 | case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER12: |
| 2567 | vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; |
| 2568 | break; |
| 2569 | default: |
| 2570 | /* |
| 2571 | * RGB->YCBCR color conversion uses the BT.709 |
| 2572 | * color space. |
| 2573 | */ |
| 2574 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
| 2575 | vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; |
| 2576 | else |
| 2577 | vsc->colorimetry = DP_COLORIMETRY_DEFAULT; |
| 2578 | break; |
| 2579 | } |
| 2580 | |
| 2581 | vsc->bpc = crtc_state->pipe_bpp / 3; |
| 2582 | |
| 2583 | /* only RGB pixelformat supports 6 bpc */ |
| 2584 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB" ")"); __builtin_expect(!!(__ret), 0); }) |
| 2585 | vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB)({ int __ret = !!((vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB" ")"); __builtin_expect(!!(__ret), 0); }); |
| 2586 | |
| 2587 | /* all YCbCr are always limited range */ |
| 2588 | vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; |
| 2589 | vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; |
| 2590 | } |
| 2591 | |
| 2592 | static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, |
| 2593 | struct intel_crtc_state *crtc_state, |
| 2594 | const struct drm_connector_state *conn_state) |
| 2595 | { |
| 2596 | struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; |
| 2597 | |
| 2598 | /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */ |
| 2599 | if (crtc_state->has_psr) |
| 2600 | return; |
| 2601 | |
| 2602 | if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) |
| 2603 | return; |
| 2604 | |
| 2605 | crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC0x07); |
| 2606 | vsc->sdp_type = DP_SDP_VSC0x07; |
| 2607 | intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, |
| 2608 | &crtc_state->infoframes.vsc); |
| 2609 | } |
| 2610 | |
| 2611 | void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, |
| 2612 | const struct intel_crtc_state *crtc_state, |
| 2613 | const struct drm_connector_state *conn_state, |
| 2614 | struct drm_dp_vsc_sdp *vsc) |
| 2615 | { |
| 2616 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 2617 | |
| 2618 | vsc->sdp_type = DP_SDP_VSC0x07; |
| 2619 | |
| 2620 | if (dev_priv->psr.psr2_enabled) { |
| 2621 | if (dev_priv->psr.colorimetry_support && |
| 2622 | intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { |
| 2623 | /* [PSR2, +Colorimetry] */ |
| 2624 | intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, |
| 2625 | vsc); |
| 2626 | } else { |
| 2627 | /* |
| 2628 | * [PSR2, -Colorimetry] |
| 2629 | * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 |
| 2630 | * 3D stereo + PSR/PSR2 + Y-coordinate. |
| 2631 | */ |
| 2632 | vsc->revision = 0x4; |
| 2633 | vsc->length = 0xe; |
| 2634 | } |
| 2635 | } else { |
| 2636 | /* |
| 2637 | * [PSR1] |
| 2638 | * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 |
| 2639 | * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or |
| 2640 | * higher). |
| 2641 | */ |
| 2642 | vsc->revision = 0x2; |
| 2643 | vsc->length = 0x8; |
| 2644 | } |
| 2645 | } |
| 2646 | |
| 2647 | static void |
| 2648 | intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, |
| 2649 | struct intel_crtc_state *crtc_state, |
| 2650 | const struct drm_connector_state *conn_state) |
| 2651 | { |
| 2652 | int ret; |
| 2653 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 2654 | struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; |
| 2655 | |
| 2656 | if (!conn_state->hdr_output_metadata) |
| 2657 | return; |
| 2658 | |
| 2659 | ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); |
| 2660 | |
| 2661 | if (ret) { |
| 2662 | drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "couldn't set HDR metadata in infoframe\n" ); |
| 2663 | return; |
| 2664 | } |
| 2665 | |
| 2666 | crtc_state->infoframes.enable |= |
| 2667 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); |
| 2668 | } |
| 2669 | |
| 2670 | static void |
| 2671 | intel_dp_drrs_compute_config(struct intel_dp *intel_dp, |
| 2672 | struct intel_crtc_state *pipe_config, |
| 2673 | int output_bpp, bool_Bool constant_n) |
| 2674 | { |
| 2675 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 2676 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 2677 | |
| 2678 | /* |
| 2679 | * DRRS and PSR can't be enable together, so giving preference to PSR |
| 2680 | * as it allows more power-savings by complete shutting down display, |
| 2681 | * so to guarantee this, intel_dp_drrs_compute_config() must be called |
| 2682 | * after intel_psr_compute_config(). |
| 2683 | */ |
| 2684 | if (pipe_config->has_psr) |
| 2685 | return; |
| 2686 | |
| 2687 | if (!intel_connector->panel.downclock_mode || |
| 2688 | dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) |
| 2689 | return; |
| 2690 | |
| 2691 | pipe_config->has_drrs = true1; |
| 2692 | intel_link_compute_m_n(output_bpp, pipe_config->lane_count, |
| 2693 | intel_connector->panel.downclock_mode->clock, |
| 2694 | pipe_config->port_clock, &pipe_config->dp_m2_n2, |
| 2695 | constant_n, pipe_config->fec_enable); |
| 2696 | } |
| 2697 | |
| 2698 | int |
| 2699 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 2700 | struct intel_crtc_state *pipe_config, |
| 2701 | struct drm_connector_state *conn_state) |
| 2702 | { |
| 2703 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 2704 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
| 2705 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2706 | struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); |
| 2707 | enum port port = encoder->port; |
| 2708 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 2709 | struct intel_digital_connector_state *intel_conn_state = |
| 2710 | to_intel_digital_connector_state(conn_state)({ const __typeof( ((struct intel_digital_connector_state *)0 )->base ) *__mptr = (conn_state); (struct intel_digital_connector_state *)( (char *)__mptr - __builtin_offsetof(struct intel_digital_connector_state , base) );}); |
| 2711 | bool_Bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0, |
| 2712 | DP_DPCD_QUIRK_CONSTANT_N); |
| 2713 | int ret = 0, output_bpp; |
| 2714 | |
| 2715 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE) && !HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi) && port != PORT_A) |
| 2716 | pipe_config->has_pch_encoder = true1; |
| 2717 | |
| 2718 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 2719 | |
| 2720 | if (lspcon->active) |
| 2721 | lspcon_ycbcr420_config(&intel_connector->base, pipe_config); |
| 2722 | else |
| 2723 | ret = intel_dp_ycbcr420_config(intel_dp, pipe_config, |
| 2724 | conn_state); |
| 2725 | if (ret) |
| 2726 | return ret; |
| 2727 | |
| 2728 | if (!intel_dp_port_has_audio(dev_priv, port)) |
| 2729 | pipe_config->has_audio = false0; |
| 2730 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) |
| 2731 | pipe_config->has_audio = intel_dp->has_audio; |
| 2732 | else |
| 2733 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; |
| 2734 | |
| 2735 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 2736 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 2737 | adjusted_mode); |
| 2738 | |
| 2739 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) |
| 2740 | ret = intel_gmch_panel_fitting(pipe_config, conn_state); |
| 2741 | else |
| 2742 | ret = intel_pch_panel_fitting(pipe_config, conn_state); |
| 2743 | if (ret) |
| 2744 | return ret; |
| 2745 | } |
| 2746 | |
| 2747 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)) |
| 2748 | return -EINVAL22; |
| 2749 | |
| 2750 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && |
| 2751 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 2752 | return -EINVAL22; |
| 2753 | |
| 2754 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK(1<<12)) |
| 2755 | return -EINVAL22; |
| 2756 | |
| 2757 | if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) |
| 2758 | return -EINVAL22; |
| 2759 | |
| 2760 | ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); |
| 2761 | if (ret < 0) |
| 2762 | return ret; |
| 2763 | |
| 2764 | pipe_config->limited_color_range = |
| 2765 | intel_dp_limited_color_range(pipe_config, conn_state); |
| 2766 | |
| 2767 | if (pipe_config->dsc.compression_enable) |
| 2768 | output_bpp = pipe_config->dsc.compressed_bpp; |
| 2769 | else |
| 2770 | output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); |
| 2771 | |
| 2772 | intel_link_compute_m_n(output_bpp, |
| 2773 | pipe_config->lane_count, |
| 2774 | adjusted_mode->crtc_clock, |
| 2775 | pipe_config->port_clock, |
| 2776 | &pipe_config->dp_m_n, |
| 2777 | constant_n, pipe_config->fec_enable); |
| 2778 | |
| 2779 | if (!HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
| 2780 | intel_dp_set_clock(encoder, pipe_config); |
| 2781 | |
| 2782 | intel_psr_compute_config(intel_dp, pipe_config); |
| 2783 | intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp, |
| 2784 | constant_n); |
| 2785 | intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); |
| 2786 | intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); |
| 2787 | |
| 2788 | return 0; |
| 2789 | } |
| 2790 | |
| 2791 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 2792 | int link_rate, u8 lane_count, |
| 2793 | bool_Bool link_mst) |
| 2794 | { |
| 2795 | intel_dp->link_trained = false0; |
| 2796 | intel_dp->link_rate = link_rate; |
| 2797 | intel_dp->lane_count = lane_count; |
| 2798 | intel_dp->link_mst = link_mst; |
| 2799 | } |
| 2800 | |
| 2801 | static void intel_dp_prepare(struct intel_encoder *encoder, |
| 2802 | const struct intel_crtc_state *pipe_config) |
| 2803 | { |
| 2804 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 2805 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2806 | enum port port = encoder->port; |
| 2807 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 2808 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
| 2809 | |
| 2810 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
| 2811 | pipe_config->lane_count, |
| 2812 | intel_crtc_has_type(pipe_config, |
| 2813 | INTEL_OUTPUT_DP_MST)); |
| 2814 | |
| 2815 | /* |
| 2816 | * There are four kinds of DP registers: |
| 2817 | * |
| 2818 | * IBX PCH |
| 2819 | * SNB CPU |
| 2820 | * IVB CPU |
| 2821 | * CPT PCH |
| 2822 | * |
| 2823 | * IBX PCH and CPU are the same for almost everything, |
| 2824 | * except that the CPU DP PLL is configured in this |
| 2825 | * register |
| 2826 | * |
| 2827 | * CPT PCH is quite different, having many bits moved |
| 2828 | * to the TRANS_DP_CTL register instead. That |
| 2829 | * configuration happens (oddly) in ilk_pch_enable |
| 2830 | */ |
| 2831 | |
| 2832 | /* Preserve the BIOS-computed detected bit. This is |
| 2833 | * supposed to be read-only. |
| 2834 | */ |
| 2835 | intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED(1 << 2); |
| 2836 | |
| 2837 | /* Handle DP bits in common between all three register formats */ |
| 2838 | intel_dp->DP |= DP_VOLTAGE_0_4(0 << 25) | DP_PRE_EMPHASIS_0(0 << 22); |
| 2839 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count)(((pipe_config->lane_count) - 1) << 19); |
| 2840 | |
| 2841 | /* Split out the IBX/CPU vs CPT settings */ |
| 2842 | |
| 2843 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) && port == PORT_A) { |
| 2844 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
| 2845 | intel_dp->DP |= DP_SYNC_HS_HIGH(1 << 3); |
| 2846 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
| 2847 | intel_dp->DP |= DP_SYNC_VS_HIGH(1 << 4); |
| 2848 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT(3 << 8); |
| 2849 | |
| 2850 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2851 | intel_dp->DP |= DP_ENHANCED_FRAMING(1 << 18); |
| 2852 | |
| 2853 | intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe)((crtc->pipe) << 29); |
| 2854 | } else if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT) && port != PORT_A) { |
| 2855 | u32 trans_dp; |
| 2856 | |
| 2857 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT(3 << 8); |
| 2858 | |
| 2859 | trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe)((const i915_reg_t){ .reg = (((0xe0300) + (crtc->pipe) * ( (0xe1300) - (0xe0300)))) })); |
| 2860 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2861 | trans_dp |= TRANS_DP_ENH_FRAMING(1 << 18); |
| 2862 | else |
| 2863 | trans_dp &= ~TRANS_DP_ENH_FRAMING(1 << 18); |
| 2864 | intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe)((const i915_reg_t){ .reg = (((0xe0300) + (crtc->pipe) * ( (0xe1300) - (0xe0300)))) }), trans_dp); |
| 2865 | } else { |
| 2866 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) && pipe_config->limited_color_range) |
| 2867 | intel_dp->DP |= DP_COLOR_RANGE_16_235(1 << 8); |
| 2868 | |
| 2869 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
| 2870 | intel_dp->DP |= DP_SYNC_HS_HIGH(1 << 3); |
| 2871 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
| 2872 | intel_dp->DP |= DP_SYNC_VS_HIGH(1 << 4); |
| 2873 | intel_dp->DP |= DP_LINK_TRAIN_OFF(3 << 28); |
| 2874 | |
| 2875 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2876 | intel_dp->DP |= DP_ENHANCED_FRAMING(1 << 18); |
| 2877 | |
| 2878 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 2879 | intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe)((crtc->pipe) << 16); |
| 2880 | else |
| 2881 | intel_dp->DP |= DP_PIPE_SEL(crtc->pipe)((crtc->pipe) << 30); |
| 2882 | } |
| 2883 | } |
| 2884 | |
| 2885 | #define IDLE_ON_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | ((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | PP_SEQUENCE_STATE_MASK((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) |
| 2886 | #define IDLE_ON_VALUE(((u32)((1UL << (31)) + 0)) | ((u32)((((typeof(((u32)(( ((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28) )) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0)) | 0 | ((u32)((((typeof(((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))))(0x8) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | PP_SEQUENCE_STATE_ON_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))) |
| 2887 | |
| 2888 | #define IDLE_OFF_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | 0) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | 0) |
| 2889 | #define IDLE_OFF_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | 0) (0 | PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | 0) |
| 2890 | |
| 2891 | #define IDLE_CYCLE_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | ((u32)( (1UL << (27)) + 0)) | ((u32)((((~0UL) >> (64 - (3 ) - 1)) & ((~0UL) << (0))) + 0))) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | PP_CYCLE_DELAY_ACTIVE((u32)((1UL << (27)) + 0)) | PP_SEQUENCE_STATE_MASK((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) |
| 2892 | #define IDLE_CYCLE_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) ) (0 | PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | PP_SEQUENCE_STATE_OFF_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))) |
| 2893 | |
| 2894 | static void intel_pps_verify_state(struct intel_dp *intel_dp); |
| 2895 | |
| 2896 | static void wait_panel_status(struct intel_dp *intel_dp, |
| 2897 | u32 mask, |
| 2898 | u32 value) |
| 2899 | { |
| 2900 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 2901 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| 2902 | |
| 2903 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 2904 | |
| 2905 | intel_pps_verify_state(intel_dp); |
| 2906 | |
| 2907 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 2908 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 2909 | |
| 2910 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
| 2911 | "mask %08x value %08x status %08x control %08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
| 2912 | mask, value,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
| 2913 | intel_de_read(dev_priv, pp_stat_reg),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
| 2914 | intel_de_read(dev_priv, pp_ctrl_reg))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)); |
| 2915 | |
| 2916 | if (intel_de_wait_for_register(dev_priv, pp_stat_reg, |
| 2917 | mask, value, 5000)) |
| 2918 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ) |
| 2919 | "Panel status timeout: status %08x control %08x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ) |
| 2920 | intel_de_read(dev_priv, pp_stat_reg),printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ) |
| 2921 | intel_de_read(dev_priv, pp_ctrl_reg))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ); |
| 2922 | |
| 2923 | drm_dbg_kms(&dev_priv->drm, "Wait complete\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Wait complete\n" ); |
| 2924 | } |
| 2925 | |
| 2926 | static void wait_panel_on(struct intel_dp *intel_dp) |
| 2927 | { |
| 2928 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 2929 | |
| 2930 | drm_dbg_kms(&i915->drm, "Wait for panel power on\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Wait for panel power on\n" ); |
| 2931 | wait_panel_status(intel_dp, IDLE_ON_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | ((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))), IDLE_ON_VALUE(((u32)((1UL << (31)) + 0)) | ((u32)((((typeof(((u32)(( ((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28) )) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0)) | 0 | ((u32)((((typeof(((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))))(0x8) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)))); |
| 2932 | } |
| 2933 | |
| 2934 | static void wait_panel_off(struct intel_dp *intel_dp) |
| 2935 | { |
| 2936 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 2937 | |
| 2938 | drm_dbg_kms(&i915->drm, "Wait for panel power off time\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Wait for panel power off time\n" ); |
| 2939 | wait_panel_status(intel_dp, IDLE_OFF_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | 0), IDLE_OFF_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | 0)); |
| 2940 | } |
| 2941 | |
| 2942 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
| 2943 | { |
| 2944 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 2945 | ktime_t panel_power_on_time; |
| 2946 | s64 panel_power_off_duration; |
| 2947 | |
| 2948 | drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Wait for panel power cycle\n" ); |
| 2949 | |
| 2950 | /* take the difference of currrent time and panel power off time |
| 2951 | * and then make panel wait for t11_t12 if needed. */ |
| 2952 | panel_power_on_time = ktime_get_boottime()ktime_get(); |
| 2953 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); |
| 2954 | |
| 2955 | /* When we disable the VDD override bit last we have to do the manual |
| 2956 | * wait. */ |
| 2957 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
| 2958 | wait_remaining_ms_from_jiffies(jiffies, |
| 2959 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); |
| 2960 | |
| 2961 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | ((u32)( (1UL << (27)) + 0)) | ((u32)((((~0UL) >> (64 - (3 ) - 1)) & ((~0UL) << (0))) + 0))), IDLE_CYCLE_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) )); |
| 2962 | } |
| 2963 | |
| 2964 | static void wait_backlight_on(struct intel_dp *intel_dp) |
| 2965 | { |
| 2966 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 2967 | intel_dp->backlight_on_delay); |
| 2968 | } |
| 2969 | |
| 2970 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
| 2971 | { |
| 2972 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 2973 | intel_dp->backlight_off_delay); |
| 2974 | } |
| 2975 | |
| 2976 | /* Read the current pp_control value, unlocking the register if it |
| 2977 | * is locked |
| 2978 | */ |
| 2979 | |
| 2980 | static u32 ilk_get_pp_control(struct intel_dp *intel_dp) |
| 2981 | { |
| 2982 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 2983 | u32 control; |
| 2984 | |
| 2985 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 2986 | |
| 2987 | control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); |
| 2988 | if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&({ int __ret = !!((!((&(dev_priv)->__info)->display .has_ddi) && (control & ((u32)((((~0UL) >> ( 64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32 )((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ( (~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__info)->display.has_ddi) && (control & ((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 2989 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)({ int __ret = !!((!((&(dev_priv)->__info)->display .has_ddi) && (control & ((u32)((((~0UL) >> ( 64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32 )((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ( (~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__info)->display.has_ddi) && (control & ((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); })) { |
| 2990 | control &= ~PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0)); |
| 2991 | control |= PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )); |
| 2992 | } |
| 2993 | return control; |
| 2994 | } |
| 2995 | |
| 2996 | /* |
| 2997 | * Must be paired with edp_panel_vdd_off(). |
| 2998 | * Must hold pps_mutex around the whole on/off sequence. |
| 2999 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 3000 | */ |
| 3001 | static bool_Bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 3002 | { |
| 3003 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3004 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3005 | u32 pp; |
| 3006 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| 3007 | bool_Bool need_to_disable = !intel_dp->want_panel_vdd; |
| 3008 | |
| 3009 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 3010 | |
| 3011 | if (!intel_dp_is_edp(intel_dp)) |
| 3012 | return false0; |
| 3013 | |
| 3014 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
| 3015 | intel_dp->want_panel_vdd = true1; |
| 3016 | |
| 3017 | if (edp_have_panel_vdd(intel_dp)) |
| 3018 | return need_to_disable; |
| 3019 | |
| 3020 | intel_display_power_get(dev_priv, |
| 3021 | intel_aux_power_domain(dig_port)); |
| 3022 | |
| 3023 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD on\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3024 | dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD on\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3025 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD on\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
| 3026 | |
| 3027 | if (!edp_have_panel_power(intel_dp)) |
| 3028 | wait_panel_power_cycle(intel_dp); |
| 3029 | |
| 3030 | pp = ilk_get_pp_control(intel_dp); |
| 3031 | pp |= EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
| 3032 | |
| 3033 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 3034 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 3035 | |
| 3036 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3037 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3038 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
| 3039 | intel_de_read(dev_priv, pp_stat_reg),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
| 3040 | intel_de_read(dev_priv, pp_ctrl_reg))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)); |
| 3041 | /* |
| 3042 | * If the panel wasn't on, delay before accessing aux channel |
| 3043 | */ |
| 3044 | if (!edp_have_panel_power(intel_dp)) { |
| 3045 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3046 | "[ENCODER:%d:%s] panel power wasn't enabled\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3047 | dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3048 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
| 3049 | drm_msleep(intel_dp->panel_power_up_delay)mdelay(intel_dp->panel_power_up_delay); |
| 3050 | } |
| 3051 | |
| 3052 | return need_to_disable; |
| 3053 | } |
| 3054 | |
| 3055 | /* |
| 3056 | * Must be paired with intel_edp_panel_vdd_off() or |
| 3057 | * intel_edp_panel_off(). |
| 3058 | * Nested calls to these functions are not allowed since |
| 3059 | * we drop the lock. Caller must use some higher level |
| 3060 | * locking to prevent nested calls from other threads. |
| 3061 | */ |
| 3062 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 3063 | { |
| 3064 | intel_wakeref_t wakeref; |
| 3065 | bool_Bool vdd; |
| 3066 | |
| 3067 | if (!intel_dp_is_edp(intel_dp)) |
| 3068 | return; |
| 3069 | |
| 3070 | vdd = false0; |
| 3071 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) |
| 3072 | vdd = edp_panel_vdd_on(intel_dp); |
| 3073 | I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",({ int __ret_warn_on = !!(!vdd); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3074 | dp_to_dig_port(intel_dp)->base.base.base.id,({ int __ret_warn_on = !!(!vdd); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3075 | dp_to_dig_port(intel_dp)->base.base.name)({ int __ret_warn_on = !!(!vdd); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 3076 | } |
| 3077 | |
| 3078 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
| 3079 | { |
| 3080 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3081 | struct intel_digital_port *dig_port = |
| 3082 | dp_to_dig_port(intel_dp); |
| 3083 | u32 pp; |
| 3084 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
| 3085 | |
| 3086 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 3087 | |
| 3088 | drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd)({ int __ret = !!((intel_dp->want_panel_vdd)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "intel_dp->want_panel_vdd" ")"); __builtin_expect (!!(__ret), 0); }); |
| 3089 | |
| 3090 | if (!edp_have_panel_vdd(intel_dp)) |
| 3091 | return; |
| 3092 | |
| 3093 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD off\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3094 | dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD off\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3095 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD off\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
| 3096 | |
| 3097 | pp = ilk_get_pp_control(intel_dp); |
| 3098 | pp &= ~EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
| 3099 | |
| 3100 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 3101 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 3102 | |
| 3103 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3104 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3105 | |
| 3106 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 3107 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
| 3108 | intel_de_read(dev_priv, pp_stat_reg),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
| 3109 | intel_de_read(dev_priv, pp_ctrl_reg))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)); |
| 3110 | |
| 3111 | if ((pp & PANEL_POWER_ON((u32)((1UL << (0)) + 0))) == 0) |
| 3112 | intel_dp->panel_power_off_time = ktime_get_boottime()ktime_get(); |
| 3113 | |
| 3114 | intel_display_power_put_unchecked(dev_priv, |
| 3115 | intel_aux_power_domain(dig_port)); |
| 3116 | } |
| 3117 | |
| 3118 | static void edp_panel_vdd_work(struct work_struct *__work) |
| 3119 | { |
| 3120 | struct intel_dp *intel_dp = |
| 3121 | container_of(to_delayed_work(__work),({ const __typeof( ((struct intel_dp *)0)->panel_vdd_work ) *__mptr = (to_delayed_work(__work)); (struct intel_dp *)( (char *)__mptr - __builtin_offsetof(struct intel_dp, panel_vdd_work ) );}) |
| 3122 | struct intel_dp, panel_vdd_work)({ const __typeof( ((struct intel_dp *)0)->panel_vdd_work ) *__mptr = (to_delayed_work(__work)); (struct intel_dp *)( (char *)__mptr - __builtin_offsetof(struct intel_dp, panel_vdd_work ) );}); |
| 3123 | intel_wakeref_t wakeref; |
| 3124 | |
| 3125 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) { |
| 3126 | if (!intel_dp->want_panel_vdd) |
| 3127 | edp_panel_vdd_off_sync(intel_dp); |
| 3128 | } |
| 3129 | } |
| 3130 | |
| 3131 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
| 3132 | { |
| 3133 | unsigned long delay; |
| 3134 | |
| 3135 | /* |
| 3136 | * Queue the timer to fire a long time from now (relative to the power |
| 3137 | * down delay) to keep the panel power up across a sequence of |
| 3138 | * operations. |
| 3139 | */ |
| 3140 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)(((uint64_t)(intel_dp->panel_power_cycle_delay * 5)) * hz / 1000); |
| 3141 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); |
| 3142 | } |
| 3143 | |
| 3144 | /* |
| 3145 | * Must be paired with edp_panel_vdd_on(). |
| 3146 | * Must hold pps_mutex around the whole on/off sequence. |
| 3147 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. |
| 3148 | */ |
| 3149 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool_Bool sync) |
| 3150 | { |
| 3151 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3152 | |
| 3153 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 3154 | |
| 3155 | if (!intel_dp_is_edp(intel_dp)) |
| 3156 | return; |
| 3157 | |
| 3158 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",({ int __ret_warn_on = !!(!intel_dp->want_panel_vdd); if ( __builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = ! !(i915_modparams.verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] VDD not forced on" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD not forced on", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 3159 | dp_to_dig_port(intel_dp)->base.base.base.id,({ int __ret_warn_on = !!(!intel_dp->want_panel_vdd); if ( __builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = ! !(i915_modparams.verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] VDD not forced on" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD not forced on", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 3160 | dp_to_dig_port(intel_dp)->base.base.name)({ int __ret_warn_on = !!(!intel_dp->want_panel_vdd); if ( __builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = ! !(i915_modparams.verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] VDD not forced on" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD not forced on", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 3161 | |
| 3162 | intel_dp->want_panel_vdd = false0; |
| 3163 | |
| 3164 | if (sync) |
| 3165 | edp_panel_vdd_off_sync(intel_dp); |
| 3166 | else |
| 3167 | edp_panel_vdd_schedule_off(intel_dp); |
| 3168 | } |
| 3169 | |
| 3170 | static void edp_panel_on(struct intel_dp *intel_dp) |
| 3171 | { |
| 3172 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3173 | u32 pp; |
| 3174 | i915_reg_t pp_ctrl_reg; |
| 3175 | |
| 3176 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 3177 | |
| 3178 | if (!intel_dp_is_edp(intel_dp)) |
| 3179 | return; |
| 3180 | |
| 3181 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name) |
| 3182 | dp_to_dig_port(intel_dp)->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name) |
| 3183 | dp_to_dig_port(intel_dp)->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); |
| 3184 | |
| 3185 | if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); }) |
| 3186 | "[ENCODER:%d:%s] panel power already on\n",({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); }) |
| 3187 | dp_to_dig_port(intel_dp)->base.base.base.id,({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); }) |
| 3188 | dp_to_dig_port(intel_dp)->base.base.name)({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); })) |
| 3189 | return; |
| 3190 | |
| 3191 | wait_panel_power_cycle(intel_dp); |
| 3192 | |
| 3193 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 3194 | pp = ilk_get_pp_control(intel_dp); |
| 3195 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) { |
| 3196 | /* ILK workaround: disable reset around power sequence */ |
| 3197 | pp &= ~PANEL_POWER_RESET((u32)((1UL << (1)) + 0)); |
| 3198 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3199 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3200 | } |
| 3201 | |
| 3202 | pp |= PANEL_POWER_ON((u32)((1UL << (0)) + 0)); |
| 3203 | if (!IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) |
| 3204 | pp |= PANEL_POWER_RESET((u32)((1UL << (1)) + 0)); |
| 3205 | |
| 3206 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3207 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3208 | |
| 3209 | wait_panel_on(intel_dp); |
| 3210 | intel_dp->last_power_on = jiffies; |
| 3211 | |
| 3212 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) { |
| 3213 | pp |= PANEL_POWER_RESET((u32)((1UL << (1)) + 0)); /* restore panel reset bit */ |
| 3214 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3215 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3216 | } |
| 3217 | } |
| 3218 | |
| 3219 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
| 3220 | { |
| 3221 | intel_wakeref_t wakeref; |
| 3222 | |
| 3223 | if (!intel_dp_is_edp(intel_dp)) |
| 3224 | return; |
| 3225 | |
| 3226 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) |
| 3227 | edp_panel_on(intel_dp); |
| 3228 | } |
| 3229 | |
| 3230 | |
| 3231 | static void edp_panel_off(struct intel_dp *intel_dp) |
| 3232 | { |
| 3233 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3234 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3235 | u32 pp; |
| 3236 | i915_reg_t pp_ctrl_reg; |
| 3237 | |
| 3238 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 3239 | |
| 3240 | if (!intel_dp_is_edp(intel_dp)) |
| 3241 | return; |
| 3242 | |
| 3243 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power off\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
| 3244 | dig_port->base.base.base.id, dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power off\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
| 3245 | |
| 3246 | drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,({ int __ret = !!(!intel_dp->want_panel_vdd); if (__ret) printf ("%s %s: " "Need [ENCODER:%d:%s] VDD to turn off panel\n", dev_driver_string ((&dev_priv->drm)->dev), "", dig_port->base.base .base.id, dig_port->base.base.name); __builtin_expect(!!(__ret ), 0); }) |
| 3247 | "Need [ENCODER:%d:%s] VDD to turn off panel\n",({ int __ret = !!(!intel_dp->want_panel_vdd); if (__ret) printf ("%s %s: " "Need [ENCODER:%d:%s] VDD to turn off panel\n", dev_driver_string ((&dev_priv->drm)->dev), "", dig_port->base.base .base.id, dig_port->base.base.name); __builtin_expect(!!(__ret ), 0); }) |
| 3248 | dig_port->base.base.base.id, dig_port->base.base.name)({ int __ret = !!(!intel_dp->want_panel_vdd); if (__ret) printf ("%s %s: " "Need [ENCODER:%d:%s] VDD to turn off panel\n", dev_driver_string ((&dev_priv->drm)->dev), "", dig_port->base.base .base.id, dig_port->base.base.name); __builtin_expect(!!(__ret ), 0); }); |
| 3249 | |
| 3250 | pp = ilk_get_pp_control(intel_dp); |
| 3251 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 3252 | * panels get very unhappy and cease to work. */ |
| 3253 | pp &= ~(PANEL_POWER_ON((u32)((1UL << (0)) + 0)) | PANEL_POWER_RESET((u32)((1UL << (1)) + 0)) | EDP_FORCE_VDD((u32)((1UL << (3)) + 0)) | |
| 3254 | EDP_BLC_ENABLE((u32)((1UL << (2)) + 0))); |
| 3255 | |
| 3256 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 3257 | |
| 3258 | intel_dp->want_panel_vdd = false0; |
| 3259 | |
| 3260 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3261 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3262 | |
| 3263 | wait_panel_off(intel_dp); |
| 3264 | intel_dp->panel_power_off_time = ktime_get_boottime()ktime_get(); |
| 3265 | |
| 3266 | /* We got a reference when we enabled the VDD. */ |
| 3267 | intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); |
| 3268 | } |
| 3269 | |
| 3270 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
| 3271 | { |
| 3272 | intel_wakeref_t wakeref; |
| 3273 | |
| 3274 | if (!intel_dp_is_edp(intel_dp)) |
| 3275 | return; |
| 3276 | |
| 3277 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) |
| 3278 | edp_panel_off(intel_dp); |
| 3279 | } |
| 3280 | |
| 3281 | /* Enable backlight in the panel power control. */ |
| 3282 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) |
| 3283 | { |
| 3284 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3285 | intel_wakeref_t wakeref; |
| 3286 | |
| 3287 | /* |
| 3288 | * If we enable the backlight right away following a panel power |
| 3289 | * on, we may see slight flicker as the panel syncs with the eDP |
| 3290 | * link. So delay a bit to make sure the image is solid before |
| 3291 | * allowing it to appear. |
| 3292 | */ |
| 3293 | wait_backlight_on(intel_dp); |
| 3294 | |
| 3295 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) { |
| 3296 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 3297 | u32 pp; |
| 3298 | |
| 3299 | pp = ilk_get_pp_control(intel_dp); |
| 3300 | pp |= EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)); |
| 3301 | |
| 3302 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3303 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3304 | } |
| 3305 | } |
| 3306 | |
| 3307 | /* Enable backlight PWM and backlight PP control. */ |
| 3308 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
| 3309 | const struct drm_connector_state *conn_state) |
| 3310 | { |
| 3311 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );})); |
| 3312 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 3313 | |
| 3314 | if (!intel_dp_is_edp(intel_dp)) |
| 3315 | return; |
| 3316 | |
| 3317 | drm_dbg_kms(&i915->drm, "\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\n"); |
| 3318 | |
| 3319 | intel_panel_enable_backlight(crtc_state, conn_state); |
| 3320 | _intel_edp_backlight_on(intel_dp); |
| 3321 | } |
| 3322 | |
| 3323 | /* Disable backlight in the panel power control. */ |
| 3324 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) |
| 3325 | { |
| 3326 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3327 | intel_wakeref_t wakeref; |
| 3328 | |
| 3329 | if (!intel_dp_is_edp(intel_dp)) |
| 3330 | return; |
| 3331 | |
| 3332 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) { |
| 3333 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 3334 | u32 pp; |
| 3335 | |
| 3336 | pp = ilk_get_pp_control(intel_dp); |
| 3337 | pp &= ~EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)); |
| 3338 | |
| 3339 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
| 3340 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
| 3341 | } |
| 3342 | |
| 3343 | intel_dp->last_backlight_off = jiffies; |
| 3344 | edp_wait_backlight_off(intel_dp); |
| 3345 | } |
| 3346 | |
| 3347 | /* Disable backlight PP control and backlight PWM. */ |
| 3348 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
| 3349 | { |
| 3350 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (old_conn_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );})); |
| 3351 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 3352 | |
| 3353 | if (!intel_dp_is_edp(intel_dp)) |
| 3354 | return; |
| 3355 | |
| 3356 | drm_dbg_kms(&i915->drm, "\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\n"); |
| 3357 | |
| 3358 | _intel_edp_backlight_off(intel_dp); |
| 3359 | intel_panel_disable_backlight(old_conn_state); |
| 3360 | } |
| 3361 | |
| 3362 | /* |
| 3363 | * Hook for controlling the panel power control backlight through the bl_power |
| 3364 | * sysfs attribute. Take care to handle multiple calls. |
| 3365 | */ |
| 3366 | static void intel_edp_backlight_power(struct intel_connector *connector, |
| 3367 | bool_Bool enable) |
| 3368 | { |
| 3369 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->base.dev); |
| 3370 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 3371 | intel_wakeref_t wakeref; |
| 3372 | bool_Bool is_enabled; |
| 3373 | |
| 3374 | is_enabled = false0; |
| 3375 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) |
| 3376 | is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)); |
| 3377 | if (is_enabled == enable) |
| 3378 | return; |
| 3379 | |
| 3380 | drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "panel power control backlight %s\n" , enable ? "enable" : "disable") |
| 3381 | enable ? "enable" : "disable")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "panel power control backlight %s\n" , enable ? "enable" : "disable"); |
| 3382 | |
| 3383 | if (enable) |
| 3384 | _intel_edp_backlight_on(intel_dp); |
| 3385 | else |
| 3386 | _intel_edp_backlight_off(intel_dp); |
| 3387 | } |
| 3388 | |
| 3389 | static void assert_dp_port(struct intel_dp *intel_dp, bool_Bool state) |
| 3390 | { |
| 3391 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3392 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 3393 | bool_Bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN(1 << 31); |
| 3394 | |
| 3395 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3396 | "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3397 | dig_port->base.base.base.id, dig_port->base.base.name,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3398 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n" , dig_port->base.base.base.id, dig_port->base.base.name , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 3399 | } |
| 3400 | #define assert_dp_port_disabled(d)assert_dp_port((d), 0) assert_dp_port((d), false0) |
| 3401 | |
| 3402 | static void assert_edp_pll(struct drm_i915_privateinteldrm_softc *dev_priv, bool_Bool state) |
| 3403 | { |
| 3404 | bool_Bool cur_state = intel_de_read(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) })) & DP_PLL_ENABLE(1 << 14); |
| 3405 | |
| 3406 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("eDP PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("eDP PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3407 | "eDP PLL state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("eDP PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("eDP PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 3408 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("eDP PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("eDP PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 3409 | } |
| 3410 | #define assert_edp_pll_enabled(d)assert_edp_pll((d), 1) assert_edp_pll((d), true1) |
| 3411 | #define assert_edp_pll_disabled(d)assert_edp_pll((d), 0) assert_edp_pll((d), false0) |
| 3412 | |
| 3413 | static void ilk_edp_pll_on(struct intel_dp *intel_dp, |
| 3414 | const struct intel_crtc_state *pipe_config) |
| 3415 | { |
| 3416 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 3417 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 3418 | |
| 3419 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)assert_pipe(dev_priv, pipe_config->cpu_transcoder, 0); |
| 3420 | assert_dp_port_disabled(intel_dp)assert_dp_port((intel_dp), 0); |
| 3421 | assert_edp_pll_disabled(dev_priv)assert_edp_pll((dev_priv), 0); |
| 3422 | |
| 3423 | drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling eDP PLL for clock %d\n" , pipe_config->port_clock) |
| 3424 | pipe_config->port_clock)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling eDP PLL for clock %d\n" , pipe_config->port_clock); |
| 3425 | |
| 3426 | intel_dp->DP &= ~DP_PLL_FREQ_MASK(3 << 16); |
| 3427 | |
| 3428 | if (pipe_config->port_clock == 162000) |
| 3429 | intel_dp->DP |= DP_PLL_FREQ_162MHZ(1 << 16); |
| 3430 | else |
| 3431 | intel_dp->DP |= DP_PLL_FREQ_270MHZ(0 << 16); |
| 3432 | |
| 3433 | intel_de_write(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), intel_dp->DP); |
| 3434 | intel_de_posting_read(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) })); |
| 3435 | udelay(500); |
| 3436 | |
| 3437 | /* |
| 3438 | * [DevILK] Work around required when enabling DP PLL |
| 3439 | * while a pipe is enabled going to FDI: |
| 3440 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI |
| 3441 | * 2. Program DP PLL enable |
| 3442 | */ |
| 3443 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) |
| 3444 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
| 3445 | |
| 3446 | intel_dp->DP |= DP_PLL_ENABLE(1 << 14); |
| 3447 | |
| 3448 | intel_de_write(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), intel_dp->DP); |
| 3449 | intel_de_posting_read(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) })); |
| 3450 | udelay(200); |
| 3451 | } |
| 3452 | |
| 3453 | static void ilk_edp_pll_off(struct intel_dp *intel_dp, |
| 3454 | const struct intel_crtc_state *old_crtc_state) |
| 3455 | { |
| 3456 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 3457 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 3458 | |
| 3459 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder)assert_pipe(dev_priv, old_crtc_state->cpu_transcoder, 0); |
| 3460 | assert_dp_port_disabled(intel_dp)assert_dp_port((intel_dp), 0); |
| 3461 | assert_edp_pll_enabled(dev_priv)assert_edp_pll((dev_priv), 1); |
| 3462 | |
| 3463 | drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling eDP PLL\n" ); |
| 3464 | |
| 3465 | intel_dp->DP &= ~DP_PLL_ENABLE(1 << 14); |
| 3466 | |
| 3467 | intel_de_write(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), intel_dp->DP); |
| 3468 | intel_de_posting_read(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) })); |
| 3469 | udelay(200); |
| 3470 | } |
| 3471 | |
| 3472 | static bool_Bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) |
| 3473 | { |
| 3474 | /* |
| 3475 | * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus |
| 3476 | * be capable of signalling downstream hpd with a long pulse. |
| 3477 | * Whether or not that means D3 is safe to use is not clear, |
| 3478 | * but let's assume so until proven otherwise. |
| 3479 | * |
| 3480 | * FIXME should really check all downstream ports... |
| 3481 | */ |
| 3482 | return intel_dp->dpcd[DP_DPCD_REV0x000] == 0x11 && |
| 3483 | drm_dp_is_branch(intel_dp->dpcd) && |
| 3484 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD(1 << 3); |
| 3485 | } |
| 3486 | |
| 3487 | void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, |
| 3488 | const struct intel_crtc_state *crtc_state, |
| 3489 | bool_Bool enable) |
| 3490 | { |
| 3491 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 3492 | int ret; |
| 3493 | |
| 3494 | if (!crtc_state->dsc.compression_enable) |
| 3495 | return; |
| 3496 | |
| 3497 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE0x160, |
| 3498 | enable ? DP_DECOMPRESSION_EN(1 << 0) : 0); |
| 3499 | if (ret < 0) |
| 3500 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to %s sink decompression state\n" , enable ? "enable" : "disable") |
| 3501 | "Failed to %s sink decompression state\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to %s sink decompression state\n" , enable ? "enable" : "disable") |
| 3502 | enable ? "enable" : "disable")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to %s sink decompression state\n" , enable ? "enable" : "disable"); |
| 3503 | } |
| 3504 | |
| 3505 | /* If the device supports it, try to set the power state appropriately */ |
| 3506 | void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) |
| 3507 | { |
| 3508 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 3509 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
| 3510 | int ret, i; |
| 3511 | |
| 3512 | /* Should have a valid DPCD by this point */ |
| 3513 | if (intel_dp->dpcd[DP_DPCD_REV0x000] < 0x11) |
| 3514 | return; |
| 3515 | |
| 3516 | if (mode != DP_SET_POWER_D00x1) { |
| 3517 | if (downstream_hpd_needs_d0(intel_dp)) |
| 3518 | return; |
| 3519 | |
| 3520 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER0x600, mode); |
| 3521 | } else { |
| 3522 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
| 3523 | |
| 3524 | /* |
| 3525 | * When turning on, we need to retry for 1ms to give the sink |
| 3526 | * time to wake up. |
| 3527 | */ |
| 3528 | for (i = 0; i < 3; i++) { |
| 3529 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER0x600, mode); |
| 3530 | if (ret == 1) |
| 3531 | break; |
| 3532 | drm_msleep(1)mdelay(1); |
| 3533 | } |
| 3534 | |
| 3535 | if (ret == 1 && lspcon->active) |
| 3536 | lspcon_wait_pcon_mode(lspcon); |
| 3537 | } |
| 3538 | |
| 3539 | if (ret != 1) |
| 3540 | drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] Set power to %s failed\n" , encoder->base.base.id, encoder->base.name, mode == 0x1 ? "D0" : "D3") |
| 3541 | encoder->base.base.id, encoder->base.name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] Set power to %s failed\n" , encoder->base.base.id, encoder->base.name, mode == 0x1 ? "D0" : "D3") |
| 3542 | mode == DP_SET_POWER_D0 ? "D0" : "D3")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] Set power to %s failed\n" , encoder->base.base.id, encoder->base.name, mode == 0x1 ? "D0" : "D3"); |
| 3543 | } |
| 3544 | |
| 3545 | static bool_Bool cpt_dp_port_selected(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 3546 | enum port port, enum pipe *pipe) |
| 3547 | { |
| 3548 | enum pipe p; |
| 3549 | |
| 3550 | for_each_pipe(dev_priv, p)for ((p) = 0; (p) < I915_MAX_PIPES; (p)++) if (!((&(dev_priv )->__info)->pipe_mask & (1UL << (p)))) {} else { |
| 3551 | u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)((const i915_reg_t){ .reg = (((0xe0300) + (p) * ((0xe1300) - ( 0xe0300)))) })); |
| 3552 | |
| 3553 | if ((val & TRANS_DP_PORT_SEL_MASK(3 << 29)) == TRANS_DP_PORT_SEL(port)(((port) - PORT_B) << 29)) { |
| 3554 | *pipe = p; |
| 3555 | return true1; |
| 3556 | } |
| 3557 | } |
| 3558 | |
| 3559 | drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No pipe for DP port %c found\n" , ((port) + 'A')) |
| 3560 | port_name(port))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No pipe for DP port %c found\n" , ((port) + 'A')); |
| 3561 | |
| 3562 | /* must initialize pipe to something for the asserts */ |
| 3563 | *pipe = PIPE_A; |
| 3564 | |
| 3565 | return false0; |
| 3566 | } |
| 3567 | |
| 3568 | bool_Bool intel_dp_port_enabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 3569 | i915_reg_t dp_reg, enum port port, |
| 3570 | enum pipe *pipe) |
| 3571 | { |
| 3572 | bool_Bool ret; |
| 3573 | u32 val; |
| 3574 | |
| 3575 | val = intel_de_read(dev_priv, dp_reg); |
| 3576 | |
| 3577 | ret = val & DP_PORT_EN(1 << 31); |
| 3578 | |
| 3579 | /* asserts want to know the pipe even if the port is disabled */ |
| 3580 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) && port == PORT_A) |
| 3581 | *pipe = (val & DP_PIPE_SEL_MASK_IVB(3 << 29)) >> DP_PIPE_SEL_SHIFT_IVB29; |
| 3582 | else if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT) && port != PORT_A) |
| 3583 | ret &= cpt_dp_port_selected(dev_priv, port, pipe); |
| 3584 | else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 3585 | *pipe = (val & DP_PIPE_SEL_MASK_CHV(3 << 16)) >> DP_PIPE_SEL_SHIFT_CHV16; |
| 3586 | else |
| 3587 | *pipe = (val & DP_PIPE_SEL_MASK(1 << 30)) >> DP_PIPE_SEL_SHIFT30; |
| 3588 | |
| 3589 | return ret; |
| 3590 | } |
| 3591 | |
| 3592 | static bool_Bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 3593 | enum pipe *pipe) |
| 3594 | { |
| 3595 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 3596 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 3597 | intel_wakeref_t wakeref; |
| 3598 | bool_Bool ret; |
| 3599 | |
| 3600 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
| 3601 | encoder->power_domain); |
| 3602 | if (!wakeref) |
| 3603 | return false0; |
| 3604 | |
| 3605 | ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, |
| 3606 | encoder->port, pipe); |
| 3607 | |
| 3608 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
| 3609 | |
| 3610 | return ret; |
| 3611 | } |
| 3612 | |
| 3613 | static void intel_dp_get_config(struct intel_encoder *encoder, |
| 3614 | struct intel_crtc_state *pipe_config) |
| 3615 | { |
| 3616 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 3617 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 3618 | u32 tmp, flags = 0; |
| 3619 | enum port port = encoder->port; |
| 3620 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 3621 | |
| 3622 | if (encoder->type == INTEL_OUTPUT_EDP) |
| 3623 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP)(1UL << (INTEL_OUTPUT_EDP)); |
| 3624 | else |
| 3625 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP)(1UL << (INTEL_OUTPUT_DP)); |
| 3626 | |
| 3627 | tmp = intel_de_read(dev_priv, intel_dp->output_reg); |
| 3628 | |
| 3629 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE(1 << 6) && port != PORT_A; |
| 3630 | |
| 3631 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT) && port != PORT_A) { |
| 3632 | u32 trans_dp = intel_de_read(dev_priv, |
| 3633 | TRANS_DP_CTL(crtc->pipe)((const i915_reg_t){ .reg = (((0xe0300) + (crtc->pipe) * ( (0xe1300) - (0xe0300)))) })); |
| 3634 | |
| 3635 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH(1 << 3)) |
| 3636 | flags |= DRM_MODE_FLAG_PHSYNC(1<<0); |
| 3637 | else |
| 3638 | flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
| 3639 | |
| 3640 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH(1 << 4)) |
| 3641 | flags |= DRM_MODE_FLAG_PVSYNC(1<<2); |
| 3642 | else |
| 3643 | flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
| 3644 | } else { |
| 3645 | if (tmp & DP_SYNC_HS_HIGH(1 << 3)) |
| 3646 | flags |= DRM_MODE_FLAG_PHSYNC(1<<0); |
| 3647 | else |
| 3648 | flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
| 3649 | |
| 3650 | if (tmp & DP_SYNC_VS_HIGH(1 << 4)) |
| 3651 | flags |= DRM_MODE_FLAG_PVSYNC(1<<2); |
| 3652 | else |
| 3653 | flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
| 3654 | } |
| 3655 | |
| 3656 | pipe_config->hw.adjusted_mode.flags |= flags; |
| 3657 | |
| 3658 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) && tmp & DP_COLOR_RANGE_16_235(1 << 8)) |
| 3659 | pipe_config->limited_color_range = true1; |
| 3660 | |
| 3661 | pipe_config->lane_count = |
| 3662 | ((tmp & DP_PORT_WIDTH_MASK(7 << 19)) >> DP_PORT_WIDTH_SHIFT19) + 1; |
| 3663 | |
| 3664 | intel_dp_get_m_n(crtc, pipe_config); |
| 3665 | |
| 3666 | if (port == PORT_A) { |
| 3667 | if ((intel_de_read(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) })) & DP_PLL_FREQ_MASK(3 << 16)) == DP_PLL_FREQ_162MHZ(1 << 16)) |
| 3668 | pipe_config->port_clock = 162000; |
| 3669 | else |
| 3670 | pipe_config->port_clock = 270000; |
| 3671 | } |
| 3672 | |
| 3673 | pipe_config->hw.adjusted_mode.crtc_clock = |
| 3674 | intel_dotclock_calculate(pipe_config->port_clock, |
| 3675 | &pipe_config->dp_m_n); |
| 3676 | |
| 3677 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
| 3678 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
| 3679 | /* |
| 3680 | * This is a big fat ugly hack. |
| 3681 | * |
| 3682 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 3683 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 3684 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 3685 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 3686 | * max, not what it tells us to use. |
| 3687 | * |
| 3688 | * Note: This will still be broken if the eDP panel is not lit |
| 3689 | * up by the BIOS, and thus we can't get the mode at module |
| 3690 | * load. |
| 3691 | */ |
| 3692 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n" , pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp) |
| 3693 | "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n" , pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp) |
| 3694 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n" , pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
| 3695 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; |
| 3696 | } |
| 3697 | } |
| 3698 | |
| 3699 | static void intel_disable_dp(struct intel_atomic_state *state, |
| 3700 | struct intel_encoder *encoder, |
| 3701 | const struct intel_crtc_state *old_crtc_state, |
| 3702 | const struct drm_connector_state *old_conn_state) |
| 3703 | { |
| 3704 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 3705 | |
| 3706 | intel_dp->link_trained = false0; |
| 3707 | |
| 3708 | if (old_crtc_state->has_audio) |
| 3709 | intel_audio_codec_disable(encoder, |
| 3710 | old_crtc_state, old_conn_state); |
| 3711 | |
| 3712 | /* Make sure the panel is off before trying to change the mode. But also |
| 3713 | * ensure that we have vdd while we switch off the panel. */ |
| 3714 | intel_edp_panel_vdd_on(intel_dp); |
| 3715 | intel_edp_backlight_off(old_conn_state); |
| 3716 | intel_dp_set_power(intel_dp, DP_SET_POWER_D30x2); |
| 3717 | intel_edp_panel_off(intel_dp); |
| 3718 | } |
| 3719 | |
| 3720 | static void g4x_disable_dp(struct intel_atomic_state *state, |
| 3721 | struct intel_encoder *encoder, |
| 3722 | const struct intel_crtc_state *old_crtc_state, |
| 3723 | const struct drm_connector_state *old_conn_state) |
| 3724 | { |
| 3725 | intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); |
| 3726 | } |
| 3727 | |
| 3728 | static void vlv_disable_dp(struct intel_atomic_state *state, |
| 3729 | struct intel_encoder *encoder, |
| 3730 | const struct intel_crtc_state *old_crtc_state, |
| 3731 | const struct drm_connector_state *old_conn_state) |
| 3732 | { |
| 3733 | intel_disable_dp(state, encoder, old_crtc_state, old_conn_state); |
| 3734 | } |
| 3735 | |
| 3736 | static void g4x_post_disable_dp(struct intel_atomic_state *state, |
| 3737 | struct intel_encoder *encoder, |
| 3738 | const struct intel_crtc_state *old_crtc_state, |
| 3739 | const struct drm_connector_state *old_conn_state) |
| 3740 | { |
| 3741 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 3742 | enum port port = encoder->port; |
| 3743 | |
| 3744 | /* |
| 3745 | * Bspec does not list a specific disable sequence for g4x DP. |
| 3746 | * Follow the ilk+ sequence (disable pipe before the port) for |
| 3747 | * g4x DP as it does not suffer from underruns like the normal |
| 3748 | * g4x modeset sequence (disable pipe after the port). |
| 3749 | */ |
| 3750 | intel_dp_link_down(encoder, old_crtc_state); |
| 3751 | |
| 3752 | /* Only ilk+ has port A */ |
| 3753 | if (port == PORT_A) |
| 3754 | ilk_edp_pll_off(intel_dp, old_crtc_state); |
| 3755 | } |
| 3756 | |
| 3757 | static void vlv_post_disable_dp(struct intel_atomic_state *state, |
| 3758 | struct intel_encoder *encoder, |
| 3759 | const struct intel_crtc_state *old_crtc_state, |
| 3760 | const struct drm_connector_state *old_conn_state) |
| 3761 | { |
| 3762 | intel_dp_link_down(encoder, old_crtc_state); |
| 3763 | } |
| 3764 | |
| 3765 | static void chv_post_disable_dp(struct intel_atomic_state *state, |
| 3766 | struct intel_encoder *encoder, |
| 3767 | const struct intel_crtc_state *old_crtc_state, |
| 3768 | const struct drm_connector_state *old_conn_state) |
| 3769 | { |
| 3770 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 3771 | |
| 3772 | intel_dp_link_down(encoder, old_crtc_state); |
| 3773 | |
| 3774 | vlv_dpio_get(dev_priv); |
| 3775 | |
| 3776 | /* Assert data lane reset */ |
| 3777 | chv_data_lane_soft_reset(encoder, old_crtc_state, true1); |
| 3778 | |
| 3779 | vlv_dpio_put(dev_priv); |
| 3780 | } |
| 3781 | |
| 3782 | static void |
| 3783 | cpt_set_link_train(struct intel_dp *intel_dp, |
| 3784 | u8 dp_train_pat) |
| 3785 | { |
| 3786 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3787 | u32 *DP = &intel_dp->DP; |
| 3788 | |
| 3789 | *DP &= ~DP_LINK_TRAIN_MASK_CPT(7 << 8); |
| 3790 | |
| 3791 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK0x3) { |
| 3792 | case DP_TRAINING_PATTERN_DISABLE0: |
| 3793 | *DP |= DP_LINK_TRAIN_OFF_CPT(3 << 8); |
| 3794 | break; |
| 3795 | case DP_TRAINING_PATTERN_11: |
| 3796 | *DP |= DP_LINK_TRAIN_PAT_1_CPT(0 << 8); |
| 3797 | break; |
| 3798 | case DP_TRAINING_PATTERN_22: |
| 3799 | *DP |= DP_LINK_TRAIN_PAT_2_CPT(1 << 8); |
| 3800 | break; |
| 3801 | case DP_TRAINING_PATTERN_33: |
| 3802 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "TPS3 not supported, using TPS2 instead\n" ) |
| 3803 | "TPS3 not supported, using TPS2 instead\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "TPS3 not supported, using TPS2 instead\n" ); |
| 3804 | *DP |= DP_LINK_TRAIN_PAT_2_CPT(1 << 8); |
| 3805 | break; |
| 3806 | } |
| 3807 | |
| 3808 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
| 3809 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 3810 | } |
| 3811 | |
| 3812 | static void |
| 3813 | g4x_set_link_train(struct intel_dp *intel_dp, |
| 3814 | u8 dp_train_pat) |
| 3815 | { |
| 3816 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3817 | u32 *DP = &intel_dp->DP; |
| 3818 | |
| 3819 | *DP &= ~DP_LINK_TRAIN_MASK(3 << 28); |
| 3820 | |
| 3821 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK0x3) { |
| 3822 | case DP_TRAINING_PATTERN_DISABLE0: |
| 3823 | *DP |= DP_LINK_TRAIN_OFF(3 << 28); |
| 3824 | break; |
| 3825 | case DP_TRAINING_PATTERN_11: |
| 3826 | *DP |= DP_LINK_TRAIN_PAT_1(0 << 28); |
| 3827 | break; |
| 3828 | case DP_TRAINING_PATTERN_22: |
| 3829 | *DP |= DP_LINK_TRAIN_PAT_2(1 << 28); |
| 3830 | break; |
| 3831 | case DP_TRAINING_PATTERN_33: |
| 3832 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "TPS3 not supported, using TPS2 instead\n" ) |
| 3833 | "TPS3 not supported, using TPS2 instead\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "TPS3 not supported, using TPS2 instead\n" ); |
| 3834 | *DP |= DP_LINK_TRAIN_PAT_2(1 << 28); |
| 3835 | break; |
| 3836 | } |
| 3837 | |
| 3838 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
| 3839 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 3840 | } |
| 3841 | |
| 3842 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
| 3843 | const struct intel_crtc_state *old_crtc_state) |
| 3844 | { |
| 3845 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 3846 | |
| 3847 | /* enable with pattern 1 (as per spec) */ |
| 3848 | |
| 3849 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_11); |
| 3850 | |
| 3851 | /* |
| 3852 | * Magic for VLV/CHV. We _must_ first set up the register |
| 3853 | * without actually enabling the port, and then do another |
| 3854 | * write to enable the port. Otherwise link training will |
| 3855 | * fail when the power sequencer is freshly used for this port. |
| 3856 | */ |
| 3857 | intel_dp->DP |= DP_PORT_EN(1 << 31); |
| 3858 | if (old_crtc_state->has_audio) |
| 3859 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE(1 << 6); |
| 3860 | |
| 3861 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
| 3862 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 3863 | } |
| 3864 | |
| 3865 | void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, |
| 3866 | const struct intel_crtc_state *crtc_state) |
| 3867 | { |
| 3868 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 3869 | u8 tmp; |
| 3870 | |
| 3871 | if (intel_dp->dpcd[DP_DPCD_REV0x000] < 0x13) |
| 3872 | return; |
| 3873 | |
| 3874 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
| 3875 | return; |
| 3876 | |
| 3877 | tmp = intel_dp->has_hdmi_sink ? |
| 3878 | DP_HDMI_DVI_OUTPUT_CONFIG(1 << 0) : 0; |
| 3879 | |
| 3880 | if (drm_dp_dpcd_writeb(&intel_dp->aux, |
| 3881 | DP_PROTOCOL_CONVERTER_CONTROL_00x3050, tmp) != 1) |
| 3882 | drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter HDMI mode to %s\n" , enableddisabled(intel_dp->has_hdmi_sink)) |
| 3883 | enableddisabled(intel_dp->has_hdmi_sink))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter HDMI mode to %s\n" , enableddisabled(intel_dp->has_hdmi_sink)); |
| 3884 | |
| 3885 | tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && |
| 3886 | intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE(1 << 0) : 0; |
| 3887 | |
| 3888 | if (drm_dp_dpcd_writeb(&intel_dp->aux, |
| 3889 | DP_PROTOCOL_CONVERTER_CONTROL_10x3051, tmp) != 1) |
| 3890 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n" , enableddisabled(intel_dp->dfp.ycbcr_444_to_420)) |
| 3891 | "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n" , enableddisabled(intel_dp->dfp.ycbcr_444_to_420)) |
| 3892 | enableddisabled(intel_dp->dfp.ycbcr_444_to_420))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n" , enableddisabled(intel_dp->dfp.ycbcr_444_to_420)); |
| 3893 | |
| 3894 | tmp = 0; |
| 3895 | |
| 3896 | if (drm_dp_dpcd_writeb(&intel_dp->aux, |
| 3897 | DP_PROTOCOL_CONVERTER_CONTROL_20x3052, tmp) <= 0) |
| 3898 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n" , enableddisabled(0)) |
| 3899 | "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n" , enableddisabled(0)) |
| 3900 | enableddisabled(false))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n" , enableddisabled(0)); |
| 3901 | } |
| 3902 | |
| 3903 | static void intel_enable_dp(struct intel_atomic_state *state, |
| 3904 | struct intel_encoder *encoder, |
| 3905 | const struct intel_crtc_state *pipe_config, |
| 3906 | const struct drm_connector_state *conn_state) |
| 3907 | { |
| 3908 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 3909 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 3910 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 3911 | u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); |
| 3912 | enum pipe pipe = crtc->pipe; |
| 3913 | intel_wakeref_t wakeref; |
| 3914 | |
| 3915 | if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN)({ int __ret = !!((dp_reg & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "dp_reg & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); })) |
| 3916 | return; |
| 3917 | |
| 3918 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) { |
| 3919 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 3920 | vlv_init_panel_power_sequencer(encoder, pipe_config); |
| 3921 | |
| 3922 | intel_dp_enable_port(intel_dp, pipe_config); |
| 3923 | |
| 3924 | edp_panel_vdd_on(intel_dp); |
| 3925 | edp_panel_on(intel_dp); |
| 3926 | edp_panel_vdd_off(intel_dp, true1); |
| 3927 | } |
| 3928 | |
| 3929 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 3930 | unsigned int lane_mask = 0x0; |
| 3931 | |
| 3932 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 3933 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
| 3934 | |
| 3935 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
| 3936 | lane_mask); |
| 3937 | } |
| 3938 | |
| 3939 | intel_dp_set_power(intel_dp, DP_SET_POWER_D00x1); |
| 3940 | intel_dp_configure_protocol_converter(intel_dp, pipe_config); |
| 3941 | intel_dp_start_link_train(intel_dp); |
| 3942 | intel_dp_stop_link_train(intel_dp); |
| 3943 | |
| 3944 | if (pipe_config->has_audio) { |
| 3945 | drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Enabling DP audio on pipe %c\n" , ((pipe) + 'A')) |
| 3946 | pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Enabling DP audio on pipe %c\n" , ((pipe) + 'A')); |
| 3947 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
| 3948 | } |
| 3949 | } |
| 3950 | |
| 3951 | static void g4x_enable_dp(struct intel_atomic_state *state, |
| 3952 | struct intel_encoder *encoder, |
| 3953 | const struct intel_crtc_state *pipe_config, |
| 3954 | const struct drm_connector_state *conn_state) |
| 3955 | { |
| 3956 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
| 3957 | intel_edp_backlight_on(pipe_config, conn_state); |
| 3958 | } |
| 3959 | |
| 3960 | static void vlv_enable_dp(struct intel_atomic_state *state, |
| 3961 | struct intel_encoder *encoder, |
| 3962 | const struct intel_crtc_state *pipe_config, |
| 3963 | const struct drm_connector_state *conn_state) |
| 3964 | { |
| 3965 | intel_edp_backlight_on(pipe_config, conn_state); |
| 3966 | } |
| 3967 | |
| 3968 | static void g4x_pre_enable_dp(struct intel_atomic_state *state, |
| 3969 | struct intel_encoder *encoder, |
| 3970 | const struct intel_crtc_state *pipe_config, |
| 3971 | const struct drm_connector_state *conn_state) |
| 3972 | { |
| 3973 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 3974 | enum port port = encoder->port; |
| 3975 | |
| 3976 | intel_dp_prepare(encoder, pipe_config); |
| 3977 | |
| 3978 | /* Only ilk+ has port A */ |
| 3979 | if (port == PORT_A) |
| 3980 | ilk_edp_pll_on(intel_dp, pipe_config); |
| 3981 | } |
| 3982 | |
| 3983 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
| 3984 | { |
| 3985 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3986 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 3987 | enum pipe pipe = intel_dp->pps_pipe; |
| 3988 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61208) + (pipe) * 0x100) }); |
| 3989 | |
| 3990 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
| 3991 | |
| 3992 | if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)({ int __ret = !!((pipe != PIPE_A && pipe != PIPE_B)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "pipe != PIPE_A && pipe != PIPE_B" ")"); __builtin_expect(!!(__ret), 0); })) |
| 3993 | return; |
| 3994 | |
| 3995 | edp_panel_vdd_off_sync(intel_dp); |
| 3996 | |
| 3997 | /* |
| 3998 | * VLV seems to get confused when multiple power sequencers |
| 3999 | * have the same port selected (even if only one has power/vdd |
| 4000 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
| 4001 | * CHV on the other hand doesn't seem to mind having the same port |
| 4002 | * selected in multiple power sequencers, but let's clear the |
| 4003 | * port select always when logically disconnecting a power sequencer |
| 4004 | * from a port. |
| 4005 | */ |
| 4006 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
| 4007 | "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
| 4008 | pipe_name(pipe), dig_port->base.base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
| 4009 | dig_port->base.base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name); |
| 4010 | intel_de_write(dev_priv, pp_on_reg, 0); |
| 4011 | intel_de_posting_read(dev_priv, pp_on_reg); |
| 4012 | |
| 4013 | intel_dp->pps_pipe = INVALID_PIPE; |
| 4014 | } |
| 4015 | |
| 4016 | static void vlv_steal_power_sequencer(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 4017 | enum pipe pipe) |
| 4018 | { |
| 4019 | struct intel_encoder *encoder; |
| 4020 | |
| 4021 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 4022 | |
| 4023 | for_each_intel_dp(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) if (!(intel_encoder_is_dp (encoder))) {} else { |
| 4024 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 4025 | |
| 4026 | drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,({ int __ret = !!(intel_dp->active_pipe == pipe); if (__ret ) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }) |
| 4027 | "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",({ int __ret = !!(intel_dp->active_pipe == pipe); if (__ret ) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }) |
| 4028 | pipe_name(pipe), encoder->base.base.id,({ int __ret = !!(intel_dp->active_pipe == pipe); if (__ret ) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }) |
| 4029 | encoder->base.name)({ int __ret = !!(intel_dp->active_pipe == pipe); if (__ret ) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }); |
| 4030 | |
| 4031 | if (intel_dp->pps_pipe != pipe) |
| 4032 | continue; |
| 4033 | |
| 4034 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name) |
| 4035 | "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name) |
| 4036 | pipe_name(pipe), encoder->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name) |
| 4037 | encoder->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name); |
| 4038 | |
| 4039 | /* make sure vdd is off before we steal it */ |
| 4040 | vlv_detach_power_sequencer(intel_dp); |
| 4041 | } |
| 4042 | } |
| 4043 | |
| 4044 | static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, |
| 4045 | const struct intel_crtc_state *crtc_state) |
| 4046 | { |
| 4047 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 4048 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 4049 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 4050 | |
| 4051 | lockdep_assert_held(&dev_priv->pps_mutex)do { (void)(&dev_priv->pps_mutex); } while(0); |
| 4052 | |
| 4053 | drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->active_pipe != INVALID_PIPE)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
| 4054 | |
| 4055 | if (intel_dp->pps_pipe != INVALID_PIPE && |
| 4056 | intel_dp->pps_pipe != crtc->pipe) { |
| 4057 | /* |
| 4058 | * If another power sequencer was being used on this |
| 4059 | * port previously make sure to turn off vdd there while |
| 4060 | * we still have control of it. |
| 4061 | */ |
| 4062 | vlv_detach_power_sequencer(intel_dp); |
| 4063 | } |
| 4064 | |
| 4065 | /* |
| 4066 | * We may be stealing the power |
| 4067 | * sequencer from another port. |
| 4068 | */ |
| 4069 | vlv_steal_power_sequencer(dev_priv, crtc->pipe); |
| 4070 | |
| 4071 | intel_dp->active_pipe = crtc->pipe; |
| 4072 | |
| 4073 | if (!intel_dp_is_edp(intel_dp)) |
| 4074 | return; |
| 4075 | |
| 4076 | /* now it's all ours */ |
| 4077 | intel_dp->pps_pipe = crtc->pipe; |
| 4078 | |
| 4079 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), encoder->base.base.id, encoder ->base.name) |
| 4080 | "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), encoder->base.base.id, encoder ->base.name) |
| 4081 | pipe_name(intel_dp->pps_pipe), encoder->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), encoder->base.base.id, encoder ->base.name) |
| 4082 | encoder->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps_pipe) + 'A'), encoder->base.base.id, encoder ->base.name); |
| 4083 | |
| 4084 | /* init power sequencer on this pipe and port */ |
| 4085 | intel_dp_init_panel_power_sequencer(intel_dp); |
| 4086 | intel_dp_init_panel_power_sequencer_registers(intel_dp, true1); |
| 4087 | } |
| 4088 | |
| 4089 | static void vlv_pre_enable_dp(struct intel_atomic_state *state, |
| 4090 | struct intel_encoder *encoder, |
| 4091 | const struct intel_crtc_state *pipe_config, |
| 4092 | const struct drm_connector_state *conn_state) |
| 4093 | { |
| 4094 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
| 4095 | |
| 4096 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
| 4097 | } |
| 4098 | |
| 4099 | static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state, |
| 4100 | struct intel_encoder *encoder, |
| 4101 | const struct intel_crtc_state *pipe_config, |
| 4102 | const struct drm_connector_state *conn_state) |
| 4103 | { |
| 4104 | intel_dp_prepare(encoder, pipe_config); |
| 4105 | |
| 4106 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
| 4107 | } |
| 4108 | |
| 4109 | static void chv_pre_enable_dp(struct intel_atomic_state *state, |
| 4110 | struct intel_encoder *encoder, |
| 4111 | const struct intel_crtc_state *pipe_config, |
| 4112 | const struct drm_connector_state *conn_state) |
| 4113 | { |
| 4114 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
| 4115 | |
| 4116 | intel_enable_dp(state, encoder, pipe_config, conn_state); |
| 4117 | |
| 4118 | /* Second common lane will stay alive on its own now */ |
| 4119 | chv_phy_release_cl2_override(encoder); |
| 4120 | } |
| 4121 | |
| 4122 | static void chv_dp_pre_pll_enable(struct intel_atomic_state *state, |
| 4123 | struct intel_encoder *encoder, |
| 4124 | const struct intel_crtc_state *pipe_config, |
| 4125 | const struct drm_connector_state *conn_state) |
| 4126 | { |
| 4127 | intel_dp_prepare(encoder, pipe_config); |
| 4128 | |
| 4129 | chv_phy_pre_pll_enable(encoder, pipe_config); |
| 4130 | } |
| 4131 | |
| 4132 | static void chv_dp_post_pll_disable(struct intel_atomic_state *state, |
| 4133 | struct intel_encoder *encoder, |
| 4134 | const struct intel_crtc_state *old_crtc_state, |
| 4135 | const struct drm_connector_state *old_conn_state) |
| 4136 | { |
| 4137 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
| 4138 | } |
| 4139 | |
| 4140 | /* |
| 4141 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 4142 | * link status information |
| 4143 | */ |
| 4144 | bool_Bool |
| 4145 | intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status) |
| 4146 | { |
| 4147 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS0x202, link_status, |
| 4148 | DP_LINK_STATUS_SIZE6) == DP_LINK_STATUS_SIZE6; |
| 4149 | } |
| 4150 | |
| 4151 | static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp) |
| 4152 | { |
| 4153 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0); |
| 4154 | } |
| 4155 | |
| 4156 | static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp) |
| 4157 | { |
| 4158 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3(3 << 0); |
| 4159 | } |
| 4160 | |
| 4161 | static u8 intel_dp_pre_empemph_max_2(struct intel_dp *intel_dp) |
| 4162 | { |
| 4163 | return DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3); |
| 4164 | } |
| 4165 | |
| 4166 | static u8 intel_dp_pre_empemph_max_3(struct intel_dp *intel_dp) |
| 4167 | { |
| 4168 | return DP_TRAIN_PRE_EMPH_LEVEL_3(3 << 3); |
| 4169 | } |
| 4170 | |
| 4171 | static void vlv_set_signal_levels(struct intel_dp *intel_dp) |
| 4172 | { |
| 4173 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 4174 | unsigned long demph_reg_value, preemph_reg_value, |
| 4175 | uniqtranscale_reg_value; |
| 4176 | u8 train_set = intel_dp->train_set[0]; |
| 4177 | |
| 4178 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK(3 << 3)) { |
| 4179 | case DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4180 | preemph_reg_value = 0x0004000; |
| 4181 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4182 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4183 | demph_reg_value = 0x2B405555; |
| 4184 | uniqtranscale_reg_value = 0x552AB83A; |
| 4185 | break; |
| 4186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4187 | demph_reg_value = 0x2B404040; |
| 4188 | uniqtranscale_reg_value = 0x5548B83A; |
| 4189 | break; |
| 4190 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0): |
| 4191 | demph_reg_value = 0x2B245555; |
| 4192 | uniqtranscale_reg_value = 0x5560B83A; |
| 4193 | break; |
| 4194 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3(3 << 0): |
| 4195 | demph_reg_value = 0x2B405555; |
| 4196 | uniqtranscale_reg_value = 0x5598DA3A; |
| 4197 | break; |
| 4198 | default: |
| 4199 | return; |
| 4200 | } |
| 4201 | break; |
| 4202 | case DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4203 | preemph_reg_value = 0x0002000; |
| 4204 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4205 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4206 | demph_reg_value = 0x2B404040; |
| 4207 | uniqtranscale_reg_value = 0x5552B83A; |
| 4208 | break; |
| 4209 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4210 | demph_reg_value = 0x2B404848; |
| 4211 | uniqtranscale_reg_value = 0x5580B83A; |
| 4212 | break; |
| 4213 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0): |
| 4214 | demph_reg_value = 0x2B404040; |
| 4215 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 4216 | break; |
| 4217 | default: |
| 4218 | return; |
| 4219 | } |
| 4220 | break; |
| 4221 | case DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4222 | preemph_reg_value = 0x0000000; |
| 4223 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4224 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4225 | demph_reg_value = 0x2B305555; |
| 4226 | uniqtranscale_reg_value = 0x5570B83A; |
| 4227 | break; |
| 4228 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4229 | demph_reg_value = 0x2B2B4040; |
| 4230 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 4231 | break; |
| 4232 | default: |
| 4233 | return; |
| 4234 | } |
| 4235 | break; |
| 4236 | case DP_TRAIN_PRE_EMPH_LEVEL_3(3 << 3): |
| 4237 | preemph_reg_value = 0x0006000; |
| 4238 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4239 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4240 | demph_reg_value = 0x1B405555; |
| 4241 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 4242 | break; |
| 4243 | default: |
| 4244 | return; |
| 4245 | } |
| 4246 | break; |
| 4247 | default: |
| 4248 | return; |
| 4249 | } |
| 4250 | |
| 4251 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
| 4252 | uniqtranscale_reg_value, 0); |
| 4253 | } |
| 4254 | |
| 4255 | static void chv_set_signal_levels(struct intel_dp *intel_dp) |
| 4256 | { |
| 4257 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
| 4258 | u32 deemph_reg_value, margin_reg_value; |
| 4259 | bool_Bool uniq_trans_scale = false0; |
| 4260 | u8 train_set = intel_dp->train_set[0]; |
| 4261 | |
| 4262 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK(3 << 3)) { |
| 4263 | case DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4264 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4265 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4266 | deemph_reg_value = 128; |
| 4267 | margin_reg_value = 52; |
| 4268 | break; |
| 4269 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4270 | deemph_reg_value = 128; |
| 4271 | margin_reg_value = 77; |
| 4272 | break; |
| 4273 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0): |
| 4274 | deemph_reg_value = 128; |
| 4275 | margin_reg_value = 102; |
| 4276 | break; |
| 4277 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3(3 << 0): |
| 4278 | deemph_reg_value = 128; |
| 4279 | margin_reg_value = 154; |
| 4280 | uniq_trans_scale = true1; |
| 4281 | break; |
| 4282 | default: |
| 4283 | return; |
| 4284 | } |
| 4285 | break; |
| 4286 | case DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4287 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4288 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4289 | deemph_reg_value = 85; |
| 4290 | margin_reg_value = 78; |
| 4291 | break; |
| 4292 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4293 | deemph_reg_value = 85; |
| 4294 | margin_reg_value = 116; |
| 4295 | break; |
| 4296 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0): |
| 4297 | deemph_reg_value = 85; |
| 4298 | margin_reg_value = 154; |
| 4299 | break; |
| 4300 | default: |
| 4301 | return; |
| 4302 | } |
| 4303 | break; |
| 4304 | case DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4305 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4306 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4307 | deemph_reg_value = 64; |
| 4308 | margin_reg_value = 104; |
| 4309 | break; |
| 4310 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4311 | deemph_reg_value = 64; |
| 4312 | margin_reg_value = 154; |
| 4313 | break; |
| 4314 | default: |
| 4315 | return; |
| 4316 | } |
| 4317 | break; |
| 4318 | case DP_TRAIN_PRE_EMPH_LEVEL_3(3 << 3): |
| 4319 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4320 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4321 | deemph_reg_value = 43; |
| 4322 | margin_reg_value = 154; |
| 4323 | break; |
| 4324 | default: |
| 4325 | return; |
| 4326 | } |
| 4327 | break; |
| 4328 | default: |
| 4329 | return; |
| 4330 | } |
| 4331 | |
| 4332 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
| 4333 | margin_reg_value, uniq_trans_scale); |
| 4334 | } |
| 4335 | |
| 4336 | static u32 g4x_signal_levels(u8 train_set) |
| 4337 | { |
| 4338 | u32 signal_levels = 0; |
| 4339 | |
| 4340 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK0x3) { |
| 4341 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0): |
| 4342 | default: |
| 4343 | signal_levels |= DP_VOLTAGE_0_4(0 << 25); |
| 4344 | break; |
| 4345 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0): |
| 4346 | signal_levels |= DP_VOLTAGE_0_6(1 << 25); |
| 4347 | break; |
| 4348 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0): |
| 4349 | signal_levels |= DP_VOLTAGE_0_8(2 << 25); |
| 4350 | break; |
| 4351 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3(3 << 0): |
| 4352 | signal_levels |= DP_VOLTAGE_1_2(3 << 25); |
| 4353 | break; |
| 4354 | } |
| 4355 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK(3 << 3)) { |
| 4356 | case DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4357 | default: |
| 4358 | signal_levels |= DP_PRE_EMPHASIS_0(0 << 22); |
| 4359 | break; |
| 4360 | case DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4361 | signal_levels |= DP_PRE_EMPHASIS_3_5(1 << 22); |
| 4362 | break; |
| 4363 | case DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4364 | signal_levels |= DP_PRE_EMPHASIS_6(2 << 22); |
| 4365 | break; |
| 4366 | case DP_TRAIN_PRE_EMPH_LEVEL_3(3 << 3): |
| 4367 | signal_levels |= DP_PRE_EMPHASIS_9_5(3 << 22); |
| 4368 | break; |
| 4369 | } |
| 4370 | return signal_levels; |
| 4371 | } |
| 4372 | |
| 4373 | static void |
| 4374 | g4x_set_signal_levels(struct intel_dp *intel_dp) |
| 4375 | { |
| 4376 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 4377 | u8 train_set = intel_dp->train_set[0]; |
| 4378 | u32 signal_levels; |
| 4379 | |
| 4380 | signal_levels = g4x_signal_levels(train_set); |
| 4381 | |
| 4382 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels) |
| 4383 | signal_levels)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels); |
| 4384 | |
| 4385 | intel_dp->DP &= ~(DP_VOLTAGE_MASK(7 << 25) | DP_PRE_EMPHASIS_MASK(7 << 22)); |
| 4386 | intel_dp->DP |= signal_levels; |
| 4387 | |
| 4388 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
| 4389 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4390 | } |
| 4391 | |
| 4392 | /* SNB CPU eDP voltage swing and pre-emphasis control */ |
| 4393 | static u32 snb_cpu_edp_signal_levels(u8 train_set) |
| 4394 | { |
| 4395 | u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK0x3 | |
| 4396 | DP_TRAIN_PRE_EMPHASIS_MASK(3 << 3)); |
| 4397 | |
| 4398 | switch (signal_levels) { |
| 4399 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4400 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4401 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B(0x0 << 22); |
| 4402 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4403 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B(0x1 << 22); |
| 4404 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4405 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4406 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B(0x3a << 22); |
| 4407 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4408 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4409 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B(0x39 << 22); |
| 4410 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4411 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3(3 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4412 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B(0x38 << 22); |
| 4413 | default: |
| 4414 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"__drm_dbg(DRM_UT_KMS, "Unsupported voltage swing/pre-emphasis level:" "0x%x\n", signal_levels) |
| 4415 | "0x%x\n", signal_levels)__drm_dbg(DRM_UT_KMS, "Unsupported voltage swing/pre-emphasis level:" "0x%x\n", signal_levels); |
| 4416 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B(0x0 << 22); |
| 4417 | } |
| 4418 | } |
| 4419 | |
| 4420 | static void |
| 4421 | snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp) |
| 4422 | { |
| 4423 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 4424 | u8 train_set = intel_dp->train_set[0]; |
| 4425 | u32 signal_levels; |
| 4426 | |
| 4427 | signal_levels = snb_cpu_edp_signal_levels(train_set); |
| 4428 | |
| 4429 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels) |
| 4430 | signal_levels)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels); |
| 4431 | |
| 4432 | intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB(0x3f << 22); |
| 4433 | intel_dp->DP |= signal_levels; |
| 4434 | |
| 4435 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
| 4436 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4437 | } |
| 4438 | |
| 4439 | /* IVB CPU eDP voltage swing and pre-emphasis control */ |
| 4440 | static u32 ivb_cpu_edp_signal_levels(u8 train_set) |
| 4441 | { |
| 4442 | u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK0x3 | |
| 4443 | DP_TRAIN_PRE_EMPHASIS_MASK(3 << 3)); |
| 4444 | |
| 4445 | switch (signal_levels) { |
| 4446 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4447 | return EDP_LINK_TRAIN_400MV_0DB_IVB(0x24 << 22); |
| 4448 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4449 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB(0x2a << 22); |
| 4450 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4451 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3): |
| 4452 | return EDP_LINK_TRAIN_400MV_6DB_IVB(0x2f << 22); |
| 4453 | |
| 4454 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4455 | return EDP_LINK_TRAIN_600MV_0DB_IVB(0x30 << 22); |
| 4456 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4457 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB(0x36 << 22); |
| 4458 | |
| 4459 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3): |
| 4460 | return EDP_LINK_TRAIN_800MV_0DB_IVB(0x38 << 22); |
| 4461 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3): |
| 4462 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB(0x3e << 22); |
| 4463 | |
| 4464 | default: |
| 4465 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"__drm_dbg(DRM_UT_KMS, "Unsupported voltage swing/pre-emphasis level:" "0x%x\n", signal_levels) |
| 4466 | "0x%x\n", signal_levels)__drm_dbg(DRM_UT_KMS, "Unsupported voltage swing/pre-emphasis level:" "0x%x\n", signal_levels); |
| 4467 | return EDP_LINK_TRAIN_500MV_0DB_IVB(0x00 << 22); |
| 4468 | } |
| 4469 | } |
| 4470 | |
| 4471 | static void |
| 4472 | ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp) |
| 4473 | { |
| 4474 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 4475 | u8 train_set = intel_dp->train_set[0]; |
| 4476 | u32 signal_levels; |
| 4477 | |
| 4478 | signal_levels = ivb_cpu_edp_signal_levels(train_set); |
| 4479 | |
| 4480 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels) |
| 4481 | signal_levels)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels); |
| 4482 | |
| 4483 | intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB(0x3f << 22); |
| 4484 | intel_dp->DP |= signal_levels; |
| 4485 | |
| 4486 | intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP); |
| 4487 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4488 | } |
| 4489 | |
| 4490 | void intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
| 4491 | { |
| 4492 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 4493 | u8 train_set = intel_dp->train_set[0]; |
| 4494 | |
| 4495 | drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using vswing level %d%s\n" , train_set & 0x3, train_set & (1 << 2) ? " (max)" : "") |
| 4496 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using vswing level %d%s\n" , train_set & 0x3, train_set & (1 << 2) ? " (max)" : "") |
| 4497 | train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using vswing level %d%s\n" , train_set & 0x3, train_set & (1 << 2) ? " (max)" : ""); |
| 4498 | drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using pre-emphasis level %d%s\n" , (train_set & (3 << 3)) >> 3, train_set & (1 << 5) ? " (max)" : "") |
| 4499 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using pre-emphasis level %d%s\n" , (train_set & (3 << 3)) >> 3, train_set & (1 << 5) ? " (max)" : "") |
| 4500 | DP_TRAIN_PRE_EMPHASIS_SHIFT,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using pre-emphasis level %d%s\n" , (train_set & (3 << 3)) >> 3, train_set & (1 << 5) ? " (max)" : "") |
| 4501 | train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using pre-emphasis level %d%s\n" , (train_set & (3 << 3)) >> 3, train_set & (1 << 5) ? " (max)" : "") |
| 4502 | " (max)" : "")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using pre-emphasis level %d%s\n" , (train_set & (3 << 3)) >> 3, train_set & (1 << 5) ? " (max)" : ""); |
| 4503 | |
| 4504 | intel_dp->set_signal_levels(intel_dp); |
| 4505 | } |
| 4506 | |
| 4507 | void |
| 4508 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
| 4509 | u8 dp_train_pat) |
| 4510 | { |
| 4511 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp); |
| 4512 | u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); |
| 4513 | |
| 4514 | if (dp_train_pat & train_pat_mask) |
| 4515 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using DP training pattern TPS%d\n" , dp_train_pat & train_pat_mask) |
| 4516 | "Using DP training pattern TPS%d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using DP training pattern TPS%d\n" , dp_train_pat & train_pat_mask) |
| 4517 | dp_train_pat & train_pat_mask)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using DP training pattern TPS%d\n" , dp_train_pat & train_pat_mask); |
| 4518 | |
| 4519 | intel_dp->set_link_train(intel_dp, dp_train_pat); |
| 4520 | } |
| 4521 | |
| 4522 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
| 4523 | { |
| 4524 | if (intel_dp->set_idle_link_train) |
| 4525 | intel_dp->set_idle_link_train(intel_dp); |
| 4526 | } |
| 4527 | |
| 4528 | static void |
| 4529 | intel_dp_link_down(struct intel_encoder *encoder, |
| 4530 | const struct intel_crtc_state *old_crtc_state) |
| 4531 | { |
| 4532 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 4533 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 4534 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 4535 | enum port port = encoder->port; |
| 4536 | u32 DP = intel_dp->DP; |
| 4537 | |
| 4538 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!(((intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, intel_dp->output_reg) & (1 << 31)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 4539 | (intel_de_read(dev_priv, intel_dp->output_reg) &({ int __ret = !!(((intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, intel_dp->output_reg) & (1 << 31)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 4540 | DP_PORT_EN) == 0)({ int __ret = !!(((intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, intel_dp->output_reg) & (1 << 31)) == 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 4541 | return; |
| 4542 | |
| 4543 | drm_dbg_kms(&dev_priv->drm, "\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "\n" ); |
| 4544 | |
| 4545 | if ((IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) && port == PORT_A) || |
| 4546 | (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT) && port != PORT_A)) { |
| 4547 | DP &= ~DP_LINK_TRAIN_MASK_CPT(7 << 8); |
| 4548 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT(2 << 8); |
| 4549 | } else { |
| 4550 | DP &= ~DP_LINK_TRAIN_MASK(3 << 28); |
| 4551 | DP |= DP_LINK_TRAIN_PAT_IDLE(2 << 28); |
| 4552 | } |
| 4553 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
| 4554 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4555 | |
| 4556 | DP &= ~(DP_PORT_EN(1 << 31) | DP_AUDIO_OUTPUT_ENABLE(1 << 6)); |
| 4557 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
| 4558 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4559 | |
| 4560 | /* |
| 4561 | * HW workaround for IBX, we need to move the port |
| 4562 | * to transcoder A after disabling it to allow the |
| 4563 | * matching HDMI port to be enabled on transcoder A. |
| 4564 | */ |
| 4565 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) && crtc->pipe == PIPE_B && port != PORT_A) { |
| 4566 | /* |
| 4567 | * We get CPU/PCH FIFO underruns on the other pipe when |
| 4568 | * doing the workaround. Sweep them under the rug. |
| 4569 | */ |
| 4570 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false0); |
| 4571 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false0); |
| 4572 | |
| 4573 | /* always enable with pattern 1 (as per spec) */ |
| 4574 | DP &= ~(DP_PIPE_SEL_MASK(1 << 30) | DP_LINK_TRAIN_MASK(3 << 28)); |
| 4575 | DP |= DP_PORT_EN(1 << 31) | DP_PIPE_SEL(PIPE_A)((PIPE_A) << 30) | |
| 4576 | DP_LINK_TRAIN_PAT_1(0 << 28); |
| 4577 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
| 4578 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4579 | |
| 4580 | DP &= ~DP_PORT_EN(1 << 31); |
| 4581 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
| 4582 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
| 4583 | |
| 4584 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
| 4585 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true1); |
| 4586 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true1); |
| 4587 | } |
| 4588 | |
| 4589 | drm_msleep(intel_dp->panel_power_down_delay)mdelay(intel_dp->panel_power_down_delay); |
| 4590 | |
| 4591 | intel_dp->DP = DP; |
| 4592 | |
| 4593 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 4594 | intel_wakeref_t wakeref; |
| 4595 | |
| 4596 | with_pps_lock(intel_dp, wakeref)for ((wakeref) = pps_lock(intel_dp); (wakeref); (wakeref) = pps_unlock ((intel_dp), (wakeref))) |
| 4597 | intel_dp->active_pipe = INVALID_PIPE; |
| 4598 | } |
| 4599 | } |
| 4600 | |
| 4601 | bool_Bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) |
| 4602 | { |
| 4603 | u8 dprx = 0; |
| 4604 | |
| 4605 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST0x2210, |
| 4606 | &dprx) != 1) |
| 4607 | return false0; |
| 4608 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED(1 << 3); |
| 4609 | } |
| 4610 | |
| 4611 | static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) |
| 4612 | { |
| 4613 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 4614 | |
| 4615 | /* |
| 4616 | * Clear the cached register set to avoid using stale values |
| 4617 | * for the sinks that do not support DSC. |
| 4618 | */ |
| 4619 | memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd))__builtin_memset((intel_dp->dsc_dpcd), (0), (sizeof(intel_dp ->dsc_dpcd))); |
| 4620 | |
| 4621 | /* Clear fec_capable to avoid using stale values */ |
| 4622 | intel_dp->fec_capable = 0; |
| 4623 | |
| 4624 | /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ |
| 4625 | if (intel_dp->dpcd[DP_DPCD_REV0x000] >= 0x14 || |
| 4626 | intel_dp->edp_dpcd[0] >= DP_EDP_140x03) { |
| 4627 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT0x060, |
| 4628 | intel_dp->dsc_dpcd, |
| 4629 | sizeof(intel_dp->dsc_dpcd)) < 0) |
| 4630 | drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read DPCD register 0x%x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , 0x060) |
| 4631 | "Failed to read DPCD register 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read DPCD register 0x%x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , 0x060) |
| 4632 | DP_DSC_SUPPORT)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read DPCD register 0x%x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , 0x060); |
| 4633 | |
| 4634 | drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DSC DPCD: %*ph\n" , (int)sizeof(intel_dp->dsc_dpcd), intel_dp->dsc_dpcd) |
| 4635 | (int)sizeof(intel_dp->dsc_dpcd),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DSC DPCD: %*ph\n" , (int)sizeof(intel_dp->dsc_dpcd), intel_dp->dsc_dpcd) |
| 4636 | intel_dp->dsc_dpcd)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DSC DPCD: %*ph\n" , (int)sizeof(intel_dp->dsc_dpcd), intel_dp->dsc_dpcd); |
| 4637 | |
| 4638 | /* FEC is supported only on DP 1.4 */ |
| 4639 | if (!intel_dp_is_edp(intel_dp) && |
| 4640 | drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY0x090, |
| 4641 | &intel_dp->fec_capable) < 0) |
| 4642 | drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read FEC DPCD register\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 4643 | "Failed to read FEC DPCD register\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read FEC DPCD register\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 4644 | |
| 4645 | drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "FEC CAPABILITY: %x\n" , intel_dp->fec_capable) |
| 4646 | intel_dp->fec_capable)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "FEC CAPABILITY: %x\n" , intel_dp->fec_capable); |
| 4647 | } |
| 4648 | } |
| 4649 | |
| 4650 | static bool_Bool |
| 4651 | intel_edp_init_dpcd(struct intel_dp *intel_dp) |
| 4652 | { |
| 4653 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 4654 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
| 4655 | |
| 4656 | /* this function is meant to be called only once */ |
| 4657 | drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0)({ int __ret = !!((intel_dp->dpcd[0x000] != 0)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->dpcd[0x000] != 0" ")"); __builtin_expect(!!(__ret), 0); }); |
| 4658 | |
| 4659 | if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) |
| 4660 | return false0; |
| 4661 | |
| 4662 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
| 4663 | drm_dp_is_branch(intel_dp->dpcd)); |
| 4664 | |
| 4665 | /* |
| 4666 | * Read the eDP display control registers. |
| 4667 | * |
| 4668 | * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in |
| 4669 | * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it |
| 4670 | * set, but require eDP 1.4+ detection (e.g. for supported link rates |
| 4671 | * method). The display control registers should read zero if they're |
| 4672 | * not supported anyway. |
| 4673 | */ |
| 4674 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV0x700, |
| 4675 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
| 4676 | sizeof(intel_dp->edp_dpcd)) |
| 4677 | drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "eDP DPCD: %*ph\n" , (int)sizeof(intel_dp->edp_dpcd), intel_dp->edp_dpcd) |
| 4678 | (int)sizeof(intel_dp->edp_dpcd),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "eDP DPCD: %*ph\n" , (int)sizeof(intel_dp->edp_dpcd), intel_dp->edp_dpcd) |
| 4679 | intel_dp->edp_dpcd)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "eDP DPCD: %*ph\n" , (int)sizeof(intel_dp->edp_dpcd), intel_dp->edp_dpcd); |
| 4680 | |
| 4681 | /* |
| 4682 | * This has to be called after intel_dp->edp_dpcd is filled, PSR checks |
| 4683 | * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] |
| 4684 | */ |
| 4685 | intel_psr_init_dpcd(intel_dp); |
| 4686 | |
| 4687 | /* Clear the default sink rates */ |
| 4688 | intel_dp->num_sink_rates = 0; |
| 4689 | |
| 4690 | /* Read the eDP 1.4+ supported link rates. */ |
| 4691 | if (intel_dp->edp_dpcd[0] >= DP_EDP_140x03) { |
| 4692 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES8]; |
| 4693 | int i; |
| 4694 | |
| 4695 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES0x010, |
| 4696 | sink_rates, sizeof(sink_rates)); |
| 4697 | |
| 4698 | for (i = 0; i < ARRAY_SIZE(sink_rates)(sizeof((sink_rates)) / sizeof((sink_rates)[0])); i++) { |
| 4699 | int val = le16_to_cpu(sink_rates[i])((__uint16_t)(sink_rates[i])); |
| 4700 | |
| 4701 | if (val == 0) |
| 4702 | break; |
| 4703 | |
| 4704 | /* Value read multiplied by 200kHz gives the per-lane |
| 4705 | * link rate in kHz. The source rates are, however, |
| 4706 | * stored in terms of LS_Clk kHz. The full conversion |
| 4707 | * back to symbols is |
| 4708 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) |
| 4709 | */ |
| 4710 | intel_dp->sink_rates[i] = (val * 200) / 10; |
| 4711 | } |
| 4712 | intel_dp->num_sink_rates = i; |
| 4713 | } |
| 4714 | |
| 4715 | /* |
| 4716 | * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, |
| 4717 | * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. |
| 4718 | */ |
| 4719 | if (intel_dp->num_sink_rates) |
| 4720 | intel_dp->use_rate_select = true1; |
| 4721 | else |
| 4722 | intel_dp_set_sink_rates(intel_dp); |
| 4723 | |
| 4724 | intel_dp_set_common_rates(intel_dp); |
| 4725 | |
| 4726 | /* Read the eDP DSC DPCD registers */ |
| 4727 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) |
| 4728 | intel_dp_get_dsc_sink_cap(intel_dp); |
| 4729 | |
| 4730 | return true1; |
| 4731 | } |
| 4732 | |
| 4733 | static bool_Bool |
| 4734 | intel_dp_has_sink_count(struct intel_dp *intel_dp) |
| 4735 | { |
| 4736 | if (!intel_dp->attached_connector) |
| 4737 | return false0; |
| 4738 | |
| 4739 | return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, |
| 4740 | intel_dp->dpcd, |
| 4741 | &intel_dp->desc); |
| 4742 | } |
| 4743 | |
| 4744 | static bool_Bool |
| 4745 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
| 4746 | { |
| 4747 | int ret; |
| 4748 | |
| 4749 | if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) |
| 4750 | return false0; |
| 4751 | |
| 4752 | /* |
| 4753 | * Don't clobber cached eDP rates. Also skip re-reading |
| 4754 | * the OUI/ID since we know it won't change. |
| 4755 | */ |
| 4756 | if (!intel_dp_is_edp(intel_dp)) { |
| 4757 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
| 4758 | drm_dp_is_branch(intel_dp->dpcd)); |
| 4759 | |
| 4760 | intel_dp_set_sink_rates(intel_dp); |
| 4761 | intel_dp_set_common_rates(intel_dp); |
| 4762 | } |
| 4763 | |
| 4764 | if (intel_dp_has_sink_count(intel_dp)) { |
| 4765 | ret = drm_dp_read_sink_count(&intel_dp->aux); |
| 4766 | if (ret < 0) |
| 4767 | return false0; |
| 4768 | |
| 4769 | /* |
| 4770 | * Sink count can change between short pulse hpd hence |
| 4771 | * a member variable in intel_dp will track any changes |
| 4772 | * between short pulse interrupts. |
| 4773 | */ |
| 4774 | intel_dp->sink_count = ret; |
| 4775 | |
| 4776 | /* |
| 4777 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that |
| 4778 | * a dongle is present but no display. Unless we require to know |
| 4779 | * if a dongle is present or not, we don't need to update |
| 4780 | * downstream port information. So, an early return here saves |
| 4781 | * time from performing other operations which are not required. |
| 4782 | */ |
| 4783 | if (!intel_dp->sink_count) |
| 4784 | return false0; |
| 4785 | } |
| 4786 | |
| 4787 | return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, |
| 4788 | intel_dp->downstream_ports) == 0; |
| 4789 | } |
| 4790 | |
| 4791 | static bool_Bool |
| 4792 | intel_dp_can_mst(struct intel_dp *intel_dp) |
| 4793 | { |
| 4794 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 4795 | |
| 4796 | return i915->params.enable_dp_mst && |
| 4797 | intel_dp->can_mst && |
| 4798 | drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); |
| 4799 | } |
| 4800 | |
| 4801 | static void |
| 4802 | intel_dp_configure_mst(struct intel_dp *intel_dp) |
| 4803 | { |
| 4804 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 4805 | struct intel_encoder *encoder = |
| 4806 | &dp_to_dig_port(intel_dp)->base; |
| 4807 | bool_Bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); |
| 4808 | |
| 4809 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n" , encoder->base.base.id, encoder->base.name, yesno(intel_dp ->can_mst), yesno(sink_can_mst), yesno(i915->params.enable_dp_mst )) |
| 4810 | "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n" , encoder->base.base.id, encoder->base.name, yesno(intel_dp ->can_mst), yesno(sink_can_mst), yesno(i915->params.enable_dp_mst )) |
| 4811 | encoder->base.base.id, encoder->base.name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n" , encoder->base.base.id, encoder->base.name, yesno(intel_dp ->can_mst), yesno(sink_can_mst), yesno(i915->params.enable_dp_mst )) |
| 4812 | yesno(intel_dp->can_mst), yesno(sink_can_mst),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n" , encoder->base.base.id, encoder->base.name, yesno(intel_dp ->can_mst), yesno(sink_can_mst), yesno(i915->params.enable_dp_mst )) |
| 4813 | yesno(i915->params.enable_dp_mst))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n" , encoder->base.base.id, encoder->base.name, yesno(intel_dp ->can_mst), yesno(sink_can_mst), yesno(i915->params.enable_dp_mst )); |
| 4814 | |
| 4815 | if (!intel_dp->can_mst) |
| 4816 | return; |
| 4817 | |
| 4818 | intel_dp->is_mst = sink_can_mst && |
| 4819 | i915->params.enable_dp_mst; |
| 4820 | |
| 4821 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, |
| 4822 | intel_dp->is_mst); |
| 4823 | } |
| 4824 | |
| 4825 | static bool_Bool |
| 4826 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 4827 | { |
| 4828 | return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI0x2002, |
| 4829 | sink_irq_vector, DP_DPRX_ESI_LEN14) == |
| 4830 | DP_DPRX_ESI_LEN14; |
| 4831 | } |
| 4832 | |
| 4833 | bool_Bool |
| 4834 | intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, |
| 4835 | const struct drm_connector_state *conn_state) |
| 4836 | { |
| 4837 | /* |
| 4838 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication |
| 4839 | * of Color Encoding Format and Content Color Gamut], in order to |
| 4840 | * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. |
| 4841 | */ |
| 4842 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
| 4843 | return true1; |
| 4844 | |
| 4845 | switch (conn_state->colorspace) { |
| 4846 | case DRM_MODE_COLORIMETRY_SYCC_6015: |
| 4847 | case DRM_MODE_COLORIMETRY_OPYCC_6016: |
| 4848 | case DRM_MODE_COLORIMETRY_BT2020_YCC10: |
| 4849 | case DRM_MODE_COLORIMETRY_BT2020_RGB9: |
| 4850 | case DRM_MODE_COLORIMETRY_BT2020_CYCC8: |
| 4851 | return true1; |
| 4852 | default: |
| 4853 | break; |
| 4854 | } |
| 4855 | |
| 4856 | return false0; |
| 4857 | } |
| 4858 | |
| 4859 | static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, |
| 4860 | struct dp_sdp *sdp, size_t size) |
| 4861 | { |
| 4862 | size_t length = sizeof(struct dp_sdp); |
| 4863 | |
| 4864 | if (size < length) |
| 4865 | return -ENOSPC28; |
| 4866 | |
| 4867 | memset(sdp, 0, size)__builtin_memset((sdp), (0), (size)); |
| 4868 | |
| 4869 | /* |
| 4870 | * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 |
| 4871 | * VSC SDP Header Bytes |
| 4872 | */ |
| 4873 | sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ |
| 4874 | sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ |
| 4875 | sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ |
| 4876 | sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ |
| 4877 | |
| 4878 | /* |
| 4879 | * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as |
| 4880 | * per DP 1.4a spec. |
| 4881 | */ |
| 4882 | if (vsc->revision != 0x5) |
| 4883 | goto out; |
| 4884 | |
| 4885 | /* VSC SDP Payload for DB16 through DB18 */ |
| 4886 | /* Pixel Encoding and Colorimetry Formats */ |
| 4887 | sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ |
| 4888 | sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ |
| 4889 | |
| 4890 | switch (vsc->bpc) { |
| 4891 | case 6: |
| 4892 | /* 6bpc: 0x0 */ |
| 4893 | break; |
| 4894 | case 8: |
| 4895 | sdp->db[17] = 0x1; /* DB17[3:0] */ |
| 4896 | break; |
| 4897 | case 10: |
| 4898 | sdp->db[17] = 0x2; |
| 4899 | break; |
| 4900 | case 12: |
| 4901 | sdp->db[17] = 0x3; |
| 4902 | break; |
| 4903 | case 16: |
| 4904 | sdp->db[17] = 0x4; |
| 4905 | break; |
| 4906 | default: |
| 4907 | MISSING_CASE(vsc->bpc)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "vsc->bpc", (long)(vsc->bpc)); __builtin_expect(!!(__ret ), 0); }); |
| 4908 | break; |
| 4909 | } |
| 4910 | /* Dynamic Range and Component Bit Depth */ |
| 4911 | if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) |
| 4912 | sdp->db[17] |= 0x80; /* DB17[7] */ |
| 4913 | |
| 4914 | /* Content Type */ |
| 4915 | sdp->db[18] = vsc->content_type & 0x7; |
| 4916 | |
| 4917 | out: |
| 4918 | return length; |
| 4919 | } |
| 4920 | |
| 4921 | static ssize_t |
| 4922 | intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe, |
| 4923 | struct dp_sdp *sdp, |
| 4924 | size_t size) |
| 4925 | { |
| 4926 | size_t length = sizeof(struct dp_sdp); |
| 4927 | const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE4 + HDMI_DRM_INFOFRAME_SIZE26; |
| 4928 | unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE4 + HDMI_DRM_INFOFRAME_SIZE26]; |
| 4929 | ssize_t len; |
| 4930 | |
| 4931 | if (size < length) |
| 4932 | return -ENOSPC28; |
| 4933 | |
| 4934 | memset(sdp, 0, size)__builtin_memset((sdp), (0), (size)); |
| 4935 | |
| 4936 | len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); |
| 4937 | if (len < 0) { |
| 4938 | DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n")__drm_dbg(DRM_UT_KMS, "buffer size is smaller than hdr metadata infoframe\n" ); |
| 4939 | return -ENOSPC28; |
| 4940 | } |
| 4941 | |
| 4942 | if (len != infoframe_size) { |
| 4943 | DRM_DEBUG_KMS("wrong static hdr metadata size\n")__drm_dbg(DRM_UT_KMS, "wrong static hdr metadata size\n"); |
| 4944 | return -ENOSPC28; |
| 4945 | } |
| 4946 | |
| 4947 | /* |
| 4948 | * Set up the infoframe sdp packet for HDR static metadata. |
| 4949 | * Prepare VSC Header for SU as per DP 1.4a spec, |
| 4950 | * Table 2-100 and Table 2-101 |
| 4951 | */ |
| 4952 | |
| 4953 | /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ |
| 4954 | sdp->sdp_header.HB0 = 0; |
| 4955 | /* |
| 4956 | * Packet Type 80h + Non-audio INFOFRAME Type value |
| 4957 | * HDMI_INFOFRAME_TYPE_DRM: 0x87 |
| 4958 | * - 80h + Non-audio INFOFRAME Type value |
| 4959 | * - InfoFrame Type: 0x07 |
| 4960 | * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] |
| 4961 | */ |
| 4962 | sdp->sdp_header.HB1 = drm_infoframe->type; |
| 4963 | /* |
| 4964 | * Least Significant Eight Bits of (Data Byte Count – 1) |
| 4965 | * infoframe_size - 1 |
| 4966 | */ |
| 4967 | sdp->sdp_header.HB2 = 0x1D; |
| 4968 | /* INFOFRAME SDP Version Number */ |
| 4969 | sdp->sdp_header.HB3 = (0x13 << 2); |
| 4970 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ |
| 4971 | sdp->db[0] = drm_infoframe->version; |
| 4972 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ |
| 4973 | sdp->db[1] = drm_infoframe->length; |
| 4974 | /* |
| 4975 | * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after |
| 4976 | * HDMI_INFOFRAME_HEADER_SIZE |
| 4977 | */ |
| 4978 | BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2)extern char _ctassert[(!(sizeof(sdp->db) < 26 + 2)) ? 1 : -1 ] __attribute__((__unused__)); |
| 4979 | memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],__builtin_memcpy((&sdp->db[2]), (&buf[4]), (26)) |
| 4980 | HDMI_DRM_INFOFRAME_SIZE)__builtin_memcpy((&sdp->db[2]), (&buf[4]), (26)); |
| 4981 | |
| 4982 | /* |
| 4983 | * Size of DP infoframe sdp packet for HDR static metadata consists of |
| 4984 | * - DP SDP Header(struct dp_sdp_header): 4 bytes |
| 4985 | * - Two Data Blocks: 2 bytes |
| 4986 | * CTA Header Byte2 (INFOFRAME Version Number) |
| 4987 | * CTA Header Byte3 (Length of INFOFRAME) |
| 4988 | * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes |
| 4989 | * |
| 4990 | * Prior to GEN11's GMP register size is identical to DP HDR static metadata |
| 4991 | * infoframe size. But GEN11+ has larger than that size, write_infoframe |
| 4992 | * will pad rest of the size. |
| 4993 | */ |
| 4994 | return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE26; |
| 4995 | } |
| 4996 | |
| 4997 | static void intel_write_dp_sdp(struct intel_encoder *encoder, |
| 4998 | const struct intel_crtc_state *crtc_state, |
| 4999 | unsigned int type) |
| 5000 | { |
| 5001 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
| 5002 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 5003 | struct dp_sdp sdp = {}; |
| 5004 | ssize_t len; |
| 5005 | |
| 5006 | if ((crtc_state->infoframes.enable & |
| 5007 | intel_hdmi_infoframe_enable(type)) == 0) |
| 5008 | return; |
| 5009 | |
| 5010 | switch (type) { |
| 5011 | case DP_SDP_VSC0x07: |
| 5012 | len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, |
| 5013 | sizeof(sdp)); |
| 5014 | break; |
| 5015 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
| 5016 | len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm, |
| 5017 | &sdp, sizeof(sdp)); |
| 5018 | break; |
| 5019 | default: |
| 5020 | MISSING_CASE(type)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "type", (long)(type)); __builtin_expect(!!(__ret), 0); }); |
| 5021 | return; |
| 5022 | } |
| 5023 | |
| 5024 | if (drm_WARN_ON(&dev_priv->drm, len < 0)({ int __ret = !!((len < 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "len < 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 5025 | return; |
| 5026 | |
| 5027 | dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); |
| 5028 | } |
| 5029 | |
| 5030 | void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, |
| 5031 | const struct intel_crtc_state *crtc_state, |
| 5032 | struct drm_dp_vsc_sdp *vsc) |
| 5033 | { |
| 5034 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
| 5035 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 5036 | struct dp_sdp sdp = {}; |
| 5037 | ssize_t len; |
| 5038 | |
| 5039 | len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp)); |
| 5040 | |
| 5041 | if (drm_WARN_ON(&dev_priv->drm, len < 0)({ int __ret = !!((len < 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "len < 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 5042 | return; |
| 5043 | |
| 5044 | dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC0x07, |
| 5045 | &sdp, len); |
| 5046 | } |
| 5047 | |
| 5048 | void intel_dp_set_infoframes(struct intel_encoder *encoder, |
| 5049 | bool_Bool enable, |
| 5050 | const struct intel_crtc_state *crtc_state, |
| 5051 | const struct drm_connector_state *conn_state) |
| 5052 | { |
| 5053 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 5054 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 5055 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(crtc_state->cpu_transcoder)] - (&(dev_priv )->__info)->trans_offsets[TRANSCODER_A] + (0x60200) + ( (&(dev_priv)->__info)->display_mmio_offset))) }); |
| 5056 | u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW(1 << 12) | VIDEO_DIP_ENABLE_GCP_HSW(1 << 16) | |
| 5057 | VIDEO_DIP_ENABLE_VS_HSW(1 << 8) | VIDEO_DIP_ENABLE_GMP_HSW(1 << 4) | |
| 5058 | VIDEO_DIP_ENABLE_SPD_HSW(1 << 0) | VIDEO_DIP_ENABLE_DRM_GLK(1 << 28); |
| 5059 | u32 val = intel_de_read(dev_priv, reg); |
| 5060 | |
| 5061 | /* TODO: Add DSC case (DIP_ENABLE_PPS) */ |
| 5062 | /* When PSR is enabled, this routine doesn't disable VSC DIP */ |
| 5063 | if (intel_psr_enabled(intel_dp)) |
| 5064 | val &= ~dip_enable; |
| 5065 | else |
| 5066 | val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW(1 << 20)); |
| 5067 | |
| 5068 | if (!enable) { |
| 5069 | intel_de_write(dev_priv, reg, val); |
| 5070 | intel_de_posting_read(dev_priv, reg); |
| 5071 | return; |
| 5072 | } |
| 5073 | |
| 5074 | intel_de_write(dev_priv, reg, val); |
| 5075 | intel_de_posting_read(dev_priv, reg); |
| 5076 | |
| 5077 | /* When PSR is enabled, VSC SDP is handled by PSR routine */ |
| 5078 | if (!intel_psr_enabled(intel_dp)) |
| 5079 | intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC0x07); |
| 5080 | |
| 5081 | intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); |
| 5082 | } |
| 5083 | |
| 5084 | static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, |
| 5085 | const void *buffer, size_t size) |
| 5086 | { |
| 5087 | const struct dp_sdp *sdp = buffer; |
| 5088 | |
| 5089 | if (size < sizeof(struct dp_sdp)) |
| 5090 | return -EINVAL22; |
| 5091 | |
| 5092 | memset(vsc, 0, sizeof(*vsc))__builtin_memset((vsc), (0), (sizeof(*vsc))); |
| 5093 | |
| 5094 | if (sdp->sdp_header.HB0 != 0) |
| 5095 | return -EINVAL22; |
| 5096 | |
| 5097 | if (sdp->sdp_header.HB1 != DP_SDP_VSC0x07) |
| 5098 | return -EINVAL22; |
| 5099 | |
| 5100 | vsc->sdp_type = sdp->sdp_header.HB1; |
| 5101 | vsc->revision = sdp->sdp_header.HB2; |
| 5102 | vsc->length = sdp->sdp_header.HB3; |
| 5103 | |
| 5104 | if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || |
| 5105 | (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { |
| 5106 | /* |
| 5107 | * - HB2 = 0x2, HB3 = 0x8 |
| 5108 | * VSC SDP supporting 3D stereo + PSR |
| 5109 | * - HB2 = 0x4, HB3 = 0xe |
| 5110 | * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of |
| 5111 | * first scan line of the SU region (applies to eDP v1.4b |
| 5112 | * and higher). |
| 5113 | */ |
| 5114 | return 0; |
| 5115 | } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { |
| 5116 | /* |
| 5117 | * - HB2 = 0x5, HB3 = 0x13 |
| 5118 | * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry |
| 5119 | * Format. |
| 5120 | */ |
| 5121 | vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; |
| 5122 | vsc->colorimetry = sdp->db[16] & 0xf; |
| 5123 | vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; |
| 5124 | |
| 5125 | switch (sdp->db[17] & 0x7) { |
| 5126 | case 0x0: |
| 5127 | vsc->bpc = 6; |
| 5128 | break; |
| 5129 | case 0x1: |
| 5130 | vsc->bpc = 8; |
| 5131 | break; |
| 5132 | case 0x2: |
| 5133 | vsc->bpc = 10; |
| 5134 | break; |
| 5135 | case 0x3: |
| 5136 | vsc->bpc = 12; |
| 5137 | break; |
| 5138 | case 0x4: |
| 5139 | vsc->bpc = 16; |
| 5140 | break; |
| 5141 | default: |
| 5142 | MISSING_CASE(sdp->db[17] & 0x7)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "sdp->db[17] & 0x7", (long)(sdp->db[17] & 0x7 )); __builtin_expect(!!(__ret), 0); }); |
| 5143 | return -EINVAL22; |
| 5144 | } |
| 5145 | |
| 5146 | vsc->content_type = sdp->db[18] & 0x7; |
| 5147 | } else { |
| 5148 | return -EINVAL22; |
| 5149 | } |
| 5150 | |
| 5151 | return 0; |
| 5152 | } |
| 5153 | |
| 5154 | static int |
| 5155 | intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, |
| 5156 | const void *buffer, size_t size) |
| 5157 | { |
| 5158 | int ret; |
| 5159 | |
| 5160 | const struct dp_sdp *sdp = buffer; |
| 5161 | |
| 5162 | if (size < sizeof(struct dp_sdp)) |
| 5163 | return -EINVAL22; |
| 5164 | |
| 5165 | if (sdp->sdp_header.HB0 != 0) |
| 5166 | return -EINVAL22; |
| 5167 | |
| 5168 | if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) |
| 5169 | return -EINVAL22; |
| 5170 | |
| 5171 | /* |
| 5172 | * Least Significant Eight Bits of (Data Byte Count – 1) |
| 5173 | * 1Dh (i.e., Data Byte Count = 30 bytes). |
| 5174 | */ |
| 5175 | if (sdp->sdp_header.HB2 != 0x1D) |
| 5176 | return -EINVAL22; |
| 5177 | |
| 5178 | /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ |
| 5179 | if ((sdp->sdp_header.HB3 & 0x3) != 0) |
| 5180 | return -EINVAL22; |
| 5181 | |
| 5182 | /* INFOFRAME SDP Version Number */ |
| 5183 | if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) |
| 5184 | return -EINVAL22; |
| 5185 | |
| 5186 | /* CTA Header Byte 2 (INFOFRAME Version Number) */ |
| 5187 | if (sdp->db[0] != 1) |
| 5188 | return -EINVAL22; |
| 5189 | |
| 5190 | /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ |
| 5191 | if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE26) |
| 5192 | return -EINVAL22; |
| 5193 | |
| 5194 | ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], |
| 5195 | HDMI_DRM_INFOFRAME_SIZE26); |
| 5196 | |
| 5197 | return ret; |
| 5198 | } |
| 5199 | |
| 5200 | static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, |
| 5201 | struct intel_crtc_state *crtc_state, |
| 5202 | struct drm_dp_vsc_sdp *vsc) |
| 5203 | { |
| 5204 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
| 5205 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 5206 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 5207 | unsigned int type = DP_SDP_VSC0x07; |
| 5208 | struct dp_sdp sdp = {}; |
| 5209 | int ret; |
| 5210 | |
| 5211 | /* When PSR is enabled, VSC SDP is handled by PSR routine */ |
| 5212 | if (intel_psr_enabled(intel_dp)) |
| 5213 | return; |
| 5214 | |
| 5215 | if ((crtc_state->infoframes.enable & |
| 5216 | intel_hdmi_infoframe_enable(type)) == 0) |
| 5217 | return; |
| 5218 | |
| 5219 | dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); |
| 5220 | |
| 5221 | ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); |
| 5222 | |
| 5223 | if (ret) |
| 5224 | drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to unpack DP VSC SDP\n" ); |
| 5225 | } |
| 5226 | |
| 5227 | static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, |
| 5228 | struct intel_crtc_state *crtc_state, |
| 5229 | struct hdmi_drm_infoframe *drm_infoframe) |
| 5230 | { |
| 5231 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
| 5232 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 5233 | unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; |
| 5234 | struct dp_sdp sdp = {}; |
| 5235 | int ret; |
| 5236 | |
| 5237 | if ((crtc_state->infoframes.enable & |
| 5238 | intel_hdmi_infoframe_enable(type)) == 0) |
| 5239 | return; |
| 5240 | |
| 5241 | dig_port->read_infoframe(encoder, crtc_state, type, &sdp, |
| 5242 | sizeof(sdp)); |
| 5243 | |
| 5244 | ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, |
| 5245 | sizeof(sdp)); |
| 5246 | |
| 5247 | if (ret) |
| 5248 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to unpack DP HDR Metadata Infoframe SDP\n" ) |
| 5249 | "Failed to unpack DP HDR Metadata Infoframe SDP\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to unpack DP HDR Metadata Infoframe SDP\n" ); |
| 5250 | } |
| 5251 | |
| 5252 | void intel_read_dp_sdp(struct intel_encoder *encoder, |
| 5253 | struct intel_crtc_state *crtc_state, |
| 5254 | unsigned int type) |
| 5255 | { |
| 5256 | if (encoder->type != INTEL_OUTPUT_DDI) |
| 5257 | return; |
| 5258 | |
| 5259 | switch (type) { |
| 5260 | case DP_SDP_VSC0x07: |
| 5261 | intel_read_dp_vsc_sdp(encoder, crtc_state, |
| 5262 | &crtc_state->infoframes.vsc); |
| 5263 | break; |
| 5264 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
| 5265 | intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, |
| 5266 | &crtc_state->infoframes.drm.drm); |
| 5267 | break; |
| 5268 | default: |
| 5269 | MISSING_CASE(type)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "type", (long)(type)); __builtin_expect(!!(__ret), 0); }); |
| 5270 | break; |
| 5271 | } |
| 5272 | } |
| 5273 | |
| 5274 | static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
| 5275 | { |
| 5276 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 5277 | int status = 0; |
| 5278 | int test_link_rate; |
| 5279 | u8 test_lane_count, test_link_bw; |
| 5280 | /* (DP CTS 1.2) |
| 5281 | * 4.3.1.11 |
| 5282 | */ |
| 5283 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ |
| 5284 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT0x220, |
| 5285 | &test_lane_count); |
| 5286 | |
| 5287 | if (status <= 0) { |
| 5288 | drm_dbg_kms(&i915->drm, "Lane count read failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Lane count read failed\n" ); |
| 5289 | return DP_TEST_NAK(1 << 1); |
| 5290 | } |
| 5291 | test_lane_count &= DP_MAX_LANE_COUNT_MASK0x1f; |
| 5292 | |
| 5293 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE0x219, |
| 5294 | &test_link_bw); |
| 5295 | if (status <= 0) { |
| 5296 | drm_dbg_kms(&i915->drm, "Link Rate read failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Link Rate read failed\n" ); |
| 5297 | return DP_TEST_NAK(1 << 1); |
| 5298 | } |
| 5299 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
| 5300 | |
| 5301 | /* Validate the requested link rate and lane count */ |
| 5302 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, |
| 5303 | test_lane_count)) |
| 5304 | return DP_TEST_NAK(1 << 1); |
| 5305 | |
| 5306 | intel_dp->compliance.test_lane_count = test_lane_count; |
| 5307 | intel_dp->compliance.test_link_rate = test_link_rate; |
| 5308 | |
| 5309 | return DP_TEST_ACK(1 << 0); |
| 5310 | } |
| 5311 | |
| 5312 | static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) |
| 5313 | { |
| 5314 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 5315 | u8 test_pattern; |
| 5316 | u8 test_misc; |
| 5317 | __be16 h_width, v_height; |
| 5318 | int status = 0; |
| 5319 | |
| 5320 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ |
| 5321 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN0x221, |
| 5322 | &test_pattern); |
| 5323 | if (status <= 0) { |
| 5324 | drm_dbg_kms(&i915->drm, "Test pattern read failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Test pattern read failed\n" ); |
| 5325 | return DP_TEST_NAK(1 << 1); |
| 5326 | } |
| 5327 | if (test_pattern != DP_COLOR_RAMP0x1) |
| 5328 | return DP_TEST_NAK(1 << 1); |
| 5329 | |
| 5330 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI0x22E, |
| 5331 | &h_width, 2); |
| 5332 | if (status <= 0) { |
| 5333 | drm_dbg_kms(&i915->drm, "H Width read failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "H Width read failed\n" ); |
| 5334 | return DP_TEST_NAK(1 << 1); |
| 5335 | } |
| 5336 | |
| 5337 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI0x230, |
| 5338 | &v_height, 2); |
| 5339 | if (status <= 0) { |
| 5340 | drm_dbg_kms(&i915->drm, "V Height read failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "V Height read failed\n" ); |
| 5341 | return DP_TEST_NAK(1 << 1); |
| 5342 | } |
| 5343 | |
| 5344 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC00x232, |
| 5345 | &test_misc); |
| 5346 | if (status <= 0) { |
| 5347 | drm_dbg_kms(&i915->drm, "TEST MISC read failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "TEST MISC read failed\n" ); |
| 5348 | return DP_TEST_NAK(1 << 1); |
| 5349 | } |
| 5350 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK(3 << 1)) != DP_COLOR_FORMAT_RGB(0 << 1)) |
| 5351 | return DP_TEST_NAK(1 << 1); |
| 5352 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA(1 << 3)) |
| 5353 | return DP_TEST_NAK(1 << 1); |
| 5354 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK(7 << 5)) { |
| 5355 | case DP_TEST_BIT_DEPTH_6(0 << 5): |
| 5356 | intel_dp->compliance.test_data.bpc = 6; |
| 5357 | break; |
| 5358 | case DP_TEST_BIT_DEPTH_8(1 << 5): |
| 5359 | intel_dp->compliance.test_data.bpc = 8; |
| 5360 | break; |
| 5361 | default: |
| 5362 | return DP_TEST_NAK(1 << 1); |
| 5363 | } |
| 5364 | |
| 5365 | intel_dp->compliance.test_data.video_pattern = test_pattern; |
| 5366 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width)(__uint16_t)(__builtin_constant_p(h_width) ? (__uint16_t)(((__uint16_t )(h_width) & 0xffU) << 8 | ((__uint16_t)(h_width) & 0xff00U) >> 8) : __swap16md(h_width)); |
| 5367 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height)(__uint16_t)(__builtin_constant_p(v_height) ? (__uint16_t)((( __uint16_t)(v_height) & 0xffU) << 8 | ((__uint16_t) (v_height) & 0xff00U) >> 8) : __swap16md(v_height)); |
| 5368 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 5369 | intel_dp->compliance.test_active = true1; |
| 5370 | |
| 5371 | return DP_TEST_ACK(1 << 0); |
| 5372 | } |
| 5373 | |
| 5374 | static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) |
| 5375 | { |
| 5376 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp); |
| 5377 | u8 test_result = DP_TEST_ACK(1 << 0); |
| 5378 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
| 5379 | struct drm_connector *connector = &intel_connector->base; |
| 5380 | |
| 5381 | if (intel_connector->detect_edid == NULL((void *)0) || |
| 5382 | connector->edid_corrupt || |
| 5383 | intel_dp->aux.i2c_defer_count > 6) { |
| 5384 | /* Check EDID read for NACKs, DEFERs and corruption |
| 5385 | * (DP CTS 1.2 Core r1.1) |
| 5386 | * 4.2.2.4 : Failed EDID read, I2C_NAK |
| 5387 | * 4.2.2.5 : Failed EDID read, I2C_DEFER |
| 5388 | * 4.2.2.6 : EDID corruption detected |
| 5389 | * Use failsafe mode for all cases |
| 5390 | */ |
| 5391 | if (intel_dp->aux.i2c_nack_count > 0 || |
| 5392 | intel_dp->aux.i2c_defer_count > 0) |
| 5393 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "EDID read had %d NACKs, %d DEFERs\n" , intel_dp->aux.i2c_nack_count, intel_dp->aux.i2c_defer_count ) |
| 5394 | "EDID read had %d NACKs, %d DEFERs\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "EDID read had %d NACKs, %d DEFERs\n" , intel_dp->aux.i2c_nack_count, intel_dp->aux.i2c_defer_count ) |
| 5395 | intel_dp->aux.i2c_nack_count,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "EDID read had %d NACKs, %d DEFERs\n" , intel_dp->aux.i2c_nack_count, intel_dp->aux.i2c_defer_count ) |
| 5396 | intel_dp->aux.i2c_defer_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "EDID read had %d NACKs, %d DEFERs\n" , intel_dp->aux.i2c_nack_count, intel_dp->aux.i2c_defer_count ); |
| 5397 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE(3 << 0); |
| 5398 | } else { |
| 5399 | struct edid *block = intel_connector->detect_edid; |
| 5400 | |
| 5401 | /* We have to write the checksum |
| 5402 | * of the last block read |
| 5403 | */ |
| 5404 | block += intel_connector->detect_edid->extensions; |
| 5405 | |
| 5406 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM0x261, |
| 5407 | block->checksum) <= 0) |
| 5408 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to write EDID checksum\n" ) |
| 5409 | "Failed to write EDID checksum\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Failed to write EDID checksum\n" ); |
| 5410 | |
| 5411 | test_result = DP_TEST_ACK(1 << 0) | DP_TEST_EDID_CHECKSUM_WRITE(1 << 2); |
| 5412 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED(1 << 0); |
| 5413 | } |
| 5414 | |
| 5415 | /* Set test active flag here so userspace doesn't interrupt things */ |
| 5416 | intel_dp->compliance.test_active = true1; |
| 5417 | |
| 5418 | return test_result; |
| 5419 | } |
| 5420 | |
| 5421 | static u8 intel_dp_prepare_phytest(struct intel_dp *intel_dp) |
| 5422 | { |
| 5423 | struct drm_dp_phy_test_params *data = |
| 5424 | &intel_dp->compliance.test_data.phytest; |
| 5425 | |
| 5426 | if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { |
| 5427 | DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n")__drm_dbg(DRM_UT_KMS, "DP Phy Test pattern AUX read failure\n" ); |
| 5428 | return DP_TEST_NAK(1 << 1); |
| 5429 | } |
| 5430 | |
| 5431 | /* |
| 5432 | * link_mst is set to false to avoid executing mst related code |
| 5433 | * during compliance testing. |
| 5434 | */ |
| 5435 | intel_dp->link_mst = false0; |
| 5436 | |
| 5437 | return DP_TEST_ACK(1 << 0); |
| 5438 | } |
| 5439 | |
| 5440 | static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp) |
| 5441 | { |
| 5442 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 5443 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
| 5444 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 5445 | struct drm_dp_phy_test_params *data = |
| 5446 | &intel_dp->compliance.test_data.phytest; |
| 5447 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (dig_port->base.base.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5448 | enum pipe pipe = crtc->pipe; |
| 5449 | u32 pattern_val; |
| 5450 | |
| 5451 | switch (data->phy_pattern) { |
| 5452 | case DP_PHY_TEST_PATTERN_NONE0x0: |
| 5453 | DRM_DEBUG_KMS("Disable Phy Test Pattern\n")__drm_dbg(DRM_UT_KMS, "Disable Phy Test Pattern\n"); |
| 5454 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe)((const i915_reg_t){ .reg = (((0x605F0) + (pipe) * ((0x615F0) - (0x605F0)))) }), 0x0); |
| 5455 | break; |
| 5456 | case DP_PHY_TEST_PATTERN_D10_20x1: |
| 5457 | DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n")__drm_dbg(DRM_UT_KMS, "Set D10.2 Phy Test Pattern\n"); |
| 5458 | intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe)((const i915_reg_t){ .reg = (((0x605F0) + (pipe) * ((0x615F0) - (0x605F0)))) }), |
| 5459 | DDI_DP_COMP_CTL_ENABLE(1 << 31) | DDI_DP_COMP_CTL_D10_2(0 << 28)); |
| 5460 | break; |
| 5461 | case DP_PHY_TEST_PATTERN_ERROR_COUNT0x2: |
| 5462 | DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n")__drm_dbg(DRM_UT_KMS, "Set Error Count Phy Test Pattern\n"); |