Bug Summary

File:dev/usb/if_run.c
Warning:line 1306, column 36
The left operand of '&' is a garbage value

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name if_run.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/usb/if_run.c
1/* $OpenBSD: if_run.c,v 1.135 2021/11/22 10:17:14 mglocker Exp $ */
2
3/*-
4 * Copyright (c) 2008-2010 Damien Bergamini <damien.bergamini@free.fr>
5 * Copyright (c) 2013-2014 Kevin Lo
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20/*-
21 * Ralink Technology RT2700U/RT2800U/RT3000U/RT3900E chipset driver.
22 * http://www.ralinktech.com/
23 */
24
25#include "bpfilter.h"
26
27#include <sys/param.h>
28#include <sys/sockio.h>
29#include <sys/mbuf.h>
30#include <sys/kernel.h>
31#include <sys/socket.h>
32#include <sys/systm.h>
33#include <sys/timeout.h>
34#include <sys/conf.h>
35#include <sys/device.h>
36#include <sys/endian.h>
37
38#include <machine/intr.h>
39
40#if NBPFILTER1 > 0
41#include <net/bpf.h>
42#endif
43#include <net/if.h>
44#include <net/if_dl.h>
45#include <net/if_media.h>
46
47#include <netinet/in.h>
48#include <netinet/if_ether.h>
49
50#include <net80211/ieee80211_var.h>
51#include <net80211/ieee80211_amrr.h>
52#include <net80211/ieee80211_radiotap.h>
53
54#include <dev/usb/usb.h>
55#include <dev/usb/usbdi.h>
56#include <dev/usb/usbdi_util.h>
57#include <dev/usb/usbdevs.h>
58
59#include <dev/ic/rt2860reg.h> /* shared with ral(4) */
60#include <dev/usb/if_runvar.h>
61
62#ifdef RUN_DEBUG
63#define DPRINTF(x) do { if (run_debug) printf x; } while (0)
64#define DPRINTFN(n, x) do { if (run_debug >= (n)) printf x; } while (0)
65int run_debug = 0;
66#else
67#define DPRINTF(x)
68#define DPRINTFN(n, x)
69#endif
70
71#define USB_ID(v, p){ USB_VENDOR_v, USB_PRODUCT_v_p } { USB_VENDOR_##v, USB_PRODUCT_##v##_##p }
72static const struct usb_devno run_devs[] = {
73 USB_ID(ABOCOM, RT2770){ 0x07b8, 0x2770 },
74 USB_ID(ABOCOM, RT2870){ 0x07b8, 0x2870 },
75 USB_ID(ABOCOM, RT3070){ 0x07b8, 0x3070 },
76 USB_ID(ABOCOM, RT3071){ 0x07b8, 0x3071 },
77 USB_ID(ABOCOM, RT3072){ 0x07b8, 0x3072 },
78 USB_ID(ABOCOM2, RT2870_1){ 0x1482, 0x3c09 },
79 USB_ID(ACCTON, RT2770){ 0x083a, 0x7512 },
80 USB_ID(ACCTON, RT2870_1){ 0x083a, 0xb522 },
81 USB_ID(ACCTON, RT2870_2){ 0x083a, 0x6618 },
82 USB_ID(ACCTON, RT2870_3){ 0x083a, 0x7522 },
83 USB_ID(ACCTON, RT2870_4){ 0x083a, 0xa618 },
84 USB_ID(ACCTON, RT2870_5){ 0x083a, 0x8522 },
85 USB_ID(ACCTON, RT3070){ 0x083a, 0x7511 },
86 USB_ID(ACCTON, RT3070_1){ 0x083a, 0xa701 },
87 USB_ID(ACCTON, RT3070_2){ 0x083a, 0xa702 },
88 USB_ID(ACCTON, RT3070_3){ 0x083a, 0xc522 },
89 USB_ID(ACCTON, RT3070_4){ 0x083a, 0xa512 },
90 USB_ID(ACCTON, RT3070_5){ 0x083a, 0xd522 },
91 USB_ID(ACCTON, RT3070_6){ 0x083a, 0xa703 },
92 USB_ID(AIRTIES, RT3070){ 0x1eda, 0x2310 },
93 USB_ID(AIRTIES, RT3070_2){ 0x1eda, 0x2012 },
94 USB_ID(ALLWIN, RT2070){ 0x8516, 0x2070 },
95 USB_ID(ALLWIN, RT2770){ 0x8516, 0x2770 },
96 USB_ID(ALLWIN, RT2870){ 0x8516, 0x2870 },
97 USB_ID(ALLWIN, RT3070){ 0x8516, 0x3070 },
98 USB_ID(ALLWIN, RT3071){ 0x8516, 0x3071 },
99 USB_ID(ALLWIN, RT3072){ 0x8516, 0x3072 },
100 USB_ID(ALLWIN, RT3572){ 0x8516, 0x3572 },
101 USB_ID(AMIGO, RT2870_1){ 0x0e0b, 0x9031 },
102 USB_ID(AMIGO, RT2870_2){ 0x0e0b, 0x9041 },
103 USB_ID(AMIT, CGWLUSB2GNR){ 0x18c5, 0x0008 },
104 USB_ID(AMIT, RT2870_1){ 0x18c5, 0x0012 },
105 USB_ID(AMIT2, RT2870){ 0x15c5, 0x0008 },
106 USB_ID(ASUS, RT2870_1){ 0x0b05, 0x1731 },
107 USB_ID(ASUS, RT2870_2){ 0x0b05, 0x1732 },
108 USB_ID(ASUS, RT2870_3){ 0x0b05, 0x1742 },
109 USB_ID(ASUS, RT2870_4){ 0x0b05, 0x1760 },
110 USB_ID(ASUS, RT2870_5){ 0x0b05, 0x1761 },
111 USB_ID(ASUS, RT3070_1){ 0x0b05, 0x1790 },
112 USB_ID(ASUS, USBN13){ 0x0b05, 0x1784 },
113 USB_ID(ASUS, USBN53){ 0x0b05, 0x179d },
114 USB_ID(ASUS, USBN66){ 0x0b05, 0x17ad },
115 USB_ID(ASUS2, USBN11){ 0x1761, 0x0b05 },
116 USB_ID(AZUREWAVE, RT2870_1){ 0x13d3, 0x3247 },
117 USB_ID(AZUREWAVE, RT2870_2){ 0x13d3, 0x3262 },
118 USB_ID(AZUREWAVE, RT3070_1){ 0x13d3, 0x3273 },
119 USB_ID(AZUREWAVE, RT3070_2){ 0x13d3, 0x3284 },
120 USB_ID(AZUREWAVE, RT3070_3){ 0x13d3, 0x3305 },
121 USB_ID(AZUREWAVE, RT3070_4){ 0x13d3, 0x3307 },
122 USB_ID(AZUREWAVE, RT3070_5){ 0x13d3, 0x3321 },
123 USB_ID(BELKIN, F9L1103){ 0x050d, 0x1103 },
124 USB_ID(BELKIN, F5D8053V3){ 0x050d, 0x815c },
125 USB_ID(BELKIN, F5D8055){ 0x050d, 0x825a },
126 USB_ID(BELKIN, F5D8055V2){ 0x050d, 0x825b },
127 USB_ID(BELKIN, F6D4050V1){ 0x050d, 0x935a },
128 USB_ID(BELKIN, F6D4050V2){ 0x050d, 0x935b },
129 USB_ID(BELKIN, F7D1101V2){ 0x050d, 0x945b },
130 USB_ID(BELKIN, RT2870_1){ 0x050d, 0x8053 },
131 USB_ID(BELKIN, RT2870_2){ 0x050d, 0x805c },
132 USB_ID(BEWAN, RT3070){ 0x07fa, 0x7712 },
133 USB_ID(CISCOLINKSYS, AE1000){ 0x13b1, 0x002f },
134 USB_ID(CISCOLINKSYS, AM10){ 0x13b1, 0x0031 },
135 USB_ID(CISCOLINKSYS2, RT3070){ 0x167b, 0x4001 },
136 USB_ID(CISCOLINKSYS3, RT3070){ 0x05a6, 0x0101 },
137 USB_ID(CONCEPTRONIC2, RT2870_1){ 0x14b2, 0x3c06 },
138 USB_ID(CONCEPTRONIC2, RT2870_2){ 0x14b2, 0x3c07 },
139 USB_ID(CONCEPTRONIC2, RT2870_3){ 0x14b2, 0x3c23 },
140 USB_ID(CONCEPTRONIC2, RT2870_5){ 0x14b2, 0x3c27 },
141 USB_ID(CONCEPTRONIC2, RT2870_6){ 0x14b2, 0x3c28 },
142 USB_ID(CONCEPTRONIC2, RT2870_7){ 0x14b2, 0x3c09 },
143 USB_ID(CONCEPTRONIC2, RT2870_8){ 0x14b2, 0x3c12 },
144 USB_ID(CONCEPTRONIC2, RT3070_1){ 0x14b2, 0x3c08 },
145 USB_ID(CONCEPTRONIC2, RT3070_2){ 0x14b2, 0x3c11 },
146 USB_ID(CONCEPTRONIC2, RT3070_3){ 0x14b2, 0x3c2c },
147 USB_ID(CONCEPTRONIC2, VIGORN61){ 0x14b2, 0x3c25 },
148 USB_ID(COREGA, CGWLUSB300GNM){ 0x07aa, 0x0042 },
149 USB_ID(COREGA, RT2870_1){ 0x07aa, 0x002f },
150 USB_ID(COREGA, RT2870_2){ 0x07aa, 0x003c },
151 USB_ID(COREGA, RT2870_3){ 0x07aa, 0x003f },
152 USB_ID(COREGA, RT3070){ 0x07aa, 0x0041 },
153 USB_ID(CYBERTAN, RT2870){ 0x129b, 0x1828 },
154 USB_ID(DLINK, DWA125B2){ 0x2001, 0x3c1e },
155 USB_ID(DLINK, DWA127){ 0x2001, 0x3c1b },
156 USB_ID(DLINK, DWA130F1){ 0x2001, 0x3c25 },
157 USB_ID(DLINK, DWA137A1){ 0x2001, 0x3317 },
158 USB_ID(DLINK, DWA140B3){ 0x2001, 0x3c15 },
159 USB_ID(DLINK, DWA140D1){ 0x2001, 0x3c20 },
160 USB_ID(DLINK, DWA160B2){ 0x2001, 0x3c1a },
161 USB_ID(DLINK, DWA162){ 0x2001, 0x3c1f },
162 USB_ID(DLINK, RT2870){ 0x2001, 0x3c09 },
163 USB_ID(DLINK, RT3072){ 0x2001, 0x3c0a },
164 USB_ID(DLINK2, DWA130){ 0x07d1, 0x3c13 },
165 USB_ID(DLINK2, RT2870_1){ 0x07d1, 0x3c09 },
166 USB_ID(DLINK2, RT2870_2){ 0x07d1, 0x3c11 },
167 USB_ID(DLINK2, RT3070_1){ 0x07d1, 0x3c0d },
168 USB_ID(DLINK2, RT3070_2){ 0x07d1, 0x3c0e },
169 USB_ID(DLINK2, RT3070_3){ 0x07d1, 0x3c0f },
170 USB_ID(DLINK2, RT3070_4){ 0x07d1, 0x3c15 },
171 USB_ID(DLINK2, RT3070_5){ 0x07d1, 0x3c16 },
172 USB_ID(DLINK2, RT3072){ 0x07d1, 0x3c0a },
173 USB_ID(DLINK2, RT3072_1){ 0x07d1, 0x3c0b },
174 USB_ID(DVICO, RT3070){ 0x0fe9, 0xb307 },
175 USB_ID(EDIMAX, EW7717){ 0x7392, 0x7717 },
176 USB_ID(EDIMAX, EW7718){ 0x7392, 0x7718 },
177 USB_ID(EDIMAX, EW7722UTN){ 0x7392, 0x7722 },
178 USB_ID(EDIMAX, RT2870_1){ 0x7392, 0x7711 },
179 USB_ID(ENCORE, RT3070_1){ 0x203d, 0x1480 },
180 USB_ID(ENCORE, RT3070_2){ 0x203d, 0x14a1 },
181 USB_ID(ENCORE, RT3070_3){ 0x203d, 0x14a9 },
182 USB_ID(GIGABYTE, GNWB31N){ 0x1044, 0x800c },
183 USB_ID(GIGABYTE, GNWB32L){ 0x1044, 0x800d },
184 USB_ID(GIGABYTE, RT2870_1){ 0x1044, 0x800b },
185 USB_ID(GIGASET, RT3070_1){ 0x1690, 0x0740 },
186 USB_ID(GIGASET, RT3070_2){ 0x1690, 0x0744 },
187 USB_ID(GUILLEMOT, HWNU300){ 0x06f8, 0xe030 },
188 USB_ID(HAWKING, HWDN2){ 0x0e66, 0x000b },
189 USB_ID(HAWKING, HWUN2){ 0x0e66, 0x0009 },
190 USB_ID(HAWKING, RT2870_1){ 0x0e66, 0x0001 },
191 USB_ID(HAWKING, RT2870_2){ 0x0e66, 0x0003 },
192 USB_ID(HAWKING, RT2870_3){ 0x0e66, 0x0013 },
193 USB_ID(HAWKING, RT2870_4){ 0x0e66, 0x0017 },
194 USB_ID(HAWKING, RT2870_5){ 0x0e66, 0x0018 },
195 USB_ID(IODATA, RT3072_1){ 0x04bb, 0x0944 },
196 USB_ID(IODATA, RT3072_2){ 0x04bb, 0x0945 },
197 USB_ID(IODATA, RT3072_3){ 0x04bb, 0x0947 },
198 USB_ID(IODATA, RT3072_4){ 0x04bb, 0x0948 },
199 USB_ID(LINKSYS4, RT3070){ 0x1737, 0x0078 },
200 USB_ID(LINKSYS4, WUSB100){ 0x1737, 0x0070 },
201 USB_ID(LINKSYS4, WUSB54GCV3){ 0x1737, 0x0077 },
202 USB_ID(LINKSYS4, WUSB600N){ 0x1737, 0x0071 },
203 USB_ID(LINKSYS4, WUSB600NV2){ 0x1737, 0x0079 },
204 USB_ID(LOGITEC, LANW150NU2){ 0x0789, 0x0168 },
205 USB_ID(LOGITEC, LANW300NU2){ 0x0789, 0x0166 },
206 USB_ID(LOGITEC, LANW300NU2S){ 0x0789, 0x0169 },
207 USB_ID(LOGITEC, RT2870_1){ 0x0789, 0x0162 },
208 USB_ID(LOGITEC, RT2870_2){ 0x0789, 0x0163 },
209 USB_ID(LOGITEC, RT2870_3){ 0x0789, 0x0164 },
210 USB_ID(MELCO, RT2870_1){ 0x0411, 0x0148 },
211 USB_ID(MELCO, RT2870_2){ 0x0411, 0x0150 },
212 USB_ID(MELCO, WLIUCAG300N){ 0x0411, 0x012e },
213 USB_ID(MELCO, WLIUCG300N){ 0x0411, 0x00e8 },
214 USB_ID(MELCO, WLIUCG301N){ 0x0411, 0x016f },
215 USB_ID(MELCO, WLIUCGN){ 0x0411, 0x015d },
216 USB_ID(MELCO, WLIUCGNHP){ 0x0411, 0x0158 },
217 USB_ID(MELCO, WLIUCGNM){ 0x0411, 0x01a2 },
218 USB_ID(MELCO, WLIUCGNM2){ 0x0411, 0x01ee },
219 USB_ID(MOTOROLA4, RT2770){ 0x100d, 0x9031 },
220 USB_ID(MOTOROLA4, RT3070){ 0x100d, 0x9032 },
221 USB_ID(MSI, RT3070_1){ 0x0db0, 0x3820 },
222 USB_ID(MSI, RT3070_2){ 0x0db0, 0x3821 },
223 USB_ID(MSI, RT3070_3){ 0x0db0, 0x3870 },
224 USB_ID(MSI, RT3070_4){ 0x0db0, 0x6899 },
225 USB_ID(MSI, RT3070_5){ 0x0db0, 0x821a },
226 USB_ID(MSI, RT3070_6){ 0x0db0, 0x870a },
227 USB_ID(MSI, RT3070_7){ 0x0db0, 0x899a },
228 USB_ID(MSI, RT3070_8){ 0x0db0, 0x3822 },
229 USB_ID(MSI, RT3070_9){ 0x0db0, 0x3871 },
230 USB_ID(MSI, RT3070_10){ 0x0db0, 0x822a },
231 USB_ID(MSI, RT3070_11){ 0x0db0, 0x871a },
232 USB_ID(MSI, RT3070_12){ 0x0db0, 0x822b },
233 USB_ID(MSI, RT3070_13){ 0x0db0, 0x822c },
234 USB_ID(MSI, RT3070_14){ 0x0db0, 0x871b },
235 USB_ID(MSI, RT3070_15){ 0x0db0, 0x871c },
236 USB_ID(OVISLINK, RT3071){ 0x1b75, 0x3071 },
237 USB_ID(OVISLINK, RT3072){ 0x1b75, 0x3072 },
238 USB_ID(PARA, RT3070){ 0x20b8, 0x8888 },
239 USB_ID(PEGATRON, RT2870){ 0x1d4d, 0x0002 },
240 USB_ID(PEGATRON, RT3070){ 0x1d4d, 0x000c },
241 USB_ID(PEGATRON, RT3070_2){ 0x1d4d, 0x000e },
242 USB_ID(PEGATRON, RT3070_3){ 0x1d4d, 0x0010 },
243 USB_ID(PEGATRON, RT3072){ 0x1d4d, 0x0011 },
244 USB_ID(PHILIPS, RT2870){ 0x0471, 0x200f },
245 USB_ID(PLANEX2, GWUS300MINIS){ 0x2019, 0xab24 },
246 USB_ID(PLANEX2, GWUSMICRO300){ 0x2019, 0xab29 },
247 USB_ID(PLANEX2, GWUSMICRON){ 0x2019, 0xed14 },
248 USB_ID(PLANEX2, RT2870){ 0x2019, 0xed06 },
249 USB_ID(PLANEX2, RT3070){ 0x2019, 0xab25 },
250 USB_ID(QCOM, RT2870){ 0x18e8, 0x6259 },
251 USB_ID(QUANTA, RT3070){ 0x1a32, 0x0304 },
252 USB_ID(RALINK, RT2070){ 0x148f, 0x2070 },
253 USB_ID(RALINK, RT2770){ 0x148f, 0x2770 },
254 USB_ID(RALINK, RT2870){ 0x148f, 0x2870 },
255 USB_ID(RALINK, RT3070){ 0x148f, 0x3070 },
256 USB_ID(RALINK, RT3071){ 0x148f, 0x3071 },
257 USB_ID(RALINK, RT3072){ 0x148f, 0x3072 },
258 USB_ID(RALINK, RT3370){ 0x148f, 0x3370 },
259 USB_ID(RALINK, RT3572){ 0x148f, 0x3572 },
260 USB_ID(RALINK, RT3573){ 0x148f, 0x3573 },
261 USB_ID(RALINK, RT5370){ 0x148f, 0x5370 },
262 USB_ID(RALINK, RT5572){ 0x148f, 0x5572 },
263 USB_ID(RALINK, RT8070){ 0x148f, 0x8070 },
264 USB_ID(SAMSUNG, WIS09ABGN){ 0x055d, 0x2018 },
265 USB_ID(SAMSUNG2, RT2870_1){ 0x04e8, 0x2018 },
266 USB_ID(SENAO, RT2870_1){ 0x1740, 0x9701 },
267 USB_ID(SENAO, RT2870_2){ 0x1740, 0x9702 },
268 USB_ID(SENAO, RT2870_3){ 0x1740, 0x0605 },
269 USB_ID(SENAO, RT2870_4){ 0x1740, 0x0615 },
270 USB_ID(SENAO, RT3070){ 0x1740, 0x9703 },
271 USB_ID(SENAO, RT3071){ 0x1740, 0x9705 },
272 USB_ID(SENAO, RT3072_1){ 0x1740, 0x9706 },
273 USB_ID(SENAO, RT3072_2){ 0x1740, 0x9707 },
274 USB_ID(SENAO, RT3072_3){ 0x1740, 0x9708 },
275 USB_ID(SENAO, RT3072_4){ 0x1740, 0x9709 },
276 USB_ID(SENAO, RT3072_5){ 0x1740, 0x9801 },
277 USB_ID(SITECOMEU, WL302){ 0x0df6, 0x002d },
278 USB_ID(SITECOMEU, WL315){ 0x0df6, 0x0039 },
279 USB_ID(SITECOMEU, WL321){ 0x0df6, 0x003b },
280 USB_ID(SITECOMEU, RT3070_3){ 0x0df6, 0x003c },
281 USB_ID(SITECOMEU, WL302){ 0x0df6, 0x002d },
282 USB_ID(SITECOMEU, WL344){ 0x0df6, 0x0040 },
283 USB_ID(SITECOMEU, WL329){ 0x0df6, 0x0041 },
284 USB_ID(SITECOMEU, WL345){ 0x0df6, 0x0042 },
285 USB_ID(SITECOMEU, RT2870_1){ 0x0df6, 0x0017 },
286 USB_ID(SITECOMEU, RT2870_2){ 0x0df6, 0x002b },
287 USB_ID(SITECOMEU, RT2870_3){ 0x0df6, 0x002c },
288 USB_ID(SITECOMEU, RT3070_1){ 0x0df6, 0x0051 },
289 USB_ID(SITECOMEU, RT3072_3){ 0x0df6, 0x0047 },
290 USB_ID(SITECOMEU, RT3072_4){ 0x0df6, 0x0048 },
291 USB_ID(SITECOMEU, RT3072_5){ 0x0df6, 0x005f },
292 USB_ID(SITECOMEU, RT3072_6){ 0x0df6, 0x004d },
293 USB_ID(SITECOMEU, WL302){ 0x0df6, 0x002d },
294 USB_ID(SITECOMEU, WL315){ 0x0df6, 0x0039 },
295 USB_ID(SITECOMEU, WL321){ 0x0df6, 0x003b },
296 USB_ID(SITECOMEU, WL324){ 0x0df6, 0x003d },
297 USB_ID(SITECOMEU, WL329){ 0x0df6, 0x0041 },
298 USB_ID(SITECOMEU, WL343){ 0x0df6, 0x003e },
299 USB_ID(SITECOMEU, WL344){ 0x0df6, 0x0040 },
300 USB_ID(SITECOMEU, WL345){ 0x0df6, 0x0042 },
301 USB_ID(SITECOMEU, WL349V4){ 0x0df6, 0x0050 },
302 USB_ID(SITECOMEU, WL608){ 0x0df6, 0x003f },
303 USB_ID(SITECOMEU, WLA4000){ 0x0df6, 0x0060 },
304 USB_ID(SITECOMEU, WLA5000){ 0x0df6, 0x0062 },
305 USB_ID(SPARKLAN, RT2870_1){ 0x15a9, 0x0006 },
306 USB_ID(SPARKLAN, RT2870_2){ 0x15a9, 0x0012 },
307 USB_ID(SPARKLAN, RT3070){ 0x15a9, 0x0010 },
308 USB_ID(SWEEX2, LW153){ 0x177f, 0x0153 },
309 USB_ID(SWEEX2, LW303){ 0x177f, 0x0302 },
310 USB_ID(SWEEX2, LW313){ 0x177f, 0x0313 },
311 USB_ID(TOSHIBA, RT3070){ 0x0930, 0x0a07 },
312 USB_ID(UMEDIA, RT2870_1){ 0x157e, 0x300e },
313 USB_ID(UMEDIA, TEW645UB){ 0x157e, 0x3013 },
314 USB_ID(ZCOM, RT2870_1){ 0x0cde, 0x0022 },
315 USB_ID(ZCOM, RT2870_2){ 0x0cde, 0x0025 },
316 USB_ID(ZINWELL, RT2870_1){ 0x5a57, 0x0280 },
317 USB_ID(ZINWELL, RT2870_2){ 0x5a57, 0x0282 },
318 USB_ID(ZINWELL, RT3070){ 0x5a57, 0x5257 },
319 USB_ID(ZINWELL, RT3072_1){ 0x5a57, 0x0283 },
320 USB_ID(ZINWELL, RT3072_2){ 0x5a57, 0x0284 },
321 USB_ID(ZYXEL, NWD2105){ 0x0586, 0x341e },
322 USB_ID(ZYXEL, NWD211AN){ 0x0586, 0x3418 },
323 USB_ID(ZYXEL, RT2870_1){ 0x0586, 0x3416 },
324 USB_ID(ZYXEL, RT2870_2){ 0x0586, 0x341a },
325 USB_ID(ZYXEL, RT3070){ 0x0586, 0x343e }
326};
327
328int run_match(struct device *, void *, void *);
329void run_attach(struct device *, struct device *, void *);
330int run_detach(struct device *, int);
331int run_alloc_rx_ring(struct run_softc *);
332void run_free_rx_ring(struct run_softc *);
333int run_alloc_tx_ring(struct run_softc *, int);
334void run_free_tx_ring(struct run_softc *, int);
335int run_load_microcode(struct run_softc *);
336int run_reset(struct run_softc *);
337int run_read(struct run_softc *, uint16_t, uint32_t *);
338int run_read_region_1(struct run_softc *, uint16_t, uint8_t *,
339 int);
340int run_write_2(struct run_softc *, uint16_t, uint16_t);
341int run_write(struct run_softc *, uint16_t, uint32_t);
342int run_write_region_1(struct run_softc *, uint16_t,
343 const uint8_t *, int);
344int run_set_region_4(struct run_softc *, uint16_t, uint32_t, int);
345int run_efuse_read(struct run_softc *, uint16_t, uint16_t *);
346int run_efuse_read_2(struct run_softc *, uint16_t, uint16_t *);
347int run_eeprom_read_2(struct run_softc *, uint16_t, uint16_t *);
348int run_rt2870_rf_write(struct run_softc *, uint8_t, uint32_t);
349int run_rt3070_rf_read(struct run_softc *, uint8_t, uint8_t *);
350int run_rt3070_rf_write(struct run_softc *, uint8_t, uint8_t);
351int run_bbp_read(struct run_softc *, uint8_t, uint8_t *);
352int run_bbp_write(struct run_softc *, uint8_t, uint8_t);
353int run_mcu_cmd(struct run_softc *, uint8_t, uint16_t);
354const char * run_get_rf(int);
355void run_get_txpower(struct run_softc *);
356void run_rt3593_get_txpower(struct run_softc *);
357int run_read_eeprom(struct run_softc *);
358struct ieee80211_node *run_node_alloc(struct ieee80211com *);
359int run_media_change(struct ifnet *);
360void run_next_scan(void *);
361void run_task(void *);
362void run_do_async(struct run_softc *, void (*)(struct run_softc *,
363 void *), void *, int);
364int run_newstate(struct ieee80211com *, enum ieee80211_state, int);
365void run_newstate_cb(struct run_softc *, void *);
366void run_updateedca(struct ieee80211com *);
367void run_updateedca_cb(struct run_softc *, void *);
368int run_set_key(struct ieee80211com *, struct ieee80211_node *,
369 struct ieee80211_key *);
370void run_set_key_cb(struct run_softc *, void *);
371void run_delete_key(struct ieee80211com *, struct ieee80211_node *,
372 struct ieee80211_key *);
373void run_delete_key_cb(struct run_softc *, void *);
374void run_calibrate_to(void *);
375void run_calibrate_cb(struct run_softc *, void *);
376void run_newassoc(struct ieee80211com *, struct ieee80211_node *,
377 int);
378void run_rx_frame(struct run_softc *, uint8_t *, int,
379 struct mbuf_list *);
380void run_rxeof(struct usbd_xfer *, void *, usbd_status);
381void run_txeof(struct usbd_xfer *, void *, usbd_status);
382int run_tx(struct run_softc *, struct mbuf *,
383 struct ieee80211_node *);
384void run_start(struct ifnet *);
385void run_watchdog(struct ifnet *);
386int run_ioctl(struct ifnet *, u_long, caddr_t);
387void run_iq_calib(struct run_softc *, u_int);
388void run_select_chan_group(struct run_softc *, int);
389void run_set_agc(struct run_softc *, uint8_t);
390void run_set_rx_antenna(struct run_softc *, int);
391void run_rt2870_set_chan(struct run_softc *, u_int);
392void run_rt3070_set_chan(struct run_softc *, u_int);
393void run_rt3572_set_chan(struct run_softc *, u_int);
394void run_rt3593_set_chan(struct run_softc *, u_int);
395void run_rt5390_set_chan(struct run_softc *, u_int);
396void run_rt5592_set_chan(struct run_softc *, u_int);
397int run_set_chan(struct run_softc *, struct ieee80211_channel *);
398void run_enable_tsf_sync(struct run_softc *);
399void run_enable_mrr(struct run_softc *);
400void run_set_txpreamble(struct run_softc *);
401void run_set_basicrates(struct run_softc *);
402void run_set_leds(struct run_softc *, uint16_t);
403void run_set_bssid(struct run_softc *, const uint8_t *);
404void run_set_macaddr(struct run_softc *, const uint8_t *);
405void run_updateslot(struct ieee80211com *);
406void run_updateslot_cb(struct run_softc *, void *);
407#if NBPFILTER1 > 0
408int8_t run_rssi2dbm(struct run_softc *, uint8_t, uint8_t);
409#endif
410void run_rt5390_bbp_init(struct run_softc *);
411int run_bbp_init(struct run_softc *);
412int run_rt3070_rf_init(struct run_softc *);
413void run_rt3593_rf_init(struct run_softc *);
414void run_rt5390_rf_init(struct run_softc *);
415int run_rt3070_filter_calib(struct run_softc *, uint8_t, uint8_t,
416 uint8_t *);
417void run_rt3070_rf_setup(struct run_softc *);
418void run_rt3593_rf_setup(struct run_softc *);
419void run_rt5390_rf_setup(struct run_softc *);
420int run_txrx_enable(struct run_softc *);
421void run_adjust_freq_offset(struct run_softc *);
422int run_init(struct ifnet *);
423void run_stop(struct ifnet *, int);
424
425struct cfdriver run_cd = {
426 NULL((void *)0), "run", DV_IFNET
427};
428
429const struct cfattach run_ca = {
430 sizeof (struct run_softc), run_match, run_attach, run_detach
431};
432
433static const struct {
434 uint32_t reg;
435 uint32_t val;
436} rt2870_def_mac[] = {
437 RT2870_DEF_MAC{ 0x042c, 0xf8f0e8e0 }, { 0x1408, 0x0000013f }, { 0x140c, 0x00008003
}, { 0x1004, 0x00000000 }, { 0x1104, 0x00000209 }, { 0x1330,
0x00000000 }, { 0x1334, 0x00080606 }, { 0x1350, 0x00001020 }
, { 0x1348, 0x000a2090 }, { 0x102c, 0x7f031e46 }, { 0x0214, 0x00002273
}, { 0x0218, 0x00002344 }, { 0x021c, 0x000034aa }, { 0x040c,
0x1f3fbf9f }, { 0x134c, 0x47d01f0f }, { 0x1404, 0x00000013 }
, { 0x1364, 0x05740003 }, { 0x1368, 0x05740003 }, { 0x0408, 0x00f40006
}, { 0x0208, 0x00000030 }, { 0x1374, 0x01744004 }, { 0x1378,
0x03f44084 }, { 0x136c, 0x01744004 }, { 0x1370, 0x03f44084 }
, { 0x1340, 0x0000583f }, { 0x1608, 0x00000002 }, { 0x1344, 0x00092b20
}, { 0x1380, 0x002400ca }, { 0x1100, 0x33a41010 }, { 0x1204,
0x00000003 }
438};
439
440static const struct {
441 uint8_t reg;
442 uint8_t val;
443} rt2860_def_bbp[] = {
444 RT2860_DEF_BBP{ 65, 0x2c }, { 66, 0x38 }, { 68, 0x0b }, { 69, 0x12 }, { 70,
0x0a }, { 73, 0x10 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x6a
}, { 84, 0x99 }, { 86, 0x00 }, { 91, 0x04 }, { 92, 0x00 }, {
103, 0x00 }, { 105, 0x05 }, { 106, 0x35 }
445},rt5390_def_bbp[] = {
446 RT5390_DEF_BBP{ 31, 0x08 }, { 65, 0x2c }, { 66, 0x38 }, { 68, 0x0b }, { 69,
0x0d }, { 70, 0x06 }, { 73, 0x13 }, { 75, 0x46 }, { 76, 0x28
}, { 77, 0x59 }, { 81, 0x37 }, { 82, 0x62 }, { 83, 0x7a }, {
84, 0x9a }, { 86, 0x38 }, { 91, 0x04 }, { 92, 0x02 }, { 103,
0xc0 }, { 104, 0x92 }, { 105, 0x3c }, { 106, 0x03 }, { 128, 0x12
}
447},rt5592_def_bbp[] = {
448 RT5592_DEF_BBP{ 20, 0x06 }, { 31, 0x08 }, { 65, 0x2c }, { 66, 0x38 }, { 68,
0xdd }, { 69, 0x1a }, { 70, 0x05 }, { 73, 0x13 }, { 74, 0x0f
}, { 75, 0x4f }, { 76, 0x28 }, { 77, 0x59 }, { 81, 0x37 }, {
82, 0x62 }, { 83, 0x6a }, { 84, 0x9a }, { 86, 0x38 }, { 88, 0x90
}, { 91, 0x04 }, { 92, 0x02 }, { 95, 0x9a }, { 98, 0x12 }, {
103, 0xc0 }, { 104, 0x92 }, { 105, 0x3c }, { 106, 0x35 }, { 128
, 0x12 }, { 134, 0xd0 }, { 135, 0xf6 }, { 137, 0x0f }
449};
450
451/*
452 * Default values for BBP register R196 for RT5592.
453 */
454static const uint8_t rt5592_bbp_r196[] = {
455 0xe0, 0x1f, 0x38, 0x32, 0x08, 0x28, 0x19, 0x0a, 0xff, 0x00,
456 0x16, 0x10, 0x10, 0x0b, 0x36, 0x2c, 0x26, 0x24, 0x42, 0x36,
457 0x30, 0x2d, 0x4c, 0x46, 0x3d, 0x40, 0x3e, 0x42, 0x3d, 0x40,
458 0x3c, 0x34, 0x2c, 0x2f, 0x3c, 0x35, 0x2e, 0x2a, 0x49, 0x41,
459 0x36, 0x31, 0x30, 0x30, 0x0e, 0x0d, 0x28, 0x21, 0x1c, 0x16,
460 0x50, 0x4a, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00,
461 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
462 0x00, 0x00, 0x7d, 0x14, 0x32, 0x2c, 0x36, 0x4c, 0x43, 0x2c,
463 0x2e, 0x36, 0x30, 0x6e
464};
465
466static const struct rfprog {
467 uint8_t chan;
468 uint32_t r1, r2, r3, r4;
469} rt2860_rf2850[] = {
470 RT2860_RF2850{ 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, { 2, 0x100bb3,
0x1301e1, 0x05a014, 0x001407 }, { 3, 0x100bb3, 0x1301e2, 0x05a014
, 0x001402 }, { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, {
5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, { 6, 0x100bb3, 0x1301e3
, 0x05a014, 0x001407 }, { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402
}, { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, { 9, 0x100bb3
, 0x1301e5, 0x05a014, 0x001402 }, { 10, 0x100bb3, 0x1301e5, 0x05a014
, 0x001407 }, { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 },
{ 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, { 13, 0x100bb3
, 0x1301e7, 0x05a014, 0x001402 }, { 14, 0x100bb3, 0x1301e8, 0x05a014
, 0x001404 }, { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 },
{ 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, { 40, 0x100bb2
, 0x1301a0, 0x056014, 0x001400 }, { 44, 0x100bb2, 0x1301a0, 0x056014
, 0x001408 }, { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 },
{ 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, { 52, 0x100bb2
, 0x1301a2, 0x056014, 0x001404 }, { 54, 0x100bb2, 0x1301a2, 0x056014
, 0x001408 }, { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 },
{ 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, { 62, 0x100bb2
, 0x1301a4, 0x056014, 0x001404 }, { 64, 0x100bb2, 0x1301a4, 0x056014
, 0x001408 }, { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }
, { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, { 104, 0x100bb2
, 0x1701ac, 0x15e014, 0x001408 }, { 108, 0x100bb3, 0x17028c, 0x15e014
, 0x001404 }, { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }
, { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, { 116, 0x100bb3
, 0x13028e, 0x05e014, 0x001408 }, { 118, 0x100bb3, 0x13028f, 0x05e014
, 0x001404 }, { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }
, { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, { 126, 0x100bb1
, 0x1300e0, 0x05e014, 0x001406 }, { 128, 0x100bb1, 0x1300e0, 0x05e014
, 0x001408 }, { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }
, { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, { 136, 0x100bb1
, 0x1300e1, 0x05e014, 0x001406 }, { 140, 0x100bb1, 0x1300e2, 0x05e014
, 0x001400 }, { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }
, { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, { 153, 0x100bb1
, 0x1300e3, 0x05e014, 0x001403 }, { 157, 0x100bb1, 0x1300e3, 0x05e014
, 0x001407 }, { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }
, { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, { 165, 0x100bb1
, 0x1300e4, 0x05e014, 0x001405 }, { 167, 0x100bb1, 0x1300f4, 0x05e014
, 0x001407 }, { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }
, { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, { 173, 0x100bb1
, 0x1300f5, 0x05e014, 0x001403 }
471};
472
473struct {
474 uint8_t n, r, k;
475} rt3070_freqs[] = {
476 RT3070_RF3052{ 0xf1, 2, 2 }, { 0xf1, 2, 7 }, { 0xf2, 2, 2 }, { 0xf2, 2, 7 }
, { 0xf3, 2, 2 }, { 0xf3, 2, 7 }, { 0xf4, 2, 2 }, { 0xf4, 2, 7
}, { 0xf5, 2, 2 }, { 0xf5, 2, 7 }, { 0xf6, 2, 2 }, { 0xf6, 2
, 7 }, { 0xf7, 2, 2 }, { 0xf8, 2, 4 }, { 0x56, 0, 4 }, { 0x56
, 0, 6 }, { 0x56, 0, 8 }, { 0x57, 0, 0 }, { 0x57, 0, 2 }, { 0x57
, 0, 4 }, { 0x57, 0, 8 }, { 0x57, 0, 10 }, { 0x58, 0, 0 }, { 0x58
, 0, 4 }, { 0x58, 0, 6 }, { 0x58, 0, 8 }, { 0x5b, 0, 8 }, { 0x5b
, 0, 10 }, { 0x5c, 0, 0 }, { 0x5c, 0, 4 }, { 0x5c, 0, 6 }, { 0x5c
, 0, 8 }, { 0x5d, 0, 0 }, { 0x5d, 0, 2 }, { 0x5d, 0, 4 }, { 0x5d
, 0, 8 }, { 0x5d, 0, 10 }, { 0x5e, 0, 0 }, { 0x5e, 0, 4 }, { 0x5e
, 0, 6 }, { 0x5e, 0, 8 }, { 0x5f, 0, 0 }, { 0x5f, 0, 9 }, { 0x5f
, 0, 11 }, { 0x60, 0, 1 }, { 0x60, 0, 5 }, { 0x60, 0, 7 }, { 0x60
, 0, 9 }, { 0x61, 0, 1 }, { 0x61, 0, 3 }, { 0x61, 0, 5 }, { 0x61
, 0, 7 }, { 0x61, 0, 9 }
477};
478
479static const struct rt5592_freqs {
480 uint16_t n;
481 uint8_t k, m, r;
482} rt5592_freqs_20mhz[] = {
483 RT5592_RF5592_20MHZ{ 0x1e2, 4, 10, 3 }, { 0x1e3, 4, 10, 3 }, { 0x1e4, 4, 10, 3 }
, { 0x1e5, 4, 10, 3 }, { 0x1e6, 4, 10, 3 }, { 0x1e7, 4, 10, 3
}, { 0x1e8, 4, 10, 3 }, { 0x1e9, 4, 10, 3 }, { 0x1ea, 4, 10,
3 }, { 0x1eb, 4, 10, 3 }, { 0x1ec, 4, 10, 3 }, { 0x1ed, 4, 10
, 3 }, { 0x1ee, 4, 10, 3 }, { 0x1f0, 8, 10, 3 }, { 0xac, 8, 12
, 1 }, { 0xad, 0, 12, 1 }, { 0xad, 4, 12, 1 }, { 0xae, 0, 12,
1 }, { 0xae, 4, 12, 1 }, { 0xae, 8, 12, 1 }, { 0xaf, 4, 12, 1
}, { 0xaf, 8, 12, 1 }, { 0xb0, 0, 12, 1 }, { 0xb0, 8, 12, 1 }
, { 0xb1, 0, 12, 1 }, { 0xb1, 4, 12, 1 }, { 0xb7, 4, 12, 1 },
{ 0xb7, 8, 12, 1 }, { 0xb8, 0, 12, 1 }, { 0xb8, 8, 12, 1 }, {
0xb9, 0, 12, 1 }, { 0xb9, 4, 12, 1 }, { 0xba, 0, 12, 1 }, { 0xba
, 4, 12, 1 }, { 0xba, 8, 12, 1 }, { 0xbb, 4, 12, 1 }, { 0xbb,
8, 12, 1 }, { 0xbc, 0, 12, 1 }, { 0xbc, 8, 12, 1 }, { 0xbd, 0
, 12, 1 }, { 0xbd, 4, 12, 1 }, { 0xbe, 0, 12, 1 }, { 0xbf, 6,
12, 1 }, { 0xbf, 10, 12, 1 }, { 0xc0, 2, 12, 1 }, { 0xc0, 10
, 12, 1 }, { 0xc1, 2, 12, 1 }, { 0xc1, 6, 12, 1 }, { 0xc2, 2,
12, 1 }, { 0xa4, 0, 12, 1 }, { 0xa4, 4, 12, 1 }, { 0xa5, 8, 12
, 1 }, { 0xa6, 0, 12, 1 }
484},rt5592_freqs_40mhz[] = {
485 RT5592_RF5592_40MHZ{ 0xf1, 2, 10, 3 }, { 0xf1, 7, 10, 3 }, { 0xf2, 2, 10, 3 }, {
0xf2, 7, 10, 3 }, { 0xf3, 2, 10, 3 }, { 0xf3, 7, 10, 3 }, { 0xf4
, 2, 10, 3 }, { 0xf4, 7, 10, 3 }, { 0xf5, 2, 10, 3 }, { 0xf5,
7, 10, 3 }, { 0xf6, 2, 10, 3 }, { 0xf6, 7, 10, 3 }, { 0xf7, 2
, 10, 3 }, { 0xf8, 4, 10, 3 }, { 0x56, 4, 12, 1 }, { 0x56, 6,
12, 1 }, { 0x56, 8, 12, 1 }, { 0x57, 0, 12, 1 }, { 0x57, 2, 12
, 1 }, { 0x57, 4, 12, 1 }, { 0x57, 8, 12, 1 }, { 0x57, 10, 12
, 1 }, { 0x58, 0, 12, 1 }, { 0x58, 4, 12, 1 }, { 0x58, 6, 12,
1 }, { 0x58, 8, 12, 1 }, { 0x5b, 8, 12, 1 }, { 0x5b, 10, 12,
1 }, { 0x5c, 0, 12, 1 }, { 0x5c, 4, 12, 1 }, { 0x5c, 6, 12, 1
}, { 0x5c, 8, 12, 1 }, { 0x5d, 0, 12, 1 }, { 0x5d, 2, 12, 1 }
, { 0x5d, 4, 12, 1 }, { 0x5d, 8, 12, 1 }, { 0x5d, 10, 12, 1 }
, { 0x5e, 0, 12, 1 }, { 0x5e, 4, 12, 1 }, { 0x5e, 6, 12, 1 },
{ 0x5e, 8, 12, 1 }, { 0x5f, 0, 12, 1 }, { 0x5f, 9, 12, 1 }, {
0x5f, 11, 12, 1 }, { 0x60, 1, 12, 1 }, { 0x60, 5, 12, 1 }, {
0x60, 7, 12, 1 }, { 0x60, 9, 12, 1 }, { 0x61, 1, 12, 1 }, { 0x52
, 0, 12, 1 }, { 0x52, 4, 12, 1 }, { 0x52, 8, 12, 1 }, { 0x53,
0, 12, 1 }
486};
487
488static const struct {
489 uint8_t reg;
490 uint8_t val;
491} rt3070_def_rf[] = {
492 RT3070_DEF_RF{ 4, 0x40 }, { 5, 0x03 }, { 6, 0x02 }, { 7, 0x60 }, { 9, 0x0f
}, { 10, 0x41 }, { 11, 0x21 }, { 12, 0x7b }, { 14, 0x90 }, {
15, 0x58 }, { 16, 0xb3 }, { 17, 0x92 }, { 18, 0x2c }, { 19, 0x02
}, { 20, 0xba }, { 21, 0xdb }, { 24, 0x16 }, { 25, 0x01 }, {
29, 0x1f }
493},rt3572_def_rf[] = {
494 RT3572_DEF_RF{ 0, 0x70 }, { 1, 0x81 }, { 2, 0xf1 }, { 3, 0x02 }, { 4, 0x4c
}, { 5, 0x05 }, { 6, 0x4a }, { 7, 0xd8 }, { 9, 0xc3 }, { 10,
0xf1 }, { 11, 0xb9 }, { 12, 0x70 }, { 13, 0x65 }, { 14, 0xa0
}, { 15, 0x53 }, { 16, 0x4c }, { 17, 0x23 }, { 18, 0xac }, {
19, 0x93 }, { 20, 0xb3 }, { 21, 0xd0 }, { 22, 0x00 }, { 23, 0x3c
}, { 24, 0x16 }, { 25, 0x15 }, { 26, 0x85 }, { 27, 0x00 }, {
28, 0x00 }, { 29, 0x9b }, { 30, 0x09 }, { 31, 0x10 }
495},rt3593_def_rf[] = {
496 RT3593_DEF_RF{ 1, 0x03 }, { 3, 0x80 }, { 5, 0x00 }, { 6, 0x40 }, { 8, 0xf1
}, { 9, 0x02 }, { 10, 0xd3 }, { 11, 0x40 }, { 12, 0x4e }, { 13
, 0x12 }, { 18, 0x40 }, { 22, 0x20 }, { 30, 0x10 }, { 31, 0x80
}, { 32, 0x78 }, { 33, 0x3b }, { 34, 0x3c }, { 35, 0xe0 }, {
38, 0x86 }, { 39, 0x23 }, { 44, 0xd3 }, { 45, 0xbb }, { 46, 0x60
}, { 49, 0x81 }, { 50, 0x86 }, { 51, 0x75 }, { 52, 0x45 }, {
53, 0x18 }, { 54, 0x18 }, { 55, 0x18 }, { 56, 0xdb }, { 57, 0x6e
}
497},rt5390_def_rf[] = {
498 RT5390_DEF_RF{ 1, 0x0f }, { 2, 0x80 }, { 3, 0x88 }, { 5, 0x10 }, { 6, 0xa0
}, { 7, 0x00 }, { 10, 0x53 }, { 11, 0x4a }, { 12, 0x46 }, { 13
, 0x9f }, { 14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03
}, { 19, 0x00 }, { 20, 0x00 }, { 21, 0x00 }, { 22, 0x20 }, {
23, 0x00 }, { 24, 0x00 }, { 25, 0xc0 }, { 26, 0x00 }, { 27, 0x09
}, { 28, 0x00 }, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, {
32, 0x80 }, { 33, 0x00 }, { 34, 0x07 }, { 35, 0x12 }, { 36, 0x00
}, { 37, 0x08 }, { 38, 0x85 }, { 39, 0x1b }, { 40, 0x0b }, {
41, 0xbb }, { 42, 0xd2 }, { 43, 0x9a }, { 44, 0x0e }, { 45, 0xa2
}, { 46, 0x7b }, { 47, 0x00 }, { 48, 0x10 }, { 49, 0x94 }, {
52, 0x38 }, { 53, 0x84 }, { 54, 0x78 }, { 55, 0x44 }, { 56, 0x22
}, { 57, 0x80 }, { 58, 0x7f }, { 59, 0x8f }, { 60, 0x45 }, {
61, 0xdd }, { 62, 0x00 }, { 63, 0x00 }
499},rt5392_def_rf[] = {
500 RT5392_DEF_RF{ 1, 0x17 }, { 3, 0x88 }, { 5, 0x10 }, { 6, 0xe0 }, { 7, 0x00
}, { 10, 0x53 }, { 11, 0x4a }, { 12, 0x46 }, { 13, 0x9f }, {
14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03 }, { 19, 0x4d
}, { 20, 0x00 }, { 21, 0x8d }, { 22, 0x20 }, { 23, 0x0b }, {
24, 0x44 }, { 25, 0x80 }, { 26, 0x82 }, { 27, 0x09 }, { 28, 0x00
}, { 29, 0x10 }, { 30, 0x10 }, { 31, 0x80 }, { 32, 0x20 }, {
33, 0xc0 }, { 34, 0x07 }, { 35, 0x12 }, { 36, 0x00 }, { 37, 0x08
}, { 38, 0x89 }, { 39, 0x1b }, { 40, 0x0f }, { 41, 0xbb }, {
42, 0xd5 }, { 43, 0x9b }, { 44, 0x0e }, { 45, 0xa2 }, { 46, 0x73
}, { 47, 0x0c }, { 48, 0x10 }, { 49, 0x94 }, { 50, 0x94 }, {
51, 0x3a }, { 52, 0x48 }, { 53, 0x44 }, { 54, 0x38 }, { 55, 0x43
}, { 56, 0xa1 }, { 57, 0x00 }, { 58, 0x39 }, { 59, 0x07 }, {
60, 0x45 }, { 61, 0x91 }, { 62, 0x39 }, { 63, 0x07 }
501},rt5592_def_rf[] = {
502 RT5592_DEF_RF{ 1, 0x3f }, { 3, 0x08 }, { 5, 0x10 }, { 6, 0xe4 }, { 7, 0x00
}, { 14, 0x00 }, { 15, 0x00 }, { 16, 0x00 }, { 18, 0x03 }, {
19, 0x4d }, { 20, 0x10 }, { 21, 0x8d }, { 26, 0x82 }, { 28, 0x00
}, { 29, 0x10 }, { 33, 0xc0 }, { 34, 0x07 }, { 35, 0x12 }, {
47, 0x0c }, { 53, 0x22 }, { 63, 0x07 }
503},rt5592_2ghz_def_rf[] = {
504 RT5592_2GHZ_DEF_RF{ 10, 0x90 }, { 11, 0x4a }, { 12, 0x52 }, { 13, 0x42 }, { 22,
0x40 }, { 24, 0x4a }, { 25, 0x80 }, { 27, 0x42 }, { 36, 0x80
}, { 37, 0x08 }, { 38, 0x89 }, { 39, 0x1b }, { 40, 0x0d }, {
41, 0x9b }, { 42, 0xd5 }, { 43, 0x72 }, { 44, 0x0e }, { 45, 0xa2
}, { 46, 0x6b }, { 48, 0x10 }, { 51, 0x3e }, { 52, 0x48 }, {
54, 0x38 }, { 56, 0xa1 }, { 57, 0x00 }, { 58, 0x39 }, { 60, 0x45
}, { 61, 0x91 }, { 62, 0x39 }
505},rt5592_5ghz_def_rf[] = {
506 RT5592_5GHZ_DEF_RF{ 10, 0x97 }, { 11, 0x40 }, { 25, 0xbf }, { 27, 0x42 }, { 36,
0x00 }, { 37, 0x04 }, { 38, 0x85 }, { 40, 0x42 }, { 41, 0xbb
}, { 42, 0xd7 }, { 45, 0x41 }, { 48, 0x00 }, { 57, 0x77 }, {
60, 0x05 }, { 61, 0x01 }
507};
508
509static const struct {
510 u_int firstchan;
511 u_int lastchan;
512 uint8_t reg;
513 uint8_t val;
514} rt5592_chan_5ghz[] = {
515 RT5592_CHAN_5GHZ{ 36, 64, 12, 0x2e }, { 100, 165, 12, 0x0e }, { 36, 64, 13, 0x22
}, { 100, 165, 13, 0x42 }, { 36, 64, 22, 0x60 }, { 100, 165,
22, 0x40 }, { 36, 64, 23, 0x7f }, { 100, 153, 23, 0x3c }, { 155
, 165, 23, 0x38 }, { 36, 50, 24, 0x09 }, { 52, 64, 24, 0x07 }
, { 100, 153, 24, 0x06 }, { 155, 165, 24, 0x05 }, { 36, 64, 39
, 0x1c }, { 100, 138, 39, 0x1a }, { 140, 165, 39, 0x18 }, { 36
, 64, 43, 0x5b }, { 100, 138, 43, 0x3b }, { 140, 165, 43, 0x1b
}, { 36, 64, 44, 0x40 }, { 100, 138, 44, 0x20 }, { 140, 165,
44, 0x10 }, { 36, 64, 46, 0x00 }, { 100, 138, 46, 0x18 }, { 140
, 165, 46, 0x08 }, { 36, 64, 51, 0xfe }, { 100, 124, 51, 0xfc
}, { 126, 165, 51, 0xec }, { 36, 64, 52, 0x0c }, { 100, 138,
52, 0x06 }, { 140, 165, 52, 0x06 }, { 36, 64, 54, 0xf8 }, { 100
, 165, 54, 0xeb }, { 36, 50, 55, 0x06 }, { 52, 64, 55, 0x04 }
, { 100, 138, 55, 0x01 }, { 140, 165, 55, 0x00 }, { 36, 50, 56
, 0xd3 }, { 52, 128, 56, 0xbb }, { 130, 165, 56, 0xab }, { 36
, 64, 58, 0x15 }, { 100, 116, 58, 0x1d }, { 118, 165, 58, 0x15
}, { 36, 64, 59, 0x7f }, { 100, 138, 59, 0x3f }, { 140, 165,
59, 0x7c }, { 36, 64, 62, 0x15 }, { 100, 116, 62, 0x1d }, { 118
, 165, 62, 0x15 }
516};
517
518int
519run_match(struct device *parent, void *match, void *aux)
520{
521 struct usb_attach_arg *uaa = aux;
522
523 if (uaa->iface == NULL((void *)0) || uaa->configno != 1)
524 return UMATCH_NONE0;
525
526 return (usb_lookup(run_devs, uaa->vendor, uaa->product)usbd_match_device((const struct usb_devno *)(run_devs), sizeof
(run_devs) / sizeof ((run_devs)[0]), sizeof ((run_devs)[0]),
(uaa->vendor), (uaa->product)) != NULL((void *)0)) ?
527 UMATCH_VENDOR_PRODUCT_CONF_IFACE8 : UMATCH_NONE0;
528}
529
530void
531run_attach(struct device *parent, struct device *self, void *aux)
532{
533 struct run_softc *sc = (struct run_softc *)self;
534 struct usb_attach_arg *uaa = aux;
535 struct ieee80211com *ic = &sc->sc_ic;
536 struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
537 usb_interface_descriptor_t *id;
538 usb_endpoint_descriptor_t *ed;
539 int i, nrx, ntx, ntries;
540 uint32_t ver;
541
542 sc->sc_udev = uaa->device;
543 sc->sc_iface = uaa->iface;
544
545 /*
546 * Find all bulk endpoints. There are 7 bulk endpoints: 1 for RX
547 * and 6 for TX (4 EDCAs + HCCA + Prio).
548 * Update 03-14-2009: some devices like the Planex GW-US300MiniS
549 * seem to have only 4 TX bulk endpoints (Fukaumi Naoki).
550 */
551 nrx = ntx = 0;
552 id = usbd_get_interface_descriptor(sc->sc_iface);
553 for (i = 0; i < id->bNumEndpoints; i++) {
554 ed = usbd_interface2endpoint_descriptor(sc->sc_iface, i);
555 if (ed == NULL((void *)0) || UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) != UE_BULK0x02)
556 continue;
557
558 if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_IN0x80) {
559 sc->rxq.pipe_no = ed->bEndpointAddress;
560 nrx++;
561 } else if (ntx < 4) {
562 sc->txq[ntx].pipe_no = ed->bEndpointAddress;
563 ntx++;
564 }
565 }
566 /* make sure we've got them all */
567 if (nrx < 1 || ntx < 4) {
568 printf("%s: missing endpoint\n", sc->sc_dev.dv_xname);
569 return;
570 }
571
572 usb_init_task(&sc->sc_task, run_task, sc, USB_TASK_TYPE_GENERIC)((&sc->sc_task)->fun = (run_task), (&sc->sc_task
)->arg = (sc), (&sc->sc_task)->type = (0), (&
sc->sc_task)->state = 0x0);
573 timeout_set(&sc->scan_to, run_next_scan, sc);
574 timeout_set(&sc->calib_to, run_calibrate_to, sc);
575
576 sc->amrr.amrr_min_success_threshold = 1;
577 sc->amrr.amrr_max_success_threshold = 10;
578
579 /* wait for the chip to settle */
580 for (ntries = 0; ntries < 100; ntries++) {
581 if (run_read(sc, RT2860_ASIC_VER_ID0x1000, &ver) != 0)
582 return;
583 if (ver != 0 && ver != 0xffffffff)
584 break;
585 DELAY(10)(*delay_func)(10);
586 }
587 if (ntries == 100) {
588 printf("%s: timeout waiting for NIC to initialize\n",
589 sc->sc_dev.dv_xname);
590 return;
591 }
592 sc->mac_ver = ver >> 16;
593 sc->mac_rev = ver & 0xffff;
594
595 /* retrieve RF rev. no and various other things from EEPROM */
596 run_read_eeprom(sc);
597
598 printf("%s: MAC/BBP RT%04X (rev 0x%04X), RF %s (MIMO %dT%dR), "
599 "address %s\n", sc->sc_dev.dv_xname, sc->mac_ver,
600 sc->mac_rev, run_get_rf(sc->rf_rev), sc->ntxchains,
601 sc->nrxchains, ether_sprintf(ic->ic_myaddr));
602
603 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
604 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
605 ic->ic_state = IEEE80211_S_INIT;
606
607 /* set device capabilities */
608 ic->ic_caps =
609 IEEE80211_C_MONITOR0x00000200 | /* monitor mode supported */
610 IEEE80211_C_SHPREAMBLE0x00000100 | /* short preamble supported */
611 IEEE80211_C_SHSLOT0x00000080 | /* short slot time supported */
612 IEEE80211_C_WEP0x00000001 | /* WEP */
613 IEEE80211_C_RSN0x00001000; /* WPA/RSN */
614
615 if (sc->rf_rev == RT2860_RF_27500x0004 ||
616 sc->rf_rev == RT2860_RF_28500x0002 ||
617 sc->rf_rev == RT3070_RF_30520x0009 ||
618 sc->rf_rev == RT3070_RF_30530x000d ||
619 sc->rf_rev == RT5592_RF_55920x000f) {
620 /* set supported .11a rates */
621 ic->ic_sup_rates[IEEE80211_MODE_11A] =
622 ieee80211_std_rateset_11a;
623
624 /* set supported .11a channels */
625 for (i = 14; i < nitems(rt2860_rf2850)(sizeof((rt2860_rf2850)) / sizeof((rt2860_rf2850)[0])); i++) {
626 uint8_t chan = rt2860_rf2850[i].chan;
627 ic->ic_channels[chan].ic_freq =
628 ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ0x0100);
629 ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A(0x0100 | 0x0040);
630 }
631 }
632
633 /* set supported .11b and .11g rates */
634 ic->ic_sup_rates[IEEE80211_MODE_11B] = ieee80211_std_rateset_11b;
635 ic->ic_sup_rates[IEEE80211_MODE_11G] = ieee80211_std_rateset_11g;
636
637 /* set supported .11b and .11g channels (1 through 14) */
638 for (i = 1; i <= 14; i++) {
639 ic->ic_channels[i].ic_freq =
640 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ0x0080);
641 ic->ic_channels[i].ic_flags =
642 IEEE80211_CHAN_CCK0x0020 | IEEE80211_CHAN_OFDM0x0040 |
643 IEEE80211_CHAN_DYN0x0400 | IEEE80211_CHAN_2GHZ0x0080;
644 }
645
646 ifp->if_softc = sc;
647 ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
648 ifp->if_ioctl = run_ioctl;
649 ifp->if_start = run_start;
650 ifp->if_watchdog = run_watchdog;
651 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ)__builtin_memcpy((ifp->if_xname), (sc->sc_dev.dv_xname)
, (16));
652
653 if_attach(ifp);
654 ieee80211_ifattach(ifp);
655 ic->ic_node_alloc = run_node_alloc;
656 ic->ic_newassoc = run_newassoc;
657 ic->ic_updateslot = run_updateslot;
658 ic->ic_updateedca = run_updateedca;
659 ic->ic_set_key = run_set_key;
660 ic->ic_delete_key = run_delete_key;
661 /* override state transition machine */
662 sc->sc_newstate = ic->ic_newstate;
663 ic->ic_newstate = run_newstate;
664 ieee80211_media_init(ifp, run_media_change, ieee80211_media_status);
665
666#if NBPFILTER1 > 0
667 bpfattach(&sc->sc_drvbpf, ifp, DLT_IEEE802_11_RADIO127,
668 sizeof (struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN64);
669
670 sc->sc_rxtap_len = sizeof sc->sc_rxtapu;
671 sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_len = htole16(sc->sc_rxtap_len)((__uint16_t)(sc->sc_rxtap_len));
672 sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_present = htole32(RUN_RX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL
| 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL | 1 << IEEE80211_RADIOTAP_ANTENNA
| 1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)));
673
674 sc->sc_txtap_len = sizeof sc->sc_txtapu;
675 sc->sc_txtapsc_txtapu.th.wt_ihdr.it_len = htole16(sc->sc_txtap_len)((__uint16_t)(sc->sc_txtap_len));
676 sc->sc_txtapsc_txtapu.th.wt_ihdr.it_present = htole32(RUN_TX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL
)));
677#endif
678}
679
680int
681run_detach(struct device *self, int flags)
682{
683 struct run_softc *sc = (struct run_softc *)self;
684 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
685 int qid, s;
686
687 s = splusb()splraise(0x5);
688
689 if (timeout_initialized(&sc->scan_to)((&sc->scan_to)->to_flags & 0x04))
690 timeout_del(&sc->scan_to);
691 if (timeout_initialized(&sc->calib_to)((&sc->calib_to)->to_flags & 0x04))
692 timeout_del(&sc->calib_to);
693
694 /* wait for all queued asynchronous commands to complete */
695 usb_rem_wait_task(sc->sc_udev, &sc->sc_task);
696
697 usbd_ref_wait(sc->sc_udev);
698
699 if (ifp->if_softc != NULL((void *)0)) {
700 ifp->if_flags &= ~IFF_RUNNING0x40;
701 ifq_clr_oactive(&ifp->if_snd);
702 ieee80211_ifdetach(ifp);
703 if_detach(ifp);
704 }
705
706 for (qid = 0; qid < 4; qid++)
707 run_free_tx_ring(sc, qid);
708 run_free_rx_ring(sc);
709
710 splx(s)spllower(s);
711
712 return 0;
713}
714
715int
716run_alloc_rx_ring(struct run_softc *sc)
717{
718 struct run_rx_ring *rxq = &sc->rxq;
719 int i, error;
720
721 error = usbd_open_pipe(sc->sc_iface, rxq->pipe_no, 0, &rxq->pipeh);
722 if (error != 0)
723 goto fail;
724
725 for (i = 0; i < RUN_RX_RING_COUNT1; i++) {
726 struct run_rx_data *data = &rxq->data[i];
727
728 data->sc = sc; /* backpointer for callbacks */
729
730 data->xfer = usbd_alloc_xfer(sc->sc_udev);
731 if (data->xfer == NULL((void *)0)) {
732 error = ENOMEM12;
733 goto fail;
734 }
735 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_RXSZ4096);
736 if (data->buf == NULL((void *)0)) {
737 error = ENOMEM12;
738 goto fail;
739 }
740 }
741 if (error != 0)
742fail: run_free_rx_ring(sc);
743 return error;
744}
745
746void
747run_free_rx_ring(struct run_softc *sc)
748{
749 struct run_rx_ring *rxq = &sc->rxq;
750 int i;
751
752 if (rxq->pipeh != NULL((void *)0)) {
753 usbd_close_pipe(rxq->pipeh);
754 rxq->pipeh = NULL((void *)0);
755 }
756 for (i = 0; i < RUN_RX_RING_COUNT1; i++) {
757 if (rxq->data[i].xfer != NULL((void *)0))
758 usbd_free_xfer(rxq->data[i].xfer);
759 rxq->data[i].xfer = NULL((void *)0);
760 }
761}
762
763int
764run_alloc_tx_ring(struct run_softc *sc, int qid)
765{
766 struct run_tx_ring *txq = &sc->txq[qid];
767 int i, error;
768 uint16_t txwisize;
769
770 txwisize = sizeof(struct rt2860_txwi);
771 if (sc->mac_ver == 0x5592)
772 txwisize += sizeof(uint32_t);
773
774 txq->cur = txq->queued = 0;
775
776 error = usbd_open_pipe(sc->sc_iface, txq->pipe_no, 0, &txq->pipeh);
777 if (error != 0)
778 goto fail;
779
780 for (i = 0; i < RUN_TX_RING_COUNT8; i++) {
781 struct run_tx_data *data = &txq->data[i];
782
783 data->sc = sc; /* backpointer for callbacks */
784 data->qid = qid;
785
786 data->xfer = usbd_alloc_xfer(sc->sc_udev);
787 if (data->xfer == NULL((void *)0)) {
788 error = ENOMEM12;
789 goto fail;
790 }
791 data->buf = usbd_alloc_buffer(data->xfer, RUN_MAX_TXSZ(sizeof (struct rt2870_txd) + sizeof (struct rt2860_txwi) + (
1 << 11) + 11));
792 if (data->buf == NULL((void *)0)) {
793 error = ENOMEM12;
794 goto fail;
795 }
796 /* zeroize the TXD + TXWI part */
797 memset(data->buf, 0, sizeof(struct rt2870_txd) + txwisize)__builtin_memset((data->buf), (0), (sizeof(struct rt2870_txd
) + txwisize));
798 }
799 if (error != 0)
800fail: run_free_tx_ring(sc, qid);
801 return error;
802}
803
804void
805run_free_tx_ring(struct run_softc *sc, int qid)
806{
807 struct run_tx_ring *txq = &sc->txq[qid];
808 int i;
809
810 if (txq->pipeh != NULL((void *)0)) {
811 usbd_close_pipe(txq->pipeh);
812 txq->pipeh = NULL((void *)0);
813 }
814 for (i = 0; i < RUN_TX_RING_COUNT8; i++) {
815 if (txq->data[i].xfer != NULL((void *)0))
816 usbd_free_xfer(txq->data[i].xfer);
817 txq->data[i].xfer = NULL((void *)0);
818 }
819}
820
821int
822run_load_microcode(struct run_softc *sc)
823{
824 usb_device_request_t req;
825 const char *fwname;
826 u_char *ucode;
827 size_t size;
828 uint32_t tmp;
829 int ntries, error;
830
831 /* RT3071/RT3072 use a different firmware */
832 if (sc->mac_ver != 0x2860 &&
833 sc->mac_ver != 0x2872 &&
834 sc->mac_ver != 0x3070)
835 fwname = "run-rt3071";
836 else
837 fwname = "run-rt2870";
838
839 if ((error = loadfirmware(fwname, &ucode, &size)) != 0) {
840 printf("%s: failed loadfirmware of file %s (error %d)\n",
841 sc->sc_dev.dv_xname, fwname, error);
842 return error;
843 }
844 if (size != 4096) {
845 printf("%s: invalid firmware size (should be 4KB)\n",
846 sc->sc_dev.dv_xname);
847 free(ucode, M_DEVBUF2, size);
848 return EINVAL22;
849 }
850
851 /* write microcode image */
852 run_write_region_1(sc, RT2870_FW_BASE0x3000, ucode, size);
853 free(ucode, M_DEVBUF2, size);
854 run_write(sc, RT2860_H2M_MAILBOX_CID0x7014, 0xffffffff);
855 run_write(sc, RT2860_H2M_MAILBOX_STATUS0x701c, 0xffffffff);
856
857 req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
858 req.bRequest = RT2870_RESET1;
859 USETW(req.wValue, 8)(*(u_int16_t *)(req.wValue) = (8));
860 USETW(req.wIndex, 0)(*(u_int16_t *)(req.wIndex) = (0));
861 USETW(req.wLength, 0)(*(u_int16_t *)(req.wLength) = (0));
862 if ((error = usbd_do_request(sc->sc_udev, &req, NULL((void *)0))) != 0)
863 return error;
864
865 usbd_delay_ms(sc->sc_udev, 10);
866 run_write(sc, RT2860_H2M_BBPAGENT0x7028, 0);
867 run_write(sc, RT2860_H2M_MAILBOX0x7010, 0);
868 run_write(sc, RT2860_H2M_INTSRC0x7024, 0);
869 if ((error = run_mcu_cmd(sc, RT2860_MCU_CMD_RFRESET0x72, 0)) != 0)
870 return error;
871
872 /* wait until microcontroller is ready */
873 for (ntries = 0; ntries < 1000; ntries++) {
874 if ((error = run_read(sc, RT2860_SYS_CTRL0x0400, &tmp)) != 0)
875 return error;
876 if (tmp & RT2860_MCU_READY(1 << 7))
877 break;
878 DELAY(1000)(*delay_func)(1000);
879 }
880 if (ntries == 1000) {
881 printf("%s: timeout waiting for MCU to initialize\n",
882 sc->sc_dev.dv_xname);
883 return ETIMEDOUT60;
884 }
885 DPRINTF(("microcode successfully loaded after %d tries\n", ntries));
886 return 0;
887}
888
889int
890run_reset(struct run_softc *sc)
891{
892 usb_device_request_t req;
893
894 req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
895 req.bRequest = RT2870_RESET1;
896 USETW(req.wValue, 1)(*(u_int16_t *)(req.wValue) = (1));
897 USETW(req.wIndex, 0)(*(u_int16_t *)(req.wIndex) = (0));
898 USETW(req.wLength, 0)(*(u_int16_t *)(req.wLength) = (0));
899 return usbd_do_request(sc->sc_udev, &req, NULL((void *)0));
900}
901
902int
903run_read(struct run_softc *sc, uint16_t reg, uint32_t *val)
904{
905 uint32_t tmp;
906 int error;
907
908 error = run_read_region_1(sc, reg, (uint8_t *)&tmp, sizeof tmp);
909 if (error == 0)
910 *val = letoh32(tmp)((__uint32_t)(tmp));
911 else
912 *val = 0xffffffff;
913 return error;
914}
915
916int
917run_read_region_1(struct run_softc *sc, uint16_t reg, uint8_t *buf, int len)
918{
919 usb_device_request_t req;
920
921 req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00);
922 req.bRequest = RT2870_READ_REGION_17;
923 USETW(req.wValue, 0)(*(u_int16_t *)(req.wValue) = (0));
924 USETW(req.wIndex, reg)(*(u_int16_t *)(req.wIndex) = (reg));
925 USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len));
926 return usbd_do_request(sc->sc_udev, &req, buf);
927}
928
929int
930run_write_2(struct run_softc *sc, uint16_t reg, uint16_t val)
931{
932 usb_device_request_t req;
933
934 req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
935 req.bRequest = RT2870_WRITE_22;
936 USETW(req.wValue, val)(*(u_int16_t *)(req.wValue) = (val));
937 USETW(req.wIndex, reg)(*(u_int16_t *)(req.wIndex) = (reg));
938 USETW(req.wLength, 0)(*(u_int16_t *)(req.wLength) = (0));
939 return usbd_do_request(sc->sc_udev, &req, NULL((void *)0));
940}
941
942int
943run_write(struct run_softc *sc, uint16_t reg, uint32_t val)
944{
945 int error;
946
947 if ((error = run_write_2(sc, reg, val & 0xffff)) == 0)
948 error = run_write_2(sc, reg + 2, val >> 16);
949 return error;
950}
951
952int
953run_write_region_1(struct run_softc *sc, uint16_t reg, const uint8_t *buf,
954 int len)
955{
956#if 1
957 int i, error = 0;
958 /*
959 * NB: the WRITE_REGION_1 command is not stable on RT2860.
960 * We thus issue multiple WRITE_2 commands instead.
961 */
962 KASSERT((len & 1) == 0)(((len & 1) == 0) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/usb/if_run.c"
, 962, "(len & 1) == 0"));
963 for (i = 0; i < len && error == 0; i += 2)
964 error = run_write_2(sc, reg + i, buf[i] | buf[i + 1] << 8);
965 return error;
966#else
967 usb_device_request_t req;
968
969 req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
970 req.bRequest = RT2870_WRITE_REGION_16;
971 USETW(req.wValue, 0)(*(u_int16_t *)(req.wValue) = (0));
972 USETW(req.wIndex, reg)(*(u_int16_t *)(req.wIndex) = (reg));
973 USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len));
974 return usbd_do_request(sc->sc_udev, &req, buf);
975#endif
976}
977
978int
979run_set_region_4(struct run_softc *sc, uint16_t reg, uint32_t val, int count)
980{
981 int error = 0;
982
983 for (; count > 0 && error == 0; count--, reg += 4)
984 error = run_write(sc, reg, val);
985 return error;
986}
987
988/* Read 16-bit from eFUSE ROM. */
989int
990run_efuse_read(struct run_softc *sc, uint16_t addr, uint16_t *val)
991{
992 uint32_t tmp;
993 uint16_t reg;
994 int error, ntries;
995
996 if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0)
997 return error;
998
999 /*-
1000 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1001 * DATA0: F E D C
1002 * DATA1: B A 9 8
1003 * DATA2: 7 6 5 4
1004 * DATA3: 3 2 1 0
1005 */
1006 tmp &= ~(RT3070_EFSROM_MODE_MASK0x000000c0 | RT3070_EFSROM_AIN_MASK0x03ff0000);
1007 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT16 | RT3070_EFSROM_KICK(1U << 30);
1008 run_write(sc, RT3070_EFUSE_CTRL0x0580, tmp);
1009 for (ntries = 0; ntries < 100; ntries++) {
1010 if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0)
1011 return error;
1012 if (!(tmp & RT3070_EFSROM_KICK(1U << 30)))
1013 break;
1014 DELAY(2)(*delay_func)(2);
1015 }
1016 if (ntries == 100)
1017 return ETIMEDOUT60;
1018
1019 if ((tmp & RT3070_EFUSE_AOUT_MASK0x0000003f) == RT3070_EFUSE_AOUT_MASK0x0000003f) {
1020 *val = 0xffff; /* address not found */
1021 return 0;
1022 }
1023 /* determine to which 32-bit register our 16-bit word belongs */
1024 reg = RT3070_EFUSE_DATA30x059c - (addr & 0xc);
1025 if ((error = run_read(sc, reg, &tmp)) != 0)
1026 return error;
1027
1028 tmp >>= (8 * (addr & 0x3));
1029 *val = (addr & 1) ? tmp >> 16 : tmp & 0xffff;
1030 return 0;
1031}
1032
1033/* Read 16-bit from eFUSE ROM for RT3xxx. */
1034int
1035run_efuse_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
1036{
1037 uint32_t tmp;
1038 uint16_t reg;
1039 int error, ntries;
1040
1041 if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0)
23
←
Taking true branch
→
1042 return error;
24
←
Returning without writing to '*val'
→
1043
1044 addr *= 2;
1045 /*-
1046 * Read one 16-byte block into registers EFUSE_DATA[0-3]:
1047 * DATA0: F E D C
1048 * DATA1: B A 9 8
1049 * DATA2: 7 6 5 4
1050 * DATA3: 3 2 1 0
1051 */
1052 tmp &= ~(RT3070_EFSROM_MODE_MASK0x000000c0 | RT3070_EFSROM_AIN_MASK0x03ff0000);
1053 tmp |= (addr & ~0xf) << RT3070_EFSROM_AIN_SHIFT16 | RT3070_EFSROM_KICK(1U << 30);
1054 run_write(sc, RT3070_EFUSE_CTRL0x0580, tmp);
1055 for (ntries = 0; ntries < 100; ntries++) {
1056 if ((error = run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp)) != 0)
1057 return error;
1058 if (!(tmp & RT3070_EFSROM_KICK(1U << 30)))
1059 break;
1060 DELAY(2)(*delay_func)(2);
1061 }
1062 if (ntries == 100)
1063 return ETIMEDOUT60;
1064
1065 if ((tmp & RT3070_EFUSE_AOUT_MASK0x0000003f) == RT3070_EFUSE_AOUT_MASK0x0000003f) {
1066 *val = 0xffff; /* address not found */
1067 return 0;
1068 }
1069 /* determine to which 32-bit register our 16-bit word belongs */
1070 reg = RT3070_EFUSE_DATA30x059c - (addr & 0xc);
1071 if ((error = run_read(sc, reg, &tmp)) != 0)
1072 return error;
1073
1074 *val = (addr & 2) ? tmp >> 16 : tmp & 0xffff;
1075 return 0;
1076}
1077
1078int
1079run_eeprom_read_2(struct run_softc *sc, uint16_t addr, uint16_t *val)
1080{
1081 usb_device_request_t req;
1082 uint16_t tmp;
1083 int error;
1084
1085 addr *= 2;
1086 req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00);
1087 req.bRequest = RT2870_EEPROM_READ9;
1088 USETW(req.wValue, 0)(*(u_int16_t *)(req.wValue) = (0));
1089 USETW(req.wIndex, addr)(*(u_int16_t *)(req.wIndex) = (addr));
1090 USETW(req.wLength, sizeof tmp)(*(u_int16_t *)(req.wLength) = (sizeof tmp));
1091 error = usbd_do_request(sc->sc_udev, &req, &tmp);
1092 if (error == 0)
1093 *val = letoh16(tmp)((__uint16_t)(tmp));
1094 else
1095 *val = 0xffff;
1096 return error;
1097}
1098
1099static __inline int
1100run_srom_read(struct run_softc *sc, uint16_t addr, uint16_t *val)
1101{
1102 /* either eFUSE ROM or EEPROM */
1103 return sc->sc_srom_read(sc, addr, val);
22
←
Calling 'run_efuse_read_2'
→
25
←
Returning from 'run_efuse_read_2'
→
26
←
Returning without writing to '*val'
→
1104}
1105
1106int
1107run_rt2870_rf_write(struct run_softc *sc, uint8_t reg, uint32_t val)
1108{
1109 uint32_t tmp;
1110 int error, ntries;
1111
1112 for (ntries = 0; ntries < 10; ntries++) {
1113 if ((error = run_read(sc, RT2860_RF_CSR_CFG00x1020, &tmp)) != 0)
1114 return error;
1115 if (!(tmp & RT2860_RF_REG_CTRL(1U << 31)))
1116 break;
1117 }
1118 if (ntries == 10)
1119 return ETIMEDOUT60;
1120
1121 /* RF registers are 24-bit on the RT2860 */
1122 tmp = RT2860_RF_REG_CTRL(1U << 31) | 24 << RT2860_RF_REG_WIDTH_SHIFT24 |
1123 (val & 0x3fffff) << 2 | (reg & 3);
1124 return run_write(sc, RT2860_RF_CSR_CFG00x1020, tmp);
1125}
1126
1127int
1128run_rt3070_rf_read(struct run_softc *sc, uint8_t reg, uint8_t *val)
1129{
1130 uint32_t tmp;
1131 int error, ntries;
1132
1133 for (ntries = 0; ntries < 100; ntries++) {
1134 if ((error = run_read(sc, RT3070_RF_CSR_CFG0x0500, &tmp)) != 0)
1135 return error;
1136 if (!(tmp & RT3070_RF_KICK(1 << 17)))
1137 break;
1138 }
1139 if (ntries == 100)
1140 return ETIMEDOUT60;
1141
1142 tmp = RT3070_RF_KICK(1 << 17) | reg << 8;
1143 if ((error = run_write(sc, RT3070_RF_CSR_CFG0x0500, tmp)) != 0)
1144 return error;
1145
1146 for (ntries = 0; ntries < 100; ntries++) {
1147 if ((error = run_read(sc, RT3070_RF_CSR_CFG0x0500, &tmp)) != 0)
1148 return error;
1149 if (!(tmp & RT3070_RF_KICK(1 << 17)))
1150 break;
1151 }
1152 if (ntries == 100)
1153 return ETIMEDOUT60;
1154
1155 *val = tmp & 0xff;
1156 return 0;
1157}
1158
1159int
1160run_rt3070_rf_write(struct run_softc *sc, uint8_t reg, uint8_t val)
1161{
1162 uint32_t tmp;
1163 int error, ntries;
1164
1165 for (ntries = 0; ntries < 10; ntries++) {
1166 if ((error = run_read(sc, RT3070_RF_CSR_CFG0x0500, &tmp)) != 0)
1167 return error;
1168 if (!(tmp & RT3070_RF_KICK(1 << 17)))
1169 break;
1170 }
1171 if (ntries == 10)
1172 return ETIMEDOUT60;
1173
1174 tmp = RT3070_RF_WRITE(1 << 16) | RT3070_RF_KICK(1 << 17) | reg << 8 | val;
1175 return run_write(sc, RT3070_RF_CSR_CFG0x0500, tmp);
1176}
1177
1178int
1179run_bbp_read(struct run_softc *sc, uint8_t reg, uint8_t *val)
1180{
1181 uint32_t tmp;
1182 int ntries, error;
1183
1184 for (ntries = 0; ntries < 10; ntries++) {
1185 if ((error = run_read(sc, RT2860_BBP_CSR_CFG0x101c, &tmp)) != 0)
1186 return error;
1187 if (!(tmp & RT2860_BBP_CSR_KICK(1 << 17)))
1188 break;
1189 }
1190 if (ntries == 10)
1191 return ETIMEDOUT60;
1192
1193 tmp = RT2860_BBP_CSR_READ(1 << 16) | RT2860_BBP_CSR_KICK(1 << 17) | reg << 8;
1194 if ((error = run_write(sc, RT2860_BBP_CSR_CFG0x101c, tmp)) != 0)
1195 return error;
1196
1197 for (ntries = 0; ntries < 10; ntries++) {
1198 if ((error = run_read(sc, RT2860_BBP_CSR_CFG0x101c, &tmp)) != 0)
1199 return error;
1200 if (!(tmp & RT2860_BBP_CSR_KICK(1 << 17)))
1201 break;
1202 }
1203 if (ntries == 10)
1204 return ETIMEDOUT60;
1205
1206 *val = tmp & 0xff;
1207 return 0;
1208}
1209
1210int
1211run_bbp_write(struct run_softc *sc, uint8_t reg, uint8_t val)
1212{
1213 uint32_t tmp;
1214 int ntries, error;
1215
1216 for (ntries = 0; ntries < 10; ntries++) {
1217 if ((error = run_read(sc, RT2860_BBP_CSR_CFG0x101c, &tmp)) != 0)
1218 return error;
1219 if (!(tmp & RT2860_BBP_CSR_KICK(1 << 17)))
1220 break;
1221 }
1222 if (ntries == 10)
1223 return ETIMEDOUT60;
1224
1225 tmp = RT2860_BBP_CSR_KICK(1 << 17) | reg << 8 | val;
1226 return run_write(sc, RT2860_BBP_CSR_CFG0x101c, tmp);
1227}
1228
1229/*
1230 * Send a command to the 8051 microcontroller unit.
1231 */
1232int
1233run_mcu_cmd(struct run_softc *sc, uint8_t cmd, uint16_t arg)
1234{
1235 uint32_t tmp;
1236 int error, ntries;
1237
1238 for (ntries = 0; ntries < 100; ntries++) {
1239 if ((error = run_read(sc, RT2860_H2M_MAILBOX0x7010, &tmp)) != 0)
1240 return error;
1241 if (!(tmp & RT2860_H2M_BUSY(1 << 24)))
1242 break;
1243 }
1244 if (ntries == 100)
1245 return ETIMEDOUT60;
1246
1247 tmp = RT2860_H2M_BUSY(1 << 24) | RT2860_TOKEN_NO_INTR0xff << 16 | arg;
1248 if ((error = run_write(sc, RT2860_H2M_MAILBOX0x7010, tmp)) == 0)
1249 error = run_write(sc, RT2860_HOST_CMD0x0404, cmd);
1250 return error;
1251}
1252
1253/*
1254 * Add `delta' (signed) to each 4-bit sub-word of a 32-bit word.
1255 * Used to adjust per-rate Tx power registers.
1256 */
1257static __inline uint32_t
1258b4inc(uint32_t b32, int8_t delta)
1259{
1260 int8_t i, b4;
1261
1262 for (i = 0; i < 8; i++) {
1263 b4 = b32 & 0xf;
1264 b4 += delta;
1265 if (b4 < 0)
1266 b4 = 0;
1267 else if (b4 > 0xf)
1268 b4 = 0xf;
1269 b32 = b32 >> 4 | b4 << 28;
1270 }
1271 return b32;
1272}
1273
1274const char *
1275run_get_rf(int rev)
1276{
1277 switch (rev) {
1278 case RT2860_RF_28200x0001: return "RT2820";
1279 case RT2860_RF_28500x0002: return "RT2850";
1280 case RT2860_RF_27200x0003: return "RT2720";
1281 case RT2860_RF_27500x0004: return "RT2750";
1282 case RT3070_RF_30200x0005: return "RT3020";
1283 case RT3070_RF_20200x0006: return "RT2020";
1284 case RT3070_RF_30210x0007: return "RT3021";
1285 case RT3070_RF_30220x0008: return "RT3022";
1286 case RT3070_RF_30520x0009: return "RT3052";
1287 case RT3070_RF_30530x000d: return "RT3053";
1288 case RT5592_RF_55920x000f: return "RT5592";
1289 case RT5390_RF_53700x5370: return "RT5370";
1290 case RT5390_RF_53720x5372: return "RT5372";
1291 }
1292 return "unknown";
1293}
1294
1295void
1296run_rt3593_get_txpower(struct run_softc *sc)
1297{
1298 uint16_t addr, val;
18
←
'val' declared without an initial value
→
1299 int i;
1300
1301 /* Read power settings for 2GHz channels. */
1302 for (i = 0; i < 14; i += 2) {
19
←
Loop condition is true. Entering loop body
→
1303 addr = (sc->ntxchains
19.1
Field 'ntxchains' is not equal to 3
 == 3) ? RT3593_EEPROM_PWR2GHZ_BASE10x30 :
20
←
'?' condition is false
→
1304 RT2860_EEPROM_PWR2GHZ_BASE10x29;
1305 run_srom_read(sc, addr + i / 2, &val);
21
←
Calling 'run_srom_read'
→
27
←
Returning from 'run_srom_read'
→
1306 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
28
←
The left operand of '&' is a garbage value
1307 sc->txpow1[i + 1] = (int8_t)(val >> 8);
1308
1309 addr = (sc->ntxchains == 3) ? RT3593_EEPROM_PWR2GHZ_BASE20x37 :
1310 RT2860_EEPROM_PWR2GHZ_BASE20x30;
1311 run_srom_read(sc, addr + i / 2, &val);
1312 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
1313 sc->txpow2[i + 1] = (int8_t)(val >> 8);
1314
1315 if (sc->ntxchains == 3) {
1316 run_srom_read(sc, RT3593_EEPROM_PWR2GHZ_BASE30x3e + i / 2,
1317 &val);
1318 sc->txpow3[i + 0] = (int8_t)(val & 0xff);
1319 sc->txpow3[i + 1] = (int8_t)(val >> 8);
1320 }
1321 }
1322 /* Fix broken Tx power entries. */
1323 for (i = 0; i < 14; i++) {
1324 if (sc->txpow1[i] > 31)
1325 sc->txpow1[i] = 5;
1326 if (sc->txpow2[i] > 31)
1327 sc->txpow2[i] = 5;
1328 if (sc->ntxchains == 3) {
1329 if (sc->txpow3[i] > 31)
1330 sc->txpow3[i] = 5;
1331 }
1332 }
1333 /* Read power settings for 5GHz channels. */
1334 for (i = 0; i < 40; i += 2) {
1335 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE10x4b + i / 2, &val);
1336 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
1337 sc->txpow1[i + 15] = (int8_t)(val >> 8);
1338
1339 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE20x65 + i / 2, &val);
1340 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
1341 sc->txpow2[i + 15] = (int8_t)(val >> 8);
1342
1343 if (sc->ntxchains == 3) {
1344 run_srom_read(sc, RT3593_EEPROM_PWR5GHZ_BASE30x7f + i / 2,
1345 &val);
1346 sc->txpow3[i + 14] = (int8_t)(val & 0xff);
1347 sc->txpow3[i + 15] = (int8_t)(val >> 8);
1348 }
1349 }
1350}
1351
1352void
1353run_get_txpower(struct run_softc *sc)
1354{
1355 uint16_t val;
1356 int i;
1357
1358 /* Read power settings for 2GHz channels. */
1359 for (i = 0; i < 14; i += 2) {
1360 run_srom_read(sc, RT2860_EEPROM_PWR2GHZ_BASE10x29 + i / 2, &val);
1361 sc->txpow1[i + 0] = (int8_t)(val & 0xff);
1362 sc->txpow1[i + 1] = (int8_t)(val >> 8);
1363
1364 if (sc->mac_ver != 0x5390) {
1365 run_srom_read(sc,
1366 RT2860_EEPROM_PWR2GHZ_BASE20x30 + i / 2, &val);
1367 sc->txpow2[i + 0] = (int8_t)(val & 0xff);
1368 sc->txpow2[i + 1] = (int8_t)(val >> 8);
1369 }
1370 }
1371 /* Fix broken Tx power entries. */
1372 for (i = 0; i < 14; i++) {
1373 if (sc->mac_ver >= 0x5390) {
1374 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 27)
1375 sc->txpow1[i] = 5;
1376 } else {
1377 if (sc->txpow1[i] < 0 || sc->txpow1[i] > 31)
1378 sc->txpow1[i] = 5;
1379 }
1380 if (sc->mac_ver > 0x5390) {
1381 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 27)
1382 sc->txpow2[i] = 5;
1383 } else if (sc->mac_ver < 0x5390) {
1384 if (sc->txpow2[i] < 0 || sc->txpow2[i] > 31)
1385 sc->txpow2[i] = 5;
1386 }
1387 DPRINTF(("chan %d: power1=%d, power2=%d\n",
1388 rt2860_rf2850[i].chan, sc->txpow1[i], sc->txpow2[i]));
1389 }
1390 /* Read power settings for 5GHz channels. */
1391 for (i = 0; i < 40; i += 2) {
1392 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE10x3c + i / 2, &val);
1393 sc->txpow1[i + 14] = (int8_t)(val & 0xff);
1394 sc->txpow1[i + 15] = (int8_t)(val >> 8);
1395
1396 run_srom_read(sc, RT2860_EEPROM_PWR5GHZ_BASE20x53 + i / 2, &val);
1397 sc->txpow2[i + 14] = (int8_t)(val & 0xff);
1398 sc->txpow2[i + 15] = (int8_t)(val >> 8);
1399 }
1400 /* Fix broken Tx power entries. */
1401 for (i = 0; i < 40; i++ ) {
1402 if (sc->mac_ver != 0x5592) {
1403 if (sc->txpow1[14 + i] < -7 || sc->txpow1[14 + i] > 15)
1404 sc->txpow1[14 + i] = 5;
1405 if (sc->txpow2[14 + i] < -7 || sc->txpow2[14 + i] > 15)
1406 sc->txpow2[14 + i] = 5;
1407 }
1408 DPRINTF(("chan %d: power1=%d, power2=%d\n",
1409 rt2860_rf2850[14 + i].chan, sc->txpow1[14 + i],
1410 sc->txpow2[14 + i]));
1411 }
1412}
1413
1414int
1415run_read_eeprom(struct run_softc *sc)
1416{
1417 struct ieee80211com *ic = &sc->sc_ic;
1418 int8_t delta_2ghz, delta_5ghz;
1419 uint32_t tmp;
1420 uint16_t val;
1421 int ridx, ant, i;
1422
1423 /* check whether the ROM is eFUSE ROM or EEPROM */
1424 sc->sc_srom_read = run_eeprom_read_2;
1425 if (sc->mac_ver >= 0x3070) {
1
Assuming field 'mac_ver' is >= 12400
→
2
←
Taking true branch
→
1426 run_read(sc, RT3070_EFUSE_CTRL0x0580, &tmp);
1427 DPRINTF(("EFUSE_CTRL=0x%08x\n", tmp));
1428 if (tmp & RT3070_SEL_EFUSE(1U << 31) || sc->mac_ver == 0x3593)
1429 sc->sc_srom_read = run_efuse_read_2;
1430 }
1431
1432 /* read ROM version */
1433 run_srom_read(sc, RT2860_EEPROM_VERSION0x01, &val);
1434 DPRINTF(("EEPROM rev=%d, FAE=%d\n", val & 0xff, val >> 8));
1435
1436 /* read MAC address */
1437 run_srom_read(sc, RT2860_EEPROM_MAC010x02, &val);
1438 ic->ic_myaddr[0] = val & 0xff;
1439 ic->ic_myaddr[1] = val >> 8;
1440 run_srom_read(sc, RT2860_EEPROM_MAC230x03, &val);
1441 ic->ic_myaddr[2] = val & 0xff;
1442 ic->ic_myaddr[3] = val >> 8;
1443 run_srom_read(sc, RT2860_EEPROM_MAC450x04, &val);
1444 ic->ic_myaddr[4] = val & 0xff;
1445 ic->ic_myaddr[5] = val >> 8;
1446
1447 if (sc->mac_ver < 0x3593) {
3
←
Assuming field 'mac_ver' is >= 13715
→
4
←
Taking false branch
→
1448 /* read vendor BBP settings */
1449 for (i = 0; i < 10; i++) {
1450 run_srom_read(sc, RT2860_EEPROM_BBP_BASE0x78 + i, &val);
1451 sc->bbp[i].val = val & 0xff;
1452 sc->bbp[i].reg = val >> 8;
1453 DPRINTF(("BBP%d=0x%02x\n", sc->bbp[i].reg,
1454 sc->bbp[i].val));
1455 }
1456 if (sc->mac_ver >= 0x3071) {
1457 /* read vendor RF settings */
1458 for (i = 0; i < 10; i++) {
1459 run_srom_read(sc, RT3071_EEPROM_RF_BASE0x82 + i,
1460 &val);
1461 sc->rf[i].val = val & 0xff;
1462 sc->rf[i].reg = val >> 8;
1463 DPRINTF(("RF%d=0x%02x\n", sc->rf[i].reg,
1464 sc->rf[i].val));
1465 }
1466 }
1467 }
1468
1469 /* read RF frequency offset from EEPROM */
1470 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_FREQ_LEDS0x1d :
5
←
Assuming field 'mac_ver' is equal to 13715
→
6
←
'?' condition is false
→
1471 RT3593_EEPROM_FREQ0x22, &val);
1472 sc->freq = ((val & 0xff) != 0xff) ? val & 0xff : 0;
7
←
'?' condition is false
→
1473 DPRINTF(("EEPROM freq offset %d\n", sc->freq & 0xff));
1474 run_srom_read(sc, (sc->mac_ver
7.1
Field 'mac_ver' is equal to 13715
 != 0x3593) ? RT2860_EEPROM_FREQ_LEDS0x1d :
8
←
'?' condition is false
→
1475 RT3593_EEPROM_FREQ_LEDS0x21, &val);
1476 if ((val >> 8) != 0xff) {
9
←
Taking false branch
→
1477 /* read LEDs operating mode */
1478 sc->leds = val >> 8;
1479 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED10x1e :
1480 RT3593_EEPROM_LED10x22, &sc->led[0]);
1481 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED20x1f :
1482 RT3593_EEPROM_LED20x23, &sc->led[1]);
1483 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LED30x20 :
1484 RT3593_EEPROM_LED30x24, &sc->led[2]);
1485 } else {
1486 /* broken EEPROM, use default settings */
1487 sc->leds = 0x01;
1488 sc->led[0] = 0x5555;
1489 sc->led[1] = 0x2221;
1490 sc->led[2] = 0x5627; /* differs from RT2860 */
1491 }
1492 DPRINTF(("EEPROM LED mode=0x%02x, LEDs=0x%04x/0x%04x/0x%04x\n",
1493 sc->leds, sc->led[0], sc->led[1], sc->led[2]));
1494
1495 /* read RF information */
1496 if (sc->mac_ver
9.1
Field 'mac_ver' is not equal to 21392
 == 0x5390 || sc->mac_ver
9.2
Field 'mac_ver' is not equal to 21394
 == 0x5392)
10
←
Taking false branch
→
1497 run_srom_read(sc, 0x00, &val);
1498 else
1499 run_srom_read(sc, RT2860_EEPROM_ANTENNA0x1a, &val);
1500 if (val
10.1
'val' is equal to 65535
 == 0xffff) {
11
←
Taking true branch
→
1501 DPRINTF(("invalid EEPROM antenna info, using default\n"));
1502 if (sc->mac_ver
11.1
Field 'mac_ver' is not equal to 13682
 == 0x3572) {
12
←
Taking false branch
→
1503 /* default to RF3052 2T2R */
1504 sc->rf_rev = RT3070_RF_30520x0009;
1505 sc->ntxchains = 2;
1506 sc->nrxchains = 2;
1507 } else if (sc->mac_ver
12.1
Field 'mac_ver' is >= 12400
 >= 0x3070) {
13
←
Taking true branch
→
1508 /* default to RF3020 1T1R */
1509 sc->rf_rev = RT3070_RF_30200x0005;
1510 sc->ntxchains = 1;
1511 sc->nrxchains = 1;
1512 } else {
1513 /* default to RF2820 1T2R */
1514 sc->rf_rev = RT2860_RF_28200x0001;
1515 sc->ntxchains = 1;
1516 sc->nrxchains = 2;
1517 }
1518 } else {
1519 if (sc->mac_ver == 0x5390 || sc->mac_ver == 0x5392) {
1520 sc->rf_rev = val;
1521 run_srom_read(sc, RT2860_EEPROM_ANTENNA0x1a, &val);
1522 } else
1523 sc->rf_rev = (val >> 8) & 0xf;
1524 sc->ntxchains = (val >> 4) & 0xf;
1525 sc->nrxchains = val & 0xf;
1526 }
1527 DPRINTF(("EEPROM RF rev=0x%02x chains=%dT%dR\n",
1528 sc->rf_rev, sc->ntxchains, sc->nrxchains));
1529
1530 /* check if RF supports automatic Tx access gain control */
1531 run_srom_read(sc, RT2860_EEPROM_CONFIG0x1b, &val);
1532 DPRINTF(("EEPROM CFG 0x%04x\n", val));
1533 /* check if driver should patch the DAC issue */
1534 if ((val >> 8) != 0xff)
14
←
Taking false branch
→
1535 sc->patch_dac = (val >> 15) & 1;
1536 if ((val & 0xff) != 0xff) {
15
←
Taking false branch
→
1537 sc->ext_5ghz_lna = (val >> 3) & 1;
1538 sc->ext_2ghz_lna = (val >> 2) & 1;
1539 /* check if RF supports automatic Tx access gain control */
1540 sc->calib_2ghz = sc->calib_5ghz = (val >> 1) & 1;
1541 /* check if we have a hardware radio switch */
1542 sc->rfswitch = val & 1;
1543 }
1544
1545 /* Read Tx power settings. */
1546 if (sc->mac_ver
15.1
Field 'mac_ver' is equal to 13715
 == 0x3593)
16
←
Taking true branch
→
1547 run_rt3593_get_txpower(sc);
17
←
Calling 'run_rt3593_get_txpower'
→
1548 else
1549 run_get_txpower(sc);
1550
1551 /* read Tx power compensation for each Tx rate */
1552 run_srom_read(sc, RT2860_EEPROM_DELTAPWR0x28, &val);
1553 delta_2ghz = delta_5ghz = 0;
1554 if ((val & 0xff) != 0xff && (val & 0x80)) {
1555 delta_2ghz = val & 0xf;
1556 if (!(val & 0x40)) /* negative number */
1557 delta_2ghz = -delta_2ghz;
1558 }
1559 val >>= 8;
1560 if ((val & 0xff) != 0xff && (val & 0x80)) {
1561 delta_5ghz = val & 0xf;
1562 if (!(val & 0x40)) /* negative number */
1563 delta_5ghz = -delta_5ghz;
1564 }
1565 DPRINTF(("power compensation=%d (2GHz), %d (5GHz)\n",
1566 delta_2ghz, delta_5ghz));
1567
1568 for (ridx = 0; ridx < 5; ridx++) {
1569 uint32_t reg;
1570
1571 run_srom_read(sc, RT2860_EEPROM_RPWR0x6f + ridx * 2, &val);
1572 reg = val;
1573 run_srom_read(sc, RT2860_EEPROM_RPWR0x6f + ridx * 2 + 1, &val);
1574 reg |= (uint32_t)val << 16;
1575
1576 sc->txpow20mhz[ridx] = reg;
1577 sc->txpow40mhz_2ghz[ridx] = b4inc(reg, delta_2ghz);
1578 sc->txpow40mhz_5ghz[ridx] = b4inc(reg, delta_5ghz);
1579
1580 DPRINTF(("ridx %d: power 20MHz=0x%08x, 40MHz/2GHz=0x%08x, "
1581 "40MHz/5GHz=0x%08x\n", ridx, sc->txpow20mhz[ridx],
1582 sc->txpow40mhz_2ghz[ridx], sc->txpow40mhz_5ghz[ridx]));
1583 }
1584
1585 /* read RSSI offsets and LNA gains from EEPROM */
1586 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_2GHZ0x23 :
1587 RT3593_EEPROM_RSSI1_2GHZ0x28, &val);
1588 sc->rssi_2ghz[0] = val & 0xff; /* Ant A */
1589 sc->rssi_2ghz[1] = val >> 8; /* Ant B */
1590 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_2GHZ0x24 :
1591 RT3593_EEPROM_RSSI2_2GHZ0x29, &val);
1592 if (sc->mac_ver >= 0x3070) {
1593 if (sc->mac_ver == 0x3593) {
1594 sc->txmixgain_2ghz = 0;
1595 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
1596 } else {
1597 /*
1598 * On RT3070 chips (limited to 2 Rx chains), this ROM
1599 * field contains the Tx mixer gain for the 2GHz band.
1600 */
1601 if ((val & 0xff) != 0xff)
1602 sc->txmixgain_2ghz = val & 0x7;
1603 }
1604 DPRINTF(("tx mixer gain=%u (2GHz)\n", sc->txmixgain_2ghz));
1605 } else
1606 sc->rssi_2ghz[2] = val & 0xff; /* Ant C */
1607 if (sc->mac_ver == 0x3593)
1608 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ0x27, &val);
1609 sc->lna[2] = val >> 8; /* channel group 2 */
1610
1611 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI1_5GHZ0x25 :
1612 RT3593_EEPROM_RSSI1_5GHZ0x2a, &val);
1613 sc->rssi_5ghz[0] = val & 0xff; /* Ant A */
1614 sc->rssi_5ghz[1] = val >> 8; /* Ant B */
1615 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_RSSI2_5GHZ0x26 :
1616 RT3593_EEPROM_RSSI2_5GHZ0x2b, &val);
1617 if (sc->mac_ver == 0x3572) {
1618 /*
1619 * On RT3572 chips (limited to 2 Rx chains), this ROM
1620 * field contains the Tx mixer gain for the 5GHz band.
1621 */
1622 if ((val & 0xff) != 0xff)
1623 sc->txmixgain_5ghz = val & 0x7;
1624 DPRINTF(("tx mixer gain=%u (5GHz)\n", sc->txmixgain_5ghz));
1625 } else
1626 sc->rssi_5ghz[2] = val & 0xff; /* Ant C */
1627 if (sc->mac_ver == 0x3593) {
1628 sc->txmixgain_5ghz = 0;
1629 run_srom_read(sc, RT3593_EEPROM_LNA_5GHZ0x27, &val);
1630 }
1631 sc->lna[3] = val >> 8; /* channel group 3 */
1632
1633 run_srom_read(sc, (sc->mac_ver != 0x3593) ? RT2860_EEPROM_LNA0x22 :
1634 RT3593_EEPROM_LNA0x26, &val);
1635 sc->lna[0] = val & 0xff; /* channel group 0 */
1636 sc->lna[1] = val >> 8; /* channel group 1 */
1637
1638 /* fix broken 5GHz LNA entries */
1639 if (sc->lna[2] == 0 || sc->lna[2] == 0xff) {
1640 DPRINTF(("invalid LNA for channel group %d\n", 2));
1641 sc->lna[2] = sc->lna[1];
1642 }
1643 if (sc->lna[3] == 0 || sc->lna[3] == 0xff) {
1644 DPRINTF(("invalid LNA for channel group %d\n", 3));
1645 sc->lna[3] = sc->lna[1];
1646 }
1647
1648 /* fix broken RSSI offset entries */
1649 for (ant = 0; ant < 3; ant++) {
1650 if (sc->rssi_2ghz[ant] < -10 || sc->rssi_2ghz[ant] > 10) {
1651 DPRINTF(("invalid RSSI%d offset: %d (2GHz)\n",
1652 ant + 1, sc->rssi_2ghz[ant]));
1653 sc->rssi_2ghz[ant] = 0;
1654 }
1655 if (sc->rssi_5ghz[ant] < -10 || sc->rssi_5ghz[ant] > 10) {
1656 DPRINTF(("invalid RSSI%d offset: %d (5GHz)\n",
1657 ant + 1, sc->rssi_5ghz[ant]));
1658 sc->rssi_5ghz[ant] = 0;
1659 }
1660 }
1661 return 0;
1662}
1663
1664struct ieee80211_node *
1665run_node_alloc(struct ieee80211com *ic)
1666{
1667 return malloc(sizeof (struct run_node), M_USBDEV102, M_NOWAIT0x0002 | M_ZERO0x0008);
1668}
1669
1670int
1671run_media_change(struct ifnet *ifp)
1672{
1673 struct run_softc *sc = ifp->if_softc;
1674 struct ieee80211com *ic = &sc->sc_ic;
1675 uint8_t rate, ridx;
1676 int error;
1677
1678 error = ieee80211_media_change(ifp);
1679 if (error != ENETRESET52)
1680 return error;
1681
1682 if (ic->ic_fixed_rate != -1) {
1683 rate = ic->ic_sup_rates[ic->ic_curmode].
1684 rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL0x7f;
1685 for (ridx = 0; ridx <= RT2860_RIDX_MAX11; ridx++)
1686 if (rt2860_rates[ridx].rate == rate)
1687 break;
1688 sc->fixed_ridx = ridx;
1689 }
1690
1691 if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
1692 (IFF_UP0x1 | IFF_RUNNING0x40)) {
1693 run_stop(ifp, 0);
1694 error = run_init(ifp);
1695 }
1696
1697 return error;
1698}
1699
1700void
1701run_next_scan(void *arg)
1702{
1703 struct run_softc *sc = arg;
1704 int s;
1705
1706 if (usbd_is_dying(sc->sc_udev))
1707 return;
1708
1709 usbd_ref_incr(sc->sc_udev);
1710
1711 s = splnet()splraise(0x7);
1712 if (sc->sc_ic.ic_state == IEEE80211_S_SCAN)
1713 ieee80211_next_scan(&sc->sc_ic.ic_ific_ac.ac_if);
1714 splx(s)spllower(s);
1715
1716 usbd_ref_decr(sc->sc_udev);
1717}
1718
1719void
1720run_task(void *arg)
1721{
1722 struct run_softc *sc = arg;
1723 struct run_host_cmd_ring *ring = &sc->cmdq;
1724 struct run_host_cmd *cmd;
1725 int s;
1726
1727 if (usbd_is_dying(sc->sc_udev))
1728 return;
1729
1730 /* process host commands */
1731 s = splusb()splraise(0x5);
1732 while (ring->next != ring->cur) {
1733 cmd = &ring->cmd[ring->next];
1734 splx(s)spllower(s);
1735 /* callback */
1736 cmd->cb(sc, cmd->data);
1737 s = splusb()splraise(0x5);
1738 ring->queued--;
1739 ring->next = (ring->next + 1) % RUN_HOST_CMD_RING_COUNT32;
1740 }
1741 splx(s)spllower(s);
1742}
1743
1744void
1745run_do_async(struct run_softc *sc, void (*cb)(struct run_softc *, void *),
1746 void *arg, int len)
1747{
1748 struct run_host_cmd_ring *ring = &sc->cmdq;
1749 struct run_host_cmd *cmd;
1750 int s;
1751
1752 if (usbd_is_dying(sc->sc_udev))
1753 return;
1754
1755 s = splusb()splraise(0x5);
1756 cmd = &ring->cmd[ring->cur];
1757 cmd->cb = cb;
1758 KASSERT(len <= sizeof (cmd->data))((len <= sizeof (cmd->data)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/usb/if_run.c", 1758, "len <= sizeof (cmd->data)"
));
1759 memcpy(cmd->data, arg, len)__builtin_memcpy((cmd->data), (arg), (len));
1760 ring->cur = (ring->cur + 1) % RUN_HOST_CMD_RING_COUNT32;
1761
1762 /* if there is no pending command already, schedule a task */
1763 if (++ring->queued == 1)
1764 usb_add_task(sc->sc_udev, &sc->sc_task);
1765 splx(s)spllower(s);
1766}
1767
1768int
1769run_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1770{
1771 struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
1772 struct run_cmd_newstate cmd;
1773
1774 /* do it in a process context */
1775 cmd.state = nstate;
1776 cmd.arg = arg;
1777 run_do_async(sc, run_newstate_cb, &cmd, sizeof cmd);
1778 return 0;
1779}
1780
1781void
1782run_newstate_cb(struct run_softc *sc, void *arg)
1783{
1784 struct run_cmd_newstate *cmd = arg;
1785 struct ieee80211com *ic = &sc->sc_ic;
1786 enum ieee80211_state ostate;
1787 struct ieee80211_node *ni;
1788 uint32_t tmp, sta[3];
1789 uint8_t wcid;
1790 int s;
1791
1792 s = splnet()splraise(0x7);
1793 ostate = ic->ic_state;
1794
1795 if (ostate == IEEE80211_S_RUN) {
1796 /* turn link LED off */
1797 run_set_leds(sc, RT2860_LED_RADIO(1 << 13));
1798 }
1799
1800 switch (cmd->state) {
1801 case IEEE80211_S_INIT:
1802 if (ostate == IEEE80211_S_RUN) {
1803 /* abort TSF synchronization */
1804 run_read(sc, RT2860_BCN_TIME_CFG0x1114, &tmp);
1805 run_write(sc, RT2860_BCN_TIME_CFG0x1114,
1806 tmp & ~(RT2860_BCN_TX_EN(1 << 20) | RT2860_TSF_TIMER_EN(1 << 16) |
1807 RT2860_TBTT_TIMER_EN(1 << 19)));
1808 }
1809 break;
1810
1811 case IEEE80211_S_SCAN:
1812 run_set_chan(sc, ic->ic_bss->ni_chan);
1813 if (!usbd_is_dying(sc->sc_udev))
1814 timeout_add_msec(&sc->scan_to, 200);
1815 break;
1816
1817 case IEEE80211_S_AUTH:
1818 case IEEE80211_S_ASSOC:
1819 run_set_chan(sc, ic->ic_bss->ni_chan);
1820 break;
1821
1822 case IEEE80211_S_RUN:
1823 run_set_chan(sc, ic->ic_bss->ni_chan);
1824
1825 ni = ic->ic_bss;
1826
1827 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1828 run_updateslot(ic);
1829 run_enable_mrr(sc);
1830 run_set_txpreamble(sc);
1831 run_set_basicrates(sc);
1832 run_set_bssid(sc, ni->ni_bssid);
1833 }
1834 if (ic->ic_opmode == IEEE80211_M_STA) {
1835 /* add BSS entry to the WCID table */
1836 wcid = RUN_AID2WCID(ni->ni_associd)((ni->ni_associd) & 0xff);
1837 run_write_region_1(sc, RT2860_WCID_ENTRY(wcid)(0x1800 + (wcid) * 8),
1838 ni->ni_macaddr, IEEE80211_ADDR_LEN6);
1839
1840 /* fake a join to init the tx rate */
1841 run_newassoc(ic, ni, 1);
1842 }
1843 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1844 run_enable_tsf_sync(sc);
1845
1846 /* clear statistic registers used by AMRR */
1847 run_read_region_1(sc, RT2860_TX_STA_CNT00x170c,
1848 (uint8_t *)sta, sizeof sta);
1849 /* start calibration timer */
1850 if (!usbd_is_dying(sc->sc_udev))
1851 timeout_add_sec(&sc->calib_to, 1);
1852 }
1853
1854 /* turn link LED on */
1855 run_set_leds(sc, RT2860_LED_RADIO(1 << 13) |
1856 (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0080) != 0
) ?
1857 RT2860_LED_LINK_2GHZ(1 << 14) : RT2860_LED_LINK_5GHZ(1 << 15)));
1858 break;
1859 }
1860 (void)sc->sc_newstate(ic, cmd->state, cmd->arg);
1861 splx(s)spllower(s);
1862}
1863
1864void
1865run_updateedca(struct ieee80211com *ic)
1866{
1867 /* do it in a process context */
1868 run_do_async(ic->ic_softcic_ac.ac_if.if_softc, run_updateedca_cb, NULL((void *)0), 0);
1869}
1870
1871/* ARGSUSED */
1872void
1873run_updateedca_cb(struct run_softc *sc, void *arg)
1874{
1875 struct ieee80211com *ic = &sc->sc_ic;
1876 int s, aci;
1877
1878 s = splnet()splraise(0x7);
1879 /* update MAC TX configuration registers */
1880 for (aci = 0; aci < EDCA_NUM_AC4; aci++) {
1881 run_write(sc, RT2860_EDCA_AC_CFG(aci)(0x1300 + (aci) * 4),
1882 ic->ic_edca_ac[aci].ac_ecwmax << 16 |
1883 ic->ic_edca_ac[aci].ac_ecwmin << 12 |
1884 ic->ic_edca_ac[aci].ac_aifsn << 8 |
1885 ic->ic_edca_ac[aci].ac_txoplimit);
1886 }
1887
1888 /* update SCH/DMA registers too */
1889 run_write(sc, RT2860_WMM_AIFSN_CFG0x0214,
1890 ic->ic_edca_ac[EDCA_AC_VO].ac_aifsn << 12 |
1891 ic->ic_edca_ac[EDCA_AC_VI].ac_aifsn << 8 |
1892 ic->ic_edca_ac[EDCA_AC_BK].ac_aifsn << 4 |
1893 ic->ic_edca_ac[EDCA_AC_BE].ac_aifsn);
1894 run_write(sc, RT2860_WMM_CWMIN_CFG0x0218,
1895 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmin << 12 |
1896 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmin << 8 |
1897 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmin << 4 |
1898 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmin);
1899 run_write(sc, RT2860_WMM_CWMAX_CFG0x021c,
1900 ic->ic_edca_ac[EDCA_AC_VO].ac_ecwmax << 12 |
1901 ic->ic_edca_ac[EDCA_AC_VI].ac_ecwmax << 8 |
1902 ic->ic_edca_ac[EDCA_AC_BK].ac_ecwmax << 4 |
1903 ic->ic_edca_ac[EDCA_AC_BE].ac_ecwmax);
1904 run_write(sc, RT2860_WMM_TXOP0_CFG0x0220,
1905 ic->ic_edca_ac[EDCA_AC_BK].ac_txoplimit << 16 |
1906 ic->ic_edca_ac[EDCA_AC_BE].ac_txoplimit);
1907 run_write(sc, RT2860_WMM_TXOP1_CFG0x0224,
1908 ic->ic_edca_ac[EDCA_AC_VO].ac_txoplimit << 16 |
1909 ic->ic_edca_ac[EDCA_AC_VI].ac_txoplimit);
1910 splx(s)spllower(s);
1911}
1912
1913int
1914run_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
1915 struct ieee80211_key *k)
1916{
1917 struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
1918 struct run_cmd_key cmd;
1919
1920 /* defer setting of WEP keys until interface is brought up */
1921 if ((ic->ic_ific_ac.ac_if.if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) !=
1922 (IFF_UP0x1 | IFF_RUNNING0x40))
1923 return 0;
1924
1925 /* do it in a process context */
1926 cmd.key = *k;
1927 cmd.ni = ni;
1928 run_do_async(sc, run_set_key_cb, &cmd, sizeof cmd);
1929 sc->sc_key_tasks++;
1930
1931 return EBUSY16;
1932}
1933
1934void
1935run_set_key_cb(struct run_softc *sc, void *arg)
1936{
1937 struct ieee80211com *ic = &sc->sc_ic;
1938 struct run_cmd_key *cmd = arg;
1939 struct ieee80211_key *k = &cmd->key;
1940 uint32_t attr;
1941 uint16_t base;
1942 uint8_t mode, wcid, iv[8];
1943
1944 sc->sc_key_tasks--;
1945
1946 /* map net80211 cipher to RT2860 security mode */
1947 switch (k->k_cipher) {
1948 case IEEE80211_CIPHER_WEP40:
1949 mode = RT2860_MODE_WEP401;
1950 break;
1951 case IEEE80211_CIPHER_WEP104:
1952 mode = RT2860_MODE_WEP1042;
1953 break;
1954 case IEEE80211_CIPHER_TKIP:
1955 mode = RT2860_MODE_TKIP3;
1956 break;
1957 case IEEE80211_CIPHER_CCMP:
1958 mode = RT2860_MODE_AES_CCMP4;
1959 break;
1960 default:
1961 IEEE80211_SEND_MGMT(ic, cmd->ni, IEEE80211_FC0_SUBTYPE_DEAUTH,((*(ic)->ic_send_mgmt)(ic, cmd->ni, 0xc0, IEEE80211_REASON_AUTH_LEAVE
, 0))
1962 IEEE80211_REASON_AUTH_LEAVE)((*(ic)->ic_send_mgmt)(ic, cmd->ni, 0xc0, IEEE80211_REASON_AUTH_LEAVE
, 0));
1963 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1)));
1964 return;
1965 }
1966
1967 if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) {
1968 wcid = 0; /* NB: update WCID0 for group keys */
1969 base = RT2860_SKEY(0, k->k_id)(0x6c00 + (0) * 128 + (k->k_id) * 32);
1970 } else {
1971 wcid = (cmd->ni != NULL((void *)0)) ? RUN_AID2WCID(cmd->ni->ni_associd)((cmd->ni->ni_associd) & 0xff) : 0;
1972 base = RT2860_PKEY(wcid)(0x4000 + (wcid) * 32);
1973 }
1974
1975 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
1976 run_write_region_1(sc, base, k->k_key, 16);
1977 run_write_region_1(sc, base + 16, &k->k_key[24], 8);
1978 run_write_region_1(sc, base + 24, &k->k_key[16], 8);
1979 } else {
1980 /* roundup len to 16-bit: XXX fix write_region_1() instead */
1981 run_write_region_1(sc, base, k->k_key, (k->k_len + 1) & ~1);
1982 }
1983
1984 if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001) ||
1985 (k->k_flags & IEEE80211_KEY_TX0x00000002)) {
1986 /* set initial packet number in IV+EIV */
1987 if (k->k_cipher == IEEE80211_CIPHER_WEP40 ||
1988 k->k_cipher == IEEE80211_CIPHER_WEP104) {
1989 memset(iv, 0, sizeof iv)__builtin_memset((iv), (0), (sizeof iv));
1990 iv[3] = sc->sc_ic.ic_def_txkey << 6;
1991 } else {
1992 if (k->k_cipher == IEEE80211_CIPHER_TKIP) {
1993 iv[0] = k->k_tsc >> 8;
1994 iv[1] = (iv[0] | 0x20) & 0x7f;
1995 iv[2] = k->k_tsc;
1996 } else /* CCMP */ {
1997 iv[0] = k->k_tsc;
1998 iv[1] = k->k_tsc >> 8;
1999 iv[2] = 0;
2000 }
2001 iv[3] = k->k_id << 6 | IEEE80211_WEP_EXTIV0x20;
2002 iv[4] = k->k_tsc >> 16;
2003 iv[5] = k->k_tsc >> 24;
2004 iv[6] = k->k_tsc >> 32;
2005 iv[7] = k->k_tsc >> 40;
2006 }
2007 run_write_region_1(sc, RT2860_IVEIV(wcid)(0x6000 + (wcid) * 8), iv, 8);
2008 }
2009
2010 if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) {
2011 /* install group key */
2012 run_read(sc, RT2860_SKEY_MODE_0_70x7000, &attr);
2013 attr &= ~(0xf << (k->k_id * 4));
2014 attr |= mode << (k->k_id * 4);
2015 run_write(sc, RT2860_SKEY_MODE_0_70x7000, attr);
2016 } else {
2017 /* install pairwise key */
2018 run_read(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), &attr);
2019 attr = (attr & ~0xf) | (mode << 1) | RT2860_RX_PKEY_EN(1 << 0);
2020 run_write(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), attr);
2021 }
2022
2023 if (sc->sc_key_tasks == 0) {
2024 if (cmd->ni != NULL((void *)0))
2025 cmd->ni->ni_port_valid = 1;
2026 ieee80211_set_link_state(ic, LINK_STATE_UP4);
2027 }
2028}
2029
2030void
2031run_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
2032 struct ieee80211_key *k)
2033{
2034 struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
2035 struct run_cmd_key cmd;
2036
2037 if (!(ic->ic_ific_ac.ac_if.if_flags & IFF_RUNNING0x40) ||
2038 ic->ic_state != IEEE80211_S_RUN)
2039 return; /* nothing to do */
2040
2041 /* do it in a process context */
2042 cmd.key = *k;
2043 cmd.ni = ni;
2044 run_do_async(sc, run_delete_key_cb, &cmd, sizeof cmd);
2045}
2046
2047void
2048run_delete_key_cb(struct run_softc *sc, void *arg)
2049{
2050 struct run_cmd_key *cmd = arg;
2051 struct ieee80211_key *k = &cmd->key;
2052 uint32_t attr;
2053 uint8_t wcid;
2054
2055 if (k->k_flags & IEEE80211_KEY_GROUP0x00000001) {
2056 /* remove group key */
2057 run_read(sc, RT2860_SKEY_MODE_0_70x7000, &attr);
2058 attr &= ~(0xf << (k->k_id * 4));
2059 run_write(sc, RT2860_SKEY_MODE_0_70x7000, attr);
2060
2061 } else {
2062 /* remove pairwise key */
2063 wcid = (cmd->ni != NULL((void *)0)) ? RUN_AID2WCID(cmd->ni->ni_associd)((cmd->ni->ni_associd) & 0xff) : 0;
2064 run_read(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), &attr);
2065 attr &= ~0xf;
2066 run_write(sc, RT2860_WCID_ATTR(wcid)(0x6800 + (wcid) * 4), attr);
2067 }
2068}
2069
2070void
2071run_calibrate_to(void *arg)
2072{
2073 /* do it in a process context */
2074 run_do_async(arg, run_calibrate_cb, NULL((void *)0), 0);
2075 /* next timeout will be rescheduled in the calibration task */
2076}
2077
2078/* ARGSUSED */
2079void
2080run_calibrate_cb(struct run_softc *sc, void *arg)
2081{
2082 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
2083 uint32_t sta[3];
2084 int s, error;
2085
2086 /* read statistic counters (clear on read) and update AMRR state */
2087 error = run_read_region_1(sc, RT2860_TX_STA_CNT00x170c, (uint8_t *)sta,
2088 sizeof sta);
2089 if (error != 0)
2090 goto skip;
2091
2092 DPRINTF(("retrycnt=%d txcnt=%d failcnt=%d\n",
2093 letoh32(sta[1]) >> 16, letoh32(sta[1]) & 0xffff,
2094 letoh32(sta[0]) & 0xffff));
2095
2096 s = splnet()splraise(0x7);
2097 /* count failed TX as errors */
2098 ifp->if_oerrorsif_data.ifi_oerrors += letoh32(sta[0])((__uint32_t)(sta[0])) & 0xffff;
2099
2100 sc->amn.amn_retrycnt =
2101 (letoh32(sta[0])((__uint32_t)(sta[0])) & 0xffff) + /* failed TX count */
2102 (letoh32(sta[1])((__uint32_t)(sta[1])) >> 16); /* TX retransmission count */
2103
2104 sc->amn.amn_txcnt =
2105 sc->amn.amn_retrycnt +
2106 (letoh32(sta[1])((__uint32_t)(sta[1])) & 0xffff); /* successful TX count */
2107
2108 ieee80211_amrr_choose(&sc->amrr, sc->sc_ic.ic_bss, &sc->amn);
2109 splx(s)spllower(s);
2110
2111skip:
2112 if (!usbd_is_dying(sc->sc_udev))
2113 timeout_add_sec(&sc->calib_to, 1);
2114}
2115
2116void
2117run_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew)
2118{
2119 struct run_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
2120 struct run_node *rn = (void *)ni;
2121 struct ieee80211_rateset *rs = &ni->ni_rates;
2122 uint8_t rate;
2123 int ridx, i, j;
2124
2125 DPRINTF(("new assoc isnew=%d addr=%s\n",
2126 isnew, ether_sprintf(ni->ni_macaddr)));
2127
2128 ieee80211_amrr_node_init(&sc->amrr, &sc->amn);
2129 /* start at lowest available bit-rate, AMRR will raise */
2130 ni->ni_txrate = 0;
2131
2132 for (i = 0; i < rs->rs_nrates; i++) {
2133 rate = rs->rs_rates[i] & IEEE80211_RATE_VAL0x7f;
2134 /* convert 802.11 rate to hardware rate index */
2135 for (ridx = 0; ridx < RT2860_RIDX_MAX11; ridx++)
2136 if (rt2860_rates[ridx].rate == rate)
2137 break;
2138 rn->ridx[i] = ridx;
2139 /* determine rate of control response frames */
2140 for (j = i; j >= 0; j--) {
2141 if ((rs->rs_rates[j] & IEEE80211_RATE_BASIC0x80) &&
2142 rt2860_rates[rn->ridx[i]].phy ==
2143 rt2860_rates[rn->ridx[j]].phy)
2144 break;
2145 }
2146 if (j >= 0) {
2147 rn->ctl_ridx[i] = rn->ridx[j];
2148 } else {
2149 /* no basic rate found, use mandatory one */
2150 rn->ctl_ridx[i] = rt2860_rates[ridx].ctl_ridx;
2151 }
2152 DPRINTF(("rate=0x%02x ridx=%d ctl_ridx=%d\n",
2153 rs->rs_rates[i], rn->ridx[i], rn->ctl_ridx[i]));
2154 }
2155}
2156
2157/*
2158 * Return the Rx chain with the highest RSSI for a given frame.
2159 */
2160static __inline uint8_t
2161run_maxrssi_chain(struct run_softc *sc, const struct rt2860_rxwi *rxwi)
2162{
2163 uint8_t rxchain = 0;
2164
2165 if (sc->nrxchains > 1) {
2166 if (rxwi->rssi[1] > rxwi->rssi[rxchain])
2167 rxchain = 1;
2168 if (sc->nrxchains > 2)
2169 if (rxwi->rssi[2] > rxwi->rssi[rxchain])
2170 rxchain = 2;
2171 }
2172 return rxchain;
2173}
2174
2175void
2176run_rx_frame(struct run_softc *sc, uint8_t *buf, int dmalen,
2177 struct mbuf_list *ml)
2178{
2179 struct ieee80211com *ic = &sc->sc_ic;
2180 struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
2181 struct ieee80211_frame *wh;
2182 struct ieee80211_rxinfo rxi;
2183 struct ieee80211_node *ni;
2184 struct rt2870_rxd *rxd;
2185 struct rt2860_rxwi *rxwi;
2186 struct mbuf *m;
2187 uint32_t flags;
2188 uint16_t len;
2189#if NBPFILTER1 > 0
2190 uint16_t phy;
2191#endif
2192 uint16_t rxwisize;
2193 uint8_t ant, rssi;
2194 int s;
2195
2196 rxwi = (struct rt2860_rxwi *)buf;
2197 rxwisize = sizeof(struct rt2860_rxwi);
2198 if (sc->mac_ver == 0x5592)
2199 rxwisize += sizeof(uint64_t);
2200 else if (sc->mac_ver == 0x3593)
2201 rxwisize += sizeof(uint32_t);
2202 len = letoh16(rxwi->len)((__uint16_t)(rxwi->len)) & 0xfff;
2203 if (__predict_false(len > dmalen)__builtin_expect(((len > dmalen) != 0), 0)) {
2204 DPRINTF(("bad RXWI length %u > %u\n", len, dmalen));
2205 return;
2206 }
2207 if (len > MCLBYTES(1 << 11)) {
2208 DPRINTF(("frame too large (length=%d)\n", len));
2209 ifp->if_ierrorsif_data.ifi_ierrors++;
2210 return;
2211 }
2212 /* Rx descriptor is located at the end */
2213 rxd = (struct rt2870_rxd *)(buf + dmalen);
2214 flags = letoh32(rxd->flags)((__uint32_t)(rxd->flags));
2215
2216 if (__predict_false(flags & (RT2860_RX_CRCERR | RT2860_RX_ICVERR))__builtin_expect(((flags & ((1 << 8) | (1 << 9
))) != 0), 0)) {
2217 ifp->if_ierrorsif_data.ifi_ierrors++;
2218 return;
2219 }
2220
2221 if (__predict_false((flags & RT2860_RX_MICERR))__builtin_expect((((flags & (1 << 10))) != 0), 0)) {
2222 /* report MIC failures to net80211 for TKIP */
2223 ic->ic_stats.is_rx_locmicfail++;
2224 ieee80211_michael_mic_failure(ic, 0/* XXX */);
2225 ifp->if_ierrorsif_data.ifi_ierrors++;
2226 return;
2227 }
2228
2229 wh = (struct ieee80211_frame *)(buf + rxwisize);
2230 rxi.rxi_flags = 0;
2231 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED0x40) {
2232 wh->i_fc[1] &= ~IEEE80211_FC1_PROTECTED0x40;
2233 rxi.rxi_flags |= IEEE80211_RXI_HWDEC0x00000001;
2234 }
2235
2236 if (flags & RT2860_RX_L2PAD(1 << 14)) {
2237 u_int hdrlen = ieee80211_get_hdrlen(wh);
2238 memmove((caddr_t)wh + 2, wh, hdrlen)__builtin_memmove(((caddr_t)wh + 2), (wh), (hdrlen));
2239 wh = (struct ieee80211_frame *)((caddr_t)wh + 2);
2240 }
2241
2242 /* could use m_devget but net80211 wants contig mgmt frames */
2243 MGETHDR(m, M_DONTWAIT, MT_DATA)m = m_gethdr((0x0002), (1));
2244 if (__predict_false(m == NULL)__builtin_expect(((m == ((void *)0)) != 0), 0)) {
2245 ifp->if_ierrorsif_data.ifi_ierrors++;
2246 return;
2247 }
2248 if (len > MHLEN((256 - sizeof(struct m_hdr)) - sizeof(struct pkthdr))) {
2249 MCLGET(m, M_DONTWAIT)(void) m_clget((m), (0x0002), (1 << 11));
2250 if (__predict_false(!(m->m_flags & M_EXT))__builtin_expect(((!(m->m_hdr.mh_flags & 0x0001)) != 0
), 0)) {
2251 ifp->if_ierrorsif_data.ifi_ierrors++;
2252 m_freem(m);
2253 return;
2254 }
2255 }
2256 /* finalize mbuf */
2257 memcpy(mtod(m, caddr_t), wh, len)__builtin_memcpy((((caddr_t)((m)->m_hdr.mh_data))), (wh), (
len));
2258 m->m_pkthdrM_dat.MH.MH_pkthdr.len = m->m_lenm_hdr.mh_len = len;
2259
2260 ant = run_maxrssi_chain(sc, rxwi);
2261 rssi = rxwi->rssi[ant];
2262
2263#if NBPFILTER1 > 0
2264 if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) {
2265 struct run_rx_radiotap_header *tap = &sc->sc_rxtapsc_rxtapu.th;
2266 struct mbuf mb;
2267
2268 tap->wr_flags = 0;
2269 tap->wr_chan_freq = htole16(ic->ic_ibss_chan->ic_freq)((__uint16_t)(ic->ic_ibss_chan->ic_freq));
2270 tap->wr_chan_flags = htole16(ic->ic_ibss_chan->ic_flags)((__uint16_t)(ic->ic_ibss_chan->ic_flags));
2271 tap->wr_antsignal = rssi;
2272 tap->wr_antenna = ant;
2273 tap->wr_dbm_antsignal = run_rssi2dbm(sc, rssi, ant);
2274 tap->wr_rate = 2; /* in case it can't be found below */
2275 phy = letoh16(rxwi->phy)((__uint16_t)(rxwi->phy));
2276 switch (phy & RT2860_PHY_MODE0xc000) {
2277 case RT2860_PHY_CCK(0 << 14):
2278 switch ((phy & RT2860_PHY_MCS0x7f) & ~RT2860_PHY_SHPRE(1 << 3)) {
2279 case 0: tap->wr_rate = 2; break;
2280 case 1: tap->wr_rate = 4; break;
2281 case 2: tap->wr_rate = 11; break;
2282 case 3: tap->wr_rate = 22; break;
2283 }
2284 if (phy & RT2860_PHY_SHPRE(1 << 3))
2285 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02;
2286 break;
2287 case RT2860_PHY_OFDM(1 << 14):
2288 switch (phy & RT2860_PHY_MCS0x7f) {
2289 case 0: tap->wr_rate = 12; break;
2290 case 1: tap->wr_rate = 18; break;
2291 case 2: tap->wr_rate = 24; break;
2292 case 3: tap->wr_rate = 36; break;
2293 case 4: tap->wr_rate = 48; break;
2294 case 5: tap->wr_rate = 72; break;
2295 case 6: tap->wr_rate = 96; break;
2296 case 7: tap->wr_rate = 108; break;
2297 }
2298 break;
2299 }
2300 mb.m_datam_hdr.mh_data = (caddr_t)tap;
2301 mb.m_lenm_hdr.mh_len = sc->sc_rxtap_len;
2302 mb.m_nextm_hdr.mh_next = m;
2303 mb.m_nextpktm_hdr.mh_nextpkt = NULL((void *)0);
2304 mb.m_typem_hdr.mh_type = 0;
2305 mb.m_flagsm_hdr.mh_flags = 0;
2306 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_IN(1 << 0));
2307 }
2308#endif
2309
2310 s = splnet()splraise(0x7);
2311 ni = ieee80211_find_rxnode(ic, wh);
2312 rxi.rxi_rssi = rssi;
2313 rxi.rxi_tstamp = 0; /* unused */
2314 ieee80211_inputm(ifp, m, ni, &rxi, ml);
2315
2316 /* node is no longer needed */
2317 ieee80211_release_node(ic, ni);
2318 splx(s)spllower(s);
2319}
2320
2321void
2322run_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2323{
2324 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
2325 struct run_rx_data *data = priv;
2326 struct run_softc *sc = data->sc;
2327 uint8_t *buf;
2328 uint32_t dmalen;
2329 int xferlen;
2330 uint16_t rxwisize;
2331
2332 rxwisize = sizeof(struct rt2860_rxwi);
2333 if (sc->mac_ver == 0x5592)
2334 rxwisize += sizeof(uint64_t);
2335 else if (sc->mac_ver == 0x3593)
2336 rxwisize += sizeof(uint32_t);
2337
2338 if (__predict_false(status != USBD_NORMAL_COMPLETION)__builtin_expect(((status != USBD_NORMAL_COMPLETION) != 0), 0
)) {
2339 DPRINTF(("RX status=%d\n", status));
2340 if (status == USBD_STALLED)
2341 usbd_clear_endpoint_stall_async(sc->rxq.pipeh);
2342 if (status != USBD_CANCELLED)
2343 goto skip;
2344 return;
2345 }
2346 usbd_get_xfer_status(xfer, NULL((void *)0), NULL((void *)0), &xferlen, NULL((void *)0));
2347
2348 if (__predict_false(xferlen < sizeof (uint32_t) + rxwisize +__builtin_expect(((xferlen < sizeof (uint32_t) + rxwisize +
sizeof(struct rt2870_rxd)) != 0), 0)
2349 sizeof(struct rt2870_rxd))__builtin_expect(((xferlen < sizeof (uint32_t) + rxwisize +
sizeof(struct rt2870_rxd)) != 0), 0)) {
2350 DPRINTF(("xfer too short %d\n", xferlen));
2351 goto skip;
2352 }
2353
2354 /* HW can aggregate multiple 802.11 frames in a single USB xfer */
2355 buf = data->buf;
2356 while (xferlen > 8) {
2357 dmalen = letoh32(*(uint32_t *)buf)((__uint32_t)(*(uint32_t *)buf)) & 0xffff;
2358
2359 if (__predict_false(dmalen == 0 || (dmalen & 3) != 0)__builtin_expect(((dmalen == 0 || (dmalen & 3) != 0) != 0
), 0)) {
2360 DPRINTF(("bad DMA length %u\n", dmalen));
2361 break;
2362 }
2363 if (__predict_false(dmalen + 8 > xferlen)__builtin_expect(((dmalen + 8 > xferlen) != 0), 0)) {
2364 DPRINTF(("bad DMA length %u > %d\n",
2365 dmalen + 8, xferlen));
2366 break;
2367 }
2368 run_rx_frame(sc, buf + sizeof (uint32_t), dmalen, &ml);
2369 buf += dmalen + 8;
2370 xferlen -= dmalen + 8;
2371 }
2372 if_input(&sc->sc_ic.ic_ific_ac.ac_if, &ml);
2373
2374skip: /* setup a new transfer */
2375 usbd_setup_xfer(xfer, sc->rxq.pipeh, data, data->buf, RUN_MAX_RXSZ4096,
2376 USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01, USBD_NO_TIMEOUT0, run_rxeof);
2377 (void)usbd_transfer(data->xfer);
2378}
2379
2380void
2381run_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2382{
2383 struct run_tx_data *data = priv;
2384 struct run_softc *sc = data->sc;
2385 struct run_tx_ring *txq = &sc->txq[data->qid];
2386 struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
2387 int s;
2388
2389 s = splnet()splraise(0x7);
2390 txq->queued--;
2391 sc->qfullmsk &= ~(1 << data->qid);
2392
2393 if (__predict_false(status != USBD_NORMAL_COMPLETION)__builtin_expect(((status != USBD_NORMAL_COMPLETION) != 0), 0
)) {
2394 DPRINTF(("TX status=%d\n", status));
2395 if (status == USBD_STALLED)
2396 usbd_clear_endpoint_stall_async(txq->pipeh);
2397 ifp->if_oerrorsif_data.ifi_oerrors++;
2398 splx(s)spllower(s);
2399 return;
2400 }
2401
2402 sc->sc_tx_timer = 0;
2403 ifq_clr_oactive(&ifp->if_snd);
2404 run_start(ifp);
2405 splx(s)spllower(s);
2406}
2407
2408int
2409run_tx(struct run_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
2410{
2411 struct ieee80211com *ic = &sc->sc_ic;
2412 struct run_node *rn = (void *)ni;
2413 struct ieee80211_frame *wh;
2414 struct run_tx_ring *ring;
2415 struct run_tx_data *data;
2416 struct rt2870_txd *txd;
2417 struct rt2860_txwi *txwi;
2418 uint16_t qos, dur;
2419 uint16_t txwisize;
2420 uint8_t type, mcs, tid, qid;
2421 int error, hasqos, ridx, ctl_ridx, xferlen;
2422
2423 wh = mtod(m, struct ieee80211_frame *)((struct ieee80211_frame *)((m)->m_hdr.mh_data));
2424 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK0x0c;
2425
2426 if ((hasqos = ieee80211_has_qos(wh))) {
2427 qos = ieee80211_get_qos(wh);
2428 tid = qos & IEEE80211_QOS_TID0x000f;
2429 qid = ieee80211_up_to_ac(ic, tid);
2430 } else {
2431 qos = 0;
2432 tid = 0;
2433 qid = EDCA_AC_BE;
2434 }
2435 ring = &sc->txq[qid];
2436 data = &ring->data[ring->cur];
2437
2438 /* pickup a rate index */
2439 if (IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) ||
2440 type != IEEE80211_FC0_TYPE_DATA0x08) {
2441 ridx = (ic->ic_curmode == IEEE80211_MODE_11A) ?
2442 RT2860_RIDX_OFDM64 : RT2860_RIDX_CCK10;
2443 ctl_ridx = rt2860_rates[ridx].ctl_ridx;
2444 } else if (ic->ic_fixed_rate != -1) {
2445 ridx = sc->fixed_ridx;
2446 ctl_ridx = rt2860_rates[ridx].ctl_ridx;
2447 } else {
2448 ridx = rn->ridx[ni->ni_txrate];
2449 ctl_ridx = rn->ctl_ridx[ni->ni_txrate];
2450 }
2451
2452 /* get MCS code from rate index */
2453 mcs = rt2860_rates[ridx].mcs;
2454
2455 txwisize = sizeof(struct rt2860_txwi);
2456 if (sc->mac_ver == 0x5592)
2457 txwisize += sizeof(uint32_t);
2458 xferlen = txwisize + m->m_pkthdrM_dat.MH.MH_pkthdr.len;
2459
2460 /* roundup to 32-bit alignment */
2461 xferlen = (xferlen + 3) & ~3;
2462
2463 txd = (struct rt2870_txd *)data->buf;
2464 txd->flags = RT2860_TX_QSEL_EDCA(2 << 1);
2465 txd->len = htole16(xferlen)((__uint16_t)(xferlen));
2466
2467 /* setup TX Wireless Information */
2468 txwi = (struct rt2860_txwi *)(txd + 1);
2469 txwi->flags = 0;
2470 txwi->xflags = hasqos ? 0 : RT2860_TX_NSEQ(1 << 1);
2471 txwi->wcid = (type == IEEE80211_FC0_TYPE_DATA0x08) ?
2472 RUN_AID2WCID(ni->ni_associd)((ni->ni_associd) & 0xff) : 0xff;
2473 txwi->len = htole16(m->m_pkthdr.len)((__uint16_t)(m->M_dat.MH.MH_pkthdr.len));
2474 if (rt2860_rates[ridx].phy == IEEE80211_T_DS) {
2475 txwi->phy = htole16(RT2860_PHY_CCK)((__uint16_t)((0 << 14)));
2476 if (ridx != RT2860_RIDX_CCK10 &&
2477 (ic->ic_flags & IEEE80211_F_SHPREAMBLE0x00040000))
2478 mcs |= RT2860_PHY_SHPRE(1 << 3);
2479 } else
2480 txwi->phy = htole16(RT2860_PHY_OFDM)((__uint16_t)((1 << 14)));
2481 txwi->phy |= htole16(mcs)((__uint16_t)(mcs));
2482
2483 txwi->txop = RT2860_TX_TXOP_BACKOFF3;
2484
2485 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)(*(wh->i_addr1) & 0x01) &&
2486 (!hasqos || (qos & IEEE80211_QOS_ACK_POLICY_MASK0x0060) !=
2487 IEEE80211_QOS_ACK_POLICY_NOACK0x0020)) {
2488 txwi->xflags |= RT2860_TX_ACK(1 << 0);
2489 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE0x00040000)
2490 dur = rt2860_rates[ctl_ridx].sp_ack_dur;
2491 else
2492 dur = rt2860_rates[ctl_ridx].lp_ack_dur;
2493 *(uint16_t *)wh->i_dur = htole16(dur)((__uint16_t)(dur));
2494 }
2495
2496#if NBPFILTER1 > 0
2497 if (__predict_false(sc->sc_drvbpf != NULL)__builtin_expect(((sc->sc_drvbpf != ((void *)0)) != 0), 0)) {
2498 struct run_tx_radiotap_header *tap = &sc->sc_txtapsc_txtapu.th;
2499 struct mbuf mb;
2500
2501 tap->wt_flags = 0;
2502 tap->wt_rate = rt2860_rates[ridx].rate;
2503 tap->wt_chan_freq = htole16(ic->ic_bss->ni_chan->ic_freq)((__uint16_t)(ic->ic_bss->ni_chan->ic_freq));
2504 tap->wt_chan_flags = htole16(ic->ic_bss->ni_chan->ic_flags)((__uint16_t)(ic->ic_bss->ni_chan->ic_flags));
2505 if (mcs & RT2860_PHY_SHPRE(1 << 3))
2506 tap->wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE0x02;
2507
2508 mb.m_datam_hdr.mh_data = (caddr_t)tap;
2509 mb.m_lenm_hdr.mh_len = sc->sc_txtap_len;
2510 mb.m_nextm_hdr.mh_next = m;
2511 mb.m_nextpktm_hdr.mh_nextpkt = NULL((void *)0);
2512 mb.m_typem_hdr.mh_type = 0;
2513 mb.m_flagsm_hdr.mh_flags = 0;
2514 bpf_mtap(sc->sc_drvbpf, &mb, BPF_DIRECTION_OUT(1 << 1));
2515 }
2516#endif
2517
2518 m_copydata(m, 0, m->m_pkthdrM_dat.MH.MH_pkthdr.len, (caddr_t)txwi + txwisize);
2519 m_freem(m);
2520
2521 xferlen += sizeof (*txd) + 4;
2522
2523 usbd_setup_xfer(data->xfer, ring->pipeh, data, data->buf, xferlen,
2524 USBD_FORCE_SHORT_XFER0x08 | USBD_NO_COPY0x01, RUN_TX_TIMEOUT5000, run_txeof);
2525 error = usbd_transfer(data->xfer);
2526 if (__predict_false(error != USBD_IN_PROGRESS && error != 0)__builtin_expect(((error != USBD_IN_PROGRESS && error
!= 0) != 0), 0))
2527 return error;
2528
2529 ieee80211_release_node(ic, ni);
2530
2531 ring->cur = (ring->cur + 1) % RUN_TX_RING_COUNT8;
2532 if (++ring->queued >= RUN_TX_RING_COUNT8)
2533 sc->qfullmsk |= 1 << qid;
2534
2535 return 0;
2536}
2537
2538void
2539run_start(struct ifnet *ifp)
2540{
2541 struct run_softc *sc = ifp->if_softc;
2542 struct ieee80211com *ic = &sc->sc_ic;
2543 struct ieee80211_node *ni;
2544 struct mbuf *m;
2545
2546 if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd))
2547 return;
2548
2549 for (;;) {
2550 if (sc->qfullmsk != 0) {
2551 ifq_set_oactive(&ifp->if_snd);
2552 break;
2553 }
2554 /* send pending management frames first */
2555 m = mq_dequeue(&ic->ic_mgtq);
2556 if (m != NULL((void *)0)) {
2557 ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie;
2558 goto sendit;
2559 }
2560 if (ic->ic_state != IEEE80211_S_RUN)
2561 break;
2562
2563 /* encapsulate and send data frames */
2564 m = ifq_dequeue(&ifp->if_snd);
2565 if (m == NULL((void *)0))
2566 break;
2567#if NBPFILTER1 > 0
2568 if (ifp->if_bpf != NULL((void *)0))
2569 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
2570#endif
2571 if ((m = ieee80211_encap(ifp, m, &ni)) == NULL((void *)0))
2572 continue;
2573sendit:
2574#if NBPFILTER1 > 0
2575 if (ic->ic_rawbpf != NULL((void *)0))
2576 bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT(1 << 1));
2577#endif
2578 if (run_tx(sc, m, ni) != 0) {
2579 ieee80211_release_node(ic, ni);
2580 ifp->if_oerrorsif_data.ifi_oerrors++;
2581 continue;
2582 }
2583
2584 sc->sc_tx_timer = 5;
2585 ifp->if_timer = 1;
2586 }
2587}
2588
2589void
2590run_watchdog(struct ifnet *ifp)
2591{
2592 struct run_softc *sc = ifp->if_softc;
2593
2594 ifp->if_timer = 0;
2595
2596 if (sc->sc_tx_timer > 0) {
2597 if (--sc->sc_tx_timer == 0) {
2598 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
2599 /* run_init(ifp); XXX needs a process context! */
2600 ifp->if_oerrorsif_data.ifi_oerrors++;
2601 return;
2602 }
2603 ifp->if_timer = 1;
2604 }
2605
2606 ieee80211_watchdog(ifp);
2607}
2608
2609int
2610run_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2611{
2612 struct run_softc *sc = ifp->if_softc;
2613 struct ieee80211com *ic = &sc->sc_ic;
2614 int s, error = 0;
2615
2616 if (usbd_is_dying(sc->sc_udev))
2617 return ENXIO6;
2618
2619 usbd_ref_incr(sc->sc_udev);
2620
2621 s = splnet()splraise(0x7);
2622
2623 switch (cmd) {
2624 case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
2625 ifp->if_flags |= IFF_UP0x1;
2626 /* FALLTHROUGH */
2627 case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
2628 if (ifp->if_flags & IFF_UP0x1) {
2629 if (!(ifp->if_flags & IFF_RUNNING0x40))
2630 run_init(ifp);
2631 } else {
2632 if (ifp->if_flags & IFF_RUNNING0x40)
2633 run_stop(ifp, 1);
2634 }
2635 break;
2636
2637 case SIOCS80211CHANNEL((unsigned long)0x80000000 | ((sizeof(struct ieee80211chanreq
) & 0x1fff) << 16) | ((('i')) << 8) | ((238))
):
2638 /*
2639 * This allows for fast channel switching in monitor mode
2640 * (used by kismet).
2641 */
2642 error = ieee80211_ioctl(ifp, cmd, data);
2643 if (error == ENETRESET52 &&
2644 ic->ic_opmode == IEEE80211_M_MONITOR) {
2645 if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
2646 (IFF_UP0x1 | IFF_RUNNING0x40))
2647 run_set_chan(sc, ic->ic_ibss_chan);
2648 error = 0;
2649 }
2650 break;
2651
2652 default:
2653 error = ieee80211_ioctl(ifp, cmd, data);
2654 }
2655
2656 if (error == ENETRESET52) {
2657 if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
2658 (IFF_UP0x1 | IFF_RUNNING0x40)) {
2659 run_stop(ifp, 0);
2660 run_init(ifp);
2661 }
2662 error = 0;
2663 }
2664
2665 splx(s)spllower(s);
2666
2667 usbd_ref_decr(sc->sc_udev);
2668
2669 return error;
2670}
2671
2672void
2673run_iq_calib(struct run_softc *sc, u_int chan)
2674{
2675 uint16_t val;
2676
2677 /* Tx0 IQ gain. */
2678 run_bbp_write(sc, 158, 0x2c);
2679 if (chan <= 14)
2680 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ0x130, &val);
2681 else if (chan <= 64) {
2682 run_efuse_read(sc,
2683 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ0x144, &val);
2684 } else if (chan <= 138) {
2685 run_efuse_read(sc,
2686 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ0x146, &val);
2687 } else if (chan <= 165) {
2688 run_efuse_read(sc,
2689 RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ0x148,
2690 &val);
2691 } else
2692 val = 0;
2693 run_bbp_write(sc, 159, val);
2694
2695 /* Tx0 IQ phase. */
2696 run_bbp_write(sc, 158, 0x2d);
2697 if (chan <= 14) {
2698 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ0x131, &val);
2699 } else if (chan <= 64) {
2700 run_efuse_read(sc,
2701 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ0x145, &val);
2702 } else if (chan <= 138) {
2703 run_efuse_read(sc,
2704 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ0x147, &val);
2705 } else if (chan <= 165) {
2706 run_efuse_read(sc,
2707 RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ0x149, &val);
2708 } else
2709 val = 0;
2710 run_bbp_write(sc, 159, val);
2711
2712 /* Tx1 IQ gain. */
2713 run_bbp_write(sc, 158, 0x4a);
2714 if (chan <= 14) {
2715 run_efuse_read(sc, RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ0x133, &val);
2716 } else if (chan <= 64) {
2717 run_efuse_read(sc,
2718 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ0x14a, &val);
2719 } else if (chan <= 138) {
2720 run_efuse_read(sc,
2721 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ0x14c, &val);
2722 } else if (chan <= 165) {
2723 run_efuse_read(sc,
2724 RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ0x14e, &val);
2725 } else
2726 val = 0;
2727 run_bbp_write(sc, 159, val);
2728
2729 /* Tx1 IQ phase. */
2730 run_bbp_write(sc, 158, 0x4b);
2731 if (chan <= 14) {
2732 run_efuse_read(sc, RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ0x134, &val);
2733 } else if (chan <= 64) {
2734 run_efuse_read(sc,
2735 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ0x14b, &val);
2736 } else if (chan <= 138) {
2737 run_efuse_read(sc,
2738 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ0x14d, &val);
2739 } else if (chan <= 165) {
2740 run_efuse_read(sc,
2741 RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ0x14f, &val);
2742 } else
2743 val = 0;
2744 run_bbp_write(sc, 159, val);
2745
2746 /* RF IQ compensation control. */
2747 run_bbp_write(sc, 158, 0x04);
2748 run_efuse_read(sc, RT5390_EEPROM_RF_IQ_COMPENSATION_CTL0x13c, &val);
2749 run_bbp_write(sc, 159, val);
2750
2751 /* RF IQ imbalance compensation control. */
2752 run_bbp_write(sc, 158, 0x03);
2753 run_efuse_read(sc,
2754 RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL0x13d, &val);
2755 run_bbp_write(sc, 159, val);
2756}
2757
2758void
2759run_select_chan_group(struct run_softc *sc, int group)
2760{
2761 uint32_t tmp;
2762 uint8_t agc;
2763
2764 run_bbp_write(sc, 62, 0x37 - sc->lna[group]);
2765 run_bbp_write(sc, 63, 0x37 - sc->lna[group]);
2766 run_bbp_write(sc, 64, 0x37 - sc->lna[group]);
2767 if (sc->mac_ver < 0x3572)
2768 run_bbp_write(sc, 86, 0x00);
2769
2770 if (sc->mac_ver == 0x3593) {
2771 run_bbp_write(sc, 77, 0x98);
2772 run_bbp_write(sc, 83, (group == 0) ? 0x8a : 0x9a);
2773 }
2774
2775 if (group == 0) {
2776 if (sc->ext_2ghz_lna) {
2777 if (sc->mac_ver >= 0x5390)
2778 run_bbp_write(sc, 75, 0x52);
2779 else {
2780 run_bbp_write(sc, 82, 0x62);
2781 run_bbp_write(sc, 75, 0x46);
2782 }
2783 } else {
2784 if (sc->mac_ver == 0x5592) {
2785 run_bbp_write(sc, 79, 0x1c);
2786 run_bbp_write(sc, 80, 0x0e);
2787 run_bbp_write(sc, 81, 0x3a);
2788 run_bbp_write(sc, 82, 0x62);
2789
2790 run_bbp_write(sc, 195, 0x80);
2791 run_bbp_write(sc, 196, 0xe0);
2792 run_bbp_write(sc, 195, 0x81);
2793 run_bbp_write(sc, 196, 0x1f);
2794 run_bbp_write(sc, 195, 0x82);
2795 run_bbp_write(sc, 196, 0x38);
2796 run_bbp_write(sc, 195, 0x83);
2797 run_bbp_write(sc, 196, 0x32);
2798 run_bbp_write(sc, 195, 0x85);
2799 run_bbp_write(sc, 196, 0x28);
2800 run_bbp_write(sc, 195, 0x86);
2801 run_bbp_write(sc, 196, 0x19);
2802 } else if (sc->mac_ver >= 0x5390)
2803 run_bbp_write(sc, 75, 0x50);
2804 else {
2805 run_bbp_write(sc, 82,
2806 (sc->mac_ver == 0x3593) ? 0x62 : 0x84);
2807 run_bbp_write(sc, 75, 0x50);
2808 }
2809 }
2810 } else {
2811 if (sc->mac_ver == 0x5592) {
2812 run_bbp_write(sc, 79, 0x18);
2813 run_bbp_write(sc, 80, 0x08);
2814 run_bbp_write(sc, 81, 0x38);
2815 run_bbp_write(sc, 82, 0x92);
2816
2817 run_bbp_write(sc, 195, 0x80);
2818 run_bbp_write(sc, 196, 0xf0);
2819 run_bbp_write(sc, 195, 0x81);
2820 run_bbp_write(sc, 196, 0x1e);
2821 run_bbp_write(sc, 195, 0x82);
2822 run_bbp_write(sc, 196, 0x28);
2823 run_bbp_write(sc, 195, 0x83);
2824 run_bbp_write(sc, 196, 0x20);
2825 run_bbp_write(sc, 195, 0x85);
2826 run_bbp_write(sc, 196, 0x7f);
2827 run_bbp_write(sc, 195, 0x86);
2828 run_bbp_write(sc, 196, 0x7f);
2829 } else if (sc->mac_ver == 0x3572)
2830 run_bbp_write(sc, 82, 0x94);
2831 else
2832 run_bbp_write(sc, 82,
2833 (sc->mac_ver == 0x3593) ? 0x82 : 0xf2);
2834 if (sc->ext_5ghz_lna)
2835 run_bbp_write(sc, 75, 0x46);
2836 else
2837 run_bbp_write(sc, 75, 0x50);
2838 }
2839
2840 run_read(sc, RT2860_TX_BAND_CFG0x132c, &tmp);
2841 tmp &= ~(RT2860_5G_BAND_SEL_N(1 << 2) | RT2860_5G_BAND_SEL_P(1 << 1));
2842 tmp |= (group == 0) ? RT2860_5G_BAND_SEL_N(1 << 2) : RT2860_5G_BAND_SEL_P(1 << 1);
2843 run_write(sc, RT2860_TX_BAND_CFG0x132c, tmp);
2844
2845 /* enable appropriate Power Amplifiers and Low Noise Amplifiers */
2846 tmp = RT2860_RFTR_EN(1U << 16) | RT2860_TRSW_EN(1U << 18) | RT2860_LNA_PE0_EN((1U << 8) | (1U << 9));
2847 if (sc->mac_ver == 0x3593)
2848 tmp |= 1 << 29 | 1 << 28;
2849 if (sc->nrxchains > 1)
2850 tmp |= RT2860_LNA_PE1_EN((1U << 10) | (1U << 11));
2851 if (group == 0) { /* 2GHz */
2852 tmp |= RT2860_PA_PE_G0_EN(1U << 1);
2853 if (sc->ntxchains > 1)
2854 tmp |= RT2860_PA_PE_G1_EN(1U << 3);
2855 if (sc->mac_ver == 0x3593) {
2856 if (sc->ntxchains > 2)
2857 tmp |= 1 << 25;
2858 }
2859 } else { /* 5GHz */
2860 tmp |= RT2860_PA_PE_A0_EN(1U << 0);
2861 if (sc->ntxchains > 1)
2862 tmp |= RT2860_PA_PE_A1_EN(1U << 2);
2863 }
2864 if (sc->mac_ver == 0x3572) {
2865 run_rt3070_rf_write(sc, 8, 0x00);
2866 run_write(sc, RT2860_TX_PIN_CFG0x1328, tmp);
2867 run_rt3070_rf_write(sc, 8, 0x80);
2868 } else
2869 run_write(sc, RT2860_TX_PIN_CFG0x1328, tmp);
2870
2871 if (sc->mac_ver == 0x5592) {
2872 run_bbp_write(sc, 195, 0x8d);
2873 run_bbp_write(sc, 196, 0x1a);
2874 }
2875
2876 if (sc->mac_ver == 0x3593) {
2877 run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp);
2878 tmp &= ~0x01010000;
2879 if (group == 0)
2880 tmp |= 0x00010000;
2881 tmp = (tmp & ~0x00009090) | 0x00000090;
2882 run_write(sc, RT2860_GPIO_CTRL0x0228, tmp);
2883 }
2884
2885 /* set initial AGC value */
2886 if (group == 0) { /* 2GHz band */
2887 if (sc->mac_ver >= 0x3070)
2888 agc = 0x1c + sc->lna[0] * 2;
2889 else
2890 agc = 0x2e + sc->lna[0];
2891 } else { /* 5GHz band */
2892 if (sc->mac_ver == 0x5592)
2893 agc = 0x24 + sc->lna[group] * 2;
2894 else if (sc->mac_ver == 0x3572 || sc->mac_ver == 0x3593)
2895 agc = 0x22 + (sc->lna[group] * 5) / 3;
2896 else
2897 agc = 0x32 + (sc->lna[group] * 5) / 3;
2898 }
2899 run_set_agc(sc, agc);
2900}
2901
2902void
2903run_rt2870_set_chan(struct run_softc *sc, u_int chan)
2904{
2905 const struct rfprog *rfprog = rt2860_rf2850;
2906 uint32_t r2, r3, r4;
2907 int8_t txpow1, txpow2;
2908 int i;
2909
2910 /* find the settings for this channel (we know it exists) */
2911 for (i = 0; rfprog[i].chan != chan; i++);
2912
2913 r2 = rfprog[i].r2;
2914 if (sc->ntxchains == 1)
2915 r2 |= 1 << 12; /* 1T: disable Tx chain 2 */
2916 if (sc->nrxchains == 1)
2917 r2 |= 1 << 15 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
2918 else if (sc->nrxchains == 2)
2919 r2 |= 1 << 4; /* 2R: disable Rx chain 3 */
2920
2921 /* use Tx power values from EEPROM */
2922 txpow1 = sc->txpow1[i];
2923 txpow2 = sc->txpow2[i];
2924 if (chan > 14) {
2925 if (txpow1 >= 0)
2926 txpow1 = txpow1 << 1 | 1;
2927 else
2928 txpow1 = (7 + txpow1) << 1;
2929 if (txpow2 >= 0)
2930 txpow2 = txpow2 << 1 | 1;
2931 else
2932 txpow2 = (7 + txpow2) << 1;
2933 }
2934 r3 = rfprog[i].r3 | txpow1 << 7;
2935 r4 = rfprog[i].r4 | sc->freq << 13 | txpow2 << 4;
2936
2937 run_rt2870_rf_write(sc, RT2860_RF10, rfprog[i].r1);
2938 run_rt2870_rf_write(sc, RT2860_RF22, r2);
2939 run_rt2870_rf_write(sc, RT2860_RF31, r3);
2940 run_rt2870_rf_write(sc, RT2860_RF43, r4);
2941
2942 DELAY(200)(*delay_func)(200);
2943
2944 run_rt2870_rf_write(sc, RT2860_RF10, rfprog[i].r1);
2945 run_rt2870_rf_write(sc, RT2860_RF22, r2);
2946 run_rt2870_rf_write(sc, RT2860_RF31, r3 | 1);
2947 run_rt2870_rf_write(sc, RT2860_RF43, r4);
2948
2949 DELAY(200)(*delay_func)(200);
2950
2951 run_rt2870_rf_write(sc, RT2860_RF10, rfprog[i].r1);
2952 run_rt2870_rf_write(sc, RT2860_RF22, r2);
2953 run_rt2870_rf_write(sc, RT2860_RF31, r3);
2954 run_rt2870_rf_write(sc, RT2860_RF43, r4);
2955}
2956
2957void
2958run_rt3070_set_chan(struct run_softc *sc, u_int chan)
2959{
2960 int8_t txpow1, txpow2;
2961 uint8_t rf;
2962 int i;
2963
2964 /* find the settings for this channel (we know it exists) */
2965 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
2966
2967 /* use Tx power values from EEPROM */
2968 txpow1 = sc->txpow1[i];
2969 txpow2 = sc->txpow2[i];
2970
2971 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n);
2972
2973 /* RT3370/RT3390: RF R3 [7:4] is not reserved bits. */
2974 run_rt3070_rf_read(sc, 3, &rf);
2975 rf = (rf & ~0x0f) | rt3070_freqs[i].k;
2976 run_rt3070_rf_write(sc, 3, rf);
2977
2978 run_rt3070_rf_read(sc, 6, &rf);
2979 rf = (rf & ~0x03) | rt3070_freqs[i].r;
2980 run_rt3070_rf_write(sc, 6, rf);
2981
2982 /* set Tx0 power */
2983 run_rt3070_rf_read(sc, 12, &rf);
2984 rf = (rf & ~0x1f) | txpow1;
2985 run_rt3070_rf_write(sc, 12, rf);
2986
2987 /* set Tx1 power */
2988 run_rt3070_rf_read(sc, 13, &rf);
2989 rf = (rf & ~0x1f) | txpow2;
2990 run_rt3070_rf_write(sc, 13, rf);
2991
2992 run_rt3070_rf_read(sc, 1, &rf);
2993 rf &= ~0xfc;
2994 if (sc->ntxchains == 1)
2995 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */
2996 else if (sc->ntxchains == 2)
2997 rf |= 1 << 7; /* 2T: disable Tx chain 3 */
2998 if (sc->nrxchains == 1)
2999 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
3000 else if (sc->nrxchains == 2)
3001 rf |= 1 << 6; /* 2R: disable Rx chain 3 */
3002 run_rt3070_rf_write(sc, 1, rf);
3003
3004 /* set RF offset */
3005 run_rt3070_rf_read(sc, 23, &rf);
3006 rf = (rf & ~0x7f) | sc->freq;
3007 run_rt3070_rf_write(sc, 23, rf);
3008
3009 /* program RF filter */
3010 run_rt3070_rf_read(sc, 24, &rf); /* Tx */
3011 rf = (rf & ~0x3f) | sc->rf24_20mhz;
3012 run_rt3070_rf_write(sc, 24, rf);
3013 run_rt3070_rf_read(sc, 31, &rf); /* Rx */
3014 rf = (rf & ~0x3f) | sc->rf24_20mhz;
3015 run_rt3070_rf_write(sc, 31, rf);
3016
3017 /* enable RF tuning */
3018 run_rt3070_rf_read(sc, 7, &rf);
3019 run_rt3070_rf_write(sc, 7, rf | 0x01);
3020}
3021
3022void
3023run_rt3572_set_chan(struct run_softc *sc, u_int chan)
3024{
3025 int8_t txpow1, txpow2;
3026 uint32_t tmp;
3027 uint8_t rf;
3028 int i;
3029
3030 /* find the settings for this channel (we know it exists) */
3031 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
3032
3033 /* use Tx power values from EEPROM */
3034 txpow1 = sc->txpow1[i];
3035 txpow2 = sc->txpow2[i];
3036
3037 if (chan <= 14) {
3038 run_bbp_write(sc, 25, sc->bbp25);
3039 run_bbp_write(sc, 26, sc->bbp26);
3040 } else {
3041 /* enable IQ phase correction */
3042 run_bbp_write(sc, 25, 0x09);
3043 run_bbp_write(sc, 26, 0xff);
3044 }
3045
3046 run_rt3070_rf_write(sc, 2, rt3070_freqs[i].n);
3047 run_rt3070_rf_write(sc, 3, rt3070_freqs[i].k);
3048 run_rt3070_rf_read(sc, 6, &rf);
3049 rf = (rf & ~0x0f) | rt3070_freqs[i].r;
3050 rf |= (chan <= 14) ? 0x08 : 0x04;
3051 run_rt3070_rf_write(sc, 6, rf);
3052
3053 /* set PLL mode */
3054 run_rt3070_rf_read(sc, 5, &rf);
3055 rf &= ~(0x08 | 0x04);
3056 rf |= (chan <= 14) ? 0x04 : 0x08;
3057 run_rt3070_rf_write(sc, 5, rf);
3058
3059 /* set Tx power for chain 0 */
3060 if (chan <= 14)
3061 rf = 0x60 | txpow1;
3062 else
3063 rf = 0xe0 | (txpow1 & 0xc) << 1 | (txpow1 & 0x3);
3064 run_rt3070_rf_write(sc, 12, rf);
3065
3066 /* set Tx power for chain 1 */
3067 if (chan <= 14)
3068 rf = 0x60 | txpow2;
3069 else
3070 rf = 0xe0 | (txpow2 & 0xc) << 1 | (txpow2 & 0x3);
3071 run_rt3070_rf_write(sc, 13, rf);
3072
3073 /* set Tx/Rx streams */
3074 run_rt3070_rf_read(sc, 1, &rf);
3075 rf &= ~0xfc;
3076 if (sc->ntxchains == 1)
3077 rf |= 1 << 7 | 1 << 5; /* 1T: disable Tx chains 2 & 3 */
3078 else if (sc->ntxchains == 2)
3079 rf |= 1 << 7; /* 2T: disable Tx chain 3 */
3080 if (sc->nrxchains == 1)
3081 rf |= 1 << 6 | 1 << 4; /* 1R: disable Rx chains 2 & 3 */
3082 else if (sc->nrxchains == 2)
3083 rf |= 1 << 6; /* 2R: disable Rx chain 3 */
3084 run_rt3070_rf_write(sc, 1, rf);
3085
3086 /* set RF offset */
3087 run_rt3070_rf_read(sc, 23, &rf);
3088 rf = (rf & ~0x7f) | sc->freq;
3089 run_rt3070_rf_write(sc, 23, rf);
3090
3091 /* program RF filter */
3092 rf = sc->rf24_20mhz;
3093 run_rt3070_rf_write(sc, 24, rf); /* Tx */
3094 run_rt3070_rf_write(sc, 31, rf); /* Rx */
3095
3096 /* enable RF tuning */
3097 run_rt3070_rf_read(sc, 7, &rf);
3098 rf = (chan <= 14) ? 0xd8 : ((rf & ~0xc8) | 0x14);
3099 run_rt3070_rf_write(sc, 7, rf);
3100
3101 /* TSSI */
3102 rf = (chan <= 14) ? 0xc3 : 0xc0;
3103 run_rt3070_rf_write(sc, 9, rf);
3104
3105 /* set loop filter 1 */
3106 run_rt3070_rf_write(sc, 10, 0xf1);
3107 /* set loop filter 2 */
3108 run_rt3070_rf_write(sc, 11, (chan <= 14) ? 0xb9 : 0x00);
3109
3110 /* set tx_mx2_ic */
3111 run_rt3070_rf_write(sc, 15, (chan <= 14) ? 0x53 : 0x43);
3112 /* set tx_mx1_ic */
3113 if (chan <= 14)
3114 rf = 0x48 | sc->txmixgain_2ghz;
3115 else
3116 rf = 0x78 | sc->txmixgain_5ghz;
3117 run_rt3070_rf_write(sc, 16, rf);
3118
3119 /* set tx_lo1 */
3120 run_rt3070_rf_write(sc, 17, 0x23);
3121 /* set tx_lo2 */
3122 if (chan <= 14)
3123 rf = 0x93;
3124 else if (chan <= 64)
3125 rf = 0xb7;
3126 else if (chan <= 128)
3127 rf = 0x74;
3128 else
3129 rf = 0x72;
3130 run_rt3070_rf_write(sc, 19, rf);
3131
3132 /* set rx_lo1 */
3133 if (chan <= 14)
3134 rf = 0xb3;
3135 else if (chan <= 64)
3136 rf = 0xf6;
3137 else if (chan <= 128)
3138 rf = 0xf4;
3139 else
3140 rf = 0xf3;
3141 run_rt3070_rf_write(sc, 20, rf);
3142
3143 /* set pfd_delay */
3144 if (chan <= 14)
3145 rf = 0x15;
3146 else if (chan <= 64)
3147 rf = 0x3d;
3148 else
3149 rf = 0x01;
3150 run_rt3070_rf_write(sc, 25, rf);
3151
3152 /* set rx_lo2 */
3153 run_rt3070_rf_write(sc, 26, (chan <= 14) ? 0x85 : 0x87);
3154 /* set ldo_rf_vc */
3155 run_rt3070_rf_write(sc, 27, (chan <= 14) ? 0x00 : 0x01);
3156 /* set drv_cc */
3157 run_rt3070_rf_write(sc, 29, (chan <= 14) ? 0x9b : 0x9f);
3158
3159 run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp);
3160 tmp &= ~0x8080;
3161 if (chan <= 14)
3162 tmp |= 0x80;
3163 run_write(sc, RT2860_GPIO_CTRL0x0228, tmp);
3164
3165 /* enable RF tuning */
3166 run_rt3070_rf_read(sc, 7, &rf);
3167 run_rt3070_rf_write(sc, 7, rf | 0x01);
3168
3169 DELAY(2000)(*delay_func)(2000);
3170}
3171
3172void
3173run_rt3593_set_chan(struct run_softc *sc, u_int chan)
3174{
3175 int8_t txpow1, txpow2, txpow3;
3176 uint8_t h20mhz, rf;
3177 int i;
3178
3179 /* find the settings for this channel (we know it exists) */
3180 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
3181
3182 /* use Tx power values from EEPROM */
3183 txpow1 = sc->txpow1[i];
3184 txpow2 = sc->txpow2[i];
3185 txpow3 = (sc->ntxchains == 3) ? sc->txpow3[i] : 0;
3186
3187 if (chan <= 14) {
3188 run_bbp_write(sc, 25, sc->bbp25);
3189 run_bbp_write(sc, 26, sc->bbp26);
3190 } else {
3191 /* Enable IQ phase correction. */
3192 run_bbp_write(sc, 25, 0x09);
3193 run_bbp_write(sc, 26, 0xff);
3194 }
3195
3196 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n);
3197 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f);
3198 run_rt3070_rf_read(sc, 11, &rf);
3199 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03);
3200 run_rt3070_rf_write(sc, 11, rf);
3201
3202 /* Set pll_idoh. */
3203 run_rt3070_rf_read(sc, 11, &rf);
3204 rf &= ~0x4c;
3205 rf |= (chan <= 14) ? 0x44 : 0x48;
3206 run_rt3070_rf_write(sc, 11, rf);
3207
3208 if (chan <= 14)
3209 rf = txpow1 & 0x1f;
3210 else
3211 rf = 0x40 | ((txpow1 & 0x18) << 1) | (txpow1 & 0x07);
3212 run_rt3070_rf_write(sc, 53, rf);
3213
3214 if (chan <= 14)
3215 rf = txpow2 & 0x1f;
3216 else
3217 rf = 0x40 | ((txpow2 & 0x18) << 1) | (txpow2 & 0x07);
3218 run_rt3070_rf_write(sc, 55, rf);
3219
3220 if (chan <= 14)
3221 rf = txpow3 & 0x1f;
3222 else
3223 rf = 0x40 | ((txpow3 & 0x18) << 1) | (txpow3 & 0x07);
3224 run_rt3070_rf_write(sc, 54, rf);
3225
3226 rf = RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1);
3227 if (sc->ntxchains == 3)
3228 rf |= RT3070_TX0_PD(1 << 3) | RT3070_TX1_PD(1 << 5) | RT3070_TX2_PD(1 << 7);
3229 else
3230 rf |= RT3070_TX0_PD(1 << 3) | RT3070_TX1_PD(1 << 5);
3231 rf |= RT3070_RX0_PD(1 << 2) | RT3070_RX1_PD(1 << 4) | RT3070_RX2_PD(1 << 6);
3232 run_rt3070_rf_write(sc, 1, rf);
3233
3234 run_adjust_freq_offset(sc);
3235
3236 run_rt3070_rf_write(sc, 31, (chan <= 14) ? 0xa0 : 0x80);
3237
3238 h20mhz = (sc->rf24_20mhz & 0x20) >> 5;
3239 run_rt3070_rf_read(sc, 30, &rf);
3240 rf = (rf & ~0x06) | (h20mhz << 1) | (h20mhz << 2);
3241 run_rt3070_rf_write(sc, 30, rf);
3242
3243 run_rt3070_rf_read(sc, 36, &rf);
3244 if (chan <= 14)
3245 rf |= 0x80;
3246 else
3247 rf &= ~0x80;
3248 run_rt3070_rf_write(sc, 36, rf);
3249
3250 /* Set vcolo_bs. */
3251 run_rt3070_rf_write(sc, 34, (chan <= 14) ? 0x3c : 0x20);
3252 /* Set pfd_delay. */
3253 run_rt3070_rf_write(sc, 12, (chan <= 14) ? 0x1a : 0x12);
3254
3255 /* Set vco bias current control. */
3256 run_rt3070_rf_read(sc, 6, &rf);
3257 rf &= ~0xc0;
3258 if (chan <= 14)
3259 rf |= 0x40;
3260 else if (chan <= 128)
3261 rf |= 0x80;
3262 else
3263 rf |= 0x40;
3264 run_rt3070_rf_write(sc, 6, rf);
3265
3266 run_rt3070_rf_read(sc, 30, &rf);
3267 rf = (rf & ~0x18) | 0x10;
3268 run_rt3070_rf_write(sc, 30, rf);
3269
3270 run_rt3070_rf_write(sc, 10, (chan <= 14) ? 0xd3 : 0xd8);
3271 run_rt3070_rf_write(sc, 13, (chan <= 14) ? 0x12 : 0x23);
3272
3273 run_rt3070_rf_read(sc, 51, &rf);
3274 rf = (rf & ~0x03) | 0x01;
3275 run_rt3070_rf_write(sc, 51, rf);
3276 /* Set tx_mx1_cc. */
3277 run_rt3070_rf_read(sc, 51, &rf);
3278 rf &= ~0x1c;
3279 rf |= (chan <= 14) ? 0x14 : 0x10;
3280 run_rt3070_rf_write(sc, 51, rf);
3281 /* Set tx_mx1_ic. */
3282 run_rt3070_rf_read(sc, 51, &rf);
3283 rf &= ~0xe0;
3284 rf |= (chan <= 14) ? 0x60 : 0x40;
3285 run_rt3070_rf_write(sc, 51, rf);
3286 /* Set tx_lo1_ic. */
3287 run_rt3070_rf_read(sc, 49, &rf);
3288 rf &= ~0x1c;
3289 rf |= (chan <= 14) ? 0x0c : 0x08;
3290 run_rt3070_rf_write(sc, 49, rf);
3291 /* Set tx_lo1_en. */
3292 run_rt3070_rf_read(sc, 50, &rf);
3293 run_rt3070_rf_write(sc, 50, rf & ~0x20);
3294 /* Set drv_cc. */
3295 run_rt3070_rf_read(sc, 57, &rf);
3296 rf &= ~0xfc;
3297 rf |= (chan <= 14) ? 0x6c : 0x3c;
3298 run_rt3070_rf_write(sc, 57, rf);
3299 /* Set rx_mix1_ic, rxa_lnactr, lna_vc, lna_inbias_en and lna_en. */
3300 run_rt3070_rf_write(sc, 44, (chan <= 14) ? 0x93 : 0x9b);
3301 /* Set drv_gnd_a, tx_vga_cc_a and tx_mx2_gain. */
3302 run_rt3070_rf_write(sc, 52, (chan <= 14) ? 0x45 : 0x05);
3303 /* Enable VCO calibration. */
3304 run_rt3070_rf_read(sc, 3, &rf);
3305 rf &= ~RT3593_VCOCAL(1 << 7);
3306 rf |= (chan <= 14) ? RT3593_VCOCAL(1 << 7) : 0xbe;
3307 run_rt3070_rf_write(sc, 3, rf);
3308
3309 if (chan <= 14)
3310 rf = 0x23;
3311 else if (chan <= 64)
3312 rf = 0x36;
3313 else if (chan <= 128)
3314 rf = 0x32;
3315 else
3316 rf = 0x30;
3317 run_rt3070_rf_write(sc, 39, rf);
3318 if (chan <= 14)
3319 rf = 0xbb;
3320 else if (chan <= 64)
3321 rf = 0xeb;
3322 else if (chan <= 128)
3323 rf = 0xb3;
3324 else
3325 rf = 0x9b;
3326 run_rt3070_rf_write(sc, 45, rf);
3327
3328 /* Set FEQ/AEQ control. */
3329 run_bbp_write(sc, 105, 0x34);
3330}
3331
3332void
3333run_rt5390_set_chan(struct run_softc *sc, u_int chan)
3334{
3335 int8_t txpow1, txpow2;
3336 uint8_t rf;
3337 int i;
3338
3339 /* find the settings for this channel (we know it exists) */
3340 for (i = 0; rt2860_rf2850[i].chan != chan; i++);
3341
3342 /* use Tx power values from EEPROM */
3343 txpow1 = sc->txpow1[i];
3344 txpow2 = sc->txpow2[i];
3345
3346 run_rt3070_rf_write(sc, 8, rt3070_freqs[i].n);
3347 run_rt3070_rf_write(sc, 9, rt3070_freqs[i].k & 0x0f);
3348 run_rt3070_rf_read(sc, 11, &rf);
3349 rf = (rf & ~0x03) | (rt3070_freqs[i].r & 0x03);
3350 run_rt3070_rf_write(sc, 11, rf);
3351
3352 run_rt3070_rf_read(sc, 49, &rf);
3353 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
3354 /* The valid range of the RF R49 is 0x00 to 0x27. */
3355 if ((rf & 0x3f) > 0x27)
3356 rf = (rf & ~0x3f) | 0x27;
3357 run_rt3070_rf_write(sc, 49, rf);
3358
3359 if (sc->mac_ver == 0x5392) {
3360 run_rt3070_rf_read(sc, 50, &rf);
3361 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
3362 /* The valid range of the RF R50 is 0x00 to 0x27. */
3363 if ((rf & 0x3f) > 0x27)
3364 rf = (rf & ~0x3f) | 0x27;
3365 run_rt3070_rf_write(sc, 50, rf);
3366 }
3367
3368 run_rt3070_rf_read(sc, 1, &rf);
3369 rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1) | RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3);
3370 if (sc->mac_ver == 0x5392)
3371 rf |= RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5);
3372 run_rt3070_rf_write(sc, 1, rf);
3373
3374 if (sc->mac_ver != 0x5392) {
3375 run_rt3070_rf_read(sc, 2, &rf);
3376 rf |= 0x80;
3377 run_rt3070_rf_write(sc, 2, rf);
3378 DELAY(10)(*delay_func)(10);
3379 rf &= 0x7f;
3380 run_rt3070_rf_write(sc, 2, rf);
3381 }
3382
3383 run_adjust_freq_offset(sc);
3384
3385 if (sc->mac_ver == 0x5392) {
3386 /* Fix for RT5392C. */
3387 if (sc->mac_rev >= 0x0223) {
3388 if (chan <= 4)
3389 rf = 0x0f;
3390 else if (chan >= 5 && chan <= 7)
3391 rf = 0x0e;
3392 else
3393 rf = 0x0d;
3394 run_rt3070_rf_write(sc, 23, rf);
3395
3396 if (chan <= 4)
3397 rf = 0x0c;
3398 else if (chan == 5)
3399 rf = 0x0b;
3400 else if (chan >= 6 && chan <= 7)
3401 rf = 0x0a;
3402 else if (chan >= 8 && chan <= 10)
3403 rf = 0x09;
3404 else
3405 rf = 0x08;
3406 run_rt3070_rf_write(sc, 59, rf);
3407 } else {
3408 if (chan <= 11)
3409 rf = 0x0f;
3410 else
3411 rf = 0x0b;
3412 run_rt3070_rf_write(sc, 59, rf);
3413 }
3414 } else {
3415 /* Fix for RT5390F. */
3416 if (sc->mac_rev >= 0x0502) {
3417 if (chan <= 11)
3418 rf = 0x43;
3419 else
3420 rf = 0x23;
3421 run_rt3070_rf_write(sc, 55, rf);
3422
3423 if (chan <= 11)
3424 rf = 0x0f;
3425 else if (chan == 12)
3426 rf = 0x0d;
3427 else
3428 rf = 0x0b;
3429 run_rt3070_rf_write(sc, 59, rf);
3430 } else {
3431 run_rt3070_rf_write(sc, 55, 0x44);
3432 run_rt3070_rf_write(sc, 59, 0x8f);
3433 }
3434 }
3435
3436 /* Enable VCO calibration. */
3437 run_rt3070_rf_read(sc, 3, &rf);
3438 rf |= RT3593_VCOCAL(1 << 7);
3439 run_rt3070_rf_write(sc, 3, rf);
3440}
3441
3442void
3443run_rt5592_set_chan(struct run_softc *sc, u_int chan)
3444{
3445 const struct rt5592_freqs *freqs;
3446 uint32_t tmp;
3447 uint8_t reg, rf, txpow_bound;
3448 int8_t txpow1, txpow2;
3449 int i;
3450
3451 run_read(sc, RT5592_DEBUG_INDEX0x05e8, &tmp);
3452 freqs = (tmp & RT5592_SEL_XTAL(1U << 31)) ?
3453 rt5592_freqs_40mhz : rt5592_freqs_20mhz;
3454
3455 /* find the settings for this channel (we know it exists) */
3456 for (i = 0; rt2860_rf2850[i].chan != chan; i++, freqs++);
3457
3458 /* use Tx power values from EEPROM */
3459 txpow1 = sc->txpow1[i];
3460 txpow2 = sc->txpow2[i];
3461
3462 run_read(sc, RT3070_LDO_CFG00x05d4, &tmp);
3463 tmp &= ~0x1c000000;
3464 if (chan > 14)
3465 tmp |= 0x14000000;
3466 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
3467
3468 /* N setting. */
3469 run_rt3070_rf_write(sc, 8, freqs->n & 0xff);
3470 run_rt3070_rf_read(sc, 9, &rf);
3471 rf &= ~(1 << 4);
3472 rf |= ((freqs->n & 0x0100) >> 8) << 4;
3473 run_rt3070_rf_write(sc, 9, rf);
3474
3475 /* K setting. */
3476 run_rt3070_rf_read(sc, 9, &rf);
3477 rf &= ~0x0f;
3478 rf |= (freqs->k & 0x0f);
3479 run_rt3070_rf_write(sc, 9, rf);
3480
3481 /* Mode setting. */
3482 run_rt3070_rf_read(sc, 11, &rf);
3483 rf &= ~0x0c;
3484 rf |= ((freqs->m - 0x8) & 0x3) << 2;
3485 run_rt3070_rf_write(sc, 11, rf);
3486 run_rt3070_rf_read(sc, 9, &rf);
3487 rf &= ~(1 << 7);
3488 rf |= (((freqs->m - 0x8) & 0x4) >> 2) << 7;
3489 run_rt3070_rf_write(sc, 9, rf);
3490
3491 /* R setting. */
3492 run_rt3070_rf_read(sc, 11, &rf);
3493 rf &= ~0x03;
3494 rf |= (freqs->r - 0x1);
3495 run_rt3070_rf_write(sc, 11, rf);
3496
3497 if (chan <= 14) {
3498 /* Initialize RF registers for 2GHZ. */
3499 for (i = 0; i < nitems(rt5592_2ghz_def_rf)(sizeof((rt5592_2ghz_def_rf)) / sizeof((rt5592_2ghz_def_rf)[0
])); i++) {
3500 run_rt3070_rf_write(sc, rt5592_2ghz_def_rf[i].reg,
3501 rt5592_2ghz_def_rf[i].val);
3502 }
3503
3504 rf = (chan <= 10) ? 0x07 : 0x06;
3505 run_rt3070_rf_write(sc, 23, rf);
3506 run_rt3070_rf_write(sc, 59, rf);
3507
3508 run_rt3070_rf_write(sc, 55, 0x43);
3509
3510 /*
3511 * RF R49/R50 Tx power ALC code.
3512 * G-band bit<7:6>=1:0, bit<5:0> range from 0x0 ~ 0x27.
3513 */
3514 reg = 2;
3515 txpow_bound = 0x27;
3516 } else {
3517 /* Initialize RF registers for 5GHZ. */
3518 for (i = 0; i < nitems(rt5592_5ghz_def_rf)(sizeof((rt5592_5ghz_def_rf)) / sizeof((rt5592_5ghz_def_rf)[0
])); i++) {
3519 run_rt3070_rf_write(sc, rt5592_5ghz_def_rf[i].reg,
3520 rt5592_5ghz_def_rf[i].val);
3521 }
3522 for (i = 0; i < nitems(rt5592_chan_5ghz)(sizeof((rt5592_chan_5ghz)) / sizeof((rt5592_chan_5ghz)[0])); i++) {
3523 if (chan >= rt5592_chan_5ghz[i].firstchan &&
3524 chan <= rt5592_chan_5ghz[i].lastchan) {
3525 run_rt3070_rf_write(sc, rt5592_chan_5ghz[i].reg,
3526 rt5592_chan_5ghz[i].val);
3527 }
3528 }
3529
3530 /*
3531 * RF R49/R50 Tx power ALC code.
3532 * A-band bit<7:6>=1:1, bit<5:0> range from 0x0 ~ 0x2b.
3533 */
3534 reg = 3;
3535 txpow_bound = 0x2b;
3536 }
3537
3538 /* RF R49 ch0 Tx power ALC code. */
3539 run_rt3070_rf_read(sc, 49, &rf);
3540 rf &= ~0xc0;
3541 rf |= (reg << 6);
3542 rf = (rf & ~0x3f) | (txpow1 & 0x3f);
3543 if ((rf & 0x3f) > txpow_bound)
3544 rf = (rf & ~0x3f) | txpow_bound;
3545 run_rt3070_rf_write(sc, 49, rf);
3546
3547 /* RF R50 ch1 Tx power ALC code. */
3548 run_rt3070_rf_read(sc, 50, &rf);
3549 rf &= ~(1 << 7 | 1 << 6);
3550 rf |= (reg << 6);
3551 rf = (rf & ~0x3f) | (txpow2 & 0x3f);
3552 if ((rf & 0x3f) > txpow_bound)
3553 rf = (rf & ~0x3f) | txpow_bound;
3554 run_rt3070_rf_write(sc, 50, rf);
3555
3556 /* Enable RF_BLOCK, PLL_PD, RX0_PD, and TX0_PD. */
3557 run_rt3070_rf_read(sc, 1, &rf);
3558 rf |= (RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1) | RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3));
3559 if (sc->ntxchains > 1)
3560 rf |= RT3070_TX1_PD(1 << 5);
3561 if (sc->nrxchains > 1)
3562 rf |= RT3070_RX1_PD(1 << 4);
3563 run_rt3070_rf_write(sc, 1, rf);
3564
3565 run_rt3070_rf_write(sc, 6, 0xe4);
3566
3567 run_rt3070_rf_write(sc, 30, 0x10);
3568 run_rt3070_rf_write(sc, 31, 0x80);
3569 run_rt3070_rf_write(sc, 32, 0x80);
3570
3571 run_adjust_freq_offset(sc);
3572
3573 /* Enable VCO calibration. */
3574 run_rt3070_rf_read(sc, 3, &rf);
3575 rf |= RT3593_VCOCAL(1 << 7);
3576 run_rt3070_rf_write(sc, 3, rf);
3577}
3578
3579void
3580run_set_agc(struct run_softc *sc, uint8_t agc)
3581{
3582 uint8_t bbp;
3583
3584 if (sc->mac_ver == 0x3572) {
3585 run_bbp_read(sc, 27, &bbp);
3586 bbp &= ~(0x3 << 5);
3587 run_bbp_write(sc, 27, bbp | 0 << 5); /* select Rx0 */
3588 run_bbp_write(sc, 66, agc);
3589 run_bbp_write(sc, 27, bbp | 1 << 5); /* select Rx1 */
3590 run_bbp_write(sc, 66, agc);
3591 } else
3592 run_bbp_write(sc, 66, agc);
3593}
3594
3595void
3596run_set_rx_antenna(struct run_softc *sc, int aux)
3597{
3598 uint32_t tmp;
3599 uint8_t bbp152;
3600
3601 if (aux) {
3602 if (sc->rf_rev == RT5390_RF_53700x5370) {
3603 run_bbp_read(sc, 152, &bbp152);
3604 run_bbp_write(sc, 152, bbp152 & ~0x80);
3605 } else {
3606 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL0x73, 0);
3607 run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp);
3608 run_write(sc, RT2860_GPIO_CTRL0x0228, (tmp & ~0x0808) | 0x08);
3609 }
3610 } else {
3611 if (sc->rf_rev == RT5390_RF_53700x5370) {
3612 run_bbp_read(sc, 152, &bbp152);
3613 run_bbp_write(sc, 152, bbp152 | 0x80);
3614 } else {
3615 run_mcu_cmd(sc, RT2860_MCU_CMD_ANTSEL0x73, 1);
3616 run_read(sc, RT2860_GPIO_CTRL0x0228, &tmp);
3617 run_write(sc, RT2860_GPIO_CTRL0x0228, tmp & ~0x0808);
3618 }
3619 }
3620}
3621
3622int
3623run_set_chan(struct run_softc *sc, struct ieee80211_channel *c)
3624{
3625 struct ieee80211com *ic = &sc->sc_ic;
3626 u_int chan, group;
3627
3628 chan = ieee80211_chan2ieee(ic, c);
3629 if (chan == 0 || chan == IEEE80211_CHAN_ANY0xffff)
3630 return EINVAL22;
3631
3632 if (sc->mac_ver == 0x5592)
3633 run_rt5592_set_chan(sc, chan);
3634 else if (sc->mac_ver >= 0x5390)
3635 run_rt5390_set_chan(sc, chan);
3636 else if (sc->mac_ver == 0x3593)
3637 run_rt3593_set_chan(sc, chan);
3638 else if (sc->mac_ver == 0x3572)
3639 run_rt3572_set_chan(sc, chan);
3640 else if (sc->mac_ver >= 0x3070)
3641 run_rt3070_set_chan(sc, chan);
3642 else
3643 run_rt2870_set_chan(sc, chan);
3644
3645 /* determine channel group */
3646 if (chan <= 14)
3647 group = 0;
3648 else if (chan <= 64)
3649 group = 1;
3650 else if (chan <= 128)
3651 group = 2;
3652 else
3653 group = 3;
3654
3655 /* XXX necessary only when group has changed! */
3656 run_select_chan_group(sc, group);
3657
3658 DELAY(1000)(*delay_func)(1000);
3659
3660 /* Perform IQ calibration. */
3661 if (sc->mac_ver >= 0x5392)
3662 run_iq_calib(sc, chan);
3663
3664 return 0;
3665}
3666
3667void
3668run_enable_tsf_sync(struct run_softc *sc)
3669{
3670 struct ieee80211com *ic = &sc->sc_ic;
3671 uint32_t tmp;
3672
3673 run_read(sc, RT2860_BCN_TIME_CFG0x1114, &tmp);
3674 tmp &= ~0x1fffff;
3675 tmp |= ic->ic_bss->ni_intval * 16;
3676 tmp |= RT2860_TSF_TIMER_EN(1 << 16) | RT2860_TBTT_TIMER_EN(1 << 19);
3677 /* local TSF is always updated with remote TSF on beacon reception */
3678 tmp |= 1 << RT2860_TSF_SYNC_MODE_SHIFT17;
3679 run_write(sc, RT2860_BCN_TIME_CFG0x1114, tmp);
3680}
3681
3682void
3683run_enable_mrr(struct run_softc *sc)
3684{
3685#define CCK(mcs) (mcs)
3686#define OFDM(mcs) (1 << 3 | (mcs))
3687 run_write(sc, RT2860_LG_FBK_CFG00x135c,
3688 OFDM(6) << 28 | /* 54->48 */
3689 OFDM(5) << 24 | /* 48->36 */
3690 OFDM(4) << 20 | /* 36->24 */
3691 OFDM(3) << 16 | /* 24->18 */
3692 OFDM(2) << 12 | /* 18->12 */
3693 OFDM(1) << 8 | /* 12-> 9 */
3694 OFDM(0) << 4 | /* 9-> 6 */
3695 OFDM(0)); /* 6-> 6 */
3696
3697 run_write(sc, RT2860_LG_FBK_CFG10x1360,
3698 CCK(2) << 12 | /* 11->5.5 */
3699 CCK(1) << 8 | /* 5.5-> 2 */
3700 CCK(0) << 4 | /* 2-> 1 */
3701 CCK(0)); /* 1-> 1 */
3702#undef OFDM
3703#undef CCK
3704}
3705
3706void
3707run_set_txpreamble(struct run_softc *sc)
3708{
3709 uint32_t tmp;
3710
3711 run_read(sc, RT2860_AUTO_RSP_CFG0x1404, &tmp);
3712 if (sc->sc_ic.ic_flags & IEEE80211_F_SHPREAMBLE0x00040000)
3713 tmp |= RT2860_CCK_SHORT_EN(1 << 4);
3714 else
3715 tmp &= ~RT2860_CCK_SHORT_EN(1 << 4);
3716 run_write(sc, RT2860_AUTO_RSP_CFG0x1404, tmp);
3717}
3718
3719void
3720run_set_basicrates(struct run_softc *sc)
3721{
3722 struct ieee80211com *ic = &sc->sc_ic;
3723
3724 /* set basic rates mask */
3725 if (ic->ic_curmode == IEEE80211_MODE_11B)
3726 run_write(sc, RT2860_LEGACY_BASIC_RATE0x1408, 0x003);
3727 else if (ic->ic_curmode == IEEE80211_MODE_11A)
3728 run_write(sc, RT2860_LEGACY_BASIC_RATE0x1408, 0x150);
3729 else /* 11g */
3730 run_write(sc, RT2860_LEGACY_BASIC_RATE0x1408, 0x15f);
3731}
3732
3733void
3734run_set_leds(struct run_softc *sc, uint16_t which)
3735{
3736 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LEDS0x50,
3737 which | (sc->leds & 0x7f));
3738}
3739
3740void
3741run_set_bssid(struct run_softc *sc, const uint8_t *bssid)
3742{
3743 run_write(sc, RT2860_MAC_BSSID_DW00x1010,
3744 bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24);
3745 run_write(sc, RT2860_MAC_BSSID_DW10x1014,
3746 bssid[4] | bssid[5] << 8);
3747}
3748
3749void
3750run_set_macaddr(struct run_softc *sc, const uint8_t *addr)
3751{
3752 run_write(sc, RT2860_MAC_ADDR_DW00x1008,
3753 addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
3754 run_write(sc, RT2860_MAC_ADDR_DW10x100c,
3755 addr[4] | addr[5] << 8 | 0xff << 16);
3756}
3757
3758void
3759run_updateslot(struct ieee80211com *ic)
3760{
3761 /* do it in a process context */
3762 run_do_async(ic->ic_softcic_ac.ac_if.if_softc, run_updateslot_cb, NULL((void *)0), 0);
3763}
3764
3765/* ARGSUSED */
3766void
3767run_updateslot_cb(struct run_softc *sc, void *arg)
3768{
3769 uint32_t tmp;
3770
3771 run_read(sc, RT2860_BKOFF_SLOT_CFG0x1104, &tmp);
3772 tmp &= ~0xff;
3773 tmp |= (sc->sc_ic.ic_flags & IEEE80211_F_SHSLOT0x00020000) ?
3774 IEEE80211_DUR_DS_SHSLOT9 : IEEE80211_DUR_DS_SLOT20;
3775 run_write(sc, RT2860_BKOFF_SLOT_CFG0x1104, tmp);
3776}
3777
3778#if NBPFILTER1 > 0
3779int8_t
3780run_rssi2dbm(struct run_softc *sc, uint8_t rssi, uint8_t rxchain)
3781{
3782 struct ieee80211com *ic = &sc->sc_ic;
3783 struct ieee80211_channel *c = ic->ic_ibss_chan;
3784 int delta;
3785
3786 if (IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) {
3787 u_int chan = ieee80211_chan2ieee(ic, c);
3788 delta = sc->rssi_5ghz[rxchain];
3789
3790 /* determine channel group */
3791 if (chan <= 64)
3792 delta -= sc->lna[1];
3793 else if (chan <= 128)
3794 delta -= sc->lna[2];
3795 else
3796 delta -= sc->lna[3];
3797 } else
3798 delta = sc->rssi_2ghz[rxchain] - sc->lna[0];
3799
3800 return -12 - delta - rssi;
3801}
3802#endif
3803
3804void
3805run_rt5390_bbp_init(struct run_softc *sc)
3806{
3807 int i;
3808 uint8_t bbp;
3809
3810 /* Apply maximum likelihood detection for 2 stream case. */
3811 run_bbp_read(sc, 105, &bbp);
3812 if (sc->nrxchains > 1)
3813 run_bbp_write(sc, 105, bbp | RT5390_MLD(1 << 2));
3814
3815 /* Avoid data lost and CRC error. */
3816 run_bbp_read(sc, 4, &bbp);
3817 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6));
3818
3819 if (sc->mac_ver == 0x5592) {
3820 for (i = 0; i < nitems(rt5592_def_bbp)(sizeof((rt5592_def_bbp)) / sizeof((rt5592_def_bbp)[0])); i++) {
3821 run_bbp_write(sc, rt5592_def_bbp[i].reg,
3822 rt5592_def_bbp[i].val);
3823 }
3824 for (i = 0; i < nitems(rt5592_bbp_r196)(sizeof((rt5592_bbp_r196)) / sizeof((rt5592_bbp_r196)[0])); i++) {
3825 run_bbp_write(sc, 195, i + 0x80);
3826 run_bbp_write(sc, 196, rt5592_bbp_r196[i]);
3827 }
3828 } else {
3829 for (i = 0; i < nitems(rt5390_def_bbp)(sizeof((rt5390_def_bbp)) / sizeof((rt5390_def_bbp)[0])); i++) {
3830 run_bbp_write(sc, rt5390_def_bbp[i].reg,
3831 rt5390_def_bbp[i].val);
3832 }
3833 }
3834 if (sc->mac_ver == 0x5392) {
3835 run_bbp_write(sc, 88, 0x90);
3836 run_bbp_write(sc, 95, 0x9a);
3837 run_bbp_write(sc, 98, 0x12);
3838 run_bbp_write(sc, 106, 0x12);
3839 run_bbp_write(sc, 134, 0xd0);
3840 run_bbp_write(sc, 135, 0xf6);
3841 run_bbp_write(sc, 148, 0x84);
3842 }
3843
3844 run_bbp_read(sc, 152, &bbp);
3845 run_bbp_write(sc, 152, bbp | 0x80);
3846
3847 /* Fix BBP254 for RT5592C. */
3848 if (sc->mac_ver == 0x5592 && sc->mac_rev >= 0x0221) {
3849 run_bbp_read(sc, 254, &bbp);
3850 run_bbp_write(sc, 254, bbp | 0x80);
3851 }
3852
3853 /* Disable hardware antenna diversity. */
3854 if (sc->mac_ver == 0x5390)
3855 run_bbp_write(sc, 154, 0);
3856
3857 /* Initialize Rx CCK/OFDM frequency offset report. */
3858 run_bbp_write(sc, 142, 1);
3859 run_bbp_write(sc, 143, 57);
3860}
3861
3862int
3863run_bbp_init(struct run_softc *sc)
3864{
3865 int i, error, ntries;
3866 uint8_t bbp0;
3867
3868 /* wait for BBP to wake up */
3869 for (ntries = 0; ntries < 20; ntries++) {
3870 if ((error = run_bbp_read(sc, 0, &bbp0)) != 0)
3871 return error;
3872 if (bbp0 != 0 && bbp0 != 0xff)
3873 break;
3874 }
3875 if (ntries == 20)
3876 return ETIMEDOUT60;
3877
3878 /* initialize BBP registers to default values */
3879 if (sc->mac_ver >= 0x5390)
3880 run_rt5390_bbp_init(sc);
3881 else {
3882 for (i = 0; i < nitems(rt2860_def_bbp)(sizeof((rt2860_def_bbp)) / sizeof((rt2860_def_bbp)[0])); i++) {
3883 run_bbp_write(sc, rt2860_def_bbp[i].reg,
3884 rt2860_def_bbp[i].val);
3885 }
3886 }
3887
3888 if (sc->mac_ver == 0x3593) {
3889 run_bbp_write(sc, 79, 0x13);
3890 run_bbp_write(sc, 80, 0x05);
3891 run_bbp_write(sc, 81, 0x33);
3892 run_bbp_write(sc, 86, 0x46);
3893 run_bbp_write(sc, 137, 0x0f);
3894 }
3895
3896 /* fix BBP84 for RT2860E */
3897 if (sc->mac_ver == 0x2860 && sc->mac_rev != 0x0101)
3898 run_bbp_write(sc, 84, 0x19);
3899
3900 if (sc->mac_ver >= 0x3070 && (sc->mac_ver != 0x3593 &&
3901 sc->mac_ver != 0x5592)) {
3902 run_bbp_write(sc, 79, 0x13);
3903 run_bbp_write(sc, 80, 0x05);
3904 run_bbp_write(sc, 81, 0x33);
3905 } else if (sc->mac_ver == 0x2860 && sc->mac_rev == 0x0100) {
3906 run_bbp_write(sc, 69, 0x16);
3907 run_bbp_write(sc, 73, 0x12);
3908 }
3909 return 0;
3910}
3911
3912int
3913run_rt3070_rf_init(struct run_softc *sc)
3914{
3915 uint32_t tmp;
3916 uint8_t bbp4, mingain, rf, target;
3917 int i;
3918
3919 run_rt3070_rf_read(sc, 30, &rf);
3920 /* toggle RF R30 bit 7 */
3921 run_rt3070_rf_write(sc, 30, rf | 0x80);
3922 DELAY(1000)(*delay_func)(1000);
3923 run_rt3070_rf_write(sc, 30, rf & ~0x80);
3924
3925 /* initialize RF registers to default value */
3926 if (sc->mac_ver == 0x3572) {
3927 for (i = 0; i < nitems(rt3572_def_rf)(sizeof((rt3572_def_rf)) / sizeof((rt3572_def_rf)[0])); i++) {
3928 run_rt3070_rf_write(sc, rt3572_def_rf[i].reg,
3929 rt3572_def_rf[i].val);
3930 }
3931 } else {
3932 for (i = 0; i < nitems(rt3070_def_rf)(sizeof((rt3070_def_rf)) / sizeof((rt3070_def_rf)[0])); i++) {
3933 run_rt3070_rf_write(sc, rt3070_def_rf[i].reg,
3934 rt3070_def_rf[i].val);
3935 }
3936 }
3937 if (sc->mac_ver == 0x3070 && sc->mac_rev < 0x0201) {
3938 /*
3939 * Change voltage from 1.2V to 1.35V for RT3070.
3940 * The DAC issue (RT3070_LDO_CFG0) has been fixed
3941 * in RT3070(F).
3942 */
3943 run_read(sc, RT3070_LDO_CFG00x05d4, &tmp);
3944 tmp = (tmp & ~0x0f000000) | 0x0d000000;
3945 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
3946
3947 } else if (sc->mac_ver == 0x3071) {
3948 run_rt3070_rf_read(sc, 6, &rf);
3949 run_rt3070_rf_write(sc, 6, rf | 0x40);
3950 run_rt3070_rf_write(sc, 31, 0x14);
3951
3952 run_read(sc, RT3070_LDO_CFG00x05d4, &tmp);
3953 tmp &= ~0x1f000000;
3954 if (sc->mac_rev < 0x0211)
3955 tmp |= 0x0d000000; /* 1.35V */
3956 else
3957 tmp |= 0x01000000; /* 1.2V */
3958 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
3959
3960 /* patch LNA_PE_G1 */
3961 run_read(sc, RT3070_GPIO_SWITCH0x05dc, &tmp);
3962 run_write(sc, RT3070_GPIO_SWITCH0x05dc, tmp & ~0x20);
3963
3964 } else if (sc->mac_ver == 0x3572) {
3965 run_rt3070_rf_read(sc, 6, &rf);
3966 run_rt3070_rf_write(sc, 6, rf | 0x40);
3967 /* increase voltage from 1.2V to 1.35V */
3968 run_read(sc, RT3070_LDO_CFG00x05d4, &tmp);
3969 tmp = (tmp & ~0x1f000000) | 0x0d000000;
3970 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
3971
3972 if (sc->mac_rev < 0x0211 || !sc->patch_dac) {
3973 DELAY(1)(*delay_func)(1); /* wait for 1msec */
3974 /* decrease voltage back to 1.2V */
3975 tmp = (tmp & ~0x1f000000) | 0x01000000;
3976 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
3977 }
3978 }
3979
3980 /* select 20MHz bandwidth */
3981 run_rt3070_rf_read(sc, 31, &rf);
3982 run_rt3070_rf_write(sc, 31, rf & ~0x20);
3983
3984 /* calibrate filter for 20MHz bandwidth */
3985 sc->rf24_20mhz = 0x1f; /* default value */
3986 target = (sc->mac_ver < 0x3071) ? 0x16 : 0x13;
3987 run_rt3070_filter_calib(sc, 0x07, target, &sc->rf24_20mhz);
3988
3989 /* select 40MHz bandwidth */
3990 run_bbp_read(sc, 4, &bbp4);
3991 run_bbp_write(sc, 4, (bbp4 & ~0x18) | 0x10);
3992 run_rt3070_rf_read(sc, 31, &rf);
3993 run_rt3070_rf_write(sc, 31, rf | 0x20);
3994
3995 /* calibrate filter for 40MHz bandwidth */
3996 sc->rf24_40mhz = 0x2f; /* default value */
3997 target = (sc->mac_ver < 0x3071) ? 0x19 : 0x15;
3998 run_rt3070_filter_calib(sc, 0x27, target, &sc->rf24_40mhz);
3999
4000 /* go back to 20MHz bandwidth */
4001 run_bbp_read(sc, 4, &bbp4);
4002 run_bbp_write(sc, 4, bbp4 & ~0x18);
4003
4004 if (sc->mac_ver == 0x3572) {
4005 /* save default BBP registers 25 and 26 values */
4006 run_bbp_read(sc, 25, &sc->bbp25);
4007 run_bbp_read(sc, 26, &sc->bbp26);
4008
4009 } else if (sc->mac_rev < 0x0201 || sc->mac_rev < 0x0211)
4010 run_rt3070_rf_write(sc, 27, 0x03);
4011
4012 run_read(sc, RT3070_OPT_140x0114, &tmp);
4013 run_write(sc, RT3070_OPT_140x0114, tmp | 1);
4014
4015 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) {
4016 run_rt3070_rf_read(sc, 17, &rf);
4017 rf &= ~RT3070_TX_LO1(1 << 3);
4018 if ((sc->mac_ver == 0x3070 ||
4019 (sc->mac_ver == 0x3071 && sc->mac_rev >= 0x0211)) &&
4020 !sc->ext_2ghz_lna)
4021 rf |= 0x20; /* fix for long range Rx issue */
4022 mingain = (sc->mac_ver == 0x3070) ? 1 : 2;
4023 if (sc->txmixgain_2ghz >= mingain)
4024 rf = (rf & ~0x7) | sc->txmixgain_2ghz;
4025 run_rt3070_rf_write(sc, 17, rf);
4026 }
4027 if (sc->mac_ver == 0x3071) {
4028 run_rt3070_rf_read(sc, 1, &rf);
4029 rf &= ~(RT3070_RX0_PD(1 << 2) | RT3070_TX0_PD(1 << 3));
4030 rf |= RT3070_RF_BLOCK(1 << 0) | RT3070_RX1_PD(1 << 4) | RT3070_TX1_PD(1 << 5);
4031 run_rt3070_rf_write(sc, 1, rf);
4032
4033 run_rt3070_rf_read(sc, 15, &rf);
4034 run_rt3070_rf_write(sc, 15, rf & ~RT3070_TX_LO2(1 << 3));
4035
4036 run_rt3070_rf_read(sc, 20, &rf);
4037 run_rt3070_rf_write(sc, 20, rf & ~RT3070_RX_LO1(1 << 3));
4038
4039 run_rt3070_rf_read(sc, 21, &rf);
4040 run_rt3070_rf_write(sc, 21, rf & ~RT3070_RX_LO2(1 << 3));
4041 }
4042 if (sc->mac_ver == 0x3070 || sc->mac_ver == 0x3071) {
4043 /* fix Tx to Rx IQ glitch by raising RF voltage */
4044 run_rt3070_rf_read(sc, 27, &rf);
4045 rf &= ~0x77;
4046 if (sc->mac_rev < 0x0211)
4047 rf |= 0x03;
4048 run_rt3070_rf_write(sc, 27, rf);
4049 }
4050 return 0;
4051}
4052
4053void
4054run_rt3593_rf_init(struct run_softc *sc)
4055{
4056 uint32_t tmp;
4057 uint8_t rf;
4058 int i;
4059
4060 /* Disable the GPIO bits 4 and 7 for LNA PE control. */
4061 run_read(sc, RT3070_GPIO_SWITCH0x05dc, &tmp);
4062 tmp &= ~(1 << 4 | 1 << 7);
4063 run_write(sc, RT3070_GPIO_SWITCH0x05dc, tmp);
4064
4065 /* Initialize RF registers to default value. */
4066 for (i = 0; i < nitems(rt3593_def_rf)(sizeof((rt3593_def_rf)) / sizeof((rt3593_def_rf)[0])); i++) {
4067 run_rt3070_rf_write(sc, rt3593_def_rf[i].reg,
4068 rt3593_def_rf[i].val);
4069 }
4070
4071 /* Toggle RF R2 to initiate calibration. */
4072 run_rt3070_rf_write(sc, 2, RT3593_RESCAL(1 << 7));
4073
4074 /* Initialize RF frequency offset. */
4075 run_adjust_freq_offset(sc);
4076
4077 run_rt3070_rf_read(sc, 18, &rf);
4078 run_rt3070_rf_write(sc, 18, rf | RT3593_AUTOTUNE_BYPASS(1 << 6));
4079
4080 /*
4081 * Increase voltage from 1.2V to 1.35V, wait for 1 msec to
4082 * decrease voltage back to 1.2V.
4083 */
4084 run_read(sc, RT3070_LDO_CFG00x05d4, &tmp);
4085 tmp = (tmp & ~0x1f000000) | 0x0d000000;
4086 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
4087 DELAY(1)(*delay_func)(1);
4088 tmp = (tmp & ~0x1f000000) | 0x01000000;
4089 run_write(sc, RT3070_LDO_CFG00x05d4, tmp);
4090
4091 sc->rf24_20mhz = 0x1f;
4092 sc->rf24_40mhz = 0x2f;
4093
4094 /* Save default BBP registers 25 and 26 values. */
4095 run_bbp_read(sc, 25, &sc->bbp25);
4096 run_bbp_read(sc, 26, &sc->bbp26);
4097
4098 run_read(sc, RT3070_OPT_140x0114, &tmp);
4099 run_write(sc, RT3070_OPT_140x0114, tmp | 1);
4100}
4101
4102void
4103run_rt5390_rf_init(struct run_softc *sc)
4104{
4105 uint32_t tmp;
4106 uint8_t rf;
4107 int i;
4108
4109 /* Toggle RF R2 to initiate calibration. */
4110 if (sc->mac_ver == 0x5390) {
4111 run_rt3070_rf_read(sc, 2, &rf);
4112 run_rt3070_rf_write(sc, 2, rf | RT3593_RESCAL(1 << 7));
4113 DELAY(10)(*delay_func)(10);
4114 run_rt3070_rf_write(sc, 2, rf & ~RT3593_RESCAL(1 << 7));
4115 } else {
4116 run_rt3070_rf_write(sc, 2, RT3593_RESCAL(1 << 7));
4117 DELAY(10)(*delay_func)(10);
4118 }
4119
4120 /* Initialize RF registers to default value. */
4121 if (sc->mac_ver == 0x5592) {
4122 for (i = 0; i < nitems(rt5592_def_rf)(sizeof((rt5592_def_rf)) / sizeof((rt5592_def_rf)[0])); i++) {
4123 run_rt3070_rf_write(sc, rt5592_def_rf[i].reg,
4124 rt5592_def_rf[i].val);
4125 }
4126 /* Initialize RF frequency offset. */
4127 run_adjust_freq_offset(sc);
4128 } else if (sc->mac_ver == 0x5392) {
4129 for (i = 0; i < nitems(rt5392_def_rf)(sizeof((rt5392_def_rf)) / sizeof((rt5392_def_rf)[0])); i++) {
4130 run_rt3070_rf_write(sc, rt5392_def_rf[i].reg,
4131 rt5392_def_rf[i].val);
4132 }
4133 if (sc->mac_rev >= 0x0223) {
4134 run_rt3070_rf_write(sc, 23, 0x0f);
4135 run_rt3070_rf_write(sc, 24, 0x3e);
4136 run_rt3070_rf_write(sc, 51, 0x32);
4137 run_rt3070_rf_write(sc, 53, 0x22);
4138 run_rt3070_rf_write(sc, 56, 0xc1);
4139 run_rt3070_rf_write(sc, 59, 0x0f);
4140 }
4141 } else {
4142 for (i = 0; i < nitems(rt5390_def_rf)(sizeof((rt5390_def_rf)) / sizeof((rt5390_def_rf)[0])); i++) {
4143 run_rt3070_rf_write(sc, rt5390_def_rf[i].reg,
4144 rt5390_def_rf[i].val);
4145 }
4146 if (sc->mac_rev >= 0x0502) {
4147 run_rt3070_rf_write(sc, 6, 0xe0);
4148 run_rt3070_rf_write(sc, 25, 0x80);
4149 run_rt3070_rf_write(sc, 46, 0x73);
4150 run_rt3070_rf_write(sc, 53, 0x00);
4151 run_rt3070_rf_write(sc, 56, 0x42);
4152 run_rt3070_rf_write(sc, 61, 0xd1);
4153 }
4154 }
4155
4156 sc->rf24_20mhz = 0x1f; /* default value */
4157 sc->rf24_40mhz = (sc->mac_ver == 0x5592) ? 0 : 0x2f;
4158
4159 if (sc->mac_rev < 0x0211)
4160 run_rt3070_rf_write(sc, 27, 0x3);
4161
4162 run_read(sc, RT3070_OPT_140x0114, &tmp);
4163 run_write(sc, RT3070_OPT_140x0114, tmp | 1);
4164}
4165
4166int
4167run_rt3070_filter_calib(struct run_softc *sc, uint8_t init, uint8_t target,
4168 uint8_t *val)
4169{
4170 uint8_t rf22, rf24;
4171 uint8_t bbp55_pb, bbp55_sb, delta;
4172 int ntries;
4173
4174 /* program filter */
4175 run_rt3070_rf_read(sc, 24, &rf24);
4176 rf24 = (rf24 & 0xc0) | init; /* initial filter value */
4177 run_rt3070_rf_write(sc, 24, rf24);
4178
4179 /* enable baseband loopback mode */
4180 run_rt3070_rf_read(sc, 22, &rf22);
4181 run_rt3070_rf_write(sc, 22, rf22 | 0x01);
4182
4183 /* set power and frequency of passband test tone */
4184 run_bbp_write(sc, 24, 0x00);
4185 for (ntries = 0; ntries < 100; ntries++) {
4186 /* transmit test tone */
4187 run_bbp_write(sc, 25, 0x90);
4188 DELAY(1000)(*delay_func)(1000);
4189 /* read received power */
4190 run_bbp_read(sc, 55, &bbp55_pb);
4191 if (bbp55_pb != 0)
4192 break;
4193 }
4194 if (ntries == 100)
4195 return ETIMEDOUT60;
4196
4197 /* set power and frequency of stopband test tone */
4198 run_bbp_write(sc, 24, 0x06);
4199 for (ntries = 0; ntries < 100; ntries++) {
4200 /* transmit test tone */
4201 run_bbp_write(sc, 25, 0x90);
4202 DELAY(1000)(*delay_func)(1000);
4203 /* read received power */
4204 run_bbp_read(sc, 55, &bbp55_sb);
4205
4206 delta = bbp55_pb - bbp55_sb;
4207 if (delta > target)
4208 break;
4209
4210 /* reprogram filter */
4211 rf24++;
4212 run_rt3070_rf_write(sc, 24, rf24);
4213 }
4214 if (ntries < 100) {
4215 if (rf24 != init)
4216 rf24--; /* backtrack */
4217 *val = rf24;
4218 run_rt3070_rf_write(sc, 24, rf24);
4219 }
4220
4221 /* restore initial state */
4222 run_bbp_write(sc, 24, 0x00);
4223
4224 /* disable baseband loopback mode */
4225 run_rt3070_rf_read(sc, 22, &rf22);
4226 run_rt3070_rf_write(sc, 22, rf22 & ~0x01);
4227
4228 return 0;
4229}
4230
4231void
4232run_rt3070_rf_setup(struct run_softc *sc)
4233{
4234 uint8_t bbp, rf;
4235 int i;
4236
4237 if (sc->mac_ver == 0x3572) {
4238 /* enable DC filter */
4239 if (sc->mac_rev >= 0x0201)
4240 run_bbp_write(sc, 103, 0xc0);
4241
4242 run_bbp_read(sc, 138, &bbp);
4243 if (sc->ntxchains == 1)
4244 bbp |= 0x20; /* turn off DAC1 */
4245 if (sc->nrxchains == 1)
4246 bbp &= ~0x02; /* turn off ADC1 */
4247 run_bbp_write(sc, 138, bbp);
4248
4249 if (sc->mac_rev >= 0x0211) {
4250 /* improve power consumption */
4251 run_bbp_read(sc, 31, &bbp);
4252 run_bbp_write(sc, 31, bbp & ~0x03);
4253 }
4254
4255 run_rt3070_rf_read(sc, 16, &rf);
4256 rf = (rf & ~0x07) | sc->txmixgain_2ghz;
4257 run_rt3070_rf_write(sc, 16, rf);
4258
4259 } else if (sc->mac_ver == 0x3071) {
4260 /* enable DC filter */
4261 if (sc->mac_rev >= 0x0211) {
4262 run_bbp_write(sc, 103, 0xc0);
4263
4264 /* improve power consumption */
4265 run_bbp_read(sc, 31, &bbp);
4266 run_bbp_write(sc, 31, bbp & ~0x03);
4267 }
4268
4269 run_bbp_read(sc, 138, &bbp);
4270 if (sc->ntxchains == 1)
4271 bbp |= 0x20; /* turn off DAC1 */
4272 if (sc->nrxchains == 1)
4273 bbp &= ~0x02; /* turn off ADC1 */
4274 run_bbp_write(sc, 138, bbp);
4275
4276 run_write(sc, RT2860_TX_SW_CFG10x1334, 0);
4277 if (sc->mac_rev < 0x0211) {
4278 run_write(sc, RT2860_TX_SW_CFG20x1338,
4279 sc->patch_dac ? 0x2c : 0x0f);
4280 } else
4281 run_write(sc, RT2860_TX_SW_CFG20x1338, 0);
4282
4283 } else if (sc->mac_ver == 0x3070) {
4284 if (sc->mac_rev >= 0x0201) {
4285 /* enable DC filter */
4286 run_bbp_write(sc, 103, 0xc0);
4287
4288 /* improve power consumption */
4289 run_bbp_read(sc, 31, &bbp);
4290 run_bbp_write(sc, 31, bbp & ~0x03);
4291 }
4292
4293 if (sc->mac_rev < 0x0201) {
4294 run_write(sc, RT2860_TX_SW_CFG10x1334, 0);
4295 run_write(sc, RT2860_TX_SW_CFG20x1338, 0x2c);
4296 } else
4297 run_write(sc, RT2860_TX_SW_CFG20x1338, 0);
4298 }
4299
4300 /* initialize RF registers from ROM for >=RT3071*/
4301 if (sc->mac_ver >= 0x3071) {
4302 for (i = 0; i < 10; i++) {
4303 if (sc->rf[i].reg == 0 || sc->rf[i].reg == 0xff)
4304 continue;
4305 run_rt3070_rf_write(sc, sc->rf[i].reg, sc->rf[i].val);
4306 }
4307 }
4308}
4309
4310void
4311run_rt3593_rf_setup(struct run_softc *sc)
4312{
4313 uint8_t bbp, rf;
4314
4315 if (sc->mac_rev >= 0x0211) {
4316 /* Enable DC filter. */
4317 run_bbp_write(sc, 103, 0xc0);
4318 }
4319 run_write(sc, RT2860_TX_SW_CFG10x1334, 0);
4320 if (sc->mac_rev < 0x0211) {
4321 run_write(sc, RT2860_TX_SW_CFG20x1338,
4322 sc->patch_dac ? 0x2c : 0x0f);
4323 } else
4324 run_write(sc, RT2860_TX_SW_CFG20x1338, 0);
4325
4326 run_rt3070_rf_read(sc, 50, &rf);
4327 run_rt3070_rf_write(sc, 50, rf & ~RT3593_TX_LO2(1 << 4));
4328
4329 run_rt3070_rf_read(sc, 51, &rf);
4330 rf = (rf & ~(RT3593_TX_LO1(1 << 4) | 0x0c)) |
4331 ((sc->txmixgain_2ghz & 0x07) << 2);
4332 run_rt3070_rf_write(sc, 51, rf);
4333
4334 run_rt3070_rf_read(sc, 38, &rf);
4335 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1(1 << 5));
4336
4337 run_rt3070_rf_read(sc, 39, &rf);
4338 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2(1 << 7));
4339
4340 run_rt3070_rf_read(sc, 1, &rf);
4341 run_rt3070_rf_write(sc, 1, rf & ~(RT3070_RF_BLOCK(1 << 0) | RT3070_PLL_PD(1 << 1)));
4342
4343 run_rt3070_rf_read(sc, 30, &rf);
4344 rf = (rf & ~0x18) | 0x10;
4345 run_rt3070_rf_write(sc, 30, rf);
4346
4347 /* Apply maximum likelihood detection for 2 stream case. */
4348 run_bbp_read(sc, 105, &bbp);
4349 if (sc->nrxchains > 1)
4350 run_bbp_write(sc, 105, bbp | RT5390_MLD(1 << 2));
4351
4352 /* Avoid data lost and CRC error. */
4353 run_bbp_read(sc, 4, &bbp);
4354 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6));
4355
4356 run_bbp_write(sc, 92, 0x02);
4357 run_bbp_write(sc, 82, 0x82);
4358 run_bbp_write(sc, 106, 0x05);
4359 run_bbp_write(sc, 104, 0x92);
4360 run_bbp_write(sc, 88, 0x90);
4361 run_bbp_write(sc, 148, 0xc8);
4362 run_bbp_write(sc, 47, 0x48);
4363 run_bbp_write(sc, 120, 0x50);
4364
4365 run_bbp_write(sc, 163, 0x9d);
4366
4367 /* SNR mapping. */
4368 run_bbp_write(sc, 142, 0x06);
4369 run_bbp_write(sc, 143, 0xa0);
4370 run_bbp_write(sc, 142, 0x07);
4371 run_bbp_write(sc, 143, 0xa1);
4372 run_bbp_write(sc, 142, 0x08);
4373 run_bbp_write(sc, 143, 0xa2);
4374
4375 run_bbp_write(sc, 31, 0x08);
4376 run_bbp_write(sc, 68, 0x0b);
4377 run_bbp_write(sc, 105, 0x04);
4378}
4379
4380void
4381run_rt5390_rf_setup(struct run_softc *sc)
4382{
4383 uint8_t bbp, rf;
4384
4385 if (sc->mac_rev >= 0x0211) {
4386 /* Enable DC filter. */
4387 run_bbp_write(sc, 103, 0xc0);
4388
4389 if (sc->mac_ver != 0x5592) {
4390 /* Improve power consumption. */
4391 run_bbp_read(sc, 31, &bbp);
4392 run_bbp_write(sc, 31, bbp & ~0x03);
4393 }
4394 }
4395
4396 run_bbp_read(sc, 138, &bbp);
4397 if (sc->ntxchains == 1)
4398 bbp |= 0x20; /* turn off DAC1 */
4399 if (sc->nrxchains == 1)
4400 bbp &= ~0x02; /* turn off ADC1 */
4401 run_bbp_write(sc, 138, bbp);
4402
4403 run_rt3070_rf_read(sc, 38, &rf);
4404 run_rt3070_rf_write(sc, 38, rf & ~RT5390_RX_LO1(1 << 5));
4405
4406 run_rt3070_rf_read(sc, 39, &rf);
4407 run_rt3070_rf_write(sc, 39, rf & ~RT5390_RX_LO2(1 << 7));
4408
4409 /* Avoid data lost and CRC error. */
4410 run_bbp_read(sc, 4, &bbp);
4411 run_bbp_write(sc, 4, bbp | RT5390_MAC_IF_CTRL(1 << 6));
4412
4413 run_rt3070_rf_read(sc, 30, &rf);
4414 rf = (rf & ~0x18) | 0x10;
4415 run_rt3070_rf_write(sc, 30, rf);
4416
4417 if (sc->mac_ver != 0x5592) {
4418 run_write(sc, RT2860_TX_SW_CFG10x1334, 0);
4419 if (sc->mac_rev < 0x0211) {
4420 run_write(sc, RT2860_TX_SW_CFG20x1338,
4421 sc->patch_dac ? 0x2c : 0x0f);
4422 } else
4423 run_write(sc, RT2860_TX_SW_CFG20x1338, 0);
4424 }
4425}
4426
4427int
4428run_txrx_enable(struct run_softc *sc)
4429{
4430 uint32_t tmp;
4431 int error, ntries;
4432
4433 run_write(sc, RT2860_MAC_SYS_CTRL0x1004, RT2860_MAC_TX_EN(1 << 2));
4434 for (ntries = 0; ntries < 200; ntries++) {
4435 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp)) != 0)
4436 return error;
4437 if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0)
4438 break;
4439 DELAY(1000)(*delay_func)(1000);
4440 }
4441 if (ntries == 200)
4442 return ETIMEDOUT60;
4443
4444 DELAY(50)(*delay_func)(50);
4445
4446 tmp |= RT2860_RX_DMA_EN(1 << 2) | RT2860_TX_DMA_EN(1 << 0) | RT2860_TX_WB_DDONE(1 << 6);
4447 run_write(sc, RT2860_WPDMA_GLO_CFG0x0208, tmp);
4448
4449 /* enable Rx bulk aggregation (set timeout and limit) */
4450 tmp = RT2860_USB_TX_EN(1U << 23) | RT2860_USB_RX_EN(1U << 22) | RT2860_USB_RX_AGG_EN(1U << 21) |
4451 RT2860_USB_RX_AGG_TO(128)((128) & 0xff) | RT2860_USB_RX_AGG_LMT(2)((2) << 8);
4452 run_write(sc, RT2860_USB_DMA_CFG0x02a0, tmp);
4453
4454 /* set Rx filter */
4455 tmp = RT2860_DROP_CRC_ERR(1 << 0) | RT2860_DROP_PHY_ERR(1 << 1);
4456 if (sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR) {
4457 tmp |= RT2860_DROP_UC_NOME(1 << 2) | RT2860_DROP_DUPL(1 << 7) |
4458 RT2860_DROP_CTS(1 << 11) | RT2860_DROP_BA(1 << 14) | RT2860_DROP_ACK(1 << 10) |
4459 RT2860_DROP_VER_ERR(1 << 4) | RT2860_DROP_CTRL_RSV(1 << 16) |
4460 RT2860_DROP_CFACK(1 << 8) | RT2860_DROP_CFEND(1 << 9);
4461 if (sc->sc_ic.ic_opmode == IEEE80211_M_STA)
4462 tmp |= RT2860_DROP_RTS(1 << 12) | RT2860_DROP_PSPOLL(1 << 13);
4463 }
4464 run_write(sc, RT2860_RX_FILTR_CFG0x1400, tmp);
4465
4466 run_write(sc, RT2860_MAC_SYS_CTRL0x1004,
4467 RT2860_MAC_RX_EN(1 << 3) | RT2860_MAC_TX_EN(1 << 2));
4468
4469 return 0;
4470}
4471
4472void
4473run_adjust_freq_offset(struct run_softc *sc)
4474{
4475 uint8_t rf, tmp;
4476
4477 run_rt3070_rf_read(sc, 17, &rf);
4478 tmp = rf;
4479 rf = (rf & ~0x7f) | (sc->freq & 0x7f);
4480 rf = MIN(rf, 0x5f)(((rf)<(0x5f))?(rf):(0x5f));
4481
4482 if (tmp != rf)
4483 run_mcu_cmd(sc, 0x74, (tmp << 8 ) | rf);
4484}
4485
4486int
4487run_init(struct ifnet *ifp)
4488{
4489 struct run_softc *sc = ifp->if_softc;
4490 struct ieee80211com *ic = &sc->sc_ic;
4491 uint32_t tmp;
4492 uint8_t bbp1, bbp3;
4493 int i, error, qid, ridx, ntries;
4494
4495 if (usbd_is_dying(sc->sc_udev))
4496 return ENXIO6;
4497
4498 for (ntries = 0; ntries < 100; ntries++) {
4499 if ((error = run_read(sc, RT2860_ASIC_VER_ID0x1000, &tmp)) != 0)
4500 goto fail;
4501 if (tmp != 0 && tmp != 0xffffffff)
4502 break;
4503 DELAY(10)(*delay_func)(10);
4504 }
4505 if (ntries == 100) {
4506 error = ETIMEDOUT60;
4507 goto fail;
4508 }
4509
4510 if ((error = run_load_microcode(sc)) != 0) {
4511 printf("%s: could not load 8051 microcode\n",
4512 sc->sc_dev.dv_xname);
4513 goto fail;
4514 }
4515
4516 /* init host command ring */
4517 sc->cmdq.cur = sc->cmdq.next = sc->cmdq.queued = 0;
4518
4519 /* init Tx rings (4 EDCAs) */
4520 for (qid = 0; qid < 4; qid++) {
4521 if ((error = run_alloc_tx_ring(sc, qid)) != 0)
4522 goto fail;
4523 }
4524 /* init Rx ring */
4525 if ((error = run_alloc_rx_ring(sc)) != 0)
4526 goto fail;
4527
4528 IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl))__builtin_memcpy((ic->ic_myaddr), (((caddr_t)((ifp->if_sadl
)->sdl_data + (ifp->if_sadl)->sdl_nlen))), (6));
4529 run_set_macaddr(sc, ic->ic_myaddr);
4530
4531 for (ntries = 0; ntries < 100; ntries++) {
4532 if ((error = run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp)) != 0)
4533 goto fail;
4534 if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0)
4535 break;
4536 DELAY(1000)(*delay_func)(1000);
4537 }
4538 if (ntries == 100) {
4539 printf("%s: timeout waiting for DMA engine\n",
4540 sc->sc_dev.dv_xname);
4541 error = ETIMEDOUT60;
4542 goto fail;
4543 }
4544 tmp &= 0xff0;
4545 tmp |= RT2860_TX_WB_DDONE(1 << 6);
4546 run_write(sc, RT2860_WPDMA_GLO_CFG0x0208, tmp);
4547
4548 /* turn off PME_OEN to solve high-current issue */
4549 run_read(sc, RT2860_SYS_CTRL0x0400, &tmp);
4550 run_write(sc, RT2860_SYS_CTRL0x0400, tmp & ~RT2860_PME_OEN(1 << 13));
4551
4552 run_write(sc, RT2860_MAC_SYS_CTRL0x1004,
4553 RT2860_BBP_HRST(1 << 1) | RT2860_MAC_SRST(1 << 0));
4554 run_write(sc, RT2860_USB_DMA_CFG0x02a0, 0);
4555
4556 if ((error = run_reset(sc)) != 0) {
4557 printf("%s: could not reset chipset\n", sc->sc_dev.dv_xname);
4558 goto fail;
4559 }
4560
4561 run_write(sc, RT2860_MAC_SYS_CTRL0x1004, 0);
4562
4563 /* init Tx power for all Tx rates (from EEPROM) */
4564 for (ridx = 0; ridx < 5; ridx++) {
4565 if (sc->txpow20mhz[ridx] == 0xffffffff)
4566 continue;
4567 run_write(sc, RT2860_TX_PWR_CFG(ridx)(0x1314 + (ridx) * 4), sc->txpow20mhz[ridx]);
4568 }
4569
4570 for (i = 0; i < nitems(rt2870_def_mac)(sizeof((rt2870_def_mac)) / sizeof((rt2870_def_mac)[0])); i++)
4571 run_write(sc, rt2870_def_mac[i].reg, rt2870_def_mac[i].val);
4572 run_write(sc, RT2860_WMM_AIFSN_CFG0x0214, 0x00002273);
4573 run_write(sc, RT2860_WMM_CWMIN_CFG0x0218, 0x00002344);
4574 run_write(sc, RT2860_WMM_CWMAX_CFG0x021c, 0x000034aa);
4575
4576 if (sc->mac_ver >= 0x5390) {
4577 run_write(sc, RT2860_TX_SW_CFG00x1330,
4578 4 << RT2860_DLY_PAPE_EN_SHIFT8 | 4);
4579 if (sc->mac_ver >= 0x5392) {
4580 run_write(sc, RT2860_MAX_LEN_CFG0x1018, 0x00002fff);
4581 if (sc->mac_ver == 0x5592) {
4582 run_write(sc, RT2860_HT_FBK_CFG10x1358, 0xedcba980);
4583 run_write(sc, RT2860_TXOP_HLDR_ET0x1608, 0x00000082);
4584 } else {
4585 run_write(sc, RT2860_HT_FBK_CFG10x1358, 0xedcb4980);
4586 run_write(sc, RT2860_LG_FBK_CFG00x135c, 0xedcba322);
4587 }
4588 }
4589 } else if (sc->mac_ver == 0x3593) {
4590 run_write(sc, RT2860_TX_SW_CFG00x1330,
4591 4 << RT2860_DLY_PAPE_EN_SHIFT8 | 2);
4592 } else if (sc->mac_ver >= 0x3070) {
4593 /* set delay of PA_PE assertion to 1us (unit of 0.25us) */
4594 run_write(sc, RT2860_TX_SW_CFG00x1330,
4595 4 << RT2860_DLY_PAPE_EN_SHIFT8);
4596 }
4597
4598 /* wait while MAC is busy */
4599 for (ntries = 0; ntries < 100; ntries++) {
4600 if ((error = run_read(sc, RT2860_MAC_STATUS_REG0x1200, &tmp)) != 0)
4601 goto fail;
4602 if (!(tmp & (RT2860_RX_STATUS_BUSY(1 << 1) | RT2860_TX_STATUS_BUSY(1 << 0))))
4603 break;
4604 DELAY(1000)(*delay_func)(1000);
4605 }
4606 if (ntries == 100) {
4607 error = ETIMEDOUT60;
4608 goto fail;
4609 }
4610
4611 /* clear Host to MCU mailbox */
4612 run_write(sc, RT2860_H2M_BBPAGENT0x7028, 0);
4613 run_write(sc, RT2860_H2M_MAILBOX0x7010, 0);
4614 DELAY(1000)(*delay_func)(1000);
4615
4616 if ((error = run_bbp_init(sc)) != 0) {
4617 printf("%s: could not initialize BBP\n", sc->sc_dev.dv_xname);
4618 goto fail;
4619 }
4620
4621 /* abort TSF synchronization */
4622 run_read(sc, RT2860_BCN_TIME_CFG0x1114, &tmp);
4623 tmp &= ~(RT2860_BCN_TX_EN(1 << 20) | RT2860_TSF_TIMER_EN(1 << 16) |
4624 RT2860_TBTT_TIMER_EN(1 << 19));
4625 run_write(sc, RT2860_BCN_TIME_CFG0x1114, tmp);
4626
4627 /* clear RX WCID search table */
4628 run_set_region_4(sc, RT2860_WCID_ENTRY(0)(0x1800 + (0) * 8), 0, 512);
4629 /* clear WCID attribute table */
4630 run_set_region_4(sc, RT2860_WCID_ATTR(0)(0x6800 + (0) * 4), 0, 8 * 32);
4631 /* clear shared key table */
4632 run_set_region_4(sc, RT2860_SKEY(0, 0)(0x6c00 + (0) * 128 + (0) * 32), 0, 8 * 32);
4633 /* clear shared key mode */
4634 run_set_region_4(sc, RT2860_SKEY_MODE_0_70x7000, 0, 4);
4635
4636 run_read(sc, RT2860_US_CYC_CNT0x02a4, &tmp);
4637 tmp = (tmp & ~0xff) | 0x1e;
4638 run_write(sc, RT2860_US_CYC_CNT0x02a4, tmp);
4639
4640 if (sc->mac_rev != 0x0101)
4641 run_write(sc, RT2860_TXOP_CTRL_CFG0x1340, 0x0000583f);
4642
4643 run_write(sc, RT2860_WMM_TXOP0_CFG0x0220, 0);
4644 run_write(sc, RT2860_WMM_TXOP1_CFG0x0224, 48 << 16 | 96);
4645
4646 /* write vendor-specific BBP values (from EEPROM) */
4647 if (sc->mac_ver < 0x3593) {
4648 for (i = 0; i < 8; i++) {
4649 if (sc->bbp[i].reg == 0 || sc->bbp[i].reg == 0xff)
4650 continue;
4651 run_bbp_write(sc, sc->bbp[i].reg, sc->bbp[i].val);
4652 }
4653 }
4654
4655 /* select Main antenna for 1T1R devices */
4656 if (sc->rf_rev == RT3070_RF_30200x0005 || sc->rf_rev == RT5390_RF_53700x5370)
4657 run_set_rx_antenna(sc, 0);
4658
4659 /* send LEDs operating mode to microcontroller */
4660 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED10x52, sc->led[0]);
4661 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED20x53, sc->led[1]);
4662 (void)run_mcu_cmd(sc, RT2860_MCU_CMD_LED30x54, sc->led[2]);
4663
4664 if (sc->mac_ver >= 0x5390)
4665 run_rt5390_rf_init(sc);
4666 else if (sc->mac_ver == 0x3593)
4667 run_rt3593_rf_init(sc);
4668 else if (sc->mac_ver >= 0x3070)
4669 run_rt3070_rf_init(sc);
4670
4671 /* disable non-existing Rx chains */
4672 run_bbp_read(sc, 3, &bbp3);
4673 bbp3 &= ~(1 << 3 | 1 << 4);
4674 if (sc->nrxchains == 2)
4675 bbp3 |= 1 << 3;
4676 else if (sc->nrxchains == 3)
4677 bbp3 |= 1 << 4;
4678 run_bbp_write(sc, 3, bbp3);
4679
4680 /* disable non-existing Tx chains */
4681 run_bbp_read(sc, 1, &bbp1);
4682 if (sc->ntxchains == 1)
4683 bbp1 &= ~(1 << 3 | 1 << 4);
4684 run_bbp_write(sc, 1, bbp1);
4685
4686 if (sc->mac_ver >= 0x5390)
4687 run_rt5390_rf_setup(sc);
4688 else if (sc->mac_ver == 0x3593)
4689 run_rt3593_rf_setup(sc);
4690 else if (sc->mac_ver >= 0x3070)
4691 run_rt3070_rf_setup(sc);
4692
4693 /* select default channel */
4694 ic->ic_bss->ni_chan = ic->ic_ibss_chan;
4695 run_set_chan(sc, ic->ic_ibss_chan);
4696
4697 /* turn radio LED on */
4698 run_set_leds(sc, RT2860_LED_RADIO(1 << 13));
4699
4700 for (i = 0; i < RUN_RX_RING_COUNT1; i++) {
4701 struct run_rx_data *data = &sc->rxq.data[i];
4702
4703 usbd_setup_xfer(data->xfer, sc->rxq.pipeh, data, data->buf,
4704 RUN_MAX_RXSZ4096, USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01,
4705 USBD_NO_TIMEOUT0, run_rxeof);
4706 error = usbd_transfer(data->xfer);
4707 if (error != 0 && error != USBD_IN_PROGRESS)
4708 goto fail;
4709 }
4710
4711 if ((error = run_txrx_enable(sc)) != 0)
4712 goto fail;
4713
4714 ifp->if_flags |= IFF_RUNNING0x40;
4715 ifq_clr_oactive(&ifp->if_snd);
4716
4717 if (ic->ic_flags & IEEE80211_F_WEPON0x00000100) {
4718 /* install WEP keys */
4719 for (i = 0; i < IEEE80211_WEP_NKID4; i++) {
4720 if (ic->ic_nw_keys[i].k_cipher != IEEE80211_CIPHER_NONE)
4721 (void)run_set_key(ic, NULL((void *)0), &ic->ic_nw_keys[i]);
4722 }
4723 }
4724
4725 if (ic->ic_opmode == IEEE80211_M_MONITOR)
4726 ieee80211_new_state(ic, IEEE80211_S_RUN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_RUN), (-1)));
4727 else
4728 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1)));
4729
4730 if (error != 0)
4731fail: run_stop(ifp, 1);
4732 return error;
4733}
4734
4735void
4736run_stop(struct ifnet *ifp, int disable)
4737{
4738 struct run_softc *sc = ifp->if_softc;
4739 struct ieee80211com *ic = &sc->sc_ic;
4740 uint32_t tmp;
4741 int s, ntries, qid;
4742
4743 if (ifp->if_flags & IFF_RUNNING0x40)
4744 run_set_leds(sc, 0); /* turn all LEDs off */
4745
4746 sc->sc_tx_timer = 0;
4747 ifp->if_timer = 0;
4748 ifp->if_flags &= ~IFF_RUNNING0x40;
4749 ifq_clr_oactive(&ifp->if_snd);
4750
4751 timeout_del(&sc->scan_to);
4752 timeout_del(&sc->calib_to);
4753
4754 s = splusb()splraise(0x5);
4755 ieee80211_new_state(ic, IEEE80211_S_INIT, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_INIT), (-1)));
4756 /* wait for all queued asynchronous commands to complete */
4757 usb_wait_task(sc->sc_udev, &sc->sc_task);
4758 splx(s)spllower(s);
4759
4760 /* Disable Tx/Rx DMA. */
4761 run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp);
4762 tmp &= ~(RT2860_RX_DMA_EN(1 << 2) | RT2860_TX_DMA_EN(1 << 0));
4763 run_write(sc, RT2860_WPDMA_GLO_CFG0x0208, tmp);
4764
4765 for (ntries = 0; ntries < 100; ntries++) {
4766 if (run_read(sc, RT2860_WPDMA_GLO_CFG0x0208, &tmp) != 0)
4767 break;
4768 if ((tmp & (RT2860_TX_DMA_BUSY(1 << 1) | RT2860_RX_DMA_BUSY(1 << 3))) == 0)
4769 break;
4770 DELAY(10)(*delay_func)(10);
4771 }
4772 if (ntries == 100) {
4773 printf("%s: timeout waiting for DMA engine\n",
4774 sc->sc_dev.dv_xname);
4775 }
4776
4777 /* disable Tx/Rx */
4778 run_read(sc, RT2860_MAC_SYS_CTRL0x1004, &tmp);
4779 tmp &= ~(RT2860_MAC_RX_EN(1 << 3) | RT2860_MAC_TX_EN(1 << 2));
4780 run_write(sc, RT2860_MAC_SYS_CTRL0x1004, tmp);
4781
4782 /* wait for pending Tx to complete */
4783 for (ntries = 0; ntries < 100; ntries++) {
4784 if (run_read(sc, RT2860_TXRXQ_PCNT0x0438, &tmp) != 0)
4785 break;
4786 if ((tmp & RT2860_TX2Q_PCNT_MASK0x00ff0000) == 0)
4787 break;
4788 }
4789 DELAY(1000)(*delay_func)(1000);
4790 run_write(sc, RT2860_USB_DMA_CFG0x02a0, 0);
4791
4792 /* reset adapter */
4793 run_write(sc, RT2860_MAC_SYS_CTRL0x1004, RT2860_BBP_HRST(1 << 1) | RT2860_MAC_SRST(1 << 0));
4794 run_write(sc, RT2860_MAC_SYS_CTRL0x1004, 0);
4795
4796 /* reset Tx and Rx rings */
4797 sc->qfullmsk = 0;
4798 for (qid = 0; qid < 4; qid++)
4799 run_free_tx_ring(sc, qid);
4800 run_free_rx_ring(sc);
4801}