File: | dev/usb/if_ure.c |
Warning: | line 290, column 6 Assigned value is garbage or undefined |
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1 | /* $OpenBSD: if_ure.c,v 1.28 2021/08/20 04:54:10 kevlo Exp $ */ | |||
2 | /*- | |||
3 | * Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org> | |||
4 | * Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com> | |||
5 | * All rights reserved. | |||
6 | * | |||
7 | * Redistribution and use in source and binary forms, with or without | |||
8 | * modification, are permitted provided that the following conditions | |||
9 | * are met: | |||
10 | * 1. Redistributions of source code must retain the above copyright | |||
11 | * notice, this list of conditions and the following disclaimer. | |||
12 | * 2. Redistributions in binary form must reproduce the above copyright | |||
13 | * notice, this list of conditions and the following disclaimer in the | |||
14 | * documentation and/or other materials provided with the distribution. | |||
15 | * | |||
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND | |||
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |||
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |||
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE | |||
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |||
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |||
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |||
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT | |||
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY | |||
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF | |||
26 | * SUCH DAMAGE. | |||
27 | */ | |||
28 | ||||
29 | #include "bpfilter.h" | |||
30 | #include "vlan.h" | |||
31 | ||||
32 | #include <sys/param.h> | |||
33 | #include <sys/systm.h> | |||
34 | #include <sys/sockio.h> | |||
35 | #include <sys/rwlock.h> | |||
36 | #include <sys/mbuf.h> | |||
37 | #include <sys/kernel.h> | |||
38 | #include <sys/socket.h> | |||
39 | #include <sys/device.h> | |||
40 | ||||
41 | #include <machine/bus.h> | |||
42 | ||||
43 | #include <net/if.h> | |||
44 | #include <net/if_media.h> | |||
45 | ||||
46 | #if NBPFILTER1 > 0 | |||
47 | #include <net/bpf.h> | |||
48 | #endif | |||
49 | ||||
50 | #include <netinet/in.h> | |||
51 | #include <netinet/if_ether.h> | |||
52 | ||||
53 | #include <dev/mii/mii.h> | |||
54 | #include <dev/mii/miivar.h> | |||
55 | ||||
56 | #include <dev/usb/usb.h> | |||
57 | #include <dev/usb/usbdi.h> | |||
58 | #include <dev/usb/usbdi_util.h> | |||
59 | #include <dev/usb/usbdivar.h> | |||
60 | #include <dev/usb/usbdevs.h> | |||
61 | ||||
62 | #include <dev/ic/rtl81x9reg.h> | |||
63 | #include <dev/usb/if_urereg.h> | |||
64 | ||||
65 | #ifdef URE_DEBUG | |||
66 | #define DPRINTF(x) do { if (uredebug) printf x; } while (0) | |||
67 | #define DPRINTFN(n,x) do { if (uredebug >= (n)) printf x; } while (0) | |||
68 | int uredebug = 0; | |||
69 | #else | |||
70 | #define DPRINTF(x) | |||
71 | #define DPRINTFN(n,x) | |||
72 | #endif | |||
73 | ||||
74 | const struct usb_devno ure_devs[] = { | |||
75 | { USB_VENDOR_ASUS0x0b05, USB_PRODUCT_ASUS_RTL81560x18d1 }, | |||
76 | { USB_VENDOR_BELKIN0x050d, USB_PRODUCT_BELKIN_RTL8152B0x047a }, | |||
77 | { USB_VENDOR_BELKIN0x050d, USB_PRODUCT_BELKIN_RTL81530x048a }, | |||
78 | { USB_VENDOR_CISCOLINKSYS0x13b1, USB_PRODUCT_CISCOLINKSYS_USB3GIGV10x0041 }, | |||
79 | { USB_VENDOR_CLEVO0x30da, USB_PRODUCT_CLEVO_RTL8153B0x5101 }, | |||
80 | { USB_VENDOR_CLUB3D0x2d1c, USB_PRODUCT_CLUB3D_RTL81530x8153 }, | |||
81 | { USB_VENDOR_DLINK0x2001, USB_PRODUCT_DLINK_RTL8153_10x7e34 }, | |||
82 | { USB_VENDOR_DLINK0x2001, USB_PRODUCT_DLINK_RTL8153_20xa710 }, | |||
83 | { USB_VENDOR_DYNABOOK0x30f3, USB_PRODUCT_DYNABOOK_RTL8153B_10x0419 }, | |||
84 | { USB_VENDOR_DYNABOOK0x30f3, USB_PRODUCT_DYNABOOK_RTL8153B_20x0425 }, | |||
85 | { USB_VENDOR_ELECOM0x056e, USB_PRODUCT_ELECOM_RTL8153B0x4013 }, | |||
86 | { USB_VENDOR_ELECOM0x056e, USB_PRODUCT_ELECOM_RTL8156B0x4017 }, | |||
87 | { USB_VENDOR_IOI0x0f21, USB_PRODUCT_IOI_RTL81530x8153 }, | |||
88 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_DOCK_ETHERNET0x3062 }, | |||
89 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINK0x720a }, | |||
90 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINKPLUS0x3054 }, | |||
91 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINKPRO0x304f }, | |||
92 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_10x3069 }, | |||
93 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_20x3098 }, | |||
94 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_30x309b }, | |||
95 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_40x309c }, | |||
96 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_50x309d }, | |||
97 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_60x7214 }, | |||
98 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_70x721e }, | |||
99 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_80x8153 }, | |||
100 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_90xa359 }, | |||
101 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_10x7205 }, | |||
102 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_20x720b }, | |||
103 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_30x720c }, | |||
104 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TABLETDOCK0x3052 }, | |||
105 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3DOCK0xa3c1 }, | |||
106 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3DOCKGEN20x3082 }, | |||
107 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3GFXDOCK0x3065 }, | |||
108 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_USBCDOCKGEN20xa387 }, | |||
109 | { USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_WIGIGDOCK0x3057 }, | |||
110 | { USB_VENDOR_LG0x043e, USB_PRODUCT_LG_RTL81530x9819 }, | |||
111 | { USB_VENDOR_LG0x043e, USB_PRODUCT_LG_RTL8153B0x9820 }, | |||
112 | { USB_VENDOR_LUXSHARE0x208e, USB_PRODUCT_LUXSHARE_RTL81530xd003 }, | |||
113 | { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_DOCKETH0x07ab }, | |||
114 | { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_DOCKETH20x07c6 }, | |||
115 | { USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_SURFETH0x0927 }, | |||
116 | { USB_VENDOR_NVIDIA0x0955, USB_PRODUCT_NVIDIA_TEGRAETH0x09ff }, | |||
117 | { USB_VENDOR_PIONEERDJ0x2b73, USB_PRODUCT_PIONEERDJ_RTL8152B0x0007 }, | |||
118 | { USB_VENDOR_PIONEERDJ0x2b73, USB_PRODUCT_PIONEERDJ_RTL8153B0x0031 }, | |||
119 | { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81520x8152 }, | |||
120 | { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL8152B0x8050 }, | |||
121 | { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81530x8153 }, | |||
122 | { USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81560x8156 }, | |||
123 | { USB_VENDOR_SAMSUNG20x04e8, USB_PRODUCT_SAMSUNG2_RTL81530xa101 }, | |||
124 | { USB_VENDOR_TOSHIBA0x0930, USB_PRODUCT_TOSHIBA_RTL8153B0x0416 }, | |||
125 | { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_EU3000x0601 }, | |||
126 | { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL8152B_10x0602 }, | |||
127 | { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL8152B_20x0603 }, | |||
128 | { USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL81530x0604 }, | |||
129 | { USB_VENDOR_TRENDNET0x20f4, USB_PRODUCT_TRENDNET_RTL81560xe02b }, | |||
130 | { USB_VENDOR_TTL0x1025, USB_PRODUCT_TTL_RTL81530x104e }, | |||
131 | { USB_VENDOR_TWINHEAD0x14ff, USB_PRODUCT_TWINHEAD_RTL8153B0x1400 }, | |||
132 | { USB_VENDOR_XIAOMI0x2717, USB_PRODUCT_XIAOMI_RTL8152B0x0011 }, | |||
133 | }; | |||
134 | ||||
135 | int ure_match(struct device *, void *, void *); | |||
136 | void ure_attach(struct device *, struct device *, void *); | |||
137 | int ure_detach(struct device *, int); | |||
138 | ||||
139 | struct cfdriver ure_cd = { | |||
140 | NULL((void *)0), "ure", DV_IFNET | |||
141 | }; | |||
142 | ||||
143 | const struct cfattach ure_ca = { | |||
144 | sizeof(struct ure_softc), ure_match, ure_attach, ure_detach | |||
145 | }; | |||
146 | ||||
147 | int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, | |||
148 | void *, int); | |||
149 | int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, | |||
150 | int); | |||
151 | int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, | |||
152 | int); | |||
153 | uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); | |||
154 | uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); | |||
155 | uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); | |||
156 | int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); | |||
157 | int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); | |||
158 | int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); | |||
159 | uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); | |||
160 | void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); | |||
161 | ||||
162 | void ure_init(void *); | |||
163 | void ure_stop(struct ure_softc *); | |||
164 | void ure_start(struct ifnet *); | |||
165 | void ure_reset(struct ure_softc *); | |||
166 | void ure_watchdog(struct ifnet *); | |||
167 | ||||
168 | void ure_miibus_statchg(struct device *); | |||
169 | int ure_miibus_readreg(struct device *, int, int); | |||
170 | void ure_miibus_writereg(struct device *, int, int, int); | |||
171 | void ure_lock_mii(struct ure_softc *); | |||
172 | void ure_unlock_mii(struct ure_softc *); | |||
173 | ||||
174 | int ure_encap_txpkt(struct mbuf *, char *, uint32_t); | |||
175 | int ure_encap_xfer(struct ifnet *, struct ure_softc *, | |||
176 | struct ure_chain *); | |||
177 | void ure_rxeof(struct usbd_xfer *, void *, usbd_status); | |||
178 | void ure_txeof(struct usbd_xfer *, void *, usbd_status); | |||
179 | int ure_xfer_list_init(struct ure_softc *, struct ure_chain *, | |||
180 | uint32_t, int); | |||
181 | void ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int); | |||
182 | ||||
183 | void ure_tick_task(void *); | |||
184 | void ure_tick(void *); | |||
185 | ||||
186 | void ure_ifmedia_init(struct ifnet *); | |||
187 | int ure_ifmedia_upd(struct ifnet *); | |||
188 | void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); | |||
189 | void ure_add_media_types(struct ure_softc *); | |||
190 | void ure_link_state(struct ure_softc *); | |||
191 | int ure_get_link_status(struct ure_softc *); | |||
192 | void ure_iff(struct ure_softc *); | |||
193 | void ure_rxvlan(struct ure_softc *); | |||
194 | int ure_ioctl(struct ifnet *, u_long, caddr_t); | |||
195 | void ure_rtl8152_init(struct ure_softc *); | |||
196 | void ure_rtl8153_init(struct ure_softc *); | |||
197 | void ure_rtl8153b_init(struct ure_softc *); | |||
198 | void ure_rtl8152_nic_reset(struct ure_softc *); | |||
199 | void ure_rtl8153_nic_reset(struct ure_softc *); | |||
200 | void ure_rtl8153_phy_status(struct ure_softc *, int); | |||
201 | void ure_reset_bmu(struct ure_softc *); | |||
202 | void ure_disable_teredo(struct ure_softc *); | |||
203 | ||||
204 | #define URE_SETBIT_1(sc, reg, index, x)ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) \ | |||
205 | ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) | |||
206 | #define URE_SETBIT_2(sc, reg, index, x)ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) \ | |||
207 | ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) | |||
208 | #define URE_SETBIT_4(sc, reg, index, x)ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) \ | |||
209 | ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) | |||
210 | ||||
211 | #define URE_CLRBIT_1(sc, reg, index, x)ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~ (x)) \ | |||
212 | ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) | |||
213 | #define URE_CLRBIT_2(sc, reg, index, x)ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~ (x)) \ | |||
214 | ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) | |||
215 | #define URE_CLRBIT_4(sc, reg, index, x)ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~ (x)) \ | |||
216 | ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) | |||
217 | ||||
218 | int | |||
219 | ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, | |||
220 | void *buf, int len) | |||
221 | { | |||
222 | usb_device_request_t req; | |||
223 | usbd_status err; | |||
224 | ||||
225 | if (usbd_is_dying(sc->ure_udev)) | |||
226 | return 0; | |||
227 | ||||
228 | if (rw == URE_CTL_WRITE0x02) | |||
229 | req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00); | |||
230 | else | |||
231 | req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00); | |||
232 | req.bRequest = UR_SET_ADDRESS0x05; | |||
233 | USETW(req.wValue, val)(*(u_int16_t *)(req.wValue) = (val)); | |||
234 | USETW(req.wIndex, index)(*(u_int16_t *)(req.wIndex) = (index)); | |||
235 | USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len)); | |||
236 | ||||
237 | DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n", | |||
238 | rw, val, index, len)); | |||
239 | err = usbd_do_request(sc->ure_udev, &req, buf); | |||
240 | if (err) { | |||
241 | DPRINTF(("ure_ctl: error %d\n", err)); | |||
242 | return -1; | |||
243 | } | |||
244 | ||||
245 | return 0; | |||
246 | } | |||
247 | ||||
248 | int | |||
249 | ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, | |||
250 | void *buf, int len) | |||
251 | { | |||
252 | return (ure_ctl(sc, URE_CTL_READ0x01, addr, index, buf, len)); | |||
253 | } | |||
254 | ||||
255 | int | |||
256 | ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, | |||
257 | void *buf, int len) | |||
258 | { | |||
259 | return (ure_ctl(sc, URE_CTL_WRITE0x02, addr, index, buf, len)); | |||
260 | } | |||
261 | ||||
262 | uint8_t | |||
263 | ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) | |||
264 | { | |||
265 | uint32_t val; | |||
266 | uint8_t temp[4]; | |||
267 | uint8_t shift; | |||
268 | ||||
269 | shift = (reg & 3) << 3; | |||
270 | reg &= ~3; | |||
271 | ||||
272 | ure_read_mem(sc, reg, index, &temp, 4); | |||
273 | val = UGETDW(temp)(*(u_int32_t *)(temp)); | |||
274 | val >>= shift; | |||
275 | ||||
276 | return (val & 0xff); | |||
277 | } | |||
278 | ||||
279 | uint16_t | |||
280 | ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) | |||
281 | { | |||
282 | uint32_t val; | |||
283 | uint8_t temp[4]; | |||
284 | uint8_t shift; | |||
285 | ||||
286 | shift = (reg & 2) << 3; | |||
287 | reg &= ~3; | |||
288 | ||||
289 | ure_read_mem(sc, reg, index, &temp, 4); | |||
290 | val = UGETDW(temp)(*(u_int32_t *)(temp)); | |||
| ||||
291 | val >>= shift; | |||
292 | ||||
293 | return (val & 0xffff); | |||
294 | } | |||
295 | ||||
296 | uint32_t | |||
297 | ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) | |||
298 | { | |||
299 | uint8_t temp[4]; | |||
300 | ||||
301 | ure_read_mem(sc, reg, index, &temp, 4); | |||
302 | return (UGETDW(temp)(*(u_int32_t *)(temp))); | |||
303 | } | |||
304 | ||||
305 | int | |||
306 | ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) | |||
307 | { | |||
308 | uint16_t byen; | |||
309 | uint8_t temp[4]; | |||
310 | uint8_t shift; | |||
311 | ||||
312 | byen = URE_BYTE_EN_BYTE0x11; | |||
313 | shift = reg & 3; | |||
314 | val &= 0xff; | |||
315 | ||||
316 | if (reg & 3) { | |||
317 | byen <<= shift; | |||
318 | val <<= (shift << 3); | |||
319 | reg &= ~3; | |||
320 | } | |||
321 | ||||
322 | USETDW(temp, val)(*(u_int32_t *)(temp) = (val)); | |||
323 | return (ure_write_mem(sc, reg, index | byen, &temp, 4)); | |||
324 | } | |||
325 | ||||
326 | int | |||
327 | ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) | |||
328 | { | |||
329 | uint16_t byen; | |||
330 | uint8_t temp[4]; | |||
331 | uint8_t shift; | |||
332 | ||||
333 | byen = URE_BYTE_EN_WORD0x33; | |||
334 | shift = reg & 2; | |||
335 | val &= 0xffff; | |||
336 | ||||
337 | if (reg & 2) { | |||
338 | byen <<= shift; | |||
339 | val <<= (shift << 3); | |||
340 | reg &= ~3; | |||
341 | } | |||
342 | ||||
343 | USETDW(temp, val)(*(u_int32_t *)(temp) = (val)); | |||
344 | return (ure_write_mem(sc, reg, index | byen, &temp, 4)); | |||
345 | } | |||
346 | ||||
347 | int | |||
348 | ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) | |||
349 | { | |||
350 | uint8_t temp[4]; | |||
351 | ||||
352 | USETDW(temp, val)(*(u_int32_t *)(temp) = (val)); | |||
353 | return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD0xff, &temp, 4)); | |||
354 | } | |||
355 | ||||
356 | uint16_t | |||
357 | ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) | |||
358 | { | |||
359 | uint16_t reg; | |||
360 | ||||
361 | ure_write_2(sc, URE_PLA_OCP_GPHY_BASE0xe86c, URE_MCU_TYPE_PLA0x0100, addr & 0xf000); | |||
362 | reg = (addr & 0x0fff) | 0xb000; | |||
363 | ||||
364 | return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA0x0100)); | |||
365 | } | |||
366 | ||||
367 | void | |||
368 | ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) | |||
369 | { | |||
370 | uint16_t reg; | |||
371 | ||||
372 | ure_write_2(sc, URE_PLA_OCP_GPHY_BASE0xe86c, URE_MCU_TYPE_PLA0x0100, addr & 0xf000); | |||
373 | reg = (addr & 0x0fff) | 0xb000; | |||
374 | ||||
375 | ure_write_2(sc, reg, URE_MCU_TYPE_PLA0x0100, data); | |||
376 | } | |||
377 | ||||
378 | int | |||
379 | ure_miibus_readreg(struct device *dev, int phy, int reg) | |||
380 | { | |||
381 | struct ure_softc *sc = (void *)dev; | |||
382 | uint16_t val; | |||
383 | ||||
384 | if (usbd_is_dying(sc->ure_udev)) | |||
385 | return 0; | |||
386 | ||||
387 | /* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */ | |||
388 | if (reg == RL_GMEDIASTAT0x006C) | |||
389 | return ure_read_1(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100); | |||
390 | ||||
391 | ure_lock_mii(sc); | |||
392 | val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII0xa400 + reg * 2); | |||
393 | ure_unlock_mii(sc); | |||
394 | ||||
395 | return val; /* letoh16? */ | |||
396 | } | |||
397 | ||||
398 | void | |||
399 | ure_miibus_writereg(struct device *dev, int phy, int reg, int val) | |||
400 | { | |||
401 | struct ure_softc *sc = (void *)dev; | |||
402 | ||||
403 | ure_lock_mii(sc); | |||
404 | ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + reg * 2, val); /* htole16? */ | |||
405 | ure_unlock_mii(sc); | |||
406 | } | |||
407 | ||||
408 | void | |||
409 | ure_miibus_statchg(struct device *dev) | |||
410 | { | |||
411 | struct ure_softc *sc = (void *)dev; | |||
412 | struct mii_data *mii = &sc->ure_mii; | |||
413 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
414 | ||||
415 | if ((ifp->if_flags & IFF_RUNNING0x40) == 0) | |||
416 | return; | |||
417 | ||||
418 | sc->ure_flags &= ~URE_FLAG_LINK0x0001; | |||
419 | if ((mii->mii_media_status & (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) == | |||
420 | (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) { | |||
421 | switch (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL)) { | |||
422 | case IFM_10_T3: | |||
423 | case IFM_100_TX6: | |||
424 | sc->ure_flags |= URE_FLAG_LINK0x0001; | |||
425 | break; | |||
426 | case IFM_1000_T16: | |||
427 | if ((sc->ure_flags & URE_FLAG_81520x1000) != 0) | |||
428 | break; | |||
429 | sc->ure_flags |= URE_FLAG_LINK0x0001; | |||
430 | break; | |||
431 | default: | |||
432 | break; | |||
433 | } | |||
434 | } | |||
435 | ||||
436 | /* Lost link, do nothing. */ | |||
437 | if ((sc->ure_flags & URE_FLAG_LINK0x0001) == 0) | |||
438 | return; | |||
439 | ||||
440 | /* | |||
441 | * After a link change the media settings are getting reset on the | |||
442 | * hardware, and need to be re-initialized again for communication | |||
443 | * to continue work. | |||
444 | */ | |||
445 | ure_ifmedia_init(ifp); | |||
446 | } | |||
447 | ||||
448 | void | |||
449 | ure_ifmedia_init(struct ifnet *ifp) | |||
450 | { | |||
451 | struct ure_softc *sc = ifp->if_softc; | |||
452 | uint32_t reg = 0; | |||
453 | ||||
454 | /* Set MAC address. */ | |||
455 | ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_CONFIG0xc0); | |||
456 | ure_write_mem(sc, URE_PLA_IDR0xc000, URE_MCU_TYPE_PLA0x0100 | URE_BYTE_EN_SIX_BYTES0x3f, | |||
457 | sc->ure_ac.ac_enaddr, 8); | |||
458 | ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00); | |||
459 | ||||
460 | if (!(sc->ure_flags & URE_FLAG_81520x1000)) { | |||
461 | reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu)(ifp->if_data.ifi_mtu + ((6 * 2) + 2) + 4 + 4) - | |||
462 | sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN8; | |||
463 | if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000)) { | |||
464 | ure_write_2(sc, URE_USB_RX_EARLY_SIZE0xd42e, URE_MCU_TYPE_USB0x0000, | |||
465 | reg / 8); | |||
466 | ||||
467 | ure_write_2(sc, URE_USB_RX_EARLY_AGG0xd42c, URE_MCU_TYPE_USB0x0000, | |||
468 | (sc->ure_flags & URE_FLAG_8153B0x2000) ? 16 : 80); | |||
469 | ure_write_2(sc, URE_USB_PM_CTRL_STATUS0xd432, | |||
470 | URE_MCU_TYPE_USB0x0000, 1875); | |||
471 | } else { | |||
472 | ure_write_2(sc, URE_USB_RX_EARLY_SIZE0xd42e, URE_MCU_TYPE_USB0x0000, | |||
473 | reg / 4); | |||
474 | switch (sc->ure_udev->speed) { | |||
475 | case USB_SPEED_SUPER4: | |||
476 | reg = URE_COALESCE_SUPER85000U / 8; | |||
477 | break; | |||
478 | case USB_SPEED_HIGH3: | |||
479 | reg = URE_COALESCE_HIGH250000U / 8; | |||
480 | break; | |||
481 | default: | |||
482 | reg = URE_COALESCE_SLOW524280U / 8; | |||
483 | break; | |||
484 | } | |||
485 | ure_write_2(sc, URE_USB_RX_EARLY_AGG0xd42c, URE_MCU_TYPE_USB0x0000, | |||
486 | reg); | |||
487 | } | |||
488 | } | |||
489 | ||||
490 | /* Reset the packet filter. */ | |||
491 | URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN)ure_write_2(sc, 0xc0b4, 0x0100, ure_read_2(sc, 0xc0b4, 0x0100 ) & ~(0x0001)); | |||
492 | URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN)ure_write_2(sc, 0xc0b4, 0x0100, ure_read_2(sc, 0xc0b4, 0x0100 ) | (0x0001)); | |||
493 | ||||
494 | /* Enable transmit and receive. */ | |||
495 | URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100 ) | (0x08 | 0x04)); | |||
496 | ||||
497 | if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000)) { | |||
498 | ure_write_1(sc, URE_USB_UPT_RXDMA_OWN0xd437, URE_MCU_TYPE_USB0x0000, | |||
499 | URE_OWN_UPDATE0x01 | URE_OWN_CLEAR0x02); | |||
500 | } | |||
501 | ||||
502 | URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100 ) & ~(0x0008)); | |||
503 | } | |||
504 | ||||
505 | int | |||
506 | ure_ifmedia_upd(struct ifnet *ifp) | |||
507 | { | |||
508 | struct ure_softc *sc = ifp->if_softc; | |||
509 | struct mii_data *mii = &sc->ure_mii; | |||
510 | struct ifmedia *ifm = &sc->ure_ifmedia; | |||
511 | int anar, gig, err, reg; | |||
512 | ||||
513 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
514 | if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL) | |||
515 | return (EINVAL22); | |||
516 | ||||
517 | reg = ure_ocp_reg_read(sc, 0xa5d4); | |||
518 | reg &= ~URE_ADV_2500TFDX0x0080; | |||
519 | ||||
520 | anar = gig = 0; | |||
521 | switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) { | |||
522 | case IFM_AUTO0ULL: | |||
523 | anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
524 | gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
525 | reg |= URE_ADV_2500TFDX0x0080; | |||
526 | break; | |||
527 | case IFM_2500_T34: | |||
528 | anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
529 | gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
530 | reg |= URE_ADV_2500TFDX0x0080; | |||
531 | ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(2500)((((2500) * 1000ULL) * 1000ULL)); | |||
532 | break; | |||
533 | case IFM_1000_T16: | |||
534 | anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020; | |||
535 | gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100; | |||
536 | ifp->if_baudrateif_data.ifi_baudrate = IF_Gbps(1)((((((1) * 1000ULL) * 1000ULL) * 1000ULL))); | |||
537 | break; | |||
538 | case IFM_100_TX6: | |||
539 | anar |= ANAR_TX0x0080 | ANAR_TX_FD0x0100; | |||
540 | ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(100)((((100) * 1000ULL) * 1000ULL)); | |||
541 | break; | |||
542 | case IFM_10_T3: | |||
543 | anar |= ANAR_100x0020 | ANAR_10_FD0x0040; | |||
544 | ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(10)((((10) * 1000ULL) * 1000ULL)); | |||
545 | break; | |||
546 | default: | |||
547 | printf("%s: unsupported media type\n", | |||
548 | sc->ure_dev.dv_xname); | |||
549 | return (EINVAL22); | |||
550 | } | |||
551 | ||||
552 | ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_ANAR0x04 * 2, | |||
553 | anar | ANAR_PAUSE_ASYM(2 << 10) | ANAR_FC0x0400); | |||
554 | ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_100T2CR0x09 * 2, gig); | |||
555 | ure_ocp_reg_write(sc, 0xa5d4, reg); | |||
556 | ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_BMCR0x00, | |||
557 | BMCR_AUTOEN0x1000 | BMCR_STARTNEG0x0200); | |||
558 | ||||
559 | return (0); | |||
560 | } | |||
561 | ||||
562 | if (mii->mii_instance) { | |||
563 | struct mii_softc *miisc; | |||
564 | LIST_FOREACH(miisc, &mii->mii_phys, mii_list)for((miisc) = ((&mii->mii_phys)->lh_first); (miisc) != ((void *)0); (miisc) = ((miisc)->mii_list.le_next)) | |||
565 | PHY_RESET(miisc)(*(miisc)->mii_funcs->pf_reset)((miisc)); | |||
566 | } | |||
567 | ||||
568 | err = mii_mediachg(mii); | |||
569 | if (err == ENXIO6) | |||
570 | return (0); | |||
571 | else | |||
572 | return (err); | |||
573 | } | |||
574 | ||||
575 | void | |||
576 | ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) | |||
577 | { | |||
578 | struct ure_softc *sc = ifp->if_softc; | |||
579 | struct mii_data *mii = &sc->ure_mii; | |||
580 | uint16_t status = 0; | |||
581 | ||||
582 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
583 | ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL; | |||
584 | if (ure_get_link_status(sc)) { | |||
585 | ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL; | |||
586 | status = ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, | |||
587 | URE_MCU_TYPE_PLA0x0100); | |||
588 | if ((status & URE_PHYSTATUS_FDX0x0001) || | |||
589 | (status & URE_PHYSTATUS_2500MBPS0x0400)) | |||
590 | ifmr->ifm_active |= IFM_FDX0x0000010000000000ULL; | |||
591 | else | |||
592 | ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL; | |||
593 | if (status & URE_PHYSTATUS_10MBPS0x0004) | |||
594 | ifmr->ifm_active |= IFM_10_T3; | |||
595 | else if (status & URE_PHYSTATUS_100MBPS0x0008) | |||
596 | ifmr->ifm_active |= IFM_100_TX6; | |||
597 | else if (status & URE_PHYSTATUS_1000MBPS0x0010) | |||
598 | ifmr->ifm_active |= IFM_1000_T16; | |||
599 | else if (status & URE_PHYSTATUS_2500MBPS0x0400) | |||
600 | ifmr->ifm_active |= IFM_2500_T34; | |||
601 | } | |||
602 | return; | |||
603 | } | |||
604 | ||||
605 | mii_pollstat(mii); | |||
606 | ifmr->ifm_active = mii->mii_media_active; | |||
607 | ifmr->ifm_status = mii->mii_media_status; | |||
608 | } | |||
609 | ||||
610 | void | |||
611 | ure_add_media_types(struct ure_softc *sc) | |||
612 | { | |||
613 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_10_T3, 0, NULL((void *)0)); | |||
614 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0)); | |||
615 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, 0, NULL((void *)0)); | |||
616 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 0, | |||
617 | NULL((void *)0)); | |||
618 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16, 0, NULL((void *)0)); | |||
619 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 0, | |||
620 | NULL((void *)0)); | |||
621 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34, 0, NULL((void *)0)); | |||
622 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34 | IFM_FDX0x0000010000000000ULL, 0, | |||
623 | NULL((void *)0)); | |||
624 | } | |||
625 | ||||
626 | void | |||
627 | ure_link_state(struct ure_softc *sc) | |||
628 | { | |||
629 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
630 | int link = LINK_STATE_DOWN2; | |||
631 | ||||
632 | if (ure_get_link_status(sc)) | |||
633 | link = LINK_STATE_UP4; | |||
634 | ||||
635 | if (ifp->if_link_stateif_data.ifi_link_state != link) { | |||
636 | ifp->if_link_stateif_data.ifi_link_state = link; | |||
637 | if_link_state_change(ifp); | |||
638 | } | |||
639 | } | |||
640 | ||||
641 | int | |||
642 | ure_get_link_status(struct ure_softc *sc) | |||
643 | { | |||
644 | if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) & | |||
645 | URE_PHYSTATUS_LINK0x0002) { | |||
646 | sc->ure_flags |= URE_FLAG_LINK0x0001; | |||
647 | return (1); | |||
648 | } else { | |||
649 | sc->ure_flags &= ~URE_FLAG_LINK0x0001; | |||
650 | return (0); | |||
651 | } | |||
652 | } | |||
653 | ||||
654 | void | |||
655 | ure_iff(struct ure_softc *sc) | |||
656 | { | |||
657 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
658 | struct ether_multi *enm; | |||
659 | struct ether_multistep step; | |||
660 | uint32_t hashes[2] = { 0, 0 }; | |||
661 | uint32_t hash; | |||
662 | uint32_t rxmode; | |||
663 | ||||
664 | if (usbd_is_dying(sc->ure_udev)) | |||
665 | return; | |||
666 | ||||
667 | rxmode = ure_read_4(sc, URE_PLA_RCR0xc010, URE_MCU_TYPE_PLA0x0100); | |||
668 | rxmode &= ~URE_RCR_ACPT_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008); | |||
669 | ifp->if_flags &= ~IFF_ALLMULTI0x200; | |||
670 | ||||
671 | /* | |||
672 | * Always accept frames destined to our station address. | |||
673 | * Always accept broadcast frames. | |||
674 | */ | |||
675 | rxmode |= URE_RCR_APM0x00000002 | URE_RCR_AB0x00000008; | |||
676 | ||||
677 | if (ifp->if_flags & IFF_PROMISC0x100 || sc->ure_ac.ac_multirangecnt > 0) { | |||
678 | ifp->if_flags |= IFF_ALLMULTI0x200; | |||
679 | rxmode |= URE_RCR_AM0x00000004; | |||
680 | if (ifp->if_flags & IFF_PROMISC0x100) | |||
681 | rxmode |= URE_RCR_AAP0x00000001; | |||
682 | hashes[0] = hashes[1] = 0xffffffff; | |||
683 | } else { | |||
684 | rxmode |= URE_RCR_AM0x00000004; | |||
685 | ||||
686 | ETHER_FIRST_MULTI(step, &sc->ure_ac, enm)do { (step).e_enm = ((&(&sc->ure_ac)->ac_multiaddrs )->lh_first); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while ( 0); | |||
687 | while (enm != NULL((void *)0)) { | |||
688 | hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN6) | |||
689 | >> 26; | |||
690 | if (hash < 32) | |||
691 | hashes[0] |= (1 << hash); | |||
692 | else | |||
693 | hashes[1] |= (1 << (hash - 32)); | |||
694 | ||||
695 | ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm = (((enm))->enm_list.le_next); } while ( 0); | |||
696 | } | |||
697 | ||||
698 | hash = swap32(hashes[0])(__uint32_t)(__builtin_constant_p(hashes[0]) ? (__uint32_t)(( (__uint32_t)(hashes[0]) & 0xff) << 24 | ((__uint32_t )(hashes[0]) & 0xff00) << 8 | ((__uint32_t)(hashes[ 0]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[0]) & 0xff000000) >> 24) : __swap32md(hashes[0])); | |||
699 | hashes[0] = swap32(hashes[1])(__uint32_t)(__builtin_constant_p(hashes[1]) ? (__uint32_t)(( (__uint32_t)(hashes[1]) & 0xff) << 24 | ((__uint32_t )(hashes[1]) & 0xff00) << 8 | ((__uint32_t)(hashes[ 1]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[1]) & 0xff000000) >> 24) : __swap32md(hashes[1])); | |||
700 | hashes[1] = hash; | |||
701 | } | |||
702 | ||||
703 | ure_write_mem(sc, URE_PLA_MAR0xcd00, URE_MCU_TYPE_PLA0x0100 | URE_BYTE_EN_DWORD0xff, | |||
704 | hashes, sizeof(hashes)); | |||
705 | ure_write_4(sc, URE_PLA_RCR0xc010, URE_MCU_TYPE_PLA0x0100, rxmode); | |||
706 | } | |||
707 | ||||
708 | void | |||
709 | ure_rxvlan(struct ure_softc *sc) | |||
710 | { | |||
711 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
712 | uint16_t reg; | |||
713 | ||||
714 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
715 | reg = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA0x0100); | |||
716 | reg &= ~0x00c0; | |||
717 | if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020) | |||
718 | reg |= 0x00c0; | |||
719 | ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA0x0100, reg); | |||
720 | } else { | |||
721 | reg = ure_read_2(sc, URE_PLA_CPCR0xe854, URE_MCU_TYPE_PLA0x0100); | |||
722 | reg &= ~URE_CPCR_RX_VLAN0x0040; | |||
723 | if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020) | |||
724 | reg |= URE_CPCR_RX_VLAN0x0040; | |||
725 | ure_write_2(sc, URE_PLA_CPCR0xe854, URE_MCU_TYPE_PLA0x0100, reg); | |||
726 | } | |||
727 | } | |||
728 | ||||
729 | void | |||
730 | ure_reset(struct ure_softc *sc) | |||
731 | { | |||
732 | int i; | |||
733 | ||||
734 | ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, URE_CR_RST0x10); | |||
735 | ||||
736 | for (i = 0; i < URE_TIMEOUT1000; i++) { | |||
737 | if (!(ure_read_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100) & | |||
738 | URE_CR_RST0x10)) | |||
739 | break; | |||
740 | DELAY(100)(*delay_func)(100); | |||
741 | } | |||
742 | if (i == URE_TIMEOUT1000) | |||
743 | printf("%s: reset never completed\n", sc->ure_dev.dv_xname); | |||
744 | } | |||
745 | ||||
746 | void | |||
747 | ure_watchdog(struct ifnet *ifp) | |||
748 | { | |||
749 | struct ure_softc *sc = ifp->if_softc; | |||
750 | struct ure_chain *c; | |||
751 | usbd_status err; | |||
752 | int i, s; | |||
753 | ||||
754 | ifp->if_timer = 0; | |||
755 | ||||
756 | if (usbd_is_dying(sc->ure_udev)) | |||
757 | return; | |||
758 | ||||
759 | if ((ifp->if_flags & (IFF_RUNNING0x40|IFF_UP0x1)) != (IFF_RUNNING0x40|IFF_UP0x1)) | |||
760 | return; | |||
761 | ||||
762 | sc = ifp->if_softc; | |||
763 | s = splnet()splraise(0x7); | |||
764 | ||||
765 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
766 | DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname)); | |||
767 | ||||
768 | for (i = 0; i < URE_TX_LIST_CNT1; i++) { | |||
769 | c = &sc->ure_cdata.ure_tx_chain[i]; | |||
770 | if (c->uc_cnt > 0) { | |||
771 | usbd_get_xfer_status(c->uc_xfer, NULL((void *)0), NULL((void *)0), NULL((void *)0), | |||
772 | &err); | |||
773 | ure_txeof(c->uc_xfer, c, err); | |||
774 | } | |||
775 | } | |||
776 | ||||
777 | if (ifq_is_oactive(&ifp->if_snd)) | |||
778 | ifq_restart(&ifp->if_snd); | |||
779 | splx(s)spllower(s); | |||
780 | } | |||
781 | ||||
782 | void | |||
783 | ure_init(void *xsc) | |||
784 | { | |||
785 | struct ure_softc *sc = xsc; | |||
786 | struct ure_chain *c; | |||
787 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
788 | usbd_status err; | |||
789 | int s, i; | |||
790 | ||||
791 | s = splnet()splraise(0x7); | |||
792 | ||||
793 | /* Cancel pending I/O. */ | |||
794 | ure_stop(sc); | |||
795 | ||||
796 | if (sc->ure_flags & URE_FLAG_81520x1000) | |||
797 | ure_rtl8152_nic_reset(sc); | |||
798 | else | |||
799 | ure_rtl8153_nic_reset(sc); | |||
800 | ||||
801 | if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain, | |||
802 | sc->ure_rxbufsz, URE_RX_LIST_CNT1) == ENOBUFS55) { | |||
803 | printf("%s: rx list init failed\n", sc->ure_dev.dv_xname); | |||
804 | splx(s)spllower(s); | |||
805 | return; | |||
806 | } | |||
807 | ||||
808 | if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain, | |||
809 | sc->ure_txbufsz, URE_TX_LIST_CNT1) == ENOBUFS55) { | |||
810 | printf("%s: tx list init failed\n", sc->ure_dev.dv_xname); | |||
811 | splx(s)spllower(s); | |||
812 | return; | |||
813 | } | |||
814 | ||||
815 | /* Initialize the SLIST we are using for the multiple tx buffers */ | |||
816 | SLIST_INIT(&sc->ure_cdata.ure_tx_free){ ((&sc->ure_cdata.ure_tx_free)->slh_first) = ((void *)0); }; | |||
817 | for (i = 0; i < URE_TX_LIST_CNT1; i++) | |||
818 | SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free,do { (&sc->ure_cdata.ure_tx_chain[i])->uc_list.sle_next = (&sc->ure_cdata.ure_tx_free)->slh_first; (&sc ->ure_cdata.ure_tx_free)->slh_first = (&sc->ure_cdata .ure_tx_chain[i]); } while (0) | |||
819 | &sc->ure_cdata.ure_tx_chain[i], uc_list)do { (&sc->ure_cdata.ure_tx_chain[i])->uc_list.sle_next = (&sc->ure_cdata.ure_tx_free)->slh_first; (&sc ->ure_cdata.ure_tx_free)->slh_first = (&sc->ure_cdata .ure_tx_chain[i]); } while (0); | |||
820 | ||||
821 | /* Setup MAC address, and enable TX/RX. */ | |||
822 | ure_ifmedia_init(ifp); | |||
823 | ||||
824 | /* Load the multicast filter. */ | |||
825 | ure_iff(sc); | |||
826 | ||||
827 | /* Open RX and TX pipes. */ | |||
828 | err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX0], | |||
829 | USBD_EXCLUSIVE_USE0x01, &sc->ure_ep[URE_ENDPT_RX0]); | |||
830 | if (err) { | |||
831 | printf("%s: open rx pipe failed: %s\n", | |||
832 | sc->ure_dev.dv_xname, usbd_errstr(err)); | |||
833 | splx(s)spllower(s); | |||
834 | return; | |||
835 | } | |||
836 | ||||
837 | err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX1], | |||
838 | USBD_EXCLUSIVE_USE0x01, &sc->ure_ep[URE_ENDPT_TX1]); | |||
839 | if (err) { | |||
840 | printf("%s: open tx pipe failed: %s\n", | |||
841 | sc->ure_dev.dv_xname, usbd_errstr(err)); | |||
842 | splx(s)spllower(s); | |||
843 | return; | |||
844 | } | |||
845 | ||||
846 | /* Start up the receive pipe. */ | |||
847 | for (i = 0; i < URE_RX_LIST_CNT1; i++) { | |||
848 | c = &sc->ure_cdata.ure_rx_chain[i]; | |||
849 | usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX0], | |||
850 | c, c->uc_buf, c->uc_bufmax, | |||
851 | USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01, | |||
852 | USBD_NO_TIMEOUT0, ure_rxeof); | |||
853 | usbd_transfer(c->uc_xfer); | |||
854 | } | |||
855 | ||||
856 | ure_ifmedia_upd(ifp); | |||
857 | ||||
858 | /* Indicate we are up and running. */ | |||
859 | sc->ure_flags &= ~URE_FLAG_LINK0x0001; | |||
860 | ifp->if_flags |= IFF_RUNNING0x40; | |||
861 | ifq_clr_oactive(&ifp->if_snd); | |||
862 | ||||
863 | timeout_add_sec(&sc->ure_stat_ch, 1); | |||
864 | ||||
865 | splx(s)spllower(s); | |||
866 | } | |||
867 | ||||
868 | void | |||
869 | ure_start(struct ifnet *ifp) | |||
870 | { | |||
871 | struct ure_softc *sc = ifp->if_softc; | |||
872 | struct ure_cdata *cd = &sc->ure_cdata; | |||
873 | struct ure_chain *c; | |||
874 | struct mbuf *m = NULL((void *)0); | |||
875 | uint32_t new_buflen; | |||
876 | int s, mlen; | |||
877 | ||||
878 | if (!(sc->ure_flags & URE_FLAG_LINK0x0001) || | |||
879 | (ifp->if_flags & (IFF_RUNNING0x40|IFF_UP0x1)) != | |||
880 | (IFF_RUNNING0x40|IFF_UP0x1)) { | |||
881 | return; | |||
882 | } | |||
883 | ||||
884 | s = splnet()splraise(0x7); | |||
885 | ||||
886 | c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first); | |||
887 | while (c != NULL((void *)0)) { | |||
888 | m = ifq_deq_begin(&ifp->if_snd); | |||
889 | if (m == NULL((void *)0)) | |||
890 | break; | |||
891 | ||||
892 | mlen = m->m_pkthdrM_dat.MH.MH_pkthdr.len; | |||
893 | ||||
894 | /* Discard packet larger than buffer. */ | |||
895 | if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) { | |||
896 | ifq_deq_commit(&ifp->if_snd, m); | |||
897 | m_freem(m); | |||
898 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
899 | continue; | |||
900 | } | |||
901 | ||||
902 | /* | |||
903 | * If packet larger than remaining space, send buffer and | |||
904 | * continue. | |||
905 | */ | |||
906 | new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN)((((c->uc_buflen)+((4)-1))/(4))*(4)); | |||
907 | if (new_buflen + sizeof(struct ure_txpkt) + mlen >= | |||
908 | c->uc_bufmax) { | |||
909 | ifq_deq_rollback(&ifp->if_snd, m); | |||
910 | SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list)do { (&cd->ure_tx_free)->slh_first = (&cd->ure_tx_free )->slh_first->uc_list.sle_next; } while (0); | |||
911 | if (ure_encap_xfer(ifp, sc, c)) { | |||
912 | SLIST_INSERT_HEAD(&cd->ure_tx_free, c,do { (c)->uc_list.sle_next = (&cd->ure_tx_free)-> slh_first; (&cd->ure_tx_free)->slh_first = (c); } while (0) | |||
913 | uc_list)do { (c)->uc_list.sle_next = (&cd->ure_tx_free)-> slh_first; (&cd->ure_tx_free)->slh_first = (c); } while (0); | |||
914 | break; | |||
915 | } | |||
916 | c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first); | |||
917 | continue; | |||
918 | } | |||
919 | ||||
920 | /* Append packet to current buffer. */ | |||
921 | mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen, | |||
922 | c->uc_bufmax - new_buflen); | |||
923 | if (mlen <= 0) { | |||
924 | ifq_deq_rollback(&ifp->if_snd, m); | |||
925 | break; | |||
926 | } | |||
927 | ||||
928 | ifq_deq_commit(&ifp->if_snd, m); | |||
929 | c->uc_cnt += 1; | |||
930 | c->uc_buflen = new_buflen + mlen; | |||
931 | ||||
932 | #if NBPFILTER1 > 0 | |||
933 | if (ifp->if_bpf) | |||
934 | bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1)); | |||
935 | #endif | |||
936 | ||||
937 | m_freem(m); | |||
938 | } | |||
939 | ||||
940 | if (c != NULL((void *)0)) { | |||
941 | /* Send current buffer unless empty */ | |||
942 | if (c->uc_buflen > 0 && c->uc_cnt > 0) { | |||
943 | SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list)do { (&cd->ure_tx_free)->slh_first = (&cd->ure_tx_free )->slh_first->uc_list.sle_next; } while (0); | |||
944 | if (ure_encap_xfer(ifp, sc, c)) { | |||
945 | SLIST_INSERT_HEAD(&cd->ure_tx_free, c,do { (c)->uc_list.sle_next = (&cd->ure_tx_free)-> slh_first; (&cd->ure_tx_free)->slh_first = (c); } while (0) | |||
946 | uc_list)do { (c)->uc_list.sle_next = (&cd->ure_tx_free)-> slh_first; (&cd->ure_tx_free)->slh_first = (c); } while (0); | |||
947 | } | |||
948 | c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first); | |||
949 | } | |||
950 | } | |||
951 | ||||
952 | ifp->if_timer = 5; | |||
953 | if (c == NULL((void *)0)) | |||
954 | ifq_set_oactive(&ifp->if_snd); | |||
955 | splx(s)spllower(s); | |||
956 | } | |||
957 | ||||
958 | void | |||
959 | ure_tick(void *xsc) | |||
960 | { | |||
961 | struct ure_softc *sc = xsc; | |||
962 | ||||
963 | if (sc == NULL((void *)0)) | |||
964 | return; | |||
965 | ||||
966 | if (usbd_is_dying(sc->ure_udev)) | |||
967 | return; | |||
968 | ||||
969 | usb_add_task(sc->ure_udev, &sc->ure_tick_task); | |||
970 | } | |||
971 | ||||
972 | void | |||
973 | ure_stop(struct ure_softc *sc) | |||
974 | { | |||
975 | struct ure_cdata *cd; | |||
976 | struct ifnet *ifp; | |||
977 | usbd_status err; | |||
978 | ||||
979 | ure_reset(sc); | |||
980 | ||||
981 | ifp = &sc->ure_ac.ac_if; | |||
982 | ifp->if_timer = 0; | |||
983 | ifp->if_flags &= ~IFF_RUNNING0x40; | |||
984 | ifq_clr_oactive(&ifp->if_snd); | |||
985 | ||||
986 | timeout_del(&sc->ure_stat_ch); | |||
987 | sc->ure_flags &= ~URE_FLAG_LINK0x0001; | |||
988 | ||||
989 | if (sc->ure_ep[URE_ENDPT_RX0] != NULL((void *)0)) { | |||
990 | err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX0]); | |||
991 | if (err) { | |||
992 | printf("%s: close rx pipe failed: %s\n", | |||
993 | sc->ure_dev.dv_xname, usbd_errstr(err)); | |||
994 | } | |||
995 | sc->ure_ep[URE_ENDPT_RX0] = NULL((void *)0); | |||
996 | } | |||
997 | ||||
998 | if (sc->ure_ep[URE_ENDPT_TX1] != NULL((void *)0)) { | |||
999 | err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX1]); | |||
1000 | if (err) { | |||
1001 | printf("%s: close tx pipe failed: %s\n", | |||
1002 | sc->ure_dev.dv_xname, usbd_errstr(err)); | |||
1003 | } | |||
1004 | sc->ure_ep[URE_ENDPT_TX1] = NULL((void *)0); | |||
1005 | } | |||
1006 | ||||
1007 | cd = &sc->ure_cdata; | |||
1008 | ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT1); | |||
1009 | ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT1); | |||
1010 | } | |||
1011 | ||||
1012 | int | |||
1013 | ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch, | |||
1014 | uint32_t bufsize, int listlen) | |||
1015 | { | |||
1016 | struct ure_chain *c; | |||
1017 | int i; | |||
1018 | ||||
1019 | for (i = 0; i < listlen; i++) { | |||
1020 | c = &ch[i]; | |||
1021 | c->uc_sc = sc; | |||
1022 | c->uc_idx = i; | |||
1023 | c->uc_buflen = 0; | |||
1024 | c->uc_bufmax = bufsize; | |||
1025 | c->uc_cnt = 0; | |||
1026 | if (c->uc_xfer == NULL((void *)0)) { | |||
1027 | c->uc_xfer = usbd_alloc_xfer(sc->ure_udev); | |||
1028 | if (c->uc_xfer == NULL((void *)0)) | |||
1029 | return (ENOBUFS55); | |||
1030 | c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax); | |||
1031 | if (c->uc_buf == NULL((void *)0)) { | |||
1032 | usbd_free_xfer(c->uc_xfer); | |||
1033 | c->uc_xfer = NULL((void *)0); | |||
1034 | return (ENOBUFS55); | |||
1035 | } | |||
1036 | } | |||
1037 | } | |||
1038 | ||||
1039 | return (0); | |||
1040 | } | |||
1041 | ||||
1042 | void | |||
1043 | ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen) | |||
1044 | { | |||
1045 | int i; | |||
1046 | ||||
1047 | for (i = 0; i < listlen; i++) { | |||
1048 | if (ch[i].uc_buf != NULL((void *)0)) { | |||
1049 | ch[i].uc_buf = NULL((void *)0); | |||
1050 | } | |||
1051 | ch[i].uc_cnt = 0; | |||
1052 | if (ch[i].uc_xfer != NULL((void *)0)) { | |||
1053 | usbd_free_xfer(ch[i].uc_xfer); | |||
1054 | ch[i].uc_xfer = NULL((void *)0); | |||
1055 | } | |||
1056 | } | |||
1057 | } | |||
1058 | ||||
1059 | void | |||
1060 | ure_rtl8152_init(struct ure_softc *sc) | |||
1061 | { | |||
1062 | uint32_t pwrctrl; | |||
1063 | ||||
1064 | /* Disable ALDPS. */ | |||
1065 | ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, URE_ENPDNPS0x0200 | URE_LINKENA0x0100 | | |||
1066 | URE_DIS_SDSAVE0x0010); | |||
1067 | usbd_delay_ms(sc->ure_udev, 20); | |||
1068 | ||||
1069 | if (sc->ure_chip & URE_CHIP_VER_4C000x01) | |||
1070 | URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100 ) & ~(0x0700)) | |||
1071 | URE_LED_MODE_MASK)ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100 ) & ~(0x0700)); | |||
1072 | ||||
1073 | URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT)ure_write_2(sc, 0xd800, 0x0000, ure_read_2(sc, 0xd800, 0x0000 ) & ~(0x0100)); | |||
1074 | URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd432, 0x0000, ure_read_2(sc, 0xd432, 0x0000 ) & ~(0x0001)) | |||
1075 | URE_RESUME_INDICATE)ure_write_2(sc, 0xd432, 0x0000, ure_read_2(sc, 0xd432, 0x0000 ) & ~(0x0001)); | |||
1076 | ||||
1077 | URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe84c, 0x0100, ure_read_2(sc, 0xe84c, 0x0100 ) | (0x0080 | 0x0040)) | |||
1078 | URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH)ure_write_2(sc, 0xe84c, 0x0100, ure_read_2(sc, 0xe84c, 0x0100 ) | (0x0080 | 0x0040)); | |||
1079 | pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100); | |||
1080 | pwrctrl &= ~URE_MCU_CLK_RATIO_MASK0x0f0f0f0f; | |||
1081 | pwrctrl |= URE_MCU_CLK_RATIO0x07010f07 | URE_D3_CLK_GATED_EN0x00004000; | |||
1082 | ure_write_4(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, pwrctrl); | |||
1083 | ure_write_2(sc, URE_PLA_GPHY_INTR_IMR0xe022, URE_MCU_TYPE_PLA0x0100, | |||
1084 | URE_GPHY_STS_MSK0x0001 | URE_SPEED_DOWN_MSK0x0002 | URE_SPDWN_RXDV_MSK0x0004 | | |||
1085 | URE_SPDWN_LINKCHG_MSK0x0008); | |||
1086 | ||||
1087 | URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100 ) | (0x0001)); | |||
1088 | ||||
1089 | /* Enable Rx aggregation. */ | |||
1090 | URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000 ) & ~(0x0010 | 0x0080)) | |||
1091 | URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000 ) & ~(0x0010 | 0x0080)); | |||
1092 | } | |||
1093 | ||||
1094 | void | |||
1095 | ure_rtl8153_init(struct ure_softc *sc) | |||
1096 | { | |||
1097 | uint16_t reg; | |||
1098 | uint8_t u1u2[8]; | |||
1099 | int i; | |||
1100 | ||||
1101 | memset(u1u2, 0x00, sizeof(u1u2))__builtin_memset((u1u2), (0x00), (sizeof(u1u2))); | |||
1102 | ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, u1u2, | |||
1103 | sizeof(u1u2)); | |||
1104 | ||||
1105 | for (i = 0; i < 500; i++) { | |||
1106 | if (ure_read_2(sc, URE_PLA_BOOT_CTRL0xe004, URE_MCU_TYPE_PLA0x0100) & | |||
1107 | URE_AUTOLOAD_DONE0x0002) | |||
1108 | break; | |||
1109 | usbd_delay_ms(sc->ure_udev, 20); | |||
1110 | } | |||
1111 | if (i == 500) | |||
1112 | printf("%s: timeout waiting for chip autoload\n", | |||
1113 | sc->ure_dev.dv_xname); | |||
1114 | ||||
1115 | ure_rtl8153_phy_status(sc, 0); | |||
1116 | ||||
1117 | if (sc->ure_chip & (URE_CHIP_VER_5C000x04 | URE_CHIP_VER_5C100x08 | | |||
1118 | URE_CHIP_VER_5C200x10)) { | |||
1119 | ure_ocp_reg_write(sc, URE_OCP_ADC_CFG0xbc06, | |||
1120 | URE_CKADSEL_L0x0100 | URE_ADC_EN0x0080 | URE_EN_EMI_L0x0040); | |||
1121 | } | |||
1122 | ||||
1123 | ure_rtl8153_phy_status(sc, 1); | |||
1124 | ||||
1125 | URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000 ) & ~(0x0001)); | |||
1126 | ||||
1127 | if (sc->ure_chip & URE_CHIP_VER_5C100x08) { | |||
1128 | reg = ure_read_2(sc, URE_USB_SSPHYLINK20xb428, URE_MCU_TYPE_USB0x0000); | |||
1129 | reg &= ~URE_PWD_DN_SCALE_MASK0x3ffe; | |||
1130 | reg |= URE_PWD_DN_SCALE(96)((96) << 1); | |||
1131 | ure_write_2(sc, URE_USB_SSPHYLINK20xb428, URE_MCU_TYPE_USB0x0000, reg); | |||
1132 | ||||
1133 | URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb41e, 0x0000, ure_read_1(sc, 0xb41e, 0x0000 ) | (0x0002 | 0x0001)) | |||
1134 | URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND)ure_write_1(sc, 0xb41e, 0x0000, ure_read_1(sc, 0xb41e, 0x0000 ) | (0x0002 | 0x0001)); | |||
1135 | } else if (sc->ure_chip & URE_CHIP_VER_5C200x10) { | |||
1136 | URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xc0b0, 0x0100, ure_read_1(sc, 0xc0b0, 0x0100 ) & ~(0x0002)) | |||
1137 | URE_ECM_ALDPS)ure_write_1(sc, 0xc0b0, 0x0100, ure_read_1(sc, 0xc0b0, 0x0100 ) & ~(0x0002)); | |||
1138 | } | |||
1139 | if (sc->ure_chip & (URE_CHIP_VER_5C200x10 | URE_CHIP_VER_5C300x20)) { | |||
1140 | if (ure_read_2(sc, URE_USB_BURST_SIZE0xcfc0, URE_MCU_TYPE_USB0x0000)) | |||
1141 | URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000 ) | (0x0001)) | |||
1142 | URE_DYNAMIC_BURST)ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000 ) | (0x0001)); | |||
1143 | else | |||
1144 | URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000 ) & ~(0x0001)) | |||
1145 | URE_DYNAMIC_BURST)ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000 ) & ~(0x0001)); | |||
1146 | } | |||
1147 | ||||
1148 | URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC)ure_write_1(sc, 0xb466, 0x0000, ure_read_1(sc, 0xb466, 0x0000 ) | (0x0001)); | |||
1149 | ||||
1150 | URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN)ure_write_2(sc, 0xe43c, 0x0000, ure_read_2(sc, 0xe43c, 0x0000 ) & ~(0x0001)); | |||
1151 | ||||
1152 | URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100 ) & ~(0x0700)) | |||
1153 | URE_LED_MODE_MASK)ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100 ) & ~(0x0700)); | |||
1154 | ||||
1155 | if ((sc->ure_chip & URE_CHIP_VER_5C100x08) && | |||
1156 | sc->ure_udev->speed != USB_SPEED_SUPER4) | |||
1157 | reg = URE_LPM_TIMER_500MS0x04; | |||
1158 | else | |||
1159 | reg = URE_LPM_TIMER_500US0x0c; | |||
1160 | ure_write_1(sc, URE_USB_LPM_CTRL0xd41a, URE_MCU_TYPE_USB0x0000, | |||
1161 | URE_FIFO_EMPTY_1FB0x30 | URE_ROK_EXIT_LPM0x02 | reg); | |||
1162 | ||||
1163 | reg = ure_read_2(sc, URE_USB_AFE_CTRL20xd824, URE_MCU_TYPE_USB0x0000); | |||
1164 | reg &= ~URE_SEN_VAL_MASK0xf800; | |||
1165 | reg |= URE_SEN_VAL_NORMAL0xa000 | URE_SEL_RXIDLE0x0100; | |||
1166 | ure_write_2(sc, URE_USB_AFE_CTRL20xd824, URE_MCU_TYPE_USB0x0000, reg); | |||
1167 | ||||
1168 | ure_write_2(sc, URE_USB_CONNECT_TIMER0xcbf8, URE_MCU_TYPE_USB0x0000, 0x0001); | |||
1169 | ||||
1170 | URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000 ) & ~(0x0001 | 0x0008)) | |||
1171 | URE_PWR_EN | URE_PHASE2_EN)ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000 ) & ~(0x0001 | 0x0008)); | |||
1172 | URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000 ) & ~(0x0001)); | |||
1173 | ||||
1174 | memset(u1u2, 0xff, sizeof(u1u2))__builtin_memset((u1u2), (0xff), (sizeof(u1u2))); | |||
1175 | ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, u1u2, | |||
1176 | sizeof(u1u2)); | |||
1177 | ||||
1178 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0); | |||
1179 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, 0); | |||
1180 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL30xe0cc, URE_MCU_TYPE_PLA0x0100, 0); | |||
1181 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL40xe0ce, URE_MCU_TYPE_PLA0x0100, 0); | |||
1182 | ||||
1183 | /* Enable Rx aggregation. */ | |||
1184 | URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000 ) & ~(0x0010 | 0x0080)) | |||
1185 | URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000 ) & ~(0x0010 | 0x0080)); | |||
1186 | ||||
1187 | URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100 ) | (0x0001)); | |||
1188 | } | |||
1189 | ||||
1190 | void | |||
1191 | ure_rtl8153b_init(struct ure_softc *sc) | |||
1192 | { | |||
1193 | uint16_t reg; | |||
1194 | int i; | |||
1195 | ||||
1196 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
1197 | URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01)ure_write_1(sc, 0xd26b, 0x0000, ure_read_1(sc, 0xd26b, 0x0000 ) & ~(0x01)); | |||
1198 | ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB0x0000, 0); | |||
1199 | URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020)ure_write_2(sc, 0xcfee, 0x0000, ure_read_2(sc, 0xcfee, 0x0000 ) | (0x0020)); | |||
1200 | } | |||
1201 | ||||
1202 | URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000 ) & ~(0x0001)); | |||
1203 | ||||
1204 | for (i = 0; i < 500; i++) { | |||
1205 | if (ure_read_2(sc, URE_PLA_BOOT_CTRL0xe004, URE_MCU_TYPE_PLA0x0100) & | |||
1206 | URE_AUTOLOAD_DONE0x0002) | |||
1207 | break; | |||
1208 | usbd_delay_ms(sc->ure_udev, 20); | |||
1209 | } | |||
1210 | if (i == 500) | |||
1211 | printf("%s: timeout waiting for chip autoload\n", | |||
1212 | sc->ure_dev.dv_xname); | |||
1213 | ||||
1214 | ure_rtl8153_phy_status(sc, 0); | |||
1215 | ure_rtl8153_phy_status(sc, 1); | |||
1216 | ||||
1217 | URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000 ) & ~(0x0001)); | |||
1218 | ||||
1219 | /* MSC timer, 32760 ms. */ | |||
1220 | ure_write_2(sc, URE_USB_MSC_TIMER0xcbfc, URE_MCU_TYPE_USB0x0000, 0x0fff); | |||
1221 | ||||
1222 | /* U1/U2/L1 idle timer, 500 us. */ | |||
1223 | ure_write_2(sc, URE_USB_U1U2_TIMER0xd4da, URE_MCU_TYPE_USB0x0000, 500); | |||
1224 | ||||
1225 | URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN)ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000 ) & ~(0x0001)); | |||
1226 | URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000 ) & ~(0x0001)); | |||
1227 | ||||
1228 | URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd80a, 0x0000, ure_read_1(sc, 0xd80a, 0x0000 ) & ~(0x0010 | 0x0020)) | |||
1229 | URE_UPS_EN | URE_USP_PREWAKE)ure_write_1(sc, 0xd80a, 0x0000, ure_read_1(sc, 0xd80a, 0x0000 ) & ~(0x0010 | 0x0020)); | |||
1230 | URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01)ure_write_1(sc, 0xcfff, 0x0000, ure_read_1(sc, 0xcfff, 0x0000 ) & ~(0x01)); | |||
1231 | ||||
1232 | if (!(sc->ure_flags & URE_FLAG_81560x4000)) { | |||
1233 | URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000 ) & ~(0x0001)) | |||
1234 | URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000 ) & ~(0x0001)); | |||
1235 | ure_rtl8153_phy_status(sc, 0); | |||
1236 | } | |||
1237 | ||||
1238 | URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xd38c, 0x0100, ure_read_1(sc, 0xd38c, 0x0100 ) & ~(0x01)) | |||
1239 | URE_UPCOMING_RUNTIME_D3)ure_write_1(sc, 0xd38c, 0x0100, ure_read_1(sc, 0xd38c, 0x0100 ) & ~(0x01)); | |||
1240 | URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xd38a, 0x0100, ure_read_1(sc, 0xd38a, 0x0100 ) & ~(0x01)) | |||
1241 | URE_LINK_CHG_EVENT)ure_write_1(sc, 0xd38a, 0x0100, ure_read_1(sc, 0xd38a, 0x0100 ) & ~(0x01)); | |||
1242 | URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xd398, 0x0100, ure_read_2(sc, 0xd398, 0x0100 ) & ~(0x0100)) | |||
1243 | URE_LINK_CHANGE_FLAG)ure_write_2(sc, 0xd398, 0x0100, ure_read_2(sc, 0xd398, 0x0100 ) & ~(0x0100)); | |||
1244 | ||||
1245 | ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_CONFIG0xc0); | |||
1246 | URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe820, 0x0100, ure_read_2(sc, 0xe820, 0x0100 ) & ~(0x0008)) | |||
1247 | URE_LINK_OFF_WAKE_EN)ure_write_2(sc, 0xe820, 0x0100, ure_read_2(sc, 0xe820, 0x0100 ) & ~(0x0008)); | |||
1248 | ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00); | |||
1249 | ||||
1250 | URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000 ) | (0x0001)); | |||
1251 | ||||
1252 | /* MAC clock speed down. */ | |||
1253 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
1254 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0x0403); | |||
1255 | reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100) & | |||
1256 | ~0xff; | |||
1257 | reg |= URE_MAC_CLK_SPDWN_EN0x8000 | 0x0003; | |||
1258 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, reg); | |||
1259 | ||||
1260 | URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100 ) & ~(0x4000)) | |||
1261 | 0x4000)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100 ) & ~(0x4000)); | |||
1262 | ||||
1263 | reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100); | |||
1264 | if (ure_get_link_status(sc)) | |||
1265 | reg |= 0x8000; | |||
1266 | else | |||
1267 | reg &= ~0x8000; | |||
1268 | reg |= 0x0001; | |||
1269 | ure_write_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100, reg); | |||
1270 | } else | |||
1271 | URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0ca, 0x0100, ure_read_2(sc, 0xe0ca, 0x0100 ) | (0x8000)) | |||
1272 | URE_MAC_CLK_SPDWN_EN)ure_write_2(sc, 0xe0ca, 0x0100, ure_read_2(sc, 0xe0ca, 0x0100 ) | (0x8000)); | |||
1273 | ||||
1274 | /* Enable Rx aggregation. */ | |||
1275 | URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000 ) & ~(0x0010 | 0x0080)) | |||
1276 | URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000 ) & ~(0x0010 | 0x0080)); | |||
1277 | ||||
1278 | if (sc->ure_flags & URE_FLAG_81560x4000) | |||
1279 | URE_SETBIT_1(sc, 0xcfd9, URE_MCU_TYPE_USB, 0x04)ure_write_1(sc, 0xcfd9, 0x0000, ure_read_1(sc, 0xcfd9, 0x0000 ) | (0x04)); | |||
1280 | ||||
1281 | URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100 ) | (0x0001)); | |||
1282 | } | |||
1283 | ||||
1284 | void | |||
1285 | ure_rtl8152_nic_reset(struct ure_softc *sc) | |||
1286 | { | |||
1287 | uint32_t rx_fifo1, rx_fifo2; | |||
1288 | int i; | |||
1289 | ||||
1290 | /* Disable ALDPS. */ | |||
1291 | ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, URE_ENPDNPS0x0200 | URE_LINKENA0x0100 | | |||
1292 | URE_DIS_SDSAVE0x0010); | |||
1293 | usbd_delay_ms(sc->ure_udev, 20); | |||
1294 | ||||
1295 | URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL)ure_write_4(sc, 0xc010, 0x0100, ure_read_4(sc, 0xc010, 0x0100 ) & ~((0x00000001 | 0x00000002 | 0x00000004 | 0x00000008) )); | |||
1296 | ||||
1297 | URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100 ) | (0x0008)); | |||
1298 | ure_disable_teredo(sc); | |||
1299 | ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00); | |||
1300 | ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, 0); | |||
1301 | ||||
1302 | URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB)ure_write_1(sc, 0xe84f, 0x0100, ure_read_1(sc, 0xe84f, 0x0100 ) & ~(0x80)); | |||
1303 | URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100 ) & ~(0x4000)); | |||
1304 | for (i = 0; i < URE_TIMEOUT1000; i++) { | |||
1305 | if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) & | |||
1306 | URE_LINK_LIST_READY0x02) | |||
1307 | break; | |||
1308 | usbd_delay_ms(sc->ure_udev, 1); | |||
1309 | } | |||
1310 | if (i == URE_TIMEOUT1000) | |||
1311 | printf("%s: timeout waiting for OOB control\n", | |||
1312 | sc->ure_dev.dv_xname); | |||
1313 | URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100 ) | (0x8000)); | |||
1314 | for (i = 0; i < URE_TIMEOUT1000; i++) { | |||
1315 | if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) & | |||
1316 | URE_LINK_LIST_READY0x02) | |||
1317 | break; | |||
1318 | usbd_delay_ms(sc->ure_udev, 1); | |||
1319 | } | |||
1320 | if (i == URE_TIMEOUT1000) | |||
1321 | printf("%s: timeout waiting for OOB control\n", | |||
1322 | sc->ure_dev.dv_xname); | |||
1323 | ||||
1324 | ure_reset(sc); | |||
1325 | ||||
1326 | /* Configure Rx FIFO threshold. */ | |||
1327 | ure_write_4(sc, URE_PLA_RXFIFO_CTRL00xc0a0, URE_MCU_TYPE_PLA0x0100, | |||
1328 | URE_RXFIFO_THR1_NORMAL0x00080002); | |||
1329 | if (sc->ure_udev->speed == USB_SPEED_FULL2) { | |||
1330 | rx_fifo1 = URE_RXFIFO_THR2_FULL0x00000060; | |||
1331 | rx_fifo2 = URE_RXFIFO_THR3_FULL0x00000078; | |||
1332 | } else { | |||
1333 | rx_fifo1 = URE_RXFIFO_THR2_HIGH0x00000038; | |||
1334 | rx_fifo2 = URE_RXFIFO_THR3_HIGH0x00000048; | |||
1335 | } | |||
1336 | ure_write_4(sc, URE_PLA_RXFIFO_CTRL10xc0a4, URE_MCU_TYPE_PLA0x0100, rx_fifo1); | |||
1337 | ure_write_4(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100, rx_fifo2); | |||
1338 | ||||
1339 | /* Configure Tx FIFO threshold. */ | |||
1340 | ure_write_4(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100, | |||
1341 | URE_TXFIFO_THR_NORMAL0x00400008); | |||
1342 | ||||
1343 | ure_write_1(sc, URE_USB_TX_AGG0xd40a, URE_MCU_TYPE_USB0x0000, | |||
1344 | URE_TX_AGG_MAX_THRESHOLD0x03); | |||
1345 | ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000, URE_RX_THR_HIGH0x7a120180); | |||
1346 | ure_write_4(sc, URE_USB_TX_DMA0xd434, URE_MCU_TYPE_USB0x0000, | |||
1347 | URE_TEST_MODE_DISABLE0x00000001 | URE_TX_SIZE_ADJUST10x00000100); | |||
1348 | ||||
1349 | ure_rxvlan(sc); | |||
1350 | ure_write_2(sc, URE_PLA_RMS0xc016, URE_MCU_TYPE_PLA0x0100, | |||
1351 | ETHER_MAX_LEN1518 + ETHER_VLAN_ENCAP_LEN4); | |||
1352 | URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO)ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100 ) | (0x0080)); | |||
1353 | ||||
1354 | /* Enable ALDPS. */ | |||
1355 | ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, | |||
1356 | URE_ENPWRSAVE0x8000 | URE_ENPDNPS0x0200 | URE_LINKENA0x0100 | URE_DIS_SDSAVE0x0010); | |||
1357 | } | |||
1358 | ||||
1359 | void | |||
1360 | ure_rtl8153_nic_reset(struct ure_softc *sc) | |||
1361 | { | |||
1362 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
1363 | uint32_t reg = 0; | |||
1364 | uint8_t u1u2[8] = { 0 }; | |||
1365 | int i; | |||
1366 | ||||
1367 | if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000)) { | |||
1368 | URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000 ) & ~(0x0001)) | |||
1369 | LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000 ) & ~(0x0001)); | |||
1370 | } else { | |||
1371 | memset(u1u2, 0x00, sizeof(u1u2))__builtin_memset((u1u2), (0x00), (sizeof(u1u2))); | |||
1372 | ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, | |||
1373 | u1u2, sizeof(u1u2)); | |||
1374 | } | |||
1375 | URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000 ) & ~(0x0001)); | |||
1376 | ||||
1377 | /* Disable ALDPS. */ | |||
1378 | ure_ocp_reg_write(sc, URE_OCP_POWER_CFG0xa430, | |||
1379 | ure_ocp_reg_read(sc, URE_OCP_POWER_CFG0xa430) & ~URE_EN_ALDPS0x0004); | |||
1380 | for (i = 0; i < 20; i++) { | |||
1381 | usbd_delay_ms(sc->ure_udev, 1); | |||
1382 | if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA0x0100) & 0x0100) | |||
1383 | break; | |||
1384 | } | |||
1385 | if (sc->ure_flags & URE_FLAG_8153B0x2000) { | |||
1386 | URE_CLRBIT_4(sc, URE_USB_UPS_FLAGS, URE_MCU_TYPE_USB,ure_write_4(sc, 0xd848, 0x0000, ure_read_4(sc, 0xd848, 0x0000 ) & ~(0x00000008)) | |||
1387 | URE_UPS_FLAGS_EN_ALDPS)ure_write_4(sc, 0xd848, 0x0000, ure_read_4(sc, 0xd848, 0x0000 ) & ~(0x00000008)); | |||
1388 | } | |||
1389 | ||||
1390 | if (!(sc->ure_flags & URE_FLAG_81560x4000)) { | |||
1391 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0); | |||
1392 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, 0); | |||
1393 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL30xe0cc, URE_MCU_TYPE_PLA0x0100, 0); | |||
1394 | ure_write_2(sc, URE_PLA_MAC_PWR_CTRL40xe0ce, URE_MCU_TYPE_PLA0x0100, 0); | |||
1395 | } | |||
1396 | URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100 ) | (0x0008)); | |||
1397 | ure_disable_teredo(sc); | |||
1398 | ||||
1399 | URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL)ure_write_4(sc, 0xc010, 0x0100, ure_read_4(sc, 0xc010, 0x0100 ) & ~((0x00000001 | 0x00000002 | 0x00000004 | 0x00000008) )); | |||
1400 | ||||
1401 | if (sc->ure_flags & URE_FLAG_81560x4000) | |||
1402 | ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, 0); | |||
1403 | else | |||
1404 | ure_reset(sc); | |||
1405 | ||||
1406 | ure_reset_bmu(sc); | |||
1407 | ||||
1408 | URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB)ure_write_1(sc, 0xe84f, 0x0100, ure_read_1(sc, 0xe84f, 0x0100 ) & ~(0x80)); | |||
1409 | URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100 ) & ~(0x4000)); | |||
1410 | ||||
1411 | if (!(sc->ure_flags & URE_FLAG_81560x4000)) { | |||
1412 | for (i = 0; i < URE_TIMEOUT1000; i++) { | |||
1413 | if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) & | |||
1414 | URE_LINK_LIST_READY0x02) | |||
1415 | break; | |||
1416 | usbd_delay_ms(sc->ure_udev, 1); | |||
1417 | } | |||
1418 | if (i == URE_TIMEOUT1000) | |||
1419 | printf("%s: timeout waiting for OOB control\n", | |||
1420 | sc->ure_dev.dv_xname); | |||
1421 | URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100 ) | (0x8000)) | |||
1422 | URE_RE_INIT_LL)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100 ) | (0x8000)); | |||
1423 | for (i = 0; i < URE_TIMEOUT1000; i++) { | |||
1424 | if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) & | |||
1425 | URE_LINK_LIST_READY0x02) | |||
1426 | break; | |||
1427 | usbd_delay_ms(sc->ure_udev, 1); | |||
1428 | } | |||
1429 | if (i == URE_TIMEOUT1000) | |||
1430 | printf("%s: timeout waiting for OOB control\n", | |||
1431 | sc->ure_dev.dv_xname); | |||
1432 | } | |||
1433 | ure_rxvlan(sc); | |||
1434 | ure_write_2(sc, URE_PLA_RMS0xc016, URE_MCU_TYPE_PLA0x0100, | |||
1435 | URE_FRAMELEN(ifp->if_mtu)(ifp->if_data.ifi_mtu + ((6 * 2) + 2) + 4 + 4)); | |||
1436 | ure_write_1(sc, URE_PLA_MTPS0xe615, URE_MCU_TYPE_PLA0x0100, MTPS_JUMBO192); | |||
1437 | ||||
1438 | if (!(sc->ure_flags & URE_FLAG_81560x4000)) { | |||
1439 | URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100 ) | (0x0080)) | |||
1440 | URE_TCR0_AUTO_FIFO)ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100 ) | (0x0080)); | |||
1441 | ure_reset(sc); | |||
1442 | } | |||
1443 | ||||
1444 | /* Configure Rx FIFO threshold. */ | |||
1445 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
1446 | ure_write_2(sc, URE_PLA_RXFIFO_CTRL00xc0a0 + 2, URE_MCU_TYPE_PLA0x0100, | |||
1447 | 0x0008); | |||
1448 | ure_write_2(sc, URE_PLA_RXFIFO_CTRL10xc0a4 + 2, URE_MCU_TYPE_PLA0x0100, | |||
1449 | 0x0100); | |||
1450 | ure_write_2(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100, 0); | |||
1451 | } else { | |||
1452 | ure_write_4(sc, URE_PLA_RXFIFO_CTRL00xc0a0, URE_MCU_TYPE_PLA0x0100, | |||
1453 | URE_RXFIFO_THR1_NORMAL0x00080002); | |||
1454 | ure_write_2(sc, URE_PLA_RXFIFO_CTRL10xc0a4, URE_MCU_TYPE_PLA0x0100, | |||
1455 | URE_RXFIFO_THR2_NORMAL0x00a0); | |||
1456 | ure_write_2(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100, | |||
1457 | URE_RXFIFO_THR3_NORMAL0x0110); | |||
1458 | } | |||
1459 | ||||
1460 | /* Configure Tx FIFO threshold. */ | |||
1461 | ure_write_4(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100, | |||
1462 | URE_TXFIFO_THR_NORMAL20x01000008); | |||
1463 | ||||
1464 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
1465 | URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100 ) & ~(0x4000)) | |||
1466 | 0x4000)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100 ) & ~(0x4000)); | |||
1467 | ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000, | |||
1468 | 0x00600400); | |||
1469 | } else if (sc->ure_flags & URE_FLAG_8153B0x2000) { | |||
1470 | ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000, | |||
1471 | URE_RX_THR_B0x00010001); | |||
1472 | } | |||
1473 | ||||
1474 | /* Enable ALDPS. */ | |||
1475 | ure_ocp_reg_write(sc, URE_OCP_POWER_CFG0xa430, | |||
1476 | ure_ocp_reg_read(sc, URE_OCP_POWER_CFG0xa430) | URE_EN_ALDPS0x0004); | |||
1477 | if (sc->ure_flags & URE_FLAG_8153B0x2000) { | |||
1478 | reg = ure_read_4(sc, URE_USB_UPS_FLAGS0xd848, URE_MCU_TYPE_USB0x0000) & | |||
1479 | URE_UPS_FLAGS_MASK0xffffffff; | |||
1480 | ure_write_4(sc, URE_USB_UPS_FLAGS0xd848, URE_MCU_TYPE_USB0x0000, | |||
1481 | reg | URE_UPS_FLAGS_EN_ALDPS0x00000008); | |||
1482 | } | |||
1483 | ||||
1484 | if ((sc->ure_chip & (URE_CHIP_VER_5C200x10 | URE_CHIP_VER_5C300x20)) || | |||
1485 | (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000))) | |||
1486 | URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000 ) | (0x0001)) | |||
1487 | URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000 ) | (0x0001)); | |||
1488 | ||||
1489 | if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000)) { | |||
1490 | URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000 ) | (0x0001)) | |||
1491 | LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000 ) | (0x0001)); | |||
1492 | } else { | |||
1493 | memset(u1u2, 0xff, sizeof(u1u2))__builtin_memset((u1u2), (0xff), (sizeof(u1u2))); | |||
1494 | ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, | |||
1495 | u1u2, sizeof(u1u2)); | |||
1496 | } | |||
1497 | } | |||
1498 | ||||
1499 | void | |||
1500 | ure_rtl8153_phy_status(struct ure_softc *sc, int enable) | |||
1501 | { | |||
1502 | uint16_t reg; | |||
1503 | int i; | |||
1504 | ||||
1505 | for (i = 0; i < 500; i++) { | |||
1506 | reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS0xa420) & | |||
1507 | URE_PHY_STAT_MASK0x0007; | |||
1508 | if (enable) { | |||
1509 | if (reg == URE_PHY_STAT_LAN_ON3) | |||
1510 | break; | |||
1511 | } else { | |||
1512 | if (reg == URE_PHY_STAT_LAN_ON3 || | |||
1513 | reg == URE_PHY_STAT_PWRDN5 || | |||
1514 | reg == URE_PHY_STAT_EXT_INIT2) | |||
1515 | break; | |||
1516 | } | |||
1517 | usbd_delay_ms(sc->ure_udev, 20); | |||
1518 | } | |||
1519 | if (i == 500) | |||
1520 | printf("%s: timeout waiting for phy to stabilize\n", | |||
1521 | sc->ure_dev.dv_xname); | |||
1522 | } | |||
1523 | ||||
1524 | void | |||
1525 | ure_reset_bmu(struct ure_softc *sc) | |||
1526 | { | |||
1527 | URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd4b0, 0x0000, ure_read_1(sc, 0xd4b0, 0x0000 ) & ~(0x01 | 0x02)) | |||
1528 | BMU_RESET_EP_IN | BMU_RESET_EP_OUT)ure_write_1(sc, 0xd4b0, 0x0000, ure_read_1(sc, 0xd4b0, 0x0000 ) & ~(0x01 | 0x02)); | |||
1529 | URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd4b0, 0x0000, ure_read_1(sc, 0xd4b0, 0x0000 ) | (0x01 | 0x02)) | |||
1530 | BMU_RESET_EP_IN | BMU_RESET_EP_OUT)ure_write_1(sc, 0xd4b0, 0x0000, ure_read_1(sc, 0xd4b0, 0x0000 ) | (0x01 | 0x02)); | |||
1531 | } | |||
1532 | ||||
1533 | void | |||
1534 | ure_disable_teredo(struct ure_softc *sc) | |||
1535 | { | |||
1536 | if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000)) | |||
1537 | ure_write_1(sc, URE_PLA_TEREDO_CFG0xc0bc, URE_MCU_TYPE_PLA0x0100, 0xff); | |||
1538 | else { | |||
1539 | URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100 ) & ~(0x8000 | 0x00fe | 0x0001)) | |||
1540 | URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK |ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100 ) & ~(0x8000 | 0x00fe | 0x0001)) | |||
1541 | URE_OOB_TEREDO_EN)ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100 ) & ~(0x8000 | 0x00fe | 0x0001)); | |||
1542 | } | |||
1543 | ure_write_2(sc, URE_PLA_WDT6_CTRL0xe428, URE_MCU_TYPE_PLA0x0100, URE_WDT6_SET_MODE0x0010); | |||
1544 | ure_write_2(sc, URE_PLA_REALWOW_TIMER0xd2e8, URE_MCU_TYPE_PLA0x0100, 0); | |||
1545 | ure_write_4(sc, URE_PLA_TEREDO_TIMER0xd2cc, URE_MCU_TYPE_PLA0x0100, 0); | |||
1546 | } | |||
1547 | ||||
1548 | int | |||
1549 | ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) | |||
1550 | { | |||
1551 | struct ure_softc *sc = ifp->if_softc; | |||
1552 | struct ifreq *ifr = (struct ifreq *)data; | |||
1553 | int s, error = 0; | |||
1554 | ||||
1555 | s = splnet()splraise(0x7); | |||
1556 | ||||
1557 | switch (cmd) { | |||
1558 | case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((12))): | |||
1559 | ifp->if_flags |= IFF_UP0x1; | |||
1560 | if (!(ifp->if_flags & IFF_RUNNING0x40)) | |||
1561 | ure_init(sc); | |||
1562 | break; | |||
1563 | ||||
1564 | case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff ) << 16) | ((('i')) << 8) | ((16))): | |||
1565 | if (ifp->if_flags & IFF_UP0x1) { | |||
1566 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
1567 | error = ENETRESET52; | |||
1568 | else | |||
1569 | ure_init(sc); | |||
1570 | } else { | |||
1571 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
1572 | ure_stop(sc); | |||
1573 | } | |||
1574 | break; | |||
1575 | ||||
1576 | case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct ifmediareq) & 0x1fff) << 16) | ((('i')) << 8) | ((56))): | |||
1577 | case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct ifreq) & 0x1fff) << 16) | ((('i')) << 8) | ((55))): | |||
1578 | if (sc->ure_flags & URE_FLAG_81560x4000) | |||
1579 | error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd); | |||
1580 | else | |||
1581 | error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media, | |||
1582 | cmd); | |||
1583 | break; | |||
1584 | ||||
1585 | default: | |||
1586 | error = ether_ioctl(ifp, &sc->ure_ac, cmd, data); | |||
1587 | } | |||
1588 | ||||
1589 | if (error == ENETRESET52) { | |||
1590 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
1591 | ure_iff(sc); | |||
1592 | error = 0; | |||
1593 | } | |||
1594 | ||||
1595 | splx(s)spllower(s); | |||
1596 | ||||
1597 | return (error); | |||
1598 | } | |||
1599 | ||||
1600 | int | |||
1601 | ure_match(struct device *parent, void *match, void *aux) | |||
1602 | { | |||
1603 | struct usb_attach_arg *uaa = aux; | |||
1604 | ||||
1605 | if (uaa->iface == NULL((void *)0) || uaa->configno != 1) | |||
1606 | return (UMATCH_NONE0); | |||
1607 | ||||
1608 | return (usb_lookup(ure_devs, uaa->vendor, uaa->product)usbd_match_device((const struct usb_devno *)(ure_devs), sizeof (ure_devs) / sizeof ((ure_devs)[0]), sizeof ((ure_devs)[0]), (uaa->vendor), (uaa->product)) != NULL((void *)0) ? | |||
1609 | UMATCH_VENDOR_PRODUCT_CONF_IFACE8 : UMATCH_NONE0); | |||
1610 | } | |||
1611 | ||||
1612 | void | |||
1613 | ure_attach(struct device *parent, struct device *self, void *aux) | |||
1614 | { | |||
1615 | struct ure_softc *sc = (struct ure_softc *)self; | |||
1616 | struct usb_attach_arg *uaa = aux; | |||
1617 | usb_interface_descriptor_t *id; | |||
1618 | usb_endpoint_descriptor_t *ed; | |||
1619 | u_char eaddr[8]; /* 4byte padded */ | |||
1620 | struct ifnet *ifp; | |||
1621 | int i, mii_flags = 0, s; | |||
1622 | uint16_t ver; | |||
1623 | ||||
1624 | sc->ure_udev = uaa->device; | |||
1625 | sc->ure_iface = uaa->iface; | |||
1626 | ||||
1627 | usb_init_task(&sc->ure_tick_task, ure_tick_task, sc,((&sc->ure_tick_task)->fun = (ure_tick_task), (& sc->ure_tick_task)->arg = (sc), (&sc->ure_tick_task )->type = (0), (&sc->ure_tick_task)->state = 0x0 ) | |||
1628 | USB_TASK_TYPE_GENERIC)((&sc->ure_tick_task)->fun = (ure_tick_task), (& sc->ure_tick_task)->arg = (sc), (&sc->ure_tick_task )->type = (0), (&sc->ure_tick_task)->state = 0x0 ); | |||
1629 | ||||
1630 | id = usbd_get_interface_descriptor(sc->ure_iface); | |||
1631 | ||||
1632 | for (i = 0; i < id->bNumEndpoints; i++) { | |||
| ||||
1633 | ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i); | |||
1634 | if (!ed) { | |||
1635 | printf("%s: couldn't get ep %d\n", | |||
1636 | sc->ure_dev.dv_xname, i); | |||
1637 | return; | |||
1638 | } | |||
1639 | if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_IN0x80 && | |||
1640 | UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) == UE_BULK0x02) { | |||
1641 | sc->ure_ed[URE_ENDPT_RX0] = ed->bEndpointAddress; | |||
1642 | } else if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_OUT0x00 && | |||
1643 | UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) == UE_BULK0x02) { | |||
1644 | sc->ure_ed[URE_ENDPT_TX1] = ed->bEndpointAddress; | |||
1645 | } | |||
1646 | } | |||
1647 | ||||
1648 | sc->ure_txbufsz = URE_TX_BUFSZ16384; | |||
1649 | sc->ure_rxbufsz = URE_8153_RX_BUFSZ32768; | |||
1650 | ||||
1651 | s = splnet()splraise(0x7); | |||
1652 | ||||
1653 | sc->ure_phyno = 0; | |||
1654 | printf("%s: ", sc->ure_dev.dv_xname); | |||
1655 | ||||
1656 | ver = ure_read_2(sc, URE_PLA_TCR10xe612, URE_MCU_TYPE_PLA0x0100) & URE_VERSION_MASK0x7cf0; | |||
1657 | switch (ver) { | |||
1658 | case 0x4c00: | |||
1659 | sc->ure_flags = URE_FLAG_81520x1000; | |||
1660 | sc->ure_rxbufsz = URE_8152_RX_BUFSZ16384; | |||
1661 | sc->ure_chip |= URE_CHIP_VER_4C000x01; | |||
1662 | printf("RTL8152 (0x4c00)"); | |||
1663 | break; | |||
1664 | case 0x4c10: | |||
1665 | sc->ure_flags = URE_FLAG_81520x1000; | |||
1666 | sc->ure_rxbufsz = URE_8152_RX_BUFSZ16384; | |||
1667 | sc->ure_chip |= URE_CHIP_VER_4C100x02; | |||
1668 | printf("RTL8152 (0x4c10)"); | |||
1669 | break; | |||
1670 | case 0x5c00: | |||
1671 | sc->ure_chip |= URE_CHIP_VER_5C000x04; | |||
1672 | printf("RTL8153 (0x5c00)"); | |||
1673 | break; | |||
1674 | case 0x5c10: | |||
1675 | sc->ure_chip |= URE_CHIP_VER_5C100x08; | |||
1676 | printf("RTL8153 (0x5c10)"); | |||
1677 | break; | |||
1678 | case 0x5c20: | |||
1679 | sc->ure_chip |= URE_CHIP_VER_5C200x10; | |||
1680 | printf("RTL8153 (0x5c20)"); | |||
1681 | break; | |||
1682 | case 0x5c30: | |||
1683 | sc->ure_chip |= URE_CHIP_VER_5C300x20; | |||
1684 | printf("RTL8153 (0x5c30)"); | |||
1685 | break; | |||
1686 | case 0x6000: | |||
1687 | sc->ure_flags = URE_FLAG_8153B0x2000; | |||
1688 | printf("RTL8153B (0x6000)"); | |||
1689 | break; | |||
1690 | case 0x6010: | |||
1691 | sc->ure_flags = URE_FLAG_8153B0x2000; | |||
1692 | printf("RTL8153B (0x6010)"); | |||
1693 | break; | |||
1694 | case 0x7020: | |||
1695 | sc->ure_flags = URE_FLAG_81560x4000; | |||
1696 | printf("RTL8156 (0x7020)"); | |||
1697 | break; | |||
1698 | case 0x7030: | |||
1699 | sc->ure_flags = URE_FLAG_81560x4000; | |||
1700 | printf("RTL8156 (0x7030)"); | |||
1701 | break; | |||
1702 | default: | |||
1703 | printf(", unknown ver %02x", ver); | |||
1704 | break; | |||
1705 | } | |||
1706 | ||||
1707 | if (sc->ure_flags & URE_FLAG_81520x1000) | |||
1708 | ure_rtl8152_init(sc); | |||
1709 | else if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000)) | |||
1710 | ure_rtl8153b_init(sc); | |||
1711 | else | |||
1712 | ure_rtl8153_init(sc); | |||
1713 | ||||
1714 | if (sc->ure_chip & URE_CHIP_VER_4C000x01) | |||
1715 | ure_read_mem(sc, URE_PLA_IDR0xc000, URE_MCU_TYPE_PLA0x0100, eaddr, | |||
1716 | sizeof(eaddr)); | |||
1717 | else | |||
1718 | ure_read_mem(sc, URE_PLA_BACKUP0xd000, URE_MCU_TYPE_PLA0x0100, eaddr, | |||
1719 | sizeof(eaddr)); | |||
1720 | ||||
1721 | printf(", address %s\n", ether_sprintf(eaddr)); | |||
1722 | ||||
1723 | bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN6); | |||
1724 | ||||
1725 | ifp = &sc->ure_ac.ac_if; | |||
1726 | ifp->if_softc = sc; | |||
1727 | strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ16); | |||
1728 | ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000; | |||
1729 | ifp->if_ioctl = ure_ioctl; | |||
1730 | ifp->if_start = ure_start; | |||
1731 | ifp->if_watchdog = ure_watchdog; | |||
1732 | ||||
1733 | ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010 | IFCAP_CSUM_IPv40x00000001 | | |||
1734 | IFCAP_CSUM_TCPv40x00000002 | IFCAP_CSUM_UDPv40x00000004; | |||
1735 | ||||
1736 | #if NVLAN1 > 0 | |||
1737 | ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020; | |||
1738 | #endif | |||
1739 | ||||
1740 | if (sc->ure_flags & URE_FLAG_81560x4000) { | |||
1741 | ifmedia_init(&sc->ure_ifmedia, IFM_IMASK0xff00000000000000ULL, ure_ifmedia_upd, | |||
1742 | ure_ifmedia_sts); | |||
1743 | ure_add_media_types(sc); | |||
1744 | ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0)); | |||
1745 | ifmedia_set(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL); | |||
1746 | sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media; | |||
1747 | } else { | |||
1748 | rw_init(&sc->ure_mii_lock, "uremii")_rw_init_flags(&sc->ure_mii_lock, "uremii", 0, ((void * )0)); | |||
1749 | ||||
1750 | sc->ure_mii.mii_ifp = ifp; | |||
1751 | sc->ure_mii.mii_readreg = ure_miibus_readreg; | |||
1752 | sc->ure_mii.mii_writereg = ure_miibus_writereg; | |||
1753 | sc->ure_mii.mii_statchg = ure_miibus_statchg; | |||
1754 | sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP0x0010; | |||
1755 | ||||
1756 | ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd, | |||
1757 | ure_ifmedia_sts); | |||
1758 | if (!(sc->ure_flags & URE_FLAG_81520x1000)) | |||
1759 | mii_flags |= MIIF_DOPAUSE0x0100; | |||
1760 | mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno, | |||
1761 | MII_OFFSET_ANY-1, mii_flags); | |||
1762 | if (LIST_FIRST(&sc->ure_mii.mii_phys)((&sc->ure_mii.mii_phys)->lh_first) == NULL((void *)0)) { | |||
1763 | ifmedia_add(&sc->ure_mii.mii_media, | |||
1764 | IFM_ETHER0x0000000000000100ULL | IFM_NONE2ULL, 0, NULL((void *)0)); | |||
1765 | ifmedia_set(&sc->ure_mii.mii_media, | |||
1766 | IFM_ETHER0x0000000000000100ULL | IFM_NONE2ULL); | |||
1767 | } else | |||
1768 | ifmedia_set(&sc->ure_mii.mii_media, | |||
1769 | IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL); | |||
1770 | } | |||
1771 | ||||
1772 | if_attach(ifp); | |||
1773 | ether_ifattach(ifp); | |||
1774 | ||||
1775 | timeout_set(&sc->ure_stat_ch, ure_tick, sc); | |||
1776 | ||||
1777 | splx(s)spllower(s); | |||
1778 | } | |||
1779 | ||||
1780 | int | |||
1781 | ure_detach(struct device *self, int flags) | |||
1782 | { | |||
1783 | struct ure_softc *sc = (struct ure_softc *)self; | |||
1784 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
1785 | int s; | |||
1786 | ||||
1787 | if (timeout_initialized(&sc->ure_stat_ch)((&sc->ure_stat_ch)->to_flags & 0x04)) | |||
1788 | timeout_del(&sc->ure_stat_ch); | |||
1789 | ||||
1790 | if (sc->ure_ep[URE_ENDPT_TX1] != NULL((void *)0)) | |||
1791 | usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX1]); | |||
1792 | if (sc->ure_ep[URE_ENDPT_RX0] != NULL((void *)0)) | |||
1793 | usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX0]); | |||
1794 | ||||
1795 | usb_rem_task(sc->ure_udev, &sc->ure_tick_task); | |||
1796 | ||||
1797 | s = splusb()splraise(0x5); | |||
1798 | ||||
1799 | if (--sc->ure_refcnt >= 0) { | |||
1800 | usb_detach_wait(&sc->ure_dev); | |||
1801 | } | |||
1802 | ||||
1803 | if (ifp->if_flags & IFF_RUNNING0x40) | |||
1804 | ure_stop(sc); | |||
1805 | ||||
1806 | mii_detach(&sc->ure_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1); | |||
1807 | ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY((uint64_t) -1)); | |||
1808 | if (ifp->if_softc != NULL((void *)0)) { | |||
1809 | ether_ifdetach(ifp); | |||
1810 | if_detach(ifp); | |||
1811 | } | |||
1812 | ||||
1813 | splx(s)spllower(s); | |||
1814 | ||||
1815 | return 0; | |||
1816 | } | |||
1817 | ||||
1818 | void | |||
1819 | ure_tick_task(void *xsc) | |||
1820 | { | |||
1821 | struct ure_softc *sc = xsc; | |||
1822 | struct mii_data *mii; | |||
1823 | int s; | |||
1824 | ||||
1825 | if (sc == NULL((void *)0)) | |||
1826 | return; | |||
1827 | ||||
1828 | if (usbd_is_dying(sc->ure_udev)) | |||
1829 | return; | |||
1830 | mii = &sc->ure_mii; | |||
1831 | ||||
1832 | s = splnet()splraise(0x7); | |||
1833 | if (sc->ure_flags & URE_FLAG_81560x4000) | |||
1834 | ure_link_state(sc); | |||
1835 | else { | |||
1836 | mii_tick(mii); | |||
1837 | if ((sc->ure_flags & URE_FLAG_LINK0x0001) == 0) | |||
1838 | ure_miibus_statchg(&sc->ure_dev); | |||
1839 | } | |||
1840 | timeout_add_sec(&sc->ure_stat_ch, 1); | |||
1841 | splx(s)spllower(s); | |||
1842 | } | |||
1843 | ||||
1844 | void | |||
1845 | ure_lock_mii(struct ure_softc *sc) | |||
1846 | { | |||
1847 | sc->ure_refcnt++; | |||
1848 | rw_enter_write(&sc->ure_mii_lock); | |||
1849 | } | |||
1850 | ||||
1851 | void | |||
1852 | ure_unlock_mii(struct ure_softc *sc) | |||
1853 | { | |||
1854 | rw_exit_write(&sc->ure_mii_lock); | |||
1855 | if (--sc->ure_refcnt < 0) | |||
1856 | usb_detach_wakeup(&sc->ure_dev); | |||
1857 | } | |||
1858 | ||||
1859 | void | |||
1860 | ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status) | |||
1861 | { | |||
1862 | struct ure_chain *c = (struct ure_chain *)priv; | |||
1863 | struct ure_softc *sc = c->uc_sc; | |||
1864 | struct ifnet *ifp = &sc->ure_ac.ac_if; | |||
1865 | u_char *buf = c->uc_buf; | |||
1866 | uint32_t cflags, rxvlan, total_len; | |||
1867 | struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 }; | |||
1868 | struct mbuf *m; | |||
1869 | int pktlen = 0, s; | |||
1870 | struct ure_rxpkt rxhdr; | |||
1871 | ||||
1872 | if (usbd_is_dying(sc->ure_udev)) | |||
1873 | return; | |||
1874 | ||||
1875 | if (!(ifp->if_flags & IFF_RUNNING0x40)) | |||
1876 | return; | |||
1877 | ||||
1878 | if (status != USBD_NORMAL_COMPLETION) { | |||
1879 | if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) | |||
1880 | return; | |||
1881 | if (usbd_ratecheck(&sc->ure_rx_notice)) { | |||
1882 | printf("%s: usb errors on rx: %s\n", | |||
1883 | sc->ure_dev.dv_xname, usbd_errstr(status)); | |||
1884 | } | |||
1885 | if (status == USBD_STALLED) | |||
1886 | usbd_clear_endpoint_stall_async( | |||
1887 | sc->ure_ep[URE_ENDPT_RX0]); | |||
1888 | goto done; | |||
1889 | } | |||
1890 | ||||
1891 | usbd_get_xfer_status(xfer, NULL((void *)0), NULL((void *)0), &total_len, NULL((void *)0)); | |||
1892 | DPRINTFN(3, ("received %d bytes\n", total_len)); | |||
1893 | ||||
1894 | do { | |||
1895 | if (total_len < sizeof(rxhdr)) { | |||
1896 | DPRINTF(("too few bytes left for a packet header\n")); | |||
1897 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
1898 | goto done; | |||
1899 | } | |||
1900 | ||||
1901 | buf += roundup(pktlen, URE_RX_BUF_ALIGN)((((pktlen)+((8)-1))/(8))*(8)); | |||
1902 | ||||
1903 | memcpy(&rxhdr, buf, sizeof(rxhdr))__builtin_memcpy((&rxhdr), (buf), (sizeof(rxhdr))); | |||
1904 | total_len -= sizeof(rxhdr); | |||
1905 | ||||
1906 | pktlen = letoh32(rxhdr.ure_pktlen)((__uint32_t)(rxhdr.ure_pktlen)) & URE_RXPKT_LEN_MASK0x7fff; | |||
1907 | DPRINTFN(4, ("next packet is %d bytes\n", pktlen)); | |||
1908 | if (pktlen > total_len) { | |||
1909 | DPRINTF(("not enough bytes left for next packet\n")); | |||
1910 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
1911 | goto done; | |||
1912 | } | |||
1913 | ||||
1914 | total_len -= roundup(pktlen, URE_RX_BUF_ALIGN)((((pktlen)+((8)-1))/(8))*(8)); | |||
1915 | buf += sizeof(rxhdr); | |||
1916 | ||||
1917 | m = m_devget(buf, pktlen, ETHER_ALIGN2); | |||
1918 | if (m == NULL((void *)0)) { | |||
1919 | DPRINTF(("unable to allocate mbuf for next packet\n")); | |||
1920 | ifp->if_ierrorsif_data.ifi_ierrors++; | |||
1921 | goto done; | |||
1922 | } | |||
1923 | ||||
1924 | cflags = letoh32(rxhdr.ure_csum)((__uint32_t)(rxhdr.ure_csum)); | |||
1925 | rxvlan = letoh32(rxhdr.ure_vlan)((__uint32_t)(rxhdr.ure_vlan)); | |||
1926 | ||||
1927 | /* Check IP header checksum. */ | |||
1928 | if ((rxvlan & URE_RXPKT_IPV4(1 << 19)) && | |||
1929 | !(cflags & URE_RXPKT_IPSUMBAD(1 << 23))) | |||
1930 | m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008; | |||
1931 | ||||
1932 | /* Check TCP/UDP checksum. */ | |||
1933 | if ((rxvlan & (URE_RXPKT_IPV4(1 << 19) | URE_RXPKT_IPV6(1 << 20))) && | |||
1934 | (((rxvlan & URE_RXPKT_TCP(1 << 22)) && | |||
1935 | !(cflags & URE_RXPKT_TCPSUMBAD(1 << 21))) || | |||
1936 | ((rxvlan & URE_RXPKT_UDP(1 << 23)) && | |||
1937 | !(cflags & URE_RXPKT_UDPSUMBAD(1 << 22))))) | |||
1938 | m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK0x0020 | | |||
1939 | M_UDP_CSUM_IN_OK0x0080; | |||
1940 | #if NVLAN1 > 0 | |||
1941 | if (rxvlan & URE_RXPKT_VLAN_TAG(1 << 16)) { | |||
1942 | m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag = | |||
1943 | swap16(rxvlan & URE_RXPKT_VLAN_DATA)(__uint16_t)(__builtin_constant_p(rxvlan & 0xffff) ? (__uint16_t )(((__uint16_t)(rxvlan & 0xffff) & 0xffU) << 8 | ((__uint16_t)(rxvlan & 0xffff) & 0xff00U) >> 8 ) : __swap16md(rxvlan & 0xffff)); | |||
1944 | m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020; | |||
1945 | } | |||
1946 | #endif | |||
1947 | ||||
1948 | ml_enqueue(&ml, m); | |||
1949 | } while (total_len > 0); | |||
1950 | ||||
1951 | done: | |||
1952 | s = splnet()splraise(0x7); | |||
1953 | if_input(ifp, &ml); | |||
1954 | splx(s)spllower(s); | |||
1955 | memset(c->uc_buf, 0, sc->ure_rxbufsz)__builtin_memset((c->uc_buf), (0), (sc->ure_rxbufsz)); | |||
1956 | ||||
1957 | usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX0], c, c->uc_buf, | |||
1958 | sc->ure_rxbufsz, USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01, | |||
1959 | USBD_NO_TIMEOUT0, ure_rxeof); | |||
1960 | usbd_transfer(xfer); | |||
1961 | } | |||
1962 | ||||
1963 | ||||
1964 | void | |||
1965 | ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status) | |||
1966 | { | |||
1967 | struct ure_softc *sc; | |||
1968 | struct ure_chain *c; | |||
1969 | struct ifnet *ifp; | |||
1970 | int s; | |||
1971 | ||||
1972 | c = priv; | |||
1973 | sc = c->uc_sc; | |||
1974 | ifp = &sc->ure_ac.ac_if; | |||
1975 | ||||
1976 | if (usbd_is_dying(sc->ure_udev)) | |||
1977 | return; | |||
1978 | ||||
1979 | if (status != USBD_NORMAL_COMPLETION) | |||
1980 | DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname, | |||
1981 | __func__, c->uc_idx, usbd_errstr(status))); | |||
1982 | ||||
1983 | s = splnet()splraise(0x7); | |||
1984 | ||||
1985 | c->uc_cnt = 0; | |||
1986 | c->uc_buflen = 0; | |||
1987 | ||||
1988 | SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list)do { (c)->uc_list.sle_next = (&sc->ure_cdata.ure_tx_free )->slh_first; (&sc->ure_cdata.ure_tx_free)->slh_first = (c); } while (0); | |||
1989 | ||||
1990 | if (status != USBD_NORMAL_COMPLETION) { | |||
1991 | if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) { | |||
1992 | splx(s)spllower(s); | |||
1993 | return; | |||
1994 | } | |||
1995 | ||||
1996 | ifp->if_oerrorsif_data.ifi_oerrors++; | |||
1997 | printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname, | |||
1998 | usbd_errstr(status)); | |||
1999 | ||||
2000 | if (status == USBD_STALLED) | |||
2001 | usbd_clear_endpoint_stall_async( | |||
2002 | sc->ure_ep[URE_ENDPT_TX1]); | |||
2003 | splx(s)spllower(s); | |||
2004 | return; | |||
2005 | } | |||
2006 | ||||
2007 | ifp->if_timer = 0; | |||
2008 | if (ifq_is_oactive(&ifp->if_snd)) | |||
2009 | ifq_restart(&ifp->if_snd); | |||
2010 | splx(s)spllower(s); | |||
2011 | } | |||
2012 | ||||
2013 | int | |||
2014 | ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen) | |||
2015 | { | |||
2016 | struct ure_txpkt txhdr; | |||
2017 | uint32_t len = sizeof(txhdr), cflags = 0; | |||
2018 | ||||
2019 | if (len + m->m_pkthdrM_dat.MH.MH_pkthdr.len > maxlen) | |||
2020 | return (-1); | |||
2021 | ||||
2022 | if ((m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & | |||
2023 | (M_IPV4_CSUM_OUT0x0001 | M_TCP_CSUM_OUT0x0002 | M_UDP_CSUM_OUT0x0004)) != 0) { | |||
2024 | cflags |= URE_TXPKT_IPV4(1 << 29); | |||
2025 | if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002) | |||
2026 | cflags |= URE_TXPKT_TCP(1 << 30); | |||
2027 | if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004) | |||
2028 | cflags |= URE_TXPKT_UDP(1 << 31); | |||
2029 | } | |||
2030 | ||||
2031 | #if NVLAN1 > 0 | |||
2032 | if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020) | |||
2033 | cflags |= swap16(m->m_pkthdr.ether_vtag | URE_TXPKT_VLAN_TAG)(__uint16_t)(__builtin_constant_p(m->M_dat.MH.MH_pkthdr.ether_vtag | (1 << 16)) ? (__uint16_t)(((__uint16_t)(m->M_dat. MH.MH_pkthdr.ether_vtag | (1 << 16)) & 0xffU) << 8 | ((__uint16_t)(m->M_dat.MH.MH_pkthdr.ether_vtag | (1 << 16)) & 0xff00U) >> 8) : __swap16md(m->M_dat.MH. MH_pkthdr.ether_vtag | (1 << 16))); | |||
2034 | #endif | |||
2035 | ||||
2036 | txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS |((__uint32_t)(m->M_dat.MH.MH_pkthdr.len | (1 << 31) | (1 << 30))) | |||
2037 | URE_TXPKT_TX_LS)((__uint32_t)(m->M_dat.MH.MH_pkthdr.len | (1 << 31) | (1 << 30))); | |||
2038 | txhdr.ure_vlan = htole32(cflags)((__uint32_t)(cflags)); | |||
2039 | memcpy(buf, &txhdr, len)__builtin_memcpy((buf), (&txhdr), (len)); | |||
2040 | ||||
2041 | m_copydata(m, 0, m->m_pkthdrM_dat.MH.MH_pkthdr.len, buf + len); | |||
2042 | len += m->m_pkthdrM_dat.MH.MH_pkthdr.len; | |||
2043 | ||||
2044 | return (len); | |||
2045 | } | |||
2046 | ||||
2047 | int | |||
2048 | ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c) | |||
2049 | { | |||
2050 | usbd_status err; | |||
2051 | ||||
2052 | usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX1], c, c->uc_buf, | |||
2053 | c->uc_buflen, USBD_FORCE_SHORT_XFER0x08 | USBD_NO_COPY0x01, 10000, | |||
2054 | ure_txeof); | |||
2055 | ||||
2056 | err = usbd_transfer(c->uc_xfer); | |||
2057 | if (err != USBD_IN_PROGRESS) { | |||
2058 | c->uc_cnt = 0; | |||
2059 | c->uc_buflen = 0; | |||
2060 | ure_stop(sc); | |||
2061 | return (EIO5); | |||
2062 | } | |||
2063 | ||||
2064 | return (0); | |||
2065 | } |