File: | dev/pci/drm/amd/display/dc/dce110/dce110_mem_input_v.c |
Warning: | line 114, column 2 Value stored to 'temp' is never read |
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1 | /* |
2 | * Copyright 2012-16 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | * Authors: AMD |
23 | * |
24 | */ |
25 | #include "dm_services.h" |
26 | |
27 | #include "dce/dce_11_0_d.h" |
28 | #include "dce/dce_11_0_sh_mask.h" |
29 | /* TODO: this needs to be looked at, used by Stella's workaround*/ |
30 | #include "gmc/gmc_8_2_d.h" |
31 | #include "gmc/gmc_8_2_sh_mask.h" |
32 | |
33 | #include "include/logger_interface.h" |
34 | #include "inc/dce_calcs.h" |
35 | |
36 | #include "dce/dce_mem_input.h" |
37 | |
38 | static void set_flip_control( |
39 | struct dce_mem_input *mem_input110, |
40 | bool_Bool immediate) |
41 | { |
42 | uint32_t value = 0; |
43 | |
44 | value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x462f, __func__) |
45 | mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x462f, __func__) |
46 | mmUNP_FLIP_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x462f, __func__); |
47 | |
48 | set_reg_field_value(value, 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
49 | UNP_FLIP_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
50 | GRPH_SURFACE_UPDATE_PENDING_MODE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
51 | |
52 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__ ) |
53 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__ ) |
54 | mmUNP_FLIP_CONTROL,dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__ ) |
55 | value)dm_write_reg_func(mem_input110->base.ctx, 0x462f, value, __func__ ); |
56 | } |
57 | |
58 | /* chroma part */ |
59 | static void program_pri_addr_c( |
60 | struct dce_mem_input *mem_input110, |
61 | PHYSICAL_ADDRESS_LOCunion large_integer address) |
62 | { |
63 | uint32_t value = 0; |
64 | uint32_t temp = 0; |
65 | /*high register MUST be programmed first*/ |
66 | temp = address.high_part & |
67 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C_MASK0xff; |
68 | |
69 | set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0) |
70 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0) |
71 | GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C)(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0); |
72 | |
73 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__ ) |
74 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__ ) |
75 | mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_C,dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__ ) |
76 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4609, value, __func__ ); |
77 | |
78 | temp = 0; |
79 | value = 0; |
80 | temp = address.low_part >> |
81 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C__GRPH_PRIMARY_SURFACE_ADDRESS_C__SHIFT0x8; |
82 | |
83 | set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00 , 0x8) |
84 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00 , 0x8) |
85 | GRPH_PRIMARY_SURFACE_ADDRESS_C)(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00 , 0x8); |
86 | |
87 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__ ) |
88 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__ ) |
89 | mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_C,dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__ ) |
90 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4607, value, __func__ ); |
91 | } |
92 | |
93 | /* luma part */ |
94 | static void program_pri_addr_l( |
95 | struct dce_mem_input *mem_input110, |
96 | PHYSICAL_ADDRESS_LOCunion large_integer address) |
97 | { |
98 | uint32_t value = 0; |
99 | uint32_t temp = 0; |
100 | |
101 | /*high register MUST be programmed first*/ |
102 | temp = address.high_part & |
103 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L_MASK0xff; |
104 | |
105 | set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0) |
106 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0) |
107 | GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L)(value) = set_reg_field_value_ex( (value), (temp), 0xff, 0x0); |
108 | |
109 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__ ) |
110 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__ ) |
111 | mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_L,dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__ ) |
112 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4608, value, __func__ ); |
113 | |
114 | temp = 0; |
Value stored to 'temp' is never read | |
115 | value = 0; |
116 | temp = address.low_part >> |
117 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L__GRPH_PRIMARY_SURFACE_ADDRESS_L__SHIFT0x8; |
118 | |
119 | set_reg_field_value(value, temp,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00 , 0x8) |
120 | UNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00 , 0x8) |
121 | GRPH_PRIMARY_SURFACE_ADDRESS_L)(value) = set_reg_field_value_ex( (value), (temp), 0xffffff00 , 0x8); |
122 | |
123 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__ ) |
124 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__ ) |
125 | mmUNP_GRPH_PRIMARY_SURFACE_ADDRESS_L,dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__ ) |
126 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4606, value, __func__ ); |
127 | } |
128 | |
129 | static void program_addr( |
130 | struct dce_mem_input *mem_input110, |
131 | const struct dc_plane_address *addr) |
132 | { |
133 | switch (addr->type) { |
134 | case PLN_ADDR_TYPE_GRAPHICS: |
135 | program_pri_addr_l( |
136 | mem_input110, |
137 | addr->grph.addr); |
138 | break; |
139 | case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE: |
140 | program_pri_addr_c( |
141 | mem_input110, |
142 | addr->video_progressive.chroma_addr); |
143 | program_pri_addr_l( |
144 | mem_input110, |
145 | addr->video_progressive.luma_addr); |
146 | break; |
147 | default: |
148 | /* not supported */ |
149 | BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 149); do {} while (0); } while (0); |
150 | } |
151 | } |
152 | |
153 | static void enable(struct dce_mem_input *mem_input110) |
154 | { |
155 | uint32_t value = 0; |
156 | |
157 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_ENABLE)dm_read_reg_func(mem_input110->base.ctx, 0x4600, __func__); |
158 | set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
159 | dm_write_reg(mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4600, value, __func__ ) |
160 | mmUNP_GRPH_ENABLE,dm_write_reg_func(mem_input110->base.ctx, 0x4600, value, __func__ ) |
161 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4600, value, __func__ ); |
162 | } |
163 | |
164 | static void program_tiling( |
165 | struct dce_mem_input *mem_input110, |
166 | const union dc_tiling_info *info, |
167 | const enum surface_pixel_format pixel_format) |
168 | { |
169 | uint32_t value = 0; |
170 | |
171 | set_reg_field_value(value, info->gfx8.num_banks,(value) = set_reg_field_value_ex( (value), (info->gfx8.num_banks ), 0xc, 0x2) |
172 | UNP_GRPH_CONTROL, GRPH_NUM_BANKS)(value) = set_reg_field_value_ex( (value), (info->gfx8.num_banks ), 0xc, 0x2); |
173 | |
174 | set_reg_field_value(value, info->gfx8.bank_width,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width ), 0xc0, 0x6) |
175 | UNP_GRPH_CONTROL, GRPH_BANK_WIDTH_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width ), 0xc0, 0x6); |
176 | |
177 | set_reg_field_value(value, info->gfx8.bank_height,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height ), 0x1800, 0xb) |
178 | UNP_GRPH_CONTROL, GRPH_BANK_HEIGHT_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height ), 0x1800, 0xb); |
179 | |
180 | set_reg_field_value(value, info->gfx8.tile_aspect,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect ), 0xc0000, 0x12) |
181 | UNP_GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect ), 0xc0000, 0x12); |
182 | |
183 | set_reg_field_value(value, info->gfx8.tile_split,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split ), 0xe000, 0xd) |
184 | UNP_GRPH_CONTROL, GRPH_TILE_SPLIT_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split ), 0xe000, 0xd); |
185 | |
186 | set_reg_field_value(value, info->gfx8.tile_mode,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode ), 0x60000000, 0x1d) |
187 | UNP_GRPH_CONTROL, GRPH_MICRO_TILE_MODE_L)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode ), 0x60000000, 0x1d); |
188 | |
189 | set_reg_field_value(value, info->gfx8.pipe_config,(value) = set_reg_field_value_ex( (value), (info->gfx8.pipe_config ), 0x1f000000, 0x18) |
190 | UNP_GRPH_CONTROL, GRPH_PIPE_CONFIG)(value) = set_reg_field_value_ex( (value), (info->gfx8.pipe_config ), 0x1f000000, 0x18); |
191 | |
192 | set_reg_field_value(value, info->gfx8.array_mode,(value) = set_reg_field_value_ex( (value), (info->gfx8.array_mode ), 0xf00000, 0x14) |
193 | UNP_GRPH_CONTROL, GRPH_ARRAY_MODE)(value) = set_reg_field_value_ex( (value), (info->gfx8.array_mode ), 0xf00000, 0x14); |
194 | |
195 | set_reg_field_value(value, 1,(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ) |
196 | UNP_GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE)(value) = set_reg_field_value_ex( (value), (1), 0x80000000, 0x1f ); |
197 | |
198 | set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x30, 0x4) |
199 | UNP_GRPH_CONTROL, GRPH_Z)(value) = set_reg_field_value_ex( (value), (0), 0x30, 0x4); |
200 | |
201 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ) |
202 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ) |
203 | mmUNP_GRPH_CONTROL,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ) |
204 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ); |
205 | |
206 | value = 0; |
207 | |
208 | set_reg_field_value(value, info->gfx8.bank_width_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width_c ), 0xc0, 0x6) |
209 | UNP_GRPH_CONTROL_C, GRPH_BANK_WIDTH_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_width_c ), 0xc0, 0x6); |
210 | |
211 | set_reg_field_value(value, info->gfx8.bank_height_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height_c ), 0x1800, 0xb) |
212 | UNP_GRPH_CONTROL_C, GRPH_BANK_HEIGHT_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.bank_height_c ), 0x1800, 0xb); |
213 | |
214 | set_reg_field_value(value, info->gfx8.tile_aspect_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect_c ), 0xc0000, 0x12) |
215 | UNP_GRPH_CONTROL_C, GRPH_MACRO_TILE_ASPECT_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_aspect_c ), 0xc0000, 0x12); |
216 | |
217 | set_reg_field_value(value, info->gfx8.tile_split_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split_c ), 0xe000, 0xd) |
218 | UNP_GRPH_CONTROL_C, GRPH_TILE_SPLIT_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_split_c ), 0xe000, 0xd); |
219 | |
220 | set_reg_field_value(value, info->gfx8.tile_mode_c,(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode_c ), 0x60000000, 0x1d) |
221 | UNP_GRPH_CONTROL_C, GRPH_MICRO_TILE_MODE_C)(value) = set_reg_field_value_ex( (value), (info->gfx8.tile_mode_c ), 0x60000000, 0x1d); |
222 | |
223 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__ ) |
224 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__ ) |
225 | mmUNP_GRPH_CONTROL_C,dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__ ) |
226 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4602, value, __func__ ); |
227 | } |
228 | |
229 | static void program_size_and_rotation( |
230 | struct dce_mem_input *mem_input110, |
231 | enum dc_rotation_angle rotation, |
232 | const struct plane_size *plane_size) |
233 | { |
234 | uint32_t value = 0; |
235 | struct plane_size local_size = *plane_size; |
236 | |
237 | if (rotation == ROTATION_ANGLE_90 || |
238 | rotation == ROTATION_ANGLE_270) { |
239 | |
240 | swap(local_size.surface_size.x,do { __typeof(local_size.surface_size.x) __tmp = (local_size. surface_size.x); (local_size.surface_size.x) = (local_size.surface_size .y); (local_size.surface_size.y) = __tmp; } while(0) |
241 | local_size.surface_size.y)do { __typeof(local_size.surface_size.x) __tmp = (local_size. surface_size.x); (local_size.surface_size.x) = (local_size.surface_size .y); (local_size.surface_size.y) = __tmp; } while(0); |
242 | swap(local_size.surface_size.width,do { __typeof(local_size.surface_size.width) __tmp = (local_size .surface_size.width); (local_size.surface_size.width) = (local_size .surface_size.height); (local_size.surface_size.height) = __tmp ; } while(0) |
243 | local_size.surface_size.height)do { __typeof(local_size.surface_size.width) __tmp = (local_size .surface_size.width); (local_size.surface_size.width) = (local_size .surface_size.height); (local_size.surface_size.height) = __tmp ; } while(0); |
244 | swap(local_size.chroma_size.x,do { __typeof(local_size.chroma_size.x) __tmp = (local_size.chroma_size .x); (local_size.chroma_size.x) = (local_size.chroma_size.y); (local_size.chroma_size.y) = __tmp; } while(0) |
245 | local_size.chroma_size.y)do { __typeof(local_size.chroma_size.x) __tmp = (local_size.chroma_size .x); (local_size.chroma_size.x) = (local_size.chroma_size.y); (local_size.chroma_size.y) = __tmp; } while(0); |
246 | swap(local_size.chroma_size.width,do { __typeof(local_size.chroma_size.width) __tmp = (local_size .chroma_size.width); (local_size.chroma_size.width) = (local_size .chroma_size.height); (local_size.chroma_size.height) = __tmp ; } while(0) |
247 | local_size.chroma_size.height)do { __typeof(local_size.chroma_size.width) __tmp = (local_size .chroma_size.width); (local_size.chroma_size.width) = (local_size .chroma_size.height); (local_size.chroma_size.height) = __tmp ; } while(0); |
248 | } |
249 | |
250 | value = 0; |
251 | set_reg_field_value(value, local_size.surface_pitch,(value) = set_reg_field_value_ex( (value), (local_size.surface_pitch ), 0x7fff, 0x0) |
252 | UNP_GRPH_PITCH_L, GRPH_PITCH_L)(value) = set_reg_field_value_ex( (value), (local_size.surface_pitch ), 0x7fff, 0x0); |
253 | |
254 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__ ) |
255 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__ ) |
256 | mmUNP_GRPH_PITCH_L,dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__ ) |
257 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4616, value, __func__ ); |
258 | |
259 | value = 0; |
260 | set_reg_field_value(value, local_size.chroma_pitch,(value) = set_reg_field_value_ex( (value), (local_size.chroma_pitch ), 0x7fff, 0x0) |
261 | UNP_GRPH_PITCH_C, GRPH_PITCH_C)(value) = set_reg_field_value_ex( (value), (local_size.chroma_pitch ), 0x7fff, 0x0); |
262 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__ ) |
263 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__ ) |
264 | mmUNP_GRPH_PITCH_C,dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__ ) |
265 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4617, value, __func__ ); |
266 | |
267 | value = 0; |
268 | set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
269 | UNP_GRPH_X_START_L, GRPH_X_START_L)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0); |
270 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__ ) |
271 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__ ) |
272 | mmUNP_GRPH_X_START_L,dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__ ) |
273 | value)dm_write_reg_func(mem_input110->base.ctx, 0x461c, value, __func__ ); |
274 | |
275 | value = 0; |
276 | set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
277 | UNP_GRPH_X_START_C, GRPH_X_START_C)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0); |
278 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__ ) |
279 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__ ) |
280 | mmUNP_GRPH_X_START_C,dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__ ) |
281 | value)dm_write_reg_func(mem_input110->base.ctx, 0x461d, value, __func__ ); |
282 | |
283 | value = 0; |
284 | set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
285 | UNP_GRPH_Y_START_L, GRPH_Y_START_L)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0); |
286 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__ ) |
287 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__ ) |
288 | mmUNP_GRPH_Y_START_L,dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__ ) |
289 | value)dm_write_reg_func(mem_input110->base.ctx, 0x461e, value, __func__ ); |
290 | |
291 | value = 0; |
292 | set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0) |
293 | UNP_GRPH_Y_START_C, GRPH_Y_START_C)(value) = set_reg_field_value_ex( (value), (0), 0x3fff, 0x0); |
294 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__ ) |
295 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__ ) |
296 | mmUNP_GRPH_Y_START_C,dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__ ) |
297 | value)dm_write_reg_func(mem_input110->base.ctx, 0x461f, value, __func__ ); |
298 | |
299 | value = 0; |
300 | set_reg_field_value(value, local_size.surface_size.x +(value) = set_reg_field_value_ex( (value), (local_size.surface_size .x + local_size.surface_size.width), 0x7fff, 0x0) |
301 | local_size.surface_size.width,(value) = set_reg_field_value_ex( (value), (local_size.surface_size .x + local_size.surface_size.width), 0x7fff, 0x0) |
302 | UNP_GRPH_X_END_L, GRPH_X_END_L)(value) = set_reg_field_value_ex( (value), (local_size.surface_size .x + local_size.surface_size.width), 0x7fff, 0x0); |
303 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__ ) |
304 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__ ) |
305 | mmUNP_GRPH_X_END_L,dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__ ) |
306 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4620, value, __func__ ); |
307 | |
308 | value = 0; |
309 | set_reg_field_value(value, local_size.chroma_size.x +(value) = set_reg_field_value_ex( (value), (local_size.chroma_size .x + local_size.chroma_size.width), 0x7fff, 0x0) |
310 | local_size.chroma_size.width,(value) = set_reg_field_value_ex( (value), (local_size.chroma_size .x + local_size.chroma_size.width), 0x7fff, 0x0) |
311 | UNP_GRPH_X_END_C, GRPH_X_END_C)(value) = set_reg_field_value_ex( (value), (local_size.chroma_size .x + local_size.chroma_size.width), 0x7fff, 0x0); |
312 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__ ) |
313 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__ ) |
314 | mmUNP_GRPH_X_END_C,dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__ ) |
315 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4621, value, __func__ ); |
316 | |
317 | value = 0; |
318 | set_reg_field_value(value, local_size.surface_size.y +(value) = set_reg_field_value_ex( (value), (local_size.surface_size .y + local_size.surface_size.height), 0x7fff, 0x0) |
319 | local_size.surface_size.height,(value) = set_reg_field_value_ex( (value), (local_size.surface_size .y + local_size.surface_size.height), 0x7fff, 0x0) |
320 | UNP_GRPH_Y_END_L, GRPH_Y_END_L)(value) = set_reg_field_value_ex( (value), (local_size.surface_size .y + local_size.surface_size.height), 0x7fff, 0x0); |
321 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__ ) |
322 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__ ) |
323 | mmUNP_GRPH_Y_END_L,dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__ ) |
324 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4622, value, __func__ ); |
325 | |
326 | value = 0; |
327 | set_reg_field_value(value, local_size.chroma_size.y +(value) = set_reg_field_value_ex( (value), (local_size.chroma_size .y + local_size.chroma_size.height), 0x7fff, 0x0) |
328 | local_size.chroma_size.height,(value) = set_reg_field_value_ex( (value), (local_size.chroma_size .y + local_size.chroma_size.height), 0x7fff, 0x0) |
329 | UNP_GRPH_Y_END_C, GRPH_Y_END_C)(value) = set_reg_field_value_ex( (value), (local_size.chroma_size .y + local_size.chroma_size.height), 0x7fff, 0x0); |
330 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__ ) |
331 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__ ) |
332 | mmUNP_GRPH_Y_END_C,dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__ ) |
333 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4623, value, __func__ ); |
334 | |
335 | value = 0; |
336 | switch (rotation) { |
337 | case ROTATION_ANGLE_90: |
338 | set_reg_field_value(value, 3,(value) = set_reg_field_value_ex( (value), (3), 0x7, 0x0) |
339 | UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (3), 0x7, 0x0); |
340 | break; |
341 | case ROTATION_ANGLE_180: |
342 | set_reg_field_value(value, 2,(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0) |
343 | UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (2), 0x7, 0x0); |
344 | break; |
345 | case ROTATION_ANGLE_270: |
346 | set_reg_field_value(value, 1,(value) = set_reg_field_value_ex( (value), (1), 0x7, 0x0) |
347 | UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (1), 0x7, 0x0); |
348 | break; |
349 | default: |
350 | set_reg_field_value(value, 0,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
351 | UNP_HW_ROTATION, ROTATION_ANGLE)(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0); |
352 | break; |
353 | } |
354 | |
355 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__ ) |
356 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__ ) |
357 | mmUNP_HW_ROTATION,dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__ ) |
358 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4635, value, __func__ ); |
359 | } |
360 | |
361 | static void program_pixel_format( |
362 | struct dce_mem_input *mem_input110, |
363 | enum surface_pixel_format format) |
364 | { |
365 | if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { |
366 | uint32_t value; |
367 | uint8_t grph_depth; |
368 | uint8_t grph_format; |
369 | |
370 | value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x4601, __func__) |
371 | mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x4601, __func__) |
372 | mmUNP_GRPH_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x4601, __func__); |
373 | |
374 | switch (format) { |
375 | case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS: |
376 | grph_depth = 0; |
377 | grph_format = 0; |
378 | break; |
379 | case SURFACE_PIXEL_FORMAT_GRPH_RGB565: |
380 | grph_depth = 1; |
381 | grph_format = 1; |
382 | break; |
383 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: |
384 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: |
385 | grph_depth = 2; |
386 | grph_format = 0; |
387 | break; |
388 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: |
389 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: |
390 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS: |
391 | grph_depth = 2; |
392 | grph_format = 1; |
393 | break; |
394 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: |
395 | case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: |
396 | case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: |
397 | grph_depth = 3; |
398 | grph_format = 0; |
399 | break; |
400 | default: |
401 | grph_depth = 2; |
402 | grph_format = 0; |
403 | break; |
404 | } |
405 | |
406 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (grph_depth), 0x3, 0x0) |
407 | value,(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3, 0x0) |
408 | grph_depth,(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3, 0x0) |
409 | UNP_GRPH_CONTROL,(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3, 0x0) |
410 | GRPH_DEPTH)(value) = set_reg_field_value_ex( (value), (grph_depth), 0x3, 0x0); |
411 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (grph_format), 0x700 , 0x8) |
412 | value,(value) = set_reg_field_value_ex( (value), (grph_format), 0x700 , 0x8) |
413 | grph_format,(value) = set_reg_field_value_ex( (value), (grph_format), 0x700 , 0x8) |
414 | UNP_GRPH_CONTROL,(value) = set_reg_field_value_ex( (value), (grph_format), 0x700 , 0x8) |
415 | GRPH_FORMAT)(value) = set_reg_field_value_ex( (value), (grph_format), 0x700 , 0x8); |
416 | |
417 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ) |
418 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ) |
419 | mmUNP_GRPH_CONTROL,dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ) |
420 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4601, value, __func__ ); |
421 | |
422 | value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__) |
423 | mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__) |
424 | mmUNP_GRPH_CONTROL_EXP)dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__); |
425 | |
426 | /* VIDEO FORMAT 0 */ |
427 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
428 | value,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
429 | 0,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
430 | UNP_GRPH_CONTROL_EXP,(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0) |
431 | VIDEO_FORMAT)(value) = set_reg_field_value_ex( (value), (0), 0x7, 0x0); |
432 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ) |
433 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ) |
434 | mmUNP_GRPH_CONTROL_EXP,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ) |
435 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ); |
436 | |
437 | } else { |
438 | /* Video 422 and 420 needs UNP_GRPH_CONTROL_EXP programmed */ |
439 | uint32_t value; |
440 | uint8_t video_format; |
441 | |
442 | value = dm_read_reg(dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__) |
443 | mem_input110->base.ctx,dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__) |
444 | mmUNP_GRPH_CONTROL_EXP)dm_read_reg_func(mem_input110->base.ctx, 0x4603, __func__); |
445 | |
446 | switch (format) { |
447 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: |
448 | video_format = 2; |
449 | break; |
450 | case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: |
451 | video_format = 3; |
452 | break; |
453 | default: |
454 | video_format = 0; |
455 | break; |
456 | } |
457 | |
458 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (video_format), 0x7 , 0x0) |
459 | value,(value) = set_reg_field_value_ex( (value), (video_format), 0x7 , 0x0) |
460 | video_format,(value) = set_reg_field_value_ex( (value), (video_format), 0x7 , 0x0) |
461 | UNP_GRPH_CONTROL_EXP,(value) = set_reg_field_value_ex( (value), (video_format), 0x7 , 0x0) |
462 | VIDEO_FORMAT)(value) = set_reg_field_value_ex( (value), (video_format), 0x7 , 0x0); |
463 | |
464 | dm_write_reg(dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ) |
465 | mem_input110->base.ctx,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ) |
466 | mmUNP_GRPH_CONTROL_EXP,dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ) |
467 | value)dm_write_reg_func(mem_input110->base.ctx, 0x4603, value, __func__ ); |
468 | } |
469 | } |
470 | |
471 | bool_Bool dce_mem_input_v_is_surface_pending(struct mem_input *mem_input) |
472 | { |
473 | struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr = (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof (struct dce_mem_input, base) );}); |
474 | uint32_t value; |
475 | |
476 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_GRPH_UPDATE)dm_read_reg_func(mem_input110->base.ctx, 0x4624, __func__); |
477 | |
478 | if (get_reg_field_value(value, UNP_GRPH_UPDATE,get_reg_field_value_ex( (value), 0x4, 0x2) |
479 | GRPH_SURFACE_UPDATE_PENDING)get_reg_field_value_ex( (value), 0x4, 0x2)) |
480 | return true1; |
481 | |
482 | mem_input->current_address = mem_input->request_address; |
483 | return false0; |
484 | } |
485 | |
486 | bool_Bool dce_mem_input_v_program_surface_flip_and_addr( |
487 | struct mem_input *mem_input, |
488 | const struct dc_plane_address *address, |
489 | bool_Bool flip_immediate) |
490 | { |
491 | struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr = (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof (struct dce_mem_input, base) );}); |
492 | |
493 | set_flip_control(mem_input110, flip_immediate); |
494 | program_addr(mem_input110, |
495 | address); |
496 | |
497 | mem_input->request_address = *address; |
498 | |
499 | return true1; |
500 | } |
501 | |
502 | /* Scatter Gather param tables */ |
503 | static const unsigned int dvmm_Hw_Setting_2DTiling[4][9] = { |
504 | { 8, 64, 64, 8, 8, 1, 4, 0, 0}, |
505 | { 16, 64, 32, 8, 16, 1, 8, 0, 0}, |
506 | { 32, 32, 32, 16, 16, 1, 8, 0, 0}, |
507 | { 64, 8, 32, 16, 16, 1, 8, 0, 0}, /* fake */ |
508 | }; |
509 | |
510 | static const unsigned int dvmm_Hw_Setting_1DTiling[4][9] = { |
511 | { 8, 512, 8, 1, 0, 1, 0, 0, 0}, /* 0 for invalid */ |
512 | { 16, 256, 8, 2, 0, 1, 0, 0, 0}, |
513 | { 32, 128, 8, 4, 0, 1, 0, 0, 0}, |
514 | { 64, 64, 8, 4, 0, 1, 0, 0, 0}, /* fake */ |
515 | }; |
516 | |
517 | static const unsigned int dvmm_Hw_Setting_Linear[4][9] = { |
518 | { 8, 4096, 1, 8, 0, 1, 0, 0, 0}, |
519 | { 16, 2048, 1, 8, 0, 1, 0, 0, 0}, |
520 | { 32, 1024, 1, 8, 0, 1, 0, 0, 0}, |
521 | { 64, 512, 1, 8, 0, 1, 0, 0, 0}, /* new for 64bpp from HW */ |
522 | }; |
523 | |
524 | /* Helper to get table entry from surface info */ |
525 | static const unsigned int *get_dvmm_hw_setting( |
526 | union dc_tiling_info *tiling_info, |
527 | enum surface_pixel_format format, |
528 | bool_Bool chroma) |
529 | { |
530 | enum bits_per_pixel { |
531 | bpp_8 = 0, |
532 | bpp_16, |
533 | bpp_32, |
534 | bpp_64 |
535 | } bpp; |
536 | |
537 | if (format >= SURFACE_PIXEL_FORMAT_INVALID) |
538 | bpp = bpp_32; |
539 | else if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) |
540 | bpp = chroma ? bpp_16 : bpp_8; |
541 | else |
542 | bpp = bpp_8; |
543 | |
544 | switch (tiling_info->gfx8.array_mode) { |
545 | case DC_ARRAY_1D_TILED_THIN1: |
546 | case DC_ARRAY_1D_TILED_THICK: |
547 | case DC_ARRAY_PRT_TILED_THIN1: |
548 | return dvmm_Hw_Setting_1DTiling[bpp]; |
549 | case DC_ARRAY_2D_TILED_THIN1: |
550 | case DC_ARRAY_2D_TILED_THICK: |
551 | case DC_ARRAY_2D_TILED_X_THICK: |
552 | case DC_ARRAY_PRT_2D_TILED_THIN1: |
553 | case DC_ARRAY_PRT_2D_TILED_THICK: |
554 | return dvmm_Hw_Setting_2DTiling[bpp]; |
555 | case DC_ARRAY_LINEAR_GENERAL: |
556 | case DC_ARRAY_LINEAR_ALLIGNED: |
557 | return dvmm_Hw_Setting_Linear[bpp]; |
558 | default: |
559 | return dvmm_Hw_Setting_2DTiling[bpp]; |
560 | } |
561 | } |
562 | |
563 | void dce_mem_input_v_program_pte_vm( |
564 | struct mem_input *mem_input, |
565 | enum surface_pixel_format format, |
566 | union dc_tiling_info *tiling_info, |
567 | enum dc_rotation_angle rotation) |
568 | { |
569 | struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr = (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof (struct dce_mem_input, base) );}); |
570 | const unsigned int *pte = get_dvmm_hw_setting(tiling_info, format, false0); |
571 | const unsigned int *pte_chroma = get_dvmm_hw_setting(tiling_info, format, true1); |
572 | |
573 | unsigned int page_width = 0; |
574 | unsigned int page_height = 0; |
575 | unsigned int page_width_chroma = 0; |
576 | unsigned int page_height_chroma = 0; |
577 | unsigned int temp_page_width = pte[1]; |
578 | unsigned int temp_page_height = pte[2]; |
579 | unsigned int min_pte_before_flip = 0; |
580 | unsigned int min_pte_before_flip_chroma = 0; |
581 | uint32_t value = 0; |
582 | |
583 | while ((temp_page_width >>= 1) != 0) |
584 | page_width++; |
585 | while ((temp_page_height >>= 1) != 0) |
586 | page_height++; |
587 | |
588 | temp_page_width = pte_chroma[1]; |
589 | temp_page_height = pte_chroma[2]; |
590 | while ((temp_page_width >>= 1) != 0) |
591 | page_width_chroma++; |
592 | while ((temp_page_height >>= 1) != 0) |
593 | page_height_chroma++; |
594 | |
595 | switch (rotation) { |
596 | case ROTATION_ANGLE_90: |
597 | case ROTATION_ANGLE_270: |
598 | min_pte_before_flip = pte[4]; |
599 | min_pte_before_flip_chroma = pte_chroma[4]; |
600 | break; |
601 | default: |
602 | min_pte_before_flip = pte[3]; |
603 | min_pte_before_flip_chroma = pte_chroma[3]; |
604 | break; |
605 | } |
606 | |
607 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT)dm_read_reg_func(mem_input110->base.ctx, 0x463a, __func__); |
608 | /* TODO: un-hardcode requestlimit */ |
609 | set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_L)(value) = set_reg_field_value_ex( (value), (0xff), 0xff, 0x0); |
610 | set_reg_field_value(value, 0xff, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT, UNP_PIPE_OUTSTANDING_REQUEST_LIMIT_C)(value) = set_reg_field_value_ex( (value), (0xff), 0xff00, 0x8 ); |
611 | dm_write_reg(mem_input110->base.ctx, mmUNP_PIPE_OUTSTANDING_REQUEST_LIMIT, value)dm_write_reg_func(mem_input110->base.ctx, 0x463a, value, __func__ ); |
612 | |
613 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x4629, __func__); |
614 | set_reg_field_value(value, page_width, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH)(value) = set_reg_field_value_ex( (value), (page_width), 0x1e , 0x1); |
615 | set_reg_field_value(value, page_height, UNP_DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT)(value) = set_reg_field_value_ex( (value), (page_height), 0x1e0 , 0x5); |
616 | set_reg_field_value(value, min_pte_before_flip, UNP_DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP)(value) = set_reg_field_value_ex( (value), (min_pte_before_flip ), 0x7fe00, 0x9); |
617 | dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL, value)dm_write_reg_func(mem_input110->base.ctx, 0x4629, value, __func__ ); |
618 | |
619 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL)dm_read_reg_func(mem_input110->base.ctx, 0x462a, __func__); |
620 | set_reg_field_value(value, pte[5], UNP_DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK)(value) = set_reg_field_value_ex( (value), (pte[5]), 0x3f, 0x0 ); |
621 | set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING)(value) = set_reg_field_value_ex( (value), (0xff), 0xff00, 0x8 ); |
622 | dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL, value)dm_write_reg_func(mem_input110->base.ctx, 0x462a, value, __func__ ); |
623 | |
624 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C)dm_read_reg_func(mem_input110->base.ctx, 0x4604, __func__); |
625 | set_reg_field_value(value, page_width_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_WIDTH_C)(value) = set_reg_field_value_ex( (value), (page_width_chroma ), 0x1e, 0x1); |
626 | set_reg_field_value(value, page_height_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_PAGE_HEIGHT_C)(value) = set_reg_field_value_ex( (value), (page_height_chroma ), 0x1e0, 0x5); |
627 | set_reg_field_value(value, min_pte_before_flip_chroma, UNP_DVMM_PTE_CONTROL_C, DVMM_MIN_PTE_BEFORE_FLIP_C)(value) = set_reg_field_value_ex( (value), (min_pte_before_flip_chroma ), 0x7fe00, 0x9); |
628 | dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_CONTROL_C, value)dm_write_reg_func(mem_input110->base.ctx, 0x4604, value, __func__ ); |
629 | |
630 | value = dm_read_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C)dm_read_reg_func(mem_input110->base.ctx, 0x462d, __func__); |
631 | set_reg_field_value(value, pte_chroma[5], UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_PTE_REQ_PER_CHUNK_C)(value) = set_reg_field_value_ex( (value), (pte_chroma[5]), 0x3f , 0x0); |
632 | set_reg_field_value(value, 0xff, UNP_DVMM_PTE_ARB_CONTROL_C, DVMM_MAX_PTE_REQ_OUTSTANDING_C)(value) = set_reg_field_value_ex( (value), (0xff), 0xff00, 0x8 ); |
633 | dm_write_reg(mem_input110->base.ctx, mmUNP_DVMM_PTE_ARB_CONTROL_C, value)dm_write_reg_func(mem_input110->base.ctx, 0x462d, value, __func__ ); |
634 | } |
635 | |
636 | void dce_mem_input_v_program_surface_config( |
637 | struct mem_input *mem_input, |
638 | enum surface_pixel_format format, |
639 | union dc_tiling_info *tiling_info, |
640 | struct plane_size *plane_size, |
641 | enum dc_rotation_angle rotation, |
642 | struct dc_plane_dcc_param *dcc, |
643 | bool_Bool horizotal_mirror) |
644 | { |
645 | struct dce_mem_input *mem_input110 = TO_DCE_MEM_INPUT(mem_input)({ const __typeof( ((struct dce_mem_input *)0)->base ) *__mptr = (mem_input); (struct dce_mem_input *)( (char *)__mptr - __builtin_offsetof (struct dce_mem_input, base) );}); |
646 | |
647 | enable(mem_input110); |
648 | program_tiling(mem_input110, tiling_info, format); |
649 | program_size_and_rotation(mem_input110, rotation, plane_size); |
650 | program_pixel_format(mem_input110, format); |
651 | } |
652 | |
653 | static void program_urgency_watermark( |
654 | const struct dc_context *ctx, |
655 | const uint32_t urgency_addr, |
656 | const uint32_t wm_addr, |
657 | struct dce_watermarks marks_low, |
658 | uint32_t total_dest_line_time_ns) |
659 | { |
660 | /* register value */ |
661 | uint32_t urgency_cntl = 0; |
662 | uint32_t wm_mask_cntl = 0; |
663 | |
664 | /*Write mask to enable reading/writing of watermark set A*/ |
665 | wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__); |
666 | set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x300, 0x8) |
667 | 1,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x300, 0x8) |
668 | DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x300, 0x8) |
669 | URGENCY_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x300, 0x8); |
670 | dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__); |
671 | |
672 | urgency_cntl = dm_read_reg(ctx, urgency_addr)dm_read_reg_func(ctx, urgency_addr, __func__); |
673 | |
674 | set_reg_field_value((urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .a_mark), 0xffff, 0x0) |
675 | urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .a_mark), 0xffff, 0x0) |
676 | marks_low.a_mark,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .a_mark), 0xffff, 0x0) |
677 | DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .a_mark), 0xffff, 0x0) |
678 | URGENCY_LOW_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .a_mark), 0xffff, 0x0); |
679 | |
680 | set_reg_field_value((urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
681 | urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
682 | total_dest_line_time_ns,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
683 | DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
684 | URGENCY_HIGH_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10); |
685 | dm_write_reg(ctx, urgency_addr, urgency_cntl)dm_write_reg_func(ctx, urgency_addr, urgency_cntl, __func__); |
686 | |
687 | /*Write mask to enable reading/writing of watermark set B*/ |
688 | wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__); |
689 | set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x300, 0x8) |
690 | 2,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x300, 0x8) |
691 | DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x300, 0x8) |
692 | URGENCY_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x300, 0x8); |
693 | dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__); |
694 | |
695 | urgency_cntl = dm_read_reg(ctx, urgency_addr)dm_read_reg_func(ctx, urgency_addr, __func__); |
696 | |
697 | set_reg_field_value(urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .b_mark), 0xffff, 0x0) |
698 | marks_low.b_mark,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .b_mark), 0xffff, 0x0) |
699 | DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .b_mark), 0xffff, 0x0) |
700 | URGENCY_LOW_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (marks_low .b_mark), 0xffff, 0x0); |
701 | |
702 | set_reg_field_value(urgency_cntl,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
703 | total_dest_line_time_ns,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
704 | DPGV0_PIPE_URGENCY_CONTROL,(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10) |
705 | URGENCY_HIGH_WATERMARK)(urgency_cntl) = set_reg_field_value_ex( (urgency_cntl), (total_dest_line_time_ns ), 0xffff0000, 0x10); |
706 | |
707 | dm_write_reg(ctx, urgency_addr, urgency_cntl)dm_write_reg_func(ctx, urgency_addr, urgency_cntl, __func__); |
708 | } |
709 | |
710 | static void program_urgency_watermark_l( |
711 | const struct dc_context *ctx, |
712 | struct dce_watermarks marks_low, |
713 | uint32_t total_dest_line_time_ns) |
714 | { |
715 | program_urgency_watermark( |
716 | ctx, |
717 | mmDPGV0_PIPE_URGENCY_CONTROL0x4733, |
718 | mmDPGV0_WATERMARK_MASK_CONTROL0x4732, |
719 | marks_low, |
720 | total_dest_line_time_ns); |
721 | } |
722 | |
723 | static void program_urgency_watermark_c( |
724 | const struct dc_context *ctx, |
725 | struct dce_watermarks marks_low, |
726 | uint32_t total_dest_line_time_ns) |
727 | { |
728 | program_urgency_watermark( |
729 | ctx, |
730 | mmDPGV1_PIPE_URGENCY_CONTROL0x4740, |
731 | mmDPGV1_WATERMARK_MASK_CONTROL0x473f, |
732 | marks_low, |
733 | total_dest_line_time_ns); |
734 | } |
735 | |
736 | static void program_stutter_watermark( |
737 | const struct dc_context *ctx, |
738 | const uint32_t stutter_addr, |
739 | const uint32_t wm_addr, |
740 | struct dce_watermarks marks) |
741 | { |
742 | /* register value */ |
743 | uint32_t stutter_cntl = 0; |
744 | uint32_t wm_mask_cntl = 0; |
745 | |
746 | /*Write mask to enable reading/writing of watermark set A*/ |
747 | |
748 | wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__); |
749 | set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x3, 0x0) |
750 | 1,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x3, 0x0) |
751 | DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x3, 0x0) |
752 | STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (1), 0x3, 0x0); |
753 | dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__); |
754 | |
755 | stutter_cntl = dm_read_reg(ctx, stutter_addr)dm_read_reg_func(ctx, stutter_addr, __func__); |
756 | |
757 | if (ctx->dc->debug.disable_stutter) { |
758 | set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0), 0x1, 0x0) |
759 | 0,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0), 0x1, 0x0) |
760 | DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0), 0x1, 0x0) |
761 | STUTTER_ENABLE)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (0), 0x1, 0x0); |
762 | } else { |
763 | set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x1, 0x0) |
764 | 1,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x1, 0x0) |
765 | DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x1, 0x0) |
766 | STUTTER_ENABLE)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x1, 0x0); |
767 | } |
768 | |
769 | set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x80, 0x7) |
770 | 1,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x80, 0x7) |
771 | DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x80, 0x7) |
772 | STUTTER_IGNORE_FBC)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (1), 0x80, 0x7); |
773 | |
774 | /*Write watermark set A*/ |
775 | set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .a_mark), 0xffff0000, 0x10) |
776 | marks.a_mark,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .a_mark), 0xffff0000, 0x10) |
777 | DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .a_mark), 0xffff0000, 0x10) |
778 | STUTTER_EXIT_SELF_REFRESH_WATERMARK)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .a_mark), 0xffff0000, 0x10); |
779 | dm_write_reg(ctx, stutter_addr, stutter_cntl)dm_write_reg_func(ctx, stutter_addr, stutter_cntl, __func__); |
780 | |
781 | /*Write mask to enable reading/writing of watermark set B*/ |
782 | wm_mask_cntl = dm_read_reg(ctx, wm_addr)dm_read_reg_func(ctx, wm_addr, __func__); |
783 | set_reg_field_value(wm_mask_cntl,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x3, 0x0) |
784 | 2,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x3, 0x0) |
785 | DPGV0_WATERMARK_MASK_CONTROL,(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x3, 0x0) |
786 | STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK)(wm_mask_cntl) = set_reg_field_value_ex( (wm_mask_cntl), (2), 0x3, 0x0); |
787 | dm_write_reg(ctx, wm_addr, wm_mask_cntl)dm_write_reg_func(ctx, wm_addr, wm_mask_cntl, __func__); |
788 | |
789 | stutter_cntl = dm_read_reg(ctx, stutter_addr)dm_read_reg_func(ctx, stutter_addr, __func__); |
790 | /*Write watermark set B*/ |
791 | set_reg_field_value(stutter_cntl,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .b_mark), 0xffff0000, 0x10) |
792 | marks.b_mark,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .b_mark), 0xffff0000, 0x10) |
793 | DPGV0_PIPE_STUTTER_CONTROL,(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .b_mark), 0xffff0000, 0x10) |
794 | STUTTER_EXIT_SELF_REFRESH_WATERMARK)(stutter_cntl) = set_reg_field_value_ex( (stutter_cntl), (marks .b_mark), 0xffff0000, 0x10); |
795 | dm_write_reg(ctx, stutter_addr, stutter_cntl)dm_write_reg_func(ctx, stutter_addr, stutter_cntl, __func__); |
796 | } |
797 | |
798 | static void program_stutter_watermark_l( |
799 | const struct dc_context *ctx, |
800 | struct dce_watermarks marks) |
801 | { |
802 | program_stutter_watermark(ctx, |
803 | mmDPGV0_PIPE_STUTTER_CONTROL0x4735, |
804 | mmDPGV0_WATERMARK_MASK_CONTROL0x4732, |
805 | marks); |
806 | } |
807 | |
808 | static void program_stutter_watermark_c( |
809 | const struct dc_context *ctx, |
810 | struct dce_watermarks marks) |
811 | { |
812 | program_stutter_watermark(ctx, |
813 | mmDPGV1_PIPE_STUTTER_CONTROL0x4742, |
814 | mmDPGV1_WATERMARK_MASK_CONTROL0x473f, |
815 | marks); |
816 | } |
817 | |
818 | static void program_nbp_watermark( |
819 | const struct dc_context *ctx, |
820 | const uint32_t wm_mask_ctrl_addr, |
821 | const uint32_t nbp_pstate_ctrl_addr, |
822 | struct dce_watermarks marks) |
823 | { |
824 | uint32_t value; |
825 | |
826 | /* Write mask to enable reading/writing of watermark set A */ |
827 | |
828 | value = dm_read_reg(ctx, wm_mask_ctrl_addr)dm_read_reg_func(ctx, wm_mask_ctrl_addr, __func__); |
829 | |
830 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10 ) |
831 | value,(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10 ) |
832 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10 ) |
833 | DPGV0_WATERMARK_MASK_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10 ) |
834 | NB_PSTATE_CHANGE_WATERMARK_MASK)(value) = set_reg_field_value_ex( (value), (1), 0x30000, 0x10 ); |
835 | dm_write_reg(ctx, wm_mask_ctrl_addr, value)dm_write_reg_func(ctx, wm_mask_ctrl_addr, value, __func__); |
836 | |
837 | value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__); |
838 | |
839 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
840 | value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
841 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
842 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
843 | NB_PSTATE_CHANGE_ENABLE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
844 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
845 | value,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
846 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
847 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
848 | NB_PSTATE_CHANGE_URGENT_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4); |
849 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
850 | value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
851 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
852 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
853 | NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
854 | dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__); |
855 | |
856 | /* Write watermark set A */ |
857 | value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__); |
858 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000 , 0x10) |
859 | value,(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000 , 0x10) |
860 | marks.a_mark,(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000 , 0x10) |
861 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000 , 0x10) |
862 | NB_PSTATE_CHANGE_WATERMARK)(value) = set_reg_field_value_ex( (value), (marks.a_mark), 0xffff0000 , 0x10); |
863 | dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__); |
864 | |
865 | /* Write mask to enable reading/writing of watermark set B */ |
866 | value = dm_read_reg(ctx, wm_mask_ctrl_addr)dm_read_reg_func(ctx, wm_mask_ctrl_addr, __func__); |
867 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
868 | value,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
869 | 2,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
870 | DPGV0_WATERMARK_MASK_CONTROL,(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ) |
871 | NB_PSTATE_CHANGE_WATERMARK_MASK)(value) = set_reg_field_value_ex( (value), (2), 0x30000, 0x10 ); |
872 | dm_write_reg(ctx, wm_mask_ctrl_addr, value)dm_write_reg_func(ctx, wm_mask_ctrl_addr, value, __func__); |
873 | |
874 | value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__); |
875 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
876 | value,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
877 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
878 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0) |
879 | NB_PSTATE_CHANGE_ENABLE)(value) = set_reg_field_value_ex( (value), (1), 0x1, 0x0); |
880 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
881 | value,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
882 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
883 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4) |
884 | NB_PSTATE_CHANGE_URGENT_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x10, 0x4); |
885 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
886 | value,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
887 | 1,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
888 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8) |
889 | NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST)(value) = set_reg_field_value_ex( (value), (1), 0x100, 0x8); |
890 | dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__); |
891 | |
892 | /* Write watermark set B */ |
893 | value = dm_read_reg(ctx, nbp_pstate_ctrl_addr)dm_read_reg_func(ctx, nbp_pstate_ctrl_addr, __func__); |
894 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000 , 0x10) |
895 | value,(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000 , 0x10) |
896 | marks.b_mark,(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000 , 0x10) |
897 | DPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL,(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000 , 0x10) |
898 | NB_PSTATE_CHANGE_WATERMARK)(value) = set_reg_field_value_ex( (value), (marks.b_mark), 0xffff0000 , 0x10); |
899 | dm_write_reg(ctx, nbp_pstate_ctrl_addr, value)dm_write_reg_func(ctx, nbp_pstate_ctrl_addr, value, __func__); |
900 | } |
901 | |
902 | static void program_nbp_watermark_l( |
903 | const struct dc_context *ctx, |
904 | struct dce_watermarks marks) |
905 | { |
906 | program_nbp_watermark(ctx, |
907 | mmDPGV0_WATERMARK_MASK_CONTROL0x4732, |
908 | mmDPGV0_PIPE_NB_PSTATE_CHANGE_CONTROL0x4736, |
909 | marks); |
910 | } |
911 | |
912 | static void program_nbp_watermark_c( |
913 | const struct dc_context *ctx, |
914 | struct dce_watermarks marks) |
915 | { |
916 | program_nbp_watermark(ctx, |
917 | mmDPGV1_WATERMARK_MASK_CONTROL0x473f, |
918 | mmDPGV1_PIPE_NB_PSTATE_CHANGE_CONTROL0x4743, |
919 | marks); |
920 | } |
921 | |
922 | void dce_mem_input_v_program_display_marks( |
923 | struct mem_input *mem_input, |
924 | struct dce_watermarks nbp, |
925 | struct dce_watermarks stutter, |
926 | struct dce_watermarks stutter_enter, |
927 | struct dce_watermarks urgent, |
928 | uint32_t total_dest_line_time_ns) |
929 | { |
930 | program_urgency_watermark_l( |
931 | mem_input->ctx, |
932 | urgent, |
933 | total_dest_line_time_ns); |
934 | |
935 | program_nbp_watermark_l( |
936 | mem_input->ctx, |
937 | nbp); |
938 | |
939 | program_stutter_watermark_l( |
940 | mem_input->ctx, |
941 | stutter); |
942 | |
943 | } |
944 | |
945 | void dce_mem_input_program_chroma_display_marks( |
946 | struct mem_input *mem_input, |
947 | struct dce_watermarks nbp, |
948 | struct dce_watermarks stutter, |
949 | struct dce_watermarks urgent, |
950 | uint32_t total_dest_line_time_ns) |
951 | { |
952 | program_urgency_watermark_c( |
953 | mem_input->ctx, |
954 | urgent, |
955 | total_dest_line_time_ns); |
956 | |
957 | program_nbp_watermark_c( |
958 | mem_input->ctx, |
959 | nbp); |
960 | |
961 | program_stutter_watermark_c( |
962 | mem_input->ctx, |
963 | stutter); |
964 | } |
965 | |
966 | void dce110_allocate_mem_input_v( |
967 | struct mem_input *mi, |
968 | uint32_t h_total,/* for current stream */ |
969 | uint32_t v_total,/* for current stream */ |
970 | uint32_t pix_clk_khz,/* for current stream */ |
971 | uint32_t total_stream_num) |
972 | { |
973 | uint32_t addr; |
974 | uint32_t value; |
975 | uint32_t pix_dur; |
976 | if (pix_clk_khz != 0) { |
977 | addr = mmDPGV0_PIPE_ARBITRATION_CONTROL10x4730; |
978 | value = dm_read_reg(mi->ctx, addr)dm_read_reg_func(mi->ctx, addr, __func__); |
979 | pix_dur = 1000000000ULL / pix_clk_khz; |
980 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
981 | value,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
982 | pix_dur,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
983 | DPGV0_PIPE_ARBITRATION_CONTROL1,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
984 | PIXEL_DURATION)(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0); |
985 | dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__); |
986 | |
987 | addr = mmDPGV1_PIPE_ARBITRATION_CONTROL10x473d; |
988 | value = dm_read_reg(mi->ctx, addr)dm_read_reg_func(mi->ctx, addr, __func__); |
989 | pix_dur = 1000000000ULL / pix_clk_khz; |
990 | set_reg_field_value((value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
991 | value,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
992 | pix_dur,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
993 | DPGV1_PIPE_ARBITRATION_CONTROL1,(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0) |
994 | PIXEL_DURATION)(value) = set_reg_field_value_ex( (value), (pix_dur), 0xffff, 0x0); |
995 | dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__); |
996 | |
997 | addr = mmDPGV0_PIPE_ARBITRATION_CONTROL20x4731; |
998 | value = 0x4000800; |
999 | dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__); |
1000 | |
1001 | addr = mmDPGV1_PIPE_ARBITRATION_CONTROL20x473e; |
1002 | value = 0x4000800; |
1003 | dm_write_reg(mi->ctx, addr, value)dm_write_reg_func(mi->ctx, addr, value, __func__); |
1004 | } |
1005 | |
1006 | } |
1007 | |
1008 | void dce110_free_mem_input_v( |
1009 | struct mem_input *mi, |
1010 | uint32_t total_stream_num) |
1011 | { |
1012 | } |
1013 | |
1014 | static const struct mem_input_funcs dce110_mem_input_v_funcs = { |
1015 | .mem_input_program_display_marks = |
1016 | dce_mem_input_v_program_display_marks, |
1017 | .mem_input_program_chroma_display_marks = |
1018 | dce_mem_input_program_chroma_display_marks, |
1019 | .allocate_mem_input = dce110_allocate_mem_input_v, |
1020 | .free_mem_input = dce110_free_mem_input_v, |
1021 | .mem_input_program_surface_flip_and_addr = |
1022 | dce_mem_input_v_program_surface_flip_and_addr, |
1023 | .mem_input_program_pte_vm = |
1024 | dce_mem_input_v_program_pte_vm, |
1025 | .mem_input_program_surface_config = |
1026 | dce_mem_input_v_program_surface_config, |
1027 | .mem_input_is_flip_pending = |
1028 | dce_mem_input_v_is_surface_pending |
1029 | }; |
1030 | /*****************************************/ |
1031 | /* Constructor, Destructor */ |
1032 | /*****************************************/ |
1033 | |
1034 | void dce110_mem_input_v_construct( |
1035 | struct dce_mem_input *dce_mi, |
1036 | struct dc_context *ctx) |
1037 | { |
1038 | dce_mi->base.funcs = &dce110_mem_input_v_funcs; |
1039 | dce_mi->base.ctx = ctx; |
1040 | } |
1041 |