Bug Summary

File:dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
Warning:line 453, column 31
Division by zero

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dcn10_dpp_dscl.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27
28#include "core_types.h"
29
30#include "reg_helper.h"
31#include "dcn10_dpp.h"
32#include "basics/conversion.h"
33
34
35#define NUM_PHASES64 64
36#define HORZ_MAX_TAPS8 8
37#define VERT_MAX_TAPS8 8
38
39#define BLACK_OFFSET_RGB_Y0x0 0x0
40#define BLACK_OFFSET_CBCR0x8000 0x8000
41
42#define REG(reg)dpp->tf_regs->reg\
43 dpp->tf_regs->reg
44
45#define CTXdpp->base.ctx \
46 dpp->base.ctx
47
48#undef FN
49#define FN(reg_name, field_name)dpp->tf_shift->field_name, dpp->tf_mask->field_name \
50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
51
52enum dcn10_coef_filter_type_sel {
53 SCL_COEF_LUMA_VERT_FILTER = 0,
54 SCL_COEF_LUMA_HORZ_FILTER = 1,
55 SCL_COEF_CHROMA_VERT_FILTER = 2,
56 SCL_COEF_CHROMA_HORZ_FILTER = 3,
57 SCL_COEF_ALPHA_VERT_FILTER = 4,
58 SCL_COEF_ALPHA_HORZ_FILTER = 5
59};
60
61enum dscl_autocal_mode {
62 AUTOCAL_MODE_OFF = 0,
63
64 /* Autocal calculate the scaling ratio and initial phase and the
65 * DSCL_MODE_SEL must be set to 1
66 */
67 AUTOCAL_MODE_AUTOSCALE = 1,
68 /* Autocal perform auto centering without replication and the
69 * DSCL_MODE_SEL must be set to 0
70 */
71 AUTOCAL_MODE_AUTOCENTER = 2,
72 /* Autocal perform auto centering and auto replication and the
73 * DSCL_MODE_SEL must be set to 0
74 */
75 AUTOCAL_MODE_AUTOREPLICATE = 3
76};
77
78enum dscl_mode_sel {
79 DSCL_MODE_SCALING_444_BYPASS = 0,
80 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
81 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
82 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
83 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
84 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
85 DSCL_MODE_DSCL_BYPASS = 6
86};
87
88static void dpp1_dscl_set_overscan(
89 struct dcn10_dpp *dpp,
90 const struct scaler_data *data)
91{
92 uint32_t left = data->recout.x;
93 uint32_t top = data->recout.y;
94
95 int right = data->h_active - data->recout.x - data->recout.width;
96 int bottom = data->v_active - data->recout.y - data->recout.height;
97
98 if (right < 0) {
99 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 99); do {
} while (0); } while (0);
100 right = 0;
101 }
102 if (bottom < 0) {
103 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 103); do
{} while (0); } while (0);
104 bottom = 0;
105 }
106
107 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_EXT_OVERSCAN_LEFT_RIGHT
, 0, 2, dpp->tf_shift->EXT_OVERSCAN_LEFT, dpp->tf_mask
->EXT_OVERSCAN_LEFT, left, dpp->tf_shift->EXT_OVERSCAN_RIGHT
, dpp->tf_mask->EXT_OVERSCAN_RIGHT, right)
108 EXT_OVERSCAN_LEFT, left,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_EXT_OVERSCAN_LEFT_RIGHT
, 0, 2, dpp->tf_shift->EXT_OVERSCAN_LEFT, dpp->tf_mask
->EXT_OVERSCAN_LEFT, left, dpp->tf_shift->EXT_OVERSCAN_RIGHT
, dpp->tf_mask->EXT_OVERSCAN_RIGHT, right)
109 EXT_OVERSCAN_RIGHT, right)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_EXT_OVERSCAN_LEFT_RIGHT
, 0, 2, dpp->tf_shift->EXT_OVERSCAN_LEFT, dpp->tf_mask
->EXT_OVERSCAN_LEFT, left, dpp->tf_shift->EXT_OVERSCAN_RIGHT
, dpp->tf_mask->EXT_OVERSCAN_RIGHT, right);
110
111 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_EXT_OVERSCAN_TOP_BOTTOM
, 0, 2, dpp->tf_shift->EXT_OVERSCAN_BOTTOM, dpp->tf_mask
->EXT_OVERSCAN_BOTTOM, bottom, dpp->tf_shift->EXT_OVERSCAN_TOP
, dpp->tf_mask->EXT_OVERSCAN_TOP, top)
112 EXT_OVERSCAN_BOTTOM, bottom,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_EXT_OVERSCAN_TOP_BOTTOM
, 0, 2, dpp->tf_shift->EXT_OVERSCAN_BOTTOM, dpp->tf_mask
->EXT_OVERSCAN_BOTTOM, bottom, dpp->tf_shift->EXT_OVERSCAN_TOP
, dpp->tf_mask->EXT_OVERSCAN_TOP, top)
113 EXT_OVERSCAN_TOP, top)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_EXT_OVERSCAN_TOP_BOTTOM
, 0, 2, dpp->tf_shift->EXT_OVERSCAN_BOTTOM, dpp->tf_mask
->EXT_OVERSCAN_BOTTOM, bottom, dpp->tf_shift->EXT_OVERSCAN_TOP
, dpp->tf_mask->EXT_OVERSCAN_TOP, top);
114}
115
116static void dpp1_dscl_set_otg_blank(
117 struct dcn10_dpp *dpp, const struct scaler_data *data)
118{
119 uint32_t h_blank_start = data->h_active;
120 uint32_t h_blank_end = 0;
121 uint32_t v_blank_start = data->v_active;
122 uint32_t v_blank_end = 0;
123
124 REG_SET_2(OTG_H_BLANK, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->OTG_H_BLANK
, 0, 2, dpp->tf_shift->OTG_H_BLANK_START, dpp->tf_mask
->OTG_H_BLANK_START, h_blank_start, dpp->tf_shift->OTG_H_BLANK_END
, dpp->tf_mask->OTG_H_BLANK_END, h_blank_end)
125 OTG_H_BLANK_START, h_blank_start,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->OTG_H_BLANK
, 0, 2, dpp->tf_shift->OTG_H_BLANK_START, dpp->tf_mask
->OTG_H_BLANK_START, h_blank_start, dpp->tf_shift->OTG_H_BLANK_END
, dpp->tf_mask->OTG_H_BLANK_END, h_blank_end)
126 OTG_H_BLANK_END, h_blank_end)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->OTG_H_BLANK
, 0, 2, dpp->tf_shift->OTG_H_BLANK_START, dpp->tf_mask
->OTG_H_BLANK_START, h_blank_start, dpp->tf_shift->OTG_H_BLANK_END
, dpp->tf_mask->OTG_H_BLANK_END, h_blank_end);
127
128 REG_SET_2(OTG_V_BLANK, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->OTG_V_BLANK
, 0, 2, dpp->tf_shift->OTG_V_BLANK_START, dpp->tf_mask
->OTG_V_BLANK_START, v_blank_start, dpp->tf_shift->OTG_V_BLANK_END
, dpp->tf_mask->OTG_V_BLANK_END, v_blank_end)
129 OTG_V_BLANK_START, v_blank_start,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->OTG_V_BLANK
, 0, 2, dpp->tf_shift->OTG_V_BLANK_START, dpp->tf_mask
->OTG_V_BLANK_START, v_blank_start, dpp->tf_shift->OTG_V_BLANK_END
, dpp->tf_mask->OTG_V_BLANK_END, v_blank_end)
130 OTG_V_BLANK_END, v_blank_end)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->OTG_V_BLANK
, 0, 2, dpp->tf_shift->OTG_V_BLANK_START, dpp->tf_mask
->OTG_V_BLANK_START, v_blank_start, dpp->tf_shift->OTG_V_BLANK_END
, dpp->tf_mask->OTG_V_BLANK_END, v_blank_end);
131}
132
133static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
134{
135 if (depth == LB_PIXEL_DEPTH_30BPP)
136 return 0; /* 10 bpc */
137 else if (depth == LB_PIXEL_DEPTH_24BPP)
138 return 1; /* 8 bpc */
139 else if (depth == LB_PIXEL_DEPTH_18BPP)
140 return 2; /* 6 bpc */
141 else if (depth == LB_PIXEL_DEPTH_36BPP)
142 return 3; /* 12 bpc */
143 else {
144 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c"
, 144); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
145 return -1; /* Unsupported */
146 }
147}
148
149static bool_Bool dpp1_dscl_is_video_format(enum pixel_format format)
150{
151 if (format >= PIXEL_FORMAT_VIDEO_BEGIN
152 && format <= PIXEL_FORMAT_VIDEO_END)
153 return true1;
154 else
155 return false0;
156}
157
158static bool_Bool dpp1_dscl_is_420_format(enum pixel_format format)
159{
160 if (format == PIXEL_FORMAT_420BPP8 ||
161 format == PIXEL_FORMAT_420BPP10)
162 return true1;
163 else
164 return false0;
165}
166
167static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
168 struct dpp *dpp_base,
169 const struct scaler_data *data,
170 bool_Bool dbg_always_scale)
171{
172 const long long one = dc_fixpt_one.value;
173
174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
175 /* DSCL is processing data in fixed format */
176 if (data->format == PIXEL_FORMAT_FP16)
177 return DSCL_MODE_DSCL_BYPASS;
178 }
179
180 if (data->ratios.horz.value == one
181 && data->ratios.vert.value == one
182 && data->ratios.horz_c.value == one
183 && data->ratios.vert_c.value == one
184 && !dbg_always_scale)
185 return DSCL_MODE_SCALING_444_BYPASS;
186
187 if (!dpp1_dscl_is_420_format(data->format)) {
188 if (dpp1_dscl_is_video_format(data->format))
189 return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
190 else
191 return DSCL_MODE_SCALING_444_RGB_ENABLE;
192 }
193 if (data->ratios.horz.value == one && data->ratios.vert.value == one)
194 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
195 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
196 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
197
198 return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
199}
200
201static void dpp1_dscl_set_lb(
202 struct dcn10_dpp *dpp,
203 const struct line_buffer_params *lb_params,
204 enum lb_memory_config mem_size_config)
205{
206 /* LB */
207 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
208 /* DSCL caps: pixel data processed in fixed format */
209 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
210 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
211
212 REG_SET_7(LB_DATA_FORMAT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
213 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
214 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
215 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
216 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
217 DITHER_EN, 0, /* Dithering enable: Disabled */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
218 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
219 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en); /* Alpha enable */
220 }
221 else {
222 /* DSCL caps: pixel data processed in float format */
223 REG_SET_2(LB_DATA_FORMAT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 2, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->
INTERLEAVE_EN, lb_params->interleave_en, dpp->tf_shift->
LB_DATA_FORMAT__ALPHA_EN, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN
, lb_params->alpha_en)
224 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 2, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->
INTERLEAVE_EN, lb_params->interleave_en, dpp->tf_shift->
LB_DATA_FORMAT__ALPHA_EN, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN
, lb_params->alpha_en)
225 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 2, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->
INTERLEAVE_EN, lb_params->interleave_en, dpp->tf_shift->
LB_DATA_FORMAT__ALPHA_EN, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN
, lb_params->alpha_en); /* Alpha enable */
226 }
227
228 REG_SET_2(LB_MEMORY_CTRL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_MEMORY_CTRL
, 0, 2, dpp->tf_shift->MEMORY_CONFIG, dpp->tf_mask->
MEMORY_CONFIG, mem_size_config, dpp->tf_shift->LB_MAX_PARTITIONS
, dpp->tf_mask->LB_MAX_PARTITIONS, 63)
229 MEMORY_CONFIG, mem_size_config,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_MEMORY_CTRL
, 0, 2, dpp->tf_shift->MEMORY_CONFIG, dpp->tf_mask->
MEMORY_CONFIG, mem_size_config, dpp->tf_shift->LB_MAX_PARTITIONS
, dpp->tf_mask->LB_MAX_PARTITIONS, 63)
230 LB_MAX_PARTITIONS, 63)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_MEMORY_CTRL
, 0, 2, dpp->tf_shift->MEMORY_CONFIG, dpp->tf_mask->
MEMORY_CONFIG, mem_size_config, dpp->tf_shift->LB_MAX_PARTITIONS
, dpp->tf_mask->LB_MAX_PARTITIONS, 63);
231}
232
233static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
234{
235 if (taps == 8)
236 return get_filter_8tap_64p(ratio);
237 else if (taps == 7)
238 return get_filter_7tap_64p(ratio);
239 else if (taps == 6)
240 return get_filter_6tap_64p(ratio);
241 else if (taps == 5)
242 return get_filter_5tap_64p(ratio);
243 else if (taps == 4)
244 return get_filter_4tap_64p(ratio);
245 else if (taps == 3)
246 return get_filter_3tap_64p(ratio);
247 else if (taps == 2)
248 return get_filter_2tap_64p();
249 else if (taps == 1)
250 return NULL((void *)0);
251 else {
252 /* should never happen, bug */
253 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 253); do
{} while (0); } while (0);
254 return NULL((void *)0);
255 }
256}
257
258static void dpp1_dscl_set_scaler_filter(
259 struct dcn10_dpp *dpp,
260 uint32_t taps,
261 enum dcn10_coef_filter_type_sel filter_type,
262 const uint16_t *filter)
263{
264 const int tap_pairs = (taps + 1) / 2;
265 int phase;
266 int pair;
267 uint16_t odd_coef, even_coef;
268
269 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type)
270 SCL_COEF_RAM_TAP_PAIR_IDX, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type)
271 SCL_COEF_RAM_PHASE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type)
272 SCL_COEF_RAM_FILTER_TYPE, filter_type)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type);
273
274 for (phase = 0; phase < (NUM_PHASES64 / 2 + 1); phase++) {
275 for (pair = 0; pair < tap_pairs; pair++) {
276 even_coef = filter[phase * taps + 2 * pair];
277 if ((pair * 2 + 1) < taps)
278 odd_coef = filter[phase * taps + 2 * pair + 1];
279 else
280 odd_coef = 0;
281
282 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
283 /* Even tap coefficient (bits 1:0 fixed to 0) */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
284 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
285 /* Write/read control for even coefficient */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
286 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
287 /* Odd tap coefficient (bits 1:0 fixed to 0) */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
288 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
289 /* Write/read control for odd coefficient */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
290 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1);
291 }
292 }
293
294}
295
296static void dpp1_dscl_set_scl_filter(
297 struct dcn10_dpp *dpp,
298 const struct scaler_data *scl_data,
299 bool_Bool chroma_coef_mode)
300{
301 bool_Bool h_2tap_hardcode_coef_en = false0;
302 bool_Bool v_2tap_hardcode_coef_en = false0;
303 bool_Bool h_2tap_sharp_en = false0;
304 bool_Bool v_2tap_sharp_en = false0;
305 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
306 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
307 bool_Bool coef_ram_current;
308 const uint16_t *filter_h = NULL((void *)0);
309 const uint16_t *filter_v = NULL((void *)0);
310 const uint16_t *filter_h_c = NULL((void *)0);
311 const uint16_t *filter_v_c = NULL((void *)0);
312
313 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
314 && scl_data->taps.h_taps_c < 3
315 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
316 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
317 && scl_data->taps.v_taps_c < 3
318 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
319
320 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
321 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
322
323 REG_UPDATE_6(DSCL_2TAP_CONTROL,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
324 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
325 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
326 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
327 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
328 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
329 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
);
330
331 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
332 bool_Bool filter_updated = false0;
333
334 filter_h = dpp1_dscl_get_filter_coeffs_64p(
335 scl_data->taps.h_taps, scl_data->ratios.horz);
336 filter_v = dpp1_dscl_get_filter_coeffs_64p(
337 scl_data->taps.v_taps, scl_data->ratios.vert);
338
339 filter_updated = (filter_h && (filter_h != dpp->filter_h))
340 || (filter_v && (filter_v != dpp->filter_v));
341
342 if (chroma_coef_mode) {
343 filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
344 scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
345 filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
346 scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
347 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
348 || (filter_v_c && (filter_v_c != dpp->filter_v_c));
349 }
350
351 if (filter_updated) {
352 uint32_t scl_mode = REG_READ(SCL_MODE)dm_read_reg_func(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, __func__);
353
354 if (!h_2tap_hardcode_coef_en && filter_h) {
355 dpp1_dscl_set_scaler_filter(
356 dpp, scl_data->taps.h_taps,
357 SCL_COEF_LUMA_HORZ_FILTER, filter_h);
358 }
359 dpp->filter_h = filter_h;
360 if (!v_2tap_hardcode_coef_en && filter_v) {
361 dpp1_dscl_set_scaler_filter(
362 dpp, scl_data->taps.v_taps,
363 SCL_COEF_LUMA_VERT_FILTER, filter_v);
364 }
365 dpp->filter_v = filter_v;
366 if (chroma_coef_mode) {
367 if (!h_2tap_hardcode_coef_en && filter_h_c) {
368 dpp1_dscl_set_scaler_filter(
369 dpp, scl_data->taps.h_taps_c,
370 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
371 }
372 if (!v_2tap_hardcode_coef_en && filter_v_c) {
373 dpp1_dscl_set_scaler_filter(
374 dpp, scl_data->taps.v_taps_c,
375 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
376 }
377 }
378 dpp->filter_h_c = filter_h_c;
379 dpp->filter_v_c = filter_v_c;
380
381 coef_ram_current = get_reg_field_value_ex(
382 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
383 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
384
385 /* Swap coefficient RAM and set chroma coefficient mode */
386 REG_SET_2(SCL_MODE, scl_mode,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, scl_mode, 2, dpp->tf_shift->SCL_COEF_RAM_SELECT, dpp->
tf_mask->SCL_COEF_RAM_SELECT, !coef_ram_current, dpp->tf_shift
->SCL_CHROMA_COEF_MODE, dpp->tf_mask->SCL_CHROMA_COEF_MODE
, chroma_coef_mode)
387 SCL_COEF_RAM_SELECT, !coef_ram_current,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, scl_mode, 2, dpp->tf_shift->SCL_COEF_RAM_SELECT, dpp->
tf_mask->SCL_COEF_RAM_SELECT, !coef_ram_current, dpp->tf_shift
->SCL_CHROMA_COEF_MODE, dpp->tf_mask->SCL_CHROMA_COEF_MODE
, chroma_coef_mode)
388 SCL_CHROMA_COEF_MODE, chroma_coef_mode)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, scl_mode, 2, dpp->tf_shift->SCL_COEF_RAM_SELECT, dpp->
tf_mask->SCL_COEF_RAM_SELECT, !coef_ram_current, dpp->tf_shift
->SCL_CHROMA_COEF_MODE, dpp->tf_mask->SCL_CHROMA_COEF_MODE
, chroma_coef_mode);
389 }
390 }
391}
392
393static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
394{
395 if (depth == LB_PIXEL_DEPTH_30BPP)
396 return 10;
397 else if (depth == LB_PIXEL_DEPTH_24BPP)
398 return 8;
399 else if (depth == LB_PIXEL_DEPTH_18BPP)
400 return 6;
401 else if (depth == LB_PIXEL_DEPTH_36BPP)
402 return 12;
403 else {
404 BREAK_TO_DEBUGGER()do { __drm_dbg(DRM_UT_DRIVER, "%s():%d\n", __func__, 404); do
{} while (0); } while (0);
405 return -1; /* Unsupported */
406 }
407}
408
409void dpp1_dscl_calc_lb_num_partitions(
410 const struct scaler_data *scl_data,
411 enum lb_memory_config lb_config,
412 int *num_part_y,
413 int *num_part_c)
414{
415 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,
416 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
417
418 int line_size = scl_data->viewport.width < scl_data->recout.width ?
1
Assuming 'scl_data->viewport.width' is >= 'scl_data->recout.width'
→
2
←
'?' condition is false
→
419 scl_data->viewport.width : scl_data->recout.width;
420 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
3
←
Assuming 'scl_data->viewport_c.width' is < 'scl_data->recout.width'
→
4
←
'?' condition is true
→
421 scl_data->viewport_c.width : scl_data->recout.width;
422
423 if (line_size == 0)
5
←
Assuming 'line_size' is equal to 0
→
6
←
Taking true branch
→
424 line_size = 1;
425
426 if (line_size_c == 0)
7
←
Assuming 'line_size_c' is not equal to 0
→
8
←
Taking false branch
→
427 line_size_c = 1;
428
429
430 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
431 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
9
←
The value 0 is assigned to 'memory_line_size_y'
→
432 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
433 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
434
435 if (lb_config == LB_MEMORY_CONFIG_1) {
10
←
Assuming 'lb_config' is equal to LB_MEMORY_CONFIG_1
→
11
←
Taking true branch
→
436 lb_memory_size = 816;
437 lb_memory_size_c = 816;
438 lb_memory_size_a = 984;
439 } else if (lb_config == LB_MEMORY_CONFIG_2) {
440 lb_memory_size = 1088;
441 lb_memory_size_c = 1088;
442 lb_memory_size_a = 1312;
443 } else if (lb_config == LB_MEMORY_CONFIG_3) {
444 /* 420 mode: using 3rd mem from Y, Cr and Cb */
445 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
446 lb_memory_size_c = 816 + 1088;
447 lb_memory_size_a = 984 + 1312 + 456;
448 } else {
449 lb_memory_size = 816 + 1088 + 848;
450 lb_memory_size_c = 816 + 1088 + 848;
451 lb_memory_size_a = 984 + 1312 + 456;
452 }
453 *num_part_y = lb_memory_size / memory_line_size_y;
12
←
Division by zero
454 *num_part_c = lb_memory_size_c / memory_line_size_c;
455 num_partitions_a = lb_memory_size_a / memory_line_size_a;
456
457 if (scl_data->lb_params.alpha_en
458 && (num_partitions_a < *num_part_y))
459 *num_part_y = num_partitions_a;
460
461 if (*num_part_y > 64)
462 *num_part_y = 64;
463 if (*num_part_c > 64)
464 *num_part_c = 64;
465
466}
467
468bool_Bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
469{
470 if (ceil_vratio > 2)
471 return vtaps <= (num_partitions - ceil_vratio + 2);
472 else
473 return vtaps <= num_partitions;
474}
475
476/*find first match configuration which meets the min required lb size*/
477static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
478 const struct scaler_data *scl_data)
479{
480 int num_part_y, num_part_c;
481 int vtaps = scl_data->taps.v_taps;
482 int vtaps_c = scl_data->taps.v_taps_c;
483 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
484 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
485
486 if (dpp->base.ctx->dc->debug.use_max_lb) {
487 if (scl_data->format == PIXEL_FORMAT_420BPP8
488 || scl_data->format == PIXEL_FORMAT_420BPP10)
489 return LB_MEMORY_CONFIG_3;
490 return LB_MEMORY_CONFIG_0;
491 }
492
493 dpp->base.caps->dscl_calc_lb_num_partitions(
494 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
495
496 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
497 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
498 return LB_MEMORY_CONFIG_1;
499
500 dpp->base.caps->dscl_calc_lb_num_partitions(
501 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
502
503 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
504 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
505 return LB_MEMORY_CONFIG_2;
506
507 if (scl_data->format == PIXEL_FORMAT_420BPP8
508 || scl_data->format == PIXEL_FORMAT_420BPP10) {
509 dpp->base.caps->dscl_calc_lb_num_partitions(
510 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
511
512 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
513 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
514 return LB_MEMORY_CONFIG_3;
515 }
516
517 dpp->base.caps->dscl_calc_lb_num_partitions(
518 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
519
520 /*Ensure we can support the requested number of vtaps*/
521 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)do { if (({ static int __warned; int __ret = !!(!(dpp1_dscl_is_lb_conf_valid
(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid
(ceil_vratio_c, num_part_c, vtaps_c))); if (__ret && !
__warned) { printf("WARNING %s failed at %s:%d\n", "!(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c"
, 522); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0)
522 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))do { if (({ static int __warned; int __ret = !!(!(dpp1_dscl_is_lb_conf_valid
(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid
(ceil_vratio_c, num_part_c, vtaps_c))); if (__ret && !
__warned) { printf("WARNING %s failed at %s:%d\n", "!(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c"
, 522); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
523
524 return LB_MEMORY_CONFIG_0;
525}
526
527void dpp1_dscl_set_scaler_auto_scale(
528 struct dpp *dpp_base,
529 const struct scaler_data *scl_data)
530{
531 enum lb_memory_config lb_config;
532 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base)({ const __typeof( ((struct dcn10_dpp *)0)->base ) *__mptr
= (dpp_base); (struct dcn10_dpp *)( (char *)__mptr - __builtin_offsetof
(struct dcn10_dpp, base) );});
533 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
534 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
535 bool_Bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
536 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
537
538 dpp1_dscl_set_overscan(dpp, scl_data);
539
540 dpp1_dscl_set_otg_blank(dpp, scl_data);
541
542 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, 1, dpp->tf_shift->DSCL_MODE, dpp->tf_mask->DSCL_MODE
, dscl_mode);
543
544 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
545 return;
546
547 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
548 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
549
550 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
551 return;
552
553 /* TODO: v_min */
554 REG_SET_3(DSCL_AUTOCAL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
555 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
556 AUTOCAL_NUM_PIPE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
557 AUTOCAL_PIPE_ID, 0)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0);
558
559 /* Black offsets */
560 if (ycbcr)
561 REG_SET_2(SCL_BLACK_OFFSET, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000)
562 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000)
563 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000);
564 else
565
566 REG_SET_2(SCL_BLACK_OFFSET, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0)
567 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0)
568 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0);
569
570 REG_SET_4(SCL_TAP_CONTROL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
571 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
572 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
573 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
574 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
575
576 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
577}
578
579
580static void dpp1_dscl_set_manual_ratio_init(
581 struct dcn10_dpp *dpp, const struct scaler_data *data)
582{
583 uint32_t init_frac = 0;
584 uint32_t init_int = 0;
585
586 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO, dpp->tf_mask
->SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) <<
5)
587 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO, dpp->tf_mask
->SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) <<
5);
588
589 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO, dpp->tf_mask
->SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) <<
5)
590 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO, dpp->tf_mask
->SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) <<
5);
591
592 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO_C, dpp->tf_mask
->SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c
) << 5)
593 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO_C, dpp->tf_mask
->SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c
) << 5);
594
595 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO_C, dpp->tf_mask
->SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c
) << 5)
596 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO_C, dpp->tf_mask
->SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c
) << 5);
597
598 /*
599 * 0.24 format for fraction, first five bits zeroed
600 */
601 init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
602 init_int = dc_fixpt_floor(data->inits.h);
603 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC, dpp->tf_mask
->SCL_H_INIT_FRAC, init_frac, dpp->tf_shift->SCL_H_INIT_INT
, dpp->tf_mask->SCL_H_INIT_INT, init_int)
604 SCL_H_INIT_FRAC, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC, dpp->tf_mask
->SCL_H_INIT_FRAC, init_frac, dpp->tf_shift->SCL_H_INIT_INT
, dpp->tf_mask->SCL_H_INIT_INT, init_int)
605 SCL_H_INIT_INT, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC, dpp->tf_mask
->SCL_H_INIT_FRAC, init_frac, dpp->tf_shift->SCL_H_INIT_INT
, dpp->tf_mask->SCL_H_INIT_INT, init_int);
606
607 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
608 init_int = dc_fixpt_floor(data->inits.h_c);
609 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC_C, dpp->tf_mask
->SCL_H_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_H_INIT_INT_C
, dpp->tf_mask->SCL_H_INIT_INT_C, init_int)
610 SCL_H_INIT_FRAC_C, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC_C, dpp->tf_mask
->SCL_H_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_H_INIT_INT_C
, dpp->tf_mask->SCL_H_INIT_INT_C, init_int)
611 SCL_H_INIT_INT_C, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC_C, dpp->tf_mask
->SCL_H_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_H_INIT_INT_C
, dpp->tf_mask->SCL_H_INIT_INT_C, init_int);
612
613 init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
614 init_int = dc_fixpt_floor(data->inits.v);
615 REG_SET_2(SCL_VERT_FILTER_INIT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC, dpp->tf_mask
->SCL_V_INIT_FRAC, init_frac, dpp->tf_shift->SCL_V_INIT_INT
, dpp->tf_mask->SCL_V_INIT_INT, init_int)
616 SCL_V_INIT_FRAC, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC, dpp->tf_mask
->SCL_V_INIT_FRAC, init_frac, dpp->tf_shift->SCL_V_INIT_INT
, dpp->tf_mask->SCL_V_INIT_INT, init_int)
617 SCL_V_INIT_INT, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC, dpp->tf_mask
->SCL_V_INIT_FRAC, init_frac, dpp->tf_shift->SCL_V_INIT_INT
, dpp->tf_mask->SCL_V_INIT_INT, init_int);
618
619 if (REG(SCL_VERT_FILTER_INIT_BOT)dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT) {
620 init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5;
621 init_int = dc_fixpt_floor(data->inits.v_bot);
622 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT
, dpp->tf_mask->SCL_V_INIT_INT_BOT, init_int)
623 SCL_V_INIT_FRAC_BOT, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT
, dpp->tf_mask->SCL_V_INIT_INT_BOT, init_int)
624 SCL_V_INIT_INT_BOT, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT
, dpp->tf_mask->SCL_V_INIT_INT_BOT, init_int);
625 }
626
627 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
628 init_int = dc_fixpt_floor(data->inits.v_c);
629 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_C, dpp->tf_mask
->SCL_V_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_C
, dpp->tf_mask->SCL_V_INIT_INT_C, init_int)
630 SCL_V_INIT_FRAC_C, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_C, dpp->tf_mask
->SCL_V_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_C
, dpp->tf_mask->SCL_V_INIT_INT_C, init_int)
631 SCL_V_INIT_INT_C, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_C, dpp->tf_mask
->SCL_V_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_C
, dpp->tf_mask->SCL_V_INIT_INT_C, init_int);
632
633 if (REG(SCL_VERT_FILTER_INIT_BOT_C)dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C) {
634 init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5;
635 init_int = dc_fixpt_floor(data->inits.v_c_bot);
636 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT_C, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT_C
, dpp->tf_mask->SCL_V_INIT_INT_BOT_C, init_int)
637 SCL_V_INIT_FRAC_BOT_C, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT_C, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT_C
, dpp->tf_mask->SCL_V_INIT_INT_BOT_C, init_int)
638 SCL_V_INIT_INT_BOT_C, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT_C, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT_C
, dpp->tf_mask->SCL_V_INIT_INT_BOT_C, init_int);
639 }
640}
641
642
643
644static void dpp1_dscl_set_recout(
645 struct dcn10_dpp *dpp, const struct rect *recout)
646{
647 int visual_confirm_on = 0;
648 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
649 visual_confirm_on = 1;
650
651 REG_SET_2(RECOUT_START, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
652 /* First pixel of RECOUT */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
653 RECOUT_START_X, recout->x,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
654 /* First line of RECOUT */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
655 RECOUT_START_Y, recout->y)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y);
656
657 REG_SET_2(RECOUT_SIZE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 4 * (dpp->base.inst + 1))
658 /* Number of RECOUT horizontal pixels */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 4 * (dpp->base.inst + 1))
659 RECOUT_WIDTH, recout->width,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 4 * (dpp->base.inst + 1))
660 /* Number of RECOUT vertical lines */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 4 * (dpp->base.inst + 1))
661 RECOUT_HEIGHT, recout->heightgeneric_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 4 * (dpp->base.inst + 1))
662 - visual_confirm_on * 4 * (dpp->base.inst + 1))generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 4 * (dpp->base.inst + 1));
663}
664
665/* Main function to program scaler and line buffer in manual scaling mode */
666void dpp1_dscl_set_scaler_manual_scale(
667 struct dpp *dpp_base,
668 const struct scaler_data *scl_data)
669{
670 enum lb_memory_config lb_config;
671 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base)({ const __typeof( ((struct dcn10_dpp *)0)->base ) *__mptr
= (dpp_base); (struct dcn10_dpp *)( (char *)__mptr - __builtin_offsetof
(struct dcn10_dpp, base) );});
672 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
673 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
674 bool_Bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
675 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
676
677 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data))__builtin_memcmp((&dpp->scl_data), (scl_data), (sizeof
(*scl_data))) == 0)
678 return;
679
680 PERF_TRACE()trace_amdgpu_dc_performance(dpp->base.ctx->perf_trace->
read_count, dpp->base.ctx->perf_trace->write_count, &
dpp->base.ctx->perf_trace->last_entry_read, &dpp
->base.ctx->perf_trace->last_entry_write, __func__, 680
);
681
682 dpp->scl_data = *scl_data;
683
684 /* Autocal off */
685 REG_SET_3(DSCL_AUTOCAL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
686 AUTOCAL_MODE, AUTOCAL_MODE_OFF,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
687 AUTOCAL_NUM_PIPE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
688 AUTOCAL_PIPE_ID, 0)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0);
689
690 /* Recout */
691 dpp1_dscl_set_recout(dpp, &scl_data->recout);
692
693 /* MPC Size */
694 REG_SET_2(MPC_SIZE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
695 /* Number of horizontal pixels of MPC */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
696 MPC_WIDTH, scl_data->h_active,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
697 /* Number of vertical lines of MPC */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
698 MPC_HEIGHT, scl_data->v_active)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active);
699
700 /* SCL mode */
701 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, 1, dpp->tf_shift->DSCL_MODE, dpp->tf_mask->DSCL_MODE
, dscl_mode);
702
703 if (dscl_mode == DSCL_MODE_DSCL_BYPASS)
704 return;
705
706 /* LB */
707 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
708 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
709
710 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
711 return;
712
713 /* Black offsets */
714 if (REG(SCL_BLACK_OFFSET)dpp->tf_regs->SCL_BLACK_OFFSET) {
715 if (ycbcr)
716 REG_SET_2(SCL_BLACK_OFFSET, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000)
717 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000)
718 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000);
719 else
720
721 REG_SET_2(SCL_BLACK_OFFSET, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0)
722 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0)
723 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0);
724 }
725
726 /* Manually calculate scale ratio and init values */
727 dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
728
729 /* HTaps/VTaps */
730 REG_SET_4(SCL_TAP_CONTROL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
731 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
732 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
733 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
734 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
735
736 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
737 PERF_TRACE()trace_amdgpu_dc_performance(dpp->base.ctx->perf_trace->
read_count, dpp->base.ctx->perf_trace->write_count, &
dpp->base.ctx->perf_trace->last_entry_read, &dpp
->base.ctx->perf_trace->last_entry_write, __func__, 737
);
738}