File: | dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c |
Warning: | line 594, column 60 Division by zero |
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1 | /* | |||
2 | * Copyright 2020 Advanced Micro Devices, Inc. | |||
3 | * | |||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
5 | * copy of this software and associated documentation files (the "Software"), | |||
6 | * to deal in the Software without restriction, including without limitation | |||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
8 | * and/or sell copies of the Software, and to permit persons to whom the | |||
9 | * Software is furnished to do so, subject to the following conditions: | |||
10 | * | |||
11 | * The above copyright notice and this permission notice shall be included in | |||
12 | * all copies or substantial portions of the Software. | |||
13 | * | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
20 | * OTHER DEALINGS IN THE SOFTWARE. | |||
21 | * | |||
22 | * Authors: AMD | |||
23 | * | |||
24 | */ | |||
25 | ||||
26 | #ifdef CONFIG_DRM_AMD_DC_DCN3_01 | |||
27 | ||||
28 | #include "../display_mode_lib.h" | |||
29 | #include "../display_mode_vba.h" | |||
30 | #include "../dml_inline_defs.h" | |||
31 | #include "display_rq_dlg_calc_30.h" | |||
32 | ||||
33 | static bool_Bool is_dual_plane(enum source_format_class source_format) | |||
34 | { | |||
35 | bool_Bool ret_val = 0; | |||
36 | ||||
37 | if ((source_format == dm_420_12) || (source_format == dm_420_8) || (source_format == dm_420_10) || (source_format == dm_rgbe_alpha)) | |||
38 | ret_val = 1; | |||
39 | ||||
40 | return ret_val; | |||
41 | } | |||
42 | ||||
43 | static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, | |||
44 | double refclk_freq_in_mhz, | |||
45 | double pclk_freq_in_mhz, | |||
46 | unsigned int odm_combine, | |||
47 | unsigned int recout_width, | |||
48 | unsigned int hactive, | |||
49 | double vratio, | |||
50 | double hscale_pixel_rate, | |||
51 | unsigned int delivery_width, | |||
52 | unsigned int req_per_swath_ub) | |||
53 | { | |||
54 | double refcyc_per_delivery = 0.0; | |||
55 | ||||
56 | if (vratio <= 1.0) { | |||
57 | if (odm_combine) | |||
58 | refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)((unsigned int)odm_combine*2) | |||
59 | * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) | |||
60 | / pclk_freq_in_mhz / (double)req_per_swath_ub; | |||
61 | else | |||
62 | refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)recout_width | |||
63 | / pclk_freq_in_mhz / (double)req_per_swath_ub; | |||
64 | } else { | |||
65 | refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)delivery_width | |||
66 | / (double)hscale_pixel_rate / (double)req_per_swath_ub; | |||
67 | } | |||
68 | ||||
69 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; | |||
70 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; | |||
71 | dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width){do { } while(0); }; | |||
72 | dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio){do { } while(0); }; | |||
73 | dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub){do { } while(0); }; | |||
74 | dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery){do { } while(0); }; | |||
75 | ||||
76 | return refcyc_per_delivery; | |||
77 | ||||
78 | } | |||
79 | ||||
80 | static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) | |||
81 | { | |||
82 | if (tile_size == dm_256k_tile) | |||
83 | return (256 * 1024); | |||
84 | else if (tile_size == dm_64k_tile) | |||
85 | return (64 * 1024); | |||
86 | else | |||
87 | return (4 * 1024); | |||
88 | } | |||
89 | ||||
90 | static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, | |||
91 | display_data_rq_regs_st *rq_regs, | |||
92 | const display_data_rq_sizing_params_st rq_sizing) | |||
93 | { | |||
94 | dml_print("DML_DLG: %s: rq_sizing param\n", __func__){do { } while(0); }; | |||
95 | print__data_rq_sizing_params_st(mode_lib, rq_sizing); | |||
96 | ||||
97 | rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; | |||
98 | ||||
99 | if (rq_sizing.min_chunk_bytes == 0) | |||
100 | rq_regs->min_chunk_size = 0; | |||
101 | else | |||
102 | rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; | |||
103 | ||||
104 | rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; | |||
105 | if (rq_sizing.min_meta_chunk_bytes == 0) | |||
106 | rq_regs->min_meta_chunk_size = 0; | |||
107 | else | |||
108 | rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; | |||
109 | ||||
110 | rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; | |||
111 | rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; | |||
112 | } | |||
113 | ||||
114 | static void extract_rq_regs(struct display_mode_lib *mode_lib, | |||
115 | display_rq_regs_st *rq_regs, | |||
116 | const display_rq_params_st rq_param) | |||
117 | { | |||
118 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; | |||
119 | unsigned int detile_buf_plane1_addr = 0; | |||
120 | ||||
121 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); | |||
122 | ||||
123 | rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), | |||
124 | 1) - 3; | |||
125 | ||||
126 | if (rq_param.yuv420) { | |||
127 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); | |||
128 | rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), | |||
129 | 1) - 3; | |||
130 | } | |||
131 | ||||
132 | rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); | |||
133 | rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); | |||
134 | ||||
135 | // FIXME: take the max between luma, chroma chunk size? | |||
136 | // okay for now, as we are setting chunk_bytes to 8kb anyways | |||
137 | if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024 || (rq_param.yuv420 && rq_param.sizing.rq_c.chunk_bytes >= 32 * 1024)) { //32kb | |||
138 | rq_regs->drq_expansion_mode = 0; | |||
139 | } else { | |||
140 | rq_regs->drq_expansion_mode = 2; | |||
141 | } | |||
142 | rq_regs->prq_expansion_mode = 1; | |||
143 | rq_regs->mrq_expansion_mode = 1; | |||
144 | rq_regs->crq_expansion_mode = 1; | |||
145 | ||||
146 | if (rq_param.yuv420) { | |||
147 | if ((double)rq_param.misc.rq_l.stored_swath_bytes | |||
148 | / (double)rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { | |||
149 | detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma | |||
150 | } else { | |||
151 | detile_buf_plane1_addr = dml_round_to_multiple((unsigned int)((2.0 * detile_buf_size_in_bytes) / 3.0), | |||
152 | 256, | |||
153 | 0) / 64.0; // 2/3 to chroma | |||
154 | } | |||
155 | } | |||
156 | rq_regs->plane1_base_address = detile_buf_plane1_addr; | |||
157 | } | |||
158 | ||||
159 | static void handle_det_buf_split(struct display_mode_lib *mode_lib, | |||
160 | display_rq_params_st *rq_param, | |||
161 | const display_pipe_source_params_st pipe_src_param) | |||
162 | { | |||
163 | unsigned int total_swath_bytes = 0; | |||
164 | unsigned int swath_bytes_l = 0; | |||
165 | unsigned int swath_bytes_c = 0; | |||
166 | unsigned int full_swath_bytes_packed_l = 0; | |||
167 | unsigned int full_swath_bytes_packed_c = 0; | |||
168 | bool_Bool req128_l = 0; | |||
169 | bool_Bool req128_c = 0; | |||
170 | bool_Bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); | |||
171 | bool_Bool surf_vert = (pipe_src_param.source_scan == dm_vert); | |||
172 | unsigned int log2_swath_height_l = 0; | |||
173 | unsigned int log2_swath_height_c = 0; | |||
174 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; | |||
175 | ||||
176 | full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; | |||
177 | full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; | |||
178 | ||||
179 | if (rq_param->yuv420_10bpc) { | |||
180 | full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2.0 / 3.0, | |||
181 | 256, | |||
182 | 1) + 256; | |||
183 | full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2.0 / 3.0, | |||
184 | 256, | |||
185 | 1) + 256; | |||
186 | } | |||
187 | ||||
188 | if (rq_param->yuv420) | |||
189 | total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; | |||
190 | else | |||
191 | total_swath_bytes = 2 * full_swath_bytes_packed_l; | |||
192 | ||||
193 | if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request | |||
194 | req128_l = 0; | |||
195 | req128_c = 0; | |||
196 | swath_bytes_l = full_swath_bytes_packed_l; | |||
197 | swath_bytes_c = full_swath_bytes_packed_c; | |||
198 | } else if (!rq_param->yuv420) { | |||
199 | req128_l = 1; | |||
200 | req128_c = 0; | |||
201 | swath_bytes_c = full_swath_bytes_packed_c; | |||
202 | swath_bytes_l = full_swath_bytes_packed_l / 2; | |||
203 | } else if ((double)full_swath_bytes_packed_l / (double)full_swath_bytes_packed_c < 1.5) { | |||
204 | req128_l = 0; | |||
205 | req128_c = 1; | |||
206 | swath_bytes_l = full_swath_bytes_packed_l; | |||
207 | swath_bytes_c = full_swath_bytes_packed_c / 2; | |||
208 | ||||
209 | total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; | |||
210 | ||||
211 | if (total_swath_bytes > detile_buf_size_in_bytes) { | |||
212 | req128_l = 1; | |||
213 | swath_bytes_l = full_swath_bytes_packed_l / 2; | |||
214 | } | |||
215 | } else { | |||
216 | req128_l = 1; | |||
217 | req128_c = 0; | |||
218 | swath_bytes_l = full_swath_bytes_packed_l/2; | |||
219 | swath_bytes_c = full_swath_bytes_packed_c; | |||
220 | ||||
221 | total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; | |||
222 | ||||
223 | if (total_swath_bytes > detile_buf_size_in_bytes) { | |||
224 | req128_c = 1; | |||
225 | swath_bytes_c = full_swath_bytes_packed_c/2; | |||
226 | } | |||
227 | } | |||
228 | ||||
229 | if (rq_param->yuv420) | |||
230 | total_swath_bytes = 2 * swath_bytes_l + 2 * swath_bytes_c; | |||
231 | else | |||
232 | total_swath_bytes = 2 * swath_bytes_l; | |||
233 | ||||
234 | rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; | |||
235 | rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; | |||
236 | ||||
237 | if (surf_linear) { | |||
238 | log2_swath_height_l = 0; | |||
239 | log2_swath_height_c = 0; | |||
240 | } else { | |||
241 | unsigned int swath_height_l; | |||
242 | unsigned int swath_height_c; | |||
243 | ||||
244 | if (!surf_vert) { | |||
245 | swath_height_l = rq_param->misc.rq_l.blk256_height; | |||
246 | swath_height_c = rq_param->misc.rq_c.blk256_height; | |||
247 | } else { | |||
248 | swath_height_l = rq_param->misc.rq_l.blk256_width; | |||
249 | swath_height_c = rq_param->misc.rq_c.blk256_width; | |||
250 | } | |||
251 | ||||
252 | if (swath_height_l > 0) | |||
253 | log2_swath_height_l = dml_log2(swath_height_l); | |||
254 | ||||
255 | if (req128_l && log2_swath_height_l > 0) | |||
256 | log2_swath_height_l -= 1; | |||
257 | ||||
258 | if (swath_height_c > 0) | |||
259 | log2_swath_height_c = dml_log2(swath_height_c); | |||
260 | ||||
261 | if (req128_c && log2_swath_height_c > 0) | |||
262 | log2_swath_height_c -= 1; | |||
263 | } | |||
264 | ||||
265 | rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; | |||
266 | rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; | |||
267 | ||||
268 | dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l){do { } while(0); }; | |||
269 | dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c){do { } while(0); }; | |||
270 | dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",{do { } while(0); } | |||
271 | __func__,{do { } while(0); } | |||
272 | full_swath_bytes_packed_l){do { } while(0); }; | |||
273 | dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",{do { } while(0); } | |||
274 | __func__,{do { } while(0); } | |||
275 | full_swath_bytes_packed_c){do { } while(0); }; | |||
276 | } | |||
277 | ||||
278 | static bool_Bool CalculateBytePerPixelAnd256BBlockSizes( | |||
279 | enum source_format_class SourcePixelFormat, | |||
280 | enum dm_swizzle_mode SurfaceTiling, | |||
281 | unsigned int *BytePerPixelY, | |||
282 | unsigned int *BytePerPixelC, | |||
283 | double *BytePerPixelDETY, | |||
284 | double *BytePerPixelDETC, | |||
285 | unsigned int *BlockHeight256BytesY, | |||
286 | unsigned int *BlockHeight256BytesC, | |||
287 | unsigned int *BlockWidth256BytesY, | |||
288 | unsigned int *BlockWidth256BytesC) | |||
289 | { | |||
290 | if (SourcePixelFormat == dm_444_64) { | |||
291 | *BytePerPixelDETY = 8; | |||
292 | *BytePerPixelDETC = 0; | |||
293 | *BytePerPixelY = 8; | |||
294 | *BytePerPixelC = 0; | |||
295 | } else if (SourcePixelFormat == dm_444_32 || SourcePixelFormat == dm_rgbe) { | |||
296 | *BytePerPixelDETY = 4; | |||
297 | *BytePerPixelDETC = 0; | |||
298 | *BytePerPixelY = 4; | |||
299 | *BytePerPixelC = 0; | |||
300 | } else if (SourcePixelFormat == dm_444_16) { | |||
301 | *BytePerPixelDETY = 2; | |||
302 | *BytePerPixelDETC = 0; | |||
303 | *BytePerPixelY = 2; | |||
304 | *BytePerPixelC = 0; | |||
305 | } else if (SourcePixelFormat == dm_444_8) { | |||
306 | *BytePerPixelDETY = 1; | |||
307 | *BytePerPixelDETC = 0; | |||
308 | *BytePerPixelY = 1; | |||
309 | *BytePerPixelC = 0; | |||
310 | } else if (SourcePixelFormat == dm_rgbe_alpha) { | |||
311 | *BytePerPixelDETY = 4; | |||
312 | *BytePerPixelDETC = 1; | |||
313 | *BytePerPixelY = 4; | |||
314 | *BytePerPixelC = 1; | |||
315 | } else if (SourcePixelFormat == dm_420_8) { | |||
316 | *BytePerPixelDETY = 1; | |||
317 | *BytePerPixelDETC = 2; | |||
318 | *BytePerPixelY = 1; | |||
319 | *BytePerPixelC = 2; | |||
320 | } else if (SourcePixelFormat == dm_420_12) { | |||
321 | *BytePerPixelDETY = 2; | |||
322 | *BytePerPixelDETC = 4; | |||
323 | *BytePerPixelY = 2; | |||
324 | *BytePerPixelC = 4; | |||
325 | } else { | |||
326 | *BytePerPixelDETY = 4.0 / 3; | |||
327 | *BytePerPixelDETC = 8.0 / 3; | |||
328 | *BytePerPixelY = 2; | |||
329 | *BytePerPixelC = 4; | |||
330 | } | |||
331 | ||||
332 | if ((SourcePixelFormat == dm_444_64 || SourcePixelFormat == dm_444_32 | |||
333 | || SourcePixelFormat == dm_444_16 || SourcePixelFormat == dm_444_8 | |||
334 | || SourcePixelFormat == dm_mono_16 || SourcePixelFormat == dm_mono_8 | |||
335 | || SourcePixelFormat == dm_rgbe)) { | |||
336 | if (SurfaceTiling == dm_sw_linear) { | |||
337 | *BlockHeight256BytesY = 1; | |||
338 | } else if (SourcePixelFormat == dm_444_64) { | |||
339 | *BlockHeight256BytesY = 4; | |||
340 | } else if (SourcePixelFormat == dm_444_8) { | |||
341 | *BlockHeight256BytesY = 16; | |||
342 | } else { | |||
343 | *BlockHeight256BytesY = 8; | |||
344 | } | |||
345 | *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; | |||
346 | *BlockHeight256BytesC = 0; | |||
347 | *BlockWidth256BytesC = 0; | |||
348 | } else { | |||
349 | if (SurfaceTiling == dm_sw_linear) { | |||
350 | *BlockHeight256BytesY = 1; | |||
351 | *BlockHeight256BytesC = 1; | |||
352 | } else if (SourcePixelFormat == dm_rgbe_alpha) { | |||
353 | *BlockHeight256BytesY = 8; | |||
354 | *BlockHeight256BytesC = 16; | |||
355 | } else if (SourcePixelFormat == dm_420_8) { | |||
356 | *BlockHeight256BytesY = 16; | |||
357 | *BlockHeight256BytesC = 8; | |||
358 | } else { | |||
359 | *BlockHeight256BytesY = 8; | |||
360 | *BlockHeight256BytesC = 8; | |||
361 | } | |||
362 | *BlockWidth256BytesY = 256U / *BytePerPixelY / *BlockHeight256BytesY; | |||
363 | *BlockWidth256BytesC = 256U / *BytePerPixelC / *BlockHeight256BytesC; | |||
364 | } | |||
365 | return true1; | |||
366 | } | |||
367 | ||||
368 | static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, | |||
369 | display_data_rq_dlg_params_st *rq_dlg_param, | |||
370 | display_data_rq_misc_params_st *rq_misc_param, | |||
371 | display_data_rq_sizing_params_st *rq_sizing_param, | |||
372 | unsigned int vp_width, | |||
373 | unsigned int vp_height, | |||
374 | unsigned int data_pitch, | |||
375 | unsigned int meta_pitch, | |||
376 | unsigned int source_format, | |||
377 | unsigned int tiling, | |||
378 | unsigned int macro_tile_size, | |||
379 | unsigned int source_scan, | |||
380 | unsigned int hostvm_enable, | |||
381 | unsigned int is_chroma, | |||
382 | unsigned int surface_height) | |||
383 | { | |||
384 | bool_Bool surf_linear = (tiling == dm_sw_linear); | |||
| ||||
385 | bool_Bool surf_vert = (source_scan == dm_vert); | |||
386 | ||||
387 | unsigned int bytes_per_element = 0; | |||
388 | unsigned int bytes_per_element_y = 0; | |||
389 | unsigned int bytes_per_element_c = 0; | |||
390 | ||||
391 | unsigned int blk256_width = 0; | |||
392 | unsigned int blk256_height = 0; | |||
393 | ||||
394 | unsigned int blk256_width_y = 0; | |||
395 | unsigned int blk256_height_y = 0; | |||
396 | unsigned int blk256_width_c = 0; | |||
397 | unsigned int blk256_height_c = 0; | |||
398 | unsigned int log2_bytes_per_element = 0; | |||
399 | unsigned int log2_blk256_width = 0; | |||
400 | unsigned int log2_blk256_height = 0; | |||
401 | unsigned int blk_bytes = 0; | |||
402 | unsigned int log2_blk_bytes = 0; | |||
403 | unsigned int log2_blk_height = 0; | |||
404 | unsigned int log2_blk_width = 0; | |||
405 | unsigned int log2_meta_req_bytes = 0; | |||
406 | unsigned int log2_meta_req_height = 0; | |||
407 | unsigned int log2_meta_req_width = 0; | |||
408 | unsigned int meta_req_width = 0; | |||
409 | unsigned int meta_req_height = 0; | |||
410 | unsigned int log2_meta_row_height = 0; | |||
411 | unsigned int meta_row_width_ub = 0; | |||
412 | unsigned int log2_meta_chunk_bytes = 0; | |||
413 | unsigned int log2_meta_chunk_height = 0; | |||
414 | ||||
415 | //full sized meta chunk width in unit of data elements | |||
416 | unsigned int log2_meta_chunk_width = 0; | |||
417 | unsigned int log2_min_meta_chunk_bytes = 0; | |||
418 | unsigned int min_meta_chunk_width = 0; | |||
419 | unsigned int meta_chunk_width = 0; | |||
420 | unsigned int meta_chunk_per_row_int = 0; | |||
421 | unsigned int meta_row_remainder = 0; | |||
422 | unsigned int meta_chunk_threshold = 0; | |||
423 | unsigned int meta_blk_bytes = 0; | |||
424 | unsigned int meta_blk_height = 0; | |||
425 | unsigned int meta_blk_width = 0; | |||
426 | unsigned int meta_surface_bytes = 0; | |||
427 | unsigned int vmpg_bytes = 0; | |||
428 | unsigned int meta_pte_req_per_frame_ub = 0; | |||
429 | unsigned int meta_pte_bytes_per_frame_ub = 0; | |||
430 | const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.gpuvm_min_page_size_bytes); | |||
431 | const bool_Bool dual_plane_en = is_dual_plane((enum source_format_class)(source_format)); | |||
432 | const unsigned int dpte_buf_in_pte_reqs = dual_plane_en
| |||
433 | (is_chroma ? mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma : mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma) | |||
434 | : (mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma); | |||
435 | ||||
436 | unsigned int log2_vmpg_height = 0; | |||
437 | unsigned int log2_vmpg_width = 0; | |||
438 | unsigned int log2_dpte_req_height_ptes = 0; | |||
439 | unsigned int log2_dpte_req_height = 0; | |||
440 | unsigned int log2_dpte_req_width = 0; | |||
441 | unsigned int log2_dpte_row_height_linear = 0; | |||
442 | unsigned int log2_dpte_row_height = 0; | |||
443 | unsigned int log2_dpte_group_width = 0; | |||
444 | unsigned int dpte_row_width_ub = 0; | |||
445 | unsigned int dpte_req_height = 0; | |||
446 | unsigned int dpte_req_width = 0; | |||
447 | unsigned int dpte_group_width = 0; | |||
448 | unsigned int log2_dpte_group_bytes = 0; | |||
449 | unsigned int log2_dpte_group_length = 0; | |||
450 | double byte_per_pixel_det_y = 0; | |||
451 | double byte_per_pixel_det_c = 0; | |||
452 | ||||
453 | CalculateBytePerPixelAnd256BBlockSizes((enum source_format_class)(source_format), | |||
454 | (enum dm_swizzle_mode)(tiling), | |||
455 | &bytes_per_element_y, | |||
456 | &bytes_per_element_c, | |||
457 | &byte_per_pixel_det_y, | |||
458 | &byte_per_pixel_det_c, | |||
459 | &blk256_height_y, | |||
460 | &blk256_height_c, | |||
461 | &blk256_width_y, | |||
462 | &blk256_width_c); | |||
463 | ||||
464 | if (!is_chroma
| |||
465 | blk256_width = blk256_width_y; | |||
466 | blk256_height = blk256_height_y; | |||
467 | bytes_per_element = bytes_per_element_y; | |||
468 | } else { | |||
469 | blk256_width = blk256_width_c; | |||
470 | blk256_height = blk256_height_c; | |||
471 | bytes_per_element = bytes_per_element_c; | |||
472 | } | |||
473 | ||||
474 | log2_bytes_per_element = dml_log2(bytes_per_element); | |||
475 | ||||
476 | dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear){do { } while(0); }; | |||
477 | dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert){do { } while(0); }; | |||
478 | dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width){do { } while(0); }; | |||
479 | dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height){do { } while(0); }; | |||
480 | ||||
481 | log2_blk256_width = dml_log2((double)blk256_width); | |||
482 | log2_blk256_height = dml_log2((double)blk256_height); | |||
483 | blk_bytes = surf_linear
| |||
484 | 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); | |||
485 | log2_blk_bytes = dml_log2((double)blk_bytes); | |||
486 | log2_blk_height = 0; | |||
487 | log2_blk_width = 0; | |||
488 | ||||
489 | // remember log rule | |||
490 | // "+" in log is multiply | |||
491 | // "-" in log is divide | |||
492 | // "/2" is like square root | |||
493 | // blk is vertical biased | |||
494 | if (tiling
| |||
495 | log2_blk_height = log2_blk256_height | |||
496 | + dml_ceil((double)(log2_blk_bytes - 8) / 2.0, 1); | |||
497 | else | |||
498 | log2_blk_height = 0; // blk height of 1 | |||
499 | ||||
500 | log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; | |||
501 | ||||
502 | if (!surf_vert
| |||
503 | int unsigned temp = 0; | |||
504 | ||||
505 | temp = dml_round_to_multiple(vp_width - 1, blk256_width, 1) + blk256_width; | |||
506 | if (data_pitch < blk256_width) { | |||
507 | dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < blk256_width=%u\n", __func__, data_pitch, blk256_width){do { } while(0); }; | |||
508 | } else { | |||
509 | if (temp > data_pitch) { | |||
510 | if (data_pitch >= vp_width) | |||
511 | temp = data_pitch; | |||
512 | else | |||
513 | dml_print("WARNING: DML_DLG: %s: swath_size calculation ignoring data_pitch=%u < vp_width=%u\n", __func__, data_pitch, vp_width){do { } while(0); }; | |||
514 | } | |||
515 | } | |||
516 | rq_dlg_param->swath_width_ub = temp; | |||
517 | rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_width; | |||
518 | } else { | |||
519 | int unsigned temp = 0; | |||
520 | ||||
521 | temp = dml_round_to_multiple(vp_height - 1, blk256_height, 1) + blk256_height; | |||
522 | if (surface_height
| |||
523 | dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < blk256_height=%u\n", __func__, surface_height, blk256_height){do { } while(0); }; | |||
524 | } else { | |||
525 | if (temp > surface_height) { | |||
526 | if (surface_height >= vp_height) | |||
527 | temp = surface_height; | |||
528 | else | |||
529 | dml_print("WARNING: DML_DLG: %s swath_size calculation ignored surface_height=%u < vp_height=%u\n", __func__, surface_height, vp_height){do { } while(0); }; | |||
530 | } | |||
531 | } | |||
532 | rq_dlg_param->swath_width_ub = temp; | |||
533 | rq_dlg_param->req_per_swath_ub = temp >> log2_blk256_height; | |||
534 | } | |||
535 | ||||
536 | if (!surf_vert
| |||
537 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height | |||
538 | * bytes_per_element; | |||
539 | else | |||
540 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width | |||
541 | * bytes_per_element; | |||
542 | ||||
543 | rq_misc_param->blk256_height = blk256_height; | |||
544 | rq_misc_param->blk256_width = blk256_width; | |||
545 | ||||
546 | // ------- | |||
547 | // meta | |||
548 | // ------- | |||
549 | log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element | |||
550 | ||||
551 | // each 64b meta request for dcn is 8x8 meta elements and | |||
552 | // a meta element covers one 256b block of the the data surface. | |||
553 | log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 | |||
554 | log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element | |||
555 | - log2_meta_req_height; | |||
556 | meta_req_width = 1 << log2_meta_req_width; | |||
557 | meta_req_height = 1 << log2_meta_req_height; | |||
558 | log2_meta_row_height = 0; | |||
559 | meta_row_width_ub = 0; | |||
560 | ||||
561 | // the dimensions of a meta row are meta_row_width x meta_row_height in elements. | |||
562 | // calculate upper bound of the meta_row_width | |||
563 | if (!surf_vert
| |||
564 | log2_meta_row_height = log2_meta_req_height; | |||
565 | meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) | |||
566 | + meta_req_width; | |||
567 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; | |||
568 | } else { | |||
569 | log2_meta_row_height = log2_meta_req_width; | |||
570 | meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) | |||
571 | + meta_req_height; | |||
572 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; | |||
573 | } | |||
574 | rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; | |||
575 | ||||
576 | rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; | |||
577 | ||||
578 | log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); | |||
579 | log2_meta_chunk_height = log2_meta_row_height; | |||
580 | ||||
581 | //full sized meta chunk width in unit of data elements | |||
582 | log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element | |||
583 | - log2_meta_chunk_height; | |||
584 | log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); | |||
585 | min_meta_chunk_width = 1 | |||
586 | << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element | |||
587 | - log2_meta_chunk_height); | |||
588 | meta_chunk_width = 1 << log2_meta_chunk_width; | |||
589 | meta_chunk_per_row_int = (unsigned int)(meta_row_width_ub / meta_chunk_width); | |||
590 | meta_row_remainder = meta_row_width_ub % meta_chunk_width; | |||
591 | meta_chunk_threshold = 0; | |||
592 | meta_blk_bytes = 4096; | |||
593 | meta_blk_height = blk256_height * 64; | |||
594 | meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; | |||
| ||||
595 | meta_surface_bytes = meta_pitch | |||
596 | * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) | |||
597 | * bytes_per_element / 256; | |||
598 | vmpg_bytes = mode_lib->soc.gpuvm_min_page_size_bytes; | |||
599 | meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, | |||
600 | 8 * vmpg_bytes, | |||
601 | 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); | |||
602 | meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request | |||
603 | rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; | |||
604 | ||||
605 | dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height){do { } while(0); }; | |||
606 | dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width){do { } while(0); }; | |||
607 | dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes){do { } while(0); }; | |||
608 | dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n",{do { } while(0); } | |||
609 | __func__,{do { } while(0); } | |||
610 | meta_pte_req_per_frame_ub){do { } while(0); }; | |||
611 | dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",{do { } while(0); } | |||
612 | __func__,{do { } while(0); } | |||
613 | meta_pte_bytes_per_frame_ub){do { } while(0); }; | |||
614 | ||||
615 | if (!surf_vert) | |||
616 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; | |||
617 | else | |||
618 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; | |||
619 | ||||
620 | if (meta_row_remainder <= meta_chunk_threshold) | |||
621 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; | |||
622 | else | |||
623 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; | |||
624 | ||||
625 | // ------ | |||
626 | // dpte | |||
627 | // ------ | |||
628 | if (surf_linear) { | |||
629 | log2_vmpg_height = 0; // one line high | |||
630 | } else { | |||
631 | log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; | |||
632 | } | |||
633 | log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; | |||
634 | ||||
635 | // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. | |||
636 | if (surf_linear) { //one 64B PTE request returns 8 PTEs | |||
637 | log2_dpte_req_height_ptes = 0; | |||
638 | log2_dpte_req_width = log2_vmpg_width + 3; | |||
639 | log2_dpte_req_height = 0; | |||
640 | } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size | |||
641 | //one 64B req gives 8x1 PTEs for 4KB tile | |||
642 | log2_dpte_req_height_ptes = 0; | |||
643 | log2_dpte_req_width = log2_blk_width + 3; | |||
644 | log2_dpte_req_height = log2_blk_height + 0; | |||
645 | } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB | |||
646 | //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB | |||
647 | log2_dpte_req_height_ptes = 4; | |||
648 | log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width | |||
649 | log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height | |||
650 | } else { //64KB page size and must 64KB tile block | |||
651 | //one 64B req gives 8x1 PTEs for 64KB tile | |||
652 | log2_dpte_req_height_ptes = 0; | |||
653 | log2_dpte_req_width = log2_blk_width + 3; | |||
654 | log2_dpte_req_height = log2_blk_height + 0; | |||
655 | } | |||
656 | ||||
657 | // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height | |||
658 | // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent | |||
659 | // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) | |||
660 | //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; | |||
661 | //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; | |||
662 | dpte_req_height = 1 << log2_dpte_req_height; | |||
663 | dpte_req_width = 1 << log2_dpte_req_width; | |||
664 | ||||
665 | // calculate pitch dpte row buffer can hold | |||
666 | // round the result down to a power of two. | |||
667 | if (surf_linear) { | |||
668 | unsigned int dpte_row_height = 0; | |||
669 | ||||
670 | log2_dpte_row_height_linear = dml_floor(dml_log2(dpte_buf_in_pte_reqs * dpte_req_width / data_pitch), 1); | |||
671 | ||||
672 | dml_print("DML_DLG: %s: is_chroma = %d\n", __func__, is_chroma){do { } while(0); }; | |||
673 | dml_print("DML_DLG: %s: dpte_buf_in_pte_reqs = %d\n", __func__, dpte_buf_in_pte_reqs){do { } while(0); }; | |||
674 | dml_print("DML_DLG: %s: log2_dpte_row_height_linear = %d\n", __func__, log2_dpte_row_height_linear){do { } while(0); }; | |||
675 | ||||
676 | ASSERT(log2_dpte_row_height_linear >= 3)do { if (({ static int __warned; int __ret = !!(!(log2_dpte_row_height_linear >= 3)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(log2_dpte_row_height_linear >= 3)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 676); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
677 | ||||
678 | if (log2_dpte_row_height_linear > 7) | |||
679 | log2_dpte_row_height_linear = 7; | |||
680 | ||||
681 | log2_dpte_row_height = log2_dpte_row_height_linear; | |||
682 | // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. | |||
683 | // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. | |||
684 | dpte_row_height = 1 << log2_dpte_row_height; | |||
685 | dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, | |||
686 | dpte_req_width, | |||
687 | 1) + dpte_req_width; | |||
688 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; | |||
689 | } else { | |||
690 | // the upper bound of the dpte_row_width without dependency on viewport position follows. | |||
691 | // for tiled mode, row height is the same as req height and row store up to vp size upper bound | |||
692 | if (!surf_vert) { | |||
693 | log2_dpte_row_height = log2_dpte_req_height; | |||
694 | dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) | |||
695 | + dpte_req_width; | |||
696 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; | |||
697 | } else { | |||
698 | log2_dpte_row_height = | |||
699 | (log2_blk_width < log2_dpte_req_width) ? | |||
700 | log2_blk_width : log2_dpte_req_width; | |||
701 | dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) | |||
702 | + dpte_req_height; | |||
703 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; | |||
704 | } | |||
705 | } | |||
706 | if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB | |||
707 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request | |||
708 | else | |||
709 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request | |||
710 | ||||
711 | rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; | |||
712 | ||||
713 | // the dpte_group_bytes is reduced for the specific case of vertical | |||
714 | // access of a tile surface that has dpte request of 8x1 ptes. | |||
715 | if (hostvm_enable) | |||
716 | rq_sizing_param->dpte_group_bytes = 512; | |||
717 | else { | |||
718 | if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group | |||
719 | rq_sizing_param->dpte_group_bytes = 512; | |||
720 | else | |||
721 | rq_sizing_param->dpte_group_bytes = 2048; | |||
722 | } | |||
723 | ||||
724 | //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. | |||
725 | log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); | |||
726 | log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests | |||
727 | ||||
728 | // full sized data pte group width in elements | |||
729 | if (!surf_vert) | |||
730 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; | |||
731 | else | |||
732 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; | |||
733 | ||||
734 | //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B | |||
735 | if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB | |||
736 | log2_dpte_group_width = log2_dpte_group_width - 1; | |||
737 | ||||
738 | dpte_group_width = 1 << log2_dpte_group_width; | |||
739 | ||||
740 | // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, | |||
741 | // the upper bound for the dpte groups per row is as follows. | |||
742 | rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double)dpte_row_width_ub / dpte_group_width, | |||
743 | 1); | |||
744 | } | |||
745 | ||||
746 | static void get_surf_rq_param(struct display_mode_lib *mode_lib, | |||
747 | display_data_rq_sizing_params_st *rq_sizing_param, | |||
748 | display_data_rq_dlg_params_st *rq_dlg_param, | |||
749 | display_data_rq_misc_params_st *rq_misc_param, | |||
750 | const display_pipe_params_st pipe_param, | |||
751 | bool_Bool is_chroma, | |||
752 | bool_Bool is_alpha) | |||
753 | { | |||
754 | bool_Bool mode_422 = 0; | |||
755 | unsigned int vp_width = 0; | |||
756 | unsigned int vp_height = 0; | |||
757 | unsigned int data_pitch = 0; | |||
758 | unsigned int meta_pitch = 0; | |||
759 | unsigned int surface_height = 0; | |||
760 | unsigned int ppe = mode_422 ? 2 : 1; | |||
761 | ||||
762 | // FIXME check if ppe apply for both luma and chroma in 422 case | |||
763 | if (is_chroma | is_alpha) { | |||
764 | vp_width = pipe_param.src.viewport_width_c / ppe; | |||
765 | vp_height = pipe_param.src.viewport_height_c; | |||
766 | data_pitch = pipe_param.src.data_pitch_c; | |||
767 | meta_pitch = pipe_param.src.meta_pitch_c; | |||
768 | surface_height = pipe_param.src.surface_height_y / 2.0; | |||
769 | } else { | |||
770 | vp_width = pipe_param.src.viewport_width / ppe; | |||
771 | vp_height = pipe_param.src.viewport_height; | |||
772 | data_pitch = pipe_param.src.data_pitch; | |||
773 | meta_pitch = pipe_param.src.meta_pitch; | |||
774 | surface_height = pipe_param.src.surface_height_y; | |||
775 | } | |||
776 | ||||
777 | if (pipe_param.dest.odm_combine) { | |||
778 | unsigned int access_dir = 0; | |||
779 | unsigned int full_src_vp_width = 0; | |||
780 | unsigned int hactive_odm = 0; | |||
781 | unsigned int src_hactive_odm = 0; | |||
782 | access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed | |||
783 | hactive_odm = pipe_param.dest.hactive / ((unsigned int)pipe_param.dest.odm_combine*2); | |||
784 | if (is_chroma) { | |||
785 | full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width; | |||
786 | src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_odm; | |||
787 | } else { | |||
788 | full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width; | |||
789 | src_hactive_odm = pipe_param.scale_ratio_depth.hscl_ratio * hactive_odm; | |||
790 | } | |||
791 | ||||
792 | if (access_dir == 0) { | |||
793 | vp_width = dml_min(full_src_vp_width, src_hactive_odm); | |||
794 | dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width){do { } while(0); }; | |||
795 | } else { | |||
796 | vp_height = dml_min(full_src_vp_width, src_hactive_odm); | |||
797 | dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height){do { } while(0); }; | |||
798 | } | |||
799 | dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width){do { } while(0); }; | |||
800 | dml_print("DML_DLG: %s: hactive_odm = %d\n", __func__, hactive_odm){do { } while(0); }; | |||
801 | dml_print("DML_DLG: %s: src_hactive_odm = %d\n", __func__, src_hactive_odm){do { } while(0); }; | |||
802 | } | |||
803 | ||||
804 | rq_sizing_param->chunk_bytes = 8192; | |||
805 | ||||
806 | if (is_alpha) { | |||
807 | rq_sizing_param->chunk_bytes = 4096; | |||
808 | } | |||
809 | ||||
810 | if (rq_sizing_param->chunk_bytes == 64 * 1024) | |||
811 | rq_sizing_param->min_chunk_bytes = 0; | |||
812 | else | |||
813 | rq_sizing_param->min_chunk_bytes = 1024; | |||
814 | ||||
815 | rq_sizing_param->meta_chunk_bytes = 2048; | |||
816 | rq_sizing_param->min_meta_chunk_bytes = 256; | |||
817 | ||||
818 | if (pipe_param.src.hostvm) | |||
819 | rq_sizing_param->mpte_group_bytes = 512; | |||
820 | else | |||
821 | rq_sizing_param->mpte_group_bytes = 2048; | |||
822 | ||||
823 | get_meta_and_pte_attr(mode_lib, | |||
824 | rq_dlg_param, | |||
825 | rq_misc_param, | |||
826 | rq_sizing_param, | |||
827 | vp_width, | |||
828 | vp_height, | |||
829 | data_pitch, | |||
830 | meta_pitch, | |||
831 | pipe_param.src.source_format, | |||
832 | pipe_param.src.sw_mode, | |||
833 | pipe_param.src.macro_tile_size, | |||
834 | pipe_param.src.source_scan, | |||
835 | pipe_param.src.hostvm, | |||
836 | is_chroma, | |||
837 | surface_height); | |||
838 | } | |||
839 | ||||
840 | static void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, | |||
841 | display_rq_params_st *rq_param, | |||
842 | const display_pipe_params_st pipe_param) | |||
843 | { | |||
844 | // get param for luma surface | |||
845 | rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 | |||
846 | || pipe_param.src.source_format == dm_420_10 | |||
847 | || pipe_param.src.source_format == dm_rgbe_alpha | |||
848 | || pipe_param.src.source_format == dm_420_12; | |||
849 | ||||
850 | rq_param->yuv420_10bpc = pipe_param.src.source_format == dm_420_10; | |||
851 | ||||
852 | rq_param->rgbe_alpha = (pipe_param.src.source_format == dm_rgbe_alpha)?1:0; | |||
853 | ||||
854 | get_surf_rq_param(mode_lib, | |||
855 | &(rq_param->sizing.rq_l), | |||
856 | &(rq_param->dlg.rq_l), | |||
857 | &(rq_param->misc.rq_l), | |||
858 | pipe_param, | |||
859 | 0, | |||
860 | 0); | |||
861 | ||||
862 | if (is_dual_plane((enum source_format_class)(pipe_param.src.source_format))) { | |||
863 | // get param for chroma surface | |||
864 | get_surf_rq_param(mode_lib, | |||
865 | &(rq_param->sizing.rq_c), | |||
866 | &(rq_param->dlg.rq_c), | |||
867 | &(rq_param->misc.rq_c), | |||
868 | pipe_param, | |||
869 | 1, | |||
870 | rq_param->rgbe_alpha); | |||
871 | } | |||
872 | ||||
873 | // calculate how to split the det buffer space between luma and chroma | |||
874 | handle_det_buf_split(mode_lib, rq_param, pipe_param.src); | |||
875 | print__rq_params_st(mode_lib, *rq_param); | |||
876 | } | |||
877 | ||||
878 | void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, | |||
879 | display_rq_regs_st *rq_regs, | |||
880 | const display_pipe_params_st pipe_param) | |||
881 | { | |||
882 | display_rq_params_st rq_param = { 0 }; | |||
883 | ||||
884 | memset(rq_regs, 0, sizeof(*rq_regs))__builtin_memset((rq_regs), (0), (sizeof(*rq_regs))); | |||
885 | dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); | |||
886 | extract_rq_regs(mode_lib, rq_regs, rq_param); | |||
887 | ||||
888 | print__rq_regs_st(mode_lib, *rq_regs); | |||
889 | } | |||
890 | ||||
891 | static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, | |||
892 | double *refcyc_per_req_delivery_pre_cur, | |||
893 | double *refcyc_per_req_delivery_cur, | |||
894 | double refclk_freq_in_mhz, | |||
895 | double ref_freq_to_pix_freq, | |||
896 | double hscale_pixel_rate_l, | |||
897 | double hscl_ratio, | |||
898 | double vratio_pre_l, | |||
899 | double vratio_l, | |||
900 | unsigned int cur_width, | |||
901 | enum cursor_bpp cur_bpp) | |||
902 | { | |||
903 | unsigned int cur_src_width = cur_width; | |||
904 | unsigned int cur_req_size = 0; | |||
905 | unsigned int cur_req_width = 0; | |||
906 | double cur_width_ub = 0.0; | |||
907 | double cur_req_per_width = 0.0; | |||
908 | double hactive_cur = 0.0; | |||
909 | ||||
910 | ASSERT(cur_src_width <= 256)do { if (({ static int __warned; int __ret = !!(!(cur_src_width <= 256)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(cur_src_width <= 256)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 910); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
911 | ||||
912 | *refcyc_per_req_delivery_pre_cur = 0.0; | |||
913 | *refcyc_per_req_delivery_cur = 0.0; | |||
914 | if (cur_src_width > 0) { | |||
915 | unsigned int cur_bit_per_pixel = 0; | |||
916 | ||||
917 | if (cur_bpp == dm_cur_2bit) { | |||
918 | cur_req_size = 64; // byte | |||
919 | cur_bit_per_pixel = 2; | |||
920 | } else { // 32bit | |||
921 | cur_bit_per_pixel = 32; | |||
922 | if (cur_src_width >= 1 && cur_src_width <= 16) | |||
923 | cur_req_size = 64; | |||
924 | else if (cur_src_width >= 17 && cur_src_width <= 31) | |||
925 | cur_req_size = 128; | |||
926 | else | |||
927 | cur_req_size = 256; | |||
928 | } | |||
929 | ||||
930 | cur_req_width = (double)cur_req_size / ((double)cur_bit_per_pixel / 8.0); | |||
931 | cur_width_ub = dml_ceil((double)cur_src_width / (double)cur_req_width, 1) | |||
932 | * (double)cur_req_width; | |||
933 | cur_req_per_width = cur_width_ub / (double)cur_req_width; | |||
934 | hactive_cur = (double)cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor | |||
935 | ||||
936 | if (vratio_pre_l <= 1.0) { | |||
937 | *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq | |||
938 | / (double)cur_req_per_width; | |||
939 | } else { | |||
940 | *refcyc_per_req_delivery_pre_cur = (double)refclk_freq_in_mhz | |||
941 | * (double)cur_src_width / hscale_pixel_rate_l | |||
942 | / (double)cur_req_per_width; | |||
943 | } | |||
944 | ||||
945 | ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 945); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
946 | ||||
947 | if (vratio_l <= 1.0) { | |||
948 | *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq | |||
949 | / (double)cur_req_per_width; | |||
950 | } else { | |||
951 | *refcyc_per_req_delivery_cur = (double)refclk_freq_in_mhz | |||
952 | * (double)cur_src_width / hscale_pixel_rate_l | |||
953 | / (double)cur_req_per_width; | |||
954 | } | |||
955 | ||||
956 | dml_print("DML_DLG: %s: cur_req_width = %d\n",{do { } while(0); } | |||
957 | __func__,{do { } while(0); } | |||
958 | cur_req_width){do { } while(0); }; | |||
959 | dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n",{do { } while(0); } | |||
960 | __func__,{do { } while(0); } | |||
961 | cur_width_ub){do { } while(0); }; | |||
962 | dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n",{do { } while(0); } | |||
963 | __func__,{do { } while(0); } | |||
964 | cur_req_per_width){do { } while(0); }; | |||
965 | dml_print("DML_DLG: %s: hactive_cur = %3.2f\n",{do { } while(0); } | |||
966 | __func__,{do { } while(0); } | |||
967 | hactive_cur){do { } while(0); }; | |||
968 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n",{do { } while(0); } | |||
969 | __func__,{do { } while(0); } | |||
970 | *refcyc_per_req_delivery_pre_cur){do { } while(0); }; | |||
971 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n",{do { } while(0); } | |||
972 | __func__,{do { } while(0); } | |||
973 | *refcyc_per_req_delivery_cur){do { } while(0); }; | |||
974 | ||||
975 | ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 975); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
976 | } | |||
977 | } | |||
978 | ||||
979 | // Note: currently taken in as is. | |||
980 | // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. | |||
981 | static void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, | |||
982 | const display_e2e_pipe_params_st *e2e_pipe_param, | |||
983 | const unsigned int num_pipes, | |||
984 | const unsigned int pipe_idx, | |||
985 | display_dlg_regs_st *disp_dlg_regs, | |||
986 | display_ttu_regs_st *disp_ttu_regs, | |||
987 | const display_rq_dlg_params_st rq_dlg_param, | |||
988 | const display_dlg_sys_params_st dlg_sys_param, | |||
989 | const bool_Bool cstate_en, | |||
990 | const bool_Bool pstate_en, | |||
991 | const bool_Bool vm_en, | |||
992 | const bool_Bool ignore_viewport_pos, | |||
993 | const bool_Bool immediate_flip_support) | |||
994 | { | |||
995 | const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; | |||
996 | const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; | |||
997 | const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; | |||
998 | const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; | |||
999 | const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; | |||
1000 | const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; | |||
1001 | ||||
1002 | // ------------------------- | |||
1003 | // Section 1.15.2.1: OTG dependent Params | |||
1004 | // ------------------------- | |||
1005 | // Timing | |||
1006 | unsigned int htotal = dst->htotal; | |||
1007 | // unsigned int hblank_start = dst.hblank_start; // TODO: Remove | |||
1008 | unsigned int hblank_end = dst->hblank_end; | |||
1009 | unsigned int vblank_start = dst->vblank_start; | |||
1010 | unsigned int vblank_end = dst->vblank_end; | |||
1011 | unsigned int min_vblank = mode_lib->ip.min_vblank_lines; | |||
1012 | ||||
1013 | double dppclk_freq_in_mhz = clks->dppclk_mhz; | |||
1014 | double dispclk_freq_in_mhz = clks->dispclk_mhz; | |||
1015 | double refclk_freq_in_mhz = clks->refclk_mhz; | |||
1016 | double pclk_freq_in_mhz = dst->pixel_rate_mhz; | |||
1017 | bool_Bool interlaced = dst->interlaced; | |||
1018 | ||||
1019 | double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; | |||
1020 | ||||
1021 | double min_dcfclk_mhz = 0; | |||
1022 | double t_calc_us = 0; | |||
1023 | double min_ttu_vblank = 0; | |||
1024 | ||||
1025 | double min_dst_y_ttu_vblank = 0; | |||
1026 | unsigned int dlg_vblank_start = 0; | |||
1027 | bool_Bool dual_plane = 0; | |||
1028 | bool_Bool mode_422 = 0; | |||
1029 | unsigned int access_dir = 0; | |||
1030 | unsigned int vp_height_l = 0; | |||
1031 | unsigned int vp_width_l = 0; | |||
1032 | unsigned int vp_height_c = 0; | |||
1033 | unsigned int vp_width_c = 0; | |||
1034 | ||||
1035 | // Scaling | |||
1036 | unsigned int htaps_l = 0; | |||
1037 | unsigned int htaps_c = 0; | |||
1038 | double hratio_l = 0; | |||
1039 | double hratio_c = 0; | |||
1040 | double vratio_l = 0; | |||
1041 | double vratio_c = 0; | |||
1042 | bool_Bool scl_enable = 0; | |||
1043 | ||||
1044 | double line_time_in_us = 0; | |||
1045 | // double vinit_l; | |||
1046 | // double vinit_c; | |||
1047 | // double vinit_bot_l; | |||
1048 | // double vinit_bot_c; | |||
1049 | ||||
1050 | // unsigned int swath_height_l; | |||
1051 | unsigned int swath_width_ub_l = 0; | |||
1052 | // unsigned int dpte_bytes_per_row_ub_l; | |||
1053 | unsigned int dpte_groups_per_row_ub_l = 0; | |||
1054 | // unsigned int meta_pte_bytes_per_frame_ub_l; | |||
1055 | // unsigned int meta_bytes_per_row_ub_l; | |||
1056 | ||||
1057 | // unsigned int swath_height_c; | |||
1058 | unsigned int swath_width_ub_c = 0; | |||
1059 | // unsigned int dpte_bytes_per_row_ub_c; | |||
1060 | unsigned int dpte_groups_per_row_ub_c = 0; | |||
1061 | ||||
1062 | unsigned int meta_chunks_per_row_ub_l = 0; | |||
1063 | unsigned int meta_chunks_per_row_ub_c = 0; | |||
1064 | unsigned int vupdate_offset = 0; | |||
1065 | unsigned int vupdate_width = 0; | |||
1066 | unsigned int vready_offset = 0; | |||
1067 | ||||
1068 | unsigned int dppclk_delay_subtotal = 0; | |||
1069 | unsigned int dispclk_delay_subtotal = 0; | |||
1070 | unsigned int pixel_rate_delay_subtotal = 0; | |||
1071 | ||||
1072 | unsigned int vstartup_start = 0; | |||
1073 | unsigned int dst_x_after_scaler = 0; | |||
1074 | unsigned int dst_y_after_scaler = 0; | |||
1075 | double line_wait = 0; | |||
1076 | double dst_y_prefetch = 0; | |||
1077 | double dst_y_per_vm_vblank = 0; | |||
1078 | double dst_y_per_row_vblank = 0; | |||
1079 | double dst_y_per_vm_flip = 0; | |||
1080 | double dst_y_per_row_flip = 0; | |||
1081 | double max_dst_y_per_vm_vblank = 0; | |||
1082 | double max_dst_y_per_row_vblank = 0; | |||
1083 | double lsw = 0; | |||
1084 | double vratio_pre_l = 0; | |||
1085 | double vratio_pre_c = 0; | |||
1086 | unsigned int req_per_swath_ub_l = 0; | |||
1087 | unsigned int req_per_swath_ub_c = 0; | |||
1088 | unsigned int meta_row_height_l = 0; | |||
1089 | unsigned int meta_row_height_c = 0; | |||
1090 | unsigned int swath_width_pixels_ub_l = 0; | |||
1091 | unsigned int swath_width_pixels_ub_c = 0; | |||
1092 | unsigned int scaler_rec_in_width_l = 0; | |||
1093 | unsigned int scaler_rec_in_width_c = 0; | |||
1094 | unsigned int dpte_row_height_l = 0; | |||
1095 | unsigned int dpte_row_height_c = 0; | |||
1096 | double hscale_pixel_rate_l = 0; | |||
1097 | double hscale_pixel_rate_c = 0; | |||
1098 | double min_hratio_fact_l = 0; | |||
1099 | double min_hratio_fact_c = 0; | |||
1100 | double refcyc_per_line_delivery_pre_l = 0; | |||
1101 | double refcyc_per_line_delivery_pre_c = 0; | |||
1102 | double refcyc_per_line_delivery_l = 0; | |||
1103 | double refcyc_per_line_delivery_c = 0; | |||
1104 | ||||
1105 | double refcyc_per_req_delivery_pre_l = 0; | |||
1106 | double refcyc_per_req_delivery_pre_c = 0; | |||
1107 | double refcyc_per_req_delivery_l = 0; | |||
1108 | double refcyc_per_req_delivery_c = 0; | |||
1109 | ||||
1110 | unsigned int full_recout_width = 0; | |||
1111 | double refcyc_per_req_delivery_pre_cur0 = 0; | |||
1112 | double refcyc_per_req_delivery_cur0 = 0; | |||
1113 | double refcyc_per_req_delivery_pre_cur1 = 0; | |||
1114 | double refcyc_per_req_delivery_cur1 = 0; | |||
1115 | ||||
1116 | unsigned int pipe_index_in_combine[DC__NUM_PIPES__MAX6] = { 0 }; | |||
1117 | ||||
1118 | memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs))__builtin_memset((disp_dlg_regs), (0), (sizeof(*disp_dlg_regs ))); | |||
1119 | memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs))__builtin_memset((disp_ttu_regs), (0), (sizeof(*disp_ttu_regs ))); | |||
1120 | ||||
1121 | dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en){do { } while(0); }; | |||
1122 | dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en){do { } while(0); }; | |||
1123 | dml_print("DML_DLG: %s: vm_en = %d\n", __func__, vm_en){do { } while(0); }; | |||
1124 | dml_print("DML_DLG: %s: ignore_viewport_pos = %d\n", __func__, ignore_viewport_pos){do { } while(0); }; | |||
1125 | dml_print("DML_DLG: %s: immediate_flip_support = %d\n", __func__, immediate_flip_support){do { } while(0); }; | |||
1126 | ||||
1127 | dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz){do { } while(0); }; | |||
1128 | dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz){do { } while(0); }; | |||
1129 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; | |||
1130 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; | |||
1131 | dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced){do { } while(0); }; | |||
1132 | ASSERT(ref_freq_to_pix_freq < 4.0)do { if (({ static int __warned; int __ret = !!(!(ref_freq_to_pix_freq < 4.0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(ref_freq_to_pix_freq < 4.0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1132); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1133 | ||||
1134 | disp_dlg_regs->ref_freq_to_pix_freq = | |||
1135 | (unsigned int)(ref_freq_to_pix_freq * dml_pow(2, 19)); | |||
1136 | disp_dlg_regs->refcyc_per_htotal = (unsigned int)(ref_freq_to_pix_freq * (double)htotal | |||
1137 | * dml_pow(2, 8)); | |||
1138 | disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits | |||
1139 | ||||
1140 | min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; | |||
1141 | t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); | |||
1142 | min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1143 | ||||
1144 | min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double)htotal; | |||
1145 | dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; | |||
1146 | ||||
1147 | disp_dlg_regs->min_dst_y_next_start = (unsigned int)(((double)dlg_vblank_start | |||
1148 | ) * dml_pow(2, 2)); | |||
1149 | ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))) ; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1149); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1150 | ||||
1151 | dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n",{do { } while(0); } | |||
1152 | __func__,{do { } while(0); } | |||
1153 | min_dcfclk_mhz){do { } while(0); }; | |||
1154 | dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n",{do { } while(0); } | |||
1155 | __func__,{do { } while(0); } | |||
1156 | min_ttu_vblank){do { } while(0); }; | |||
1157 | dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n",{do { } while(0); } | |||
1158 | __func__,{do { } while(0); } | |||
1159 | min_dst_y_ttu_vblank){do { } while(0); }; | |||
1160 | dml_print("DML_DLG: %s: t_calc_us = %3.2f\n",{do { } while(0); } | |||
1161 | __func__,{do { } while(0); } | |||
1162 | t_calc_us){do { } while(0); }; | |||
1163 | dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",{do { } while(0); } | |||
1164 | __func__,{do { } while(0); } | |||
1165 | disp_dlg_regs->min_dst_y_next_start){do { } while(0); }; | |||
1166 | dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n",{do { } while(0); } | |||
1167 | __func__,{do { } while(0); } | |||
1168 | ref_freq_to_pix_freq){do { } while(0); }; | |||
1169 | ||||
1170 | // ------------------------- | |||
1171 | // Section 1.15.2.2: Prefetch, Active and TTU | |||
1172 | // ------------------------- | |||
1173 | // Prefetch Calc | |||
1174 | // Source | |||
1175 | // dcc_en = src.dcc; | |||
1176 | dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); | |||
1177 | mode_422 = 0; // TODO | |||
1178 | access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed | |||
1179 | vp_height_l = src->viewport_height; | |||
1180 | vp_width_l = src->viewport_width; | |||
1181 | vp_height_c = src->viewport_height_c; | |||
1182 | vp_width_c = src->viewport_width_c; | |||
1183 | ||||
1184 | // Scaling | |||
1185 | htaps_l = taps->htaps; | |||
1186 | htaps_c = taps->htaps_c; | |||
1187 | hratio_l = scl->hscl_ratio; | |||
1188 | hratio_c = scl->hscl_ratio_c; | |||
1189 | vratio_l = scl->vscl_ratio; | |||
1190 | vratio_c = scl->vscl_ratio_c; | |||
1191 | scl_enable = scl->scl_enable; | |||
1192 | ||||
1193 | line_time_in_us = (htotal / pclk_freq_in_mhz); | |||
1194 | swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; | |||
1195 | dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; | |||
1196 | swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; | |||
1197 | dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; | |||
1198 | ||||
1199 | meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; | |||
1200 | meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; | |||
1201 | vupdate_offset = dst->vupdate_offset; | |||
1202 | vupdate_width = dst->vupdate_width; | |||
1203 | vready_offset = dst->vready_offset; | |||
1204 | ||||
1205 | dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; | |||
1206 | dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; | |||
1207 | ||||
1208 | if (scl_enable) | |||
1209 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; | |||
1210 | else | |||
1211 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; | |||
1212 | ||||
1213 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter | |||
1214 | + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; | |||
1215 | ||||
1216 | if (dout->dsc_enable) { | |||
1217 | double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1218 | ||||
1219 | dispclk_delay_subtotal += dsc_delay; | |||
1220 | } | |||
1221 | ||||
1222 | pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz | |||
1223 | + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; | |||
1224 | ||||
1225 | vstartup_start = dst->vstartup_start; | |||
1226 | if (interlaced) { | |||
1227 | if (vstartup_start / 2.0 | |||
1228 | - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal | |||
1229 | <= vblank_end / 2.0) | |||
1230 | disp_dlg_regs->vready_after_vcount0 = 1; | |||
1231 | else | |||
1232 | disp_dlg_regs->vready_after_vcount0 = 0; | |||
1233 | } else { | |||
1234 | if (vstartup_start | |||
1235 | - (double)(vready_offset + vupdate_width + vupdate_offset) / htotal | |||
1236 | <= vblank_end) | |||
1237 | disp_dlg_regs->vready_after_vcount0 = 1; | |||
1238 | else | |||
1239 | disp_dlg_regs->vready_after_vcount0 = 0; | |||
1240 | } | |||
1241 | ||||
1242 | // TODO: Where is this coming from? | |||
1243 | if (interlaced) | |||
1244 | vstartup_start = vstartup_start / 2; | |||
1245 | ||||
1246 | // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? | |||
1247 | if (vstartup_start >= min_vblank) { | |||
1248 | dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",{do { } while(0); } | |||
1249 | __func__,{do { } while(0); } | |||
1250 | vblank_start,{do { } while(0); } | |||
1251 | vblank_end){do { } while(0); }; | |||
1252 | dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } | |||
1253 | __func__,{do { } while(0); } | |||
1254 | vstartup_start,{do { } while(0); } | |||
1255 | min_vblank){do { } while(0); }; | |||
1256 | min_vblank = vstartup_start + 1; | |||
1257 | dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } | |||
1258 | __func__,{do { } while(0); } | |||
1259 | vstartup_start,{do { } while(0); } | |||
1260 | min_vblank){do { } while(0); }; | |||
1261 | } | |||
1262 | ||||
1263 | dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1264 | dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1265 | ||||
1266 | // do some adjustment on the dst_after scaler to account for odm combine mode | |||
1267 | dml_print("DML_DLG: %s: input dst_x_after_scaler = %d\n",{do { } while(0); } | |||
1268 | __func__,{do { } while(0); } | |||
1269 | dst_x_after_scaler){do { } while(0); }; | |||
1270 | dml_print("DML_DLG: %s: input dst_y_after_scaler = %d\n",{do { } while(0); } | |||
1271 | __func__,{do { } while(0); } | |||
1272 | dst_y_after_scaler){do { } while(0); }; | |||
1273 | ||||
1274 | // need to figure out which side of odm combine we're in | |||
1275 | if (dst->odm_combine) { | |||
1276 | // figure out which pipes go together | |||
1277 | bool_Bool visited[DC__NUM_PIPES__MAX6] = { false0 }; | |||
1278 | unsigned int i, j, k; | |||
1279 | ||||
1280 | for (k = 0; k < num_pipes; ++k) { | |||
1281 | visited[k] = false0; | |||
1282 | pipe_index_in_combine[k] = 0; | |||
1283 | } | |||
1284 | ||||
1285 | for (i = 0; i < num_pipes; i++) { | |||
1286 | if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) { | |||
1287 | ||||
1288 | unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp; | |||
1289 | unsigned int grp_idx = 0; | |||
1290 | ||||
1291 | for (j = i; j < num_pipes; j++) { | |||
1292 | if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp | |||
1293 | && e2e_pipe_param[j].pipe.src.is_hsplit && !visited[j]) { | |||
1294 | pipe_index_in_combine[j] = grp_idx; | |||
1295 | dml_print("DML_DLG: %s: pipe[%d] is in grp %d idx %d\n", __func__, j, grp, grp_idx){do { } while(0); }; | |||
1296 | grp_idx++; | |||
1297 | visited[j] = true1; | |||
1298 | } | |||
1299 | } | |||
1300 | } | |||
1301 | } | |||
1302 | ||||
1303 | } | |||
1304 | ||||
1305 | if (dst->odm_combine == dm_odm_combine_mode_disabled) { | |||
1306 | disp_dlg_regs->refcyc_h_blank_end = (unsigned int)((double) hblank_end * ref_freq_to_pix_freq); | |||
1307 | } else { | |||
1308 | unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TODO: We should really check that 4to1 is supported before setting it to 4 | |||
1309 | unsigned int odm_pipe_index = pipe_index_in_combine[pipe_idx]; | |||
1310 | disp_dlg_regs->refcyc_h_blank_end = (unsigned int)(((double) hblank_end + odm_pipe_index * (double) dst->hactive / odm_combine_factor) * ref_freq_to_pix_freq); | |||
1311 | } | |||
1312 | ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1312); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1313 | ||||
1314 | dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal){do { } while(0); }; | |||
1315 | dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n",{do { } while(0); } | |||
1316 | __func__,{do { } while(0); } | |||
1317 | pixel_rate_delay_subtotal){do { } while(0); }; | |||
1318 | dml_print("DML_DLG: %s: dst_x_after_scaler[%d] = %d\n",{do { } while(0); } | |||
1319 | __func__,{do { } while(0); } | |||
1320 | pipe_idx,{do { } while(0); } | |||
1321 | dst_x_after_scaler){do { } while(0); }; | |||
1322 | dml_print("DML_DLG: %s: dst_y_after_scaler[%d] = %d\n",{do { } while(0); } | |||
1323 | __func__,{do { } while(0); } | |||
1324 | pipe_idx,{do { } while(0); } | |||
1325 | dst_y_after_scaler){do { } while(0); }; | |||
1326 | ||||
1327 | // Lwait | |||
1328 | // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? | |||
1329 | line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us; | |||
1330 | if (cstate_en) | |||
1331 | line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); | |||
1332 | if (pstate_en) | |||
1333 | line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us | |||
1334 | + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? | |||
1335 | line_wait); | |||
1336 | line_wait = line_wait / line_time_in_us; | |||
1337 | ||||
1338 | dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1339 | dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch){do { } while(0); }; | |||
1340 | ||||
1341 | dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, | |||
1342 | e2e_pipe_param, | |||
1343 | num_pipes, | |||
1344 | pipe_idx); | |||
1345 | dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, | |||
1346 | e2e_pipe_param, | |||
1347 | num_pipes, | |||
1348 | pipe_idx); | |||
1349 | dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1350 | dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1351 | ||||
1352 | max_dst_y_per_vm_vblank = 32.0; //U5.2 | |||
1353 | max_dst_y_per_row_vblank = 16.0; //U4.2 | |||
1354 | ||||
1355 | // magic! | |||
1356 | if (htotal <= 75) { | |||
1357 | min_vblank = 300; | |||
1358 | max_dst_y_per_vm_vblank = 100.0; | |||
1359 | max_dst_y_per_row_vblank = 100.0; | |||
1360 | } | |||
1361 | ||||
1362 | dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip){do { } while(0); }; | |||
1363 | dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip){do { } while(0); }; | |||
1364 | dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank){do { } while(0); }; | |||
1365 | dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank){do { } while(0); }; | |||
1366 | ||||
1367 | ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1367); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1368 | ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_row_vblank < max_dst_y_per_row_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_row_vblank < max_dst_y_per_row_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1368); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1369 | ||||
1370 | ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))do { if (({ static int __warned; int __ret = !!(!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1370); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1371 | lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); | |||
1372 | ||||
1373 | dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw){do { } while(0); }; | |||
1374 | ||||
1375 | vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1376 | vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | |||
1377 | ||||
1378 | dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l){do { } while(0); }; | |||
1379 | dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c){do { } while(0); }; | |||
1380 | ||||
1381 | // Active | |||
1382 | req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; | |||
1383 | req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; | |||
1384 | meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; | |||
1385 | meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; | |||
1386 | swath_width_pixels_ub_l = 0; | |||
1387 | swath_width_pixels_ub_c = 0; | |||
1388 | scaler_rec_in_width_l = 0; | |||
1389 | scaler_rec_in_width_c = 0; | |||
1390 | dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; | |||
1391 | dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; | |||
1392 | ||||
1393 | if (mode_422) { | |||
1394 | swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element | |||
1395 | swath_width_pixels_ub_c = swath_width_ub_c * 2; | |||
1396 | } else { | |||
1397 | swath_width_pixels_ub_l = swath_width_ub_l * 1; | |||
1398 | swath_width_pixels_ub_c = swath_width_ub_c * 1; | |||
1399 | } | |||
1400 | ||||
1401 | hscale_pixel_rate_l = 0.; | |||
1402 | hscale_pixel_rate_c = 0.; | |||
1403 | min_hratio_fact_l = 1.0; | |||
1404 | min_hratio_fact_c = 1.0; | |||
1405 | ||||
1406 | if (hratio_l <= 1) | |||
1407 | min_hratio_fact_l = 2.0; | |||
1408 | else if (htaps_l <= 6) { | |||
1409 | if ((hratio_l * 2.0) > 4.0) | |||
1410 | min_hratio_fact_l = 4.0; | |||
1411 | else | |||
1412 | min_hratio_fact_l = hratio_l * 2.0; | |||
1413 | } else { | |||
1414 | if (hratio_l > 4.0) | |||
1415 | min_hratio_fact_l = 4.0; | |||
1416 | else | |||
1417 | min_hratio_fact_l = hratio_l; | |||
1418 | } | |||
1419 | ||||
1420 | hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; | |||
1421 | ||||
1422 | if (hratio_c <= 1) | |||
1423 | min_hratio_fact_c = 2.0; | |||
1424 | else if (htaps_c <= 6) { | |||
1425 | if ((hratio_c * 2.0) > 4.0) | |||
1426 | min_hratio_fact_c = 4.0; | |||
1427 | else | |||
1428 | min_hratio_fact_c = hratio_c * 2.0; | |||
1429 | } else { | |||
1430 | if (hratio_c > 4.0) | |||
1431 | min_hratio_fact_c = 4.0; | |||
1432 | else | |||
1433 | min_hratio_fact_c = hratio_c; | |||
1434 | } | |||
1435 | ||||
1436 | hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; | |||
1437 | ||||
1438 | refcyc_per_line_delivery_pre_l = 0.; | |||
1439 | refcyc_per_line_delivery_pre_c = 0.; | |||
1440 | refcyc_per_line_delivery_l = 0.; | |||
1441 | refcyc_per_line_delivery_c = 0.; | |||
1442 | ||||
1443 | refcyc_per_req_delivery_pre_l = 0.; | |||
1444 | refcyc_per_req_delivery_pre_c = 0.; | |||
1445 | refcyc_per_req_delivery_l = 0.; | |||
1446 | refcyc_per_req_delivery_c = 0.; | |||
1447 | ||||
1448 | full_recout_width = 0; | |||
1449 | // In ODM | |||
1450 | if (src->is_hsplit) { | |||
1451 | // This "hack" is only allowed (and valid) for MPC combine. In ODM | |||
1452 | // combine, you MUST specify the full_recout_width...according to Oswin | |||
1453 | if (dst->full_recout_width == 0 && !dst->odm_combine) { | |||
1454 | dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",{do { } while(0); } | |||
1455 | __func__){do { } while(0); }; | |||
1456 | full_recout_width = dst->recout_width * 2; // assume half split for dcn1 | |||
1457 | } else | |||
1458 | full_recout_width = dst->full_recout_width; | |||
1459 | } else | |||
1460 | full_recout_width = dst->recout_width; | |||
1461 | ||||
1462 | // As of DCN2, mpc_combine and odm_combine are mutually exclusive | |||
1463 | refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, | |||
1464 | refclk_freq_in_mhz, | |||
1465 | pclk_freq_in_mhz, | |||
1466 | dst->odm_combine, | |||
1467 | full_recout_width, | |||
1468 | dst->hactive, | |||
1469 | vratio_pre_l, | |||
1470 | hscale_pixel_rate_l, | |||
1471 | swath_width_pixels_ub_l, | |||
1472 | 1); // per line | |||
1473 | ||||
1474 | refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, | |||
1475 | refclk_freq_in_mhz, | |||
1476 | pclk_freq_in_mhz, | |||
1477 | dst->odm_combine, | |||
1478 | full_recout_width, | |||
1479 | dst->hactive, | |||
1480 | vratio_l, | |||
1481 | hscale_pixel_rate_l, | |||
1482 | swath_width_pixels_ub_l, | |||
1483 | 1); // per line | |||
1484 | ||||
1485 | dml_print("DML_DLG: %s: full_recout_width = %d\n",{do { } while(0); } | |||
1486 | __func__,{do { } while(0); } | |||
1487 | full_recout_width){do { } while(0); }; | |||
1488 | dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n",{do { } while(0); } | |||
1489 | __func__,{do { } while(0); } | |||
1490 | hscale_pixel_rate_l){do { } while(0); }; | |||
1491 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",{do { } while(0); } | |||
1492 | __func__,{do { } while(0); } | |||
1493 | refcyc_per_line_delivery_pre_l){do { } while(0); }; | |||
1494 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n",{do { } while(0); } | |||
1495 | __func__,{do { } while(0); } | |||
1496 | refcyc_per_line_delivery_l){do { } while(0); }; | |||
1497 | ||||
1498 | if (dual_plane) { | |||
1499 | refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, | |||
1500 | refclk_freq_in_mhz, | |||
1501 | pclk_freq_in_mhz, | |||
1502 | dst->odm_combine, | |||
1503 | full_recout_width, | |||
1504 | dst->hactive, | |||
1505 | vratio_pre_c, | |||
1506 | hscale_pixel_rate_c, | |||
1507 | swath_width_pixels_ub_c, | |||
1508 | 1); // per line | |||
1509 | ||||
1510 | refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, | |||
1511 | refclk_freq_in_mhz, | |||
1512 | pclk_freq_in_mhz, | |||
1513 | dst->odm_combine, | |||
1514 | full_recout_width, | |||
1515 | dst->hactive, | |||
1516 | vratio_c, | |||
1517 | hscale_pixel_rate_c, | |||
1518 | swath_width_pixels_ub_c, | |||
1519 | 1); // per line | |||
1520 | ||||
1521 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",{do { } while(0); } | |||
1522 | __func__,{do { } while(0); } | |||
1523 | refcyc_per_line_delivery_pre_c){do { } while(0); }; | |||
1524 | dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n",{do { } while(0); } | |||
1525 | __func__,{do { } while(0); } | |||
1526 | refcyc_per_line_delivery_c){do { } while(0); }; | |||
1527 | } | |||
1528 | ||||
1529 | // smehta: this is a hack added until we get the real dml, sorry, need to make progress | |||
1530 | if (src->dynamic_metadata_enable && src->gpuvm) { | |||
1531 | unsigned int levels = mode_lib->ip.gpuvm_max_page_table_levels; | |||
1532 | double ref_cycles; | |||
1533 | ||||
1534 | if (src->hostvm) | |||
1535 | levels = levels * (mode_lib->ip.hostvm_max_page_table_levels+1); | |||
1536 | ||||
1537 | ref_cycles = (levels * mode_lib->soc.urgent_latency_vm_data_only_us) * refclk_freq_in_mhz; | |||
1538 | dml_print("BENyamin: dst_y_prefetch = %f %d %f %f \n",{do { } while(0); } | |||
1539 | ref_cycles, levels, mode_lib->soc.urgent_latency_vm_data_only_us, refclk_freq_in_mhz){do { } while(0); }; | |||
1540 | disp_dlg_regs->refcyc_per_vm_dmdata = (unsigned int) ref_cycles; | |||
1541 | } | |||
1542 | dml_print("BENyamin: dmdta_en vm = %d %d \n",{do { } while(0); } | |||
1543 | src->dynamic_metadata_enable, src->vm){do { } while(0); }; | |||
1544 | // TTU - Luma / Chroma | |||
1545 | if (access_dir) { // vertical access | |||
1546 | scaler_rec_in_width_l = vp_height_l; | |||
1547 | scaler_rec_in_width_c = vp_height_c; | |||
1548 | } else { | |||
1549 | scaler_rec_in_width_l = vp_width_l; | |||
1550 | scaler_rec_in_width_c = vp_width_c; | |||
1551 | } | |||
1552 | ||||
1553 | refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, | |||
1554 | refclk_freq_in_mhz, | |||
1555 | pclk_freq_in_mhz, | |||
1556 | dst->odm_combine, | |||
1557 | full_recout_width, | |||
1558 | dst->hactive, | |||
1559 | vratio_pre_l, | |||
1560 | hscale_pixel_rate_l, | |||
1561 | scaler_rec_in_width_l, | |||
1562 | req_per_swath_ub_l); // per req | |||
1563 | refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, | |||
1564 | refclk_freq_in_mhz, | |||
1565 | pclk_freq_in_mhz, | |||
1566 | dst->odm_combine, | |||
1567 | full_recout_width, | |||
1568 | dst->hactive, | |||
1569 | vratio_l, | |||
1570 | hscale_pixel_rate_l, | |||
1571 | scaler_rec_in_width_l, | |||
1572 | req_per_swath_ub_l); // per req | |||
1573 | ||||
1574 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",{do { } while(0); } | |||
1575 | __func__,{do { } while(0); } | |||
1576 | refcyc_per_req_delivery_pre_l){do { } while(0); }; | |||
1577 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n",{do { } while(0); } | |||
1578 | __func__,{do { } while(0); } | |||
1579 | refcyc_per_req_delivery_l){do { } while(0); }; | |||
1580 | ||||
1581 | ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1581); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1582 | ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1582); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1583 | ||||
1584 | if (dual_plane) { | |||
1585 | refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, | |||
1586 | refclk_freq_in_mhz, | |||
1587 | pclk_freq_in_mhz, | |||
1588 | dst->odm_combine, | |||
1589 | full_recout_width, | |||
1590 | dst->hactive, | |||
1591 | vratio_pre_c, | |||
1592 | hscale_pixel_rate_c, | |||
1593 | scaler_rec_in_width_c, | |||
1594 | req_per_swath_ub_c); // per req | |||
1595 | refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, | |||
1596 | refclk_freq_in_mhz, | |||
1597 | pclk_freq_in_mhz, | |||
1598 | dst->odm_combine, | |||
1599 | full_recout_width, | |||
1600 | dst->hactive, | |||
1601 | vratio_c, | |||
1602 | hscale_pixel_rate_c, | |||
1603 | scaler_rec_in_width_c, | |||
1604 | req_per_swath_ub_c); // per req | |||
1605 | ||||
1606 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",{do { } while(0); } | |||
1607 | __func__,{do { } while(0); } | |||
1608 | refcyc_per_req_delivery_pre_c){do { } while(0); }; | |||
1609 | dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n",{do { } while(0); } | |||
1610 | __func__,{do { } while(0); } | |||
1611 | refcyc_per_req_delivery_c){do { } while(0); }; | |||
1612 | ||||
1613 | ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1613); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1614 | ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1614); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1615 | } | |||
1616 | ||||
1617 | // TTU - Cursor | |||
1618 | refcyc_per_req_delivery_pre_cur0 = 0.0; | |||
1619 | refcyc_per_req_delivery_cur0 = 0.0; | |||
1620 | if (src->num_cursors > 0) { | |||
1621 | calculate_ttu_cursor(mode_lib, | |||
1622 | &refcyc_per_req_delivery_pre_cur0, | |||
1623 | &refcyc_per_req_delivery_cur0, | |||
1624 | refclk_freq_in_mhz, | |||
1625 | ref_freq_to_pix_freq, | |||
1626 | hscale_pixel_rate_l, | |||
1627 | scl->hscl_ratio, | |||
1628 | vratio_pre_l, | |||
1629 | vratio_l, | |||
1630 | src->cur0_src_width, | |||
1631 | (enum cursor_bpp)(src->cur0_bpp)); | |||
1632 | } | |||
1633 | ||||
1634 | refcyc_per_req_delivery_pre_cur1 = 0.0; | |||
1635 | refcyc_per_req_delivery_cur1 = 0.0; | |||
1636 | if (src->num_cursors > 1) { | |||
1637 | calculate_ttu_cursor(mode_lib, | |||
1638 | &refcyc_per_req_delivery_pre_cur1, | |||
1639 | &refcyc_per_req_delivery_cur1, | |||
1640 | refclk_freq_in_mhz, | |||
1641 | ref_freq_to_pix_freq, | |||
1642 | hscale_pixel_rate_l, | |||
1643 | scl->hscl_ratio, | |||
1644 | vratio_pre_l, | |||
1645 | vratio_l, | |||
1646 | src->cur1_src_width, | |||
1647 | (enum cursor_bpp)(src->cur1_bpp)); | |||
1648 | } | |||
1649 | ||||
1650 | // TTU - Misc | |||
1651 | // all hard-coded | |||
1652 | ||||
1653 | // Assignment to register structures | |||
1654 | disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line | |||
1655 | ASSERT(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8)do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_after_scaler < (unsigned int)8)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_dlg_regs->dst_y_after_scaler < (unsigned int)8)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1655); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1656 | disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk | |||
1657 | ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)) ); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1657); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1658 | disp_dlg_regs->dst_y_prefetch = (unsigned int)(dst_y_prefetch * dml_pow(2, 2)); | |||
1659 | disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int)(dst_y_per_vm_vblank * dml_pow(2, 2)); | |||
1660 | disp_dlg_regs->dst_y_per_row_vblank = (unsigned int)(dst_y_per_row_vblank * dml_pow(2, 2)); | |||
1661 | disp_dlg_regs->dst_y_per_vm_flip = (unsigned int)(dst_y_per_vm_flip * dml_pow(2, 2)); | |||
1662 | disp_dlg_regs->dst_y_per_row_flip = (unsigned int)(dst_y_per_row_flip * dml_pow(2, 2)); | |||
1663 | ||||
1664 | disp_dlg_regs->vratio_prefetch = (unsigned int)(vratio_pre_l * dml_pow(2, 19)); | |||
1665 | disp_dlg_regs->vratio_prefetch_c = (unsigned int)(vratio_pre_c * dml_pow(2, 19)); | |||
1666 | ||||
1667 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank){do { } while(0); }; | |||
1668 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank){do { } while(0); }; | |||
1669 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip){do { } while(0); }; | |||
1670 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip){do { } while(0); }; | |||
1671 | disp_dlg_regs->refcyc_per_pte_group_vblank_l = | |||
1672 | (unsigned int)(dst_y_per_row_vblank * (double)htotal | |||
1673 | * ref_freq_to_pix_freq / (double)dpte_groups_per_row_ub_l); | |||
1674 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1674); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1675 | ||||
1676 | if (dual_plane) { | |||
1677 | disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int)(dst_y_per_row_vblank | |||
1678 | * (double)htotal * ref_freq_to_pix_freq | |||
1679 | / (double)dpte_groups_per_row_ub_c); | |||
1680 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_cdo { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1681); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0) | |||
1681 | < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1681); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1682 | } | |||
1683 | ||||
1684 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = | |||
1685 | (unsigned int)(dst_y_per_row_vblank * (double)htotal | |||
1686 | * ref_freq_to_pix_freq / (double)meta_chunks_per_row_ub_l); | |||
1687 | ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1687); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1688 | ||||
1689 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = | |||
1690 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now | |||
1691 | ||||
1692 | disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int)(dst_y_per_row_flip * htotal | |||
1693 | * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; | |||
1694 | disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int)(dst_y_per_row_flip * htotal | |||
1695 | * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; | |||
1696 | ||||
1697 | if (dual_plane) { | |||
1698 | disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int)(dst_y_per_row_flip | |||
1699 | * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; | |||
1700 | disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int)(dst_y_per_row_flip | |||
1701 | * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; | |||
1702 | } | |||
1703 | ||||
1704 | disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; | |||
1705 | disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; | |||
1706 | disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); | |||
1707 | disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); | |||
1708 | ||||
1709 | // Clamp to max for now | |||
1710 | if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) | |||
1711 | disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; | |||
1712 | ||||
1713 | if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) | |||
1714 | disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; | |||
1715 | ||||
1716 | if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) | |||
1717 | disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; | |||
1718 | ||||
1719 | if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) | |||
1720 | disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; | |||
1721 | ||||
1722 | disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int)((double)dpte_row_height_l | |||
1723 | / (double)vratio_l * dml_pow(2, 2)); | |||
1724 | ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1724); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1725 | ||||
1726 | if (dual_plane) { | |||
1727 | disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int)((double)dpte_row_height_c | |||
1728 | / (double)vratio_c * dml_pow(2, 2)); | |||
1729 | if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int)dml_pow(2, 17)) { | |||
1730 | dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",{do { } while(0); } | |||
1731 | __func__,{do { } while(0); } | |||
1732 | disp_dlg_regs->dst_y_per_pte_row_nom_c,{do { } while(0); } | |||
1733 | (unsigned int)dml_pow(2, 17) - 1){do { } while(0); }; | |||
1734 | } | |||
1735 | } | |||
1736 | ||||
1737 | disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int)((double)meta_row_height_l | |||
1738 | / (double)vratio_l * dml_pow(2, 2)); | |||
1739 | ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1739); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1740 | ||||
1741 | disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now | |||
1742 | ||||
1743 | dml_print("DML: Trow: %fus\n", line_time_in_us * (double)dpte_row_height_l / (double)vratio_l){do { } while(0); }; | |||
1744 | ||||
1745 | disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int)((double)dpte_row_height_l | |||
1746 | / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq | |||
1747 | / (double)dpte_groups_per_row_ub_l); | |||
1748 | if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int)dml_pow(2, 23)) | |||
1749 | disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; | |||
1750 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int)((double)meta_row_height_l | |||
1751 | / (double)vratio_l * (double)htotal * ref_freq_to_pix_freq | |||
1752 | / (double)meta_chunks_per_row_ub_l); | |||
1753 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int)dml_pow(2, 23)) | |||
1754 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; | |||
1755 | ||||
1756 | if (dual_plane) { | |||
1757 | disp_dlg_regs->refcyc_per_pte_group_nom_c = | |||
1758 | (unsigned int)((double)dpte_row_height_c / (double)vratio_c | |||
1759 | * (double)htotal * ref_freq_to_pix_freq | |||
1760 | / (double)dpte_groups_per_row_ub_c); | |||
1761 | if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int)dml_pow(2, 23)) | |||
1762 | disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; | |||
1763 | ||||
1764 | // TODO: Is this the right calculation? Does htotal need to be halved? | |||
1765 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = | |||
1766 | (unsigned int)((double)meta_row_height_c / (double)vratio_c | |||
1767 | * (double)htotal * ref_freq_to_pix_freq | |||
1768 | / (double)meta_chunks_per_row_ub_c); | |||
1769 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int)dml_pow(2, 23)) | |||
1770 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; | |||
1771 | } | |||
1772 | ||||
1773 | disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_l, | |||
1774 | 1); | |||
1775 | disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int)dml_floor(refcyc_per_line_delivery_l, | |||
1776 | 1); | |||
1777 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1777); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1778 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1778); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1779 | ||||
1780 | disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int)dml_floor(refcyc_per_line_delivery_pre_c, | |||
1781 | 1); | |||
1782 | disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int)dml_floor(refcyc_per_line_delivery_c, | |||
1783 | 1); | |||
1784 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1784); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1785 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1785); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1786 | ||||
1787 | disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; | |||
1788 | disp_dlg_regs->dst_y_offset_cur0 = 0; | |||
1789 | disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; | |||
1790 | disp_dlg_regs->dst_y_offset_cur1 = 0; | |||
1791 | ||||
1792 | disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off | |||
1793 | ||||
1794 | disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int)(refcyc_per_req_delivery_pre_l | |||
1795 | * dml_pow(2, 10)); | |||
1796 | disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int)(refcyc_per_req_delivery_l | |||
1797 | * dml_pow(2, 10)); | |||
1798 | disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int)(refcyc_per_req_delivery_pre_c | |||
1799 | * dml_pow(2, 10)); | |||
1800 | disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int)(refcyc_per_req_delivery_c | |||
1801 | * dml_pow(2, 10)); | |||
1802 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = | |||
1803 | (unsigned int)(refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); | |||
1804 | disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int)(refcyc_per_req_delivery_cur0 | |||
1805 | * dml_pow(2, 10)); | |||
1806 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = | |||
1807 | (unsigned int)(refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); | |||
1808 | disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int)(refcyc_per_req_delivery_cur1 | |||
1809 | * dml_pow(2, 10)); | |||
1810 | disp_ttu_regs->qos_level_low_wm = 0; | |||
1811 | ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_low_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1811); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1812 | disp_ttu_regs->qos_level_high_wm = (unsigned int)(4.0 * (double)htotal | |||
1813 | * ref_freq_to_pix_freq); | |||
1814 | ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_high_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1814); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1815 | ||||
1816 | disp_ttu_regs->qos_level_flip = 14; | |||
1817 | disp_ttu_regs->qos_level_fixed_l = 8; | |||
1818 | disp_ttu_regs->qos_level_fixed_c = 8; | |||
1819 | disp_ttu_regs->qos_level_fixed_cur0 = 8; | |||
1820 | disp_ttu_regs->qos_ramp_disable_l = 0; | |||
1821 | disp_ttu_regs->qos_ramp_disable_c = 0; | |||
1822 | disp_ttu_regs->qos_ramp_disable_cur0 = 0; | |||
1823 | ||||
1824 | disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; | |||
1825 | ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->min_ttu_vblank < dml_pow(2, 24))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c" , 1825); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | |||
1826 | ||||
1827 | print__ttu_regs_st(mode_lib, *disp_ttu_regs); | |||
1828 | print__dlg_regs_st(mode_lib, *disp_dlg_regs); | |||
1829 | } | |||
1830 | ||||
1831 | void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, | |||
1832 | display_dlg_regs_st *dlg_regs, | |||
1833 | display_ttu_regs_st *ttu_regs, | |||
1834 | display_e2e_pipe_params_st *e2e_pipe_param, | |||
1835 | const unsigned int num_pipes, | |||
1836 | const unsigned int pipe_idx, | |||
1837 | const bool_Bool cstate_en, | |||
1838 | const bool_Bool pstate_en, | |||
1839 | const bool_Bool vm_en, | |||
1840 | const bool_Bool ignore_viewport_pos, | |||
1841 | const bool_Bool immediate_flip_support) | |||
1842 | { | |||
1843 | display_rq_params_st rq_param = { 0 }; | |||
1844 | display_dlg_sys_params_st dlg_sys_param = { 0 }; | |||
1845 | ||||
1846 | // Get watermark and Tex. | |||
1847 | dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); | |||
1848 | dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, | |||
1849 | e2e_pipe_param, | |||
1850 | num_pipes); | |||
1851 | dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); | |||
1852 | dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); | |||
1853 | dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); | |||
1854 | dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); | |||
1855 | dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, | |||
1856 | e2e_pipe_param, | |||
1857 | num_pipes); | |||
1858 | dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, | |||
1859 | e2e_pipe_param, | |||
1860 | num_pipes); | |||
1861 | dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency | |||
1862 | / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated | |||
1863 | ||||
1864 | print__dlg_sys_params_st(mode_lib, dlg_sys_param); | |||
1865 | ||||
1866 | // system parameter calculation done | |||
1867 | ||||
1868 | dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx){do { } while(0); }; | |||
1869 | dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe); | |||
1870 | dml_rq_dlg_get_dlg_params(mode_lib, | |||
1871 | e2e_pipe_param, | |||
1872 | num_pipes, | |||
1873 | pipe_idx, | |||
1874 | dlg_regs, | |||
1875 | ttu_regs, | |||
1876 | rq_param.dlg, | |||
1877 | dlg_sys_param, | |||
1878 | cstate_en, | |||
1879 | pstate_en, | |||
1880 | vm_en, | |||
1881 | ignore_viewport_pos, | |||
1882 | immediate_flip_support); | |||
1883 | dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx){do { } while(0); }; | |||
1884 | } | |||
1885 | ||||
1886 | #endif |