File: | dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c |
Warning: | line 527, column 40 Division by zero |
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1 | /* | ||||
2 | * Copyright 2017 Advanced Micro Devices, Inc. | ||||
3 | * | ||||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||
5 | * copy of this software and associated documentation files (the "Software"), | ||||
6 | * to deal in the Software without restriction, including without limitation | ||||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||||
9 | * Software is furnished to do so, subject to the following conditions: | ||||
10 | * | ||||
11 | * The above copyright notice and this permission notice shall be included in | ||||
12 | * all copies or substantial portions of the Software. | ||||
13 | * | ||||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||||
21 | * | ||||
22 | * Authors: AMD | ||||
23 | * | ||||
24 | */ | ||||
25 | |||||
26 | |||||
27 | #include "../display_mode_lib.h" | ||||
28 | #include "../display_mode_vba.h" | ||||
29 | #include "../dml_inline_defs.h" | ||||
30 | #include "display_rq_dlg_calc_21.h" | ||||
31 | |||||
32 | /* | ||||
33 | * NOTE: | ||||
34 | * This file is gcc-parseable HW gospel, coming straight from HW engineers. | ||||
35 | * | ||||
36 | * It doesn't adhere to Linux kernel style and sometimes will do things in odd | ||||
37 | * ways. Unless there is something clearly wrong with it the code should | ||||
38 | * remain as-is as it provides us with a guarantee from HW that it is correct. | ||||
39 | */ | ||||
40 | |||||
41 | static void calculate_ttu_cursor( | ||||
42 | struct display_mode_lib *mode_lib, | ||||
43 | double *refcyc_per_req_delivery_pre_cur, | ||||
44 | double *refcyc_per_req_delivery_cur, | ||||
45 | double refclk_freq_in_mhz, | ||||
46 | double ref_freq_to_pix_freq, | ||||
47 | double hscale_pixel_rate_l, | ||||
48 | double hscl_ratio, | ||||
49 | double vratio_pre_l, | ||||
50 | double vratio_l, | ||||
51 | unsigned int cur_width, | ||||
52 | enum cursor_bpp cur_bpp); | ||||
53 | |||||
54 | static unsigned int get_bytes_per_element(enum source_format_class source_format, bool_Bool is_chroma) | ||||
55 | { | ||||
56 | unsigned int ret_val = 0; | ||||
57 | |||||
58 | if (source_format == dm_444_16) { | ||||
59 | if (!is_chroma) | ||||
60 | ret_val = 2; | ||||
61 | } else if (source_format == dm_444_32) { | ||||
62 | if (!is_chroma) | ||||
63 | ret_val = 4; | ||||
64 | } else if (source_format == dm_444_64) { | ||||
65 | if (!is_chroma) | ||||
66 | ret_val = 8; | ||||
67 | } else if (source_format
| ||||
68 | if (is_chroma) | ||||
69 | ret_val = 2; | ||||
70 | else | ||||
71 | ret_val = 1; | ||||
72 | } else if (source_format
| ||||
73 | if (is_chroma) | ||||
74 | ret_val = 4; | ||||
75 | else | ||||
76 | ret_val = 2; | ||||
77 | } else if (source_format == dm_444_8) { | ||||
78 | ret_val = 1; | ||||
79 | } | ||||
80 | return ret_val; | ||||
81 | } | ||||
82 | |||||
83 | static bool_Bool is_dual_plane(enum source_format_class source_format) | ||||
84 | { | ||||
85 | bool_Bool ret_val = false0; | ||||
86 | |||||
87 | if ((source_format == dm_420_8) || (source_format == dm_420_10)) | ||||
88 | ret_val = true1; | ||||
89 | |||||
90 | return ret_val; | ||||
91 | } | ||||
92 | |||||
93 | static double get_refcyc_per_delivery( | ||||
94 | struct display_mode_lib *mode_lib, | ||||
95 | double refclk_freq_in_mhz, | ||||
96 | double pclk_freq_in_mhz, | ||||
97 | bool_Bool odm_combine, | ||||
98 | unsigned int recout_width, | ||||
99 | unsigned int hactive, | ||||
100 | double vratio, | ||||
101 | double hscale_pixel_rate, | ||||
102 | unsigned int delivery_width, | ||||
103 | unsigned int req_per_swath_ub) | ||||
104 | { | ||||
105 | double refcyc_per_delivery = 0.0; | ||||
106 | |||||
107 | if (vratio <= 1.0) { | ||||
108 | if (odm_combine) | ||||
109 | refcyc_per_delivery = (double) refclk_freq_in_mhz | ||||
110 | * dml_min((double) recout_width, (double) hactive / 2.0) | ||||
111 | / pclk_freq_in_mhz / (double) req_per_swath_ub; | ||||
112 | else | ||||
113 | refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width | ||||
114 | / pclk_freq_in_mhz / (double) req_per_swath_ub; | ||||
115 | } else { | ||||
116 | refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width | ||||
117 | / (double) hscale_pixel_rate / (double) req_per_swath_ub; | ||||
118 | } | ||||
119 | |||||
120 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; | ||||
121 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; | ||||
122 | dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width){do { } while(0); }; | ||||
123 | dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio){do { } while(0); }; | ||||
124 | dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub){do { } while(0); }; | ||||
125 | dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery){do { } while(0); }; | ||||
126 | |||||
127 | return refcyc_per_delivery; | ||||
128 | |||||
129 | } | ||||
130 | |||||
131 | static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) | ||||
132 | { | ||||
133 | if (tile_size == dm_256k_tile) | ||||
134 | return (256 * 1024); | ||||
135 | else if (tile_size == dm_64k_tile) | ||||
136 | return (64 * 1024); | ||||
137 | else | ||||
138 | return (4 * 1024); | ||||
139 | } | ||||
140 | |||||
141 | static void extract_rq_sizing_regs( | ||||
142 | struct display_mode_lib *mode_lib, | ||||
143 | display_data_rq_regs_st *rq_regs, | ||||
144 | const display_data_rq_sizing_params_st rq_sizing) | ||||
145 | { | ||||
146 | dml_print("DML_DLG: %s: rq_sizing param\n", __func__){do { } while(0); }; | ||||
147 | print__data_rq_sizing_params_st(mode_lib, rq_sizing); | ||||
148 | |||||
149 | rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; | ||||
150 | |||||
151 | if (rq_sizing.min_chunk_bytes == 0) | ||||
152 | rq_regs->min_chunk_size = 0; | ||||
153 | else | ||||
154 | rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; | ||||
155 | |||||
156 | rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; | ||||
157 | if (rq_sizing.min_meta_chunk_bytes == 0) | ||||
158 | rq_regs->min_meta_chunk_size = 0; | ||||
159 | else | ||||
160 | rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; | ||||
161 | |||||
162 | rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; | ||||
163 | rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; | ||||
164 | } | ||||
165 | |||||
166 | static void extract_rq_regs( | ||||
167 | struct display_mode_lib *mode_lib, | ||||
168 | display_rq_regs_st *rq_regs, | ||||
169 | const display_rq_params_st rq_param) | ||||
170 | { | ||||
171 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; | ||||
172 | unsigned int detile_buf_plane1_addr = 0; | ||||
173 | |||||
174 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); | ||||
175 | |||||
176 | rq_regs->rq_regs_l.pte_row_height_linear = dml_floor( | ||||
177 | dml_log2(rq_param.dlg.rq_l.dpte_row_height), | ||||
178 | 1) - 3; | ||||
179 | |||||
180 | if (rq_param.yuv420) { | ||||
181 | extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); | ||||
182 | rq_regs->rq_regs_c.pte_row_height_linear = dml_floor( | ||||
183 | dml_log2(rq_param.dlg.rq_c.dpte_row_height), | ||||
184 | 1) - 3; | ||||
185 | } | ||||
186 | |||||
187 | rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); | ||||
188 | rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); | ||||
189 | |||||
190 | // FIXME: take the max between luma, chroma chunk size? | ||||
191 | // okay for now, as we are setting chunk_bytes to 8kb anyways | ||||
192 | if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb | ||||
193 | rq_regs->drq_expansion_mode = 0; | ||||
194 | } else { | ||||
195 | rq_regs->drq_expansion_mode = 2; | ||||
196 | } | ||||
197 | rq_regs->prq_expansion_mode = 1; | ||||
198 | rq_regs->mrq_expansion_mode = 1; | ||||
199 | rq_regs->crq_expansion_mode = 1; | ||||
200 | |||||
201 | if (rq_param.yuv420) { | ||||
202 | if ((double) rq_param.misc.rq_l.stored_swath_bytes | ||||
203 | / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { | ||||
204 | detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma | ||||
205 | } else { | ||||
206 | detile_buf_plane1_addr = dml_round_to_multiple( | ||||
207 | (unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), | ||||
208 | 256, | ||||
209 | 0) / 64.0; // 2/3 to chroma | ||||
210 | } | ||||
211 | } | ||||
212 | rq_regs->plane1_base_address = detile_buf_plane1_addr; | ||||
213 | } | ||||
214 | |||||
215 | static void handle_det_buf_split( | ||||
216 | struct display_mode_lib *mode_lib, | ||||
217 | display_rq_params_st *rq_param, | ||||
218 | const display_pipe_source_params_st pipe_src_param) | ||||
219 | { | ||||
220 | unsigned int total_swath_bytes = 0; | ||||
221 | unsigned int swath_bytes_l = 0; | ||||
222 | unsigned int swath_bytes_c = 0; | ||||
223 | unsigned int full_swath_bytes_packed_l = 0; | ||||
224 | unsigned int full_swath_bytes_packed_c = 0; | ||||
225 | bool_Bool req128_l = false0; | ||||
226 | bool_Bool req128_c = false0; | ||||
227 | bool_Bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); | ||||
228 | bool_Bool surf_vert = (pipe_src_param.source_scan == dm_vert); | ||||
229 | unsigned int log2_swath_height_l = 0; | ||||
230 | unsigned int log2_swath_height_c = 0; | ||||
231 | unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; | ||||
232 | |||||
233 | full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; | ||||
234 | full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; | ||||
235 | |||||
236 | if (rq_param->yuv420_10bpc) { | ||||
237 | full_swath_bytes_packed_l = dml_round_to_multiple( | ||||
238 | rq_param->misc.rq_l.full_swath_bytes * 2 / 3, | ||||
239 | 256, | ||||
240 | 1) + 256; | ||||
241 | full_swath_bytes_packed_c = dml_round_to_multiple( | ||||
242 | rq_param->misc.rq_c.full_swath_bytes * 2 / 3, | ||||
243 | 256, | ||||
244 | 1) + 256; | ||||
245 | } | ||||
246 | |||||
247 | if (rq_param->yuv420) { | ||||
248 | total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; | ||||
249 | |||||
250 | if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request | ||||
251 | req128_l = false0; | ||||
252 | req128_c = false0; | ||||
253 | swath_bytes_l = full_swath_bytes_packed_l; | ||||
254 | swath_bytes_c = full_swath_bytes_packed_c; | ||||
255 | } else { //128b request (for luma only for yuv420 8bpc) | ||||
256 | req128_l = true1; | ||||
257 | req128_c = false0; | ||||
258 | swath_bytes_l = full_swath_bytes_packed_l / 2; | ||||
259 | swath_bytes_c = full_swath_bytes_packed_c; | ||||
260 | } | ||||
261 | // Note: assumption, the config that pass in will fit into | ||||
262 | // the detiled buffer. | ||||
263 | } else { | ||||
264 | total_swath_bytes = 2 * full_swath_bytes_packed_l; | ||||
265 | |||||
266 | if (total_swath_bytes <= detile_buf_size_in_bytes) | ||||
267 | req128_l = false0; | ||||
268 | else | ||||
269 | req128_l = true1; | ||||
270 | |||||
271 | swath_bytes_l = total_swath_bytes; | ||||
272 | swath_bytes_c = 0; | ||||
273 | } | ||||
274 | rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; | ||||
275 | rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; | ||||
276 | |||||
277 | if (surf_linear) { | ||||
278 | log2_swath_height_l = 0; | ||||
279 | log2_swath_height_c = 0; | ||||
280 | } else { | ||||
281 | unsigned int swath_height_l; | ||||
282 | unsigned int swath_height_c; | ||||
283 | |||||
284 | if (!surf_vert) { | ||||
285 | swath_height_l = rq_param->misc.rq_l.blk256_height; | ||||
286 | swath_height_c = rq_param->misc.rq_c.blk256_height; | ||||
287 | } else { | ||||
288 | swath_height_l = rq_param->misc.rq_l.blk256_width; | ||||
289 | swath_height_c = rq_param->misc.rq_c.blk256_width; | ||||
290 | } | ||||
291 | |||||
292 | if (swath_height_l > 0) | ||||
293 | log2_swath_height_l = dml_log2(swath_height_l); | ||||
294 | |||||
295 | if (req128_l && log2_swath_height_l > 0) | ||||
296 | log2_swath_height_l -= 1; | ||||
297 | |||||
298 | if (swath_height_c > 0) | ||||
299 | log2_swath_height_c = dml_log2(swath_height_c); | ||||
300 | |||||
301 | if (req128_c && log2_swath_height_c > 0) | ||||
302 | log2_swath_height_c -= 1; | ||||
303 | } | ||||
304 | |||||
305 | rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; | ||||
306 | rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; | ||||
307 | |||||
308 | dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l){do { } while(0); }; | ||||
309 | dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c){do { } while(0); }; | ||||
310 | dml_print({do { } while(0); } | ||||
311 | "DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",{do { } while(0); } | ||||
312 | __func__,{do { } while(0); } | ||||
313 | full_swath_bytes_packed_l){do { } while(0); }; | ||||
314 | dml_print({do { } while(0); } | ||||
315 | "DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",{do { } while(0); } | ||||
316 | __func__,{do { } while(0); } | ||||
317 | full_swath_bytes_packed_c){do { } while(0); }; | ||||
318 | } | ||||
319 | |||||
320 | static void get_meta_and_pte_attr( | ||||
321 | struct display_mode_lib *mode_lib, | ||||
322 | display_data_rq_dlg_params_st *rq_dlg_param, | ||||
323 | display_data_rq_misc_params_st *rq_misc_param, | ||||
324 | display_data_rq_sizing_params_st *rq_sizing_param, | ||||
325 | unsigned int vp_width, | ||||
326 | unsigned int vp_height, | ||||
327 | unsigned int data_pitch, | ||||
328 | unsigned int meta_pitch, | ||||
329 | unsigned int source_format, | ||||
330 | unsigned int tiling, | ||||
331 | unsigned int macro_tile_size, | ||||
332 | unsigned int source_scan, | ||||
333 | unsigned int hostvm_enable, | ||||
334 | unsigned int is_chroma) | ||||
335 | { | ||||
336 | bool_Bool surf_linear = (tiling == dm_sw_linear); | ||||
337 | bool_Bool surf_vert = (source_scan == dm_vert); | ||||
338 | |||||
339 | unsigned int bytes_per_element; | ||||
340 | unsigned int bytes_per_element_y = get_bytes_per_element( | ||||
341 | (enum source_format_class) (source_format), | ||||
342 | false0); | ||||
343 | unsigned int bytes_per_element_c = get_bytes_per_element( | ||||
344 | (enum source_format_class) (source_format), | ||||
345 | true1); | ||||
346 | |||||
347 | unsigned int blk256_width = 0; | ||||
348 | unsigned int blk256_height = 0; | ||||
349 | |||||
350 | unsigned int blk256_width_y = 0; | ||||
351 | unsigned int blk256_height_y = 0; | ||||
352 | unsigned int blk256_width_c = 0; | ||||
353 | unsigned int blk256_height_c = 0; | ||||
354 | unsigned int log2_bytes_per_element; | ||||
355 | unsigned int log2_blk256_width; | ||||
356 | unsigned int log2_blk256_height; | ||||
357 | unsigned int blk_bytes; | ||||
358 | unsigned int log2_blk_bytes; | ||||
359 | unsigned int log2_blk_height; | ||||
360 | unsigned int log2_blk_width; | ||||
361 | unsigned int log2_meta_req_bytes; | ||||
362 | unsigned int log2_meta_req_height; | ||||
363 | unsigned int log2_meta_req_width; | ||||
364 | unsigned int meta_req_width; | ||||
365 | unsigned int meta_req_height; | ||||
366 | unsigned int log2_meta_row_height; | ||||
367 | unsigned int meta_row_width_ub; | ||||
368 | unsigned int log2_meta_chunk_bytes; | ||||
369 | unsigned int log2_meta_chunk_height; | ||||
370 | |||||
371 | //full sized meta chunk width in unit of data elements | ||||
372 | unsigned int log2_meta_chunk_width; | ||||
373 | unsigned int log2_min_meta_chunk_bytes; | ||||
374 | unsigned int min_meta_chunk_width; | ||||
375 | unsigned int meta_chunk_width; | ||||
376 | unsigned int meta_chunk_per_row_int; | ||||
377 | unsigned int meta_row_remainder; | ||||
378 | unsigned int meta_chunk_threshold; | ||||
379 | unsigned int meta_blk_bytes; | ||||
380 | unsigned int meta_blk_height; | ||||
381 | unsigned int meta_blk_width; | ||||
382 | unsigned int meta_surface_bytes; | ||||
383 | unsigned int vmpg_bytes; | ||||
384 | unsigned int meta_pte_req_per_frame_ub; | ||||
385 | unsigned int meta_pte_bytes_per_frame_ub; | ||||
386 | const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); | ||||
387 | const unsigned int dpte_buf_in_pte_reqs = | ||||
388 | mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma + mode_lib->ip.dpte_buffer_size_in_pte_reqs_chroma; | ||||
389 | const unsigned int pde_proc_buffer_size_64k_reqs = | ||||
390 | mode_lib->ip.pde_proc_buffer_size_64k_reqs; | ||||
391 | |||||
392 | unsigned int log2_vmpg_height = 0; | ||||
393 | unsigned int log2_vmpg_width = 0; | ||||
394 | unsigned int log2_dpte_req_height_ptes = 0; | ||||
395 | unsigned int log2_dpte_req_height = 0; | ||||
396 | unsigned int log2_dpte_req_width = 0; | ||||
397 | unsigned int log2_dpte_row_height_linear = 0; | ||||
398 | unsigned int log2_dpte_row_height = 0; | ||||
399 | unsigned int log2_dpte_group_width = 0; | ||||
400 | unsigned int dpte_row_width_ub = 0; | ||||
401 | unsigned int dpte_req_height = 0; | ||||
402 | unsigned int dpte_req_width = 0; | ||||
403 | unsigned int dpte_group_width = 0; | ||||
404 | unsigned int log2_dpte_group_bytes = 0; | ||||
405 | unsigned int log2_dpte_group_length = 0; | ||||
406 | unsigned int pde_buf_entries; | ||||
407 | bool_Bool yuv420 = (source_format
| ||||
408 | |||||
409 | Calculate256BBlockSizes( | ||||
410 | (enum source_format_class) (source_format), | ||||
411 | (enum dm_swizzle_mode) (tiling), | ||||
412 | bytes_per_element_y, | ||||
413 | bytes_per_element_c, | ||||
414 | &blk256_height_y, | ||||
415 | &blk256_height_c, | ||||
416 | &blk256_width_y, | ||||
417 | &blk256_width_c); | ||||
418 | |||||
419 | if (!is_chroma
| ||||
420 | blk256_width = blk256_width_y; | ||||
421 | blk256_height = blk256_height_y; | ||||
422 | bytes_per_element = bytes_per_element_y; | ||||
423 | } else { | ||||
424 | blk256_width = blk256_width_c; | ||||
425 | blk256_height = blk256_height_c; | ||||
426 | bytes_per_element = bytes_per_element_c; | ||||
427 | } | ||||
428 | |||||
429 | log2_bytes_per_element = dml_log2(bytes_per_element); | ||||
430 | |||||
431 | dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear){do { } while(0); }; | ||||
432 | dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert){do { } while(0); }; | ||||
433 | dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width){do { } while(0); }; | ||||
434 | dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height){do { } while(0); }; | ||||
435 | |||||
436 | log2_blk256_width = dml_log2((double) blk256_width); | ||||
437 | log2_blk256_height = dml_log2((double) blk256_height); | ||||
438 | blk_bytes = surf_linear
| ||||
439 | 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); | ||||
440 | log2_blk_bytes = dml_log2((double) blk_bytes); | ||||
441 | log2_blk_height = 0; | ||||
442 | log2_blk_width = 0; | ||||
443 | |||||
444 | // remember log rule | ||||
445 | // "+" in log is multiply | ||||
446 | // "-" in log is divide | ||||
447 | // "/2" is like square root | ||||
448 | // blk is vertical biased | ||||
449 | if (tiling
| ||||
450 | log2_blk_height = log2_blk256_height | ||||
451 | + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); | ||||
452 | else | ||||
453 | log2_blk_height = 0; // blk height of 1 | ||||
454 | |||||
455 | log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; | ||||
456 | |||||
457 | if (!surf_vert
| ||||
458 | rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) | ||||
459 | + blk256_width; | ||||
460 | rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; | ||||
461 | } else { | ||||
462 | rq_dlg_param->swath_width_ub = dml_round_to_multiple( | ||||
463 | vp_height - 1, | ||||
464 | blk256_height, | ||||
465 | 1) + blk256_height; | ||||
466 | rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; | ||||
467 | } | ||||
468 | |||||
469 | if (!surf_vert
| ||||
470 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height | ||||
471 | * bytes_per_element; | ||||
472 | else | ||||
473 | rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width | ||||
474 | * bytes_per_element; | ||||
475 | |||||
476 | rq_misc_param->blk256_height = blk256_height; | ||||
477 | rq_misc_param->blk256_width = blk256_width; | ||||
478 | |||||
479 | // ------- | ||||
480 | // meta | ||||
481 | // ------- | ||||
482 | log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element | ||||
483 | |||||
484 | // each 64b meta request for dcn is 8x8 meta elements and | ||||
485 | // a meta element covers one 256b block of the the data surface. | ||||
486 | log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 | ||||
487 | log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element | ||||
488 | - log2_meta_req_height; | ||||
489 | meta_req_width = 1 << log2_meta_req_width; | ||||
490 | meta_req_height = 1 << log2_meta_req_height; | ||||
491 | log2_meta_row_height = 0; | ||||
492 | meta_row_width_ub = 0; | ||||
493 | |||||
494 | // the dimensions of a meta row are meta_row_width x meta_row_height in elements. | ||||
495 | // calculate upper bound of the meta_row_width | ||||
496 | if (!surf_vert
| ||||
497 | log2_meta_row_height = log2_meta_req_height; | ||||
498 | meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) | ||||
499 | + meta_req_width; | ||||
500 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; | ||||
501 | } else { | ||||
502 | log2_meta_row_height = log2_meta_req_width; | ||||
503 | meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) | ||||
504 | + meta_req_height; | ||||
505 | rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; | ||||
506 | } | ||||
507 | rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; | ||||
508 | |||||
509 | rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; | ||||
510 | |||||
511 | log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); | ||||
512 | log2_meta_chunk_height = log2_meta_row_height; | ||||
513 | |||||
514 | //full sized meta chunk width in unit of data elements | ||||
515 | log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element | ||||
516 | - log2_meta_chunk_height; | ||||
517 | log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); | ||||
518 | min_meta_chunk_width = 1 | ||||
519 | << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element | ||||
520 | - log2_meta_chunk_height); | ||||
521 | meta_chunk_width = 1 << log2_meta_chunk_width; | ||||
522 | meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); | ||||
523 | meta_row_remainder = meta_row_width_ub % meta_chunk_width; | ||||
524 | meta_chunk_threshold = 0; | ||||
525 | meta_blk_bytes = 4096; | ||||
526 | meta_blk_height = blk256_height * 64; | ||||
527 | meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; | ||||
| |||||
528 | meta_surface_bytes = meta_pitch | ||||
529 | * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) | ||||
530 | + meta_blk_height) * bytes_per_element / 256; | ||||
531 | vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; | ||||
532 | meta_pte_req_per_frame_ub = (dml_round_to_multiple( | ||||
533 | meta_surface_bytes - vmpg_bytes, | ||||
534 | 8 * vmpg_bytes, | ||||
535 | 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); | ||||
536 | meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request | ||||
537 | rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; | ||||
538 | |||||
539 | dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height){do { } while(0); }; | ||||
540 | dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width){do { } while(0); }; | ||||
541 | dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes){do { } while(0); }; | ||||
542 | dml_print({do { } while(0); } | ||||
543 | "DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n",{do { } while(0); } | ||||
544 | __func__,{do { } while(0); } | ||||
545 | meta_pte_req_per_frame_ub){do { } while(0); }; | ||||
546 | dml_print({do { } while(0); } | ||||
547 | "DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",{do { } while(0); } | ||||
548 | __func__,{do { } while(0); } | ||||
549 | meta_pte_bytes_per_frame_ub){do { } while(0); }; | ||||
550 | |||||
551 | if (!surf_vert) | ||||
552 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; | ||||
553 | else | ||||
554 | meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; | ||||
555 | |||||
556 | if (meta_row_remainder <= meta_chunk_threshold) | ||||
557 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; | ||||
558 | else | ||||
559 | rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; | ||||
560 | |||||
561 | // ------ | ||||
562 | // dpte | ||||
563 | // ------ | ||||
564 | if (surf_linear) { | ||||
565 | log2_vmpg_height = 0; // one line high | ||||
566 | } else { | ||||
567 | log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; | ||||
568 | } | ||||
569 | log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; | ||||
570 | |||||
571 | // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. | ||||
572 | if (surf_linear) { //one 64B PTE request returns 8 PTEs | ||||
573 | log2_dpte_req_height_ptes = 0; | ||||
574 | log2_dpte_req_width = log2_vmpg_width + 3; | ||||
575 | log2_dpte_req_height = 0; | ||||
576 | } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size | ||||
577 | //one 64B req gives 8x1 PTEs for 4KB tile | ||||
578 | log2_dpte_req_height_ptes = 0; | ||||
579 | log2_dpte_req_width = log2_blk_width + 3; | ||||
580 | log2_dpte_req_height = log2_blk_height + 0; | ||||
581 | } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB | ||||
582 | //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB | ||||
583 | log2_dpte_req_height_ptes = 4; | ||||
584 | log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width | ||||
585 | log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height | ||||
586 | } else { //64KB page size and must 64KB tile block | ||||
587 | //one 64B req gives 8x1 PTEs for 64KB tile | ||||
588 | log2_dpte_req_height_ptes = 0; | ||||
589 | log2_dpte_req_width = log2_blk_width + 3; | ||||
590 | log2_dpte_req_height = log2_blk_height + 0; | ||||
591 | } | ||||
592 | |||||
593 | // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height | ||||
594 | // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent | ||||
595 | // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) | ||||
596 | //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; | ||||
597 | //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; | ||||
598 | dpte_req_height = 1 << log2_dpte_req_height; | ||||
599 | dpte_req_width = 1 << log2_dpte_req_width; | ||||
600 | |||||
601 | // calculate pitch dpte row buffer can hold | ||||
602 | // round the result down to a power of two. | ||||
603 | pde_buf_entries = | ||||
604 | yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; | ||||
605 | if (surf_linear) { | ||||
606 | unsigned int dpte_row_height; | ||||
607 | |||||
608 | log2_dpte_row_height_linear = dml_floor( | ||||
609 | dml_log2( | ||||
610 | dml_min( | ||||
611 | 64 * 1024 * pde_buf_entries | ||||
612 | / bytes_per_element, | ||||
613 | dpte_buf_in_pte_reqs | ||||
614 | * dpte_req_width) | ||||
615 | / data_pitch), | ||||
616 | 1); | ||||
617 | |||||
618 | ASSERT(log2_dpte_row_height_linear >= 3)do { if (({ static int __warned; int __ret = !!(!(log2_dpte_row_height_linear >= 3)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(log2_dpte_row_height_linear >= 3)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 618); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
619 | |||||
620 | if (log2_dpte_row_height_linear > 7) | ||||
621 | log2_dpte_row_height_linear = 7; | ||||
622 | |||||
623 | log2_dpte_row_height = log2_dpte_row_height_linear; | ||||
624 | // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. | ||||
625 | // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. | ||||
626 | dpte_row_height = 1 << log2_dpte_row_height; | ||||
627 | dpte_row_width_ub = dml_round_to_multiple( | ||||
628 | data_pitch * dpte_row_height - 1, | ||||
629 | dpte_req_width, | ||||
630 | 1) + dpte_req_width; | ||||
631 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; | ||||
632 | } else { | ||||
633 | // the upper bound of the dpte_row_width without dependency on viewport position follows. | ||||
634 | // for tiled mode, row height is the same as req height and row store up to vp size upper bound | ||||
635 | if (!surf_vert) { | ||||
636 | log2_dpte_row_height = log2_dpte_req_height; | ||||
637 | dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) | ||||
638 | + dpte_req_width; | ||||
639 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; | ||||
640 | } else { | ||||
641 | log2_dpte_row_height = | ||||
642 | (log2_blk_width < log2_dpte_req_width) ? | ||||
643 | log2_blk_width : log2_dpte_req_width; | ||||
644 | dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) | ||||
645 | + dpte_req_height; | ||||
646 | rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; | ||||
647 | } | ||||
648 | } | ||||
649 | if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB | ||||
650 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request | ||||
651 | else | ||||
652 | rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request | ||||
653 | |||||
654 | rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; | ||||
655 | |||||
656 | // the dpte_group_bytes is reduced for the specific case of vertical | ||||
657 | // access of a tile surface that has dpte request of 8x1 ptes. | ||||
658 | |||||
659 | if (hostvm_enable) | ||||
660 | rq_sizing_param->dpte_group_bytes = 512; | ||||
661 | else { | ||||
662 | if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group | ||||
663 | rq_sizing_param->dpte_group_bytes = 512; | ||||
664 | else | ||||
665 | //full size | ||||
666 | rq_sizing_param->dpte_group_bytes = 2048; | ||||
667 | } | ||||
668 | |||||
669 | //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. | ||||
670 | log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); | ||||
671 | log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests | ||||
672 | |||||
673 | // full sized data pte group width in elements | ||||
674 | if (!surf_vert) | ||||
675 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; | ||||
676 | else | ||||
677 | log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; | ||||
678 | |||||
679 | //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B | ||||
680 | if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB | ||||
681 | log2_dpte_group_width = log2_dpte_group_width - 1; | ||||
682 | |||||
683 | dpte_group_width = 1 << log2_dpte_group_width; | ||||
684 | |||||
685 | // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, | ||||
686 | // the upper bound for the dpte groups per row is as follows. | ||||
687 | rq_dlg_param->dpte_groups_per_row_ub = dml_ceil( | ||||
688 | (double) dpte_row_width_ub / dpte_group_width, | ||||
689 | 1); | ||||
690 | } | ||||
691 | |||||
692 | static void get_surf_rq_param( | ||||
693 | struct display_mode_lib *mode_lib, | ||||
694 | display_data_rq_sizing_params_st *rq_sizing_param, | ||||
695 | display_data_rq_dlg_params_st *rq_dlg_param, | ||||
696 | display_data_rq_misc_params_st *rq_misc_param, | ||||
697 | const display_pipe_params_st pipe_param, | ||||
698 | bool_Bool is_chroma) | ||||
699 | { | ||||
700 | bool_Bool mode_422 = false0; | ||||
701 | unsigned int vp_width = 0; | ||||
702 | unsigned int vp_height = 0; | ||||
703 | unsigned int data_pitch = 0; | ||||
704 | unsigned int meta_pitch = 0; | ||||
705 | unsigned int ppe = mode_422
| ||||
706 | |||||
707 | // FIXME check if ppe apply for both luma and chroma in 422 case | ||||
708 | if (is_chroma
| ||||
709 | vp_width = pipe_param.src.viewport_width_c / ppe; | ||||
710 | vp_height = pipe_param.src.viewport_height_c; | ||||
711 | data_pitch = pipe_param.src.data_pitch_c; | ||||
712 | meta_pitch = pipe_param.src.meta_pitch_c; | ||||
713 | } else { | ||||
714 | vp_width = pipe_param.src.viewport_width / ppe; | ||||
715 | vp_height = pipe_param.src.viewport_height; | ||||
716 | data_pitch = pipe_param.src.data_pitch; | ||||
717 | meta_pitch = pipe_param.src.meta_pitch; | ||||
718 | } | ||||
719 | |||||
720 | if (pipe_param.dest.odm_combine) { | ||||
721 | unsigned int access_dir; | ||||
722 | unsigned int full_src_vp_width; | ||||
723 | unsigned int hactive_half; | ||||
724 | unsigned int src_hactive_half; | ||||
725 | access_dir = (pipe_param.src.source_scan == dm_vert); // vp access direction: horizontal or vertical accessed | ||||
726 | hactive_half = pipe_param.dest.hactive / 2; | ||||
727 | if (is_chroma) { | ||||
728 | full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio_c * pipe_param.dest.full_recout_width; | ||||
729 | src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio_c * hactive_half; | ||||
730 | } else { | ||||
731 | full_src_vp_width = pipe_param.scale_ratio_depth.hscl_ratio * pipe_param.dest.full_recout_width; | ||||
732 | src_hactive_half = pipe_param.scale_ratio_depth.hscl_ratio * hactive_half; | ||||
733 | } | ||||
734 | |||||
735 | if (access_dir == 0) { | ||||
736 | vp_width = dml_min(full_src_vp_width, src_hactive_half); | ||||
737 | dml_print("DML_DLG: %s: vp_width = %d\n", __func__, vp_width){do { } while(0); }; | ||||
738 | } else { | ||||
739 | vp_height = dml_min(full_src_vp_width, src_hactive_half); | ||||
740 | dml_print("DML_DLG: %s: vp_height = %d\n", __func__, vp_height){do { } while(0); }; | ||||
741 | |||||
742 | } | ||||
743 | dml_print("DML_DLG: %s: full_src_vp_width = %d\n", __func__, full_src_vp_width){do { } while(0); }; | ||||
744 | dml_print("DML_DLG: %s: hactive_half = %d\n", __func__, hactive_half){do { } while(0); }; | ||||
745 | dml_print("DML_DLG: %s: src_hactive_half = %d\n", __func__, src_hactive_half){do { } while(0); }; | ||||
746 | } | ||||
747 | rq_sizing_param->chunk_bytes = 8192; | ||||
748 | |||||
749 | if (rq_sizing_param->chunk_bytes == 64 * 1024) | ||||
750 | rq_sizing_param->min_chunk_bytes = 0; | ||||
751 | else | ||||
752 | rq_sizing_param->min_chunk_bytes = 1024; | ||||
753 | |||||
754 | rq_sizing_param->meta_chunk_bytes = 2048; | ||||
755 | rq_sizing_param->min_meta_chunk_bytes = 256; | ||||
756 | |||||
757 | if (pipe_param.src.hostvm) | ||||
758 | rq_sizing_param->mpte_group_bytes = 512; | ||||
759 | else | ||||
760 | rq_sizing_param->mpte_group_bytes = 2048; | ||||
761 | |||||
762 | get_meta_and_pte_attr( | ||||
763 | mode_lib, | ||||
764 | rq_dlg_param, | ||||
765 | rq_misc_param, | ||||
766 | rq_sizing_param, | ||||
767 | vp_width, | ||||
768 | vp_height, | ||||
769 | data_pitch, | ||||
770 | meta_pitch, | ||||
771 | pipe_param.src.source_format, | ||||
772 | pipe_param.src.sw_mode, | ||||
773 | pipe_param.src.macro_tile_size, | ||||
774 | pipe_param.src.source_scan, | ||||
775 | pipe_param.src.hostvm, | ||||
776 | is_chroma); | ||||
777 | } | ||||
778 | |||||
779 | static void dml_rq_dlg_get_rq_params( | ||||
780 | struct display_mode_lib *mode_lib, | ||||
781 | display_rq_params_st *rq_param, | ||||
782 | const display_pipe_params_st pipe_param) | ||||
783 | { | ||||
784 | // get param for luma surface | ||||
785 | rq_param->yuv420 = pipe_param.src.source_format == dm_420_8 | ||||
786 | || pipe_param.src.source_format == dm_420_10; | ||||
787 | rq_param->yuv420_10bpc = pipe_param.src.source_format
| ||||
788 | |||||
789 | get_surf_rq_param( | ||||
790 | mode_lib, | ||||
791 | &(rq_param->sizing.rq_l), | ||||
792 | &(rq_param->dlg.rq_l), | ||||
793 | &(rq_param->misc.rq_l), | ||||
794 | pipe_param, | ||||
795 | 0); | ||||
796 | |||||
797 | if (is_dual_plane((enum source_format_class) (pipe_param.src.source_format))) { | ||||
798 | // get param for chroma surface | ||||
799 | get_surf_rq_param( | ||||
800 | mode_lib, | ||||
801 | &(rq_param->sizing.rq_c), | ||||
802 | &(rq_param->dlg.rq_c), | ||||
803 | &(rq_param->misc.rq_c), | ||||
804 | pipe_param, | ||||
805 | 1); | ||||
806 | } | ||||
807 | |||||
808 | // calculate how to split the det buffer space between luma and chroma | ||||
809 | handle_det_buf_split(mode_lib, rq_param, pipe_param.src); | ||||
810 | print__rq_params_st(mode_lib, *rq_param); | ||||
811 | } | ||||
812 | |||||
813 | void dml21_rq_dlg_get_rq_reg( | ||||
814 | struct display_mode_lib *mode_lib, | ||||
815 | display_rq_regs_st *rq_regs, | ||||
816 | const display_pipe_params_st pipe_param) | ||||
817 | { | ||||
818 | display_rq_params_st rq_param = {0}; | ||||
819 | |||||
820 | memset(rq_regs, 0, sizeof(*rq_regs))__builtin_memset((rq_regs), (0), (sizeof(*rq_regs))); | ||||
821 | dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param); | ||||
822 | extract_rq_regs(mode_lib, rq_regs, rq_param); | ||||
823 | |||||
824 | print__rq_regs_st(mode_lib, *rq_regs); | ||||
825 | } | ||||
826 | |||||
827 | // Note: currently taken in as is. | ||||
828 | // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. | ||||
829 | static void dml_rq_dlg_get_dlg_params( | ||||
830 | struct display_mode_lib *mode_lib, | ||||
831 | const display_e2e_pipe_params_st *e2e_pipe_param, | ||||
832 | const unsigned int num_pipes, | ||||
833 | const unsigned int pipe_idx, | ||||
834 | display_dlg_regs_st *disp_dlg_regs, | ||||
835 | display_ttu_regs_st *disp_ttu_regs, | ||||
836 | const display_rq_dlg_params_st rq_dlg_param, | ||||
837 | const display_dlg_sys_params_st dlg_sys_param, | ||||
838 | const bool_Bool cstate_en, | ||||
839 | const bool_Bool pstate_en) | ||||
840 | { | ||||
841 | const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; | ||||
842 | const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; | ||||
843 | const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; | ||||
844 | const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; | ||||
845 | const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; | ||||
846 | const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; | ||||
847 | |||||
848 | // ------------------------- | ||||
849 | // Section 1.15.2.1: OTG dependent Params | ||||
850 | // ------------------------- | ||||
851 | // Timing | ||||
852 | unsigned int htotal = dst->htotal; | ||||
853 | // unsigned int hblank_start = dst.hblank_start; // TODO: Remove | ||||
854 | unsigned int hblank_end = dst->hblank_end; | ||||
855 | unsigned int vblank_start = dst->vblank_start; | ||||
856 | unsigned int vblank_end = dst->vblank_end; | ||||
857 | unsigned int min_vblank = mode_lib->ip.min_vblank_lines; | ||||
858 | |||||
859 | double dppclk_freq_in_mhz = clks->dppclk_mhz; | ||||
860 | double dispclk_freq_in_mhz = clks->dispclk_mhz; | ||||
861 | double refclk_freq_in_mhz = clks->refclk_mhz; | ||||
862 | double pclk_freq_in_mhz = dst->pixel_rate_mhz; | ||||
863 | bool_Bool interlaced = dst->interlaced; | ||||
864 | |||||
865 | double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; | ||||
866 | |||||
867 | double min_dcfclk_mhz; | ||||
868 | double t_calc_us; | ||||
869 | double min_ttu_vblank; | ||||
870 | |||||
871 | double min_dst_y_ttu_vblank; | ||||
872 | unsigned int dlg_vblank_start; | ||||
873 | bool_Bool dual_plane; | ||||
874 | bool_Bool mode_422; | ||||
875 | unsigned int access_dir; | ||||
876 | unsigned int vp_height_l; | ||||
877 | unsigned int vp_width_l; | ||||
878 | unsigned int vp_height_c; | ||||
879 | unsigned int vp_width_c; | ||||
880 | |||||
881 | // Scaling | ||||
882 | unsigned int htaps_l; | ||||
883 | unsigned int htaps_c; | ||||
884 | double hratio_l; | ||||
885 | double hratio_c; | ||||
886 | double vratio_l; | ||||
887 | double vratio_c; | ||||
888 | bool_Bool scl_enable; | ||||
889 | |||||
890 | double line_time_in_us; | ||||
891 | // double vinit_l; | ||||
892 | // double vinit_c; | ||||
893 | // double vinit_bot_l; | ||||
894 | // double vinit_bot_c; | ||||
895 | |||||
896 | // unsigned int swath_height_l; | ||||
897 | unsigned int swath_width_ub_l; | ||||
898 | // unsigned int dpte_bytes_per_row_ub_l; | ||||
899 | unsigned int dpte_groups_per_row_ub_l; | ||||
900 | // unsigned int meta_pte_bytes_per_frame_ub_l; | ||||
901 | // unsigned int meta_bytes_per_row_ub_l; | ||||
902 | |||||
903 | // unsigned int swath_height_c; | ||||
904 | unsigned int swath_width_ub_c; | ||||
905 | // unsigned int dpte_bytes_per_row_ub_c; | ||||
906 | unsigned int dpte_groups_per_row_ub_c; | ||||
907 | |||||
908 | unsigned int meta_chunks_per_row_ub_l; | ||||
909 | unsigned int meta_chunks_per_row_ub_c; | ||||
910 | unsigned int vupdate_offset; | ||||
911 | unsigned int vupdate_width; | ||||
912 | unsigned int vready_offset; | ||||
913 | |||||
914 | unsigned int dppclk_delay_subtotal; | ||||
915 | unsigned int dispclk_delay_subtotal; | ||||
916 | unsigned int pixel_rate_delay_subtotal; | ||||
917 | |||||
918 | unsigned int vstartup_start; | ||||
919 | unsigned int dst_x_after_scaler; | ||||
920 | unsigned int dst_y_after_scaler; | ||||
921 | double line_wait; | ||||
922 | double dst_y_prefetch; | ||||
923 | double dst_y_per_vm_vblank; | ||||
924 | double dst_y_per_row_vblank; | ||||
925 | double dst_y_per_vm_flip; | ||||
926 | double dst_y_per_row_flip; | ||||
927 | double max_dst_y_per_vm_vblank; | ||||
928 | double max_dst_y_per_row_vblank; | ||||
929 | double lsw; | ||||
930 | double vratio_pre_l; | ||||
931 | double vratio_pre_c; | ||||
932 | unsigned int req_per_swath_ub_l; | ||||
933 | unsigned int req_per_swath_ub_c; | ||||
934 | unsigned int meta_row_height_l; | ||||
935 | unsigned int meta_row_height_c; | ||||
936 | unsigned int swath_width_pixels_ub_l; | ||||
937 | unsigned int swath_width_pixels_ub_c; | ||||
938 | unsigned int scaler_rec_in_width_l; | ||||
939 | unsigned int scaler_rec_in_width_c; | ||||
940 | unsigned int dpte_row_height_l; | ||||
941 | unsigned int dpte_row_height_c; | ||||
942 | double hscale_pixel_rate_l; | ||||
943 | double hscale_pixel_rate_c; | ||||
944 | double min_hratio_fact_l; | ||||
945 | double min_hratio_fact_c; | ||||
946 | double refcyc_per_line_delivery_pre_l; | ||||
947 | double refcyc_per_line_delivery_pre_c; | ||||
948 | double refcyc_per_line_delivery_l; | ||||
949 | double refcyc_per_line_delivery_c; | ||||
950 | |||||
951 | double refcyc_per_req_delivery_pre_l; | ||||
952 | double refcyc_per_req_delivery_pre_c; | ||||
953 | double refcyc_per_req_delivery_l; | ||||
954 | double refcyc_per_req_delivery_c; | ||||
955 | |||||
956 | unsigned int full_recout_width; | ||||
957 | double refcyc_per_req_delivery_pre_cur0; | ||||
958 | double refcyc_per_req_delivery_cur0; | ||||
959 | double refcyc_per_req_delivery_pre_cur1; | ||||
960 | double refcyc_per_req_delivery_cur1; | ||||
961 | |||||
962 | memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs))__builtin_memset((disp_dlg_regs), (0), (sizeof(*disp_dlg_regs ))); | ||||
963 | memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs))__builtin_memset((disp_ttu_regs), (0), (sizeof(*disp_ttu_regs ))); | ||||
964 | |||||
965 | dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en){do { } while(0); }; | ||||
966 | dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en){do { } while(0); }; | ||||
967 | |||||
968 | dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz){do { } while(0); }; | ||||
969 | dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz){do { } while(0); }; | ||||
970 | dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz){do { } while(0); }; | ||||
971 | dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz){do { } while(0); }; | ||||
972 | dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced){do { } while(0); }; | ||||
973 | ASSERT(ref_freq_to_pix_freq < 4.0)do { if (({ static int __warned; int __ret = !!(!(ref_freq_to_pix_freq < 4.0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(ref_freq_to_pix_freq < 4.0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 973); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
974 | |||||
975 | disp_dlg_regs->ref_freq_to_pix_freq = | ||||
976 | (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); | ||||
977 | disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal | ||||
978 | * dml_pow(2, 8)); | ||||
979 | disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits | ||||
980 | disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end | ||||
981 | * (double) ref_freq_to_pix_freq); | ||||
982 | ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_h_blank_end < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 982); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
983 | |||||
984 | min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; | ||||
985 | t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); | ||||
986 | min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
987 | |||||
988 | min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; | ||||
989 | dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; | ||||
990 | |||||
991 | disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start) * dml_pow(2, 2)); | ||||
992 | ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))) ; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->min_dst_y_next_start < (unsigned int)dml_pow(2, 18))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 992); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
993 | |||||
994 | dml_print({do { } while(0); } | ||||
995 | "DML_DLG: %s: min_dcfclk_mhz = %3.2f\n",{do { } while(0); } | ||||
996 | __func__,{do { } while(0); } | ||||
997 | min_dcfclk_mhz){do { } while(0); }; | ||||
998 | dml_print({do { } while(0); } | ||||
999 | "DML_DLG: %s: min_ttu_vblank = %3.2f\n",{do { } while(0); } | ||||
1000 | __func__,{do { } while(0); } | ||||
1001 | min_ttu_vblank){do { } while(0); }; | ||||
1002 | dml_print({do { } while(0); } | ||||
1003 | "DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n",{do { } while(0); } | ||||
1004 | __func__,{do { } while(0); } | ||||
1005 | min_dst_y_ttu_vblank){do { } while(0); }; | ||||
1006 | dml_print({do { } while(0); } | ||||
1007 | "DML_DLG: %s: t_calc_us = %3.2f\n",{do { } while(0); } | ||||
1008 | __func__,{do { } while(0); } | ||||
1009 | t_calc_us){do { } while(0); }; | ||||
1010 | dml_print({do { } while(0); } | ||||
1011 | "DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n",{do { } while(0); } | ||||
1012 | __func__,{do { } while(0); } | ||||
1013 | disp_dlg_regs->min_dst_y_next_start){do { } while(0); }; | ||||
1014 | dml_print({do { } while(0); } | ||||
1015 | "DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n",{do { } while(0); } | ||||
1016 | __func__,{do { } while(0); } | ||||
1017 | ref_freq_to_pix_freq){do { } while(0); }; | ||||
1018 | |||||
1019 | // ------------------------- | ||||
1020 | // Section 1.15.2.2: Prefetch, Active and TTU | ||||
1021 | // ------------------------- | ||||
1022 | // Prefetch Calc | ||||
1023 | // Source | ||||
1024 | // dcc_en = src.dcc; | ||||
1025 | dual_plane = is_dual_plane((enum source_format_class) (src->source_format)); | ||||
1026 | mode_422 = false0; // FIXME | ||||
1027 | access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed | ||||
1028 | // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); | ||||
1029 | // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); | ||||
1030 | vp_height_l = src->viewport_height; | ||||
1031 | vp_width_l = src->viewport_width; | ||||
1032 | vp_height_c = src->viewport_height_c; | ||||
1033 | vp_width_c = src->viewport_width_c; | ||||
1034 | |||||
1035 | // Scaling | ||||
1036 | htaps_l = taps->htaps; | ||||
1037 | htaps_c = taps->htaps_c; | ||||
1038 | hratio_l = scl->hscl_ratio; | ||||
1039 | hratio_c = scl->hscl_ratio_c; | ||||
1040 | vratio_l = scl->vscl_ratio; | ||||
1041 | vratio_c = scl->vscl_ratio_c; | ||||
1042 | scl_enable = scl->scl_enable; | ||||
1043 | |||||
1044 | line_time_in_us = (htotal / pclk_freq_in_mhz); | ||||
1045 | swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; | ||||
1046 | dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; | ||||
1047 | swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; | ||||
1048 | dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; | ||||
1049 | |||||
1050 | meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; | ||||
1051 | meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; | ||||
1052 | vupdate_offset = dst->vupdate_offset; | ||||
1053 | vupdate_width = dst->vupdate_width; | ||||
1054 | vready_offset = dst->vready_offset; | ||||
1055 | |||||
1056 | dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; | ||||
1057 | dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; | ||||
1058 | |||||
1059 | if (scl_enable) | ||||
1060 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; | ||||
1061 | else | ||||
1062 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; | ||||
1063 | |||||
1064 | dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter | ||||
1065 | + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; | ||||
1066 | |||||
1067 | if (dout->dsc_enable) { | ||||
1068 | double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1069 | |||||
1070 | dispclk_delay_subtotal += dsc_delay; | ||||
1071 | } | ||||
1072 | |||||
1073 | pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz | ||||
1074 | + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; | ||||
1075 | |||||
1076 | vstartup_start = dst->vstartup_start; | ||||
1077 | if (interlaced) { | ||||
1078 | if (vstartup_start / 2.0 | ||||
1079 | - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal | ||||
1080 | <= vblank_end / 2.0) | ||||
1081 | disp_dlg_regs->vready_after_vcount0 = 1; | ||||
1082 | else | ||||
1083 | disp_dlg_regs->vready_after_vcount0 = 0; | ||||
1084 | } else { | ||||
1085 | if (vstartup_start | ||||
1086 | - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal | ||||
1087 | <= vblank_end) | ||||
1088 | disp_dlg_regs->vready_after_vcount0 = 1; | ||||
1089 | else | ||||
1090 | disp_dlg_regs->vready_after_vcount0 = 0; | ||||
1091 | } | ||||
1092 | |||||
1093 | // TODO: Where is this coming from? | ||||
1094 | if (interlaced) | ||||
1095 | vstartup_start = vstartup_start / 2; | ||||
1096 | |||||
1097 | // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? | ||||
1098 | if (vstartup_start >= min_vblank) { | ||||
1099 | dml_print({do { } while(0); } | ||||
1100 | "WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",{do { } while(0); } | ||||
1101 | __func__,{do { } while(0); } | ||||
1102 | vblank_start,{do { } while(0); } | ||||
1103 | vblank_end){do { } while(0); }; | ||||
1104 | dml_print({do { } while(0); } | ||||
1105 | "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } | ||||
1106 | __func__,{do { } while(0); } | ||||
1107 | vstartup_start,{do { } while(0); } | ||||
1108 | min_vblank){do { } while(0); }; | ||||
1109 | min_vblank = vstartup_start + 1; | ||||
1110 | dml_print({do { } while(0); } | ||||
1111 | "WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",{do { } while(0); } | ||||
1112 | __func__,{do { } while(0); } | ||||
1113 | vstartup_start,{do { } while(0); } | ||||
1114 | min_vblank){do { } while(0); }; | ||||
1115 | } | ||||
1116 | |||||
1117 | dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1118 | dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1119 | |||||
1120 | dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal){do { } while(0); }; | ||||
1121 | dml_print({do { } while(0); } | ||||
1122 | "DML_DLG: %s: pixel_rate_delay_subtotal = %d\n",{do { } while(0); } | ||||
1123 | __func__,{do { } while(0); } | ||||
1124 | pixel_rate_delay_subtotal){do { } while(0); }; | ||||
1125 | dml_print({do { } while(0); } | ||||
1126 | "DML_DLG: %s: dst_x_after_scaler = %d\n",{do { } while(0); } | ||||
1127 | __func__,{do { } while(0); } | ||||
1128 | dst_x_after_scaler){do { } while(0); }; | ||||
1129 | dml_print({do { } while(0); } | ||||
1130 | "DML_DLG: %s: dst_y_after_scaler = %d\n",{do { } while(0); } | ||||
1131 | __func__,{do { } while(0); } | ||||
1132 | dst_y_after_scaler){do { } while(0); }; | ||||
1133 | |||||
1134 | // Lwait | ||||
1135 | // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? | ||||
1136 | line_wait = mode_lib->soc.urgent_latency_pixel_data_only_us; | ||||
1137 | if (cstate_en) | ||||
1138 | line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); | ||||
1139 | if (pstate_en) | ||||
1140 | line_wait = dml_max( | ||||
1141 | mode_lib->soc.dram_clock_change_latency_us | ||||
1142 | + mode_lib->soc.urgent_latency_pixel_data_only_us, // TODO: Should this be urgent_latency_pixel_mixed_with_vm_data_us? | ||||
1143 | line_wait); | ||||
1144 | line_wait = line_wait / line_time_in_us; | ||||
1145 | |||||
1146 | dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1147 | dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch){do { } while(0); }; | ||||
1148 | |||||
1149 | dst_y_per_vm_vblank = get_dst_y_per_vm_vblank( | ||||
1150 | mode_lib, | ||||
1151 | e2e_pipe_param, | ||||
1152 | num_pipes, | ||||
1153 | pipe_idx); | ||||
1154 | dst_y_per_row_vblank = get_dst_y_per_row_vblank( | ||||
1155 | mode_lib, | ||||
1156 | e2e_pipe_param, | ||||
1157 | num_pipes, | ||||
1158 | pipe_idx); | ||||
1159 | dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1160 | dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1161 | |||||
1162 | max_dst_y_per_vm_vblank = 32.0; | ||||
1163 | max_dst_y_per_row_vblank = 16.0; | ||||
1164 | |||||
1165 | // magic! | ||||
1166 | if (htotal <= 75) { | ||||
1167 | min_vblank = 300; | ||||
1168 | max_dst_y_per_vm_vblank = 100.0; | ||||
1169 | max_dst_y_per_row_vblank = 100.0; | ||||
1170 | } | ||||
1171 | |||||
1172 | dml_print("DML_DLG: %s: dst_y_per_vm_flip = %3.2f\n", __func__, dst_y_per_vm_flip){do { } while(0); }; | ||||
1173 | dml_print("DML_DLG: %s: dst_y_per_row_flip = %3.2f\n", __func__, dst_y_per_row_flip){do { } while(0); }; | ||||
1174 | dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank){do { } while(0); }; | ||||
1175 | dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank){do { } while(0); }; | ||||
1176 | |||||
1177 | ASSERT(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_vm_vblank < max_dst_y_per_vm_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1177); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1178 | ASSERT(dst_y_per_row_vblank < max_dst_y_per_row_vblank)do { if (({ static int __warned; int __ret = !!(!(dst_y_per_row_vblank < max_dst_y_per_row_vblank)); if (__ret && !__warned ) { printf("WARNING %s failed at %s:%d\n", "!(dst_y_per_row_vblank < max_dst_y_per_row_vblank)" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1178); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1179 | |||||
1180 | ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))do { if (({ static int __warned; int __ret = !!(!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1180); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1181 | lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); | ||||
1182 | |||||
1183 | dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw){do { } while(0); }; | ||||
1184 | |||||
1185 | vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1186 | vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); | ||||
1187 | |||||
1188 | dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l){do { } while(0); }; | ||||
1189 | dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c){do { } while(0); }; | ||||
1190 | |||||
1191 | // Active | ||||
1192 | req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; | ||||
1193 | req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; | ||||
1194 | meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; | ||||
1195 | meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; | ||||
1196 | swath_width_pixels_ub_l = 0; | ||||
1197 | swath_width_pixels_ub_c = 0; | ||||
1198 | scaler_rec_in_width_l = 0; | ||||
1199 | scaler_rec_in_width_c = 0; | ||||
1200 | dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; | ||||
1201 | dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; | ||||
1202 | |||||
1203 | if (mode_422) { | ||||
1204 | swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element | ||||
1205 | swath_width_pixels_ub_c = swath_width_ub_c * 2; | ||||
1206 | } else { | ||||
1207 | swath_width_pixels_ub_l = swath_width_ub_l * 1; | ||||
1208 | swath_width_pixels_ub_c = swath_width_ub_c * 1; | ||||
1209 | } | ||||
1210 | |||||
1211 | hscale_pixel_rate_l = 0.; | ||||
1212 | hscale_pixel_rate_c = 0.; | ||||
1213 | min_hratio_fact_l = 1.0; | ||||
1214 | min_hratio_fact_c = 1.0; | ||||
1215 | |||||
1216 | if (hratio_l <= 1) | ||||
1217 | min_hratio_fact_l = 2.0; | ||||
1218 | else if (htaps_l <= 6) { | ||||
1219 | if ((hratio_l * 2.0) > 4.0) | ||||
1220 | min_hratio_fact_l = 4.0; | ||||
1221 | else | ||||
1222 | min_hratio_fact_l = hratio_l * 2.0; | ||||
1223 | } else { | ||||
1224 | if (hratio_l > 4.0) | ||||
1225 | min_hratio_fact_l = 4.0; | ||||
1226 | else | ||||
1227 | min_hratio_fact_l = hratio_l; | ||||
1228 | } | ||||
1229 | |||||
1230 | hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; | ||||
1231 | |||||
1232 | if (hratio_c <= 1) | ||||
1233 | min_hratio_fact_c = 2.0; | ||||
1234 | else if (htaps_c <= 6) { | ||||
1235 | if ((hratio_c * 2.0) > 4.0) | ||||
1236 | min_hratio_fact_c = 4.0; | ||||
1237 | else | ||||
1238 | min_hratio_fact_c = hratio_c * 2.0; | ||||
1239 | } else { | ||||
1240 | if (hratio_c > 4.0) | ||||
1241 | min_hratio_fact_c = 4.0; | ||||
1242 | else | ||||
1243 | min_hratio_fact_c = hratio_c; | ||||
1244 | } | ||||
1245 | |||||
1246 | hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; | ||||
1247 | |||||
1248 | refcyc_per_line_delivery_pre_l = 0.; | ||||
1249 | refcyc_per_line_delivery_pre_c = 0.; | ||||
1250 | refcyc_per_line_delivery_l = 0.; | ||||
1251 | refcyc_per_line_delivery_c = 0.; | ||||
1252 | |||||
1253 | refcyc_per_req_delivery_pre_l = 0.; | ||||
1254 | refcyc_per_req_delivery_pre_c = 0.; | ||||
1255 | refcyc_per_req_delivery_l = 0.; | ||||
1256 | refcyc_per_req_delivery_c = 0.; | ||||
1257 | |||||
1258 | full_recout_width = 0; | ||||
1259 | // In ODM | ||||
1260 | if (src->is_hsplit) { | ||||
1261 | // This "hack" is only allowed (and valid) for MPC combine. In ODM | ||||
1262 | // combine, you MUST specify the full_recout_width...according to Oswin | ||||
1263 | if (dst->full_recout_width == 0 && !dst->odm_combine) { | ||||
1264 | dml_print({do { } while(0); } | ||||
1265 | "DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",{do { } while(0); } | ||||
1266 | __func__){do { } while(0); }; | ||||
1267 | full_recout_width = dst->recout_width * 2; // assume half split for dcn1 | ||||
1268 | } else | ||||
1269 | full_recout_width = dst->full_recout_width; | ||||
1270 | } else | ||||
1271 | full_recout_width = dst->recout_width; | ||||
1272 | |||||
1273 | // As of DCN2, mpc_combine and odm_combine are mutually exclusive | ||||
1274 | refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( | ||||
1275 | mode_lib, | ||||
1276 | refclk_freq_in_mhz, | ||||
1277 | pclk_freq_in_mhz, | ||||
1278 | dst->odm_combine, | ||||
1279 | full_recout_width, | ||||
1280 | dst->hactive, | ||||
1281 | vratio_pre_l, | ||||
1282 | hscale_pixel_rate_l, | ||||
1283 | swath_width_pixels_ub_l, | ||||
1284 | 1); // per line | ||||
1285 | |||||
1286 | refcyc_per_line_delivery_l = get_refcyc_per_delivery( | ||||
1287 | mode_lib, | ||||
1288 | refclk_freq_in_mhz, | ||||
1289 | pclk_freq_in_mhz, | ||||
1290 | dst->odm_combine, | ||||
1291 | full_recout_width, | ||||
1292 | dst->hactive, | ||||
1293 | vratio_l, | ||||
1294 | hscale_pixel_rate_l, | ||||
1295 | swath_width_pixels_ub_l, | ||||
1296 | 1); // per line | ||||
1297 | |||||
1298 | dml_print("DML_DLG: %s: full_recout_width = %d\n", __func__, full_recout_width){do { } while(0); }; | ||||
1299 | dml_print({do { } while(0); } | ||||
1300 | "DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n",{do { } while(0); } | ||||
1301 | __func__,{do { } while(0); } | ||||
1302 | hscale_pixel_rate_l){do { } while(0); }; | ||||
1303 | dml_print({do { } while(0); } | ||||
1304 | "DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",{do { } while(0); } | ||||
1305 | __func__,{do { } while(0); } | ||||
1306 | refcyc_per_line_delivery_pre_l){do { } while(0); }; | ||||
1307 | dml_print({do { } while(0); } | ||||
1308 | "DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n",{do { } while(0); } | ||||
1309 | __func__,{do { } while(0); } | ||||
1310 | refcyc_per_line_delivery_l){do { } while(0); }; | ||||
1311 | |||||
1312 | if (dual_plane) { | ||||
1313 | refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery( | ||||
1314 | mode_lib, | ||||
1315 | refclk_freq_in_mhz, | ||||
1316 | pclk_freq_in_mhz, | ||||
1317 | dst->odm_combine, | ||||
1318 | full_recout_width, | ||||
1319 | dst->hactive, | ||||
1320 | vratio_pre_c, | ||||
1321 | hscale_pixel_rate_c, | ||||
1322 | swath_width_pixels_ub_c, | ||||
1323 | 1); // per line | ||||
1324 | |||||
1325 | refcyc_per_line_delivery_c = get_refcyc_per_delivery( | ||||
1326 | mode_lib, | ||||
1327 | refclk_freq_in_mhz, | ||||
1328 | pclk_freq_in_mhz, | ||||
1329 | dst->odm_combine, | ||||
1330 | full_recout_width, | ||||
1331 | dst->hactive, | ||||
1332 | vratio_c, | ||||
1333 | hscale_pixel_rate_c, | ||||
1334 | swath_width_pixels_ub_c, | ||||
1335 | 1); // per line | ||||
1336 | |||||
1337 | dml_print({do { } while(0); } | ||||
1338 | "DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",{do { } while(0); } | ||||
1339 | __func__,{do { } while(0); } | ||||
1340 | refcyc_per_line_delivery_pre_c){do { } while(0); }; | ||||
1341 | dml_print({do { } while(0); } | ||||
1342 | "DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n",{do { } while(0); } | ||||
1343 | __func__,{do { } while(0); } | ||||
1344 | refcyc_per_line_delivery_c){do { } while(0); }; | ||||
1345 | } | ||||
1346 | |||||
1347 | // TTU - Luma / Chroma | ||||
1348 | if (access_dir) { // vertical access | ||||
1349 | scaler_rec_in_width_l = vp_height_l; | ||||
1350 | scaler_rec_in_width_c = vp_height_c; | ||||
1351 | } else { | ||||
1352 | scaler_rec_in_width_l = vp_width_l; | ||||
1353 | scaler_rec_in_width_c = vp_width_c; | ||||
1354 | } | ||||
1355 | |||||
1356 | refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery( | ||||
1357 | mode_lib, | ||||
1358 | refclk_freq_in_mhz, | ||||
1359 | pclk_freq_in_mhz, | ||||
1360 | dst->odm_combine, | ||||
1361 | full_recout_width, | ||||
1362 | dst->hactive, | ||||
1363 | vratio_pre_l, | ||||
1364 | hscale_pixel_rate_l, | ||||
1365 | scaler_rec_in_width_l, | ||||
1366 | req_per_swath_ub_l); // per req | ||||
1367 | refcyc_per_req_delivery_l = get_refcyc_per_delivery( | ||||
1368 | mode_lib, | ||||
1369 | refclk_freq_in_mhz, | ||||
1370 | pclk_freq_in_mhz, | ||||
1371 | dst->odm_combine, | ||||
1372 | full_recout_width, | ||||
1373 | dst->hactive, | ||||
1374 | vratio_l, | ||||
1375 | hscale_pixel_rate_l, | ||||
1376 | scaler_rec_in_width_l, | ||||
1377 | req_per_swath_ub_l); // per req | ||||
1378 | |||||
1379 | dml_print({do { } while(0); } | ||||
1380 | "DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",{do { } while(0); } | ||||
1381 | __func__,{do { } while(0); } | ||||
1382 | refcyc_per_req_delivery_pre_l){do { } while(0); }; | ||||
1383 | dml_print({do { } while(0); } | ||||
1384 | "DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n",{do { } while(0); } | ||||
1385 | __func__,{do { } while(0); } | ||||
1386 | refcyc_per_req_delivery_l){do { } while(0); }; | ||||
1387 | |||||
1388 | ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1388); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1389 | ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_l < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_l < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1389); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1390 | |||||
1391 | if (dual_plane) { | ||||
1392 | refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery( | ||||
1393 | mode_lib, | ||||
1394 | refclk_freq_in_mhz, | ||||
1395 | pclk_freq_in_mhz, | ||||
1396 | dst->odm_combine, | ||||
1397 | full_recout_width, | ||||
1398 | dst->hactive, | ||||
1399 | vratio_pre_c, | ||||
1400 | hscale_pixel_rate_c, | ||||
1401 | scaler_rec_in_width_c, | ||||
1402 | req_per_swath_ub_c); // per req | ||||
1403 | refcyc_per_req_delivery_c = get_refcyc_per_delivery( | ||||
1404 | mode_lib, | ||||
1405 | refclk_freq_in_mhz, | ||||
1406 | pclk_freq_in_mhz, | ||||
1407 | dst->odm_combine, | ||||
1408 | full_recout_width, | ||||
1409 | dst->hactive, | ||||
1410 | vratio_c, | ||||
1411 | hscale_pixel_rate_c, | ||||
1412 | scaler_rec_in_width_c, | ||||
1413 | req_per_swath_ub_c); // per req | ||||
1414 | |||||
1415 | dml_print({do { } while(0); } | ||||
1416 | "DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",{do { } while(0); } | ||||
1417 | __func__,{do { } while(0); } | ||||
1418 | refcyc_per_req_delivery_pre_c){do { } while(0); }; | ||||
1419 | dml_print({do { } while(0); } | ||||
1420 | "DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n",{do { } while(0); } | ||||
1421 | __func__,{do { } while(0); } | ||||
1422 | refcyc_per_req_delivery_c){do { } while(0); }; | ||||
1423 | |||||
1424 | ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_pre_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1424); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1425 | ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(refcyc_per_req_delivery_c < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(refcyc_per_req_delivery_c < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1425); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1426 | } | ||||
1427 | |||||
1428 | // TTU - Cursor | ||||
1429 | refcyc_per_req_delivery_pre_cur0 = 0.0; | ||||
1430 | refcyc_per_req_delivery_cur0 = 0.0; | ||||
1431 | if (src->num_cursors > 0) { | ||||
1432 | calculate_ttu_cursor( | ||||
1433 | mode_lib, | ||||
1434 | &refcyc_per_req_delivery_pre_cur0, | ||||
1435 | &refcyc_per_req_delivery_cur0, | ||||
1436 | refclk_freq_in_mhz, | ||||
1437 | ref_freq_to_pix_freq, | ||||
1438 | hscale_pixel_rate_l, | ||||
1439 | scl->hscl_ratio, | ||||
1440 | vratio_pre_l, | ||||
1441 | vratio_l, | ||||
1442 | src->cur0_src_width, | ||||
1443 | (enum cursor_bpp) (src->cur0_bpp)); | ||||
1444 | } | ||||
1445 | |||||
1446 | refcyc_per_req_delivery_pre_cur1 = 0.0; | ||||
1447 | refcyc_per_req_delivery_cur1 = 0.0; | ||||
1448 | if (src->num_cursors > 1) { | ||||
1449 | calculate_ttu_cursor( | ||||
1450 | mode_lib, | ||||
1451 | &refcyc_per_req_delivery_pre_cur1, | ||||
1452 | &refcyc_per_req_delivery_cur1, | ||||
1453 | refclk_freq_in_mhz, | ||||
1454 | ref_freq_to_pix_freq, | ||||
1455 | hscale_pixel_rate_l, | ||||
1456 | scl->hscl_ratio, | ||||
1457 | vratio_pre_l, | ||||
1458 | vratio_l, | ||||
1459 | src->cur1_src_width, | ||||
1460 | (enum cursor_bpp) (src->cur1_bpp)); | ||||
1461 | } | ||||
1462 | |||||
1463 | // TTU - Misc | ||||
1464 | // all hard-coded | ||||
1465 | |||||
1466 | // Assignment to register structures | ||||
1467 | disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line | ||||
1468 | disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk | ||||
1469 | ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13)) ); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1469); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1470 | disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); | ||||
1471 | disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); | ||||
1472 | disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); | ||||
1473 | disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); | ||||
1474 | disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); | ||||
1475 | |||||
1476 | disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); | ||||
1477 | disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); | ||||
1478 | |||||
1479 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_vblank){do { } while(0); }; | ||||
1480 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_vblank = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_vblank){do { } while(0); }; | ||||
1481 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_vm_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_vm_flip){do { } while(0); }; | ||||
1482 | dml_print("DML_DLG: %s: disp_dlg_regs->dst_y_per_row_flip = 0x%x\n", __func__, disp_dlg_regs->dst_y_per_row_flip){do { } while(0); }; | ||||
1483 | |||||
1484 | disp_dlg_regs->refcyc_per_pte_group_vblank_l = | ||||
1485 | (unsigned int) (dst_y_per_row_vblank * (double) htotal | ||||
1486 | * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); | ||||
1487 | if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) && | ||||
1488 | disp_dlg_regs->refcyc_per_pte_group_vblank_l >= (unsigned int)dml_pow(2, 13)) | ||||
1489 | disp_dlg_regs->refcyc_per_pte_group_vblank_l = (1 << 13) - 1; | ||||
1490 | else | ||||
1491 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1491); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1492 | |||||
1493 | if (dual_plane) { | ||||
1494 | disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank | ||||
1495 | * (double) htotal * ref_freq_to_pix_freq | ||||
1496 | / (double) dpte_groups_per_row_ub_c); | ||||
1497 | if ((refclk_freq_in_mhz / ref_freq_to_pix_freq < 28) && | ||||
1498 | disp_dlg_regs->refcyc_per_pte_group_vblank_c >= (unsigned int)dml_pow(2, 13)) | ||||
1499 | disp_dlg_regs->refcyc_per_pte_group_vblank_c = (1 << 13) - 1; | ||||
1500 | else | ||||
1501 | ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_cdo { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1502); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0) | ||||
1502 | < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_pte_group_vblank_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1502); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1503 | } | ||||
1504 | |||||
1505 | if (src->dcc) | ||||
1506 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = | ||||
1507 | (unsigned int) (dst_y_per_row_vblank * (double) htotal | ||||
1508 | * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); | ||||
1509 | else | ||||
1510 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 0; | ||||
1511 | ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1511); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1512 | |||||
1513 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = | ||||
1514 | disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now | ||||
1515 | |||||
1516 | disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal | ||||
1517 | * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; | ||||
1518 | disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal | ||||
1519 | * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; | ||||
1520 | |||||
1521 | if (dual_plane) { | ||||
1522 | disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip | ||||
1523 | * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; | ||||
1524 | disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip | ||||
1525 | * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; | ||||
1526 | } | ||||
1527 | |||||
1528 | disp_dlg_regs->refcyc_per_vm_group_vblank = get_refcyc_per_vm_group_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; | ||||
1529 | disp_dlg_regs->refcyc_per_vm_group_flip = get_refcyc_per_vm_group_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz; | ||||
1530 | disp_dlg_regs->refcyc_per_vm_req_vblank = get_refcyc_per_vm_req_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); | ||||
1531 | disp_dlg_regs->refcyc_per_vm_req_flip = get_refcyc_per_vm_req_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx) * refclk_freq_in_mhz * dml_pow(2, 10); | ||||
1532 | |||||
1533 | // Clamp to max for now | ||||
1534 | if (disp_dlg_regs->refcyc_per_vm_group_vblank >= (unsigned int)dml_pow(2, 23)) | ||||
1535 | disp_dlg_regs->refcyc_per_vm_group_vblank = dml_pow(2, 23) - 1; | ||||
1536 | |||||
1537 | if (disp_dlg_regs->refcyc_per_vm_group_flip >= (unsigned int)dml_pow(2, 23)) | ||||
1538 | disp_dlg_regs->refcyc_per_vm_group_flip = dml_pow(2, 23) - 1; | ||||
1539 | |||||
1540 | if (disp_dlg_regs->refcyc_per_vm_req_vblank >= (unsigned int)dml_pow(2, 23)) | ||||
1541 | disp_dlg_regs->refcyc_per_vm_req_vblank = dml_pow(2, 23) - 1; | ||||
1542 | |||||
1543 | if (disp_dlg_regs->refcyc_per_vm_req_flip >= (unsigned int)dml_pow(2, 23)) | ||||
1544 | disp_dlg_regs->refcyc_per_vm_req_flip = dml_pow(2, 23) - 1; | ||||
1545 | disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l | ||||
1546 | / (double) vratio_l * dml_pow(2, 2)); | ||||
1547 | ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int)dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1547); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1548 | |||||
1549 | if (dual_plane) { | ||||
1550 | disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c | ||||
1551 | / (double) vratio_c * dml_pow(2, 2)); | ||||
1552 | if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { | ||||
1553 | dml_print({do { } while(0); } | ||||
1554 | "DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",{do { } while(0); } | ||||
1555 | __func__,{do { } while(0); } | ||||
1556 | disp_dlg_regs->dst_y_per_pte_row_nom_c,{do { } while(0); } | ||||
1557 | (unsigned int)dml_pow(2, 17) - 1){do { } while(0); }; | ||||
1558 | } | ||||
1559 | } | ||||
1560 | |||||
1561 | disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l | ||||
1562 | / (double) vratio_l * dml_pow(2, 2)); | ||||
1563 | ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17 ))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int)dml_pow(2, 17))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1563); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1564 | |||||
1565 | disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now | ||||
1566 | |||||
1567 | dml_print({do { } while(0); } | ||||
1568 | "DML: Trow: %fus\n",{do { } while(0); } | ||||
1569 | line_time_in_us * (double)dpte_row_height_l / (double)vratio_l){do { } while(0); }; | ||||
1570 | |||||
1571 | disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l | ||||
1572 | / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq | ||||
1573 | / (double) dpte_groups_per_row_ub_l); | ||||
1574 | if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) | ||||
1575 | disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; | ||||
1576 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l | ||||
1577 | / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq | ||||
1578 | / (double) meta_chunks_per_row_ub_l); | ||||
1579 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) | ||||
1580 | disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; | ||||
1581 | |||||
1582 | if (dual_plane) { | ||||
1583 | disp_dlg_regs->refcyc_per_pte_group_nom_c = | ||||
1584 | (unsigned int) ((double) dpte_row_height_c / (double) vratio_c | ||||
1585 | * (double) htotal * ref_freq_to_pix_freq | ||||
1586 | / (double) dpte_groups_per_row_ub_c); | ||||
1587 | if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) | ||||
1588 | disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; | ||||
1589 | |||||
1590 | // TODO: Is this the right calculation? Does htotal need to be halved? | ||||
1591 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = | ||||
1592 | (unsigned int) ((double) meta_row_height_c / (double) vratio_c | ||||
1593 | * (double) htotal * ref_freq_to_pix_freq | ||||
1594 | / (double) meta_chunks_per_row_ub_c); | ||||
1595 | if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) | ||||
1596 | disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; | ||||
1597 | } | ||||
1598 | |||||
1599 | disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( | ||||
1600 | refcyc_per_line_delivery_pre_l, 1); | ||||
1601 | disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor( | ||||
1602 | refcyc_per_line_delivery_l, 1); | ||||
1603 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1603); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1604 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1604); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1605 | |||||
1606 | disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor( | ||||
1607 | refcyc_per_line_delivery_pre_c, 1); | ||||
1608 | disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor( | ||||
1609 | refcyc_per_line_delivery_c, 1); | ||||
1610 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow (2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1610); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1611 | ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(disp_dlg_regs ->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int)dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1611); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1612 | |||||
1613 | disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; | ||||
1614 | disp_dlg_regs->dst_y_offset_cur0 = 0; | ||||
1615 | disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; | ||||
1616 | disp_dlg_regs->dst_y_offset_cur1 = 0; | ||||
1617 | |||||
1618 | disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off | ||||
1619 | |||||
1620 | disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l | ||||
1621 | * dml_pow(2, 10)); | ||||
1622 | disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l | ||||
1623 | * dml_pow(2, 10)); | ||||
1624 | disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c | ||||
1625 | * dml_pow(2, 10)); | ||||
1626 | disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c | ||||
1627 | * dml_pow(2, 10)); | ||||
1628 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = | ||||
1629 | (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); | ||||
1630 | disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 | ||||
1631 | * dml_pow(2, 10)); | ||||
1632 | disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = | ||||
1633 | (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); | ||||
1634 | disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 | ||||
1635 | * dml_pow(2, 10)); | ||||
1636 | disp_ttu_regs->qos_level_low_wm = 0; | ||||
1637 | ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_low_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1637); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1638 | disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal | ||||
1639 | * ref_freq_to_pix_freq); | ||||
1640 | ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->qos_level_high_wm < dml_pow(2, 14))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1640); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1641 | |||||
1642 | disp_ttu_regs->qos_level_flip = 14; | ||||
1643 | disp_ttu_regs->qos_level_fixed_l = 8; | ||||
1644 | disp_ttu_regs->qos_level_fixed_c = 8; | ||||
1645 | disp_ttu_regs->qos_level_fixed_cur0 = 8; | ||||
1646 | disp_ttu_regs->qos_ramp_disable_l = 0; | ||||
1647 | disp_ttu_regs->qos_ramp_disable_c = 0; | ||||
1648 | disp_ttu_regs->qos_ramp_disable_cur0 = 0; | ||||
1649 | |||||
1650 | disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; | ||||
1651 | ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))do { if (({ static int __warned; int __ret = !!(!(disp_ttu_regs ->min_ttu_vblank < dml_pow(2, 24))); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n", "!(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1651); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1652 | |||||
1653 | print__ttu_regs_st(mode_lib, *disp_ttu_regs); | ||||
1654 | print__dlg_regs_st(mode_lib, *disp_dlg_regs); | ||||
1655 | } | ||||
1656 | |||||
1657 | void dml21_rq_dlg_get_dlg_reg( | ||||
1658 | struct display_mode_lib *mode_lib, | ||||
1659 | display_dlg_regs_st *dlg_regs, | ||||
1660 | display_ttu_regs_st *ttu_regs, | ||||
1661 | display_e2e_pipe_params_st *e2e_pipe_param, | ||||
1662 | const unsigned int num_pipes, | ||||
1663 | const unsigned int pipe_idx, | ||||
1664 | const bool_Bool cstate_en, | ||||
1665 | const bool_Bool pstate_en, | ||||
1666 | const bool_Bool vm_en, | ||||
1667 | const bool_Bool ignore_viewport_pos, | ||||
1668 | const bool_Bool immediate_flip_support) | ||||
1669 | { | ||||
1670 | display_rq_params_st rq_param = {0}; | ||||
1671 | display_dlg_sys_params_st dlg_sys_param = {0}; | ||||
1672 | |||||
1673 | // Get watermark and Tex. | ||||
1674 | dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); | ||||
1675 | dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep( | ||||
1676 | mode_lib, | ||||
1677 | e2e_pipe_param, | ||||
1678 | num_pipes); | ||||
1679 | dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); | ||||
1680 | dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); | ||||
1681 | dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); | ||||
1682 | dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); | ||||
1683 | dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw( | ||||
1684 | mode_lib, | ||||
1685 | e2e_pipe_param, | ||||
1686 | num_pipes); | ||||
1687 | dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes( | ||||
1688 | mode_lib, | ||||
1689 | e2e_pipe_param, | ||||
1690 | num_pipes); | ||||
1691 | dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency | ||||
1692 | / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated | ||||
1693 | |||||
1694 | print__dlg_sys_params_st(mode_lib, dlg_sys_param); | ||||
1695 | |||||
1696 | // system parameter calculation done | ||||
1697 | |||||
1698 | dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx){do { } while(0); }; | ||||
| |||||
1699 | dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe); | ||||
1700 | dml_rq_dlg_get_dlg_params( | ||||
1701 | mode_lib, | ||||
1702 | e2e_pipe_param, | ||||
1703 | num_pipes, | ||||
1704 | pipe_idx, | ||||
1705 | dlg_regs, | ||||
1706 | ttu_regs, | ||||
1707 | rq_param.dlg, | ||||
1708 | dlg_sys_param, | ||||
1709 | cstate_en, | ||||
1710 | pstate_en); | ||||
1711 | dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx){do { } while(0); }; | ||||
1712 | } | ||||
1713 | |||||
1714 | void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param) | ||||
1715 | { | ||||
1716 | memset(arb_param, 0, sizeof(*arb_param))__builtin_memset((arb_param), (0), (sizeof(*arb_param))); | ||||
1717 | arb_param->max_req_outstanding = 256; | ||||
1718 | arb_param->min_req_outstanding = 68; | ||||
1719 | arb_param->sat_level_us = 60; | ||||
1720 | } | ||||
1721 | |||||
1722 | static void calculate_ttu_cursor( | ||||
1723 | struct display_mode_lib *mode_lib, | ||||
1724 | double *refcyc_per_req_delivery_pre_cur, | ||||
1725 | double *refcyc_per_req_delivery_cur, | ||||
1726 | double refclk_freq_in_mhz, | ||||
1727 | double ref_freq_to_pix_freq, | ||||
1728 | double hscale_pixel_rate_l, | ||||
1729 | double hscl_ratio, | ||||
1730 | double vratio_pre_l, | ||||
1731 | double vratio_l, | ||||
1732 | unsigned int cur_width, | ||||
1733 | enum cursor_bpp cur_bpp) | ||||
1734 | { | ||||
1735 | unsigned int cur_src_width = cur_width; | ||||
1736 | unsigned int cur_req_size = 0; | ||||
1737 | unsigned int cur_req_width = 0; | ||||
1738 | double cur_width_ub = 0.0; | ||||
1739 | double cur_req_per_width = 0.0; | ||||
1740 | double hactive_cur = 0.0; | ||||
1741 | |||||
1742 | ASSERT(cur_src_width <= 256)do { if (({ static int __warned; int __ret = !!(!(cur_src_width <= 256)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n" , "!(cur_src_width <= 256)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1742); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1743 | |||||
1744 | *refcyc_per_req_delivery_pre_cur = 0.0; | ||||
1745 | *refcyc_per_req_delivery_cur = 0.0; | ||||
1746 | if (cur_src_width > 0) { | ||||
1747 | unsigned int cur_bit_per_pixel = 0; | ||||
1748 | |||||
1749 | if (cur_bpp == dm_cur_2bit) { | ||||
1750 | cur_req_size = 64; // byte | ||||
1751 | cur_bit_per_pixel = 2; | ||||
1752 | } else { // 32bit | ||||
1753 | cur_bit_per_pixel = 32; | ||||
1754 | if (cur_src_width >= 1 && cur_src_width <= 16) | ||||
1755 | cur_req_size = 64; | ||||
1756 | else if (cur_src_width >= 17 && cur_src_width <= 31) | ||||
1757 | cur_req_size = 128; | ||||
1758 | else | ||||
1759 | cur_req_size = 256; | ||||
1760 | } | ||||
1761 | |||||
1762 | cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); | ||||
1763 | cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) | ||||
1764 | * (double) cur_req_width; | ||||
1765 | cur_req_per_width = cur_width_ub / (double) cur_req_width; | ||||
1766 | hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor | ||||
1767 | |||||
1768 | if (vratio_pre_l <= 1.0) { | ||||
1769 | *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq | ||||
1770 | / (double) cur_req_per_width; | ||||
1771 | } else { | ||||
1772 | *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz | ||||
1773 | * (double) cur_src_width / hscale_pixel_rate_l | ||||
1774 | / (double) cur_req_per_width; | ||||
1775 | } | ||||
1776 | |||||
1777 | ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1777); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1778 | |||||
1779 | if (vratio_l <= 1.0) { | ||||
1780 | *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq | ||||
1781 | / (double) cur_req_per_width; | ||||
1782 | } else { | ||||
1783 | *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz | ||||
1784 | * (double) cur_src_width / hscale_pixel_rate_l | ||||
1785 | / (double) cur_req_per_width; | ||||
1786 | } | ||||
1787 | |||||
1788 | dml_print({do { } while(0); } | ||||
1789 | "DML_DLG: %s: cur_req_width = %d\n",{do { } while(0); } | ||||
1790 | __func__,{do { } while(0); } | ||||
1791 | cur_req_width){do { } while(0); }; | ||||
1792 | dml_print({do { } while(0); } | ||||
1793 | "DML_DLG: %s: cur_width_ub = %3.2f\n",{do { } while(0); } | ||||
1794 | __func__,{do { } while(0); } | ||||
1795 | cur_width_ub){do { } while(0); }; | ||||
1796 | dml_print({do { } while(0); } | ||||
1797 | "DML_DLG: %s: cur_req_per_width = %3.2f\n",{do { } while(0); } | ||||
1798 | __func__,{do { } while(0); } | ||||
1799 | cur_req_per_width){do { } while(0); }; | ||||
1800 | dml_print({do { } while(0); } | ||||
1801 | "DML_DLG: %s: hactive_cur = %3.2f\n",{do { } while(0); } | ||||
1802 | __func__,{do { } while(0); } | ||||
1803 | hactive_cur){do { } while(0); }; | ||||
1804 | dml_print({do { } while(0); } | ||||
1805 | "DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n",{do { } while(0); } | ||||
1806 | __func__,{do { } while(0); } | ||||
1807 | *refcyc_per_req_delivery_pre_cur){do { } while(0); }; | ||||
1808 | dml_print({do { } while(0); } | ||||
1809 | "DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n",{do { } while(0); } | ||||
1810 | __func__,{do { } while(0); } | ||||
1811 | *refcyc_per_req_delivery_cur){do { } while(0); }; | ||||
1812 | |||||
1813 | ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13))do { if (({ static int __warned; int __ret = !!(!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))); if (__ret && !__warned) { printf ("WARNING %s failed at %s:%d\n", "!(*refcyc_per_req_delivery_cur < dml_pow(2, 13))" , "/usr/src/sys/dev/pci/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c" , 1813); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do {} while (0); } while (0); | ||||
1814 | } | ||||
1815 | } | ||||
1816 |