Bug Summary

File:dev/pci/drm/i915/display/intel_dsi_vbt.c
Warning:line 524, column 27
Value stored to 'i915' during its initialization is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name intel_dsi_vbt.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_dsi_vbt.c
1/*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Shobhit Kumar <shobhit.kumar@intel.com>
24 *
25 */
26
27#include <linux/gpio/consumer.h>
28#ifdef notyet
29#include <linux/gpio/machine.h>
30#include <linux/mfd/intel_soc_pmic.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pinctrl/machine.h>
33#endif
34#include <linux/slab.h>
35
36#include <asm/intel-mid.h>
37#include <asm/unaligned.h>
38
39#include <drm/drm_crtc.h>
40#include <drm/drm_edid.h>
41
42#include <video/mipi_display.h>
43
44#include "i915_drv.h"
45#include "intel_display_types.h"
46#include "intel_dsi.h"
47#include "intel_sideband.h"
48
49#define MIPI_TRANSFER_MODE_SHIFT0 0
50#define MIPI_VIRTUAL_CHANNEL_SHIFT1 1
51#define MIPI_PORT_SHIFT3 3
52
53/* base offsets for gpio pads */
54#define VLV_GPIO_NC_0_HV_DDI0_HPD0x4130 0x4130
55#define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA0x4120 0x4120
56#define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL0x4110 0x4110
57#define VLV_GPIO_NC_3_PANEL0_VDDEN0x4140 0x4140
58#define VLV_GPIO_NC_4_PANEL0_BKLTEN0x4150 0x4150
59#define VLV_GPIO_NC_5_PANEL0_BKLTCTL0x4160 0x4160
60#define VLV_GPIO_NC_6_HV_DDI1_HPD0x4180 0x4180
61#define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA0x4190 0x4190
62#define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL0x4170 0x4170
63#define VLV_GPIO_NC_9_PANEL1_VDDEN0x4100 0x4100
64#define VLV_GPIO_NC_10_PANEL1_BKLTEN0x40E0 0x40E0
65#define VLV_GPIO_NC_11_PANEL1_BKLTCTL0x40F0 0x40F0
66
67#define VLV_GPIO_PCONF0(base_offset)(base_offset) (base_offset)
68#define VLV_GPIO_PAD_VAL(base_offset)((base_offset) + 8) ((base_offset) + 8)
69
70struct gpio_map {
71 u16 base_offset;
72 bool_Bool init;
73};
74
75static struct gpio_map vlv_gpio_table[] = {
76 { VLV_GPIO_NC_0_HV_DDI0_HPD0x4130 },
77 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA0x4120 },
78 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL0x4110 },
79 { VLV_GPIO_NC_3_PANEL0_VDDEN0x4140 },
80 { VLV_GPIO_NC_4_PANEL0_BKLTEN0x4150 },
81 { VLV_GPIO_NC_5_PANEL0_BKLTCTL0x4160 },
82 { VLV_GPIO_NC_6_HV_DDI1_HPD0x4180 },
83 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA0x4190 },
84 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL0x4170 },
85 { VLV_GPIO_NC_9_PANEL1_VDDEN0x4100 },
86 { VLV_GPIO_NC_10_PANEL1_BKLTEN0x40E0 },
87 { VLV_GPIO_NC_11_PANEL1_BKLTCTL0x40F0 },
88};
89
90struct i2c_adapter_lookup {
91 u16 slave_addr;
92 struct intel_dsi *intel_dsi;
93#ifdef notyet
94 acpi_handle dev_handle;
95#endif
96};
97
98#define CHV_GPIO_IDX_START_N0 0
99#define CHV_GPIO_IDX_START_E73 73
100#define CHV_GPIO_IDX_START_SW100 100
101#define CHV_GPIO_IDX_START_SE198 198
102
103#define CHV_VBT_MAX_PINS_PER_FMLY15 15
104
105#define CHV_GPIO_PAD_CFG0(f, i)(0x4400 + (f) * 0x400 + (i) * 8) (0x4400 + (f) * 0x400 + (i) * 8)
106#define CHV_GPIO_GPIOEN(1 << 15) (1 << 15)
107#define CHV_GPIO_GPIOCFG_GPIO(0 << 8) (0 << 8)
108#define CHV_GPIO_GPIOCFG_GPO(1 << 8) (1 << 8)
109#define CHV_GPIO_GPIOCFG_GPI(2 << 8) (2 << 8)
110#define CHV_GPIO_GPIOCFG_HIZ(3 << 8) (3 << 8)
111#define CHV_GPIO_GPIOTXSTATE(state)((!!(state)) << 1) ((!!(state)) << 1)
112
113#define CHV_GPIO_PAD_CFG1(f, i)(0x4400 + (f) * 0x400 + (i) * 8 + 4) (0x4400 + (f) * 0x400 + (i) * 8 + 4)
114#define CHV_GPIO_CFGLOCK(1 << 31) (1 << 31)
115
116/* ICL DSI Display GPIO Pins */
117#define ICL_GPIO_DDSP_HPD_A0 0
118#define ICL_GPIO_L_VDDEN_11 1
119#define ICL_GPIO_L_BKLTEN_12 2
120#define ICL_GPIO_DDPA_CTRLCLK_13 3
121#define ICL_GPIO_DDPA_CTRLDATA_14 4
122#define ICL_GPIO_DDSP_HPD_B5 5
123#define ICL_GPIO_L_VDDEN_26 6
124#define ICL_GPIO_L_BKLTEN_27 7
125#define ICL_GPIO_DDPA_CTRLCLK_28 8
126#define ICL_GPIO_DDPA_CTRLDATA_29 9
127
128static enum port intel_dsi_seq_port_to_port(u8 port)
129{
130 return port ? PORT_C : PORT_A;
131}
132
133static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi,
134 const u8 *data)
135{
136 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_dsi->base.base.dev);
137 struct mipi_dsi_device *dsi_device;
138 u8 type, flags, seq_port;
139 u16 len;
140 enum port port;
141
142 drm_dbg_kms(&dev_priv->drm, "\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "\n"
);
143
144 flags = *data++;
145 type = *data++;
146
147 len = *((u16 *) data);
148 data += 2;
149
150 seq_port = (flags >> MIPI_PORT_SHIFT3) & 3;
151
152 /* For DSI single link on Port A & C, the seq_port value which is
153 * parsed from Sequence Block#53 of VBT has been set to 0
154 * Now, read/write of packets for the DSI single link on Port A and
155 * Port C will based on the DVO port from VBT block 2.
156 */
157 if (intel_dsi->ports == (1 << PORT_C))
158 port = PORT_C;
159 else
160 port = intel_dsi_seq_port_to_port(seq_port);
161
162 dsi_device = intel_dsi->dsi_hosts[port]->device;
163 if (!dsi_device) {
164 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no dsi device for port %c\n"
, ((port) + 'A'))
165 port_name(port))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no dsi device for port %c\n"
, ((port) + 'A'));
166 goto out;
167 }
168
169 if ((flags >> MIPI_TRANSFER_MODE_SHIFT0) & 1)
170 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM(1 << 0);
171 else
172 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM(1 << 0);
173
174 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT1) & 3;
175
176 switch (type) {
177 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM0x03:
178 mipi_dsi_generic_write(dsi_device, NULL((void *)0), 0);
179 break;
180 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM0x13:
181 mipi_dsi_generic_write(dsi_device, data, 1);
182 break;
183 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM0x23:
184 mipi_dsi_generic_write(dsi_device, data, 2);
185 break;
186 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM0x04:
187 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM0x14:
188 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM0x24:
189 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Generic Read not yet implemented or used\n"
)
190 "Generic Read not yet implemented or used\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Generic Read not yet implemented or used\n"
);
191 break;
192 case MIPI_DSI_GENERIC_LONG_WRITE0x29:
193 mipi_dsi_generic_write(dsi_device, data, len);
194 break;
195 case MIPI_DSI_DCS_SHORT_WRITE0x05:
196 mipi_dsi_dcs_write_buffer(dsi_device, data, 1);
197 break;
198 case MIPI_DSI_DCS_SHORT_WRITE_PARAM0x15:
199 mipi_dsi_dcs_write_buffer(dsi_device, data, 2);
200 break;
201 case MIPI_DSI_DCS_READ0x06:
202 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DCS Read not yet implemented or used\n"
)
203 "DCS Read not yet implemented or used\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DCS Read not yet implemented or used\n"
);
204 break;
205 case MIPI_DSI_DCS_LONG_WRITE0x39:
206 mipi_dsi_dcs_write_buffer(dsi_device, data, len);
207 break;
208 }
209
210 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 11)
211 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
212
213out:
214 data += len;
215
216 return data;
217}
218
219static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data)
220{
221 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
222 u32 delay = *((const u32 *) data);
223
224 drm_dbg_kms(&i915->drm, "\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\n");
225
226 usleep_range(delay, delay + 10);
227 data += 4;
228
229 return data;
230}
231
232static void vlv_exec_gpio(struct drm_i915_privateinteldrm_softc *dev_priv,
233 u8 gpio_source, u8 gpio_index, bool_Bool value)
234{
235 struct gpio_map *map;
236 u16 pconf0, padval;
237 u32 tmp;
238 u8 port;
239
240 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)(sizeof((vlv_gpio_table)) / sizeof((vlv_gpio_table)[0]))) {
241 drm_dbg_kms(&dev_priv->drm, "unknown gpio index %u\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unknown gpio index %u\n"
, gpio_index)
242 gpio_index)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unknown gpio index %u\n"
, gpio_index);
243 return;
244 }
245
246 map = &vlv_gpio_table[gpio_index];
247
248 if (dev_priv->vbt.dsi.seq_version >= 3) {
249 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */
250 port = IOSF_PORT_GPIO_NC0x13;
251 } else {
252 if (gpio_source == 0) {
253 port = IOSF_PORT_GPIO_NC0x13;
254 } else if (gpio_source == 1) {
255 drm_dbg_kms(&dev_priv->drm, "SC gpio not supported\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "SC gpio not supported\n"
);
256 return;
257 } else {
258 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source)
259 "unknown gpio source %u\n", gpio_source)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source);
260 return;
261 }
262 }
263
264 pconf0 = VLV_GPIO_PCONF0(map->base_offset)(map->base_offset);
265 padval = VLV_GPIO_PAD_VAL(map->base_offset)((map->base_offset) + 8);
266
267 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
268 if (!map->init) {
269 /* FIXME: remove constant below */
270 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
271 map->init = true1;
272 }
273
274 tmp = 0x4 | value;
275 vlv_iosf_sb_write(dev_priv, port, padval, tmp);
276 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
277}
278
279static void chv_exec_gpio(struct drm_i915_privateinteldrm_softc *dev_priv,
280 u8 gpio_source, u8 gpio_index, bool_Bool value)
281{
282 u16 cfg0, cfg1;
283 u16 family_num;
284 u8 port;
285
286 if (dev_priv->vbt.dsi.seq_version >= 3) {
287 if (gpio_index >= CHV_GPIO_IDX_START_SE198) {
288 /* XXX: it's unclear whether 255->57 is part of SE. */
289 gpio_index -= CHV_GPIO_IDX_START_SE198;
290 port = CHV_IOSF_PORT_GPIO_SE0x48;
291 } else if (gpio_index >= CHV_GPIO_IDX_START_SW100) {
292 gpio_index -= CHV_GPIO_IDX_START_SW100;
293 port = CHV_IOSF_PORT_GPIO_SW0xb2;
294 } else if (gpio_index >= CHV_GPIO_IDX_START_E73) {
295 gpio_index -= CHV_GPIO_IDX_START_E73;
296 port = CHV_IOSF_PORT_GPIO_E0xa8;
297 } else {
298 port = CHV_IOSF_PORT_GPIO_N0x13;
299 }
300 } else {
301 /* XXX: The spec is unclear about CHV GPIO on seq v2 */
302 if (gpio_source != 0) {
303 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source)
304 "unknown gpio source %u\n", gpio_source)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unknown gpio source %u\n"
, gpio_source);
305 return;
306 }
307
308 if (gpio_index >= CHV_GPIO_IDX_START_E73) {
309 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid gpio index %u for GPIO N\n"
, gpio_index)
310 "invalid gpio index %u for GPIO N\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid gpio index %u for GPIO N\n"
, gpio_index)
311 gpio_index)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid gpio index %u for GPIO N\n"
, gpio_index);
312 return;
313 }
314
315 port = CHV_IOSF_PORT_GPIO_N0x13;
316 }
317
318 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY15;
319 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY15;
320
321 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index)(0x4400 + (family_num) * 0x400 + (gpio_index) * 8);
322 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index)(0x4400 + (family_num) * 0x400 + (gpio_index) * 8 + 4);
323
324 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
325 vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
326 vlv_iosf_sb_write(dev_priv, port, cfg0,
327 CHV_GPIO_GPIOEN(1 << 15) | CHV_GPIO_GPIOCFG_GPO(1 << 8) |
328 CHV_GPIO_GPIOTXSTATE(value)((!!(value)) << 1));
329 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)(1UL << (VLV_IOSF_SB_GPIO)));
330}
331
332static void bxt_exec_gpio(struct drm_i915_privateinteldrm_softc *dev_priv,
333 u8 gpio_source, u8 gpio_index, bool_Bool value)
334{
335 STUB()do { printf("%s: stub\n", __func__); } while(0);
336#ifdef __linux__
337 /* XXX: this table is a quick ugly hack. */
338 static struct gpio_desc *bxt_gpio_table[U8_MAX0xff + 1];
339 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index];
340
341 if (!gpio_desc) {
342 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev,
343 NULL((void *)0), gpio_index,
344 value ? GPIOD_OUT_LOW :
345 GPIOD_OUT_HIGH);
346
347 if (IS_ERR_OR_NULL(gpio_desc)) {
348 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "GPIO index %u request failed (%ld)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , gpio_index
, PTR_ERR(gpio_desc))
349 "GPIO index %u request failed (%ld)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "GPIO index %u request failed (%ld)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , gpio_index
, PTR_ERR(gpio_desc))
350 gpio_index, PTR_ERR(gpio_desc))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "GPIO index %u request failed (%ld)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , gpio_index
, PTR_ERR(gpio_desc));
351 return;
352 }
353
354 bxt_gpio_table[gpio_index] = gpio_desc;
355 }
356
357 gpiod_set_value(gpio_desc, value);
358#endif
359}
360
361static void icl_exec_gpio(struct drm_i915_privateinteldrm_softc *dev_priv,
362 u8 gpio_source, u8 gpio_index, bool_Bool value)
363{
364 drm_dbg_kms(&dev_priv->drm, "Skipping ICL GPIO element execution\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Skipping ICL GPIO element execution\n"
);
365}
366
367static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
368{
369 struct drm_device *dev = intel_dsi->base.base.dev;
370 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
371 u8 gpio_source, gpio_index = 0, gpio_number;
372 bool_Bool value;
373
374 drm_dbg_kms(&dev_priv->drm, "\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "\n"
);
375
376 if (dev_priv->vbt.dsi.seq_version >= 3)
377 gpio_index = *data++;
378
379 gpio_number = *data++;
380
381 /* gpio source in sequence v2 only */
382 if (dev_priv->vbt.dsi.seq_version == 2)
383 gpio_source = (*data >> 1) & 3;
384 else
385 gpio_source = 0;
386
387 /* pull up/down */
388 value = *data++ & 1;
389
390 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11)
391 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value);
392 else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW))
393 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
394 else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
395 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value);
396 else
397 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value);
398
399 return data;
400}
401
402#if defined(CONFIG_ACPI1) && defined(__linux__)
403static int i2c_adapter_lookup(struct acpi_resource *ares, void *data)
404{
405 struct i2c_adapter_lookup *lookup = data;
406 struct intel_dsi *intel_dsi = lookup->intel_dsi;
407 struct acpi_resource_i2c_serialbus *sb;
408 struct i2c_adapter *adapter;
409 acpi_handle adapter_handle;
410 acpi_status status;
411
412 if (!i2c_acpi_get_i2c_resource(ares, &sb))
413 return 1;
414
415 if (lookup->slave_addr != sb->slave_address)
416 return 1;
417
418 status = acpi_get_handle(lookup->dev_handle,
419 sb->resource_source.string_ptr,
420 &adapter_handle);
421 if (ACPI_FAILURE(status)((status) != 0))
422 return 1;
423
424 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle);
425 if (adapter)
426 intel_dsi->i2c_bus_num = adapter->nr;
427
428 return 1;
429}
430
431static void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
432 const u16 slave_addr)
433{
434 struct drm_device *drm_dev = intel_dsi->base.base.dev;
435 struct device *dev = &drm_dev->pdev->dev;
436 struct acpi_device *acpi_dev;
437 struct list_head resource_list;
438 struct i2c_adapter_lookup lookup;
439
440 acpi_dev = ACPI_COMPANION(dev);
441 if (acpi_dev) {
442 memset(&lookup, 0, sizeof(lookup))__builtin_memset((&lookup), (0), (sizeof(lookup)));
443 lookup.slave_addr = slave_addr;
444 lookup.intel_dsi = intel_dsi;
445 lookup.dev_handle = acpi_device_handle(acpi_dev);
446
447 INIT_LIST_HEAD(&resource_list);
448 acpi_dev_get_resources(acpi_dev, &resource_list,
449 i2c_adapter_lookup,
450 &lookup);
451 acpi_dev_free_resource_list(&resource_list);
452 }
453}
454#else
455static inline void i2c_acpi_find_adapter(struct intel_dsi *intel_dsi,
456 const u16 slave_addr)
457{
458}
459#endif
460
461static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data)
462{
463 STUB()do { printf("%s: stub\n", __func__); } while(0);
464 return NULL((void *)0);
465#ifdef notyet
466 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
467 struct i2c_adapter *adapter;
468 struct i2c_msg msg;
469 int ret;
470 u8 vbt_i2c_bus_num = *(data + 2);
471 u16 slave_addr = *(u16 *)(data + 3);
472 u8 reg_offset = *(data + 5);
473 u8 payload_size = *(data + 6);
474 u8 *payload_data;
475
476 if (intel_dsi->i2c_bus_num < 0) {
477 intel_dsi->i2c_bus_num = vbt_i2c_bus_num;
478 i2c_acpi_find_adapter(intel_dsi, slave_addr);
479 }
480
481 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num);
482 if (!adapter) {
483 drm_err(&i915->drm, "Cannot find a valid i2c bus for xfer\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Cannot find a valid i2c bus for xfer\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
484 goto err_bus;
485 }
486
487 payload_data = kzalloc(payload_size + 1, GFP_KERNEL(0x0001 | 0x0004));
488 if (!payload_data)
489 goto err_alloc;
490
491 payload_data[0] = reg_offset;
492 memcpy(&payload_data[1], (data + 7), payload_size)__builtin_memcpy((&payload_data[1]), ((data + 7)), (payload_size
));
493
494 msg.addr = slave_addr;
495 msg.flags = 0;
496 msg.len = payload_size + 1;
497 msg.buf = payload_data;
498
499 ret = i2c_transfer(adapter, &msg, 1);
500 if (ret < 0)
501 drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to xfer payload of size (%u) to reg (%u)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , payload_size
, reg_offset)
502 "Failed to xfer payload of size (%u) to reg (%u)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to xfer payload of size (%u) to reg (%u)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , payload_size
, reg_offset)
503 payload_size, reg_offset)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to xfer payload of size (%u) to reg (%u)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , payload_size
, reg_offset);
504
505 kfree(payload_data);
506err_alloc:
507 i2c_put_adapter(adapter);
508err_bus:
509 return data + payload_size + 7;
510#endif
511}
512
513static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data)
514{
515 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
516
517 drm_dbg_kms(&i915->drm, "Skipping SPI element execution\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Skipping SPI element execution\n"
);
518
519 return data + *(data + 5) + 6;
520}
521
522static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data)
523{
524 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
Value stored to 'i915' during its initialization is never read
525#ifdef CONFIG_PMIC_OPREGION
526 u32 value, mask, reg_address;
527 u16 i2c_address;
528 int ret;
529
530 /* byte 0 aka PMIC Flag is reserved */
531 i2c_address = get_unaligned_le16(data + 1);
532 reg_address = get_unaligned_le32(data + 3)((__uint32_t)(*(__uint32_t *)(data + 3)));
533 value = get_unaligned_le32(data + 7)((__uint32_t)(*(__uint32_t *)(data + 7)));
534 mask = get_unaligned_le32(data + 11)((__uint32_t)(*(__uint32_t *)(data + 11)));
535
536 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address,
537 reg_address,
538 value, mask);
539 if (ret)
540 drm_err(&i915->drm, "%s failed, error: %d\n", __func__, ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s failed, error: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
, ret);
541#else
542 drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
543 "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
544#endif
545
546 return data + 15;
547}
548
549typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi,
550 const u8 *data);
551static const fn_mipi_elem_exec exec_elem[] = {
552 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet,
553 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay,
554 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio,
555 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c,
556 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi,
557 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic,
558};
559
560/*
561 * MIPI Sequence from VBT #53 parsing logic
562 * We have already separated each seqence during bios parsing
563 * Following is generic execution function for any sequence
564 */
565
566static const char * const seq_name[] = {
567 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET",
568 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP",
569 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON",
570 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF",
571 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET",
572 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON",
573 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF",
574 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON",
575 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF",
576 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON",
577 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF",
578};
579
580static const char *sequence_name(enum mipi_seq seq_id)
581{
582 if (seq_id < ARRAY_SIZE(seq_name)(sizeof((seq_name)) / sizeof((seq_name)[0])) && seq_name[seq_id])
583 return seq_name[seq_id];
584 else
585 return "(unknown)";
586}
587
588static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi,
589 enum mipi_seq seq_id)
590{
591 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_dsi->base.base.dev);
592 const u8 *data;
593 fn_mipi_elem_exec mipi_elem_exec;
594
595 if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((seq_id >= (sizeof((dev_priv->vbt.dsi
.sequence)) / sizeof((dev_priv->vbt.dsi.sequence)[0])))); if
(__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "seq_id >= (sizeof((dev_priv->vbt.dsi.sequence)) / sizeof((dev_priv->vbt.dsi.sequence)[0]))"
")"); __builtin_expect(!!(__ret), 0); })
596 seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))({ int __ret = !!((seq_id >= (sizeof((dev_priv->vbt.dsi
.sequence)) / sizeof((dev_priv->vbt.dsi.sequence)[0])))); if
(__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv
->drm))->dev), "", "drm_WARN_ON(" "seq_id >= (sizeof((dev_priv->vbt.dsi.sequence)) / sizeof((dev_priv->vbt.dsi.sequence)[0]))"
")"); __builtin_expect(!!(__ret), 0); }))
597 return;
598
599 data = dev_priv->vbt.dsi.sequence[seq_id];
600 if (!data)
601 return;
602
603 drm_WARN_ON(&dev_priv->drm, *data != seq_id)({ int __ret = !!((*data != seq_id)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "*data != seq_id" ")"); __builtin_expect(!!(
__ret), 0); });
604
605 drm_dbg_kms(&dev_priv->drm, "Starting MIPI sequence %d - %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Starting MIPI sequence %d - %s\n"
, seq_id, sequence_name(seq_id))
606 seq_id, sequence_name(seq_id))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Starting MIPI sequence %d - %s\n"
, seq_id, sequence_name(seq_id));
607
608 /* Skip Sequence Byte. */
609 data++;
610
611 /* Skip Size of Sequence. */
612 if (dev_priv->vbt.dsi.seq_version >= 3)
613 data += 4;
614
615 while (1) {
616 u8 operation_byte = *data++;
617 u8 operation_size = 0;
618
619 if (operation_byte == MIPI_SEQ_ELEM_END)
620 break;
621
622 if (operation_byte < ARRAY_SIZE(exec_elem)(sizeof((exec_elem)) / sizeof((exec_elem)[0])))
623 mipi_elem_exec = exec_elem[operation_byte];
624 else
625 mipi_elem_exec = NULL((void *)0);
626
627 /* Size of Operation. */
628 if (dev_priv->vbt.dsi.seq_version >= 3)
629 operation_size = *data++;
630
631 if (mipi_elem_exec) {
632 const u8 *next = data + operation_size;
633
634 data = mipi_elem_exec(intel_dsi, data);
635
636 /* Consistency check if we have size. */
637 if (operation_size && data != next) {
638 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Inconsistent operation size\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
639 "Inconsistent operation size\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Inconsistent operation size\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
640 return;
641 }
642 } else if (operation_size) {
643 /* We have size, skip. */
644 drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unsupported MIPI operation byte %u\n"
, operation_byte)
645 "Unsupported MIPI operation byte %u\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unsupported MIPI operation byte %u\n"
, operation_byte)
646 operation_byte)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unsupported MIPI operation byte %u\n"
, operation_byte);
647 data += operation_size;
648 } else {
649 /* No size, can't skip without parsing. */
650 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported MIPI operation byte %u\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , operation_byte
)
651 "Unsupported MIPI operation byte %u\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported MIPI operation byte %u\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , operation_byte
)
652 operation_byte)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported MIPI operation byte %u\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , operation_byte
);
653 return;
654 }
655 }
656}
657
658void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
659 enum mipi_seq seq_id)
660{
661 STUB()do { printf("%s: stub\n", __func__); } while(0);
662#ifdef notyet
663 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel)
664 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
665 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight)
666 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1);
667
668 intel_dsi_vbt_exec(intel_dsi, seq_id);
669
670 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel)
671 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
672 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight)
673 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0);
674#endif
675}
676
677void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
678{
679 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_dsi->base.base.dev);
680
681 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
682 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
683 return;
684
685 drm_msleep(msec)mdelay(msec);
686}
687
688void intel_dsi_log_params(struct intel_dsi *intel_dsi)
689{
690 struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_dsi->base.base.dev);
691
692 drm_dbg_kms(&i915->drm, "Pclk %d\n", intel_dsi->pclk)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Pclk %d\n"
, intel_dsi->pclk);
693 drm_dbg_kms(&i915->drm, "Pixel overlap %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Pixel overlap %d\n"
, intel_dsi->pixel_overlap)
694 intel_dsi->pixel_overlap)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Pixel overlap %d\n"
, intel_dsi->pixel_overlap);
695 drm_dbg_kms(&i915->drm, "Lane count %d\n", intel_dsi->lane_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Lane count %d\n"
, intel_dsi->lane_count);
696 drm_dbg_kms(&i915->drm, "DPHY param reg 0x%x\n", intel_dsi->dphy_reg)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DPHY param reg 0x%x\n"
, intel_dsi->dphy_reg);
697 drm_dbg_kms(&i915->drm, "Video mode format %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>")
698 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ?drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>")
699 "non-burst with sync pulse" :drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>")
700 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ?drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>")
701 "non-burst with sync events" :drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>")
702 intel_dsi->video_mode_format == VIDEO_MODE_BURST ?drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>")
703 "burst" : "<unknown>")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Video mode format %s\n"
, intel_dsi->video_mode_format == (1 << 0) ? "non-burst with sync pulse"
: intel_dsi->video_mode_format == (2 << 0) ? "non-burst with sync events"
: intel_dsi->video_mode_format == (3 << 0) ? "burst"
: "<unknown>");
704 drm_dbg_kms(&i915->drm, "Burst mode ratio %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Burst mode ratio %d\n"
, intel_dsi->burst_mode_ratio)
705 intel_dsi->burst_mode_ratio)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Burst mode ratio %d\n"
, intel_dsi->burst_mode_ratio);
706 drm_dbg_kms(&i915->drm, "Reset timer %d\n", intel_dsi->rst_timer_val)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Reset timer %d\n"
, intel_dsi->rst_timer_val);
707 drm_dbg_kms(&i915->drm, "Eot %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Eot %s\n"
, enableddisabled(intel_dsi->eotp_pkt))
708 enableddisabled(intel_dsi->eotp_pkt))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Eot %s\n"
, enableddisabled(intel_dsi->eotp_pkt));
709 drm_dbg_kms(&i915->drm, "Clockstop %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Clockstop %s\n"
, enableddisabled(!intel_dsi->clock_stop))
710 enableddisabled(!intel_dsi->clock_stop))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Clockstop %s\n"
, enableddisabled(!intel_dsi->clock_stop));
711 drm_dbg_kms(&i915->drm, "Mode %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Mode %s\n"
, intel_dsi->operation_mode ? "command" : "video")
712 intel_dsi->operation_mode ? "command" : "video")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Mode %s\n"
, intel_dsi->operation_mode ? "command" : "video");
713 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1)
714 drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"
)
715 "Dual link: DSI_DUAL_LINK_FRONT_BACK\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_FRONT_BACK\n"
);
716 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT2)
717 drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"
)
718 "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"
);
719 else
720 drm_dbg_kms(&i915->drm, "Dual link: NONE\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Dual link: NONE\n"
);
721 drm_dbg_kms(&i915->drm, "Pixel Format %d\n", intel_dsi->pixel_format)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Pixel Format %d\n"
, intel_dsi->pixel_format);
722 drm_dbg_kms(&i915->drm, "TLPX %d\n", intel_dsi->escape_clk_div)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "TLPX %d\n"
, intel_dsi->escape_clk_div);
723 drm_dbg_kms(&i915->drm, "LP RX Timeout 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "LP RX Timeout 0x%x\n"
, intel_dsi->lp_rx_timeout)
724 intel_dsi->lp_rx_timeout)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "LP RX Timeout 0x%x\n"
, intel_dsi->lp_rx_timeout);
725 drm_dbg_kms(&i915->drm, "Turnaround Timeout 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Turnaround Timeout 0x%x\n"
, intel_dsi->turn_arnd_val)
726 intel_dsi->turn_arnd_val)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Turnaround Timeout 0x%x\n"
, intel_dsi->turn_arnd_val);
727 drm_dbg_kms(&i915->drm, "Init Count 0x%x\n", intel_dsi->init_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Init Count 0x%x\n"
, intel_dsi->init_count);
728 drm_dbg_kms(&i915->drm, "HS to LP Count 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "HS to LP Count 0x%x\n"
, intel_dsi->hs_to_lp_count)
729 intel_dsi->hs_to_lp_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "HS to LP Count 0x%x\n"
, intel_dsi->hs_to_lp_count);
730 drm_dbg_kms(&i915->drm, "LP Byte Clock %d\n", intel_dsi->lp_byte_clk)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "LP Byte Clock %d\n"
, intel_dsi->lp_byte_clk);
731 drm_dbg_kms(&i915->drm, "DBI BW Timer 0x%x\n", intel_dsi->bw_timer)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "DBI BW Timer 0x%x\n"
, intel_dsi->bw_timer);
732 drm_dbg_kms(&i915->drm, "LP to HS Clock Count 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "LP to HS Clock Count 0x%x\n"
, intel_dsi->clk_lp_to_hs_count)
733 intel_dsi->clk_lp_to_hs_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "LP to HS Clock Count 0x%x\n"
, intel_dsi->clk_lp_to_hs_count);
734 drm_dbg_kms(&i915->drm, "HS to LP Clock Count 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "HS to LP Clock Count 0x%x\n"
, intel_dsi->clk_hs_to_lp_count)
735 intel_dsi->clk_hs_to_lp_count)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "HS to LP Clock Count 0x%x\n"
, intel_dsi->clk_hs_to_lp_count);
736 drm_dbg_kms(&i915->drm, "BTA %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "BTA %s\n"
, enableddisabled(!(intel_dsi->video_frmt_cfg_bits & (
1 << 3))))
737 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA)))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "BTA %s\n"
, enableddisabled(!(intel_dsi->video_frmt_cfg_bits & (
1 << 3))));
738}
739
740bool_Bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
741{
742 struct drm_device *dev = intel_dsi->base.base.dev;
743 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
744 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
745 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps;
746 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode;
747 u16 burst_mode_ratio;
748 enum port port;
749
750 drm_dbg_kms(&dev_priv->drm, "\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "\n"
);
751
752 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1;
753 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0;
754 intel_dsi->lane_count = mipi_config->lane_cnt + 1;
755 intel_dsi->pixel_format =
756 pixel_format_from_register_bits(
757 mipi_config->videomode_color_format << 7);
758
759 intel_dsi->dual_link = mipi_config->dual_link;
760 intel_dsi->pixel_overlap = mipi_config->pixel_overlap;
761 intel_dsi->operation_mode = mipi_config->is_cmd_mode;
762 intel_dsi->video_mode_format = mipi_config->video_transfer_mode;
763 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel;
764 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout;
765 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout;
766 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout;
767 intel_dsi->rst_timer_val = mipi_config->device_reset_timer;
768 intel_dsi->init_count = mipi_config->master_init_timer;
769 intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
770 intel_dsi->video_frmt_cfg_bits =
771 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA(1 << 3) : 0;
772 intel_dsi->bgr_enabled = mipi_config->rgb_flip;
773
774 /* Starting point, adjusted depending on dual link and burst mode */
775 intel_dsi->pclk = mode->clock;
776
777 /* In dual link mode each port needs half of pixel clock */
778 if (intel_dsi->dual_link) {
779 intel_dsi->pclk /= 2;
780
781 /* we can enable pixel_overlap if needed by panel. In this
782 * case we need to increase the pixelclock for extra pixels
783 */
784 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1) {
785 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000)(((mode->vtotal * intel_dsi->pixel_overlap * 60) + ((1000
) - 1)) / (1000));
786 }
787 }
788
789 /* Burst Mode Ratio
790 * Target ddr frequency from VBT / non burst ddr freq
791 * multiply by 100 to preserve remainder
792 */
793 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST(3 << 0)) {
794 if (mipi_config->target_burst_mode_freq) {
795 u32 bitrate = intel_dsi_bitrate(intel_dsi);
796
797 /*
798 * Sometimes the VBT contains a slightly lower clock,
799 * then the bitrate we have calculated, in this case
800 * just replace it with the calculated bitrate.
801 */
802 if (mipi_config->target_burst_mode_freq < bitrate &&
803 intel_fuzzy_clock_check(
804 mipi_config->target_burst_mode_freq,
805 bitrate))
806 mipi_config->target_burst_mode_freq = bitrate;
807
808 if (mipi_config->target_burst_mode_freq < bitrate) {
809 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode freq is less than computed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
810 "Burst mode freq is less than computed\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode freq is less than computed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
811 return false0;
812 }
813
814 burst_mode_ratio = DIV_ROUND_UP((((mipi_config->target_burst_mode_freq * 100) + ((bitrate)
- 1)) / (bitrate))
815 mipi_config->target_burst_mode_freq * 100,(((mipi_config->target_burst_mode_freq * 100) + ((bitrate)
- 1)) / (bitrate))
816 bitrate)(((mipi_config->target_burst_mode_freq * 100) + ((bitrate)
- 1)) / (bitrate));
817
818 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100)(((intel_dsi->pclk * burst_mode_ratio) + ((100) - 1)) / (100
));
819 } else {
820 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode target is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
821 "Burst mode target is not set\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Burst mode target is not set\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
822 return false0;
823 }
824 } else
825 burst_mode_ratio = 100;
826
827 intel_dsi->burst_mode_ratio = burst_mode_ratio;
828
829 /* delays in VBT are in unit of 100us, so need to convert
830 * here in ms
831 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */
832 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10;
833 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10;
834 intel_dsi->panel_on_delay = pps->panel_on_delay / 10;
835 intel_dsi->panel_off_delay = pps->panel_off_delay / 10;
836 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10;
837
838 intel_dsi->i2c_bus_num = -1;
839
840 /* a regular driver would get the device in probe */
841 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
842 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device);
843 }
844
845 return true1;
846}
847
848#ifdef notyet
849
850/*
851 * On some BYT/CHT devs some sequences are incomplete and we need to manually
852 * control some GPIOs. We need to add a GPIO lookup table before we get these.
853 * If the GOP did not initialize the panel (HDMI inserted) we may need to also
854 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM.
855 */
856static struct gpiod_lookup_table pmic_panel_gpio_table = {
857 /* Intel GFX is consumer */
858 .dev_id = "0000:00:02.0",
859 .table = {
860 /* Panel EN/DISABLE */
861 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH),
862 { }
863 },
864};
865
866static struct gpiod_lookup_table soc_panel_gpio_table = {
867 .dev_id = "0000:00:02.0",
868 .table = {
869 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH),
870 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH),
871 { }
872 },
873};
874
875static const struct pinctrl_map soc_pwm_pinctrl_map[] = {
876 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00",
877 "pwm0_grp", "pwm"),
878};
879
880#endif /* notyet */
881
882void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool_Bool panel_is_on)
883{
884 STUB()do { printf("%s: stub\n", __func__); } while(0);
885#ifdef notyet
886 struct drm_device *dev = intel_dsi->base.base.dev;
887 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
888 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
889 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
890 bool_Bool want_backlight_gpio = false0;
891 bool_Bool want_panel_gpio = false0;
892 struct pinctrl *pinctrl;
893 int ret;
894
895 if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) &&
896 mipi_config->pwm_blc == PPS_BLC_PMIC0) {
897 gpiod_add_lookup_table(&pmic_panel_gpio_table);
898 want_panel_gpio = true1;
899 }
900
901 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && mipi_config->pwm_blc == PPS_BLC_SOC1) {
902 gpiod_add_lookup_table(&soc_panel_gpio_table);
903 want_panel_gpio = true1;
904 want_backlight_gpio = true1;
905
906 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */
907 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map,
908 ARRAY_SIZE(soc_pwm_pinctrl_map)(sizeof((soc_pwm_pinctrl_map)) / sizeof((soc_pwm_pinctrl_map)
[0])));
909 if (ret)
910 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register pwm0 pinmux mapping\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
911 "Failed to register pwm0 pinmux mapping\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register pwm0 pinmux mapping\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
912
913 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0");
914 if (IS_ERR(pinctrl))
915 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to set pinmux to PWM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
916 "Failed to set pinmux to PWM\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to set pinmux to PWM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
917 }
918
919 if (want_panel_gpio) {
920 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags);
921 if (IS_ERR(intel_dsi->gpio_panel)) {
922 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for panel control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
923 "Failed to own gpio for panel control\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for panel control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
924 intel_dsi->gpio_panel = NULL((void *)0);
925 }
926 }
927
928 if (want_backlight_gpio) {
929 intel_dsi->gpio_backlight =
930 gpiod_get(dev->dev, "backlight", flags);
931 if (IS_ERR(intel_dsi->gpio_backlight)) {
932 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for backlight control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
933 "Failed to own gpio for backlight control\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to own gpio for backlight control\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
934 intel_dsi->gpio_backlight = NULL((void *)0);
935 }
936 }
937#endif
938}
939
940void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi)
941{
942 STUB()do { printf("%s: stub\n", __func__); } while(0);
943#ifdef notyet
944 struct drm_device *dev = intel_dsi->base.base.dev;
945 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
946 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config;
947
948 if (intel_dsi->gpio_panel) {
949 gpiod_put(intel_dsi->gpio_panel);
950 intel_dsi->gpio_panel = NULL((void *)0);
951 }
952
953 if (intel_dsi->gpio_backlight) {
954 gpiod_put(intel_dsi->gpio_backlight);
955 intel_dsi->gpio_backlight = NULL((void *)0);
956 }
957
958 if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) &&
959 mipi_config->pwm_blc == PPS_BLC_PMIC0)
960 gpiod_remove_lookup_table(&pmic_panel_gpio_table);
961
962 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && mipi_config->pwm_blc == PPS_BLC_SOC1) {
963 pinctrl_unregister_mappings(soc_pwm_pinctrl_map);
964 gpiod_remove_lookup_table(&soc_panel_gpio_table);
965 }
966#endif
967}