File: | dev/pci/drm/radeon/r420.c |
Warning: | line 113, column 2 Value stored to 'tmp' is never read |
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1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
3 | * Copyright 2008 Red Hat Inc. |
4 | * Copyright 2009 Jerome Glisse. |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), |
8 | * to deal in the Software without restriction, including without limitation |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
10 | * and/or sell copies of the Software, and to permit persons to whom the |
11 | * Software is furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
22 | * OTHER DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: Dave Airlie |
25 | * Alex Deucher |
26 | * Jerome Glisse |
27 | */ |
28 | |
29 | #include <linux/pci.h> |
30 | #include <linux/seq_file.h> |
31 | #include <linux/slab.h> |
32 | |
33 | #include <drm/drm_debugfs.h> |
34 | #include <drm/drm_device.h> |
35 | #include <drm/drm_file.h> |
36 | |
37 | #include "atom.h" |
38 | #include "r100d.h" |
39 | #include "r420_reg_safe.h" |
40 | #include "r420d.h" |
41 | #include "radeon.h" |
42 | #include "radeon_asic.h" |
43 | #include "radeon_reg.h" |
44 | |
45 | void r420_pm_init_profile(struct radeon_device *rdev) |
46 | { |
47 | /* default */ |
48 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index; |
49 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
50 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0; |
51 | rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 0; |
52 | /* low sh */ |
53 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = 0; |
54 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = 0; |
55 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0; |
56 | rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0; |
57 | /* mid sh */ |
58 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = 0; |
59 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = 1; |
60 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0; |
61 | rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 0; |
62 | /* high sh */ |
63 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = 0; |
64 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
65 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0; |
66 | rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 0; |
67 | /* low mh */ |
68 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = 0; |
69 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
70 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0; |
71 | rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0; |
72 | /* mid mh */ |
73 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = 0; |
74 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
75 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0; |
76 | rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 0; |
77 | /* high mh */ |
78 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = 0; |
79 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = rdev->pm.default_power_state_index; |
80 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0; |
81 | rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 0; |
82 | } |
83 | |
84 | static void r420_set_reg_safe(struct radeon_device *rdev) |
85 | { |
86 | rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; |
87 | rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm)(sizeof((r420_reg_safe_bm)) / sizeof((r420_reg_safe_bm)[0])); |
88 | } |
89 | |
90 | void r420_pipes_init(struct radeon_device *rdev) |
91 | { |
92 | unsigned tmp; |
93 | unsigned gb_pipe_select; |
94 | unsigned num_pipes; |
95 | |
96 | /* GA_ENHANCE workaround TCL deadlock issue */ |
97 | WREG32(R300_GA_ENHANCE, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL |r100_mm_wreg(rdev, (0x4274), ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)), 0) |
98 | (1 << 2) | (1 << 3))r100_mm_wreg(rdev, (0x4274), ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)), 0); |
99 | /* add idle wait as per freedesktop.org bug 24041 */ |
100 | if (r100_gui_wait_for_idle(rdev)) { |
101 | pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while programming pipes. Bad things might happen.\n" ); |
102 | } |
103 | /* get max number of pipes */ |
104 | gb_pipe_select = RREG32(R400_GB_PIPE_SELECT)r100_mm_rreg(rdev, (0x402c), 0); |
105 | num_pipes = ((gb_pipe_select >> 12) & 3) + 1; |
106 | |
107 | /* SE chips have 1 pipe */ |
108 | if ((rdev->pdev->device == 0x5e4c) || |
109 | (rdev->pdev->device == 0x5e4f)) |
110 | num_pipes = 1; |
111 | |
112 | rdev->num_gb_pipes = num_pipes; |
113 | tmp = 0; |
Value stored to 'tmp' is never read | |
114 | switch (num_pipes) { |
115 | default: |
116 | /* force to 1 pipe */ |
117 | num_pipes = 1; |
118 | fallthroughdo {} while (0); |
119 | case 1: |
120 | tmp = (0 << 1); |
121 | break; |
122 | case 2: |
123 | tmp = (3 << 1); |
124 | break; |
125 | case 3: |
126 | tmp = (6 << 1); |
127 | break; |
128 | case 4: |
129 | tmp = (7 << 1); |
130 | break; |
131 | } |
132 | WREG32(R500_SU_REG_DEST, (1 << num_pipes) - 1)r100_mm_wreg(rdev, (0x42c8), ((1 << num_pipes) - 1), 0); |
133 | /* Sub pixel 1/12 so we can have 4K rendering according to doc */ |
134 | tmp |= R300_TILE_SIZE_16(1 << 4) | R300_ENABLE_TILING(1 << 0); |
135 | WREG32(R300_GB_TILE_CONFIG, tmp)r100_mm_wreg(rdev, (0x4018), (tmp), 0); |
136 | if (r100_gui_wait_for_idle(rdev)) { |
137 | pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while programming pipes. Bad things might happen.\n" ); |
138 | } |
139 | |
140 | tmp = RREG32(R300_DST_PIPE_CONFIG)r100_mm_rreg(rdev, (0x170c), 0); |
141 | WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG)r100_mm_wreg(rdev, (0x170c), (tmp | (1 << 31)), 0); |
142 | |
143 | WREG32(R300_RB2D_DSTCACHE_MODE,r100_mm_wreg(rdev, (0x3428), (r100_mm_rreg(rdev, (0x3428), 0) | (1 << 8) | (1 << 17)), 0) |
144 | RREG32(R300_RB2D_DSTCACHE_MODE) |r100_mm_wreg(rdev, (0x3428), (r100_mm_rreg(rdev, (0x3428), 0) | (1 << 8) | (1 << 17)), 0) |
145 | R300_DC_AUTOFLUSH_ENABLE |r100_mm_wreg(rdev, (0x3428), (r100_mm_rreg(rdev, (0x3428), 0) | (1 << 8) | (1 << 17)), 0) |
146 | R300_DC_DC_DISABLE_IGNORE_PE)r100_mm_wreg(rdev, (0x3428), (r100_mm_rreg(rdev, (0x3428), 0) | (1 << 8) | (1 << 17)), 0); |
147 | |
148 | if (r100_gui_wait_for_idle(rdev)) { |
149 | pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while programming pipes. Bad things might happen.\n" ); |
150 | } |
151 | |
152 | if (rdev->family == CHIP_RV530) { |
153 | tmp = RREG32(RV530_GB_PIPE_SELECT2)r100_mm_rreg(rdev, (0x4124), 0); |
154 | if ((tmp & 3) == 3) |
155 | rdev->num_z_pipes = 2; |
156 | else |
157 | rdev->num_z_pipes = 1; |
158 | } else |
159 | rdev->num_z_pipes = 1; |
160 | |
161 | DRM_INFO("radeon: %d quad pipes, %d z pipes initialized.\n",printk("\0016" "[" "drm" "] " "radeon: %d quad pipes, %d z pipes initialized.\n" , rdev->num_gb_pipes, rdev->num_z_pipes) |
162 | rdev->num_gb_pipes, rdev->num_z_pipes)printk("\0016" "[" "drm" "] " "radeon: %d quad pipes, %d z pipes initialized.\n" , rdev->num_gb_pipes, rdev->num_z_pipes); |
163 | } |
164 | |
165 | u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) |
166 | { |
167 | unsigned long flags; |
168 | u32 r; |
169 | |
170 | spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while (0); |
171 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg))r100_mm_wreg(rdev, (0x0001F8), ((((reg) & 0x7F) << 0 )), 0); |
172 | r = RREG32(R_0001FC_MC_IND_DATA)r100_mm_rreg(rdev, (0x0001FC), 0); |
173 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while (0); |
174 | return r; |
175 | } |
176 | |
177 | void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
178 | { |
179 | unsigned long flags; |
180 | |
181 | spin_lock_irqsave(&rdev->mc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mc_idx_lock); } while (0); |
182 | WREG32(R_0001F8_MC_IND_INDEX, S_0001F8_MC_IND_ADDR(reg) |r100_mm_wreg(rdev, (0x0001F8), ((((reg) & 0x7F) << 0 ) | (((1) & 0x1) << 8)), 0) |
183 | S_0001F8_MC_IND_WR_EN(1))r100_mm_wreg(rdev, (0x0001F8), ((((reg) & 0x7F) << 0 ) | (((1) & 0x1) << 8)), 0); |
184 | WREG32(R_0001FC_MC_IND_DATA, v)r100_mm_wreg(rdev, (0x0001FC), (v), 0); |
185 | spin_unlock_irqrestore(&rdev->mc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mc_idx_lock); } while (0); |
186 | } |
187 | |
188 | static void r420_debugfs(struct radeon_device *rdev) |
189 | { |
190 | if (r100_debugfs_rbbm_init(rdev)) { |
191 | DRM_ERROR("Failed to register debugfs file for RBBM !\n")__drm_err("Failed to register debugfs file for RBBM !\n"); |
192 | } |
193 | if (r420_debugfs_pipes_info_init(rdev)) { |
194 | DRM_ERROR("Failed to register debugfs file for pipes !\n")__drm_err("Failed to register debugfs file for pipes !\n"); |
195 | } |
196 | } |
197 | |
198 | static void r420_clock_resume(struct radeon_device *rdev) |
199 | { |
200 | u32 sclk_cntl; |
201 | |
202 | if (radeon_dynclks != -1 && radeon_dynclks) |
203 | radeon_atom_set_clock_gating(rdev, 1); |
204 | sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL)rdev->pll_rreg(rdev, (0x00000D)); |
205 | sclk_cntl |= S_00000D_FORCE_CP(1)(((1) & 0x1) << 16) | S_00000D_FORCE_VIP(1)(((1) & 0x1) << 23); |
206 | if (rdev->family == CHIP_R420) |
207 | sclk_cntl |= S_00000D_FORCE_PX(1)(((1) & 0x1) << 26) | S_00000D_FORCE_TX(1)(((1) & 0x1) << 27); |
208 | WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl)rdev->pll_wreg(rdev, (0x00000D), (sclk_cntl)); |
209 | } |
210 | |
211 | static void r420_cp_errata_init(struct radeon_device *rdev) |
212 | { |
213 | int r; |
214 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0]; |
215 | |
216 | /* RV410 and R420 can lock up if CP DMA to host memory happens |
217 | * while the 2D engine is busy. |
218 | * |
219 | * The proper workaround is to queue a RESYNC at the beginning |
220 | * of the CP init, apparently. |
221 | */ |
222 | radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); |
223 | r = radeon_ring_lock(rdev, ring, 8); |
224 | WARN_ON(r)({ int __ret = !!(r); if (__ret) printf("WARNING %s failed at %s:%d\n" , "r", "/usr/src/sys/dev/pci/drm/radeon/r420.c", 224); __builtin_expect (!!(__ret), 0); }); |
225 | radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1)(0x00000000 | ((((0x778) >> 2) << 0) & (0x1ffff << 0)) | ((((1)) << 16) & (0x3fff << 16 )))); |
226 | radeon_ring_write(ring, rdev->config.r300.resync_scratch); |
227 | radeon_ring_write(ring, 0xDEADBEEF); |
228 | radeon_ring_unlock_commit(rdev, ring, false0); |
229 | } |
230 | |
231 | static void r420_cp_errata_fini(struct radeon_device *rdev) |
232 | { |
233 | int r; |
234 | struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0]; |
235 | |
236 | /* Catch the RESYNC we dispatched all the way back, |
237 | * at the very beginning of the CP init. |
238 | */ |
239 | r = radeon_ring_lock(rdev, ring, 8); |
240 | WARN_ON(r)({ int __ret = !!(r); if (__ret) printf("WARNING %s failed at %s:%d\n" , "r", "/usr/src/sys/dev/pci/drm/radeon/r420.c", 240); __builtin_expect (!!(__ret), 0); }); |
241 | radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)(0x00000000 | ((((0x4e4c) >> 2) << 0) & (0x1ffff << 0)) | ((((0)) << 16) & (0x3fff << 16 )))); |
242 | radeon_ring_write(ring, R300_RB3D_DC_FINISH(1 << 4)); |
243 | radeon_ring_unlock_commit(rdev, ring, false0); |
244 | radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); |
245 | } |
246 | |
247 | static int r420_startup(struct radeon_device *rdev) |
248 | { |
249 | int r; |
250 | |
251 | /* set common regs */ |
252 | r100_set_common_regs(rdev); |
253 | /* program mc */ |
254 | r300_mc_program(rdev); |
255 | /* Resume clock */ |
256 | r420_clock_resume(rdev); |
257 | /* Initialize GART (initialize after TTM so we can allocate |
258 | * memory through TTM but finalize after TTM) */ |
259 | if (rdev->flags & RADEON_IS_PCIE) { |
260 | r = rv370_pcie_gart_enable(rdev); |
261 | if (r) |
262 | return r; |
263 | } |
264 | if (rdev->flags & RADEON_IS_PCI) { |
265 | r = r100_pci_gart_enable(rdev); |
266 | if (r) |
267 | return r; |
268 | } |
269 | r420_pipes_init(rdev); |
270 | |
271 | /* allocate wb buffer */ |
272 | r = radeon_wb_init(rdev); |
273 | if (r) |
274 | return r; |
275 | |
276 | r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX0); |
277 | if (r) { |
278 | dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
279 | return r; |
280 | } |
281 | |
282 | /* Enable IRQ */ |
283 | if (!rdev->irq.installed) { |
284 | r = radeon_irq_kms_init(rdev); |
285 | if (r) |
286 | return r; |
287 | } |
288 | |
289 | r100_irq_set(rdev); |
290 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x0130), 0); |
291 | /* 1M ring buffer */ |
292 | r = r100_cp_init(rdev, 1024 * 1024); |
293 | if (r) { |
294 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP (%d).\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
295 | return r; |
296 | } |
297 | r420_cp_errata_init(rdev); |
298 | |
299 | r = radeon_ib_pool_init(rdev); |
300 | if (r) { |
301 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "IB initialization failed (%d).\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
302 | return r; |
303 | } |
304 | |
305 | return 0; |
306 | } |
307 | |
308 | int r420_resume(struct radeon_device *rdev) |
309 | { |
310 | int r; |
311 | |
312 | /* Make sur GART are not working */ |
313 | if (rdev->flags & RADEON_IS_PCIE) |
314 | rv370_pcie_gart_disable(rdev); |
315 | if (rdev->flags & RADEON_IS_PCI) |
316 | r100_pci_gart_disable(rdev); |
317 | /* Resume clock before doing reset */ |
318 | r420_clock_resume(rdev); |
319 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
320 | if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) { |
321 | dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)) |
322 | RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)) |
323 | RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)); |
324 | } |
325 | /* check if cards are posted or not */ |
326 | if (rdev->is_atom_bios) { |
327 | atom_asic_init(rdev->mode_info.atom_context); |
328 | } else { |
329 | radeon_combios_asic_init(rdev->ddev); |
330 | } |
331 | /* Resume clock after posting */ |
332 | r420_clock_resume(rdev); |
333 | /* Initialize surface registers */ |
334 | radeon_surface_init(rdev); |
335 | |
336 | rdev->accel_working = true1; |
337 | r = r420_startup(rdev); |
338 | if (r) { |
339 | rdev->accel_working = false0; |
340 | } |
341 | return r; |
342 | } |
343 | |
344 | int r420_suspend(struct radeon_device *rdev) |
345 | { |
346 | radeon_pm_suspend(rdev); |
347 | r420_cp_errata_fini(rdev); |
348 | r100_cp_disable(rdev); |
349 | radeon_wb_disable(rdev); |
350 | r100_irq_disable(rdev); |
351 | if (rdev->flags & RADEON_IS_PCIE) |
352 | rv370_pcie_gart_disable(rdev); |
353 | if (rdev->flags & RADEON_IS_PCI) |
354 | r100_pci_gart_disable(rdev); |
355 | return 0; |
356 | } |
357 | |
358 | void r420_fini(struct radeon_device *rdev) |
359 | { |
360 | radeon_pm_fini(rdev); |
361 | r100_cp_fini(rdev); |
362 | radeon_wb_fini(rdev); |
363 | radeon_ib_pool_fini(rdev); |
364 | radeon_gem_fini(rdev); |
365 | if (rdev->flags & RADEON_IS_PCIE) |
366 | rv370_pcie_gart_fini(rdev); |
367 | if (rdev->flags & RADEON_IS_PCI) |
368 | r100_pci_gart_fini(rdev); |
369 | radeon_agp_fini(rdev); |
370 | radeon_irq_kms_fini(rdev); |
371 | radeon_fence_driver_fini(rdev); |
372 | radeon_bo_fini(rdev); |
373 | if (rdev->is_atom_bios) { |
374 | radeon_atombios_fini(rdev); |
375 | } else { |
376 | radeon_combios_fini(rdev); |
377 | } |
378 | kfree(rdev->bios); |
379 | rdev->bios = NULL((void *)0); |
380 | } |
381 | |
382 | int r420_init(struct radeon_device *rdev) |
383 | { |
384 | int r; |
385 | |
386 | /* Initialize scratch registers */ |
387 | radeon_scratch_init(rdev); |
388 | /* Initialize surface registers */ |
389 | radeon_surface_init(rdev); |
390 | /* TODO: disable VGA need to use VGA request */ |
391 | /* restore some register to sane defaults */ |
392 | r100_restore_sanity(rdev); |
393 | /* BIOS*/ |
394 | if (!radeon_get_bios(rdev)) { |
395 | if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600))) |
396 | return -EINVAL22; |
397 | } |
398 | if (rdev->is_atom_bios) { |
399 | r = radeon_atombios_init(rdev); |
400 | if (r) { |
401 | return r; |
402 | } |
403 | } else { |
404 | r = radeon_combios_init(rdev); |
405 | if (r) { |
406 | return r; |
407 | } |
408 | } |
409 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
410 | if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) { |
411 | dev_warn(rdev->dev,printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)) |
412 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)) |
413 | RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)) |
414 | RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg (rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0)); |
415 | } |
416 | /* check if cards are posted or not */ |
417 | if (radeon_boot_test_post_card(rdev) == false0) |
418 | return -EINVAL22; |
419 | |
420 | /* Initialize clocks */ |
421 | radeon_get_clock_info(rdev->ddev); |
422 | /* initialize AGP */ |
423 | if (rdev->flags & RADEON_IS_AGP) { |
424 | r = radeon_agp_init(rdev); |
425 | if (r) { |
426 | radeon_agp_disable(rdev); |
427 | } |
428 | } |
429 | /* initialize memory controller */ |
430 | r300_mc_init(rdev); |
431 | r420_debugfs(rdev); |
432 | /* Fence driver */ |
433 | r = radeon_fence_driver_init(rdev); |
434 | if (r) { |
435 | return r; |
436 | } |
437 | /* Memory manager */ |
438 | r = radeon_bo_init(rdev); |
439 | if (r) { |
440 | return r; |
441 | } |
442 | if (rdev->family == CHIP_R420) |
443 | r100_enable_bm(rdev); |
444 | |
445 | if (rdev->flags & RADEON_IS_PCIE) { |
446 | r = rv370_pcie_gart_init(rdev); |
447 | if (r) |
448 | return r; |
449 | } |
450 | if (rdev->flags & RADEON_IS_PCI) { |
451 | r = r100_pci_gart_init(rdev); |
452 | if (r) |
453 | return r; |
454 | } |
455 | r420_set_reg_safe(rdev); |
456 | |
457 | /* Initialize power management */ |
458 | radeon_pm_init(rdev); |
459 | |
460 | rdev->accel_working = true1; |
461 | r = r420_startup(rdev); |
462 | if (r) { |
463 | /* Somethings want wront with the accel init stop accel */ |
464 | dev_err(rdev->dev, "Disabling GPU acceleration\n")printf("drm:pid%d:%s *ERROR* " "Disabling GPU acceleration\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
465 | r100_cp_fini(rdev); |
466 | radeon_wb_fini(rdev); |
467 | radeon_ib_pool_fini(rdev); |
468 | radeon_irq_kms_fini(rdev); |
469 | if (rdev->flags & RADEON_IS_PCIE) |
470 | rv370_pcie_gart_fini(rdev); |
471 | if (rdev->flags & RADEON_IS_PCI) |
472 | r100_pci_gart_fini(rdev); |
473 | radeon_agp_fini(rdev); |
474 | rdev->accel_working = false0; |
475 | } |
476 | return 0; |
477 | } |
478 | |
479 | /* |
480 | * Debugfs info |
481 | */ |
482 | #if defined(CONFIG_DEBUG_FS) |
483 | static int r420_debugfs_pipes_info(struct seq_file *m, void *data) |
484 | { |
485 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
486 | struct drm_device *dev = node->minor->dev; |
487 | struct radeon_device *rdev = dev->dev_private; |
488 | uint32_t tmp; |
489 | |
490 | tmp = RREG32(R400_GB_PIPE_SELECT)r100_mm_rreg(rdev, (0x402c), 0); |
491 | seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp); |
492 | tmp = RREG32(R300_GB_TILE_CONFIG)r100_mm_rreg(rdev, (0x4018), 0); |
493 | seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp); |
494 | tmp = RREG32(R300_DST_PIPE_CONFIG)r100_mm_rreg(rdev, (0x170c), 0); |
495 | seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp); |
496 | return 0; |
497 | } |
498 | |
499 | static struct drm_info_list r420_pipes_info_list[] = { |
500 | {"r420_pipes_info", r420_debugfs_pipes_info, 0, NULL((void *)0)}, |
501 | }; |
502 | #endif |
503 | |
504 | int r420_debugfs_pipes_info_init(struct radeon_device *rdev) |
505 | { |
506 | #if defined(CONFIG_DEBUG_FS) |
507 | return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); |
508 | #else |
509 | return 0; |
510 | #endif |
511 | } |