Bug Summary

File:dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
Warning:line 58, column 2
Value stored to 'pwm_period_cntl' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name dce_panel_cntl.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dce/dce_panel_cntl.c
1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "reg_helper.h"
27#include "core_types.h"
28#include "dc_dmub_srv.h"
29#include "panel_cntl.h"
30#include "dce_panel_cntl.h"
31#include "atom.h"
32
33#define TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );})\
34 container_of(panel_cntl, struct dce_panel_cntl, base)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );})
35
36#define CTXdce_panel_cntl->base.ctx \
37 dce_panel_cntl->base.ctx
38
39#define DC_LOGGERdce_panel_cntl->base.ctx->logger \
40 dce_panel_cntl->base.ctx->logger
41
42#define REG(reg)dce_panel_cntl->regs->reg\
43 dce_panel_cntl->regs->reg
44
45#undef FN
46#define FN(reg_name, field_name)dce_panel_cntl->shift->field_name, dce_panel_cntl->mask
->field_name \
47 dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
48
49static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
50{
51 uint64_t current_backlight;
52 uint32_t round_result;
53 uint32_t pwm_period_cntl, bl_period, bl_int_count;
54 uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
55 uint32_t bl_period_mask, bl_pwm_mask;
56 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );});
57
58 pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, __func__);
Value stored to 'pwm_period_cntl' is never read
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, dce_panel_cntl->shift->BL_PWM_PERIOD
, dce_panel_cntl->mask->BL_PWM_PERIOD, &bl_period);
60 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, dce_panel_cntl->shift->BL_PWM_PERIOD_BITCNT
, dce_panel_cntl->mask->BL_PWM_PERIOD_BITCNT, &bl_int_count
);
61
62 bl_pwm_cntl = REG_READ(BL_PWM_CNTL)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL, __func__);
63 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm))generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL, dce_panel_cntl->shift->BL_ACTIVE_INT_FRAC_CNT
, dce_panel_cntl->mask->BL_ACTIVE_INT_FRAC_CNT, (uint32_t
*)(&bl_pwm));
64 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL, dce_panel_cntl->shift->BL_PWM_FRACTIONAL_EN
, dce_panel_cntl->mask->BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en
);
65
66 if (bl_int_count == 0)
67 bl_int_count = 16;
68
69 bl_period_mask = (1 << bl_int_count) - 1;
70 bl_period &= bl_period_mask;
71
72 bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
73
74 if (fractional_duty_cycle_en == 0)
75 bl_pwm &= bl_pwm_mask;
76 else
77 bl_pwm &= 0xFFFF;
78
79 current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count);
80
81 if (bl_period == 0)
82 bl_period = 0xFFFF;
83
84 current_backlight = div_u64(current_backlight, bl_period);
85 current_backlight = (current_backlight + 1) >> 1;
86
87 current_backlight = (uint64_t)(current_backlight) * bl_period;
88
89 round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
90
91 round_result = (round_result >> (bl_int_count-1)) & 1;
92
93 current_backlight >>= bl_int_count;
94 current_backlight += round_result;
95
96 return (uint32_t)(current_backlight);
97}
98
99static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
100{
101 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );});
102 uint32_t value;
103 uint32_t current_backlight;
104
105 /* It must not be 0, so we have to restore them
106 * Bios bug w/a - period resets to zero,
107 * restoring to cache values which is always correct
108 */
109 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL, dce_panel_cntl->shift->BL_ACTIVE_INT_FRAC_CNT
, dce_panel_cntl->mask->BL_ACTIVE_INT_FRAC_CNT, &value
);
110
111 if (value == 0 || value == 1) {
112 if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
113 REG_WRITE(BL_PWM_CNTL,dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL, panel_cntl->stored_backlight_registers
.BL_PWM_CNTL, __func__)
114 panel_cntl->stored_backlight_registers.BL_PWM_CNTL)dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL, panel_cntl->stored_backlight_registers
.BL_PWM_CNTL, __func__);
115 REG_WRITE(BL_PWM_CNTL2,dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL2, panel_cntl->stored_backlight_registers
.BL_PWM_CNTL2, __func__)
116 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2)dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL2, panel_cntl->stored_backlight_registers
.BL_PWM_CNTL2, __func__);
117 REG_WRITE(BL_PWM_PERIOD_CNTL,dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_PERIOD_CNTL, panel_cntl->stored_backlight_registers
.BL_PWM_PERIOD_CNTL, __func__)
118 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL)dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_PERIOD_CNTL, panel_cntl->stored_backlight_registers
.BL_PWM_PERIOD_CNTL, __func__);
119 REG_UPDATE(PWRSEQ_REF_DIV,generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->PWRSEQ_REF_DIV, 1, dce_panel_cntl->shift->
BL_PWM_REF_DIV, dce_panel_cntl->mask->BL_PWM_REF_DIV, panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
)
120 BL_PWM_REF_DIV,generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->PWRSEQ_REF_DIV, 1, dce_panel_cntl->shift->
BL_PWM_REF_DIV, dce_panel_cntl->mask->BL_PWM_REF_DIV, panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
)
121 panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV)generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->PWRSEQ_REF_DIV, 1, dce_panel_cntl->shift->
BL_PWM_REF_DIV, dce_panel_cntl->mask->BL_PWM_REF_DIV, panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
);
122 } else {
123 /* TODO: Note: This should not really happen since VBIOS
124 * should have initialized PWM registers on boot.
125 */
126 REG_WRITE(BL_PWM_CNTL, 0xC000FA00)dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL, 0xC000FA00, __func__);
127 REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0)dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_PERIOD_CNTL, 0x000C0FA0, __func__);
128 }
129 } else {
130 panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
131 REG_READ(BL_PWM_CNTL)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL, __func__);
132 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
133 REG_READ(BL_PWM_CNTL2)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL2, __func__);
134 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
135 REG_READ(BL_PWM_PERIOD_CNTL)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, __func__);
136
137 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_REF_DIV, dce_panel_cntl->shift->BL_PWM_REF_DIV
, dce_panel_cntl->mask->BL_PWM_REF_DIV, &panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
)
138 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_REF_DIV, dce_panel_cntl->shift->BL_PWM_REF_DIV
, dce_panel_cntl->mask->BL_PWM_REF_DIV, &panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
);
139 }
140
141 // Have driver take backlight control
142 // TakeBacklightControl(true)
143 value = REG_READ(BIOS_SCRATCH_2)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BIOS_SCRATCH_2, __func__);
144 value |= ATOM_S2_VRI_BRIGHT_ENABLE0x20000000L;
145 REG_WRITE(BIOS_SCRATCH_2, value)dm_write_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BIOS_SCRATCH_2, value, __func__);
146
147 // Enable the backlight output
148 REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1)generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL, 1, dce_panel_cntl->shift->BL_PWM_EN
, dce_panel_cntl->mask->BL_PWM_EN, 1);
149
150 // Unlock group 2 backlight registers
151 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 1, dce_panel_cntl->shift
->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 0)
152 BL_PWM_GRP1_REG_LOCK, 0)generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 1, dce_panel_cntl->shift
->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 0);
153
154 current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
155
156 return current_backlight;
157}
158
159static bool_Bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
160{
161 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );});
162 uint32_t blon, blon_ovrd, pwrseq_target_state;
163
164 REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd)generic_reg_get2(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_CNTL, dce_panel_cntl->shift->LVTMA_BLON
, dce_panel_cntl->mask->LVTMA_BLON, &blon, dce_panel_cntl
->shift->LVTMA_BLON_OVRD, dce_panel_cntl->mask->LVTMA_BLON_OVRD
, &blon_ovrd);
165 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_CNTL, dce_panel_cntl->shift->LVTMA_PWRSEQ_TARGET_STATE
, dce_panel_cntl->mask->LVTMA_PWRSEQ_TARGET_STATE, &
pwrseq_target_state);
166
167 if (blon_ovrd)
168 return blon;
169 else
170 return pwrseq_target_state;
171}
172
173static bool_Bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
174{
175 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );});
176 uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
177
178 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_STATE, dce_panel_cntl->shift->LVTMA_PWRSEQ_TARGET_STATE_R
, dce_panel_cntl->mask->LVTMA_PWRSEQ_TARGET_STATE_R, &
pwr_seq_state);
179
180 REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd)generic_reg_get2(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_CNTL, dce_panel_cntl->shift->LVTMA_DIGON
, dce_panel_cntl->mask->LVTMA_DIGON, &dig_on, dce_panel_cntl
->shift->LVTMA_DIGON_OVRD, dce_panel_cntl->mask->
LVTMA_DIGON_OVRD, &dig_on_ovrd);
181
182 return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
183}
184
185static void dce_store_backlight_level(struct panel_cntl *panel_cntl)
186{
187 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );});
188
189 panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
190 REG_READ(BL_PWM_CNTL)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL, __func__);
191 panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
192 REG_READ(BL_PWM_CNTL2)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_CNTL2, __func__);
193 panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
194 REG_READ(BL_PWM_PERIOD_CNTL)dm_read_reg_func(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, __func__);
195
196 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_REF_DIV, dce_panel_cntl->shift->BL_PWM_REF_DIV
, dce_panel_cntl->mask->BL_PWM_REF_DIV, &panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
)
197 &panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV)generic_reg_get(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->PWRSEQ_REF_DIV, dce_panel_cntl->shift->BL_PWM_REF_DIV
, dce_panel_cntl->mask->BL_PWM_REF_DIV, &panel_cntl
->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV
);
198}
199
200static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
201 uint32_t backlight_pwm_u16_16)
202{
203 uint32_t backlight_16bit;
204 uint32_t masked_pwm_period;
205 uint8_t bit_count;
206 uint64_t active_duty_cycle;
207 uint32_t pwm_period_bitcnt;
208 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr - __builtin_offsetof
(struct dce_panel_cntl, base) );});
209
210 /*
211 * 1. Find 16 bit backlight active duty cycle, where 0 <= backlight
212 * active duty cycle <= backlight period
213 */
214
215 /* 1.1 Apply bitmask for backlight period value based on value of BITCNT
216 */
217 REG_GET_2(BL_PWM_PERIOD_CNTL,generic_reg_get2(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, dce_panel_cntl->shift->BL_PWM_PERIOD_BITCNT
, dce_panel_cntl->mask->BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt
, dce_panel_cntl->shift->BL_PWM_PERIOD, dce_panel_cntl->
mask->BL_PWM_PERIOD, &masked_pwm_period)
218 BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,generic_reg_get2(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, dce_panel_cntl->shift->BL_PWM_PERIOD_BITCNT
, dce_panel_cntl->mask->BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt
, dce_panel_cntl->shift->BL_PWM_PERIOD, dce_panel_cntl->
mask->BL_PWM_PERIOD, &masked_pwm_period)
219 BL_PWM_PERIOD, &masked_pwm_period)generic_reg_get2(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_PERIOD_CNTL, dce_panel_cntl->shift->BL_PWM_PERIOD_BITCNT
, dce_panel_cntl->mask->BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt
, dce_panel_cntl->shift->BL_PWM_PERIOD, dce_panel_cntl->
mask->BL_PWM_PERIOD, &masked_pwm_period);
220
221 if (pwm_period_bitcnt == 0)
222 bit_count = 16;
223 else
224 bit_count = pwm_period_bitcnt;
225
226 /* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
227 masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
228
229 /* 1.2 Calculate integer active duty cycle required upper 16 bits
230 * contain integer component, lower 16 bits contain fractional component
231 * of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
232 */
233 active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
234
235 /* 1.3 Calculate 16 bit active duty cycle from integer and fractional
236 * components shift by bitCount then mask 16 bits and add rounding bit
237 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
238 */
239 backlight_16bit = active_duty_cycle >> bit_count;
240 backlight_16bit &= 0xFFFF;
241 backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
242
243 /*
244 * 2. Program register with updated value
245 */
246
247 /* 2.1 Lock group 2 backlight registers */
248
249 REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 2, dce_panel_cntl->shift
->BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, dce_panel_cntl->mask
->BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, dce_panel_cntl->
shift->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 1)
250 BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 2, dce_panel_cntl->shift
->BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, dce_panel_cntl->mask
->BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, dce_panel_cntl->
shift->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 1)
251 BL_PWM_GRP1_REG_LOCK, 1)generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 2, dce_panel_cntl->shift
->BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, dce_panel_cntl->mask
->BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1, dce_panel_cntl->
shift->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 1);
252
253 // 2.2 Write new active duty cycle
254 REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit)generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_CNTL, 1, dce_panel_cntl->shift->BL_ACTIVE_INT_FRAC_CNT
, dce_panel_cntl->mask->BL_ACTIVE_INT_FRAC_CNT, backlight_16bit
);
255
256 /* 2.3 Unlock group 2 backlight registers */
257 REG_UPDATE(BL_PWM_GRP1_REG_LOCK,generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 1, dce_panel_cntl->shift
->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 0)
258 BL_PWM_GRP1_REG_LOCK, 0)generic_reg_update_ex(dce_panel_cntl->base.ctx, dce_panel_cntl
->regs->BL_PWM_GRP1_REG_LOCK, 1, dce_panel_cntl->shift
->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->mask->BL_PWM_GRP1_REG_LOCK
, 0);
259
260 /* 3 Wait for pending bit to be cleared */
261 REG_WAIT(BL_PWM_GRP1_REG_LOCK,generic_reg_wait(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->shift->BL_PWM_GRP1_REG_UPDATE_PENDING
, dce_panel_cntl->mask->BL_PWM_GRP1_REG_UPDATE_PENDING,
0, 1, 10000, __func__, 263)
262 BL_PWM_GRP1_REG_UPDATE_PENDING, 0,generic_reg_wait(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->shift->BL_PWM_GRP1_REG_UPDATE_PENDING
, dce_panel_cntl->mask->BL_PWM_GRP1_REG_UPDATE_PENDING,
0, 1, 10000, __func__, 263)
263 1, 10000)generic_reg_wait(dce_panel_cntl->base.ctx, dce_panel_cntl->
regs->BL_PWM_GRP1_REG_LOCK, dce_panel_cntl->shift->BL_PWM_GRP1_REG_UPDATE_PENDING
, dce_panel_cntl->mask->BL_PWM_GRP1_REG_UPDATE_PENDING,
0, 1, 10000, __func__, 263);
264}
265
266static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl)
267{
268 struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl)({ const __typeof( ((struct dce_panel_cntl *)0)->base ) *__mptr
= (*panel_cntl); (struct dce_panel_cntl *)( (char *)__mptr -
__builtin_offsetof(struct dce_panel_cntl, base) );});
269
270 kfree(dce_panel_cntl);
271 *panel_cntl = NULL((void *)0);
272}
273
274static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
275 .destroy = dce_panel_cntl_destroy,
276 .hw_init = dce_panel_cntl_hw_init,
277 .is_panel_backlight_on = dce_is_panel_backlight_on,
278 .is_panel_powered_on = dce_is_panel_powered_on,
279 .store_backlight_level = dce_store_backlight_level,
280 .driver_set_backlight = dce_driver_set_backlight,
281 .get_current_backlight = dce_get_16_bit_backlight_from_pwm,
282};
283
284void dce_panel_cntl_construct(
285 struct dce_panel_cntl *dce_panel_cntl,
286 const struct panel_cntl_init_data *init_data,
287 const struct dce_panel_cntl_registers *regs,
288 const struct dce_panel_cntl_shift *shift,
289 const struct dce_panel_cntl_mask *mask)
290{
291 struct panel_cntl *base = &dce_panel_cntl->base;
292
293 base->stored_backlight_registers.BL_PWM_CNTL = 0;
294 base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
295 base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
296 base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
297
298 dce_panel_cntl->regs = regs;
299 dce_panel_cntl->shift = shift;
300 dce_panel_cntl->mask = mask;
301
302 dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;
303 dce_panel_cntl->base.ctx = init_data->ctx;
304 dce_panel_cntl->base.inst = init_data->inst;
305}