File: | dev/pci/drm/amd/amdgpu/sdma_v3_0.c |
Warning: | line 318, column 51 Access to field 'data' results in a dereference of a null pointer (loaded from field 'fw') |
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1 | /* | ||||
2 | * Copyright 2014 Advanced Micro Devices, Inc. | ||||
3 | * | ||||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||||
5 | * copy of this software and associated documentation files (the "Software"), | ||||
6 | * to deal in the Software without restriction, including without limitation | ||||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||||
9 | * Software is furnished to do so, subject to the following conditions: | ||||
10 | * | ||||
11 | * The above copyright notice and this permission notice shall be included in | ||||
12 | * all copies or substantial portions of the Software. | ||||
13 | * | ||||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||||
21 | * | ||||
22 | * Authors: Alex Deucher | ||||
23 | */ | ||||
24 | |||||
25 | #include <linux/delay.h> | ||||
26 | #include <linux/firmware.h> | ||||
27 | #include <linux/module.h> | ||||
28 | |||||
29 | #include "amdgpu.h" | ||||
30 | #include "amdgpu_ucode.h" | ||||
31 | #include "amdgpu_trace.h" | ||||
32 | #include "vi.h" | ||||
33 | #include "vid.h" | ||||
34 | |||||
35 | #include "oss/oss_3_0_d.h" | ||||
36 | #include "oss/oss_3_0_sh_mask.h" | ||||
37 | |||||
38 | #include "gmc/gmc_8_1_d.h" | ||||
39 | #include "gmc/gmc_8_1_sh_mask.h" | ||||
40 | |||||
41 | #include "gca/gfx_8_0_d.h" | ||||
42 | #include "gca/gfx_8_0_enum.h" | ||||
43 | #include "gca/gfx_8_0_sh_mask.h" | ||||
44 | |||||
45 | #include "bif/bif_5_0_d.h" | ||||
46 | #include "bif/bif_5_0_sh_mask.h" | ||||
47 | |||||
48 | #include "tonga_sdma_pkt_open.h" | ||||
49 | |||||
50 | #include "ivsrcid/ivsrcid_vislands30.h" | ||||
51 | |||||
52 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev); | ||||
53 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev); | ||||
54 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev); | ||||
55 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev); | ||||
56 | |||||
57 | MODULE_FIRMWARE("amdgpu/tonga_sdma.bin"); | ||||
58 | MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin"); | ||||
59 | MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); | ||||
60 | MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); | ||||
61 | MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); | ||||
62 | MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); | ||||
63 | MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); | ||||
64 | MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); | ||||
65 | MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); | ||||
66 | MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); | ||||
67 | MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); | ||||
68 | MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin"); | ||||
69 | MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin"); | ||||
70 | MODULE_FIRMWARE("amdgpu/vegam_sdma.bin"); | ||||
71 | MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin"); | ||||
72 | |||||
73 | |||||
74 | static const u32 sdma_offsets[SDMA_MAX_INSTANCE2] = | ||||
75 | { | ||||
76 | SDMA0_REGISTER_OFFSET0x0, | ||||
77 | SDMA1_REGISTER_OFFSET0x200 | ||||
78 | }; | ||||
79 | |||||
80 | static const u32 golden_settings_tonga_a11[] = | ||||
81 | { | ||||
82 | mmSDMA0_CHICKEN_BITS0x3405, 0xfc910007, 0x00810007, | ||||
83 | mmSDMA0_CLK_CTRL0x3403, 0xff000fff, 0x00000000, | ||||
84 | mmSDMA0_GFX_IB_CNTL0x348a, 0x800f0111, 0x00000100, | ||||
85 | mmSDMA0_RLC0_IB_CNTL0x350a, 0x800f0111, 0x00000100, | ||||
86 | mmSDMA0_RLC1_IB_CNTL0x358a, 0x800f0111, 0x00000100, | ||||
87 | mmSDMA1_CHICKEN_BITS0x3605, 0xfc910007, 0x00810007, | ||||
88 | mmSDMA1_CLK_CTRL0x3603, 0xff000fff, 0x00000000, | ||||
89 | mmSDMA1_GFX_IB_CNTL0x368a, 0x800f0111, 0x00000100, | ||||
90 | mmSDMA1_RLC0_IB_CNTL0x370a, 0x800f0111, 0x00000100, | ||||
91 | mmSDMA1_RLC1_IB_CNTL0x378a, 0x800f0111, 0x00000100, | ||||
92 | }; | ||||
93 | |||||
94 | static const u32 tonga_mgcg_cgcg_init[] = | ||||
95 | { | ||||
96 | mmSDMA0_CLK_CTRL0x3403, 0xff000ff0, 0x00000100, | ||||
97 | mmSDMA1_CLK_CTRL0x3603, 0xff000ff0, 0x00000100 | ||||
98 | }; | ||||
99 | |||||
100 | static const u32 golden_settings_fiji_a10[] = | ||||
101 | { | ||||
102 | mmSDMA0_CHICKEN_BITS0x3405, 0xfc910007, 0x00810007, | ||||
103 | mmSDMA0_GFX_IB_CNTL0x348a, 0x800f0111, 0x00000100, | ||||
104 | mmSDMA0_RLC0_IB_CNTL0x350a, 0x800f0111, 0x00000100, | ||||
105 | mmSDMA0_RLC1_IB_CNTL0x358a, 0x800f0111, 0x00000100, | ||||
106 | mmSDMA1_CHICKEN_BITS0x3605, 0xfc910007, 0x00810007, | ||||
107 | mmSDMA1_GFX_IB_CNTL0x368a, 0x800f0111, 0x00000100, | ||||
108 | mmSDMA1_RLC0_IB_CNTL0x370a, 0x800f0111, 0x00000100, | ||||
109 | mmSDMA1_RLC1_IB_CNTL0x378a, 0x800f0111, 0x00000100, | ||||
110 | }; | ||||
111 | |||||
112 | static const u32 fiji_mgcg_cgcg_init[] = | ||||
113 | { | ||||
114 | mmSDMA0_CLK_CTRL0x3403, 0xff000ff0, 0x00000100, | ||||
115 | mmSDMA1_CLK_CTRL0x3603, 0xff000ff0, 0x00000100 | ||||
116 | }; | ||||
117 | |||||
118 | static const u32 golden_settings_polaris11_a11[] = | ||||
119 | { | ||||
120 | mmSDMA0_CHICKEN_BITS0x3405, 0xfc910007, 0x00810007, | ||||
121 | mmSDMA0_CLK_CTRL0x3403, 0xff000fff, 0x00000000, | ||||
122 | mmSDMA0_GFX_IB_CNTL0x348a, 0x800f0111, 0x00000100, | ||||
123 | mmSDMA0_RLC0_IB_CNTL0x350a, 0x800f0111, 0x00000100, | ||||
124 | mmSDMA0_RLC1_IB_CNTL0x358a, 0x800f0111, 0x00000100, | ||||
125 | mmSDMA1_CHICKEN_BITS0x3605, 0xfc910007, 0x00810007, | ||||
126 | mmSDMA1_CLK_CTRL0x3603, 0xff000fff, 0x00000000, | ||||
127 | mmSDMA1_GFX_IB_CNTL0x368a, 0x800f0111, 0x00000100, | ||||
128 | mmSDMA1_RLC0_IB_CNTL0x370a, 0x800f0111, 0x00000100, | ||||
129 | mmSDMA1_RLC1_IB_CNTL0x378a, 0x800f0111, 0x00000100, | ||||
130 | }; | ||||
131 | |||||
132 | static const u32 golden_settings_polaris10_a11[] = | ||||
133 | { | ||||
134 | mmSDMA0_CHICKEN_BITS0x3405, 0xfc910007, 0x00810007, | ||||
135 | mmSDMA0_CLK_CTRL0x3403, 0xff000fff, 0x00000000, | ||||
136 | mmSDMA0_GFX_IB_CNTL0x348a, 0x800f0111, 0x00000100, | ||||
137 | mmSDMA0_RLC0_IB_CNTL0x350a, 0x800f0111, 0x00000100, | ||||
138 | mmSDMA0_RLC1_IB_CNTL0x358a, 0x800f0111, 0x00000100, | ||||
139 | mmSDMA1_CHICKEN_BITS0x3605, 0xfc910007, 0x00810007, | ||||
140 | mmSDMA1_CLK_CTRL0x3603, 0xff000fff, 0x00000000, | ||||
141 | mmSDMA1_GFX_IB_CNTL0x368a, 0x800f0111, 0x00000100, | ||||
142 | mmSDMA1_RLC0_IB_CNTL0x370a, 0x800f0111, 0x00000100, | ||||
143 | mmSDMA1_RLC1_IB_CNTL0x378a, 0x800f0111, 0x00000100, | ||||
144 | }; | ||||
145 | |||||
146 | static const u32 cz_golden_settings_a11[] = | ||||
147 | { | ||||
148 | mmSDMA0_CHICKEN_BITS0x3405, 0xfc910007, 0x00810007, | ||||
149 | mmSDMA0_CLK_CTRL0x3403, 0xff000fff, 0x00000000, | ||||
150 | mmSDMA0_GFX_IB_CNTL0x348a, 0x00000100, 0x00000100, | ||||
151 | mmSDMA0_POWER_CNTL0x3402, 0x00000800, 0x0003c800, | ||||
152 | mmSDMA0_RLC0_IB_CNTL0x350a, 0x00000100, 0x00000100, | ||||
153 | mmSDMA0_RLC1_IB_CNTL0x358a, 0x00000100, 0x00000100, | ||||
154 | mmSDMA1_CHICKEN_BITS0x3605, 0xfc910007, 0x00810007, | ||||
155 | mmSDMA1_CLK_CTRL0x3603, 0xff000fff, 0x00000000, | ||||
156 | mmSDMA1_GFX_IB_CNTL0x368a, 0x00000100, 0x00000100, | ||||
157 | mmSDMA1_POWER_CNTL0x3602, 0x00000800, 0x0003c800, | ||||
158 | mmSDMA1_RLC0_IB_CNTL0x370a, 0x00000100, 0x00000100, | ||||
159 | mmSDMA1_RLC1_IB_CNTL0x378a, 0x00000100, 0x00000100, | ||||
160 | }; | ||||
161 | |||||
162 | static const u32 cz_mgcg_cgcg_init[] = | ||||
163 | { | ||||
164 | mmSDMA0_CLK_CTRL0x3403, 0xff000ff0, 0x00000100, | ||||
165 | mmSDMA1_CLK_CTRL0x3603, 0xff000ff0, 0x00000100 | ||||
166 | }; | ||||
167 | |||||
168 | static const u32 stoney_golden_settings_a11[] = | ||||
169 | { | ||||
170 | mmSDMA0_GFX_IB_CNTL0x348a, 0x00000100, 0x00000100, | ||||
171 | mmSDMA0_POWER_CNTL0x3402, 0x00000800, 0x0003c800, | ||||
172 | mmSDMA0_RLC0_IB_CNTL0x350a, 0x00000100, 0x00000100, | ||||
173 | mmSDMA0_RLC1_IB_CNTL0x358a, 0x00000100, 0x00000100, | ||||
174 | }; | ||||
175 | |||||
176 | static const u32 stoney_mgcg_cgcg_init[] = | ||||
177 | { | ||||
178 | mmSDMA0_CLK_CTRL0x3403, 0xffffffff, 0x00000100, | ||||
179 | }; | ||||
180 | |||||
181 | /* | ||||
182 | * sDMA - System DMA | ||||
183 | * Starting with CIK, the GPU has new asynchronous | ||||
184 | * DMA engines. These engines are used for compute | ||||
185 | * and gfx. There are two DMA engines (SDMA0, SDMA1) | ||||
186 | * and each one supports 1 ring buffer used for gfx | ||||
187 | * and 2 queues used for compute. | ||||
188 | * | ||||
189 | * The programming model is very similar to the CP | ||||
190 | * (ring buffer, IBs, etc.), but sDMA has it's own | ||||
191 | * packet format that is different from the PM4 format | ||||
192 | * used by the CP. sDMA supports copying data, writing | ||||
193 | * embedded data, solid fills, and a number of other | ||||
194 | * things. It also has support for tiling/detiling of | ||||
195 | * buffers. | ||||
196 | */ | ||||
197 | |||||
198 | static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) | ||||
199 | { | ||||
200 | switch (adev->asic_type) { | ||||
201 | case CHIP_FIJI: | ||||
202 | amdgpu_device_program_register_sequence(adev, | ||||
203 | fiji_mgcg_cgcg_init, | ||||
204 | ARRAY_SIZE(fiji_mgcg_cgcg_init)(sizeof((fiji_mgcg_cgcg_init)) / sizeof((fiji_mgcg_cgcg_init) [0]))); | ||||
205 | amdgpu_device_program_register_sequence(adev, | ||||
206 | golden_settings_fiji_a10, | ||||
207 | ARRAY_SIZE(golden_settings_fiji_a10)(sizeof((golden_settings_fiji_a10)) / sizeof((golden_settings_fiji_a10 )[0]))); | ||||
208 | break; | ||||
209 | case CHIP_TONGA: | ||||
210 | amdgpu_device_program_register_sequence(adev, | ||||
211 | tonga_mgcg_cgcg_init, | ||||
212 | ARRAY_SIZE(tonga_mgcg_cgcg_init)(sizeof((tonga_mgcg_cgcg_init)) / sizeof((tonga_mgcg_cgcg_init )[0]))); | ||||
213 | amdgpu_device_program_register_sequence(adev, | ||||
214 | golden_settings_tonga_a11, | ||||
215 | ARRAY_SIZE(golden_settings_tonga_a11)(sizeof((golden_settings_tonga_a11)) / sizeof((golden_settings_tonga_a11 )[0]))); | ||||
216 | break; | ||||
217 | case CHIP_POLARIS11: | ||||
218 | case CHIP_POLARIS12: | ||||
219 | case CHIP_VEGAM: | ||||
220 | amdgpu_device_program_register_sequence(adev, | ||||
221 | golden_settings_polaris11_a11, | ||||
222 | ARRAY_SIZE(golden_settings_polaris11_a11)(sizeof((golden_settings_polaris11_a11)) / sizeof((golden_settings_polaris11_a11 )[0]))); | ||||
223 | break; | ||||
224 | case CHIP_POLARIS10: | ||||
225 | amdgpu_device_program_register_sequence(adev, | ||||
226 | golden_settings_polaris10_a11, | ||||
227 | ARRAY_SIZE(golden_settings_polaris10_a11)(sizeof((golden_settings_polaris10_a11)) / sizeof((golden_settings_polaris10_a11 )[0]))); | ||||
228 | break; | ||||
229 | case CHIP_CARRIZO: | ||||
230 | amdgpu_device_program_register_sequence(adev, | ||||
231 | cz_mgcg_cgcg_init, | ||||
232 | ARRAY_SIZE(cz_mgcg_cgcg_init)(sizeof((cz_mgcg_cgcg_init)) / sizeof((cz_mgcg_cgcg_init)[0]) )); | ||||
233 | amdgpu_device_program_register_sequence(adev, | ||||
234 | cz_golden_settings_a11, | ||||
235 | ARRAY_SIZE(cz_golden_settings_a11)(sizeof((cz_golden_settings_a11)) / sizeof((cz_golden_settings_a11 )[0]))); | ||||
236 | break; | ||||
237 | case CHIP_STONEY: | ||||
238 | amdgpu_device_program_register_sequence(adev, | ||||
239 | stoney_mgcg_cgcg_init, | ||||
240 | ARRAY_SIZE(stoney_mgcg_cgcg_init)(sizeof((stoney_mgcg_cgcg_init)) / sizeof((stoney_mgcg_cgcg_init )[0]))); | ||||
241 | amdgpu_device_program_register_sequence(adev, | ||||
242 | stoney_golden_settings_a11, | ||||
243 | ARRAY_SIZE(stoney_golden_settings_a11)(sizeof((stoney_golden_settings_a11)) / sizeof((stoney_golden_settings_a11 )[0]))); | ||||
244 | break; | ||||
245 | default: | ||||
246 | break; | ||||
247 | } | ||||
248 | } | ||||
249 | |||||
250 | static void sdma_v3_0_free_microcode(struct amdgpu_device *adev) | ||||
251 | { | ||||
252 | int i; | ||||
253 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
254 | release_firmware(adev->sdma.instance[i].fw); | ||||
255 | adev->sdma.instance[i].fw = NULL((void *)0); | ||||
256 | } | ||||
257 | } | ||||
258 | |||||
259 | /** | ||||
260 | * sdma_v3_0_init_microcode - load ucode images from disk | ||||
261 | * | ||||
262 | * @adev: amdgpu_device pointer | ||||
263 | * | ||||
264 | * Use the firmware interface to load the ucode images into | ||||
265 | * the driver (not loaded into hw). | ||||
266 | * Returns 0 on success, error on failure. | ||||
267 | */ | ||||
268 | static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) | ||||
269 | { | ||||
270 | const char *chip_name; | ||||
271 | char fw_name[30]; | ||||
272 | int err = 0, i; | ||||
273 | struct amdgpu_firmware_info *info = NULL((void *)0); | ||||
274 | const struct common_firmware_header *header = NULL((void *)0); | ||||
275 | const struct sdma_firmware_header_v1_0 *hdr; | ||||
276 | |||||
277 | DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n"); | ||||
278 | |||||
279 | switch (adev->asic_type) { | ||||
280 | case CHIP_TONGA: | ||||
281 | chip_name = "tonga"; | ||||
282 | break; | ||||
283 | case CHIP_FIJI: | ||||
284 | chip_name = "fiji"; | ||||
285 | break; | ||||
286 | case CHIP_POLARIS10: | ||||
287 | chip_name = "polaris10"; | ||||
288 | break; | ||||
289 | case CHIP_POLARIS11: | ||||
290 | chip_name = "polaris11"; | ||||
291 | break; | ||||
292 | case CHIP_POLARIS12: | ||||
293 | chip_name = "polaris12"; | ||||
294 | break; | ||||
295 | case CHIP_VEGAM: | ||||
296 | chip_name = "vegam"; | ||||
297 | break; | ||||
298 | case CHIP_CARRIZO: | ||||
299 | chip_name = "carrizo"; | ||||
300 | break; | ||||
301 | case CHIP_STONEY: | ||||
302 | chip_name = "stoney"; | ||||
303 | break; | ||||
304 | default: BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/sdma_v3_0.c" , 304); } while (0); | ||||
305 | } | ||||
306 | |||||
307 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
308 | if (i
| ||||
309 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); | ||||
310 | else | ||||
311 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); | ||||
312 | err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); | ||||
313 | if (err) | ||||
314 | goto out; | ||||
315 | err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); | ||||
316 | if (err) | ||||
317 | goto out; | ||||
318 | hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; | ||||
| |||||
319 | adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version)); | ||||
320 | adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version)((__uint32_t)(hdr->ucode_feature_version)); | ||||
321 | if (adev->sdma.instance[i].feature_version >= 20) | ||||
322 | adev->sdma.instance[i].burst_nop = true1; | ||||
323 | |||||
324 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; | ||||
325 | info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; | ||||
326 | info->fw = adev->sdma.instance[i].fw; | ||||
327 | header = (const struct common_firmware_header *)info->fw->data; | ||||
328 | adev->firmware.fw_size += | ||||
329 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); | ||||
330 | |||||
331 | } | ||||
332 | out: | ||||
333 | if (err) { | ||||
334 | pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name)printk("\0013" "amdgpu: " "sdma_v3_0: Failed to load firmware \"%s\"\n" , fw_name); | ||||
335 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
336 | release_firmware(adev->sdma.instance[i].fw); | ||||
337 | adev->sdma.instance[i].fw = NULL((void *)0); | ||||
338 | } | ||||
339 | } | ||||
340 | return err; | ||||
341 | } | ||||
342 | |||||
343 | /** | ||||
344 | * sdma_v3_0_ring_get_rptr - get the current read pointer | ||||
345 | * | ||||
346 | * @ring: amdgpu ring pointer | ||||
347 | * | ||||
348 | * Get the current rptr from the hardware (VI+). | ||||
349 | */ | ||||
350 | static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring) | ||||
351 | { | ||||
352 | /* XXX check if swapping is necessary on BE */ | ||||
353 | return ring->adev->wb.wb[ring->rptr_offs] >> 2; | ||||
354 | } | ||||
355 | |||||
356 | /** | ||||
357 | * sdma_v3_0_ring_get_wptr - get the current write pointer | ||||
358 | * | ||||
359 | * @ring: amdgpu ring pointer | ||||
360 | * | ||||
361 | * Get the current wptr from the hardware (VI+). | ||||
362 | */ | ||||
363 | static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) | ||||
364 | { | ||||
365 | struct amdgpu_device *adev = ring->adev; | ||||
366 | u32 wptr; | ||||
367 | |||||
368 | if (ring->use_doorbell || ring->use_pollmem) { | ||||
369 | /* XXX check if swapping is necessary on BE */ | ||||
370 | wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; | ||||
371 | } else { | ||||
372 | wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me])amdgpu_device_rreg(adev, (0x3484 + sdma_offsets[ring->me]) , 0) >> 2; | ||||
373 | } | ||||
374 | |||||
375 | return wptr; | ||||
376 | } | ||||
377 | |||||
378 | /** | ||||
379 | * sdma_v3_0_ring_set_wptr - commit the write pointer | ||||
380 | * | ||||
381 | * @ring: amdgpu ring pointer | ||||
382 | * | ||||
383 | * Write the wptr back to the hardware (VI+). | ||||
384 | */ | ||||
385 | static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) | ||||
386 | { | ||||
387 | struct amdgpu_device *adev = ring->adev; | ||||
388 | |||||
389 | if (ring->use_doorbell) { | ||||
390 | u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; | ||||
391 | /* XXX check if swapping is necessary on BE */ | ||||
392 | WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2))({ typeof(*wb) __tmp = ((((u32)(ring->wptr)) << 2)); *(volatile typeof(*wb) *)&(*wb) = __tmp; __tmp; }); | ||||
393 | WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2)amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)( ring->wptr)) << 2)); | ||||
394 | } else if (ring->use_pollmem) { | ||||
395 | u32 *wb = (u32 *)&adev->wb.wb[ring->wptr_offs]; | ||||
396 | |||||
397 | WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2))({ typeof(*wb) __tmp = ((((u32)(ring->wptr)) << 2)); *(volatile typeof(*wb) *)&(*wb) = __tmp; __tmp; }); | ||||
398 | } else { | ||||
399 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2)amdgpu_device_wreg(adev, (0x3484 + sdma_offsets[ring->me]) , (((u32)(ring->wptr)) << 2), 0); | ||||
400 | } | ||||
401 | } | ||||
402 | |||||
403 | static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) | ||||
404 | { | ||||
405 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); | ||||
406 | int i; | ||||
407 | |||||
408 | for (i = 0; i < count; i++) | ||||
409 | if (sdma && sdma->burst_nop && (i == 0)) | ||||
410 | amdgpu_ring_write(ring, ring->funcs->nop | | ||||
411 | SDMA_PKT_NOP_HEADER_COUNT(count - 1)(((count - 1) & 0x00003FFF) << 16)); | ||||
412 | else | ||||
413 | amdgpu_ring_write(ring, ring->funcs->nop); | ||||
414 | } | ||||
415 | |||||
416 | /** | ||||
417 | * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine | ||||
418 | * | ||||
419 | * @ring: amdgpu ring pointer | ||||
420 | * @ib: IB object to schedule | ||||
421 | * | ||||
422 | * Schedule an IB in the DMA ring (VI). | ||||
423 | */ | ||||
424 | static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring, | ||||
425 | struct amdgpu_job *job, | ||||
426 | struct amdgpu_ib *ib, | ||||
427 | uint32_t flags) | ||||
428 | { | ||||
429 | unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0); | ||||
430 | |||||
431 | /* IB packet must end on a 8 DW boundary */ | ||||
432 | sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)((u32)(ring->wptr))) & 7); | ||||
433 | |||||
434 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT)(((4) & 0x000000FF) << 0) | | ||||
435 | SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf)(((vmid & 0xf) & 0x0000000F) << 16)); | ||||
436 | /* base must be 32 byte aligned */ | ||||
437 | amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)) & 0xffffffe0); | ||||
438 | amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16))); | ||||
439 | amdgpu_ring_write(ring, ib->length_dw); | ||||
440 | amdgpu_ring_write(ring, 0); | ||||
441 | amdgpu_ring_write(ring, 0); | ||||
442 | |||||
443 | } | ||||
444 | |||||
445 | /** | ||||
446 | * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring | ||||
447 | * | ||||
448 | * @ring: amdgpu ring pointer | ||||
449 | * | ||||
450 | * Emit an hdp flush packet on the requested DMA ring. | ||||
451 | */ | ||||
452 | static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) | ||||
453 | { | ||||
454 | u32 ref_and_mask = 0; | ||||
455 | |||||
456 | if (ring->me == 0) | ||||
457 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1)(((ref_and_mask) & ~0x400) | (0x400 & ((1) << 0xa ))); | ||||
458 | else | ||||
459 | ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1)(((ref_and_mask) & ~0x800) | (0x800 & ((1) << 0xb ))); | ||||
460 | |||||
461 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) | | ||||
462 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1)(((1) & 0x00000001) << 26) | | ||||
463 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28)); /* == */ | ||||
464 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE0x1538 << 2); | ||||
465 | amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ0x1537 << 2); | ||||
466 | amdgpu_ring_write(ring, ref_and_mask); /* reference */ | ||||
467 | amdgpu_ring_write(ring, ref_and_mask); /* mask */ | ||||
468 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) | | ||||
469 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */ | ||||
470 | } | ||||
471 | |||||
472 | /** | ||||
473 | * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring | ||||
474 | * | ||||
475 | * @ring: amdgpu ring pointer | ||||
476 | * @fence: amdgpu fence object | ||||
477 | * | ||||
478 | * Add a DMA fence packet to the ring to write | ||||
479 | * the fence seq number and DMA trap packet to generate | ||||
480 | * an interrupt if needed (VI). | ||||
481 | */ | ||||
482 | static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | ||||
483 | unsigned flags) | ||||
484 | { | ||||
485 | bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0); | ||||
486 | /* write the fence */ | ||||
487 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0)); | ||||
488 | amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr))); | ||||
489 | amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16))); | ||||
490 | amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq))); | ||||
491 | |||||
492 | /* optionally write high bits as well */ | ||||
493 | if (write64bit) { | ||||
494 | addr += 4; | ||||
495 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE)(((5) & 0x000000FF) << 0)); | ||||
496 | amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr))); | ||||
497 | amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16))); | ||||
498 | amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16))); | ||||
499 | } | ||||
500 | |||||
501 | /* generate an interrupt */ | ||||
502 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP)(((6) & 0x000000FF) << 0)); | ||||
503 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)(((0) & 0x0FFFFFFF) << 0)); | ||||
504 | } | ||||
505 | |||||
506 | /** | ||||
507 | * sdma_v3_0_gfx_stop - stop the gfx async dma engines | ||||
508 | * | ||||
509 | * @adev: amdgpu_device pointer | ||||
510 | * | ||||
511 | * Stop the gfx async dma ring buffers (VI). | ||||
512 | */ | ||||
513 | static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) | ||||
514 | { | ||||
515 | struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; | ||||
516 | struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; | ||||
517 | u32 rb_cntl, ib_cntl; | ||||
518 | int i; | ||||
519 | |||||
520 | if ((adev->mman.buffer_funcs_ring == sdma0) || | ||||
521 | (adev->mman.buffer_funcs_ring == sdma1)) | ||||
522 | amdgpu_ttm_set_buffer_funcs_status(adev, false0); | ||||
523 | |||||
524 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
525 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3480 + sdma_offsets[i]), 0); | ||||
526 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0)(((rb_cntl) & ~0x1) | (0x1 & ((0) << 0x0))); | ||||
527 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl)amdgpu_device_wreg(adev, (0x3480 + sdma_offsets[i]), (rb_cntl ), 0); | ||||
528 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x348a + sdma_offsets[i]), 0); | ||||
529 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0)(((ib_cntl) & ~0x1) | (0x1 & ((0) << 0x0))); | ||||
530 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl)amdgpu_device_wreg(adev, (0x348a + sdma_offsets[i]), (ib_cntl ), 0); | ||||
531 | } | ||||
532 | } | ||||
533 | |||||
534 | /** | ||||
535 | * sdma_v3_0_rlc_stop - stop the compute async dma engines | ||||
536 | * | ||||
537 | * @adev: amdgpu_device pointer | ||||
538 | * | ||||
539 | * Stop the compute async dma queues (VI). | ||||
540 | */ | ||||
541 | static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev) | ||||
542 | { | ||||
543 | /* XXX todo */ | ||||
544 | } | ||||
545 | |||||
546 | /** | ||||
547 | * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch | ||||
548 | * | ||||
549 | * @adev: amdgpu_device pointer | ||||
550 | * @enable: enable/disable the DMA MEs context switch. | ||||
551 | * | ||||
552 | * Halt or unhalt the async dma engines context switch (VI). | ||||
553 | */ | ||||
554 | static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool_Bool enable) | ||||
555 | { | ||||
556 | u32 f32_cntl, phase_quantum = 0; | ||||
557 | int i; | ||||
558 | |||||
559 | if (amdgpu_sdma_phase_quantum) { | ||||
560 | unsigned value = amdgpu_sdma_phase_quantum; | ||||
561 | unsigned unit = 0; | ||||
562 | |||||
563 | while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK0xffff00 >> | ||||
564 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8)) { | ||||
565 | value = (value + 1) >> 1; | ||||
566 | unit++; | ||||
567 | } | ||||
568 | if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK0xf >> | ||||
569 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0)) { | ||||
570 | value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK0xffff00 >> | ||||
571 | SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8); | ||||
572 | unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK0xf >> | ||||
573 | SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0); | ||||
574 | WARN_ONCE(1,({ static int __warned; int __ret = !!(1); if (__ret && !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n" , value << unit); __warned = 1; } __builtin_expect(!!(__ret ), 0); }) | ||||
575 | "clamping sdma_phase_quantum to %uK clock cycles\n",({ static int __warned; int __ret = !!(1); if (__ret && !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n" , value << unit); __warned = 1; } __builtin_expect(!!(__ret ), 0); }) | ||||
576 | value << unit)({ static int __warned; int __ret = !!(1); if (__ret && !__warned) { printf("clamping sdma_phase_quantum to %uK clock cycles\n" , value << unit); __warned = 1; } __builtin_expect(!!(__ret ), 0); }); | ||||
577 | } | ||||
578 | phase_quantum = | ||||
579 | value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT0x8 | | ||||
580 | unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT0x0; | ||||
581 | } | ||||
582 | |||||
583 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
584 | f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3404 + sdma_offsets[i]), 0); | ||||
585 | if (enable) { | ||||
586 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x40000) | (0x40000 & ((1) << 0x12 ))) | ||||
587 | AUTO_CTXSW_ENABLE, 1)(((f32_cntl) & ~0x40000) | (0x40000 & ((1) << 0x12 ))); | ||||
588 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x2) | (0x2 & ((1) << 0x1))) | ||||
589 | ATC_L1_ENABLE, 1)(((f32_cntl) & ~0x2) | (0x2 & ((1) << 0x1))); | ||||
590 | if (amdgpu_sdma_phase_quantum) { | ||||
591 | WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3414 + sdma_offsets[i]), (phase_quantum ), 0) | ||||
592 | phase_quantum)amdgpu_device_wreg(adev, (0x3414 + sdma_offsets[i]), (phase_quantum ), 0); | ||||
593 | WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3415 + sdma_offsets[i]), (phase_quantum ), 0) | ||||
594 | phase_quantum)amdgpu_device_wreg(adev, (0x3415 + sdma_offsets[i]), (phase_quantum ), 0); | ||||
595 | } | ||||
596 | } else { | ||||
597 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x40000) | (0x40000 & ((0) << 0x12 ))) | ||||
598 | AUTO_CTXSW_ENABLE, 0)(((f32_cntl) & ~0x40000) | (0x40000 & ((0) << 0x12 ))); | ||||
599 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,(((f32_cntl) & ~0x2) | (0x2 & ((1) << 0x1))) | ||||
600 | ATC_L1_ENABLE, 1)(((f32_cntl) & ~0x2) | (0x2 & ((1) << 0x1))); | ||||
601 | } | ||||
602 | |||||
603 | WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl)amdgpu_device_wreg(adev, (0x3404 + sdma_offsets[i]), (f32_cntl ), 0); | ||||
604 | } | ||||
605 | } | ||||
606 | |||||
607 | /** | ||||
608 | * sdma_v3_0_enable - stop the async dma engines | ||||
609 | * | ||||
610 | * @adev: amdgpu_device pointer | ||||
611 | * @enable: enable/disable the DMA MEs. | ||||
612 | * | ||||
613 | * Halt or unhalt the async dma engines (VI). | ||||
614 | */ | ||||
615 | static void sdma_v3_0_enable(struct amdgpu_device *adev, bool_Bool enable) | ||||
616 | { | ||||
617 | u32 f32_cntl; | ||||
618 | int i; | ||||
619 | |||||
620 | if (!enable) { | ||||
621 | sdma_v3_0_gfx_stop(adev); | ||||
622 | sdma_v3_0_rlc_stop(adev); | ||||
623 | } | ||||
624 | |||||
625 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
626 | f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3412 + sdma_offsets[i]), 0); | ||||
627 | if (enable) | ||||
628 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0)(((f32_cntl) & ~0x1) | (0x1 & ((0) << 0x0))); | ||||
629 | else | ||||
630 | f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1)(((f32_cntl) & ~0x1) | (0x1 & ((1) << 0x0))); | ||||
631 | WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl)amdgpu_device_wreg(adev, (0x3412 + sdma_offsets[i]), (f32_cntl ), 0); | ||||
632 | } | ||||
633 | } | ||||
634 | |||||
635 | /** | ||||
636 | * sdma_v3_0_gfx_resume - setup and start the async dma engines | ||||
637 | * | ||||
638 | * @adev: amdgpu_device pointer | ||||
639 | * | ||||
640 | * Set up the gfx DMA ring buffers and enable them (VI). | ||||
641 | * Returns 0 for success, error for failure. | ||||
642 | */ | ||||
643 | static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) | ||||
644 | { | ||||
645 | struct amdgpu_ring *ring; | ||||
646 | u32 rb_cntl, ib_cntl, wptr_poll_cntl; | ||||
647 | u32 rb_bufsz; | ||||
648 | u32 wb_offset; | ||||
649 | u32 doorbell; | ||||
650 | u64 wptr_gpu_addr; | ||||
651 | int i, j, r; | ||||
652 | |||||
653 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
654 | ring = &adev->sdma.instance[i].ring; | ||||
655 | amdgpu_ring_clear_ring(ring); | ||||
656 | wb_offset = (ring->rptr_offs * 4); | ||||
657 | |||||
658 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); | ||||
659 | for (j = 0; j < 16; j++) { | ||||
660 | vi_srbm_select(adev, 0, 0, 0, j); | ||||
661 | /* SDMA GFX */ | ||||
662 | WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x34a7 + sdma_offsets[i]), (0), 0); | ||||
663 | WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x34a8 + sdma_offsets[i]), (0), 0); | ||||
664 | } | ||||
665 | vi_srbm_select(adev, 0, 0, 0, 0); | ||||
666 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); | ||||
667 | |||||
668 | WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3406 + sdma_offsets[i]), (adev-> gfx.config.gb_addr_config & 0x70), 0) | ||||
669 | adev->gfx.config.gb_addr_config & 0x70)amdgpu_device_wreg(adev, (0x3406 + sdma_offsets[i]), (adev-> gfx.config.gb_addr_config & 0x70), 0); | ||||
670 | |||||
671 | WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x3409 + sdma_offsets[i]), (0), 0); | ||||
672 | |||||
673 | /* Set ring buffer size in dwords */ | ||||
674 | rb_bufsz = order_base_2(ring->ring_size / 4)drm_order(ring->ring_size / 4); | ||||
675 | rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3480 + sdma_offsets[i]), 0); | ||||
676 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz)(((rb_cntl) & ~0x3e) | (0x3e & ((rb_bufsz) << 0x1 ))); | ||||
677 | #ifdef __BIG_ENDIAN | ||||
678 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1)(((rb_cntl) & ~0x200) | (0x200 & ((1) << 0x9))); | ||||
679 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,(((rb_cntl) & ~0x2000) | (0x2000 & ((1) << 0xd) )) | ||||
680 | RPTR_WRITEBACK_SWAP_ENABLE, 1)(((rb_cntl) & ~0x2000) | (0x2000 & ((1) << 0xd) )); | ||||
681 | #endif | ||||
682 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl)amdgpu_device_wreg(adev, (0x3480 + sdma_offsets[i]), (rb_cntl ), 0); | ||||
683 | |||||
684 | /* Initialize the ring buffer's read and write pointers */ | ||||
685 | ring->wptr = 0; | ||||
686 | WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x3483 + sdma_offsets[i]), (0), 0); | ||||
687 | sdma_v3_0_ring_set_wptr(ring); | ||||
688 | WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x348b + sdma_offsets[i]), (0), 0); | ||||
689 | WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x348c + sdma_offsets[i]), (0), 0); | ||||
690 | |||||
691 | /* set the wb address whether it's enabled or not */ | ||||
692 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3488 + sdma_offsets[i]), (((u32)( ((adev->wb.gpu_addr + wb_offset) >> 16) >> 16) ) & 0xFFFFFFFF), 0) | ||||
693 | upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF)amdgpu_device_wreg(adev, (0x3488 + sdma_offsets[i]), (((u32)( ((adev->wb.gpu_addr + wb_offset) >> 16) >> 16) ) & 0xFFFFFFFF), 0); | ||||
694 | WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3489 + sdma_offsets[i]), (((u32)( adev->wb.gpu_addr + wb_offset)) & 0xFFFFFFFC), 0) | ||||
695 | lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)amdgpu_device_wreg(adev, (0x3489 + sdma_offsets[i]), (((u32)( adev->wb.gpu_addr + wb_offset)) & 0xFFFFFFFC), 0); | ||||
696 | |||||
697 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1)(((rb_cntl) & ~0x1000) | (0x1000 & ((1) << 0xc) )); | ||||
698 | |||||
699 | WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8)amdgpu_device_wreg(adev, (0x3481 + sdma_offsets[i]), (ring-> gpu_addr >> 8), 0); | ||||
700 | WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40)amdgpu_device_wreg(adev, (0x3482 + sdma_offsets[i]), (ring-> gpu_addr >> 40), 0); | ||||
701 | |||||
702 | doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3492 + sdma_offsets[i]), 0); | ||||
703 | |||||
704 | if (ring->use_doorbell) { | ||||
705 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,(((doorbell) & ~0x1fffff) | (0x1fffff & ((ring->doorbell_index ) << 0x0))) | ||||
706 | OFFSET, ring->doorbell_index)(((doorbell) & ~0x1fffff) | (0x1fffff & ((ring->doorbell_index ) << 0x0))); | ||||
707 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1)(((doorbell) & ~0x10000000) | (0x10000000 & ((1) << 0x1c))); | ||||
708 | } else { | ||||
709 | doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0)(((doorbell) & ~0x10000000) | (0x10000000 & ((0) << 0x1c))); | ||||
710 | } | ||||
711 | WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell)amdgpu_device_wreg(adev, (0x3492 + sdma_offsets[i]), (doorbell ), 0); | ||||
712 | |||||
713 | /* setup the wptr shadow polling */ | ||||
714 | wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); | ||||
715 | |||||
716 | WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3487 + sdma_offsets[i]), (((u32)( wptr_gpu_addr))), 0) | ||||
717 | lower_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, (0x3487 + sdma_offsets[i]), (((u32)( wptr_gpu_addr))), 0); | ||||
718 | WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],amdgpu_device_wreg(adev, (0x3486 + sdma_offsets[i]), (((u32)( ((wptr_gpu_addr) >> 16) >> 16))), 0) | ||||
719 | upper_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, (0x3486 + sdma_offsets[i]), (((u32)( ((wptr_gpu_addr) >> 16) >> 16))), 0); | ||||
720 | wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3485 + sdma_offsets[i]), 0); | ||||
721 | if (ring->use_pollmem) { | ||||
722 | /*wptr polling is not enogh fast, directly clean the wptr register */ | ||||
723 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0)amdgpu_device_wreg(adev, (0x3484 + sdma_offsets[i]), (0), 0); | ||||
724 | wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,(((wptr_poll_cntl) & ~0x1) | (0x1 & ((1) << 0x0 ))) | ||||
725 | SDMA0_GFX_RB_WPTR_POLL_CNTL,(((wptr_poll_cntl) & ~0x1) | (0x1 & ((1) << 0x0 ))) | ||||
726 | ENABLE, 1)(((wptr_poll_cntl) & ~0x1) | (0x1 & ((1) << 0x0 ))); | ||||
727 | } else { | ||||
728 | wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,(((wptr_poll_cntl) & ~0x1) | (0x1 & ((0) << 0x0 ))) | ||||
729 | SDMA0_GFX_RB_WPTR_POLL_CNTL,(((wptr_poll_cntl) & ~0x1) | (0x1 & ((0) << 0x0 ))) | ||||
730 | ENABLE, 0)(((wptr_poll_cntl) & ~0x1) | (0x1 & ((0) << 0x0 ))); | ||||
731 | } | ||||
732 | WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl)amdgpu_device_wreg(adev, (0x3485 + sdma_offsets[i]), (wptr_poll_cntl ), 0); | ||||
733 | |||||
734 | /* enable DMA RB */ | ||||
735 | rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1)(((rb_cntl) & ~0x1) | (0x1 & ((1) << 0x0))); | ||||
736 | WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl)amdgpu_device_wreg(adev, (0x3480 + sdma_offsets[i]), (rb_cntl ), 0); | ||||
737 | |||||
738 | ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x348a + sdma_offsets[i]), 0); | ||||
739 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1)(((ib_cntl) & ~0x1) | (0x1 & ((1) << 0x0))); | ||||
740 | #ifdef __BIG_ENDIAN | ||||
741 | ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1)(((ib_cntl) & ~0x10) | (0x10 & ((1) << 0x4))); | ||||
742 | #endif | ||||
743 | /* enable DMA IBs */ | ||||
744 | WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl)amdgpu_device_wreg(adev, (0x348a + sdma_offsets[i]), (ib_cntl ), 0); | ||||
745 | |||||
746 | ring->sched.ready = true1; | ||||
747 | } | ||||
748 | |||||
749 | /* unhalt the MEs */ | ||||
750 | sdma_v3_0_enable(adev, true1); | ||||
751 | /* enable sdma ring preemption */ | ||||
752 | sdma_v3_0_ctx_switch_enable(adev, true1); | ||||
753 | |||||
754 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
755 | ring = &adev->sdma.instance[i].ring; | ||||
756 | r = amdgpu_ring_test_helper(ring); | ||||
757 | if (r) | ||||
758 | return r; | ||||
759 | |||||
760 | if (adev->mman.buffer_funcs_ring == ring) | ||||
761 | amdgpu_ttm_set_buffer_funcs_status(adev, true1); | ||||
762 | } | ||||
763 | |||||
764 | return 0; | ||||
765 | } | ||||
766 | |||||
767 | /** | ||||
768 | * sdma_v3_0_rlc_resume - setup and start the async dma engines | ||||
769 | * | ||||
770 | * @adev: amdgpu_device pointer | ||||
771 | * | ||||
772 | * Set up the compute DMA queues and enable them (VI). | ||||
773 | * Returns 0 for success, error for failure. | ||||
774 | */ | ||||
775 | static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev) | ||||
776 | { | ||||
777 | /* XXX todo */ | ||||
778 | return 0; | ||||
779 | } | ||||
780 | |||||
781 | /** | ||||
782 | * sdma_v3_0_start - setup and start the async dma engines | ||||
783 | * | ||||
784 | * @adev: amdgpu_device pointer | ||||
785 | * | ||||
786 | * Set up the DMA engines and enable them (VI). | ||||
787 | * Returns 0 for success, error for failure. | ||||
788 | */ | ||||
789 | static int sdma_v3_0_start(struct amdgpu_device *adev) | ||||
790 | { | ||||
791 | int r; | ||||
792 | |||||
793 | /* disable sdma engine before programing it */ | ||||
794 | sdma_v3_0_ctx_switch_enable(adev, false0); | ||||
795 | sdma_v3_0_enable(adev, false0); | ||||
796 | |||||
797 | /* start the gfx rings and rlc compute queues */ | ||||
798 | r = sdma_v3_0_gfx_resume(adev); | ||||
799 | if (r) | ||||
800 | return r; | ||||
801 | r = sdma_v3_0_rlc_resume(adev); | ||||
802 | if (r) | ||||
803 | return r; | ||||
804 | |||||
805 | return 0; | ||||
806 | } | ||||
807 | |||||
808 | /** | ||||
809 | * sdma_v3_0_ring_test_ring - simple async dma engine test | ||||
810 | * | ||||
811 | * @ring: amdgpu_ring structure holding ring information | ||||
812 | * | ||||
813 | * Test the DMA engine by writing using it to write an | ||||
814 | * value to memory. (VI). | ||||
815 | * Returns 0 for success, error for failure. | ||||
816 | */ | ||||
817 | static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring) | ||||
818 | { | ||||
819 | struct amdgpu_device *adev = ring->adev; | ||||
820 | unsigned i; | ||||
821 | unsigned index; | ||||
822 | int r; | ||||
823 | u32 tmp; | ||||
824 | u64 gpu_addr; | ||||
825 | |||||
826 | r = amdgpu_device_wb_get(adev, &index); | ||||
827 | if (r) | ||||
828 | return r; | ||||
829 | |||||
830 | gpu_addr = adev->wb.gpu_addr + (index * 4); | ||||
831 | tmp = 0xCAFEDEAD; | ||||
832 | adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp)); | ||||
833 | |||||
834 | r = amdgpu_ring_alloc(ring, 5); | ||||
835 | if (r) | ||||
836 | goto error_free_wb; | ||||
837 | |||||
838 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) | | ||||
839 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8)); | ||||
840 | amdgpu_ring_write(ring, lower_32_bits(gpu_addr)((u32)(gpu_addr))); | ||||
841 | amdgpu_ring_write(ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16))); | ||||
842 | amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)(((1) & 0x003FFFFF) << 0)); | ||||
843 | amdgpu_ring_write(ring, 0xDEADBEEF); | ||||
844 | amdgpu_ring_commit(ring); | ||||
845 | |||||
846 | for (i = 0; i < adev->usec_timeout; i++) { | ||||
847 | tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index])); | ||||
848 | if (tmp == 0xDEADBEEF) | ||||
849 | break; | ||||
850 | udelay(1); | ||||
851 | } | ||||
852 | |||||
853 | if (i >= adev->usec_timeout) | ||||
854 | r = -ETIMEDOUT60; | ||||
855 | |||||
856 | error_free_wb: | ||||
857 | amdgpu_device_wb_free(adev, index); | ||||
858 | return r; | ||||
859 | } | ||||
860 | |||||
861 | /** | ||||
862 | * sdma_v3_0_ring_test_ib - test an IB on the DMA engine | ||||
863 | * | ||||
864 | * @ring: amdgpu_ring structure holding ring information | ||||
865 | * | ||||
866 | * Test a simple IB in the DMA ring (VI). | ||||
867 | * Returns 0 on success, error on failure. | ||||
868 | */ | ||||
869 | static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) | ||||
870 | { | ||||
871 | struct amdgpu_device *adev = ring->adev; | ||||
872 | struct amdgpu_ib ib; | ||||
873 | struct dma_fence *f = NULL((void *)0); | ||||
874 | unsigned index; | ||||
875 | u32 tmp = 0; | ||||
876 | u64 gpu_addr; | ||||
877 | long r; | ||||
878 | |||||
879 | r = amdgpu_device_wb_get(adev, &index); | ||||
880 | if (r) | ||||
881 | return r; | ||||
882 | |||||
883 | gpu_addr = adev->wb.gpu_addr + (index * 4); | ||||
884 | tmp = 0xCAFEDEAD; | ||||
885 | adev->wb.wb[index] = cpu_to_le32(tmp)((__uint32_t)(tmp)); | ||||
886 | memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib))); | ||||
887 | r = amdgpu_ib_get(adev, NULL((void *)0), 256, | ||||
888 | AMDGPU_IB_POOL_DIRECT, &ib); | ||||
889 | if (r) | ||||
890 | goto err0; | ||||
891 | |||||
892 | ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) | | ||||
893 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8); | ||||
894 | ib.ptr[1] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); | ||||
895 | ib.ptr[2] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); | ||||
896 | ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1)(((1) & 0x003FFFFF) << 0); | ||||
897 | ib.ptr[4] = 0xDEADBEEF; | ||||
898 | ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); | ||||
899 | ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); | ||||
900 | ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); | ||||
901 | ib.length_dw = 8; | ||||
902 | |||||
903 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f); | ||||
904 | if (r) | ||||
905 | goto err1; | ||||
906 | |||||
907 | r = dma_fence_wait_timeout(f, false0, timeout); | ||||
908 | if (r == 0) { | ||||
909 | r = -ETIMEDOUT60; | ||||
910 | goto err1; | ||||
911 | } else if (r < 0) { | ||||
912 | goto err1; | ||||
913 | } | ||||
914 | tmp = le32_to_cpu(adev->wb.wb[index])((__uint32_t)(adev->wb.wb[index])); | ||||
915 | if (tmp == 0xDEADBEEF) | ||||
916 | r = 0; | ||||
917 | else | ||||
918 | r = -EINVAL22; | ||||
919 | err1: | ||||
920 | amdgpu_ib_free(adev, &ib, NULL((void *)0)); | ||||
921 | dma_fence_put(f); | ||||
922 | err0: | ||||
923 | amdgpu_device_wb_free(adev, index); | ||||
924 | return r; | ||||
925 | } | ||||
926 | |||||
927 | /** | ||||
928 | * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART | ||||
929 | * | ||||
930 | * @ib: indirect buffer to fill with commands | ||||
931 | * @pe: addr of the page entry | ||||
932 | * @src: src addr to copy from | ||||
933 | * @count: number of page entries to update | ||||
934 | * | ||||
935 | * Update PTEs by copying them from the GART using sDMA (CIK). | ||||
936 | */ | ||||
937 | static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib, | ||||
938 | uint64_t pe, uint64_t src, | ||||
939 | unsigned count) | ||||
940 | { | ||||
941 | unsigned bytes = count * 8; | ||||
942 | |||||
943 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) | | ||||
944 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8); | ||||
945 | ib->ptr[ib->length_dw++] = bytes; | ||||
946 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | ||||
947 | ib->ptr[ib->length_dw++] = lower_32_bits(src)((u32)(src)); | ||||
948 | ib->ptr[ib->length_dw++] = upper_32_bits(src)((u32)(((src) >> 16) >> 16)); | ||||
949 | ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); | ||||
950 | ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16)); | ||||
951 | } | ||||
952 | |||||
953 | /** | ||||
954 | * sdma_v3_0_vm_write_pte - update PTEs by writing them manually | ||||
955 | * | ||||
956 | * @ib: indirect buffer to fill with commands | ||||
957 | * @pe: addr of the page entry | ||||
958 | * @value: dst addr to write into pe | ||||
959 | * @count: number of page entries to update | ||||
960 | * @incr: increase next addr by incr bytes | ||||
961 | * | ||||
962 | * Update PTEs by writing them manually using sDMA (CIK). | ||||
963 | */ | ||||
964 | static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, | ||||
965 | uint64_t value, unsigned count, | ||||
966 | uint32_t incr) | ||||
967 | { | ||||
968 | unsigned ndw = count * 2; | ||||
969 | |||||
970 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE)(((2) & 0x000000FF) << 0) | | ||||
971 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR)(((0) & 0x000000FF) << 8); | ||||
972 | ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); | ||||
973 | ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16)); | ||||
974 | ib->ptr[ib->length_dw++] = ndw; | ||||
975 | for (; ndw > 0; ndw -= 2) { | ||||
976 | ib->ptr[ib->length_dw++] = lower_32_bits(value)((u32)(value)); | ||||
977 | ib->ptr[ib->length_dw++] = upper_32_bits(value)((u32)(((value) >> 16) >> 16)); | ||||
978 | value += incr; | ||||
979 | } | ||||
980 | } | ||||
981 | |||||
982 | /** | ||||
983 | * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA | ||||
984 | * | ||||
985 | * @ib: indirect buffer to fill with commands | ||||
986 | * @pe: addr of the page entry | ||||
987 | * @addr: dst addr to write into pe | ||||
988 | * @count: number of page entries to update | ||||
989 | * @incr: increase next addr by incr bytes | ||||
990 | * @flags: access flags | ||||
991 | * | ||||
992 | * Update the page tables using sDMA (CIK). | ||||
993 | */ | ||||
994 | static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, | ||||
995 | uint64_t addr, unsigned count, | ||||
996 | uint32_t incr, uint64_t flags) | ||||
997 | { | ||||
998 | /* for physically contiguous pages (vram) */ | ||||
999 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE)(((12) & 0x000000FF) << 0); | ||||
1000 | ib->ptr[ib->length_dw++] = lower_32_bits(pe)((u32)(pe)); /* dst addr */ | ||||
1001 | ib->ptr[ib->length_dw++] = upper_32_bits(pe)((u32)(((pe) >> 16) >> 16)); | ||||
1002 | ib->ptr[ib->length_dw++] = lower_32_bits(flags)((u32)(flags)); /* mask */ | ||||
1003 | ib->ptr[ib->length_dw++] = upper_32_bits(flags)((u32)(((flags) >> 16) >> 16)); | ||||
1004 | ib->ptr[ib->length_dw++] = lower_32_bits(addr)((u32)(addr)); /* value */ | ||||
1005 | ib->ptr[ib->length_dw++] = upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)); | ||||
1006 | ib->ptr[ib->length_dw++] = incr; /* increment size */ | ||||
1007 | ib->ptr[ib->length_dw++] = 0; | ||||
1008 | ib->ptr[ib->length_dw++] = count; /* number of entries */ | ||||
1009 | } | ||||
1010 | |||||
1011 | /** | ||||
1012 | * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw | ||||
1013 | * | ||||
1014 | * @ib: indirect buffer to fill with padding | ||||
1015 | * | ||||
1016 | */ | ||||
1017 | static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) | ||||
1018 | { | ||||
1019 | struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring); | ||||
1020 | u32 pad_count; | ||||
1021 | int i; | ||||
1022 | |||||
1023 | pad_count = (-ib->length_dw) & 7; | ||||
1024 | for (i = 0; i < pad_count; i++) | ||||
1025 | if (sdma && sdma->burst_nop && (i == 0)) | ||||
1026 | ib->ptr[ib->length_dw++] = | ||||
1027 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0) | | ||||
1028 | SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1)(((pad_count - 1) & 0x00003FFF) << 16); | ||||
1029 | else | ||||
1030 | ib->ptr[ib->length_dw++] = | ||||
1031 | SDMA_PKT_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0); | ||||
1032 | } | ||||
1033 | |||||
1034 | /** | ||||
1035 | * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline | ||||
1036 | * | ||||
1037 | * @ring: amdgpu_ring pointer | ||||
1038 | * | ||||
1039 | * Make sure all previous operations are completed (CIK). | ||||
1040 | */ | ||||
1041 | static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) | ||||
1042 | { | ||||
1043 | uint32_t seq = ring->fence_drv.sync_seq; | ||||
1044 | uint64_t addr = ring->fence_drv.gpu_addr; | ||||
1045 | |||||
1046 | /* wait for idle */ | ||||
1047 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) | | ||||
1048 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) | | ||||
1049 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)(((3) & 0x00000007) << 28) | /* equal */ | ||||
1050 | SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1)(((1) & 0x00000001) << 31)); | ||||
1051 | amdgpu_ring_write(ring, addr & 0xfffffffc); | ||||
1052 | amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xffffffff); | ||||
1053 | amdgpu_ring_write(ring, seq); /* reference */ | ||||
1054 | amdgpu_ring_write(ring, 0xffffffff); /* mask */ | ||||
1055 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) | | ||||
1056 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)(((4) & 0x0000FFFF) << 0)); /* retry count, poll interval */ | ||||
1057 | } | ||||
1058 | |||||
1059 | /** | ||||
1060 | * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA | ||||
1061 | * | ||||
1062 | * @ring: amdgpu_ring pointer | ||||
1063 | * @vm: amdgpu_vm pointer | ||||
1064 | * | ||||
1065 | * Update the page table base and flush the VM TLB | ||||
1066 | * using sDMA (VI). | ||||
1067 | */ | ||||
1068 | static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | ||||
1069 | unsigned vmid, uint64_t pd_addr) | ||||
1070 | { | ||||
1071 | amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring ), (vmid), (pd_addr)); | ||||
1072 | |||||
1073 | /* wait for flush */ | ||||
1074 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM)(((8) & 0x000000FF) << 0) | | ||||
1075 | SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0)(((0) & 0x00000001) << 26) | | ||||
1076 | SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)(((0) & 0x00000007) << 28)); /* always */ | ||||
1077 | amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST0x51e << 2); | ||||
1078 | amdgpu_ring_write(ring, 0); | ||||
1079 | amdgpu_ring_write(ring, 0); /* reference */ | ||||
1080 | amdgpu_ring_write(ring, 0); /* mask */ | ||||
1081 | amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff)(((0xfff) & 0x00000FFF) << 16) | | ||||
1082 | SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)(((10) & 0x0000FFFF) << 0)); /* retry count, poll interval */ | ||||
1083 | } | ||||
1084 | |||||
1085 | static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, | ||||
1086 | uint32_t reg, uint32_t val) | ||||
1087 | { | ||||
1088 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE)(((14) & 0x000000FF) << 0) | | ||||
1089 | SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf)(((0xf) & 0x0000000F) << 28)); | ||||
1090 | amdgpu_ring_write(ring, reg); | ||||
1091 | amdgpu_ring_write(ring, val); | ||||
1092 | } | ||||
1093 | |||||
1094 | static int sdma_v3_0_early_init(void *handle) | ||||
1095 | { | ||||
1096 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1097 | |||||
1098 | switch (adev->asic_type) { | ||||
1099 | case CHIP_STONEY: | ||||
1100 | adev->sdma.num_instances = 1; | ||||
1101 | break; | ||||
1102 | default: | ||||
1103 | adev->sdma.num_instances = SDMA_MAX_INSTANCE2; | ||||
1104 | break; | ||||
1105 | } | ||||
1106 | |||||
1107 | sdma_v3_0_set_ring_funcs(adev); | ||||
1108 | sdma_v3_0_set_buffer_funcs(adev); | ||||
1109 | sdma_v3_0_set_vm_pte_funcs(adev); | ||||
1110 | sdma_v3_0_set_irq_funcs(adev); | ||||
1111 | |||||
1112 | return 0; | ||||
1113 | } | ||||
1114 | |||||
1115 | static int sdma_v3_0_sw_init(void *handle) | ||||
1116 | { | ||||
1117 | struct amdgpu_ring *ring; | ||||
1118 | int r, i; | ||||
1119 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1120 | |||||
1121 | /* SDMA trap event */ | ||||
1122 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_SDMA_TRAP0x000000e0, | ||||
1123 | &adev->sdma.trap_irq); | ||||
1124 | if (r) | ||||
| |||||
1125 | return r; | ||||
1126 | |||||
1127 | /* SDMA Privileged inst */ | ||||
1128 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, 241, | ||||
1129 | &adev->sdma.illegal_inst_irq); | ||||
1130 | if (r) | ||||
1131 | return r; | ||||
1132 | |||||
1133 | /* SDMA Privileged inst */ | ||||
1134 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE0x000000f7, | ||||
1135 | &adev->sdma.illegal_inst_irq); | ||||
1136 | if (r) | ||||
1137 | return r; | ||||
1138 | |||||
1139 | r = sdma_v3_0_init_microcode(adev); | ||||
1140 | if (r) { | ||||
1141 | DRM_ERROR("Failed to load sdma firmware!\n")__drm_err("Failed to load sdma firmware!\n"); | ||||
1142 | return r; | ||||
1143 | } | ||||
1144 | |||||
1145 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1146 | ring = &adev->sdma.instance[i].ring; | ||||
1147 | ring->ring_obj = NULL((void *)0); | ||||
1148 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { | ||||
1149 | ring->use_doorbell = true1; | ||||
1150 | ring->doorbell_index = adev->doorbell_index.sdma_engine[i]; | ||||
1151 | } else { | ||||
1152 | ring->use_pollmem = true1; | ||||
1153 | } | ||||
1154 | |||||
1155 | snprintf(ring->name, sizeof(ring->name), "sdma%d", i); | ||||
1156 | r = amdgpu_ring_init(adev, ring, 1024, | ||||
1157 | &adev->sdma.trap_irq, | ||||
1158 | (i == 0) ? | ||||
1159 | AMDGPU_SDMA_IRQ_INSTANCE0 : | ||||
1160 | AMDGPU_SDMA_IRQ_INSTANCE1, | ||||
1161 | AMDGPU_RING_PRIO_DEFAULT1); | ||||
1162 | if (r) | ||||
1163 | return r; | ||||
1164 | } | ||||
1165 | |||||
1166 | return r; | ||||
1167 | } | ||||
1168 | |||||
1169 | static int sdma_v3_0_sw_fini(void *handle) | ||||
1170 | { | ||||
1171 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1172 | int i; | ||||
1173 | |||||
1174 | for (i = 0; i < adev->sdma.num_instances; i++) | ||||
1175 | amdgpu_ring_fini(&adev->sdma.instance[i].ring); | ||||
1176 | |||||
1177 | sdma_v3_0_free_microcode(adev); | ||||
1178 | return 0; | ||||
1179 | } | ||||
1180 | |||||
1181 | static int sdma_v3_0_hw_init(void *handle) | ||||
1182 | { | ||||
1183 | int r; | ||||
1184 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1185 | |||||
1186 | sdma_v3_0_init_golden_registers(adev); | ||||
1187 | |||||
1188 | r = sdma_v3_0_start(adev); | ||||
1189 | if (r) | ||||
1190 | return r; | ||||
1191 | |||||
1192 | return r; | ||||
1193 | } | ||||
1194 | |||||
1195 | static int sdma_v3_0_hw_fini(void *handle) | ||||
1196 | { | ||||
1197 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1198 | |||||
1199 | sdma_v3_0_ctx_switch_enable(adev, false0); | ||||
1200 | sdma_v3_0_enable(adev, false0); | ||||
1201 | |||||
1202 | return 0; | ||||
1203 | } | ||||
1204 | |||||
1205 | static int sdma_v3_0_suspend(void *handle) | ||||
1206 | { | ||||
1207 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1208 | |||||
1209 | return sdma_v3_0_hw_fini(adev); | ||||
1210 | } | ||||
1211 | |||||
1212 | static int sdma_v3_0_resume(void *handle) | ||||
1213 | { | ||||
1214 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1215 | |||||
1216 | return sdma_v3_0_hw_init(adev); | ||||
1217 | } | ||||
1218 | |||||
1219 | static bool_Bool sdma_v3_0_is_idle(void *handle) | ||||
1220 | { | ||||
1221 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1222 | u32 tmp = RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0); | ||||
1223 | |||||
1224 | if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK0x20 | | ||||
1225 | SRBM_STATUS2__SDMA1_BUSY_MASK0x40)) | ||||
1226 | return false0; | ||||
1227 | |||||
1228 | return true1; | ||||
1229 | } | ||||
1230 | |||||
1231 | static int sdma_v3_0_wait_for_idle(void *handle) | ||||
1232 | { | ||||
1233 | unsigned i; | ||||
1234 | u32 tmp; | ||||
1235 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1236 | |||||
1237 | for (i = 0; i < adev->usec_timeout; i++) { | ||||
1238 | tmp = RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0) & (SRBM_STATUS2__SDMA_BUSY_MASK0x20 | | ||||
1239 | SRBM_STATUS2__SDMA1_BUSY_MASK0x40); | ||||
1240 | |||||
1241 | if (!tmp) | ||||
1242 | return 0; | ||||
1243 | udelay(1); | ||||
1244 | } | ||||
1245 | return -ETIMEDOUT60; | ||||
1246 | } | ||||
1247 | |||||
1248 | static bool_Bool sdma_v3_0_check_soft_reset(void *handle) | ||||
1249 | { | ||||
1250 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1251 | u32 srbm_soft_reset = 0; | ||||
1252 | u32 tmp = RREG32(mmSRBM_STATUS2)amdgpu_device_rreg(adev, (0x393), 0); | ||||
1253 | |||||
1254 | if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK0x20) || | ||||
1255 | (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK0x40)) { | ||||
1256 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK0x100000; | ||||
1257 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK0x40; | ||||
1258 | } | ||||
1259 | |||||
1260 | if (srbm_soft_reset) { | ||||
1261 | adev->sdma.srbm_soft_reset = srbm_soft_reset; | ||||
1262 | return true1; | ||||
1263 | } else { | ||||
1264 | adev->sdma.srbm_soft_reset = 0; | ||||
1265 | return false0; | ||||
1266 | } | ||||
1267 | } | ||||
1268 | |||||
1269 | static int sdma_v3_0_pre_soft_reset(void *handle) | ||||
1270 | { | ||||
1271 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1272 | u32 srbm_soft_reset = 0; | ||||
1273 | |||||
1274 | if (!adev->sdma.srbm_soft_reset) | ||||
1275 | return 0; | ||||
1276 | |||||
1277 | srbm_soft_reset = adev->sdma.srbm_soft_reset; | ||||
1278 | |||||
1279 | if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA)(((srbm_soft_reset) & 0x100000) >> 0x14) || | ||||
1280 | REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)(((srbm_soft_reset) & 0x40) >> 0x6)) { | ||||
1281 | sdma_v3_0_ctx_switch_enable(adev, false0); | ||||
1282 | sdma_v3_0_enable(adev, false0); | ||||
1283 | } | ||||
1284 | |||||
1285 | return 0; | ||||
1286 | } | ||||
1287 | |||||
1288 | static int sdma_v3_0_post_soft_reset(void *handle) | ||||
1289 | { | ||||
1290 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1291 | u32 srbm_soft_reset = 0; | ||||
1292 | |||||
1293 | if (!adev->sdma.srbm_soft_reset) | ||||
1294 | return 0; | ||||
1295 | |||||
1296 | srbm_soft_reset = adev->sdma.srbm_soft_reset; | ||||
1297 | |||||
1298 | if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA)(((srbm_soft_reset) & 0x100000) >> 0x14) || | ||||
1299 | REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)(((srbm_soft_reset) & 0x40) >> 0x6)) { | ||||
1300 | sdma_v3_0_gfx_resume(adev); | ||||
1301 | sdma_v3_0_rlc_resume(adev); | ||||
1302 | } | ||||
1303 | |||||
1304 | return 0; | ||||
1305 | } | ||||
1306 | |||||
1307 | static int sdma_v3_0_soft_reset(void *handle) | ||||
1308 | { | ||||
1309 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1310 | u32 srbm_soft_reset = 0; | ||||
1311 | u32 tmp; | ||||
1312 | |||||
1313 | if (!adev->sdma.srbm_soft_reset) | ||||
1314 | return 0; | ||||
1315 | |||||
1316 | srbm_soft_reset = adev->sdma.srbm_soft_reset; | ||||
1317 | |||||
1318 | if (srbm_soft_reset) { | ||||
1319 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); | ||||
1320 | tmp |= srbm_soft_reset; | ||||
1321 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0); | ||||
1322 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); | ||||
1323 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); | ||||
1324 | |||||
1325 | udelay(50); | ||||
1326 | |||||
1327 | tmp &= ~srbm_soft_reset; | ||||
1328 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); | ||||
1329 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); | ||||
1330 | |||||
1331 | /* Wait a little for things to settle down */ | ||||
1332 | udelay(50); | ||||
1333 | } | ||||
1334 | |||||
1335 | return 0; | ||||
1336 | } | ||||
1337 | |||||
1338 | static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev, | ||||
1339 | struct amdgpu_irq_src *source, | ||||
1340 | unsigned type, | ||||
1341 | enum amdgpu_interrupt_state state) | ||||
1342 | { | ||||
1343 | u32 sdma_cntl; | ||||
1344 | |||||
1345 | switch (type) { | ||||
1346 | case AMDGPU_SDMA_IRQ_INSTANCE0: | ||||
1347 | switch (state) { | ||||
1348 | case AMDGPU_IRQ_STATE_DISABLE: | ||||
1349 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x0), 0); | ||||
1350 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0)(((sdma_cntl) & ~0x1) | (0x1 & ((0) << 0x0))); | ||||
1351 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x0), (sdma_cntl), 0); | ||||
1352 | break; | ||||
1353 | case AMDGPU_IRQ_STATE_ENABLE: | ||||
1354 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x0), 0); | ||||
1355 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1)(((sdma_cntl) & ~0x1) | (0x1 & ((1) << 0x0))); | ||||
1356 | WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x0), (sdma_cntl), 0); | ||||
1357 | break; | ||||
1358 | default: | ||||
1359 | break; | ||||
1360 | } | ||||
1361 | break; | ||||
1362 | case AMDGPU_SDMA_IRQ_INSTANCE1: | ||||
1363 | switch (state) { | ||||
1364 | case AMDGPU_IRQ_STATE_DISABLE: | ||||
1365 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x200), 0); | ||||
1366 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0)(((sdma_cntl) & ~0x1) | (0x1 & ((0) << 0x0))); | ||||
1367 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x200), (sdma_cntl), 0); | ||||
1368 | break; | ||||
1369 | case AMDGPU_IRQ_STATE_ENABLE: | ||||
1370 | sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET)amdgpu_device_rreg(adev, (0x3404 + 0x200), 0); | ||||
1371 | sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1)(((sdma_cntl) & ~0x1) | (0x1 & ((1) << 0x0))); | ||||
1372 | WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl)amdgpu_device_wreg(adev, (0x3404 + 0x200), (sdma_cntl), 0); | ||||
1373 | break; | ||||
1374 | default: | ||||
1375 | break; | ||||
1376 | } | ||||
1377 | break; | ||||
1378 | default: | ||||
1379 | break; | ||||
1380 | } | ||||
1381 | return 0; | ||||
1382 | } | ||||
1383 | |||||
1384 | static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, | ||||
1385 | struct amdgpu_irq_src *source, | ||||
1386 | struct amdgpu_iv_entry *entry) | ||||
1387 | { | ||||
1388 | u8 instance_id, queue_id; | ||||
1389 | |||||
1390 | instance_id = (entry->ring_id & 0x3) >> 0; | ||||
1391 | queue_id = (entry->ring_id & 0xc) >> 2; | ||||
1392 | DRM_DEBUG("IH: SDMA trap\n")__drm_dbg(DRM_UT_CORE, "IH: SDMA trap\n"); | ||||
1393 | switch (instance_id) { | ||||
1394 | case 0: | ||||
1395 | switch (queue_id) { | ||||
1396 | case 0: | ||||
1397 | amdgpu_fence_process(&adev->sdma.instance[0].ring); | ||||
1398 | break; | ||||
1399 | case 1: | ||||
1400 | /* XXX compute */ | ||||
1401 | break; | ||||
1402 | case 2: | ||||
1403 | /* XXX compute */ | ||||
1404 | break; | ||||
1405 | } | ||||
1406 | break; | ||||
1407 | case 1: | ||||
1408 | switch (queue_id) { | ||||
1409 | case 0: | ||||
1410 | amdgpu_fence_process(&adev->sdma.instance[1].ring); | ||||
1411 | break; | ||||
1412 | case 1: | ||||
1413 | /* XXX compute */ | ||||
1414 | break; | ||||
1415 | case 2: | ||||
1416 | /* XXX compute */ | ||||
1417 | break; | ||||
1418 | } | ||||
1419 | break; | ||||
1420 | } | ||||
1421 | return 0; | ||||
1422 | } | ||||
1423 | |||||
1424 | static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, | ||||
1425 | struct amdgpu_irq_src *source, | ||||
1426 | struct amdgpu_iv_entry *entry) | ||||
1427 | { | ||||
1428 | u8 instance_id, queue_id; | ||||
1429 | |||||
1430 | DRM_ERROR("Illegal instruction in SDMA command stream\n")__drm_err("Illegal instruction in SDMA command stream\n"); | ||||
1431 | instance_id = (entry->ring_id & 0x3) >> 0; | ||||
1432 | queue_id = (entry->ring_id & 0xc) >> 2; | ||||
1433 | |||||
1434 | if (instance_id <= 1 && queue_id == 0) | ||||
1435 | drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched); | ||||
1436 | return 0; | ||||
1437 | } | ||||
1438 | |||||
1439 | static void sdma_v3_0_update_sdma_medium_grain_clock_gating( | ||||
1440 | struct amdgpu_device *adev, | ||||
1441 | bool_Bool enable) | ||||
1442 | { | ||||
1443 | uint32_t temp, data; | ||||
1444 | int i; | ||||
1445 | |||||
1446 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG(1 << 11))) { | ||||
1447 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1448 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3403 + sdma_offsets[i]), 0); | ||||
1449 | data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK0x1000000 | | ||||
1450 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK0x2000000 | | ||||
1451 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK0x4000000 | | ||||
1452 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x8000000 | | ||||
1453 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x10000000 | | ||||
1454 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x20000000 | | ||||
1455 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x40000000 | | ||||
1456 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x80000000); | ||||
1457 | if (data != temp) | ||||
1458 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data)amdgpu_device_wreg(adev, (0x3403 + sdma_offsets[i]), (data), 0 ); | ||||
1459 | } | ||||
1460 | } else { | ||||
1461 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1462 | temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3403 + sdma_offsets[i]), 0); | ||||
1463 | data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK0x1000000 | | ||||
1464 | SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK0x2000000 | | ||||
1465 | SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK0x4000000 | | ||||
1466 | SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK0x8000000 | | ||||
1467 | SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK0x10000000 | | ||||
1468 | SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK0x20000000 | | ||||
1469 | SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK0x40000000 | | ||||
1470 | SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x80000000; | ||||
1471 | |||||
1472 | if (data != temp) | ||||
1473 | WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data)amdgpu_device_wreg(adev, (0x3403 + sdma_offsets[i]), (data), 0 ); | ||||
1474 | } | ||||
1475 | } | ||||
1476 | } | ||||
1477 | |||||
1478 | static void sdma_v3_0_update_sdma_medium_grain_light_sleep( | ||||
1479 | struct amdgpu_device *adev, | ||||
1480 | bool_Bool enable) | ||||
1481 | { | ||||
1482 | uint32_t temp, data; | ||||
1483 | int i; | ||||
1484 | |||||
1485 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS(1 << 10))) { | ||||
1486 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1487 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3402 + sdma_offsets[i]), 0); | ||||
1488 | data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x100; | ||||
1489 | |||||
1490 | if (temp != data) | ||||
1491 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data)amdgpu_device_wreg(adev, (0x3402 + sdma_offsets[i]), (data), 0 ); | ||||
1492 | } | ||||
1493 | } else { | ||||
1494 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1495 | temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i])amdgpu_device_rreg(adev, (0x3402 + sdma_offsets[i]), 0); | ||||
1496 | data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x100; | ||||
1497 | |||||
1498 | if (temp != data) | ||||
1499 | WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data)amdgpu_device_wreg(adev, (0x3402 + sdma_offsets[i]), (data), 0 ); | ||||
1500 | } | ||||
1501 | } | ||||
1502 | } | ||||
1503 | |||||
1504 | static int sdma_v3_0_set_clockgating_state(void *handle, | ||||
1505 | enum amd_clockgating_state state) | ||||
1506 | { | ||||
1507 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1508 | |||||
1509 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) | ||||
1510 | return 0; | ||||
1511 | |||||
1512 | switch (adev->asic_type) { | ||||
1513 | case CHIP_FIJI: | ||||
1514 | case CHIP_CARRIZO: | ||||
1515 | case CHIP_STONEY: | ||||
1516 | sdma_v3_0_update_sdma_medium_grain_clock_gating(adev, | ||||
1517 | state == AMD_CG_STATE_GATE); | ||||
1518 | sdma_v3_0_update_sdma_medium_grain_light_sleep(adev, | ||||
1519 | state == AMD_CG_STATE_GATE); | ||||
1520 | break; | ||||
1521 | default: | ||||
1522 | break; | ||||
1523 | } | ||||
1524 | return 0; | ||||
1525 | } | ||||
1526 | |||||
1527 | static int sdma_v3_0_set_powergating_state(void *handle, | ||||
1528 | enum amd_powergating_state state) | ||||
1529 | { | ||||
1530 | return 0; | ||||
1531 | } | ||||
1532 | |||||
1533 | static void sdma_v3_0_get_clockgating_state(void *handle, u32 *flags) | ||||
1534 | { | ||||
1535 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; | ||||
1536 | int data; | ||||
1537 | |||||
1538 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) | ||||
1539 | *flags = 0; | ||||
1540 | |||||
1541 | /* AMD_CG_SUPPORT_SDMA_MGCG */ | ||||
1542 | data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0])amdgpu_device_rreg(adev, (0x3403 + sdma_offsets[0]), 0); | ||||
1543 | if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK0x80000000)) | ||||
1544 | *flags |= AMD_CG_SUPPORT_SDMA_MGCG(1 << 11); | ||||
1545 | |||||
1546 | /* AMD_CG_SUPPORT_SDMA_LS */ | ||||
1547 | data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0])amdgpu_device_rreg(adev, (0x3402 + sdma_offsets[0]), 0); | ||||
1548 | if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK0x100) | ||||
1549 | *flags |= AMD_CG_SUPPORT_SDMA_LS(1 << 10); | ||||
1550 | } | ||||
1551 | |||||
1552 | static const struct amd_ip_funcs sdma_v3_0_ip_funcs = { | ||||
1553 | .name = "sdma_v3_0", | ||||
1554 | .early_init = sdma_v3_0_early_init, | ||||
1555 | .late_init = NULL((void *)0), | ||||
1556 | .sw_init = sdma_v3_0_sw_init, | ||||
1557 | .sw_fini = sdma_v3_0_sw_fini, | ||||
1558 | .hw_init = sdma_v3_0_hw_init, | ||||
1559 | .hw_fini = sdma_v3_0_hw_fini, | ||||
1560 | .suspend = sdma_v3_0_suspend, | ||||
1561 | .resume = sdma_v3_0_resume, | ||||
1562 | .is_idle = sdma_v3_0_is_idle, | ||||
1563 | .wait_for_idle = sdma_v3_0_wait_for_idle, | ||||
1564 | .check_soft_reset = sdma_v3_0_check_soft_reset, | ||||
1565 | .pre_soft_reset = sdma_v3_0_pre_soft_reset, | ||||
1566 | .post_soft_reset = sdma_v3_0_post_soft_reset, | ||||
1567 | .soft_reset = sdma_v3_0_soft_reset, | ||||
1568 | .set_clockgating_state = sdma_v3_0_set_clockgating_state, | ||||
1569 | .set_powergating_state = sdma_v3_0_set_powergating_state, | ||||
1570 | .get_clockgating_state = sdma_v3_0_get_clockgating_state, | ||||
1571 | }; | ||||
1572 | |||||
1573 | static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { | ||||
1574 | .type = AMDGPU_RING_TYPE_SDMA, | ||||
1575 | .align_mask = 0xf, | ||||
1576 | .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP)(((0) & 0x000000FF) << 0), | ||||
1577 | .support_64bit_ptrs = false0, | ||||
1578 | .get_rptr = sdma_v3_0_ring_get_rptr, | ||||
1579 | .get_wptr = sdma_v3_0_ring_get_wptr, | ||||
1580 | .set_wptr = sdma_v3_0_ring_set_wptr, | ||||
1581 | .emit_frame_size = | ||||
1582 | 6 + /* sdma_v3_0_ring_emit_hdp_flush */ | ||||
1583 | 3 + /* hdp invalidate */ | ||||
1584 | 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ | ||||
1585 | VI_FLUSH_GPU_TLB_NUM_WREG3 * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */ | ||||
1586 | 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ | ||||
1587 | .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ | ||||
1588 | .emit_ib = sdma_v3_0_ring_emit_ib, | ||||
1589 | .emit_fence = sdma_v3_0_ring_emit_fence, | ||||
1590 | .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, | ||||
1591 | .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, | ||||
1592 | .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, | ||||
1593 | .test_ring = sdma_v3_0_ring_test_ring, | ||||
1594 | .test_ib = sdma_v3_0_ring_test_ib, | ||||
1595 | .insert_nop = sdma_v3_0_ring_insert_nop, | ||||
1596 | .pad_ib = sdma_v3_0_ring_pad_ib, | ||||
1597 | .emit_wreg = sdma_v3_0_ring_emit_wreg, | ||||
1598 | }; | ||||
1599 | |||||
1600 | static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) | ||||
1601 | { | ||||
1602 | int i; | ||||
1603 | |||||
1604 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1605 | adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; | ||||
1606 | adev->sdma.instance[i].ring.me = i; | ||||
1607 | } | ||||
1608 | } | ||||
1609 | |||||
1610 | static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { | ||||
1611 | .set = sdma_v3_0_set_trap_irq_state, | ||||
1612 | .process = sdma_v3_0_process_trap_irq, | ||||
1613 | }; | ||||
1614 | |||||
1615 | static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { | ||||
1616 | .process = sdma_v3_0_process_illegal_inst_irq, | ||||
1617 | }; | ||||
1618 | |||||
1619 | static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) | ||||
1620 | { | ||||
1621 | adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; | ||||
1622 | adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; | ||||
1623 | adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; | ||||
1624 | } | ||||
1625 | |||||
1626 | /** | ||||
1627 | * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine | ||||
1628 | * | ||||
1629 | * @ring: amdgpu_ring structure holding ring information | ||||
1630 | * @src_offset: src GPU address | ||||
1631 | * @dst_offset: dst GPU address | ||||
1632 | * @byte_count: number of bytes to xfer | ||||
1633 | * | ||||
1634 | * Copy GPU buffers using the DMA engine (VI). | ||||
1635 | * Used by the amdgpu ttm implementation to move pages if | ||||
1636 | * registered as the asic copy callback. | ||||
1637 | */ | ||||
1638 | static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib, | ||||
1639 | uint64_t src_offset, | ||||
1640 | uint64_t dst_offset, | ||||
1641 | uint32_t byte_count, | ||||
1642 | bool_Bool tmz) | ||||
1643 | { | ||||
1644 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY)(((1) & 0x000000FF) << 0) | | ||||
1645 | SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR)(((0) & 0x000000FF) << 8); | ||||
1646 | ib->ptr[ib->length_dw++] = byte_count; | ||||
1647 | ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ | ||||
1648 | ib->ptr[ib->length_dw++] = lower_32_bits(src_offset)((u32)(src_offset)); | ||||
1649 | ib->ptr[ib->length_dw++] = upper_32_bits(src_offset)((u32)(((src_offset) >> 16) >> 16)); | ||||
1650 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset)); | ||||
1651 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16)); | ||||
1652 | } | ||||
1653 | |||||
1654 | /** | ||||
1655 | * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine | ||||
1656 | * | ||||
1657 | * @ring: amdgpu_ring structure holding ring information | ||||
1658 | * @src_data: value to write to buffer | ||||
1659 | * @dst_offset: dst GPU address | ||||
1660 | * @byte_count: number of bytes to xfer | ||||
1661 | * | ||||
1662 | * Fill GPU buffers using the DMA engine (VI). | ||||
1663 | */ | ||||
1664 | static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib, | ||||
1665 | uint32_t src_data, | ||||
1666 | uint64_t dst_offset, | ||||
1667 | uint32_t byte_count) | ||||
1668 | { | ||||
1669 | ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL)(((11) & 0x000000FF) << 0); | ||||
1670 | ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset)((u32)(dst_offset)); | ||||
1671 | ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset)((u32)(((dst_offset) >> 16) >> 16)); | ||||
1672 | ib->ptr[ib->length_dw++] = src_data; | ||||
1673 | ib->ptr[ib->length_dw++] = byte_count; | ||||
1674 | } | ||||
1675 | |||||
1676 | static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = { | ||||
1677 | .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ | ||||
1678 | .copy_num_dw = 7, | ||||
1679 | .emit_copy_buffer = sdma_v3_0_emit_copy_buffer, | ||||
1680 | |||||
1681 | .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */ | ||||
1682 | .fill_num_dw = 5, | ||||
1683 | .emit_fill_buffer = sdma_v3_0_emit_fill_buffer, | ||||
1684 | }; | ||||
1685 | |||||
1686 | static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) | ||||
1687 | { | ||||
1688 | adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; | ||||
1689 | adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; | ||||
1690 | } | ||||
1691 | |||||
1692 | static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { | ||||
1693 | .copy_pte_num_dw = 7, | ||||
1694 | .copy_pte = sdma_v3_0_vm_copy_pte, | ||||
1695 | |||||
1696 | .write_pte = sdma_v3_0_vm_write_pte, | ||||
1697 | .set_pte_pde = sdma_v3_0_vm_set_pte_pde, | ||||
1698 | }; | ||||
1699 | |||||
1700 | static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) | ||||
1701 | { | ||||
1702 | unsigned i; | ||||
1703 | |||||
1704 | adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; | ||||
1705 | for (i = 0; i < adev->sdma.num_instances; i++) { | ||||
1706 | adev->vm_manager.vm_pte_scheds[i] = | ||||
1707 | &adev->sdma.instance[i].ring.sched; | ||||
1708 | } | ||||
1709 | adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; | ||||
1710 | } | ||||
1711 | |||||
1712 | const struct amdgpu_ip_block_version sdma_v3_0_ip_block = | ||||
1713 | { | ||||
1714 | .type = AMD_IP_BLOCK_TYPE_SDMA, | ||||
1715 | .major = 3, | ||||
1716 | .minor = 0, | ||||
1717 | .rev = 0, | ||||
1718 | .funcs = &sdma_v3_0_ip_funcs, | ||||
1719 | }; | ||||
1720 | |||||
1721 | const struct amdgpu_ip_block_version sdma_v3_1_ip_block = | ||||
1722 | { | ||||
1723 | .type = AMD_IP_BLOCK_TYPE_SDMA, | ||||
1724 | .major = 3, | ||||
1725 | .minor = 1, | ||||
1726 | .rev = 0, | ||||
1727 | .funcs = &sdma_v3_0_ip_funcs, | ||||
1728 | }; |
1 | /* Public domain. */ |
2 | |
3 | #ifndef _LINUX_FIRMWARE_H |
4 | #define _LINUX_FIRMWARE_H |
5 | |
6 | #include <sys/types.h> |
7 | #include <sys/malloc.h> |
8 | #include <sys/device.h> |
9 | #include <linux/types.h> |
10 | #include <linux/gfp.h> |
11 | |
12 | #ifndef __DECONST |
13 | #define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var)) ((type)(__uintptr_t)(const void *)(var)) |
14 | #endif |
15 | |
16 | struct firmware { |
17 | size_t size; |
18 | const u8 *data; |
19 | }; |
20 | |
21 | static inline int |
22 | request_firmware(const struct firmware **fw, const char *name, |
23 | struct device *device) |
24 | { |
25 | int r; |
26 | struct firmware *f = malloc(sizeof(struct firmware), M_DRM145, |
27 | M_WAITOK0x0001 | M_ZERO0x0008); |
28 | r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size); |
29 | if (r != 0) { |
30 | free(f, M_DRM145, sizeof(struct firmware)); |
31 | *fw = NULL((void *)0); |
32 | return -r; |
33 | } else { |
34 | *fw = f; |
35 | return 0; |
36 | } |
37 | } |
38 | |
39 | static inline int |
40 | request_firmware_direct(const struct firmware **fw, const char *name, |
41 | struct device *device) |
42 | { |
43 | return request_firmware(fw, name, device); |
44 | } |
45 | |
46 | #define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22 |
47 | |
48 | static inline void |
49 | release_firmware(const struct firmware *fw) |
50 | { |
51 | if (fw) |
52 | free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size); |
53 | free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw)); |
54 | } |
55 | |
56 | #endif |