File: | dev/pci/drm/amd/amdgpu/vcn_v3_0.c |
Warning: | line 1468, column 4 Value stored to 'r' is never read |
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1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/firmware.h> |
25 | #include "amdgpu.h" |
26 | #include "amdgpu_vcn.h" |
27 | #include "amdgpu_pm.h" |
28 | #include "soc15.h" |
29 | #include "soc15d.h" |
30 | #include "vcn_v2_0.h" |
31 | #include "mmsch_v3_0.h" |
32 | |
33 | #include "vcn/vcn_3_0_0_offset.h" |
34 | #include "vcn/vcn_3_0_0_sh_mask.h" |
35 | #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h" |
36 | |
37 | #define mmUVD_CONTEXT_ID_INTERNAL_OFFSET0x27 0x27 |
38 | #define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET0x0f 0x0f |
39 | #define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET0x10 0x10 |
40 | #define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET0x11 0x11 |
41 | #define mmUVD_NO_OP_INTERNAL_OFFSET0x29 0x29 |
42 | #define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET0x66 0x66 |
43 | #define mmUVD_SCRATCH9_INTERNAL_OFFSET0xc01d 0xc01d |
44 | |
45 | #define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET0x431 0x431 |
46 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x3b4 0x3b4 |
47 | #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x3b5 0x3b5 |
48 | #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET0x25c 0x25c |
49 | |
50 | #define VCN_INSTANCES_SIENNA_CICHLID2 2 |
51 | |
52 | static int amdgpu_ih_clientid_vcns[] = { |
53 | SOC15_IH_CLIENTID_VCN, |
54 | SOC15_IH_CLIENTID_VCN1 |
55 | }; |
56 | |
57 | static int amdgpu_ucode_id_vcns[] = { |
58 | AMDGPU_UCODE_ID_VCN, |
59 | AMDGPU_UCODE_ID_VCN1 |
60 | }; |
61 | |
62 | static int vcn_v3_0_start_sriov(struct amdgpu_device *adev); |
63 | static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev); |
64 | static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev); |
65 | static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev); |
66 | static int vcn_v3_0_set_powergating_state(void *handle, |
67 | enum amd_powergating_state state); |
68 | static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, |
69 | int inst_idx, struct dpg_pause_state *new_state); |
70 | |
71 | static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring); |
72 | static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); |
73 | |
74 | /** |
75 | * vcn_v3_0_early_init - set function pointers |
76 | * |
77 | * @handle: amdgpu_device pointer |
78 | * |
79 | * Set ring and irq function pointers |
80 | */ |
81 | static int vcn_v3_0_early_init(void *handle) |
82 | { |
83 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
84 | |
85 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
86 | adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID2; |
87 | adev->vcn.harvest_config = 0; |
88 | adev->vcn.num_enc_rings = 1; |
89 | |
90 | } else { |
91 | if (adev->asic_type == CHIP_SIENNA_CICHLID) { |
92 | u32 harvest; |
93 | int i; |
94 | |
95 | adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID2; |
96 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { |
97 | harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0007), 0); |
98 | if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK0x00000002L) |
99 | adev->vcn.harvest_config |= 1 << i; |
100 | } |
101 | |
102 | if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0(1 << 0) | |
103 | AMDGPU_VCN_HARVEST_VCN1(1 << 1))) |
104 | /* both instances are harvested, disable the block */ |
105 | return -ENOENT2; |
106 | } else |
107 | adev->vcn.num_vcn_inst = 1; |
108 | |
109 | adev->vcn.num_enc_rings = 2; |
110 | } |
111 | |
112 | vcn_v3_0_set_dec_ring_funcs(adev); |
113 | vcn_v3_0_set_enc_ring_funcs(adev); |
114 | vcn_v3_0_set_irq_funcs(adev); |
115 | |
116 | return 0; |
117 | } |
118 | |
119 | /** |
120 | * vcn_v3_0_sw_init - sw init for VCN block |
121 | * |
122 | * @handle: amdgpu_device pointer |
123 | * |
124 | * Load firmware and sw initialization |
125 | */ |
126 | static int vcn_v3_0_sw_init(void *handle) |
127 | { |
128 | struct amdgpu_ring *ring; |
129 | int i, j, r; |
130 | int vcn_doorbell_index = 0; |
131 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
132 | |
133 | r = amdgpu_vcn_sw_init(adev); |
134 | if (r) |
135 | return r; |
136 | |
137 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
138 | const struct common_firmware_header *hdr; |
139 | hdr = (const struct common_firmware_header *)adev->vcn.fw->data; |
140 | adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; |
141 | adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; |
142 | adev->firmware.fw_size += |
143 | roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->ucode_size_bytes))) + (((1 << 12 )) - 1)) & (~((__typeof(((__uint32_t)(hdr->ucode_size_bytes ))))((1 << 12)) - 1))); |
144 | |
145 | if (adev->vcn.num_vcn_inst == VCN_INSTANCES_SIENNA_CICHLID2) { |
146 | adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1; |
147 | adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw; |
148 | adev->firmware.fw_size += |
149 | roundup2(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->ucode_size_bytes))) + (((1 << 12 )) - 1)) & (~((__typeof(((__uint32_t)(hdr->ucode_size_bytes ))))((1 << 12)) - 1))); |
150 | } |
151 | dev_info(adev->dev, "Will use PSP to load VCN firmware\n")do { } while(0); |
152 | } |
153 | |
154 | r = amdgpu_vcn_resume(adev); |
155 | if (r) |
156 | return r; |
157 | |
158 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
159 | vcn_doorbell_index = adev->doorbell_index.vcn.vcn_ring0_1; |
160 | /* get DWORD offset */ |
161 | vcn_doorbell_index = vcn_doorbell_index << 1; |
162 | } |
163 | |
164 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { |
165 | if (adev->vcn.harvest_config & (1 << i)) |
166 | continue; |
167 | |
168 | adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET0x27; |
169 | adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET0x431; |
170 | adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x3b4; |
171 | adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x3b5; |
172 | adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET0x25c; |
173 | adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET0x66; |
174 | |
175 | adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET0xc01d; |
176 | adev->vcn.inst[i].external.scratch9 = SOC15_REG_OFFSET(VCN, i, mmUVD_SCRATCH9)(adev->reg_offset[VCN_HWIP][i][1] + 0x001d); |
177 | adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET0x10; |
178 | adev->vcn.inst[i].external.data0 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA0)(adev->reg_offset[VCN_HWIP][i][1] + 0x0090); |
179 | adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET0x11; |
180 | adev->vcn.inst[i].external.data1 = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_DATA1)(adev->reg_offset[VCN_HWIP][i][1] + 0x0091); |
181 | adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET0x0f; |
182 | adev->vcn.inst[i].external.cmd = SOC15_REG_OFFSET(VCN, i, mmUVD_GPCOM_VCPU_CMD)(adev->reg_offset[VCN_HWIP][i][1] + 0x008f); |
183 | adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET0x29; |
184 | adev->vcn.inst[i].external.nop = SOC15_REG_OFFSET(VCN, i, mmUVD_NO_OP)(adev->reg_offset[VCN_HWIP][i][1] + 0x00a9); |
185 | |
186 | /* VCN DEC TRAP */ |
187 | r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], |
188 | VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT124, &adev->vcn.inst[i].irq); |
189 | if (r) |
190 | return r; |
191 | |
192 | ring = &adev->vcn.inst[i].ring_dec; |
193 | ring->use_doorbell = true1; |
194 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
195 | ring->doorbell_index = vcn_doorbell_index; |
196 | /* NOTE: increment so next VCN engine use next DOORBELL DWORD */ |
197 | vcn_doorbell_index++; |
198 | } else { |
199 | ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i; |
200 | } |
201 | if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 0) |
202 | ring->no_scheduler = true1; |
203 | snprintf(ring->name, sizeof(ring->name), "vcn_dec_%d", i); |
204 | r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, |
205 | AMDGPU_RING_PRIO_DEFAULT1); |
206 | if (r) |
207 | return r; |
208 | |
209 | for (j = 0; j < adev->vcn.num_enc_rings; ++j) { |
210 | /* VCN ENC TRAP */ |
211 | r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[i], |
212 | j + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE119, &adev->vcn.inst[i].irq); |
213 | if (r) |
214 | return r; |
215 | |
216 | ring = &adev->vcn.inst[i].ring_enc[j]; |
217 | ring->use_doorbell = true1; |
218 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
219 | ring->doorbell_index = vcn_doorbell_index; |
220 | /* NOTE: increment so next VCN engine use next DOORBELL DWORD */ |
221 | vcn_doorbell_index++; |
222 | } else { |
223 | ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; |
224 | } |
225 | if (adev->asic_type == CHIP_SIENNA_CICHLID && i != 1) |
226 | ring->no_scheduler = true1; |
227 | snprintf(ring->name, sizeof(ring->name), "vcn_enc_%d.%d", i, j); |
228 | r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0, |
229 | AMDGPU_RING_PRIO_DEFAULT1); |
230 | if (r) |
231 | return r; |
232 | } |
233 | } |
234 | |
235 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
236 | r = amdgpu_virt_alloc_mm_table(adev); |
237 | if (r) |
238 | return r; |
239 | } |
240 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) |
241 | adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; |
242 | |
243 | return 0; |
244 | } |
245 | |
246 | /** |
247 | * vcn_v3_0_sw_fini - sw fini for VCN block |
248 | * |
249 | * @handle: amdgpu_device pointer |
250 | * |
251 | * VCN suspend and free up sw allocation |
252 | */ |
253 | static int vcn_v3_0_sw_fini(void *handle) |
254 | { |
255 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
256 | int r; |
257 | |
258 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) |
259 | amdgpu_virt_free_mm_table(adev); |
260 | |
261 | r = amdgpu_vcn_suspend(adev); |
262 | if (r) |
263 | return r; |
264 | |
265 | r = amdgpu_vcn_sw_fini(adev); |
266 | |
267 | return r; |
268 | } |
269 | |
270 | /** |
271 | * vcn_v3_0_hw_init - start and test VCN block |
272 | * |
273 | * @handle: amdgpu_device pointer |
274 | * |
275 | * Initialize the hardware, boot up the VCPU and do some testing |
276 | */ |
277 | static int vcn_v3_0_hw_init(void *handle) |
278 | { |
279 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
280 | struct amdgpu_ring *ring; |
281 | int i, j, r; |
282 | |
283 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
284 | r = vcn_v3_0_start_sriov(adev); |
285 | if (r) |
286 | goto done; |
287 | |
288 | /* initialize VCN dec and enc ring buffers */ |
289 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
290 | if (adev->vcn.harvest_config & (1 << i)) |
291 | continue; |
292 | |
293 | ring = &adev->vcn.inst[i].ring_dec; |
294 | ring->wptr = 0; |
295 | ring->wptr_old = 0; |
296 | vcn_v3_0_dec_ring_set_wptr(ring); |
297 | ring->sched.ready = true1; |
298 | |
299 | for (j = 0; j < adev->vcn.num_enc_rings; ++j) { |
300 | ring = &adev->vcn.inst[i].ring_enc[j]; |
301 | ring->wptr = 0; |
302 | ring->wptr_old = 0; |
303 | vcn_v3_0_enc_ring_set_wptr(ring); |
304 | ring->sched.ready = true1; |
305 | } |
306 | } |
307 | } else { |
308 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
309 | if (adev->vcn.harvest_config & (1 << i)) |
310 | continue; |
311 | |
312 | ring = &adev->vcn.inst[i].ring_dec; |
313 | |
314 | adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, |
315 | ring->doorbell_index, i); |
316 | |
317 | r = amdgpu_ring_test_helper(ring); |
318 | if (r) |
319 | goto done; |
320 | |
321 | for (j = 0; j < adev->vcn.num_enc_rings; ++j) { |
322 | ring = &adev->vcn.inst[i].ring_enc[j]; |
323 | r = amdgpu_ring_test_helper(ring); |
324 | if (r) |
325 | goto done; |
326 | } |
327 | } |
328 | } |
329 | |
330 | done: |
331 | if (!r) |
332 | DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",printk("\0016" "[" "drm" "] " "VCN decode and encode initialized successfully(under %s).\n" , (adev->pg_flags & (1 << 15))?"DPG Mode":"SPG Mode" ) |
333 | (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode")printk("\0016" "[" "drm" "] " "VCN decode and encode initialized successfully(under %s).\n" , (adev->pg_flags & (1 << 15))?"DPG Mode":"SPG Mode" ); |
334 | |
335 | return r; |
336 | } |
337 | |
338 | /** |
339 | * vcn_v3_0_hw_fini - stop the hardware block |
340 | * |
341 | * @handle: amdgpu_device pointer |
342 | * |
343 | * Stop the VCN block, mark ring as not ready any more |
344 | */ |
345 | static int vcn_v3_0_hw_fini(void *handle) |
346 | { |
347 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
348 | int i; |
349 | |
350 | cancel_delayed_work_sync(&adev->vcn.idle_work); |
351 | |
352 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
353 | if (adev->vcn.harvest_config & (1 << i)) |
354 | continue; |
355 | |
356 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
357 | if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) || |
358 | (adev->vcn.cur_state != AMD_PG_STATE_GATE && |
359 | RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0))) { |
360 | vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE); |
361 | } |
362 | } |
363 | } |
364 | |
365 | return 0; |
366 | } |
367 | |
368 | /** |
369 | * vcn_v3_0_suspend - suspend VCN block |
370 | * |
371 | * @handle: amdgpu_device pointer |
372 | * |
373 | * HW fini and suspend VCN block |
374 | */ |
375 | static int vcn_v3_0_suspend(void *handle) |
376 | { |
377 | int r; |
378 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
379 | |
380 | r = vcn_v3_0_hw_fini(adev); |
381 | if (r) |
382 | return r; |
383 | |
384 | r = amdgpu_vcn_suspend(adev); |
385 | |
386 | return r; |
387 | } |
388 | |
389 | /** |
390 | * vcn_v3_0_resume - resume VCN block |
391 | * |
392 | * @handle: amdgpu_device pointer |
393 | * |
394 | * Resume firmware and hw init VCN block |
395 | */ |
396 | static int vcn_v3_0_resume(void *handle) |
397 | { |
398 | int r; |
399 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
400 | |
401 | r = amdgpu_vcn_resume(adev); |
402 | if (r) |
403 | return r; |
404 | |
405 | r = vcn_v3_0_hw_init(adev); |
406 | |
407 | return r; |
408 | } |
409 | |
410 | /** |
411 | * vcn_v3_0_mc_resume - memory controller programming |
412 | * |
413 | * @adev: amdgpu_device pointer |
414 | * @inst: instance number |
415 | * |
416 | * Let the VCN memory controller know it's offsets |
417 | */ |
418 | static void vcn_v3_0_mc_resume(struct amdgpu_device *adev, int inst) |
419 | { |
420 | uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 - 1)); |
421 | uint32_t offset; |
422 | |
423 | /* cache window 0: fw */ |
424 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
425 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043c)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)), 0) |
426 | (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043c)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_lo)), 0); |
427 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043d)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)), 0) |
428 | (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043d)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst].tmr_mc_addr_hi)), 0); |
429 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0140)), (0), 0); |
430 | offset = 0; |
431 | } else { |
432 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043c)), (((u32)(adev->vcn.inst[inst].gpu_addr))), 0) |
433 | lower_32_bits(adev->vcn.inst[inst].gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043c)), (((u32)(adev->vcn.inst[inst].gpu_addr))), 0); |
434 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043d)), (((u32)(((adev->vcn.inst[inst].gpu_addr) >> 16) >> 16))), 0) |
435 | upper_32_bits(adev->vcn.inst[inst].gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x043d)), (((u32)(((adev->vcn.inst[inst].gpu_addr) >> 16) >> 16))), 0); |
436 | offset = size; |
437 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0140)), (256 >> 3), 0) |
438 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0140)), (256 >> 3), 0); |
439 | } |
440 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0141)), (size), 0); |
441 | |
442 | /* cache window 1: stack */ |
443 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0468)), (((u32)(adev->vcn.inst[inst].gpu_addr + offset ))), 0) |
444 | lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0468)), (((u32)(adev->vcn.inst[inst].gpu_addr + offset ))), 0); |
445 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0469)), (((u32)(((adev->vcn.inst[inst].gpu_addr + offset) >> 16) >> 16))), 0) |
446 | upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0469)), (((u32)(((adev->vcn.inst[inst].gpu_addr + offset) >> 16) >> 16))), 0); |
447 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET1, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0142)), (0), 0); |
448 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0143)), ((128*1024)), 0); |
449 | |
450 | /* cache window 2: context */ |
451 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x046c)), (((u32)(adev->vcn.inst[inst].gpu_addr + offset + (128*1024)))), 0) |
452 | lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x046c)), (((u32)(adev->vcn.inst[inst].gpu_addr + offset + (128*1024)))), 0); |
453 | WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x046d)), (((u32)(((adev->vcn.inst[inst].gpu_addr + offset + (128*1024)) >> 16) >> 16))), 0) |
454 | upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x046d)), (((u32)(((adev->vcn.inst[inst].gpu_addr + offset + (128*1024)) >> 16) >> 16))), 0); |
455 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_OFFSET2, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0144)), (0), 0); |
456 | WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0145)), ((512*1024)), 0); |
457 | } |
458 | |
459 | static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool_Bool indirect) |
460 | { |
461 | uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 - 1)); |
462 | uint32_t offset; |
463 | |
464 | /* cache window 0: fw */ |
465 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
466 | if (!indirect) { |
467 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode [AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware .ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while (0) |
468 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode [AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware .ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while (0) |
469 | (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode [AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware .ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while (0); |
470 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode [AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware .ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while (0) |
471 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode [AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware .ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while (0) |
472 | (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((adev->firmware.ucode [AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware .ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while (0); |
473 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
474 | VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
475 | } else { |
476 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
477 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
478 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
479 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
480 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
481 | VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
482 | } |
483 | offset = 0; |
484 | } else { |
485 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr))), 0); amdgpu_device_wreg(adev, ((adev-> reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range, aon_range, aon1_range; addr = (adev ->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr ) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr)); } } while (0) |
486 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr))), 0); amdgpu_device_wreg(adev, ((adev-> reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range, aon_range, aon1_range; addr = (adev ->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr ) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr)); } } while (0) |
487 | lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr))), 0); amdgpu_device_wreg(adev, ((adev-> reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range, aon_range, aon1_range; addr = (adev ->reg_offset[VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr ) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr)); } } while (0); |
488 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr) >> 16) >> 16))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev-> vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while (0) |
489 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr) >> 16) >> 16))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev-> vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while (0) |
490 | upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr) >> 16) >> 16))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x043d ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x043d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev-> vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while (0); |
491 | offset = size; |
492 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3 ; } } while (0) |
493 | VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3 ; } } while (0) |
494 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0140 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0140); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3 ; } } while (0); |
495 | } |
496 | |
497 | if (!indirect) |
498 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (size), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0141 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0141); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = size; } } while (0) |
499 | VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (size), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0141 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0141); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = size; } } while (0); |
500 | else |
501 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0141 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0141); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
502 | VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0141 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0141); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
503 | |
504 | /* cache window 1: stack */ |
505 | if (!indirect) { |
506 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr + offset))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0468 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0468); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr + offset)); } } while (0) |
507 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr + offset))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0468 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0468); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr + offset)); } } while (0) |
508 | lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr + offset))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0468 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0468); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr + offset)); } } while (0); |
509 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr + offset) >> 16) >> 16))), 0) ; amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range, aon_range , aon1_range; addr = (adev->reg_offset[VCN_HWIP][inst_idx] [1] + 0x0469); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr ) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800 )) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))) )); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + ( 0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + ( 0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn. inst[inst_idx].dpg_sram_curr_addr++ = ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0469 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(( (adev->vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16)); } } while (0) |
510 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr + offset) >> 16) >> 16))), 0) ; amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range, aon_range , aon1_range; addr = (adev->reg_offset[VCN_HWIP][inst_idx] [1] + 0x0469); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr ) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800 )) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))) )); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + ( 0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + ( 0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn. inst[inst_idx].dpg_sram_curr_addr++ = ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0469 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(( (adev->vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16)); } } while (0) |
511 | upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr + offset) >> 16) >> 16))), 0) ; amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range, aon_range , aon1_range; addr = (adev->reg_offset[VCN_HWIP][inst_idx] [1] + 0x0469); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr ) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800 )) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))) )); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + ( 0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + ( 0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn. inst[inst_idx].dpg_sram_curr_addr++ = ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0469 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(( (adev->vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16)); } } while (0); |
512 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0142 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0142); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
513 | VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0142 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0142); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
514 | } else { |
515 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0468 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0468); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
516 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0468 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0468); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
517 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0469 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0469); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
518 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0469 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0469); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
519 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0142 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0142); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
520 | VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0142 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0142); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
521 | } |
522 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((128*1024)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0143 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0143); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (128*1024); } } while (0) |
523 | VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((128*1024)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0143 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0143); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (128*1024); } } while (0); |
524 | |
525 | /* cache window 2: context */ |
526 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr + offset + (128*1024)))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x046c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x046c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while (0) |
527 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr + offset + (128*1024)))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x046c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x046c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while (0) |
528 | lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst [inst_idx].gpu_addr + offset + (128*1024)))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x046c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x046c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev-> vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while (0); |
529 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr + offset + (128*1024)) >> 16) >> 16))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x046d); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x046d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev-> vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16 ) >> 16)); } } while (0) |
530 | VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr + offset + (128*1024)) >> 16) >> 16))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x046d); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x046d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev-> vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16 ) >> 16)); } } while (0) |
531 | upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst [inst_idx].gpu_addr + offset + (128*1024)) >> 16) >> 16))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x046d); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x046d); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev-> vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16 ) >> 16)); } } while (0); |
532 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0144 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0144); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
533 | VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0144 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0144); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
534 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((512*1024)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0145 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0145); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (512*1024); } } while (0) |
535 | VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), ((512*1024)), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0145 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0145); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (512*1024); } } while (0); |
536 | |
537 | /* non-cache window */ |
538 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0438 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0438); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
539 | VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0438 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0438); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
540 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0439 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0439); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
541 | VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0439 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0439); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
542 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0152 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0152); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
543 | VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0152 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0152); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
544 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0153 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0153); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
545 | VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0153 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0153); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
546 | } |
547 | |
548 | static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) |
549 | { |
550 | uint32_t data = 0; |
551 | |
552 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN(1 << 14)) { |
553 | data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT0x0 |
554 | | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT0x2 |
555 | | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT0x4 |
556 | | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT0x6 |
557 | | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT0x8 |
558 | | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT0xa |
559 | | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT0xc |
560 | | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT0xe |
561 | | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT0x10 |
562 | | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT0x12 |
563 | | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT0x14 |
564 | | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT0x18 |
565 | | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT0x1a |
566 | | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT0x1c); |
567 | |
568 | WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0000)), (data), 0); |
569 | SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x3F3FFFFF)) != (UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 )) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev ->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); loop--; if ( !loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst, "mmUVD_PGFSM_STATUS", (unsigned)UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 , (unsigned)(tmp_ & (0x3F3FFFFF))); ret = -60; break; } } } while (0); ret; }) |
570 | UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0, 0x3F3FFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x3F3FFFFF)) != (UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 )) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev ->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); loop--; if ( !loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst, "mmUVD_PGFSM_STATUS", (unsigned)UVD_PGFSM_STATUS__UVDM_UVDU_UVDLM_PWR_ON_3_0 , (unsigned)(tmp_ & (0x3F3FFFFF))); ret = -60; break; } } } while (0); ret; }); |
571 | } else { |
572 | data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT0x0 |
573 | | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT0x2 |
574 | | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT0x4 |
575 | | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT0x6 |
576 | | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT0x8 |
577 | | 1 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT0xa |
578 | | 1 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT0xc |
579 | | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT0xe |
580 | | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT0x10 |
581 | | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT0x12 |
582 | | 1 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT0x14 |
583 | | 1 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT0x18 |
584 | | 1 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT0x1a |
585 | | 1 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT0x1c); |
586 | WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0000)), (data), 0); |
587 | SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x3F3FFFFF)) != (0)) { if (old_ != tmp_) { loop = adev ->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst, "mmUVD_PGFSM_STATUS", (unsigned)0, (unsigned)(tmp_ & (0x3F3FFFFF))); ret = -60; break; } } } while (0); ret; }); |
588 | } |
589 | |
590 | data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x0004), 0); |
591 | data &= ~0x103; |
592 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN(1 << 14)) |
593 | data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | |
594 | UVD_POWER_STATUS__UVD_PG_EN_MASK0x00000100L; |
595 | |
596 | WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0004)), (data), 0); |
597 | } |
598 | |
599 | static void vcn_v3_0_enable_static_power_gating(struct amdgpu_device *adev, int inst) |
600 | { |
601 | uint32_t data; |
602 | |
603 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN(1 << 14)) { |
604 | /* Before power off, this indicator has to be turned on */ |
605 | data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x0004), 0); |
606 | data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK0x00000003L; |
607 | data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; |
608 | WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0004)), (data), 0); |
609 | |
610 | data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT0x0 |
611 | | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT0x2 |
612 | | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT0x4 |
613 | | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT0x6 |
614 | | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT0x8 |
615 | | 2 << UVD_PGFSM_CONFIG__UVDIRL_PWR_CONFIG__SHIFT0xa |
616 | | 2 << UVD_PGFSM_CONFIG__UVDLM_PWR_CONFIG__SHIFT0xc |
617 | | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT0xe |
618 | | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT0x10 |
619 | | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT0x12 |
620 | | 2 << UVD_PGFSM_CONFIG__UVDAB_PWR_CONFIG__SHIFT0x14 |
621 | | 2 << UVD_PGFSM_CONFIG__UVDATD_PWR_CONFIG__SHIFT0x18 |
622 | | 2 << UVD_PGFSM_CONFIG__UVDNA_PWR_CONFIG__SHIFT0x1a |
623 | | 2 << UVD_PGFSM_CONFIG__UVDNB_PWR_CONFIG__SHIFT0x1c); |
624 | WREG32_SOC15(VCN, inst, mmUVD_PGFSM_CONFIG, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0000)), (data), 0); |
625 | |
626 | data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT0x0 |
627 | | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT0x2 |
628 | | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT0x4 |
629 | | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT0x6 |
630 | | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT0x8 |
631 | | 2 << UVD_PGFSM_STATUS__UVDIRL_PWR_STATUS__SHIFT0xa |
632 | | 2 << UVD_PGFSM_STATUS__UVDLM_PWR_STATUS__SHIFT0xc |
633 | | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT0xe |
634 | | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT0x10 |
635 | | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT0x12 |
636 | | 2 << UVD_PGFSM_STATUS__UVDAB_PWR_STATUS__SHIFT0x14 |
637 | | 2 << UVD_PGFSM_STATUS__UVDATD_PWR_STATUS__SHIFT0x18 |
638 | | 2 << UVD_PGFSM_STATUS__UVDNA_PWR_STATUS__SHIFT0x1a |
639 | | 2 << UVD_PGFSM_STATUS__UVDNB_PWR_STATUS__SHIFT0x1c); |
640 | SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, data, 0x3F3FFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x3F3FFFFF)) != (data)) { if (old_ != tmp_) { loop = adev ->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0001), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst, "mmUVD_PGFSM_STATUS", (unsigned)data, (unsigned)(tmp_ & (0x3F3FFFFF))); ret = -60; break; } } } while (0); ret ; }); |
641 | } |
642 | } |
643 | |
644 | /** |
645 | * vcn_v3_0_disable_clock_gating - disable VCN clock gating |
646 | * |
647 | * @adev: amdgpu_device pointer |
648 | * @inst: instance number |
649 | * |
650 | * Disable clock gating for VCN block |
651 | */ |
652 | static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst) |
653 | { |
654 | uint32_t data; |
655 | |
656 | /* VCN disable CGC */ |
657 | data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008a), 0); |
658 | if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1 << 24)) |
659 | data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0; |
660 | else |
661 | data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK0x00000001L; |
662 | data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2; |
663 | data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6; |
664 | WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008a)), (data), 0); |
665 | |
666 | data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x0088), 0); |
667 | data &= ~(UVD_CGC_GATE__SYS_MASK0x00000001L |
668 | | UVD_CGC_GATE__UDEC_MASK0x00000002L |
669 | | UVD_CGC_GATE__MPEG2_MASK0x00000004L |
670 | | UVD_CGC_GATE__REGS_MASK0x00000008L |
671 | | UVD_CGC_GATE__RBC_MASK0x00000010L |
672 | | UVD_CGC_GATE__LMI_MC_MASK0x00000020L |
673 | | UVD_CGC_GATE__LMI_UMC_MASK0x00000040L |
674 | | UVD_CGC_GATE__IDCT_MASK0x00000080L |
675 | | UVD_CGC_GATE__MPRD_MASK0x00000100L |
676 | | UVD_CGC_GATE__MPC_MASK0x00000200L |
677 | | UVD_CGC_GATE__LBSI_MASK0x00000400L |
678 | | UVD_CGC_GATE__LRBBM_MASK0x00000800L |
679 | | UVD_CGC_GATE__UDEC_RE_MASK0x00001000L |
680 | | UVD_CGC_GATE__UDEC_CM_MASK0x00002000L |
681 | | UVD_CGC_GATE__UDEC_IT_MASK0x00004000L |
682 | | UVD_CGC_GATE__UDEC_DB_MASK0x00008000L |
683 | | UVD_CGC_GATE__UDEC_MP_MASK0x00010000L |
684 | | UVD_CGC_GATE__WCB_MASK0x00020000L |
685 | | UVD_CGC_GATE__VCPU_MASK0x00040000L |
686 | | UVD_CGC_GATE__MMSCH_MASK0x00100000L); |
687 | |
688 | WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x0088)), (data), 0); |
689 | |
690 | SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0088), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0xFFFFFFFF)) != (0)) { if (old_ != tmp_) { loop = adev ->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst][1] + 0x0088), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst, "mmUVD_CGC_GATE", (unsigned)0, (unsigned)(tmp_ & ( 0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; }); |
691 | |
692 | data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008a), 0); |
693 | data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L |
694 | | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L |
695 | | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L |
696 | | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L |
697 | | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L |
698 | | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L |
699 | | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L |
700 | | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L |
701 | | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L |
702 | | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L |
703 | | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L |
704 | | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L |
705 | | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L |
706 | | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L |
707 | | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L |
708 | | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L |
709 | | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L |
710 | | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L |
711 | | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L |
712 | | UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L); |
713 | WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008a)), (data), 0); |
714 | |
715 | data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008c), 0); |
716 | data |= (UVD_SUVD_CGC_GATE__SRE_MASK0x00000001L |
717 | | UVD_SUVD_CGC_GATE__SIT_MASK0x00000002L |
718 | | UVD_SUVD_CGC_GATE__SMP_MASK0x00000004L |
719 | | UVD_SUVD_CGC_GATE__SCM_MASK0x00000008L |
720 | | UVD_SUVD_CGC_GATE__SDB_MASK0x00000010L |
721 | | UVD_SUVD_CGC_GATE__SRE_H264_MASK0x00000020L |
722 | | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK0x00000040L |
723 | | UVD_SUVD_CGC_GATE__SIT_H264_MASK0x00000080L |
724 | | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK0x00000100L |
725 | | UVD_SUVD_CGC_GATE__SCM_H264_MASK0x00000200L |
726 | | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK0x00000400L |
727 | | UVD_SUVD_CGC_GATE__SDB_H264_MASK0x00000800L |
728 | | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK0x00001000L |
729 | | UVD_SUVD_CGC_GATE__SCLR_MASK0x00002000L |
730 | | UVD_SUVD_CGC_GATE__ENT_MASK0x00008000L |
731 | | UVD_SUVD_CGC_GATE__IME_MASK0x00010000L |
732 | | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK0x00020000L |
733 | | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK0x00040000L |
734 | | UVD_SUVD_CGC_GATE__SITE_MASK0x00080000L |
735 | | UVD_SUVD_CGC_GATE__SRE_VP9_MASK0x00100000L |
736 | | UVD_SUVD_CGC_GATE__SCM_VP9_MASK0x00200000L |
737 | | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK0x00400000L |
738 | | UVD_SUVD_CGC_GATE__SDB_VP9_MASK0x00800000L |
739 | | UVD_SUVD_CGC_GATE__IME_HEVC_MASK0x01000000L |
740 | | UVD_SUVD_CGC_GATE__EFC_MASK0x02000000L |
741 | | UVD_SUVD_CGC_GATE__SAOE_MASK0x04000000L |
742 | | UVD_SUVD_CGC_GATE__SRE_AV1_MASK0x08000000L |
743 | | UVD_SUVD_CGC_GATE__FBC_PCLK_MASK0x10000000L |
744 | | UVD_SUVD_CGC_GATE__FBC_CCLK_MASK0x20000000L |
745 | | UVD_SUVD_CGC_GATE__SCM_AV1_MASK0x40000000L |
746 | | UVD_SUVD_CGC_GATE__SMPA_MASK0x80000000L); |
747 | WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008c)), (data), 0); |
748 | |
749 | data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x00ff), 0); |
750 | data |= (UVD_SUVD_CGC_GATE2__MPBE0_MASK0x00000001L |
751 | | UVD_SUVD_CGC_GATE2__MPBE1_MASK0x00000002L |
752 | | UVD_SUVD_CGC_GATE2__SIT_AV1_MASK0x00000004L |
753 | | UVD_SUVD_CGC_GATE2__SDB_AV1_MASK0x00000008L |
754 | | UVD_SUVD_CGC_GATE2__MPC1_MASK0x00000010L); |
755 | WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_GATE2, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x00ff)), (data), 0); |
756 | |
757 | data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008e), 0); |
758 | data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK0x00000001L |
759 | | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK0x00000002L |
760 | | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK0x00000004L |
761 | | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK0x00000008L |
762 | | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK0x00000010L |
763 | | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK0x00000020L |
764 | | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK0x00000080L |
765 | | UVD_SUVD_CGC_CTRL__IME_MODE_MASK0x00000100L |
766 | | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK0x00000200L |
767 | | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK0x00000400L |
768 | | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK0x00000800L |
769 | | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK0x00001000L |
770 | | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK0x00002000L |
771 | | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK0x00004000L |
772 | | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK0x00008000L |
773 | | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK0x00010000L |
774 | | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK0x00020000L |
775 | | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK0x10000000L |
776 | | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK0x20000000L); |
777 | WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008e)), (data), 0); |
778 | } |
779 | |
780 | static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev, |
781 | uint8_t sram_sel, int inst_idx, uint8_t indirect) |
782 | { |
783 | uint32_t reg_data = 0; |
784 | |
785 | /* enable sw clock gating control */ |
786 | if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1 << 24)) |
787 | reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0; |
788 | else |
789 | reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0; |
790 | reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2; |
791 | reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6; |
792 | reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L | |
793 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L | |
794 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L | |
795 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L | |
796 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L | |
797 | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L | |
798 | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L | |
799 | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L | |
800 | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L | |
801 | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L | |
802 | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L | |
803 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L | |
804 | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L | |
805 | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L | |
806 | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L | |
807 | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L | |
808 | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L | |
809 | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L | |
810 | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L | |
811 | UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L); |
812 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (reg_data), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x008a ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x008a); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = reg_data; } } while (0) |
813 | VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (reg_data), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x008a ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x008a); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = reg_data; } } while (0); |
814 | |
815 | /* turn off clock gating */ |
816 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0088 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0088); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
817 | VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0088 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0088); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
818 | |
819 | /* turn on SUVD clock gating */ |
820 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (1), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x008c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x008c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 1; } } while ( 0) |
821 | VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (1), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x008c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x008c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 1; } } while ( 0); |
822 | |
823 | /* turn on sw mode in UVD_SUVD_CGC_CTRL */ |
824 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x008e ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x008e); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
825 | VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x008e ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x008e); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
826 | } |
827 | |
828 | /** |
829 | * vcn_v3_0_enable_clock_gating - enable VCN clock gating |
830 | * |
831 | * @adev: amdgpu_device pointer |
832 | * @inst: instance number |
833 | * |
834 | * Enable clock gating for VCN block |
835 | */ |
836 | static void vcn_v3_0_enable_clock_gating(struct amdgpu_device *adev, int inst) |
837 | { |
838 | uint32_t data; |
839 | |
840 | /* enable VCN CGC */ |
841 | data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008a), 0); |
842 | if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1 << 24)) |
843 | data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0; |
844 | else |
845 | data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0; |
846 | data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2; |
847 | data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6; |
848 | WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008a)), (data), 0); |
849 | |
850 | data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008a), 0); |
851 | data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L |
852 | | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L |
853 | | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L |
854 | | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L |
855 | | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L |
856 | | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L |
857 | | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L |
858 | | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L |
859 | | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L |
860 | | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L |
861 | | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L |
862 | | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L |
863 | | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L |
864 | | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L |
865 | | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L |
866 | | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L |
867 | | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L |
868 | | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L |
869 | | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L |
870 | | UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L); |
871 | WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008a)), (data), 0); |
872 | |
873 | data = RREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst] [1] + 0x008e), 0); |
874 | data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK0x00000001L |
875 | | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK0x00000002L |
876 | | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK0x00000004L |
877 | | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK0x00000008L |
878 | | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK0x00000010L |
879 | | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK0x00000020L |
880 | | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK0x00000080L |
881 | | UVD_SUVD_CGC_CTRL__IME_MODE_MASK0x00000100L |
882 | | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK0x00000200L |
883 | | UVD_SUVD_CGC_CTRL__EFC_MODE_MASK0x00000400L |
884 | | UVD_SUVD_CGC_CTRL__SAOE_MODE_MASK0x00000800L |
885 | | UVD_SUVD_CGC_CTRL__SMPA_MODE_MASK0x00001000L |
886 | | UVD_SUVD_CGC_CTRL__MPBE0_MODE_MASK0x00002000L |
887 | | UVD_SUVD_CGC_CTRL__MPBE1_MODE_MASK0x00004000L |
888 | | UVD_SUVD_CGC_CTRL__SIT_AV1_MODE_MASK0x00008000L |
889 | | UVD_SUVD_CGC_CTRL__SDB_AV1_MODE_MASK0x00010000L |
890 | | UVD_SUVD_CGC_CTRL__MPC1_MODE_MASK0x00020000L |
891 | | UVD_SUVD_CGC_CTRL__FBC_PCLK_MASK0x10000000L |
892 | | UVD_SUVD_CGC_CTRL__FBC_CCLK_MASK0x20000000L); |
893 | WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst ][1] + 0x008e)), (data), 0); |
894 | } |
895 | |
896 | static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool_Bool indirect) |
897 | { |
898 | struct amdgpu_ring *ring; |
899 | uint32_t rb_bufsz, tmp; |
900 | |
901 | /* disable register anti-hang mechanism */ |
902 | WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000003L ); tmp_ |= ((1) & ~(~0x00000003L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0) |
903 | ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000003L ); tmp_ |= ((1) & ~(~0x00000003L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0); |
904 | /* enable dynamic power gating mode */ |
905 | tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); |
906 | tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK0x00000004L; |
907 | tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK0x00000100L; |
908 | WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004)), (tmp), 0); |
909 | |
910 | if (indirect) |
911 | adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t*)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr; |
912 | |
913 | /* enable clock gating */ |
914 | vcn_v3_0_clock_gating_dpg_mode(adev, 0, inst_idx, indirect); |
915 | |
916 | /* enable VCPU clock */ |
917 | tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT0x14); |
918 | tmp |= UVD_VCPU_CNTL__CLK_EN_MASK0x00000200L; |
919 | tmp |= UVD_VCPU_CNTL__BLK_RST_MASK0x10000000L; |
920 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0156 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0156); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0) |
921 | VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0156 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0156); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0); |
922 | |
923 | /* disable master interupt */ |
924 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00a1 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00a1); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
925 | VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00a1 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00a1); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
926 | |
927 | /* setup mmUVD_LMI_CTRL */ |
928 | tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK0x00000100L | |
929 | UVD_LMI_CTRL__REQ_MODE_MASK0x00000200L | |
930 | UVD_LMI_CTRL__CRC_RESET_MASK0x00004000L | |
931 | UVD_LMI_CTRL__MASK_MC_URGENT_MASK0x00001000L | |
932 | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK0x00002000L | |
933 | UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK0x00200000L | |
934 | (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT0x0) | |
935 | 0x00100000L); |
936 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x04a8 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x04a8); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0) |
937 | VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x04a8 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x04a8); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0); |
938 | |
939 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02cc ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02cc); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3 ; } } while (0) |
940 | VCN, inst_idx, mmUVD_MPC_CNTL),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02cc ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02cc); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3 ; } } while (0) |
941 | 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02cc ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02cc); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3 ; } } while (0); |
942 | |
943 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
944 | VCN, inst_idx, mmUVD_MPC_SET_MUXA0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
945 | ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
946 | (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
947 | (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
948 | (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02ce); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0); |
949 | |
950 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
951 | VCN, inst_idx, mmUVD_MPC_SET_MUXB0),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
952 | ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
953 | (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
954 | (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0) |
955 | (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP] [inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range , aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((( (0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr ) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d0); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18)); } } while (0); |
956 | |
957 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02d2 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d2); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while ( 0) |
958 | VCN, inst_idx, mmUVD_MPC_SET_MUX),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02d2 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d2); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while ( 0) |
959 | ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02d2 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d2); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while ( 0) |
960 | (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02d2 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d2); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while ( 0) |
961 | (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02d2 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x02d2); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while ( 0); |
962 | |
963 | vcn_v3_0_mc_resume_dpg_mode(adev, inst_idx, indirect); |
964 | |
965 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x10), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x026c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x026c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x10; } } while (0) |
966 | VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x10), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x026c ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x026c); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x10; } } while (0); |
967 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x026b ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x026b); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x3; } } while (0) |
968 | VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x3), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x026b ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x026b); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x3; } } while (0); |
969 | |
970 | /* enable LMI MC and UMC channels */ |
971 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x04a6 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x04a6); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
972 | VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x04a6 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x04a6); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
973 | |
974 | /* unblock VCPU register access */ |
975 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00c6 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00c6); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0) |
976 | VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00c6 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00c6); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while ( 0); |
977 | |
978 | tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT0x14); |
979 | tmp |= UVD_VCPU_CNTL__CLK_EN_MASK0x00000200L; |
980 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0156 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0156); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0) |
981 | VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0156 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0156); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0); |
982 | |
983 | /* enable master interrupt */ |
984 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00a1 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00a1); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; } } while (0) |
985 | VCN, inst_idx, mmUVD_MASTINT_EN),do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00a1 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00a1); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; } } while (0) |
986 | UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00a1 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x00a1); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; } } while (0); |
987 | |
988 | /* add nop to workaround PSP size check */ |
989 | WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0156 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0156); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0) |
990 | VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { amdgpu_device_wreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0012)), (tmp), 0); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011) ), ((0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset , addr; _Bool video_range, video1_range, aon_range, aon1_range ; addr = (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0156 ); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200 )) && ((0xFFFFF & addr) < ((0x48200 + 0x2600)) ))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + ( 0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = (0xFFFFF & addr); internal_reg_offset >>= 2; }) << 0x10)), 0); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr ++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range , video1_range, aon_range, aon1_range; addr = (adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0156); addr <<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))))); video1_range = ((( (0xFFFFF & addr) >= (0x48200)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF & addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range ) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + ( 0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset = ( 0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev ->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while (0); |
991 | |
992 | if (indirect) |
993 | psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, |
994 | (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - |
995 | (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr)); |
996 | |
997 | ring = &adev->vcn.inst[inst_idx].ring_dec; |
998 | /* force RBC into idle state */ |
999 | rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size); |
1000 | tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) << 0x0))); |
1001 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) << 0x8))); |
1002 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) << 0x10))); |
1003 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) << 0x18))); |
1004 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c))); |
1005 | WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02de)), (tmp), 0); |
1006 | |
1007 | /* Stall DPG before WPTR/RPTR reset */ |
1008 | WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004) ), (tmp_), 0); } while (0) |
1009 | UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004) ), (tmp_), 0); } while (0) |
1010 | ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004) ), (tmp_), 0); } while (0); |
1011 | |
1012 | /* set the write pointer delay */ |
1013 | WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e6)), (0), 0); |
1014 | |
1015 | /* set the wb address */ |
1016 | WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02df)), ((((u32)(((ring->gpu_addr) >> 16) >> 16)) >> 2)), 0) |
1017 | (upper_32_bits(ring->gpu_addr) >> 2))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02df)), ((((u32)(((ring->gpu_addr) >> 16) >> 16)) >> 2)), 0); |
1018 | |
1019 | /* programm the RB_BASE for ring buffer */ |
1020 | WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0432)), (((u32)(ring->gpu_addr))), 0) |
1021 | lower_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0432)), (((u32)(ring->gpu_addr))), 0); |
1022 | WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0) |
1023 | upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0); |
1024 | |
1025 | /* Initialize the ring buffer's read and write pointers */ |
1026 | WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e0)), (0), 0); |
1027 | |
1028 | WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0016)), (0), 0); |
1029 | |
1030 | ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e0), 0); |
1031 | WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e1)), (((u32)(ring->wptr))), 0) |
1032 | lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e1)), (((u32)(ring->wptr))), 0); |
1033 | |
1034 | /* Unstall DPG */ |
1035 | WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0) |
1036 | 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0); |
1037 | |
1038 | return 0; |
1039 | } |
1040 | |
1041 | static int vcn_v3_0_start(struct amdgpu_device *adev) |
1042 | { |
1043 | struct amdgpu_ring *ring; |
1044 | uint32_t rb_bufsz, tmp; |
1045 | int i, j, k, r; |
1046 | |
1047 | if (adev->pm.dpm_enabled) |
1048 | amdgpu_dpm_enable_uvd(adev, true1); |
1049 | |
1050 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1051 | if (adev->vcn.harvest_config & (1 << i)) |
1052 | continue; |
1053 | |
1054 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)){ |
1055 | r = vcn_v3_0_start_dpg_mode(adev, i, adev->vcn.indirect_sram); |
1056 | continue; |
1057 | } |
1058 | |
1059 | /* disable VCN power gating */ |
1060 | vcn_v3_0_disable_static_power_gating(adev, i); |
1061 | |
1062 | /* set VCN status busy */ |
1063 | tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0) | UVD_STATUS__UVD_BUSY; |
1064 | WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0080)), (tmp), 0); |
1065 | |
1066 | /*SW clock gating */ |
1067 | vcn_v3_0_disable_clock_gating(adev, i); |
1068 | |
1069 | /* enable VCPU clock */ |
1070 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x00000200L); tmp_ |= ((0x00000200L) & ~(~0x00000200L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0) |
1071 | UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x00000200L); tmp_ |= ((0x00000200L) & ~(~0x00000200L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0); |
1072 | |
1073 | /* disable master interrupt */ |
1074 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_ |= ((0) & ~(~0x00000002L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_), 0); } while (0) |
1075 | ~UVD_MASTINT_EN__VCPU_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_ |= ((0) & ~(~0x00000002L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_), 0); } while (0); |
1076 | |
1077 | /* enable LMI MC and UMC channels */ |
1078 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x04a6)), 0); tmp_ &= (~0x00000100L); tmp_ |= ((0) & ~(~0x00000100L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp_), 0); } while (0) |
1079 | ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x04a6)), 0); tmp_ &= (~0x00000100L); tmp_ |= ((0) & ~(~0x00000100L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp_), 0); } while (0); |
1080 | |
1081 | tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0084), 0); |
1082 | tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK0x00000004L; |
1083 | tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK0x00002000L; |
1084 | WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0084)), (tmp), 0); |
1085 | |
1086 | /* setup mmUVD_LMI_CTRL */ |
1087 | tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a8), 0); |
1088 | WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04a8)), (tmp | 0x00000100L | 0x00001000L | 0x00002000L | 0x00200000L), 0) |
1089 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04a8)), (tmp | 0x00000100L | 0x00001000L | 0x00002000L | 0x00200000L), 0) |
1090 | UVD_LMI_CTRL__MASK_MC_URGENT_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04a8)), (tmp | 0x00000100L | 0x00001000L | 0x00002000L | 0x00200000L), 0) |
1091 | UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04a8)), (tmp | 0x00000100L | 0x00001000L | 0x00002000L | 0x00200000L), 0) |
1092 | UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04a8)), (tmp | 0x00000100L | 0x00001000L | 0x00002000L | 0x00200000L), 0); |
1093 | |
1094 | /* setup mmUVD_MPC_CNTL */ |
1095 | tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x02cc), 0); |
1096 | tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK0x00000038L; |
1097 | tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT0x3; |
1098 | WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02cc)), (tmp), 0); |
1099 | |
1100 | /* setup UVD_MPC_SET_MUXA0 */ |
1101 | WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1102 | ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1103 | (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1104 | (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1105 | (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02ce)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); |
1106 | |
1107 | /* setup UVD_MPC_SET_MUXB0 */ |
1108 | WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1109 | ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1110 | (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1111 | (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0) |
1112 | (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d0)), (((0x1 << 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 << 0x18))), 0); |
1113 | |
1114 | /* setup mmUVD_MPC_SET_MUX */ |
1115 | WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0) |
1116 | ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0) |
1117 | (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0) |
1118 | (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02d2)), (((0x0 << 0x0) | (0x1 << 0x3) | (0x2 << 0x6))), 0); |
1119 | |
1120 | vcn_v3_0_mc_resume(adev, i); |
1121 | |
1122 | /* VCN global tiling registers */ |
1123 | WREG32_SOC15(VCN, i, mmUVD_GFX10_ADDR_CONFIG,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x004a)), (adev->gfx.config.gb_addr_config), 0) |
1124 | adev->gfx.config.gb_addr_config)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x004a)), (adev->gfx.config.gb_addr_config), 0); |
1125 | |
1126 | /* unblock VCPU register access */ |
1127 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_ |= ((0) & ~(~0x00000008L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_), 0); } while (0) |
1128 | ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_ |= ((0) & ~(~0x00000008L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_), 0); } while (0); |
1129 | |
1130 | /* release VCPU reset to boot */ |
1131 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while (0) |
1132 | ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while (0); |
1133 | |
1134 | for (j = 0; j < 10; ++j) { |
1135 | uint32_t status; |
1136 | |
1137 | for (k = 0; k < 100; ++k) { |
1138 | status = RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); |
1139 | if (status & 2) |
1140 | break; |
1141 | mdelay(10); |
1142 | } |
1143 | r = 0; |
1144 | if (status & 2) |
1145 | break; |
1146 | |
1147 | DRM_ERROR("VCN[%d] decode not responding, trying to reset the VCPU!!!\n", i)__drm_err("VCN[%d] decode not responding, trying to reset the VCPU!!!\n" , i); |
1148 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0) |
1149 | UVD_VCPU_CNTL__BLK_RST_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0) |
1150 | ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0); |
1151 | mdelay(10); |
1152 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while (0) |
1153 | ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev ->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while (0); |
1154 | |
1155 | mdelay(10); |
1156 | r = -1; |
1157 | } |
1158 | |
1159 | if (r) { |
1160 | DRM_ERROR("VCN[%d] decode not responding, giving up!!!\n", i)__drm_err("VCN[%d] decode not responding, giving up!!!\n", i); |
1161 | return r; |
1162 | } |
1163 | |
1164 | /* enable master interrupt */ |
1165 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_ |= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_ ), 0); } while (0) |
1166 | UVD_MASTINT_EN__VCPU_EN_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_ |= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_ ), 0); } while (0) |
1167 | ~UVD_MASTINT_EN__VCPU_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_ |= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_ ), 0); } while (0); |
1168 | |
1169 | /* clear the busy bit of VCN_STATUS */ |
1170 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0080)), 0); tmp_ &= (~(2 << 0x1 )); tmp_ |= ((0) & ~(~(2 << 0x1))); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp_ ), 0); } while (0) |
1171 | ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT))do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0080)), 0); tmp_ &= (~(2 << 0x1 )); tmp_ |= ((0) & ~(~(2 << 0x1))); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp_ ), 0); } while (0); |
1172 | |
1173 | WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04b0)), (0), 0); |
1174 | |
1175 | ring = &adev->vcn.inst[i].ring_dec; |
1176 | /* force RBC into idle state */ |
1177 | rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size); |
1178 | tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) << 0x0))); |
1179 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) << 0x8))); |
1180 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) << 0x10))); |
1181 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) << 0x18))); |
1182 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c))); |
1183 | WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02de)), (tmp), 0); |
1184 | |
1185 | /* programm the RB_BASE for ring buffer */ |
1186 | WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0432)), (((u32)(ring->gpu_addr))), 0) |
1187 | lower_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0432)), (((u32)(ring->gpu_addr))), 0); |
1188 | WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0) |
1189 | upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0433)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0); |
1190 | |
1191 | /* Initialize the ring buffer's read and write pointers */ |
1192 | WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02e0)), (0), 0); |
1193 | |
1194 | ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x02e0), 0); |
1195 | WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02e1)), (((u32)(ring->wptr))), 0) |
1196 | lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x02e1)), (((u32)(ring->wptr))), 0); |
1197 | ring = &adev->vcn.inst[i].ring_enc[0]; |
1198 | WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00ad)), (((u32)(ring->wptr))), 0); |
1199 | WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00ae)), (((u32)(ring->wptr))), 0); |
1200 | WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00aa)), (ring->gpu_addr), 0); |
1201 | WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00ab)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0); |
1202 | WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00ac)), (ring->ring_size / 4), 0); |
1203 | |
1204 | ring = &adev->vcn.inst[i].ring_enc[1]; |
1205 | WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00b2)), (((u32)(ring->wptr))), 0); |
1206 | WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00b3)), (((u32)(ring->wptr))), 0); |
1207 | WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00af)), (ring->gpu_addr), 0); |
1208 | WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00b0)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0); |
1209 | WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x00b1)), (ring->ring_size / 4), 0); |
1210 | } |
1211 | |
1212 | return 0; |
1213 | } |
1214 | |
1215 | static int vcn_v3_0_start_sriov(struct amdgpu_device *adev) |
1216 | { |
1217 | int i, j; |
1218 | struct amdgpu_ring *ring; |
1219 | uint64_t cache_addr; |
1220 | uint64_t rb_addr; |
1221 | uint64_t ctx_addr; |
1222 | uint32_t param, resp, expected; |
1223 | uint32_t offset, cache_size; |
1224 | uint32_t tmp, timeout; |
1225 | uint32_t id; |
1226 | |
1227 | struct amdgpu_mm_table *table = &adev->virt.mm_table; |
1228 | uint32_t *table_loc; |
1229 | uint32_t table_size; |
1230 | uint32_t size, size_dw; |
1231 | |
1232 | struct mmsch_v3_0_cmd_direct_write |
1233 | direct_wt = { {0} }; |
1234 | struct mmsch_v3_0_cmd_direct_read_modify_write |
1235 | direct_rd_mod_wt = { {0} }; |
1236 | struct mmsch_v3_0_cmd_direct_polling |
1237 | direct_poll = { {0} }; |
1238 | struct mmsch_v3_0_cmd_end end = { {0} }; |
1239 | struct mmsch_v3_0_init_header header; |
1240 | |
1241 | direct_wt.cmd_header.command_type = |
1242 | MMSCH_COMMAND__DIRECT_REG_WRITE; |
1243 | direct_rd_mod_wt.cmd_header.command_type = |
1244 | MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE; |
1245 | direct_poll.cmd_header.command_type = |
1246 | MMSCH_COMMAND__DIRECT_REG_POLLING; |
1247 | end.cmd_header.command_type = |
1248 | MMSCH_COMMAND__END; |
1249 | |
1250 | header.version = MMSCH_VERSION(3 << 16 | 0); |
1251 | header.total_size = sizeof(struct mmsch_v3_0_init_header) >> 2; |
1252 | for (i = 0; i < AMDGPU_MAX_VCN_INSTANCES2; i++) { |
1253 | header.inst[i].init_status = 0; |
1254 | header.inst[i].table_offset = 0; |
1255 | header.inst[i].table_size = 0; |
1256 | } |
1257 | |
1258 | table_loc = (uint32_t *)table->cpu_addr; |
1259 | table_loc += header.total_size; |
1260 | for (i = 0; i < adev->vcn.num_vcn_inst; i++) { |
1261 | if (adev->vcn.harvest_config & (1 << i)) |
1262 | continue; |
1263 | |
1264 | table_size = 0; |
1265 | |
1266 | MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_read_modify_write ); size_dw = size / 4; direct_rd_mod_wt.cmd_header.reg_offset = (adev->reg_offset[VCN_HWIP][i][1] + 0x0080); direct_rd_mod_wt .mask_value = ~UVD_STATUS__UVD_BUSY; direct_rd_mod_wt.write_data = UVD_STATUS__UVD_BUSY; __builtin_memcpy(((void *)table_loc) , (&direct_rd_mod_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1267 | mmUVD_STATUS),{ size = sizeof(struct mmsch_v3_0_cmd_direct_read_modify_write ); size_dw = size / 4; direct_rd_mod_wt.cmd_header.reg_offset = (adev->reg_offset[VCN_HWIP][i][1] + 0x0080); direct_rd_mod_wt .mask_value = ~UVD_STATUS__UVD_BUSY; direct_rd_mod_wt.write_data = UVD_STATUS__UVD_BUSY; __builtin_memcpy(((void *)table_loc) , (&direct_rd_mod_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1268 | ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY){ size = sizeof(struct mmsch_v3_0_cmd_direct_read_modify_write ); size_dw = size / 4; direct_rd_mod_wt.cmd_header.reg_offset = (adev->reg_offset[VCN_HWIP][i][1] + 0x0080); direct_rd_mod_wt .mask_value = ~UVD_STATUS__UVD_BUSY; direct_rd_mod_wt.write_data = UVD_STATUS__UVD_BUSY; __builtin_memcpy(((void *)table_loc) , (&direct_rd_mod_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1269 | |
1270 | cache_size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 - 1)); |
1271 | |
1272 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
1273 | id = amdgpu_ucode_id_vcns[i]; |
1274 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043c); direct_wt.reg_value = adev->firmware .ucode[id].tmr_mc_addr_lo; __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1275 | mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043c); direct_wt.reg_value = adev->firmware .ucode[id].tmr_mc_addr_lo; __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1276 | adev->firmware.ucode[id].tmr_mc_addr_lo){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043c); direct_wt.reg_value = adev->firmware .ucode[id].tmr_mc_addr_lo; __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1277 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043d); direct_wt.reg_value = adev->firmware .ucode[id].tmr_mc_addr_hi; __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1278 | mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043d); direct_wt.reg_value = adev->firmware .ucode[id].tmr_mc_addr_hi; __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1279 | adev->firmware.ucode[id].tmr_mc_addr_hi){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043d); direct_wt.reg_value = adev->firmware .ucode[id].tmr_mc_addr_hi; __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1280 | offset = 0; |
1281 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0140); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1282 | mmUVD_VCPU_CACHE_OFFSET0),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0140); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1283 | 0){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0140); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1284 | } else { |
1285 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043c); direct_wt.reg_value = ((u32)(adev ->vcn.inst[i].gpu_addr)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1286 | mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043c); direct_wt.reg_value = ((u32)(adev ->vcn.inst[i].gpu_addr)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1287 | lower_32_bits(adev->vcn.inst[i].gpu_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043c); direct_wt.reg_value = ((u32)(adev ->vcn.inst[i].gpu_addr)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1288 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043d); direct_wt.reg_value = ((u32)(((adev ->vcn.inst[i].gpu_addr) >> 16) >> 16)); __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1289 | mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043d); direct_wt.reg_value = ((u32)(((adev ->vcn.inst[i].gpu_addr) >> 16) >> 16)); __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1290 | upper_32_bits(adev->vcn.inst[i].gpu_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x043d); direct_wt.reg_value = ((u32)(((adev ->vcn.inst[i].gpu_addr) >> 16) >> 16)); __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1291 | offset = cache_size; |
1292 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0140); direct_wt.reg_value = 256 >> 3; __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1293 | mmUVD_VCPU_CACHE_OFFSET0),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0140); direct_wt.reg_value = 256 >> 3; __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1294 | AMDGPU_UVD_FIRMWARE_OFFSET >> 3){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0140); direct_wt.reg_value = 256 >> 3; __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; }; |
1295 | } |
1296 | |
1297 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0141); direct_wt.reg_value = cache_size; __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; } |
1298 | mmUVD_VCPU_CACHE_SIZE0),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0141); direct_wt.reg_value = cache_size; __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; } |
1299 | cache_size){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0141); direct_wt.reg_value = cache_size; __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; }; |
1300 | |
1301 | cache_addr = adev->vcn.inst[i].gpu_addr + offset; |
1302 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0468); direct_wt.reg_value = ((u32)(cache_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1303 | mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0468); direct_wt.reg_value = ((u32)(cache_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1304 | lower_32_bits(cache_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0468); direct_wt.reg_value = ((u32)(cache_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; }; |
1305 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0469); direct_wt.reg_value = ((u32)(((cache_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1306 | mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0469); direct_wt.reg_value = ((u32)(((cache_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1307 | upper_32_bits(cache_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0469); direct_wt.reg_value = ((u32)(((cache_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1308 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0142); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1309 | mmUVD_VCPU_CACHE_OFFSET1),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0142); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1310 | 0){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0142); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1311 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0143); direct_wt.reg_value = (128*1024); __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; } |
1312 | mmUVD_VCPU_CACHE_SIZE1),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0143); direct_wt.reg_value = (128*1024); __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; } |
1313 | AMDGPU_VCN_STACK_SIZE){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0143); direct_wt.reg_value = (128*1024); __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; }; |
1314 | |
1315 | cache_addr = adev->vcn.inst[i].gpu_addr + offset + |
1316 | AMDGPU_VCN_STACK_SIZE(128*1024); |
1317 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x046c); direct_wt.reg_value = ((u32)(cache_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1318 | mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x046c); direct_wt.reg_value = ((u32)(cache_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1319 | lower_32_bits(cache_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x046c); direct_wt.reg_value = ((u32)(cache_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; }; |
1320 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x046d); direct_wt.reg_value = ((u32)(((cache_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1321 | mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x046d); direct_wt.reg_value = ((u32)(((cache_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1322 | upper_32_bits(cache_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x046d); direct_wt.reg_value = ((u32)(((cache_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1323 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0144); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1324 | mmUVD_VCPU_CACHE_OFFSET2),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0144); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1325 | 0){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0144); direct_wt.reg_value = 0; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1326 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0145); direct_wt.reg_value = (512*1024); __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; } |
1327 | mmUVD_VCPU_CACHE_SIZE2),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0145); direct_wt.reg_value = (512*1024); __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; } |
1328 | AMDGPU_VCN_CONTEXT_SIZE){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0145); direct_wt.reg_value = (512*1024); __builtin_memcpy(((void *)table_loc), (&direct_wt), (size )); table_loc += size_dw; table_size += size_dw; }; |
1329 | |
1330 | for (j = 0; j < adev->vcn.num_enc_rings; ++j) { |
1331 | ring = &adev->vcn.inst[i].ring_enc[j]; |
1332 | ring->wptr = 0; |
1333 | rb_addr = ring->gpu_addr; |
1334 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00aa); direct_wt.reg_value = ((u32)(rb_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1335 | mmUVD_RB_BASE_LO),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00aa); direct_wt.reg_value = ((u32)(rb_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1336 | lower_32_bits(rb_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00aa); direct_wt.reg_value = ((u32)(rb_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; }; |
1337 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00ab); direct_wt.reg_value = ((u32)(((rb_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1338 | mmUVD_RB_BASE_HI),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00ab); direct_wt.reg_value = ((u32)(((rb_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1339 | upper_32_bits(rb_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00ab); direct_wt.reg_value = ((u32)(((rb_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1340 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00ac); direct_wt.reg_value = ring->ring_size / 4; __builtin_memcpy(((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1341 | mmUVD_RB_SIZE),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00ac); direct_wt.reg_value = ring->ring_size / 4; __builtin_memcpy(((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1342 | ring->ring_size / 4){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x00ac); direct_wt.reg_value = ring->ring_size / 4; __builtin_memcpy(((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1343 | } |
1344 | |
1345 | ring = &adev->vcn.inst[i].ring_dec; |
1346 | ring->wptr = 0; |
1347 | rb_addr = ring->gpu_addr; |
1348 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0432); direct_wt.reg_value = ((u32)(rb_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1349 | mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0432); direct_wt.reg_value = ((u32)(rb_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; } |
1350 | lower_32_bits(rb_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0432); direct_wt.reg_value = ((u32)(rb_addr )); __builtin_memcpy(((void *)table_loc), (&direct_wt), ( size)); table_loc += size_dw; table_size += size_dw; }; |
1351 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0433); direct_wt.reg_value = ((u32)(((rb_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1352 | mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0433); direct_wt.reg_value = ((u32)(((rb_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1353 | upper_32_bits(rb_addr)){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x0433); direct_wt.reg_value = ((u32)(((rb_addr ) >> 16) >> 16)); __builtin_memcpy(((void *)table_loc ), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1354 | /* force RBC into idle state */ |
1355 | tmp = order_base_2(ring->ring_size)drm_order(ring->ring_size); |
1356 | tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, tmp)(((0) & ~0x0000001FL) | (0x0000001FL & ((tmp) << 0x0))); |
1357 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) << 0x8))); |
1358 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) << 0x10))); |
1359 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) << 0x18))); |
1360 | tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c))); |
1361 | MMSCH_V3_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCN, i,{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x02de); direct_wt.reg_value = tmp; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1362 | mmUVD_RBC_RB_CNTL),{ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x02de); direct_wt.reg_value = tmp; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; } |
1363 | tmp){ size = sizeof(struct mmsch_v3_0_cmd_direct_write); size_dw = size / 4; direct_wt.cmd_header.reg_offset = (adev->reg_offset [VCN_HWIP][i][1] + 0x02de); direct_wt.reg_value = tmp; __builtin_memcpy (((void *)table_loc), (&direct_wt), (size)); table_loc += size_dw; table_size += size_dw; }; |
1364 | |
1365 | /* add end packet */ |
1366 | MMSCH_V3_0_INSERT_END(){ size = sizeof(struct mmsch_v3_0_cmd_end); size_dw = size / 4 ; __builtin_memcpy(((void *)table_loc), (&end), (size)); table_loc += size_dw; table_size += size_dw; }; |
1367 | |
1368 | /* refine header */ |
1369 | header.inst[i].init_status = 1; |
1370 | header.inst[i].table_offset = header.total_size; |
1371 | header.inst[i].table_size = table_size; |
1372 | header.total_size += table_size; |
1373 | } |
1374 | |
1375 | /* Update init table header in memory */ |
1376 | size = sizeof(struct mmsch_v3_0_init_header); |
1377 | table_loc = (uint32_t *)table->cpu_addr; |
1378 | memcpy((void *)table_loc, &header, size)__builtin_memcpy(((void *)table_loc), (&header), (size)); |
1379 | |
1380 | /* message MMSCH (in VCN[0]) to initialize this client |
1381 | * 1, write to mmsch_vf_ctx_addr_lo/hi register with GPU mc addr |
1382 | * of memory descriptor location |
1383 | */ |
1384 | ctx_addr = table->gpu_addr; |
1385 | WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0 ] + 0x000c)), (((u32)(ctx_addr))), 0); |
1386 | WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0 ] + 0x000d)), (((u32)(((ctx_addr) >> 16) >> 16))) , 0); |
1387 | |
1388 | /* 2, update vmid of descriptor */ |
1389 | tmp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][0][0] + 0x000b), 0); |
1390 | tmp &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK0x0000001FL; |
1391 | /* use domain0 for MM scheduler */ |
1392 | tmp |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT0x0); |
1393 | WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0 ] + 0x000b)), (tmp), 0); |
1394 | |
1395 | /* 3, notify mmsch about the size of this descriptor */ |
1396 | size = header.total_size; |
1397 | WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0 ] + 0x000e)), (size), 0); |
1398 | |
1399 | /* 4, set resp to zero */ |
1400 | WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0 ] + 0x0013)), (0), 0); |
1401 | |
1402 | /* 5, kick off the initialization and wait until |
1403 | * MMSCH_VF_MAILBOX_RESP becomes non-zero |
1404 | */ |
1405 | param = 0x10000001; |
1406 | WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, param)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][0][0 ] + 0x0012)), (param), 0); |
1407 | tmp = 0; |
1408 | timeout = 1000; |
1409 | resp = 0; |
1410 | expected = param + 1; |
1411 | while (resp != expected) { |
1412 | resp = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][0][0] + 0x0013), 0); |
1413 | if (resp == expected) |
1414 | break; |
1415 | |
1416 | udelay(10); |
1417 | tmp = tmp + 10; |
1418 | if (tmp >= timeout) { |
1419 | DRM_ERROR("failed to init MMSCH. TIME-OUT after %d usec"\__drm_err("failed to init MMSCH. TIME-OUT after %d usec" " waiting for mmMMSCH_VF_MAILBOX_RESP " "(expected=0x%08x, readback=0x%08x)\n", tmp, expected, resp) |
1420 | " waiting for mmMMSCH_VF_MAILBOX_RESP "\__drm_err("failed to init MMSCH. TIME-OUT after %d usec" " waiting for mmMMSCH_VF_MAILBOX_RESP " "(expected=0x%08x, readback=0x%08x)\n", tmp, expected, resp) |
1421 | "(expected=0x%08x, readback=0x%08x)\n",__drm_err("failed to init MMSCH. TIME-OUT after %d usec" " waiting for mmMMSCH_VF_MAILBOX_RESP " "(expected=0x%08x, readback=0x%08x)\n", tmp, expected, resp) |
1422 | tmp, expected, resp)__drm_err("failed to init MMSCH. TIME-OUT after %d usec" " waiting for mmMMSCH_VF_MAILBOX_RESP " "(expected=0x%08x, readback=0x%08x)\n", tmp, expected, resp); |
1423 | return -EBUSY16; |
1424 | } |
1425 | } |
1426 | |
1427 | return 0; |
1428 | } |
1429 | |
1430 | static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) |
1431 | { |
1432 | uint32_t tmp; |
1433 | |
1434 | /* Wait for power status to be 1 */ |
1435 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret ; }) |
1436 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret ; }); |
1437 | |
1438 | /* wait for read ptr to be equal to write ptr */ |
1439 | tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00ae), 0); |
1440 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00ad), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00ad), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_RB_RPTR", (unsigned)tmp, (unsigned)(tmp_ & (0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; }); |
1441 | |
1442 | tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00b3), 0); |
1443 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00b2), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00b2), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_RB_RPTR2", (unsigned)tmp, (unsigned)(tmp_ & (0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; }); |
1444 | |
1445 | tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e1), 0) & 0x7FFFFFFF; |
1446 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e0), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x02e0), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_RBC_RB_RPTR", (unsigned)tmp, (unsigned)(tmp_ & (0xFFFFFFFF))); ret = -60; break; } } } while (0); ret ; }); |
1447 | |
1448 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret ; }) |
1449 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret ; }); |
1450 | |
1451 | /* disable dynamic power gating mode */ |
1452 | WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000004L ); tmp_ |= ((0) & ~(~0x00000004L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0) |
1453 | ~UVD_POWER_STATUS__UVD_PG_MODE_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000004L ); tmp_ |= ((0) & ~(~0x00000004L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0); |
1454 | |
1455 | return 0; |
1456 | } |
1457 | |
1458 | static int vcn_v3_0_stop(struct amdgpu_device *adev) |
1459 | { |
1460 | uint32_t tmp; |
1461 | int i, r = 0; |
1462 | |
1463 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1464 | if (adev->vcn.harvest_config & (1 << i)) |
1465 | continue; |
1466 | |
1467 | if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) { |
1468 | r = vcn_v3_0_stop_dpg_mode(adev, i); |
Value stored to 'r' is never read | |
1469 | continue; |
1470 | } |
1471 | |
1472 | /* wait for vcn idle */ |
1473 | r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x7 )) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev-> usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop --; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_ & (0x7))); ret = -60; break; } } } while (0); ret; }); |
1474 | if (r) |
1475 | return r; |
1476 | |
1477 | tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK0x00000008L | |
1478 | UVD_LMI_STATUS__READ_CLEAN_MASK0x00000001L | |
1479 | UVD_LMI_STATUS__WRITE_CLEAN_MASK0x00000002L | |
1480 | UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK0x00000004L; |
1481 | r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (tmp )) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout ; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev , (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , i, "mmUVD_LMI_STATUS", (unsigned)tmp, (unsigned)(tmp_ & (tmp))); ret = -60; break; } } } while (0); ret; }); |
1482 | if (r) |
1483 | return r; |
1484 | |
1485 | /* disable LMI UMC channel */ |
1486 | tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a6), 0); |
1487 | tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK0x00000100L; |
1488 | WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x04a6)), (tmp), 0); |
1489 | tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK0x00000200L| |
1490 | UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK0x00000040L; |
1491 | r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (tmp )) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout ; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev , (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , i, "mmUVD_LMI_STATUS", (unsigned)tmp, (unsigned)(tmp_ & (tmp))); ret = -60; break; } } } while (0); ret; }); |
1492 | if (r) |
1493 | return r; |
1494 | |
1495 | /* block VCPU register access */ |
1496 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_ |= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_ ), 0); } while (0) |
1497 | UVD_RB_ARB_CTRL__VCPU_DIS_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_ |= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_ ), 0); } while (0) |
1498 | ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_ |= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_ ), 0); } while (0); |
1499 | |
1500 | /* reset VCPU */ |
1501 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0) |
1502 | UVD_VCPU_CNTL__BLK_RST_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0) |
1503 | ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_ |= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_ ), 0); } while (0); |
1504 | |
1505 | /* disable VCPU clock */ |
1506 | WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~(0x00000200L)) ; tmp_ |= ((0) & ~(~(0x00000200L))); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0 ); } while (0) |
1507 | ~(UVD_VCPU_CNTL__CLK_EN_MASK))do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~(0x00000200L)) ; tmp_ |= ((0) & ~(~(0x00000200L))); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0 ); } while (0); |
1508 | |
1509 | /* apply soft reset */ |
1510 | tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0084), 0); |
1511 | tmp |= UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK0x00002000L; |
1512 | WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0084)), (tmp), 0); |
1513 | tmp = RREG32_SOC15(VCN, i, mmUVD_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0084), 0); |
1514 | tmp |= UVD_SOFT_RESET__LMI_SOFT_RESET_MASK0x00000004L; |
1515 | WREG32_SOC15(VCN, i, mmUVD_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0084)), (tmp), 0); |
1516 | |
1517 | /* clear status */ |
1518 | WREG32_SOC15(VCN, i, mmUVD_STATUS, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][i][1 ] + 0x0080)), (0), 0); |
1519 | |
1520 | /* apply HW clock gating */ |
1521 | vcn_v3_0_enable_clock_gating(adev, i); |
1522 | |
1523 | /* enable VCN power gating */ |
1524 | vcn_v3_0_enable_static_power_gating(adev, i); |
1525 | } |
1526 | |
1527 | if (adev->pm.dpm_enabled) |
1528 | amdgpu_dpm_enable_uvd(adev, false0); |
1529 | |
1530 | return 0; |
1531 | } |
1532 | |
1533 | static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev, |
1534 | int inst_idx, struct dpg_pause_state *new_state) |
1535 | { |
1536 | struct amdgpu_ring *ring; |
1537 | uint32_t reg_data = 0; |
1538 | int ret_code; |
1539 | |
1540 | /* pause/unpause if state is changed */ |
1541 | if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { |
1542 | DRM_DEBUG("dpg pause state changed %d -> %d",__drm_dbg(DRM_UT_CORE, "dpg pause state changed %d -> %d", adev->vcn.inst[inst_idx].pause_state.fw_based, new_state-> fw_based) |
1543 | adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based)__drm_dbg(DRM_UT_CORE, "dpg pause state changed %d -> %d", adev->vcn.inst[inst_idx].pause_state.fw_based, new_state-> fw_based); |
1544 | reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0014), 0) & |
1545 | (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK0x00000008L); |
1546 | |
1547 | if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { |
1548 | ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret ; }) |
1549 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret ; }); |
1550 | |
1551 | if (!ret_code) { |
1552 | /* pause DPG */ |
1553 | reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK0x00000004L; |
1554 | WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0014)), (reg_data), 0); |
1555 | |
1556 | /* wait for ACK */ |
1557 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_ ) { loop = adev->usec_timeout; old_ = tmp_; } else udelay( 1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned )(tmp_ & (0x00000008L))); ret = -60; break; } } } while ( 0); ret; }) |
1558 | UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_ ) { loop = adev->usec_timeout; old_ = tmp_; } else udelay( 1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned )(tmp_ & (0x00000008L))); ret = -60; break; } } } while ( 0); ret; }) |
1559 | UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_ ) { loop = adev->usec_timeout; old_ = tmp_; } else udelay( 1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP ][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned )(tmp_ & (0x00000008L))); ret = -60; break; } } } while ( 0); ret; }); |
1560 | |
1561 | /* Stall DPG before WPTR/RPTR reset */ |
1562 | WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004) ), (tmp_), 0); } while (0) |
1563 | UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004) ), (tmp_), 0); } while (0) |
1564 | ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg (adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004) ), (tmp_), 0); } while (0); |
1565 | |
1566 | /* Restore */ |
1567 | ring = &adev->vcn.inst[inst_idx].ring_enc[0]; |
1568 | ring->wptr = 0; |
1569 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00aa)), (ring->gpu_addr), 0); |
1570 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00ab)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0); |
1571 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00ac)), (ring->ring_size / 4), 0); |
1572 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00ad)), (((u32)(ring->wptr))), 0); |
1573 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00ae)), (((u32)(ring->wptr))), 0); |
1574 | |
1575 | ring = &adev->vcn.inst[inst_idx].ring_enc[1]; |
1576 | ring->wptr = 0; |
1577 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00af)), (ring->gpu_addr), 0); |
1578 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00b0)), (((u32)(((ring->gpu_addr) >> 16) >> 16))), 0); |
1579 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00b1)), (ring->ring_size / 4), 0); |
1580 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00b2)), (((u32)(ring->wptr))), 0); |
1581 | WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x00b3)), (((u32)(ring->wptr))), 0); |
1582 | |
1583 | /* Unstall DPG */ |
1584 | WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0) |
1585 | 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset [VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L ); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev , ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_ ), 0); } while (0); |
1586 | |
1587 | SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON )) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev ->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON , (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret; }) |
1588 | UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); uint32_t loop = adev->usec_timeout; ret = 0; while (( tmp_ & (0x00000003L)) != (UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON )) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev ->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , inst_idx, "mmUVD_POWER_STATUS", (unsigned)UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON , (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } } } while (0); ret; }); |
1589 | } |
1590 | } else { |
1591 | /* unpause dpg, no need to wait */ |
1592 | reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK0x00000004L; |
1593 | WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data)amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][inst_idx ][1] + 0x0014)), (reg_data), 0); |
1594 | } |
1595 | adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; |
1596 | } |
1597 | |
1598 | return 0; |
1599 | } |
1600 | |
1601 | /** |
1602 | * vcn_v3_0_dec_ring_get_rptr - get read pointer |
1603 | * |
1604 | * @ring: amdgpu_ring pointer |
1605 | * |
1606 | * Returns the current hardware read pointer |
1607 | */ |
1608 | static uint64_t vcn_v3_0_dec_ring_get_rptr(struct amdgpu_ring *ring) |
1609 | { |
1610 | struct amdgpu_device *adev = ring->adev; |
1611 | |
1612 | return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring-> me][1] + 0x02e0), 0); |
1613 | } |
1614 | |
1615 | /** |
1616 | * vcn_v3_0_dec_ring_get_wptr - get write pointer |
1617 | * |
1618 | * @ring: amdgpu_ring pointer |
1619 | * |
1620 | * Returns the current hardware write pointer |
1621 | */ |
1622 | static uint64_t vcn_v3_0_dec_ring_get_wptr(struct amdgpu_ring *ring) |
1623 | { |
1624 | struct amdgpu_device *adev = ring->adev; |
1625 | |
1626 | if (ring->use_doorbell) |
1627 | return adev->wb.wb[ring->wptr_offs]; |
1628 | else |
1629 | return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring-> me][1] + 0x02e1), 0); |
1630 | } |
1631 | |
1632 | /** |
1633 | * vcn_v3_0_dec_ring_set_wptr - set write pointer |
1634 | * |
1635 | * @ring: amdgpu_ring pointer |
1636 | * |
1637 | * Commits the write pointer to the hardware |
1638 | */ |
1639 | static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring) |
1640 | { |
1641 | struct amdgpu_device *adev = ring->adev; |
1642 | |
1643 | if (ring->use_doorbell) { |
1644 | adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr)((u32)(ring->wptr)); |
1645 | WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)( ring->wptr)))); |
1646 | } else { |
1647 | WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring ->me][1] + 0x02e1)), (((u32)(ring->wptr))), 0); |
1648 | } |
1649 | } |
1650 | |
1651 | static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { |
1652 | .type = AMDGPU_RING_TYPE_VCN_DEC, |
1653 | .align_mask = 0xf, |
1654 | .vmhub = AMDGPU_MMHUB_01, |
1655 | .get_rptr = vcn_v3_0_dec_ring_get_rptr, |
1656 | .get_wptr = vcn_v3_0_dec_ring_get_wptr, |
1657 | .set_wptr = vcn_v3_0_dec_ring_set_wptr, |
1658 | .emit_frame_size = |
1659 | SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 6 + |
1660 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 8 + |
1661 | 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */ |
1662 | 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */ |
1663 | 6, |
1664 | .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */ |
1665 | .emit_ib = vcn_v2_0_dec_ring_emit_ib, |
1666 | .emit_fence = vcn_v2_0_dec_ring_emit_fence, |
1667 | .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush, |
1668 | .test_ring = vcn_v2_0_dec_ring_test_ring, |
1669 | .test_ib = amdgpu_vcn_dec_ring_test_ib, |
1670 | .insert_nop = vcn_v2_0_dec_ring_insert_nop, |
1671 | .insert_start = vcn_v2_0_dec_ring_insert_start, |
1672 | .insert_end = vcn_v2_0_dec_ring_insert_end, |
1673 | .pad_ib = amdgpu_ring_generic_pad_ib, |
1674 | .begin_use = amdgpu_vcn_ring_begin_use, |
1675 | .end_use = amdgpu_vcn_ring_end_use, |
1676 | .emit_wreg = vcn_v2_0_dec_ring_emit_wreg, |
1677 | .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait, |
1678 | .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, |
1679 | }; |
1680 | |
1681 | /** |
1682 | * vcn_v3_0_enc_ring_get_rptr - get enc read pointer |
1683 | * |
1684 | * @ring: amdgpu_ring pointer |
1685 | * |
1686 | * Returns the current hardware enc read pointer |
1687 | */ |
1688 | static uint64_t vcn_v3_0_enc_ring_get_rptr(struct amdgpu_ring *ring) |
1689 | { |
1690 | struct amdgpu_device *adev = ring->adev; |
1691 | |
1692 | if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) |
1693 | return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring-> me][1] + 0x00ad), 0); |
1694 | else |
1695 | return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring-> me][1] + 0x00b2), 0); |
1696 | } |
1697 | |
1698 | /** |
1699 | * vcn_v3_0_enc_ring_get_wptr - get enc write pointer |
1700 | * |
1701 | * @ring: amdgpu_ring pointer |
1702 | * |
1703 | * Returns the current hardware enc write pointer |
1704 | */ |
1705 | static uint64_t vcn_v3_0_enc_ring_get_wptr(struct amdgpu_ring *ring) |
1706 | { |
1707 | struct amdgpu_device *adev = ring->adev; |
1708 | |
1709 | if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { |
1710 | if (ring->use_doorbell) |
1711 | return adev->wb.wb[ring->wptr_offs]; |
1712 | else |
1713 | return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring-> me][1] + 0x00ae), 0); |
1714 | } else { |
1715 | if (ring->use_doorbell) |
1716 | return adev->wb.wb[ring->wptr_offs]; |
1717 | else |
1718 | return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][ring-> me][1] + 0x00b3), 0); |
1719 | } |
1720 | } |
1721 | |
1722 | /** |
1723 | * vcn_v3_0_enc_ring_set_wptr - set enc write pointer |
1724 | * |
1725 | * @ring: amdgpu_ring pointer |
1726 | * |
1727 | * Commits the enc write pointer to the hardware |
1728 | */ |
1729 | static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring) |
1730 | { |
1731 | struct amdgpu_device *adev = ring->adev; |
1732 | |
1733 | if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) { |
1734 | if (ring->use_doorbell) { |
1735 | adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr)((u32)(ring->wptr)); |
1736 | WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)( ring->wptr)))); |
1737 | } else { |
1738 | WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring ->me][1] + 0x00ae)), (((u32)(ring->wptr))), 0); |
1739 | } |
1740 | } else { |
1741 | if (ring->use_doorbell) { |
1742 | adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr)((u32)(ring->wptr)); |
1743 | WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)( ring->wptr)))); |
1744 | } else { |
1745 | WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring ->me][1] + 0x00b3)), (((u32)(ring->wptr))), 0); |
1746 | } |
1747 | } |
1748 | } |
1749 | |
1750 | static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { |
1751 | .type = AMDGPU_RING_TYPE_VCN_ENC, |
1752 | .align_mask = 0x3f, |
1753 | .nop = VCN_ENC_CMD_NO_OP0x00000000, |
1754 | .vmhub = AMDGPU_MMHUB_01, |
1755 | .get_rptr = vcn_v3_0_enc_ring_get_rptr, |
1756 | .get_wptr = vcn_v3_0_enc_ring_get_wptr, |
1757 | .set_wptr = vcn_v3_0_enc_ring_set_wptr, |
1758 | .emit_frame_size = |
1759 | SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 + |
1760 | SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 4 + |
1761 | 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */ |
1762 | 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */ |
1763 | 1, /* vcn_v2_0_enc_ring_insert_end */ |
1764 | .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */ |
1765 | .emit_ib = vcn_v2_0_enc_ring_emit_ib, |
1766 | .emit_fence = vcn_v2_0_enc_ring_emit_fence, |
1767 | .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush, |
1768 | .test_ring = amdgpu_vcn_enc_ring_test_ring, |
1769 | .test_ib = amdgpu_vcn_enc_ring_test_ib, |
1770 | .insert_nop = amdgpu_ring_insert_nop, |
1771 | .insert_end = vcn_v2_0_enc_ring_insert_end, |
1772 | .pad_ib = amdgpu_ring_generic_pad_ib, |
1773 | .begin_use = amdgpu_vcn_ring_begin_use, |
1774 | .end_use = amdgpu_vcn_ring_end_use, |
1775 | .emit_wreg = vcn_v2_0_enc_ring_emit_wreg, |
1776 | .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait, |
1777 | .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, |
1778 | }; |
1779 | |
1780 | static void vcn_v3_0_set_dec_ring_funcs(struct amdgpu_device *adev) |
1781 | { |
1782 | int i; |
1783 | |
1784 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1785 | if (adev->vcn.harvest_config & (1 << i)) |
1786 | continue; |
1787 | |
1788 | adev->vcn.inst[i].ring_dec.funcs = &vcn_v3_0_dec_ring_vm_funcs; |
1789 | adev->vcn.inst[i].ring_dec.me = i; |
1790 | DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i)printk("\0016" "[" "drm" "] " "VCN(%d) decode is enabled in VM mode\n" , i); |
1791 | } |
1792 | } |
1793 | |
1794 | static void vcn_v3_0_set_enc_ring_funcs(struct amdgpu_device *adev) |
1795 | { |
1796 | int i, j; |
1797 | |
1798 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1799 | if (adev->vcn.harvest_config & (1 << i)) |
1800 | continue; |
1801 | |
1802 | for (j = 0; j < adev->vcn.num_enc_rings; ++j) { |
1803 | adev->vcn.inst[i].ring_enc[j].funcs = &vcn_v3_0_enc_ring_vm_funcs; |
1804 | adev->vcn.inst[i].ring_enc[j].me = i; |
1805 | } |
1806 | DRM_INFO("VCN(%d) encode is enabled in VM mode\n", i)printk("\0016" "[" "drm" "] " "VCN(%d) encode is enabled in VM mode\n" , i); |
1807 | } |
1808 | } |
1809 | |
1810 | static bool_Bool vcn_v3_0_is_idle(void *handle) |
1811 | { |
1812 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1813 | int i, ret = 1; |
1814 | |
1815 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1816 | if (adev->vcn.harvest_config & (1 << i)) |
1817 | continue; |
1818 | |
1819 | ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0) == UVD_STATUS__IDLE); |
1820 | } |
1821 | |
1822 | return ret; |
1823 | } |
1824 | |
1825 | static int vcn_v3_0_wait_for_idle(void *handle) |
1826 | { |
1827 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1828 | int i, ret = 0; |
1829 | |
1830 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1831 | if (adev->vcn.harvest_config & (1 << i)) |
1832 | continue; |
1833 | |
1834 | ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (UVD_STATUS__IDLE )) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev-> usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop --; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_ & (UVD_STATUS__IDLE))); ret = -60; break; } } } while (0 ); ret; }) |
1835 | UVD_STATUS__IDLE)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t loop = adev->usec_timeout; ret = 0; while ((tmp_ & (UVD_STATUS__IDLE )) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev-> usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg (adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop --; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n" , i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_ & (UVD_STATUS__IDLE))); ret = -60; break; } } } while (0 ); ret; }); |
1836 | if (ret) |
1837 | return ret; |
1838 | } |
1839 | |
1840 | return ret; |
1841 | } |
1842 | |
1843 | static int vcn_v3_0_set_clockgating_state(void *handle, |
1844 | enum amd_clockgating_state state) |
1845 | { |
1846 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1847 | bool_Bool enable = (state == AMD_CG_STATE_GATE) ? true1 : false0; |
1848 | int i; |
1849 | |
1850 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1851 | if (adev->vcn.harvest_config & (1 << i)) |
1852 | continue; |
1853 | |
1854 | if (enable) { |
1855 | if (RREG32_SOC15(VCN, i, mmUVD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0) != UVD_STATUS__IDLE) |
1856 | return -EBUSY16; |
1857 | vcn_v3_0_enable_clock_gating(adev, i); |
1858 | } else { |
1859 | vcn_v3_0_disable_clock_gating(adev, i); |
1860 | } |
1861 | } |
1862 | |
1863 | return 0; |
1864 | } |
1865 | |
1866 | static int vcn_v3_0_set_powergating_state(void *handle, |
1867 | enum amd_powergating_state state) |
1868 | { |
1869 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1870 | int ret; |
1871 | |
1872 | /* for SRIOV, guest should not control VCN Power-gating |
1873 | * MMSCH FW should control Power-gating and clock-gating |
1874 | * guest should avoid touching CGC and PG |
1875 | */ |
1876 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
1877 | adev->vcn.cur_state = AMD_PG_STATE_UNGATE; |
1878 | return 0; |
1879 | } |
1880 | |
1881 | if(state == adev->vcn.cur_state) |
1882 | return 0; |
1883 | |
1884 | if (state == AMD_PG_STATE_GATE) |
1885 | ret = vcn_v3_0_stop(adev); |
1886 | else |
1887 | ret = vcn_v3_0_start(adev); |
1888 | |
1889 | if(!ret) |
1890 | adev->vcn.cur_state = state; |
1891 | |
1892 | return ret; |
1893 | } |
1894 | |
1895 | static int vcn_v3_0_set_interrupt_state(struct amdgpu_device *adev, |
1896 | struct amdgpu_irq_src *source, |
1897 | unsigned type, |
1898 | enum amdgpu_interrupt_state state) |
1899 | { |
1900 | return 0; |
1901 | } |
1902 | |
1903 | static int vcn_v3_0_process_interrupt(struct amdgpu_device *adev, |
1904 | struct amdgpu_irq_src *source, |
1905 | struct amdgpu_iv_entry *entry) |
1906 | { |
1907 | uint32_t ip_instance; |
1908 | |
1909 | switch (entry->client_id) { |
1910 | case SOC15_IH_CLIENTID_VCN: |
1911 | ip_instance = 0; |
1912 | break; |
1913 | case SOC15_IH_CLIENTID_VCN1: |
1914 | ip_instance = 1; |
1915 | break; |
1916 | default: |
1917 | DRM_ERROR("Unhandled client id: %d\n", entry->client_id)__drm_err("Unhandled client id: %d\n", entry->client_id); |
1918 | return 0; |
1919 | } |
1920 | |
1921 | DRM_DEBUG("IH: VCN TRAP\n")__drm_dbg(DRM_UT_CORE, "IH: VCN TRAP\n"); |
1922 | |
1923 | switch (entry->src_id) { |
1924 | case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT124: |
1925 | amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec); |
1926 | break; |
1927 | case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE119: |
1928 | amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]); |
1929 | break; |
1930 | case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY120: |
1931 | amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]); |
1932 | break; |
1933 | default: |
1934 | DRM_ERROR("Unhandled interrupt: %d %d\n",__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry ->src_data[0]) |
1935 | entry->src_id, entry->src_data[0])__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry ->src_data[0]); |
1936 | break; |
1937 | } |
1938 | |
1939 | return 0; |
1940 | } |
1941 | |
1942 | static const struct amdgpu_irq_src_funcs vcn_v3_0_irq_funcs = { |
1943 | .set = vcn_v3_0_set_interrupt_state, |
1944 | .process = vcn_v3_0_process_interrupt, |
1945 | }; |
1946 | |
1947 | static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) |
1948 | { |
1949 | int i; |
1950 | |
1951 | for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { |
1952 | if (adev->vcn.harvest_config & (1 << i)) |
1953 | continue; |
1954 | |
1955 | adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1; |
1956 | adev->vcn.inst[i].irq.funcs = &vcn_v3_0_irq_funcs; |
1957 | } |
1958 | } |
1959 | |
1960 | static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { |
1961 | .name = "vcn_v3_0", |
1962 | .early_init = vcn_v3_0_early_init, |
1963 | .late_init = NULL((void *)0), |
1964 | .sw_init = vcn_v3_0_sw_init, |
1965 | .sw_fini = vcn_v3_0_sw_fini, |
1966 | .hw_init = vcn_v3_0_hw_init, |
1967 | .hw_fini = vcn_v3_0_hw_fini, |
1968 | .suspend = vcn_v3_0_suspend, |
1969 | .resume = vcn_v3_0_resume, |
1970 | .is_idle = vcn_v3_0_is_idle, |
1971 | .wait_for_idle = vcn_v3_0_wait_for_idle, |
1972 | .check_soft_reset = NULL((void *)0), |
1973 | .pre_soft_reset = NULL((void *)0), |
1974 | .soft_reset = NULL((void *)0), |
1975 | .post_soft_reset = NULL((void *)0), |
1976 | .set_clockgating_state = vcn_v3_0_set_clockgating_state, |
1977 | .set_powergating_state = vcn_v3_0_set_powergating_state, |
1978 | }; |
1979 | |
1980 | const struct amdgpu_ip_block_version vcn_v3_0_ip_block = |
1981 | { |
1982 | .type = AMD_IP_BLOCK_TYPE_VCN, |
1983 | .major = 3, |
1984 | .minor = 0, |
1985 | .rev = 0, |
1986 | .funcs = &vcn_v3_0_ip_funcs, |
1987 | }; |