| File: | dev/pci/drm/i915/display/intel_display.c |
| Warning: | line 8552, column 2 Value stored to 'dpio_val' is never read |
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| 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
| 27 | #include <linux/i2c.h> |
| 28 | #include <linux/input.h> |
| 29 | #include <linux/intel-iommu.h> |
| 30 | #include <linux/kernel.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/dma-resv.h> |
| 33 | #include <linux/slab.h> |
| 34 | |
| 35 | #include <drm/drm_atomic.h> |
| 36 | #include <drm/drm_atomic_helper.h> |
| 37 | #include <drm/drm_atomic_uapi.h> |
| 38 | #include <drm/drm_damage_helper.h> |
| 39 | #include <drm/drm_dp_helper.h> |
| 40 | #include <drm/drm_edid.h> |
| 41 | #include <drm/drm_fourcc.h> |
| 42 | #include <drm/drm_plane_helper.h> |
| 43 | #include <drm/drm_probe_helper.h> |
| 44 | #include <drm/drm_rect.h> |
| 45 | |
| 46 | #include "display/intel_crt.h" |
| 47 | #include "display/intel_ddi.h" |
| 48 | #include "display/intel_dp.h" |
| 49 | #include "display/intel_dp_mst.h" |
| 50 | #include "display/intel_dpll_mgr.h" |
| 51 | #include "display/intel_dsi.h" |
| 52 | #include "display/intel_dvo.h" |
| 53 | #include "display/intel_gmbus.h" |
| 54 | #include "display/intel_hdmi.h" |
| 55 | #include "display/intel_lvds.h" |
| 56 | #include "display/intel_sdvo.h" |
| 57 | #include "display/intel_tv.h" |
| 58 | #include "display/intel_vdsc.h" |
| 59 | |
| 60 | #include "gt/intel_rps.h" |
| 61 | |
| 62 | #include "i915_drv.h" |
| 63 | #include "i915_trace.h" |
| 64 | #include "intel_acpi.h" |
| 65 | #include "intel_atomic.h" |
| 66 | #include "intel_atomic_plane.h" |
| 67 | #include "intel_bw.h" |
| 68 | #include "intel_cdclk.h" |
| 69 | #include "intel_color.h" |
| 70 | #include "intel_csr.h" |
| 71 | #include "intel_display_types.h" |
| 72 | #include "intel_dp_link_training.h" |
| 73 | #include "intel_fbc.h" |
| 74 | #include "intel_fbdev.h" |
| 75 | #include "intel_fifo_underrun.h" |
| 76 | #include "intel_frontbuffer.h" |
| 77 | #include "intel_hdcp.h" |
| 78 | #include "intel_hotplug.h" |
| 79 | #include "intel_overlay.h" |
| 80 | #include "intel_pipe_crc.h" |
| 81 | #include "intel_pm.h" |
| 82 | #include "intel_psr.h" |
| 83 | #include "intel_quirks.h" |
| 84 | #include "intel_sideband.h" |
| 85 | #include "intel_sprite.h" |
| 86 | #include "intel_tc.h" |
| 87 | #include "intel_vga.h" |
| 88 | |
| 89 | /* Primary plane formats for gen <= 3 */ |
| 90 | static const u32 i8xx_primary_formats[] = { |
| 91 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
| 92 | DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)), |
| 93 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
| 94 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 95 | }; |
| 96 | |
| 97 | /* Primary plane formats for ivb (no fp16 due to hw issue) */ |
| 98 | static const u32 ivb_primary_formats[] = { |
| 99 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
| 100 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
| 101 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 102 | DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 103 | DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 104 | DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 105 | }; |
| 106 | |
| 107 | /* Primary plane formats for gen >= 4, except ivb */ |
| 108 | static const u32 i965_primary_formats[] = { |
| 109 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
| 110 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
| 111 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 112 | DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 113 | DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 114 | DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 115 | DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)), |
| 116 | }; |
| 117 | |
| 118 | /* Primary plane formats for vlv/chv */ |
| 119 | static const u32 vlv_primary_formats[] = { |
| 120 | DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)), |
| 121 | DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), |
| 122 | DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 123 | DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 124 | DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 125 | DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 126 | DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 127 | DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 128 | DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 129 | DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)), |
| 130 | DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)), |
| 131 | }; |
| 132 | |
| 133 | static const u64 i9xx_format_modifiers[] = { |
| 134 | I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )), |
| 135 | DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ), |
| 136 | DRM_FORMAT_MOD_INVALID((((__u64)0) << 56) | ((((1ULL << 56) - 1)) & 0x00ffffffffffffffULL)) |
| 137 | }; |
| 138 | |
| 139 | /* Cursor formats */ |
| 140 | static const u32 intel_cursor_formats[] = { |
| 141 | DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), |
| 142 | }; |
| 143 | |
| 144 | static const u64 cursor_format_modifiers[] = { |
| 145 | DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ), |
| 146 | DRM_FORMAT_MOD_INVALID((((__u64)0) << 56) | ((((1ULL << 56) - 1)) & 0x00ffffffffffffffULL)) |
| 147 | }; |
| 148 | |
| 149 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 150 | struct intel_crtc_state *pipe_config); |
| 151 | static void ilk_pch_clock_get(struct intel_crtc *crtc, |
| 152 | struct intel_crtc_state *pipe_config); |
| 153 | |
| 154 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
| 155 | struct drm_i915_gem_object *obj, |
| 156 | struct drm_mode_fb_cmd2 *mode_cmd); |
| 157 | static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state); |
| 158 | static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state); |
| 159 | static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
| 160 | const struct intel_link_m_n *m_n, |
| 161 | const struct intel_link_m_n *m2_n2); |
| 162 | static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state); |
| 163 | static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state); |
| 164 | static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state); |
| 165 | static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state); |
| 166 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
| 167 | const struct intel_crtc_state *pipe_config); |
| 168 | static void chv_prepare_pll(struct intel_crtc *crtc, |
| 169 | const struct intel_crtc_state *pipe_config); |
| 170 | static void skl_pfit_enable(const struct intel_crtc_state *crtc_state); |
| 171 | static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state); |
| 172 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
| 173 | struct drm_modeset_acquire_ctx *ctx); |
| 174 | static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc); |
| 175 | |
| 176 | struct intel_limit { |
| 177 | struct { |
| 178 | int min, max; |
| 179 | } dot, vco, n, m, m1, m2, p, p1; |
| 180 | |
| 181 | struct { |
| 182 | int dot_limit; |
| 183 | int p2_slow, p2_fast; |
| 184 | } p2; |
| 185 | }; |
| 186 | |
| 187 | /* returns HPLL frequency in kHz */ |
| 188 | int vlv_get_hpll_vco(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 189 | { |
| 190 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
| 191 | |
| 192 | /* Obtain SKU information */ |
| 193 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG0x8) & |
| 194 | CCK_FUSE_HPLL_FREQ_MASK0x3; |
| 195 | |
| 196 | return vco_freq[hpll_freq] * 1000; |
| 197 | } |
| 198 | |
| 199 | int vlv_get_cck_clock(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 200 | const char *name, u32 reg, int ref_freq) |
| 201 | { |
| 202 | u32 val; |
| 203 | int divider; |
| 204 | |
| 205 | val = vlv_cck_read(dev_priv, reg); |
| 206 | divider = val & CCK_FREQUENCY_VALUES(0x1f << 0); |
| 207 | |
| 208 | drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=({ int __ret = !!((val & (0x1f << 8)) != (divider << 8)); if (__ret) printf("%s %s: " "%s change in progress\n", dev_driver_string ((&dev_priv->drm)->dev), "", name); __builtin_expect (!!(__ret), 0); }) |
| 209 | (divider << CCK_FREQUENCY_STATUS_SHIFT),({ int __ret = !!((val & (0x1f << 8)) != (divider << 8)); if (__ret) printf("%s %s: " "%s change in progress\n", dev_driver_string ((&dev_priv->drm)->dev), "", name); __builtin_expect (!!(__ret), 0); }) |
| 210 | "%s change in progress\n", name)({ int __ret = !!((val & (0x1f << 8)) != (divider << 8)); if (__ret) printf("%s %s: " "%s change in progress\n", dev_driver_string ((&dev_priv->drm)->dev), "", name); __builtin_expect (!!(__ret), 0); }); |
| 211 | |
| 212 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1)(((ref_freq << 1) + ((divider + 1) / 2)) / (divider + 1 )); |
| 213 | } |
| 214 | |
| 215 | int vlv_get_cck_clock_hpll(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 216 | const char *name, u32 reg) |
| 217 | { |
| 218 | int hpll; |
| 219 | |
| 220 | vlv_cck_get(dev_priv); |
| 221 | |
| 222 | if (dev_priv->hpll_freq == 0) |
| 223 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
| 224 | |
| 225 | hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); |
| 226 | |
| 227 | vlv_cck_put(dev_priv); |
| 228 | |
| 229 | return hpll; |
| 230 | } |
| 231 | |
| 232 | static void intel_update_czclk(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 233 | { |
| 234 | if (!(IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))) |
| 235 | return; |
| 236 | |
| 237 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", |
| 238 | CCK_CZ_CLOCK_CONTROL0x62); |
| 239 | |
| 240 | drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "CZ clock rate: %d kHz\n" , dev_priv->czclk_freq) |
| 241 | dev_priv->czclk_freq)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "CZ clock rate: %d kHz\n" , dev_priv->czclk_freq); |
| 242 | } |
| 243 | |
| 244 | /* units of 100MHz */ |
| 245 | static u32 intel_fdi_link_freq(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 246 | const struct intel_crtc_state *pipe_config) |
| 247 | { |
| 248 | if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
| 249 | return pipe_config->port_clock; /* SPLL */ |
| 250 | else |
| 251 | return dev_priv->fdi_pll_freq; |
| 252 | } |
| 253 | |
| 254 | static const struct intel_limit intel_limits_i8xx_dac = { |
| 255 | .dot = { .min = 25000, .max = 350000 }, |
| 256 | .vco = { .min = 908000, .max = 1512000 }, |
| 257 | .n = { .min = 2, .max = 16 }, |
| 258 | .m = { .min = 96, .max = 140 }, |
| 259 | .m1 = { .min = 18, .max = 26 }, |
| 260 | .m2 = { .min = 6, .max = 16 }, |
| 261 | .p = { .min = 4, .max = 128 }, |
| 262 | .p1 = { .min = 2, .max = 33 }, |
| 263 | .p2 = { .dot_limit = 165000, |
| 264 | .p2_slow = 4, .p2_fast = 2 }, |
| 265 | }; |
| 266 | |
| 267 | static const struct intel_limit intel_limits_i8xx_dvo = { |
| 268 | .dot = { .min = 25000, .max = 350000 }, |
| 269 | .vco = { .min = 908000, .max = 1512000 }, |
| 270 | .n = { .min = 2, .max = 16 }, |
| 271 | .m = { .min = 96, .max = 140 }, |
| 272 | .m1 = { .min = 18, .max = 26 }, |
| 273 | .m2 = { .min = 6, .max = 16 }, |
| 274 | .p = { .min = 4, .max = 128 }, |
| 275 | .p1 = { .min = 2, .max = 33 }, |
| 276 | .p2 = { .dot_limit = 165000, |
| 277 | .p2_slow = 4, .p2_fast = 4 }, |
| 278 | }; |
| 279 | |
| 280 | static const struct intel_limit intel_limits_i8xx_lvds = { |
| 281 | .dot = { .min = 25000, .max = 350000 }, |
| 282 | .vco = { .min = 908000, .max = 1512000 }, |
| 283 | .n = { .min = 2, .max = 16 }, |
| 284 | .m = { .min = 96, .max = 140 }, |
| 285 | .m1 = { .min = 18, .max = 26 }, |
| 286 | .m2 = { .min = 6, .max = 16 }, |
| 287 | .p = { .min = 4, .max = 128 }, |
| 288 | .p1 = { .min = 1, .max = 6 }, |
| 289 | .p2 = { .dot_limit = 165000, |
| 290 | .p2_slow = 14, .p2_fast = 7 }, |
| 291 | }; |
| 292 | |
| 293 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
| 294 | .dot = { .min = 20000, .max = 400000 }, |
| 295 | .vco = { .min = 1400000, .max = 2800000 }, |
| 296 | .n = { .min = 1, .max = 6 }, |
| 297 | .m = { .min = 70, .max = 120 }, |
| 298 | .m1 = { .min = 8, .max = 18 }, |
| 299 | .m2 = { .min = 3, .max = 7 }, |
| 300 | .p = { .min = 5, .max = 80 }, |
| 301 | .p1 = { .min = 1, .max = 8 }, |
| 302 | .p2 = { .dot_limit = 200000, |
| 303 | .p2_slow = 10, .p2_fast = 5 }, |
| 304 | }; |
| 305 | |
| 306 | static const struct intel_limit intel_limits_i9xx_lvds = { |
| 307 | .dot = { .min = 20000, .max = 400000 }, |
| 308 | .vco = { .min = 1400000, .max = 2800000 }, |
| 309 | .n = { .min = 1, .max = 6 }, |
| 310 | .m = { .min = 70, .max = 120 }, |
| 311 | .m1 = { .min = 8, .max = 18 }, |
| 312 | .m2 = { .min = 3, .max = 7 }, |
| 313 | .p = { .min = 7, .max = 98 }, |
| 314 | .p1 = { .min = 1, .max = 8 }, |
| 315 | .p2 = { .dot_limit = 112000, |
| 316 | .p2_slow = 14, .p2_fast = 7 }, |
| 317 | }; |
| 318 | |
| 319 | |
| 320 | static const struct intel_limit intel_limits_g4x_sdvo = { |
| 321 | .dot = { .min = 25000, .max = 270000 }, |
| 322 | .vco = { .min = 1750000, .max = 3500000}, |
| 323 | .n = { .min = 1, .max = 4 }, |
| 324 | .m = { .min = 104, .max = 138 }, |
| 325 | .m1 = { .min = 17, .max = 23 }, |
| 326 | .m2 = { .min = 5, .max = 11 }, |
| 327 | .p = { .min = 10, .max = 30 }, |
| 328 | .p1 = { .min = 1, .max = 3}, |
| 329 | .p2 = { .dot_limit = 270000, |
| 330 | .p2_slow = 10, |
| 331 | .p2_fast = 10 |
| 332 | }, |
| 333 | }; |
| 334 | |
| 335 | static const struct intel_limit intel_limits_g4x_hdmi = { |
| 336 | .dot = { .min = 22000, .max = 400000 }, |
| 337 | .vco = { .min = 1750000, .max = 3500000}, |
| 338 | .n = { .min = 1, .max = 4 }, |
| 339 | .m = { .min = 104, .max = 138 }, |
| 340 | .m1 = { .min = 16, .max = 23 }, |
| 341 | .m2 = { .min = 5, .max = 11 }, |
| 342 | .p = { .min = 5, .max = 80 }, |
| 343 | .p1 = { .min = 1, .max = 8}, |
| 344 | .p2 = { .dot_limit = 165000, |
| 345 | .p2_slow = 10, .p2_fast = 5 }, |
| 346 | }; |
| 347 | |
| 348 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
| 349 | .dot = { .min = 20000, .max = 115000 }, |
| 350 | .vco = { .min = 1750000, .max = 3500000 }, |
| 351 | .n = { .min = 1, .max = 3 }, |
| 352 | .m = { .min = 104, .max = 138 }, |
| 353 | .m1 = { .min = 17, .max = 23 }, |
| 354 | .m2 = { .min = 5, .max = 11 }, |
| 355 | .p = { .min = 28, .max = 112 }, |
| 356 | .p1 = { .min = 2, .max = 8 }, |
| 357 | .p2 = { .dot_limit = 0, |
| 358 | .p2_slow = 14, .p2_fast = 14 |
| 359 | }, |
| 360 | }; |
| 361 | |
| 362 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
| 363 | .dot = { .min = 80000, .max = 224000 }, |
| 364 | .vco = { .min = 1750000, .max = 3500000 }, |
| 365 | .n = { .min = 1, .max = 3 }, |
| 366 | .m = { .min = 104, .max = 138 }, |
| 367 | .m1 = { .min = 17, .max = 23 }, |
| 368 | .m2 = { .min = 5, .max = 11 }, |
| 369 | .p = { .min = 14, .max = 42 }, |
| 370 | .p1 = { .min = 2, .max = 6 }, |
| 371 | .p2 = { .dot_limit = 0, |
| 372 | .p2_slow = 7, .p2_fast = 7 |
| 373 | }, |
| 374 | }; |
| 375 | |
| 376 | static const struct intel_limit pnv_limits_sdvo = { |
| 377 | .dot = { .min = 20000, .max = 400000}, |
| 378 | .vco = { .min = 1700000, .max = 3500000 }, |
| 379 | /* Pineview's Ncounter is a ring counter */ |
| 380 | .n = { .min = 3, .max = 6 }, |
| 381 | .m = { .min = 2, .max = 256 }, |
| 382 | /* Pineview only has one combined m divider, which we treat as m2. */ |
| 383 | .m1 = { .min = 0, .max = 0 }, |
| 384 | .m2 = { .min = 0, .max = 254 }, |
| 385 | .p = { .min = 5, .max = 80 }, |
| 386 | .p1 = { .min = 1, .max = 8 }, |
| 387 | .p2 = { .dot_limit = 200000, |
| 388 | .p2_slow = 10, .p2_fast = 5 }, |
| 389 | }; |
| 390 | |
| 391 | static const struct intel_limit pnv_limits_lvds = { |
| 392 | .dot = { .min = 20000, .max = 400000 }, |
| 393 | .vco = { .min = 1700000, .max = 3500000 }, |
| 394 | .n = { .min = 3, .max = 6 }, |
| 395 | .m = { .min = 2, .max = 256 }, |
| 396 | .m1 = { .min = 0, .max = 0 }, |
| 397 | .m2 = { .min = 0, .max = 254 }, |
| 398 | .p = { .min = 7, .max = 112 }, |
| 399 | .p1 = { .min = 1, .max = 8 }, |
| 400 | .p2 = { .dot_limit = 112000, |
| 401 | .p2_slow = 14, .p2_fast = 14 }, |
| 402 | }; |
| 403 | |
| 404 | /* Ironlake / Sandybridge |
| 405 | * |
| 406 | * We calculate clock using (register_value + 2) for N/M1/M2, so here |
| 407 | * the range value for them is (actual_value - 2). |
| 408 | */ |
| 409 | static const struct intel_limit ilk_limits_dac = { |
| 410 | .dot = { .min = 25000, .max = 350000 }, |
| 411 | .vco = { .min = 1760000, .max = 3510000 }, |
| 412 | .n = { .min = 1, .max = 5 }, |
| 413 | .m = { .min = 79, .max = 127 }, |
| 414 | .m1 = { .min = 12, .max = 22 }, |
| 415 | .m2 = { .min = 5, .max = 9 }, |
| 416 | .p = { .min = 5, .max = 80 }, |
| 417 | .p1 = { .min = 1, .max = 8 }, |
| 418 | .p2 = { .dot_limit = 225000, |
| 419 | .p2_slow = 10, .p2_fast = 5 }, |
| 420 | }; |
| 421 | |
| 422 | static const struct intel_limit ilk_limits_single_lvds = { |
| 423 | .dot = { .min = 25000, .max = 350000 }, |
| 424 | .vco = { .min = 1760000, .max = 3510000 }, |
| 425 | .n = { .min = 1, .max = 3 }, |
| 426 | .m = { .min = 79, .max = 118 }, |
| 427 | .m1 = { .min = 12, .max = 22 }, |
| 428 | .m2 = { .min = 5, .max = 9 }, |
| 429 | .p = { .min = 28, .max = 112 }, |
| 430 | .p1 = { .min = 2, .max = 8 }, |
| 431 | .p2 = { .dot_limit = 225000, |
| 432 | .p2_slow = 14, .p2_fast = 14 }, |
| 433 | }; |
| 434 | |
| 435 | static const struct intel_limit ilk_limits_dual_lvds = { |
| 436 | .dot = { .min = 25000, .max = 350000 }, |
| 437 | .vco = { .min = 1760000, .max = 3510000 }, |
| 438 | .n = { .min = 1, .max = 3 }, |
| 439 | .m = { .min = 79, .max = 127 }, |
| 440 | .m1 = { .min = 12, .max = 22 }, |
| 441 | .m2 = { .min = 5, .max = 9 }, |
| 442 | .p = { .min = 14, .max = 56 }, |
| 443 | .p1 = { .min = 2, .max = 8 }, |
| 444 | .p2 = { .dot_limit = 225000, |
| 445 | .p2_slow = 7, .p2_fast = 7 }, |
| 446 | }; |
| 447 | |
| 448 | /* LVDS 100mhz refclk limits. */ |
| 449 | static const struct intel_limit ilk_limits_single_lvds_100m = { |
| 450 | .dot = { .min = 25000, .max = 350000 }, |
| 451 | .vco = { .min = 1760000, .max = 3510000 }, |
| 452 | .n = { .min = 1, .max = 2 }, |
| 453 | .m = { .min = 79, .max = 126 }, |
| 454 | .m1 = { .min = 12, .max = 22 }, |
| 455 | .m2 = { .min = 5, .max = 9 }, |
| 456 | .p = { .min = 28, .max = 112 }, |
| 457 | .p1 = { .min = 2, .max = 8 }, |
| 458 | .p2 = { .dot_limit = 225000, |
| 459 | .p2_slow = 14, .p2_fast = 14 }, |
| 460 | }; |
| 461 | |
| 462 | static const struct intel_limit ilk_limits_dual_lvds_100m = { |
| 463 | .dot = { .min = 25000, .max = 350000 }, |
| 464 | .vco = { .min = 1760000, .max = 3510000 }, |
| 465 | .n = { .min = 1, .max = 3 }, |
| 466 | .m = { .min = 79, .max = 126 }, |
| 467 | .m1 = { .min = 12, .max = 22 }, |
| 468 | .m2 = { .min = 5, .max = 9 }, |
| 469 | .p = { .min = 14, .max = 42 }, |
| 470 | .p1 = { .min = 2, .max = 6 }, |
| 471 | .p2 = { .dot_limit = 225000, |
| 472 | .p2_slow = 7, .p2_fast = 7 }, |
| 473 | }; |
| 474 | |
| 475 | static const struct intel_limit intel_limits_vlv = { |
| 476 | /* |
| 477 | * These are the data rate limits (measured in fast clocks) |
| 478 | * since those are the strictest limits we have. The fast |
| 479 | * clock and actual rate limits are more relaxed, so checking |
| 480 | * them would make no difference. |
| 481 | */ |
| 482 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, |
| 483 | .vco = { .min = 4000000, .max = 6000000 }, |
| 484 | .n = { .min = 1, .max = 7 }, |
| 485 | .m1 = { .min = 2, .max = 3 }, |
| 486 | .m2 = { .min = 11, .max = 156 }, |
| 487 | .p1 = { .min = 2, .max = 3 }, |
| 488 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
| 489 | }; |
| 490 | |
| 491 | static const struct intel_limit intel_limits_chv = { |
| 492 | /* |
| 493 | * These are the data rate limits (measured in fast clocks) |
| 494 | * since those are the strictest limits we have. The fast |
| 495 | * clock and actual rate limits are more relaxed, so checking |
| 496 | * them would make no difference. |
| 497 | */ |
| 498 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, |
| 499 | .vco = { .min = 4800000, .max = 6480000 }, |
| 500 | .n = { .min = 1, .max = 1 }, |
| 501 | .m1 = { .min = 2, .max = 2 }, |
| 502 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, |
| 503 | .p1 = { .min = 2, .max = 4 }, |
| 504 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, |
| 505 | }; |
| 506 | |
| 507 | static const struct intel_limit intel_limits_bxt = { |
| 508 | /* FIXME: find real dot limits */ |
| 509 | .dot = { .min = 0, .max = INT_MAX0x7fffffff }, |
| 510 | .vco = { .min = 4800000, .max = 6700000 }, |
| 511 | .n = { .min = 1, .max = 1 }, |
| 512 | .m1 = { .min = 2, .max = 2 }, |
| 513 | /* FIXME: find real m2 limits */ |
| 514 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, |
| 515 | .p1 = { .min = 2, .max = 4 }, |
| 516 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, |
| 517 | }; |
| 518 | |
| 519 | /* WA Display #0827: Gen9:all */ |
| 520 | static void |
| 521 | skl_wa_827(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe, bool_Bool enable) |
| 522 | { |
| 523 | if (enable) |
| 524 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) }), |
| 525 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) })) | DUPS1_GATING_DIS(1 << 15) | DUPS2_GATING_DIS(1 << 19)); |
| 526 | else |
| 527 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) }), |
| 528 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) })) & ~(DUPS1_GATING_DIS(1 << 15) | DUPS2_GATING_DIS(1 << 19))); |
| 529 | } |
| 530 | |
| 531 | /* Wa_2006604312:icl,ehl */ |
| 532 | static void |
| 533 | icl_wa_scalerclkgating(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe, |
| 534 | bool_Bool enable) |
| 535 | { |
| 536 | if (enable) |
| 537 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) }), |
| 538 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) })) | DPFR_GATING_DIS(1 << 8)); |
| 539 | else |
| 540 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) }), |
| 541 | intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) })) & ~DPFR_GATING_DIS(1 << 8)); |
| 542 | } |
| 543 | |
| 544 | static bool_Bool |
| 545 | needs_modeset(const struct intel_crtc_state *state) |
| 546 | { |
| 547 | return drm_atomic_crtc_needs_modeset(&state->uapi); |
| 548 | } |
| 549 | |
| 550 | static bool_Bool |
| 551 | is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state) |
| 552 | { |
| 553 | return crtc_state->master_transcoder != INVALID_TRANSCODER; |
| 554 | } |
| 555 | |
| 556 | static bool_Bool |
| 557 | is_trans_port_sync_master(const struct intel_crtc_state *crtc_state) |
| 558 | { |
| 559 | return crtc_state->sync_mode_slaves_mask != 0; |
| 560 | } |
| 561 | |
| 562 | bool_Bool |
| 563 | is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) |
| 564 | { |
| 565 | return is_trans_port_sync_master(crtc_state) || |
| 566 | is_trans_port_sync_slave(crtc_state); |
| 567 | } |
| 568 | |
| 569 | /* |
| 570 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), |
| 571 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast |
| 572 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. |
| 573 | * The helpers' return value is the rate of the clock that is fed to the |
| 574 | * display engine's pipe which can be the above fast dot clock rate or a |
| 575 | * divided-down version of it. |
| 576 | */ |
| 577 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
| 578 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
| 579 | { |
| 580 | clock->m = clock->m2 + 2; |
| 581 | clock->p = clock->p1 * clock->p2; |
| 582 | if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!((clock->n == 0 || clock->p == 0)); if (__ret) printf("%s", "WARN_ON(" "clock->n == 0 || clock->p == 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 583 | return 0; |
| 584 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n)(((refclk * clock->m) + ((clock->n) / 2)) / (clock-> n)); |
| 585 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
| 586 | |
| 587 | return clock->dot; |
| 588 | } |
| 589 | |
| 590 | static u32 i9xx_dpll_compute_m(struct dpll *dpll) |
| 591 | { |
| 592 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); |
| 593 | } |
| 594 | |
| 595 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
| 596 | { |
| 597 | clock->m = i9xx_dpll_compute_m(clock); |
| 598 | clock->p = clock->p1 * clock->p2; |
| 599 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)({ int __ret = !!((clock->n + 2 == 0 || clock->p == 0)) ; if (__ret) printf("%s", "WARN_ON(" "clock->n + 2 == 0 || clock->p == 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 600 | return 0; |
| 601 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2)(((refclk * clock->m) + ((clock->n + 2) / 2)) / (clock-> n + 2)); |
| 602 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
| 603 | |
| 604 | return clock->dot; |
| 605 | } |
| 606 | |
| 607 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
| 608 | { |
| 609 | clock->m = clock->m1 * clock->m2; |
| 610 | clock->p = clock->p1 * clock->p2; |
| 611 | if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!((clock->n == 0 || clock->p == 0)); if (__ret) printf("%s", "WARN_ON(" "clock->n == 0 || clock->p == 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 612 | return 0; |
| 613 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n)(((refclk * clock->m) + ((clock->n) / 2)) / (clock-> n)); |
| 614 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
| 615 | |
| 616 | return clock->dot / 5; |
| 617 | } |
| 618 | |
| 619 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
| 620 | { |
| 621 | clock->m = clock->m1 * clock->m2; |
| 622 | clock->p = clock->p1 * clock->p2; |
| 623 | if (WARN_ON(clock->n == 0 || clock->p == 0)({ int __ret = !!((clock->n == 0 || clock->p == 0)); if (__ret) printf("%s", "WARN_ON(" "clock->n == 0 || clock->p == 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 624 | return 0; |
| 625 | clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m),(((mul_u32_u32(refclk, clock->m)) + ((clock->n << 22) / 2)) / (clock->n << 22)) |
| 626 | clock->n << 22)(((mul_u32_u32(refclk, clock->m)) + ((clock->n << 22) / 2)) / (clock->n << 22)); |
| 627 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p)(((clock->vco) + ((clock->p) / 2)) / (clock->p)); |
| 628 | |
| 629 | return clock->dot / 5; |
| 630 | } |
| 631 | |
| 632 | /* |
| 633 | * Returns whether the given set of divisors are valid for a given refclk with |
| 634 | * the given connectors. |
| 635 | */ |
| 636 | static bool_Bool intel_pll_is_valid(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 637 | const struct intel_limit *limit, |
| 638 | const struct dpll *clock) |
| 639 | { |
| 640 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
| 641 | return false0; |
| 642 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
| 643 | return false0; |
| 644 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
| 645 | return false0; |
| 646 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
| 647 | return false0; |
| 648 | |
| 649 | if (!IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) && !IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && |
| 650 | !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && !IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) |
| 651 | if (clock->m1 <= clock->m2) |
| 652 | return false0; |
| 653 | |
| 654 | if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && |
| 655 | !IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) { |
| 656 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
| 657 | return false0; |
| 658 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
| 659 | return false0; |
| 660 | } |
| 661 | |
| 662 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
| 663 | return false0; |
| 664 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
| 665 | * connector, etc., rather than just a single range. |
| 666 | */ |
| 667 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) |
| 668 | return false0; |
| 669 | |
| 670 | return true1; |
| 671 | } |
| 672 | |
| 673 | static int |
| 674 | i9xx_select_p2_div(const struct intel_limit *limit, |
| 675 | const struct intel_crtc_state *crtc_state, |
| 676 | int target) |
| 677 | { |
| 678 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 679 | |
| 680 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 681 | /* |
| 682 | * For LVDS just rely on its current settings for dual-channel. |
| 683 | * We haven't figured out how to reliably set up different |
| 684 | * single/dual channel state, if we even can. |
| 685 | */ |
| 686 | if (intel_is_dual_link_lvds(dev_priv)) |
| 687 | return limit->p2.p2_fast; |
| 688 | else |
| 689 | return limit->p2.p2_slow; |
| 690 | } else { |
| 691 | if (target < limit->p2.dot_limit) |
| 692 | return limit->p2.p2_slow; |
| 693 | else |
| 694 | return limit->p2.p2_fast; |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | /* |
| 699 | * Returns a set of divisors for the desired target clock with the given |
| 700 | * refclk, or FALSE. The returned values represent the clock equation: |
| 701 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 702 | * |
| 703 | * Target and reference clocks are specified in kHz. |
| 704 | * |
| 705 | * If match_clock is provided, then best_clock P divider must match the P |
| 706 | * divider from @match_clock used for LVDS downclocking. |
| 707 | */ |
| 708 | static bool_Bool |
| 709 | i9xx_find_best_dpll(const struct intel_limit *limit, |
| 710 | struct intel_crtc_state *crtc_state, |
| 711 | int target, int refclk, struct dpll *match_clock, |
| 712 | struct dpll *best_clock) |
| 713 | { |
| 714 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
| 715 | struct dpll clock; |
| 716 | int err = target; |
| 717 | |
| 718 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
| 719 | |
| 720 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 721 | |
| 722 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 723 | clock.m1++) { |
| 724 | for (clock.m2 = limit->m2.min; |
| 725 | clock.m2 <= limit->m2.max; clock.m2++) { |
| 726 | if (clock.m2 >= clock.m1) |
| 727 | break; |
| 728 | for (clock.n = limit->n.min; |
| 729 | clock.n <= limit->n.max; clock.n++) { |
| 730 | for (clock.p1 = limit->p1.min; |
| 731 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 732 | int this_err; |
| 733 | |
| 734 | i9xx_calc_dpll_params(refclk, &clock); |
| 735 | if (!intel_pll_is_valid(to_i915(dev), |
| 736 | limit, |
| 737 | &clock)) |
| 738 | continue; |
| 739 | if (match_clock && |
| 740 | clock.p != match_clock->p) |
| 741 | continue; |
| 742 | |
| 743 | this_err = abs(clock.dot - target); |
| 744 | if (this_err < err) { |
| 745 | *best_clock = clock; |
| 746 | err = this_err; |
| 747 | } |
| 748 | } |
| 749 | } |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | return (err != target); |
| 754 | } |
| 755 | |
| 756 | /* |
| 757 | * Returns a set of divisors for the desired target clock with the given |
| 758 | * refclk, or FALSE. The returned values represent the clock equation: |
| 759 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 760 | * |
| 761 | * Target and reference clocks are specified in kHz. |
| 762 | * |
| 763 | * If match_clock is provided, then best_clock P divider must match the P |
| 764 | * divider from @match_clock used for LVDS downclocking. |
| 765 | */ |
| 766 | static bool_Bool |
| 767 | pnv_find_best_dpll(const struct intel_limit *limit, |
| 768 | struct intel_crtc_state *crtc_state, |
| 769 | int target, int refclk, struct dpll *match_clock, |
| 770 | struct dpll *best_clock) |
| 771 | { |
| 772 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
| 773 | struct dpll clock; |
| 774 | int err = target; |
| 775 | |
| 776 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
| 777 | |
| 778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 779 | |
| 780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
| 781 | clock.m1++) { |
| 782 | for (clock.m2 = limit->m2.min; |
| 783 | clock.m2 <= limit->m2.max; clock.m2++) { |
| 784 | for (clock.n = limit->n.min; |
| 785 | clock.n <= limit->n.max; clock.n++) { |
| 786 | for (clock.p1 = limit->p1.min; |
| 787 | clock.p1 <= limit->p1.max; clock.p1++) { |
| 788 | int this_err; |
| 789 | |
| 790 | pnv_calc_dpll_params(refclk, &clock); |
| 791 | if (!intel_pll_is_valid(to_i915(dev), |
| 792 | limit, |
| 793 | &clock)) |
| 794 | continue; |
| 795 | if (match_clock && |
| 796 | clock.p != match_clock->p) |
| 797 | continue; |
| 798 | |
| 799 | this_err = abs(clock.dot - target); |
| 800 | if (this_err < err) { |
| 801 | *best_clock = clock; |
| 802 | err = this_err; |
| 803 | } |
| 804 | } |
| 805 | } |
| 806 | } |
| 807 | } |
| 808 | |
| 809 | return (err != target); |
| 810 | } |
| 811 | |
| 812 | /* |
| 813 | * Returns a set of divisors for the desired target clock with the given |
| 814 | * refclk, or FALSE. The returned values represent the clock equation: |
| 815 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 816 | * |
| 817 | * Target and reference clocks are specified in kHz. |
| 818 | * |
| 819 | * If match_clock is provided, then best_clock P divider must match the P |
| 820 | * divider from @match_clock used for LVDS downclocking. |
| 821 | */ |
| 822 | static bool_Bool |
| 823 | g4x_find_best_dpll(const struct intel_limit *limit, |
| 824 | struct intel_crtc_state *crtc_state, |
| 825 | int target, int refclk, struct dpll *match_clock, |
| 826 | struct dpll *best_clock) |
| 827 | { |
| 828 | struct drm_device *dev = crtc_state->uapi.crtc->dev; |
| 829 | struct dpll clock; |
| 830 | int max_n; |
| 831 | bool_Bool found = false0; |
| 832 | /* approximately equals target * 0.00585 */ |
| 833 | int err_most = (target >> 8) + (target >> 9); |
| 834 | |
| 835 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
| 836 | |
| 837 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
| 838 | |
| 839 | max_n = limit->n.max; |
| 840 | /* based on hardware requirement, prefer smaller n to precision */ |
| 841 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
| 842 | /* based on hardware requirement, prefere larger m1,m2 */ |
| 843 | for (clock.m1 = limit->m1.max; |
| 844 | clock.m1 >= limit->m1.min; clock.m1--) { |
| 845 | for (clock.m2 = limit->m2.max; |
| 846 | clock.m2 >= limit->m2.min; clock.m2--) { |
| 847 | for (clock.p1 = limit->p1.max; |
| 848 | clock.p1 >= limit->p1.min; clock.p1--) { |
| 849 | int this_err; |
| 850 | |
| 851 | i9xx_calc_dpll_params(refclk, &clock); |
| 852 | if (!intel_pll_is_valid(to_i915(dev), |
| 853 | limit, |
| 854 | &clock)) |
| 855 | continue; |
| 856 | |
| 857 | this_err = abs(clock.dot - target); |
| 858 | if (this_err < err_most) { |
| 859 | *best_clock = clock; |
| 860 | err_most = this_err; |
| 861 | max_n = clock.n; |
| 862 | found = true1; |
| 863 | } |
| 864 | } |
| 865 | } |
| 866 | } |
| 867 | } |
| 868 | return found; |
| 869 | } |
| 870 | |
| 871 | /* |
| 872 | * Check if the calculated PLL configuration is more optimal compared to the |
| 873 | * best configuration and error found so far. Return the calculated error. |
| 874 | */ |
| 875 | static bool_Bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, |
| 876 | const struct dpll *calculated_clock, |
| 877 | const struct dpll *best_clock, |
| 878 | unsigned int best_error_ppm, |
| 879 | unsigned int *error_ppm) |
| 880 | { |
| 881 | /* |
| 882 | * For CHV ignore the error and consider only the P value. |
| 883 | * Prefer a bigger P value based on HW requirements. |
| 884 | */ |
| 885 | if (IS_CHERRYVIEW(to_i915(dev))IS_PLATFORM(to_i915(dev), INTEL_CHERRYVIEW)) { |
| 886 | *error_ppm = 0; |
| 887 | |
| 888 | return calculated_clock->p > best_clock->p; |
| 889 | } |
| 890 | |
| 891 | if (drm_WARN_ON_ONCE(dev, !target_freq)({ static int __warned; int __ret = !!((!target_freq)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string (((dev))->dev), "", "drm_WARN_ON_ONCE(" "!target_freq" ")" ); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
| 892 | return false0; |
| 893 | |
| 894 | *error_ppm = div_u64(1000000ULL * |
| 895 | abs(target_freq - calculated_clock->dot), |
| 896 | target_freq); |
| 897 | /* |
| 898 | * Prefer a better P value over a better (smaller) error if the error |
| 899 | * is small. Ensure this preference for future configurations too by |
| 900 | * setting the error to 0. |
| 901 | */ |
| 902 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { |
| 903 | *error_ppm = 0; |
| 904 | |
| 905 | return true1; |
| 906 | } |
| 907 | |
| 908 | return *error_ppm + 10 < best_error_ppm; |
| 909 | } |
| 910 | |
| 911 | /* |
| 912 | * Returns a set of divisors for the desired target clock with the given |
| 913 | * refclk, or FALSE. The returned values represent the clock equation: |
| 914 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 915 | */ |
| 916 | static bool_Bool |
| 917 | vlv_find_best_dpll(const struct intel_limit *limit, |
| 918 | struct intel_crtc_state *crtc_state, |
| 919 | int target, int refclk, struct dpll *match_clock, |
| 920 | struct dpll *best_clock) |
| 921 | { |
| 922 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 923 | struct drm_device *dev = crtc->base.dev; |
| 924 | struct dpll clock; |
| 925 | unsigned int bestppm = 1000000; |
| 926 | /* min update 19.2 MHz */ |
| 927 | int max_n = min(limit->n.max, refclk / 19200)(((limit->n.max)<(refclk / 19200))?(limit->n.max):(refclk / 19200)); |
| 928 | bool_Bool found = false0; |
| 929 | |
| 930 | target *= 5; /* fast clock */ |
| 931 | |
| 932 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
| 933 | |
| 934 | /* based on hardware requirement, prefer smaller n to precision */ |
| 935 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
| 936 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 937 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
| 938 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
| 939 | clock.p = clock.p1 * clock.p2; |
| 940 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
| 941 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
| 942 | unsigned int ppm; |
| 943 | |
| 944 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,(((target * clock.p * clock.n) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)) |
| 945 | refclk * clock.m1)(((target * clock.p * clock.n) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)); |
| 946 | |
| 947 | vlv_calc_dpll_params(refclk, &clock); |
| 948 | |
| 949 | if (!intel_pll_is_valid(to_i915(dev), |
| 950 | limit, |
| 951 | &clock)) |
| 952 | continue; |
| 953 | |
| 954 | if (!vlv_PLL_is_optimal(dev, target, |
| 955 | &clock, |
| 956 | best_clock, |
| 957 | bestppm, &ppm)) |
| 958 | continue; |
| 959 | |
| 960 | *best_clock = clock; |
| 961 | bestppm = ppm; |
| 962 | found = true1; |
| 963 | } |
| 964 | } |
| 965 | } |
| 966 | } |
| 967 | |
| 968 | return found; |
| 969 | } |
| 970 | |
| 971 | /* |
| 972 | * Returns a set of divisors for the desired target clock with the given |
| 973 | * refclk, or FALSE. The returned values represent the clock equation: |
| 974 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. |
| 975 | */ |
| 976 | static bool_Bool |
| 977 | chv_find_best_dpll(const struct intel_limit *limit, |
| 978 | struct intel_crtc_state *crtc_state, |
| 979 | int target, int refclk, struct dpll *match_clock, |
| 980 | struct dpll *best_clock) |
| 981 | { |
| 982 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 983 | struct drm_device *dev = crtc->base.dev; |
| 984 | unsigned int best_error_ppm; |
| 985 | struct dpll clock; |
| 986 | u64 m2; |
| 987 | int found = false0; |
| 988 | |
| 989 | memset(best_clock, 0, sizeof(*best_clock))__builtin_memset((best_clock), (0), (sizeof(*best_clock))); |
| 990 | best_error_ppm = 1000000; |
| 991 | |
| 992 | /* |
| 993 | * Based on hardware doc, the n always set to 1, and m1 always |
| 994 | * set to 2. If requires to support 200Mhz refclk, we need to |
| 995 | * revisit this because n may not 1 anymore. |
| 996 | */ |
| 997 | clock.n = 1, clock.m1 = 2; |
| 998 | target *= 5; /* fast clock */ |
| 999 | |
| 1000 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
| 1001 | for (clock.p2 = limit->p2.p2_fast; |
| 1002 | clock.p2 >= limit->p2.p2_slow; |
| 1003 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
| 1004 | unsigned int error_ppm; |
| 1005 | |
| 1006 | clock.p = clock.p1 * clock.p2; |
| 1007 | |
| 1008 | m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,(((mul_u32_u32(target, clock.p * clock.n) << 22) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)) |
| 1009 | refclk * clock.m1)(((mul_u32_u32(target, clock.p * clock.n) << 22) + ((refclk * clock.m1) / 2)) / (refclk * clock.m1)); |
| 1010 | |
| 1011 | if (m2 > INT_MAX0x7fffffff/clock.m1) |
| 1012 | continue; |
| 1013 | |
| 1014 | clock.m2 = m2; |
| 1015 | |
| 1016 | chv_calc_dpll_params(refclk, &clock); |
| 1017 | |
| 1018 | if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) |
| 1019 | continue; |
| 1020 | |
| 1021 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
| 1022 | best_error_ppm, &error_ppm)) |
| 1023 | continue; |
| 1024 | |
| 1025 | *best_clock = clock; |
| 1026 | best_error_ppm = error_ppm; |
| 1027 | found = true1; |
| 1028 | } |
| 1029 | } |
| 1030 | |
| 1031 | return found; |
| 1032 | } |
| 1033 | |
| 1034 | bool_Bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, |
| 1035 | struct dpll *best_clock) |
| 1036 | { |
| 1037 | int refclk = 100000; |
| 1038 | const struct intel_limit *limit = &intel_limits_bxt; |
| 1039 | |
| 1040 | return chv_find_best_dpll(limit, crtc_state, |
| 1041 | crtc_state->port_clock, refclk, |
| 1042 | NULL((void *)0), best_clock); |
| 1043 | } |
| 1044 | |
| 1045 | static bool_Bool pipe_scanline_is_moving(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1046 | enum pipe pipe) |
| 1047 | { |
| 1048 | i915_reg_t reg = PIPEDSL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70000) + ((&(dev_priv)->__info)->display_mmio_offset )) }); |
| 1049 | u32 line1, line2; |
| 1050 | u32 line_mask; |
| 1051 | |
| 1052 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 1053 | line_mask = DSL_LINEMASK_GEN20x00000fff; |
| 1054 | else |
| 1055 | line_mask = DSL_LINEMASK_GEN30x00001fff; |
| 1056 | |
| 1057 | line1 = intel_de_read(dev_priv, reg) & line_mask; |
| 1058 | drm_msleep(5)mdelay(5); |
| 1059 | line2 = intel_de_read(dev_priv, reg) & line_mask; |
| 1060 | |
| 1061 | return line1 != line2; |
| 1062 | } |
| 1063 | |
| 1064 | static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool_Bool state) |
| 1065 | { |
| 1066 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1067 | enum pipe pipe = crtc->pipe; |
| 1068 | |
| 1069 | /* Wait for the display line to settle/start moving */ |
| 1070 | if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (((100) * 1000))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if (((pipe_scanline_is_moving (dev_priv, pipe) == state))) { ret__ = 0; break; } if (expired__ ) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((1000))) wait__ <<= 1; } ret__; })) |
| 1071 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "pipe %c scanline %s wait timed out\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), onoff(state)) |
| 1072 | "pipe %c scanline %s wait timed out\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "pipe %c scanline %s wait timed out\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), onoff(state)) |
| 1073 | pipe_name(pipe), onoff(state))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "pipe %c scanline %s wait timed out\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), onoff(state)); |
| 1074 | } |
| 1075 | |
| 1076 | static void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc) |
| 1077 | { |
| 1078 | wait_for_pipe_scanline_moving(crtc, false0); |
| 1079 | } |
| 1080 | |
| 1081 | static void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) |
| 1082 | { |
| 1083 | wait_for_pipe_scanline_moving(crtc, true1); |
| 1084 | } |
| 1085 | |
| 1086 | static void |
| 1087 | intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) |
| 1088 | { |
| 1089 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1090 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1091 | |
| 1092 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 1093 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
| 1094 | i915_reg_t reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) }); |
| 1095 | |
| 1096 | /* Wait for the Pipe State to go off */ |
| 1097 | if (intel_de_wait_for_clear(dev_priv, reg, |
| 1098 | I965_PIPECONF_ACTIVE(1 << 30), 100)) |
| 1099 | drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "pipe_off wait timed out\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }) |
| 1100 | "pipe_off wait timed out\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "pipe_off wait timed out\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }); |
| 1101 | } else { |
| 1102 | intel_wait_for_pipe_scanline_stopped(crtc); |
| 1103 | } |
| 1104 | } |
| 1105 | |
| 1106 | /* Only for pre-ILK configs */ |
| 1107 | void assert_pll(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1108 | enum pipe pipe, bool_Bool state) |
| 1109 | { |
| 1110 | u32 val; |
| 1111 | bool_Bool cur_state; |
| 1112 | |
| 1113 | val = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 1114 | cur_state = !!(val & DPLL_VCO_ENABLE(1 << 31)); |
| 1115 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1116 | "PLL state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1117 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1118 | } |
| 1119 | |
| 1120 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
| 1121 | void assert_dsi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, bool_Bool state) |
| 1122 | { |
| 1123 | u32 val; |
| 1124 | bool_Bool cur_state; |
| 1125 | |
| 1126 | vlv_cck_get(dev_priv); |
| 1127 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL0x48); |
| 1128 | vlv_cck_put(dev_priv); |
| 1129 | |
| 1130 | cur_state = val & DSI_PLL_VCO_EN(1 << 31); |
| 1131 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("DSI PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("DSI PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1132 | "DSI PLL state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("DSI PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("DSI PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1133 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("DSI PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("DSI PLL state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1134 | } |
| 1135 | |
| 1136 | static void assert_fdi_tx(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1137 | enum pipe pipe, bool_Bool state) |
| 1138 | { |
| 1139 | bool_Bool cur_state; |
| 1140 | |
| 1141 | if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) { |
| 1142 | /* |
| 1143 | * DDI does not have a specific FDI_TX register. |
| 1144 | * |
| 1145 | * FDI is never fed from EDP transcoder |
| 1146 | * so pipe->transcoder cast is fine here. |
| 1147 | */ |
| 1148 | enum transcoder cpu_transcoder = (enum transcoder)pipe; |
| 1149 | u32 val = intel_de_read(dev_priv, |
| 1150 | TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60400) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 1151 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE(1 << 31)); |
| 1152 | } else { |
| 1153 | u32 val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) })); |
| 1154 | cur_state = !!(val & FDI_TX_ENABLE(1 << 31)); |
| 1155 | } |
| 1156 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI TX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI TX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1157 | "FDI TX state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI TX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI TX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1158 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI TX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI TX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1159 | } |
| 1160 | #define assert_fdi_tx_enabled(d, p)assert_fdi_tx(d, p, 1) assert_fdi_tx(d, p, true1) |
| 1161 | #define assert_fdi_tx_disabled(d, p)assert_fdi_tx(d, p, 0) assert_fdi_tx(d, p, false0) |
| 1162 | |
| 1163 | static void assert_fdi_rx(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1164 | enum pipe pipe, bool_Bool state) |
| 1165 | { |
| 1166 | u32 val; |
| 1167 | bool_Bool cur_state; |
| 1168 | |
| 1169 | val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) })); |
| 1170 | cur_state = !!(val & FDI_RX_ENABLE(1 << 31)); |
| 1171 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI RX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI RX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1172 | "FDI RX state assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI RX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI RX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1173 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI RX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI RX state assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1174 | } |
| 1175 | #define assert_fdi_rx_enabled(d, p)assert_fdi_rx(d, p, 1) assert_fdi_rx(d, p, true1) |
| 1176 | #define assert_fdi_rx_disabled(d, p)assert_fdi_rx(d, p, 0) assert_fdi_rx(d, p, false0) |
| 1177 | |
| 1178 | static void assert_fdi_tx_pll_enabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1179 | enum pipe pipe) |
| 1180 | { |
| 1181 | u32 val; |
| 1182 | |
| 1183 | /* ILK FDI PLL is always enabled */ |
| 1184 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) |
| 1185 | return; |
| 1186 | |
| 1187 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
| 1188 | if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
| 1189 | return; |
| 1190 | |
| 1191 | val = intel_de_read(dev_priv, FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) })); |
| 1192 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n")({ int __ret_warn_on = !!(!(val & (1 << 14))); if ( __builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = ! !(i915_modparams.verbose_state_checks); if (__ret) printf("FDI TX PLL assertion failure, should be active but is disabled\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("FDI TX PLL assertion failure, should be active but is disabled\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1193 | } |
| 1194 | |
| 1195 | void assert_fdi_rx_pll(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1196 | enum pipe pipe, bool_Bool state) |
| 1197 | { |
| 1198 | u32 val; |
| 1199 | bool_Bool cur_state; |
| 1200 | |
| 1201 | val = intel_de_read(dev_priv, FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) })); |
| 1202 | cur_state = !!(val & FDI_RX_PLL_ENABLE(1 << 13)); |
| 1203 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI RX PLL assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI RX PLL assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1204 | "FDI RX PLL assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI RX PLL assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI RX PLL assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1205 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("FDI RX PLL assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret) , 0); })) __drm_err("FDI RX PLL assertion failure (expected %s, current %s)\n" , onoff(state), onoff(cur_state)); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1206 | } |
| 1207 | |
| 1208 | void assert_panel_unlocked(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 1209 | { |
| 1210 | i915_reg_t pp_reg; |
| 1211 | u32 val; |
| 1212 | enum pipe panel_pipe = INVALID_PIPE; |
| 1213 | bool_Bool locked = true1; |
| 1214 | |
| 1215 | if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))({ int __ret = !!((((&(dev_priv)->__info)->display. has_ddi))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__info)->display.has_ddi)" ")"); __builtin_expect(!!(__ret), 0); })) |
| 1216 | return; |
| 1217 | |
| 1218 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 1219 | u32 port_sel; |
| 1220 | |
| 1221 | pp_reg = PP_CONTROL(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (0) * 0x100) }); |
| 1222 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61208) + (0) * 0x100) })) & PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)); |
| 1223 | |
| 1224 | switch (port_sel) { |
| 1225 | case PANEL_PORT_SELECT_LVDS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
| 1226 | intel_lvds_port_enabled(dev_priv, PCH_LVDS((const i915_reg_t){ .reg = (0xe1180) }), &panel_pipe); |
| 1227 | break; |
| 1228 | case PANEL_PORT_SELECT_DPA((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
| 1229 | intel_dp_port_enabled(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), PORT_A, &panel_pipe); |
| 1230 | break; |
| 1231 | case PANEL_PORT_SELECT_DPC((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
| 1232 | intel_dp_port_enabled(dev_priv, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) }), PORT_C, &panel_pipe); |
| 1233 | break; |
| 1234 | case PANEL_PORT_SELECT_DPD((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
| 1235 | intel_dp_port_enabled(dev_priv, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) }), PORT_D, &panel_pipe); |
| 1236 | break; |
| 1237 | default: |
| 1238 | MISSING_CASE(port_sel)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "port_sel", (long)(port_sel)); __builtin_expect(!!(__ret), 0 ); }); |
| 1239 | break; |
| 1240 | } |
| 1241 | } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 1242 | /* presumably write lock depends on pipe, not port select */ |
| 1243 | pp_reg = PP_CONTROL(pipe)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (pipe) * 0x100) }); |
| 1244 | panel_pipe = pipe; |
| 1245 | } else { |
| 1246 | u32 port_sel; |
| 1247 | |
| 1248 | pp_reg = PP_CONTROL(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (0) * 0x100) }); |
| 1249 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61208) + (0) * 0x100) })) & PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)); |
| 1250 | |
| 1251 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((port_sel != ((u32)((((typeof(((u32)((((~0UL ) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0 ))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0)))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "port_sel != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1252 | port_sel != PANEL_PORT_SELECT_LVDS)({ int __ret = !!((port_sel != ((u32)((((typeof(((u32)((((~0UL ) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0 ))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0)))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "port_sel != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1253 | intel_lvds_port_enabled(dev_priv, LVDS((const i915_reg_t){ .reg = (0x61180) }), &panel_pipe); |
| 1254 | } |
| 1255 | |
| 1256 | val = intel_de_read(dev_priv, pp_reg); |
| 1257 | if (!(val & PANEL_POWER_ON((u32)((1UL << (0)) + 0))) || |
| 1258 | ((val & PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) == PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )))) |
| 1259 | locked = false0; |
| 1260 | |
| 1261 | I915_STATE_WARN(panel_pipe == pipe && locked,({ int __ret_warn_on = !!(panel_pipe == pipe && locked ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A' )); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1262 | "panel assertion failure, pipe %c regs locked\n",({ int __ret_warn_on = !!(panel_pipe == pipe && locked ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A' )); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1263 | pipe_name(pipe))({ int __ret_warn_on = !!(panel_pipe == pipe && locked ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A' )); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1264 | } |
| 1265 | |
| 1266 | void assert_pipe(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1267 | enum transcoder cpu_transcoder, bool_Bool state) |
| 1268 | { |
| 1269 | bool_Bool cur_state; |
| 1270 | enum intel_display_power_domain power_domain; |
| 1271 | intel_wakeref_t wakeref; |
| 1272 | |
| 1273 | /* we keep both pipes enabled on 830 */ |
| 1274 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 1275 | state = true1; |
| 1276 | |
| 1277 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A); |
| 1278 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 1279 | if (wakeref) { |
| 1280 | u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 1281 | cur_state = !!(val & PIPECONF_ENABLE(1 << 31)); |
| 1282 | |
| 1283 | intel_display_power_put(dev_priv, power_domain, wakeref); |
| 1284 | } else { |
| 1285 | cur_state = false0; |
| 1286 | } |
| 1287 | |
| 1288 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1289 | "transcoder %s assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1290 | transcoder_name(cpu_transcoder),({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1291 | onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret), 0); })) __drm_err("transcoder %s assertion failure (expected %s, current %s)\n" , transcoder_name(cpu_transcoder), onoff(state), onoff(cur_state )); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1292 | } |
| 1293 | |
| 1294 | static void assert_plane(struct intel_plane *plane, bool_Bool state) |
| 1295 | { |
| 1296 | enum pipe pipe; |
| 1297 | bool_Bool cur_state; |
| 1298 | |
| 1299 | cur_state = plane->get_hw_state(plane, &pipe); |
| 1300 | |
| 1301 | I915_STATE_WARN(cur_state != state,({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n" , plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect (!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n" , plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 1302 | "%s assertion failure (expected %s, current %s)\n",({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n" , plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect (!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n" , plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 1303 | plane->base.name, onoff(state), onoff(cur_state))({ int __ret_warn_on = !!(cur_state != state); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("%s assertion failure (expected %s, current %s)\n" , plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect (!!(__ret), 0); })) __drm_err("%s assertion failure (expected %s, current %s)\n" , plane->base.name, onoff(state), onoff(cur_state)); __builtin_expect (!!(__ret_warn_on), 0); }); |
| 1304 | } |
| 1305 | |
| 1306 | #define assert_plane_enabled(p)assert_plane(p, 1) assert_plane(p, true1) |
| 1307 | #define assert_plane_disabled(p)assert_plane(p, 0) assert_plane(p, false0) |
| 1308 | |
| 1309 | static void assert_planes_disabled(struct intel_crtc *crtc) |
| 1310 | { |
| 1311 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1312 | struct intel_plane *plane; |
| 1313 | |
| 1314 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane), base.head) );}); &plane ->base.head != (&(&dev_priv->drm)->mode_config .plane_list); plane = ({ const __typeof( ((__typeof(*plane) * )0)->base.head ) *__mptr = (plane->base.head.next); (__typeof (*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane ), base.head) );})) if (!((plane)->pipe == (crtc)->pipe )) {} else |
| 1315 | assert_plane_disabled(plane)assert_plane(plane, 0); |
| 1316 | } |
| 1317 | |
| 1318 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
| 1319 | { |
| 1320 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)({ int __ret_warn_on = !!((drm_crtc_vblank_get(crtc) == 0)); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("%s" , "WARN_ON(" "drm_crtc_vblank_get(crtc) == 0" ")"); __builtin_expect (!!(__ret), 0); })) __drm_err("%s", "WARN_ON(" "drm_crtc_vblank_get(crtc) == 0" ")"); __builtin_expect(!!(__ret_warn_on), 0); })) |
| 1321 | drm_crtc_vblank_put(crtc); |
| 1322 | } |
| 1323 | |
| 1324 | void assert_pch_transcoder_disabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1325 | enum pipe pipe) |
| 1326 | { |
| 1327 | u32 val; |
| 1328 | bool_Bool enabled; |
| 1329 | |
| 1330 | val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008) - (0xf0008)))) })); |
| 1331 | enabled = !!(val & TRANS_ENABLE(1 << 31)); |
| 1332 | I915_STATE_WARN(enabled,({ int __ret_warn_on = !!(enabled); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("transcoder assertion failed, should be off on pipe %c but is still active\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("transcoder assertion failed, should be off on pipe %c but is still active\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1333 | "transcoder assertion failed, should be off on pipe %c but is still active\n",({ int __ret_warn_on = !!(enabled); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("transcoder assertion failed, should be off on pipe %c but is still active\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("transcoder assertion failed, should be off on pipe %c but is still active\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1334 | pipe_name(pipe))({ int __ret_warn_on = !!(enabled); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("transcoder assertion failed, should be off on pipe %c but is still active\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("transcoder assertion failed, should be off on pipe %c but is still active\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1335 | } |
| 1336 | |
| 1337 | static void assert_pch_dp_disabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1338 | enum pipe pipe, enum port port, |
| 1339 | i915_reg_t dp_reg) |
| 1340 | { |
| 1341 | enum pipe port_pipe; |
| 1342 | bool_Bool state; |
| 1343 | |
| 1344 | state = intel_dp_port_enabled(dev_priv, dp_reg, port, &port_pipe); |
| 1345 | |
| 1346 | I915_STATE_WARN(state && port_pipe == pipe,({ int __ret_warn_on = !!(state && port_pipe == pipe) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("PCH DP %c enabled on transcoder %c, should be disabled\n", ( (port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret), 0 ); })) __drm_err("PCH DP %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1347 | "PCH DP %c enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(state && port_pipe == pipe) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("PCH DP %c enabled on transcoder %c, should be disabled\n", ( (port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret), 0 ); })) __drm_err("PCH DP %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1348 | port_name(port), pipe_name(pipe))({ int __ret_warn_on = !!(state && port_pipe == pipe) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("PCH DP %c enabled on transcoder %c, should be disabled\n", ( (port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret), 0 ); })) __drm_err("PCH DP %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1349 | |
| 1350 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX ) && !state && port_pipe == PIPE_B); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("IBX PCH DP %c still using transcoder B\n" , ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("IBX PCH DP %c still using transcoder B\n", ((port) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1351 | "IBX PCH DP %c still using transcoder B\n",({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX ) && !state && port_pipe == PIPE_B); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("IBX PCH DP %c still using transcoder B\n" , ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("IBX PCH DP %c still using transcoder B\n", ((port) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1352 | port_name(port))({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX ) && !state && port_pipe == PIPE_B); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("IBX PCH DP %c still using transcoder B\n" , ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("IBX PCH DP %c still using transcoder B\n", ((port) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1353 | } |
| 1354 | |
| 1355 | static void assert_pch_hdmi_disabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1356 | enum pipe pipe, enum port port, |
| 1357 | i915_reg_t hdmi_reg) |
| 1358 | { |
| 1359 | enum pipe port_pipe; |
| 1360 | bool_Bool state; |
| 1361 | |
| 1362 | state = intel_sdvo_port_enabled(dev_priv, hdmi_reg, &port_pipe); |
| 1363 | |
| 1364 | I915_STATE_WARN(state && port_pipe == pipe,({ int __ret_warn_on = !!(state && port_pipe == pipe) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("PCH HDMI %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret) , 0); })) __drm_err("PCH HDMI %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1365 | "PCH HDMI %c enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(state && port_pipe == pipe) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("PCH HDMI %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret) , 0); })) __drm_err("PCH HDMI %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 1366 | port_name(port), pipe_name(pipe))({ int __ret_warn_on = !!(state && port_pipe == pipe) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("PCH HDMI %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret) , 0); })) __drm_err("PCH HDMI %c enabled on transcoder %c, should be disabled\n" , ((port) + 'A'), ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 1367 | |
| 1368 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX ) && !state && port_pipe == PIPE_B); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("IBX PCH HDMI %c still using transcoder B\n" , ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("IBX PCH HDMI %c still using transcoder B\n", ((port) + 'A') ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1369 | "IBX PCH HDMI %c still using transcoder B\n",({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX ) && !state && port_pipe == PIPE_B); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("IBX PCH HDMI %c still using transcoder B\n" , ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("IBX PCH HDMI %c still using transcoder B\n", ((port) + 'A') ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1370 | port_name(port))({ int __ret_warn_on = !!((((dev_priv)->pch_type) == PCH_IBX ) && !state && port_pipe == PIPE_B); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("IBX PCH HDMI %c still using transcoder B\n" , ((port) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("IBX PCH HDMI %c still using transcoder B\n", ((port) + 'A') ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1371 | } |
| 1372 | |
| 1373 | static void assert_pch_ports_disabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1374 | enum pipe pipe) |
| 1375 | { |
| 1376 | enum pipe port_pipe; |
| 1377 | |
| 1378 | assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B((const i915_reg_t){ .reg = (0xe4100) })); |
| 1379 | assert_pch_dp_disabled(dev_priv, pipe, PORT_C, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) })); |
| 1380 | assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) })); |
| 1381 | |
| 1382 | I915_STATE_WARN(intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) &&({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, (( const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH VGA enabled on transcoder %c, should be disabled\n", (( pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1383 | port_pipe == pipe,({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, (( const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH VGA enabled on transcoder %c, should be disabled\n", (( pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1384 | "PCH VGA enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, (( const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH VGA enabled on transcoder %c, should be disabled\n", (( pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1385 | pipe_name(pipe))({ int __ret_warn_on = !!(intel_crt_port_enabled(dev_priv, (( const i915_reg_t){ .reg = (0xe1100) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH VGA enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH VGA enabled on transcoder %c, should be disabled\n", (( pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1386 | |
| 1387 | I915_STATE_WARN(intel_lvds_port_enabled(dev_priv, PCH_LVDS, &port_pipe) &&({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, ( (const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH LVDS enabled on transcoder %c, should be disabled\n", ( (pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1388 | port_pipe == pipe,({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, ( (const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH LVDS enabled on transcoder %c, should be disabled\n", ( (pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1389 | "PCH LVDS enabled on transcoder %c, should be disabled\n",({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, ( (const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH LVDS enabled on transcoder %c, should be disabled\n", ( (pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 1390 | pipe_name(pipe))({ int __ret_warn_on = !!(intel_lvds_port_enabled(dev_priv, ( (const i915_reg_t){ .reg = (0xe1180) }), &port_pipe) && port_pipe == pipe); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("PCH LVDS enabled on transcoder %c, should be disabled\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("PCH LVDS enabled on transcoder %c, should be disabled\n", ( (pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 1391 | |
| 1392 | /* PCH SDVOB multiplex with HDMIB */ |
| 1393 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB((const i915_reg_t){ .reg = (0xe1140) })); |
| 1394 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_C, PCH_HDMIC((const i915_reg_t){ .reg = (0xe1150) })); |
| 1395 | assert_pch_hdmi_disabled(dev_priv, pipe, PORT_D, PCH_HDMID((const i915_reg_t){ .reg = (0xe1160) })); |
| 1396 | } |
| 1397 | |
| 1398 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
| 1399 | const struct intel_crtc_state *pipe_config) |
| 1400 | { |
| 1401 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1402 | enum pipe pipe = crtc->pipe; |
| 1403 | |
| 1404 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), pipe_config->dpll_hw_state.dpll); |
| 1405 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 1406 | udelay(150); |
| 1407 | |
| 1408 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_LOCK_VLV(1 << 15), 1)) |
| 1409 | drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DPLL %d failed to lock\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , pipe); |
| 1410 | } |
| 1411 | |
| 1412 | static void vlv_enable_pll(struct intel_crtc *crtc, |
| 1413 | const struct intel_crtc_state *pipe_config) |
| 1414 | { |
| 1415 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1416 | enum pipe pipe = crtc->pipe; |
| 1417 | |
| 1418 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)assert_pipe(dev_priv, pipe_config->cpu_transcoder, 0); |
| 1419 | |
| 1420 | /* PLL is protected by panel, make sure we can write it */ |
| 1421 | assert_panel_unlocked(dev_priv, pipe); |
| 1422 | |
| 1423 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) |
| 1424 | _vlv_enable_pll(crtc, pipe_config); |
| 1425 | |
| 1426 | intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(pipe)])) }), |
| 1427 | pipe_config->dpll_hw_state.dpll_md); |
| 1428 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(pipe)])) })); |
| 1429 | } |
| 1430 | |
| 1431 | |
| 1432 | static void _chv_enable_pll(struct intel_crtc *crtc, |
| 1433 | const struct intel_crtc_state *pipe_config) |
| 1434 | { |
| 1435 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1436 | enum pipe pipe = crtc->pipe; |
| 1437 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 1438 | u32 tmp; |
| 1439 | |
| 1440 | vlv_dpio_get(dev_priv); |
| 1441 | |
| 1442 | /* Enable back the 10bit clock to display controller */ |
| 1443 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138)))); |
| 1444 | tmp |= DPIO_DCLKP_EN(1 << 13); |
| 1445 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), tmp); |
| 1446 | |
| 1447 | vlv_dpio_put(dev_priv); |
| 1448 | |
| 1449 | /* |
| 1450 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. |
| 1451 | */ |
| 1452 | udelay(1); |
| 1453 | |
| 1454 | /* Enable PLL */ |
| 1455 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), pipe_config->dpll_hw_state.dpll); |
| 1456 | |
| 1457 | /* Check PLL is locked */ |
| 1458 | if (intel_de_wait_for_set(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_LOCK_VLV(1 << 15), 1)) |
| 1459 | drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PLL %d failed to lock\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , pipe); |
| 1460 | } |
| 1461 | |
| 1462 | static void chv_enable_pll(struct intel_crtc *crtc, |
| 1463 | const struct intel_crtc_state *pipe_config) |
| 1464 | { |
| 1465 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1466 | enum pipe pipe = crtc->pipe; |
| 1467 | |
| 1468 | assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder)assert_pipe(dev_priv, pipe_config->cpu_transcoder, 0); |
| 1469 | |
| 1470 | /* PLL is protected by panel, make sure we can write it */ |
| 1471 | assert_panel_unlocked(dev_priv, pipe); |
| 1472 | |
| 1473 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) |
| 1474 | _chv_enable_pll(crtc, pipe_config); |
| 1475 | |
| 1476 | if (pipe != PIPE_A) { |
| 1477 | /* |
| 1478 | * WaPixelRepeatModeFixForC0:chv |
| 1479 | * |
| 1480 | * DPLLCMD is AWOL. Use chicken bits to propagate |
| 1481 | * the value from DPLLBMD to either pipe B or C. |
| 1482 | */ |
| 1483 | intel_de_write(dev_priv, CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }), CBR_DPLLBMD_PIPE(pipe)(1 << (7 + (pipe) * 11))); |
| 1484 | intel_de_write(dev_priv, DPLL_MD(PIPE_B)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(PIPE_B)] )) }), |
| 1485 | pipe_config->dpll_hw_state.dpll_md); |
| 1486 | intel_de_write(dev_priv, CBR4_VLV((const i915_reg_t){ .reg = (0x180000 + 0x70450) }), 0); |
| 1487 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; |
| 1488 | |
| 1489 | /* |
| 1490 | * DPLLB VGA mode also seems to cause problems. |
| 1491 | * We should always have it disabled. |
| 1492 | */ |
| 1493 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)-> display_mmio_offset) + 0x6014), (((&(dev_priv)->__info )->display_mmio_offset) + 0x6018), (((&(dev_priv)-> __info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1494 | (intel_de_read(dev_priv, DPLL(PIPE_B)) &({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)-> display_mmio_offset) + 0x6014), (((&(dev_priv)->__info )->display_mmio_offset) + 0x6018), (((&(dev_priv)-> __info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1495 | DPLL_VGA_MODE_DIS) == 0)({ int __ret = !!(((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)-> display_mmio_offset) + 0x6014), (((&(dev_priv)->__info )->display_mmio_offset) + 0x6018), (((&(dev_priv)-> __info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv)->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv)->__info)->display_mmio_offset) + 0x6030) })[(PIPE_B)])) })) & (1 << 28)) == 0" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1496 | } else { |
| 1497 | intel_de_write(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(pipe)])) }), |
| 1498 | pipe_config->dpll_hw_state.dpll_md); |
| 1499 | intel_de_posting_read(dev_priv, DPLL_MD(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(pipe)])) })); |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | static bool_Bool i9xx_has_pps(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 1504 | { |
| 1505 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 1506 | return false0; |
| 1507 | |
| 1508 | return IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) || IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile); |
| 1509 | } |
| 1510 | |
| 1511 | static void i9xx_enable_pll(struct intel_crtc *crtc, |
| 1512 | const struct intel_crtc_state *crtc_state) |
| 1513 | { |
| 1514 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1515 | i915_reg_t reg = DPLL(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(crtc-> pipe)])) }); |
| 1516 | u32 dpll = crtc_state->dpll_hw_state.dpll; |
| 1517 | int i; |
| 1518 | |
| 1519 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 0); |
| 1520 | |
| 1521 | /* PLL is protected by panel, make sure we can write it */ |
| 1522 | if (i9xx_has_pps(dev_priv)) |
| 1523 | assert_panel_unlocked(dev_priv, crtc->pipe); |
| 1524 | |
| 1525 | /* |
| 1526 | * Apparently we need to have VGA mode enabled prior to changing |
| 1527 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old |
| 1528 | * dividers, even though the register value does change. |
| 1529 | */ |
| 1530 | intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS(1 << 28)); |
| 1531 | intel_de_write(dev_priv, reg, dpll); |
| 1532 | |
| 1533 | /* Wait for the clocks to stabilize. */ |
| 1534 | intel_de_posting_read(dev_priv, reg); |
| 1535 | udelay(150); |
| 1536 | |
| 1537 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 1538 | intel_de_write(dev_priv, DPLL_MD(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(crtc-> pipe)])) }), |
| 1539 | crtc_state->dpll_hw_state.dpll_md); |
| 1540 | } else { |
| 1541 | /* The pixel multiplier can only be updated once the |
| 1542 | * DPLL is enabled and the clocks are stable. |
| 1543 | * |
| 1544 | * So write it again. |
| 1545 | */ |
| 1546 | intel_de_write(dev_priv, reg, dpll); |
| 1547 | } |
| 1548 | |
| 1549 | /* We do this three times for luck */ |
| 1550 | for (i = 0; i < 3; i++) { |
| 1551 | intel_de_write(dev_priv, reg, dpll); |
| 1552 | intel_de_posting_read(dev_priv, reg); |
| 1553 | udelay(150); /* wait for warmup */ |
| 1554 | } |
| 1555 | } |
| 1556 | |
| 1557 | static void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) |
| 1558 | { |
| 1559 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1560 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1561 | enum pipe pipe = crtc->pipe; |
| 1562 | |
| 1563 | /* Don't disable pipe or pipe PLLs if needed */ |
| 1564 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 1565 | return; |
| 1566 | |
| 1567 | /* Make sure the pipe isn't still relying on us */ |
| 1568 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 0); |
| 1569 | |
| 1570 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_VGA_MODE_DIS(1 << 28)); |
| 1571 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 1572 | } |
| 1573 | |
| 1574 | static void vlv_disable_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 1575 | { |
| 1576 | u32 val; |
| 1577 | |
| 1578 | /* Make sure the pipe isn't still relying on us */ |
| 1579 | assert_pipe_disabled(dev_priv, (enum transcoder)pipe)assert_pipe(dev_priv, (enum transcoder)pipe, 0); |
| 1580 | |
| 1581 | val = DPLL_INTEGRATED_REF_CLK_VLV(1 << 13) | |
| 1582 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
| 1583 | if (pipe != PIPE_A) |
| 1584 | val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
| 1585 | |
| 1586 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), val); |
| 1587 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 1588 | } |
| 1589 | |
| 1590 | static void chv_disable_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 1591 | { |
| 1592 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 1593 | u32 val; |
| 1594 | |
| 1595 | /* Make sure the pipe isn't still relying on us */ |
| 1596 | assert_pipe_disabled(dev_priv, (enum transcoder)pipe)assert_pipe(dev_priv, (enum transcoder)pipe, 0); |
| 1597 | |
| 1598 | val = DPLL_SSC_REF_CLK_CHV(1 << 13) | |
| 1599 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
| 1600 | if (pipe != PIPE_A) |
| 1601 | val |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
| 1602 | |
| 1603 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), val); |
| 1604 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 1605 | |
| 1606 | vlv_dpio_get(dev_priv); |
| 1607 | |
| 1608 | /* Disable 10bit clock to display controller */ |
| 1609 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138)))); |
| 1610 | val &= ~DPIO_DCLKP_EN(1 << 13); |
| 1611 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), val); |
| 1612 | |
| 1613 | vlv_dpio_put(dev_priv); |
| 1614 | } |
| 1615 | |
| 1616 | void vlv_wait_port_ready(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1617 | struct intel_digital_port *dig_port, |
| 1618 | unsigned int expected_mask) |
| 1619 | { |
| 1620 | u32 port_mask; |
| 1621 | i915_reg_t dpll_reg; |
| 1622 | |
| 1623 | switch (dig_port->base.port) { |
| 1624 | case PORT_B: |
| 1625 | port_mask = DPLL_PORTB_READY_MASK(0xf); |
| 1626 | dpll_reg = DPLL(0)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(0)])) }); |
| 1627 | break; |
| 1628 | case PORT_C: |
| 1629 | port_mask = DPLL_PORTC_READY_MASK(0xf << 4); |
| 1630 | dpll_reg = DPLL(0)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(0)])) }); |
| 1631 | expected_mask <<= 4; |
| 1632 | break; |
| 1633 | case PORT_D: |
| 1634 | port_mask = DPLL_PORTD_READY_MASK(0xf); |
| 1635 | dpll_reg = DPIO_PHY_STATUS((const i915_reg_t){ .reg = (0x180000 + 0x6240) }); |
| 1636 | break; |
| 1637 | default: |
| 1638 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 1638); } while (0); |
| 1639 | } |
| 1640 | |
| 1641 | if (intel_de_wait_for_register(dev_priv, dpll_reg, |
| 1642 | port_mask, expected_mask, 1000)) |
| 1643 | drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name, intel_de_read (dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect (!!(__ret), 0); }) |
| 1644 | "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name, intel_de_read (dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect (!!(__ret), 0); }) |
| 1645 | dig_port->base.base.base.id, dig_port->base.base.name,({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name, intel_de_read (dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect (!!(__ret), 0); }) |
| 1646 | intel_de_read(dev_priv, dpll_reg) & port_mask,({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name, intel_de_read (dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect (!!(__ret), 0); }) |
| 1647 | expected_mask)({ int __ret = !!(1); if (__ret) printf("%s %s: " "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name, intel_de_read (dev_priv, dpll_reg) & port_mask, expected_mask); __builtin_expect (!!(__ret), 0); }); |
| 1648 | } |
| 1649 | |
| 1650 | static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) |
| 1651 | { |
| 1652 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1653 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1654 | enum pipe pipe = crtc->pipe; |
| 1655 | i915_reg_t reg; |
| 1656 | u32 val, pipeconf_val; |
| 1657 | |
| 1658 | /* Make sure PCH DPLL is enabled */ |
| 1659 | assert_shared_dpll_enabled(dev_priv, crtc_state->shared_dpll)assert_shared_dpll(dev_priv, crtc_state->shared_dpll, 1); |
| 1660 | |
| 1661 | /* FDI must be feeding us bits for PCH ports */ |
| 1662 | assert_fdi_tx_enabled(dev_priv, pipe)assert_fdi_tx(dev_priv, pipe, 1); |
| 1663 | assert_fdi_rx_enabled(dev_priv, pipe)assert_fdi_rx(dev_priv, pipe, 1); |
| 1664 | |
| 1665 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 1666 | reg = TRANS_CHICKEN2(pipe)((const i915_reg_t){ .reg = (((0xf0064) + (pipe) * ((0xf1064) - (0xf0064)))) }); |
| 1667 | val = intel_de_read(dev_priv, reg); |
| 1668 | /* |
| 1669 | * Workaround: Set the timing override bit |
| 1670 | * before enabling the pch transcoder. |
| 1671 | */ |
| 1672 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31); |
| 1673 | /* Configure frame start delay to match the CPU */ |
| 1674 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK(3 << 27); |
| 1675 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0)((0) << 27); |
| 1676 | intel_de_write(dev_priv, reg, val); |
| 1677 | } |
| 1678 | |
| 1679 | reg = PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008) - (0xf0008)))) }); |
| 1680 | val = intel_de_read(dev_priv, reg); |
| 1681 | pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 1682 | |
| 1683 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) { |
| 1684 | /* Configure frame start delay to match the CPU */ |
| 1685 | val &= ~TRANS_FRAME_START_DELAY_MASK(3 << 27); |
| 1686 | val |= TRANS_FRAME_START_DELAY(0)((0) << 27); |
| 1687 | |
| 1688 | /* |
| 1689 | * Make the BPC in transcoder be consistent with |
| 1690 | * that in pipeconf reg. For HDMI we must use 8bpc |
| 1691 | * here for both 8bpc and 12bpc. |
| 1692 | */ |
| 1693 | val &= ~PIPECONF_BPC_MASK(0x7 << 5); |
| 1694 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
| 1695 | val |= PIPECONF_8BPC(0 << 5); |
| 1696 | else |
| 1697 | val |= pipeconf_val & PIPECONF_BPC_MASK(0x7 << 5); |
| 1698 | } |
| 1699 | |
| 1700 | val &= ~TRANS_INTERLACE_MASK(7 << 21); |
| 1701 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK(7 << 21)) == PIPECONF_INTERLACED_ILK(3 << 21)) { |
| 1702 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) && |
| 1703 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
| 1704 | val |= TRANS_LEGACY_INTERLACED_ILK(2 << 21); |
| 1705 | else |
| 1706 | val |= TRANS_INTERLACED(3 << 21); |
| 1707 | } else { |
| 1708 | val |= TRANS_PROGRESSIVE(0 << 21); |
| 1709 | } |
| 1710 | |
| 1711 | intel_de_write(dev_priv, reg, val | TRANS_ENABLE(1 << 31)); |
| 1712 | if (intel_de_wait_for_set(dev_priv, reg, TRANS_STATE_ENABLE(1 << 30), 100)) |
| 1713 | drm_err(&dev_priv->drm, "failed to enable transcoder %c\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to enable transcoder %c\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
| 1714 | pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to enable transcoder %c\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')); |
| 1715 | } |
| 1716 | |
| 1717 | static void lpt_enable_pch_transcoder(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1718 | enum transcoder cpu_transcoder) |
| 1719 | { |
| 1720 | u32 val, pipeconf_val; |
| 1721 | |
| 1722 | /* FDI must be feeding us bits for PCH ports */ |
| 1723 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder)assert_fdi_tx(dev_priv, (enum pipe) cpu_transcoder, 1); |
| 1724 | assert_fdi_rx_enabled(dev_priv, PIPE_A)assert_fdi_rx(dev_priv, PIPE_A, 1); |
| 1725 | |
| 1726 | val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064 ) - (0xf0064)))) })); |
| 1727 | /* Workaround: set timing override bit. */ |
| 1728 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31); |
| 1729 | /* Configure frame start delay to match the CPU */ |
| 1730 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK(3 << 27); |
| 1731 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0)((0) << 27); |
| 1732 | intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064 ) - (0xf0064)))) }), val); |
| 1733 | |
| 1734 | val = TRANS_ENABLE(1 << 31); |
| 1735 | pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 1736 | |
| 1737 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW(3 << 21)) == |
| 1738 | PIPECONF_INTERLACED_ILK(3 << 21)) |
| 1739 | val |= TRANS_INTERLACED(3 << 21); |
| 1740 | else |
| 1741 | val |= TRANS_PROGRESSIVE(0 << 21); |
| 1742 | |
| 1743 | intel_de_write(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008 ) - (0xf0008)))) }), val); |
| 1744 | if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008 ) - (0xf0008)))) }), |
| 1745 | TRANS_STATE_ENABLE(1 << 30), 100)) |
| 1746 | drm_err(&dev_priv->drm, "Failed to enable PCH transcoder\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to enable PCH transcoder\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1747 | } |
| 1748 | |
| 1749 | static void ilk_disable_pch_transcoder(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 1750 | enum pipe pipe) |
| 1751 | { |
| 1752 | i915_reg_t reg; |
| 1753 | u32 val; |
| 1754 | |
| 1755 | /* FDI relies on the transcoder */ |
| 1756 | assert_fdi_tx_disabled(dev_priv, pipe)assert_fdi_tx(dev_priv, pipe, 0); |
| 1757 | assert_fdi_rx_disabled(dev_priv, pipe)assert_fdi_rx(dev_priv, pipe, 0); |
| 1758 | |
| 1759 | /* Ports must be off as well */ |
| 1760 | assert_pch_ports_disabled(dev_priv, pipe); |
| 1761 | |
| 1762 | reg = PCH_TRANSCONF(pipe)((const i915_reg_t){ .reg = (((0xf0008) + (pipe) * ((0xf1008) - (0xf0008)))) }); |
| 1763 | val = intel_de_read(dev_priv, reg); |
| 1764 | val &= ~TRANS_ENABLE(1 << 31); |
| 1765 | intel_de_write(dev_priv, reg, val); |
| 1766 | /* wait for PCH transcoder off, transcoder state */ |
| 1767 | if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE(1 << 30), 50)) |
| 1768 | drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to disable transcoder %c\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
| 1769 | pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to disable transcoder %c\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')); |
| 1770 | |
| 1771 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 1772 | /* Workaround: Clear the timing override chicken bit again. */ |
| 1773 | reg = TRANS_CHICKEN2(pipe)((const i915_reg_t){ .reg = (((0xf0064) + (pipe) * ((0xf1064) - (0xf0064)))) }); |
| 1774 | val = intel_de_read(dev_priv, reg); |
| 1775 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31); |
| 1776 | intel_de_write(dev_priv, reg, val); |
| 1777 | } |
| 1778 | } |
| 1779 | |
| 1780 | void lpt_disable_pch_transcoder(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 1781 | { |
| 1782 | u32 val; |
| 1783 | |
| 1784 | val = intel_de_read(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008 ) - (0xf0008)))) })); |
| 1785 | val &= ~TRANS_ENABLE(1 << 31); |
| 1786 | intel_de_write(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008 ) - (0xf0008)))) }), val); |
| 1787 | /* wait for PCH transcoder off, transcoder state */ |
| 1788 | if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008 ) - (0xf0008)))) }), |
| 1789 | TRANS_STATE_ENABLE(1 << 30), 50)) |
| 1790 | drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to disable PCH transcoder\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 1791 | |
| 1792 | /* Workaround: clear timing override bit. */ |
| 1793 | val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064 ) - (0xf0064)))) })); |
| 1794 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE(1 << 31); |
| 1795 | intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A)((const i915_reg_t){ .reg = (((0xf0064) + (PIPE_A) * ((0xf1064 ) - (0xf0064)))) }), val); |
| 1796 | } |
| 1797 | |
| 1798 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
| 1799 | { |
| 1800 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1801 | |
| 1802 | if (HAS_PCH_LPT(dev_priv)(((dev_priv)->pch_type) == PCH_LPT)) |
| 1803 | return PIPE_A; |
| 1804 | else |
| 1805 | return crtc->pipe; |
| 1806 | } |
| 1807 | |
| 1808 | static u32 intel_crtc_max_vblank_count(const struct intel_crtc_state *crtc_state) |
| 1809 | { |
| 1810 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 1811 | |
| 1812 | /* |
| 1813 | * On i965gm the hardware frame counter reads |
| 1814 | * zero when the TV encoder is enabled :( |
| 1815 | */ |
| 1816 | if (IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) && |
| 1817 | (crtc_state->output_types & BIT(INTEL_OUTPUT_TVOUT)(1UL << (INTEL_OUTPUT_TVOUT)))) |
| 1818 | return 0; |
| 1819 | |
| 1820 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 1821 | return 0xffffffff; /* full 32 bit counter */ |
| 1822 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 3) |
| 1823 | return 0xffffff; /* only 24 bits of frame count */ |
| 1824 | else |
| 1825 | return 0; /* Gen2 doesn't have a hardware frame counter */ |
| 1826 | } |
| 1827 | |
| 1828 | void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state) |
| 1829 | { |
| 1830 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1831 | |
| 1832 | assert_vblank_disabled(&crtc->base); |
| 1833 | drm_crtc_set_max_vblank_count(&crtc->base, |
| 1834 | intel_crtc_max_vblank_count(crtc_state)); |
| 1835 | drm_crtc_vblank_on(&crtc->base); |
| 1836 | } |
| 1837 | |
| 1838 | void intel_crtc_vblank_off(const struct intel_crtc_state *crtc_state) |
| 1839 | { |
| 1840 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1841 | |
| 1842 | drm_crtc_vblank_off(&crtc->base); |
| 1843 | assert_vblank_disabled(&crtc->base); |
| 1844 | } |
| 1845 | |
| 1846 | void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state) |
| 1847 | { |
| 1848 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1849 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1850 | enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; |
| 1851 | enum pipe pipe = crtc->pipe; |
| 1852 | i915_reg_t reg; |
| 1853 | u32 val; |
| 1854 | |
| 1855 | drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling pipe %c\n" , ((pipe) + 'A')); |
| 1856 | |
| 1857 | assert_planes_disabled(crtc); |
| 1858 | |
| 1859 | /* |
| 1860 | * A pipe without a PLL won't actually be able to drive bits from |
| 1861 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't |
| 1862 | * need the check. |
| 1863 | */ |
| 1864 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) { |
| 1865 | if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI)) |
| 1866 | assert_dsi_pll_enabled(dev_priv)assert_dsi_pll(dev_priv, 1); |
| 1867 | else |
| 1868 | assert_pll_enabled(dev_priv, pipe)assert_pll(dev_priv, pipe, 1); |
| 1869 | } else { |
| 1870 | if (new_crtc_state->has_pch_encoder) { |
| 1871 | /* if driving the PCH, we need FDI enabled */ |
| 1872 | assert_fdi_rx_pll_enabled(dev_priv,assert_fdi_rx_pll(dev_priv, intel_crtc_pch_transcoder(crtc), 1 ) |
| 1873 | intel_crtc_pch_transcoder(crtc))assert_fdi_rx_pll(dev_priv, intel_crtc_pch_transcoder(crtc), 1 ); |
| 1874 | assert_fdi_tx_pll_enabled(dev_priv, |
| 1875 | (enum pipe) cpu_transcoder); |
| 1876 | } |
| 1877 | /* FIXME: assert CPU port conditions for SNB+ */ |
| 1878 | } |
| 1879 | |
| 1880 | trace_intel_pipe_enable(crtc); |
| 1881 | |
| 1882 | reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) }); |
| 1883 | val = intel_de_read(dev_priv, reg); |
| 1884 | if (val & PIPECONF_ENABLE(1 << 31)) { |
| 1885 | /* we keep both pipes enabled on 830 */ |
| 1886 | drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv))({ int __ret = !!((!IS_PLATFORM(dev_priv, INTEL_I830))); if ( __ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "!IS_PLATFORM(dev_priv, INTEL_I830)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1887 | return; |
| 1888 | } |
| 1889 | |
| 1890 | intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE(1 << 31)); |
| 1891 | intel_de_posting_read(dev_priv, reg); |
| 1892 | |
| 1893 | /* |
| 1894 | * Until the pipe starts PIPEDSL reads will return a stale value, |
| 1895 | * which causes an apparent vblank timestamp jump when PIPEDSL |
| 1896 | * resets to its proper value. That also messes up the frame count |
| 1897 | * when it's derived from the timestamps. So let's wait for the |
| 1898 | * pipe to start properly before we call drm_crtc_vblank_on() |
| 1899 | */ |
| 1900 | if (intel_crtc_max_vblank_count(new_crtc_state) == 0) |
| 1901 | intel_wait_for_pipe_scanline_moving(crtc); |
| 1902 | } |
| 1903 | |
| 1904 | void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) |
| 1905 | { |
| 1906 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 1907 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 1908 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
| 1909 | enum pipe pipe = crtc->pipe; |
| 1910 | i915_reg_t reg; |
| 1911 | u32 val; |
| 1912 | |
| 1913 | drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling pipe %c\n" , ((pipe) + 'A')); |
| 1914 | |
| 1915 | /* |
| 1916 | * Make sure planes won't keep trying to pump pixels to us, |
| 1917 | * or we might hang the display. |
| 1918 | */ |
| 1919 | assert_planes_disabled(crtc); |
| 1920 | |
| 1921 | trace_intel_pipe_disable(crtc); |
| 1922 | |
| 1923 | reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) }); |
| 1924 | val = intel_de_read(dev_priv, reg); |
| 1925 | if ((val & PIPECONF_ENABLE(1 << 31)) == 0) |
| 1926 | return; |
| 1927 | |
| 1928 | /* |
| 1929 | * Double wide has implications for planes |
| 1930 | * so best keep it disabled when not needed. |
| 1931 | */ |
| 1932 | if (old_crtc_state->double_wide) |
| 1933 | val &= ~PIPECONF_DOUBLE_WIDE(1 << 30); |
| 1934 | |
| 1935 | /* Don't disable pipe or pipe PLLs if needed */ |
| 1936 | if (!IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 1937 | val &= ~PIPECONF_ENABLE(1 << 31); |
| 1938 | |
| 1939 | intel_de_write(dev_priv, reg, val); |
| 1940 | if ((val & PIPECONF_ENABLE(1 << 31)) == 0) |
| 1941 | intel_wait_for_pipe_off(old_crtc_state); |
| 1942 | } |
| 1943 | |
| 1944 | static unsigned int intel_tile_size(const struct drm_i915_privateinteldrm_softc *dev_priv) |
| 1945 | { |
| 1946 | return IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) ? 2048 : 4096; |
| 1947 | } |
| 1948 | |
| 1949 | static bool_Bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) |
| 1950 | { |
| 1951 | if (!is_ccs_modifier(fb->modifier)) |
| 1952 | return false0; |
| 1953 | |
| 1954 | return plane >= fb->format->num_planes / 2; |
| 1955 | } |
| 1956 | |
| 1957 | static bool_Bool is_gen12_ccs_modifier(u64 modifier) |
| 1958 | { |
| 1959 | return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )) || |
| 1960 | modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )); |
| 1961 | |
| 1962 | } |
| 1963 | |
| 1964 | static bool_Bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) |
| 1965 | { |
| 1966 | return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); |
| 1967 | } |
| 1968 | |
| 1969 | static bool_Bool is_aux_plane(const struct drm_framebuffer *fb, int plane) |
| 1970 | { |
| 1971 | if (is_ccs_modifier(fb->modifier)) |
| 1972 | return is_ccs_plane(fb, plane); |
| 1973 | |
| 1974 | return plane == 1; |
| 1975 | } |
| 1976 | |
| 1977 | static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) |
| 1978 | { |
| 1979 | drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||({ int __ret = !!((!is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2 ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb ->dev))->dev), "", "drm_WARN_ON(" "!is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1980 | (main_plane && main_plane >= fb->format->num_planes / 2))({ int __ret = !!((!is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2 ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb ->dev))->dev), "", "drm_WARN_ON(" "!is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1981 | |
| 1982 | return fb->format->num_planes / 2 + main_plane; |
| 1983 | } |
| 1984 | |
| 1985 | static int ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) |
| 1986 | { |
| 1987 | drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) ||({ int __ret = !!((!is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON(" "!is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2" ")"); __builtin_expect(!!(__ret), 0); }) |
| 1988 | ccs_plane < fb->format->num_planes / 2)({ int __ret = !!((!is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON(" "!is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2" ")"); __builtin_expect(!!(__ret), 0); }); |
| 1989 | |
| 1990 | return ccs_plane - fb->format->num_planes / 2; |
| 1991 | } |
| 1992 | |
| 1993 | /* Return either the main plane's CCS or - if not a CCS FB - UV plane */ |
| 1994 | int intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) |
| 1995 | { |
| 1996 | if (is_ccs_modifier(fb->modifier)) |
| 1997 | return main_to_ccs_plane(fb, main_plane); |
| 1998 | |
| 1999 | return 1; |
| 2000 | } |
| 2001 | |
| 2002 | bool_Bool |
| 2003 | intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, |
| 2004 | uint64_t modifier) |
| 2005 | { |
| 2006 | return info->is_yuv && |
| 2007 | info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2); |
| 2008 | } |
| 2009 | |
| 2010 | static bool_Bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, |
| 2011 | int color_plane) |
| 2012 | { |
| 2013 | return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && |
| 2014 | color_plane == 1; |
| 2015 | } |
| 2016 | |
| 2017 | static unsigned int |
| 2018 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) |
| 2019 | { |
| 2020 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 2021 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 2022 | |
| 2023 | switch (fb->modifier) { |
| 2024 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 2025 | return intel_tile_size(dev_priv); |
| 2026 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 2027 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 2028 | return 128; |
| 2029 | else |
| 2030 | return 512; |
| 2031 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 2032 | if (is_ccs_plane(fb, color_plane)) |
| 2033 | return 128; |
| 2034 | fallthroughdo {} while (0); |
| 2035 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 2036 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 2037 | if (is_ccs_plane(fb, color_plane)) |
| 2038 | return 64; |
| 2039 | fallthroughdo {} while (0); |
| 2040 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 2041 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) || HAS_128_BYTE_Y_TILING(dev_priv)(!(0 + (&(dev_priv)->__info)->gen == (2)) && !(IS_PLATFORM(dev_priv, INTEL_I915G) || IS_PLATFORM(dev_priv , INTEL_I915GM)))) |
| 2042 | return 128; |
| 2043 | else |
| 2044 | return 512; |
| 2045 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 2046 | if (is_ccs_plane(fb, color_plane)) |
| 2047 | return 128; |
| 2048 | fallthroughdo {} while (0); |
| 2049 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 2050 | switch (cpp) { |
| 2051 | case 1: |
| 2052 | return 64; |
| 2053 | case 2: |
| 2054 | case 4: |
| 2055 | return 128; |
| 2056 | case 8: |
| 2057 | case 16: |
| 2058 | return 256; |
| 2059 | default: |
| 2060 | MISSING_CASE(cpp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "cpp", (long)(cpp)); __builtin_expect(!!(__ret), 0); }); |
| 2061 | return cpp; |
| 2062 | } |
| 2063 | break; |
| 2064 | default: |
| 2065 | MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->modifier", (long)(fb->modifier)); __builtin_expect (!!(__ret), 0); }); |
| 2066 | return cpp; |
| 2067 | } |
| 2068 | } |
| 2069 | |
| 2070 | static unsigned int |
| 2071 | intel_tile_height(const struct drm_framebuffer *fb, int color_plane) |
| 2072 | { |
| 2073 | if (is_gen12_ccs_plane(fb, color_plane)) |
| 2074 | return 1; |
| 2075 | |
| 2076 | return intel_tile_size(to_i915(fb->dev)) / |
| 2077 | intel_tile_width_bytes(fb, color_plane); |
| 2078 | } |
| 2079 | |
| 2080 | /* Return the tile dimensions in pixel units */ |
| 2081 | static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane, |
| 2082 | unsigned int *tile_width, |
| 2083 | unsigned int *tile_height) |
| 2084 | { |
| 2085 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane); |
| 2086 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 2087 | |
| 2088 | *tile_width = tile_width_bytes / cpp; |
| 2089 | *tile_height = intel_tile_height(fb, color_plane); |
| 2090 | } |
| 2091 | |
| 2092 | static unsigned int intel_tile_row_size(const struct drm_framebuffer *fb, |
| 2093 | int color_plane) |
| 2094 | { |
| 2095 | unsigned int tile_width, tile_height; |
| 2096 | |
| 2097 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
| 2098 | |
| 2099 | return fb->pitches[color_plane] * tile_height; |
| 2100 | } |
| 2101 | |
| 2102 | unsigned int |
| 2103 | intel_fb_align_height(const struct drm_framebuffer *fb, |
| 2104 | int color_plane, unsigned int height) |
| 2105 | { |
| 2106 | unsigned int tile_height = intel_tile_height(fb, color_plane); |
| 2107 | |
| 2108 | return roundup2(height, tile_height)(((height) + ((tile_height) - 1)) & (~((__typeof(height)) (tile_height) - 1))); |
| 2109 | } |
| 2110 | |
| 2111 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
| 2112 | { |
| 2113 | unsigned int size = 0; |
| 2114 | int i; |
| 2115 | |
| 2116 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane)(sizeof((rot_info->plane)) / sizeof((rot_info->plane)[0 ])); i++) |
| 2117 | size += rot_info->plane[i].width * rot_info->plane[i].height; |
| 2118 | |
| 2119 | return size; |
| 2120 | } |
| 2121 | |
| 2122 | unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info) |
| 2123 | { |
| 2124 | unsigned int size = 0; |
| 2125 | int i; |
| 2126 | |
| 2127 | for (i = 0 ; i < ARRAY_SIZE(rem_info->plane)(sizeof((rem_info->plane)) / sizeof((rem_info->plane)[0 ])); i++) |
| 2128 | size += rem_info->plane[i].width * rem_info->plane[i].height; |
| 2129 | |
| 2130 | return size; |
| 2131 | } |
| 2132 | |
| 2133 | static void |
| 2134 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
| 2135 | const struct drm_framebuffer *fb, |
| 2136 | unsigned int rotation) |
| 2137 | { |
| 2138 | view->type = I915_GGTT_VIEW_NORMAL; |
| 2139 | if (drm_rotation_90_or_270(rotation)) { |
| 2140 | view->type = I915_GGTT_VIEW_ROTATED; |
| 2141 | view->rotated = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );})->rot_info; |
| 2142 | } |
| 2143 | } |
| 2144 | |
| 2145 | static unsigned int intel_cursor_alignment(const struct drm_i915_privateinteldrm_softc *dev_priv) |
| 2146 | { |
| 2147 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 2148 | return 16 * 1024; |
| 2149 | else if (IS_I85X(dev_priv)IS_PLATFORM(dev_priv, INTEL_I85X)) |
| 2150 | return 256; |
| 2151 | else if (IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G) || IS_I865G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I865G)) |
| 2152 | return 32; |
| 2153 | else |
| 2154 | return 4 * 1024; |
| 2155 | } |
| 2156 | |
| 2157 | static unsigned int intel_linear_alignment(const struct drm_i915_privateinteldrm_softc *dev_priv) |
| 2158 | { |
| 2159 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 2160 | return 256 * 1024; |
| 2161 | else if (IS_I965G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965G) || IS_I965GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I965GM) || |
| 2162 | IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 2163 | return 128 * 1024; |
| 2164 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 2165 | return 4 * 1024; |
| 2166 | else |
| 2167 | return 0; |
| 2168 | } |
| 2169 | |
| 2170 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
| 2171 | int color_plane) |
| 2172 | { |
| 2173 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 2174 | |
| 2175 | /* AUX_DIST needs only 4K alignment */ |
| 2176 | if ((INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 12 && is_aux_plane(fb, color_plane)) || |
| 2177 | is_ccs_plane(fb, color_plane)) |
| 2178 | return 4096; |
| 2179 | |
| 2180 | switch (fb->modifier) { |
| 2181 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 2182 | return intel_linear_alignment(dev_priv); |
| 2183 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 2184 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 2185 | return 256 * 1024; |
| 2186 | return 0; |
| 2187 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 2188 | if (is_semiplanar_uv_plane(fb, color_plane)) |
| 2189 | return intel_tile_row_size(fb, color_plane); |
| 2190 | fallthroughdo {} while (0); |
| 2191 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 2192 | return 16 * 1024; |
| 2193 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 2194 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 2195 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 2196 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 && |
| 2197 | is_semiplanar_uv_plane(fb, color_plane)) |
| 2198 | return intel_tile_row_size(fb, color_plane); |
| 2199 | fallthroughdo {} while (0); |
| 2200 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 2201 | return 1 * 1024 * 1024; |
| 2202 | default: |
| 2203 | MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->modifier", (long)(fb->modifier)); __builtin_expect (!!(__ret), 0); }); |
| 2204 | return 0; |
| 2205 | } |
| 2206 | } |
| 2207 | |
| 2208 | static bool_Bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) |
| 2209 | { |
| 2210 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 2211 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 2212 | |
| 2213 | return INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4 || |
| 2214 | (plane->has_fbc && |
| 2215 | plane_state->view.type == I915_GGTT_VIEW_NORMAL); |
| 2216 | } |
| 2217 | |
| 2218 | struct i915_vma * |
| 2219 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
| 2220 | const struct i915_ggtt_view *view, |
| 2221 | bool_Bool uses_fence, |
| 2222 | unsigned long *out_flags) |
| 2223 | { |
| 2224 | struct drm_device *dev = fb->dev; |
| 2225 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 2226 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 2227 | intel_wakeref_t wakeref; |
| 2228 | struct i915_vma *vma; |
| 2229 | unsigned int pinctl; |
| 2230 | u32 alignment; |
| 2231 | |
| 2232 | if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))({ int __ret = !!((!i915_gem_object_is_framebuffer(obj))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev))-> dev), "", "drm_WARN_ON(" "!i915_gem_object_is_framebuffer(obj)" ")"); __builtin_expect(!!(__ret), 0); })) |
| 2233 | return ERR_PTR(-EINVAL22); |
| 2234 | |
| 2235 | alignment = intel_surf_alignment(fb, 0); |
| 2236 | if (drm_WARN_ON(dev, alignment && !is_power_of_2(alignment))({ int __ret = !!((alignment && !(((alignment) != 0) && (((alignment) - 1) & (alignment)) == 0))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "alignment && !(((alignment) != 0) && (((alignment) - 1) & (alignment)) == 0)" ")"); __builtin_expect(!!(__ret), 0); })) |
| 2237 | return ERR_PTR(-EINVAL22); |
| 2238 | |
| 2239 | /* Note that the w/a also requires 64 PTE of padding following the |
| 2240 | * bo. We currently fill all unused PTE with the shadow page and so |
| 2241 | * we should always have valid PTE following the scanout preventing |
| 2242 | * the VT-d warning. |
| 2243 | */ |
| 2244 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
| 2245 | alignment = 256 * 1024; |
| 2246 | |
| 2247 | /* |
| 2248 | * Global gtt pte registers are special registers which actually forward |
| 2249 | * writes to a chunk of system memory. Which means that there is no risk |
| 2250 | * that the register values disappear as soon as we call |
| 2251 | * intel_runtime_pm_put(), so it is correct to wrap only the |
| 2252 | * pin/unpin/fence and not more. |
| 2253 | */ |
| 2254 | wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); |
| 2255 | |
| 2256 | atomic_inc(&dev_priv->gpu_error.pending_fb_pin)__sync_fetch_and_add(&dev_priv->gpu_error.pending_fb_pin , 1); |
| 2257 | |
| 2258 | /* |
| 2259 | * Valleyview is definitely limited to scanning out the first |
| 2260 | * 512MiB. Lets presume this behaviour was inherited from the |
| 2261 | * g4x display engine and that all earlier gen are similarly |
| 2262 | * limited. Testing suggests that it is a little more |
| 2263 | * complicated than this. For example, Cherryview appears quite |
| 2264 | * happy to scanout from anywhere within its global aperture. |
| 2265 | */ |
| 2266 | pinctl = 0; |
| 2267 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) |
| 2268 | pinctl |= PIN_MAPPABLE(1ULL << (3)); |
| 2269 | |
| 2270 | vma = i915_gem_object_pin_to_display_plane(obj, |
| 2271 | alignment, view, pinctl); |
| 2272 | if (IS_ERR(vma)) |
| 2273 | goto err; |
| 2274 | |
| 2275 | if (uses_fence && i915_vma_is_map_and_fenceable(vma)) { |
| 2276 | int ret; |
| 2277 | |
| 2278 | /* |
| 2279 | * Install a fence for tiled scan-out. Pre-i965 always needs a |
| 2280 | * fence, whereas 965+ only requires a fence if using |
| 2281 | * framebuffer compression. For simplicity, we always, when |
| 2282 | * possible, install a fence as the cost is not that onerous. |
| 2283 | * |
| 2284 | * If we fail to fence the tiled scanout, then either the |
| 2285 | * modeset will reject the change (which is highly unlikely as |
| 2286 | * the affected systems, all but one, do not have unmappable |
| 2287 | * space) or we will not be able to enable full powersaving |
| 2288 | * techniques (also likely not to apply due to various limits |
| 2289 | * FBC and the like impose on the size of the buffer, which |
| 2290 | * presumably we violated anyway with this unmappable buffer). |
| 2291 | * Anyway, it is presumably better to stumble onwards with |
| 2292 | * something and try to run the system in a "less than optimal" |
| 2293 | * mode that matches the user configuration. |
| 2294 | */ |
| 2295 | ret = i915_vma_pin_fence(vma); |
| 2296 | if (ret != 0 && INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) { |
| 2297 | i915_vma_unpin(vma); |
| 2298 | vma = ERR_PTR(ret); |
| 2299 | goto err; |
| 2300 | } |
| 2301 | |
| 2302 | if (ret == 0 && vma->fence) |
| 2303 | *out_flags |= PLANE_HAS_FENCE(1UL << (0)); |
| 2304 | } |
| 2305 | |
| 2306 | i915_vma_get(vma); |
| 2307 | err: |
| 2308 | atomic_dec(&dev_priv->gpu_error.pending_fb_pin)__sync_fetch_and_sub(&dev_priv->gpu_error.pending_fb_pin , 1); |
| 2309 | intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); |
| 2310 | return vma; |
| 2311 | } |
| 2312 | |
| 2313 | void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) |
| 2314 | { |
| 2315 | if (flags & PLANE_HAS_FENCE(1UL << (0))) |
| 2316 | i915_vma_unpin_fence(vma); |
| 2317 | i915_vma_unpin(vma); |
| 2318 | i915_vma_put(vma); |
| 2319 | } |
| 2320 | |
| 2321 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane, |
| 2322 | unsigned int rotation) |
| 2323 | { |
| 2324 | if (drm_rotation_90_or_270(rotation)) |
| 2325 | return to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );})->rotated[color_plane].pitch; |
| 2326 | else |
| 2327 | return fb->pitches[color_plane]; |
| 2328 | } |
| 2329 | |
| 2330 | /* |
| 2331 | * Convert the x/y offsets into a linear offset. |
| 2332 | * Only valid with 0/180 degree rotation, which is fine since linear |
| 2333 | * offset is only used with linear buffers on pre-hsw and tiled buffers |
| 2334 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. |
| 2335 | */ |
| 2336 | u32 intel_fb_xy_to_linear(int x, int y, |
| 2337 | const struct intel_plane_state *state, |
| 2338 | int color_plane) |
| 2339 | { |
| 2340 | const struct drm_framebuffer *fb = state->hw.fb; |
| 2341 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 2342 | unsigned int pitch = state->color_plane[color_plane].stride; |
| 2343 | |
| 2344 | return y * pitch + x * cpp; |
| 2345 | } |
| 2346 | |
| 2347 | /* |
| 2348 | * Add the x/y offsets derived from fb->offsets[] to the user |
| 2349 | * specified plane src x/y offsets. The resulting x/y offsets |
| 2350 | * specify the start of scanout from the beginning of the gtt mapping. |
| 2351 | */ |
| 2352 | void intel_add_fb_offsets(int *x, int *y, |
| 2353 | const struct intel_plane_state *state, |
| 2354 | int color_plane) |
| 2355 | |
| 2356 | { |
| 2357 | *x += state->color_plane[color_plane].x; |
| 2358 | *y += state->color_plane[color_plane].y; |
| 2359 | } |
| 2360 | |
| 2361 | static u32 intel_adjust_tile_offset(int *x, int *y, |
| 2362 | unsigned int tile_width, |
| 2363 | unsigned int tile_height, |
| 2364 | unsigned int tile_size, |
| 2365 | unsigned int pitch_tiles, |
| 2366 | u32 old_offset, |
| 2367 | u32 new_offset) |
| 2368 | { |
| 2369 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
| 2370 | unsigned int tiles; |
| 2371 | |
| 2372 | WARN_ON(old_offset & (tile_size - 1))({ int __ret = !!((old_offset & (tile_size - 1))); if (__ret ) printf("%s", "WARN_ON(" "old_offset & (tile_size - 1)" ")" ); __builtin_expect(!!(__ret), 0); }); |
| 2373 | WARN_ON(new_offset & (tile_size - 1))({ int __ret = !!((new_offset & (tile_size - 1))); if (__ret ) printf("%s", "WARN_ON(" "new_offset & (tile_size - 1)" ")" ); __builtin_expect(!!(__ret), 0); }); |
| 2374 | WARN_ON(new_offset > old_offset)({ int __ret = !!((new_offset > old_offset)); if (__ret) printf ("%s", "WARN_ON(" "new_offset > old_offset" ")"); __builtin_expect (!!(__ret), 0); }); |
| 2375 | |
| 2376 | tiles = (old_offset - new_offset) / tile_size; |
| 2377 | |
| 2378 | *y += tiles / pitch_tiles * tile_height; |
| 2379 | *x += tiles % pitch_tiles * tile_width; |
| 2380 | |
| 2381 | /* minimize x in case it got needlessly big */ |
| 2382 | *y += *x / pitch_pixels * tile_height; |
| 2383 | *x %= pitch_pixels; |
| 2384 | |
| 2385 | return new_offset; |
| 2386 | } |
| 2387 | |
| 2388 | static bool_Bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) |
| 2389 | { |
| 2390 | return fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) || |
| 2391 | is_gen12_ccs_plane(fb, color_plane); |
| 2392 | } |
| 2393 | |
| 2394 | static u32 intel_adjust_aligned_offset(int *x, int *y, |
| 2395 | const struct drm_framebuffer *fb, |
| 2396 | int color_plane, |
| 2397 | unsigned int rotation, |
| 2398 | unsigned int pitch, |
| 2399 | u32 old_offset, u32 new_offset) |
| 2400 | { |
| 2401 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 2402 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 2403 | |
| 2404 | drm_WARN_ON(&dev_priv->drm, new_offset > old_offset)({ int __ret = !!((new_offset > old_offset)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "new_offset > old_offset" ")"); __builtin_expect (!!(__ret), 0); }); |
| 2405 | |
| 2406 | if (!is_surface_linear(fb, color_plane)) { |
| 2407 | unsigned int tile_size, tile_width, tile_height; |
| 2408 | unsigned int pitch_tiles; |
| 2409 | |
| 2410 | tile_size = intel_tile_size(dev_priv); |
| 2411 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
| 2412 | |
| 2413 | if (drm_rotation_90_or_270(rotation)) { |
| 2414 | pitch_tiles = pitch / tile_height; |
| 2415 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 2416 | } else { |
| 2417 | pitch_tiles = pitch / (tile_width * cpp); |
| 2418 | } |
| 2419 | |
| 2420 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
| 2421 | tile_size, pitch_tiles, |
| 2422 | old_offset, new_offset); |
| 2423 | } else { |
| 2424 | old_offset += *y * pitch + *x * cpp; |
| 2425 | |
| 2426 | *y = (old_offset - new_offset) / pitch; |
| 2427 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; |
| 2428 | } |
| 2429 | |
| 2430 | return new_offset; |
| 2431 | } |
| 2432 | |
| 2433 | /* |
| 2434 | * Adjust the tile offset by moving the difference into |
| 2435 | * the x/y offsets. |
| 2436 | */ |
| 2437 | static u32 intel_plane_adjust_aligned_offset(int *x, int *y, |
| 2438 | const struct intel_plane_state *state, |
| 2439 | int color_plane, |
| 2440 | u32 old_offset, u32 new_offset) |
| 2441 | { |
| 2442 | return intel_adjust_aligned_offset(x, y, state->hw.fb, color_plane, |
| 2443 | state->hw.rotation, |
| 2444 | state->color_plane[color_plane].stride, |
| 2445 | old_offset, new_offset); |
| 2446 | } |
| 2447 | |
| 2448 | /* |
| 2449 | * Computes the aligned offset to the base tile and adjusts |
| 2450 | * x, y. bytes per pixel is assumed to be a power-of-two. |
| 2451 | * |
| 2452 | * In the 90/270 rotated case, x and y are assumed |
| 2453 | * to be already rotated to match the rotated GTT view, and |
| 2454 | * pitch is the tile_height aligned framebuffer height. |
| 2455 | * |
| 2456 | * This function is used when computing the derived information |
| 2457 | * under intel_framebuffer, so using any of that information |
| 2458 | * here is not allowed. Anything under drm_framebuffer can be |
| 2459 | * used. This is why the user has to pass in the pitch since it |
| 2460 | * is specified in the rotated orientation. |
| 2461 | */ |
| 2462 | static u32 intel_compute_aligned_offset(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2463 | int *x, int *y, |
| 2464 | const struct drm_framebuffer *fb, |
| 2465 | int color_plane, |
| 2466 | unsigned int pitch, |
| 2467 | unsigned int rotation, |
| 2468 | u32 alignment) |
| 2469 | { |
| 2470 | unsigned int cpp = fb->format->cpp[color_plane]; |
| 2471 | u32 offset, offset_aligned; |
| 2472 | |
| 2473 | if (!is_surface_linear(fb, color_plane)) { |
| 2474 | unsigned int tile_size, tile_width, tile_height; |
| 2475 | unsigned int tile_rows, tiles, pitch_tiles; |
| 2476 | |
| 2477 | tile_size = intel_tile_size(dev_priv); |
| 2478 | intel_tile_dims(fb, color_plane, &tile_width, &tile_height); |
| 2479 | |
| 2480 | if (drm_rotation_90_or_270(rotation)) { |
| 2481 | pitch_tiles = pitch / tile_height; |
| 2482 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 2483 | } else { |
| 2484 | pitch_tiles = pitch / (tile_width * cpp); |
| 2485 | } |
| 2486 | |
| 2487 | tile_rows = *y / tile_height; |
| 2488 | *y %= tile_height; |
| 2489 | |
| 2490 | tiles = *x / tile_width; |
| 2491 | *x %= tile_width; |
| 2492 | |
| 2493 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
| 2494 | |
| 2495 | offset_aligned = offset; |
| 2496 | if (alignment) |
| 2497 | offset_aligned = rounddown(offset_aligned, alignment)(((offset_aligned) / (alignment)) * (alignment)); |
| 2498 | |
| 2499 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
| 2500 | tile_size, pitch_tiles, |
| 2501 | offset, offset_aligned); |
| 2502 | } else { |
| 2503 | offset = *y * pitch + *x * cpp; |
| 2504 | offset_aligned = offset; |
| 2505 | if (alignment) { |
| 2506 | offset_aligned = rounddown(offset_aligned, alignment)(((offset_aligned) / (alignment)) * (alignment)); |
| 2507 | *y = (offset % alignment) / pitch; |
| 2508 | *x = ((offset % alignment) - *y * pitch) / cpp; |
| 2509 | } else { |
| 2510 | *y = *x = 0; |
| 2511 | } |
| 2512 | } |
| 2513 | |
| 2514 | return offset_aligned; |
| 2515 | } |
| 2516 | |
| 2517 | static u32 intel_plane_compute_aligned_offset(int *x, int *y, |
| 2518 | const struct intel_plane_state *state, |
| 2519 | int color_plane) |
| 2520 | { |
| 2521 | struct intel_plane *intel_plane = to_intel_plane(state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 2522 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_plane->base.dev); |
| 2523 | const struct drm_framebuffer *fb = state->hw.fb; |
| 2524 | unsigned int rotation = state->hw.rotation; |
| 2525 | int pitch = state->color_plane[color_plane].stride; |
| 2526 | u32 alignment; |
| 2527 | |
| 2528 | if (intel_plane->id == PLANE_CURSOR) |
| 2529 | alignment = intel_cursor_alignment(dev_priv); |
| 2530 | else |
| 2531 | alignment = intel_surf_alignment(fb, color_plane); |
| 2532 | |
| 2533 | return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane, |
| 2534 | pitch, rotation, alignment); |
| 2535 | } |
| 2536 | |
| 2537 | /* Convert the fb->offset[] into x/y offsets */ |
| 2538 | static int intel_fb_offset_to_xy(int *x, int *y, |
| 2539 | const struct drm_framebuffer *fb, |
| 2540 | int color_plane) |
| 2541 | { |
| 2542 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 2543 | unsigned int height; |
| 2544 | u32 alignment; |
| 2545 | |
| 2546 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 && |
| 2547 | is_semiplanar_uv_plane(fb, color_plane)) |
| 2548 | alignment = intel_tile_row_size(fb, color_plane); |
| 2549 | else if (fb->modifier != DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) )) |
| 2550 | alignment = intel_tile_size(dev_priv); |
| 2551 | else |
| 2552 | alignment = 0; |
| 2553 | |
| 2554 | if (alignment != 0 && fb->offsets[color_plane] % alignment) { |
| 2555 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n" , fb->offsets[color_plane], color_plane) |
| 2556 | "Misaligned offset 0x%08x for color plane %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n" , fb->offsets[color_plane], color_plane) |
| 2557 | fb->offsets[color_plane], color_plane)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Misaligned offset 0x%08x for color plane %d\n" , fb->offsets[color_plane], color_plane); |
| 2558 | return -EINVAL22; |
| 2559 | } |
| 2560 | |
| 2561 | height = drm_framebuffer_plane_height(fb->height, fb, color_plane); |
| 2562 | height = roundup2(height, intel_tile_height(fb, color_plane))(((height) + ((intel_tile_height(fb, color_plane)) - 1)) & (~((__typeof(height))(intel_tile_height(fb, color_plane)) - 1 ))); |
| 2563 | |
| 2564 | /* Catch potential overflows early */ |
| 2565 | if (add_overflows_t(u32, mul_u32_u32(height, fb->pitches[color_plane]),({ typeof(mul_u32_u32(height, fb->pitches[color_plane])) a = (mul_u32_u32(height, fb->pitches[color_plane])); typeof (fb->offsets[color_plane]) b = (fb->offsets[color_plane ]); (u32)(a + b) < a; }) |
| 2566 | fb->offsets[color_plane])({ typeof(mul_u32_u32(height, fb->pitches[color_plane])) a = (mul_u32_u32(height, fb->pitches[color_plane])); typeof (fb->offsets[color_plane]) b = (fb->offsets[color_plane ]); (u32)(a + b) < a; })) { |
| 2567 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ) |
| 2568 | "Bad offset 0x%08x or pitch %d for color plane %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ) |
| 2569 | fb->offsets[color_plane], fb->pitches[color_plane],drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ) |
| 2570 | color_plane)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Bad offset 0x%08x or pitch %d for color plane %d\n" , fb->offsets[color_plane], fb->pitches[color_plane], color_plane ); |
| 2571 | return -ERANGE34; |
| 2572 | } |
| 2573 | |
| 2574 | *x = 0; |
| 2575 | *y = 0; |
| 2576 | |
| 2577 | intel_adjust_aligned_offset(x, y, |
| 2578 | fb, color_plane, DRM_MODE_ROTATE_0(1<<0), |
| 2579 | fb->pitches[color_plane], |
| 2580 | fb->offsets[color_plane], 0); |
| 2581 | |
| 2582 | return 0; |
| 2583 | } |
| 2584 | |
| 2585 | static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) |
| 2586 | { |
| 2587 | switch (fb_modifier) { |
| 2588 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 2589 | return I915_TILING_X1; |
| 2590 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 2591 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 2592 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 2593 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 2594 | return I915_TILING_Y2; |
| 2595 | default: |
| 2596 | return I915_TILING_NONE0; |
| 2597 | } |
| 2598 | } |
| 2599 | |
| 2600 | /* |
| 2601 | * From the Sky Lake PRM: |
| 2602 | * "The Color Control Surface (CCS) contains the compression status of |
| 2603 | * the cache-line pairs. The compression state of the cache-line pair |
| 2604 | * is specified by 2 bits in the CCS. Each CCS cache-line represents |
| 2605 | * an area on the main surface of 16 x16 sets of 128 byte Y-tiled |
| 2606 | * cache-line-pairs. CCS is always Y tiled." |
| 2607 | * |
| 2608 | * Since cache line pairs refers to horizontally adjacent cache lines, |
| 2609 | * each cache line in the CCS corresponds to an area of 32x16 cache |
| 2610 | * lines on the main surface. Since each pixel is 4 bytes, this gives |
| 2611 | * us a ratio of one byte in the CCS for each 8x16 pixels in the |
| 2612 | * main surface. |
| 2613 | */ |
| 2614 | static const struct drm_format_info skl_ccs_formats[] = { |
| 2615 | { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 2616 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, |
| 2617 | { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 2618 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, |
| 2619 | { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 2620 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true1, }, |
| 2621 | { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 2622 | .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true1, }, |
| 2623 | }; |
| 2624 | |
| 2625 | /* |
| 2626 | * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the |
| 2627 | * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles |
| 2628 | * in the main surface. With 4 byte pixels and each Y-tile having dimensions of |
| 2629 | * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in |
| 2630 | * the main surface. |
| 2631 | */ |
| 2632 | static const struct drm_format_info gen12_ccs_formats[] = { |
| 2633 | { .format = DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 2634 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2635 | .hsub = 1, .vsub = 1, }, |
| 2636 | { .format = DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 24, .num_planes = 2, |
| 2637 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2638 | .hsub = 1, .vsub = 1, }, |
| 2639 | { .format = DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 2640 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2641 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 2642 | { .format = DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)), .depth = 32, .num_planes = 2, |
| 2643 | .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2644 | .hsub = 1, .vsub = 1, .has_alpha = true1 }, |
| 2645 | { .format = DRM_FORMAT_YUYV((__u32)('Y') | ((__u32)('U') << 8) | ((__u32)('Y') << 16) | ((__u32)('V') << 24)), .num_planes = 2, |
| 2646 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2647 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 2648 | { .format = DRM_FORMAT_YVYU((__u32)('Y') | ((__u32)('V') << 8) | ((__u32)('Y') << 16) | ((__u32)('U') << 24)), .num_planes = 2, |
| 2649 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2650 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 2651 | { .format = DRM_FORMAT_UYVY((__u32)('U') | ((__u32)('Y') << 8) | ((__u32)('V') << 16) | ((__u32)('Y') << 24)), .num_planes = 2, |
| 2652 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2653 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 2654 | { .format = DRM_FORMAT_VYUY((__u32)('V') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('Y') << 24)), .num_planes = 2, |
| 2655 | .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, |
| 2656 | .hsub = 2, .vsub = 1, .is_yuv = true1 }, |
| 2657 | { .format = DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)), .num_planes = 4, |
| 2658 | .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, |
| 2659 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 2660 | { .format = DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)), .num_planes = 4, |
| 2661 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, |
| 2662 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 2663 | { .format = DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)), .num_planes = 4, |
| 2664 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, |
| 2665 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 2666 | { .format = DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)), .num_planes = 4, |
| 2667 | .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, |
| 2668 | .hsub = 2, .vsub = 2, .is_yuv = true1 }, |
| 2669 | }; |
| 2670 | |
| 2671 | static const struct drm_format_info * |
| 2672 | lookup_format_info(const struct drm_format_info formats[], |
| 2673 | int num_formats, u32 format) |
| 2674 | { |
| 2675 | int i; |
| 2676 | |
| 2677 | for (i = 0; i < num_formats; i++) { |
| 2678 | if (formats[i].format == format) |
| 2679 | return &formats[i]; |
| 2680 | } |
| 2681 | |
| 2682 | return NULL((void *)0); |
| 2683 | } |
| 2684 | |
| 2685 | static const struct drm_format_info * |
| 2686 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) |
| 2687 | { |
| 2688 | switch (cmd->modifier[0]) { |
| 2689 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 2690 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 2691 | return lookup_format_info(skl_ccs_formats, |
| 2692 | ARRAY_SIZE(skl_ccs_formats)(sizeof((skl_ccs_formats)) / sizeof((skl_ccs_formats)[0])), |
| 2693 | cmd->pixel_format); |
| 2694 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 2695 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 2696 | return lookup_format_info(gen12_ccs_formats, |
| 2697 | ARRAY_SIZE(gen12_ccs_formats)(sizeof((gen12_ccs_formats)) / sizeof((gen12_ccs_formats)[0]) ), |
| 2698 | cmd->pixel_format); |
| 2699 | default: |
| 2700 | return NULL((void *)0); |
| 2701 | } |
| 2702 | } |
| 2703 | |
| 2704 | bool_Bool is_ccs_modifier(u64 modifier) |
| 2705 | { |
| 2706 | return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )) || |
| 2707 | modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )) || |
| 2708 | modifier == I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )) || |
| 2709 | modifier == I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )); |
| 2710 | } |
| 2711 | |
| 2712 | static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane) |
| 2713 | { |
| 2714 | return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],(((fb->pitches[ccs_to_main_plane(fb, ccs_plane)]) + ((512) - 1)) / (512)) |
| 2715 | 512)(((fb->pitches[ccs_to_main_plane(fb, ccs_plane)]) + ((512) - 1)) / (512)) * 64; |
| 2716 | } |
| 2717 | |
| 2718 | u32 intel_plane_fb_max_stride(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2719 | u32 pixel_format, u64 modifier) |
| 2720 | { |
| 2721 | struct intel_crtc *crtc; |
| 2722 | struct intel_plane *plane; |
| 2723 | |
| 2724 | /* |
| 2725 | * We assume the primary plane for pipe A has |
| 2726 | * the highest stride limits of them all, |
| 2727 | * if in case pipe A is disabled, use the first pipe from pipe_mask. |
| 2728 | */ |
| 2729 | crtc = intel_get_first_crtc(dev_priv); |
| 2730 | if (!crtc) |
| 2731 | return 0; |
| 2732 | |
| 2733 | plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 2734 | |
| 2735 | return plane->max_stride(plane, pixel_format, modifier, |
| 2736 | DRM_MODE_ROTATE_0(1<<0)); |
| 2737 | } |
| 2738 | |
| 2739 | static |
| 2740 | u32 intel_fb_max_stride(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 2741 | u32 pixel_format, u64 modifier) |
| 2742 | { |
| 2743 | /* |
| 2744 | * Arbitrary limit for gen4+ chosen to match the |
| 2745 | * render engine max stride. |
| 2746 | * |
| 2747 | * The new CCS hash mode makes remapping impossible |
| 2748 | */ |
| 2749 | if (!is_ccs_modifier(modifier)) { |
| 2750 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 7) |
| 2751 | return 256*1024; |
| 2752 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 2753 | return 128*1024; |
| 2754 | } |
| 2755 | |
| 2756 | return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); |
| 2757 | } |
| 2758 | |
| 2759 | static u32 |
| 2760 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) |
| 2761 | { |
| 2762 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(fb->dev); |
| 2763 | u32 tile_width; |
| 2764 | |
| 2765 | if (is_surface_linear(fb, color_plane)) { |
| 2766 | u32 max_stride = intel_plane_fb_max_stride(dev_priv, |
| 2767 | fb->format->format, |
| 2768 | fb->modifier); |
| 2769 | |
| 2770 | /* |
| 2771 | * To make remapping with linear generally feasible |
| 2772 | * we need the stride to be page aligned. |
| 2773 | */ |
| 2774 | if (fb->pitches[color_plane] > max_stride && |
| 2775 | !is_ccs_modifier(fb->modifier)) |
| 2776 | return intel_tile_size(dev_priv); |
| 2777 | else |
| 2778 | return 64; |
| 2779 | } |
| 2780 | |
| 2781 | tile_width = intel_tile_width_bytes(fb, color_plane); |
| 2782 | if (is_ccs_modifier(fb->modifier)) { |
| 2783 | /* |
| 2784 | * Display WA #0531: skl,bxt,kbl,glk |
| 2785 | * |
| 2786 | * Render decompression and plane width > 3840 |
| 2787 | * combined with horizontal panning requires the |
| 2788 | * plane stride to be a multiple of 4. We'll just |
| 2789 | * require the entire fb to accommodate that to avoid |
| 2790 | * potential runtime errors at plane configuration time. |
| 2791 | */ |
| 2792 | if (IS_GEN(dev_priv, 9)(0 + (&(dev_priv)->__info)->gen == (9)) && color_plane == 0 && fb->width > 3840) |
| 2793 | tile_width *= 4; |
| 2794 | /* |
| 2795 | * The main surface pitch must be padded to a multiple of four |
| 2796 | * tile widths. |
| 2797 | */ |
| 2798 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 2799 | tile_width *= 4; |
| 2800 | } |
| 2801 | return tile_width; |
| 2802 | } |
| 2803 | |
| 2804 | bool_Bool intel_plane_can_remap(const struct intel_plane_state *plane_state) |
| 2805 | { |
| 2806 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 2807 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 2808 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 2809 | int i; |
| 2810 | |
| 2811 | /* We don't want to deal with remapping with cursors */ |
| 2812 | if (plane->id == PLANE_CURSOR) |
| 2813 | return false0; |
| 2814 | |
| 2815 | /* |
| 2816 | * The display engine limits already match/exceed the |
| 2817 | * render engine limits, so not much point in remapping. |
| 2818 | * Would also need to deal with the fence POT alignment |
| 2819 | * and gen2 2KiB GTT tile size. |
| 2820 | */ |
| 2821 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) |
| 2822 | return false0; |
| 2823 | |
| 2824 | /* |
| 2825 | * The new CCS hash mode isn't compatible with remapping as |
| 2826 | * the virtual address of the pages affects the compressed data. |
| 2827 | */ |
| 2828 | if (is_ccs_modifier(fb->modifier)) |
| 2829 | return false0; |
| 2830 | |
| 2831 | /* Linear needs a page aligned stride for remapping */ |
| 2832 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) )) { |
| 2833 | unsigned int alignment = intel_tile_size(dev_priv) - 1; |
| 2834 | |
| 2835 | for (i = 0; i < fb->format->num_planes; i++) { |
| 2836 | if (fb->pitches[i] & alignment) |
| 2837 | return false0; |
| 2838 | } |
| 2839 | } |
| 2840 | |
| 2841 | return true1; |
| 2842 | } |
| 2843 | |
| 2844 | static bool_Bool intel_plane_needs_remap(const struct intel_plane_state *plane_state) |
| 2845 | { |
| 2846 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 2847 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 2848 | unsigned int rotation = plane_state->hw.rotation; |
| 2849 | u32 stride, max_stride; |
| 2850 | |
| 2851 | /* |
| 2852 | * No remapping for invisible planes since we don't have |
| 2853 | * an actual source viewport to remap. |
| 2854 | */ |
| 2855 | if (!plane_state->uapi.visible) |
| 2856 | return false0; |
| 2857 | |
| 2858 | if (!intel_plane_can_remap(plane_state)) |
| 2859 | return false0; |
| 2860 | |
| 2861 | /* |
| 2862 | * FIXME: aux plane limits on gen9+ are |
| 2863 | * unclear in Bspec, for now no checking. |
| 2864 | */ |
| 2865 | stride = intel_fb_pitch(fb, 0, rotation); |
| 2866 | max_stride = plane->max_stride(plane, fb->format->format, |
| 2867 | fb->modifier, rotation); |
| 2868 | |
| 2869 | return stride > max_stride; |
| 2870 | } |
| 2871 | |
| 2872 | static void |
| 2873 | intel_fb_plane_get_subsampling(int *hsub, int *vsub, |
| 2874 | const struct drm_framebuffer *fb, |
| 2875 | int color_plane) |
| 2876 | { |
| 2877 | int main_plane; |
| 2878 | |
| 2879 | if (color_plane == 0) { |
| 2880 | *hsub = 1; |
| 2881 | *vsub = 1; |
| 2882 | |
| 2883 | return; |
| 2884 | } |
| 2885 | |
| 2886 | /* |
| 2887 | * TODO: Deduct the subsampling from the char block for all CCS |
| 2888 | * formats and planes. |
| 2889 | */ |
| 2890 | if (!is_gen12_ccs_plane(fb, color_plane)) { |
| 2891 | *hsub = fb->format->hsub; |
| 2892 | *vsub = fb->format->vsub; |
| 2893 | |
| 2894 | return; |
| 2895 | } |
| 2896 | |
| 2897 | main_plane = ccs_to_main_plane(fb, color_plane); |
| 2898 | *hsub = drm_format_info_block_width(fb->format, color_plane) / |
| 2899 | drm_format_info_block_width(fb->format, main_plane); |
| 2900 | |
| 2901 | /* |
| 2902 | * The min stride check in the core framebuffer_check() function |
| 2903 | * assumes that format->hsub applies to every plane except for the |
| 2904 | * first plane. That's incorrect for the CCS AUX plane of the first |
| 2905 | * plane, but for the above check to pass we must define the block |
| 2906 | * width with that subsampling applied to it. Adjust the width here |
| 2907 | * accordingly, so we can calculate the actual subsampling factor. |
| 2908 | */ |
| 2909 | if (main_plane == 0) |
| 2910 | *hsub *= fb->format->hsub; |
| 2911 | |
| 2912 | *vsub = 32; |
| 2913 | } |
| 2914 | static int |
| 2915 | intel_fb_check_ccs_xy(struct drm_framebuffer *fb, int ccs_plane, int x, int y) |
| 2916 | { |
| 2917 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(fb->dev); |
| 2918 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 2919 | int main_plane; |
| 2920 | int hsub, vsub; |
| 2921 | int tile_width, tile_height; |
| 2922 | int ccs_x, ccs_y; |
| 2923 | int main_x, main_y; |
| 2924 | |
| 2925 | if (!is_ccs_plane(fb, ccs_plane)) |
| 2926 | return 0; |
| 2927 | |
| 2928 | intel_tile_dims(fb, ccs_plane, &tile_width, &tile_height); |
| 2929 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); |
| 2930 | |
| 2931 | tile_width *= hsub; |
| 2932 | tile_height *= vsub; |
| 2933 | |
| 2934 | ccs_x = (x * hsub) % tile_width; |
| 2935 | ccs_y = (y * vsub) % tile_height; |
| 2936 | |
| 2937 | main_plane = ccs_to_main_plane(fb, ccs_plane); |
| 2938 | main_x = intel_fb->normal[main_plane].x % tile_width; |
| 2939 | main_y = intel_fb->normal[main_plane].y % tile_height; |
| 2940 | |
| 2941 | /* |
| 2942 | * CCS doesn't have its own x/y offset register, so the intra CCS tile |
| 2943 | * x/y offsets must match between CCS and the main surface. |
| 2944 | */ |
| 2945 | if (main_x != ccs_x || main_y != ccs_y) { |
| 2946 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y) |
| 2947 | "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y) |
| 2948 | main_x, main_y,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y) |
| 2949 | ccs_x, ccs_y,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y) |
| 2950 | intel_fb->normal[main_plane].x,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y) |
| 2951 | intel_fb->normal[main_plane].y,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y) |
| 2952 | x, y)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n" , main_x, main_y, ccs_x, ccs_y, intel_fb->normal[main_plane ].x, intel_fb->normal[main_plane].y, x, y); |
| 2953 | return -EINVAL22; |
| 2954 | } |
| 2955 | |
| 2956 | return 0; |
| 2957 | } |
| 2958 | |
| 2959 | static void |
| 2960 | intel_fb_plane_dims(int *w, int *h, struct drm_framebuffer *fb, int color_plane) |
| 2961 | { |
| 2962 | int main_plane = is_ccs_plane(fb, color_plane) ? |
| 2963 | ccs_to_main_plane(fb, color_plane) : 0; |
| 2964 | int main_hsub, main_vsub; |
| 2965 | int hsub, vsub; |
| 2966 | |
| 2967 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, main_plane); |
| 2968 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, color_plane); |
| 2969 | *w = fb->width / main_hsub / hsub; |
| 2970 | *h = fb->height / main_vsub / vsub; |
| 2971 | } |
| 2972 | |
| 2973 | /* |
| 2974 | * Setup the rotated view for an FB plane and return the size the GTT mapping |
| 2975 | * requires for this view. |
| 2976 | */ |
| 2977 | static u32 |
| 2978 | setup_fb_rotation(int plane, const struct intel_remapped_plane_info *plane_info, |
| 2979 | u32 gtt_offset_rotated, int x, int y, |
| 2980 | unsigned int width, unsigned int height, |
| 2981 | unsigned int tile_size, |
| 2982 | unsigned int tile_width, unsigned int tile_height, |
| 2983 | struct drm_framebuffer *fb) |
| 2984 | { |
| 2985 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 2986 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; |
| 2987 | unsigned int pitch_tiles; |
| 2988 | struct drm_rect r; |
| 2989 | |
| 2990 | /* Y or Yf modifiers required for 90/270 rotation */ |
| 2991 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )) && |
| 2992 | fb->modifier != I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL ))) |
| 2993 | return 0; |
| 2994 | |
| 2995 | if (drm_WARN_ON(fb->dev, plane >= ARRAY_SIZE(rot_info->plane))({ int __ret = !!((plane >= (sizeof((rot_info->plane)) / sizeof((rot_info->plane)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((fb->dev))->dev), "", "drm_WARN_ON(" "plane >= (sizeof((rot_info->plane)) / sizeof((rot_info->plane)[0]))" ")"); __builtin_expect(!!(__ret), 0); })) |
| 2996 | return 0; |
| 2997 | |
| 2998 | rot_info->plane[plane] = *plane_info; |
| 2999 | |
| 3000 | intel_fb->rotated[plane].pitch = plane_info->height * tile_height; |
| 3001 | |
| 3002 | /* rotate the x/y offsets to match the GTT view */ |
| 3003 | drm_rect_init(&r, x, y, width, height); |
| 3004 | drm_rect_rotate(&r, |
| 3005 | plane_info->width * tile_width, |
| 3006 | plane_info->height * tile_height, |
| 3007 | DRM_MODE_ROTATE_270(1<<3)); |
| 3008 | x = r.x1; |
| 3009 | y = r.y1; |
| 3010 | |
| 3011 | /* rotate the tile dimensions to match the GTT view */ |
| 3012 | pitch_tiles = intel_fb->rotated[plane].pitch / tile_height; |
| 3013 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 3014 | |
| 3015 | /* |
| 3016 | * We only keep the x/y offsets, so push all of the |
| 3017 | * gtt offset into the x/y offsets. |
| 3018 | */ |
| 3019 | intel_adjust_tile_offset(&x, &y, |
| 3020 | tile_width, tile_height, |
| 3021 | tile_size, pitch_tiles, |
| 3022 | gtt_offset_rotated * tile_size, 0); |
| 3023 | |
| 3024 | /* |
| 3025 | * First pixel of the framebuffer from |
| 3026 | * the start of the rotated gtt mapping. |
| 3027 | */ |
| 3028 | intel_fb->rotated[plane].x = x; |
| 3029 | intel_fb->rotated[plane].y = y; |
| 3030 | |
| 3031 | return plane_info->width * plane_info->height; |
| 3032 | } |
| 3033 | |
| 3034 | static int |
| 3035 | intel_fill_fb_info(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 3036 | struct drm_framebuffer *fb) |
| 3037 | { |
| 3038 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 3039 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 3040 | u32 gtt_offset_rotated = 0; |
| 3041 | unsigned int max_size = 0; |
| 3042 | int i, num_planes = fb->format->num_planes; |
| 3043 | unsigned int tile_size = intel_tile_size(dev_priv); |
| 3044 | |
| 3045 | for (i = 0; i < num_planes; i++) { |
| 3046 | unsigned int width, height; |
| 3047 | unsigned int cpp, size; |
| 3048 | u32 offset; |
| 3049 | int x, y; |
| 3050 | int ret; |
| 3051 | |
| 3052 | cpp = fb->format->cpp[i]; |
| 3053 | intel_fb_plane_dims(&width, &height, fb, i); |
| 3054 | |
| 3055 | ret = intel_fb_offset_to_xy(&x, &y, fb, i); |
| 3056 | if (ret) { |
| 3057 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , i, fb->offsets[i]) |
| 3058 | "bad fb plane %d offset: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , i, fb->offsets[i]) |
| 3059 | i, fb->offsets[i])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , i, fb->offsets[i]); |
| 3060 | return ret; |
| 3061 | } |
| 3062 | |
| 3063 | ret = intel_fb_check_ccs_xy(fb, i, x, y); |
| 3064 | if (ret) |
| 3065 | return ret; |
| 3066 | |
| 3067 | /* |
| 3068 | * The fence (if used) is aligned to the start of the object |
| 3069 | * so having the framebuffer wrap around across the edge of the |
| 3070 | * fenced region doesn't really work. We have no API to configure |
| 3071 | * the fence start offset within the object (nor could we probably |
| 3072 | * on gen2/3). So it's just easier if we just require that the |
| 3073 | * fb layout agrees with the fence layout. We already check that the |
| 3074 | * fb stride matches the fence stride elsewhere. |
| 3075 | */ |
| 3076 | if (i == 0 && i915_gem_object_is_tiled(obj) && |
| 3077 | (x + width) * cpp > fb->pitches[i]) { |
| 3078 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , i, fb->offsets[i]) |
| 3079 | "bad fb plane %d offset: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , i, fb->offsets[i]) |
| 3080 | i, fb->offsets[i])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad fb plane %d offset: 0x%x\n" , i, fb->offsets[i]); |
| 3081 | return -EINVAL22; |
| 3082 | } |
| 3083 | |
| 3084 | /* |
| 3085 | * First pixel of the framebuffer from |
| 3086 | * the start of the normal gtt mapping. |
| 3087 | */ |
| 3088 | intel_fb->normal[i].x = x; |
| 3089 | intel_fb->normal[i].y = y; |
| 3090 | |
| 3091 | offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i, |
| 3092 | fb->pitches[i], |
| 3093 | DRM_MODE_ROTATE_0(1<<0), |
| 3094 | tile_size); |
| 3095 | offset /= tile_size; |
| 3096 | |
| 3097 | if (!is_surface_linear(fb, i)) { |
| 3098 | struct intel_remapped_plane_info plane_info; |
| 3099 | unsigned int tile_width, tile_height; |
| 3100 | |
| 3101 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
| 3102 | |
| 3103 | plane_info.offset = offset; |
| 3104 | plane_info.stride = DIV_ROUND_UP(fb->pitches[i],(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width * cpp)) |
| 3105 | tile_width * cpp)(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width * cpp)); |
| 3106 | plane_info.width = DIV_ROUND_UP(x + width, tile_width)(((x + width) + ((tile_width) - 1)) / (tile_width)); |
| 3107 | plane_info.height = DIV_ROUND_UP(y + height,(((y + height) + ((tile_height) - 1)) / (tile_height)) |
| 3108 | tile_height)(((y + height) + ((tile_height) - 1)) / (tile_height)); |
| 3109 | |
| 3110 | /* how many tiles does this plane need */ |
| 3111 | size = plane_info.stride * plane_info.height; |
| 3112 | /* |
| 3113 | * If the plane isn't horizontally tile aligned, |
| 3114 | * we need one more tile. |
| 3115 | */ |
| 3116 | if (x != 0) |
| 3117 | size++; |
| 3118 | |
| 3119 | gtt_offset_rotated += |
| 3120 | setup_fb_rotation(i, &plane_info, |
| 3121 | gtt_offset_rotated, |
| 3122 | x, y, width, height, |
| 3123 | tile_size, |
| 3124 | tile_width, tile_height, |
| 3125 | fb); |
| 3126 | } else { |
| 3127 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] +((((y + height) * fb->pitches[i] + x * cpp) + ((tile_size) - 1)) / (tile_size)) |
| 3128 | x * cpp, tile_size)((((y + height) * fb->pitches[i] + x * cpp) + ((tile_size) - 1)) / (tile_size)); |
| 3129 | } |
| 3130 | |
| 3131 | /* how many tiles in total needed in the bo */ |
| 3132 | max_size = max(max_size, offset + size)(((max_size)>(offset + size))?(max_size):(offset + size)); |
| 3133 | } |
| 3134 | |
| 3135 | if (mul_u32_u32(max_size, tile_size) > obj->base.size) { |
| 3136 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n" , mul_u32_u32(max_size, tile_size), obj->base.size) |
| 3137 | "fb too big for bo (need %llu bytes, have %zu bytes)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n" , mul_u32_u32(max_size, tile_size), obj->base.size) |
| 3138 | mul_u32_u32(max_size, tile_size), obj->base.size)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fb too big for bo (need %llu bytes, have %zu bytes)\n" , mul_u32_u32(max_size, tile_size), obj->base.size); |
| 3139 | return -EINVAL22; |
| 3140 | } |
| 3141 | |
| 3142 | return 0; |
| 3143 | } |
| 3144 | |
| 3145 | static void |
| 3146 | intel_plane_remap_gtt(struct intel_plane_state *plane_state) |
| 3147 | { |
| 3148 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 3149 | to_i915(plane_state->uapi.plane->dev); |
| 3150 | struct drm_framebuffer *fb = plane_state->hw.fb; |
| 3151 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 3152 | struct intel_rotation_info *info = &plane_state->view.rotated; |
| 3153 | unsigned int rotation = plane_state->hw.rotation; |
| 3154 | int i, num_planes = fb->format->num_planes; |
| 3155 | unsigned int tile_size = intel_tile_size(dev_priv); |
| 3156 | unsigned int src_x, src_y; |
| 3157 | unsigned int src_w, src_h; |
| 3158 | u32 gtt_offset = 0; |
| 3159 | |
| 3160 | memset(&plane_state->view, 0, sizeof(plane_state->view))__builtin_memset((&plane_state->view), (0), (sizeof(plane_state ->view))); |
| 3161 | plane_state->view.type = drm_rotation_90_or_270(rotation) ? |
| 3162 | I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED; |
| 3163 | |
| 3164 | src_x = plane_state->uapi.src.x1 >> 16; |
| 3165 | src_y = plane_state->uapi.src.y1 >> 16; |
| 3166 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
| 3167 | src_h = drm_rect_height(&plane_state->uapi.src) >> 16; |
| 3168 | |
| 3169 | drm_WARN_ON(&dev_priv->drm, is_ccs_modifier(fb->modifier))({ int __ret = !!((is_ccs_modifier(fb->modifier))); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "is_ccs_modifier(fb->modifier)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 3170 | |
| 3171 | /* Make src coordinates relative to the viewport */ |
| 3172 | drm_rect_translate(&plane_state->uapi.src, |
| 3173 | -(src_x << 16), -(src_y << 16)); |
| 3174 | |
| 3175 | /* Rotate src coordinates to match rotated GTT view */ |
| 3176 | if (drm_rotation_90_or_270(rotation)) |
| 3177 | drm_rect_rotate(&plane_state->uapi.src, |
| 3178 | src_w << 16, src_h << 16, |
| 3179 | DRM_MODE_ROTATE_270(1<<3)); |
| 3180 | |
| 3181 | for (i = 0; i < num_planes; i++) { |
| 3182 | unsigned int hsub = i ? fb->format->hsub : 1; |
| 3183 | unsigned int vsub = i ? fb->format->vsub : 1; |
| 3184 | unsigned int cpp = fb->format->cpp[i]; |
| 3185 | unsigned int tile_width, tile_height; |
| 3186 | unsigned int width, height; |
| 3187 | unsigned int pitch_tiles; |
| 3188 | unsigned int x, y; |
| 3189 | u32 offset; |
| 3190 | |
| 3191 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
| 3192 | |
| 3193 | x = src_x / hsub; |
| 3194 | y = src_y / vsub; |
| 3195 | width = src_w / hsub; |
| 3196 | height = src_h / vsub; |
| 3197 | |
| 3198 | /* |
| 3199 | * First pixel of the src viewport from the |
| 3200 | * start of the normal gtt mapping. |
| 3201 | */ |
| 3202 | x += intel_fb->normal[i].x; |
| 3203 | y += intel_fb->normal[i].y; |
| 3204 | |
| 3205 | offset = intel_compute_aligned_offset(dev_priv, &x, &y, |
| 3206 | fb, i, fb->pitches[i], |
| 3207 | DRM_MODE_ROTATE_0(1<<0), tile_size); |
| 3208 | offset /= tile_size; |
| 3209 | |
| 3210 | drm_WARN_ON(&dev_priv->drm, i >= ARRAY_SIZE(info->plane))({ int __ret = !!((i >= (sizeof((info->plane)) / sizeof ((info->plane)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "i >= (sizeof((info->plane)) / sizeof((info->plane)[0]))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 3211 | info->plane[i].offset = offset; |
| 3212 | info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width * cpp)) |
| 3213 | tile_width * cpp)(((fb->pitches[i]) + ((tile_width * cpp) - 1)) / (tile_width * cpp)); |
| 3214 | info->plane[i].width = DIV_ROUND_UP(x + width, tile_width)(((x + width) + ((tile_width) - 1)) / (tile_width)); |
| 3215 | info->plane[i].height = DIV_ROUND_UP(y + height, tile_height)(((y + height) + ((tile_height) - 1)) / (tile_height)); |
| 3216 | |
| 3217 | if (drm_rotation_90_or_270(rotation)) { |
| 3218 | struct drm_rect r; |
| 3219 | |
| 3220 | /* rotate the x/y offsets to match the GTT view */ |
| 3221 | drm_rect_init(&r, x, y, width, height); |
| 3222 | drm_rect_rotate(&r, |
| 3223 | info->plane[i].width * tile_width, |
| 3224 | info->plane[i].height * tile_height, |
| 3225 | DRM_MODE_ROTATE_270(1<<3)); |
| 3226 | x = r.x1; |
| 3227 | y = r.y1; |
| 3228 | |
| 3229 | pitch_tiles = info->plane[i].height; |
| 3230 | plane_state->color_plane[i].stride = pitch_tiles * tile_height; |
| 3231 | |
| 3232 | /* rotate the tile dimensions to match the GTT view */ |
| 3233 | swap(tile_width, tile_height)do { __typeof(tile_width) __tmp = (tile_width); (tile_width) = (tile_height); (tile_height) = __tmp; } while(0); |
| 3234 | } else { |
| 3235 | pitch_tiles = info->plane[i].width; |
| 3236 | plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp; |
| 3237 | } |
| 3238 | |
| 3239 | /* |
| 3240 | * We only keep the x/y offsets, so push all of the |
| 3241 | * gtt offset into the x/y offsets. |
| 3242 | */ |
| 3243 | intel_adjust_tile_offset(&x, &y, |
| 3244 | tile_width, tile_height, |
| 3245 | tile_size, pitch_tiles, |
| 3246 | gtt_offset * tile_size, 0); |
| 3247 | |
| 3248 | gtt_offset += info->plane[i].width * info->plane[i].height; |
| 3249 | |
| 3250 | plane_state->color_plane[i].offset = 0; |
| 3251 | plane_state->color_plane[i].x = x; |
| 3252 | plane_state->color_plane[i].y = y; |
| 3253 | } |
| 3254 | } |
| 3255 | |
| 3256 | static int |
| 3257 | intel_plane_compute_gtt(struct intel_plane_state *plane_state) |
| 3258 | { |
| 3259 | const struct intel_framebuffer *fb = |
| 3260 | to_intel_framebuffer(plane_state->hw.fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (plane_state->hw.fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer , base) );}); |
| 3261 | unsigned int rotation = plane_state->hw.rotation; |
| 3262 | int i, num_planes; |
| 3263 | |
| 3264 | if (!fb) |
| 3265 | return 0; |
| 3266 | |
| 3267 | num_planes = fb->base.format->num_planes; |
| 3268 | |
| 3269 | if (intel_plane_needs_remap(plane_state)) { |
| 3270 | intel_plane_remap_gtt(plane_state); |
| 3271 | |
| 3272 | /* |
| 3273 | * Sometimes even remapping can't overcome |
| 3274 | * the stride limitations :( Can happen with |
| 3275 | * big plane sizes and suitably misaligned |
| 3276 | * offsets. |
| 3277 | */ |
| 3278 | return intel_plane_check_stride(plane_state); |
| 3279 | } |
| 3280 | |
| 3281 | intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation); |
| 3282 | |
| 3283 | for (i = 0; i < num_planes; i++) { |
| 3284 | plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation); |
| 3285 | plane_state->color_plane[i].offset = 0; |
| 3286 | |
| 3287 | if (drm_rotation_90_or_270(rotation)) { |
| 3288 | plane_state->color_plane[i].x = fb->rotated[i].x; |
| 3289 | plane_state->color_plane[i].y = fb->rotated[i].y; |
| 3290 | } else { |
| 3291 | plane_state->color_plane[i].x = fb->normal[i].x; |
| 3292 | plane_state->color_plane[i].y = fb->normal[i].y; |
| 3293 | } |
| 3294 | } |
| 3295 | |
| 3296 | /* Rotate src coordinates to match rotated GTT view */ |
| 3297 | if (drm_rotation_90_or_270(rotation)) |
| 3298 | drm_rect_rotate(&plane_state->uapi.src, |
| 3299 | fb->base.width << 16, fb->base.height << 16, |
| 3300 | DRM_MODE_ROTATE_270(1<<3)); |
| 3301 | |
| 3302 | return intel_plane_check_stride(plane_state); |
| 3303 | } |
| 3304 | |
| 3305 | static int i9xx_format_to_fourcc(int format) |
| 3306 | { |
| 3307 | switch (format) { |
| 3308 | case DISPPLANE_8BPP(0x2 << 26): |
| 3309 | return DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)); |
| 3310 | case DISPPLANE_BGRA555(0x3 << 26): |
| 3311 | return DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)); |
| 3312 | case DISPPLANE_BGRX555(0x4 << 26): |
| 3313 | return DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)); |
| 3314 | case DISPPLANE_BGRX565(0x5 << 26): |
| 3315 | return DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)); |
| 3316 | default: |
| 3317 | case DISPPLANE_BGRX888(0x6 << 26): |
| 3318 | return DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3319 | case DISPPLANE_RGBX888(0xe << 26): |
| 3320 | return DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3321 | case DISPPLANE_BGRA888(0x7 << 26): |
| 3322 | return DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3323 | case DISPPLANE_RGBA888(0xf << 26): |
| 3324 | return DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3325 | case DISPPLANE_BGRX101010(0xa << 26): |
| 3326 | return DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3327 | case DISPPLANE_RGBX101010(0x8 << 26): |
| 3328 | return DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3329 | case DISPPLANE_BGRA101010(0xb << 26): |
| 3330 | return DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3331 | case DISPPLANE_RGBA101010(0x9 << 26): |
| 3332 | return DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3333 | case DISPPLANE_RGBX161616(0xc << 26): |
| 3334 | return DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)); |
| 3335 | } |
| 3336 | } |
| 3337 | |
| 3338 | int skl_format_to_fourcc(int format, bool_Bool rgb_order, bool_Bool alpha) |
| 3339 | { |
| 3340 | switch (format) { |
| 3341 | case PLANE_CTL_FORMAT_RGB_565(14 << 24): |
| 3342 | return DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)); |
| 3343 | case PLANE_CTL_FORMAT_NV12(1 << 24): |
| 3344 | return DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)); |
| 3345 | case PLANE_CTL_FORMAT_XYUV(8 << 24): |
| 3346 | return DRM_FORMAT_XYUV8888((__u32)('X') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('V') << 24)); |
| 3347 | case PLANE_CTL_FORMAT_P010(3 << 24): |
| 3348 | return DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)); |
| 3349 | case PLANE_CTL_FORMAT_P012(5 << 24): |
| 3350 | return DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)); |
| 3351 | case PLANE_CTL_FORMAT_P016(7 << 24): |
| 3352 | return DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)); |
| 3353 | case PLANE_CTL_FORMAT_Y210(1 << 23): |
| 3354 | return DRM_FORMAT_Y210((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)); |
| 3355 | case PLANE_CTL_FORMAT_Y212(3 << 23): |
| 3356 | return DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)); |
| 3357 | case PLANE_CTL_FORMAT_Y216(5 << 23): |
| 3358 | return DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)); |
| 3359 | case PLANE_CTL_FORMAT_Y410(7 << 23): |
| 3360 | return DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3361 | case PLANE_CTL_FORMAT_Y412(9 << 23): |
| 3362 | return DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('6') << 24)); |
| 3363 | case PLANE_CTL_FORMAT_Y416(0xb << 23): |
| 3364 | return DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)); |
| 3365 | default: |
| 3366 | case PLANE_CTL_FORMAT_XRGB_8888(4 << 24): |
| 3367 | if (rgb_order) { |
| 3368 | if (alpha) |
| 3369 | return DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3370 | else |
| 3371 | return DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3372 | } else { |
| 3373 | if (alpha) |
| 3374 | return DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3375 | else |
| 3376 | return DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 3377 | } |
| 3378 | case PLANE_CTL_FORMAT_XRGB_2101010(2 << 24): |
| 3379 | if (rgb_order) { |
| 3380 | if (alpha) |
| 3381 | return DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3382 | else |
| 3383 | return DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3384 | } else { |
| 3385 | if (alpha) |
| 3386 | return DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3387 | else |
| 3388 | return DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)); |
| 3389 | } |
| 3390 | case PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24): |
| 3391 | if (rgb_order) { |
| 3392 | if (alpha) |
| 3393 | return DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)); |
| 3394 | else |
| 3395 | return DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)); |
| 3396 | } else { |
| 3397 | if (alpha) |
| 3398 | return DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)); |
| 3399 | else |
| 3400 | return DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)); |
| 3401 | } |
| 3402 | } |
| 3403 | } |
| 3404 | |
| 3405 | static struct i915_vma * |
| 3406 | initial_plane_vma(struct drm_i915_privateinteldrm_softc *i915, |
| 3407 | struct intel_initial_plane_config *plane_config) |
| 3408 | { |
| 3409 | struct drm_i915_gem_object *obj; |
| 3410 | struct i915_vma *vma; |
| 3411 | u32 base, size; |
| 3412 | |
| 3413 | if (plane_config->size == 0) |
| 3414 | return NULL((void *)0); |
| 3415 | |
| 3416 | base = round_down(plane_config->base,(((plane_config->base) / ((1ULL << (12)))) * ((1ULL << (12)))) |
| 3417 | I915_GTT_MIN_ALIGNMENT)(((plane_config->base) / ((1ULL << (12)))) * ((1ULL << (12)))); |
| 3418 | size = round_up(plane_config->base + plane_config->size,((((plane_config->base + plane_config->size) + (((1ULL << (12))) - 1)) / ((1ULL << (12)))) * ((1ULL << (12 )))) |
| 3419 | I915_GTT_MIN_ALIGNMENT)((((plane_config->base + plane_config->size) + (((1ULL << (12))) - 1)) / ((1ULL << (12)))) * ((1ULL << (12 )))); |
| 3420 | size -= base; |
| 3421 | |
| 3422 | /* |
| 3423 | * If the FB is too big, just don't use it since fbdev is not very |
| 3424 | * important and we should probably use that space with FBC or other |
| 3425 | * features. |
| 3426 | */ |
| 3427 | if (size * 2 > i915->stolen_usable_size) |
| 3428 | return NULL((void *)0); |
| 3429 | |
| 3430 | obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size); |
| 3431 | if (IS_ERR(obj)) |
| 3432 | return NULL((void *)0); |
| 3433 | |
| 3434 | /* |
| 3435 | * Mark it WT ahead of time to avoid changing the |
| 3436 | * cache_level during fbdev initialization. The |
| 3437 | * unbind there would get stuck waiting for rcu. |
| 3438 | */ |
| 3439 | i915_gem_object_set_cache_coherency(obj, HAS_WT(i915)((IS_PLATFORM(i915, INTEL_HASWELL) || IS_PLATFORM(i915, INTEL_BROADWELL )) && ((i915)->edram_size_mb)) ? |
| 3440 | I915_CACHE_WT : I915_CACHE_NONE); |
| 3441 | |
| 3442 | switch (plane_config->tiling) { |
| 3443 | case I915_TILING_NONE0: |
| 3444 | break; |
| 3445 | case I915_TILING_X1: |
| 3446 | case I915_TILING_Y2: |
| 3447 | obj->tiling_and_stride = |
| 3448 | plane_config->fb->base.pitches[0] | |
| 3449 | plane_config->tiling; |
| 3450 | break; |
| 3451 | default: |
| 3452 | MISSING_CASE(plane_config->tiling)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "plane_config->tiling", (long)(plane_config->tiling)) ; __builtin_expect(!!(__ret), 0); }); |
| 3453 | goto err_obj; |
| 3454 | } |
| 3455 | |
| 3456 | vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL((void *)0)); |
| 3457 | if (IS_ERR(vma)) |
| 3458 | goto err_obj; |
| 3459 | |
| 3460 | if (i915_ggtt_pin(vma, NULL((void *)0), 0, PIN_MAPPABLE(1ULL << (3)) | PIN_OFFSET_FIXED(1ULL << (7)) | base)) |
| 3461 | goto err_obj; |
| 3462 | |
| 3463 | if (i915_gem_object_is_tiled(obj) && |
| 3464 | !i915_vma_is_map_and_fenceable(vma)) |
| 3465 | goto err_obj; |
| 3466 | |
| 3467 | return vma; |
| 3468 | |
| 3469 | err_obj: |
| 3470 | i915_gem_object_put(obj); |
| 3471 | return NULL((void *)0); |
| 3472 | } |
| 3473 | |
| 3474 | static bool_Bool |
| 3475 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
| 3476 | struct intel_initial_plane_config *plane_config) |
| 3477 | { |
| 3478 | struct drm_device *dev = crtc->base.dev; |
| 3479 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 3480 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
| 3481 | struct drm_framebuffer *fb = &plane_config->fb->base; |
| 3482 | struct i915_vma *vma; |
| 3483 | |
| 3484 | switch (fb->modifier) { |
| 3485 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 3486 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 3487 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 3488 | break; |
| 3489 | default: |
| 3490 | drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unsupported modifier for initial FB: 0x%llx\n" , fb->modifier) |
| 3491 | "Unsupported modifier for initial FB: 0x%llx\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unsupported modifier for initial FB: 0x%llx\n" , fb->modifier) |
| 3492 | fb->modifier)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unsupported modifier for initial FB: 0x%llx\n" , fb->modifier); |
| 3493 | return false0; |
| 3494 | } |
| 3495 | |
| 3496 | vma = initial_plane_vma(dev_priv, plane_config); |
| 3497 | if (!vma) |
| 3498 | return false0; |
| 3499 | |
| 3500 | mode_cmd.pixel_format = fb->format->format; |
| 3501 | mode_cmd.width = fb->width; |
| 3502 | mode_cmd.height = fb->height; |
| 3503 | mode_cmd.pitches[0] = fb->pitches[0]; |
| 3504 | mode_cmd.modifier[0] = fb->modifier; |
| 3505 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS(1<<1); |
| 3506 | |
| 3507 | if (intel_framebuffer_init(to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}), |
| 3508 | vma->obj, &mode_cmd)) { |
| 3509 | drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "intel fb init failed\n" ); |
| 3510 | goto err_vma; |
| 3511 | } |
| 3512 | |
| 3513 | plane_config->vma = vma; |
| 3514 | return true1; |
| 3515 | |
| 3516 | err_vma: |
| 3517 | i915_vma_put(vma); |
| 3518 | return false0; |
| 3519 | } |
| 3520 | |
| 3521 | static void |
| 3522 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, |
| 3523 | struct intel_plane_state *plane_state, |
| 3524 | bool_Bool visible) |
| 3525 | { |
| 3526 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 3527 | |
| 3528 | plane_state->uapi.visible = visible; |
| 3529 | |
| 3530 | if (visible) |
| 3531 | crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base); |
| 3532 | else |
| 3533 | crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base); |
| 3534 | } |
| 3535 | |
| 3536 | static void fixup_active_planes(struct intel_crtc_state *crtc_state) |
| 3537 | { |
| 3538 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 3539 | struct drm_plane *plane; |
| 3540 | |
| 3541 | /* |
| 3542 | * Active_planes aliases if multiple "primary" or cursor planes |
| 3543 | * have been used on the same (or wrong) pipe. plane_mask uses |
| 3544 | * unique ids, hence we can use that to reconstruct active_planes. |
| 3545 | */ |
| 3546 | crtc_state->active_planes = 0; |
| 3547 | |
| 3548 | drm_for_each_plane_mask(plane, &dev_priv->drm,for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)-> head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(plane)), head) );}); &(plane )->head != (&(&dev_priv->drm)->mode_config.plane_list ); (plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)-> head ) *__mptr = ((plane)->head.next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(plane)), head ) );})) if (!((crtc_state->uapi.plane_mask) & drm_plane_mask (plane))) {} else |
| 3549 | crtc_state->uapi.plane_mask)for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)-> head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(plane)), head) );}); &(plane )->head != (&(&dev_priv->drm)->mode_config.plane_list ); (plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)-> head ) *__mptr = ((plane)->head.next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(plane)), head ) );})) if (!((crtc_state->uapi.plane_mask) & drm_plane_mask (plane))) {} else |
| 3550 | crtc_state->active_planes |= BIT(to_intel_plane(plane)->id)(1UL << (({ const __typeof( ((struct intel_plane *)0)-> base ) *__mptr = (plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );})->id)); |
| 3551 | } |
| 3552 | |
| 3553 | static void intel_plane_disable_noatomic(struct intel_crtc *crtc, |
| 3554 | struct intel_plane *plane) |
| 3555 | { |
| 3556 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 3557 | struct intel_crtc_state *crtc_state = |
| 3558 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 3559 | struct intel_plane_state *plane_state = |
| 3560 | to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane->base.state); (struct intel_plane_state * )( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 3561 | |
| 3562 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n" , plane->base.base.id, plane->base.name, crtc->base. base.id, crtc->base.name) |
| 3563 | "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n" , plane->base.base.id, plane->base.name, crtc->base. base.id, crtc->base.name) |
| 3564 | plane->base.base.id, plane->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n" , plane->base.base.id, plane->base.name, crtc->base. base.id, crtc->base.name) |
| 3565 | crtc->base.base.id, crtc->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n" , plane->base.base.id, plane->base.name, crtc->base. base.id, crtc->base.name); |
| 3566 | |
| 3567 | intel_set_plane_visible(crtc_state, plane_state, false0); |
| 3568 | fixup_active_planes(crtc_state); |
| 3569 | crtc_state->data_rate[plane->id] = 0; |
| 3570 | crtc_state->min_cdclk[plane->id] = 0; |
| 3571 | |
| 3572 | if (plane->id == PLANE_PRIMARY) |
| 3573 | hsw_disable_ips(crtc_state); |
| 3574 | |
| 3575 | /* |
| 3576 | * Vblank time updates from the shadow to live plane control register |
| 3577 | * are blocked if the memory self-refresh mode is active at that |
| 3578 | * moment. So to make sure the plane gets truly disabled, disable |
| 3579 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 3580 | * will be checked/applied by the HW only at the next frame start |
| 3581 | * event which is after the vblank start event, so we need to have a |
| 3582 | * wait-for-vblank between disabling the plane and the pipe. |
| 3583 | */ |
| 3584 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && |
| 3585 | intel_set_memory_cxsr(dev_priv, false0)) |
| 3586 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
| 3587 | |
| 3588 | /* |
| 3589 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 3590 | * So disable underrun reporting before all the planes get disabled. |
| 3591 | */ |
| 3592 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) && !crtc_state->active_planes) |
| 3593 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false0); |
| 3594 | |
| 3595 | intel_disable_plane(plane, crtc_state); |
| 3596 | } |
| 3597 | |
| 3598 | static struct intel_frontbuffer * |
| 3599 | to_intel_frontbuffer(struct drm_framebuffer *fb) |
| 3600 | { |
| 3601 | return fb ? to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );})->frontbuffer : NULL((void *)0); |
| 3602 | } |
| 3603 | |
| 3604 | static void |
| 3605 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
| 3606 | struct intel_initial_plane_config *plane_config) |
| 3607 | { |
| 3608 | struct drm_device *dev = intel_crtc->base.dev; |
| 3609 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 3610 | struct drm_crtc *c; |
| 3611 | struct drm_plane *primary = intel_crtc->base.primary; |
| 3612 | struct drm_plane_state *plane_state = primary->state; |
| 3613 | struct intel_plane *intel_plane = to_intel_plane(primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );}); |
| 3614 | struct intel_plane_state *intel_state = |
| 3615 | to_intel_plane_state(plane_state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}); |
| 3616 | struct drm_framebuffer *fb; |
| 3617 | struct i915_vma *vma; |
| 3618 | |
| 3619 | if (!plane_config->fb) |
| 3620 | return; |
| 3621 | |
| 3622 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
| 3623 | fb = &plane_config->fb->base; |
| 3624 | vma = plane_config->vma; |
| 3625 | goto valid_fb; |
| 3626 | } |
| 3627 | |
| 3628 | /* |
| 3629 | * Failed to alloc the obj, check to see if we should share |
| 3630 | * an fb with another CRTC instead |
| 3631 | */ |
| 3632 | for_each_crtc(dev, c)for (c = ({ const __typeof( ((__typeof(*c) *)0)->head ) *__mptr = ((&(dev)->mode_config.crtc_list)->next); (__typeof (*c) *)( (char *)__mptr - __builtin_offsetof(__typeof(*c), head ) );}); &c->head != (&(dev)->mode_config.crtc_list ); c = ({ const __typeof( ((__typeof(*c) *)0)->head ) *__mptr = (c->head.next); (__typeof(*c) *)( (char *)__mptr - __builtin_offsetof (__typeof(*c), head) );})) { |
| 3633 | struct intel_plane_state *state; |
| 3634 | |
| 3635 | if (c == &intel_crtc->base) |
| 3636 | continue; |
| 3637 | |
| 3638 | if (!to_intel_crtc(c)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (c); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );})->active) |
| 3639 | continue; |
| 3640 | |
| 3641 | state = to_intel_plane_state(c->primary->state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (c->primary->state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 3642 | if (!state->vma) |
| 3643 | continue; |
| 3644 | |
| 3645 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
| 3646 | fb = state->hw.fb; |
| 3647 | vma = state->vma; |
| 3648 | goto valid_fb; |
| 3649 | } |
| 3650 | } |
| 3651 | |
| 3652 | /* |
| 3653 | * We've failed to reconstruct the BIOS FB. Current display state |
| 3654 | * indicates that the primary plane is visible, but has a NULL FB, |
| 3655 | * which will lead to problems later if we don't fix it up. The |
| 3656 | * simplest solution is to just disable the primary plane now and |
| 3657 | * pretend the BIOS never had it enabled. |
| 3658 | */ |
| 3659 | intel_plane_disable_noatomic(intel_crtc, intel_plane); |
| 3660 | |
| 3661 | return; |
| 3662 | |
| 3663 | valid_fb: |
| 3664 | intel_state->hw.rotation = plane_config->rotation; |
| 3665 | intel_fill_fb_ggtt_view(&intel_state->view, fb, |
| 3666 | intel_state->hw.rotation); |
| 3667 | intel_state->color_plane[0].stride = |
| 3668 | intel_fb_pitch(fb, 0, intel_state->hw.rotation); |
| 3669 | |
| 3670 | __i915_vma_pin(vma); |
| 3671 | intel_state->vma = i915_vma_get(vma); |
| 3672 | if (intel_plane_uses_fence(intel_state) && i915_vma_pin_fence(vma) == 0) |
| 3673 | if (vma->fence) |
| 3674 | intel_state->flags |= PLANE_HAS_FENCE(1UL << (0)); |
| 3675 | |
| 3676 | plane_state->src_x = 0; |
| 3677 | plane_state->src_y = 0; |
| 3678 | plane_state->src_w = fb->width << 16; |
| 3679 | plane_state->src_h = fb->height << 16; |
| 3680 | |
| 3681 | plane_state->crtc_x = 0; |
| 3682 | plane_state->crtc_y = 0; |
| 3683 | plane_state->crtc_w = fb->width; |
| 3684 | plane_state->crtc_h = fb->height; |
| 3685 | |
| 3686 | intel_state->uapi.src = drm_plane_state_src(plane_state); |
| 3687 | intel_state->uapi.dst = drm_plane_state_dest(plane_state); |
| 3688 | |
| 3689 | if (plane_config->tiling) |
| 3690 | dev_priv->preserve_bios_swizzle = true1; |
| 3691 | |
| 3692 | plane_state->fb = fb; |
| 3693 | drm_framebuffer_get(fb); |
| 3694 | |
| 3695 | plane_state->crtc = &intel_crtc->base; |
| 3696 | intel_plane_copy_uapi_to_hw_state(intel_state, intel_state); |
| 3697 | |
| 3698 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
| 3699 | |
| 3700 | atomic_or(to_intel_plane(primary)->frontbuffer_bit,x86_atomic_setbits_u32(&to_intel_frontbuffer(fb)->bits , ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );})->frontbuffer_bit) |
| 3701 | &to_intel_frontbuffer(fb)->bits)x86_atomic_setbits_u32(&to_intel_frontbuffer(fb)->bits , ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );})->frontbuffer_bit); |
| 3702 | } |
| 3703 | |
| 3704 | static int skl_max_plane_width(const struct drm_framebuffer *fb, |
| 3705 | int color_plane, |
| 3706 | unsigned int rotation) |
| 3707 | { |
| 3708 | int cpp = fb->format->cpp[color_plane]; |
| 3709 | |
| 3710 | switch (fb->modifier) { |
| 3711 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 3712 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 3713 | /* |
| 3714 | * Validated limit is 4k, but has 5k should |
| 3715 | * work apart from the following features: |
| 3716 | * - Ytile (already limited to 4k) |
| 3717 | * - FP16 (already limited to 4k) |
| 3718 | * - render compression (already limited to 4k) |
| 3719 | * - KVMR sprite and cursor (don't care) |
| 3720 | * - horizontal panning (TODO verify this) |
| 3721 | * - pipe and plane scaling (TODO verify this) |
| 3722 | */ |
| 3723 | if (cpp == 8) |
| 3724 | return 4096; |
| 3725 | else |
| 3726 | return 5120; |
| 3727 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 3728 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 3729 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 3730 | /* FIXME AUX plane? */ |
| 3731 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 3732 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 3733 | if (cpp == 8) |
| 3734 | return 2048; |
| 3735 | else |
| 3736 | return 4096; |
| 3737 | default: |
| 3738 | MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->modifier", (long)(fb->modifier)); __builtin_expect (!!(__ret), 0); }); |
| 3739 | return 2048; |
| 3740 | } |
| 3741 | } |
| 3742 | |
| 3743 | static int glk_max_plane_width(const struct drm_framebuffer *fb, |
| 3744 | int color_plane, |
| 3745 | unsigned int rotation) |
| 3746 | { |
| 3747 | int cpp = fb->format->cpp[color_plane]; |
| 3748 | |
| 3749 | switch (fb->modifier) { |
| 3750 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 3751 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 3752 | if (cpp == 8) |
| 3753 | return 4096; |
| 3754 | else |
| 3755 | return 5120; |
| 3756 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 3757 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 3758 | /* FIXME AUX plane? */ |
| 3759 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 3760 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 3761 | if (cpp == 8) |
| 3762 | return 2048; |
| 3763 | else |
| 3764 | return 5120; |
| 3765 | default: |
| 3766 | MISSING_CASE(fb->modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->modifier", (long)(fb->modifier)); __builtin_expect (!!(__ret), 0); }); |
| 3767 | return 2048; |
| 3768 | } |
| 3769 | } |
| 3770 | |
| 3771 | static int icl_min_plane_width(const struct drm_framebuffer *fb) |
| 3772 | { |
| 3773 | /* Wa_14011264657, Wa_14011050563: gen11+ */ |
| 3774 | switch (fb->format->format) { |
| 3775 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 3776 | return 18; |
| 3777 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 3778 | return 10; |
| 3779 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 3780 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 3781 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 3782 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 3783 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 3784 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 3785 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 3786 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 3787 | case DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 3788 | case DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 3789 | case DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 3790 | return 6; |
| 3791 | case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 3792 | return 20; |
| 3793 | case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)): |
| 3794 | case DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 3795 | case DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 3796 | return 12; |
| 3797 | case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 3798 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 3799 | case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 3800 | case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 3801 | case DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('6') << 24)): |
| 3802 | case DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 3803 | return 4; |
| 3804 | default: |
| 3805 | return 1; |
| 3806 | } |
| 3807 | } |
| 3808 | |
| 3809 | static int icl_max_plane_width(const struct drm_framebuffer *fb, |
| 3810 | int color_plane, |
| 3811 | unsigned int rotation) |
| 3812 | { |
| 3813 | return 5120; |
| 3814 | } |
| 3815 | |
| 3816 | static int skl_max_plane_height(void) |
| 3817 | { |
| 3818 | return 4096; |
| 3819 | } |
| 3820 | |
| 3821 | static int icl_max_plane_height(void) |
| 3822 | { |
| 3823 | return 4320; |
| 3824 | } |
| 3825 | |
| 3826 | static bool_Bool |
| 3827 | skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, |
| 3828 | int main_x, int main_y, u32 main_offset, |
| 3829 | int ccs_plane) |
| 3830 | { |
| 3831 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 3832 | int aux_x = plane_state->color_plane[ccs_plane].x; |
| 3833 | int aux_y = plane_state->color_plane[ccs_plane].y; |
| 3834 | u32 aux_offset = plane_state->color_plane[ccs_plane].offset; |
| 3835 | u32 alignment = intel_surf_alignment(fb, ccs_plane); |
| 3836 | int hsub; |
| 3837 | int vsub; |
| 3838 | |
| 3839 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); |
| 3840 | while (aux_offset >= main_offset && aux_y <= main_y) { |
| 3841 | int x, y; |
| 3842 | |
| 3843 | if (aux_x == main_x && aux_y == main_y) |
| 3844 | break; |
| 3845 | |
| 3846 | if (aux_offset == 0) |
| 3847 | break; |
| 3848 | |
| 3849 | x = aux_x / hsub; |
| 3850 | y = aux_y / vsub; |
| 3851 | aux_offset = intel_plane_adjust_aligned_offset(&x, &y, |
| 3852 | plane_state, |
| 3853 | ccs_plane, |
| 3854 | aux_offset, |
| 3855 | aux_offset - |
| 3856 | alignment); |
| 3857 | aux_x = x * hsub + aux_x % hsub; |
| 3858 | aux_y = y * vsub + aux_y % vsub; |
| 3859 | } |
| 3860 | |
| 3861 | if (aux_x != main_x || aux_y != main_y) |
| 3862 | return false0; |
| 3863 | |
| 3864 | plane_state->color_plane[ccs_plane].offset = aux_offset; |
| 3865 | plane_state->color_plane[ccs_plane].x = aux_x; |
| 3866 | plane_state->color_plane[ccs_plane].y = aux_y; |
| 3867 | |
| 3868 | return true1; |
| 3869 | } |
| 3870 | |
| 3871 | unsigned int |
| 3872 | intel_plane_fence_y_offset(const struct intel_plane_state *plane_state) |
| 3873 | { |
| 3874 | int x = 0, y = 0; |
| 3875 | |
| 3876 | intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
| 3877 | plane_state->color_plane[0].offset, 0); |
| 3878 | |
| 3879 | return y; |
| 3880 | } |
| 3881 | |
| 3882 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
| 3883 | { |
| 3884 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane_state->uapi.plane->dev); |
| 3885 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 3886 | unsigned int rotation = plane_state->hw.rotation; |
| 3887 | int x = plane_state->uapi.src.x1 >> 16; |
| 3888 | int y = plane_state->uapi.src.y1 >> 16; |
| 3889 | int w = drm_rect_width(&plane_state->uapi.src) >> 16; |
| 3890 | int h = drm_rect_height(&plane_state->uapi.src) >> 16; |
| 3891 | int max_width, min_width, max_height; |
| 3892 | u32 alignment, offset; |
| 3893 | int aux_plane = intel_main_to_aux_plane(fb, 0); |
| 3894 | u32 aux_offset = plane_state->color_plane[aux_plane].offset; |
| 3895 | |
| 3896 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) { |
| 3897 | max_width = icl_max_plane_width(fb, 0, rotation); |
| 3898 | min_width = icl_min_plane_width(fb); |
| 3899 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) { |
| 3900 | max_width = glk_max_plane_width(fb, 0, rotation); |
| 3901 | min_width = 1; |
| 3902 | } else { |
| 3903 | max_width = skl_max_plane_width(fb, 0, rotation); |
| 3904 | min_width = 1; |
| 3905 | } |
| 3906 | |
| 3907 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 3908 | max_height = icl_max_plane_height(); |
| 3909 | else |
| 3910 | max_height = skl_max_plane_height(); |
| 3911 | |
| 3912 | if (w > max_width || w < min_width || h > max_height) { |
| 3913 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n" , w, h, min_width, max_width, max_height) |
| 3914 | "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n" , w, h, min_width, max_width, max_height) |
| 3915 | w, h, min_width, max_width, max_height)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n" , w, h, min_width, max_width, max_height); |
| 3916 | return -EINVAL22; |
| 3917 | } |
| 3918 | |
| 3919 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
| 3920 | offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0); |
| 3921 | alignment = intel_surf_alignment(fb, 0); |
| 3922 | if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment))({ int __ret = !!((alignment && !(((alignment) != 0) && (((alignment) - 1) & (alignment)) == 0))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "alignment && !(((alignment) != 0) && (((alignment) - 1) & (alignment)) == 0)" ")"); __builtin_expect(!!(__ret), 0); })) |
| 3923 | return -EINVAL22; |
| 3924 | |
| 3925 | /* |
| 3926 | * AUX surface offset is specified as the distance from the |
| 3927 | * main surface offset, and it must be non-negative. Make |
| 3928 | * sure that is what we will get. |
| 3929 | */ |
| 3930 | if (offset > aux_offset) |
| 3931 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
| 3932 | offset, aux_offset & ~(alignment - 1)); |
| 3933 | |
| 3934 | /* |
| 3935 | * When using an X-tiled surface, the plane blows up |
| 3936 | * if the x offset + width exceed the stride. |
| 3937 | * |
| 3938 | * TODO: linear and Y-tiled seem fine, Yf untested, |
| 3939 | */ |
| 3940 | if (fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) { |
| 3941 | int cpp = fb->format->cpp[0]; |
| 3942 | |
| 3943 | while ((x + w) * cpp > plane_state->color_plane[0].stride) { |
| 3944 | if (offset == 0) { |
| 3945 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to X-tiling\n" ) |
| 3946 | "Unable to find suitable display surface offset due to X-tiling\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to X-tiling\n" ); |
| 3947 | return -EINVAL22; |
| 3948 | } |
| 3949 | |
| 3950 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
| 3951 | offset, offset - alignment); |
| 3952 | } |
| 3953 | } |
| 3954 | |
| 3955 | /* |
| 3956 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure |
| 3957 | * they match with the main surface x/y offsets. |
| 3958 | */ |
| 3959 | if (is_ccs_modifier(fb->modifier)) { |
| 3960 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, |
| 3961 | offset, aux_plane)) { |
| 3962 | if (offset == 0) |
| 3963 | break; |
| 3964 | |
| 3965 | offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0, |
| 3966 | offset, offset - alignment); |
| 3967 | } |
| 3968 | |
| 3969 | if (x != plane_state->color_plane[aux_plane].x || |
| 3970 | y != plane_state->color_plane[aux_plane].y) { |
| 3971 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n" ) |
| 3972 | "Unable to find suitable display surface offset due to CCS\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n" ); |
| 3973 | return -EINVAL22; |
| 3974 | } |
| 3975 | } |
| 3976 | |
| 3977 | plane_state->color_plane[0].offset = offset; |
| 3978 | plane_state->color_plane[0].x = x; |
| 3979 | plane_state->color_plane[0].y = y; |
| 3980 | |
| 3981 | /* |
| 3982 | * Put the final coordinates back so that the src |
| 3983 | * coordinate checks will see the right values. |
| 3984 | */ |
| 3985 | drm_rect_translate_to(&plane_state->uapi.src, |
| 3986 | x << 16, y << 16); |
| 3987 | |
| 3988 | return 0; |
| 3989 | } |
| 3990 | |
| 3991 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
| 3992 | { |
| 3993 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane_state->uapi.plane->dev); |
| 3994 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 3995 | unsigned int rotation = plane_state->hw.rotation; |
| 3996 | int uv_plane = 1; |
| 3997 | int max_width = skl_max_plane_width(fb, uv_plane, rotation); |
| 3998 | int max_height = 4096; |
| 3999 | int x = plane_state->uapi.src.x1 >> 17; |
| 4000 | int y = plane_state->uapi.src.y1 >> 17; |
| 4001 | int w = drm_rect_width(&plane_state->uapi.src) >> 17; |
| 4002 | int h = drm_rect_height(&plane_state->uapi.src) >> 17; |
| 4003 | u32 offset; |
| 4004 | |
| 4005 | intel_add_fb_offsets(&x, &y, plane_state, uv_plane); |
| 4006 | offset = intel_plane_compute_aligned_offset(&x, &y, |
| 4007 | plane_state, uv_plane); |
| 4008 | |
| 4009 | /* FIXME not quite sure how/if these apply to the chroma plane */ |
| 4010 | if (w > max_width || h > max_height) { |
| 4011 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CbCr source size %dx%d too big (limit %dx%d)\n" , w, h, max_width, max_height) |
| 4012 | "CbCr source size %dx%d too big (limit %dx%d)\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CbCr source size %dx%d too big (limit %dx%d)\n" , w, h, max_width, max_height) |
| 4013 | w, h, max_width, max_height)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CbCr source size %dx%d too big (limit %dx%d)\n" , w, h, max_width, max_height); |
| 4014 | return -EINVAL22; |
| 4015 | } |
| 4016 | |
| 4017 | if (is_ccs_modifier(fb->modifier)) { |
| 4018 | int ccs_plane = main_to_ccs_plane(fb, uv_plane); |
| 4019 | int aux_offset = plane_state->color_plane[ccs_plane].offset; |
| 4020 | int alignment = intel_surf_alignment(fb, uv_plane); |
| 4021 | |
| 4022 | if (offset > aux_offset) |
| 4023 | offset = intel_plane_adjust_aligned_offset(&x, &y, |
| 4024 | plane_state, |
| 4025 | uv_plane, |
| 4026 | offset, |
| 4027 | aux_offset & ~(alignment - 1)); |
| 4028 | |
| 4029 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, |
| 4030 | offset, ccs_plane)) { |
| 4031 | if (offset == 0) |
| 4032 | break; |
| 4033 | |
| 4034 | offset = intel_plane_adjust_aligned_offset(&x, &y, |
| 4035 | plane_state, |
| 4036 | uv_plane, |
| 4037 | offset, offset - alignment); |
| 4038 | } |
| 4039 | |
| 4040 | if (x != plane_state->color_plane[ccs_plane].x || |
| 4041 | y != plane_state->color_plane[ccs_plane].y) { |
| 4042 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n" ) |
| 4043 | "Unable to find suitable display surface offset due to CCS\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Unable to find suitable display surface offset due to CCS\n" ); |
| 4044 | return -EINVAL22; |
| 4045 | } |
| 4046 | } |
| 4047 | |
| 4048 | plane_state->color_plane[uv_plane].offset = offset; |
| 4049 | plane_state->color_plane[uv_plane].x = x; |
| 4050 | plane_state->color_plane[uv_plane].y = y; |
| 4051 | |
| 4052 | return 0; |
| 4053 | } |
| 4054 | |
| 4055 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
| 4056 | { |
| 4057 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4058 | int src_x = plane_state->uapi.src.x1 >> 16; |
| 4059 | int src_y = plane_state->uapi.src.y1 >> 16; |
| 4060 | u32 offset; |
| 4061 | int ccs_plane; |
| 4062 | |
| 4063 | for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) { |
| 4064 | int main_hsub, main_vsub; |
| 4065 | int hsub, vsub; |
| 4066 | int x, y; |
| 4067 | |
| 4068 | if (!is_ccs_plane(fb, ccs_plane)) |
| 4069 | continue; |
| 4070 | |
| 4071 | intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, |
| 4072 | ccs_to_main_plane(fb, ccs_plane)); |
| 4073 | intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane); |
| 4074 | |
| 4075 | hsub *= main_hsub; |
| 4076 | vsub *= main_vsub; |
| 4077 | x = src_x / hsub; |
| 4078 | y = src_y / vsub; |
| 4079 | |
| 4080 | intel_add_fb_offsets(&x, &y, plane_state, ccs_plane); |
| 4081 | |
| 4082 | offset = intel_plane_compute_aligned_offset(&x, &y, |
| 4083 | plane_state, |
| 4084 | ccs_plane); |
| 4085 | |
| 4086 | plane_state->color_plane[ccs_plane].offset = offset; |
| 4087 | plane_state->color_plane[ccs_plane].x = (x * hsub + |
| 4088 | src_x % hsub) / |
| 4089 | main_hsub; |
| 4090 | plane_state->color_plane[ccs_plane].y = (y * vsub + |
| 4091 | src_y % vsub) / |
| 4092 | main_vsub; |
| 4093 | } |
| 4094 | |
| 4095 | return 0; |
| 4096 | } |
| 4097 | |
| 4098 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
| 4099 | { |
| 4100 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4101 | int ret, i; |
| 4102 | |
| 4103 | ret = intel_plane_compute_gtt(plane_state); |
| 4104 | if (ret) |
| 4105 | return ret; |
| 4106 | |
| 4107 | if (!plane_state->uapi.visible) |
| 4108 | return 0; |
| 4109 | |
| 4110 | /* |
| 4111 | * Handle the AUX surface first since the main surface setup depends on |
| 4112 | * it. |
| 4113 | */ |
| 4114 | if (is_ccs_modifier(fb->modifier)) { |
| 4115 | ret = skl_check_ccs_aux_surface(plane_state); |
| 4116 | if (ret) |
| 4117 | return ret; |
| 4118 | } |
| 4119 | |
| 4120 | if (intel_format_info_is_yuv_semiplanar(fb->format, |
| 4121 | fb->modifier)) { |
| 4122 | ret = skl_check_nv12_aux_surface(plane_state); |
| 4123 | if (ret) |
| 4124 | return ret; |
| 4125 | } |
| 4126 | |
| 4127 | for (i = fb->format->num_planes; i < ARRAY_SIZE(plane_state->color_plane)(sizeof((plane_state->color_plane)) / sizeof((plane_state-> color_plane)[0])); i++) { |
| 4128 | plane_state->color_plane[i].offset = ~0xfff; |
| 4129 | plane_state->color_plane[i].x = 0; |
| 4130 | plane_state->color_plane[i].y = 0; |
| 4131 | } |
| 4132 | |
| 4133 | ret = skl_check_main_surface(plane_state); |
| 4134 | if (ret) |
| 4135 | return ret; |
| 4136 | |
| 4137 | return 0; |
| 4138 | } |
| 4139 | |
| 4140 | static void i9xx_plane_ratio(const struct intel_crtc_state *crtc_state, |
| 4141 | const struct intel_plane_state *plane_state, |
| 4142 | unsigned int *num, unsigned int *den) |
| 4143 | { |
| 4144 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4145 | unsigned int cpp = fb->format->cpp[0]; |
| 4146 | |
| 4147 | /* |
| 4148 | * g4x bspec says 64bpp pixel rate can't exceed 80% |
| 4149 | * of cdclk when the sprite plane is enabled on the |
| 4150 | * same pipe. ilk/snb bspec says 64bpp pixel rate is |
| 4151 | * never allowed to exceed 80% of cdclk. Let's just go |
| 4152 | * with the ilk/snb limit always. |
| 4153 | */ |
| 4154 | if (cpp == 8) { |
| 4155 | *num = 10; |
| 4156 | *den = 8; |
| 4157 | } else { |
| 4158 | *num = 1; |
| 4159 | *den = 1; |
| 4160 | } |
| 4161 | } |
| 4162 | |
| 4163 | static int i9xx_plane_min_cdclk(const struct intel_crtc_state *crtc_state, |
| 4164 | const struct intel_plane_state *plane_state) |
| 4165 | { |
| 4166 | unsigned int pixel_rate; |
| 4167 | unsigned int num, den; |
| 4168 | |
| 4169 | /* |
| 4170 | * Note that crtc_state->pixel_rate accounts for both |
| 4171 | * horizontal and vertical panel fitter downscaling factors. |
| 4172 | * Pre-HSW bspec tells us to only consider the horizontal |
| 4173 | * downscaling factor here. We ignore that and just consider |
| 4174 | * both for simplicity. |
| 4175 | */ |
| 4176 | pixel_rate = crtc_state->pixel_rate; |
| 4177 | |
| 4178 | i9xx_plane_ratio(crtc_state, plane_state, &num, &den); |
| 4179 | |
| 4180 | /* two pixels per clock with double wide pipe */ |
| 4181 | if (crtc_state->double_wide) |
| 4182 | den *= 2; |
| 4183 | |
| 4184 | return DIV_ROUND_UP(pixel_rate * num, den)(((pixel_rate * num) + ((den) - 1)) / (den)); |
| 4185 | } |
| 4186 | |
| 4187 | unsigned int |
| 4188 | i9xx_plane_max_stride(struct intel_plane *plane, |
| 4189 | u32 pixel_format, u64 modifier, |
| 4190 | unsigned int rotation) |
| 4191 | { |
| 4192 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 4193 | |
| 4194 | if (!HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) { |
| 4195 | return 32*1024; |
| 4196 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 4197 | if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
| 4198 | return 16*1024; |
| 4199 | else |
| 4200 | return 32*1024; |
| 4201 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 3) { |
| 4202 | if (modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
| 4203 | return 8*1024; |
| 4204 | else |
| 4205 | return 16*1024; |
| 4206 | } else { |
| 4207 | if (plane->i9xx_plane == PLANE_C) |
| 4208 | return 4*1024; |
| 4209 | else |
| 4210 | return 8*1024; |
| 4211 | } |
| 4212 | } |
| 4213 | |
| 4214 | static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
| 4215 | { |
| 4216 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 4217 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 4218 | u32 dspcntr = 0; |
| 4219 | |
| 4220 | if (crtc_state->gamma_enable) |
| 4221 | dspcntr |= DISPPLANE_GAMMA_ENABLE(1 << 30); |
| 4222 | |
| 4223 | if (crtc_state->csc_enable) |
| 4224 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE(1 << 24); |
| 4225 | |
| 4226 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5) |
| 4227 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe)((crtc->pipe) << 24); |
| 4228 | |
| 4229 | return dspcntr; |
| 4230 | } |
| 4231 | |
| 4232 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
| 4233 | const struct intel_plane_state *plane_state) |
| 4234 | { |
| 4235 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 4236 | to_i915(plane_state->uapi.plane->dev); |
| 4237 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4238 | unsigned int rotation = plane_state->hw.rotation; |
| 4239 | u32 dspcntr; |
| 4240 | |
| 4241 | dspcntr = DISPLAY_PLANE_ENABLE(1 << 31); |
| 4242 | |
| 4243 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5)) || |
| 4244 | IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6)) || IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
| 4245 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE(1 << 14); |
| 4246 | |
| 4247 | switch (fb->format->format) { |
| 4248 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 4249 | dspcntr |= DISPPLANE_8BPP(0x2 << 26); |
| 4250 | break; |
| 4251 | case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 4252 | dspcntr |= DISPPLANE_BGRX555(0x4 << 26); |
| 4253 | break; |
| 4254 | case DRM_FORMAT_ARGB1555((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 4255 | dspcntr |= DISPPLANE_BGRA555(0x3 << 26); |
| 4256 | break; |
| 4257 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 4258 | dspcntr |= DISPPLANE_BGRX565(0x5 << 26); |
| 4259 | break; |
| 4260 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4261 | dspcntr |= DISPPLANE_BGRX888(0x6 << 26); |
| 4262 | break; |
| 4263 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4264 | dspcntr |= DISPPLANE_RGBX888(0xe << 26); |
| 4265 | break; |
| 4266 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4267 | dspcntr |= DISPPLANE_BGRA888(0x7 << 26); |
| 4268 | break; |
| 4269 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4270 | dspcntr |= DISPPLANE_RGBA888(0xf << 26); |
| 4271 | break; |
| 4272 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4273 | dspcntr |= DISPPLANE_BGRX101010(0xa << 26); |
| 4274 | break; |
| 4275 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4276 | dspcntr |= DISPPLANE_RGBX101010(0x8 << 26); |
| 4277 | break; |
| 4278 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4279 | dspcntr |= DISPPLANE_BGRA101010(0xb << 26); |
| 4280 | break; |
| 4281 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4282 | dspcntr |= DISPPLANE_RGBA101010(0x9 << 26); |
| 4283 | break; |
| 4284 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4285 | dspcntr |= DISPPLANE_RGBX161616(0xc << 26); |
| 4286 | break; |
| 4287 | default: |
| 4288 | MISSING_CASE(fb->format->format)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb->format->format", (long)(fb->format->format )); __builtin_expect(!!(__ret), 0); }); |
| 4289 | return 0; |
| 4290 | } |
| 4291 | |
| 4292 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4 && |
| 4293 | fb->modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL ))) |
| 4294 | dspcntr |= DISPPLANE_TILED(1 << 10); |
| 4295 | |
| 4296 | if (rotation & DRM_MODE_ROTATE_180(1<<2)) |
| 4297 | dspcntr |= DISPPLANE_ROTATE_180(1 << 15); |
| 4298 | |
| 4299 | if (rotation & DRM_MODE_REFLECT_X(1<<4)) |
| 4300 | dspcntr |= DISPPLANE_MIRROR(1 << 8); |
| 4301 | |
| 4302 | return dspcntr; |
| 4303 | } |
| 4304 | |
| 4305 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
| 4306 | { |
| 4307 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 4308 | to_i915(plane_state->uapi.plane->dev); |
| 4309 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4310 | int src_x, src_y, src_w; |
| 4311 | u32 offset; |
| 4312 | int ret; |
| 4313 | |
| 4314 | ret = intel_plane_compute_gtt(plane_state); |
| 4315 | if (ret) |
| 4316 | return ret; |
| 4317 | |
| 4318 | if (!plane_state->uapi.visible) |
| 4319 | return 0; |
| 4320 | |
| 4321 | src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
| 4322 | src_x = plane_state->uapi.src.x1 >> 16; |
| 4323 | src_y = plane_state->uapi.src.y1 >> 16; |
| 4324 | |
| 4325 | /* Undocumented hardware limit on i965/g4x/vlv/chv */ |
| 4326 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && fb->format->cpp[0] == 8 && src_w > 2048) |
| 4327 | return -EINVAL22; |
| 4328 | |
| 4329 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
| 4330 | |
| 4331 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 4332 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, |
| 4333 | plane_state, 0); |
| 4334 | else |
| 4335 | offset = 0; |
| 4336 | |
| 4337 | /* |
| 4338 | * Put the final coordinates back so that the src |
| 4339 | * coordinate checks will see the right values. |
| 4340 | */ |
| 4341 | drm_rect_translate_to(&plane_state->uapi.src, |
| 4342 | src_x << 16, src_y << 16); |
| 4343 | |
| 4344 | /* HSW/BDW do this automagically in hardware */ |
| 4345 | if (!IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && !IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 4346 | unsigned int rotation = plane_state->hw.rotation; |
| 4347 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
| 4348 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; |
| 4349 | |
| 4350 | if (rotation & DRM_MODE_ROTATE_180(1<<2)) { |
| 4351 | src_x += src_w - 1; |
| 4352 | src_y += src_h - 1; |
| 4353 | } else if (rotation & DRM_MODE_REFLECT_X(1<<4)) { |
| 4354 | src_x += src_w - 1; |
| 4355 | } |
| 4356 | } |
| 4357 | |
| 4358 | plane_state->color_plane[0].offset = offset; |
| 4359 | plane_state->color_plane[0].x = src_x; |
| 4360 | plane_state->color_plane[0].y = src_y; |
| 4361 | |
| 4362 | return 0; |
| 4363 | } |
| 4364 | |
| 4365 | static bool_Bool i9xx_plane_has_windowing(struct intel_plane *plane) |
| 4366 | { |
| 4367 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 4368 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
| 4369 | |
| 4370 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 4371 | return i9xx_plane == PLANE_B; |
| 4372 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 4373 | return false0; |
| 4374 | else if (IS_GEN(dev_priv, 4)(0 + (&(dev_priv)->__info)->gen == (4))) |
| 4375 | return i9xx_plane == PLANE_C; |
| 4376 | else |
| 4377 | return i9xx_plane == PLANE_B || |
| 4378 | i9xx_plane == PLANE_C; |
| 4379 | } |
| 4380 | |
| 4381 | static int |
| 4382 | i9xx_plane_check(struct intel_crtc_state *crtc_state, |
| 4383 | struct intel_plane_state *plane_state) |
| 4384 | { |
| 4385 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 4386 | int ret; |
| 4387 | |
| 4388 | ret = chv_plane_check_rotation(plane_state); |
| 4389 | if (ret) |
| 4390 | return ret; |
| 4391 | |
| 4392 | ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, |
| 4393 | &crtc_state->uapi, |
| 4394 | DRM_PLANE_HELPER_NO_SCALING(1<<16), |
| 4395 | DRM_PLANE_HELPER_NO_SCALING(1<<16), |
| 4396 | i9xx_plane_has_windowing(plane), |
| 4397 | true1); |
| 4398 | if (ret) |
| 4399 | return ret; |
| 4400 | |
| 4401 | ret = i9xx_check_plane_surface(plane_state); |
| 4402 | if (ret) |
| 4403 | return ret; |
| 4404 | |
| 4405 | if (!plane_state->uapi.visible) |
| 4406 | return 0; |
| 4407 | |
| 4408 | ret = intel_plane_check_src_coordinates(plane_state); |
| 4409 | if (ret) |
| 4410 | return ret; |
| 4411 | |
| 4412 | plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state); |
| 4413 | |
| 4414 | return 0; |
| 4415 | } |
| 4416 | |
| 4417 | static void i9xx_update_plane(struct intel_plane *plane, |
| 4418 | const struct intel_crtc_state *crtc_state, |
| 4419 | const struct intel_plane_state *plane_state) |
| 4420 | { |
| 4421 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 4422 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
| 4423 | u32 linear_offset; |
| 4424 | int x = plane_state->color_plane[0].x; |
| 4425 | int y = plane_state->color_plane[0].y; |
| 4426 | int crtc_x = plane_state->uapi.dst.x1; |
| 4427 | int crtc_y = plane_state->uapi.dst.y1; |
| 4428 | int crtc_w = drm_rect_width(&plane_state->uapi.dst); |
| 4429 | int crtc_h = drm_rect_height(&plane_state->uapi.dst); |
| 4430 | unsigned long irqflags; |
| 4431 | u32 dspaddr_offset; |
| 4432 | u32 dspcntr; |
| 4433 | |
| 4434 | dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); |
| 4435 | |
| 4436 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
| 4437 | |
| 4438 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 4439 | dspaddr_offset = plane_state->color_plane[0].offset; |
| 4440 | else |
| 4441 | dspaddr_offset = linear_offset; |
| 4442 | |
| 4443 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); } while (0); |
| 4444 | |
| 4445 | intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70188) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4446 | plane_state->color_plane[0].stride); |
| 4447 | |
| 4448 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) { |
| 4449 | /* |
| 4450 | * PLANE_A doesn't actually have a full window |
| 4451 | * generator but let's assume we still need to |
| 4452 | * program whatever is there. |
| 4453 | */ |
| 4454 | intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7018C) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4455 | (crtc_y << 16) | crtc_x); |
| 4456 | intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70190) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4457 | ((crtc_h - 1) << 16) | (crtc_w - 1)); |
| 4458 | } else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && i9xx_plane == PLANE_B) { |
| 4459 | intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60a08) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 4460 | (crtc_y << 16) | crtc_x); |
| 4461 | intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60a0c) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 4462 | ((crtc_h - 1) << 16) | (crtc_w - 1)); |
| 4463 | intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(i9xx_plane)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60a10) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), 0); |
| 4464 | } |
| 4465 | |
| 4466 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 4467 | intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4468 | (y << 16) | x); |
| 4469 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 4470 | intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4471 | linear_offset); |
| 4472 | intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4473 | (y << 16) | x); |
| 4474 | } |
| 4475 | |
| 4476 | /* |
| 4477 | * The control register self-arms if the plane was previously |
| 4478 | * disabled. Try to make the plane enable atomic by writing |
| 4479 | * the control register just before the surface register. |
| 4480 | */ |
| 4481 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) }), dspcntr); |
| 4482 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 4483 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4484 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); |
| 4485 | else |
| 4486 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 4487 | intel_plane_ggtt_offset(plane_state) + dspaddr_offset); |
| 4488 | |
| 4489 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock ); } while (0); |
| 4490 | } |
| 4491 | |
| 4492 | static void i9xx_disable_plane(struct intel_plane *plane, |
| 4493 | const struct intel_crtc_state *crtc_state) |
| 4494 | { |
| 4495 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 4496 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
| 4497 | unsigned long irqflags; |
| 4498 | u32 dspcntr; |
| 4499 | |
| 4500 | /* |
| 4501 | * DSPCNTR pipe gamma enable on g4x+ and pipe csc |
| 4502 | * enable on ilk+ affect the pipe bottom color as |
| 4503 | * well, so we must configure them even if the plane |
| 4504 | * is disabled. |
| 4505 | * |
| 4506 | * On pre-g4x there is no way to gamma correct the |
| 4507 | * pipe bottom color but we'll keep on doing this |
| 4508 | * anyway so that the crtc state readout works correctly. |
| 4509 | */ |
| 4510 | dspcntr = i9xx_plane_ctl_crtc(crtc_state); |
| 4511 | |
| 4512 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); } while (0); |
| 4513 | |
| 4514 | intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) }), dspcntr); |
| 4515 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 4516 | intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset )) }), 0); |
| 4517 | else |
| 4518 | intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset )) }), 0); |
| 4519 | |
| 4520 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock ); } while (0); |
| 4521 | } |
| 4522 | |
| 4523 | static bool_Bool i9xx_plane_get_hw_state(struct intel_plane *plane, |
| 4524 | enum pipe *pipe) |
| 4525 | { |
| 4526 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 4527 | enum intel_display_power_domain power_domain; |
| 4528 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
| 4529 | intel_wakeref_t wakeref; |
| 4530 | bool_Bool ret; |
| 4531 | u32 val; |
| 4532 | |
| 4533 | /* |
| 4534 | * Not 100% correct for planes that can move between pipes, |
| 4535 | * but that's only the case for gen2-4 which don't have any |
| 4536 | * display power wells. |
| 4537 | */ |
| 4538 | power_domain = POWER_DOMAIN_PIPE(plane->pipe)((plane->pipe) + POWER_DOMAIN_PIPE_A); |
| 4539 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 4540 | if (!wakeref) |
| 4541 | return false0; |
| 4542 | |
| 4543 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 4544 | |
| 4545 | ret = val & DISPLAY_PLANE_ENABLE(1 << 31); |
| 4546 | |
| 4547 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) |
| 4548 | *pipe = plane->pipe; |
| 4549 | else |
| 4550 | *pipe = (val & DISPPLANE_SEL_PIPE_MASK(3 << 24)) >> |
| 4551 | DISPPLANE_SEL_PIPE_SHIFT24; |
| 4552 | |
| 4553 | intel_display_power_put(dev_priv, power_domain, wakeref); |
| 4554 | |
| 4555 | return ret; |
| 4556 | } |
| 4557 | |
| 4558 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
| 4559 | { |
| 4560 | struct drm_device *dev = intel_crtc->base.dev; |
| 4561 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 4562 | unsigned long irqflags; |
| 4563 | |
| 4564 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); } while (0); |
| 4565 | |
| 4566 | intel_de_write_fw(dev_priv, SKL_PS_CTRL(intel_crtc->pipe, id)((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280) - (0x68180)))) + (intel_crtc->pipe) * ((((0x68980) + (id) * ((0x68A80) - (0x68980)))) - (((0x68180) + (id) * ((0x68280 ) - (0x68180))))))) }), 0); |
| 4567 | intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(intel_crtc->pipe, id)((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270) - (0x68170)))) + (intel_crtc->pipe) * ((((0x68970) + (id) * ((0x68A70) - (0x68970)))) - (((0x68170) + (id) * ((0x68270 ) - (0x68170))))))) }), 0); |
| 4568 | intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(intel_crtc->pipe, id)((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274) - (0x68174)))) + (intel_crtc->pipe) * ((((0x68974) + (id) * ((0x68A74) - (0x68974)))) - (((0x68174) + (id) * ((0x68274 ) - (0x68174))))))) }), 0); |
| 4569 | |
| 4570 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock ); } while (0); |
| 4571 | } |
| 4572 | |
| 4573 | /* |
| 4574 | * This function detaches (aka. unbinds) unused scalers in hardware |
| 4575 | */ |
| 4576 | static void skl_detach_scalers(const struct intel_crtc_state *crtc_state) |
| 4577 | { |
| 4578 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 4579 | const struct intel_crtc_scaler_state *scaler_state = |
| 4580 | &crtc_state->scaler_state; |
| 4581 | int i; |
| 4582 | |
| 4583 | /* loop through and disable scalers that aren't in use */ |
| 4584 | for (i = 0; i < intel_crtc->num_scalers; i++) { |
| 4585 | if (!scaler_state->scalers[i].in_use) |
| 4586 | skl_detach_scaler(intel_crtc, i); |
| 4587 | } |
| 4588 | } |
| 4589 | |
| 4590 | static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb, |
| 4591 | int color_plane, unsigned int rotation) |
| 4592 | { |
| 4593 | /* |
| 4594 | * The stride is either expressed as a multiple of 64 bytes chunks for |
| 4595 | * linear buffers or in number of tiles for tiled buffers. |
| 4596 | */ |
| 4597 | if (is_surface_linear(fb, color_plane)) |
| 4598 | return 64; |
| 4599 | else if (drm_rotation_90_or_270(rotation)) |
| 4600 | return intel_tile_height(fb, color_plane); |
| 4601 | else |
| 4602 | return intel_tile_width_bytes(fb, color_plane); |
| 4603 | } |
| 4604 | |
| 4605 | u32 skl_plane_stride(const struct intel_plane_state *plane_state, |
| 4606 | int color_plane) |
| 4607 | { |
| 4608 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4609 | unsigned int rotation = plane_state->hw.rotation; |
| 4610 | u32 stride = plane_state->color_plane[color_plane].stride; |
| 4611 | |
| 4612 | if (color_plane >= fb->format->num_planes) |
| 4613 | return 0; |
| 4614 | |
| 4615 | return stride / skl_plane_stride_mult(fb, color_plane, rotation); |
| 4616 | } |
| 4617 | |
| 4618 | static u32 skl_plane_ctl_format(u32 pixel_format) |
| 4619 | { |
| 4620 | switch (pixel_format) { |
| 4621 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 4622 | return PLANE_CTL_FORMAT_INDEXED(12 << 24); |
| 4623 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 4624 | return PLANE_CTL_FORMAT_RGB_565(14 << 24); |
| 4625 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4626 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4627 | return PLANE_CTL_FORMAT_XRGB_8888(4 << 24) | PLANE_CTL_ORDER_RGBX(1 << 20); |
| 4628 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4629 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 4630 | return PLANE_CTL_FORMAT_XRGB_8888(4 << 24); |
| 4631 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4632 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4633 | return PLANE_CTL_FORMAT_XRGB_2101010(2 << 24) | PLANE_CTL_ORDER_RGBX(1 << 20); |
| 4634 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4635 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4636 | return PLANE_CTL_FORMAT_XRGB_2101010(2 << 24); |
| 4637 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4638 | case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4639 | return PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24) | PLANE_CTL_ORDER_RGBX(1 << 20); |
| 4640 | case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4641 | case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 4642 | return PLANE_CTL_FORMAT_XRGB_16161616F(6 << 24); |
| 4643 | case DRM_FORMAT_XYUV8888((__u32)('X') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('V') << 24)): |
| 4644 | return PLANE_CTL_FORMAT_XYUV(8 << 24); |
| 4645 | case DRM_FORMAT_YUYV((__u32)('Y') | ((__u32)('U') << 8) | ((__u32)('Y') << 16) | ((__u32)('V') << 24)): |
| 4646 | return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_YUYV(0 << 16); |
| 4647 | case DRM_FORMAT_YVYU((__u32)('Y') | ((__u32)('V') << 8) | ((__u32)('Y') << 16) | ((__u32)('U') << 24)): |
| 4648 | return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_YVYU(2 << 16); |
| 4649 | case DRM_FORMAT_UYVY((__u32)('U') | ((__u32)('Y') << 8) | ((__u32)('V') << 16) | ((__u32)('Y') << 24)): |
| 4650 | return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_UYVY(1 << 16); |
| 4651 | case DRM_FORMAT_VYUY((__u32)('V') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('Y') << 24)): |
| 4652 | return PLANE_CTL_FORMAT_YUV422(0 << 24) | PLANE_CTL_YUV422_VYUY(3 << 16); |
| 4653 | case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 4654 | return PLANE_CTL_FORMAT_NV12(1 << 24); |
| 4655 | case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)): |
| 4656 | return PLANE_CTL_FORMAT_P010(3 << 24); |
| 4657 | case DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 4658 | return PLANE_CTL_FORMAT_P012(5 << 24); |
| 4659 | case DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 4660 | return PLANE_CTL_FORMAT_P016(7 << 24); |
| 4661 | case DRM_FORMAT_Y210((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)): |
| 4662 | return PLANE_CTL_FORMAT_Y210(1 << 23); |
| 4663 | case DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 4664 | return PLANE_CTL_FORMAT_Y212(3 << 23); |
| 4665 | case DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 4666 | return PLANE_CTL_FORMAT_Y216(5 << 23); |
| 4667 | case DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 4668 | return PLANE_CTL_FORMAT_Y410(7 << 23); |
| 4669 | case DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('6') << 24)): |
| 4670 | return PLANE_CTL_FORMAT_Y412(9 << 23); |
| 4671 | case DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 4672 | return PLANE_CTL_FORMAT_Y416(0xb << 23); |
| 4673 | default: |
| 4674 | MISSING_CASE(pixel_format)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "pixel_format", (long)(pixel_format)); __builtin_expect(!!( __ret), 0); }); |
| 4675 | } |
| 4676 | |
| 4677 | return 0; |
| 4678 | } |
| 4679 | |
| 4680 | static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state) |
| 4681 | { |
| 4682 | if (!plane_state->hw.fb->format->has_alpha) |
| 4683 | return PLANE_CTL_ALPHA_DISABLE(0 << 4); |
| 4684 | |
| 4685 | switch (plane_state->hw.pixel_blend_mode) { |
| 4686 | case DRM_MODE_BLEND_PIXEL_NONE2: |
| 4687 | return PLANE_CTL_ALPHA_DISABLE(0 << 4); |
| 4688 | case DRM_MODE_BLEND_PREMULTI0: |
| 4689 | return PLANE_CTL_ALPHA_SW_PREMULTIPLY(2 << 4); |
| 4690 | case DRM_MODE_BLEND_COVERAGE1: |
| 4691 | return PLANE_CTL_ALPHA_HW_PREMULTIPLY(3 << 4); |
| 4692 | default: |
| 4693 | MISSING_CASE(plane_state->hw.pixel_blend_mode)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "plane_state->hw.pixel_blend_mode", (long)(plane_state-> hw.pixel_blend_mode)); __builtin_expect(!!(__ret), 0); }); |
| 4694 | return PLANE_CTL_ALPHA_DISABLE(0 << 4); |
| 4695 | } |
| 4696 | } |
| 4697 | |
| 4698 | static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state) |
| 4699 | { |
| 4700 | if (!plane_state->hw.fb->format->has_alpha) |
| 4701 | return PLANE_COLOR_ALPHA_DISABLE(0 << 4); |
| 4702 | |
| 4703 | switch (plane_state->hw.pixel_blend_mode) { |
| 4704 | case DRM_MODE_BLEND_PIXEL_NONE2: |
| 4705 | return PLANE_COLOR_ALPHA_DISABLE(0 << 4); |
| 4706 | case DRM_MODE_BLEND_PREMULTI0: |
| 4707 | return PLANE_COLOR_ALPHA_SW_PREMULTIPLY(2 << 4); |
| 4708 | case DRM_MODE_BLEND_COVERAGE1: |
| 4709 | return PLANE_COLOR_ALPHA_HW_PREMULTIPLY(3 << 4); |
| 4710 | default: |
| 4711 | MISSING_CASE(plane_state->hw.pixel_blend_mode)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "plane_state->hw.pixel_blend_mode", (long)(plane_state-> hw.pixel_blend_mode)); __builtin_expect(!!(__ret), 0); }); |
| 4712 | return PLANE_COLOR_ALPHA_DISABLE(0 << 4); |
| 4713 | } |
| 4714 | } |
| 4715 | |
| 4716 | static u32 skl_plane_ctl_tiling(u64 fb_modifier) |
| 4717 | { |
| 4718 | switch (fb_modifier) { |
| 4719 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 4720 | break; |
| 4721 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 4722 | return PLANE_CTL_TILED_X(1 << 10); |
| 4723 | case I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )): |
| 4724 | return PLANE_CTL_TILED_Y(4 << 10); |
| 4725 | case I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )): |
| 4726 | return PLANE_CTL_TILED_Y(4 << 10) | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15); |
| 4727 | case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )): |
| 4728 | return PLANE_CTL_TILED_Y(4 << 10) | |
| 4729 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15) | |
| 4730 | PLANE_CTL_CLEAR_COLOR_DISABLE(1 << 13); |
| 4731 | case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )): |
| 4732 | return PLANE_CTL_TILED_Y(4 << 10) | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE(1 << 4); |
| 4733 | case I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )): |
| 4734 | return PLANE_CTL_TILED_YF(5 << 10); |
| 4735 | case I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )): |
| 4736 | return PLANE_CTL_TILED_YF(5 << 10) | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15); |
| 4737 | default: |
| 4738 | MISSING_CASE(fb_modifier)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "fb_modifier", (long)(fb_modifier)); __builtin_expect(!!(__ret ), 0); }); |
| 4739 | } |
| 4740 | |
| 4741 | return 0; |
| 4742 | } |
| 4743 | |
| 4744 | static u32 skl_plane_ctl_rotate(unsigned int rotate) |
| 4745 | { |
| 4746 | switch (rotate) { |
| 4747 | case DRM_MODE_ROTATE_0(1<<0): |
| 4748 | break; |
| 4749 | /* |
| 4750 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
| 4751 | * while i915 HW rotation is clockwise, thats why this swapping. |
| 4752 | */ |
| 4753 | case DRM_MODE_ROTATE_90(1<<1): |
| 4754 | return PLANE_CTL_ROTATE_2700x3; |
| 4755 | case DRM_MODE_ROTATE_180(1<<2): |
| 4756 | return PLANE_CTL_ROTATE_1800x2; |
| 4757 | case DRM_MODE_ROTATE_270(1<<3): |
| 4758 | return PLANE_CTL_ROTATE_900x1; |
| 4759 | default: |
| 4760 | MISSING_CASE(rotate)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "rotate", (long)(rotate)); __builtin_expect(!!(__ret), 0); } ); |
| 4761 | } |
| 4762 | |
| 4763 | return 0; |
| 4764 | } |
| 4765 | |
| 4766 | static u32 cnl_plane_ctl_flip(unsigned int reflect) |
| 4767 | { |
| 4768 | switch (reflect) { |
| 4769 | case 0: |
| 4770 | break; |
| 4771 | case DRM_MODE_REFLECT_X(1<<4): |
| 4772 | return PLANE_CTL_FLIP_HORIZONTAL(1 << 8); |
| 4773 | case DRM_MODE_REFLECT_Y(1<<5): |
| 4774 | default: |
| 4775 | MISSING_CASE(reflect)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "reflect", (long)(reflect)); __builtin_expect(!!(__ret), 0) ; }); |
| 4776 | } |
| 4777 | |
| 4778 | return 0; |
| 4779 | } |
| 4780 | |
| 4781 | u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state) |
| 4782 | { |
| 4783 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 4784 | u32 plane_ctl = 0; |
| 4785 | |
| 4786 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) |
| 4787 | return plane_ctl; |
| 4788 | |
| 4789 | if (crtc_state->gamma_enable) |
| 4790 | plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE(1 << 30); |
| 4791 | |
| 4792 | if (crtc_state->csc_enable) |
| 4793 | plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE(1 << 23); |
| 4794 | |
| 4795 | return plane_ctl; |
| 4796 | } |
| 4797 | |
| 4798 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
| 4799 | const struct intel_plane_state *plane_state) |
| 4800 | { |
| 4801 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 4802 | to_i915(plane_state->uapi.plane->dev); |
| 4803 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4804 | unsigned int rotation = plane_state->hw.rotation; |
| 4805 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
| 4806 | u32 plane_ctl; |
| 4807 | |
| 4808 | plane_ctl = PLANE_CTL_ENABLE(1 << 31); |
| 4809 | |
| 4810 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 10 && !IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) { |
| 4811 | plane_ctl |= skl_plane_ctl_alpha(plane_state); |
| 4812 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE(1 << 13); |
| 4813 | |
| 4814 | if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) |
| 4815 | plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709(1 << 18); |
| 4816 | |
| 4817 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
| 4818 | plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE(1 << 28); |
| 4819 | } |
| 4820 | |
| 4821 | plane_ctl |= skl_plane_ctl_format(fb->format->format); |
| 4822 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); |
| 4823 | plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK( (1<<0) | (1<<1) | (1<<2) | (1<<3))); |
| 4824 | |
| 4825 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10) |
| 4826 | plane_ctl |= cnl_plane_ctl_flip(rotation & |
| 4827 | DRM_MODE_REFLECT_MASK( (1<<4) | (1<<5))); |
| 4828 | |
| 4829 | if (key->flags & I915_SET_COLORKEY_DESTINATION(1<<1)) |
| 4830 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION(2 << 21); |
| 4831 | else if (key->flags & I915_SET_COLORKEY_SOURCE(1<<2)) |
| 4832 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE(1 << 21); |
| 4833 | |
| 4834 | return plane_ctl; |
| 4835 | } |
| 4836 | |
| 4837 | u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state) |
| 4838 | { |
| 4839 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 4840 | u32 plane_color_ctl = 0; |
| 4841 | |
| 4842 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 4843 | return plane_color_ctl; |
| 4844 | |
| 4845 | if (crtc_state->gamma_enable) |
| 4846 | plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE(1 << 30); |
| 4847 | |
| 4848 | if (crtc_state->csc_enable) |
| 4849 | plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE(1 << 23); |
| 4850 | |
| 4851 | return plane_color_ctl; |
| 4852 | } |
| 4853 | |
| 4854 | u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, |
| 4855 | const struct intel_plane_state *plane_state) |
| 4856 | { |
| 4857 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 4858 | to_i915(plane_state->uapi.plane->dev); |
| 4859 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 4860 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 4861 | u32 plane_color_ctl = 0; |
| 4862 | |
| 4863 | plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE(1 << 13); |
| 4864 | plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state); |
| 4865 | |
| 4866 | if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) { |
| 4867 | switch (plane_state->hw.color_encoding) { |
| 4868 | case DRM_COLOR_YCBCR_BT709: |
| 4869 | plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709(2 << 17); |
| 4870 | break; |
| 4871 | case DRM_COLOR_YCBCR_BT2020: |
| 4872 | plane_color_ctl |= |
| 4873 | PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020(3 << 17); |
| 4874 | break; |
| 4875 | default: |
| 4876 | plane_color_ctl |= |
| 4877 | PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601(1 << 17); |
| 4878 | } |
| 4879 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
| 4880 | plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE(1 << 28); |
| 4881 | } else if (fb->format->is_yuv) { |
| 4882 | plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE(1 << 20); |
| 4883 | if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) |
| 4884 | plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE(1 << 28); |
| 4885 | } |
| 4886 | |
| 4887 | return plane_color_ctl; |
| 4888 | } |
| 4889 | |
| 4890 | static int |
| 4891 | __intel_display_resume(struct drm_device *dev, |
| 4892 | struct drm_atomic_state *state, |
| 4893 | struct drm_modeset_acquire_ctx *ctx) |
| 4894 | { |
| 4895 | struct drm_crtc_state *crtc_state; |
| 4896 | struct drm_crtc *crtc; |
| 4897 | int i, ret; |
| 4898 | |
| 4899 | intel_modeset_setup_hw_state(dev, ctx); |
| 4900 | intel_vga_redisable(to_i915(dev)); |
| 4901 | |
| 4902 | if (!state) |
| 4903 | return 0; |
| 4904 | |
| 4905 | /* |
| 4906 | * We've duplicated the state, pointers to the old state are invalid. |
| 4907 | * |
| 4908 | * Don't attempt to use the old state until we commit the duplicated state. |
| 4909 | */ |
| 4910 | for_each_new_crtc_in_state(state, crtc, crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc ; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = ( state)->crtcs[i].ptr, (void)(crtc) , (crtc_state) = (state )->crtcs[i].new_state, (void)(crtc_state) , 1))) {} else { |
| 4911 | /* |
| 4912 | * Force recalculation even if we restore |
| 4913 | * current state. With fast modeset this may not result |
| 4914 | * in a modeset when the state is compatible. |
| 4915 | */ |
| 4916 | crtc_state->mode_changed = true1; |
| 4917 | } |
| 4918 | |
| 4919 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
| 4920 | if (!HAS_GMCH(to_i915(dev))((&(to_i915(dev))->__info)->display.has_gmch)) |
| 4921 | to_intel_atomic_state(state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state, base) );})->skip_intermediate_wm = true1; |
| 4922 | |
| 4923 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
| 4924 | |
| 4925 | drm_WARN_ON(dev, ret == -EDEADLK)({ int __ret = !!((ret == -11)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "ret == -11" ")"); __builtin_expect(!!(__ret), 0); }); |
| 4926 | return ret; |
| 4927 | } |
| 4928 | |
| 4929 | static bool_Bool gpu_reset_clobbers_display(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 4930 | { |
| 4931 | return (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->gpu_reset_clobbers_display && |
| 4932 | intel_has_gpu_reset(&dev_priv->gt)); |
| 4933 | } |
| 4934 | |
| 4935 | void intel_prepare_reset(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 4936 | { |
| 4937 | struct drm_device *dev = &dev_priv->drm; |
| 4938 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; |
| 4939 | struct drm_atomic_state *state; |
| 4940 | int ret; |
| 4941 | |
| 4942 | /* reset doesn't touch the display */ |
| 4943 | if (!dev_priv->params.force_reset_modeset_test && |
| 4944 | !gpu_reset_clobbers_display(dev_priv)) |
| 4945 | return; |
| 4946 | |
| 4947 | /* We have a modeset vs reset deadlock, defensively unbreak it. */ |
| 4948 | set_bit(I915_RESET_MODESET1, &dev_priv->gt.reset.flags); |
| 4949 | smp_mb__after_atomic()do { } while (0); |
| 4950 | wake_up_bit(&dev_priv->gt.reset.flags, I915_RESET_MODESET1); |
| 4951 | |
| 4952 | if (atomic_read(&dev_priv->gpu_error.pending_fb_pin)({ typeof(*(&dev_priv->gpu_error.pending_fb_pin)) __tmp = *(volatile typeof(*(&dev_priv->gpu_error.pending_fb_pin )) *)&(*(&dev_priv->gpu_error.pending_fb_pin)); membar_datadep_consumer (); __tmp; })) { |
| 4953 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Modeset potentially stuck, unbreaking through wedging\n" ) |
| 4954 | "Modeset potentially stuck, unbreaking through wedging\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Modeset potentially stuck, unbreaking through wedging\n" ); |
| 4955 | intel_gt_set_wedged(&dev_priv->gt); |
| 4956 | } |
| 4957 | |
| 4958 | /* |
| 4959 | * Need mode_config.mutex so that we don't |
| 4960 | * trample ongoing ->detect() and whatnot. |
| 4961 | */ |
| 4962 | mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex); |
| 4963 | drm_modeset_acquire_init(ctx, 0); |
| 4964 | while (1) { |
| 4965 | ret = drm_modeset_lock_all_ctx(dev, ctx); |
| 4966 | if (ret != -EDEADLK11) |
| 4967 | break; |
| 4968 | |
| 4969 | drm_modeset_backoff(ctx); |
| 4970 | } |
| 4971 | /* |
| 4972 | * Disabling the crtcs gracefully seems nicer. Also the |
| 4973 | * g33 docs say we should at least disable all the planes. |
| 4974 | */ |
| 4975 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
| 4976 | if (IS_ERR(state)) { |
| 4977 | ret = PTR_ERR(state); |
| 4978 | drm_err(&dev_priv->drm, "Duplicating state failed with %i\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Duplicating state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
| 4979 | ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Duplicating state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 4980 | return; |
| 4981 | } |
| 4982 | |
| 4983 | ret = drm_atomic_helper_disable_all(dev, ctx); |
| 4984 | if (ret) { |
| 4985 | drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspending crtc's failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
| 4986 | ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspending crtc's failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 4987 | drm_atomic_state_put(state); |
| 4988 | return; |
| 4989 | } |
| 4990 | |
| 4991 | dev_priv->modeset_restore_state = state; |
| 4992 | state->acquire_ctx = ctx; |
| 4993 | } |
| 4994 | |
| 4995 | void intel_finish_reset(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 4996 | { |
| 4997 | struct drm_device *dev = &dev_priv->drm; |
| 4998 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; |
| 4999 | struct drm_atomic_state *state; |
| 5000 | int ret; |
| 5001 | |
| 5002 | /* reset doesn't touch the display */ |
| 5003 | if (!test_bit(I915_RESET_MODESET1, &dev_priv->gt.reset.flags)) |
| 5004 | return; |
| 5005 | |
| 5006 | state = fetch_and_zero(&dev_priv->modeset_restore_state)({ typeof(*&dev_priv->modeset_restore_state) __T = *(& dev_priv->modeset_restore_state); *(&dev_priv->modeset_restore_state ) = (typeof(*&dev_priv->modeset_restore_state))0; __T; }); |
| 5007 | if (!state) |
| 5008 | goto unlock; |
| 5009 | |
| 5010 | /* reset doesn't touch the display */ |
| 5011 | if (!gpu_reset_clobbers_display(dev_priv)) { |
| 5012 | /* for testing only restore the display */ |
| 5013 | ret = __intel_display_resume(dev, state, ctx); |
| 5014 | if (ret) |
| 5015 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
| 5016 | "Restoring old state failed with %i\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 5017 | } else { |
| 5018 | /* |
| 5019 | * The display has been reset as well, |
| 5020 | * so need a full re-initialization. |
| 5021 | */ |
| 5022 | intel_pps_unlock_regs_wa(dev_priv); |
| 5023 | intel_modeset_init_hw(dev_priv); |
| 5024 | intel_init_clock_gating(dev_priv); |
| 5025 | |
| 5026 | spin_lock_irq(&dev_priv->irq_lock)mtx_enter(&dev_priv->irq_lock); |
| 5027 | if (dev_priv->display.hpd_irq_setup) |
| 5028 | dev_priv->display.hpd_irq_setup(dev_priv); |
| 5029 | spin_unlock_irq(&dev_priv->irq_lock)mtx_leave(&dev_priv->irq_lock); |
| 5030 | |
| 5031 | ret = __intel_display_resume(dev, state, ctx); |
| 5032 | if (ret) |
| 5033 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
| 5034 | "Restoring old state failed with %i\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 5035 | |
| 5036 | intel_hpd_init(dev_priv); |
| 5037 | } |
| 5038 | |
| 5039 | drm_atomic_state_put(state); |
| 5040 | unlock: |
| 5041 | drm_modeset_drop_locks(ctx); |
| 5042 | drm_modeset_acquire_fini(ctx); |
| 5043 | mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex); |
| 5044 | |
| 5045 | clear_bit_unlock(I915_RESET_MODESET1, &dev_priv->gt.reset.flags); |
| 5046 | } |
| 5047 | |
| 5048 | static void icl_set_pipe_chicken(struct intel_crtc *crtc) |
| 5049 | { |
| 5050 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 5051 | enum pipe pipe = crtc->pipe; |
| 5052 | u32 tmp; |
| 5053 | |
| 5054 | tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038) - (0x70038)))) })); |
| 5055 | |
| 5056 | /* |
| 5057 | * Display WA #1153: icl |
| 5058 | * enable hardware to bypass the alpha math |
| 5059 | * and rounding for per-pixel values 00 and 0xff |
| 5060 | */ |
| 5061 | tmp |= PER_PIXEL_ALPHA_BYPASS_EN(1 << 7); |
| 5062 | /* |
| 5063 | * Display WA # 1605353570: icl |
| 5064 | * Set the pixel rounding bit to 1 for allowing |
| 5065 | * passthrough of Frame buffer pixels unmodified |
| 5066 | * across pipe |
| 5067 | */ |
| 5068 | tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU(1 << 15); |
| 5069 | intel_de_write(dev_priv, PIPE_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0x70038) + (pipe) * ((0x71038) - (0x70038)))) }), tmp); |
| 5070 | } |
| 5071 | |
| 5072 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
| 5073 | { |
| 5074 | struct drm_device *dev = crtc->base.dev; |
| 5075 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 5076 | enum pipe pipe = crtc->pipe; |
| 5077 | i915_reg_t reg; |
| 5078 | u32 temp; |
| 5079 | |
| 5080 | /* enable normal train */ |
| 5081 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5082 | temp = intel_de_read(dev_priv, reg); |
| 5083 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) { |
| 5084 | temp &= ~FDI_LINK_TRAIN_NONE_IVB(3 << 8); |
| 5085 | temp |= FDI_LINK_TRAIN_NONE_IVB(3 << 8) | FDI_TX_ENHANCE_FRAME_ENABLE(1 << 18); |
| 5086 | } else { |
| 5087 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5088 | temp |= FDI_LINK_TRAIN_NONE(3 << 28) | FDI_TX_ENHANCE_FRAME_ENABLE(1 << 18); |
| 5089 | } |
| 5090 | intel_de_write(dev_priv, reg, temp); |
| 5091 | |
| 5092 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5093 | temp = intel_de_read(dev_priv, reg); |
| 5094 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 5095 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8); |
| 5096 | temp |= FDI_LINK_TRAIN_NORMAL_CPT(3 << 8); |
| 5097 | } else { |
| 5098 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5099 | temp |= FDI_LINK_TRAIN_NONE(3 << 28); |
| 5100 | } |
| 5101 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE(1 << 6)); |
| 5102 | |
| 5103 | /* wait one idle pattern time */ |
| 5104 | intel_de_posting_read(dev_priv, reg); |
| 5105 | udelay(1000); |
| 5106 | |
| 5107 | /* IVB wants error correction enabled */ |
| 5108 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
| 5109 | intel_de_write(dev_priv, reg, |
| 5110 | intel_de_read(dev_priv, reg) | FDI_FS_ERRC_ENABLE(1 << 27) | FDI_FE_ERRC_ENABLE(1 << 26)); |
| 5111 | } |
| 5112 | |
| 5113 | /* The FDI link training functions for ILK/Ibexpeak. */ |
| 5114 | static void ilk_fdi_link_train(struct intel_crtc *crtc, |
| 5115 | const struct intel_crtc_state *crtc_state) |
| 5116 | { |
| 5117 | struct drm_device *dev = crtc->base.dev; |
| 5118 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 5119 | enum pipe pipe = crtc->pipe; |
| 5120 | i915_reg_t reg; |
| 5121 | u32 temp, tries; |
| 5122 | |
| 5123 | /* FDI needs bits from pipe first */ |
| 5124 | assert_pipe_enabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 1); |
| 5125 | |
| 5126 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 5127 | for train result */ |
| 5128 | reg = FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018) - (0xf0018)))) }); |
| 5129 | temp = intel_de_read(dev_priv, reg); |
| 5130 | temp &= ~FDI_RX_SYMBOL_LOCK(1 << 9); |
| 5131 | temp &= ~FDI_RX_BIT_LOCK(1 << 8); |
| 5132 | intel_de_write(dev_priv, reg, temp); |
| 5133 | intel_de_read(dev_priv, reg); |
| 5134 | udelay(150); |
| 5135 | |
| 5136 | /* enable CPU FDI TX and PCH FDI RX */ |
| 5137 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5138 | temp = intel_de_read(dev_priv, reg); |
| 5139 | temp &= ~FDI_DP_PORT_WIDTH_MASK(7 << 19); |
| 5140 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes)(((crtc_state->fdi_lanes) - 1) << 19); |
| 5141 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5142 | temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28); |
| 5143 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE(1 << 31)); |
| 5144 | |
| 5145 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5146 | temp = intel_de_read(dev_priv, reg); |
| 5147 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5148 | temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28); |
| 5149 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE(1 << 31)); |
| 5150 | |
| 5151 | intel_de_posting_read(dev_priv, reg); |
| 5152 | udelay(150); |
| 5153 | |
| 5154 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
| 5155 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010) - (0xc200c)))) }), |
| 5156 | FDI_RX_PHASE_SYNC_POINTER_OVR(1 << 1)); |
| 5157 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010) - (0xc200c)))) }), |
| 5158 | FDI_RX_PHASE_SYNC_POINTER_OVR(1 << 1) | FDI_RX_PHASE_SYNC_POINTER_EN(1 << 0)); |
| 5159 | |
| 5160 | reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014) - (0xf0014)))) }); |
| 5161 | for (tries = 0; tries < 5; tries++) { |
| 5162 | temp = intel_de_read(dev_priv, reg); |
| 5163 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n" , temp); |
| 5164 | |
| 5165 | if ((temp & FDI_RX_BIT_LOCK(1 << 8))) { |
| 5166 | drm_dbg_kms(&dev_priv->drm, "FDI train 1 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done.\n" ); |
| 5167 | intel_de_write(dev_priv, reg, temp | FDI_RX_BIT_LOCK(1 << 8)); |
| 5168 | break; |
| 5169 | } |
| 5170 | } |
| 5171 | if (tries == 5) |
| 5172 | drm_err(&dev_priv->drm, "FDI train 1 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 1 fail!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 5173 | |
| 5174 | /* Train 2 */ |
| 5175 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5176 | temp = intel_de_read(dev_priv, reg); |
| 5177 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5178 | temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28); |
| 5179 | intel_de_write(dev_priv, reg, temp); |
| 5180 | |
| 5181 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5182 | temp = intel_de_read(dev_priv, reg); |
| 5183 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5184 | temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28); |
| 5185 | intel_de_write(dev_priv, reg, temp); |
| 5186 | |
| 5187 | intel_de_posting_read(dev_priv, reg); |
| 5188 | udelay(150); |
| 5189 | |
| 5190 | reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014) - (0xf0014)))) }); |
| 5191 | for (tries = 0; tries < 5; tries++) { |
| 5192 | temp = intel_de_read(dev_priv, reg); |
| 5193 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n" , temp); |
| 5194 | |
| 5195 | if (temp & FDI_RX_SYMBOL_LOCK(1 << 9)) { |
| 5196 | intel_de_write(dev_priv, reg, |
| 5197 | temp | FDI_RX_SYMBOL_LOCK(1 << 9)); |
| 5198 | drm_dbg_kms(&dev_priv->drm, "FDI train 2 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done.\n" ); |
| 5199 | break; |
| 5200 | } |
| 5201 | } |
| 5202 | if (tries == 5) |
| 5203 | drm_err(&dev_priv->drm, "FDI train 2 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 2 fail!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 5204 | |
| 5205 | drm_dbg_kms(&dev_priv->drm, "FDI train done\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train done\n" ); |
| 5206 | |
| 5207 | } |
| 5208 | |
| 5209 | static const int snb_b_fdi_train_param[] = { |
| 5210 | FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22), |
| 5211 | FDI_LINK_TRAIN_400MV_6DB_SNB_B(0x3a << 22), |
| 5212 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B(0x39 << 22), |
| 5213 | FDI_LINK_TRAIN_800MV_0DB_SNB_B(0x38 << 22), |
| 5214 | }; |
| 5215 | |
| 5216 | /* The FDI link training functions for SNB/Cougarpoint. */ |
| 5217 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
| 5218 | const struct intel_crtc_state *crtc_state) |
| 5219 | { |
| 5220 | struct drm_device *dev = crtc->base.dev; |
| 5221 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 5222 | enum pipe pipe = crtc->pipe; |
| 5223 | i915_reg_t reg; |
| 5224 | u32 temp, i, retry; |
| 5225 | |
| 5226 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 5227 | for train result */ |
| 5228 | reg = FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018) - (0xf0018)))) }); |
| 5229 | temp = intel_de_read(dev_priv, reg); |
| 5230 | temp &= ~FDI_RX_SYMBOL_LOCK(1 << 9); |
| 5231 | temp &= ~FDI_RX_BIT_LOCK(1 << 8); |
| 5232 | intel_de_write(dev_priv, reg, temp); |
| 5233 | |
| 5234 | intel_de_posting_read(dev_priv, reg); |
| 5235 | udelay(150); |
| 5236 | |
| 5237 | /* enable CPU FDI TX and PCH FDI RX */ |
| 5238 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5239 | temp = intel_de_read(dev_priv, reg); |
| 5240 | temp &= ~FDI_DP_PORT_WIDTH_MASK(7 << 19); |
| 5241 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes)(((crtc_state->fdi_lanes) - 1) << 19); |
| 5242 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5243 | temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28); |
| 5244 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22); |
| 5245 | /* SNB-B */ |
| 5246 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22); |
| 5247 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE(1 << 31)); |
| 5248 | |
| 5249 | intel_de_write(dev_priv, FDI_RX_MISC(pipe)((const i915_reg_t){ .reg = (((0xf0010) + (pipe) * ((0xf1010) - (0xf0010)))) }), |
| 5250 | FDI_RX_TP1_TO_TP2_48(2 << 20) | FDI_RX_FDI_DELAY_90(0x90 << 0)); |
| 5251 | |
| 5252 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5253 | temp = intel_de_read(dev_priv, reg); |
| 5254 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 5255 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8); |
| 5256 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT(0 << 8); |
| 5257 | } else { |
| 5258 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5259 | temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28); |
| 5260 | } |
| 5261 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE(1 << 31)); |
| 5262 | |
| 5263 | intel_de_posting_read(dev_priv, reg); |
| 5264 | udelay(150); |
| 5265 | |
| 5266 | for (i = 0; i < 4; i++) { |
| 5267 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5268 | temp = intel_de_read(dev_priv, reg); |
| 5269 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22); |
| 5270 | temp |= snb_b_fdi_train_param[i]; |
| 5271 | intel_de_write(dev_priv, reg, temp); |
| 5272 | |
| 5273 | intel_de_posting_read(dev_priv, reg); |
| 5274 | udelay(500); |
| 5275 | |
| 5276 | for (retry = 0; retry < 5; retry++) { |
| 5277 | reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014) - (0xf0014)))) }); |
| 5278 | temp = intel_de_read(dev_priv, reg); |
| 5279 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n" , temp); |
| 5280 | if (temp & FDI_RX_BIT_LOCK(1 << 8)) { |
| 5281 | intel_de_write(dev_priv, reg, |
| 5282 | temp | FDI_RX_BIT_LOCK(1 << 8)); |
| 5283 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done.\n" ) |
| 5284 | "FDI train 1 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done.\n" ); |
| 5285 | break; |
| 5286 | } |
| 5287 | udelay(50); |
| 5288 | } |
| 5289 | if (retry < 5) |
| 5290 | break; |
| 5291 | } |
| 5292 | if (i == 4) |
| 5293 | drm_err(&dev_priv->drm, "FDI train 1 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 1 fail!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 5294 | |
| 5295 | /* Train 2 */ |
| 5296 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5297 | temp = intel_de_read(dev_priv, reg); |
| 5298 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5299 | temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28); |
| 5300 | if (IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6))) { |
| 5301 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22); |
| 5302 | /* SNB-B */ |
| 5303 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B(0x0 << 22); |
| 5304 | } |
| 5305 | intel_de_write(dev_priv, reg, temp); |
| 5306 | |
| 5307 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5308 | temp = intel_de_read(dev_priv, reg); |
| 5309 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 5310 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8); |
| 5311 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT(1 << 8); |
| 5312 | } else { |
| 5313 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5314 | temp |= FDI_LINK_TRAIN_PATTERN_2(1 << 28); |
| 5315 | } |
| 5316 | intel_de_write(dev_priv, reg, temp); |
| 5317 | |
| 5318 | intel_de_posting_read(dev_priv, reg); |
| 5319 | udelay(150); |
| 5320 | |
| 5321 | for (i = 0; i < 4; i++) { |
| 5322 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5323 | temp = intel_de_read(dev_priv, reg); |
| 5324 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22); |
| 5325 | temp |= snb_b_fdi_train_param[i]; |
| 5326 | intel_de_write(dev_priv, reg, temp); |
| 5327 | |
| 5328 | intel_de_posting_read(dev_priv, reg); |
| 5329 | udelay(500); |
| 5330 | |
| 5331 | for (retry = 0; retry < 5; retry++) { |
| 5332 | reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014) - (0xf0014)))) }); |
| 5333 | temp = intel_de_read(dev_priv, reg); |
| 5334 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n" , temp); |
| 5335 | if (temp & FDI_RX_SYMBOL_LOCK(1 << 9)) { |
| 5336 | intel_de_write(dev_priv, reg, |
| 5337 | temp | FDI_RX_SYMBOL_LOCK(1 << 9)); |
| 5338 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done.\n" ) |
| 5339 | "FDI train 2 done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done.\n" ); |
| 5340 | break; |
| 5341 | } |
| 5342 | udelay(50); |
| 5343 | } |
| 5344 | if (retry < 5) |
| 5345 | break; |
| 5346 | } |
| 5347 | if (i == 4) |
| 5348 | drm_err(&dev_priv->drm, "FDI train 2 fail!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI train 2 fail!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 5349 | |
| 5350 | drm_dbg_kms(&dev_priv->drm, "FDI train done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train done.\n" ); |
| 5351 | } |
| 5352 | |
| 5353 | /* Manual link training for Ivy Bridge A0 parts */ |
| 5354 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
| 5355 | const struct intel_crtc_state *crtc_state) |
| 5356 | { |
| 5357 | struct drm_device *dev = crtc->base.dev; |
| 5358 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 5359 | enum pipe pipe = crtc->pipe; |
| 5360 | i915_reg_t reg; |
| 5361 | u32 temp, i, j; |
| 5362 | |
| 5363 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
| 5364 | for train result */ |
| 5365 | reg = FDI_RX_IMR(pipe)((const i915_reg_t){ .reg = (((0xf0018) + (pipe) * ((0xf1018) - (0xf0018)))) }); |
| 5366 | temp = intel_de_read(dev_priv, reg); |
| 5367 | temp &= ~FDI_RX_SYMBOL_LOCK(1 << 9); |
| 5368 | temp &= ~FDI_RX_BIT_LOCK(1 << 8); |
| 5369 | intel_de_write(dev_priv, reg, temp); |
| 5370 | |
| 5371 | intel_de_posting_read(dev_priv, reg); |
| 5372 | udelay(150); |
| 5373 | |
| 5374 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR before link train 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR before link train 0x%x\n" , intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf0014 ) + (pipe) * ((0xf1014) - (0xf0014)))) }))) |
| 5375 | intel_de_read(dev_priv, FDI_RX_IIR(pipe)))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR before link train 0x%x\n" , intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf0014 ) + (pipe) * ((0xf1014) - (0xf0014)))) }))); |
| 5376 | |
| 5377 | /* Try each vswing and preemphasis setting twice before moving on */ |
| 5378 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param)(sizeof((snb_b_fdi_train_param)) / sizeof((snb_b_fdi_train_param )[0])) * 2; j++) { |
| 5379 | /* disable first in case we need to retry */ |
| 5380 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5381 | temp = intel_de_read(dev_priv, reg); |
| 5382 | temp &= ~(FDI_LINK_TRAIN_AUTO(1 << 10) | FDI_LINK_TRAIN_NONE_IVB(3 << 8)); |
| 5383 | temp &= ~FDI_TX_ENABLE(1 << 31); |
| 5384 | intel_de_write(dev_priv, reg, temp); |
| 5385 | |
| 5386 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5387 | temp = intel_de_read(dev_priv, reg); |
| 5388 | temp &= ~FDI_LINK_TRAIN_AUTO(1 << 10); |
| 5389 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8); |
| 5390 | temp &= ~FDI_RX_ENABLE(1 << 31); |
| 5391 | intel_de_write(dev_priv, reg, temp); |
| 5392 | |
| 5393 | /* enable CPU FDI TX and PCH FDI RX */ |
| 5394 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5395 | temp = intel_de_read(dev_priv, reg); |
| 5396 | temp &= ~FDI_DP_PORT_WIDTH_MASK(7 << 19); |
| 5397 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes)(((crtc_state->fdi_lanes) - 1) << 19); |
| 5398 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB(0 << 8); |
| 5399 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK(0x3f << 22); |
| 5400 | temp |= snb_b_fdi_train_param[j/2]; |
| 5401 | temp |= FDI_COMPOSITE_SYNC(1 << 11); |
| 5402 | intel_de_write(dev_priv, reg, temp | FDI_TX_ENABLE(1 << 31)); |
| 5403 | |
| 5404 | intel_de_write(dev_priv, FDI_RX_MISC(pipe)((const i915_reg_t){ .reg = (((0xf0010) + (pipe) * ((0xf1010) - (0xf0010)))) }), |
| 5405 | FDI_RX_TP1_TO_TP2_48(2 << 20) | FDI_RX_FDI_DELAY_90(0x90 << 0)); |
| 5406 | |
| 5407 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5408 | temp = intel_de_read(dev_priv, reg); |
| 5409 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT(0 << 8); |
| 5410 | temp |= FDI_COMPOSITE_SYNC(1 << 11); |
| 5411 | intel_de_write(dev_priv, reg, temp | FDI_RX_ENABLE(1 << 31)); |
| 5412 | |
| 5413 | intel_de_posting_read(dev_priv, reg); |
| 5414 | udelay(1); /* should be 0.5us */ |
| 5415 | |
| 5416 | for (i = 0; i < 4; i++) { |
| 5417 | reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014) - (0xf0014)))) }); |
| 5418 | temp = intel_de_read(dev_priv, reg); |
| 5419 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n" , temp); |
| 5420 | |
| 5421 | if (temp & FDI_RX_BIT_LOCK(1 << 8) || |
| 5422 | (intel_de_read(dev_priv, reg) & FDI_RX_BIT_LOCK(1 << 8))) { |
| 5423 | intel_de_write(dev_priv, reg, |
| 5424 | temp | FDI_RX_BIT_LOCK(1 << 8)); |
| 5425 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done, level %i.\n" , i) |
| 5426 | "FDI train 1 done, level %i.\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done, level %i.\n" , i) |
| 5427 | i)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 done, level %i.\n" , i); |
| 5428 | break; |
| 5429 | } |
| 5430 | udelay(1); /* should be 0.5us */ |
| 5431 | } |
| 5432 | if (i == 4) { |
| 5433 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 fail on vswing %d\n" , j / 2) |
| 5434 | "FDI train 1 fail on vswing %d\n", j / 2)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 1 fail on vswing %d\n" , j / 2); |
| 5435 | continue; |
| 5436 | } |
| 5437 | |
| 5438 | /* Train 2 */ |
| 5439 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5440 | temp = intel_de_read(dev_priv, reg); |
| 5441 | temp &= ~FDI_LINK_TRAIN_NONE_IVB(3 << 8); |
| 5442 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB(1 << 8); |
| 5443 | intel_de_write(dev_priv, reg, temp); |
| 5444 | |
| 5445 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5446 | temp = intel_de_read(dev_priv, reg); |
| 5447 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8); |
| 5448 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT(1 << 8); |
| 5449 | intel_de_write(dev_priv, reg, temp); |
| 5450 | |
| 5451 | intel_de_posting_read(dev_priv, reg); |
| 5452 | udelay(2); /* should be 1.5us */ |
| 5453 | |
| 5454 | for (i = 0; i < 4; i++) { |
| 5455 | reg = FDI_RX_IIR(pipe)((const i915_reg_t){ .reg = (((0xf0014) + (pipe) * ((0xf1014) - (0xf0014)))) }); |
| 5456 | temp = intel_de_read(dev_priv, reg); |
| 5457 | drm_dbg_kms(&dev_priv->drm, "FDI_RX_IIR 0x%x\n", temp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI_RX_IIR 0x%x\n" , temp); |
| 5458 | |
| 5459 | if (temp & FDI_RX_SYMBOL_LOCK(1 << 9) || |
| 5460 | (intel_de_read(dev_priv, reg) & FDI_RX_SYMBOL_LOCK(1 << 9))) { |
| 5461 | intel_de_write(dev_priv, reg, |
| 5462 | temp | FDI_RX_SYMBOL_LOCK(1 << 9)); |
| 5463 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done, level %i.\n" , i) |
| 5464 | "FDI train 2 done, level %i.\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done, level %i.\n" , i) |
| 5465 | i)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 done, level %i.\n" , i); |
| 5466 | goto train_done; |
| 5467 | } |
| 5468 | udelay(2); /* should be 1.5us */ |
| 5469 | } |
| 5470 | if (i == 4) |
| 5471 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 fail on vswing %d\n" , j / 2) |
| 5472 | "FDI train 2 fail on vswing %d\n", j / 2)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train 2 fail on vswing %d\n" , j / 2); |
| 5473 | } |
| 5474 | |
| 5475 | train_done: |
| 5476 | drm_dbg_kms(&dev_priv->drm, "FDI train done.\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "FDI train done.\n" ); |
| 5477 | } |
| 5478 | |
| 5479 | static void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) |
| 5480 | { |
| 5481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5482 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_crtc->base.dev); |
| 5483 | enum pipe pipe = intel_crtc->pipe; |
| 5484 | i915_reg_t reg; |
| 5485 | u32 temp; |
| 5486 | |
| 5487 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
| 5488 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5489 | temp = intel_de_read(dev_priv, reg); |
| 5490 | temp &= ~(FDI_DP_PORT_WIDTH_MASK(7 << 19) | (0x7 << 16)); |
| 5491 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes)(((crtc_state->fdi_lanes) - 1) << 19); |
| 5492 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & PIPECONF_BPC_MASK(0x7 << 5)) << 11; |
| 5493 | intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE(1 << 13)); |
| 5494 | |
| 5495 | intel_de_posting_read(dev_priv, reg); |
| 5496 | udelay(200); |
| 5497 | |
| 5498 | /* Switch from Rawclk to PCDclk */ |
| 5499 | temp = intel_de_read(dev_priv, reg); |
| 5500 | intel_de_write(dev_priv, reg, temp | FDI_PCDCLK(1 << 4)); |
| 5501 | |
| 5502 | intel_de_posting_read(dev_priv, reg); |
| 5503 | udelay(200); |
| 5504 | |
| 5505 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
| 5506 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5507 | temp = intel_de_read(dev_priv, reg); |
| 5508 | if ((temp & FDI_TX_PLL_ENABLE(1 << 14)) == 0) { |
| 5509 | intel_de_write(dev_priv, reg, temp | FDI_TX_PLL_ENABLE(1 << 14)); |
| 5510 | |
| 5511 | intel_de_posting_read(dev_priv, reg); |
| 5512 | udelay(100); |
| 5513 | } |
| 5514 | } |
| 5515 | |
| 5516 | static void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc) |
| 5517 | { |
| 5518 | struct drm_device *dev = intel_crtc->base.dev; |
| 5519 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 5520 | enum pipe pipe = intel_crtc->pipe; |
| 5521 | i915_reg_t reg; |
| 5522 | u32 temp; |
| 5523 | |
| 5524 | /* Switch from PCDclk to Rawclk */ |
| 5525 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5526 | temp = intel_de_read(dev_priv, reg); |
| 5527 | intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK(1 << 4)); |
| 5528 | |
| 5529 | /* Disable CPU FDI TX PLL */ |
| 5530 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5531 | temp = intel_de_read(dev_priv, reg); |
| 5532 | intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE(1 << 14)); |
| 5533 | |
| 5534 | intel_de_posting_read(dev_priv, reg); |
| 5535 | udelay(100); |
| 5536 | |
| 5537 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5538 | temp = intel_de_read(dev_priv, reg); |
| 5539 | intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE(1 << 13)); |
| 5540 | |
| 5541 | /* Wait for the clocks to turn off. */ |
| 5542 | intel_de_posting_read(dev_priv, reg); |
| 5543 | udelay(100); |
| 5544 | } |
| 5545 | |
| 5546 | static void ilk_fdi_disable(struct intel_crtc *crtc) |
| 5547 | { |
| 5548 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 5549 | enum pipe pipe = crtc->pipe; |
| 5550 | i915_reg_t reg; |
| 5551 | u32 temp; |
| 5552 | |
| 5553 | /* disable CPU FDI tx and PCH FDI rx */ |
| 5554 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5555 | temp = intel_de_read(dev_priv, reg); |
| 5556 | intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE(1 << 31)); |
| 5557 | intel_de_posting_read(dev_priv, reg); |
| 5558 | |
| 5559 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5560 | temp = intel_de_read(dev_priv, reg); |
| 5561 | temp &= ~(0x7 << 16); |
| 5562 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & PIPECONF_BPC_MASK(0x7 << 5)) << 11; |
| 5563 | intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE(1 << 31)); |
| 5564 | |
| 5565 | intel_de_posting_read(dev_priv, reg); |
| 5566 | udelay(100); |
| 5567 | |
| 5568 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
| 5569 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) |
| 5570 | intel_de_write(dev_priv, FDI_RX_CHICKEN(pipe)((const i915_reg_t){ .reg = (((0xc200c) + (pipe) * ((0xc2010) - (0xc200c)))) }), |
| 5571 | FDI_RX_PHASE_SYNC_POINTER_OVR(1 << 1)); |
| 5572 | |
| 5573 | /* still set train pattern 1 */ |
| 5574 | reg = FDI_TX_CTL(pipe)((const i915_reg_t){ .reg = (((0x60100) + (pipe) * ((0x61100) - (0x60100)))) }); |
| 5575 | temp = intel_de_read(dev_priv, reg); |
| 5576 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5577 | temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28); |
| 5578 | intel_de_write(dev_priv, reg, temp); |
| 5579 | |
| 5580 | reg = FDI_RX_CTL(pipe)((const i915_reg_t){ .reg = (((0xf000c) + (pipe) * ((0xf100c) - (0xf000c)))) }); |
| 5581 | temp = intel_de_read(dev_priv, reg); |
| 5582 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 5583 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT(3 << 8); |
| 5584 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT(0 << 8); |
| 5585 | } else { |
| 5586 | temp &= ~FDI_LINK_TRAIN_NONE(3 << 28); |
| 5587 | temp |= FDI_LINK_TRAIN_PATTERN_1(0 << 28); |
| 5588 | } |
| 5589 | /* BPC in FDI rx is consistent with that in PIPECONF */ |
| 5590 | temp &= ~(0x07 << 16); |
| 5591 | temp |= (intel_de_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & PIPECONF_BPC_MASK(0x7 << 5)) << 11; |
| 5592 | intel_de_write(dev_priv, reg, temp); |
| 5593 | |
| 5594 | intel_de_posting_read(dev_priv, reg); |
| 5595 | udelay(100); |
| 5596 | } |
| 5597 | |
| 5598 | bool_Bool intel_has_pending_fb_unpin(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 5599 | { |
| 5600 | struct drm_crtc *crtc; |
| 5601 | bool_Bool cleanup_done; |
| 5602 | |
| 5603 | drm_for_each_crtc(crtc, &dev_priv->drm)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head ) *__mptr = ((&(&dev_priv->drm)->mode_config.crtc_list )->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), head) );}); &crtc->head != (&(& dev_priv->drm)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head ) *__mptr = (crtc-> head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), head) );})) { |
| 5604 | struct drm_crtc_commit *commit; |
| 5605 | spin_lock(&crtc->commit_lock)mtx_enter(&crtc->commit_lock); |
| 5606 | commit = list_first_entry_or_null(&crtc->commit_list,(list_empty(&crtc->commit_list) ? ((void *)0) : ({ const __typeof( ((struct drm_crtc_commit *)0)->commit_entry ) * __mptr = ((&crtc->commit_list)->next); (struct drm_crtc_commit *)( (char *)__mptr - __builtin_offsetof(struct drm_crtc_commit , commit_entry) );})) |
| 5607 | struct drm_crtc_commit, commit_entry)(list_empty(&crtc->commit_list) ? ((void *)0) : ({ const __typeof( ((struct drm_crtc_commit *)0)->commit_entry ) * __mptr = ((&crtc->commit_list)->next); (struct drm_crtc_commit *)( (char *)__mptr - __builtin_offsetof(struct drm_crtc_commit , commit_entry) );})); |
| 5608 | cleanup_done = commit ? |
| 5609 | try_wait_for_completion(&commit->cleanup_done) : true1; |
| 5610 | spin_unlock(&crtc->commit_lock)mtx_leave(&crtc->commit_lock); |
| 5611 | |
| 5612 | if (cleanup_done) |
| 5613 | continue; |
| 5614 | |
| 5615 | drm_crtc_wait_one_vblank(crtc); |
| 5616 | |
| 5617 | return true1; |
| 5618 | } |
| 5619 | |
| 5620 | return false0; |
| 5621 | } |
| 5622 | |
| 5623 | void lpt_disable_iclkip(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 5624 | { |
| 5625 | u32 temp; |
| 5626 | |
| 5627 | intel_de_write(dev_priv, PIXCLK_GATE((const i915_reg_t){ .reg = (0xC6020) }), PIXCLK_GATE_GATE(0 << 0)); |
| 5628 | |
| 5629 | mutex_lock(&dev_priv->sb_lock)rw_enter_write(&dev_priv->sb_lock); |
| 5630 | |
| 5631 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL60x060C, SBI_ICLK); |
| 5632 | temp |= SBI_SSCCTL_DISABLE(1 << 0); |
| 5633 | intel_sbi_write(dev_priv, SBI_SSCCTL60x060C, temp, SBI_ICLK); |
| 5634 | |
| 5635 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 5636 | } |
| 5637 | |
| 5638 | /* Program iCLKIP clock to the desired frequency */ |
| 5639 | static void lpt_program_iclkip(const struct intel_crtc_state *crtc_state) |
| 5640 | { |
| 5641 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5642 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 5643 | int clock = crtc_state->hw.adjusted_mode.crtc_clock; |
| 5644 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
| 5645 | u32 temp; |
| 5646 | |
| 5647 | lpt_disable_iclkip(dev_priv); |
| 5648 | |
| 5649 | /* The iCLK virtual clock root frequency is in MHz, |
| 5650 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
| 5651 | * divisors, it is necessary to divide one by another, so we |
| 5652 | * convert the virtual clock precision to KHz here for higher |
| 5653 | * precision. |
| 5654 | */ |
| 5655 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { |
| 5656 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 5657 | u32 iclk_pi_range = 64; |
| 5658 | u32 desired_divisor; |
| 5659 | |
| 5660 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,(((iclk_virtual_root_freq) + ((clock << auxdiv) / 2)) / (clock << auxdiv)) |
| 5661 | clock << auxdiv)(((iclk_virtual_root_freq) + ((clock << auxdiv) / 2)) / (clock << auxdiv)); |
| 5662 | divsel = (desired_divisor / iclk_pi_range) - 2; |
| 5663 | phaseinc = desired_divisor % iclk_pi_range; |
| 5664 | |
| 5665 | /* |
| 5666 | * Near 20MHz is a corner case which is |
| 5667 | * out of range for the 7-bit divisor |
| 5668 | */ |
| 5669 | if (divsel <= 0x7f) |
| 5670 | break; |
| 5671 | } |
| 5672 | |
| 5673 | /* This should not happen with any sane values */ |
| 5674 | drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIVSEL(divsel) &({ int __ret = !!((((divsel) << 1) & ~(0x7f << 1))); if (__ret) printf("%s %s: " "%s", dev_driver_string((( &dev_priv->drm))->dev), "", "drm_WARN_ON(" "((divsel) << 1) & ~(0x7f << 1)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 5675 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK)({ int __ret = !!((((divsel) << 1) & ~(0x7f << 1))); if (__ret) printf("%s %s: " "%s", dev_driver_string((( &dev_priv->drm))->dev), "", "drm_WARN_ON(" "((divsel) << 1) & ~(0x7f << 1)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 5676 | drm_WARN_ON(&dev_priv->drm, SBI_SSCDIVINTPHASE_DIR(phasedir) &({ int __ret = !!((((phasedir) << 15) & ~(0x7f << 8))); if (__ret) printf("%s %s: " "%s", dev_driver_string((( &dev_priv->drm))->dev), "", "drm_WARN_ON(" "((phasedir) << 15) & ~(0x7f << 8)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 5677 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK)({ int __ret = !!((((phasedir) << 15) & ~(0x7f << 8))); if (__ret) printf("%s %s: " "%s", dev_driver_string((( &dev_priv->drm))->dev), "", "drm_WARN_ON(" "((phasedir) << 15) & ~(0x7f << 8)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 5678 | |
| 5679 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n" , clock, auxdiv, divsel, phasedir, phaseinc) |
| 5680 | "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n" , clock, auxdiv, divsel, phasedir, phaseinc) |
| 5681 | clock, auxdiv, divsel, phasedir, phaseinc)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n" , clock, auxdiv, divsel, phasedir, phaseinc); |
| 5682 | |
| 5683 | mutex_lock(&dev_priv->sb_lock)rw_enter_write(&dev_priv->sb_lock); |
| 5684 | |
| 5685 | /* Program SSCDIVINTPHASE6 */ |
| 5686 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE60x0600, SBI_ICLK); |
| 5687 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK(0x7f << 1); |
| 5688 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel)((divsel) << 1); |
| 5689 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK(0x7f << 8); |
| 5690 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc)((phaseinc) << 8); |
| 5691 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir)((phasedir) << 15); |
| 5692 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE(1 << 0); |
| 5693 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE60x0600, temp, SBI_ICLK); |
| 5694 | |
| 5695 | /* Program SSCAUXDIV */ |
| 5696 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV60x0610, SBI_ICLK); |
| 5697 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1)((1) << 4); |
| 5698 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv)((auxdiv) << 4); |
| 5699 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV60x0610, temp, SBI_ICLK); |
| 5700 | |
| 5701 | /* Enable modulator and associated divider */ |
| 5702 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL60x060C, SBI_ICLK); |
| 5703 | temp &= ~SBI_SSCCTL_DISABLE(1 << 0); |
| 5704 | intel_sbi_write(dev_priv, SBI_SSCCTL60x060C, temp, SBI_ICLK); |
| 5705 | |
| 5706 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 5707 | |
| 5708 | /* Wait for initialization time */ |
| 5709 | udelay(24); |
| 5710 | |
| 5711 | intel_de_write(dev_priv, PIXCLK_GATE((const i915_reg_t){ .reg = (0xC6020) }), PIXCLK_GATE_UNGATE(1 << 0)); |
| 5712 | } |
| 5713 | |
| 5714 | int lpt_get_iclkip(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 5715 | { |
| 5716 | u32 divsel, phaseinc, auxdiv; |
| 5717 | u32 iclk_virtual_root_freq = 172800 * 1000; |
| 5718 | u32 iclk_pi_range = 64; |
| 5719 | u32 desired_divisor; |
| 5720 | u32 temp; |
| 5721 | |
| 5722 | if ((intel_de_read(dev_priv, PIXCLK_GATE((const i915_reg_t){ .reg = (0xC6020) })) & PIXCLK_GATE_UNGATE(1 << 0)) == 0) |
| 5723 | return 0; |
| 5724 | |
| 5725 | mutex_lock(&dev_priv->sb_lock)rw_enter_write(&dev_priv->sb_lock); |
| 5726 | |
| 5727 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL60x060C, SBI_ICLK); |
| 5728 | if (temp & SBI_SSCCTL_DISABLE(1 << 0)) { |
| 5729 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 5730 | return 0; |
| 5731 | } |
| 5732 | |
| 5733 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE60x0600, SBI_ICLK); |
| 5734 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK(0x7f << 1)) >> |
| 5735 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT1; |
| 5736 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK(0x7f << 8)) >> |
| 5737 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT8; |
| 5738 | |
| 5739 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV60x0610, SBI_ICLK); |
| 5740 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK(1 << 4)) >> |
| 5741 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT4; |
| 5742 | |
| 5743 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 5744 | |
| 5745 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; |
| 5746 | |
| 5747 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,(((iclk_virtual_root_freq) + ((desired_divisor << auxdiv ) / 2)) / (desired_divisor << auxdiv)) |
| 5748 | desired_divisor << auxdiv)(((iclk_virtual_root_freq) + ((desired_divisor << auxdiv ) / 2)) / (desired_divisor << auxdiv)); |
| 5749 | } |
| 5750 | |
| 5751 | static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_state, |
| 5752 | enum pipe pch_transcoder) |
| 5753 | { |
| 5754 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5755 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 5756 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
| 5757 | |
| 5758 | intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder)((const i915_reg_t){ .reg = (((0xe0000) + (pch_transcoder) * ( (0xe1000) - (0xe0000)))) }), |
| 5759 | intel_de_read(dev_priv, HTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60000) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5760 | intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder)((const i915_reg_t){ .reg = (((0xe0004) + (pch_transcoder) * ( (0xe1004) - (0xe0004)))) }), |
| 5761 | intel_de_read(dev_priv, HBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60004) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5762 | intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder)((const i915_reg_t){ .reg = (((0xe0008) + (pch_transcoder) * ( (0xe1008) - (0xe0008)))) }), |
| 5763 | intel_de_read(dev_priv, HSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60008) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5764 | |
| 5765 | intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder)((const i915_reg_t){ .reg = (((0xe000c) + (pch_transcoder) * ( (0xe100c) - (0xe000c)))) }), |
| 5766 | intel_de_read(dev_priv, VTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x6000c) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5767 | intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder)((const i915_reg_t){ .reg = (((0xe0010) + (pch_transcoder) * ( (0xe1010) - (0xe0010)))) }), |
| 5768 | intel_de_read(dev_priv, VBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60010) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5769 | intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder)((const i915_reg_t){ .reg = (((0xe0014) + (pch_transcoder) * ( (0xe1014) - (0xe0014)))) }), |
| 5770 | intel_de_read(dev_priv, VSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60014) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5771 | intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder)((const i915_reg_t){ .reg = (((0xe0028) + (pch_transcoder) * ( (0xe1028) - (0xe0028)))) }), |
| 5772 | intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60028) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 5773 | } |
| 5774 | |
| 5775 | static void cpt_set_fdi_bc_bifurcation(struct drm_i915_privateinteldrm_softc *dev_priv, bool_Bool enable) |
| 5776 | { |
| 5777 | u32 temp; |
| 5778 | |
| 5779 | temp = intel_de_read(dev_priv, SOUTH_CHICKEN1((const i915_reg_t){ .reg = (0xc2000) })); |
| 5780 | if (!!(temp & FDI_BC_BIFURCATION_SELECT(1 << 12)) == enable) |
| 5781 | return; |
| 5782 | |
| 5783 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0xf000c) + (PIPE_B) * ((0xf100c) - (0xf000c)))) } )) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_B) * ((0xf100c) - (0xf000c)))) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 5784 | intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) &({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0xf000c) + (PIPE_B) * ((0xf100c) - (0xf000c)))) } )) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_B) * ((0xf100c) - (0xf000c)))) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 5785 | FDI_RX_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0xf000c) + (PIPE_B) * ((0xf100c) - (0xf000c)))) } )) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_B) * ((0xf100c) - (0xf000c)))) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 5786 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0xf000c) + (PIPE_C) * ((0xf100c) - (0xf000c)))) } )) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_C) * ((0xf100c) - (0xf000c)))) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 5787 | intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) &({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0xf000c) + (PIPE_C) * ((0xf100c) - (0xf000c)))) } )) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_C) * ((0xf100c) - (0xf000c)))) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 5788 | FDI_RX_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0xf000c) + (PIPE_C) * ((0xf100c) - (0xf000c)))) } )) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_C) * ((0xf100c) - (0xf000c)))) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 5789 | |
| 5790 | temp &= ~FDI_BC_BIFURCATION_SELECT(1 << 12); |
| 5791 | if (enable) |
| 5792 | temp |= FDI_BC_BIFURCATION_SELECT(1 << 12); |
| 5793 | |
| 5794 | drm_dbg_kms(&dev_priv->drm, "%sabling fdi C rx\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%sabling fdi C rx\n" , enable ? "en" : "dis") |
| 5795 | enable ? "en" : "dis")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%sabling fdi C rx\n" , enable ? "en" : "dis"); |
| 5796 | intel_de_write(dev_priv, SOUTH_CHICKEN1((const i915_reg_t){ .reg = (0xc2000) }), temp); |
| 5797 | intel_de_posting_read(dev_priv, SOUTH_CHICKEN1((const i915_reg_t){ .reg = (0xc2000) })); |
| 5798 | } |
| 5799 | |
| 5800 | static void ivb_update_fdi_bc_bifurcation(const struct intel_crtc_state *crtc_state) |
| 5801 | { |
| 5802 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5803 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 5804 | |
| 5805 | switch (crtc->pipe) { |
| 5806 | case PIPE_A: |
| 5807 | break; |
| 5808 | case PIPE_B: |
| 5809 | if (crtc_state->fdi_lanes > 2) |
| 5810 | cpt_set_fdi_bc_bifurcation(dev_priv, false0); |
| 5811 | else |
| 5812 | cpt_set_fdi_bc_bifurcation(dev_priv, true1); |
| 5813 | |
| 5814 | break; |
| 5815 | case PIPE_C: |
| 5816 | cpt_set_fdi_bc_bifurcation(dev_priv, true1); |
| 5817 | |
| 5818 | break; |
| 5819 | default: |
| 5820 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 5820); } while (0); |
| 5821 | } |
| 5822 | } |
| 5823 | |
| 5824 | /* |
| 5825 | * Finds the encoder associated with the given CRTC. This can only be |
| 5826 | * used when we know that the CRTC isn't feeding multiple encoders! |
| 5827 | */ |
| 5828 | static struct intel_encoder * |
| 5829 | intel_get_crtc_new_encoder(const struct intel_atomic_state *state, |
| 5830 | const struct intel_crtc_state *crtc_state) |
| 5831 | { |
| 5832 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5833 | const struct drm_connector_state *connector_state; |
| 5834 | const struct drm_connector *connector; |
| 5835 | struct intel_encoder *encoder = NULL((void *)0); |
| 5836 | int num_encoders = 0; |
| 5837 | int i; |
| 5838 | |
| 5839 | for_each_new_connector_in_state(&state->base, connector, connector_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (connector_state) = (&state->base)-> connectors[i].new_state, (void)(connector_state) , 1))) {} else { |
| 5840 | if (connector_state->crtc != &crtc->base) |
| 5841 | continue; |
| 5842 | |
| 5843 | encoder = to_intel_encoder(connector_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (connector_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 5844 | num_encoders++; |
| 5845 | } |
| 5846 | |
| 5847 | drm_WARN(encoder->base.dev, num_encoders != 1,({ int __ret = !!(num_encoders != 1); if (__ret) printf("%s %s: " "%d encoders for pipe %c\n", dev_driver_string((encoder-> base.dev)->dev), "", num_encoders, ((crtc->pipe) + 'A') ); __builtin_expect(!!(__ret), 0); }) |
| 5848 | "%d encoders for pipe %c\n",({ int __ret = !!(num_encoders != 1); if (__ret) printf("%s %s: " "%d encoders for pipe %c\n", dev_driver_string((encoder-> base.dev)->dev), "", num_encoders, ((crtc->pipe) + 'A') ); __builtin_expect(!!(__ret), 0); }) |
| 5849 | num_encoders, pipe_name(crtc->pipe))({ int __ret = !!(num_encoders != 1); if (__ret) printf("%s %s: " "%d encoders for pipe %c\n", dev_driver_string((encoder-> base.dev)->dev), "", num_encoders, ((crtc->pipe) + 'A') ); __builtin_expect(!!(__ret), 0); }); |
| 5850 | |
| 5851 | return encoder; |
| 5852 | } |
| 5853 | |
| 5854 | /* |
| 5855 | * Enable PCH resources required for PCH ports: |
| 5856 | * - PCH PLLs |
| 5857 | * - FDI training & RX/TX |
| 5858 | * - update transcoder timings |
| 5859 | * - DP transcoding bits |
| 5860 | * - transcoder |
| 5861 | */ |
| 5862 | static void ilk_pch_enable(const struct intel_atomic_state *state, |
| 5863 | const struct intel_crtc_state *crtc_state) |
| 5864 | { |
| 5865 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5866 | struct drm_device *dev = crtc->base.dev; |
| 5867 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 5868 | enum pipe pipe = crtc->pipe; |
| 5869 | u32 temp; |
| 5870 | |
| 5871 | assert_pch_transcoder_disabled(dev_priv, pipe); |
| 5872 | |
| 5873 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
| 5874 | ivb_update_fdi_bc_bifurcation(crtc_state); |
| 5875 | |
| 5876 | /* Write the TU size bits before fdi link training, so that error |
| 5877 | * detection works. */ |
| 5878 | intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe)((const i915_reg_t){ .reg = (((0xf0030) + (pipe) * ((0xf1030) - (0xf0030)))) }), |
| 5879 | intel_de_read(dev_priv, PIPE_DATA_M1(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60030) + ((&(dev_priv)->__info)-> display_mmio_offset))) })) & TU_SIZE_MASK(0x3f << 25)); |
| 5880 | |
| 5881 | /* For PCH output, training FDI link */ |
| 5882 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
| 5883 | |
| 5884 | /* We need to program the right clock selection before writing the pixel |
| 5885 | * mutliplier into the DPLL. */ |
| 5886 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 5887 | u32 sel; |
| 5888 | |
| 5889 | temp = intel_de_read(dev_priv, PCH_DPLL_SEL((const i915_reg_t){ .reg = (0xc7000) })); |
| 5890 | temp |= TRANS_DPLL_ENABLE(pipe)(1 << ((pipe) * 4 + 3)); |
| 5891 | sel = TRANS_DPLLB_SEL(pipe)(1 << ((pipe) * 4)); |
| 5892 | if (crtc_state->shared_dpll == |
| 5893 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
| 5894 | temp |= sel; |
| 5895 | else |
| 5896 | temp &= ~sel; |
| 5897 | intel_de_write(dev_priv, PCH_DPLL_SEL((const i915_reg_t){ .reg = (0xc7000) }), temp); |
| 5898 | } |
| 5899 | |
| 5900 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
| 5901 | * transcoder, and we actually should do this to not upset any PCH |
| 5902 | * transcoder that already use the clock when we share it. |
| 5903 | * |
| 5904 | * Note that enable_shared_dpll tries to do the right thing, but |
| 5905 | * get_shared_dpll unconditionally resets the pll - we need that to have |
| 5906 | * the right LVDS enable sequence. */ |
| 5907 | intel_enable_shared_dpll(crtc_state); |
| 5908 | |
| 5909 | /* set transcoder timing, panel must allow it */ |
| 5910 | assert_panel_unlocked(dev_priv, pipe); |
| 5911 | ilk_pch_transcoder_set_timings(crtc_state, pipe); |
| 5912 | |
| 5913 | intel_fdi_normal_train(crtc); |
| 5914 | |
| 5915 | /* For PCH DP, enable TRANS_DP_CTL */ |
| 5916 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT) && |
| 5917 | intel_crtc_has_dp_encoder(crtc_state)) { |
| 5918 | const struct drm_display_mode *adjusted_mode = |
| 5919 | &crtc_state->hw.adjusted_mode; |
| 5920 | u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & PIPECONF_BPC_MASK(0x7 << 5)) >> 5; |
| 5921 | i915_reg_t reg = TRANS_DP_CTL(pipe)((const i915_reg_t){ .reg = (((0xe0300) + (pipe) * ((0xe1300) - (0xe0300)))) }); |
| 5922 | enum port port; |
| 5923 | |
| 5924 | temp = intel_de_read(dev_priv, reg); |
| 5925 | temp &= ~(TRANS_DP_PORT_SEL_MASK(3 << 29) | |
| 5926 | TRANS_DP_SYNC_MASK(3 << 3) | |
| 5927 | TRANS_DP_BPC_MASK(3 << 9)); |
| 5928 | temp |= TRANS_DP_OUTPUT_ENABLE(1 << 31); |
| 5929 | temp |= bpc << 9; /* same format but at 11:9 */ |
| 5930 | |
| 5931 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
| 5932 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH(1 << 3); |
| 5933 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
| 5934 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH(1 << 4); |
| 5935 | |
| 5936 | port = intel_get_crtc_new_encoder(state, crtc_state)->port; |
| 5937 | drm_WARN_ON(dev, port < PORT_B || port > PORT_D)({ int __ret = !!((port < PORT_B || port > PORT_D)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev))-> dev), "", "drm_WARN_ON(" "port < PORT_B || port > PORT_D" ")"); __builtin_expect(!!(__ret), 0); }); |
| 5938 | temp |= TRANS_DP_PORT_SEL(port)(((port) - PORT_B) << 29); |
| 5939 | |
| 5940 | intel_de_write(dev_priv, reg, temp); |
| 5941 | } |
| 5942 | |
| 5943 | ilk_enable_pch_transcoder(crtc_state); |
| 5944 | } |
| 5945 | |
| 5946 | void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
| 5947 | { |
| 5948 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 5949 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 5950 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
| 5951 | |
| 5952 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
| 5953 | |
| 5954 | lpt_program_iclkip(crtc_state); |
| 5955 | |
| 5956 | /* Set transcoder timing. */ |
| 5957 | ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); |
| 5958 | |
| 5959 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
| 5960 | } |
| 5961 | |
| 5962 | static void cpt_verify_modeset(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 5963 | enum pipe pipe) |
| 5964 | { |
| 5965 | i915_reg_t dslreg = PIPEDSL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70000) + ((&(dev_priv)->__info)->display_mmio_offset )) }); |
| 5966 | u32 temp; |
| 5967 | |
| 5968 | temp = intel_de_read(dev_priv, dslreg); |
| 5969 | udelay(500); |
| 5970 | if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (((5) * 1000))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if (((intel_de_read (dev_priv, dslreg) != temp))) { ret__ = 0; break; } if (expired__ ) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((1000))) wait__ <<= 1; } ret__; })) { |
| 5971 | if (wait_for(intel_de_read(dev_priv, dslreg) != temp, 5)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (((5) * 1000))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if (((intel_de_read (dev_priv, dslreg) != temp))) { ret__ = 0; break; } if (expired__ ) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((1000))) wait__ <<= 1; } ret__; })) |
| 5972 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mode set failed: pipe %c stuck\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
| 5973 | "mode set failed: pipe %c stuck\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mode set failed: pipe %c stuck\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
| 5974 | pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mode set failed: pipe %c stuck\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')); |
| 5975 | } |
| 5976 | } |
| 5977 | |
| 5978 | /* |
| 5979 | * The hardware phase 0.0 refers to the center of the pixel. |
| 5980 | * We want to start from the top/left edge which is phase |
| 5981 | * -0.5. That matches how the hardware calculates the scaling |
| 5982 | * factors (from top-left of the first pixel to bottom-right |
| 5983 | * of the last pixel, as opposed to the pixel centers). |
| 5984 | * |
| 5985 | * For 4:2:0 subsampled chroma planes we obviously have to |
| 5986 | * adjust that so that the chroma sample position lands in |
| 5987 | * the right spot. |
| 5988 | * |
| 5989 | * Note that for packed YCbCr 4:2:2 formats there is no way to |
| 5990 | * control chroma siting. The hardware simply replicates the |
| 5991 | * chroma samples for both of the luma samples, and thus we don't |
| 5992 | * actually get the expected MPEG2 chroma siting convention :( |
| 5993 | * The same behaviour is observed on pre-SKL platforms as well. |
| 5994 | * |
| 5995 | * Theory behind the formula (note that we ignore sub-pixel |
| 5996 | * source coordinates): |
| 5997 | * s = source sample position |
| 5998 | * d = destination sample position |
| 5999 | * |
| 6000 | * Downscaling 4:1: |
| 6001 | * -0.5 |
| 6002 | * | 0.0 |
| 6003 | * | | 1.5 (initial phase) |
| 6004 | * | | | |
| 6005 | * v v v |
| 6006 | * | s | s | s | s | |
| 6007 | * | d | |
| 6008 | * |
| 6009 | * Upscaling 1:4: |
| 6010 | * -0.5 |
| 6011 | * | -0.375 (initial phase) |
| 6012 | * | | 0.0 |
| 6013 | * | | | |
| 6014 | * v v v |
| 6015 | * | s | |
| 6016 | * | d | d | d | d | |
| 6017 | */ |
| 6018 | u16 skl_scaler_calc_phase(int sub, int scale, bool_Bool chroma_cosited) |
| 6019 | { |
| 6020 | int phase = -0x8000; |
| 6021 | u16 trip = 0; |
| 6022 | |
| 6023 | if (chroma_cosited) |
| 6024 | phase += (sub - 1) * 0x8000 / sub; |
| 6025 | |
| 6026 | phase += scale / (2 * sub); |
| 6027 | |
| 6028 | /* |
| 6029 | * Hardware initial phase limited to [-0.5:1.5]. |
| 6030 | * Since the max hardware scale factor is 3.0, we |
| 6031 | * should never actually excdeed 1.0 here. |
| 6032 | */ |
| 6033 | WARN_ON(phase < -0x8000 || phase > 0x18000)({ int __ret = !!((phase < -0x8000 || phase > 0x18000)) ; if (__ret) printf("%s", "WARN_ON(" "phase < -0x8000 || phase > 0x18000" ")"); __builtin_expect(!!(__ret), 0); }); |
| 6034 | |
| 6035 | if (phase < 0) |
| 6036 | phase = 0x10000 + phase; |
| 6037 | else |
| 6038 | trip = PS_PHASE_TRIP(1 << 0); |
| 6039 | |
| 6040 | return ((phase >> 2) & PS_PHASE_MASK(0x7fff << 1)) | trip; |
| 6041 | } |
| 6042 | |
| 6043 | #define SKL_MIN_SRC_W8 8 |
| 6044 | #define SKL_MAX_SRC_W4096 4096 |
| 6045 | #define SKL_MIN_SRC_H8 8 |
| 6046 | #define SKL_MAX_SRC_H4096 4096 |
| 6047 | #define SKL_MIN_DST_W8 8 |
| 6048 | #define SKL_MAX_DST_W4096 4096 |
| 6049 | #define SKL_MIN_DST_H8 8 |
| 6050 | #define SKL_MAX_DST_H4096 4096 |
| 6051 | #define ICL_MAX_SRC_W5120 5120 |
| 6052 | #define ICL_MAX_SRC_H4096 4096 |
| 6053 | #define ICL_MAX_DST_W5120 5120 |
| 6054 | #define ICL_MAX_DST_H4096 4096 |
| 6055 | #define SKL_MIN_YUV_420_SRC_W16 16 |
| 6056 | #define SKL_MIN_YUV_420_SRC_H16 16 |
| 6057 | |
| 6058 | static int |
| 6059 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool_Bool force_detach, |
| 6060 | unsigned int scaler_user, int *scaler_id, |
| 6061 | int src_w, int src_h, int dst_w, int dst_h, |
| 6062 | const struct drm_format_info *format, |
| 6063 | u64 modifier, bool_Bool need_scaler) |
| 6064 | { |
| 6065 | struct intel_crtc_scaler_state *scaler_state = |
| 6066 | &crtc_state->scaler_state; |
| 6067 | struct intel_crtc *intel_crtc = |
| 6068 | to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6069 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_crtc->base.dev); |
| 6070 | const struct drm_display_mode *adjusted_mode = |
| 6071 | &crtc_state->hw.adjusted_mode; |
| 6072 | |
| 6073 | /* |
| 6074 | * Src coordinates are already rotated by 270 degrees for |
| 6075 | * the 90/270 degree plane rotation cases (to match the |
| 6076 | * GTT mapping), hence no need to account for rotation here. |
| 6077 | */ |
| 6078 | if (src_w != dst_w || src_h != dst_h) |
| 6079 | need_scaler = true1; |
| 6080 | |
| 6081 | /* |
| 6082 | * Scaling/fitting not supported in IF-ID mode in GEN9+ |
| 6083 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. |
| 6084 | * Once NV12 is enabled, handle it here while allocating scaler |
| 6085 | * for NV12. |
| 6086 | */ |
| 6087 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 && crtc_state->hw.enable && |
| 6088 | need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) { |
| 6089 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Pipe/Plane scaling not supported with IF-ID mode\n" ) |
| 6090 | "Pipe/Plane scaling not supported with IF-ID mode\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Pipe/Plane scaling not supported with IF-ID mode\n" ); |
| 6091 | return -EINVAL22; |
| 6092 | } |
| 6093 | |
| 6094 | /* |
| 6095 | * if plane is being disabled or scaler is no more required or force detach |
| 6096 | * - free scaler binded to this plane/crtc |
| 6097 | * - in order to do this, update crtc->scaler_usage |
| 6098 | * |
| 6099 | * Here scaler state in crtc_state is set free so that |
| 6100 | * scaler can be assigned to other user. Actual register |
| 6101 | * update to free the scaler is done in plane/panel-fit programming. |
| 6102 | * For this purpose crtc/plane_state->scaler_id isn't reset here. |
| 6103 | */ |
| 6104 | if (force_detach || !need_scaler) { |
| 6105 | if (*scaler_id >= 0) { |
| 6106 | scaler_state->scaler_users &= ~(1 << scaler_user); |
| 6107 | scaler_state->scalers[*scaler_id].in_use = 0; |
| 6108 | |
| 6109 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "Staged freeing scaler id %d scaler_users = 0x%x\n", intel_crtc ->pipe, scaler_user, *scaler_id, scaler_state->scaler_users ) |
| 6110 | "scaler_user index %u.%u: "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "Staged freeing scaler id %d scaler_users = 0x%x\n", intel_crtc ->pipe, scaler_user, *scaler_id, scaler_state->scaler_users ) |
| 6111 | "Staged freeing scaler id %d scaler_users = 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "Staged freeing scaler id %d scaler_users = 0x%x\n", intel_crtc ->pipe, scaler_user, *scaler_id, scaler_state->scaler_users ) |
| 6112 | intel_crtc->pipe, scaler_user, *scaler_id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "Staged freeing scaler id %d scaler_users = 0x%x\n", intel_crtc ->pipe, scaler_user, *scaler_id, scaler_state->scaler_users ) |
| 6113 | scaler_state->scaler_users)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "Staged freeing scaler id %d scaler_users = 0x%x\n", intel_crtc ->pipe, scaler_user, *scaler_id, scaler_state->scaler_users ); |
| 6114 | *scaler_id = -1; |
| 6115 | } |
| 6116 | return 0; |
| 6117 | } |
| 6118 | |
| 6119 | if (format && intel_format_info_is_yuv_semiplanar(format, modifier) && |
| 6120 | (src_h < SKL_MIN_YUV_420_SRC_H16 || src_w < SKL_MIN_YUV_420_SRC_W16)) { |
| 6121 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Planar YUV: src dimensions not met\n" ) |
| 6122 | "Planar YUV: src dimensions not met\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Planar YUV: src dimensions not met\n" ); |
| 6123 | return -EINVAL22; |
| 6124 | } |
| 6125 | |
| 6126 | /* range checks */ |
| 6127 | if (src_w < SKL_MIN_SRC_W8 || src_h < SKL_MIN_SRC_H8 || |
| 6128 | dst_w < SKL_MIN_DST_W8 || dst_h < SKL_MIN_DST_H8 || |
| 6129 | (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11 && |
| 6130 | (src_w > ICL_MAX_SRC_W5120 || src_h > ICL_MAX_SRC_H4096 || |
| 6131 | dst_w > ICL_MAX_DST_W5120 || dst_h > ICL_MAX_DST_H4096)) || |
| 6132 | (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 11 && |
| 6133 | (src_w > SKL_MAX_SRC_W4096 || src_h > SKL_MAX_SRC_H4096 || |
| 6134 | dst_w > SKL_MAX_DST_W4096 || dst_h > SKL_MAX_DST_H4096))) { |
| 6135 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: src %ux%u dst %ux%u " "size is out of scaler range\n", intel_crtc->pipe, scaler_user , src_w, src_h, dst_w, dst_h) |
| 6136 | "scaler_user index %u.%u: src %ux%u dst %ux%u "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: src %ux%u dst %ux%u " "size is out of scaler range\n", intel_crtc->pipe, scaler_user , src_w, src_h, dst_w, dst_h) |
| 6137 | "size is out of scaler range\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: src %ux%u dst %ux%u " "size is out of scaler range\n", intel_crtc->pipe, scaler_user , src_w, src_h, dst_w, dst_h) |
| 6138 | intel_crtc->pipe, scaler_user, src_w, src_h,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: src %ux%u dst %ux%u " "size is out of scaler range\n", intel_crtc->pipe, scaler_user , src_w, src_h, dst_w, dst_h) |
| 6139 | dst_w, dst_h)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: src %ux%u dst %ux%u " "size is out of scaler range\n", intel_crtc->pipe, scaler_user , src_w, src_h, dst_w, dst_h); |
| 6140 | return -EINVAL22; |
| 6141 | } |
| 6142 | |
| 6143 | /* mark this plane as a scaler user in crtc_state */ |
| 6144 | scaler_state->scaler_users |= (1 << scaler_user); |
| 6145 | drm_dbg_kms(&dev_priv->drm, "scaler_user index %u.%u: "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n" , intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h , scaler_state->scaler_users) |
| 6146 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n" , intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h , scaler_state->scaler_users) |
| 6147 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n" , intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h , scaler_state->scaler_users) |
| 6148 | scaler_state->scaler_users)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "scaler_user index %u.%u: " "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n" , intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h , scaler_state->scaler_users); |
| 6149 | |
| 6150 | return 0; |
| 6151 | } |
| 6152 | |
| 6153 | static int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state) |
| 6154 | { |
| 6155 | const struct drm_display_mode *adjusted_mode = |
| 6156 | &crtc_state->hw.adjusted_mode; |
| 6157 | int width, height; |
| 6158 | |
| 6159 | if (crtc_state->pch_pfit.enabled) { |
| 6160 | width = drm_rect_width(&crtc_state->pch_pfit.dst); |
| 6161 | height = drm_rect_height(&crtc_state->pch_pfit.dst); |
| 6162 | } else { |
| 6163 | width = adjusted_mode->crtc_hdisplay; |
| 6164 | height = adjusted_mode->crtc_vdisplay; |
| 6165 | } |
| 6166 | |
| 6167 | return skl_update_scaler(crtc_state, !crtc_state->hw.active, |
| 6168 | SKL_CRTC_INDEX31, |
| 6169 | &crtc_state->scaler_state.scaler_id, |
| 6170 | crtc_state->pipe_src_w, crtc_state->pipe_src_h, |
| 6171 | width, height, NULL((void *)0), 0, |
| 6172 | crtc_state->pch_pfit.enabled); |
| 6173 | } |
| 6174 | |
| 6175 | /** |
| 6176 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. |
| 6177 | * @crtc_state: crtc's scaler state |
| 6178 | * @plane_state: atomic plane state to update |
| 6179 | * |
| 6180 | * Return |
| 6181 | * 0 - scaler_usage updated successfully |
| 6182 | * error - requested scaling cannot be supported or other error condition |
| 6183 | */ |
| 6184 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
| 6185 | struct intel_plane_state *plane_state) |
| 6186 | { |
| 6187 | struct intel_plane *intel_plane = |
| 6188 | to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 6189 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_plane->base.dev); |
| 6190 | struct drm_framebuffer *fb = plane_state->hw.fb; |
| 6191 | int ret; |
| 6192 | bool_Bool force_detach = !fb || !plane_state->uapi.visible; |
| 6193 | bool_Bool need_scaler = false0; |
| 6194 | |
| 6195 | /* Pre-gen11 and SDR planes always need a scaler for planar formats. */ |
| 6196 | if (!icl_is_hdr_plane(dev_priv, intel_plane->id) && |
| 6197 | fb && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) |
| 6198 | need_scaler = true1; |
| 6199 | |
| 6200 | ret = skl_update_scaler(crtc_state, force_detach, |
| 6201 | drm_plane_index(&intel_plane->base), |
| 6202 | &plane_state->scaler_id, |
| 6203 | drm_rect_width(&plane_state->uapi.src) >> 16, |
| 6204 | drm_rect_height(&plane_state->uapi.src) >> 16, |
| 6205 | drm_rect_width(&plane_state->uapi.dst), |
| 6206 | drm_rect_height(&plane_state->uapi.dst), |
| 6207 | fb ? fb->format : NULL((void *)0), |
| 6208 | fb ? fb->modifier : 0, |
| 6209 | need_scaler); |
| 6210 | |
| 6211 | if (ret || plane_state->scaler_id < 0) |
| 6212 | return ret; |
| 6213 | |
| 6214 | /* check colorkey */ |
| 6215 | if (plane_state->ckey.flags) { |
| 6216 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] scaling with color key not allowed" , intel_plane->base.base.id, intel_plane->base.name) |
| 6217 | "[PLANE:%d:%s] scaling with color key not allowed",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] scaling with color key not allowed" , intel_plane->base.base.id, intel_plane->base.name) |
| 6218 | intel_plane->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] scaling with color key not allowed" , intel_plane->base.base.id, intel_plane->base.name) |
| 6219 | intel_plane->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] scaling with color key not allowed" , intel_plane->base.base.id, intel_plane->base.name); |
| 6220 | return -EINVAL22; |
| 6221 | } |
| 6222 | |
| 6223 | /* Check src format */ |
| 6224 | switch (fb->format->format) { |
| 6225 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 6226 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 6227 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 6228 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 6229 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 6230 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 6231 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 6232 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 6233 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 6234 | case DRM_FORMAT_YUYV((__u32)('Y') | ((__u32)('U') << 8) | ((__u32)('Y') << 16) | ((__u32)('V') << 24)): |
| 6235 | case DRM_FORMAT_YVYU((__u32)('Y') | ((__u32)('V') << 8) | ((__u32)('Y') << 16) | ((__u32)('U') << 24)): |
| 6236 | case DRM_FORMAT_UYVY((__u32)('U') | ((__u32)('Y') << 8) | ((__u32)('V') << 16) | ((__u32)('Y') << 24)): |
| 6237 | case DRM_FORMAT_VYUY((__u32)('V') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('Y') << 24)): |
| 6238 | case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 6239 | case DRM_FORMAT_XYUV8888((__u32)('X') | ((__u32)('Y') << 8) | ((__u32)('U') << 16) | ((__u32)('V') << 24)): |
| 6240 | case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)): |
| 6241 | case DRM_FORMAT_P012((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 6242 | case DRM_FORMAT_P016((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 6243 | case DRM_FORMAT_Y210((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('0') << 24)): |
| 6244 | case DRM_FORMAT_Y212((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('2') << 24)): |
| 6245 | case DRM_FORMAT_Y216((__u32)('Y') | ((__u32)('2') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 6246 | case DRM_FORMAT_XVYU2101010((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 6247 | case DRM_FORMAT_XVYU12_16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('3') << 16) | ((__u32)('6') << 24)): |
| 6248 | case DRM_FORMAT_XVYU16161616((__u32)('X') | ((__u32)('V') << 8) | ((__u32)('4') << 16) | ((__u32)('8') << 24)): |
| 6249 | break; |
| 6250 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 6251 | case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 6252 | case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 6253 | case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 6254 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 6255 | break; |
| 6256 | fallthroughdo {} while (0); |
| 6257 | default: |
| 6258 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n" , intel_plane->base.base.id, intel_plane->base.name, fb ->base.id, fb->format->format) |
| 6259 | "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n" , intel_plane->base.base.id, intel_plane->base.name, fb ->base.id, fb->format->format) |
| 6260 | intel_plane->base.base.id, intel_plane->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n" , intel_plane->base.base.id, intel_plane->base.name, fb ->base.id, fb->format->format) |
| 6261 | fb->base.id, fb->format->format)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n" , intel_plane->base.base.id, intel_plane->base.name, fb ->base.id, fb->format->format); |
| 6262 | return -EINVAL22; |
| 6263 | } |
| 6264 | |
| 6265 | return 0; |
| 6266 | } |
| 6267 | |
| 6268 | void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state) |
| 6269 | { |
| 6270 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6271 | int i; |
| 6272 | |
| 6273 | for (i = 0; i < crtc->num_scalers; i++) |
| 6274 | skl_detach_scaler(crtc, i); |
| 6275 | } |
| 6276 | |
| 6277 | static void skl_pfit_enable(const struct intel_crtc_state *crtc_state) |
| 6278 | { |
| 6279 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6280 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 6281 | const struct intel_crtc_scaler_state *scaler_state = |
| 6282 | &crtc_state->scaler_state; |
| 6283 | struct drm_rect src = { |
| 6284 | .x2 = crtc_state->pipe_src_w << 16, |
| 6285 | .y2 = crtc_state->pipe_src_h << 16, |
| 6286 | }; |
| 6287 | const struct drm_rect *dst = &crtc_state->pch_pfit.dst; |
| 6288 | u16 uv_rgb_hphase, uv_rgb_vphase; |
| 6289 | enum pipe pipe = crtc->pipe; |
| 6290 | int width = drm_rect_width(dst); |
| 6291 | int height = drm_rect_height(dst); |
| 6292 | int x = dst->x1; |
| 6293 | int y = dst->y1; |
| 6294 | int hscale, vscale; |
| 6295 | unsigned long irqflags; |
| 6296 | int id; |
| 6297 | |
| 6298 | if (!crtc_state->pch_pfit.enabled) |
| 6299 | return; |
| 6300 | |
| 6301 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((crtc_state->scaler_state.scaler_id < 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "crtc_state->scaler_state.scaler_id < 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 6302 | crtc_state->scaler_state.scaler_id < 0)({ int __ret = !!((crtc_state->scaler_state.scaler_id < 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "crtc_state->scaler_state.scaler_id < 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 6303 | return; |
| 6304 | |
| 6305 | hscale = drm_rect_calc_hscale(&src, dst, 0, INT_MAX0x7fffffff); |
| 6306 | vscale = drm_rect_calc_vscale(&src, dst, 0, INT_MAX0x7fffffff); |
| 6307 | |
| 6308 | uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false0); |
| 6309 | uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false0); |
| 6310 | |
| 6311 | id = scaler_state->scaler_id; |
| 6312 | |
| 6313 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); } while (0); |
| 6314 | |
| 6315 | intel_de_write_fw(dev_priv, SKL_PS_CTRL(pipe, id)((const i915_reg_t){ .reg = (((((0x68180) + (id) * ((0x68280) - (0x68180)))) + (pipe) * ((((0x68980) + (id) * ((0x68A80) - (0x68980)))) - (((0x68180) + (id) * ((0x68280) - (0x68180))) )))) }), PS_SCALER_EN(1 << 31) | |
| 6316 | PS_FILTER_MEDIUM(0 << 23) | scaler_state->scalers[id].mode); |
| 6317 | intel_de_write_fw(dev_priv, SKL_PS_VPHASE(pipe, id)((const i915_reg_t){ .reg = (((((0x68188) + (id) * ((0x68288) - (0x68188)))) + (pipe) * ((((0x68988) + (id) * ((0x68A88) - (0x68988)))) - (((0x68188) + (id) * ((0x68288) - (0x68188))) )))) }), |
| 6318 | PS_Y_PHASE(0)((0) << 16) | PS_UV_RGB_PHASE(uv_rgb_vphase)((uv_rgb_vphase) << 0)); |
| 6319 | intel_de_write_fw(dev_priv, SKL_PS_HPHASE(pipe, id)((const i915_reg_t){ .reg = (((((0x68194) + (id) * ((0x68294) - (0x68194)))) + (pipe) * ((((0x68994) + (id) * ((0x68A94) - (0x68994)))) - (((0x68194) + (id) * ((0x68294) - (0x68194))) )))) }), |
| 6320 | PS_Y_PHASE(0)((0) << 16) | PS_UV_RGB_PHASE(uv_rgb_hphase)((uv_rgb_hphase) << 0)); |
| 6321 | intel_de_write_fw(dev_priv, SKL_PS_WIN_POS(pipe, id)((const i915_reg_t){ .reg = (((((0x68170) + (id) * ((0x68270) - (0x68170)))) + (pipe) * ((((0x68970) + (id) * ((0x68A70) - (0x68970)))) - (((0x68170) + (id) * ((0x68270) - (0x68170))) )))) }), |
| 6322 | x << 16 | y); |
| 6323 | intel_de_write_fw(dev_priv, SKL_PS_WIN_SZ(pipe, id)((const i915_reg_t){ .reg = (((((0x68174) + (id) * ((0x68274) - (0x68174)))) + (pipe) * ((((0x68974) + (id) * ((0x68A74) - (0x68974)))) - (((0x68174) + (id) * ((0x68274) - (0x68174))) )))) }), |
| 6324 | width << 16 | height); |
| 6325 | |
| 6326 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock ); } while (0); |
| 6327 | } |
| 6328 | |
| 6329 | static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state) |
| 6330 | { |
| 6331 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6332 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 6333 | const struct drm_rect *dst = &crtc_state->pch_pfit.dst; |
| 6334 | enum pipe pipe = crtc->pipe; |
| 6335 | int width = drm_rect_width(dst); |
| 6336 | int height = drm_rect_height(dst); |
| 6337 | int x = dst->x1; |
| 6338 | int y = dst->y1; |
| 6339 | |
| 6340 | if (!crtc_state->pch_pfit.enabled) |
| 6341 | return; |
| 6342 | |
| 6343 | /* Force use of hard-coded filter coefficients |
| 6344 | * as some pre-programmed values are broken, |
| 6345 | * e.g. x201. |
| 6346 | */ |
| 6347 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 6348 | intel_de_write(dev_priv, PF_CTL(pipe)((const i915_reg_t){ .reg = (((0x68080) + (pipe) * ((0x68880) - (0x68080)))) }), PF_ENABLE(1 << 31) | |
| 6349 | PF_FILTER_MED_3x3(1 << 23) | PF_PIPE_SEL_IVB(pipe)((pipe) << 29)); |
| 6350 | else |
| 6351 | intel_de_write(dev_priv, PF_CTL(pipe)((const i915_reg_t){ .reg = (((0x68080) + (pipe) * ((0x68880) - (0x68080)))) }), PF_ENABLE(1 << 31) | |
| 6352 | PF_FILTER_MED_3x3(1 << 23)); |
| 6353 | intel_de_write(dev_priv, PF_WIN_POS(pipe)((const i915_reg_t){ .reg = (((0x68070) + (pipe) * ((0x68870) - (0x68070)))) }), x << 16 | y); |
| 6354 | intel_de_write(dev_priv, PF_WIN_SZ(pipe)((const i915_reg_t){ .reg = (((0x68074) + (pipe) * ((0x68874) - (0x68074)))) }), width << 16 | height); |
| 6355 | } |
| 6356 | |
| 6357 | void hsw_enable_ips(const struct intel_crtc_state *crtc_state) |
| 6358 | { |
| 6359 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6360 | struct drm_device *dev = crtc->base.dev; |
| 6361 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 6362 | |
| 6363 | if (!crtc_state->ips_enabled) |
| 6364 | return; |
| 6365 | |
| 6366 | /* |
| 6367 | * We can only enable IPS after we enable a plane and wait for a vblank |
| 6368 | * This function is called from post_plane_update, which is run after |
| 6369 | * a vblank wait. |
| 6370 | */ |
| 6371 | drm_WARN_ON(dev, !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))({ int __ret = !!((!(crtc_state->active_planes & ~(1UL << (PLANE_CURSOR))))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "!(crtc_state->active_planes & ~(1UL << (PLANE_CURSOR)))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 6372 | |
| 6373 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 6374 | drm_WARN_ON(dev, sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,({ int __ret = !!((sandybridge_pcode_write_timeout(dev_priv, 0x19 , (1 << 31) | (1 << 30), 500, 0))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "sandybridge_pcode_write_timeout(dev_priv, 0x19, (1 << 31) | (1 << 30), 500, 0)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 6375 | IPS_ENABLE | IPS_PCODE_CONTROL))({ int __ret = !!((sandybridge_pcode_write_timeout(dev_priv, 0x19 , (1 << 31) | (1 << 30), 500, 0))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "sandybridge_pcode_write_timeout(dev_priv, 0x19, (1 << 31) | (1 << 30), 500, 0)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 6376 | /* Quoting Art Runyan: "its not safe to expect any particular |
| 6377 | * value in IPS_CTL bit 31 after enabling IPS through the |
| 6378 | * mailbox." Moreover, the mailbox may return a bogus state, |
| 6379 | * so we need to just enable it and continue on. |
| 6380 | */ |
| 6381 | } else { |
| 6382 | intel_de_write(dev_priv, IPS_CTL((const i915_reg_t){ .reg = (0x43408) }), IPS_ENABLE(1 << 31)); |
| 6383 | /* The bit only becomes 1 in the next vblank, so this wait here |
| 6384 | * is essentially intel_wait_for_vblank. If we don't have this |
| 6385 | * and don't wait for vblanks until the end of crtc_enable, then |
| 6386 | * the HW state readout code will complain that the expected |
| 6387 | * IPS_CTL value is not the one we read. */ |
| 6388 | if (intel_de_wait_for_set(dev_priv, IPS_CTL((const i915_reg_t){ .reg = (0x43408) }), IPS_ENABLE(1 << 31), 50)) |
| 6389 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for IPS enable\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 6390 | "Timed out waiting for IPS enable\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for IPS enable\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 6391 | } |
| 6392 | } |
| 6393 | |
| 6394 | void hsw_disable_ips(const struct intel_crtc_state *crtc_state) |
| 6395 | { |
| 6396 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6397 | struct drm_device *dev = crtc->base.dev; |
| 6398 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 6399 | |
| 6400 | if (!crtc_state->ips_enabled) |
| 6401 | return; |
| 6402 | |
| 6403 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 6404 | drm_WARN_ON(dev,({ int __ret = !!((sandybridge_pcode_write_timeout(dev_priv, 0x19 , 0, 500, 0))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((dev))->dev), "", "drm_WARN_ON(" "sandybridge_pcode_write_timeout(dev_priv, 0x19, 0, 500, 0)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 6405 | sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0))({ int __ret = !!((sandybridge_pcode_write_timeout(dev_priv, 0x19 , 0, 500, 0))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((dev))->dev), "", "drm_WARN_ON(" "sandybridge_pcode_write_timeout(dev_priv, 0x19, 0, 500, 0)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 6406 | /* |
| 6407 | * Wait for PCODE to finish disabling IPS. The BSpec specified |
| 6408 | * 42ms timeout value leads to occasional timeouts so use 100ms |
| 6409 | * instead. |
| 6410 | */ |
| 6411 | if (intel_de_wait_for_clear(dev_priv, IPS_CTL((const i915_reg_t){ .reg = (0x43408) }), IPS_ENABLE(1 << 31), 100)) |
| 6412 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for IPS disable\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 6413 | "Timed out waiting for IPS disable\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for IPS disable\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 6414 | } else { |
| 6415 | intel_de_write(dev_priv, IPS_CTL((const i915_reg_t){ .reg = (0x43408) }), 0); |
| 6416 | intel_de_posting_read(dev_priv, IPS_CTL((const i915_reg_t){ .reg = (0x43408) })); |
| 6417 | } |
| 6418 | |
| 6419 | /* We need to wait for a vblank before we can disable the plane. */ |
| 6420 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
| 6421 | } |
| 6422 | |
| 6423 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
| 6424 | { |
| 6425 | if (intel_crtc->overlay) |
| 6426 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
| 6427 | |
| 6428 | /* Let userspace switch the overlay on again. In most cases userspace |
| 6429 | * has to recompute where to put it anyway. |
| 6430 | */ |
| 6431 | } |
| 6432 | |
| 6433 | static bool_Bool hsw_pre_update_disable_ips(const struct intel_crtc_state *old_crtc_state, |
| 6434 | const struct intel_crtc_state *new_crtc_state) |
| 6435 | { |
| 6436 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6437 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 6438 | |
| 6439 | if (!old_crtc_state->ips_enabled) |
| 6440 | return false0; |
| 6441 | |
| 6442 | if (needs_modeset(new_crtc_state)) |
| 6443 | return true1; |
| 6444 | |
| 6445 | /* |
| 6446 | * Workaround : Do not read or write the pipe palette/gamma data while |
| 6447 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 6448 | * |
| 6449 | * Disable IPS before we program the LUT. |
| 6450 | */ |
| 6451 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && |
| 6452 | (new_crtc_state->uapi.color_mgmt_changed || |
| 6453 | new_crtc_state->update_pipe) && |
| 6454 | new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT(3 << 0)) |
| 6455 | return true1; |
| 6456 | |
| 6457 | return !new_crtc_state->ips_enabled; |
| 6458 | } |
| 6459 | |
| 6460 | static bool_Bool hsw_post_update_enable_ips(const struct intel_crtc_state *old_crtc_state, |
| 6461 | const struct intel_crtc_state *new_crtc_state) |
| 6462 | { |
| 6463 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6464 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 6465 | |
| 6466 | if (!new_crtc_state->ips_enabled) |
| 6467 | return false0; |
| 6468 | |
| 6469 | if (needs_modeset(new_crtc_state)) |
| 6470 | return true1; |
| 6471 | |
| 6472 | /* |
| 6473 | * Workaround : Do not read or write the pipe palette/gamma data while |
| 6474 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. |
| 6475 | * |
| 6476 | * Re-enable IPS after the LUT has been programmed. |
| 6477 | */ |
| 6478 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && |
| 6479 | (new_crtc_state->uapi.color_mgmt_changed || |
| 6480 | new_crtc_state->update_pipe) && |
| 6481 | new_crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT(3 << 0)) |
| 6482 | return true1; |
| 6483 | |
| 6484 | /* |
| 6485 | * We can't read out IPS on broadwell, assume the worst and |
| 6486 | * forcibly enable IPS on the first fastset. |
| 6487 | */ |
| 6488 | if (new_crtc_state->update_pipe && old_crtc_state->inherited) |
| 6489 | return true1; |
| 6490 | |
| 6491 | return !old_crtc_state->ips_enabled; |
| 6492 | } |
| 6493 | |
| 6494 | static bool_Bool needs_nv12_wa(const struct intel_crtc_state *crtc_state) |
| 6495 | { |
| 6496 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 6497 | |
| 6498 | if (!crtc_state->nv12_planes) |
| 6499 | return false0; |
| 6500 | |
| 6501 | /* WA Display #0827: Gen9:all */ |
| 6502 | if (IS_GEN(dev_priv, 9)(0 + (&(dev_priv)->__info)->gen == (9)) && !IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) |
| 6503 | return true1; |
| 6504 | |
| 6505 | return false0; |
| 6506 | } |
| 6507 | |
| 6508 | static bool_Bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state) |
| 6509 | { |
| 6510 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 6511 | |
| 6512 | /* Wa_2006604312:icl,ehl */ |
| 6513 | if (crtc_state->scaler_state.scaler_users > 0 && IS_GEN(dev_priv, 11)(0 + (&(dev_priv)->__info)->gen == (11))) |
| 6514 | return true1; |
| 6515 | |
| 6516 | return false0; |
| 6517 | } |
| 6518 | |
| 6519 | static bool_Bool planes_enabling(const struct intel_crtc_state *old_crtc_state, |
| 6520 | const struct intel_crtc_state *new_crtc_state) |
| 6521 | { |
| 6522 | return (!old_crtc_state->active_planes || needs_modeset(new_crtc_state)) && |
| 6523 | new_crtc_state->active_planes; |
| 6524 | } |
| 6525 | |
| 6526 | static bool_Bool planes_disabling(const struct intel_crtc_state *old_crtc_state, |
| 6527 | const struct intel_crtc_state *new_crtc_state) |
| 6528 | { |
| 6529 | return old_crtc_state->active_planes && |
| 6530 | (!new_crtc_state->active_planes || needs_modeset(new_crtc_state)); |
| 6531 | } |
| 6532 | |
| 6533 | static void intel_post_plane_update(struct intel_atomic_state *state, |
| 6534 | struct intel_crtc *crtc) |
| 6535 | { |
| 6536 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 6537 | const struct intel_crtc_state *old_crtc_state = |
| 6538 | intel_atomic_get_old_crtc_state(state, crtc); |
| 6539 | const struct intel_crtc_state *new_crtc_state = |
| 6540 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6541 | enum pipe pipe = crtc->pipe; |
| 6542 | |
| 6543 | intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits); |
| 6544 | |
| 6545 | if (new_crtc_state->update_wm_post && new_crtc_state->hw.active) |
| 6546 | intel_update_watermarks(crtc); |
| 6547 | |
| 6548 | if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state)) |
| 6549 | hsw_enable_ips(new_crtc_state); |
| 6550 | |
| 6551 | intel_fbc_post_update(state, crtc); |
| 6552 | |
| 6553 | if (needs_nv12_wa(old_crtc_state) && |
| 6554 | !needs_nv12_wa(new_crtc_state)) |
| 6555 | skl_wa_827(dev_priv, pipe, false0); |
| 6556 | |
| 6557 | if (needs_scalerclk_wa(old_crtc_state) && |
| 6558 | !needs_scalerclk_wa(new_crtc_state)) |
| 6559 | icl_wa_scalerclkgating(dev_priv, pipe, false0); |
| 6560 | } |
| 6561 | |
| 6562 | static void intel_pre_plane_update(struct intel_atomic_state *state, |
| 6563 | struct intel_crtc *crtc) |
| 6564 | { |
| 6565 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 6566 | const struct intel_crtc_state *old_crtc_state = |
| 6567 | intel_atomic_get_old_crtc_state(state, crtc); |
| 6568 | const struct intel_crtc_state *new_crtc_state = |
| 6569 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6570 | enum pipe pipe = crtc->pipe; |
| 6571 | |
| 6572 | if (hsw_pre_update_disable_ips(old_crtc_state, new_crtc_state)) |
| 6573 | hsw_disable_ips(old_crtc_state); |
| 6574 | |
| 6575 | if (intel_fbc_pre_update(state, crtc)) |
| 6576 | intel_wait_for_vblank(dev_priv, pipe); |
| 6577 | |
| 6578 | /* Display WA 827 */ |
| 6579 | if (!needs_nv12_wa(old_crtc_state) && |
| 6580 | needs_nv12_wa(new_crtc_state)) |
| 6581 | skl_wa_827(dev_priv, pipe, true1); |
| 6582 | |
| 6583 | /* Wa_2006604312:icl,ehl */ |
| 6584 | if (!needs_scalerclk_wa(old_crtc_state) && |
| 6585 | needs_scalerclk_wa(new_crtc_state)) |
| 6586 | icl_wa_scalerclkgating(dev_priv, pipe, true1); |
| 6587 | |
| 6588 | /* |
| 6589 | * Vblank time updates from the shadow to live plane control register |
| 6590 | * are blocked if the memory self-refresh mode is active at that |
| 6591 | * moment. So to make sure the plane gets truly disabled, disable |
| 6592 | * first the self-refresh mode. The self-refresh enable bit in turn |
| 6593 | * will be checked/applied by the HW only at the next frame start |
| 6594 | * event which is after the vblank start event, so we need to have a |
| 6595 | * wait-for-vblank between disabling the plane and the pipe. |
| 6596 | */ |
| 6597 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && old_crtc_state->hw.active && |
| 6598 | new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false0)) |
| 6599 | intel_wait_for_vblank(dev_priv, pipe); |
| 6600 | |
| 6601 | /* |
| 6602 | * IVB workaround: must disable low power watermarks for at least |
| 6603 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 6604 | * when scaling is disabled. |
| 6605 | * |
| 6606 | * WaCxSRDisabledForSpriteScaling:ivb |
| 6607 | */ |
| 6608 | if (old_crtc_state->hw.active && |
| 6609 | new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv)) |
| 6610 | intel_wait_for_vblank(dev_priv, pipe); |
| 6611 | |
| 6612 | /* |
| 6613 | * If we're doing a modeset we don't need to do any |
| 6614 | * pre-vblank watermark programming here. |
| 6615 | */ |
| 6616 | if (!needs_modeset(new_crtc_state)) { |
| 6617 | /* |
| 6618 | * For platforms that support atomic watermarks, program the |
| 6619 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these |
| 6620 | * will be the intermediate values that are safe for both pre- and |
| 6621 | * post- vblank; when vblank happens, the 'active' values will be set |
| 6622 | * to the final 'target' values and we'll do this again to get the |
| 6623 | * optimal watermarks. For gen9+ platforms, the values we program here |
| 6624 | * will be the final target values which will get automatically latched |
| 6625 | * at vblank time; no further programming will be necessary. |
| 6626 | * |
| 6627 | * If a platform hasn't been transitioned to atomic watermarks yet, |
| 6628 | * we'll continue to update watermarks the old way, if flags tell |
| 6629 | * us to. |
| 6630 | */ |
| 6631 | if (dev_priv->display.initial_watermarks) |
| 6632 | dev_priv->display.initial_watermarks(state, crtc); |
| 6633 | else if (new_crtc_state->update_wm_pre) |
| 6634 | intel_update_watermarks(crtc); |
| 6635 | } |
| 6636 | |
| 6637 | /* |
| 6638 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 6639 | * So disable underrun reporting before all the planes get disabled. |
| 6640 | * |
| 6641 | * We do this after .initial_watermarks() so that we have a |
| 6642 | * chance of catching underruns with the intermediate watermarks |
| 6643 | * vs. the old plane configuration. |
| 6644 | */ |
| 6645 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) && planes_disabling(old_crtc_state, new_crtc_state)) |
| 6646 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false0); |
| 6647 | } |
| 6648 | |
| 6649 | static void intel_crtc_disable_planes(struct intel_atomic_state *state, |
| 6650 | struct intel_crtc *crtc) |
| 6651 | { |
| 6652 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 6653 | const struct intel_crtc_state *new_crtc_state = |
| 6654 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6655 | unsigned int update_mask = new_crtc_state->update_planes; |
| 6656 | const struct intel_plane_state *old_plane_state; |
| 6657 | struct intel_plane *plane; |
| 6658 | unsigned fb_bits = 0; |
| 6659 | int i; |
| 6660 | |
| 6661 | intel_crtc_dpms_overlay_disable(crtc); |
| 6662 | |
| 6663 | for_each_old_intel_plane_in_state(state, plane, old_plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (old_plane_state) = ({ const __typeof ( ((struct intel_plane_state *)0)->uapi ) *__mptr = ((state )->base.planes[i].old_state); (struct intel_plane_state *) ( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}), 1); (i)++) if (!(plane)) {} else { |
| 6664 | if (crtc->pipe != plane->pipe || |
| 6665 | !(update_mask & BIT(plane->id)(1UL << (plane->id)))) |
| 6666 | continue; |
| 6667 | |
| 6668 | intel_disable_plane(plane, new_crtc_state); |
| 6669 | |
| 6670 | if (old_plane_state->uapi.visible) |
| 6671 | fb_bits |= plane->frontbuffer_bit; |
| 6672 | } |
| 6673 | |
| 6674 | intel_frontbuffer_flip(dev_priv, fb_bits); |
| 6675 | } |
| 6676 | |
| 6677 | /* |
| 6678 | * intel_connector_primary_encoder - get the primary encoder for a connector |
| 6679 | * @connector: connector for which to return the encoder |
| 6680 | * |
| 6681 | * Returns the primary encoder for a connector. There is a 1:1 mapping from |
| 6682 | * all connectors to their encoder, except for DP-MST connectors which have |
| 6683 | * both a virtual and a primary encoder. These DP-MST primary encoders can be |
| 6684 | * pointed to by as many DP-MST connectors as there are pipes. |
| 6685 | */ |
| 6686 | static struct intel_encoder * |
| 6687 | intel_connector_primary_encoder(struct intel_connector *connector) |
| 6688 | { |
| 6689 | struct intel_encoder *encoder; |
| 6690 | |
| 6691 | if (connector->mst_port) |
| 6692 | return &dp_to_dig_port(connector->mst_port)->base; |
| 6693 | |
| 6694 | encoder = intel_attached_encoder(connector); |
| 6695 | drm_WARN_ON(connector->base.dev, !encoder)({ int __ret = !!((!encoder)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((connector->base.dev))->dev), "", "drm_WARN_ON(" "!encoder" ")"); __builtin_expect(!!(__ret), 0); }); |
| 6696 | |
| 6697 | return encoder; |
| 6698 | } |
| 6699 | |
| 6700 | static void intel_encoders_update_prepare(struct intel_atomic_state *state) |
| 6701 | { |
| 6702 | struct drm_connector_state *new_conn_state; |
| 6703 | struct drm_connector *connector; |
| 6704 | int i; |
| 6705 | |
| 6706 | for_each_new_connector_in_state(&state->base, connector, new_conn_state,for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (new_conn_state) = (&state->base)-> connectors[i].new_state, (void)(new_conn_state) , 1))) {} else |
| 6707 | i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (new_conn_state) = (&state->base)-> connectors[i].new_state, (void)(new_conn_state) , 1))) {} else { |
| 6708 | struct intel_connector *intel_connector; |
| 6709 | struct intel_encoder *encoder; |
| 6710 | struct intel_crtc *crtc; |
| 6711 | |
| 6712 | if (!intel_connector_needs_modeset(state, connector)) |
| 6713 | continue; |
| 6714 | |
| 6715 | intel_connector = to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );}); |
| 6716 | encoder = intel_connector_primary_encoder(intel_connector); |
| 6717 | if (!encoder->update_prepare) |
| 6718 | continue; |
| 6719 | |
| 6720 | crtc = new_conn_state->crtc ? |
| 6721 | to_intel_crtc(new_conn_state->crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_conn_state->crtc); (struct intel_crtc *)( (char *) __mptr - __builtin_offsetof(struct intel_crtc, base) );}) : NULL((void *)0); |
| 6722 | encoder->update_prepare(state, encoder, crtc); |
| 6723 | } |
| 6724 | } |
| 6725 | |
| 6726 | static void intel_encoders_update_complete(struct intel_atomic_state *state) |
| 6727 | { |
| 6728 | struct drm_connector_state *new_conn_state; |
| 6729 | struct drm_connector *connector; |
| 6730 | int i; |
| 6731 | |
| 6732 | for_each_new_connector_in_state(&state->base, connector, new_conn_state,for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (new_conn_state) = (&state->base)-> connectors[i].new_state, (void)(new_conn_state) , 1))) {} else |
| 6733 | i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (new_conn_state) = (&state->base)-> connectors[i].new_state, (void)(new_conn_state) , 1))) {} else { |
| 6734 | struct intel_connector *intel_connector; |
| 6735 | struct intel_encoder *encoder; |
| 6736 | struct intel_crtc *crtc; |
| 6737 | |
| 6738 | if (!intel_connector_needs_modeset(state, connector)) |
| 6739 | continue; |
| 6740 | |
| 6741 | intel_connector = to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );}); |
| 6742 | encoder = intel_connector_primary_encoder(intel_connector); |
| 6743 | if (!encoder->update_complete) |
| 6744 | continue; |
| 6745 | |
| 6746 | crtc = new_conn_state->crtc ? |
| 6747 | to_intel_crtc(new_conn_state->crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_conn_state->crtc); (struct intel_crtc *)( (char *) __mptr - __builtin_offsetof(struct intel_crtc, base) );}) : NULL((void *)0); |
| 6748 | encoder->update_complete(state, encoder, crtc); |
| 6749 | } |
| 6750 | } |
| 6751 | |
| 6752 | static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state, |
| 6753 | struct intel_crtc *crtc) |
| 6754 | { |
| 6755 | const struct intel_crtc_state *crtc_state = |
| 6756 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6757 | const struct drm_connector_state *conn_state; |
| 6758 | struct drm_connector *conn; |
| 6759 | int i; |
| 6760 | |
| 6761 | for_each_new_connector_in_state(&state->base, conn, conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
| 6762 | struct intel_encoder *encoder = |
| 6763 | to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6764 | |
| 6765 | if (conn_state->crtc != &crtc->base) |
| 6766 | continue; |
| 6767 | |
| 6768 | if (encoder->pre_pll_enable) |
| 6769 | encoder->pre_pll_enable(state, encoder, |
| 6770 | crtc_state, conn_state); |
| 6771 | } |
| 6772 | } |
| 6773 | |
| 6774 | static void intel_encoders_pre_enable(struct intel_atomic_state *state, |
| 6775 | struct intel_crtc *crtc) |
| 6776 | { |
| 6777 | const struct intel_crtc_state *crtc_state = |
| 6778 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6779 | const struct drm_connector_state *conn_state; |
| 6780 | struct drm_connector *conn; |
| 6781 | int i; |
| 6782 | |
| 6783 | for_each_new_connector_in_state(&state->base, conn, conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
| 6784 | struct intel_encoder *encoder = |
| 6785 | to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6786 | |
| 6787 | if (conn_state->crtc != &crtc->base) |
| 6788 | continue; |
| 6789 | |
| 6790 | if (encoder->pre_enable) |
| 6791 | encoder->pre_enable(state, encoder, |
| 6792 | crtc_state, conn_state); |
| 6793 | } |
| 6794 | } |
| 6795 | |
| 6796 | static void intel_encoders_enable(struct intel_atomic_state *state, |
| 6797 | struct intel_crtc *crtc) |
| 6798 | { |
| 6799 | const struct intel_crtc_state *crtc_state = |
| 6800 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6801 | const struct drm_connector_state *conn_state; |
| 6802 | struct drm_connector *conn; |
| 6803 | int i; |
| 6804 | |
| 6805 | for_each_new_connector_in_state(&state->base, conn, conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
| 6806 | struct intel_encoder *encoder = |
| 6807 | to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6808 | |
| 6809 | if (conn_state->crtc != &crtc->base) |
| 6810 | continue; |
| 6811 | |
| 6812 | if (encoder->enable) |
| 6813 | encoder->enable(state, encoder, |
| 6814 | crtc_state, conn_state); |
| 6815 | intel_opregion_notify_encoder(encoder, true1); |
| 6816 | } |
| 6817 | } |
| 6818 | |
| 6819 | static void intel_encoders_disable(struct intel_atomic_state *state, |
| 6820 | struct intel_crtc *crtc) |
| 6821 | { |
| 6822 | const struct intel_crtc_state *old_crtc_state = |
| 6823 | intel_atomic_get_old_crtc_state(state, crtc); |
| 6824 | const struct drm_connector_state *old_conn_state; |
| 6825 | struct drm_connector *conn; |
| 6826 | int i; |
| 6827 | |
| 6828 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (old_conn_state) = (&state->base)->connectors [i].old_state, 1))) {} else { |
| 6829 | struct intel_encoder *encoder = |
| 6830 | to_intel_encoder(old_conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (old_conn_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6831 | |
| 6832 | if (old_conn_state->crtc != &crtc->base) |
| 6833 | continue; |
| 6834 | |
| 6835 | intel_opregion_notify_encoder(encoder, false0); |
| 6836 | if (encoder->disable) |
| 6837 | encoder->disable(state, encoder, |
| 6838 | old_crtc_state, old_conn_state); |
| 6839 | } |
| 6840 | } |
| 6841 | |
| 6842 | static void intel_encoders_post_disable(struct intel_atomic_state *state, |
| 6843 | struct intel_crtc *crtc) |
| 6844 | { |
| 6845 | const struct intel_crtc_state *old_crtc_state = |
| 6846 | intel_atomic_get_old_crtc_state(state, crtc); |
| 6847 | const struct drm_connector_state *old_conn_state; |
| 6848 | struct drm_connector *conn; |
| 6849 | int i; |
| 6850 | |
| 6851 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (old_conn_state) = (&state->base)->connectors [i].old_state, 1))) {} else { |
| 6852 | struct intel_encoder *encoder = |
| 6853 | to_intel_encoder(old_conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (old_conn_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6854 | |
| 6855 | if (old_conn_state->crtc != &crtc->base) |
| 6856 | continue; |
| 6857 | |
| 6858 | if (encoder->post_disable) |
| 6859 | encoder->post_disable(state, encoder, |
| 6860 | old_crtc_state, old_conn_state); |
| 6861 | } |
| 6862 | } |
| 6863 | |
| 6864 | static void intel_encoders_post_pll_disable(struct intel_atomic_state *state, |
| 6865 | struct intel_crtc *crtc) |
| 6866 | { |
| 6867 | const struct intel_crtc_state *old_crtc_state = |
| 6868 | intel_atomic_get_old_crtc_state(state, crtc); |
| 6869 | const struct drm_connector_state *old_conn_state; |
| 6870 | struct drm_connector *conn; |
| 6871 | int i; |
| 6872 | |
| 6873 | for_each_old_connector_in_state(&state->base, conn, old_conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (old_conn_state) = (&state->base)->connectors [i].old_state, 1))) {} else { |
| 6874 | struct intel_encoder *encoder = |
| 6875 | to_intel_encoder(old_conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (old_conn_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6876 | |
| 6877 | if (old_conn_state->crtc != &crtc->base) |
| 6878 | continue; |
| 6879 | |
| 6880 | if (encoder->post_pll_disable) |
| 6881 | encoder->post_pll_disable(state, encoder, |
| 6882 | old_crtc_state, old_conn_state); |
| 6883 | } |
| 6884 | } |
| 6885 | |
| 6886 | static void intel_encoders_update_pipe(struct intel_atomic_state *state, |
| 6887 | struct intel_crtc *crtc) |
| 6888 | { |
| 6889 | const struct intel_crtc_state *crtc_state = |
| 6890 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6891 | const struct drm_connector_state *conn_state; |
| 6892 | struct drm_connector *conn; |
| 6893 | int i; |
| 6894 | |
| 6895 | for_each_new_connector_in_state(&state->base, conn, conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
| 6896 | struct intel_encoder *encoder = |
| 6897 | to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 6898 | |
| 6899 | if (conn_state->crtc != &crtc->base) |
| 6900 | continue; |
| 6901 | |
| 6902 | if (encoder->update_pipe) |
| 6903 | encoder->update_pipe(state, encoder, |
| 6904 | crtc_state, conn_state); |
| 6905 | } |
| 6906 | } |
| 6907 | |
| 6908 | static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state) |
| 6909 | { |
| 6910 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 6911 | struct intel_plane *plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 6912 | |
| 6913 | plane->disable_plane(plane, crtc_state); |
| 6914 | } |
| 6915 | |
| 6916 | static void ilk_crtc_enable(struct intel_atomic_state *state, |
| 6917 | struct intel_crtc *crtc) |
| 6918 | { |
| 6919 | const struct intel_crtc_state *new_crtc_state = |
| 6920 | intel_atomic_get_new_crtc_state(state, crtc); |
| 6921 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 6922 | enum pipe pipe = crtc->pipe; |
| 6923 | |
| 6924 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)({ int __ret = !!((crtc->active)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "crtc->active" ")"); __builtin_expect(!!( __ret), 0); })) |
| 6925 | return; |
| 6926 | |
| 6927 | /* |
| 6928 | * Sometimes spurious CPU pipe underruns happen during FDI |
| 6929 | * training, at least with VGA+HDMI cloning. Suppress them. |
| 6930 | * |
| 6931 | * On ILK we get an occasional spurious CPU pipe underruns |
| 6932 | * between eDP port A enable and vdd enable. Also PCH port |
| 6933 | * enable seems to result in the occasional CPU pipe underrun. |
| 6934 | * |
| 6935 | * Spurious PCH underruns also occur during PCH enabling. |
| 6936 | */ |
| 6937 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false0); |
| 6938 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false0); |
| 6939 | |
| 6940 | if (new_crtc_state->has_pch_encoder) |
| 6941 | intel_prepare_shared_dpll(new_crtc_state); |
| 6942 | |
| 6943 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
| 6944 | intel_dp_set_m_n(new_crtc_state, M1_N1); |
| 6945 | |
| 6946 | intel_set_pipe_timings(new_crtc_state); |
| 6947 | intel_set_pipe_src_size(new_crtc_state); |
| 6948 | |
| 6949 | if (new_crtc_state->has_pch_encoder) |
| 6950 | intel_cpu_transcoder_set_m_n(new_crtc_state, |
| 6951 | &new_crtc_state->fdi_m_n, NULL((void *)0)); |
| 6952 | |
| 6953 | ilk_set_pipeconf(new_crtc_state); |
| 6954 | |
| 6955 | crtc->active = true1; |
| 6956 | |
| 6957 | intel_encoders_pre_enable(state, crtc); |
| 6958 | |
| 6959 | if (new_crtc_state->has_pch_encoder) { |
| 6960 | /* Note: FDI PLL enabling _must_ be done before we enable the |
| 6961 | * cpu pipes, hence this is separate from all the other fdi/pch |
| 6962 | * enabling. */ |
| 6963 | ilk_fdi_pll_enable(new_crtc_state); |
| 6964 | } else { |
| 6965 | assert_fdi_tx_disabled(dev_priv, pipe)assert_fdi_tx(dev_priv, pipe, 0); |
| 6966 | assert_fdi_rx_disabled(dev_priv, pipe)assert_fdi_rx(dev_priv, pipe, 0); |
| 6967 | } |
| 6968 | |
| 6969 | ilk_pfit_enable(new_crtc_state); |
| 6970 | |
| 6971 | /* |
| 6972 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 6973 | * clocks enabled |
| 6974 | */ |
| 6975 | intel_color_load_luts(new_crtc_state); |
| 6976 | intel_color_commit(new_crtc_state); |
| 6977 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
| 6978 | intel_disable_primary_plane(new_crtc_state); |
| 6979 | |
| 6980 | if (dev_priv->display.initial_watermarks) |
| 6981 | dev_priv->display.initial_watermarks(state, crtc); |
| 6982 | intel_enable_pipe(new_crtc_state); |
| 6983 | |
| 6984 | if (new_crtc_state->has_pch_encoder) |
| 6985 | ilk_pch_enable(state, new_crtc_state); |
| 6986 | |
| 6987 | intel_crtc_vblank_on(new_crtc_state); |
| 6988 | |
| 6989 | intel_encoders_enable(state, crtc); |
| 6990 | |
| 6991 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) |
| 6992 | cpt_verify_modeset(dev_priv, pipe); |
| 6993 | |
| 6994 | /* |
| 6995 | * Must wait for vblank to avoid spurious PCH FIFO underruns. |
| 6996 | * And a second vblank wait is needed at least on ILK with |
| 6997 | * some interlaced HDMI modes. Let's do the double wait always |
| 6998 | * in case there are more corner cases we don't know about. |
| 6999 | */ |
| 7000 | if (new_crtc_state->has_pch_encoder) { |
| 7001 | intel_wait_for_vblank(dev_priv, pipe); |
| 7002 | intel_wait_for_vblank(dev_priv, pipe); |
| 7003 | } |
| 7004 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true1); |
| 7005 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true1); |
| 7006 | } |
| 7007 | |
| 7008 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 7009 | static bool_Bool hsw_crtc_supports_ips(struct intel_crtc *crtc) |
| 7010 | { |
| 7011 | return HAS_IPS(to_i915(crtc->base.dev))(IS_SUBPLATFORM(to_i915(crtc->base.dev), INTEL_HASWELL, (0 )) || IS_PLATFORM(to_i915(crtc->base.dev), INTEL_BROADWELL )) && crtc->pipe == PIPE_A; |
| 7012 | } |
| 7013 | |
| 7014 | static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 7015 | enum pipe pipe, bool_Bool apply) |
| 7016 | { |
| 7017 | u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) })); |
| 7018 | u32 mask = DPF_GATING_DIS(1 << 10) | DPF_RAM_GATING_DIS(1 << 9) | DPFR_GATING_DIS(1 << 8); |
| 7019 | |
| 7020 | if (apply) |
| 7021 | val |= mask; |
| 7022 | else |
| 7023 | val &= ~mask; |
| 7024 | |
| 7025 | intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe)((const i915_reg_t){ .reg = (((0x46520) + (pipe) * ((0x46524) - (0x46520)))) }), val); |
| 7026 | } |
| 7027 | |
| 7028 | static void icl_pipe_mbus_enable(struct intel_crtc *crtc) |
| 7029 | { |
| 7030 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7031 | enum pipe pipe = crtc->pipe; |
| 7032 | u32 val; |
| 7033 | |
| 7034 | val = MBUS_DBOX_A_CREDIT(2)((2) << 0); |
| 7035 | |
| 7036 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) { |
| 7037 | val |= MBUS_DBOX_BW_CREDIT(2)((2) << 14); |
| 7038 | val |= MBUS_DBOX_B_CREDIT(12)((12) << 8); |
| 7039 | } else { |
| 7040 | val |= MBUS_DBOX_BW_CREDIT(1)((1) << 14); |
| 7041 | val |= MBUS_DBOX_B_CREDIT(8)((8) << 8); |
| 7042 | } |
| 7043 | |
| 7044 | intel_de_write(dev_priv, PIPE_MBUS_DBOX_CTL(pipe)((const i915_reg_t){ .reg = (((0x7003C) + (pipe) * ((0x7103C) - (0x7003C)))) }), val); |
| 7045 | } |
| 7046 | |
| 7047 | static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state) |
| 7048 | { |
| 7049 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7050 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7051 | |
| 7052 | intel_de_write(dev_priv, WM_LINETIME(crtc->pipe)((const i915_reg_t){ .reg = (((0x45270) + (crtc->pipe) * ( (0x45274) - (0x45270)))) }), |
| 7053 | HSW_LINETIME(crtc_state->linetime)((u32)((((typeof(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (0))) + 0))))((crtc_state->linetime)) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) | |
| 7054 | HSW_IPS_LINETIME(crtc_state->ips_linetime)((u32)((((typeof(((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) << (16))) + 0))))((crtc_state->ips_linetime )) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 24) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (( (u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0))); |
| 7055 | } |
| 7056 | |
| 7057 | static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) |
| 7058 | { |
| 7059 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7060 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7061 | i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder)((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP ] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4 , [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(crtc_state ->cpu_transcoder)])) }); |
| 7062 | u32 val; |
| 7063 | |
| 7064 | val = intel_de_read(dev_priv, reg); |
| 7065 | val &= ~HSW_FRAME_START_DELAY_MASK(3 << 27); |
| 7066 | val |= HSW_FRAME_START_DELAY(0)((0) << 27); |
| 7067 | intel_de_write(dev_priv, reg, val); |
| 7068 | } |
| 7069 | |
| 7070 | static void hsw_crtc_enable(struct intel_atomic_state *state, |
| 7071 | struct intel_crtc *crtc) |
| 7072 | { |
| 7073 | const struct intel_crtc_state *new_crtc_state = |
| 7074 | intel_atomic_get_new_crtc_state(state, crtc); |
| 7075 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7076 | enum pipe pipe = crtc->pipe, hsw_workaround_pipe; |
| 7077 | enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder; |
| 7078 | bool_Bool psl_clkgate_wa; |
| 7079 | |
| 7080 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)({ int __ret = !!((crtc->active)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "crtc->active" ")"); __builtin_expect(!!( __ret), 0); })) |
| 7081 | return; |
| 7082 | |
| 7083 | intel_encoders_pre_pll_enable(state, crtc); |
| 7084 | |
| 7085 | if (new_crtc_state->shared_dpll) |
| 7086 | intel_enable_shared_dpll(new_crtc_state); |
| 7087 | |
| 7088 | intel_encoders_pre_enable(state, crtc); |
| 7089 | |
| 7090 | if (!transcoder_is_dsi(cpu_transcoder)) |
| 7091 | intel_set_pipe_timings(new_crtc_state); |
| 7092 | |
| 7093 | intel_set_pipe_src_size(new_crtc_state); |
| 7094 | |
| 7095 | if (cpu_transcoder != TRANSCODER_EDP && |
| 7096 | !transcoder_is_dsi(cpu_transcoder)) |
| 7097 | intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x6002c) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 7098 | new_crtc_state->pixel_multiplier - 1); |
| 7099 | |
| 7100 | if (new_crtc_state->has_pch_encoder) |
| 7101 | intel_cpu_transcoder_set_m_n(new_crtc_state, |
| 7102 | &new_crtc_state->fdi_m_n, NULL((void *)0)); |
| 7103 | |
| 7104 | if (!transcoder_is_dsi(cpu_transcoder)) { |
| 7105 | hsw_set_frame_start_delay(new_crtc_state); |
| 7106 | hsw_set_pipeconf(new_crtc_state); |
| 7107 | } |
| 7108 | |
| 7109 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 7110 | bdw_set_pipemisc(new_crtc_state); |
| 7111 | |
| 7112 | crtc->active = true1; |
| 7113 | |
| 7114 | /* Display WA #1180: WaDisableScalarClockGating: glk, cnl */ |
| 7115 | psl_clkgate_wa = (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)) && |
| 7116 | new_crtc_state->pch_pfit.enabled; |
| 7117 | if (psl_clkgate_wa) |
| 7118 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true1); |
| 7119 | |
| 7120 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 7121 | skl_pfit_enable(new_crtc_state); |
| 7122 | else |
| 7123 | ilk_pfit_enable(new_crtc_state); |
| 7124 | |
| 7125 | /* |
| 7126 | * On ILK+ LUT must be loaded before the pipe is running but with |
| 7127 | * clocks enabled |
| 7128 | */ |
| 7129 | intel_color_load_luts(new_crtc_state); |
| 7130 | intel_color_commit(new_crtc_state); |
| 7131 | /* update DSPCNTR to configure gamma/csc for pipe bottom color */ |
| 7132 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9) |
| 7133 | intel_disable_primary_plane(new_crtc_state); |
| 7134 | |
| 7135 | hsw_set_linetime_wm(new_crtc_state); |
| 7136 | |
| 7137 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 7138 | icl_set_pipe_chicken(crtc); |
| 7139 | |
| 7140 | if (dev_priv->display.initial_watermarks) |
| 7141 | dev_priv->display.initial_watermarks(state, crtc); |
| 7142 | |
| 7143 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 7144 | icl_pipe_mbus_enable(crtc); |
| 7145 | |
| 7146 | intel_encoders_enable(state, crtc); |
| 7147 | |
| 7148 | if (psl_clkgate_wa) { |
| 7149 | intel_wait_for_vblank(dev_priv, pipe); |
| 7150 | glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false0); |
| 7151 | } |
| 7152 | |
| 7153 | /* If we change the relative order between pipe/planes enabling, we need |
| 7154 | * to change the workaround. */ |
| 7155 | hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe; |
| 7156 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && hsw_workaround_pipe != INVALID_PIPE) { |
| 7157 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
| 7158 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
| 7159 | } |
| 7160 | } |
| 7161 | |
| 7162 | void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state) |
| 7163 | { |
| 7164 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7165 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7166 | enum pipe pipe = crtc->pipe; |
| 7167 | |
| 7168 | /* To avoid upsetting the power well on haswell only disable the pfit if |
| 7169 | * it's in use. The hw state code will make sure we get this right. */ |
| 7170 | if (!old_crtc_state->pch_pfit.enabled) |
| 7171 | return; |
| 7172 | |
| 7173 | intel_de_write(dev_priv, PF_CTL(pipe)((const i915_reg_t){ .reg = (((0x68080) + (pipe) * ((0x68880) - (0x68080)))) }), 0); |
| 7174 | intel_de_write(dev_priv, PF_WIN_POS(pipe)((const i915_reg_t){ .reg = (((0x68070) + (pipe) * ((0x68870) - (0x68070)))) }), 0); |
| 7175 | intel_de_write(dev_priv, PF_WIN_SZ(pipe)((const i915_reg_t){ .reg = (((0x68074) + (pipe) * ((0x68874) - (0x68074)))) }), 0); |
| 7176 | } |
| 7177 | |
| 7178 | static void ilk_crtc_disable(struct intel_atomic_state *state, |
| 7179 | struct intel_crtc *crtc) |
| 7180 | { |
| 7181 | const struct intel_crtc_state *old_crtc_state = |
| 7182 | intel_atomic_get_old_crtc_state(state, crtc); |
| 7183 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7184 | enum pipe pipe = crtc->pipe; |
| 7185 | |
| 7186 | /* |
| 7187 | * Sometimes spurious CPU pipe underruns happen when the |
| 7188 | * pipe is already disabled, but FDI RX/TX is still enabled. |
| 7189 | * Happens at least with VGA+HDMI cloning. Suppress them. |
| 7190 | */ |
| 7191 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false0); |
| 7192 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false0); |
| 7193 | |
| 7194 | intel_encoders_disable(state, crtc); |
| 7195 | |
| 7196 | intel_crtc_vblank_off(old_crtc_state); |
| 7197 | |
| 7198 | intel_disable_pipe(old_crtc_state); |
| 7199 | |
| 7200 | ilk_pfit_disable(old_crtc_state); |
| 7201 | |
| 7202 | if (old_crtc_state->has_pch_encoder) |
| 7203 | ilk_fdi_disable(crtc); |
| 7204 | |
| 7205 | intel_encoders_post_disable(state, crtc); |
| 7206 | |
| 7207 | if (old_crtc_state->has_pch_encoder) { |
| 7208 | ilk_disable_pch_transcoder(dev_priv, pipe); |
| 7209 | |
| 7210 | if (HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 7211 | i915_reg_t reg; |
| 7212 | u32 temp; |
| 7213 | |
| 7214 | /* disable TRANS_DP_CTL */ |
| 7215 | reg = TRANS_DP_CTL(pipe)((const i915_reg_t){ .reg = (((0xe0300) + (pipe) * ((0xe1300) - (0xe0300)))) }); |
| 7216 | temp = intel_de_read(dev_priv, reg); |
| 7217 | temp &= ~(TRANS_DP_OUTPUT_ENABLE(1 << 31) | |
| 7218 | TRANS_DP_PORT_SEL_MASK(3 << 29)); |
| 7219 | temp |= TRANS_DP_PORT_SEL_NONE(3 << 29); |
| 7220 | intel_de_write(dev_priv, reg, temp); |
| 7221 | |
| 7222 | /* disable DPLL_SEL */ |
| 7223 | temp = intel_de_read(dev_priv, PCH_DPLL_SEL((const i915_reg_t){ .reg = (0xc7000) })); |
| 7224 | temp &= ~(TRANS_DPLL_ENABLE(pipe)(1 << ((pipe) * 4 + 3)) | TRANS_DPLLB_SEL(pipe)(1 << ((pipe) * 4))); |
| 7225 | intel_de_write(dev_priv, PCH_DPLL_SEL((const i915_reg_t){ .reg = (0xc7000) }), temp); |
| 7226 | } |
| 7227 | |
| 7228 | ilk_fdi_pll_disable(crtc); |
| 7229 | } |
| 7230 | |
| 7231 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true1); |
| 7232 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true1); |
| 7233 | } |
| 7234 | |
| 7235 | static void hsw_crtc_disable(struct intel_atomic_state *state, |
| 7236 | struct intel_crtc *crtc) |
| 7237 | { |
| 7238 | /* |
| 7239 | * FIXME collapse everything to one hook. |
| 7240 | * Need care with mst->ddi interactions. |
| 7241 | */ |
| 7242 | intel_encoders_disable(state, crtc); |
| 7243 | intel_encoders_post_disable(state, crtc); |
| 7244 | } |
| 7245 | |
| 7246 | static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) |
| 7247 | { |
| 7248 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7249 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7250 | |
| 7251 | if (!crtc_state->gmch_pfit.control) |
| 7252 | return; |
| 7253 | |
| 7254 | /* |
| 7255 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
| 7256 | * according to register description and PRM. |
| 7257 | */ |
| 7258 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((&(dev_priv)->__info)->display_mmio_offset ) + 0x61230) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->display_mmio_offset) + 0x61230) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 7259 | intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((&(dev_priv)->__info)->display_mmio_offset ) + 0x61230) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->display_mmio_offset) + 0x61230) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 7260 | assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder)assert_pipe(dev_priv, crtc_state->cpu_transcoder, 0); |
| 7261 | |
| 7262 | intel_de_write(dev_priv, PFIT_PGM_RATIOS((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> display_mmio_offset) + 0x61234) }), |
| 7263 | crtc_state->gmch_pfit.pgm_ratios); |
| 7264 | intel_de_write(dev_priv, PFIT_CONTROL((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> display_mmio_offset) + 0x61230) }), crtc_state->gmch_pfit.control); |
| 7265 | |
| 7266 | /* Border color in case we don't scale up to the full screen. Black by |
| 7267 | * default, change to something else for debugging. */ |
| 7268 | intel_de_write(dev_priv, BCLRPAT(crtc->pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(crtc->pipe)] - (&(dev_priv)->__info) ->trans_offsets[TRANSCODER_A] + (0x60020) + ((&(dev_priv )->__info)->display_mmio_offset))) }), 0); |
| 7269 | } |
| 7270 | |
| 7271 | bool_Bool intel_phy_is_combo(struct drm_i915_privateinteldrm_softc *dev_priv, enum phy phy) |
| 7272 | { |
| 7273 | if (phy == PHY_NONE) |
| 7274 | return false0; |
| 7275 | else if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) |
| 7276 | return phy <= PHY_D; |
| 7277 | else if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) |
| 7278 | return phy <= PHY_C; |
| 7279 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 7280 | return phy <= PHY_B; |
| 7281 | else |
| 7282 | return false0; |
| 7283 | } |
| 7284 | |
| 7285 | bool_Bool intel_phy_is_tc(struct drm_i915_privateinteldrm_softc *dev_priv, enum phy phy) |
| 7286 | { |
| 7287 | if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) |
| 7288 | return false0; |
| 7289 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 7290 | return phy >= PHY_D && phy <= PHY_I; |
| 7291 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11 && !IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) |
| 7292 | return phy >= PHY_C && phy <= PHY_F; |
| 7293 | else |
| 7294 | return false0; |
| 7295 | } |
| 7296 | |
| 7297 | enum phy intel_port_to_phy(struct drm_i915_privateinteldrm_softc *i915, enum port port) |
| 7298 | { |
| 7299 | if (IS_ROCKETLAKE(i915)IS_PLATFORM(i915, INTEL_ROCKETLAKE) && port >= PORT_D) |
| 7300 | return (enum phy)port - 1; |
| 7301 | else if (IS_ELKHARTLAKE(i915)IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && port == PORT_D) |
| 7302 | return PHY_A; |
| 7303 | |
| 7304 | return (enum phy)port; |
| 7305 | } |
| 7306 | |
| 7307 | enum tc_port intel_port_to_tc(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port) |
| 7308 | { |
| 7309 | if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port))) |
| 7310 | return PORT_TC_NONE; |
| 7311 | |
| 7312 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 7313 | return port - PORT_D; |
| 7314 | |
| 7315 | return port - PORT_C; |
| 7316 | } |
| 7317 | |
| 7318 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
| 7319 | { |
| 7320 | switch (port) { |
| 7321 | case PORT_A: |
| 7322 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
| 7323 | case PORT_B: |
| 7324 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
| 7325 | case PORT_C: |
| 7326 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
| 7327 | case PORT_D: |
| 7328 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
| 7329 | case PORT_E: |
| 7330 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
| 7331 | case PORT_F: |
| 7332 | return POWER_DOMAIN_PORT_DDI_F_LANES; |
| 7333 | case PORT_G: |
| 7334 | return POWER_DOMAIN_PORT_DDI_G_LANES; |
| 7335 | case PORT_H: |
| 7336 | return POWER_DOMAIN_PORT_DDI_H_LANES; |
| 7337 | case PORT_I: |
| 7338 | return POWER_DOMAIN_PORT_DDI_I_LANES; |
| 7339 | default: |
| 7340 | MISSING_CASE(port)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "port", (long)(port)); __builtin_expect(!!(__ret), 0); }); |
| 7341 | return POWER_DOMAIN_PORT_OTHER; |
| 7342 | } |
| 7343 | } |
| 7344 | |
| 7345 | enum intel_display_power_domain |
| 7346 | intel_aux_power_domain(struct intel_digital_port *dig_port) |
| 7347 | { |
| 7348 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
| 7349 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
| 7350 | |
| 7351 | if (intel_phy_is_tc(dev_priv, phy) && |
| 7352 | dig_port->tc_mode == TC_PORT_TBT_ALT) { |
| 7353 | switch (dig_port->aux_ch) { |
| 7354 | case AUX_CH_C: |
| 7355 | return POWER_DOMAIN_AUX_C_TBT; |
| 7356 | case AUX_CH_D: |
| 7357 | return POWER_DOMAIN_AUX_D_TBT; |
| 7358 | case AUX_CH_E: |
| 7359 | return POWER_DOMAIN_AUX_E_TBT; |
| 7360 | case AUX_CH_F: |
| 7361 | return POWER_DOMAIN_AUX_F_TBT; |
| 7362 | case AUX_CH_G: |
| 7363 | return POWER_DOMAIN_AUX_G_TBT; |
| 7364 | case AUX_CH_H: |
| 7365 | return POWER_DOMAIN_AUX_H_TBT; |
| 7366 | case AUX_CH_I: |
| 7367 | return POWER_DOMAIN_AUX_I_TBT; |
| 7368 | default: |
| 7369 | MISSING_CASE(dig_port->aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "dig_port->aux_ch", (long)(dig_port->aux_ch)); __builtin_expect (!!(__ret), 0); }); |
| 7370 | return POWER_DOMAIN_AUX_C_TBT; |
| 7371 | } |
| 7372 | } |
| 7373 | |
| 7374 | return intel_legacy_aux_to_power_domain(dig_port->aux_ch); |
| 7375 | } |
| 7376 | |
| 7377 | /* |
| 7378 | * Converts aux_ch to power_domain without caring about TBT ports for that use |
| 7379 | * intel_aux_power_domain() |
| 7380 | */ |
| 7381 | enum intel_display_power_domain |
| 7382 | intel_legacy_aux_to_power_domain(enum aux_ch aux_ch) |
| 7383 | { |
| 7384 | switch (aux_ch) { |
| 7385 | case AUX_CH_A: |
| 7386 | return POWER_DOMAIN_AUX_A; |
| 7387 | case AUX_CH_B: |
| 7388 | return POWER_DOMAIN_AUX_B; |
| 7389 | case AUX_CH_C: |
| 7390 | return POWER_DOMAIN_AUX_C; |
| 7391 | case AUX_CH_D: |
| 7392 | return POWER_DOMAIN_AUX_D; |
| 7393 | case AUX_CH_E: |
| 7394 | return POWER_DOMAIN_AUX_E; |
| 7395 | case AUX_CH_F: |
| 7396 | return POWER_DOMAIN_AUX_F; |
| 7397 | case AUX_CH_G: |
| 7398 | return POWER_DOMAIN_AUX_G; |
| 7399 | case AUX_CH_H: |
| 7400 | return POWER_DOMAIN_AUX_H; |
| 7401 | case AUX_CH_I: |
| 7402 | return POWER_DOMAIN_AUX_I; |
| 7403 | default: |
| 7404 | MISSING_CASE(aux_ch)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "aux_ch", (long)(aux_ch)); __builtin_expect(!!(__ret), 0); } ); |
| 7405 | return POWER_DOMAIN_AUX_A; |
| 7406 | } |
| 7407 | } |
| 7408 | |
| 7409 | static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state) |
| 7410 | { |
| 7411 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7412 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7413 | struct drm_encoder *encoder; |
| 7414 | enum pipe pipe = crtc->pipe; |
| 7415 | u64 mask; |
| 7416 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
| 7417 | |
| 7418 | if (!crtc_state->hw.active) |
| 7419 | return 0; |
| 7420 | |
| 7421 | mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe))(1ULL << (((pipe) + POWER_DOMAIN_PIPE_A))); |
| 7422 | mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder))(1ULL << (((transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (transcoder) + POWER_DOMAIN_TRANSCODER_A))); |
| 7423 | if (crtc_state->pch_pfit.enabled || |
| 7424 | crtc_state->pch_pfit.force_thru) |
| 7425 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))(1ULL << (((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER))); |
| 7426 | |
| 7427 | drm_for_each_encoder_mask(encoder, &dev_priv->drm,for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *) 0)->head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*(encoder)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(encoder)), head) );}); & (encoder)->head != (&(&dev_priv->drm)->mode_config .encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder )) *)0)->head ) *__mptr = ((encoder)->head.next); (__typeof (*(encoder)) *)( (char *)__mptr - __builtin_offsetof(__typeof (*(encoder)), head) );})) if (!((crtc_state->uapi.encoder_mask ) & drm_encoder_mask(encoder))) {} else |
| 7428 | crtc_state->uapi.encoder_mask)for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *) 0)->head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*(encoder)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(encoder)), head) );}); & (encoder)->head != (&(&dev_priv->drm)->mode_config .encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder )) *)0)->head ) *__mptr = ((encoder)->head.next); (__typeof (*(encoder)) *)( (char *)__mptr - __builtin_offsetof(__typeof (*(encoder)), head) );})) if (!((crtc_state->uapi.encoder_mask ) & drm_encoder_mask(encoder))) {} else { |
| 7429 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );}); |
| 7430 | |
| 7431 | mask |= BIT_ULL(intel_encoder->power_domain)(1ULL << (intel_encoder->power_domain)); |
| 7432 | } |
| 7433 | |
| 7434 | if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi) && crtc_state->has_audio) |
| 7435 | mask |= BIT_ULL(POWER_DOMAIN_AUDIO)(1ULL << (POWER_DOMAIN_AUDIO)); |
| 7436 | |
| 7437 | if (crtc_state->shared_dpll) |
| 7438 | mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE)(1ULL << (POWER_DOMAIN_DISPLAY_CORE)); |
| 7439 | |
| 7440 | return mask; |
| 7441 | } |
| 7442 | |
| 7443 | static u64 |
| 7444 | modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state) |
| 7445 | { |
| 7446 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7447 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7448 | enum intel_display_power_domain domain; |
| 7449 | u64 domains, new_domains, old_domains; |
| 7450 | |
| 7451 | old_domains = crtc->enabled_power_domains; |
| 7452 | crtc->enabled_power_domains = new_domains = |
| 7453 | get_crtc_power_domains(crtc_state); |
| 7454 | |
| 7455 | domains = new_domains & ~old_domains; |
| 7456 | |
| 7457 | for_each_power_domain(domain, domains)for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++ ) if (!((1ULL << (domain)) & (domains))) {} else |
| 7458 | intel_display_power_get(dev_priv, domain); |
| 7459 | |
| 7460 | return old_domains & ~new_domains; |
| 7461 | } |
| 7462 | |
| 7463 | static void modeset_put_power_domains(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 7464 | u64 domains) |
| 7465 | { |
| 7466 | enum intel_display_power_domain domain; |
| 7467 | |
| 7468 | for_each_power_domain(domain, domains)for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++ ) if (!((1ULL << (domain)) & (domains))) {} else |
| 7469 | intel_display_power_put_unchecked(dev_priv, domain); |
| 7470 | } |
| 7471 | |
| 7472 | static void valleyview_crtc_enable(struct intel_atomic_state *state, |
| 7473 | struct intel_crtc *crtc) |
| 7474 | { |
| 7475 | const struct intel_crtc_state *new_crtc_state = |
| 7476 | intel_atomic_get_new_crtc_state(state, crtc); |
| 7477 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7478 | enum pipe pipe = crtc->pipe; |
| 7479 | |
| 7480 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)({ int __ret = !!((crtc->active)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "crtc->active" ")"); __builtin_expect(!!( __ret), 0); })) |
| 7481 | return; |
| 7482 | |
| 7483 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
| 7484 | intel_dp_set_m_n(new_crtc_state, M1_N1); |
| 7485 | |
| 7486 | intel_set_pipe_timings(new_crtc_state); |
| 7487 | intel_set_pipe_src_size(new_crtc_state); |
| 7488 | |
| 7489 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && pipe == PIPE_B) { |
| 7490 | intel_de_write(dev_priv, CHV_BLEND(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60a00) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), CHV_BLEND_LEGACY(0 << 30)); |
| 7491 | intel_de_write(dev_priv, CHV_CANVAS(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60a04) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), 0); |
| 7492 | } |
| 7493 | |
| 7494 | i9xx_set_pipeconf(new_crtc_state); |
| 7495 | |
| 7496 | crtc->active = true1; |
| 7497 | |
| 7498 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true1); |
| 7499 | |
| 7500 | intel_encoders_pre_pll_enable(state, crtc); |
| 7501 | |
| 7502 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 7503 | chv_prepare_pll(crtc, new_crtc_state); |
| 7504 | chv_enable_pll(crtc, new_crtc_state); |
| 7505 | } else { |
| 7506 | vlv_prepare_pll(crtc, new_crtc_state); |
| 7507 | vlv_enable_pll(crtc, new_crtc_state); |
| 7508 | } |
| 7509 | |
| 7510 | intel_encoders_pre_enable(state, crtc); |
| 7511 | |
| 7512 | i9xx_pfit_enable(new_crtc_state); |
| 7513 | |
| 7514 | intel_color_load_luts(new_crtc_state); |
| 7515 | intel_color_commit(new_crtc_state); |
| 7516 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
| 7517 | intel_disable_primary_plane(new_crtc_state); |
| 7518 | |
| 7519 | dev_priv->display.initial_watermarks(state, crtc); |
| 7520 | intel_enable_pipe(new_crtc_state); |
| 7521 | |
| 7522 | intel_crtc_vblank_on(new_crtc_state); |
| 7523 | |
| 7524 | intel_encoders_enable(state, crtc); |
| 7525 | } |
| 7526 | |
| 7527 | static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state) |
| 7528 | { |
| 7529 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7530 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7531 | |
| 7532 | intel_de_write(dev_priv, FP0(crtc->pipe)((const i915_reg_t){ .reg = (((0x6040) + (crtc->pipe) * (( 0x6048) - (0x6040)))) }), |
| 7533 | crtc_state->dpll_hw_state.fp0); |
| 7534 | intel_de_write(dev_priv, FP1(crtc->pipe)((const i915_reg_t){ .reg = (((0x6044) + (crtc->pipe) * (( 0x604c) - (0x6044)))) }), |
| 7535 | crtc_state->dpll_hw_state.fp1); |
| 7536 | } |
| 7537 | |
| 7538 | static void i9xx_crtc_enable(struct intel_atomic_state *state, |
| 7539 | struct intel_crtc *crtc) |
| 7540 | { |
| 7541 | const struct intel_crtc_state *new_crtc_state = |
| 7542 | intel_atomic_get_new_crtc_state(state, crtc); |
| 7543 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7544 | enum pipe pipe = crtc->pipe; |
| 7545 | |
| 7546 | if (drm_WARN_ON(&dev_priv->drm, crtc->active)({ int __ret = !!((crtc->active)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "crtc->active" ")"); __builtin_expect(!!( __ret), 0); })) |
| 7547 | return; |
| 7548 | |
| 7549 | i9xx_set_pll_dividers(new_crtc_state); |
| 7550 | |
| 7551 | if (intel_crtc_has_dp_encoder(new_crtc_state)) |
| 7552 | intel_dp_set_m_n(new_crtc_state, M1_N1); |
| 7553 | |
| 7554 | intel_set_pipe_timings(new_crtc_state); |
| 7555 | intel_set_pipe_src_size(new_crtc_state); |
| 7556 | |
| 7557 | i9xx_set_pipeconf(new_crtc_state); |
| 7558 | |
| 7559 | crtc->active = true1; |
| 7560 | |
| 7561 | if (!IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 7562 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true1); |
| 7563 | |
| 7564 | intel_encoders_pre_enable(state, crtc); |
| 7565 | |
| 7566 | i9xx_enable_pll(crtc, new_crtc_state); |
| 7567 | |
| 7568 | i9xx_pfit_enable(new_crtc_state); |
| 7569 | |
| 7570 | intel_color_load_luts(new_crtc_state); |
| 7571 | intel_color_commit(new_crtc_state); |
| 7572 | /* update DSPCNTR to configure gamma for pipe bottom color */ |
| 7573 | intel_disable_primary_plane(new_crtc_state); |
| 7574 | |
| 7575 | if (dev_priv->display.initial_watermarks) |
| 7576 | dev_priv->display.initial_watermarks(state, crtc); |
| 7577 | else |
| 7578 | intel_update_watermarks(crtc); |
| 7579 | intel_enable_pipe(new_crtc_state); |
| 7580 | |
| 7581 | intel_crtc_vblank_on(new_crtc_state); |
| 7582 | |
| 7583 | intel_encoders_enable(state, crtc); |
| 7584 | |
| 7585 | /* prevents spurious underruns */ |
| 7586 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 7587 | intel_wait_for_vblank(dev_priv, pipe); |
| 7588 | } |
| 7589 | |
| 7590 | static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) |
| 7591 | { |
| 7592 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7593 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7594 | |
| 7595 | if (!old_crtc_state->gmch_pfit.control) |
| 7596 | return; |
| 7597 | |
| 7598 | assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder)assert_pipe(dev_priv, old_crtc_state->cpu_transcoder, 0); |
| 7599 | |
| 7600 | drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling pfit, current: 0x%08x\n" , intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((& (dev_priv)->__info)->display_mmio_offset) + 0x61230) }) )) |
| 7601 | intel_de_read(dev_priv, PFIT_CONTROL))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling pfit, current: 0x%08x\n" , intel_de_read(dev_priv, ((const i915_reg_t){ .reg = (((& (dev_priv)->__info)->display_mmio_offset) + 0x61230) }) )); |
| 7602 | intel_de_write(dev_priv, PFIT_CONTROL((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> display_mmio_offset) + 0x61230) }), 0); |
| 7603 | } |
| 7604 | |
| 7605 | static void i9xx_crtc_disable(struct intel_atomic_state *state, |
| 7606 | struct intel_crtc *crtc) |
| 7607 | { |
| 7608 | struct intel_crtc_state *old_crtc_state = |
| 7609 | intel_atomic_get_old_crtc_state(state, crtc); |
| 7610 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7611 | enum pipe pipe = crtc->pipe; |
| 7612 | |
| 7613 | /* |
| 7614 | * On gen2 planes are double buffered but the pipe isn't, so we must |
| 7615 | * wait for planes to fully turn off before disabling the pipe. |
| 7616 | */ |
| 7617 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 7618 | intel_wait_for_vblank(dev_priv, pipe); |
| 7619 | |
| 7620 | intel_encoders_disable(state, crtc); |
| 7621 | |
| 7622 | intel_crtc_vblank_off(old_crtc_state); |
| 7623 | |
| 7624 | intel_disable_pipe(old_crtc_state); |
| 7625 | |
| 7626 | i9xx_pfit_disable(old_crtc_state); |
| 7627 | |
| 7628 | intel_encoders_post_disable(state, crtc); |
| 7629 | |
| 7630 | if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) { |
| 7631 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 7632 | chv_disable_pll(dev_priv, pipe); |
| 7633 | else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)) |
| 7634 | vlv_disable_pll(dev_priv, pipe); |
| 7635 | else |
| 7636 | i9xx_disable_pll(old_crtc_state); |
| 7637 | } |
| 7638 | |
| 7639 | intel_encoders_post_pll_disable(state, crtc); |
| 7640 | |
| 7641 | if (!IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 7642 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false0); |
| 7643 | |
| 7644 | if (!dev_priv->display.initial_watermarks) |
| 7645 | intel_update_watermarks(crtc); |
| 7646 | |
| 7647 | /* clock the pipe down to 640x480@60 to potentially save power */ |
| 7648 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 7649 | i830_enable_pipe(dev_priv, pipe); |
| 7650 | } |
| 7651 | |
| 7652 | static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, |
| 7653 | struct drm_modeset_acquire_ctx *ctx) |
| 7654 | { |
| 7655 | struct intel_encoder *encoder; |
| 7656 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7657 | struct intel_bw_state *bw_state = |
| 7658 | to_intel_bw_state(dev_priv->bw_obj.state)({ const __typeof( ((struct intel_bw_state *)0)->base ) *__mptr = ((dev_priv->bw_obj.state)); (struct intel_bw_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_bw_state, base ) );}); |
| 7659 | struct intel_cdclk_state *cdclk_state = |
| 7660 | to_intel_cdclk_state(dev_priv->cdclk.obj.state)({ const __typeof( ((struct intel_cdclk_state *)0)->base ) *__mptr = ((dev_priv->cdclk.obj.state)); (struct intel_cdclk_state *)( (char *)__mptr - __builtin_offsetof(struct intel_cdclk_state , base) );}); |
| 7661 | struct intel_dbuf_state *dbuf_state = |
| 7662 | to_intel_dbuf_state(dev_priv->dbuf.obj.state)({ const __typeof( ((struct intel_dbuf_state *)0)->base ) * __mptr = ((dev_priv->dbuf.obj.state)); (struct intel_dbuf_state *)( (char *)__mptr - __builtin_offsetof(struct intel_dbuf_state , base) );}); |
| 7663 | struct intel_crtc_state *crtc_state = |
| 7664 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 7665 | enum intel_display_power_domain domain; |
| 7666 | struct intel_plane *plane; |
| 7667 | struct drm_atomic_state *state; |
| 7668 | struct intel_crtc_state *temp_crtc_state; |
| 7669 | enum pipe pipe = crtc->pipe; |
| 7670 | u64 domains; |
| 7671 | int ret; |
| 7672 | |
| 7673 | if (!crtc_state->hw.active) |
| 7674 | return; |
| 7675 | |
| 7676 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane), base.head) );}); &plane ->base.head != (&(&dev_priv->drm)->mode_config .plane_list); plane = ({ const __typeof( ((__typeof(*plane) * )0)->base.head ) *__mptr = (plane->base.head.next); (__typeof (*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane ), base.head) );})) if (!((plane)->pipe == (crtc)->pipe )) {} else { |
| 7677 | const struct intel_plane_state *plane_state = |
| 7678 | to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane->base.state); (struct intel_plane_state * )( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 7679 | |
| 7680 | if (plane_state->uapi.visible) |
| 7681 | intel_plane_disable_noatomic(crtc, plane); |
| 7682 | } |
| 7683 | |
| 7684 | state = drm_atomic_state_alloc(&dev_priv->drm); |
| 7685 | if (!state) { |
| 7686 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to disable [CRTC:%d:%s], out of memory" , crtc->base.base.id, crtc->base.name) |
| 7687 | "failed to disable [CRTC:%d:%s], out of memory",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to disable [CRTC:%d:%s], out of memory" , crtc->base.base.id, crtc->base.name) |
| 7688 | crtc->base.base.id, crtc->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to disable [CRTC:%d:%s], out of memory" , crtc->base.base.id, crtc->base.name); |
| 7689 | return; |
| 7690 | } |
| 7691 | |
| 7692 | state->acquire_ctx = ctx; |
| 7693 | |
| 7694 | /* Everything's already locked, -EDEADLK can't happen. */ |
| 7695 | temp_crtc_state = intel_atomic_get_crtc_state(state, crtc); |
| 7696 | ret = drm_atomic_add_affected_connectors(state, &crtc->base); |
| 7697 | |
| 7698 | drm_WARN_ON(&dev_priv->drm, IS_ERR(temp_crtc_state) || ret)({ int __ret = !!((IS_ERR(temp_crtc_state) || ret)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "IS_ERR(temp_crtc_state) || ret" ")"); __builtin_expect(!!(__ret), 0); }); |
| 7699 | |
| 7700 | dev_priv->display.crtc_disable(to_intel_atomic_state(state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state, base) );}), crtc); |
| 7701 | |
| 7702 | drm_atomic_state_put(state); |
| 7703 | |
| 7704 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n" , crtc->base.base.id, crtc->base.name) |
| 7705 | "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n" , crtc->base.base.id, crtc->base.name) |
| 7706 | crtc->base.base.id, crtc->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n" , crtc->base.base.id, crtc->base.name); |
| 7707 | |
| 7708 | crtc->active = false0; |
| 7709 | crtc->base.enabled = false0; |
| 7710 | |
| 7711 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((drm_atomic_set_mode_for_crtc(&crtc_state ->uapi, ((void *)0)) < 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "drm_atomic_set_mode_for_crtc(&crtc_state->uapi, ((void *)0)) < 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 7712 | drm_atomic_set_mode_for_crtc(&crtc_state->uapi, NULL) < 0)({ int __ret = !!((drm_atomic_set_mode_for_crtc(&crtc_state ->uapi, ((void *)0)) < 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "drm_atomic_set_mode_for_crtc(&crtc_state->uapi, ((void *)0)) < 0" ")"); __builtin_expect(!!(__ret), 0); }); |
| 7713 | crtc_state->uapi.active = false0; |
| 7714 | crtc_state->uapi.connector_mask = 0; |
| 7715 | crtc_state->uapi.encoder_mask = 0; |
| 7716 | intel_crtc_free_hw_state(crtc_state); |
| 7717 | memset(&crtc_state->hw, 0, sizeof(crtc_state->hw))__builtin_memset((&crtc_state->hw), (0), (sizeof(crtc_state ->hw))); |
| 7718 | |
| 7719 | for_each_encoder_on_crtc(&dev_priv->drm, &crtc->base, encoder)for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *) 0)->base.head ) *__mptr = ((&(&dev_priv->drm)-> mode_config.encoder_list)->next); (__typeof(*(encoder)) *) ( (char *)__mptr - __builtin_offsetof(__typeof(*(encoder)), base .head) );}); &(encoder)->base.head != (&(&dev_priv ->drm)->mode_config.encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder)) *)0)->base.head ) *__mptr = ((encoder)->base.head.next); (__typeof(*(encoder)) *)( ( char *)__mptr - __builtin_offsetof(__typeof(*(encoder)), base .head) );})) if (!((encoder)->base.crtc == (&crtc-> base))) {} else |
| 7720 | encoder->base.crtc = NULL((void *)0); |
| 7721 | |
| 7722 | intel_fbc_disable(crtc); |
| 7723 | intel_update_watermarks(crtc); |
| 7724 | intel_disable_shared_dpll(crtc_state); |
| 7725 | |
| 7726 | domains = crtc->enabled_power_domains; |
| 7727 | for_each_power_domain(domain, domains)for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++ ) if (!((1ULL << (domain)) & (domains))) {} else |
| 7728 | intel_display_power_put_unchecked(dev_priv, domain); |
| 7729 | crtc->enabled_power_domains = 0; |
| 7730 | |
| 7731 | dev_priv->active_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 7732 | cdclk_state->min_cdclk[pipe] = 0; |
| 7733 | cdclk_state->min_voltage_level[pipe] = 0; |
| 7734 | cdclk_state->active_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 7735 | |
| 7736 | dbuf_state->active_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 7737 | |
| 7738 | bw_state->data_rate[pipe] = 0; |
| 7739 | bw_state->num_active_planes[pipe] = 0; |
| 7740 | } |
| 7741 | |
| 7742 | /* |
| 7743 | * turn all crtc's off, but do not adjust state |
| 7744 | * This has to be paired with a call to intel_modeset_setup_hw_state. |
| 7745 | */ |
| 7746 | int intel_display_suspend(struct drm_device *dev) |
| 7747 | { |
| 7748 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 7749 | struct drm_atomic_state *state; |
| 7750 | int ret; |
| 7751 | |
| 7752 | state = drm_atomic_helper_suspend(dev); |
| 7753 | ret = PTR_ERR_OR_ZERO(state); |
| 7754 | if (ret) |
| 7755 | drm_err(&dev_priv->drm, "Suspending crtc's failed with %i\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspending crtc's failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
| 7756 | ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspending crtc's failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 7757 | else |
| 7758 | dev_priv->modeset_restore_state = state; |
| 7759 | return ret; |
| 7760 | } |
| 7761 | |
| 7762 | void intel_encoder_destroy(struct drm_encoder *encoder) |
| 7763 | { |
| 7764 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );}); |
| 7765 | |
| 7766 | drm_encoder_cleanup(encoder); |
| 7767 | kfree(intel_encoder); |
| 7768 | } |
| 7769 | |
| 7770 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
| 7771 | * internal consistency). */ |
| 7772 | static void intel_connector_verify_state(struct intel_crtc_state *crtc_state, |
| 7773 | struct drm_connector_state *conn_state) |
| 7774 | { |
| 7775 | struct intel_connector *connector = to_intel_connector(conn_state->connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (conn_state->connector); (struct intel_connector * )( (char *)__mptr - __builtin_offsetof(struct intel_connector , base) );}); |
| 7776 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->base.dev); |
| 7777 | |
| 7778 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s]\n" , connector->base.base.id, connector->base.name) |
| 7779 | connector->base.base.id, connector->base.name)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s]\n" , connector->base.base.id, connector->base.name); |
| 7780 | |
| 7781 | if (connector->get_hw_state(connector)) { |
| 7782 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
| 7783 | |
| 7784 | I915_STATE_WARN(!crtc_state,({ int __ret_warn_on = !!(!crtc_state); if (__builtin_expect( !!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams. verbose_state_checks); if (__ret) printf("connector enabled without attached crtc\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("connector enabled without attached crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 7785 | "connector enabled without attached crtc\n")({ int __ret_warn_on = !!(!crtc_state); if (__builtin_expect( !!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams. verbose_state_checks); if (__ret) printf("connector enabled without attached crtc\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("connector enabled without attached crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 7786 | |
| 7787 | if (!crtc_state) |
| 7788 | return; |
| 7789 | |
| 7790 | I915_STATE_WARN(!crtc_state->hw.active,({ int __ret_warn_on = !!(!crtc_state->hw.active); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("connector is active, but attached crtc isn't\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("connector is active, but attached crtc isn't\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 7791 | "connector is active, but attached crtc isn't\n")({ int __ret_warn_on = !!(!crtc_state->hw.active); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("connector is active, but attached crtc isn't\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("connector is active, but attached crtc isn't\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 7792 | |
| 7793 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
| 7794 | return; |
| 7795 | |
| 7796 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base,({ int __ret_warn_on = !!(conn_state->best_encoder != & encoder->base); if (__builtin_expect(!!(__ret_warn_on), 0) ) if (!({ int __ret = !!(i915_modparams.verbose_state_checks) ; if (__ret) printf("atomic encoder doesn't match attached encoder\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("atomic encoder doesn't match attached encoder\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 7797 | "atomic encoder doesn't match attached encoder\n")({ int __ret_warn_on = !!(conn_state->best_encoder != & encoder->base); if (__builtin_expect(!!(__ret_warn_on), 0) ) if (!({ int __ret = !!(i915_modparams.verbose_state_checks) ; if (__ret) printf("atomic encoder doesn't match attached encoder\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("atomic encoder doesn't match attached encoder\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 7798 | |
| 7799 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,({ int __ret_warn_on = !!(conn_state->crtc != encoder-> base.crtc); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("attached encoder crtc differs from connector crtc\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("attached encoder crtc differs from connector crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 7800 | "attached encoder crtc differs from connector crtc\n")({ int __ret_warn_on = !!(conn_state->crtc != encoder-> base.crtc); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("attached encoder crtc differs from connector crtc\n" ); __builtin_expect(!!(__ret), 0); })) __drm_err("attached encoder crtc differs from connector crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 7801 | } else { |
| 7802 | I915_STATE_WARN(crtc_state && crtc_state->hw.active,({ int __ret_warn_on = !!(crtc_state && crtc_state-> hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("attached crtc is active, but connector isn't\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("attached crtc is active, but connector isn't\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 7803 | "attached crtc is active, but connector isn't\n")({ int __ret_warn_on = !!(crtc_state && crtc_state-> hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("attached crtc is active, but connector isn't\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("attached crtc is active, but connector isn't\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 7804 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder,({ int __ret_warn_on = !!(!crtc_state && conn_state-> best_encoder); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("best encoder set without crtc!\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("best encoder set without crtc!\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 7805 | "best encoder set without crtc!\n")({ int __ret_warn_on = !!(!crtc_state && conn_state-> best_encoder); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("best encoder set without crtc!\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("best encoder set without crtc!\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 7806 | } |
| 7807 | } |
| 7808 | |
| 7809 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
| 7810 | { |
| 7811 | if (crtc_state->hw.enable && crtc_state->has_pch_encoder) |
| 7812 | return crtc_state->fdi_lanes; |
| 7813 | |
| 7814 | return 0; |
| 7815 | } |
| 7816 | |
| 7817 | static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
| 7818 | struct intel_crtc_state *pipe_config) |
| 7819 | { |
| 7820 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 7821 | struct drm_atomic_state *state = pipe_config->uapi.state; |
| 7822 | struct intel_crtc *other_crtc; |
| 7823 | struct intel_crtc_state *other_crtc_state; |
| 7824 | |
| 7825 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "checking fdi config on pipe %c, lanes %i\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7826 | "checking fdi config on pipe %c, lanes %i\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "checking fdi config on pipe %c, lanes %i\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7827 | pipe_name(pipe), pipe_config->fdi_lanes)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "checking fdi config on pipe %c, lanes %i\n" , ((pipe) + 'A'), pipe_config->fdi_lanes); |
| 7828 | if (pipe_config->fdi_lanes > 4) { |
| 7829 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid fdi lane config on pipe %c: %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7830 | "invalid fdi lane config on pipe %c: %i lanes\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid fdi lane config on pipe %c: %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7831 | pipe_name(pipe), pipe_config->fdi_lanes)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid fdi lane config on pipe %c: %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes); |
| 7832 | return -EINVAL22; |
| 7833 | } |
| 7834 | |
| 7835 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 7836 | if (pipe_config->fdi_lanes > 2) { |
| 7837 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "only 2 lanes on haswell, required: %i lanes\n" , pipe_config->fdi_lanes) |
| 7838 | "only 2 lanes on haswell, required: %i lanes\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "only 2 lanes on haswell, required: %i lanes\n" , pipe_config->fdi_lanes) |
| 7839 | pipe_config->fdi_lanes)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "only 2 lanes on haswell, required: %i lanes\n" , pipe_config->fdi_lanes); |
| 7840 | return -EINVAL22; |
| 7841 | } else { |
| 7842 | return 0; |
| 7843 | } |
| 7844 | } |
| 7845 | |
| 7846 | if (INTEL_NUM_PIPES(dev_priv)(hweight8((&(dev_priv)->__info)->pipe_mask)) == 2) |
| 7847 | return 0; |
| 7848 | |
| 7849 | /* Ivybridge 3 pipe is really complicated */ |
| 7850 | switch (pipe) { |
| 7851 | case PIPE_A: |
| 7852 | return 0; |
| 7853 | case PIPE_B: |
| 7854 | if (pipe_config->fdi_lanes <= 2) |
| 7855 | return 0; |
| 7856 | |
| 7857 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
| 7858 | other_crtc_state = |
| 7859 | intel_atomic_get_crtc_state(state, other_crtc); |
| 7860 | if (IS_ERR(other_crtc_state)) |
| 7861 | return PTR_ERR(other_crtc_state); |
| 7862 | |
| 7863 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { |
| 7864 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid shared fdi lane config on pipe %c: %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7865 | "invalid shared fdi lane config on pipe %c: %i lanes\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid shared fdi lane config on pipe %c: %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7866 | pipe_name(pipe), pipe_config->fdi_lanes)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "invalid shared fdi lane config on pipe %c: %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes); |
| 7867 | return -EINVAL22; |
| 7868 | } |
| 7869 | return 0; |
| 7870 | case PIPE_C: |
| 7871 | if (pipe_config->fdi_lanes > 2) { |
| 7872 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "only 2 lanes on pipe %c: required %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7873 | "only 2 lanes on pipe %c: required %i lanes\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "only 2 lanes on pipe %c: required %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes) |
| 7874 | pipe_name(pipe), pipe_config->fdi_lanes)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "only 2 lanes on pipe %c: required %i lanes\n" , ((pipe) + 'A'), pipe_config->fdi_lanes); |
| 7875 | return -EINVAL22; |
| 7876 | } |
| 7877 | |
| 7878 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
| 7879 | other_crtc_state = |
| 7880 | intel_atomic_get_crtc_state(state, other_crtc); |
| 7881 | if (IS_ERR(other_crtc_state)) |
| 7882 | return PTR_ERR(other_crtc_state); |
| 7883 | |
| 7884 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { |
| 7885 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fdi link B uses too many lanes to enable link C\n" ) |
| 7886 | "fdi link B uses too many lanes to enable link C\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fdi link B uses too many lanes to enable link C\n" ); |
| 7887 | return -EINVAL22; |
| 7888 | } |
| 7889 | return 0; |
| 7890 | default: |
| 7891 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 7891); } while (0); |
| 7892 | } |
| 7893 | } |
| 7894 | |
| 7895 | #define RETRY1 1 |
| 7896 | static int ilk_fdi_compute_config(struct intel_crtc *intel_crtc, |
| 7897 | struct intel_crtc_state *pipe_config) |
| 7898 | { |
| 7899 | struct drm_device *dev = intel_crtc->base.dev; |
| 7900 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(dev); |
| 7901 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
| 7902 | int lane, link_bw, fdi_dotclock, ret; |
| 7903 | bool_Bool needs_recompute = false0; |
| 7904 | |
| 7905 | retry: |
| 7906 | /* FDI is a binary signal running at ~2.7GHz, encoding |
| 7907 | * each output octet as 10 bits. The actual frequency |
| 7908 | * is stored as a divider into a 100MHz clock, and the |
| 7909 | * mode pixel clock is stored in units of 1KHz. |
| 7910 | * Hence the bw of each lane in terms of the mode signal |
| 7911 | * is: |
| 7912 | */ |
| 7913 | link_bw = intel_fdi_link_freq(i915, pipe_config); |
| 7914 | |
| 7915 | fdi_dotclock = adjusted_mode->crtc_clock; |
| 7916 | |
| 7917 | lane = ilk_get_lanes_required(fdi_dotclock, link_bw, |
| 7918 | pipe_config->pipe_bpp); |
| 7919 | |
| 7920 | pipe_config->fdi_lanes = lane; |
| 7921 | |
| 7922 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
| 7923 | link_bw, &pipe_config->fdi_m_n, false0, false0); |
| 7924 | |
| 7925 | ret = ilk_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
| 7926 | if (ret == -EDEADLK11) |
| 7927 | return ret; |
| 7928 | |
| 7929 | if (ret == -EINVAL22 && pipe_config->pipe_bpp > 6*3) { |
| 7930 | pipe_config->pipe_bpp -= 2*3; |
| 7931 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "fdi link bw constraint, reducing pipe bpp to %i\n" , pipe_config->pipe_bpp) |
| 7932 | "fdi link bw constraint, reducing pipe bpp to %i\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "fdi link bw constraint, reducing pipe bpp to %i\n" , pipe_config->pipe_bpp) |
| 7933 | pipe_config->pipe_bpp)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "fdi link bw constraint, reducing pipe bpp to %i\n" , pipe_config->pipe_bpp); |
| 7934 | needs_recompute = true1; |
| 7935 | pipe_config->bw_constrained = true1; |
| 7936 | |
| 7937 | goto retry; |
| 7938 | } |
| 7939 | |
| 7940 | if (needs_recompute) |
| 7941 | return RETRY1; |
| 7942 | |
| 7943 | return ret; |
| 7944 | } |
| 7945 | |
| 7946 | bool_Bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state) |
| 7947 | { |
| 7948 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 7949 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 7950 | |
| 7951 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
| 7952 | if (!hsw_crtc_supports_ips(crtc)) |
| 7953 | return false0; |
| 7954 | |
| 7955 | if (!dev_priv->params.enable_ips) |
| 7956 | return false0; |
| 7957 | |
| 7958 | if (crtc_state->pipe_bpp > 24) |
| 7959 | return false0; |
| 7960 | |
| 7961 | /* |
| 7962 | * We compare against max which means we must take |
| 7963 | * the increased cdclk requirement into account when |
| 7964 | * calculating the new cdclk. |
| 7965 | * |
| 7966 | * Should measure whether using a lower cdclk w/o IPS |
| 7967 | */ |
| 7968 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) && |
| 7969 | crtc_state->pixel_rate > dev_priv->max_cdclk_freq * 95 / 100) |
| 7970 | return false0; |
| 7971 | |
| 7972 | return true1; |
| 7973 | } |
| 7974 | |
| 7975 | static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state) |
| 7976 | { |
| 7977 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 7978 | to_i915(crtc_state->uapi.crtc->dev); |
| 7979 | struct intel_atomic_state *state = |
| 7980 | to_intel_atomic_state(crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 7981 | |
| 7982 | crtc_state->ips_enabled = false0; |
| 7983 | |
| 7984 | if (!hsw_crtc_state_ips_capable(crtc_state)) |
| 7985 | return 0; |
| 7986 | |
| 7987 | /* |
| 7988 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets |
| 7989 | * enabled and disabled dynamically based on package C states, |
| 7990 | * user space can't make reliable use of the CRCs, so let's just |
| 7991 | * completely disable it. |
| 7992 | */ |
| 7993 | if (crtc_state->crc_enabled) |
| 7994 | return 0; |
| 7995 | |
| 7996 | /* IPS should be fine as long as at least one plane is enabled. */ |
| 7997 | if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)(1UL << (PLANE_CURSOR)))) |
| 7998 | return 0; |
| 7999 | |
| 8000 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 8001 | const struct intel_cdclk_state *cdclk_state; |
| 8002 | |
| 8003 | cdclk_state = intel_atomic_get_cdclk_state(state); |
| 8004 | if (IS_ERR(cdclk_state)) |
| 8005 | return PTR_ERR(cdclk_state); |
| 8006 | |
| 8007 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
| 8008 | if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100) |
| 8009 | return 0; |
| 8010 | } |
| 8011 | |
| 8012 | crtc_state->ips_enabled = true1; |
| 8013 | |
| 8014 | return 0; |
| 8015 | } |
| 8016 | |
| 8017 | static bool_Bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
| 8018 | { |
| 8019 | const struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8020 | |
| 8021 | /* GDG double wide on either pipe, otherwise pipe A only */ |
| 8022 | return INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4 && |
| 8023 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G)); |
| 8024 | } |
| 8025 | |
| 8026 | static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state) |
| 8027 | { |
| 8028 | u32 pixel_rate = crtc_state->hw.adjusted_mode.crtc_clock; |
| 8029 | unsigned int pipe_w, pipe_h, pfit_w, pfit_h; |
| 8030 | |
| 8031 | /* |
| 8032 | * We only use IF-ID interlacing. If we ever use |
| 8033 | * PF-ID we'll need to adjust the pixel_rate here. |
| 8034 | */ |
| 8035 | |
| 8036 | if (!crtc_state->pch_pfit.enabled) |
| 8037 | return pixel_rate; |
| 8038 | |
| 8039 | pipe_w = crtc_state->pipe_src_w; |
| 8040 | pipe_h = crtc_state->pipe_src_h; |
| 8041 | |
| 8042 | pfit_w = drm_rect_width(&crtc_state->pch_pfit.dst); |
| 8043 | pfit_h = drm_rect_height(&crtc_state->pch_pfit.dst); |
| 8044 | |
| 8045 | if (pipe_w < pfit_w) |
| 8046 | pipe_w = pfit_w; |
| 8047 | if (pipe_h < pfit_h) |
| 8048 | pipe_h = pfit_h; |
| 8049 | |
| 8050 | if (drm_WARN_ON(crtc_state->uapi.crtc->dev,({ int __ret = !!((!pfit_w || !pfit_h)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((crtc_state->uapi.crtc->dev)) ->dev), "", "drm_WARN_ON(" "!pfit_w || !pfit_h" ")"); __builtin_expect (!!(__ret), 0); }) |
| 8051 | !pfit_w || !pfit_h)({ int __ret = !!((!pfit_w || !pfit_h)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((crtc_state->uapi.crtc->dev)) ->dev), "", "drm_WARN_ON(" "!pfit_w || !pfit_h" ")"); __builtin_expect (!!(__ret), 0); })) |
| 8052 | return pixel_rate; |
| 8053 | |
| 8054 | return div_u64(mul_u32_u32(pixel_rate, pipe_w * pipe_h), |
| 8055 | pfit_w * pfit_h); |
| 8056 | } |
| 8057 | |
| 8058 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
| 8059 | { |
| 8060 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 8061 | |
| 8062 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) |
| 8063 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ |
| 8064 | crtc_state->pixel_rate = |
| 8065 | crtc_state->hw.adjusted_mode.crtc_clock; |
| 8066 | else |
| 8067 | crtc_state->pixel_rate = |
| 8068 | ilk_pipe_pixel_rate(crtc_state); |
| 8069 | } |
| 8070 | |
| 8071 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
| 8072 | struct intel_crtc_state *pipe_config) |
| 8073 | { |
| 8074 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8075 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
| 8076 | int clock_limit = dev_priv->max_dotclk_freq; |
| 8077 | |
| 8078 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) { |
| 8079 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
| 8080 | |
| 8081 | /* |
| 8082 | * Enable double wide mode when the dot clock |
| 8083 | * is > 90% of the (display) core speed. |
| 8084 | */ |
| 8085 | if (intel_crtc_supports_double_wide(crtc) && |
| 8086 | adjusted_mode->crtc_clock > clock_limit) { |
| 8087 | clock_limit = dev_priv->max_dotclk_freq; |
| 8088 | pipe_config->double_wide = true1; |
| 8089 | } |
| 8090 | } |
| 8091 | |
| 8092 | if (adjusted_mode->crtc_clock > clock_limit) { |
| 8093 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n" , adjusted_mode->crtc_clock, clock_limit, yesno(pipe_config ->double_wide)) |
| 8094 | "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n" , adjusted_mode->crtc_clock, clock_limit, yesno(pipe_config ->double_wide)) |
| 8095 | adjusted_mode->crtc_clock, clock_limit,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n" , adjusted_mode->crtc_clock, clock_limit, yesno(pipe_config ->double_wide)) |
| 8096 | yesno(pipe_config->double_wide))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n" , adjusted_mode->crtc_clock, clock_limit, yesno(pipe_config ->double_wide)); |
| 8097 | return -EINVAL22; |
| 8098 | } |
| 8099 | |
| 8100 | if ((pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
| 8101 | pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) && |
| 8102 | pipe_config->hw.ctm) { |
| 8103 | /* |
| 8104 | * There is only one pipe CSC unit per pipe, and we need that |
| 8105 | * for output conversion from RGB->YCBCR. So if CTM is already |
| 8106 | * applied we can't support YCBCR420 output. |
| 8107 | */ |
| 8108 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "YCBCR420 and CTM together are not possible\n" ) |
| 8109 | "YCBCR420 and CTM together are not possible\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "YCBCR420 and CTM together are not possible\n" ); |
| 8110 | return -EINVAL22; |
| 8111 | } |
| 8112 | |
| 8113 | /* |
| 8114 | * Pipe horizontal size must be even in: |
| 8115 | * - DVO ganged mode |
| 8116 | * - LVDS dual channel mode |
| 8117 | * - Double wide pipe |
| 8118 | */ |
| 8119 | if (pipe_config->pipe_src_w & 1) { |
| 8120 | if (pipe_config->double_wide) { |
| 8121 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Odd pipe source width not supported with double wide pipe\n" ) |
| 8122 | "Odd pipe source width not supported with double wide pipe\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Odd pipe source width not supported with double wide pipe\n" ); |
| 8123 | return -EINVAL22; |
| 8124 | } |
| 8125 | |
| 8126 | if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
| 8127 | intel_is_dual_link_lvds(dev_priv)) { |
| 8128 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Odd pipe source width not supported with dual link LVDS\n" ) |
| 8129 | "Odd pipe source width not supported with dual link LVDS\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Odd pipe source width not supported with dual link LVDS\n" ); |
| 8130 | return -EINVAL22; |
| 8131 | } |
| 8132 | } |
| 8133 | |
| 8134 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
| 8135 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. |
| 8136 | */ |
| 8137 | if ((INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) > 4 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) && |
| 8138 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
| 8139 | return -EINVAL22; |
| 8140 | |
| 8141 | intel_crtc_compute_pixel_rate(pipe_config); |
| 8142 | |
| 8143 | if (pipe_config->has_pch_encoder) |
| 8144 | return ilk_fdi_compute_config(crtc, pipe_config); |
| 8145 | |
| 8146 | return 0; |
| 8147 | } |
| 8148 | |
| 8149 | static void |
| 8150 | intel_reduce_m_n_ratio(u32 *num, u32 *den) |
| 8151 | { |
| 8152 | while (*num > DATA_LINK_M_N_MASK(0xffffff) || |
| 8153 | *den > DATA_LINK_M_N_MASK(0xffffff)) { |
| 8154 | *num >>= 1; |
| 8155 | *den >>= 1; |
| 8156 | } |
| 8157 | } |
| 8158 | |
| 8159 | static void compute_m_n(unsigned int m, unsigned int n, |
| 8160 | u32 *ret_m, u32 *ret_n, |
| 8161 | bool_Bool constant_n) |
| 8162 | { |
| 8163 | /* |
| 8164 | * Several DP dongles in particular seem to be fussy about |
| 8165 | * too large link M/N values. Give N value as 0x8000 that |
| 8166 | * should be acceptable by specific devices. 0x8000 is the |
| 8167 | * specified fixed N value for asynchronous clock mode, |
| 8168 | * which the devices expect also in synchronous clock mode. |
| 8169 | */ |
| 8170 | if (constant_n) |
| 8171 | *ret_n = DP_LINK_CONSTANT_N_VALUE0x8000; |
| 8172 | else |
| 8173 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX)({ unsigned int __min_a = (roundup_pow_of_two(n)); unsigned int __min_b = ((0x800000)); __min_a < __min_b ? __min_a : __min_b ; }); |
| 8174 | |
| 8175 | *ret_m = div_u64(mul_u32_u32(m, *ret_n), n); |
| 8176 | intel_reduce_m_n_ratio(ret_m, ret_n); |
| 8177 | } |
| 8178 | |
| 8179 | void |
| 8180 | intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, |
| 8181 | int pixel_clock, int link_clock, |
| 8182 | struct intel_link_m_n *m_n, |
| 8183 | bool_Bool constant_n, bool_Bool fec_enable) |
| 8184 | { |
| 8185 | u32 data_clock = bits_per_pixel * pixel_clock; |
| 8186 | |
| 8187 | if (fec_enable) |
| 8188 | data_clock = intel_dp_mode_to_fec_clock(data_clock); |
| 8189 | |
| 8190 | m_n->tu = 64; |
| 8191 | compute_m_n(data_clock, |
| 8192 | link_clock * nlanes * 8, |
| 8193 | &m_n->gmch_m, &m_n->gmch_n, |
| 8194 | constant_n); |
| 8195 | |
| 8196 | compute_m_n(pixel_clock, link_clock, |
| 8197 | &m_n->link_m, &m_n->link_n, |
| 8198 | constant_n); |
| 8199 | } |
| 8200 | |
| 8201 | static void intel_panel_sanitize_ssc(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 8202 | { |
| 8203 | /* |
| 8204 | * There may be no VBT; and if the BIOS enabled SSC we can |
| 8205 | * just keep using it to avoid unnecessary flicker. Whereas if the |
| 8206 | * BIOS isn't using it, don't assume it will work even if the VBT |
| 8207 | * indicates as much. |
| 8208 | */ |
| 8209 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) || HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
| 8210 | bool_Bool bios_lvds_use_ssc = intel_de_read(dev_priv, |
| 8211 | PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) })) & |
| 8212 | DREF_SSC1_ENABLE(1 << 1); |
| 8213 | |
| 8214 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { |
| 8215 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "SSC %s by BIOS, overriding VBT which says %s\n" , enableddisabled(bios_lvds_use_ssc), enableddisabled(dev_priv ->vbt.lvds_use_ssc)) |
| 8216 | "SSC %s by BIOS, overriding VBT which says %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "SSC %s by BIOS, overriding VBT which says %s\n" , enableddisabled(bios_lvds_use_ssc), enableddisabled(dev_priv ->vbt.lvds_use_ssc)) |
| 8217 | enableddisabled(bios_lvds_use_ssc),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "SSC %s by BIOS, overriding VBT which says %s\n" , enableddisabled(bios_lvds_use_ssc), enableddisabled(dev_priv ->vbt.lvds_use_ssc)) |
| 8218 | enableddisabled(dev_priv->vbt.lvds_use_ssc))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "SSC %s by BIOS, overriding VBT which says %s\n" , enableddisabled(bios_lvds_use_ssc), enableddisabled(dev_priv ->vbt.lvds_use_ssc)); |
| 8219 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; |
| 8220 | } |
| 8221 | } |
| 8222 | } |
| 8223 | |
| 8224 | static bool_Bool intel_panel_use_ssc(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 8225 | { |
| 8226 | if (dev_priv->params.panel_use_ssc >= 0) |
| 8227 | return dev_priv->params.panel_use_ssc != 0; |
| 8228 | return dev_priv->vbt.lvds_use_ssc |
| 8229 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE(1<<1)); |
| 8230 | } |
| 8231 | |
| 8232 | static u32 pnv_dpll_compute_fp(struct dpll *dpll) |
| 8233 | { |
| 8234 | return (1 << dpll->n) << 16 | dpll->m2; |
| 8235 | } |
| 8236 | |
| 8237 | static u32 i9xx_dpll_compute_fp(struct dpll *dpll) |
| 8238 | { |
| 8239 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; |
| 8240 | } |
| 8241 | |
| 8242 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
| 8243 | struct intel_crtc_state *crtc_state, |
| 8244 | struct dpll *reduced_clock) |
| 8245 | { |
| 8246 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8247 | u32 fp, fp2 = 0; |
| 8248 | |
| 8249 | if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 8250 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
| 8251 | if (reduced_clock) |
| 8252 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
| 8253 | } else { |
| 8254 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
| 8255 | if (reduced_clock) |
| 8256 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
| 8257 | } |
| 8258 | |
| 8259 | crtc_state->dpll_hw_state.fp0 = fp; |
| 8260 | |
| 8261 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 8262 | reduced_clock) { |
| 8263 | crtc_state->dpll_hw_state.fp1 = fp2; |
| 8264 | } else { |
| 8265 | crtc_state->dpll_hw_state.fp1 = fp; |
| 8266 | } |
| 8267 | } |
| 8268 | |
| 8269 | static void vlv_pllb_recal_opamp(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe |
| 8270 | pipe) |
| 8271 | { |
| 8272 | u32 reg_val; |
| 8273 | |
| 8274 | /* |
| 8275 | * PLLB opamp always calibrates to max value of 0x3f, force enable it |
| 8276 | * and set it to a reasonable value instead. |
| 8277 | */ |
| 8278 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044)))); |
| 8279 | reg_val &= 0xffffff00; |
| 8280 | reg_val |= 0x00000030; |
| 8281 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044))), reg_val); |
| 8282 | |
| 8283 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW130x80ac); |
| 8284 | reg_val &= 0x00ffffff; |
| 8285 | reg_val |= 0x8c000000; |
| 8286 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW130x80ac, reg_val); |
| 8287 | |
| 8288 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044)))); |
| 8289 | reg_val &= 0xffffff00; |
| 8290 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1)((0x8044) + (1) * ((0x8064) - (0x8044))), reg_val); |
| 8291 | |
| 8292 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW130x80ac); |
| 8293 | reg_val &= 0x00ffffff; |
| 8294 | reg_val |= 0xb0000000; |
| 8295 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW130x80ac, reg_val); |
| 8296 | } |
| 8297 | |
| 8298 | static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
| 8299 | const struct intel_link_m_n *m_n) |
| 8300 | { |
| 8301 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 8302 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8303 | enum pipe pipe = crtc->pipe; |
| 8304 | |
| 8305 | intel_de_write(dev_priv, PCH_TRANS_DATA_M1(pipe)((const i915_reg_t){ .reg = (((0xe0030) + (pipe) * ((0xe1030) - (0xe0030)))) }), |
| 8306 | TU_SIZE(m_n->tu)(((m_n->tu) - 1) << 25) | m_n->gmch_m); |
| 8307 | intel_de_write(dev_priv, PCH_TRANS_DATA_N1(pipe)((const i915_reg_t){ .reg = (((0xe0034) + (pipe) * ((0xe1034) - (0xe0034)))) }), m_n->gmch_n); |
| 8308 | intel_de_write(dev_priv, PCH_TRANS_LINK_M1(pipe)((const i915_reg_t){ .reg = (((0xe0040) + (pipe) * ((0xe1040) - (0xe0040)))) }), m_n->link_m); |
| 8309 | intel_de_write(dev_priv, PCH_TRANS_LINK_N1(pipe)((const i915_reg_t){ .reg = (((0xe0044) + (pipe) * ((0xe1044) - (0xe0044)))) }), m_n->link_n); |
| 8310 | } |
| 8311 | |
| 8312 | static bool_Bool transcoder_has_m2_n2(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 8313 | enum transcoder transcoder) |
| 8314 | { |
| 8315 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 8316 | return transcoder == TRANSCODER_EDP; |
| 8317 | |
| 8318 | /* |
| 8319 | * Strictly speaking some registers are available before |
| 8320 | * gen7, but we only support DRRS on gen7+ |
| 8321 | */ |
| 8322 | return IS_GEN(dev_priv, 7)(0 + (&(dev_priv)->__info)->gen == (7)) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW); |
| 8323 | } |
| 8324 | |
| 8325 | static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, |
| 8326 | const struct intel_link_m_n *m_n, |
| 8327 | const struct intel_link_m_n *m2_n2) |
| 8328 | { |
| 8329 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 8330 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8331 | enum pipe pipe = crtc->pipe; |
| 8332 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
| 8333 | |
| 8334 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) { |
| 8335 | intel_de_write(dev_priv, PIPE_DATA_M1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60030) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8336 | TU_SIZE(m_n->tu)(((m_n->tu) - 1) << 25) | m_n->gmch_m); |
| 8337 | intel_de_write(dev_priv, PIPE_DATA_N1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60034) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8338 | m_n->gmch_n); |
| 8339 | intel_de_write(dev_priv, PIPE_LINK_M1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60040) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8340 | m_n->link_m); |
| 8341 | intel_de_write(dev_priv, PIPE_LINK_N1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60044) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8342 | m_n->link_n); |
| 8343 | /* |
| 8344 | * M2_N2 registers are set only if DRRS is supported |
| 8345 | * (to make sure the registers are not unnecessarily accessed). |
| 8346 | */ |
| 8347 | if (m2_n2 && crtc_state->has_drrs && |
| 8348 | transcoder_has_m2_n2(dev_priv, transcoder)) { |
| 8349 | intel_de_write(dev_priv, PIPE_DATA_M2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60038) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8350 | TU_SIZE(m2_n2->tu)(((m2_n2->tu) - 1) << 25) | m2_n2->gmch_m); |
| 8351 | intel_de_write(dev_priv, PIPE_DATA_N2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x6003c) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8352 | m2_n2->gmch_n); |
| 8353 | intel_de_write(dev_priv, PIPE_LINK_M2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60048) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8354 | m2_n2->link_m); |
| 8355 | intel_de_write(dev_priv, PIPE_LINK_N2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x6004c) + ((&(dev_priv)-> __info)->display_mmio_offset))) }), |
| 8356 | m2_n2->link_n); |
| 8357 | } |
| 8358 | } else { |
| 8359 | intel_de_write(dev_priv, PIPE_DATA_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70050) + (pipe) * ((0x71050) - (0x70050)))) }), |
| 8360 | TU_SIZE(m_n->tu)(((m_n->tu) - 1) << 25) | m_n->gmch_m); |
| 8361 | intel_de_write(dev_priv, PIPE_DATA_N_G4X(pipe)((const i915_reg_t){ .reg = (((0x70054) + (pipe) * ((0x71054) - (0x70054)))) }), m_n->gmch_n); |
| 8362 | intel_de_write(dev_priv, PIPE_LINK_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70060) + (pipe) * ((0x71060) - (0x70060)))) }), m_n->link_m); |
| 8363 | intel_de_write(dev_priv, PIPE_LINK_N_G4X(pipe)((const i915_reg_t){ .reg = (((0x70064) + (pipe) * ((0x71064) - (0x70064)))) }), m_n->link_n); |
| 8364 | } |
| 8365 | } |
| 8366 | |
| 8367 | void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n) |
| 8368 | { |
| 8369 | const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL((void *)0); |
| 8370 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev); |
| 8371 | |
| 8372 | if (m_n == M1_N1) { |
| 8373 | dp_m_n = &crtc_state->dp_m_n; |
| 8374 | dp_m2_n2 = &crtc_state->dp_m2_n2; |
| 8375 | } else if (m_n == M2_N2) { |
| 8376 | |
| 8377 | /* |
| 8378 | * M2_N2 registers are not supported. Hence m2_n2 divider value |
| 8379 | * needs to be programmed into M1_N1. |
| 8380 | */ |
| 8381 | dp_m_n = &crtc_state->dp_m2_n2; |
| 8382 | } else { |
| 8383 | drm_err(&i915->drm, "Unsupported divider value\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unsupported divider value\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 8384 | return; |
| 8385 | } |
| 8386 | |
| 8387 | if (crtc_state->has_pch_encoder) |
| 8388 | intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n); |
| 8389 | else |
| 8390 | intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2); |
| 8391 | } |
| 8392 | |
| 8393 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
| 8394 | struct intel_crtc_state *pipe_config) |
| 8395 | { |
| 8396 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV(1 << 13) | |
| 8397 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
| 8398 | if (crtc->pipe != PIPE_A) |
| 8399 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
| 8400 | |
| 8401 | /* DPLL not used with DSI, but still need the rest set up */ |
| 8402 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
| 8403 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE(1 << 31) | |
| 8404 | DPLL_EXT_BUFFER_ENABLE_VLV(1 << 30); |
| 8405 | |
| 8406 | pipe_config->dpll_hw_state.dpll_md = |
| 8407 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT8; |
| 8408 | } |
| 8409 | |
| 8410 | static void chv_compute_dpll(struct intel_crtc *crtc, |
| 8411 | struct intel_crtc_state *pipe_config) |
| 8412 | { |
| 8413 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV(1 << 13) | |
| 8414 | DPLL_REF_CLK_ENABLE_VLV(1 << 29) | DPLL_VGA_MODE_DIS(1 << 28); |
| 8415 | if (crtc->pipe != PIPE_A) |
| 8416 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV(1 << 14); |
| 8417 | |
| 8418 | /* DPLL not used with DSI, but still need the rest set up */ |
| 8419 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
| 8420 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE(1 << 31); |
| 8421 | |
| 8422 | pipe_config->dpll_hw_state.dpll_md = |
| 8423 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT8; |
| 8424 | } |
| 8425 | |
| 8426 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
| 8427 | const struct intel_crtc_state *pipe_config) |
| 8428 | { |
| 8429 | struct drm_device *dev = crtc->base.dev; |
| 8430 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 8431 | enum pipe pipe = crtc->pipe; |
| 8432 | u32 mdiv; |
| 8433 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
| 8434 | u32 coreclk, reg_val; |
| 8435 | |
| 8436 | /* Enable Refclk */ |
| 8437 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), |
| 8438 | pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE(1 << 31) | DPLL_EXT_BUFFER_ENABLE_VLV(1 << 30))); |
| 8439 | |
| 8440 | /* No need to actually set up the DPLL with DSI */ |
| 8441 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) == 0) |
| 8442 | return; |
| 8443 | |
| 8444 | vlv_dpio_get(dev_priv); |
| 8445 | |
| 8446 | bestn = pipe_config->dpll.n; |
| 8447 | bestm1 = pipe_config->dpll.m1; |
| 8448 | bestm2 = pipe_config->dpll.m2; |
| 8449 | bestp1 = pipe_config->dpll.p1; |
| 8450 | bestp2 = pipe_config->dpll.p2; |
| 8451 | |
| 8452 | /* See eDP HDMI DPIO driver vbios notes doc */ |
| 8453 | |
| 8454 | /* PLL B needs special handling */ |
| 8455 | if (pipe == PIPE_B) |
| 8456 | vlv_pllb_recal_opamp(dev_priv, pipe); |
| 8457 | |
| 8458 | /* Set up Tx target for periodic Rcomp update */ |
| 8459 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST0xc044, 0x0100000f); |
| 8460 | |
| 8461 | /* Disable target IRef on PLL */ |
| 8462 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)((0x8040) + (pipe) * ((0x8060) - (0x8040)))); |
| 8463 | reg_val &= 0x00ffffff; |
| 8464 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe)((0x8040) + (pipe) * ((0x8060) - (0x8040))), reg_val); |
| 8465 | |
| 8466 | /* Disable fast lock */ |
| 8467 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW00x8100, 0x610); |
| 8468 | |
| 8469 | /* Set idtafcrecal before PLL is enabled */ |
| 8470 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT(8)) | (bestm2 & DPIO_M2DIV_MASK0xff)); |
| 8471 | mdiv |= ((bestp1 << DPIO_P1_SHIFT(21)) | (bestp2 << DPIO_P2_SHIFT(16))); |
| 8472 | mdiv |= ((bestn << DPIO_N_SHIFT(12))); |
| 8473 | mdiv |= (1 << DPIO_K_SHIFT(24)); |
| 8474 | |
| 8475 | /* |
| 8476 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, |
| 8477 | * but we don't support that). |
| 8478 | * Note: don't use the DAC post divider as it seems unstable. |
| 8479 | */ |
| 8480 | mdiv |= (DPIO_POST_DIV_HDMIDP1 << DPIO_POST_DIV_SHIFT(28)); |
| 8481 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe)((0x800c) + (pipe) * ((0x802c) - (0x800c))), mdiv); |
| 8482 | |
| 8483 | mdiv |= DPIO_ENABLE_CALIBRATION(1 << 11); |
| 8484 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe)((0x800c) + (pipe) * ((0x802c) - (0x800c))), mdiv); |
| 8485 | |
| 8486 | /* Set HBR and RBR LPF coefficients */ |
| 8487 | if (pipe_config->port_clock == 162000 || |
| 8488 | intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || |
| 8489 | intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) |
| 8490 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe)((0x8048) + (pipe) * ((0x8068) - (0x8048))), |
| 8491 | 0x009f0003); |
| 8492 | else |
| 8493 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe)((0x8048) + (pipe) * ((0x8068) - (0x8048))), |
| 8494 | 0x00d0000f); |
| 8495 | |
| 8496 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
| 8497 | /* Use SSC source */ |
| 8498 | if (pipe == PIPE_A) |
| 8499 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
| 8500 | 0x0df40000); |
| 8501 | else |
| 8502 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
| 8503 | 0x0df70000); |
| 8504 | } else { /* HDMI or VGA */ |
| 8505 | /* Use bend source */ |
| 8506 | if (pipe == PIPE_A) |
| 8507 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
| 8508 | 0x0df70000); |
| 8509 | else |
| 8510 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe)((0x8014) + (pipe) * ((0x8034) - (0x8014))), |
| 8511 | 0x0df40000); |
| 8512 | } |
| 8513 | |
| 8514 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)((0x801c) + (pipe) * ((0x803c) - (0x801c)))); |
| 8515 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
| 8516 | if (intel_crtc_has_dp_encoder(pipe_config)) |
| 8517 | coreclk |= 0x01000000; |
| 8518 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe)((0x801c) + (pipe) * ((0x803c) - (0x801c))), coreclk); |
| 8519 | |
| 8520 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe)((0x804c) + (pipe) * ((0x806c) - (0x804c))), 0x87871000); |
| 8521 | |
| 8522 | vlv_dpio_put(dev_priv); |
| 8523 | } |
| 8524 | |
| 8525 | static void chv_prepare_pll(struct intel_crtc *crtc, |
| 8526 | const struct intel_crtc_state *pipe_config) |
| 8527 | { |
| 8528 | struct drm_device *dev = crtc->base.dev; |
| 8529 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 8530 | enum pipe pipe = crtc->pipe; |
| 8531 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 8532 | u32 loopfilter, tribuf_calcntr; |
| 8533 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
| 8534 | u32 dpio_val; |
| 8535 | int vco; |
| 8536 | |
| 8537 | /* Enable Refclk and SSC */ |
| 8538 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), |
| 8539 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE(1 << 31)); |
| 8540 | |
| 8541 | /* No need to actually set up the DPLL with DSI */ |
| 8542 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) == 0) |
| 8543 | return; |
| 8544 | |
| 8545 | bestn = pipe_config->dpll.n; |
| 8546 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; |
| 8547 | bestm1 = pipe_config->dpll.m1; |
| 8548 | bestm2 = pipe_config->dpll.m2 >> 22; |
| 8549 | bestp1 = pipe_config->dpll.p1; |
| 8550 | bestp2 = pipe_config->dpll.p2; |
| 8551 | vco = pipe_config->dpll.vco; |
| 8552 | dpio_val = 0; |
Value stored to 'dpio_val' is never read | |
| 8553 | loopfilter = 0; |
| 8554 | |
| 8555 | vlv_dpio_get(dev_priv); |
| 8556 | |
| 8557 | /* p1 and p2 divider */ |
| 8558 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port)((0x8134) + (port) * ((0x8080) - (0x8134))), |
| 8559 | 5 << DPIO_CHV_S1_DIV_SHIFT21 | |
| 8560 | bestp1 << DPIO_CHV_P1_DIV_SHIFT13 | |
| 8561 | bestp2 << DPIO_CHV_P2_DIV_SHIFT8 | |
| 8562 | 1 << DPIO_CHV_K_DIV_SHIFT4); |
| 8563 | |
| 8564 | /* Feedback post-divider - m2 */ |
| 8565 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port)((0x8000) + (port) * ((0x8180) - (0x8000))), bestm2); |
| 8566 | |
| 8567 | /* Feedback refclk divider - n and m1 */ |
| 8568 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port)((0x8004) + (port) * ((0x8184) - (0x8004))), |
| 8569 | DPIO_CHV_M1_DIV_BY_2(0 << 0) | |
| 8570 | 1 << DPIO_CHV_N_DIV_SHIFT8); |
| 8571 | |
| 8572 | /* M2 fraction division */ |
| 8573 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port)((0x8008) + (port) * ((0x8188) - (0x8008))), bestm2_frac); |
| 8574 | |
| 8575 | /* M2 fraction division enable */ |
| 8576 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)((0x800c) + (port) * ((0x818c) - (0x800c)))); |
| 8577 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK(0xF << 0) | DPIO_CHV_FRAC_DIV_EN(1 << 16)); |
| 8578 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT0); |
| 8579 | if (bestm2_frac) |
| 8580 | dpio_val |= DPIO_CHV_FRAC_DIV_EN(1 << 16); |
| 8581 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port)((0x800c) + (port) * ((0x818c) - (0x800c))), dpio_val); |
| 8582 | |
| 8583 | /* Program digital lock detect threshold */ |
| 8584 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)((0x8024) + (port) * ((0x81A4) - (0x8024)))); |
| 8585 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK(7 << 1) | |
| 8586 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1); |
| 8587 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT1); |
| 8588 | if (!bestm2_frac) |
| 8589 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE1; |
| 8590 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port)((0x8024) + (port) * ((0x81A4) - (0x8024))), dpio_val); |
| 8591 | |
| 8592 | /* Loop filter */ |
| 8593 | if (vco == 5400000) { |
| 8594 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT0); |
| 8595 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT8); |
| 8596 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
| 8597 | tribuf_calcntr = 0x9; |
| 8598 | } else if (vco <= 6200000) { |
| 8599 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT0); |
| 8600 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT8); |
| 8601 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
| 8602 | tribuf_calcntr = 0x9; |
| 8603 | } else if (vco <= 6480000) { |
| 8604 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT0); |
| 8605 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT8); |
| 8606 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
| 8607 | tribuf_calcntr = 0x8; |
| 8608 | } else { |
| 8609 | /* Not supported. Apply the same limits as in the max case */ |
| 8610 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT0); |
| 8611 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT8); |
| 8612 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT16); |
| 8613 | tribuf_calcntr = 0; |
| 8614 | } |
| 8615 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port)((0x8018) + (port) * ((0x8198) - (0x8018))), loopfilter); |
| 8616 | |
| 8617 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)((0x8020) + (port) * ((0x81A0) - (0x8020)))); |
| 8618 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK(0x3FF << 0); |
| 8619 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT0); |
| 8620 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port)((0x8020) + (port) * ((0x81A0) - (0x8020))), dpio_val); |
| 8621 | |
| 8622 | /* AFC Recal */ |
| 8623 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138))), |
| 8624 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)((0x8138) + (port) * ((0x8084) - (0x8138)))) | |
| 8625 | DPIO_AFC_RECAL(1 << 14)); |
| 8626 | |
| 8627 | vlv_dpio_put(dev_priv); |
| 8628 | } |
| 8629 | |
| 8630 | /** |
| 8631 | * vlv_force_pll_on - forcibly enable just the PLL |
| 8632 | * @dev_priv: i915 private structure |
| 8633 | * @pipe: pipe PLL to enable |
| 8634 | * @dpll: PLL configuration |
| 8635 | * |
| 8636 | * Enable the PLL for @pipe using the supplied @dpll config. To be used |
| 8637 | * in cases where we need the PLL enabled even when @pipe is not going to |
| 8638 | * be enabled. |
| 8639 | */ |
| 8640 | int vlv_force_pll_on(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe, |
| 8641 | const struct dpll *dpll) |
| 8642 | { |
| 8643 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 8644 | struct intel_crtc_state *pipe_config; |
| 8645 | |
| 8646 | pipe_config = intel_crtc_state_alloc(crtc); |
| 8647 | if (!pipe_config) |
| 8648 | return -ENOMEM12; |
| 8649 | |
| 8650 | pipe_config->cpu_transcoder = (enum transcoder)pipe; |
| 8651 | pipe_config->pixel_multiplier = 1; |
| 8652 | pipe_config->dpll = *dpll; |
| 8653 | |
| 8654 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 8655 | chv_compute_dpll(crtc, pipe_config); |
| 8656 | chv_prepare_pll(crtc, pipe_config); |
| 8657 | chv_enable_pll(crtc, pipe_config); |
| 8658 | } else { |
| 8659 | vlv_compute_dpll(crtc, pipe_config); |
| 8660 | vlv_prepare_pll(crtc, pipe_config); |
| 8661 | vlv_enable_pll(crtc, pipe_config); |
| 8662 | } |
| 8663 | |
| 8664 | kfree(pipe_config); |
| 8665 | |
| 8666 | return 0; |
| 8667 | } |
| 8668 | |
| 8669 | /** |
| 8670 | * vlv_force_pll_off - forcibly disable just the PLL |
| 8671 | * @dev_priv: i915 private structure |
| 8672 | * @pipe: pipe PLL to disable |
| 8673 | * |
| 8674 | * Disable the PLL for @pipe. To be used in cases where we need |
| 8675 | * the PLL enabled even when @pipe is not going to be enabled. |
| 8676 | */ |
| 8677 | void vlv_force_pll_off(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 8678 | { |
| 8679 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 8680 | chv_disable_pll(dev_priv, pipe); |
| 8681 | else |
| 8682 | vlv_disable_pll(dev_priv, pipe); |
| 8683 | } |
| 8684 | |
| 8685 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
| 8686 | struct intel_crtc_state *crtc_state, |
| 8687 | struct dpll *reduced_clock) |
| 8688 | { |
| 8689 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8690 | u32 dpll; |
| 8691 | struct dpll *clock = &crtc_state->dpll; |
| 8692 | |
| 8693 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
| 8694 | |
| 8695 | dpll = DPLL_VGA_MODE_DIS(1 << 28); |
| 8696 | |
| 8697 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
| 8698 | dpll |= DPLLB_MODE_LVDS(2 << 26); |
| 8699 | else |
| 8700 | dpll |= DPLLB_MODE_DAC_SERIAL(1 << 26); |
| 8701 | |
| 8702 | if (IS_I945G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945G) || IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) || |
| 8703 | IS_G33(dev_priv)IS_PLATFORM(dev_priv, INTEL_G33) || IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 8704 | dpll |= (crtc_state->pixel_multiplier - 1) |
| 8705 | << SDVO_MULTIPLIER_SHIFT_HIRES4; |
| 8706 | } |
| 8707 | |
| 8708 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
| 8709 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
| 8710 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
| 8711 | |
| 8712 | if (intel_crtc_has_dp_encoder(crtc_state)) |
| 8713 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
| 8714 | |
| 8715 | /* compute bitmask from p1 value */ |
| 8716 | if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) |
| 8717 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW15; |
| 8718 | else { |
| 8719 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
| 8720 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) && reduced_clock) |
| 8721 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT0; |
| 8722 | } |
| 8723 | switch (clock->p2) { |
| 8724 | case 5: |
| 8725 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5(1 << 24); |
| 8726 | break; |
| 8727 | case 7: |
| 8728 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7(1 << 24); |
| 8729 | break; |
| 8730 | case 10: |
| 8731 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10(0 << 24); |
| 8732 | break; |
| 8733 | case 14: |
| 8734 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14(0 << 24); |
| 8735 | break; |
| 8736 | } |
| 8737 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 8738 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT9); |
| 8739 | |
| 8740 | if (crtc_state->sdvo_tv_clock) |
| 8741 | dpll |= PLL_REF_INPUT_TVCLKINBC(2 << 13); |
| 8742 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 8743 | intel_panel_use_ssc(dev_priv)) |
| 8744 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13); |
| 8745 | else |
| 8746 | dpll |= PLL_REF_INPUT_DREFCLK(0 << 13); |
| 8747 | |
| 8748 | dpll |= DPLL_VCO_ENABLE(1 << 31); |
| 8749 | crtc_state->dpll_hw_state.dpll = dpll; |
| 8750 | |
| 8751 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 8752 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
| 8753 | << DPLL_MD_UDI_MULTIPLIER_SHIFT8; |
| 8754 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
| 8755 | } |
| 8756 | } |
| 8757 | |
| 8758 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
| 8759 | struct intel_crtc_state *crtc_state, |
| 8760 | struct dpll *reduced_clock) |
| 8761 | { |
| 8762 | struct drm_device *dev = crtc->base.dev; |
| 8763 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 8764 | u32 dpll; |
| 8765 | struct dpll *clock = &crtc_state->dpll; |
| 8766 | |
| 8767 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
| 8768 | |
| 8769 | dpll = DPLL_VGA_MODE_DIS(1 << 28); |
| 8770 | |
| 8771 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 8772 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
| 8773 | } else { |
| 8774 | if (clock->p1 == 2) |
| 8775 | dpll |= PLL_P1_DIVIDE_BY_TWO(1 << 21); |
| 8776 | else |
| 8777 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
| 8778 | if (clock->p2 == 4) |
| 8779 | dpll |= PLL_P2_DIVIDE_BY_4(1 << 23); |
| 8780 | } |
| 8781 | |
| 8782 | /* |
| 8783 | * Bspec: |
| 8784 | * "[Almador Errata}: For the correct operation of the muxed DVO pins |
| 8785 | * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, |
| 8786 | * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock |
| 8787 | * Enable) must be set to “1” in both the DPLL A Control Register |
| 8788 | * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." |
| 8789 | * |
| 8790 | * For simplicity We simply keep both bits always enabled in |
| 8791 | * both DPLLS. The spec says we should disable the DVO 2X clock |
| 8792 | * when not needed, but this seems to work fine in practice. |
| 8793 | */ |
| 8794 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) || |
| 8795 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) |
| 8796 | dpll |= DPLL_DVO_2X_MODE(1 << 30); |
| 8797 | |
| 8798 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 8799 | intel_panel_use_ssc(dev_priv)) |
| 8800 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13); |
| 8801 | else |
| 8802 | dpll |= PLL_REF_INPUT_DREFCLK(0 << 13); |
| 8803 | |
| 8804 | dpll |= DPLL_VCO_ENABLE(1 << 31); |
| 8805 | crtc_state->dpll_hw_state.dpll = dpll; |
| 8806 | } |
| 8807 | |
| 8808 | static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) |
| 8809 | { |
| 8810 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 8811 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8812 | enum pipe pipe = crtc->pipe; |
| 8813 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
| 8814 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
| 8815 | u32 crtc_vtotal, crtc_vblank_end; |
| 8816 | int vsyncshift = 0; |
| 8817 | |
| 8818 | /* We need to be careful not to changed the adjusted mode, for otherwise |
| 8819 | * the hw state checker will get angry at the mismatch. */ |
| 8820 | crtc_vtotal = adjusted_mode->crtc_vtotal; |
| 8821 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; |
| 8822 | |
| 8823 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) { |
| 8824 | /* the chip adds 2 halflines automatically */ |
| 8825 | crtc_vtotal -= 1; |
| 8826 | crtc_vblank_end -= 1; |
| 8827 | |
| 8828 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
| 8829 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
| 8830 | else |
| 8831 | vsyncshift = adjusted_mode->crtc_hsync_start - |
| 8832 | adjusted_mode->crtc_htotal / 2; |
| 8833 | if (vsyncshift < 0) |
| 8834 | vsyncshift += adjusted_mode->crtc_htotal; |
| 8835 | } |
| 8836 | |
| 8837 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) > 3) |
| 8838 | intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60028) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8839 | vsyncshift); |
| 8840 | |
| 8841 | intel_de_write(dev_priv, HTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60000) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8842 | (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16)); |
| 8843 | intel_de_write(dev_priv, HBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60004) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8844 | (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
| 8845 | intel_de_write(dev_priv, HSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60008) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8846 | (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
| 8847 | |
| 8848 | intel_de_write(dev_priv, VTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x6000c) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8849 | (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16)); |
| 8850 | intel_de_write(dev_priv, VBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60010) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8851 | (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16)); |
| 8852 | intel_de_write(dev_priv, VSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60014) + ((&(dev_priv )->__info)->display_mmio_offset))) }), |
| 8853 | (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
| 8854 | |
| 8855 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
| 8856 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is |
| 8857 | * documented on the DDI_FUNC_CTL register description, EDP Input Select |
| 8858 | * bits. */ |
| 8859 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && cpu_transcoder == TRANSCODER_EDP && |
| 8860 | (pipe == PIPE_B || pipe == PIPE_C)) |
| 8861 | intel_de_write(dev_priv, VTOTAL(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x6000c) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), |
| 8862 | intel_de_read(dev_priv, VTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x6000c) + ((&(dev_priv )->__info)->display_mmio_offset))) }))); |
| 8863 | |
| 8864 | } |
| 8865 | |
| 8866 | static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) |
| 8867 | { |
| 8868 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 8869 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8870 | enum pipe pipe = crtc->pipe; |
| 8871 | |
| 8872 | /* pipesrc controls the size that is scaled from, which should |
| 8873 | * always be the user's requested size. |
| 8874 | */ |
| 8875 | intel_de_write(dev_priv, PIPESRC(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x6001c) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), |
| 8876 | ((crtc_state->pipe_src_w - 1) << 16) | (crtc_state->pipe_src_h - 1)); |
| 8877 | } |
| 8878 | |
| 8879 | static bool_Bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) |
| 8880 | { |
| 8881 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 8882 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
| 8883 | |
| 8884 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 8885 | return false0; |
| 8886 | |
| 8887 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || |
| 8888 | IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 8889 | return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })) & PIPECONF_INTERLACE_MASK_HSW(3 << 21); |
| 8890 | else |
| 8891 | return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })) & PIPECONF_INTERLACE_MASK(7 << 21); |
| 8892 | } |
| 8893 | |
| 8894 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
| 8895 | struct intel_crtc_state *pipe_config) |
| 8896 | { |
| 8897 | struct drm_device *dev = crtc->base.dev; |
| 8898 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 8899 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 8900 | u32 tmp; |
| 8901 | |
| 8902 | tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60000) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8903 | pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
| 8904 | pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; |
| 8905 | |
| 8906 | if (!transcoder_is_dsi(cpu_transcoder)) { |
| 8907 | tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60004) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8908 | pipe_config->hw.adjusted_mode.crtc_hblank_start = |
| 8909 | (tmp & 0xffff) + 1; |
| 8910 | pipe_config->hw.adjusted_mode.crtc_hblank_end = |
| 8911 | ((tmp >> 16) & 0xffff) + 1; |
| 8912 | } |
| 8913 | tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60008) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8914 | pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
| 8915 | pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 8916 | |
| 8917 | tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x6000c) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8918 | pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
| 8919 | pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; |
| 8920 | |
| 8921 | if (!transcoder_is_dsi(cpu_transcoder)) { |
| 8922 | tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60010) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8923 | pipe_config->hw.adjusted_mode.crtc_vblank_start = |
| 8924 | (tmp & 0xffff) + 1; |
| 8925 | pipe_config->hw.adjusted_mode.crtc_vblank_end = |
| 8926 | ((tmp >> 16) & 0xffff) + 1; |
| 8927 | } |
| 8928 | tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60014) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8929 | pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
| 8930 | pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; |
| 8931 | |
| 8932 | if (intel_pipe_is_interlaced(pipe_config)) { |
| 8933 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE(1<<4); |
| 8934 | pipe_config->hw.adjusted_mode.crtc_vtotal += 1; |
| 8935 | pipe_config->hw.adjusted_mode.crtc_vblank_end += 1; |
| 8936 | } |
| 8937 | } |
| 8938 | |
| 8939 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, |
| 8940 | struct intel_crtc_state *pipe_config) |
| 8941 | { |
| 8942 | struct drm_device *dev = crtc->base.dev; |
| 8943 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 8944 | u32 tmp; |
| 8945 | |
| 8946 | tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(crtc->pipe)] - (&(dev_priv)->__info) ->trans_offsets[TRANSCODER_A] + (0x6001c) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 8947 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
| 8948 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; |
| 8949 | |
| 8950 | pipe_config->hw.mode.vdisplay = pipe_config->pipe_src_h; |
| 8951 | pipe_config->hw.mode.hdisplay = pipe_config->pipe_src_w; |
| 8952 | } |
| 8953 | |
| 8954 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
| 8955 | struct intel_crtc_state *pipe_config) |
| 8956 | { |
| 8957 | mode->hdisplay = pipe_config->hw.adjusted_mode.crtc_hdisplay; |
| 8958 | mode->htotal = pipe_config->hw.adjusted_mode.crtc_htotal; |
| 8959 | mode->hsync_start = pipe_config->hw.adjusted_mode.crtc_hsync_start; |
| 8960 | mode->hsync_end = pipe_config->hw.adjusted_mode.crtc_hsync_end; |
| 8961 | |
| 8962 | mode->vdisplay = pipe_config->hw.adjusted_mode.crtc_vdisplay; |
| 8963 | mode->vtotal = pipe_config->hw.adjusted_mode.crtc_vtotal; |
| 8964 | mode->vsync_start = pipe_config->hw.adjusted_mode.crtc_vsync_start; |
| 8965 | mode->vsync_end = pipe_config->hw.adjusted_mode.crtc_vsync_end; |
| 8966 | |
| 8967 | mode->flags = pipe_config->hw.adjusted_mode.flags; |
| 8968 | mode->type = DRM_MODE_TYPE_DRIVER(1<<6); |
| 8969 | |
| 8970 | mode->clock = pipe_config->hw.adjusted_mode.crtc_clock; |
| 8971 | |
| 8972 | drm_mode_set_name(mode); |
| 8973 | } |
| 8974 | |
| 8975 | static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) |
| 8976 | { |
| 8977 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 8978 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 8979 | u32 pipeconf; |
| 8980 | |
| 8981 | pipeconf = 0; |
| 8982 | |
| 8983 | /* we keep both pipes enabled on 830 */ |
| 8984 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 8985 | pipeconf |= intel_de_read(dev_priv, PIPECONF(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })) & PIPECONF_ENABLE(1 << 31); |
| 8986 | |
| 8987 | if (crtc_state->double_wide) |
| 8988 | pipeconf |= PIPECONF_DOUBLE_WIDE(1 << 30); |
| 8989 | |
| 8990 | /* only g4x and later have fancy bpc/dither controls */ |
| 8991 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || |
| 8992 | IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 8993 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
| 8994 | if (crtc_state->dither && crtc_state->pipe_bpp != 30) |
| 8995 | pipeconf |= PIPECONF_DITHER_EN(1 << 4) | |
| 8996 | PIPECONF_DITHER_TYPE_SP(0 << 2); |
| 8997 | |
| 8998 | switch (crtc_state->pipe_bpp) { |
| 8999 | case 18: |
| 9000 | pipeconf |= PIPECONF_6BPC(2 << 5); |
| 9001 | break; |
| 9002 | case 24: |
| 9003 | pipeconf |= PIPECONF_8BPC(0 << 5); |
| 9004 | break; |
| 9005 | case 30: |
| 9006 | pipeconf |= PIPECONF_10BPC(1 << 5); |
| 9007 | break; |
| 9008 | default: |
| 9009 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 9010 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 9010); } while (0); |
| 9011 | } |
| 9012 | } |
| 9013 | |
| 9014 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE(1<<4)) { |
| 9015 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4 || |
| 9016 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
| 9017 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION(6 << 21); |
| 9018 | else |
| 9019 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT(5 << 21); |
| 9020 | } else { |
| 9021 | pipeconf |= PIPECONF_PROGRESSIVE(0 << 21); |
| 9022 | } |
| 9023 | |
| 9024 | if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) && |
| 9025 | crtc_state->limited_color_range) |
| 9026 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT(1 << 13); |
| 9027 | |
| 9028 | pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode)((crtc_state->gamma_mode) << 24); |
| 9029 | |
| 9030 | pipeconf |= PIPECONF_FRAME_START_DELAY(0)((0) << 27); |
| 9031 | |
| 9032 | intel_de_write(dev_priv, PIPECONF(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) }), pipeconf); |
| 9033 | intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 9034 | } |
| 9035 | |
| 9036 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
| 9037 | struct intel_crtc_state *crtc_state) |
| 9038 | { |
| 9039 | struct drm_device *dev = crtc->base.dev; |
| 9040 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 9041 | const struct intel_limit *limit; |
| 9042 | int refclk = 48000; |
| 9043 | |
| 9044 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 9045 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 9046 | |
| 9047 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 9048 | if (intel_panel_use_ssc(dev_priv)) { |
| 9049 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 9050 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9051 | "using SSC reference clock of %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9052 | refclk)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
| 9053 | } |
| 9054 | |
| 9055 | limit = &intel_limits_i8xx_lvds; |
| 9056 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
| 9057 | limit = &intel_limits_i8xx_dvo; |
| 9058 | } else { |
| 9059 | limit = &intel_limits_i8xx_dac; |
| 9060 | } |
| 9061 | |
| 9062 | if (!crtc_state->clock_set && |
| 9063 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9064 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 9065 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 9066 | "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9067 | return -EINVAL22; |
| 9068 | } |
| 9069 | |
| 9070 | i8xx_compute_dpll(crtc, crtc_state, NULL((void *)0)); |
| 9071 | |
| 9072 | return 0; |
| 9073 | } |
| 9074 | |
| 9075 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
| 9076 | struct intel_crtc_state *crtc_state) |
| 9077 | { |
| 9078 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 9079 | const struct intel_limit *limit; |
| 9080 | int refclk = 96000; |
| 9081 | |
| 9082 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 9083 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 9084 | |
| 9085 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 9086 | if (intel_panel_use_ssc(dev_priv)) { |
| 9087 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 9088 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9089 | "using SSC reference clock of %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9090 | refclk)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
| 9091 | } |
| 9092 | |
| 9093 | if (intel_is_dual_link_lvds(dev_priv)) |
| 9094 | limit = &intel_limits_g4x_dual_channel_lvds; |
| 9095 | else |
| 9096 | limit = &intel_limits_g4x_single_channel_lvds; |
| 9097 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
| 9098 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
| 9099 | limit = &intel_limits_g4x_hdmi; |
| 9100 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
| 9101 | limit = &intel_limits_g4x_sdvo; |
| 9102 | } else { |
| 9103 | /* The option is for other outputs */ |
| 9104 | limit = &intel_limits_i9xx_sdvo; |
| 9105 | } |
| 9106 | |
| 9107 | if (!crtc_state->clock_set && |
| 9108 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9109 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 9110 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 9111 | "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9112 | return -EINVAL22; |
| 9113 | } |
| 9114 | |
| 9115 | i9xx_compute_dpll(crtc, crtc_state, NULL((void *)0)); |
| 9116 | |
| 9117 | return 0; |
| 9118 | } |
| 9119 | |
| 9120 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
| 9121 | struct intel_crtc_state *crtc_state) |
| 9122 | { |
| 9123 | struct drm_device *dev = crtc->base.dev; |
| 9124 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 9125 | const struct intel_limit *limit; |
| 9126 | int refclk = 96000; |
| 9127 | |
| 9128 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 9129 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 9130 | |
| 9131 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 9132 | if (intel_panel_use_ssc(dev_priv)) { |
| 9133 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 9134 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9135 | "using SSC reference clock of %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9136 | refclk)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
| 9137 | } |
| 9138 | |
| 9139 | limit = &pnv_limits_lvds; |
| 9140 | } else { |
| 9141 | limit = &pnv_limits_sdvo; |
| 9142 | } |
| 9143 | |
| 9144 | if (!crtc_state->clock_set && |
| 9145 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9146 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 9147 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 9148 | "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9149 | return -EINVAL22; |
| 9150 | } |
| 9151 | |
| 9152 | i9xx_compute_dpll(crtc, crtc_state, NULL((void *)0)); |
| 9153 | |
| 9154 | return 0; |
| 9155 | } |
| 9156 | |
| 9157 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
| 9158 | struct intel_crtc_state *crtc_state) |
| 9159 | { |
| 9160 | struct drm_device *dev = crtc->base.dev; |
| 9161 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 9162 | const struct intel_limit *limit; |
| 9163 | int refclk = 96000; |
| 9164 | |
| 9165 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 9166 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 9167 | |
| 9168 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 9169 | if (intel_panel_use_ssc(dev_priv)) { |
| 9170 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 9171 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9172 | "using SSC reference clock of %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk) |
| 9173 | refclk)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , refclk); |
| 9174 | } |
| 9175 | |
| 9176 | limit = &intel_limits_i9xx_lvds; |
| 9177 | } else { |
| 9178 | limit = &intel_limits_i9xx_sdvo; |
| 9179 | } |
| 9180 | |
| 9181 | if (!crtc_state->clock_set && |
| 9182 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9183 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 9184 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 9185 | "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9186 | return -EINVAL22; |
| 9187 | } |
| 9188 | |
| 9189 | i9xx_compute_dpll(crtc, crtc_state, NULL((void *)0)); |
| 9190 | |
| 9191 | return 0; |
| 9192 | } |
| 9193 | |
| 9194 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
| 9195 | struct intel_crtc_state *crtc_state) |
| 9196 | { |
| 9197 | int refclk = 100000; |
| 9198 | const struct intel_limit *limit = &intel_limits_chv; |
| 9199 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev); |
| 9200 | |
| 9201 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 9202 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 9203 | |
| 9204 | if (!crtc_state->clock_set && |
| 9205 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9206 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 9207 | drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9208 | return -EINVAL22; |
| 9209 | } |
| 9210 | |
| 9211 | chv_compute_dpll(crtc, crtc_state); |
| 9212 | |
| 9213 | return 0; |
| 9214 | } |
| 9215 | |
| 9216 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, |
| 9217 | struct intel_crtc_state *crtc_state) |
| 9218 | { |
| 9219 | int refclk = 100000; |
| 9220 | const struct intel_limit *limit = &intel_limits_vlv; |
| 9221 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc_state->uapi.crtc->dev); |
| 9222 | |
| 9223 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 9224 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 9225 | |
| 9226 | if (!crtc_state->clock_set && |
| 9227 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 9228 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 9229 | drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9230 | return -EINVAL22; |
| 9231 | } |
| 9232 | |
| 9233 | vlv_compute_dpll(crtc, crtc_state); |
| 9234 | |
| 9235 | return 0; |
| 9236 | } |
| 9237 | |
| 9238 | static bool_Bool i9xx_has_pfit(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 9239 | { |
| 9240 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830)) |
| 9241 | return false0; |
| 9242 | |
| 9243 | return INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4 || |
| 9244 | IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW) || IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile); |
| 9245 | } |
| 9246 | |
| 9247 | static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) |
| 9248 | { |
| 9249 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 9250 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 9251 | u32 tmp; |
| 9252 | |
| 9253 | if (!i9xx_has_pfit(dev_priv)) |
| 9254 | return; |
| 9255 | |
| 9256 | tmp = intel_de_read(dev_priv, PFIT_CONTROL((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> display_mmio_offset) + 0x61230) })); |
| 9257 | if (!(tmp & PFIT_ENABLE(1 << 31))) |
| 9258 | return; |
| 9259 | |
| 9260 | /* Check whether the pfit is attached to our pipe. */ |
| 9261 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) { |
| 9262 | if (crtc->pipe != PIPE_B) |
| 9263 | return; |
| 9264 | } else { |
| 9265 | if ((tmp & PFIT_PIPE_MASK(3 << 29)) != (crtc->pipe << PFIT_PIPE_SHIFT29)) |
| 9266 | return; |
| 9267 | } |
| 9268 | |
| 9269 | crtc_state->gmch_pfit.control = tmp; |
| 9270 | crtc_state->gmch_pfit.pgm_ratios = |
| 9271 | intel_de_read(dev_priv, PFIT_PGM_RATIOS((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> display_mmio_offset) + 0x61234) })); |
| 9272 | } |
| 9273 | |
| 9274 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
| 9275 | struct intel_crtc_state *pipe_config) |
| 9276 | { |
| 9277 | struct drm_device *dev = crtc->base.dev; |
| 9278 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 9279 | enum pipe pipe = crtc->pipe; |
| 9280 | struct dpll clock; |
| 9281 | u32 mdiv; |
| 9282 | int refclk = 100000; |
| 9283 | |
| 9284 | /* In case of DSI, DPLL will not be used */ |
| 9285 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) == 0) |
| 9286 | return; |
| 9287 | |
| 9288 | vlv_dpio_get(dev_priv); |
| 9289 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)((0x800c) + (pipe) * ((0x802c) - (0x800c)))); |
| 9290 | vlv_dpio_put(dev_priv); |
| 9291 | |
| 9292 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT(8)) & 7; |
| 9293 | clock.m2 = mdiv & DPIO_M2DIV_MASK0xff; |
| 9294 | clock.n = (mdiv >> DPIO_N_SHIFT(12)) & 0xf; |
| 9295 | clock.p1 = (mdiv >> DPIO_P1_SHIFT(21)) & 7; |
| 9296 | clock.p2 = (mdiv >> DPIO_P2_SHIFT(16)) & 0x1f; |
| 9297 | |
| 9298 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
| 9299 | } |
| 9300 | |
| 9301 | static void |
| 9302 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, |
| 9303 | struct intel_initial_plane_config *plane_config) |
| 9304 | { |
| 9305 | struct drm_device *dev = crtc->base.dev; |
| 9306 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 9307 | struct intel_plane *plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 9308 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
| 9309 | enum pipe pipe; |
| 9310 | u32 val, base, offset; |
| 9311 | int fourcc, pixel_format; |
| 9312 | unsigned int aligned_height; |
| 9313 | struct drm_framebuffer *fb; |
| 9314 | struct intel_framebuffer *intel_fb; |
| 9315 | |
| 9316 | if (!plane->get_hw_state(plane, &pipe)) |
| 9317 | return; |
| 9318 | |
| 9319 | drm_WARN_ON(dev, pipe != crtc->pipe)({ int __ret = !!((pipe != crtc->pipe)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "pipe != crtc->pipe" ")"); __builtin_expect(!!(__ret), 0) ; }); |
| 9320 | |
| 9321 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL(0x0001 | 0x0004)); |
| 9322 | if (!intel_fb) { |
| 9323 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to alloc fb\n" ); |
| 9324 | return; |
| 9325 | } |
| 9326 | |
| 9327 | fb = &intel_fb->base; |
| 9328 | |
| 9329 | fb->dev = dev; |
| 9330 | |
| 9331 | val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9332 | |
| 9333 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 9334 | if (val & DISPPLANE_TILED(1 << 10)) { |
| 9335 | plane_config->tiling = I915_TILING_X1; |
| 9336 | fb->modifier = I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
| 9337 | } |
| 9338 | |
| 9339 | if (val & DISPPLANE_ROTATE_180(1 << 15)) |
| 9340 | plane_config->rotation = DRM_MODE_ROTATE_180(1<<2); |
| 9341 | } |
| 9342 | |
| 9343 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && pipe == PIPE_B && |
| 9344 | val & DISPPLANE_MIRROR(1 << 8)) |
| 9345 | plane_config->rotation |= DRM_MODE_REFLECT_X(1<<4); |
| 9346 | |
| 9347 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK(0xf << 26); |
| 9348 | fourcc = i9xx_format_to_fourcc(pixel_format); |
| 9349 | fb->format = drm_format_info(fourcc); |
| 9350 | |
| 9351 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
| 9352 | offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9353 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & 0xfffff000; |
| 9354 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 9355 | if (plane_config->tiling) |
| 9356 | offset = intel_de_read(dev_priv, |
| 9357 | DSPTILEOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9358 | else |
| 9359 | offset = intel_de_read(dev_priv, |
| 9360 | DSPLINOFF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9361 | base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & 0xfffff000; |
| 9362 | } else { |
| 9363 | base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9364 | } |
| 9365 | plane_config->base = base; |
| 9366 | |
| 9367 | val = intel_de_read(dev_priv, PIPESRC(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x6001c) + ((&(dev_priv)->__info)-> display_mmio_offset))) })); |
| 9368 | fb->width = ((val >> 16) & 0xfff) + 1; |
| 9369 | fb->height = ((val >> 0) & 0xfff) + 1; |
| 9370 | |
| 9371 | val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70188) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9372 | fb->pitches[0] = val & 0xffffffc0; |
| 9373 | |
| 9374 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
| 9375 | |
| 9376 | plane_config->size = fb->pitches[0] * aligned_height; |
| 9377 | |
| 9378 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 9379 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 9380 | crtc->base.name, plane->base.name, fb->width, fb->height,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 9381 | fb->format->cpp[0] * 8, base, fb->pitches[0],drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 9382 | plane_config->size)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size); |
| 9383 | |
| 9384 | plane_config->fb = intel_fb; |
| 9385 | } |
| 9386 | |
| 9387 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
| 9388 | struct intel_crtc_state *pipe_config) |
| 9389 | { |
| 9390 | struct drm_device *dev = crtc->base.dev; |
| 9391 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 9392 | enum pipe pipe = crtc->pipe; |
| 9393 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
| 9394 | struct dpll clock; |
| 9395 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
| 9396 | int refclk = 100000; |
| 9397 | |
| 9398 | /* In case of DSI, DPLL will not be used */ |
| 9399 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE(1 << 31)) == 0) |
| 9400 | return; |
| 9401 | |
| 9402 | vlv_dpio_get(dev_priv); |
| 9403 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)((0x8134) + (port) * ((0x8080) - (0x8134)))); |
| 9404 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)((0x8000) + (port) * ((0x8180) - (0x8000)))); |
| 9405 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)((0x8004) + (port) * ((0x8184) - (0x8004)))); |
| 9406 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)((0x8008) + (port) * ((0x8188) - (0x8008)))); |
| 9407 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)((0x800c) + (port) * ((0x818c) - (0x800c)))); |
| 9408 | vlv_dpio_put(dev_priv); |
| 9409 | |
| 9410 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2(0 << 0) ? 2 : 0; |
| 9411 | clock.m2 = (pll_dw0 & 0xff) << 22; |
| 9412 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN(1 << 16)) |
| 9413 | clock.m2 |= pll_dw2 & 0x3fffff; |
| 9414 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT8) & 0xf; |
| 9415 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT13) & 0x7; |
| 9416 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT8) & 0x1f; |
| 9417 | |
| 9418 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
| 9419 | } |
| 9420 | |
| 9421 | static enum intel_output_format |
| 9422 | bdw_get_pipemisc_output_format(struct intel_crtc *crtc) |
| 9423 | { |
| 9424 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 9425 | u32 tmp; |
| 9426 | |
| 9427 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70030) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 9428 | |
| 9429 | if (tmp & PIPEMISC_YUV420_ENABLE(1 << 27)) { |
| 9430 | /* We support 4:2:0 in full blend mode only */ |
| 9431 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!(((tmp & (1 << 26)) == 0)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "(tmp & (1 << 26)) == 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 9432 | (tmp & PIPEMISC_YUV420_MODE_FULL_BLEND) == 0)({ int __ret = !!(((tmp & (1 << 26)) == 0)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "(tmp & (1 << 26)) == 0" ")"); __builtin_expect(!!(__ret), 0); }); |
| 9433 | |
| 9434 | return INTEL_OUTPUT_FORMAT_YCBCR420; |
| 9435 | } else if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV(1 << 11)) { |
| 9436 | return INTEL_OUTPUT_FORMAT_YCBCR444; |
| 9437 | } else { |
| 9438 | return INTEL_OUTPUT_FORMAT_RGB; |
| 9439 | } |
| 9440 | } |
| 9441 | |
| 9442 | static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state) |
| 9443 | { |
| 9444 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 9445 | struct intel_plane *plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 9446 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 9447 | enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; |
| 9448 | u32 tmp; |
| 9449 | |
| 9450 | tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i9xx_plane] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 9451 | |
| 9452 | if (tmp & DISPPLANE_GAMMA_ENABLE(1 << 30)) |
| 9453 | crtc_state->gamma_enable = true1; |
| 9454 | |
| 9455 | if (!HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && |
| 9456 | tmp & DISPPLANE_PIPE_CSC_ENABLE(1 << 24)) |
| 9457 | crtc_state->csc_enable = true1; |
| 9458 | } |
| 9459 | |
| 9460 | static bool_Bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
| 9461 | struct intel_crtc_state *pipe_config) |
| 9462 | { |
| 9463 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 9464 | enum intel_display_power_domain power_domain; |
| 9465 | intel_wakeref_t wakeref; |
| 9466 | u32 tmp; |
| 9467 | bool_Bool ret; |
| 9468 | |
| 9469 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe)((crtc->pipe) + POWER_DOMAIN_PIPE_A); |
| 9470 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 9471 | if (!wakeref) |
| 9472 | return false0; |
| 9473 | |
| 9474 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 9475 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 9476 | pipe_config->shared_dpll = NULL((void *)0); |
| 9477 | |
| 9478 | ret = false0; |
| 9479 | |
| 9480 | tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 9481 | if (!(tmp & PIPECONF_ENABLE(1 << 31))) |
| 9482 | goto out; |
| 9483 | |
| 9484 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || |
| 9485 | IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 9486 | switch (tmp & PIPECONF_BPC_MASK(0x7 << 5)) { |
| 9487 | case PIPECONF_6BPC(2 << 5): |
| 9488 | pipe_config->pipe_bpp = 18; |
| 9489 | break; |
| 9490 | case PIPECONF_8BPC(0 << 5): |
| 9491 | pipe_config->pipe_bpp = 24; |
| 9492 | break; |
| 9493 | case PIPECONF_10BPC(1 << 5): |
| 9494 | pipe_config->pipe_bpp = 30; |
| 9495 | break; |
| 9496 | default: |
| 9497 | break; |
| 9498 | } |
| 9499 | } |
| 9500 | |
| 9501 | if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) && |
| 9502 | (tmp & PIPECONF_COLOR_RANGE_SELECT(1 << 13))) |
| 9503 | pipe_config->limited_color_range = true1; |
| 9504 | |
| 9505 | pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_I9XX(1 << 24)) >> |
| 9506 | PIPECONF_GAMMA_MODE_SHIFT24; |
| 9507 | |
| 9508 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 9509 | pipe_config->cgm_mode = intel_de_read(dev_priv, |
| 9510 | CGM_PIPE_MODE(crtc->pipe)((const i915_reg_t){ .reg = ((((0x180000 + 0x67A00)) + (crtc-> pipe) * (((0x180000 + 0x69A00)) - ((0x180000 + 0x67A00))))) } )); |
| 9511 | |
| 9512 | i9xx_get_pipe_color_config(pipe_config); |
| 9513 | intel_color_get_config(pipe_config); |
| 9514 | |
| 9515 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) |
| 9516 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE(1 << 30); |
| 9517 | |
| 9518 | intel_get_pipe_timings(crtc, pipe_config); |
| 9519 | intel_get_pipe_src_size(crtc, pipe_config); |
| 9520 | |
| 9521 | i9xx_get_pfit_config(pipe_config); |
| 9522 | |
| 9523 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 9524 | /* No way to read it out on pipes B and C */ |
| 9525 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && crtc->pipe != PIPE_A) |
| 9526 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
| 9527 | else |
| 9528 | tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x601c), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6020), (((&(dev_priv )->__info)->display_mmio_offset) + 0x603c) })[(crtc-> pipe)])) })); |
| 9529 | pipe_config->pixel_multiplier = |
| 9530 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK0x00003f00) |
| 9531 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT8) + 1; |
| 9532 | pipe_config->dpll_hw_state.dpll_md = tmp; |
| 9533 | } else if (IS_I945G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945G) || IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) || |
| 9534 | IS_G33(dev_priv)IS_PLATFORM(dev_priv, INTEL_G33) || IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 9535 | tmp = intel_de_read(dev_priv, DPLL(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(crtc-> pipe)])) })); |
| 9536 | pipe_config->pixel_multiplier = |
| 9537 | ((tmp & SDVO_MULTIPLIER_MASK0x000000ff) |
| 9538 | >> SDVO_MULTIPLIER_SHIFT_HIRES4) + 1; |
| 9539 | } else { |
| 9540 | /* Note that on i915G/GM the pixel multiplier is in the sdvo |
| 9541 | * port and will be fixed up in the encoder->get_config |
| 9542 | * function. */ |
| 9543 | pipe_config->pixel_multiplier = 1; |
| 9544 | } |
| 9545 | pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, |
| 9546 | DPLL(crtc->pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(crtc-> pipe)])) })); |
| 9547 | if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 9548 | pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, |
| 9549 | FP0(crtc->pipe)((const i915_reg_t){ .reg = (((0x6040) + (crtc->pipe) * (( 0x6048) - (0x6040)))) })); |
| 9550 | pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, |
| 9551 | FP1(crtc->pipe)((const i915_reg_t){ .reg = (((0x6044) + (crtc->pipe) * (( 0x604c) - (0x6044)))) })); |
| 9552 | } else { |
| 9553 | /* Mask out read-only status bits. */ |
| 9554 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV(1 << 15) | |
| 9555 | DPLL_PORTC_READY_MASK(0xf << 4) | |
| 9556 | DPLL_PORTB_READY_MASK(0xf)); |
| 9557 | } |
| 9558 | |
| 9559 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 9560 | chv_crtc_clock_get(crtc, pipe_config); |
| 9561 | else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)) |
| 9562 | vlv_crtc_clock_get(crtc, pipe_config); |
| 9563 | else |
| 9564 | i9xx_crtc_clock_get(crtc, pipe_config); |
| 9565 | |
| 9566 | /* |
| 9567 | * Normally the dotclock is filled in by the encoder .get_config() |
| 9568 | * but in case the pipe is enabled w/o any ports we need a sane |
| 9569 | * default. |
| 9570 | */ |
| 9571 | pipe_config->hw.adjusted_mode.crtc_clock = |
| 9572 | pipe_config->port_clock / pipe_config->pixel_multiplier; |
| 9573 | |
| 9574 | ret = true1; |
| 9575 | |
| 9576 | out: |
| 9577 | intel_display_power_put(dev_priv, power_domain, wakeref); |
| 9578 | |
| 9579 | return ret; |
| 9580 | } |
| 9581 | |
| 9582 | static void ilk_init_pch_refclk(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 9583 | { |
| 9584 | struct intel_encoder *encoder; |
| 9585 | int i; |
| 9586 | u32 val, final; |
| 9587 | bool_Bool has_lvds = false0; |
| 9588 | bool_Bool has_cpu_edp = false0; |
| 9589 | bool_Bool has_panel = false0; |
| 9590 | bool_Bool has_ck505 = false0; |
| 9591 | bool_Bool can_ssc = false0; |
| 9592 | bool_Bool using_ssc_source = false0; |
| 9593 | |
| 9594 | /* We need to take the global config into account */ |
| 9595 | for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) { |
| 9596 | switch (encoder->type) { |
| 9597 | case INTEL_OUTPUT_LVDS: |
| 9598 | has_panel = true1; |
| 9599 | has_lvds = true1; |
| 9600 | break; |
| 9601 | case INTEL_OUTPUT_EDP: |
| 9602 | has_panel = true1; |
| 9603 | if (encoder->port == PORT_A) |
| 9604 | has_cpu_edp = true1; |
| 9605 | break; |
| 9606 | default: |
| 9607 | break; |
| 9608 | } |
| 9609 | } |
| 9610 | |
| 9611 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) { |
| 9612 | has_ck505 = dev_priv->vbt.display_clock_mode; |
| 9613 | can_ssc = has_ck505; |
| 9614 | } else { |
| 9615 | has_ck505 = false0; |
| 9616 | can_ssc = true1; |
| 9617 | } |
| 9618 | |
| 9619 | /* Check if any DPLLs are using the SSC source */ |
| 9620 | for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) { |
| 9621 | u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)((const i915_reg_t){ .reg = ((i) == 0 ? 0xc6014 : 0xc6018) })); |
| 9622 | |
| 9623 | if (!(temp & DPLL_VCO_ENABLE(1 << 31))) |
| 9624 | continue; |
| 9625 | |
| 9626 | if ((temp & PLL_REF_INPUT_MASK(3 << 13)) == |
| 9627 | PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13)) { |
| 9628 | using_ssc_source = true1; |
| 9629 | break; |
| 9630 | } |
| 9631 | } |
| 9632 | |
| 9633 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n" , has_panel, has_lvds, has_ck505, using_ssc_source) |
| 9634 | "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n" , has_panel, has_lvds, has_ck505, using_ssc_source) |
| 9635 | has_panel, has_lvds, has_ck505, using_ssc_source)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n" , has_panel, has_lvds, has_ck505, using_ssc_source); |
| 9636 | |
| 9637 | /* Ironlake: try to setup display ref clock before DPLL |
| 9638 | * enabling. This is only under driver's control after |
| 9639 | * PCH B stepping, previous chipset stepping should be |
| 9640 | * ignoring this setting. |
| 9641 | */ |
| 9642 | val = intel_de_read(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) })); |
| 9643 | |
| 9644 | /* As we must carefully and slowly disable/enable each source in turn, |
| 9645 | * compute the final state we want first and check if we need to |
| 9646 | * make any changes at all. |
| 9647 | */ |
| 9648 | final = val; |
| 9649 | final &= ~DREF_NONSPREAD_SOURCE_MASK(3 << 9); |
| 9650 | if (has_ck505) |
| 9651 | final |= DREF_NONSPREAD_CK505_ENABLE(1 << 9); |
| 9652 | else |
| 9653 | final |= DREF_NONSPREAD_SOURCE_ENABLE(2 << 9); |
| 9654 | |
| 9655 | final &= ~DREF_SSC_SOURCE_MASK(3 << 11); |
| 9656 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK(3 << 13); |
| 9657 | final &= ~DREF_SSC1_ENABLE(1 << 1); |
| 9658 | |
| 9659 | if (has_panel) { |
| 9660 | final |= DREF_SSC_SOURCE_ENABLE(2 << 11); |
| 9661 | |
| 9662 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 9663 | final |= DREF_SSC1_ENABLE(1 << 1); |
| 9664 | |
| 9665 | if (has_cpu_edp) { |
| 9666 | if (intel_panel_use_ssc(dev_priv) && can_ssc) |
| 9667 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD(2 << 13); |
| 9668 | else |
| 9669 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD(3 << 13); |
| 9670 | } else |
| 9671 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE(0 << 13); |
| 9672 | } else if (using_ssc_source) { |
| 9673 | final |= DREF_SSC_SOURCE_ENABLE(2 << 11); |
| 9674 | final |= DREF_SSC1_ENABLE(1 << 1); |
| 9675 | } |
| 9676 | |
| 9677 | if (final == val) |
| 9678 | return; |
| 9679 | |
| 9680 | /* Always enable nonspread source */ |
| 9681 | val &= ~DREF_NONSPREAD_SOURCE_MASK(3 << 9); |
| 9682 | |
| 9683 | if (has_ck505) |
| 9684 | val |= DREF_NONSPREAD_CK505_ENABLE(1 << 9); |
| 9685 | else |
| 9686 | val |= DREF_NONSPREAD_SOURCE_ENABLE(2 << 9); |
| 9687 | |
| 9688 | if (has_panel) { |
| 9689 | val &= ~DREF_SSC_SOURCE_MASK(3 << 11); |
| 9690 | val |= DREF_SSC_SOURCE_ENABLE(2 << 11); |
| 9691 | |
| 9692 | /* SSC must be turned on before enabling the CPU output */ |
| 9693 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
| 9694 | drm_dbg_kms(&dev_priv->drm, "Using SSC on panel\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using SSC on panel\n" ); |
| 9695 | val |= DREF_SSC1_ENABLE(1 << 1); |
| 9696 | } else |
| 9697 | val &= ~DREF_SSC1_ENABLE(1 << 1); |
| 9698 | |
| 9699 | /* Get SSC going before enabling the outputs */ |
| 9700 | intel_de_write(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) }), val); |
| 9701 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) })); |
| 9702 | udelay(200); |
| 9703 | |
| 9704 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK(3 << 13); |
| 9705 | |
| 9706 | /* Enable CPU source on CPU attached eDP */ |
| 9707 | if (has_cpu_edp) { |
| 9708 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
| 9709 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using SSC on eDP\n" ) |
| 9710 | "Using SSC on eDP\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using SSC on eDP\n" ); |
| 9711 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD(2 << 13); |
| 9712 | } else |
| 9713 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD(3 << 13); |
| 9714 | } else |
| 9715 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE(0 << 13); |
| 9716 | |
| 9717 | intel_de_write(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) }), val); |
| 9718 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) })); |
| 9719 | udelay(200); |
| 9720 | } else { |
| 9721 | drm_dbg_kms(&dev_priv->drm, "Disabling CPU source output\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling CPU source output\n" ); |
| 9722 | |
| 9723 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK(3 << 13); |
| 9724 | |
| 9725 | /* Turn off CPU output */ |
| 9726 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE(0 << 13); |
| 9727 | |
| 9728 | intel_de_write(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) }), val); |
| 9729 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) })); |
| 9730 | udelay(200); |
| 9731 | |
| 9732 | if (!using_ssc_source) { |
| 9733 | drm_dbg_kms(&dev_priv->drm, "Disabling SSC source\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Disabling SSC source\n" ); |
| 9734 | |
| 9735 | /* Turn off the SSC source */ |
| 9736 | val &= ~DREF_SSC_SOURCE_MASK(3 << 11); |
| 9737 | val |= DREF_SSC_SOURCE_DISABLE(0 << 11); |
| 9738 | |
| 9739 | /* Turn off SSC1 */ |
| 9740 | val &= ~DREF_SSC1_ENABLE(1 << 1); |
| 9741 | |
| 9742 | intel_de_write(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) }), val); |
| 9743 | intel_de_posting_read(dev_priv, PCH_DREF_CONTROL((const i915_reg_t){ .reg = (0xC6200) })); |
| 9744 | udelay(200); |
| 9745 | } |
| 9746 | } |
| 9747 | |
| 9748 | BUG_ON(val != final)((!(val != final)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 9748, "!(val != final)")); |
| 9749 | } |
| 9750 | |
| 9751 | static void lpt_reset_fdi_mphy(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 9752 | { |
| 9753 | u32 tmp; |
| 9754 | |
| 9755 | tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2((const i915_reg_t){ .reg = (0xc2004) })); |
| 9756 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL(1 << 12); |
| 9757 | intel_de_write(dev_priv, SOUTH_CHICKEN2((const i915_reg_t){ .reg = (0xc2004) }), tmp); |
| 9758 | |
| 9759 | if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &({ int ret__; extern char _ctassert[(!(!__builtin_constant_p( 100))) ? 1 : -1 ] __attribute__((__unused__)); if ((100) > 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw (), 1000ll * (((100)))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if (((intel_de_read (dev_priv, ((const i915_reg_t){ .reg = (0xc2004) })) & (1 << 13)))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<= 1; } ret__; }); else ret__ = ( { int cpu, ret, timeout = ((100)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = (({struct cpu_info *__ci; asm volatile ("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_cpuid); } base = local_clock (); for (;;) { u64 now = local_clock(); if (!(0)) ; __asm volatile ("" : : : "memory"); if ((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (0xc2004) })) & (1 << 13))) { ret = 0; break ; } if (now - base >= timeout) { ret = -60; break; } cpu_relax (); if (!(0)) { ; if (__builtin_expect(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu = (({struct cpu_info *__ci; asm volatile( "movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_cpuid); base = local_clock (); } } } ret; }); ret__; }) |
| 9760 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)({ int ret__; extern char _ctassert[(!(!__builtin_constant_p( 100))) ? 1 : -1 ] __attribute__((__unused__)); if ((100) > 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw (), 1000ll * (((100)))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if (((intel_de_read (dev_priv, ((const i915_reg_t){ .reg = (0xc2004) })) & (1 << 13)))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<= 1; } ret__; }); else ret__ = ( { int cpu, ret, timeout = ((100)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = (({struct cpu_info *__ci; asm volatile ("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_cpuid); } base = local_clock (); for (;;) { u64 now = local_clock(); if (!(0)) ; __asm volatile ("" : : : "memory"); if ((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (0xc2004) })) & (1 << 13))) { ret = 0; break ; } if (now - base >= timeout) { ret = -60; break; } cpu_relax (); if (!(0)) { ; if (__builtin_expect(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu = (({struct cpu_info *__ci; asm volatile( "movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_cpuid); base = local_clock (); } } } ret; }); ret__; })) |
| 9761 | drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI mPHY reset assert timeout\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9762 | |
| 9763 | tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2((const i915_reg_t){ .reg = (0xc2004) })); |
| 9764 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL(1 << 12); |
| 9765 | intel_de_write(dev_priv, SOUTH_CHICKEN2((const i915_reg_t){ .reg = (0xc2004) }), tmp); |
| 9766 | |
| 9767 | if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &({ int ret__; extern char _ctassert[(!(!__builtin_constant_p( 100))) ? 1 : -1 ] __attribute__((__unused__)); if ((100) > 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw (), 1000ll * (((100)))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read (dev_priv, ((const i915_reg_t){ .reg = (0xc2004) })) & (1 << 13)) == 0))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if ( wait__ < ((10))) wait__ <<= 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((100)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"); if (((intel_de_read(dev_priv , ((const i915_reg_t){ .reg = (0xc2004) })) & (1 << 13)) == 0)) { ret = 0; break; } if (now - base >= timeout ) { ret = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect (!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self ))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self ))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; } ); ret__; }) |
| 9768 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)({ int ret__; extern char _ctassert[(!(!__builtin_constant_p( 100))) ? 1 : -1 ] __attribute__((__unused__)); if ((100) > 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw (), 1000ll * (((100)))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read (dev_priv, ((const i915_reg_t){ .reg = (0xc2004) })) & (1 << 13)) == 0))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if ( wait__ < ((10))) wait__ <<= 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((100)) * 1000; u64 base; do { } while (0); if (!(0)) { ; cpu = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64 now = local_clock(); if (!(0)) ; __asm volatile("" : : : "memory"); if (((intel_de_read(dev_priv , ((const i915_reg_t){ .reg = (0xc2004) })) & (1 << 13)) == 0)) { ret = 0; break; } if (now - base >= timeout ) { ret = -60; break; } cpu_relax(); if (!(0)) { ; if (__builtin_expect (!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self ))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self ))); __ci;})->ci_cpuid); base = local_clock(); } } } ret; } ); ret__; })) |
| 9769 | drm_err(&dev_priv->drm, "FDI mPHY reset de-assert timeout\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "FDI mPHY reset de-assert timeout\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 9770 | } |
| 9771 | |
| 9772 | /* WaMPhyProgramming:hsw */ |
| 9773 | static void lpt_program_fdi_mphy(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 9774 | { |
| 9775 | u32 tmp; |
| 9776 | |
| 9777 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); |
| 9778 | tmp &= ~(0xFF << 24); |
| 9779 | tmp |= (0x12 << 24); |
| 9780 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); |
| 9781 | |
| 9782 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
| 9783 | tmp |= (1 << 11); |
| 9784 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); |
| 9785 | |
| 9786 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); |
| 9787 | tmp |= (1 << 11); |
| 9788 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); |
| 9789 | |
| 9790 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
| 9791 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 9792 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); |
| 9793 | |
| 9794 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); |
| 9795 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); |
| 9796 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); |
| 9797 | |
| 9798 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
| 9799 | tmp &= ~(7 << 13); |
| 9800 | tmp |= (5 << 13); |
| 9801 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); |
| 9802 | |
| 9803 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
| 9804 | tmp &= ~(7 << 13); |
| 9805 | tmp |= (5 << 13); |
| 9806 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); |
| 9807 | |
| 9808 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); |
| 9809 | tmp &= ~0xFF; |
| 9810 | tmp |= 0x1C; |
| 9811 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); |
| 9812 | |
| 9813 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); |
| 9814 | tmp &= ~0xFF; |
| 9815 | tmp |= 0x1C; |
| 9816 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); |
| 9817 | |
| 9818 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); |
| 9819 | tmp &= ~(0xFF << 16); |
| 9820 | tmp |= (0x1C << 16); |
| 9821 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); |
| 9822 | |
| 9823 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); |
| 9824 | tmp &= ~(0xFF << 16); |
| 9825 | tmp |= (0x1C << 16); |
| 9826 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); |
| 9827 | |
| 9828 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
| 9829 | tmp |= (1 << 27); |
| 9830 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); |
| 9831 | |
| 9832 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
| 9833 | tmp |= (1 << 27); |
| 9834 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); |
| 9835 | |
| 9836 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
| 9837 | tmp &= ~(0xF << 28); |
| 9838 | tmp |= (4 << 28); |
| 9839 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); |
| 9840 | |
| 9841 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
| 9842 | tmp &= ~(0xF << 28); |
| 9843 | tmp |= (4 << 28); |
| 9844 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); |
| 9845 | } |
| 9846 | |
| 9847 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
| 9848 | * Programming" based on the parameters passed: |
| 9849 | * - Sequence to enable CLKOUT_DP |
| 9850 | * - Sequence to enable CLKOUT_DP without spread |
| 9851 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O |
| 9852 | */ |
| 9853 | static void lpt_enable_clkout_dp(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 9854 | bool_Bool with_spread, bool_Bool with_fdi) |
| 9855 | { |
| 9856 | u32 reg, tmp; |
| 9857 | |
| 9858 | if (drm_WARN(&dev_priv->drm, with_fdi && !with_spread,({ int __ret = !!(with_fdi && !with_spread); if (__ret ) printf("%s %s: " "FDI requires downspread\n", dev_driver_string ((&dev_priv->drm)->dev), ""); __builtin_expect(!!(__ret ), 0); }) |
| 9859 | "FDI requires downspread\n")({ int __ret = !!(with_fdi && !with_spread); if (__ret ) printf("%s %s: " "FDI requires downspread\n", dev_driver_string ((&dev_priv->drm)->dev), ""); __builtin_expect(!!(__ret ), 0); })) |
| 9860 | with_spread = true1; |
| 9861 | if (drm_WARN(&dev_priv->drm, HAS_PCH_LPT_LP(dev_priv) &&({ int __ret = !!((((dev_priv)->pch_id) == 0x9c00 || ((dev_priv )->pch_id) == 0x9c80) && with_fdi); if (__ret) printf ("%s %s: " "LP PCH doesn't have FDI\n", dev_driver_string((& dev_priv->drm)->dev), ""); __builtin_expect(!!(__ret), 0 ); }) |
| 9862 | with_fdi, "LP PCH doesn't have FDI\n")({ int __ret = !!((((dev_priv)->pch_id) == 0x9c00 || ((dev_priv )->pch_id) == 0x9c80) && with_fdi); if (__ret) printf ("%s %s: " "LP PCH doesn't have FDI\n", dev_driver_string((& dev_priv->drm)->dev), ""); __builtin_expect(!!(__ret), 0 ); })) |
| 9863 | with_fdi = false0; |
| 9864 | |
| 9865 | mutex_lock(&dev_priv->sb_lock)rw_enter_write(&dev_priv->sb_lock); |
| 9866 | |
| 9867 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL0x020c, SBI_ICLK); |
| 9868 | tmp &= ~SBI_SSCCTL_DISABLE(1 << 0); |
| 9869 | tmp |= SBI_SSCCTL_PATHALT(1 << 3); |
| 9870 | intel_sbi_write(dev_priv, SBI_SSCCTL0x020c, tmp, SBI_ICLK); |
| 9871 | |
| 9872 | udelay(24); |
| 9873 | |
| 9874 | if (with_spread) { |
| 9875 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL0x020c, SBI_ICLK); |
| 9876 | tmp &= ~SBI_SSCCTL_PATHALT(1 << 3); |
| 9877 | intel_sbi_write(dev_priv, SBI_SSCCTL0x020c, tmp, SBI_ICLK); |
| 9878 | |
| 9879 | if (with_fdi) { |
| 9880 | lpt_reset_fdi_mphy(dev_priv); |
| 9881 | lpt_program_fdi_mphy(dev_priv); |
| 9882 | } |
| 9883 | } |
| 9884 | |
| 9885 | reg = HAS_PCH_LPT_LP(dev_priv)(((dev_priv)->pch_id) == 0x9c00 || ((dev_priv)->pch_id) == 0x9c80) ? SBI_GEN00x1f00 : SBI_DBUFF00x2a00; |
| 9886 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 9887 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE(1 << 0); |
| 9888 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 9889 | |
| 9890 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 9891 | } |
| 9892 | |
| 9893 | /* Sequence to disable CLKOUT_DP */ |
| 9894 | void lpt_disable_clkout_dp(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 9895 | { |
| 9896 | u32 reg, tmp; |
| 9897 | |
| 9898 | mutex_lock(&dev_priv->sb_lock)rw_enter_write(&dev_priv->sb_lock); |
| 9899 | |
| 9900 | reg = HAS_PCH_LPT_LP(dev_priv)(((dev_priv)->pch_id) == 0x9c00 || ((dev_priv)->pch_id) == 0x9c80) ? SBI_GEN00x1f00 : SBI_DBUFF00x2a00; |
| 9901 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
| 9902 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE(1 << 0); |
| 9903 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); |
| 9904 | |
| 9905 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL0x020c, SBI_ICLK); |
| 9906 | if (!(tmp & SBI_SSCCTL_DISABLE(1 << 0))) { |
| 9907 | if (!(tmp & SBI_SSCCTL_PATHALT(1 << 3))) { |
| 9908 | tmp |= SBI_SSCCTL_PATHALT(1 << 3); |
| 9909 | intel_sbi_write(dev_priv, SBI_SSCCTL0x020c, tmp, SBI_ICLK); |
| 9910 | udelay(32); |
| 9911 | } |
| 9912 | tmp |= SBI_SSCCTL_DISABLE(1 << 0); |
| 9913 | intel_sbi_write(dev_priv, SBI_SSCCTL0x020c, tmp, SBI_ICLK); |
| 9914 | } |
| 9915 | |
| 9916 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 9917 | } |
| 9918 | |
| 9919 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
| 9920 | |
| 9921 | static const u16 sscdivintphase[] = { |
| 9922 | [BEND_IDX( 50)] = 0x3B23, |
| 9923 | [BEND_IDX( 45)] = 0x3B23, |
| 9924 | [BEND_IDX( 40)] = 0x3C23, |
| 9925 | [BEND_IDX( 35)] = 0x3C23, |
| 9926 | [BEND_IDX( 30)] = 0x3D23, |
| 9927 | [BEND_IDX( 25)] = 0x3D23, |
| 9928 | [BEND_IDX( 20)] = 0x3E23, |
| 9929 | [BEND_IDX( 15)] = 0x3E23, |
| 9930 | [BEND_IDX( 10)] = 0x3F23, |
| 9931 | [BEND_IDX( 5)] = 0x3F23, |
| 9932 | [BEND_IDX( 0)] = 0x0025, |
| 9933 | [BEND_IDX( -5)] = 0x0025, |
| 9934 | [BEND_IDX(-10)] = 0x0125, |
| 9935 | [BEND_IDX(-15)] = 0x0125, |
| 9936 | [BEND_IDX(-20)] = 0x0225, |
| 9937 | [BEND_IDX(-25)] = 0x0225, |
| 9938 | [BEND_IDX(-30)] = 0x0325, |
| 9939 | [BEND_IDX(-35)] = 0x0325, |
| 9940 | [BEND_IDX(-40)] = 0x0425, |
| 9941 | [BEND_IDX(-45)] = 0x0425, |
| 9942 | [BEND_IDX(-50)] = 0x0525, |
| 9943 | }; |
| 9944 | |
| 9945 | /* |
| 9946 | * Bend CLKOUT_DP |
| 9947 | * steps -50 to 50 inclusive, in steps of 5 |
| 9948 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) |
| 9949 | * change in clock period = -(steps / 10) * 5.787 ps |
| 9950 | */ |
| 9951 | static void lpt_bend_clkout_dp(struct drm_i915_privateinteldrm_softc *dev_priv, int steps) |
| 9952 | { |
| 9953 | u32 tmp; |
| 9954 | int idx = BEND_IDX(steps); |
| 9955 | |
| 9956 | if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0)({ int __ret = !!((steps % 5 != 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "steps % 5 != 0" ")"); __builtin_expect(!!(__ret ), 0); })) |
| 9957 | return; |
| 9958 | |
| 9959 | if (drm_WARN_ON(&dev_priv->drm, idx >= ARRAY_SIZE(sscdivintphase))({ int __ret = !!((idx >= (sizeof((sscdivintphase)) / sizeof ((sscdivintphase)[0])))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "idx >= (sizeof((sscdivintphase)) / sizeof((sscdivintphase)[0]))" ")"); __builtin_expect(!!(__ret), 0); })) |
| 9960 | return; |
| 9961 | |
| 9962 | mutex_lock(&dev_priv->sb_lock)rw_enter_write(&dev_priv->sb_lock); |
| 9963 | |
| 9964 | if (steps % 10 != 0) |
| 9965 | tmp = 0xAAAAAAAB; |
| 9966 | else |
| 9967 | tmp = 0x00000000; |
| 9968 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE0x0204, tmp, SBI_ICLK); |
| 9969 | |
| 9970 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE0x0200, SBI_ICLK); |
| 9971 | tmp &= 0xffff0000; |
| 9972 | tmp |= sscdivintphase[idx]; |
| 9973 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE0x0200, tmp, SBI_ICLK); |
| 9974 | |
| 9975 | mutex_unlock(&dev_priv->sb_lock)rw_exit_write(&dev_priv->sb_lock); |
| 9976 | } |
| 9977 | |
| 9978 | #undef BEND_IDX |
| 9979 | |
| 9980 | static bool_Bool spll_uses_pch_ssc(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 9981 | { |
| 9982 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP((const i915_reg_t){ .reg = (0x42014) })); |
| 9983 | u32 ctl = intel_de_read(dev_priv, SPLL_CTL((const i915_reg_t){ .reg = (0x46020) })); |
| 9984 | |
| 9985 | if ((ctl & SPLL_PLL_ENABLE(1 << 31)) == 0) |
| 9986 | return false0; |
| 9987 | |
| 9988 | if ((ctl & SPLL_REF_MASK(3 << 28)) == SPLL_REF_MUXED_SSC(1 << 28) && |
| 9989 | (fuse_strap & HSW_CPU_SSC_ENABLE(1 << 21)) == 0) |
| 9990 | return true1; |
| 9991 | |
| 9992 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) && |
| 9993 | (ctl & SPLL_REF_MASK(3 << 28)) == SPLL_REF_PCH_SSC_BDW(2 << 28)) |
| 9994 | return true1; |
| 9995 | |
| 9996 | return false0; |
| 9997 | } |
| 9998 | |
| 9999 | static bool_Bool wrpll_uses_pch_ssc(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 10000 | enum intel_dpll_id id) |
| 10001 | { |
| 10002 | u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP((const i915_reg_t){ .reg = (0x42014) })); |
| 10003 | u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)((const i915_reg_t){ .reg = (((0x46040) + (id) * ((0x46060) - (0x46040)))) })); |
| 10004 | |
| 10005 | if ((ctl & WRPLL_PLL_ENABLE(1 << 31)) == 0) |
| 10006 | return false0; |
| 10007 | |
| 10008 | if ((ctl & WRPLL_REF_MASK(3 << 28)) == WRPLL_REF_PCH_SSC(1 << 28)) |
| 10009 | return true1; |
| 10010 | |
| 10011 | if ((IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HSW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0))) && |
| 10012 | (ctl & WRPLL_REF_MASK(3 << 28)) == WRPLL_REF_MUXED_SSC_BDW(2 << 28) && |
| 10013 | (fuse_strap & HSW_CPU_SSC_ENABLE(1 << 21)) == 0) |
| 10014 | return true1; |
| 10015 | |
| 10016 | return false0; |
| 10017 | } |
| 10018 | |
| 10019 | static void lpt_init_pch_refclk(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 10020 | { |
| 10021 | struct intel_encoder *encoder; |
| 10022 | bool_Bool has_fdi = false0; |
| 10023 | |
| 10024 | for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) { |
| 10025 | switch (encoder->type) { |
| 10026 | case INTEL_OUTPUT_ANALOG: |
| 10027 | has_fdi = true1; |
| 10028 | break; |
| 10029 | default: |
| 10030 | break; |
| 10031 | } |
| 10032 | } |
| 10033 | |
| 10034 | /* |
| 10035 | * The BIOS may have decided to use the PCH SSC |
| 10036 | * reference so we must not disable it until the |
| 10037 | * relevant PLLs have stopped relying on it. We'll |
| 10038 | * just leave the PCH SSC reference enabled in case |
| 10039 | * any active PLL is using it. It will get disabled |
| 10040 | * after runtime suspend if we don't have FDI. |
| 10041 | * |
| 10042 | * TODO: Move the whole reference clock handling |
| 10043 | * to the modeset sequence proper so that we can |
| 10044 | * actually enable/disable/reconfigure these things |
| 10045 | * safely. To do that we need to introduce a real |
| 10046 | * clock hierarchy. That would also allow us to do |
| 10047 | * clock bending finally. |
| 10048 | */ |
| 10049 | dev_priv->pch_ssc_use = 0; |
| 10050 | |
| 10051 | if (spll_uses_pch_ssc(dev_priv)) { |
| 10052 | drm_dbg_kms(&dev_priv->drm, "SPLL using PCH SSC\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "SPLL using PCH SSC\n" ); |
| 10053 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL)(1UL << (DPLL_ID_SPLL)); |
| 10054 | } |
| 10055 | |
| 10056 | if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { |
| 10057 | drm_dbg_kms(&dev_priv->drm, "WRPLL1 using PCH SSC\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "WRPLL1 using PCH SSC\n" ); |
| 10058 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1)(1UL << (DPLL_ID_WRPLL1)); |
| 10059 | } |
| 10060 | |
| 10061 | if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { |
| 10062 | drm_dbg_kms(&dev_priv->drm, "WRPLL2 using PCH SSC\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "WRPLL2 using PCH SSC\n" ); |
| 10063 | dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2)(1UL << (DPLL_ID_WRPLL2)); |
| 10064 | } |
| 10065 | |
| 10066 | if (dev_priv->pch_ssc_use) |
| 10067 | return; |
| 10068 | |
| 10069 | if (has_fdi) { |
| 10070 | lpt_bend_clkout_dp(dev_priv, 0); |
| 10071 | lpt_enable_clkout_dp(dev_priv, true1, true1); |
| 10072 | } else { |
| 10073 | lpt_disable_clkout_dp(dev_priv); |
| 10074 | } |
| 10075 | } |
| 10076 | |
| 10077 | /* |
| 10078 | * Initialize reference clocks when the driver loads |
| 10079 | */ |
| 10080 | void intel_init_pch_refclk(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 10081 | { |
| 10082 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) || HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) |
| 10083 | ilk_init_pch_refclk(dev_priv); |
| 10084 | else if (HAS_PCH_LPT(dev_priv)(((dev_priv)->pch_type) == PCH_LPT)) |
| 10085 | lpt_init_pch_refclk(dev_priv); |
| 10086 | } |
| 10087 | |
| 10088 | static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) |
| 10089 | { |
| 10090 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 10091 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10092 | enum pipe pipe = crtc->pipe; |
| 10093 | u32 val; |
| 10094 | |
| 10095 | val = 0; |
| 10096 | |
| 10097 | switch (crtc_state->pipe_bpp) { |
| 10098 | case 18: |
| 10099 | val |= PIPECONF_6BPC(2 << 5); |
| 10100 | break; |
| 10101 | case 24: |
| 10102 | val |= PIPECONF_8BPC(0 << 5); |
| 10103 | break; |
| 10104 | case 30: |
| 10105 | val |= PIPECONF_10BPC(1 << 5); |
| 10106 | break; |
| 10107 | case 36: |
| 10108 | val |= PIPECONF_12BPC(3 << 5); |
| 10109 | break; |
| 10110 | default: |
| 10111 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
| 10112 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 10112); } while (0); |
| 10113 | } |
| 10114 | |
| 10115 | if (crtc_state->dither) |
| 10116 | val |= (PIPECONF_DITHER_EN(1 << 4) | PIPECONF_DITHER_TYPE_SP(0 << 2)); |
| 10117 | |
| 10118 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 10119 | val |= PIPECONF_INTERLACED_ILK(3 << 21); |
| 10120 | else |
| 10121 | val |= PIPECONF_PROGRESSIVE(0 << 21); |
| 10122 | |
| 10123 | /* |
| 10124 | * This would end up with an odd purple hue over |
| 10125 | * the entire display. Make sure we don't do it. |
| 10126 | */ |
| 10127 | drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&({ int __ret = !!((crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB" ")"); __builtin_expect(!!(__ret), 0); }) |
| 10128 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)({ int __ret = !!((crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB" ")"); __builtin_expect(!!(__ret), 0); }); |
| 10129 | |
| 10130 | if (crtc_state->limited_color_range && |
| 10131 | !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) |
| 10132 | val |= PIPECONF_COLOR_RANGE_SELECT(1 << 13); |
| 10133 | |
| 10134 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) |
| 10135 | val |= PIPECONF_OUTPUT_COLORSPACE_YUV709(2 << 11); |
| 10136 | |
| 10137 | val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode)((crtc_state->gamma_mode) << 24); |
| 10138 | |
| 10139 | val |= PIPECONF_FRAME_START_DELAY(0)((0) << 27); |
| 10140 | |
| 10141 | intel_de_write(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) }), val); |
| 10142 | intel_de_posting_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 10143 | } |
| 10144 | |
| 10145 | static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state) |
| 10146 | { |
| 10147 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 10148 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10149 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
| 10150 | u32 val = 0; |
| 10151 | |
| 10152 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && crtc_state->dither) |
| 10153 | val |= (PIPECONF_DITHER_EN(1 << 4) | PIPECONF_DITHER_TYPE_SP(0 << 2)); |
| 10154 | |
| 10155 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 10156 | val |= PIPECONF_INTERLACED_ILK(3 << 21); |
| 10157 | else |
| 10158 | val |= PIPECONF_PROGRESSIVE(0 << 21); |
| 10159 | |
| 10160 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && |
| 10161 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) |
| 10162 | val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW(1 << 11); |
| 10163 | |
| 10164 | intel_de_write(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) }), val); |
| 10165 | intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 10166 | } |
| 10167 | |
| 10168 | static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) |
| 10169 | { |
| 10170 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 10171 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10172 | u32 val = 0; |
| 10173 | |
| 10174 | switch (crtc_state->pipe_bpp) { |
| 10175 | case 18: |
| 10176 | val |= PIPEMISC_DITHER_6_BPC(2 << 5); |
| 10177 | break; |
| 10178 | case 24: |
| 10179 | val |= PIPEMISC_DITHER_8_BPC(0 << 5); |
| 10180 | break; |
| 10181 | case 30: |
| 10182 | val |= PIPEMISC_DITHER_10_BPC(1 << 5); |
| 10183 | break; |
| 10184 | case 36: |
| 10185 | val |= PIPEMISC_DITHER_12_BPC(3 << 5); |
| 10186 | break; |
| 10187 | default: |
| 10188 | MISSING_CASE(crtc_state->pipe_bpp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "crtc_state->pipe_bpp", (long)(crtc_state->pipe_bpp)) ; __builtin_expect(!!(__ret), 0); }); |
| 10189 | break; |
| 10190 | } |
| 10191 | |
| 10192 | if (crtc_state->dither) |
| 10193 | val |= PIPEMISC_DITHER_ENABLE(1 << 4) | PIPEMISC_DITHER_TYPE_SP(0 << 2); |
| 10194 | |
| 10195 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || |
| 10196 | crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
| 10197 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV(1 << 11); |
| 10198 | |
| 10199 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
| 10200 | val |= PIPEMISC_YUV420_ENABLE(1 << 27) | |
| 10201 | PIPEMISC_YUV420_MODE_FULL_BLEND(1 << 26); |
| 10202 | |
| 10203 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11 && |
| 10204 | (crtc_state->active_planes & ~(icl_hdr_plane_mask() | |
| 10205 | BIT(PLANE_CURSOR)(1UL << (PLANE_CURSOR)))) == 0) |
| 10206 | val |= PIPEMISC_HDR_MODE_PRECISION(1 << 23); |
| 10207 | |
| 10208 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 10209 | val |= PIPEMISC_PIXEL_ROUNDING_TRUNC((u32)((1UL << (8)) + 0)); |
| 10210 | |
| 10211 | intel_de_write(dev_priv, PIPEMISC(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70030) + ((&(dev_priv)->__info )->display_mmio_offset)) }), val); |
| 10212 | } |
| 10213 | |
| 10214 | int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) |
| 10215 | { |
| 10216 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10217 | u32 tmp; |
| 10218 | |
| 10219 | tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70030) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 10220 | |
| 10221 | switch (tmp & PIPEMISC_DITHER_BPC_MASK(7 << 5)) { |
| 10222 | case PIPEMISC_DITHER_6_BPC(2 << 5): |
| 10223 | return 18; |
| 10224 | case PIPEMISC_DITHER_8_BPC(0 << 5): |
| 10225 | return 24; |
| 10226 | case PIPEMISC_DITHER_10_BPC(1 << 5): |
| 10227 | return 30; |
| 10228 | case PIPEMISC_DITHER_12_BPC(3 << 5): |
| 10229 | return 36; |
| 10230 | default: |
| 10231 | MISSING_CASE(tmp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "tmp", (long)(tmp)); __builtin_expect(!!(__ret), 0); }); |
| 10232 | return 0; |
| 10233 | } |
| 10234 | } |
| 10235 | |
| 10236 | int ilk_get_lanes_required(int target_clock, int link_bw, int bpp) |
| 10237 | { |
| 10238 | /* |
| 10239 | * Account for spread spectrum to avoid |
| 10240 | * oversubscribing the link. Max center spread |
| 10241 | * is 2.5%; use 5% for safety's sake. |
| 10242 | */ |
| 10243 | u32 bps = target_clock * bpp * 21 / 20; |
| 10244 | return DIV_ROUND_UP(bps, link_bw * 8)(((bps) + ((link_bw * 8) - 1)) / (link_bw * 8)); |
| 10245 | } |
| 10246 | |
| 10247 | static bool_Bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) |
| 10248 | { |
| 10249 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
| 10250 | } |
| 10251 | |
| 10252 | static void ilk_compute_dpll(struct intel_crtc *crtc, |
| 10253 | struct intel_crtc_state *crtc_state, |
| 10254 | struct dpll *reduced_clock) |
| 10255 | { |
| 10256 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10257 | u32 dpll, fp, fp2; |
| 10258 | int factor; |
| 10259 | |
| 10260 | /* Enable autotuning of the PLL clock (if permissible) */ |
| 10261 | factor = 21; |
| 10262 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 10263 | if ((intel_panel_use_ssc(dev_priv) && |
| 10264 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
| 10265 | (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) && |
| 10266 | intel_is_dual_link_lvds(dev_priv))) |
| 10267 | factor = 25; |
| 10268 | } else if (crtc_state->sdvo_tv_clock) { |
| 10269 | factor = 20; |
| 10270 | } |
| 10271 | |
| 10272 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
| 10273 | |
| 10274 | if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
| 10275 | fp |= FP_CB_TUNE(0x3 << 22); |
| 10276 | |
| 10277 | if (reduced_clock) { |
| 10278 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
| 10279 | |
| 10280 | if (reduced_clock->m < factor * reduced_clock->n) |
| 10281 | fp2 |= FP_CB_TUNE(0x3 << 22); |
| 10282 | } else { |
| 10283 | fp2 = fp; |
| 10284 | } |
| 10285 | |
| 10286 | dpll = 0; |
| 10287 | |
| 10288 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
| 10289 | dpll |= DPLLB_MODE_LVDS(2 << 26); |
| 10290 | else |
| 10291 | dpll |= DPLLB_MODE_DAC_SERIAL(1 << 26); |
| 10292 | |
| 10293 | dpll |= (crtc_state->pixel_multiplier - 1) |
| 10294 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT9; |
| 10295 | |
| 10296 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
| 10297 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
| 10298 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
| 10299 | |
| 10300 | if (intel_crtc_has_dp_encoder(crtc_state)) |
| 10301 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
| 10302 | |
| 10303 | /* |
| 10304 | * The high speed IO clock is only really required for |
| 10305 | * SDVO/HDMI/DP, but we also enable it for CRT to make it |
| 10306 | * possible to share the DPLL between CRT and HDMI. Enabling |
| 10307 | * the clock needlessly does no real harm, except use up a |
| 10308 | * bit of power potentially. |
| 10309 | * |
| 10310 | * We'll limit this to IVB with 3 pipes, since it has only two |
| 10311 | * DPLLs and so DPLL sharing is the only way to get three pipes |
| 10312 | * driving PCH ports at the same time. On SNB we could do this, |
| 10313 | * and potentially avoid enabling the second DPLL, but it's not |
| 10314 | * clear if it''s a win or loss power wise. No point in doing |
| 10315 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. |
| 10316 | */ |
| 10317 | if (INTEL_NUM_PIPES(dev_priv)(hweight8((&(dev_priv)->__info)->pipe_mask)) == 3 && |
| 10318 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) |
| 10319 | dpll |= DPLL_SDVO_HIGH_SPEED(1 << 30); |
| 10320 | |
| 10321 | /* compute bitmask from p1 value */ |
| 10322 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT16; |
| 10323 | /* also FPA1 */ |
| 10324 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT0; |
| 10325 | |
| 10326 | switch (crtc_state->dpll.p2) { |
| 10327 | case 5: |
| 10328 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5(1 << 24); |
| 10329 | break; |
| 10330 | case 7: |
| 10331 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7(1 << 24); |
| 10332 | break; |
| 10333 | case 10: |
| 10334 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10(0 << 24); |
| 10335 | break; |
| 10336 | case 14: |
| 10337 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14(0 << 24); |
| 10338 | break; |
| 10339 | } |
| 10340 | |
| 10341 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
| 10342 | intel_panel_use_ssc(dev_priv)) |
| 10343 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13); |
| 10344 | else |
| 10345 | dpll |= PLL_REF_INPUT_DREFCLK(0 << 13); |
| 10346 | |
| 10347 | dpll |= DPLL_VCO_ENABLE(1 << 31); |
| 10348 | |
| 10349 | crtc_state->dpll_hw_state.dpll = dpll; |
| 10350 | crtc_state->dpll_hw_state.fp0 = fp; |
| 10351 | crtc_state->dpll_hw_state.fp1 = fp2; |
| 10352 | } |
| 10353 | |
| 10354 | static int ilk_crtc_compute_clock(struct intel_crtc *crtc, |
| 10355 | struct intel_crtc_state *crtc_state) |
| 10356 | { |
| 10357 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10358 | struct intel_atomic_state *state = |
| 10359 | to_intel_atomic_state(crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 10360 | const struct intel_limit *limit; |
| 10361 | int refclk = 120000; |
| 10362 | |
| 10363 | memset(&crtc_state->dpll_hw_state, 0,__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))) |
| 10364 | sizeof(crtc_state->dpll_hw_state))__builtin_memset((&crtc_state->dpll_hw_state), (0), (sizeof (crtc_state->dpll_hw_state))); |
| 10365 | |
| 10366 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
| 10367 | if (!crtc_state->has_pch_encoder) |
| 10368 | return 0; |
| 10369 | |
| 10370 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
| 10371 | if (intel_panel_use_ssc(dev_priv)) { |
| 10372 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , dev_priv->vbt.lvds_ssc_freq) |
| 10373 | "using SSC reference clock of %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , dev_priv->vbt.lvds_ssc_freq) |
| 10374 | dev_priv->vbt.lvds_ssc_freq)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "using SSC reference clock of %d kHz\n" , dev_priv->vbt.lvds_ssc_freq); |
| 10375 | refclk = dev_priv->vbt.lvds_ssc_freq; |
| 10376 | } |
| 10377 | |
| 10378 | if (intel_is_dual_link_lvds(dev_priv)) { |
| 10379 | if (refclk == 100000) |
| 10380 | limit = &ilk_limits_dual_lvds_100m; |
| 10381 | else |
| 10382 | limit = &ilk_limits_dual_lvds; |
| 10383 | } else { |
| 10384 | if (refclk == 100000) |
| 10385 | limit = &ilk_limits_single_lvds_100m; |
| 10386 | else |
| 10387 | limit = &ilk_limits_single_lvds; |
| 10388 | } |
| 10389 | } else { |
| 10390 | limit = &ilk_limits_dac; |
| 10391 | } |
| 10392 | |
| 10393 | if (!crtc_state->clock_set && |
| 10394 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
| 10395 | refclk, NULL((void *)0), &crtc_state->dpll)) { |
| 10396 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 10397 | "Couldn't find PLL settings for mode!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Couldn't find PLL settings for mode!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 10398 | return -EINVAL22; |
| 10399 | } |
| 10400 | |
| 10401 | ilk_compute_dpll(crtc, crtc_state, NULL((void *)0)); |
| 10402 | |
| 10403 | if (!intel_reserve_shared_dplls(state, crtc, NULL((void *)0))) { |
| 10404 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to find PLL for pipe %c\n" , ((crtc->pipe) + 'A')) |
| 10405 | "failed to find PLL for pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to find PLL for pipe %c\n" , ((crtc->pipe) + 'A')) |
| 10406 | pipe_name(crtc->pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to find PLL for pipe %c\n" , ((crtc->pipe) + 'A')); |
| 10407 | return -EINVAL22; |
| 10408 | } |
| 10409 | |
| 10410 | return 0; |
| 10411 | } |
| 10412 | |
| 10413 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
| 10414 | struct intel_link_m_n *m_n) |
| 10415 | { |
| 10416 | struct drm_device *dev = crtc->base.dev; |
| 10417 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 10418 | enum pipe pipe = crtc->pipe; |
| 10419 | |
| 10420 | m_n->link_m = intel_de_read(dev_priv, PCH_TRANS_LINK_M1(pipe)((const i915_reg_t){ .reg = (((0xe0040) + (pipe) * ((0xe1040) - (0xe0040)))) })); |
| 10421 | m_n->link_n = intel_de_read(dev_priv, PCH_TRANS_LINK_N1(pipe)((const i915_reg_t){ .reg = (((0xe0044) + (pipe) * ((0xe1044) - (0xe0044)))) })); |
| 10422 | m_n->gmch_m = intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)((const i915_reg_t){ .reg = (((0xe0030) + (pipe) * ((0xe1030) - (0xe0030)))) })) |
| 10423 | & ~TU_SIZE_MASK(0x3f << 25); |
| 10424 | m_n->gmch_n = intel_de_read(dev_priv, PCH_TRANS_DATA_N1(pipe)((const i915_reg_t){ .reg = (((0xe0034) + (pipe) * ((0xe1034) - (0xe0034)))) })); |
| 10425 | m_n->tu = ((intel_de_read(dev_priv, PCH_TRANS_DATA_M1(pipe)((const i915_reg_t){ .reg = (((0xe0030) + (pipe) * ((0xe1030) - (0xe0030)))) })) |
| 10426 | & TU_SIZE_MASK(0x3f << 25)) >> TU_SIZE_SHIFT25) + 1; |
| 10427 | } |
| 10428 | |
| 10429 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, |
| 10430 | enum transcoder transcoder, |
| 10431 | struct intel_link_m_n *m_n, |
| 10432 | struct intel_link_m_n *m2_n2) |
| 10433 | { |
| 10434 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10435 | enum pipe pipe = crtc->pipe; |
| 10436 | |
| 10437 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) { |
| 10438 | m_n->link_m = intel_de_read(dev_priv, |
| 10439 | PIPE_LINK_M1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60040) + ((&(dev_priv)-> __info)->display_mmio_offset))) })); |
| 10440 | m_n->link_n = intel_de_read(dev_priv, |
| 10441 | PIPE_LINK_N1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60044) + ((&(dev_priv)-> __info)->display_mmio_offset))) })); |
| 10442 | m_n->gmch_m = intel_de_read(dev_priv, |
| 10443 | PIPE_DATA_M1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60030) + ((&(dev_priv)-> __info)->display_mmio_offset))) })) |
| 10444 | & ~TU_SIZE_MASK(0x3f << 25); |
| 10445 | m_n->gmch_n = intel_de_read(dev_priv, |
| 10446 | PIPE_DATA_N1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60034) + ((&(dev_priv)-> __info)->display_mmio_offset))) })); |
| 10447 | m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M1(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60030) + ((&(dev_priv)-> __info)->display_mmio_offset))) })) |
| 10448 | & TU_SIZE_MASK(0x3f << 25)) >> TU_SIZE_SHIFT25) + 1; |
| 10449 | |
| 10450 | if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) { |
| 10451 | m2_n2->link_m = intel_de_read(dev_priv, |
| 10452 | PIPE_LINK_M2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60048) + ((&(dev_priv)-> __info)->display_mmio_offset))) })); |
| 10453 | m2_n2->link_n = intel_de_read(dev_priv, |
| 10454 | PIPE_LINK_N2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x6004c) + ((&(dev_priv)-> __info)->display_mmio_offset))) })); |
| 10455 | m2_n2->gmch_m = intel_de_read(dev_priv, |
| 10456 | PIPE_DATA_M2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60038) + ((&(dev_priv)-> __info)->display_mmio_offset))) })) |
| 10457 | & ~TU_SIZE_MASK(0x3f << 25); |
| 10458 | m2_n2->gmch_n = intel_de_read(dev_priv, |
| 10459 | PIPE_DATA_N2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x6003c) + ((&(dev_priv)-> __info)->display_mmio_offset))) })); |
| 10460 | m2_n2->tu = ((intel_de_read(dev_priv, PIPE_DATA_M2(transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(transcoder)] - (&(dev_priv)->__info)-> trans_offsets[TRANSCODER_A] + (0x60038) + ((&(dev_priv)-> __info)->display_mmio_offset))) })) |
| 10461 | & TU_SIZE_MASK(0x3f << 25)) >> TU_SIZE_SHIFT25) + 1; |
| 10462 | } |
| 10463 | } else { |
| 10464 | m_n->link_m = intel_de_read(dev_priv, PIPE_LINK_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70060) + (pipe) * ((0x71060) - (0x70060)))) })); |
| 10465 | m_n->link_n = intel_de_read(dev_priv, PIPE_LINK_N_G4X(pipe)((const i915_reg_t){ .reg = (((0x70064) + (pipe) * ((0x71064) - (0x70064)))) })); |
| 10466 | m_n->gmch_m = intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70050) + (pipe) * ((0x71050) - (0x70050)))) })) |
| 10467 | & ~TU_SIZE_MASK(0x3f << 25); |
| 10468 | m_n->gmch_n = intel_de_read(dev_priv, PIPE_DATA_N_G4X(pipe)((const i915_reg_t){ .reg = (((0x70054) + (pipe) * ((0x71054) - (0x70054)))) })); |
| 10469 | m_n->tu = ((intel_de_read(dev_priv, PIPE_DATA_M_G4X(pipe)((const i915_reg_t){ .reg = (((0x70050) + (pipe) * ((0x71050) - (0x70050)))) })) |
| 10470 | & TU_SIZE_MASK(0x3f << 25)) >> TU_SIZE_SHIFT25) + 1; |
| 10471 | } |
| 10472 | } |
| 10473 | |
| 10474 | void intel_dp_get_m_n(struct intel_crtc *crtc, |
| 10475 | struct intel_crtc_state *pipe_config) |
| 10476 | { |
| 10477 | if (pipe_config->has_pch_encoder) |
| 10478 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
| 10479 | else |
| 10480 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
| 10481 | &pipe_config->dp_m_n, |
| 10482 | &pipe_config->dp_m2_n2); |
| 10483 | } |
| 10484 | |
| 10485 | static void ilk_get_fdi_m_n_config(struct intel_crtc *crtc, |
| 10486 | struct intel_crtc_state *pipe_config) |
| 10487 | { |
| 10488 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, |
| 10489 | &pipe_config->fdi_m_n, NULL((void *)0)); |
| 10490 | } |
| 10491 | |
| 10492 | static void ilk_get_pfit_pos_size(struct intel_crtc_state *crtc_state, |
| 10493 | u32 pos, u32 size) |
| 10494 | { |
| 10495 | drm_rect_init(&crtc_state->pch_pfit.dst, |
| 10496 | pos >> 16, pos & 0xffff, |
| 10497 | size >> 16, size & 0xffff); |
| 10498 | } |
| 10499 | |
| 10500 | static void skl_get_pfit_config(struct intel_crtc_state *crtc_state) |
| 10501 | { |
| 10502 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 10503 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10504 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; |
| 10505 | int id = -1; |
| 10506 | int i; |
| 10507 | |
| 10508 | /* find scaler attached to this pipe */ |
| 10509 | for (i = 0; i < crtc->num_scalers; i++) { |
| 10510 | u32 ctl, pos, size; |
| 10511 | |
| 10512 | ctl = intel_de_read(dev_priv, SKL_PS_CTRL(crtc->pipe, i)((const i915_reg_t){ .reg = (((((0x68180) + (i) * ((0x68280) - (0x68180)))) + (crtc->pipe) * ((((0x68980) + (i) * ((0x68A80 ) - (0x68980)))) - (((0x68180) + (i) * ((0x68280) - (0x68180) )))))) })); |
| 10513 | if ((ctl & (PS_SCALER_EN(1 << 31) | PS_PLANE_SEL_MASK(7 << 25))) != PS_SCALER_EN(1 << 31)) |
| 10514 | continue; |
| 10515 | |
| 10516 | id = i; |
| 10517 | crtc_state->pch_pfit.enabled = true1; |
| 10518 | |
| 10519 | pos = intel_de_read(dev_priv, SKL_PS_WIN_POS(crtc->pipe, i)((const i915_reg_t){ .reg = (((((0x68170) + (i) * ((0x68270) - (0x68170)))) + (crtc->pipe) * ((((0x68970) + (i) * ((0x68A70 ) - (0x68970)))) - (((0x68170) + (i) * ((0x68270) - (0x68170) )))))) })); |
| 10520 | size = intel_de_read(dev_priv, SKL_PS_WIN_SZ(crtc->pipe, i)((const i915_reg_t){ .reg = (((((0x68174) + (i) * ((0x68274) - (0x68174)))) + (crtc->pipe) * ((((0x68974) + (i) * ((0x68A74 ) - (0x68974)))) - (((0x68174) + (i) * ((0x68274) - (0x68174) )))))) })); |
| 10521 | |
| 10522 | ilk_get_pfit_pos_size(crtc_state, pos, size); |
| 10523 | |
| 10524 | scaler_state->scalers[i].in_use = true1; |
| 10525 | break; |
| 10526 | } |
| 10527 | |
| 10528 | scaler_state->scaler_id = id; |
| 10529 | if (id >= 0) |
| 10530 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX31); |
| 10531 | else |
| 10532 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX31); |
| 10533 | } |
| 10534 | |
| 10535 | static void |
| 10536 | skl_get_initial_plane_config(struct intel_crtc *crtc, |
| 10537 | struct intel_initial_plane_config *plane_config) |
| 10538 | { |
| 10539 | struct drm_device *dev = crtc->base.dev; |
| 10540 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 10541 | struct intel_plane *plane = to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 10542 | enum plane_id plane_id = plane->id; |
| 10543 | enum pipe pipe; |
| 10544 | u32 val, base, offset, stride_mult, tiling, alpha; |
| 10545 | int fourcc, pixel_format; |
| 10546 | unsigned int aligned_height; |
| 10547 | struct drm_framebuffer *fb; |
| 10548 | struct intel_framebuffer *intel_fb; |
| 10549 | |
| 10550 | if (!plane->get_hw_state(plane, &pipe)) |
| 10551 | return; |
| 10552 | |
| 10553 | drm_WARN_ON(dev, pipe != crtc->pipe)({ int __ret = !!((pipe != crtc->pipe)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "pipe != crtc->pipe" ")"); __builtin_expect(!!(__ret), 0) ; }); |
| 10554 | |
| 10555 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL(0x0001 | 0x0004)); |
| 10556 | if (!intel_fb) { |
| 10557 | drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to alloc fb\n" ); |
| 10558 | return; |
| 10559 | } |
| 10560 | |
| 10561 | fb = &intel_fb->base; |
| 10562 | |
| 10563 | fb->dev = dev; |
| 10564 | |
| 10565 | val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id)((const i915_reg_t){ .reg = (((((0x70180) + (pipe) * ((0x71180 ) - (0x70180)))) + (plane_id) * ((((0x70280) + (pipe) * ((0x71280 ) - (0x70280)))) - (((0x70180) + (pipe) * ((0x71180) - (0x70180 ))))))) })); |
| 10566 | |
| 10567 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 10568 | pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK(0x1f << 23); |
| 10569 | else |
| 10570 | pixel_format = val & PLANE_CTL_FORMAT_MASK(0xf << 24); |
| 10571 | |
| 10572 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) { |
| 10573 | alpha = intel_de_read(dev_priv, |
| 10574 | PLANE_COLOR_CTL(pipe, plane_id)((const i915_reg_t){ .reg = (((((0x701CC) + (pipe) * ((0x711CC ) - (0x701CC)))) + (plane_id) * ((((0x702CC) + (pipe) * ((0x712CC ) - (0x702CC)))) - (((0x701CC) + (pipe) * ((0x711CC) - (0x701CC ))))))) })); |
| 10575 | alpha &= PLANE_COLOR_ALPHA_MASK(0x3 << 4); |
| 10576 | } else { |
| 10577 | alpha = val & PLANE_CTL_ALPHA_MASK(0x3 << 4); |
| 10578 | } |
| 10579 | |
| 10580 | fourcc = skl_format_to_fourcc(pixel_format, |
| 10581 | val & PLANE_CTL_ORDER_RGBX(1 << 20), alpha); |
| 10582 | fb->format = drm_format_info(fourcc); |
| 10583 | |
| 10584 | tiling = val & PLANE_CTL_TILED_MASK(0x7 << 10); |
| 10585 | switch (tiling) { |
| 10586 | case PLANE_CTL_TILED_LINEAR(0 << 10): |
| 10587 | fb->modifier = DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ); |
| 10588 | break; |
| 10589 | case PLANE_CTL_TILED_X(1 << 10): |
| 10590 | plane_config->tiling = I915_TILING_X1; |
| 10591 | fb->modifier = I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
| 10592 | break; |
| 10593 | case PLANE_CTL_TILED_Y(4 << 10): |
| 10594 | plane_config->tiling = I915_TILING_Y2; |
| 10595 | if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15)) |
| 10596 | fb->modifier = INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12 ? |
| 10597 | I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS((((__u64)0x01) << 56) | ((6) & 0x00ffffffffffffffULL )) : |
| 10598 | I915_FORMAT_MOD_Y_TILED_CCS((((__u64)0x01) << 56) | ((4) & 0x00ffffffffffffffULL )); |
| 10599 | else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE(1 << 4)) |
| 10600 | fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS((((__u64)0x01) << 56) | ((7) & 0x00ffffffffffffffULL )); |
| 10601 | else |
| 10602 | fb->modifier = I915_FORMAT_MOD_Y_TILED((((__u64)0x01) << 56) | ((2) & 0x00ffffffffffffffULL )); |
| 10603 | break; |
| 10604 | case PLANE_CTL_TILED_YF(5 << 10): |
| 10605 | if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE(1 << 15)) |
| 10606 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS((((__u64)0x01) << 56) | ((5) & 0x00ffffffffffffffULL )); |
| 10607 | else |
| 10608 | fb->modifier = I915_FORMAT_MOD_Yf_TILED((((__u64)0x01) << 56) | ((3) & 0x00ffffffffffffffULL )); |
| 10609 | break; |
| 10610 | default: |
| 10611 | MISSING_CASE(tiling)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "tiling", (long)(tiling)); __builtin_expect(!!(__ret), 0); } ); |
| 10612 | goto error; |
| 10613 | } |
| 10614 | |
| 10615 | /* |
| 10616 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
| 10617 | * while i915 HW rotation is clockwise, thats why this swapping. |
| 10618 | */ |
| 10619 | switch (val & PLANE_CTL_ROTATE_MASK0x3) { |
| 10620 | case PLANE_CTL_ROTATE_00x0: |
| 10621 | plane_config->rotation = DRM_MODE_ROTATE_0(1<<0); |
| 10622 | break; |
| 10623 | case PLANE_CTL_ROTATE_900x1: |
| 10624 | plane_config->rotation = DRM_MODE_ROTATE_270(1<<3); |
| 10625 | break; |
| 10626 | case PLANE_CTL_ROTATE_1800x2: |
| 10627 | plane_config->rotation = DRM_MODE_ROTATE_180(1<<2); |
| 10628 | break; |
| 10629 | case PLANE_CTL_ROTATE_2700x3: |
| 10630 | plane_config->rotation = DRM_MODE_ROTATE_90(1<<1); |
| 10631 | break; |
| 10632 | } |
| 10633 | |
| 10634 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 && |
| 10635 | val & PLANE_CTL_FLIP_HORIZONTAL(1 << 8)) |
| 10636 | plane_config->rotation |= DRM_MODE_REFLECT_X(1<<4); |
| 10637 | |
| 10638 | /* 90/270 degree rotation would require extra work */ |
| 10639 | if (drm_rotation_90_or_270(plane_config->rotation)) |
| 10640 | goto error; |
| 10641 | |
| 10642 | base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)((const i915_reg_t){ .reg = (((((0x7019c) + (pipe) * ((0x7119c ) - (0x7019c)))) + (plane_id) * ((((0x7029c) + (pipe) * ((0x7129c ) - (0x7029c)))) - (((0x7019c) + (pipe) * ((0x7119c) - (0x7019c ))))))) })) & 0xfffff000; |
| 10643 | plane_config->base = base; |
| 10644 | |
| 10645 | offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id)((const i915_reg_t){ .reg = (((((0x701a4) + (pipe) * ((0x711a4 ) - (0x701a4)))) + (plane_id) * ((((0x702a4) + (pipe) * ((0x712a4 ) - (0x702a4)))) - (((0x701a4) + (pipe) * ((0x711a4) - (0x701a4 ))))))) })); |
| 10646 | |
| 10647 | val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id)((const i915_reg_t){ .reg = (((((0x70190) + (pipe) * ((0x71190 ) - (0x70190)))) + (plane_id) * ((((0x70290) + (pipe) * ((0x71290 ) - (0x70290)))) - (((0x70190) + (pipe) * ((0x71190) - (0x70190 ))))))) })); |
| 10648 | fb->height = ((val >> 16) & 0xffff) + 1; |
| 10649 | fb->width = ((val >> 0) & 0xffff) + 1; |
| 10650 | |
| 10651 | val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id)((const i915_reg_t){ .reg = (((((0x70188) + (pipe) * ((0x71188 ) - (0x70188)))) + (plane_id) * ((((0x70288) + (pipe) * ((0x71288 ) - (0x70288)))) - (((0x70188) + (pipe) * ((0x71188) - (0x70188 ))))))) })); |
| 10652 | stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0(1<<0)); |
| 10653 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
| 10654 | |
| 10655 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
| 10656 | |
| 10657 | plane_config->size = fb->pitches[0] * aligned_height; |
| 10658 | |
| 10659 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 10660 | "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 10661 | crtc->base.name, plane->base.name, fb->width, fb->height,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 10662 | fb->format->cpp[0] * 8, base, fb->pitches[0],drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size) |
| 10663 | plane_config->size)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n" , crtc->base.name, plane->base.name, fb->width, fb-> height, fb->format->cpp[0] * 8, base, fb->pitches[0] , plane_config->size); |
| 10664 | |
| 10665 | plane_config->fb = intel_fb; |
| 10666 | return; |
| 10667 | |
| 10668 | error: |
| 10669 | kfree(intel_fb); |
| 10670 | } |
| 10671 | |
| 10672 | static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) |
| 10673 | { |
| 10674 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 10675 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10676 | u32 ctl, pos, size; |
| 10677 | |
| 10678 | ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe)((const i915_reg_t){ .reg = (((0x68080) + (crtc->pipe) * ( (0x68880) - (0x68080)))) })); |
| 10679 | if ((ctl & PF_ENABLE(1 << 31)) == 0) |
| 10680 | return; |
| 10681 | |
| 10682 | crtc_state->pch_pfit.enabled = true1; |
| 10683 | |
| 10684 | pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe)((const i915_reg_t){ .reg = (((0x68070) + (crtc->pipe) * ( (0x68870) - (0x68070)))) })); |
| 10685 | size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe)((const i915_reg_t){ .reg = (((0x68074) + (crtc->pipe) * ( (0x68874) - (0x68074)))) })); |
| 10686 | |
| 10687 | ilk_get_pfit_pos_size(crtc_state, pos, size); |
| 10688 | |
| 10689 | /* |
| 10690 | * We currently do not free assignements of panel fitters on |
| 10691 | * ivb/hsw (since we don't use the higher upscaling modes which |
| 10692 | * differentiates them) so just WARN about this case for now. |
| 10693 | */ |
| 10694 | drm_WARN_ON(&dev_priv->drm, IS_GEN(dev_priv, 7) &&({ int __ret = !!(((0 + (&(dev_priv)->__info)->gen == (7)) && (ctl & (3 << 29)) != ((crtc->pipe ) << 29))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(0 + (&(dev_priv)->__info)->gen == (7)) && (ctl & (3 << 29)) != ((crtc->pipe) << 29)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 10695 | (ctl & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe))({ int __ret = !!(((0 + (&(dev_priv)->__info)->gen == (7)) && (ctl & (3 << 29)) != ((crtc->pipe ) << 29))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "(0 + (&(dev_priv)->__info)->gen == (7)) && (ctl & (3 << 29)) != ((crtc->pipe) << 29)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 10696 | } |
| 10697 | |
| 10698 | static bool_Bool ilk_get_pipe_config(struct intel_crtc *crtc, |
| 10699 | struct intel_crtc_state *pipe_config) |
| 10700 | { |
| 10701 | struct drm_device *dev = crtc->base.dev; |
| 10702 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 10703 | enum intel_display_power_domain power_domain; |
| 10704 | intel_wakeref_t wakeref; |
| 10705 | u32 tmp; |
| 10706 | bool_Bool ret; |
| 10707 | |
| 10708 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe)((crtc->pipe) + POWER_DOMAIN_PIPE_A); |
| 10709 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 10710 | if (!wakeref) |
| 10711 | return false0; |
| 10712 | |
| 10713 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 10714 | pipe_config->shared_dpll = NULL((void *)0); |
| 10715 | |
| 10716 | ret = false0; |
| 10717 | tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 10718 | if (!(tmp & PIPECONF_ENABLE(1 << 31))) |
| 10719 | goto out; |
| 10720 | |
| 10721 | switch (tmp & PIPECONF_BPC_MASK(0x7 << 5)) { |
| 10722 | case PIPECONF_6BPC(2 << 5): |
| 10723 | pipe_config->pipe_bpp = 18; |
| 10724 | break; |
| 10725 | case PIPECONF_8BPC(0 << 5): |
| 10726 | pipe_config->pipe_bpp = 24; |
| 10727 | break; |
| 10728 | case PIPECONF_10BPC(1 << 5): |
| 10729 | pipe_config->pipe_bpp = 30; |
| 10730 | break; |
| 10731 | case PIPECONF_12BPC(3 << 5): |
| 10732 | pipe_config->pipe_bpp = 36; |
| 10733 | break; |
| 10734 | default: |
| 10735 | break; |
| 10736 | } |
| 10737 | |
| 10738 | if (tmp & PIPECONF_COLOR_RANGE_SELECT(1 << 13)) |
| 10739 | pipe_config->limited_color_range = true1; |
| 10740 | |
| 10741 | switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK(3 << 11)) { |
| 10742 | case PIPECONF_OUTPUT_COLORSPACE_YUV601(1 << 11): |
| 10743 | case PIPECONF_OUTPUT_COLORSPACE_YUV709(2 << 11): |
| 10744 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; |
| 10745 | break; |
| 10746 | default: |
| 10747 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 10748 | break; |
| 10749 | } |
| 10750 | |
| 10751 | pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK(3 << 24)) >> |
| 10752 | PIPECONF_GAMMA_MODE_SHIFT24; |
| 10753 | |
| 10754 | pipe_config->csc_mode = intel_de_read(dev_priv, |
| 10755 | PIPE_CSC_MODE(crtc->pipe)((const i915_reg_t){ .reg = (((0x49028) + (crtc->pipe) * ( (0x49128) - (0x49028)))) })); |
| 10756 | |
| 10757 | i9xx_get_pipe_color_config(pipe_config); |
| 10758 | intel_color_get_config(pipe_config); |
| 10759 | |
| 10760 | if (intel_de_read(dev_priv, PCH_TRANSCONF(crtc->pipe)((const i915_reg_t){ .reg = (((0xf0008) + (crtc->pipe) * ( (0xf1008) - (0xf0008)))) })) & TRANS_ENABLE(1 << 31)) { |
| 10761 | struct intel_shared_dpll *pll; |
| 10762 | enum intel_dpll_id pll_id; |
| 10763 | |
| 10764 | pipe_config->has_pch_encoder = true1; |
| 10765 | |
| 10766 | tmp = intel_de_read(dev_priv, FDI_RX_CTL(crtc->pipe)((const i915_reg_t){ .reg = (((0xf000c) + (crtc->pipe) * ( (0xf100c) - (0xf000c)))) })); |
| 10767 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK(7 << 19) & tmp) >> |
| 10768 | FDI_DP_PORT_WIDTH_SHIFT19) + 1; |
| 10769 | |
| 10770 | ilk_get_fdi_m_n_config(crtc, pipe_config); |
| 10771 | |
| 10772 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) { |
| 10773 | /* |
| 10774 | * The pipe->pch transcoder and pch transcoder->pll |
| 10775 | * mapping is fixed. |
| 10776 | */ |
| 10777 | pll_id = (enum intel_dpll_id) crtc->pipe; |
| 10778 | } else { |
| 10779 | tmp = intel_de_read(dev_priv, PCH_DPLL_SEL((const i915_reg_t){ .reg = (0xc7000) })); |
| 10780 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)(1 << ((crtc->pipe) * 4))) |
| 10781 | pll_id = DPLL_ID_PCH_PLL_B; |
| 10782 | else |
| 10783 | pll_id= DPLL_ID_PCH_PLL_A; |
| 10784 | } |
| 10785 | |
| 10786 | pipe_config->shared_dpll = |
| 10787 | intel_get_shared_dpll_by_id(dev_priv, pll_id); |
| 10788 | pll = pipe_config->shared_dpll; |
| 10789 | |
| 10790 | drm_WARN_ON(dev, !pll->info->funcs->get_hw_state(dev_priv, pll,({ int __ret = !!((!pll->info->funcs->get_hw_state(dev_priv , pll, &pipe_config->dpll_hw_state))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "!pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 10791 | &pipe_config->dpll_hw_state))({ int __ret = !!((!pll->info->funcs->get_hw_state(dev_priv , pll, &pipe_config->dpll_hw_state))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "!pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 10792 | |
| 10793 | tmp = pipe_config->dpll_hw_state.dpll; |
| 10794 | pipe_config->pixel_multiplier = |
| 10795 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK(7 << 9)) |
| 10796 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT9) + 1; |
| 10797 | |
| 10798 | ilk_pch_clock_get(crtc, pipe_config); |
| 10799 | } else { |
| 10800 | pipe_config->pixel_multiplier = 1; |
| 10801 | } |
| 10802 | |
| 10803 | intel_get_pipe_timings(crtc, pipe_config); |
| 10804 | intel_get_pipe_src_size(crtc, pipe_config); |
| 10805 | |
| 10806 | ilk_get_pfit_config(pipe_config); |
| 10807 | |
| 10808 | ret = true1; |
| 10809 | |
| 10810 | out: |
| 10811 | intel_display_power_put(dev_priv, power_domain, wakeref); |
| 10812 | |
| 10813 | return ret; |
| 10814 | } |
| 10815 | |
| 10816 | static int hsw_crtc_compute_clock(struct intel_crtc *crtc, |
| 10817 | struct intel_crtc_state *crtc_state) |
| 10818 | { |
| 10819 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 10820 | struct intel_atomic_state *state = |
| 10821 | to_intel_atomic_state(crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 10822 | |
| 10823 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || |
| 10824 | INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) { |
| 10825 | struct intel_encoder *encoder = |
| 10826 | intel_get_crtc_new_encoder(state, crtc_state); |
| 10827 | |
| 10828 | if (!intel_reserve_shared_dplls(state, crtc, encoder)) { |
| 10829 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to find PLL for pipe %c\n" , ((crtc->pipe) + 'A')) |
| 10830 | "failed to find PLL for pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to find PLL for pipe %c\n" , ((crtc->pipe) + 'A')) |
| 10831 | pipe_name(crtc->pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to find PLL for pipe %c\n" , ((crtc->pipe) + 'A')); |
| 10832 | return -EINVAL22; |
| 10833 | } |
| 10834 | } |
| 10835 | |
| 10836 | return 0; |
| 10837 | } |
| 10838 | |
| 10839 | static void cnl_get_ddi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port, |
| 10840 | struct intel_crtc_state *pipe_config) |
| 10841 | { |
| 10842 | enum intel_dpll_id id; |
| 10843 | u32 temp; |
| 10844 | |
| 10845 | temp = intel_de_read(dev_priv, DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x6C200) })) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)(3 << ((port) == PORT_F ? 21 : (port) * 2)); |
| 10846 | id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)((port) == PORT_F ? 21 : (port) * 2); |
| 10847 | |
| 10848 | if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL2)({ int __ret = !!((id < 0 || id > 2)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "id < 0 || id > 2" ")"); __builtin_expect (!!(__ret), 0); })) |
| 10849 | return; |
| 10850 | |
| 10851 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
| 10852 | } |
| 10853 | |
| 10854 | static void icl_get_ddi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port, |
| 10855 | struct intel_crtc_state *pipe_config) |
| 10856 | { |
| 10857 | enum phy phy = intel_port_to_phy(dev_priv, port); |
| 10858 | enum icl_port_dpll_id port_dpll_id; |
| 10859 | enum intel_dpll_id id; |
| 10860 | u32 temp; |
| 10861 | |
| 10862 | if (intel_phy_is_combo(dev_priv, phy)) { |
| 10863 | u32 mask, shift; |
| 10864 | |
| 10865 | if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) { |
| 10866 | mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << (((const u32 []){ 0, 2, 4, 27 })[phy])); |
| 10867 | shift = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)(((const u32 []){ 0, 2, 4, 27 })[phy]); |
| 10868 | } else { |
| 10869 | mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << ((phy) * 2)); |
| 10870 | shift = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)((phy) * 2); |
| 10871 | } |
| 10872 | |
| 10873 | temp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) })) & mask; |
| 10874 | id = temp >> shift; |
| 10875 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
| 10876 | } else if (intel_phy_is_tc(dev_priv, phy)) { |
| 10877 | u32 clk_sel = intel_de_read(dev_priv, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })) & DDI_CLK_SEL_MASK(0xF << 28); |
| 10878 | |
| 10879 | if (clk_sel == DDI_CLK_SEL_MG(0x8 << 28)) { |
| 10880 | id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv, |
| 10881 | port)); |
| 10882 | port_dpll_id = ICL_PORT_DPLL_MG_PHY; |
| 10883 | } else { |
| 10884 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((clk_sel < (0xC << 28))); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "clk_sel < (0xC << 28)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 10885 | clk_sel < DDI_CLK_SEL_TBT_162)({ int __ret = !!((clk_sel < (0xC << 28))); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "clk_sel < (0xC << 28)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 10886 | id = DPLL_ID_ICL_TBTPLL; |
| 10887 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
| 10888 | } |
| 10889 | } else { |
| 10890 | drm_WARN(&dev_priv->drm, 1, "Invalid port %x\n", port)({ int __ret = !!(1); if (__ret) printf("%s %s: " "Invalid port %x\n" , dev_driver_string((&dev_priv->drm)->dev), "", port ); __builtin_expect(!!(__ret), 0); }); |
| 10891 | return; |
| 10892 | } |
| 10893 | |
| 10894 | pipe_config->icl_port_dplls[port_dpll_id].pll = |
| 10895 | intel_get_shared_dpll_by_id(dev_priv, id); |
| 10896 | |
| 10897 | icl_set_active_port_dpll(pipe_config, port_dpll_id); |
| 10898 | } |
| 10899 | |
| 10900 | static void bxt_get_ddi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 10901 | enum port port, |
| 10902 | struct intel_crtc_state *pipe_config) |
| 10903 | { |
| 10904 | enum intel_dpll_id id; |
| 10905 | |
| 10906 | switch (port) { |
| 10907 | case PORT_A: |
| 10908 | id = DPLL_ID_SKL_DPLL0; |
| 10909 | break; |
| 10910 | case PORT_B: |
| 10911 | id = DPLL_ID_SKL_DPLL1; |
| 10912 | break; |
| 10913 | case PORT_C: |
| 10914 | id = DPLL_ID_SKL_DPLL2; |
| 10915 | break; |
| 10916 | default: |
| 10917 | drm_err(&dev_priv->drm, "Incorrect port type\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Incorrect port type\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 10918 | return; |
| 10919 | } |
| 10920 | |
| 10921 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
| 10922 | } |
| 10923 | |
| 10924 | static void skl_get_ddi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port, |
| 10925 | struct intel_crtc_state *pipe_config) |
| 10926 | { |
| 10927 | enum intel_dpll_id id; |
| 10928 | u32 temp; |
| 10929 | |
| 10930 | temp = intel_de_read(dev_priv, DPLL_CTRL2((const i915_reg_t){ .reg = (0x6C05C) })) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)(3 << ((port) * 3 + 1)); |
| 10931 | id = temp >> (port * 3 + 1); |
| 10932 | |
| 10933 | if (drm_WARN_ON(&dev_priv->drm, id < SKL_DPLL0 || id > SKL_DPLL3)({ int __ret = !!((id < 0 || id > 3)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "id < 0 || id > 3" ")"); __builtin_expect (!!(__ret), 0); })) |
| 10934 | return; |
| 10935 | |
| 10936 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
| 10937 | } |
| 10938 | |
| 10939 | static void hsw_get_ddi_pll(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port, |
| 10940 | struct intel_crtc_state *pipe_config) |
| 10941 | { |
| 10942 | enum intel_dpll_id id; |
| 10943 | u32 ddi_pll_sel = intel_de_read(dev_priv, PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })); |
| 10944 | |
| 10945 | switch (ddi_pll_sel) { |
| 10946 | case PORT_CLK_SEL_WRPLL1(4 << 29): |
| 10947 | id = DPLL_ID_WRPLL1; |
| 10948 | break; |
| 10949 | case PORT_CLK_SEL_WRPLL2(5 << 29): |
| 10950 | id = DPLL_ID_WRPLL2; |
| 10951 | break; |
| 10952 | case PORT_CLK_SEL_SPLL(3 << 29): |
| 10953 | id = DPLL_ID_SPLL; |
| 10954 | break; |
| 10955 | case PORT_CLK_SEL_LCPLL_810(2 << 29): |
| 10956 | id = DPLL_ID_LCPLL_810; |
| 10957 | break; |
| 10958 | case PORT_CLK_SEL_LCPLL_1350(1 << 29): |
| 10959 | id = DPLL_ID_LCPLL_1350; |
| 10960 | break; |
| 10961 | case PORT_CLK_SEL_LCPLL_2700(0 << 29): |
| 10962 | id = DPLL_ID_LCPLL_2700; |
| 10963 | break; |
| 10964 | default: |
| 10965 | MISSING_CASE(ddi_pll_sel)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "ddi_pll_sel", (long)(ddi_pll_sel)); __builtin_expect(!!(__ret ), 0); }); |
| 10966 | fallthroughdo {} while (0); |
| 10967 | case PORT_CLK_SEL_NONE(7 << 29): |
| 10968 | return; |
| 10969 | } |
| 10970 | |
| 10971 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); |
| 10972 | } |
| 10973 | |
| 10974 | static bool_Bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
| 10975 | struct intel_crtc_state *pipe_config, |
| 10976 | u64 *power_domain_mask, |
| 10977 | intel_wakeref_t *wakerefs) |
| 10978 | { |
| 10979 | struct drm_device *dev = crtc->base.dev; |
| 10980 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 10981 | enum intel_display_power_domain power_domain; |
| 10982 | unsigned long panel_transcoder_mask = BIT(TRANSCODER_EDP)(1UL << (TRANSCODER_EDP)); |
| 10983 | unsigned long enabled_panel_transcoders = 0; |
| 10984 | enum transcoder panel_transcoder; |
| 10985 | intel_wakeref_t wf; |
| 10986 | u32 tmp; |
| 10987 | |
| 10988 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 10989 | panel_transcoder_mask |= |
| 10990 | BIT(TRANSCODER_DSI_0)(1UL << (TRANSCODER_DSI_0)) | BIT(TRANSCODER_DSI_1)(1UL << (TRANSCODER_DSI_1)); |
| 10991 | |
| 10992 | /* |
| 10993 | * The pipe->transcoder mapping is fixed with the exception of the eDP |
| 10994 | * and DSI transcoders handled below. |
| 10995 | */ |
| 10996 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
| 10997 | |
| 10998 | /* |
| 10999 | * XXX: Do intel_display_power_get_if_enabled before reading this (for |
| 11000 | * consistency and less surprising code; it's in always on power). |
| 11001 | */ |
| 11002 | for_each_cpu_transcoder_masked(dev_priv, panel_transcoder,for ((panel_transcoder) = 0; (panel_transcoder) < I915_MAX_TRANSCODERS ; (panel_transcoder)++) if (!((&(dev_priv)->__info)-> cpu_transcoder_mask & (1UL << (panel_transcoder)))) {} else if (!((panel_transcoder_mask) & (1UL << (panel_transcoder )))) {} else |
| 11003 | panel_transcoder_mask)for ((panel_transcoder) = 0; (panel_transcoder) < I915_MAX_TRANSCODERS ; (panel_transcoder)++) if (!((&(dev_priv)->__info)-> cpu_transcoder_mask & (1UL << (panel_transcoder)))) {} else if (!((panel_transcoder_mask) & (1UL << (panel_transcoder )))) {} else { |
| 11004 | bool_Bool force_thru = false0; |
| 11005 | enum pipe trans_pipe; |
| 11006 | |
| 11007 | tmp = intel_de_read(dev_priv, |
| 11008 | TRANS_DDI_FUNC_CTL(panel_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(panel_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60400) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 11009 | if (!(tmp & TRANS_DDI_FUNC_ENABLE(1 << 31))) |
| 11010 | continue; |
| 11011 | |
| 11012 | /* |
| 11013 | * Log all enabled ones, only use the first one. |
| 11014 | * |
| 11015 | * FIXME: This won't work for two separate DSI displays. |
| 11016 | */ |
| 11017 | enabled_panel_transcoders |= BIT(panel_transcoder)(1UL << (panel_transcoder)); |
| 11018 | if (enabled_panel_transcoders != BIT(panel_transcoder)(1UL << (panel_transcoder))) |
| 11019 | continue; |
| 11020 | |
| 11021 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK(7 << 12)) { |
| 11022 | default: |
| 11023 | drm_WARN(dev, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "unknown pipe linked to transcoder %s\n" , dev_driver_string((dev)->dev), "", transcoder_name(panel_transcoder )); __builtin_expect(!!(__ret), 0); }) |
| 11024 | "unknown pipe linked to transcoder %s\n",({ int __ret = !!(1); if (__ret) printf("%s %s: " "unknown pipe linked to transcoder %s\n" , dev_driver_string((dev)->dev), "", transcoder_name(panel_transcoder )); __builtin_expect(!!(__ret), 0); }) |
| 11025 | transcoder_name(panel_transcoder))({ int __ret = !!(1); if (__ret) printf("%s %s: " "unknown pipe linked to transcoder %s\n" , dev_driver_string((dev)->dev), "", transcoder_name(panel_transcoder )); __builtin_expect(!!(__ret), 0); }); |
| 11026 | fallthroughdo {} while (0); |
| 11027 | case TRANS_DDI_EDP_INPUT_A_ONOFF(4 << 12): |
| 11028 | force_thru = true1; |
| 11029 | fallthroughdo {} while (0); |
| 11030 | case TRANS_DDI_EDP_INPUT_A_ON(0 << 12): |
| 11031 | trans_pipe = PIPE_A; |
| 11032 | break; |
| 11033 | case TRANS_DDI_EDP_INPUT_B_ONOFF(5 << 12): |
| 11034 | trans_pipe = PIPE_B; |
| 11035 | break; |
| 11036 | case TRANS_DDI_EDP_INPUT_C_ONOFF(6 << 12): |
| 11037 | trans_pipe = PIPE_C; |
| 11038 | break; |
| 11039 | case TRANS_DDI_EDP_INPUT_D_ONOFF(7 << 12): |
| 11040 | trans_pipe = PIPE_D; |
| 11041 | break; |
| 11042 | } |
| 11043 | |
| 11044 | if (trans_pipe == crtc->pipe) { |
| 11045 | pipe_config->cpu_transcoder = panel_transcoder; |
| 11046 | pipe_config->pch_pfit.force_thru = force_thru; |
| 11047 | } |
| 11048 | } |
| 11049 | |
| 11050 | /* |
| 11051 | * Valid combos: none, eDP, DSI0, DSI1, DSI0+DSI1 |
| 11052 | */ |
| 11053 | drm_WARN_ON(dev, (enabled_panel_transcoders & BIT(TRANSCODER_EDP)) &&({ int __ret = !!(((enabled_panel_transcoders & (1UL << (TRANSCODER_EDP))) && enabled_panel_transcoders != ( 1UL << (TRANSCODER_EDP)))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "(enabled_panel_transcoders & (1UL << (TRANSCODER_EDP))) && enabled_panel_transcoders != (1UL << (TRANSCODER_EDP))" ")"); __builtin_expect(!!(__ret), 0); }) |
| 11054 | enabled_panel_transcoders != BIT(TRANSCODER_EDP))({ int __ret = !!(((enabled_panel_transcoders & (1UL << (TRANSCODER_EDP))) && enabled_panel_transcoders != ( 1UL << (TRANSCODER_EDP)))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "(enabled_panel_transcoders & (1UL << (TRANSCODER_EDP))) && enabled_panel_transcoders != (1UL << (TRANSCODER_EDP))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11055 | |
| 11056 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)((pipe_config->cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (pipe_config->cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A ); |
| 11057 | drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain))({ int __ret = !!((*power_domain_mask & (1ULL << (power_domain )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev ))->dev), "", "drm_WARN_ON(" "*power_domain_mask & (1ULL << (power_domain))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11058 | |
| 11059 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 11060 | if (!wf) |
| 11061 | return false0; |
| 11062 | |
| 11063 | wakerefs[power_domain] = wf; |
| 11064 | *power_domain_mask |= BIT_ULL(power_domain)(1ULL << (power_domain)); |
| 11065 | |
| 11066 | tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe_config->cpu_transcoder] - (&(dev_priv )->__info)->pipe_offsets[PIPE_A] + (0x70008) + ((&( dev_priv)->__info)->display_mmio_offset)) })); |
| 11067 | |
| 11068 | return tmp & PIPECONF_ENABLE(1 << 31); |
| 11069 | } |
| 11070 | |
| 11071 | static bool_Bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
| 11072 | struct intel_crtc_state *pipe_config, |
| 11073 | u64 *power_domain_mask, |
| 11074 | intel_wakeref_t *wakerefs) |
| 11075 | { |
| 11076 | struct drm_device *dev = crtc->base.dev; |
| 11077 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 11078 | enum intel_display_power_domain power_domain; |
| 11079 | enum transcoder cpu_transcoder; |
| 11080 | intel_wakeref_t wf; |
| 11081 | enum port port; |
| 11082 | u32 tmp; |
| 11083 | |
| 11084 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C))for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if (!(((1UL << (PORT_A)) | (1UL << (PORT_C))) & (1UL << (port)))) {} else { |
| 11085 | if (port == PORT_A) |
| 11086 | cpu_transcoder = TRANSCODER_DSI_A; |
| 11087 | else |
| 11088 | cpu_transcoder = TRANSCODER_DSI_C; |
| 11089 | |
| 11090 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A); |
| 11091 | drm_WARN_ON(dev, *power_domain_mask & BIT_ULL(power_domain))({ int __ret = !!((*power_domain_mask & (1ULL << (power_domain )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev ))->dev), "", "drm_WARN_ON(" "*power_domain_mask & (1ULL << (power_domain))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11092 | |
| 11093 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 11094 | if (!wf) |
| 11095 | continue; |
| 11096 | |
| 11097 | wakerefs[power_domain] = wf; |
| 11098 | *power_domain_mask |= BIT_ULL(power_domain)(1ULL << (power_domain)); |
| 11099 | |
| 11100 | /* |
| 11101 | * The PLL needs to be enabled with a valid divider |
| 11102 | * configuration, otherwise accessing DSI registers will hang |
| 11103 | * the machine. See BSpec North Display Engine |
| 11104 | * registers/MIPI[BXT]. We can break out here early, since we |
| 11105 | * need the same DSI PLL to be enabled for both DSI ports. |
| 11106 | */ |
| 11107 | if (!bxt_dsi_pll_is_enabled(dev_priv)) |
| 11108 | break; |
| 11109 | |
| 11110 | /* XXX: this works for video mode only */ |
| 11111 | tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0 )) })); |
| 11112 | if (!(tmp & DPI_ENABLE(1 << 31))) |
| 11113 | continue; |
| 11114 | |
| 11115 | tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (dev_priv-> mipi_mmio_base + 0xb104) : (dev_priv->mipi_mmio_base + 0xb904 ))) })); |
| 11116 | if ((tmp & BXT_PIPE_SELECT_MASK(7 << 7)) != BXT_PIPE_SELECT(crtc->pipe)((crtc->pipe) << 7)) |
| 11117 | continue; |
| 11118 | |
| 11119 | pipe_config->cpu_transcoder = cpu_transcoder; |
| 11120 | break; |
| 11121 | } |
| 11122 | |
| 11123 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
| 11124 | } |
| 11125 | |
| 11126 | static void hsw_get_ddi_port_state(struct intel_crtc *crtc, |
| 11127 | struct intel_crtc_state *pipe_config) |
| 11128 | { |
| 11129 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 11130 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
| 11131 | struct intel_shared_dpll *pll; |
| 11132 | enum port port; |
| 11133 | u32 tmp; |
| 11134 | |
| 11135 | if (transcoder_is_dsi(cpu_transcoder)) { |
| 11136 | port = (cpu_transcoder == TRANSCODER_DSI_A) ? |
| 11137 | PORT_A : PORT_B; |
| 11138 | } else { |
| 11139 | tmp = intel_de_read(dev_priv, |
| 11140 | TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60400) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 11141 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 11142 | port = TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp)((((tmp) & (0xf << 27)) >> 27) - 1); |
| 11143 | else |
| 11144 | port = TRANS_DDI_FUNC_CTL_VAL_TO_PORT(tmp)(((tmp) & (7 << 28)) >> 28); |
| 11145 | } |
| 11146 | |
| 11147 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 11148 | icl_get_ddi_pll(dev_priv, port, pipe_config); |
| 11149 | else if (IS_CANNONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)) |
| 11150 | cnl_get_ddi_pll(dev_priv, port, pipe_config); |
| 11151 | else if (IS_GEN9_BC(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && !((&(dev_priv)->__info)->is_lp))) |
| 11152 | skl_get_ddi_pll(dev_priv, port, pipe_config); |
| 11153 | else if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) |
| 11154 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
| 11155 | else |
| 11156 | hsw_get_ddi_pll(dev_priv, port, pipe_config); |
| 11157 | |
| 11158 | pll = pipe_config->shared_dpll; |
| 11159 | if (pll) { |
| 11160 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((!pll->info->funcs->get_hw_state(dev_priv , pll, &pipe_config->dpll_hw_state))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 11161 | !pll->info->funcs->get_hw_state(dev_priv, pll,({ int __ret = !!((!pll->info->funcs->get_hw_state(dev_priv , pll, &pipe_config->dpll_hw_state))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 11162 | &pipe_config->dpll_hw_state))({ int __ret = !!((!pll->info->funcs->get_hw_state(dev_priv , pll, &pipe_config->dpll_hw_state))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!pll->info->funcs->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11163 | } |
| 11164 | |
| 11165 | /* |
| 11166 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
| 11167 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
| 11168 | * the PCH transcoder is on. |
| 11169 | */ |
| 11170 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9 && |
| 11171 | (port == PORT_E) && intel_de_read(dev_priv, LPT_TRANSCONF((const i915_reg_t){ .reg = (((0xf0008) + (PIPE_A) * ((0xf1008 ) - (0xf0008)))) })) & TRANS_ENABLE(1 << 31)) { |
| 11172 | pipe_config->has_pch_encoder = true1; |
| 11173 | |
| 11174 | tmp = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A)((const i915_reg_t){ .reg = (((0xf000c) + (PIPE_A) * ((0xf100c ) - (0xf000c)))) })); |
| 11175 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK(7 << 19) & tmp) >> |
| 11176 | FDI_DP_PORT_WIDTH_SHIFT19) + 1; |
| 11177 | |
| 11178 | ilk_get_fdi_m_n_config(crtc, pipe_config); |
| 11179 | } |
| 11180 | } |
| 11181 | |
| 11182 | static bool_Bool hsw_get_pipe_config(struct intel_crtc *crtc, |
| 11183 | struct intel_crtc_state *pipe_config) |
| 11184 | { |
| 11185 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 11186 | intel_wakeref_t wakerefs[POWER_DOMAIN_NUM], wf; |
| 11187 | enum intel_display_power_domain power_domain; |
| 11188 | u64 power_domain_mask; |
| 11189 | bool_Bool active; |
| 11190 | u32 tmp; |
| 11191 | |
| 11192 | pipe_config->master_transcoder = INVALID_TRANSCODER; |
| 11193 | |
| 11194 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe)((crtc->pipe) + POWER_DOMAIN_PIPE_A); |
| 11195 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 11196 | if (!wf) |
| 11197 | return false0; |
| 11198 | |
| 11199 | wakerefs[power_domain] = wf; |
| 11200 | power_domain_mask = BIT_ULL(power_domain)(1ULL << (power_domain)); |
| 11201 | |
| 11202 | pipe_config->shared_dpll = NULL((void *)0); |
| 11203 | |
| 11204 | active = hsw_get_transcoder_state(crtc, pipe_config, |
| 11205 | &power_domain_mask, wakerefs); |
| 11206 | |
| 11207 | if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)) && |
| 11208 | bxt_get_dsi_transcoder_state(crtc, pipe_config, |
| 11209 | &power_domain_mask, wakerefs)) { |
| 11210 | drm_WARN_ON(&dev_priv->drm, active)({ int __ret = !!((active)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "active" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11211 | active = true1; |
| 11212 | } |
| 11213 | |
| 11214 | if (!active) |
| 11215 | goto out; |
| 11216 | |
| 11217 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || |
| 11218 | INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) { |
| 11219 | hsw_get_ddi_port_state(crtc, pipe_config); |
| 11220 | intel_get_pipe_timings(crtc, pipe_config); |
| 11221 | } |
| 11222 | |
| 11223 | intel_get_pipe_src_size(crtc, pipe_config); |
| 11224 | |
| 11225 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) { |
| 11226 | u32 tmp = intel_de_read(dev_priv, |
| 11227 | PIPECONF(pipe_config->cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe_config->cpu_transcoder] - (&(dev_priv )->__info)->pipe_offsets[PIPE_A] + (0x70008) + ((&( dev_priv)->__info)->display_mmio_offset)) })); |
| 11228 | |
| 11229 | if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW(1 << 11)) |
| 11230 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; |
| 11231 | else |
| 11232 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
| 11233 | } else { |
| 11234 | pipe_config->output_format = |
| 11235 | bdw_get_pipemisc_output_format(crtc); |
| 11236 | |
| 11237 | /* |
| 11238 | * Currently there is no interface defined to |
| 11239 | * check user preference between RGB/YCBCR444 |
| 11240 | * or YCBCR420. So the only possible case for |
| 11241 | * YCBCR444 usage is driving YCBCR420 output |
| 11242 | * with LSPCON, when pipe is configured for |
| 11243 | * YCBCR444 output and LSPCON takes care of |
| 11244 | * downsampling it. |
| 11245 | */ |
| 11246 | pipe_config->lspcon_downsampling = |
| 11247 | pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444; |
| 11248 | } |
| 11249 | |
| 11250 | pipe_config->gamma_mode = intel_de_read(dev_priv, |
| 11251 | GAMMA_MODE(crtc->pipe)((const i915_reg_t){ .reg = (((0x4a480) + (crtc->pipe) * ( (0x4ac80) - (0x4a480)))) })); |
| 11252 | |
| 11253 | pipe_config->csc_mode = intel_de_read(dev_priv, |
| 11254 | PIPE_CSC_MODE(crtc->pipe)((const i915_reg_t){ .reg = (((0x49028) + (crtc->pipe) * ( (0x49128) - (0x49028)))) })); |
| 11255 | |
| 11256 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) { |
| 11257 | tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70034) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 11258 | |
| 11259 | if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE(1 << 31)) |
| 11260 | pipe_config->gamma_enable = true1; |
| 11261 | |
| 11262 | if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE(1 << 30)) |
| 11263 | pipe_config->csc_enable = true1; |
| 11264 | } else { |
| 11265 | i9xx_get_pipe_color_config(pipe_config); |
| 11266 | } |
| 11267 | |
| 11268 | intel_color_get_config(pipe_config); |
| 11269 | |
| 11270 | tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe)((const i915_reg_t){ .reg = (((0x45270) + (crtc->pipe) * ( (0x45274) - (0x45270)))) })); |
| 11271 | pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp)((u32)((typeof(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (0))) + 0))))(((tmp) & (((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (0))) + 0))) ) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (8 ) - 1)) & ((~0UL) << (0))) + 0))) - 1)))); |
| 11272 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 11273 | pipe_config->ips_linetime = |
| 11274 | REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp)((u32)((typeof(((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) << (16))) + 0))))(((tmp) & (((u32)((((~0UL ) >> (64 - (24) - 1)) & ((~0UL) << (16))) + 0 )))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (24) - 1)) & ((~0UL) << (16))) + 0))) - 1)))); |
| 11275 | |
| 11276 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe)((crtc->pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER); |
| 11277 | drm_WARN_ON(&dev_priv->drm, power_domain_mask & BIT_ULL(power_domain))({ int __ret = !!((power_domain_mask & (1ULL << (power_domain )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "power_domain_mask & (1ULL << (power_domain))" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11278 | |
| 11279 | wf = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 11280 | if (wf) { |
| 11281 | wakerefs[power_domain] = wf; |
| 11282 | power_domain_mask |= BIT_ULL(power_domain)(1ULL << (power_domain)); |
| 11283 | |
| 11284 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 11285 | skl_get_pfit_config(pipe_config); |
| 11286 | else |
| 11287 | ilk_get_pfit_config(pipe_config); |
| 11288 | } |
| 11289 | |
| 11290 | if (hsw_crtc_supports_ips(crtc)) { |
| 11291 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 11292 | pipe_config->ips_enabled = intel_de_read(dev_priv, |
| 11293 | IPS_CTL((const i915_reg_t){ .reg = (0x43408) })) & IPS_ENABLE(1 << 31); |
| 11294 | else { |
| 11295 | /* |
| 11296 | * We cannot readout IPS state on broadwell, set to |
| 11297 | * true so we can set it to a defined state on first |
| 11298 | * commit. |
| 11299 | */ |
| 11300 | pipe_config->ips_enabled = true1; |
| 11301 | } |
| 11302 | } |
| 11303 | |
| 11304 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
| 11305 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
| 11306 | pipe_config->pixel_multiplier = |
| 11307 | intel_de_read(dev_priv, |
| 11308 | PIPE_MULT(pipe_config->cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe_config->cpu_transcoder)] - (&(dev_priv )->__info)->trans_offsets[TRANSCODER_A] + (0x6002c) + ( (&(dev_priv)->__info)->display_mmio_offset))) })) + 1; |
| 11309 | } else { |
| 11310 | pipe_config->pixel_multiplier = 1; |
| 11311 | } |
| 11312 | |
| 11313 | out: |
| 11314 | for_each_power_domain(power_domain, power_domain_mask)for ((power_domain) = 0; (power_domain) < POWER_DOMAIN_NUM ; (power_domain)++) if (!((1ULL << (power_domain)) & (power_domain_mask))) {} else |
| 11315 | intel_display_power_put(dev_priv, |
| 11316 | power_domain, wakerefs[power_domain]); |
| 11317 | |
| 11318 | return active; |
| 11319 | } |
| 11320 | |
| 11321 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
| 11322 | { |
| 11323 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 11324 | to_i915(plane_state->uapi.plane->dev); |
| 11325 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 11326 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 11327 | u32 base; |
| 11328 | |
| 11329 | if (INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.cursor_needs_physical) |
| 11330 | base = sg_dma_address(obj->mm.pages->sgl)((obj->mm.pages->sgl)->dma_address); |
| 11331 | else |
| 11332 | base = intel_plane_ggtt_offset(plane_state); |
| 11333 | |
| 11334 | return base + plane_state->color_plane[0].offset; |
| 11335 | } |
| 11336 | |
| 11337 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
| 11338 | { |
| 11339 | int x = plane_state->uapi.dst.x1; |
| 11340 | int y = plane_state->uapi.dst.y1; |
| 11341 | u32 pos = 0; |
| 11342 | |
| 11343 | if (x < 0) { |
| 11344 | pos |= CURSOR_POS_SIGN0x8000 << CURSOR_X_SHIFT0; |
| 11345 | x = -x; |
| 11346 | } |
| 11347 | pos |= x << CURSOR_X_SHIFT0; |
| 11348 | |
| 11349 | if (y < 0) { |
| 11350 | pos |= CURSOR_POS_SIGN0x8000 << CURSOR_Y_SHIFT16; |
| 11351 | y = -y; |
| 11352 | } |
| 11353 | pos |= y << CURSOR_Y_SHIFT16; |
| 11354 | |
| 11355 | return pos; |
| 11356 | } |
| 11357 | |
| 11358 | static bool_Bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
| 11359 | { |
| 11360 | const struct drm_mode_config *config = |
| 11361 | &plane_state->uapi.plane->dev->mode_config; |
| 11362 | int width = drm_rect_width(&plane_state->uapi.dst); |
| 11363 | int height = drm_rect_height(&plane_state->uapi.dst); |
| 11364 | |
| 11365 | return width > 0 && width <= config->cursor_width && |
| 11366 | height > 0 && height <= config->cursor_height; |
| 11367 | } |
| 11368 | |
| 11369 | static int intel_cursor_check_surface(struct intel_plane_state *plane_state) |
| 11370 | { |
| 11371 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 11372 | to_i915(plane_state->uapi.plane->dev); |
| 11373 | unsigned int rotation = plane_state->hw.rotation; |
| 11374 | int src_x, src_y; |
| 11375 | u32 offset; |
| 11376 | int ret; |
| 11377 | |
| 11378 | ret = intel_plane_compute_gtt(plane_state); |
| 11379 | if (ret) |
| 11380 | return ret; |
| 11381 | |
| 11382 | if (!plane_state->uapi.visible) |
| 11383 | return 0; |
| 11384 | |
| 11385 | src_x = plane_state->uapi.src.x1 >> 16; |
| 11386 | src_y = plane_state->uapi.src.y1 >> 16; |
| 11387 | |
| 11388 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
| 11389 | offset = intel_plane_compute_aligned_offset(&src_x, &src_y, |
| 11390 | plane_state, 0); |
| 11391 | |
| 11392 | if (src_x != 0 || src_y != 0) { |
| 11393 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Arbitrary cursor panning not supported\n" ) |
| 11394 | "Arbitrary cursor panning not supported\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Arbitrary cursor panning not supported\n" ); |
| 11395 | return -EINVAL22; |
| 11396 | } |
| 11397 | |
| 11398 | /* |
| 11399 | * Put the final coordinates back so that the src |
| 11400 | * coordinate checks will see the right values. |
| 11401 | */ |
| 11402 | drm_rect_translate_to(&plane_state->uapi.src, |
| 11403 | src_x << 16, src_y << 16); |
| 11404 | |
| 11405 | /* ILK+ do this automagically in hardware */ |
| 11406 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && rotation & DRM_MODE_ROTATE_180(1<<2)) { |
| 11407 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 11408 | int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; |
| 11409 | int src_h = drm_rect_height(&plane_state->uapi.src) >> 16; |
| 11410 | |
| 11411 | offset += (src_h * src_w - 1) * fb->format->cpp[0]; |
| 11412 | } |
| 11413 | |
| 11414 | plane_state->color_plane[0].offset = offset; |
| 11415 | plane_state->color_plane[0].x = src_x; |
| 11416 | plane_state->color_plane[0].y = src_y; |
| 11417 | |
| 11418 | return 0; |
| 11419 | } |
| 11420 | |
| 11421 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
| 11422 | struct intel_plane_state *plane_state) |
| 11423 | { |
| 11424 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 11425 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane_state->uapi.plane->dev); |
| 11426 | int ret; |
| 11427 | |
| 11428 | if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) )) { |
| 11429 | drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "cursor cannot be tiled\n" ); |
| 11430 | return -EINVAL22; |
| 11431 | } |
| 11432 | |
| 11433 | ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, |
| 11434 | &crtc_state->uapi, |
| 11435 | DRM_PLANE_HELPER_NO_SCALING(1<<16), |
| 11436 | DRM_PLANE_HELPER_NO_SCALING(1<<16), |
| 11437 | true1, true1); |
| 11438 | if (ret) |
| 11439 | return ret; |
| 11440 | |
| 11441 | /* Use the unclipped src/dst rectangles, which we program to hw */ |
| 11442 | plane_state->uapi.src = drm_plane_state_src(&plane_state->uapi); |
| 11443 | plane_state->uapi.dst = drm_plane_state_dest(&plane_state->uapi); |
| 11444 | |
| 11445 | ret = intel_cursor_check_surface(plane_state); |
| 11446 | if (ret) |
| 11447 | return ret; |
| 11448 | |
| 11449 | if (!plane_state->uapi.visible) |
| 11450 | return 0; |
| 11451 | |
| 11452 | ret = intel_plane_check_src_coordinates(plane_state); |
| 11453 | if (ret) |
| 11454 | return ret; |
| 11455 | |
| 11456 | return 0; |
| 11457 | } |
| 11458 | |
| 11459 | static unsigned int |
| 11460 | i845_cursor_max_stride(struct intel_plane *plane, |
| 11461 | u32 pixel_format, u64 modifier, |
| 11462 | unsigned int rotation) |
| 11463 | { |
| 11464 | return 2048; |
| 11465 | } |
| 11466 | |
| 11467 | static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) |
| 11468 | { |
| 11469 | u32 cntl = 0; |
| 11470 | |
| 11471 | if (crtc_state->gamma_enable) |
| 11472 | cntl |= CURSOR_GAMMA_ENABLE0x40000000; |
| 11473 | |
| 11474 | return cntl; |
| 11475 | } |
| 11476 | |
| 11477 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
| 11478 | const struct intel_plane_state *plane_state) |
| 11479 | { |
| 11480 | return CURSOR_ENABLE0x80000000 | |
| 11481 | CURSOR_FORMAT_ARGB(0x04 << 24) | |
| 11482 | CURSOR_STRIDE(plane_state->color_plane[0].stride)((ffs(plane_state->color_plane[0].stride) - 9) << 28 ); |
| 11483 | } |
| 11484 | |
| 11485 | static bool_Bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
| 11486 | { |
| 11487 | int width = drm_rect_width(&plane_state->uapi.dst); |
| 11488 | |
| 11489 | /* |
| 11490 | * 845g/865g are only limited by the width of their cursors, |
| 11491 | * the height is arbitrary up to the precision of the register. |
| 11492 | */ |
| 11493 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64)(((width) & ((64) - 1)) == 0); |
| 11494 | } |
| 11495 | |
| 11496 | static int i845_check_cursor(struct intel_crtc_state *crtc_state, |
| 11497 | struct intel_plane_state *plane_state) |
| 11498 | { |
| 11499 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 11500 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane_state->uapi.plane->dev); |
| 11501 | int ret; |
| 11502 | |
| 11503 | ret = intel_check_cursor(crtc_state, plane_state); |
| 11504 | if (ret) |
| 11505 | return ret; |
| 11506 | |
| 11507 | /* if we want to turn off the cursor ignore width and height */ |
| 11508 | if (!fb) |
| 11509 | return 0; |
| 11510 | |
| 11511 | /* Check for which cursor types we support */ |
| 11512 | if (!i845_cursor_size_ok(plane_state)) { |
| 11513 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)) |
| 11514 | "Cursor dimension %dx%d not supported\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)) |
| 11515 | drm_rect_width(&plane_state->uapi.dst),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)) |
| 11516 | drm_rect_height(&plane_state->uapi.dst))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)); |
| 11517 | return -EINVAL22; |
| 11518 | } |
| 11519 | |
| 11520 | drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&({ int __ret = !!((plane_state->uapi.visible && plane_state ->color_plane[0].stride != fb->pitches[0])); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm ))->dev), "", "drm_WARN_ON(" "plane_state->uapi.visible && plane_state->color_plane[0].stride != fb->pitches[0]" ")"); __builtin_expect(!!(__ret), 0); }) |
| 11521 | plane_state->color_plane[0].stride != fb->pitches[0])({ int __ret = !!((plane_state->uapi.visible && plane_state ->color_plane[0].stride != fb->pitches[0])); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm ))->dev), "", "drm_WARN_ON(" "plane_state->uapi.visible && plane_state->color_plane[0].stride != fb->pitches[0]" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11522 | |
| 11523 | switch (fb->pitches[0]) { |
| 11524 | case 256: |
| 11525 | case 512: |
| 11526 | case 1024: |
| 11527 | case 2048: |
| 11528 | break; |
| 11529 | default: |
| 11530 | drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Invalid cursor stride (%u)\n" , fb->pitches[0]) |
| 11531 | fb->pitches[0])drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Invalid cursor stride (%u)\n" , fb->pitches[0]); |
| 11532 | return -EINVAL22; |
| 11533 | } |
| 11534 | |
| 11535 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
| 11536 | |
| 11537 | return 0; |
| 11538 | } |
| 11539 | |
| 11540 | static void i845_update_cursor(struct intel_plane *plane, |
| 11541 | const struct intel_crtc_state *crtc_state, |
| 11542 | const struct intel_plane_state *plane_state) |
| 11543 | { |
| 11544 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 11545 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
| 11546 | unsigned long irqflags; |
| 11547 | |
| 11548 | if (plane_state && plane_state->uapi.visible) { |
| 11549 | unsigned int width = drm_rect_width(&plane_state->uapi.dst); |
| 11550 | unsigned int height = drm_rect_height(&plane_state->uapi.dst); |
| 11551 | |
| 11552 | cntl = plane_state->ctl | |
| 11553 | i845_cursor_ctl_crtc(crtc_state); |
| 11554 | |
| 11555 | size = (height << 12) | width; |
| 11556 | |
| 11557 | base = intel_cursor_base(plane_state); |
| 11558 | pos = intel_cursor_position(plane_state); |
| 11559 | } |
| 11560 | |
| 11561 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); } while (0); |
| 11562 | |
| 11563 | /* On these chipsets we can only modify the base/size/stride |
| 11564 | * whilst the cursor is disabled. |
| 11565 | */ |
| 11566 | if (plane->cursor.base != base || |
| 11567 | plane->cursor.size != size || |
| 11568 | plane->cursor.cntl != cntl) { |
| 11569 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) }), 0); |
| 11570 | intel_de_write_fw(dev_priv, CURBASE(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70084) + ((&(dev_priv)->__info)->display_mmio_offset )) }), base); |
| 11571 | intel_de_write_fw(dev_priv, CURSIZE((const i915_reg_t){ .reg = (0x700a0) }), size); |
| 11572 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset )) }), pos); |
| 11573 | intel_de_write_fw(dev_priv, CURCNTR(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) }), cntl); |
| 11574 | |
| 11575 | plane->cursor.base = base; |
| 11576 | plane->cursor.size = size; |
| 11577 | plane->cursor.cntl = cntl; |
| 11578 | } else { |
| 11579 | intel_de_write_fw(dev_priv, CURPOS(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset )) }), pos); |
| 11580 | } |
| 11581 | |
| 11582 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock ); } while (0); |
| 11583 | } |
| 11584 | |
| 11585 | static void i845_disable_cursor(struct intel_plane *plane, |
| 11586 | const struct intel_crtc_state *crtc_state) |
| 11587 | { |
| 11588 | i845_update_cursor(plane, crtc_state, NULL((void *)0)); |
| 11589 | } |
| 11590 | |
| 11591 | static bool_Bool i845_cursor_get_hw_state(struct intel_plane *plane, |
| 11592 | enum pipe *pipe) |
| 11593 | { |
| 11594 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 11595 | enum intel_display_power_domain power_domain; |
| 11596 | intel_wakeref_t wakeref; |
| 11597 | bool_Bool ret; |
| 11598 | |
| 11599 | power_domain = POWER_DOMAIN_PIPE(PIPE_A)((PIPE_A) + POWER_DOMAIN_PIPE_A); |
| 11600 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 11601 | if (!wakeref) |
| 11602 | return false0; |
| 11603 | |
| 11604 | ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & CURSOR_ENABLE0x80000000; |
| 11605 | |
| 11606 | *pipe = PIPE_A; |
| 11607 | |
| 11608 | intel_display_power_put(dev_priv, power_domain, wakeref); |
| 11609 | |
| 11610 | return ret; |
| 11611 | } |
| 11612 | |
| 11613 | static unsigned int |
| 11614 | i9xx_cursor_max_stride(struct intel_plane *plane, |
| 11615 | u32 pixel_format, u64 modifier, |
| 11616 | unsigned int rotation) |
| 11617 | { |
| 11618 | return plane->base.dev->mode_config.cursor_width * 4; |
| 11619 | } |
| 11620 | |
| 11621 | static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state) |
| 11622 | { |
| 11623 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 11624 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 11625 | u32 cntl = 0; |
| 11626 | |
| 11627 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 11628 | return cntl; |
| 11629 | |
| 11630 | if (crtc_state->gamma_enable) |
| 11631 | cntl = MCURSOR_GAMMA_ENABLE(1 << 26); |
| 11632 | |
| 11633 | if (crtc_state->csc_enable) |
| 11634 | cntl |= MCURSOR_PIPE_CSC_ENABLE(1 << 24); |
| 11635 | |
| 11636 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5 && !IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 11637 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe)((crtc->pipe) << 28); |
| 11638 | |
| 11639 | return cntl; |
| 11640 | } |
| 11641 | |
| 11642 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
| 11643 | const struct intel_plane_state *plane_state) |
| 11644 | { |
| 11645 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 11646 | to_i915(plane_state->uapi.plane->dev); |
| 11647 | u32 cntl = 0; |
| 11648 | |
| 11649 | if (IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6)) || IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
| 11650 | cntl |= MCURSOR_TRICKLE_FEED_DISABLE(1 << 14); |
| 11651 | |
| 11652 | switch (drm_rect_width(&plane_state->uapi.dst)) { |
| 11653 | case 64: |
| 11654 | cntl |= MCURSOR_MODE_64_ARGB_AX((1 << 5) | 0x07); |
| 11655 | break; |
| 11656 | case 128: |
| 11657 | cntl |= MCURSOR_MODE_128_ARGB_AX((1 << 5) | 0x02); |
| 11658 | break; |
| 11659 | case 256: |
| 11660 | cntl |= MCURSOR_MODE_256_ARGB_AX((1 << 5) | 0x03); |
| 11661 | break; |
| 11662 | default: |
| 11663 | MISSING_CASE(drm_rect_width(&plane_state->uapi.dst))({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "drm_rect_width(&plane_state->uapi.dst)", (long)(drm_rect_width (&plane_state->uapi.dst))); __builtin_expect(!!(__ret) , 0); }); |
| 11664 | return 0; |
| 11665 | } |
| 11666 | |
| 11667 | if (plane_state->hw.rotation & DRM_MODE_ROTATE_180(1<<2)) |
| 11668 | cntl |= MCURSOR_ROTATE_180(1 << 15); |
| 11669 | |
| 11670 | return cntl; |
| 11671 | } |
| 11672 | |
| 11673 | static bool_Bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
| 11674 | { |
| 11675 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 11676 | to_i915(plane_state->uapi.plane->dev); |
| 11677 | int width = drm_rect_width(&plane_state->uapi.dst); |
| 11678 | int height = drm_rect_height(&plane_state->uapi.dst); |
| 11679 | |
| 11680 | if (!intel_cursor_size_ok(plane_state)) |
| 11681 | return false0; |
| 11682 | |
| 11683 | /* Cursor width is limited to a few power-of-two sizes */ |
| 11684 | switch (width) { |
| 11685 | case 256: |
| 11686 | case 128: |
| 11687 | case 64: |
| 11688 | break; |
| 11689 | default: |
| 11690 | return false0; |
| 11691 | } |
| 11692 | |
| 11693 | /* |
| 11694 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor |
| 11695 | * height from 8 lines up to the cursor width, when the |
| 11696 | * cursor is not rotated. Everything else requires square |
| 11697 | * cursors. |
| 11698 | */ |
| 11699 | if (HAS_CUR_FBC(dev_priv)(!((&(dev_priv)->__info)->display.has_gmch) && ((&(dev_priv)->__info)->gen) >= 7) && |
| 11700 | plane_state->hw.rotation & DRM_MODE_ROTATE_0(1<<0)) { |
| 11701 | if (height < 8 || height > width) |
| 11702 | return false0; |
| 11703 | } else { |
| 11704 | if (height != width) |
| 11705 | return false0; |
| 11706 | } |
| 11707 | |
| 11708 | return true1; |
| 11709 | } |
| 11710 | |
| 11711 | static int i9xx_check_cursor(struct intel_crtc_state *crtc_state, |
| 11712 | struct intel_plane_state *plane_state) |
| 11713 | { |
| 11714 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 11715 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 11716 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 11717 | enum pipe pipe = plane->pipe; |
| 11718 | int ret; |
| 11719 | |
| 11720 | ret = intel_check_cursor(crtc_state, plane_state); |
| 11721 | if (ret) |
| 11722 | return ret; |
| 11723 | |
| 11724 | /* if we want to turn off the cursor ignore width and height */ |
| 11725 | if (!fb) |
| 11726 | return 0; |
| 11727 | |
| 11728 | /* Check for which cursor types we support */ |
| 11729 | if (!i9xx_cursor_size_ok(plane_state)) { |
| 11730 | drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)) |
| 11731 | "Cursor dimension %dx%d not supported\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)) |
| 11732 | drm_rect_width(&plane_state->uapi.dst),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)) |
| 11733 | drm_rect_height(&plane_state->uapi.dst))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Cursor dimension %dx%d not supported\n" , drm_rect_width(&plane_state->uapi.dst), drm_rect_height (&plane_state->uapi.dst)); |
| 11734 | return -EINVAL22; |
| 11735 | } |
| 11736 | |
| 11737 | drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&({ int __ret = !!((plane_state->uapi.visible && plane_state ->color_plane[0].stride != fb->pitches[0])); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "plane_state->uapi.visible && plane_state->color_plane[0].stride != fb->pitches[0]" ")"); __builtin_expect(!!(__ret), 0); }) |
| 11738 | plane_state->color_plane[0].stride != fb->pitches[0])({ int __ret = !!((plane_state->uapi.visible && plane_state ->color_plane[0].stride != fb->pitches[0])); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "plane_state->uapi.visible && plane_state->color_plane[0].stride != fb->pitches[0]" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11739 | |
| 11740 | if (fb->pitches[0] != |
| 11741 | drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) { |
| 11742 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid cursor stride (%u) (cursor width %d)\n" , fb->pitches[0], drm_rect_width(&plane_state->uapi .dst)) |
| 11743 | "Invalid cursor stride (%u) (cursor width %d)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid cursor stride (%u) (cursor width %d)\n" , fb->pitches[0], drm_rect_width(&plane_state->uapi .dst)) |
| 11744 | fb->pitches[0],drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid cursor stride (%u) (cursor width %d)\n" , fb->pitches[0], drm_rect_width(&plane_state->uapi .dst)) |
| 11745 | drm_rect_width(&plane_state->uapi.dst))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Invalid cursor stride (%u) (cursor width %d)\n" , fb->pitches[0], drm_rect_width(&plane_state->uapi .dst)); |
| 11746 | return -EINVAL22; |
| 11747 | } |
| 11748 | |
| 11749 | /* |
| 11750 | * There's something wrong with the cursor on CHV pipe C. |
| 11751 | * If it straddles the left edge of the screen then |
| 11752 | * moving it away from the edge or disabling it often |
| 11753 | * results in a pipe underrun, and often that can lead to |
| 11754 | * dead pipe (constant underrun reported, and it scans |
| 11755 | * out just a solid color). To recover from that, the |
| 11756 | * display power well must be turned off and on again. |
| 11757 | * Refuse the put the cursor into that compromised position. |
| 11758 | */ |
| 11759 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && pipe == PIPE_C && |
| 11760 | plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) { |
| 11761 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "CHV cursor C not allowed to straddle the left screen edge\n" ) |
| 11762 | "CHV cursor C not allowed to straddle the left screen edge\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "CHV cursor C not allowed to straddle the left screen edge\n" ); |
| 11763 | return -EINVAL22; |
| 11764 | } |
| 11765 | |
| 11766 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
| 11767 | |
| 11768 | return 0; |
| 11769 | } |
| 11770 | |
| 11771 | static void i9xx_update_cursor(struct intel_plane *plane, |
| 11772 | const struct intel_crtc_state *crtc_state, |
| 11773 | const struct intel_plane_state *plane_state) |
| 11774 | { |
| 11775 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 11776 | enum pipe pipe = plane->pipe; |
| 11777 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
| 11778 | unsigned long irqflags; |
| 11779 | |
| 11780 | if (plane_state && plane_state->uapi.visible) { |
| 11781 | unsigned width = drm_rect_width(&plane_state->uapi.dst); |
| 11782 | unsigned height = drm_rect_height(&plane_state->uapi.dst); |
| 11783 | |
| 11784 | cntl = plane_state->ctl | |
| 11785 | i9xx_cursor_ctl_crtc(crtc_state); |
| 11786 | |
| 11787 | if (width != height) |
| 11788 | fbc_ctl = CUR_FBC_CTL_EN(1 << 31) | (height - 1); |
| 11789 | |
| 11790 | base = intel_cursor_base(plane_state); |
| 11791 | pos = intel_cursor_position(plane_state); |
| 11792 | } |
| 11793 | |
| 11794 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)do { irqflags = 0; mtx_enter(&dev_priv->uncore.lock); } while (0); |
| 11795 | |
| 11796 | /* |
| 11797 | * On some platforms writing CURCNTR first will also |
| 11798 | * cause CURPOS to be armed by the CURBASE write. |
| 11799 | * Without the CURCNTR write the CURPOS write would |
| 11800 | * arm itself. Thus we always update CURCNTR before |
| 11801 | * CURPOS. |
| 11802 | * |
| 11803 | * On other platforms CURPOS always requires the |
| 11804 | * CURBASE write to arm the update. Additonally |
| 11805 | * a write to any of the cursor register will cancel |
| 11806 | * an already armed cursor update. Thus leaving out |
| 11807 | * the CURBASE write after CURPOS could lead to a |
| 11808 | * cursor that doesn't appear to move, or even change |
| 11809 | * shape. Thus we always write CURBASE. |
| 11810 | * |
| 11811 | * The other registers are armed by by the CURBASE write |
| 11812 | * except when the plane is getting enabled at which time |
| 11813 | * the CURCNTR write arms the update. |
| 11814 | */ |
| 11815 | |
| 11816 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 11817 | skl_write_cursor_wm(plane, crtc_state); |
| 11818 | |
| 11819 | if (plane->cursor.base != base || |
| 11820 | plane->cursor.size != fbc_ctl || |
| 11821 | plane->cursor.cntl != cntl) { |
| 11822 | if (HAS_CUR_FBC(dev_priv)(!((&(dev_priv)->__info)->display.has_gmch) && ((&(dev_priv)->__info)->gen) >= 7)) |
| 11823 | intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x700a0) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 11824 | fbc_ctl); |
| 11825 | intel_de_write_fw(dev_priv, CURCNTR(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) }), cntl); |
| 11826 | intel_de_write_fw(dev_priv, CURPOS(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset )) }), pos); |
| 11827 | intel_de_write_fw(dev_priv, CURBASE(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70084) + ((&(dev_priv)->__info)->display_mmio_offset )) }), base); |
| 11828 | |
| 11829 | plane->cursor.base = base; |
| 11830 | plane->cursor.size = fbc_ctl; |
| 11831 | plane->cursor.cntl = cntl; |
| 11832 | } else { |
| 11833 | intel_de_write_fw(dev_priv, CURPOS(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset )) }), pos); |
| 11834 | intel_de_write_fw(dev_priv, CURBASE(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(pipe)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70084) + ((&(dev_priv)->__info)->display_mmio_offset )) }), base); |
| 11835 | } |
| 11836 | |
| 11837 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)do { (void)(irqflags); mtx_leave(&dev_priv->uncore.lock ); } while (0); |
| 11838 | } |
| 11839 | |
| 11840 | static void i9xx_disable_cursor(struct intel_plane *plane, |
| 11841 | const struct intel_crtc_state *crtc_state) |
| 11842 | { |
| 11843 | i9xx_update_cursor(plane, crtc_state, NULL((void *)0)); |
| 11844 | } |
| 11845 | |
| 11846 | static bool_Bool i9xx_cursor_get_hw_state(struct intel_plane *plane, |
| 11847 | enum pipe *pipe) |
| 11848 | { |
| 11849 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 11850 | enum intel_display_power_domain power_domain; |
| 11851 | intel_wakeref_t wakeref; |
| 11852 | bool_Bool ret; |
| 11853 | u32 val; |
| 11854 | |
| 11855 | /* |
| 11856 | * Not 100% correct for planes that can move between pipes, |
| 11857 | * but that's only the case for gen2-3 which don't have any |
| 11858 | * display power wells. |
| 11859 | */ |
| 11860 | power_domain = POWER_DOMAIN_PIPE(plane->pipe)((plane->pipe) + POWER_DOMAIN_PIPE_A); |
| 11861 | wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); |
| 11862 | if (!wakeref) |
| 11863 | return false0; |
| 11864 | |
| 11865 | val = intel_de_read(dev_priv, CURCNTR(plane->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(plane->pipe)] - (&(dev_priv)->__info )->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)-> __info)->display_mmio_offset)) })); |
| 11866 | |
| 11867 | ret = val & MCURSOR_MODE0x27; |
| 11868 | |
| 11869 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 11870 | *pipe = plane->pipe; |
| 11871 | else |
| 11872 | *pipe = (val & MCURSOR_PIPE_SELECT_MASK(0x3 << 28)) >> |
| 11873 | MCURSOR_PIPE_SELECT_SHIFT28; |
| 11874 | |
| 11875 | intel_display_power_put(dev_priv, power_domain, wakeref); |
| 11876 | |
| 11877 | return ret; |
| 11878 | } |
| 11879 | |
| 11880 | /* VESA 640x480x72Hz mode to set on the pipe */ |
| 11881 | static const struct drm_display_mode load_detect_mode = { |
| 11882 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,.name = "640x480", .status = 0, .type = ((1<<4)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (491), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)) |
| 11883 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC).name = "640x480", .status = 0, .type = ((1<<4)), .clock = (31500), .hdisplay = (640), .hsync_start = (664), .hsync_end = (704), .htotal = (832), .hskew = (0), .vdisplay = (480), . vsync_start = (489), .vsync_end = (491), .vtotal = (520), .vscan = (0), .flags = ((1<<1) | (1<<3)), |
| 11884 | }; |
| 11885 | |
| 11886 | struct drm_framebuffer * |
| 11887 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
| 11888 | struct drm_mode_fb_cmd2 *mode_cmd) |
| 11889 | { |
| 11890 | struct intel_framebuffer *intel_fb; |
| 11891 | int ret; |
| 11892 | |
| 11893 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL(0x0001 | 0x0004)); |
| 11894 | if (!intel_fb) |
| 11895 | return ERR_PTR(-ENOMEM12); |
| 11896 | |
| 11897 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
| 11898 | if (ret) |
| 11899 | goto err; |
| 11900 | |
| 11901 | return &intel_fb->base; |
| 11902 | |
| 11903 | err: |
| 11904 | kfree(intel_fb); |
| 11905 | return ERR_PTR(ret); |
| 11906 | } |
| 11907 | |
| 11908 | static int intel_modeset_disable_planes(struct drm_atomic_state *state, |
| 11909 | struct drm_crtc *crtc) |
| 11910 | { |
| 11911 | struct drm_plane *plane; |
| 11912 | struct drm_plane_state *plane_state; |
| 11913 | int ret, i; |
| 11914 | |
| 11915 | ret = drm_atomic_add_affected_planes(state, crtc); |
| 11916 | if (ret) |
| 11917 | return ret; |
| 11918 | |
| 11919 | for_each_new_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane ; (i)++) if (!((state)->planes[i].ptr && ((plane) = (state)->planes[i].ptr, (void)(plane) , (plane_state) = ( state)->planes[i].new_state, (void)(plane_state) , 1))) {} else { |
| 11920 | if (plane_state->crtc != crtc) |
| 11921 | continue; |
| 11922 | |
| 11923 | ret = drm_atomic_set_crtc_for_plane(plane_state, NULL((void *)0)); |
| 11924 | if (ret) |
| 11925 | return ret; |
| 11926 | |
| 11927 | drm_atomic_set_fb_for_plane(plane_state, NULL((void *)0)); |
| 11928 | } |
| 11929 | |
| 11930 | return 0; |
| 11931 | } |
| 11932 | |
| 11933 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
| 11934 | struct intel_load_detect_pipe *old, |
| 11935 | struct drm_modeset_acquire_ctx *ctx) |
| 11936 | { |
| 11937 | struct intel_crtc *intel_crtc; |
| 11938 | struct intel_encoder *intel_encoder = |
| 11939 | intel_attached_encoder(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 11940 | struct drm_crtc *possible_crtc; |
| 11941 | struct drm_encoder *encoder = &intel_encoder->base; |
| 11942 | struct drm_crtc *crtc = NULL((void *)0); |
| 11943 | struct drm_device *dev = encoder->dev; |
| 11944 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 11945 | struct drm_mode_config *config = &dev->mode_config; |
| 11946 | struct drm_atomic_state *state = NULL((void *)0), *restore_state = NULL((void *)0); |
| 11947 | struct drm_connector_state *connector_state; |
| 11948 | struct intel_crtc_state *crtc_state; |
| 11949 | int ret, i = -1; |
| 11950 | |
| 11951 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , connector->base.id, connector->name, encoder->base .id, encoder->name) |
| 11952 | connector->base.id, connector->name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , connector->base.id, connector->name, encoder->base .id, encoder->name) |
| 11953 | encoder->base.id, encoder->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , connector->base.id, connector->name, encoder->base .id, encoder->name); |
| 11954 | |
| 11955 | old->restore_state = NULL((void *)0); |
| 11956 | |
| 11957 | drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex))({ int __ret = !!((!drm_modeset_is_locked(&config->connection_mutex ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev ))->dev), "", "drm_WARN_ON(" "!drm_modeset_is_locked(&config->connection_mutex)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 11958 | |
| 11959 | /* |
| 11960 | * Algorithm gets a little messy: |
| 11961 | * |
| 11962 | * - if the connector already has an assigned crtc, use it (but make |
| 11963 | * sure it's on first) |
| 11964 | * |
| 11965 | * - try to find the first unused crtc that can drive this connector, |
| 11966 | * and use that if we find one |
| 11967 | */ |
| 11968 | |
| 11969 | /* See if we already have a CRTC for this connector */ |
| 11970 | if (connector->state->crtc) { |
| 11971 | crtc = connector->state->crtc; |
| 11972 | |
| 11973 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
| 11974 | if (ret) |
| 11975 | goto fail; |
| 11976 | |
| 11977 | /* Make sure the crtc and connector are running */ |
| 11978 | goto found; |
| 11979 | } |
| 11980 | |
| 11981 | /* Find an unused one (if possible) */ |
| 11982 | for_each_crtc(dev, possible_crtc)for (possible_crtc = ({ const __typeof( ((__typeof(*possible_crtc ) *)0)->head ) *__mptr = ((&(dev)->mode_config.crtc_list )->next); (__typeof(*possible_crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*possible_crtc), head) );}); &possible_crtc-> head != (&(dev)->mode_config.crtc_list); possible_crtc = ({ const __typeof( ((__typeof(*possible_crtc) *)0)->head ) *__mptr = (possible_crtc->head.next); (__typeof(*possible_crtc ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*possible_crtc ), head) );})) { |
| 11983 | i++; |
| 11984 | if (!(encoder->possible_crtcs & (1 << i))) |
| 11985 | continue; |
| 11986 | |
| 11987 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); |
| 11988 | if (ret) |
| 11989 | goto fail; |
| 11990 | |
| 11991 | if (possible_crtc->state->enable) { |
| 11992 | drm_modeset_unlock(&possible_crtc->mutex); |
| 11993 | continue; |
| 11994 | } |
| 11995 | |
| 11996 | crtc = possible_crtc; |
| 11997 | break; |
| 11998 | } |
| 11999 | |
| 12000 | /* |
| 12001 | * If we didn't find an unused CRTC, don't use any. |
| 12002 | */ |
| 12003 | if (!crtc) { |
| 12004 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no pipe available for load-detect\n" ) |
| 12005 | "no pipe available for load-detect\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "no pipe available for load-detect\n" ); |
| 12006 | ret = -ENODEV19; |
| 12007 | goto fail; |
| 12008 | } |
| 12009 | |
| 12010 | found: |
| 12011 | intel_crtc = to_intel_crtc(crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}); |
| 12012 | |
| 12013 | state = drm_atomic_state_alloc(dev); |
| 12014 | restore_state = drm_atomic_state_alloc(dev); |
| 12015 | if (!state || !restore_state) { |
| 12016 | ret = -ENOMEM12; |
| 12017 | goto fail; |
| 12018 | } |
| 12019 | |
| 12020 | state->acquire_ctx = ctx; |
| 12021 | restore_state->acquire_ctx = ctx; |
| 12022 | |
| 12023 | connector_state = drm_atomic_get_connector_state(state, connector); |
| 12024 | if (IS_ERR(connector_state)) { |
| 12025 | ret = PTR_ERR(connector_state); |
| 12026 | goto fail; |
| 12027 | } |
| 12028 | |
| 12029 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
| 12030 | if (ret) |
| 12031 | goto fail; |
| 12032 | |
| 12033 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
| 12034 | if (IS_ERR(crtc_state)) { |
| 12035 | ret = PTR_ERR(crtc_state); |
| 12036 | goto fail; |
| 12037 | } |
| 12038 | |
| 12039 | crtc_state->uapi.active = true1; |
| 12040 | |
| 12041 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->uapi, |
| 12042 | &load_detect_mode); |
| 12043 | if (ret) |
| 12044 | goto fail; |
| 12045 | |
| 12046 | ret = intel_modeset_disable_planes(state, crtc); |
| 12047 | if (ret) |
| 12048 | goto fail; |
| 12049 | |
| 12050 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); |
| 12051 | if (!ret) |
| 12052 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); |
| 12053 | if (!ret) |
| 12054 | ret = drm_atomic_add_affected_planes(restore_state, crtc); |
| 12055 | if (ret) { |
| 12056 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to create a copy of old state to restore: %i\n" , ret) |
| 12057 | "Failed to create a copy of old state to restore: %i\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to create a copy of old state to restore: %i\n" , ret) |
| 12058 | ret)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Failed to create a copy of old state to restore: %i\n" , ret); |
| 12059 | goto fail; |
| 12060 | } |
| 12061 | |
| 12062 | ret = drm_atomic_commit(state); |
| 12063 | if (ret) { |
| 12064 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to set mode on load-detect pipe\n" ) |
| 12065 | "failed to set mode on load-detect pipe\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "failed to set mode on load-detect pipe\n" ); |
| 12066 | goto fail; |
| 12067 | } |
| 12068 | |
| 12069 | old->restore_state = restore_state; |
| 12070 | drm_atomic_state_put(state); |
| 12071 | |
| 12072 | /* let the connector get through one full cycle before testing */ |
| 12073 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
| 12074 | return true1; |
| 12075 | |
| 12076 | fail: |
| 12077 | if (state) { |
| 12078 | drm_atomic_state_put(state); |
| 12079 | state = NULL((void *)0); |
| 12080 | } |
| 12081 | if (restore_state) { |
| 12082 | drm_atomic_state_put(restore_state); |
| 12083 | restore_state = NULL((void *)0); |
| 12084 | } |
| 12085 | |
| 12086 | if (ret == -EDEADLK11) |
| 12087 | return ret; |
| 12088 | |
| 12089 | return false0; |
| 12090 | } |
| 12091 | |
| 12092 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
| 12093 | struct intel_load_detect_pipe *old, |
| 12094 | struct drm_modeset_acquire_ctx *ctx) |
| 12095 | { |
| 12096 | struct intel_encoder *intel_encoder = |
| 12097 | intel_attached_encoder(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
| 12098 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(intel_encoder->base.dev); |
| 12099 | struct drm_encoder *encoder = &intel_encoder->base; |
| 12100 | struct drm_atomic_state *state = old->restore_state; |
| 12101 | int ret; |
| 12102 | |
| 12103 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , connector->base.id, connector->name, encoder->base .id, encoder->name) |
| 12104 | connector->base.id, connector->name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , connector->base.id, connector->name, encoder->base .id, encoder->name) |
| 12105 | encoder->base.id, encoder->name)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n" , connector->base.id, connector->name, encoder->base .id, encoder->name); |
| 12106 | |
| 12107 | if (!state) |
| 12108 | return; |
| 12109 | |
| 12110 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
| 12111 | if (ret) |
| 12112 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Couldn't release load detect pipe: %i\n" , ret) |
| 12113 | "Couldn't release load detect pipe: %i\n", ret)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Couldn't release load detect pipe: %i\n" , ret); |
| 12114 | drm_atomic_state_put(state); |
| 12115 | } |
| 12116 | |
| 12117 | static int i9xx_pll_refclk(struct drm_device *dev, |
| 12118 | const struct intel_crtc_state *pipe_config) |
| 12119 | { |
| 12120 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 12121 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 12122 | |
| 12123 | if ((dpll & PLL_REF_INPUT_MASK(3 << 13)) == PLLB_REF_INPUT_SPREADSPECTRUMIN(3 << 13)) |
| 12124 | return dev_priv->vbt.lvds_ssc_freq; |
| 12125 | else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) |
| 12126 | return 120000; |
| 12127 | else if (!IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) |
| 12128 | return 96000; |
| 12129 | else |
| 12130 | return 48000; |
| 12131 | } |
| 12132 | |
| 12133 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
| 12134 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
| 12135 | struct intel_crtc_state *pipe_config) |
| 12136 | { |
| 12137 | struct drm_device *dev = crtc->base.dev; |
| 12138 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 12139 | enum pipe pipe = crtc->pipe; |
| 12140 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
| 12141 | u32 fp; |
| 12142 | struct dpll clock; |
| 12143 | int port_clock; |
| 12144 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
| 12145 | |
| 12146 | if ((dpll & DISPLAY_RATE_SELECT_FPA1(1 << 8)) == 0) |
| 12147 | fp = pipe_config->dpll_hw_state.fp0; |
| 12148 | else |
| 12149 | fp = pipe_config->dpll_hw_state.fp1; |
| 12150 | |
| 12151 | clock.m1 = (fp & FP_M1_DIV_MASK0x00003f00) >> FP_M1_DIV_SHIFT8; |
| 12152 | if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 12153 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK0x00ff0000) >> FP_N_DIV_SHIFT16) - 1; |
| 12154 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK0x000000ff) >> FP_M2_DIV_SHIFT0; |
| 12155 | } else { |
| 12156 | clock.n = (fp & FP_N_DIV_MASK0x003f0000) >> FP_N_DIV_SHIFT16; |
| 12157 | clock.m2 = (fp & FP_M2_DIV_MASK0x0000003f) >> FP_M2_DIV_SHIFT0; |
| 12158 | } |
| 12159 | |
| 12160 | if (!IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) { |
| 12161 | if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) |
| 12162 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW0x00ff8000) >> |
| 12163 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW15); |
| 12164 | else |
| 12165 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK0x00ff0000) >> |
| 12166 | DPLL_FPA01_P1_POST_DIV_SHIFT16); |
| 12167 | |
| 12168 | switch (dpll & DPLL_MODE_MASK(3 << 26)) { |
| 12169 | case DPLLB_MODE_DAC_SERIAL(1 << 26): |
| 12170 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5(1 << 24) ? |
| 12171 | 5 : 10; |
| 12172 | break; |
| 12173 | case DPLLB_MODE_LVDS(2 << 26): |
| 12174 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7(1 << 24) ? |
| 12175 | 7 : 14; |
| 12176 | break; |
| 12177 | default: |
| 12178 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unknown DPLL mode %08x in programmed " "mode\n", (int)(dpll & (3 << 26))) |
| 12179 | "Unknown DPLL mode %08x in programmed "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unknown DPLL mode %08x in programmed " "mode\n", (int)(dpll & (3 << 26))) |
| 12180 | "mode\n", (int)(dpll & DPLL_MODE_MASK))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Unknown DPLL mode %08x in programmed " "mode\n", (int)(dpll & (3 << 26))); |
| 12181 | return; |
| 12182 | } |
| 12183 | |
| 12184 | if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) |
| 12185 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
| 12186 | else |
| 12187 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
| 12188 | } else { |
| 12189 | u32 lvds = IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) ? 0 : intel_de_read(dev_priv, |
| 12190 | LVDS((const i915_reg_t){ .reg = (0x61180) })); |
| 12191 | bool_Bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN(1 << 31)); |
| 12192 | |
| 12193 | if (is_lvds) { |
| 12194 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS0x003f0000) >> |
| 12195 | DPLL_FPA01_P1_POST_DIV_SHIFT16); |
| 12196 | |
| 12197 | if (lvds & LVDS_CLKB_POWER_UP(3 << 4)) |
| 12198 | clock.p2 = 7; |
| 12199 | else |
| 12200 | clock.p2 = 14; |
| 12201 | } else { |
| 12202 | if (dpll & PLL_P1_DIVIDE_BY_TWO(1 << 21)) |
| 12203 | clock.p1 = 2; |
| 12204 | else { |
| 12205 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I8300x001f0000) >> |
| 12206 | DPLL_FPA01_P1_POST_DIV_SHIFT16) + 2; |
| 12207 | } |
| 12208 | if (dpll & PLL_P2_DIVIDE_BY_4(1 << 23)) |
| 12209 | clock.p2 = 4; |
| 12210 | else |
| 12211 | clock.p2 = 2; |
| 12212 | } |
| 12213 | |
| 12214 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
| 12215 | } |
| 12216 | |
| 12217 | /* |
| 12218 | * This value includes pixel_multiplier. We will use |
| 12219 | * port_clock to compute adjusted_mode.crtc_clock in the |
| 12220 | * encoder's get_config() function. |
| 12221 | */ |
| 12222 | pipe_config->port_clock = port_clock; |
| 12223 | } |
| 12224 | |
| 12225 | int intel_dotclock_calculate(int link_freq, |
| 12226 | const struct intel_link_m_n *m_n) |
| 12227 | { |
| 12228 | /* |
| 12229 | * The calculation for the data clock is: |
| 12230 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
| 12231 | * But we want to avoid losing precison if possible, so: |
| 12232 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
| 12233 | * |
| 12234 | * and the link clock is simpler: |
| 12235 | * link_clock = (m * link_clock) / n |
| 12236 | */ |
| 12237 | |
| 12238 | if (!m_n->link_n) |
| 12239 | return 0; |
| 12240 | |
| 12241 | return div_u64(mul_u32_u32(m_n->link_m, link_freq), m_n->link_n); |
| 12242 | } |
| 12243 | |
| 12244 | static void ilk_pch_clock_get(struct intel_crtc *crtc, |
| 12245 | struct intel_crtc_state *pipe_config) |
| 12246 | { |
| 12247 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12248 | |
| 12249 | /* read out port_clock from the DPLL */ |
| 12250 | i9xx_crtc_clock_get(crtc, pipe_config); |
| 12251 | |
| 12252 | /* |
| 12253 | * In case there is an active pipe without active ports, |
| 12254 | * we may need some idea for the dotclock anyway. |
| 12255 | * Calculate one based on the FDI configuration. |
| 12256 | */ |
| 12257 | pipe_config->hw.adjusted_mode.crtc_clock = |
| 12258 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
| 12259 | &pipe_config->fdi_m_n); |
| 12260 | } |
| 12261 | |
| 12262 | static void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, |
| 12263 | struct intel_crtc *crtc) |
| 12264 | { |
| 12265 | memset(crtc_state, 0, sizeof(*crtc_state))__builtin_memset((crtc_state), (0), (sizeof(*crtc_state))); |
| 12266 | |
| 12267 | __drm_atomic_helper_crtc_state_reset(&crtc_state->uapi, &crtc->base); |
| 12268 | |
| 12269 | crtc_state->cpu_transcoder = INVALID_TRANSCODER; |
| 12270 | crtc_state->master_transcoder = INVALID_TRANSCODER; |
| 12271 | crtc_state->hsw_workaround_pipe = INVALID_PIPE; |
| 12272 | crtc_state->output_format = INTEL_OUTPUT_FORMAT_INVALID; |
| 12273 | crtc_state->scaler_state.scaler_id = -1; |
| 12274 | crtc_state->mst_master_transcoder = INVALID_TRANSCODER; |
| 12275 | } |
| 12276 | |
| 12277 | static struct intel_crtc_state *intel_crtc_state_alloc(struct intel_crtc *crtc) |
| 12278 | { |
| 12279 | struct intel_crtc_state *crtc_state; |
| 12280 | |
| 12281 | crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL(0x0001 | 0x0004)); |
| 12282 | |
| 12283 | if (crtc_state) |
| 12284 | intel_crtc_state_reset(crtc_state, crtc); |
| 12285 | |
| 12286 | return crtc_state; |
| 12287 | } |
| 12288 | |
| 12289 | /* Returns the currently programmed mode of the given encoder. */ |
| 12290 | struct drm_display_mode * |
| 12291 | intel_encoder_current_mode(struct intel_encoder *encoder) |
| 12292 | { |
| 12293 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 12294 | struct intel_crtc_state *crtc_state; |
| 12295 | struct drm_display_mode *mode; |
| 12296 | struct intel_crtc *crtc; |
| 12297 | enum pipe pipe; |
| 12298 | |
| 12299 | if (!encoder->get_hw_state(encoder, &pipe)) |
| 12300 | return NULL((void *)0); |
| 12301 | |
| 12302 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 12303 | |
| 12304 | mode = kzalloc(sizeof(*mode), GFP_KERNEL(0x0001 | 0x0004)); |
| 12305 | if (!mode) |
| 12306 | return NULL((void *)0); |
| 12307 | |
| 12308 | crtc_state = intel_crtc_state_alloc(crtc); |
| 12309 | if (!crtc_state) { |
| 12310 | kfree(mode); |
| 12311 | return NULL((void *)0); |
| 12312 | } |
| 12313 | |
| 12314 | if (!dev_priv->display.get_pipe_config(crtc, crtc_state)) { |
| 12315 | kfree(crtc_state); |
| 12316 | kfree(mode); |
| 12317 | return NULL((void *)0); |
| 12318 | } |
| 12319 | |
| 12320 | encoder->get_config(encoder, crtc_state); |
| 12321 | |
| 12322 | intel_mode_from_pipe_config(mode, crtc_state); |
| 12323 | |
| 12324 | kfree(crtc_state); |
| 12325 | |
| 12326 | return mode; |
| 12327 | } |
| 12328 | |
| 12329 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
| 12330 | { |
| 12331 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}); |
| 12332 | |
| 12333 | drm_crtc_cleanup(crtc); |
| 12334 | kfree(intel_crtc); |
| 12335 | } |
| 12336 | |
| 12337 | /** |
| 12338 | * intel_wm_need_update - Check whether watermarks need updating |
| 12339 | * @cur: current plane state |
| 12340 | * @new: new plane state |
| 12341 | * |
| 12342 | * Check current plane state versus the new one to determine whether |
| 12343 | * watermarks need to be recalculated. |
| 12344 | * |
| 12345 | * Returns true or false. |
| 12346 | */ |
| 12347 | static bool_Bool intel_wm_need_update(const struct intel_plane_state *cur, |
| 12348 | struct intel_plane_state *new) |
| 12349 | { |
| 12350 | /* Update watermarks on tiling or size changes. */ |
| 12351 | if (new->uapi.visible != cur->uapi.visible) |
| 12352 | return true1; |
| 12353 | |
| 12354 | if (!cur->hw.fb || !new->hw.fb) |
| 12355 | return false0; |
| 12356 | |
| 12357 | if (cur->hw.fb->modifier != new->hw.fb->modifier || |
| 12358 | cur->hw.rotation != new->hw.rotation || |
| 12359 | drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) || |
| 12360 | drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) || |
| 12361 | drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) || |
| 12362 | drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst)) |
| 12363 | return true1; |
| 12364 | |
| 12365 | return false0; |
| 12366 | } |
| 12367 | |
| 12368 | static bool_Bool needs_scaling(const struct intel_plane_state *state) |
| 12369 | { |
| 12370 | int src_w = drm_rect_width(&state->uapi.src) >> 16; |
| 12371 | int src_h = drm_rect_height(&state->uapi.src) >> 16; |
| 12372 | int dst_w = drm_rect_width(&state->uapi.dst); |
| 12373 | int dst_h = drm_rect_height(&state->uapi.dst); |
| 12374 | |
| 12375 | return (src_w != dst_w || src_h != dst_h); |
| 12376 | } |
| 12377 | |
| 12378 | int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state, |
| 12379 | struct intel_crtc_state *crtc_state, |
| 12380 | const struct intel_plane_state *old_plane_state, |
| 12381 | struct intel_plane_state *plane_state) |
| 12382 | { |
| 12383 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 12384 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 12385 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12386 | bool_Bool mode_changed = needs_modeset(crtc_state); |
| 12387 | bool_Bool was_crtc_enabled = old_crtc_state->hw.active; |
| 12388 | bool_Bool is_crtc_enabled = crtc_state->hw.active; |
| 12389 | bool_Bool turn_off, turn_on, visible, was_visible; |
| 12390 | int ret; |
| 12391 | |
| 12392 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 && plane->id != PLANE_CURSOR) { |
| 12393 | ret = skl_update_scaler_plane(crtc_state, plane_state); |
| 12394 | if (ret) |
| 12395 | return ret; |
| 12396 | } |
| 12397 | |
| 12398 | was_visible = old_plane_state->uapi.visible; |
| 12399 | visible = plane_state->uapi.visible; |
| 12400 | |
| 12401 | if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible)({ int __ret = !!((was_visible)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "was_visible" ")"); __builtin_expect(!!(__ret ), 0); })) |
| 12402 | was_visible = false0; |
| 12403 | |
| 12404 | /* |
| 12405 | * Visibility is calculated as if the crtc was on, but |
| 12406 | * after scaler setup everything depends on it being off |
| 12407 | * when the crtc isn't active. |
| 12408 | * |
| 12409 | * FIXME this is wrong for watermarks. Watermarks should also |
| 12410 | * be computed as if the pipe would be active. Perhaps move |
| 12411 | * per-plane wm computation to the .check_plane() hook, and |
| 12412 | * only combine the results from all planes in the current place? |
| 12413 | */ |
| 12414 | if (!is_crtc_enabled) { |
| 12415 | intel_plane_set_invisible(crtc_state, plane_state); |
| 12416 | visible = false0; |
| 12417 | } |
| 12418 | |
| 12419 | if (!was_visible && !visible) |
| 12420 | return 0; |
| 12421 | |
| 12422 | turn_off = was_visible && (!visible || mode_changed); |
| 12423 | turn_on = visible && (!was_visible || mode_changed); |
| 12424 | |
| 12425 | drm_dbg_atomic(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n" , crtc->base.base.id, crtc->base.name, plane->base.base .id, plane->base.name, was_visible, visible, turn_off, turn_on , mode_changed) |
| 12426 | "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n" , crtc->base.base.id, crtc->base.name, plane->base.base .id, plane->base.name, was_visible, visible, turn_off, turn_on , mode_changed) |
| 12427 | crtc->base.base.id, crtc->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n" , crtc->base.base.id, crtc->base.name, plane->base.base .id, plane->base.name, was_visible, visible, turn_off, turn_on , mode_changed) |
| 12428 | plane->base.base.id, plane->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n" , crtc->base.base.id, crtc->base.name, plane->base.base .id, plane->base.name, was_visible, visible, turn_off, turn_on , mode_changed) |
| 12429 | was_visible, visible,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n" , crtc->base.base.id, crtc->base.name, plane->base.base .id, plane->base.name, was_visible, visible, turn_off, turn_on , mode_changed) |
| 12430 | turn_off, turn_on, mode_changed)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n" , crtc->base.base.id, crtc->base.name, plane->base.base .id, plane->base.name, was_visible, visible, turn_off, turn_on , mode_changed); |
| 12431 | |
| 12432 | if (turn_on) { |
| 12433 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5 && !IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 12434 | crtc_state->update_wm_pre = true1; |
| 12435 | |
| 12436 | /* must disable cxsr around plane enable/disable */ |
| 12437 | if (plane->id != PLANE_CURSOR) |
| 12438 | crtc_state->disable_cxsr = true1; |
| 12439 | } else if (turn_off) { |
| 12440 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5 && !IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 12441 | crtc_state->update_wm_post = true1; |
| 12442 | |
| 12443 | /* must disable cxsr around plane enable/disable */ |
| 12444 | if (plane->id != PLANE_CURSOR) |
| 12445 | crtc_state->disable_cxsr = true1; |
| 12446 | } else if (intel_wm_need_update(old_plane_state, plane_state)) { |
| 12447 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5 && !IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
| 12448 | /* FIXME bollocks */ |
| 12449 | crtc_state->update_wm_pre = true1; |
| 12450 | crtc_state->update_wm_post = true1; |
| 12451 | } |
| 12452 | } |
| 12453 | |
| 12454 | if (visible || was_visible) |
| 12455 | crtc_state->fb_bits |= plane->frontbuffer_bit; |
| 12456 | |
| 12457 | /* |
| 12458 | * ILK/SNB DVSACNTR/Sprite Enable |
| 12459 | * IVB SPR_CTL/Sprite Enable |
| 12460 | * "When in Self Refresh Big FIFO mode, a write to enable the |
| 12461 | * plane will be internally buffered and delayed while Big FIFO |
| 12462 | * mode is exiting." |
| 12463 | * |
| 12464 | * Which means that enabling the sprite can take an extra frame |
| 12465 | * when we start in big FIFO mode (LP1+). Thus we need to drop |
| 12466 | * down to LP0 and wait for vblank in order to make sure the |
| 12467 | * sprite gets enabled on the next vblank after the register write. |
| 12468 | * Doing otherwise would risk enabling the sprite one frame after |
| 12469 | * we've already signalled flip completion. We can resume LP1+ |
| 12470 | * once the sprite has been enabled. |
| 12471 | * |
| 12472 | * |
| 12473 | * WaCxSRDisabledForSpriteScaling:ivb |
| 12474 | * IVB SPR_SCALE/Scaling Enable |
| 12475 | * "Low Power watermarks must be disabled for at least one |
| 12476 | * frame before enabling sprite scaling, and kept disabled |
| 12477 | * until sprite scaling is disabled." |
| 12478 | * |
| 12479 | * ILK/SNB DVSASCALE/Scaling Enable |
| 12480 | * "When in Self Refresh Big FIFO mode, scaling enable will be |
| 12481 | * masked off while Big FIFO mode is exiting." |
| 12482 | * |
| 12483 | * Despite the w/a only being listed for IVB we assume that |
| 12484 | * the ILK/SNB note has similar ramifications, hence we apply |
| 12485 | * the w/a on all three platforms. |
| 12486 | * |
| 12487 | * With experimental results seems this is needed also for primary |
| 12488 | * plane, not only sprite plane. |
| 12489 | */ |
| 12490 | if (plane->id != PLANE_CURSOR && |
| 12491 | (IS_GEN_RANGE(dev_priv, 5, 6)(!!((&(dev_priv)->__info)->gen_mask & ( 0 + 0 + (((~0UL) >> (64 - (((6)) - 1) - 1)) & ((~0UL) << (((5)) - 1)))))) || |
| 12492 | IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) && |
| 12493 | (turn_on || (!needs_scaling(old_plane_state) && |
| 12494 | needs_scaling(plane_state)))) |
| 12495 | crtc_state->disable_lp_wm = true1; |
| 12496 | |
| 12497 | return 0; |
| 12498 | } |
| 12499 | |
| 12500 | static bool_Bool encoders_cloneable(const struct intel_encoder *a, |
| 12501 | const struct intel_encoder *b) |
| 12502 | { |
| 12503 | /* masks could be asymmetric, so check both ways */ |
| 12504 | return a == b || (a->cloneable & (1 << b->type) && |
| 12505 | b->cloneable & (1 << a->type)); |
| 12506 | } |
| 12507 | |
| 12508 | static bool_Bool check_single_encoder_cloning(struct drm_atomic_state *state, |
| 12509 | struct intel_crtc *crtc, |
| 12510 | struct intel_encoder *encoder) |
| 12511 | { |
| 12512 | struct intel_encoder *source_encoder; |
| 12513 | struct drm_connector *connector; |
| 12514 | struct drm_connector_state *connector_state; |
| 12515 | int i; |
| 12516 | |
| 12517 | for_each_new_connector_in_state(state, connector, connector_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if ( !((state)->connectors[i].ptr && ((connector) = (state )->connectors[i].ptr, (void)(connector) , (connector_state ) = (state)->connectors[i].new_state, (void)(connector_state ) , 1))) {} else { |
| 12518 | if (connector_state->crtc != &crtc->base) |
| 12519 | continue; |
| 12520 | |
| 12521 | source_encoder = |
| 12522 | to_intel_encoder(connector_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (connector_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 12523 | if (!encoders_cloneable(encoder, source_encoder)) |
| 12524 | return false0; |
| 12525 | } |
| 12526 | |
| 12527 | return true1; |
| 12528 | } |
| 12529 | |
| 12530 | static int icl_add_linked_planes(struct intel_atomic_state *state) |
| 12531 | { |
| 12532 | struct intel_plane *plane, *linked; |
| 12533 | struct intel_plane_state *plane_state, *linked_plane_state; |
| 12534 | int i; |
| 12535 | |
| 12536 | for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else { |
| 12537 | linked = plane_state->planar_linked_plane; |
| 12538 | |
| 12539 | if (!linked) |
| 12540 | continue; |
| 12541 | |
| 12542 | linked_plane_state = intel_atomic_get_plane_state(state, linked); |
| 12543 | if (IS_ERR(linked_plane_state)) |
| 12544 | return PTR_ERR(linked_plane_state); |
| 12545 | |
| 12546 | drm_WARN_ON(state->base.dev,({ int __ret = !!((linked_plane_state->planar_linked_plane != plane)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((state->base.dev))->dev), "", "drm_WARN_ON(" "linked_plane_state->planar_linked_plane != plane" ")"); __builtin_expect(!!(__ret), 0); }) |
| 12547 | linked_plane_state->planar_linked_plane != plane)({ int __ret = !!((linked_plane_state->planar_linked_plane != plane)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((state->base.dev))->dev), "", "drm_WARN_ON(" "linked_plane_state->planar_linked_plane != plane" ")"); __builtin_expect(!!(__ret), 0); }); |
| 12548 | drm_WARN_ON(state->base.dev,({ int __ret = !!((linked_plane_state->planar_slave == plane_state ->planar_slave)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((state->base.dev))->dev), "", "drm_WARN_ON(" "linked_plane_state->planar_slave == plane_state->planar_slave" ")"); __builtin_expect(!!(__ret), 0); }) |
| 12549 | linked_plane_state->planar_slave == plane_state->planar_slave)({ int __ret = !!((linked_plane_state->planar_slave == plane_state ->planar_slave)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((state->base.dev))->dev), "", "drm_WARN_ON(" "linked_plane_state->planar_slave == plane_state->planar_slave" ")"); __builtin_expect(!!(__ret), 0); }); |
| 12550 | } |
| 12551 | |
| 12552 | return 0; |
| 12553 | } |
| 12554 | |
| 12555 | static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) |
| 12556 | { |
| 12557 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 12558 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12559 | struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 12560 | struct intel_plane *plane, *linked; |
| 12561 | struct intel_plane_state *plane_state; |
| 12562 | int i; |
| 12563 | |
| 12564 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 11) |
| 12565 | return 0; |
| 12566 | |
| 12567 | /* |
| 12568 | * Destroy all old plane links and make the slave plane invisible |
| 12569 | * in the crtc_state->active_planes mask. |
| 12570 | */ |
| 12571 | for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else { |
| 12572 | if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane) |
| 12573 | continue; |
| 12574 | |
| 12575 | plane_state->planar_linked_plane = NULL((void *)0); |
| 12576 | if (plane_state->planar_slave && !plane_state->uapi.visible) { |
| 12577 | crtc_state->active_planes &= ~BIT(plane->id)(1UL << (plane->id)); |
| 12578 | crtc_state->update_planes |= BIT(plane->id)(1UL << (plane->id)); |
| 12579 | } |
| 12580 | |
| 12581 | plane_state->planar_slave = false0; |
| 12582 | } |
| 12583 | |
| 12584 | if (!crtc_state->nv12_planes) |
| 12585 | return 0; |
| 12586 | |
| 12587 | for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else { |
| 12588 | struct intel_plane_state *linked_state = NULL((void *)0); |
| 12589 | |
| 12590 | if (plane->pipe != crtc->pipe || |
| 12591 | !(crtc_state->nv12_planes & BIT(plane->id)(1UL << (plane->id)))) |
| 12592 | continue; |
| 12593 | |
| 12594 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked)for (linked = ({ const __typeof( ((__typeof(*linked) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*linked) *)( (char *)__mptr - __builtin_offsetof(__typeof(*linked), base.head) );}); & linked->base.head != (&(&dev_priv->drm)->mode_config .plane_list); linked = ({ const __typeof( ((__typeof(*linked) *)0)->base.head ) *__mptr = (linked->base.head.next); ( __typeof(*linked) *)( (char *)__mptr - __builtin_offsetof(__typeof (*linked), base.head) );})) if (!((linked)->pipe == (crtc) ->pipe)) {} else { |
| 12595 | if (!icl_is_nv12_y_plane(dev_priv, linked->id)) |
| 12596 | continue; |
| 12597 | |
| 12598 | if (crtc_state->active_planes & BIT(linked->id)(1UL << (linked->id))) |
| 12599 | continue; |
| 12600 | |
| 12601 | linked_state = intel_atomic_get_plane_state(state, linked); |
| 12602 | if (IS_ERR(linked_state)) |
| 12603 | return PTR_ERR(linked_state); |
| 12604 | |
| 12605 | break; |
| 12606 | } |
| 12607 | |
| 12608 | if (!linked_state) { |
| 12609 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Need %d free Y planes for planar YUV\n" , hweight8(crtc_state->nv12_planes)) |
| 12610 | "Need %d free Y planes for planar YUV\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Need %d free Y planes for planar YUV\n" , hweight8(crtc_state->nv12_planes)) |
| 12611 | hweight8(crtc_state->nv12_planes))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Need %d free Y planes for planar YUV\n" , hweight8(crtc_state->nv12_planes)); |
| 12612 | |
| 12613 | return -EINVAL22; |
| 12614 | } |
| 12615 | |
| 12616 | plane_state->planar_linked_plane = linked; |
| 12617 | |
| 12618 | linked_state->planar_slave = true1; |
| 12619 | linked_state->planar_linked_plane = plane; |
| 12620 | crtc_state->active_planes |= BIT(linked->id)(1UL << (linked->id)); |
| 12621 | crtc_state->update_planes |= BIT(linked->id)(1UL << (linked->id)); |
| 12622 | drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using %s as Y plane for %s\n" , linked->base.name, plane->base.name) |
| 12623 | linked->base.name, plane->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Using %s as Y plane for %s\n" , linked->base.name, plane->base.name); |
| 12624 | |
| 12625 | /* Copy parameters to slave plane */ |
| 12626 | linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE(1 << 19); |
| 12627 | linked_state->color_ctl = plane_state->color_ctl; |
| 12628 | linked_state->view = plane_state->view; |
| 12629 | memcpy(linked_state->color_plane, plane_state->color_plane,__builtin_memcpy((linked_state->color_plane), (plane_state ->color_plane), (sizeof(linked_state->color_plane))) |
| 12630 | sizeof(linked_state->color_plane))__builtin_memcpy((linked_state->color_plane), (plane_state ->color_plane), (sizeof(linked_state->color_plane))); |
| 12631 | |
| 12632 | intel_plane_copy_uapi_to_hw_state(linked_state, plane_state); |
| 12633 | linked_state->uapi.src = plane_state->uapi.src; |
| 12634 | linked_state->uapi.dst = plane_state->uapi.dst; |
| 12635 | |
| 12636 | if (icl_is_hdr_plane(dev_priv, plane->id)) { |
| 12637 | if (linked->id == PLANE_SPRITE5) |
| 12638 | plane_state->cus_ctl |= PLANE_CUS_PLANE_7(1 << 30); |
| 12639 | else if (linked->id == PLANE_SPRITE4) |
| 12640 | plane_state->cus_ctl |= PLANE_CUS_PLANE_6(0 << 30); |
| 12641 | else if (linked->id == PLANE_SPRITE3) |
| 12642 | plane_state->cus_ctl |= PLANE_CUS_PLANE_5_RKL(1 << 30); |
| 12643 | else if (linked->id == PLANE_SPRITE2) |
| 12644 | plane_state->cus_ctl |= PLANE_CUS_PLANE_4_RKL(0 << 30); |
| 12645 | else |
| 12646 | MISSING_CASE(linked->id)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "linked->id", (long)(linked->id)); __builtin_expect(! !(__ret), 0); }); |
| 12647 | } |
| 12648 | } |
| 12649 | |
| 12650 | return 0; |
| 12651 | } |
| 12652 | |
| 12653 | static bool_Bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) |
| 12654 | { |
| 12655 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 12656 | struct intel_atomic_state *state = |
| 12657 | to_intel_atomic_state(new_crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (new_crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 12658 | const struct intel_crtc_state *old_crtc_state = |
| 12659 | intel_atomic_get_old_crtc_state(state, crtc); |
| 12660 | |
| 12661 | return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; |
| 12662 | } |
| 12663 | |
| 12664 | static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) |
| 12665 | { |
| 12666 | const struct drm_display_mode *adjusted_mode = |
| 12667 | &crtc_state->hw.adjusted_mode; |
| 12668 | int linetime_wm; |
| 12669 | |
| 12670 | if (!crtc_state->hw.enable) |
| 12671 | return 0; |
| 12672 | |
| 12673 | linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,(((adjusted_mode->crtc_htotal * 1000 * 8) + ((adjusted_mode ->crtc_clock) / 2)) / (adjusted_mode->crtc_clock)) |
| 12674 | adjusted_mode->crtc_clock)(((adjusted_mode->crtc_htotal * 1000 * 8) + ((adjusted_mode ->crtc_clock) / 2)) / (adjusted_mode->crtc_clock)); |
| 12675 | |
| 12676 | return min(linetime_wm, 0x1ff)(((linetime_wm)<(0x1ff))?(linetime_wm):(0x1ff)); |
| 12677 | } |
| 12678 | |
| 12679 | static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state, |
| 12680 | const struct intel_cdclk_state *cdclk_state) |
| 12681 | { |
| 12682 | const struct drm_display_mode *adjusted_mode = |
| 12683 | &crtc_state->hw.adjusted_mode; |
| 12684 | int linetime_wm; |
| 12685 | |
| 12686 | if (!crtc_state->hw.enable) |
| 12687 | return 0; |
| 12688 | |
| 12689 | linetime_wm = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,(((adjusted_mode->crtc_htotal * 1000 * 8) + ((cdclk_state-> logical.cdclk) / 2)) / (cdclk_state->logical.cdclk)) |
| 12690 | cdclk_state->logical.cdclk)(((adjusted_mode->crtc_htotal * 1000 * 8) + ((cdclk_state-> logical.cdclk) / 2)) / (cdclk_state->logical.cdclk)); |
| 12691 | |
| 12692 | return min(linetime_wm, 0x1ff)(((linetime_wm)<(0x1ff))?(linetime_wm):(0x1ff)); |
| 12693 | } |
| 12694 | |
| 12695 | static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state) |
| 12696 | { |
| 12697 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 12698 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12699 | const struct drm_display_mode *adjusted_mode = |
| 12700 | &crtc_state->hw.adjusted_mode; |
| 12701 | int linetime_wm; |
| 12702 | |
| 12703 | if (!crtc_state->hw.enable) |
| 12704 | return 0; |
| 12705 | |
| 12706 | linetime_wm = DIV_ROUND_UP(adjusted_mode->crtc_htotal * 1000 * 8,(((adjusted_mode->crtc_htotal * 1000 * 8) + ((crtc_state-> pixel_rate) - 1)) / (crtc_state->pixel_rate)) |
| 12707 | crtc_state->pixel_rate)(((adjusted_mode->crtc_htotal * 1000 * 8) + ((crtc_state-> pixel_rate) - 1)) / (crtc_state->pixel_rate)); |
| 12708 | |
| 12709 | /* Display WA #1135: BXT:ALL GLK:ALL */ |
| 12710 | if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp)) && dev_priv->ipc_enabled) |
| 12711 | linetime_wm /= 2; |
| 12712 | |
| 12713 | return min(linetime_wm, 0x1ff)(((linetime_wm)<(0x1ff))?(linetime_wm):(0x1ff)); |
| 12714 | } |
| 12715 | |
| 12716 | static int hsw_compute_linetime_wm(struct intel_atomic_state *state, |
| 12717 | struct intel_crtc *crtc) |
| 12718 | { |
| 12719 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12720 | struct intel_crtc_state *crtc_state = |
| 12721 | intel_atomic_get_new_crtc_state(state, crtc); |
| 12722 | const struct intel_cdclk_state *cdclk_state; |
| 12723 | |
| 12724 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 12725 | crtc_state->linetime = skl_linetime_wm(crtc_state); |
| 12726 | else |
| 12727 | crtc_state->linetime = hsw_linetime_wm(crtc_state); |
| 12728 | |
| 12729 | if (!hsw_crtc_supports_ips(crtc)) |
| 12730 | return 0; |
| 12731 | |
| 12732 | cdclk_state = intel_atomic_get_cdclk_state(state); |
| 12733 | if (IS_ERR(cdclk_state)) |
| 12734 | return PTR_ERR(cdclk_state); |
| 12735 | |
| 12736 | crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state, |
| 12737 | cdclk_state); |
| 12738 | |
| 12739 | return 0; |
| 12740 | } |
| 12741 | |
| 12742 | static int intel_crtc_atomic_check(struct intel_atomic_state *state, |
| 12743 | struct intel_crtc *crtc) |
| 12744 | { |
| 12745 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12746 | struct intel_crtc_state *crtc_state = |
| 12747 | intel_atomic_get_new_crtc_state(state, crtc); |
| 12748 | bool_Bool mode_changed = needs_modeset(crtc_state); |
| 12749 | int ret; |
| 12750 | |
| 12751 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 5 && !IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) && |
| 12752 | mode_changed && !crtc_state->hw.active) |
| 12753 | crtc_state->update_wm_post = true1; |
| 12754 | |
| 12755 | if (mode_changed && crtc_state->hw.enable && |
| 12756 | dev_priv->display.crtc_compute_clock && |
| 12757 | !drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll)({ int __ret = !!((crtc_state->shared_dpll)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "crtc_state->shared_dpll" ")"); __builtin_expect (!!(__ret), 0); })) { |
| 12758 | ret = dev_priv->display.crtc_compute_clock(crtc, crtc_state); |
| 12759 | if (ret) |
| 12760 | return ret; |
| 12761 | } |
| 12762 | |
| 12763 | /* |
| 12764 | * May need to update pipe gamma enable bits |
| 12765 | * when C8 planes are getting enabled/disabled. |
| 12766 | */ |
| 12767 | if (c8_planes_changed(crtc_state)) |
| 12768 | crtc_state->uapi.color_mgmt_changed = true1; |
| 12769 | |
| 12770 | if (mode_changed || crtc_state->update_pipe || |
| 12771 | crtc_state->uapi.color_mgmt_changed) { |
| 12772 | ret = intel_color_check(crtc_state); |
| 12773 | if (ret) |
| 12774 | return ret; |
| 12775 | } |
| 12776 | |
| 12777 | if (dev_priv->display.compute_pipe_wm) { |
| 12778 | ret = dev_priv->display.compute_pipe_wm(crtc_state); |
| 12779 | if (ret) { |
| 12780 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Target pipe watermarks are invalid\n" ) |
| 12781 | "Target pipe watermarks are invalid\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Target pipe watermarks are invalid\n" ); |
| 12782 | return ret; |
| 12783 | } |
| 12784 | } |
| 12785 | |
| 12786 | if (dev_priv->display.compute_intermediate_wm) { |
| 12787 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((!dev_priv->display.compute_pipe_wm)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "!dev_priv->display.compute_pipe_wm" ")"); __builtin_expect(!!(__ret), 0); }) |
| 12788 | !dev_priv->display.compute_pipe_wm)({ int __ret = !!((!dev_priv->display.compute_pipe_wm)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "!dev_priv->display.compute_pipe_wm" ")"); __builtin_expect(!!(__ret), 0); })) |
| 12789 | return 0; |
| 12790 | |
| 12791 | /* |
| 12792 | * Calculate 'intermediate' watermarks that satisfy both the |
| 12793 | * old state and the new state. We can program these |
| 12794 | * immediately. |
| 12795 | */ |
| 12796 | ret = dev_priv->display.compute_intermediate_wm(crtc_state); |
| 12797 | if (ret) { |
| 12798 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No valid intermediate pipe watermarks are possible\n" ) |
| 12799 | "No valid intermediate pipe watermarks are possible\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No valid intermediate pipe watermarks are possible\n" ); |
| 12800 | return ret; |
| 12801 | } |
| 12802 | } |
| 12803 | |
| 12804 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) { |
| 12805 | if (mode_changed || crtc_state->update_pipe) { |
| 12806 | ret = skl_update_scaler_crtc(crtc_state); |
| 12807 | if (ret) |
| 12808 | return ret; |
| 12809 | } |
| 12810 | |
| 12811 | ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state); |
| 12812 | if (ret) |
| 12813 | return ret; |
| 12814 | } |
| 12815 | |
| 12816 | if (HAS_IPS(dev_priv)(IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0)) || IS_PLATFORM( dev_priv, INTEL_BROADWELL))) { |
| 12817 | ret = hsw_compute_ips_config(crtc_state); |
| 12818 | if (ret) |
| 12819 | return ret; |
| 12820 | } |
| 12821 | |
| 12822 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || |
| 12823 | IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) { |
| 12824 | ret = hsw_compute_linetime_wm(state, crtc); |
| 12825 | if (ret) |
| 12826 | return ret; |
| 12827 | |
| 12828 | } |
| 12829 | |
| 12830 | if (!mode_changed) |
| 12831 | intel_psr2_sel_fetch_update(state, crtc); |
| 12832 | |
| 12833 | return 0; |
| 12834 | } |
| 12835 | |
| 12836 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
| 12837 | { |
| 12838 | struct intel_connector *connector; |
| 12839 | struct drm_connector_list_iter conn_iter; |
| 12840 | |
| 12841 | drm_connector_list_iter_begin(dev, &conn_iter); |
| 12842 | for_each_intel_connector_iter(connector, &conn_iter)while ((connector = ({ const __typeof( ((struct intel_connector *)0)->base ) *__mptr = (drm_connector_list_iter_next(& conn_iter)); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof (struct intel_connector, base) );}))) { |
| 12843 | if (connector->base.state->crtc) |
| 12844 | drm_connector_put(&connector->base); |
| 12845 | |
| 12846 | if (connector->base.encoder) { |
| 12847 | connector->base.state->best_encoder = |
| 12848 | connector->base.encoder; |
| 12849 | connector->base.state->crtc = |
| 12850 | connector->base.encoder->crtc; |
| 12851 | |
| 12852 | drm_connector_get(&connector->base); |
| 12853 | } else { |
| 12854 | connector->base.state->best_encoder = NULL((void *)0); |
| 12855 | connector->base.state->crtc = NULL((void *)0); |
| 12856 | } |
| 12857 | } |
| 12858 | drm_connector_list_iter_end(&conn_iter); |
| 12859 | } |
| 12860 | |
| 12861 | static int |
| 12862 | compute_sink_pipe_bpp(const struct drm_connector_state *conn_state, |
| 12863 | struct intel_crtc_state *pipe_config) |
| 12864 | { |
| 12865 | struct drm_connector *connector = conn_state->connector; |
| 12866 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(pipe_config->uapi.crtc->dev); |
| 12867 | const struct drm_display_info *info = &connector->display_info; |
| 12868 | int bpp; |
| 12869 | |
| 12870 | switch (conn_state->max_bpc) { |
| 12871 | case 6 ... 7: |
| 12872 | bpp = 6 * 3; |
| 12873 | break; |
| 12874 | case 8 ... 9: |
| 12875 | bpp = 8 * 3; |
| 12876 | break; |
| 12877 | case 10 ... 11: |
| 12878 | bpp = 10 * 3; |
| 12879 | break; |
| 12880 | case 12 ... 16: |
| 12881 | bpp = 12 * 3; |
| 12882 | break; |
| 12883 | default: |
| 12884 | MISSING_CASE(conn_state->max_bpc)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "conn_state->max_bpc", (long)(conn_state->max_bpc)); __builtin_expect (!!(__ret), 0); }); |
| 12885 | return -EINVAL22; |
| 12886 | } |
| 12887 | |
| 12888 | if (bpp < pipe_config->pipe_bpp) { |
| 12889 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp) |
| 12890 | "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp) |
| 12891 | "EDID bpp %d, requested bpp %d, max platform bpp %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp) |
| 12892 | connector->base.id, connector->name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp) |
| 12893 | bpp, 3 * info->bpc,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp) |
| 12894 | 3 * conn_state->max_requested_bpc,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp) |
| 12895 | pipe_config->pipe_bpp)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of " "EDID bpp %d, requested bpp %d, max platform bpp %d\n", connector ->base.id, connector->name, bpp, 3 * info->bpc, 3 * conn_state ->max_requested_bpc, pipe_config->pipe_bpp); |
| 12896 | |
| 12897 | pipe_config->pipe_bpp = bpp; |
| 12898 | } |
| 12899 | |
| 12900 | return 0; |
| 12901 | } |
| 12902 | |
| 12903 | static int |
| 12904 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
| 12905 | struct intel_crtc_state *pipe_config) |
| 12906 | { |
| 12907 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 12908 | struct drm_atomic_state *state = pipe_config->uapi.state; |
| 12909 | struct drm_connector *connector; |
| 12910 | struct drm_connector_state *connector_state; |
| 12911 | int bpp, i; |
| 12912 | |
| 12913 | if ((IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || |
| 12914 | IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))) |
| 12915 | bpp = 10*3; |
| 12916 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) |
| 12917 | bpp = 12*3; |
| 12918 | else |
| 12919 | bpp = 8*3; |
| 12920 | |
| 12921 | pipe_config->pipe_bpp = bpp; |
| 12922 | |
| 12923 | /* Clamp display bpp to connector max bpp */ |
| 12924 | for_each_new_connector_in_state(state, connector, connector_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if ( !((state)->connectors[i].ptr && ((connector) = (state )->connectors[i].ptr, (void)(connector) , (connector_state ) = (state)->connectors[i].new_state, (void)(connector_state ) , 1))) {} else { |
| 12925 | int ret; |
| 12926 | |
| 12927 | if (connector_state->crtc != &crtc->base) |
| 12928 | continue; |
| 12929 | |
| 12930 | ret = compute_sink_pipe_bpp(connector_state, pipe_config); |
| 12931 | if (ret) |
| 12932 | return ret; |
| 12933 | } |
| 12934 | |
| 12935 | return 0; |
| 12936 | } |
| 12937 | |
| 12938 | static void intel_dump_crtc_timings(struct drm_i915_privateinteldrm_softc *i915, |
| 12939 | const struct drm_display_mode *mode) |
| 12940 | { |
| 12941 | drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12942 | "type: 0x%x flags: 0x%x\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12943 | mode->crtc_clock,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12944 | mode->crtc_hdisplay, mode->crtc_hsync_start,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12945 | mode->crtc_hsync_end, mode->crtc_htotal,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12946 | mode->crtc_vdisplay, mode->crtc_vsync_start,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12947 | mode->crtc_vsync_end, mode->crtc_vtotal,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags) |
| 12948 | mode->type, mode->flags)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "crtc timings: %d %d %d %d %d %d %d %d %d, " "type: 0x%x flags: 0x%x\n", mode->crtc_clock, mode->crtc_hdisplay , mode->crtc_hsync_start, mode->crtc_hsync_end, mode-> crtc_htotal, mode->crtc_vdisplay, mode->crtc_vsync_start , mode->crtc_vsync_end, mode->crtc_vtotal, mode->type , mode->flags); |
| 12949 | } |
| 12950 | |
| 12951 | static void |
| 12952 | intel_dump_m_n_config(const struct intel_crtc_state *pipe_config, |
| 12953 | const char *id, unsigned int lane_count, |
| 12954 | const struct intel_link_m_n *m_n) |
| 12955 | { |
| 12956 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(pipe_config->uapi.crtc->dev); |
| 12957 | |
| 12958 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , id, lane_count, m_n->gmch_m, m_n->gmch_n, m_n->link_m , m_n->link_n, m_n->tu) |
| 12959 | "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , id, lane_count, m_n->gmch_m, m_n->gmch_n, m_n->link_m , m_n->link_n, m_n->tu) |
| 12960 | id, lane_count,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , id, lane_count, m_n->gmch_m, m_n->gmch_n, m_n->link_m , m_n->link_n, m_n->tu) |
| 12961 | m_n->gmch_m, m_n->gmch_n,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , id, lane_count, m_n->gmch_m, m_n->gmch_n, m_n->link_m , m_n->link_n, m_n->tu) |
| 12962 | m_n->link_m, m_n->link_n, m_n->tu)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n" , id, lane_count, m_n->gmch_m, m_n->gmch_n, m_n->link_m , m_n->link_n, m_n->tu); |
| 12963 | } |
| 12964 | |
| 12965 | static void |
| 12966 | intel_dump_infoframe(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 12967 | const union hdmi_infoframe *frame) |
| 12968 | { |
| 12969 | if (!drm_debug_enabled(DRM_UT_KMS)) |
| 12970 | return; |
| 12971 | |
| 12972 | hdmi_infoframe_log(KERN_DEBUG"\0017", dev_priv->drm.dev, frame); |
| 12973 | } |
| 12974 | |
| 12975 | static void |
| 12976 | intel_dump_dp_vsc_sdp(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 12977 | const struct drm_dp_vsc_sdp *vsc) |
| 12978 | { |
| 12979 | if (!drm_debug_enabled(DRM_UT_KMS)) |
| 12980 | return; |
| 12981 | |
| 12982 | drm_dp_vsc_sdp_log(KERN_DEBUG"\0017", dev_priv->drm.dev, vsc); |
| 12983 | } |
| 12984 | |
| 12985 | #define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x |
| 12986 | |
| 12987 | static const char * const output_type_str[] = { |
| 12988 | OUTPUT_TYPE(UNUSED), |
| 12989 | OUTPUT_TYPE(ANALOG), |
| 12990 | OUTPUT_TYPE(DVO), |
| 12991 | OUTPUT_TYPE(SDVO), |
| 12992 | OUTPUT_TYPE(LVDS((const i915_reg_t){ .reg = (0x61180) })), |
| 12993 | OUTPUT_TYPE(TVOUT), |
| 12994 | OUTPUT_TYPE(HDMI), |
| 12995 | OUTPUT_TYPE(DP), |
| 12996 | OUTPUT_TYPE(EDP), |
| 12997 | OUTPUT_TYPE(DSI), |
| 12998 | OUTPUT_TYPE(DDI), |
| 12999 | OUTPUT_TYPE(DP_MST), |
| 13000 | }; |
| 13001 | |
| 13002 | #undef OUTPUT_TYPE |
| 13003 | |
| 13004 | static void snprintf_output_types(char *buf, size_t len, |
| 13005 | unsigned int output_types) |
| 13006 | { |
| 13007 | char *str = buf; |
| 13008 | int i; |
| 13009 | |
| 13010 | str[0] = '\0'; |
| 13011 | |
| 13012 | for (i = 0; i < ARRAY_SIZE(output_type_str)(sizeof((output_type_str)) / sizeof((output_type_str)[0])); i++) { |
| 13013 | int r; |
| 13014 | |
| 13015 | if ((output_types & BIT(i)(1UL << (i))) == 0) |
| 13016 | continue; |
| 13017 | |
| 13018 | r = snprintf(str, len, "%s%s", |
| 13019 | str != buf ? "," : "", output_type_str[i]); |
| 13020 | if (r >= len) |
| 13021 | break; |
| 13022 | str += r; |
| 13023 | len -= r; |
| 13024 | |
| 13025 | output_types &= ~BIT(i)(1UL << (i)); |
| 13026 | } |
| 13027 | |
| 13028 | WARN_ON_ONCE(output_types != 0)({ static int __warned; int __ret = !!((output_types != 0)); if (__ret && !__warned) { printf("%s", "WARN_ON_ONCE(" "output_types != 0" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); }); |
| 13029 | } |
| 13030 | |
| 13031 | static const char * const output_format_str[] = { |
| 13032 | [INTEL_OUTPUT_FORMAT_INVALID] = "Invalid", |
| 13033 | [INTEL_OUTPUT_FORMAT_RGB] = "RGB", |
| 13034 | [INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0", |
| 13035 | [INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4", |
| 13036 | }; |
| 13037 | |
| 13038 | static const char *output_formats(enum intel_output_format format) |
| 13039 | { |
| 13040 | if (format >= ARRAY_SIZE(output_format_str)(sizeof((output_format_str)) / sizeof((output_format_str)[0]) )) |
| 13041 | format = INTEL_OUTPUT_FORMAT_INVALID; |
| 13042 | return output_format_str[format]; |
| 13043 | } |
| 13044 | |
| 13045 | static void intel_dump_plane_state(const struct intel_plane_state *plane_state) |
| 13046 | { |
| 13047 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 13048 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(plane->base.dev); |
| 13049 | const struct drm_framebuffer *fb = plane_state->hw.fb; |
| 13050 | struct drm_format_name_buf format_name; |
| 13051 | |
| 13052 | if (!fb) { |
| 13053 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n" , plane->base.base.id, plane->base.name, yesno(plane_state ->uapi.visible)) |
| 13054 | "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n" , plane->base.base.id, plane->base.name, yesno(plane_state ->uapi.visible)) |
| 13055 | plane->base.base.id, plane->base.name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n" , plane->base.base.id, plane->base.name, yesno(plane_state ->uapi.visible)) |
| 13056 | yesno(plane_state->uapi.visible))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [NOFB], visible: %s\n" , plane->base.base.id, plane->base.name, yesno(plane_state ->uapi.visible)); |
| 13057 | return; |
| 13058 | } |
| 13059 | |
| 13060 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n" , plane->base.base.id, plane->base.name, fb->base.id , fb->width, fb->height, drm_get_format_name(fb->format ->format, &format_name), yesno(plane_state->uapi.visible )) |
| 13061 | "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n" , plane->base.base.id, plane->base.name, fb->base.id , fb->width, fb->height, drm_get_format_name(fb->format ->format, &format_name), yesno(plane_state->uapi.visible )) |
| 13062 | plane->base.base.id, plane->base.name,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n" , plane->base.base.id, plane->base.name, fb->base.id , fb->width, fb->height, drm_get_format_name(fb->format ->format, &format_name), yesno(plane_state->uapi.visible )) |
| 13063 | fb->base.id, fb->width, fb->height,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n" , plane->base.base.id, plane->base.name, fb->base.id , fb->width, fb->height, drm_get_format_name(fb->format ->format, &format_name), yesno(plane_state->uapi.visible )) |
| 13064 | drm_get_format_name(fb->format->format, &format_name),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n" , plane->base.base.id, plane->base.name, fb->base.id , fb->width, fb->height, drm_get_format_name(fb->format ->format, &format_name), yesno(plane_state->uapi.visible )) |
| 13065 | yesno(plane_state->uapi.visible))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %s, visible: %s\n" , plane->base.base.id, plane->base.name, fb->base.id , fb->width, fb->height, drm_get_format_name(fb->format ->format, &format_name), yesno(plane_state->uapi.visible )); |
| 13066 | drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\trotation: 0x%x, scaler: %d\n" , plane_state->hw.rotation, plane_state->scaler_id) |
| 13067 | plane_state->hw.rotation, plane_state->scaler_id)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\trotation: 0x%x, scaler: %d\n" , plane_state->hw.rotation, plane_state->scaler_id); |
| 13068 | if (plane_state->uapi.visible) |
| 13069 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tsrc: " "%d.%06ux%d.%06u%+d.%06u%+d.%06u" " dst: " "%dx%d%+d%+d" "\n" , drm_rect_width(&plane_state->uapi.src) >> 16, ( (drm_rect_width(&plane_state->uapi.src) & 0xffff) * 15625) >> 10, drm_rect_height(&plane_state->uapi .src) >> 16, ((drm_rect_height(&plane_state->uapi .src) & 0xffff) * 15625) >> 10, (&plane_state-> uapi.src)->x1 >> 16, (((&plane_state->uapi.src )->x1 & 0xffff) * 15625) >> 10, (&plane_state ->uapi.src)->y1 >> 16, (((&plane_state->uapi .src)->y1 & 0xffff) * 15625) >> 10, drm_rect_width (&plane_state->uapi.dst), drm_rect_height(&plane_state ->uapi.dst), (&plane_state->uapi.dst)->x1, (& plane_state->uapi.dst)->y1) |
| 13070 | "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tsrc: " "%d.%06ux%d.%06u%+d.%06u%+d.%06u" " dst: " "%dx%d%+d%+d" "\n" , drm_rect_width(&plane_state->uapi.src) >> 16, ( (drm_rect_width(&plane_state->uapi.src) & 0xffff) * 15625) >> 10, drm_rect_height(&plane_state->uapi .src) >> 16, ((drm_rect_height(&plane_state->uapi .src) & 0xffff) * 15625) >> 10, (&plane_state-> uapi.src)->x1 >> 16, (((&plane_state->uapi.src )->x1 & 0xffff) * 15625) >> 10, (&plane_state ->uapi.src)->y1 >> 16, (((&plane_state->uapi .src)->y1 & 0xffff) * 15625) >> 10, drm_rect_width (&plane_state->uapi.dst), drm_rect_height(&plane_state ->uapi.dst), (&plane_state->uapi.dst)->x1, (& plane_state->uapi.dst)->y1) |
| 13071 | DRM_RECT_FP_ARG(&plane_state->uapi.src),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tsrc: " "%d.%06ux%d.%06u%+d.%06u%+d.%06u" " dst: " "%dx%d%+d%+d" "\n" , drm_rect_width(&plane_state->uapi.src) >> 16, ( (drm_rect_width(&plane_state->uapi.src) & 0xffff) * 15625) >> 10, drm_rect_height(&plane_state->uapi .src) >> 16, ((drm_rect_height(&plane_state->uapi .src) & 0xffff) * 15625) >> 10, (&plane_state-> uapi.src)->x1 >> 16, (((&plane_state->uapi.src )->x1 & 0xffff) * 15625) >> 10, (&plane_state ->uapi.src)->y1 >> 16, (((&plane_state->uapi .src)->y1 & 0xffff) * 15625) >> 10, drm_rect_width (&plane_state->uapi.dst), drm_rect_height(&plane_state ->uapi.dst), (&plane_state->uapi.dst)->x1, (& plane_state->uapi.dst)->y1) |
| 13072 | DRM_RECT_ARG(&plane_state->uapi.dst))drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "\tsrc: " "%d.%06ux%d.%06u%+d.%06u%+d.%06u" " dst: " "%dx%d%+d%+d" "\n" , drm_rect_width(&plane_state->uapi.src) >> 16, ( (drm_rect_width(&plane_state->uapi.src) & 0xffff) * 15625) >> 10, drm_rect_height(&plane_state->uapi .src) >> 16, ((drm_rect_height(&plane_state->uapi .src) & 0xffff) * 15625) >> 10, (&plane_state-> uapi.src)->x1 >> 16, (((&plane_state->uapi.src )->x1 & 0xffff) * 15625) >> 10, (&plane_state ->uapi.src)->y1 >> 16, (((&plane_state->uapi .src)->y1 & 0xffff) * 15625) >> 10, drm_rect_width (&plane_state->uapi.dst), drm_rect_height(&plane_state ->uapi.dst), (&plane_state->uapi.dst)->x1, (& plane_state->uapi.dst)->y1); |
| 13073 | } |
| 13074 | |
| 13075 | static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config, |
| 13076 | struct intel_atomic_state *state, |
| 13077 | const char *context) |
| 13078 | { |
| 13079 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 13080 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 13081 | const struct intel_plane_state *plane_state; |
| 13082 | struct intel_plane *plane; |
| 13083 | char buf[64]; |
| 13084 | int i; |
| 13085 | |
| 13086 | drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] enable: %s %s\n" , crtc->base.base.id, crtc->base.name, yesno(pipe_config ->hw.enable), context) |
| 13087 | crtc->base.base.id, crtc->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] enable: %s %s\n" , crtc->base.base.id, crtc->base.name, yesno(pipe_config ->hw.enable), context) |
| 13088 | yesno(pipe_config->hw.enable), context)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] enable: %s %s\n" , crtc->base.base.id, crtc->base.name, yesno(pipe_config ->hw.enable), context); |
| 13089 | |
| 13090 | if (!pipe_config->hw.enable) |
| 13091 | goto dump_planes; |
| 13092 | |
| 13093 | snprintf_output_types(buf, sizeof(buf), pipe_config->output_types); |
| 13094 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "active: %s, output_types: %s (0x%x), output format: %s\n" , yesno(pipe_config->hw.active), buf, pipe_config->output_types , output_formats(pipe_config->output_format)) |
| 13095 | "active: %s, output_types: %s (0x%x), output format: %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "active: %s, output_types: %s (0x%x), output format: %s\n" , yesno(pipe_config->hw.active), buf, pipe_config->output_types , output_formats(pipe_config->output_format)) |
| 13096 | yesno(pipe_config->hw.active),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "active: %s, output_types: %s (0x%x), output format: %s\n" , yesno(pipe_config->hw.active), buf, pipe_config->output_types , output_formats(pipe_config->output_format)) |
| 13097 | buf, pipe_config->output_types,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "active: %s, output_types: %s (0x%x), output format: %s\n" , yesno(pipe_config->hw.active), buf, pipe_config->output_types , output_formats(pipe_config->output_format)) |
| 13098 | output_formats(pipe_config->output_format))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "active: %s, output_types: %s (0x%x), output format: %s\n" , yesno(pipe_config->hw.active), buf, pipe_config->output_types , output_formats(pipe_config->output_format)); |
| 13099 | |
| 13100 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n" , transcoder_name(pipe_config->cpu_transcoder), pipe_config ->pipe_bpp, pipe_config->dither) |
| 13101 | "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n" , transcoder_name(pipe_config->cpu_transcoder), pipe_config ->pipe_bpp, pipe_config->dither) |
| 13102 | transcoder_name(pipe_config->cpu_transcoder),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n" , transcoder_name(pipe_config->cpu_transcoder), pipe_config ->pipe_bpp, pipe_config->dither) |
| 13103 | pipe_config->pipe_bpp, pipe_config->dither)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n" , transcoder_name(pipe_config->cpu_transcoder), pipe_config ->pipe_bpp, pipe_config->dither); |
| 13104 | |
| 13105 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n" , transcoder_name(pipe_config->master_transcoder), pipe_config ->sync_mode_slaves_mask) |
| 13106 | "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n" , transcoder_name(pipe_config->master_transcoder), pipe_config ->sync_mode_slaves_mask) |
| 13107 | transcoder_name(pipe_config->master_transcoder),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n" , transcoder_name(pipe_config->master_transcoder), pipe_config ->sync_mode_slaves_mask) |
| 13108 | pipe_config->sync_mode_slaves_mask)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n" , transcoder_name(pipe_config->master_transcoder), pipe_config ->sync_mode_slaves_mask); |
| 13109 | |
| 13110 | if (pipe_config->has_pch_encoder) |
| 13111 | intel_dump_m_n_config(pipe_config, "fdi", |
| 13112 | pipe_config->fdi_lanes, |
| 13113 | &pipe_config->fdi_m_n); |
| 13114 | |
| 13115 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
| 13116 | intel_dump_m_n_config(pipe_config, "dp m_n", |
| 13117 | pipe_config->lane_count, &pipe_config->dp_m_n); |
| 13118 | if (pipe_config->has_drrs) |
| 13119 | intel_dump_m_n_config(pipe_config, "dp m2_n2", |
| 13120 | pipe_config->lane_count, |
| 13121 | &pipe_config->dp_m2_n2); |
| 13122 | } |
| 13123 | |
| 13124 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n" , pipe_config->has_audio, pipe_config->has_infoframe, pipe_config ->infoframes.enable) |
| 13125 | "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n" , pipe_config->has_audio, pipe_config->has_infoframe, pipe_config ->infoframes.enable) |
| 13126 | pipe_config->has_audio, pipe_config->has_infoframe,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n" , pipe_config->has_audio, pipe_config->has_infoframe, pipe_config ->infoframes.enable) |
| 13127 | pipe_config->infoframes.enable)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n" , pipe_config->has_audio, pipe_config->has_infoframe, pipe_config ->infoframes.enable); |
| 13128 | |
| 13129 | if (pipe_config->infoframes.enable & |
| 13130 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) |
| 13131 | drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "GCP: 0x%x\n" , pipe_config->infoframes.gcp) |
| 13132 | pipe_config->infoframes.gcp)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "GCP: 0x%x\n" , pipe_config->infoframes.gcp); |
| 13133 | if (pipe_config->infoframes.enable & |
| 13134 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) |
| 13135 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi); |
| 13136 | if (pipe_config->infoframes.enable & |
| 13137 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD)) |
| 13138 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd); |
| 13139 | if (pipe_config->infoframes.enable & |
| 13140 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR)) |
| 13141 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi); |
| 13142 | if (pipe_config->infoframes.enable & |
| 13143 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) |
| 13144 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); |
| 13145 | if (pipe_config->infoframes.enable & |
| 13146 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA)) |
| 13147 | intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm); |
| 13148 | if (pipe_config->infoframes.enable & |
| 13149 | intel_hdmi_infoframe_enable(DP_SDP_VSC0x07)) |
| 13150 | intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc); |
| 13151 | |
| 13152 | drm_dbg_kms(&dev_priv->drm, "requested mode:\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "requested mode:\n" ); |
| 13153 | drm_mode_debug_printmodeline(&pipe_config->hw.mode); |
| 13154 | drm_dbg_kms(&dev_priv->drm, "adjusted mode:\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "adjusted mode:\n" ); |
| 13155 | drm_mode_debug_printmodeline(&pipe_config->hw.adjusted_mode); |
| 13156 | intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode); |
| 13157 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port clock: %d, pipe src size: %dx%d, pixel rate %d\n" , pipe_config->port_clock, pipe_config->pipe_src_w, pipe_config ->pipe_src_h, pipe_config->pixel_rate) |
| 13158 | "port clock: %d, pipe src size: %dx%d, pixel rate %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port clock: %d, pipe src size: %dx%d, pixel rate %d\n" , pipe_config->port_clock, pipe_config->pipe_src_w, pipe_config ->pipe_src_h, pipe_config->pixel_rate) |
| 13159 | pipe_config->port_clock,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port clock: %d, pipe src size: %dx%d, pixel rate %d\n" , pipe_config->port_clock, pipe_config->pipe_src_w, pipe_config ->pipe_src_h, pipe_config->pixel_rate) |
| 13160 | pipe_config->pipe_src_w, pipe_config->pipe_src_h,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port clock: %d, pipe src size: %dx%d, pixel rate %d\n" , pipe_config->port_clock, pipe_config->pipe_src_w, pipe_config ->pipe_src_h, pipe_config->pixel_rate) |
| 13161 | pipe_config->pixel_rate)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "port clock: %d, pipe src size: %dx%d, pixel rate %d\n" , pipe_config->port_clock, pipe_config->pipe_src_w, pipe_config ->pipe_src_h, pipe_config->pixel_rate); |
| 13162 | |
| 13163 | drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "linetime: %d, ips linetime: %d\n" , pipe_config->linetime, pipe_config->ips_linetime) |
| 13164 | pipe_config->linetime, pipe_config->ips_linetime)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "linetime: %d, ips linetime: %d\n" , pipe_config->linetime, pipe_config->ips_linetime); |
| 13165 | |
| 13166 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 13167 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n" , crtc->num_scalers, pipe_config->scaler_state.scaler_users , pipe_config->scaler_state.scaler_id) |
| 13168 | "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n" , crtc->num_scalers, pipe_config->scaler_state.scaler_users , pipe_config->scaler_state.scaler_id) |
| 13169 | crtc->num_scalers,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n" , crtc->num_scalers, pipe_config->scaler_state.scaler_users , pipe_config->scaler_state.scaler_id) |
| 13170 | pipe_config->scaler_state.scaler_users,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n" , crtc->num_scalers, pipe_config->scaler_state.scaler_users , pipe_config->scaler_state.scaler_id) |
| 13171 | pipe_config->scaler_state.scaler_id)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n" , crtc->num_scalers, pipe_config->scaler_state.scaler_users , pipe_config->scaler_state.scaler_id); |
| 13172 | |
| 13173 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) |
| 13174 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n" , pipe_config->gmch_pfit.control, pipe_config->gmch_pfit .pgm_ratios, pipe_config->gmch_pfit.lvds_border_bits) |
| 13175 | "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n" , pipe_config->gmch_pfit.control, pipe_config->gmch_pfit .pgm_ratios, pipe_config->gmch_pfit.lvds_border_bits) |
| 13176 | pipe_config->gmch_pfit.control,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n" , pipe_config->gmch_pfit.control, pipe_config->gmch_pfit .pgm_ratios, pipe_config->gmch_pfit.lvds_border_bits) |
| 13177 | pipe_config->gmch_pfit.pgm_ratios,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n" , pipe_config->gmch_pfit.control, pipe_config->gmch_pfit .pgm_ratios, pipe_config->gmch_pfit.lvds_border_bits) |
| 13178 | pipe_config->gmch_pfit.lvds_border_bits)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n" , pipe_config->gmch_pfit.control, pipe_config->gmch_pfit .pgm_ratios, pipe_config->gmch_pfit.lvds_border_bits); |
| 13179 | else |
| 13180 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pch pfit: " "%dx%d%+d%+d" ", %s, force thru: %s\n", drm_rect_width(& pipe_config->pch_pfit.dst), drm_rect_height(&pipe_config ->pch_pfit.dst), (&pipe_config->pch_pfit.dst)->x1 , (&pipe_config->pch_pfit.dst)->y1, enableddisabled (pipe_config->pch_pfit.enabled), yesno(pipe_config->pch_pfit .force_thru)) |
| 13181 | "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pch pfit: " "%dx%d%+d%+d" ", %s, force thru: %s\n", drm_rect_width(& pipe_config->pch_pfit.dst), drm_rect_height(&pipe_config ->pch_pfit.dst), (&pipe_config->pch_pfit.dst)->x1 , (&pipe_config->pch_pfit.dst)->y1, enableddisabled (pipe_config->pch_pfit.enabled), yesno(pipe_config->pch_pfit .force_thru)) |
| 13182 | DRM_RECT_ARG(&pipe_config->pch_pfit.dst),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pch pfit: " "%dx%d%+d%+d" ", %s, force thru: %s\n", drm_rect_width(& pipe_config->pch_pfit.dst), drm_rect_height(&pipe_config ->pch_pfit.dst), (&pipe_config->pch_pfit.dst)->x1 , (&pipe_config->pch_pfit.dst)->y1, enableddisabled (pipe_config->pch_pfit.enabled), yesno(pipe_config->pch_pfit .force_thru)) |
| 13183 | enableddisabled(pipe_config->pch_pfit.enabled),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pch pfit: " "%dx%d%+d%+d" ", %s, force thru: %s\n", drm_rect_width(& pipe_config->pch_pfit.dst), drm_rect_height(&pipe_config ->pch_pfit.dst), (&pipe_config->pch_pfit.dst)->x1 , (&pipe_config->pch_pfit.dst)->y1, enableddisabled (pipe_config->pch_pfit.enabled), yesno(pipe_config->pch_pfit .force_thru)) |
| 13184 | yesno(pipe_config->pch_pfit.force_thru))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pch pfit: " "%dx%d%+d%+d" ", %s, force thru: %s\n", drm_rect_width(& pipe_config->pch_pfit.dst), drm_rect_height(&pipe_config ->pch_pfit.dst), (&pipe_config->pch_pfit.dst)->x1 , (&pipe_config->pch_pfit.dst)->y1, enableddisabled (pipe_config->pch_pfit.enabled), yesno(pipe_config->pch_pfit .force_thru)); |
| 13185 | |
| 13186 | drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ips: %i, double wide: %i\n" , pipe_config->ips_enabled, pipe_config->double_wide) |
| 13187 | pipe_config->ips_enabled, pipe_config->double_wide)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ips: %i, double wide: %i\n" , pipe_config->ips_enabled, pipe_config->double_wide); |
| 13188 | |
| 13189 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
| 13190 | |
| 13191 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 13192 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable) |
| 13193 | "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable) |
| 13194 | pipe_config->cgm_mode, pipe_config->gamma_mode,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable) |
| 13195 | pipe_config->gamma_enable, pipe_config->csc_enable)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->cgm_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable); |
| 13196 | else |
| 13197 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable) |
| 13198 | "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable) |
| 13199 | pipe_config->csc_mode, pipe_config->gamma_mode,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable) |
| 13200 | pipe_config->gamma_enable, pipe_config->csc_enable)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n" , pipe_config->csc_mode, pipe_config->gamma_mode, pipe_config ->gamma_enable, pipe_config->csc_enable); |
| 13201 | |
| 13202 | drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "MST master transcoder: %s\n" , transcoder_name(pipe_config->mst_master_transcoder)) |
| 13203 | transcoder_name(pipe_config->mst_master_transcoder))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "MST master transcoder: %s\n" , transcoder_name(pipe_config->mst_master_transcoder)); |
| 13204 | |
| 13205 | dump_planes: |
| 13206 | if (!state) |
| 13207 | return; |
| 13208 | |
| 13209 | for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else { |
| 13210 | if (plane->pipe == crtc->pipe) |
| 13211 | intel_dump_plane_state(plane_state); |
| 13212 | } |
| 13213 | } |
| 13214 | |
| 13215 | static bool_Bool check_digital_port_conflicts(struct intel_atomic_state *state) |
| 13216 | { |
| 13217 | struct drm_device *dev = state->base.dev; |
| 13218 | struct drm_connector *connector; |
| 13219 | struct drm_connector_list_iter conn_iter; |
| 13220 | unsigned int used_ports = 0; |
| 13221 | unsigned int used_mst_ports = 0; |
| 13222 | bool_Bool ret = true1; |
| 13223 | |
| 13224 | /* |
| 13225 | * We're going to peek into connector->state, |
| 13226 | * hence connection_mutex must be held. |
| 13227 | */ |
| 13228 | drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex); |
| 13229 | |
| 13230 | /* |
| 13231 | * Walk the connector list instead of the encoder |
| 13232 | * list to detect the problem on ddi platforms |
| 13233 | * where there's just one encoder per digital port. |
| 13234 | */ |
| 13235 | drm_connector_list_iter_begin(dev, &conn_iter); |
| 13236 | drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter ))) { |
| 13237 | struct drm_connector_state *connector_state; |
| 13238 | struct intel_encoder *encoder; |
| 13239 | |
| 13240 | connector_state = |
| 13241 | drm_atomic_get_new_connector_state(&state->base, |
| 13242 | connector); |
| 13243 | if (!connector_state) |
| 13244 | connector_state = connector->state; |
| 13245 | |
| 13246 | if (!connector_state->best_encoder) |
| 13247 | continue; |
| 13248 | |
| 13249 | encoder = to_intel_encoder(connector_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (connector_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 13250 | |
| 13251 | drm_WARN_ON(dev, !connector_state->crtc)({ int __ret = !!((!connector_state->crtc)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "!connector_state->crtc" ")"); __builtin_expect(!!(__ret) , 0); }); |
| 13252 | |
| 13253 | switch (encoder->type) { |
| 13254 | case INTEL_OUTPUT_DDI: |
| 13255 | if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev)))({ int __ret = !!((!((&(to_i915(dev))->__info)->display .has_ddi))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((dev))->dev), "", "drm_WARN_ON(" "!((&(to_i915(dev))->__info)->display.has_ddi)" ")"); __builtin_expect(!!(__ret), 0); })) |
| 13256 | break; |
| 13257 | fallthroughdo {} while (0); |
| 13258 | case INTEL_OUTPUT_DP: |
| 13259 | case INTEL_OUTPUT_HDMI: |
| 13260 | case INTEL_OUTPUT_EDP: |
| 13261 | /* the same port mustn't appear more than once */ |
| 13262 | if (used_ports & BIT(encoder->port)(1UL << (encoder->port))) |
| 13263 | ret = false0; |
| 13264 | |
| 13265 | used_ports |= BIT(encoder->port)(1UL << (encoder->port)); |
| 13266 | break; |
| 13267 | case INTEL_OUTPUT_DP_MST: |
| 13268 | used_mst_ports |= |
| 13269 | 1 << encoder->port; |
| 13270 | break; |
| 13271 | default: |
| 13272 | break; |
| 13273 | } |
| 13274 | } |
| 13275 | drm_connector_list_iter_end(&conn_iter); |
| 13276 | |
| 13277 | /* can't mix MST and SST/HDMI on the same port */ |
| 13278 | if (used_ports & used_mst_ports) |
| 13279 | return false0; |
| 13280 | |
| 13281 | return ret; |
| 13282 | } |
| 13283 | |
| 13284 | static void |
| 13285 | intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_crtc_state *crtc_state) |
| 13286 | { |
| 13287 | intel_crtc_copy_color_blobs(crtc_state); |
| 13288 | } |
| 13289 | |
| 13290 | static void |
| 13291 | intel_crtc_copy_uapi_to_hw_state(struct intel_crtc_state *crtc_state) |
| 13292 | { |
| 13293 | crtc_state->hw.enable = crtc_state->uapi.enable; |
| 13294 | crtc_state->hw.active = crtc_state->uapi.active; |
| 13295 | crtc_state->hw.mode = crtc_state->uapi.mode; |
| 13296 | crtc_state->hw.adjusted_mode = crtc_state->uapi.adjusted_mode; |
| 13297 | intel_crtc_copy_uapi_to_hw_state_nomodeset(crtc_state); |
| 13298 | } |
| 13299 | |
| 13300 | static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) |
| 13301 | { |
| 13302 | crtc_state->uapi.enable = crtc_state->hw.enable; |
| 13303 | crtc_state->uapi.active = crtc_state->hw.active; |
| 13304 | drm_WARN_ON(crtc_state->uapi.crtc->dev,({ int __ret = !!((drm_atomic_set_mode_for_crtc(&crtc_state ->uapi, &crtc_state->hw.mode) < 0)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((crtc_state->uapi.crtc ->dev))->dev), "", "drm_WARN_ON(" "drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0" ")"); __builtin_expect(!!(__ret), 0); }) |
| 13305 | drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0)({ int __ret = !!((drm_atomic_set_mode_for_crtc(&crtc_state ->uapi, &crtc_state->hw.mode) < 0)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((crtc_state->uapi.crtc ->dev))->dev), "", "drm_WARN_ON(" "drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0" ")"); __builtin_expect(!!(__ret), 0); }); |
| 13306 | |
| 13307 | crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; |
| 13308 | |
| 13309 | /* copy color blobs to uapi */ |
| 13310 | drm_property_replace_blob(&crtc_state->uapi.degamma_lut, |
| 13311 | crtc_state->hw.degamma_lut); |
| 13312 | drm_property_replace_blob(&crtc_state->uapi.gamma_lut, |
| 13313 | crtc_state->hw.gamma_lut); |
| 13314 | drm_property_replace_blob(&crtc_state->uapi.ctm, |
| 13315 | crtc_state->hw.ctm); |
| 13316 | } |
| 13317 | |
| 13318 | static int |
| 13319 | intel_crtc_prepare_cleared_state(struct intel_crtc_state *crtc_state) |
| 13320 | { |
| 13321 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 13322 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 13323 | struct intel_crtc_state *saved_state; |
| 13324 | |
| 13325 | saved_state = intel_crtc_state_alloc(crtc); |
| 13326 | if (!saved_state) |
| 13327 | return -ENOMEM12; |
| 13328 | |
| 13329 | /* free the old crtc_state->hw members */ |
| 13330 | intel_crtc_free_hw_state(crtc_state); |
| 13331 | |
| 13332 | /* FIXME: before the switch to atomic started, a new pipe_config was |
| 13333 | * kzalloc'd. Code that depends on any field being zero should be |
| 13334 | * fixed, so that the crtc_state can be safely duplicated. For now, |
| 13335 | * only fields that are know to not cause problems are preserved. */ |
| 13336 | |
| 13337 | saved_state->uapi = crtc_state->uapi; |
| 13338 | saved_state->scaler_state = crtc_state->scaler_state; |
| 13339 | saved_state->shared_dpll = crtc_state->shared_dpll; |
| 13340 | saved_state->dpll_hw_state = crtc_state->dpll_hw_state; |
| 13341 | memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,__builtin_memcpy((saved_state->icl_port_dplls), (crtc_state ->icl_port_dplls), (sizeof(saved_state->icl_port_dplls) )) |
| 13342 | sizeof(saved_state->icl_port_dplls))__builtin_memcpy((saved_state->icl_port_dplls), (crtc_state ->icl_port_dplls), (sizeof(saved_state->icl_port_dplls) )); |
| 13343 | saved_state->crc_enabled = crtc_state->crc_enabled; |
| 13344 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || |
| 13345 | IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 13346 | saved_state->wm = crtc_state->wm; |
| 13347 | |
| 13348 | memcpy(crtc_state, saved_state, sizeof(*crtc_state))__builtin_memcpy((crtc_state), (saved_state), (sizeof(*crtc_state ))); |
| 13349 | kfree(saved_state); |
| 13350 | |
| 13351 | intel_crtc_copy_uapi_to_hw_state(crtc_state); |
| 13352 | |
| 13353 | return 0; |
| 13354 | } |
| 13355 | |
| 13356 | static int |
| 13357 | intel_modeset_pipe_config(struct intel_crtc_state *pipe_config) |
| 13358 | { |
| 13359 | struct drm_crtc *crtc = pipe_config->uapi.crtc; |
| 13360 | struct drm_atomic_state *state = pipe_config->uapi.state; |
| 13361 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(pipe_config->uapi.crtc->dev); |
| 13362 | struct drm_connector *connector; |
| 13363 | struct drm_connector_state *connector_state; |
| 13364 | int base_bpp, ret, i; |
| 13365 | bool_Bool retry = true1; |
| 13366 | |
| 13367 | pipe_config->cpu_transcoder = |
| 13368 | (enum transcoder) to_intel_crtc(crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );})->pipe; |
| 13369 | |
| 13370 | /* |
| 13371 | * Sanitize sync polarity flags based on requested ones. If neither |
| 13372 | * positive or negative polarity is requested, treat this as meaning |
| 13373 | * negative polarity. |
| 13374 | */ |
| 13375 | if (!(pipe_config->hw.adjusted_mode.flags & |
| 13376 | (DRM_MODE_FLAG_PHSYNC(1<<0) | DRM_MODE_FLAG_NHSYNC(1<<1)))) |
| 13377 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
| 13378 | |
| 13379 | if (!(pipe_config->hw.adjusted_mode.flags & |
| 13380 | (DRM_MODE_FLAG_PVSYNC(1<<2) | DRM_MODE_FLAG_NVSYNC(1<<3)))) |
| 13381 | pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
| 13382 | |
| 13383 | ret = compute_baseline_pipe_bpp(to_intel_crtc(crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}), |
| 13384 | pipe_config); |
| 13385 | if (ret) |
| 13386 | return ret; |
| 13387 | |
| 13388 | base_bpp = pipe_config->pipe_bpp; |
| 13389 | |
| 13390 | /* |
| 13391 | * Determine the real pipe dimensions. Note that stereo modes can |
| 13392 | * increase the actual pipe size due to the frame doubling and |
| 13393 | * insertion of additional space for blanks between the frame. This |
| 13394 | * is stored in the crtc timings. We use the requested mode to do this |
| 13395 | * computation to clearly distinguish it from the adjusted mode, which |
| 13396 | * can be changed by the connectors in the below retry loop. |
| 13397 | */ |
| 13398 | drm_mode_get_hv_timing(&pipe_config->hw.mode, |
| 13399 | &pipe_config->pipe_src_w, |
| 13400 | &pipe_config->pipe_src_h); |
| 13401 | |
| 13402 | for_each_new_connector_in_state(state, connector, connector_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if ( !((state)->connectors[i].ptr && ((connector) = (state )->connectors[i].ptr, (void)(connector) , (connector_state ) = (state)->connectors[i].new_state, (void)(connector_state ) , 1))) {} else { |
| 13403 | struct intel_encoder *encoder = |
| 13404 | to_intel_encoder(connector_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (connector_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 13405 | |
| 13406 | if (connector_state->crtc != crtc) |
| 13407 | continue; |
| 13408 | |
| 13409 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}), encoder)) { |
| 13410 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "rejecting invalid cloning configuration\n" ) |
| 13411 | "rejecting invalid cloning configuration\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "rejecting invalid cloning configuration\n" ); |
| 13412 | return -EINVAL22; |
| 13413 | } |
| 13414 | |
| 13415 | /* |
| 13416 | * Determine output_types before calling the .compute_config() |
| 13417 | * hooks so that the hooks can use this information safely. |
| 13418 | */ |
| 13419 | if (encoder->compute_output_type) |
| 13420 | pipe_config->output_types |= |
| 13421 | BIT(encoder->compute_output_type(encoder, pipe_config,(1UL << (encoder->compute_output_type(encoder, pipe_config , connector_state))) |
| 13422 | connector_state))(1UL << (encoder->compute_output_type(encoder, pipe_config , connector_state))); |
| 13423 | else |
| 13424 | pipe_config->output_types |= BIT(encoder->type)(1UL << (encoder->type)); |
| 13425 | } |
| 13426 | |
| 13427 | encoder_retry: |
| 13428 | /* Ensure the port clock defaults are reset when retrying. */ |
| 13429 | pipe_config->port_clock = 0; |
| 13430 | pipe_config->pixel_multiplier = 1; |
| 13431 | |
| 13432 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
| 13433 | drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode, |
| 13434 | CRTC_STEREO_DOUBLE(1 << 1)); |
| 13435 | |
| 13436 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
| 13437 | * adjust it according to limitations or connector properties, and also |
| 13438 | * a chance to reject the mode entirely. |
| 13439 | */ |
| 13440 | for_each_new_connector_in_state(state, connector, connector_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if ( !((state)->connectors[i].ptr && ((connector) = (state )->connectors[i].ptr, (void)(connector) , (connector_state ) = (state)->connectors[i].new_state, (void)(connector_state ) , 1))) {} else { |
| 13441 | struct intel_encoder *encoder = |
| 13442 | to_intel_encoder(connector_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (connector_state->best_encoder); (struct intel_encoder * )( (char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 13443 | |
| 13444 | if (connector_state->crtc != crtc) |
| 13445 | continue; |
| 13446 | |
| 13447 | ret = encoder->compute_config(encoder, pipe_config, |
| 13448 | connector_state); |
| 13449 | if (ret < 0) { |
| 13450 | if (ret != -EDEADLK11) |
| 13451 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Encoder config failure: %d\n" , ret) |
| 13452 | "Encoder config failure: %d\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Encoder config failure: %d\n" , ret) |
| 13453 | ret)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Encoder config failure: %d\n" , ret); |
| 13454 | return ret; |
| 13455 | } |
| 13456 | } |
| 13457 | |
| 13458 | /* Set default port clock if not overwritten by the encoder. Needs to be |
| 13459 | * done afterwards in case the encoder adjusts the mode. */ |
| 13460 | if (!pipe_config->port_clock) |
| 13461 | pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock |
| 13462 | * pipe_config->pixel_multiplier; |
| 13463 | |
| 13464 | ret = intel_crtc_compute_config(to_intel_crtc(crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}), pipe_config); |
| 13465 | if (ret == -EDEADLK11) |
| 13466 | return ret; |
| 13467 | if (ret < 0) { |
| 13468 | drm_dbg_kms(&i915->drm, "CRTC fixup failed\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CRTC fixup failed\n" ); |
| 13469 | return ret; |
| 13470 | } |
| 13471 | |
| 13472 | if (ret == RETRY1) { |
| 13473 | if (drm_WARN(&i915->drm, !retry,({ int __ret = !!(!retry); if (__ret) printf("%s %s: " "loop in pipe configuration computation\n" , dev_driver_string((&i915->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }) |
| 13474 | "loop in pipe configuration computation\n")({ int __ret = !!(!retry); if (__ret) printf("%s %s: " "loop in pipe configuration computation\n" , dev_driver_string((&i915->drm)->dev), ""); __builtin_expect (!!(__ret), 0); })) |
| 13475 | return -EINVAL22; |
| 13476 | |
| 13477 | drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "CRTC bw constrained, retrying\n" ); |
| 13478 | retry = false0; |
| 13479 | goto encoder_retry; |
| 13480 | } |
| 13481 | |
| 13482 | /* Dithering seems to not pass-through bits correctly when it should, so |
| 13483 | * only enable it on 6bpc panels and when its not a compliance |
| 13484 | * test requesting 6bpc video pattern. |
| 13485 | */ |
| 13486 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && |
| 13487 | !pipe_config->dither_force_disable; |
| 13488 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "hw max bpp: %i, pipe bpp: %i, dithering: %i\n" , base_bpp, pipe_config->pipe_bpp, pipe_config->dither) |
| 13489 | "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "hw max bpp: %i, pipe bpp: %i, dithering: %i\n" , base_bpp, pipe_config->pipe_bpp, pipe_config->dither) |
| 13490 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "hw max bpp: %i, pipe bpp: %i, dithering: %i\n" , base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
| 13491 | |
| 13492 | return 0; |
| 13493 | } |
| 13494 | |
| 13495 | static int |
| 13496 | intel_modeset_pipe_config_late(struct intel_crtc_state *crtc_state) |
| 13497 | { |
| 13498 | struct intel_atomic_state *state = |
| 13499 | to_intel_atomic_state(crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 13500 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 13501 | struct drm_connector_state *conn_state; |
| 13502 | struct drm_connector *connector; |
| 13503 | int i; |
| 13504 | |
| 13505 | for_each_new_connector_in_state(&state->base, connector,for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else |
| 13506 | conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
| 13507 | struct intel_encoder *encoder = |
| 13508 | to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
| 13509 | int ret; |
| 13510 | |
| 13511 | if (conn_state->crtc != &crtc->base || |
| 13512 | !encoder->compute_config_late) |
| 13513 | continue; |
| 13514 | |
| 13515 | ret = encoder->compute_config_late(encoder, crtc_state, |
| 13516 | conn_state); |
| 13517 | if (ret) |
| 13518 | return ret; |
| 13519 | } |
| 13520 | |
| 13521 | return 0; |
| 13522 | } |
| 13523 | |
| 13524 | bool_Bool intel_fuzzy_clock_check(int clock1, int clock2) |
| 13525 | { |
| 13526 | int diff; |
| 13527 | |
| 13528 | if (clock1 == clock2) |
| 13529 | return true1; |
| 13530 | |
| 13531 | if (!clock1 || !clock2) |
| 13532 | return false0; |
| 13533 | |
| 13534 | diff = abs(clock1 - clock2); |
| 13535 | |
| 13536 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) |
| 13537 | return true1; |
| 13538 | |
| 13539 | return false0; |
| 13540 | } |
| 13541 | |
| 13542 | static bool_Bool |
| 13543 | intel_compare_m_n(unsigned int m, unsigned int n, |
| 13544 | unsigned int m2, unsigned int n2, |
| 13545 | bool_Bool exact) |
| 13546 | { |
| 13547 | if (m == m2 && n == n2) |
| 13548 | return true1; |
| 13549 | |
| 13550 | if (exact || !m || !n || !m2 || !n2) |
| 13551 | return false0; |
| 13552 | |
| 13553 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX)extern char _ctassert[(!((0xffffff) > 0x7fffffff)) ? 1 : - 1 ] __attribute__((__unused__)); |
| 13554 | |
| 13555 | if (n > n2) { |
| 13556 | while (n > n2) { |
| 13557 | m2 <<= 1; |
| 13558 | n2 <<= 1; |
| 13559 | } |
| 13560 | } else if (n < n2) { |
| 13561 | while (n < n2) { |
| 13562 | m <<= 1; |
| 13563 | n <<= 1; |
| 13564 | } |
| 13565 | } |
| 13566 | |
| 13567 | if (n != n2) |
| 13568 | return false0; |
| 13569 | |
| 13570 | return intel_fuzzy_clock_check(m, m2); |
| 13571 | } |
| 13572 | |
| 13573 | static bool_Bool |
| 13574 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, |
| 13575 | const struct intel_link_m_n *m2_n2, |
| 13576 | bool_Bool exact) |
| 13577 | { |
| 13578 | return m_n->tu == m2_n2->tu && |
| 13579 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, |
| 13580 | m2_n2->gmch_m, m2_n2->gmch_n, exact) && |
| 13581 | intel_compare_m_n(m_n->link_m, m_n->link_n, |
| 13582 | m2_n2->link_m, m2_n2->link_n, exact); |
| 13583 | } |
| 13584 | |
| 13585 | static bool_Bool |
| 13586 | intel_compare_infoframe(const union hdmi_infoframe *a, |
| 13587 | const union hdmi_infoframe *b) |
| 13588 | { |
| 13589 | return memcmp(a, b, sizeof(*a))__builtin_memcmp((a), (b), (sizeof(*a))) == 0; |
| 13590 | } |
| 13591 | |
| 13592 | static bool_Bool |
| 13593 | intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a, |
| 13594 | const struct drm_dp_vsc_sdp *b) |
| 13595 | { |
| 13596 | return memcmp(a, b, sizeof(*a))__builtin_memcmp((a), (b), (sizeof(*a))) == 0; |
| 13597 | } |
| 13598 | |
| 13599 | static void |
| 13600 | pipe_config_infoframe_mismatch(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 13601 | bool_Bool fastset, const char *name, |
| 13602 | const union hdmi_infoframe *a, |
| 13603 | const union hdmi_infoframe *b) |
| 13604 | { |
| 13605 | if (fastset) { |
| 13606 | if (!drm_debug_enabled(DRM_UT_KMS)) |
| 13607 | return; |
| 13608 | |
| 13609 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fastset mismatch in %s infoframe\n" , name) |
| 13610 | "fastset mismatch in %s infoframe\n", name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fastset mismatch in %s infoframe\n" , name); |
| 13611 | drm_dbg_kms(&dev_priv->drm, "expected:\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "expected:\n" ); |
| 13612 | hdmi_infoframe_log(KERN_DEBUG"\0017", dev_priv->drm.dev, a); |
| 13613 | drm_dbg_kms(&dev_priv->drm, "found:\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "found:\n" ); |
| 13614 | hdmi_infoframe_log(KERN_DEBUG"\0017", dev_priv->drm.dev, b); |
| 13615 | } else { |
| 13616 | drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in %s infoframe\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , name); |
| 13617 | drm_err(&dev_priv->drm, "expected:\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "expected:\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 13618 | hdmi_infoframe_log(KERN_ERR"\0013", dev_priv->drm.dev, a); |
| 13619 | drm_err(&dev_priv->drm, "found:\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "found:\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 13620 | hdmi_infoframe_log(KERN_ERR"\0013", dev_priv->drm.dev, b); |
| 13621 | } |
| 13622 | } |
| 13623 | |
| 13624 | static void |
| 13625 | pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 13626 | bool_Bool fastset, const char *name, |
| 13627 | const struct drm_dp_vsc_sdp *a, |
| 13628 | const struct drm_dp_vsc_sdp *b) |
| 13629 | { |
| 13630 | if (fastset) { |
| 13631 | if (!drm_debug_enabled(DRM_UT_KMS)) |
| 13632 | return; |
| 13633 | |
| 13634 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fastset mismatch in %s dp sdp\n" , name) |
| 13635 | "fastset mismatch in %s dp sdp\n", name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "fastset mismatch in %s dp sdp\n" , name); |
| 13636 | drm_dbg_kms(&dev_priv->drm, "expected:\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "expected:\n" ); |
| 13637 | drm_dp_vsc_sdp_log(KERN_DEBUG"\0017", dev_priv->drm.dev, a); |
| 13638 | drm_dbg_kms(&dev_priv->drm, "found:\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "found:\n" ); |
| 13639 | drm_dp_vsc_sdp_log(KERN_DEBUG"\0017", dev_priv->drm.dev, b); |
| 13640 | } else { |
| 13641 | drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in %s dp sdp\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , name); |
| 13642 | drm_err(&dev_priv->drm, "expected:\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "expected:\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 13643 | drm_dp_vsc_sdp_log(KERN_ERR"\0013", dev_priv->drm.dev, a); |
| 13644 | drm_err(&dev_priv->drm, "found:\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "found:\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 13645 | drm_dp_vsc_sdp_log(KERN_ERR"\0013", dev_priv->drm.dev, b); |
| 13646 | } |
| 13647 | } |
| 13648 | |
| 13649 | static void __printf(4, 5)__attribute__((__format__(__kprintf__,4,5))) |
| 13650 | pipe_config_mismatch(bool_Bool fastset, const struct intel_crtc *crtc, |
| 13651 | const char *name, const char *format, ...) |
| 13652 | { |
| 13653 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev); |
| 13654 | struct va_format vaf; |
| 13655 | va_list args; |
| 13656 | |
| 13657 | va_start(args, format)__builtin_va_start((args), format); |
| 13658 | vaf.fmt = format; |
| 13659 | vaf.va = &args; |
| 13660 | |
| 13661 | if (fastset) |
| 13662 | drm_dbg_kms(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] fastset mismatch in %s %pV\n" , crtc->base.base.id, crtc->base.name, name, &vaf) |
| 13663 | "[CRTC:%d:%s] fastset mismatch in %s %pV\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] fastset mismatch in %s %pV\n" , crtc->base.base.id, crtc->base.name, name, &vaf) |
| 13664 | crtc->base.base.id, crtc->base.name, name, &vaf)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] fastset mismatch in %s %pV\n" , crtc->base.base.id, crtc->base.name, name, &vaf); |
| 13665 | else |
| 13666 | drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "[CRTC:%d:%s] mismatch in %s %pV\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , crtc-> base.base.id, crtc->base.name, name, &vaf) |
| 13667 | crtc->base.base.id, crtc->base.name, name, &vaf)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "[CRTC:%d:%s] mismatch in %s %pV\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , crtc-> base.base.id, crtc->base.name, name, &vaf); |
| 13668 | |
| 13669 | va_end(args)__builtin_va_end((args)); |
| 13670 | } |
| 13671 | |
| 13672 | static bool_Bool fastboot_enabled(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 13673 | { |
| 13674 | if (dev_priv->params.fastboot != -1) |
| 13675 | return dev_priv->params.fastboot; |
| 13676 | |
| 13677 | /* Enable fastboot by default on Skylake and newer */ |
| 13678 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 13679 | return true1; |
| 13680 | |
| 13681 | /* Enable fastboot by default on VLV and CHV */ |
| 13682 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 13683 | return true1; |
| 13684 | |
| 13685 | /* Disabled by default on all others */ |
| 13686 | return false0; |
| 13687 | } |
| 13688 | |
| 13689 | static bool_Bool |
| 13690 | intel_pipe_config_compare(const struct intel_crtc_state *current_config, |
| 13691 | const struct intel_crtc_state *pipe_config, |
| 13692 | bool_Bool fastset) |
| 13693 | { |
| 13694 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(current_config->uapi.crtc->dev); |
| 13695 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 13696 | bool_Bool ret = true1; |
| 13697 | u32 bp_gamma = 0; |
| 13698 | bool_Bool fixup_inherited = fastset && |
| 13699 | current_config->inherited && !pipe_config->inherited; |
| 13700 | |
| 13701 | if (fixup_inherited && !fastboot_enabled(dev_priv)) { |
| 13702 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial modeset and fastboot not set\n" ) |
| 13703 | "initial modeset and fastboot not set\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "initial modeset and fastboot not set\n" ); |
| 13704 | ret = false0; |
| 13705 | } |
| 13706 | |
| 13707 | #define PIPE_CONF_CHECK_X(name) do { \ |
| 13708 | if (current_config->name != pipe_config->name) { \ |
| 13709 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13710 | "(expected 0x%08x, found 0x%08x)", \ |
| 13711 | current_config->name, \ |
| 13712 | pipe_config->name); \ |
| 13713 | ret = false0; \ |
| 13714 | } \ |
| 13715 | } while (0) |
| 13716 | |
| 13717 | #define PIPE_CONF_CHECK_I(name) do { \ |
| 13718 | if (current_config->name != pipe_config->name) { \ |
| 13719 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13720 | "(expected %i, found %i)", \ |
| 13721 | current_config->name, \ |
| 13722 | pipe_config->name); \ |
| 13723 | ret = false0; \ |
| 13724 | } \ |
| 13725 | } while (0) |
| 13726 | |
| 13727 | #define PIPE_CONF_CHECK_BOOL(name) do { \ |
| 13728 | if (current_config->name != pipe_config->name) { \ |
| 13729 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13730 | "(expected %s, found %s)", \ |
| 13731 | yesno(current_config->name), \ |
| 13732 | yesno(pipe_config->name)); \ |
| 13733 | ret = false0; \ |
| 13734 | } \ |
| 13735 | } while (0) |
| 13736 | |
| 13737 | /* |
| 13738 | * Checks state where we only read out the enabling, but not the entire |
| 13739 | * state itself (like full infoframes or ELD for audio). These states |
| 13740 | * require a full modeset on bootup to fix up. |
| 13741 | */ |
| 13742 | #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \ |
| 13743 | if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \ |
| 13744 | PIPE_CONF_CHECK_BOOL(name); \ |
| 13745 | } else { \ |
| 13746 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13747 | "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \ |
| 13748 | yesno(current_config->name), \ |
| 13749 | yesno(pipe_config->name)); \ |
| 13750 | ret = false0; \ |
| 13751 | } \ |
| 13752 | } while (0) |
| 13753 | |
| 13754 | #define PIPE_CONF_CHECK_P(name) do { \ |
| 13755 | if (current_config->name != pipe_config->name) { \ |
| 13756 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13757 | "(expected %p, found %p)", \ |
| 13758 | current_config->name, \ |
| 13759 | pipe_config->name); \ |
| 13760 | ret = false0; \ |
| 13761 | } \ |
| 13762 | } while (0) |
| 13763 | |
| 13764 | #define PIPE_CONF_CHECK_M_N(name)do { if (!intel_compare_link_m_n(¤t_config->name , &pipe_config->name, !fastset)) { pipe_config_mismatch (fastset, crtc, "name", "(expected tu %i gmch %i/%i link %i/%i, " "found tu %i, gmch %i/%i link %i/%i)", current_config->name .tu, current_config->name.gmch_m, current_config->name. gmch_n, current_config->name.link_m, current_config->name .link_n, pipe_config->name.tu, pipe_config->name.gmch_m , pipe_config->name.gmch_n, pipe_config->name.link_m, pipe_config ->name.link_n); ret = 0; } } while (0) do { \ |
| 13765 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 13766 | &pipe_config->name,\ |
| 13767 | !fastset)) { \ |
| 13768 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13769 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 13770 | "found tu %i, gmch %i/%i link %i/%i)", \ |
| 13771 | current_config->name.tu, \ |
| 13772 | current_config->name.gmch_m, \ |
| 13773 | current_config->name.gmch_n, \ |
| 13774 | current_config->name.link_m, \ |
| 13775 | current_config->name.link_n, \ |
| 13776 | pipe_config->name.tu, \ |
| 13777 | pipe_config->name.gmch_m, \ |
| 13778 | pipe_config->name.gmch_n, \ |
| 13779 | pipe_config->name.link_m, \ |
| 13780 | pipe_config->name.link_n); \ |
| 13781 | ret = false0; \ |
| 13782 | } \ |
| 13783 | } while (0) |
| 13784 | |
| 13785 | /* This is required for BDW+ where there is only one set of registers for |
| 13786 | * switching between high and low RR. |
| 13787 | * This macro can be used whenever a comparison has to be made between one |
| 13788 | * hw state and multiple sw state variables. |
| 13789 | */ |
| 13790 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name)do { if (!intel_compare_link_m_n(¤t_config->name , &pipe_config->name, !fastset) && !intel_compare_link_m_n (¤t_config->alt_name, &pipe_config->name, !fastset)) { pipe_config_mismatch(fastset, crtc, "name", "(expected tu %i gmch %i/%i link %i/%i, " "or tu %i gmch %i/%i link %i/%i, " "found tu %i, gmch %i/%i link %i/%i)" , current_config->name.tu, current_config->name.gmch_m, current_config->name.gmch_n, current_config->name.link_m , current_config->name.link_n, current_config->alt_name .tu, current_config->alt_name.gmch_m, current_config->alt_name .gmch_n, current_config->alt_name.link_m, current_config-> alt_name.link_n, pipe_config->name.tu, pipe_config->name .gmch_m, pipe_config->name.gmch_n, pipe_config->name.link_m , pipe_config->name.link_n); ret = 0; } } while (0) do { \ |
| 13791 | if (!intel_compare_link_m_n(¤t_config->name, \ |
| 13792 | &pipe_config->name, !fastset) && \ |
| 13793 | !intel_compare_link_m_n(¤t_config->alt_name, \ |
| 13794 | &pipe_config->name, !fastset)) { \ |
| 13795 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13796 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
| 13797 | "or tu %i gmch %i/%i link %i/%i, " \ |
| 13798 | "found tu %i, gmch %i/%i link %i/%i)", \ |
| 13799 | current_config->name.tu, \ |
| 13800 | current_config->name.gmch_m, \ |
| 13801 | current_config->name.gmch_n, \ |
| 13802 | current_config->name.link_m, \ |
| 13803 | current_config->name.link_n, \ |
| 13804 | current_config->alt_name.tu, \ |
| 13805 | current_config->alt_name.gmch_m, \ |
| 13806 | current_config->alt_name.gmch_n, \ |
| 13807 | current_config->alt_name.link_m, \ |
| 13808 | current_config->alt_name.link_n, \ |
| 13809 | pipe_config->name.tu, \ |
| 13810 | pipe_config->name.gmch_m, \ |
| 13811 | pipe_config->name.gmch_n, \ |
| 13812 | pipe_config->name.link_m, \ |
| 13813 | pipe_config->name.link_n); \ |
| 13814 | ret = false0; \ |
| 13815 | } \ |
| 13816 | } while (0) |
| 13817 | |
| 13818 | #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \ |
| 13819 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ |
| 13820 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13821 | "(%x) (expected %i, found %i)", \ |
| 13822 | (mask), \ |
| 13823 | current_config->name & (mask), \ |
| 13824 | pipe_config->name & (mask)); \ |
| 13825 | ret = false0; \ |
| 13826 | } \ |
| 13827 | } while (0) |
| 13828 | |
| 13829 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \ |
| 13830 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ |
| 13831 | pipe_config_mismatch(fastset, crtc, __stringify(name)"name", \ |
| 13832 | "(expected %i, found %i)", \ |
| 13833 | current_config->name, \ |
| 13834 | pipe_config->name); \ |
| 13835 | ret = false0; \ |
| 13836 | } \ |
| 13837 | } while (0) |
| 13838 | |
| 13839 | #define PIPE_CONF_CHECK_INFOFRAME(name)do { if (!intel_compare_infoframe(¤t_config->infoframes .name, &pipe_config->infoframes.name)) { pipe_config_infoframe_mismatch (dev_priv, fastset, "name", ¤t_config->infoframes .name, &pipe_config->infoframes.name); ret = 0; } } while (0) do { \ |
| 13840 | if (!intel_compare_infoframe(¤t_config->infoframes.name, \ |
| 13841 | &pipe_config->infoframes.name)) { \ |
| 13842 | pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name)"name", \ |
| 13843 | ¤t_config->infoframes.name, \ |
| 13844 | &pipe_config->infoframes.name); \ |
| 13845 | ret = false0; \ |
| 13846 | } \ |
| 13847 | } while (0) |
| 13848 | |
| 13849 | #define PIPE_CONF_CHECK_DP_VSC_SDP(name)do { if (!current_config->has_psr && !pipe_config-> has_psr && !intel_compare_dp_vsc_sdp(¤t_config ->infoframes.name, &pipe_config->infoframes.name)) { pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, "name", & current_config->infoframes.name, &pipe_config->infoframes .name); ret = 0; } } while (0) do { \ |
| 13850 | if (!current_config->has_psr && !pipe_config->has_psr && \ |
| 13851 | !intel_compare_dp_vsc_sdp(¤t_config->infoframes.name, \ |
| 13852 | &pipe_config->infoframes.name)) { \ |
| 13853 | pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name)"name", \ |
| 13854 | ¤t_config->infoframes.name, \ |
| 13855 | &pipe_config->infoframes.name); \ |
| 13856 | ret = false0; \ |
| 13857 | } \ |
| 13858 | } while (0) |
| 13859 | |
| 13860 | #define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \ |
| 13861 | if (current_config->name1 != pipe_config->name1) { \ |
| 13862 | pipe_config_mismatch(fastset, crtc, __stringify(name1)"name1", \ |
| 13863 | "(expected %i, found %i, won't compare lut values)", \ |
| 13864 | current_config->name1, \ |
| 13865 | pipe_config->name1); \ |
| 13866 | ret = false0;\ |
| 13867 | } else { \ |
| 13868 | if (!intel_color_lut_equal(current_config->name2, \ |
| 13869 | pipe_config->name2, pipe_config->name1, \ |
| 13870 | bit_precision)) { \ |
| 13871 | pipe_config_mismatch(fastset, crtc, __stringify(name2)"name2", \ |
| 13872 | "hw_state doesn't match sw_state"); \ |
| 13873 | ret = false0; \ |
| 13874 | } \ |
| 13875 | } \ |
| 13876 | } while (0) |
| 13877 | |
| 13878 | #define PIPE_CONF_QUIRK(quirk) \ |
| 13879 | ((current_config->quirks | pipe_config->quirks) & (quirk)) |
| 13880 | |
| 13881 | PIPE_CONF_CHECK_I(cpu_transcoder); |
| 13882 | |
| 13883 | PIPE_CONF_CHECK_BOOL(has_pch_encoder); |
| 13884 | PIPE_CONF_CHECK_I(fdi_lanes); |
| 13885 | PIPE_CONF_CHECK_M_N(fdi_m_n)do { if (!intel_compare_link_m_n(¤t_config->fdi_m_n , &pipe_config->fdi_m_n, !fastset)) { pipe_config_mismatch (fastset, crtc, "fdi_m_n", "(expected tu %i gmch %i/%i link %i/%i, " "found tu %i, gmch %i/%i link %i/%i)", current_config->fdi_m_n .tu, current_config->fdi_m_n.gmch_m, current_config->fdi_m_n .gmch_n, current_config->fdi_m_n.link_m, current_config-> fdi_m_n.link_n, pipe_config->fdi_m_n.tu, pipe_config->fdi_m_n .gmch_m, pipe_config->fdi_m_n.gmch_n, pipe_config->fdi_m_n .link_m, pipe_config->fdi_m_n.link_n); ret = 0; } } while ( 0); |
| 13886 | |
| 13887 | PIPE_CONF_CHECK_I(lane_count); |
| 13888 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
| 13889 | |
| 13890 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 8) { |
| 13891 | PIPE_CONF_CHECK_M_N(dp_m_n)do { if (!intel_compare_link_m_n(¤t_config->dp_m_n , &pipe_config->dp_m_n, !fastset)) { pipe_config_mismatch (fastset, crtc, "dp_m_n", "(expected tu %i gmch %i/%i link %i/%i, " "found tu %i, gmch %i/%i link %i/%i)", current_config->dp_m_n .tu, current_config->dp_m_n.gmch_m, current_config->dp_m_n .gmch_n, current_config->dp_m_n.link_m, current_config-> dp_m_n.link_n, pipe_config->dp_m_n.tu, pipe_config->dp_m_n .gmch_m, pipe_config->dp_m_n.gmch_n, pipe_config->dp_m_n .link_m, pipe_config->dp_m_n.link_n); ret = 0; } } while ( 0); |
| 13892 | |
| 13893 | if (current_config->has_drrs) |
| 13894 | PIPE_CONF_CHECK_M_N(dp_m2_n2)do { if (!intel_compare_link_m_n(¤t_config->dp_m2_n2 , &pipe_config->dp_m2_n2, !fastset)) { pipe_config_mismatch (fastset, crtc, "dp_m2_n2", "(expected tu %i gmch %i/%i link %i/%i, " "found tu %i, gmch %i/%i link %i/%i)", current_config->dp_m2_n2 .tu, current_config->dp_m2_n2.gmch_m, current_config->dp_m2_n2 .gmch_n, current_config->dp_m2_n2.link_m, current_config-> dp_m2_n2.link_n, pipe_config->dp_m2_n2.tu, pipe_config-> dp_m2_n2.gmch_m, pipe_config->dp_m2_n2.gmch_n, pipe_config ->dp_m2_n2.link_m, pipe_config->dp_m2_n2.link_n); ret = 0; } } while (0); |
| 13895 | } else |
| 13896 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2)do { if (!intel_compare_link_m_n(¤t_config->dp_m_n , &pipe_config->dp_m_n, !fastset) && !intel_compare_link_m_n (¤t_config->dp_m2_n2, &pipe_config->dp_m_n , !fastset)) { pipe_config_mismatch(fastset, crtc, "dp_m_n", "(expected tu %i gmch %i/%i link %i/%i, " "or tu %i gmch %i/%i link %i/%i, " "found tu %i, gmch %i/%i link %i/%i)" , current_config->dp_m_n.tu, current_config->dp_m_n.gmch_m , current_config->dp_m_n.gmch_n, current_config->dp_m_n .link_m, current_config->dp_m_n.link_n, current_config-> dp_m2_n2.tu, current_config->dp_m2_n2.gmch_m, current_config ->dp_m2_n2.gmch_n, current_config->dp_m2_n2.link_m, current_config ->dp_m2_n2.link_n, pipe_config->dp_m_n.tu, pipe_config-> dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, pipe_config-> dp_m_n.link_m, pipe_config->dp_m_n.link_n); ret = 0; } } while (0); |
| 13897 | |
| 13898 | PIPE_CONF_CHECK_X(output_types); |
| 13899 | |
| 13900 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); |
| 13901 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); |
| 13902 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); |
| 13903 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); |
| 13904 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); |
| 13905 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); |
| 13906 | |
| 13907 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); |
| 13908 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); |
| 13909 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); |
| 13910 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); |
| 13911 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); |
| 13912 | PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); |
| 13913 | |
| 13914 | PIPE_CONF_CHECK_I(pixel_multiplier); |
| 13915 | PIPE_CONF_CHECK_I(output_format); |
| 13916 | PIPE_CONF_CHECK_BOOL(has_hdmi_sink); |
| 13917 | if ((INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 8 && !IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) || |
| 13918 | IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 13919 | PIPE_CONF_CHECK_BOOL(limited_color_range); |
| 13920 | |
| 13921 | PIPE_CONF_CHECK_BOOL(hdmi_scrambling); |
| 13922 | PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio); |
| 13923 | PIPE_CONF_CHECK_BOOL(has_infoframe); |
| 13924 | PIPE_CONF_CHECK_BOOL(fec_enable); |
| 13925 | |
| 13926 | PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio); |
| 13927 | |
| 13928 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
| 13929 | DRM_MODE_FLAG_INTERLACE(1<<4)); |
| 13930 | |
| 13931 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS(1<<0))) { |
| 13932 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
| 13933 | DRM_MODE_FLAG_PHSYNC(1<<0)); |
| 13934 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
| 13935 | DRM_MODE_FLAG_NHSYNC(1<<1)); |
| 13936 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
| 13937 | DRM_MODE_FLAG_PVSYNC(1<<2)); |
| 13938 | PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags, |
| 13939 | DRM_MODE_FLAG_NVSYNC(1<<3)); |
| 13940 | } |
| 13941 | |
| 13942 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
| 13943 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
| 13944 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4) |
| 13945 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
| 13946 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
| 13947 | |
| 13948 | /* |
| 13949 | * Changing the EDP transcoder input mux |
| 13950 | * (A_ONOFF vs. A_ON) requires a full modeset. |
| 13951 | */ |
| 13952 | PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru); |
| 13953 | |
| 13954 | if (!fastset) { |
| 13955 | PIPE_CONF_CHECK_I(pipe_src_w); |
| 13956 | PIPE_CONF_CHECK_I(pipe_src_h); |
| 13957 | |
| 13958 | PIPE_CONF_CHECK_BOOL(pch_pfit.enabled); |
| 13959 | if (current_config->pch_pfit.enabled) { |
| 13960 | PIPE_CONF_CHECK_I(pch_pfit.dst.x1); |
| 13961 | PIPE_CONF_CHECK_I(pch_pfit.dst.y1); |
| 13962 | PIPE_CONF_CHECK_I(pch_pfit.dst.x2); |
| 13963 | PIPE_CONF_CHECK_I(pch_pfit.dst.y2); |
| 13964 | } |
| 13965 | |
| 13966 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
| 13967 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
| 13968 | |
| 13969 | PIPE_CONF_CHECK_X(gamma_mode); |
| 13970 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 13971 | PIPE_CONF_CHECK_X(cgm_mode); |
| 13972 | else |
| 13973 | PIPE_CONF_CHECK_X(csc_mode); |
| 13974 | PIPE_CONF_CHECK_BOOL(gamma_enable); |
| 13975 | PIPE_CONF_CHECK_BOOL(csc_enable); |
| 13976 | |
| 13977 | PIPE_CONF_CHECK_I(linetime); |
| 13978 | PIPE_CONF_CHECK_I(ips_linetime); |
| 13979 | |
| 13980 | bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); |
| 13981 | if (bp_gamma) |
| 13982 | PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); |
| 13983 | } |
| 13984 | |
| 13985 | PIPE_CONF_CHECK_BOOL(double_wide); |
| 13986 | |
| 13987 | PIPE_CONF_CHECK_P(shared_dpll); |
| 13988 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
| 13989 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
| 13990 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
| 13991 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); |
| 13992 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
| 13993 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
| 13994 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
| 13995 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); |
| 13996 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); |
| 13997 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); |
| 13998 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); |
| 13999 | PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); |
| 14000 | PIPE_CONF_CHECK_X(dpll_hw_state.pll0); |
| 14001 | PIPE_CONF_CHECK_X(dpll_hw_state.pll1); |
| 14002 | PIPE_CONF_CHECK_X(dpll_hw_state.pll2); |
| 14003 | PIPE_CONF_CHECK_X(dpll_hw_state.pll3); |
| 14004 | PIPE_CONF_CHECK_X(dpll_hw_state.pll6); |
| 14005 | PIPE_CONF_CHECK_X(dpll_hw_state.pll8); |
| 14006 | PIPE_CONF_CHECK_X(dpll_hw_state.pll9); |
| 14007 | PIPE_CONF_CHECK_X(dpll_hw_state.pll10); |
| 14008 | PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); |
| 14009 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl); |
| 14010 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1); |
| 14011 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); |
| 14012 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0); |
| 14013 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1); |
| 14014 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf); |
| 14015 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock); |
| 14016 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc); |
| 14017 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias); |
| 14018 | PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias); |
| 14019 | |
| 14020 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
| 14021 | PIPE_CONF_CHECK_X(dsi_pll.div); |
| 14022 | |
| 14023 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) || INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) |
| 14024 | PIPE_CONF_CHECK_I(pipe_bpp); |
| 14025 | |
| 14026 | PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock); |
| 14027 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
| 14028 | |
| 14029 | PIPE_CONF_CHECK_I(min_voltage_level); |
| 14030 | |
| 14031 | PIPE_CONF_CHECK_X(infoframes.enable); |
| 14032 | PIPE_CONF_CHECK_X(infoframes.gcp); |
| 14033 | PIPE_CONF_CHECK_INFOFRAME(avi)do { if (!intel_compare_infoframe(¤t_config->infoframes .avi, &pipe_config->infoframes.avi)) { pipe_config_infoframe_mismatch (dev_priv, fastset, "avi", ¤t_config->infoframes .avi, &pipe_config->infoframes.avi); ret = 0; } } while (0); |
| 14034 | PIPE_CONF_CHECK_INFOFRAME(spd)do { if (!intel_compare_infoframe(¤t_config->infoframes .spd, &pipe_config->infoframes.spd)) { pipe_config_infoframe_mismatch (dev_priv, fastset, "spd", ¤t_config->infoframes .spd, &pipe_config->infoframes.spd); ret = 0; } } while (0); |
| 14035 | PIPE_CONF_CHECK_INFOFRAME(hdmi)do { if (!intel_compare_infoframe(¤t_config->infoframes .hdmi, &pipe_config->infoframes.hdmi)) { pipe_config_infoframe_mismatch (dev_priv, fastset, "hdmi", ¤t_config->infoframes .hdmi, &pipe_config->infoframes.hdmi); ret = 0; } } while (0); |
| 14036 | PIPE_CONF_CHECK_INFOFRAME(drm)do { if (!intel_compare_infoframe(¤t_config->infoframes .drm, &pipe_config->infoframes.drm)) { pipe_config_infoframe_mismatch (dev_priv, fastset, "drm", ¤t_config->infoframes .drm, &pipe_config->infoframes.drm); ret = 0; } } while (0); |
| 14037 | PIPE_CONF_CHECK_DP_VSC_SDP(vsc)do { if (!current_config->has_psr && !pipe_config-> has_psr && !intel_compare_dp_vsc_sdp(¤t_config ->infoframes.vsc, &pipe_config->infoframes.vsc)) { pipe_config_dp_vsc_sdp_mismatch (dev_priv, fastset, "vsc", ¤t_config->infoframes .vsc, &pipe_config->infoframes.vsc); ret = 0; } } while (0); |
| 14038 | |
| 14039 | PIPE_CONF_CHECK_X(sync_mode_slaves_mask); |
| 14040 | PIPE_CONF_CHECK_I(master_transcoder); |
| 14041 | |
| 14042 | PIPE_CONF_CHECK_I(dsc.compression_enable); |
| 14043 | PIPE_CONF_CHECK_I(dsc.dsc_split); |
| 14044 | PIPE_CONF_CHECK_I(dsc.compressed_bpp); |
| 14045 | |
| 14046 | PIPE_CONF_CHECK_I(mst_master_transcoder); |
| 14047 | |
| 14048 | #undef PIPE_CONF_CHECK_X |
| 14049 | #undef PIPE_CONF_CHECK_I |
| 14050 | #undef PIPE_CONF_CHECK_BOOL |
| 14051 | #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE |
| 14052 | #undef PIPE_CONF_CHECK_P |
| 14053 | #undef PIPE_CONF_CHECK_FLAGS |
| 14054 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
| 14055 | #undef PIPE_CONF_CHECK_COLOR_LUT |
| 14056 | #undef PIPE_CONF_QUIRK |
| 14057 | |
| 14058 | return ret; |
| 14059 | } |
| 14060 | |
| 14061 | static void intel_pipe_config_sanity_check(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 14062 | const struct intel_crtc_state *pipe_config) |
| 14063 | { |
| 14064 | if (pipe_config->has_pch_encoder) { |
| 14065 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
| 14066 | &pipe_config->fdi_m_n); |
| 14067 | int dotclock = pipe_config->hw.adjusted_mode.crtc_clock; |
| 14068 | |
| 14069 | /* |
| 14070 | * FDI already provided one idea for the dotclock. |
| 14071 | * Yell if the encoder disagrees. |
| 14072 | */ |
| 14073 | drm_WARN(&dev_priv->drm,({ int __ret = !!(!intel_fuzzy_clock_check(fdi_dotclock, dotclock )); if (__ret) printf("%s %s: " "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n" , dev_driver_string((&dev_priv->drm)->dev), "", fdi_dotclock , dotclock); __builtin_expect(!!(__ret), 0); }) |
| 14074 | !intel_fuzzy_clock_check(fdi_dotclock, dotclock),({ int __ret = !!(!intel_fuzzy_clock_check(fdi_dotclock, dotclock )); if (__ret) printf("%s %s: " "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n" , dev_driver_string((&dev_priv->drm)->dev), "", fdi_dotclock , dotclock); __builtin_expect(!!(__ret), 0); }) |
| 14075 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",({ int __ret = !!(!intel_fuzzy_clock_check(fdi_dotclock, dotclock )); if (__ret) printf("%s %s: " "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n" , dev_driver_string((&dev_priv->drm)->dev), "", fdi_dotclock , dotclock); __builtin_expect(!!(__ret), 0); }) |
| 14076 | fdi_dotclock, dotclock)({ int __ret = !!(!intel_fuzzy_clock_check(fdi_dotclock, dotclock )); if (__ret) printf("%s %s: " "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n" , dev_driver_string((&dev_priv->drm)->dev), "", fdi_dotclock , dotclock); __builtin_expect(!!(__ret), 0); }); |
| 14077 | } |
| 14078 | } |
| 14079 | |
| 14080 | static void verify_wm_state(struct intel_crtc *crtc, |
| 14081 | struct intel_crtc_state *new_crtc_state) |
| 14082 | { |
| 14083 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 14084 | struct skl_hw_state { |
| 14085 | struct skl_ddb_entry ddb_y[I915_MAX_PLANES]; |
| 14086 | struct skl_ddb_entry ddb_uv[I915_MAX_PLANES]; |
| 14087 | struct skl_pipe_wm wm; |
| 14088 | } *hw; |
| 14089 | struct skl_pipe_wm *sw_wm; |
| 14090 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; |
| 14091 | u8 hw_enabled_slices; |
| 14092 | const enum pipe pipe = crtc->pipe; |
| 14093 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
| 14094 | |
| 14095 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9 || !new_crtc_state->hw.active) |
| 14096 | return; |
| 14097 | |
| 14098 | hw = kzalloc(sizeof(*hw), GFP_KERNEL(0x0001 | 0x0004)); |
| 14099 | if (!hw) |
| 14100 | return; |
| 14101 | |
| 14102 | skl_pipe_wm_get_hw_state(crtc, &hw->wm); |
| 14103 | sw_wm = &new_crtc_state->wm.skl.optimal; |
| 14104 | |
| 14105 | skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv); |
| 14106 | |
| 14107 | hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv); |
| 14108 | |
| 14109 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11 && |
| 14110 | hw_enabled_slices != dev_priv->dbuf.enabled_slices) |
| 14111 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , dev_priv ->dbuf.enabled_slices, hw_enabled_slices) |
| 14112 | "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , dev_priv ->dbuf.enabled_slices, hw_enabled_slices) |
| 14113 | dev_priv->dbuf.enabled_slices,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , dev_priv ->dbuf.enabled_slices, hw_enabled_slices) |
| 14114 | hw_enabled_slices)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , dev_priv ->dbuf.enabled_slices, hw_enabled_slices); |
| 14115 | |
| 14116 | /* planes */ |
| 14117 | for_each_universal_plane(dev_priv, pipe, plane)for ((plane) = 0; (plane) < (&(dev_priv)->__runtime )->num_sprites[(pipe)] + 1; (plane)++) { |
| 14118 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; |
| 14119 | |
| 14120 | hw_plane_wm = &hw->wm.planes[plane]; |
| 14121 | sw_plane_wm = &sw_wm->planes[plane]; |
| 14122 | |
| 14123 | /* Watermarks */ |
| 14124 | for (level = 0; level <= max_level; level++) { |
| 14125 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], |
| 14126 | &sw_plane_wm->wm[level]) || |
| 14127 | (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], |
| 14128 | &sw_plane_wm->sagv_wm0))) |
| 14129 | continue; |
| 14130 | |
| 14131 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14132 | "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14133 | pipe_name(pipe), plane + 1, level,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14134 | sw_plane_wm->wm[level].plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14135 | sw_plane_wm->wm[level].plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14136 | sw_plane_wm->wm[level].plane_res_l,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14137 | hw_plane_wm->wm[level].plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14138 | hw_plane_wm->wm[level].plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ) |
| 14139 | hw_plane_wm->wm[level].plane_res_l)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, level, sw_plane_wm->wm[level].plane_en , sw_plane_wm->wm[level].plane_res_b, sw_plane_wm->wm[level ].plane_res_l, hw_plane_wm->wm[level].plane_en, hw_plane_wm ->wm[level].plane_res_b, hw_plane_wm->wm[level].plane_res_l ); |
| 14140 | } |
| 14141 | |
| 14142 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
| 14143 | &sw_plane_wm->trans_wm)) { |
| 14144 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14145 | "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14146 | pipe_name(pipe), plane + 1,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14147 | sw_plane_wm->trans_wm.plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14148 | sw_plane_wm->trans_wm.plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14149 | sw_plane_wm->trans_wm.plane_res_l,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14150 | hw_plane_wm->trans_wm.plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14151 | hw_plane_wm->trans_wm.plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14152 | hw_plane_wm->trans_wm.plane_res_l)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_plane_wm->trans_wm.plane_en, sw_plane_wm ->trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l , hw_plane_wm->trans_wm.plane_en, hw_plane_wm->trans_wm .plane_res_b, hw_plane_wm->trans_wm.plane_res_l); |
| 14153 | } |
| 14154 | |
| 14155 | /* DDB */ |
| 14156 | hw_ddb_entry = &hw->ddb_y[plane]; |
| 14157 | sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; |
| 14158 | |
| 14159 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
| 14160 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_ddb_entry->start, sw_ddb_entry-> end, hw_ddb_entry->start, hw_ddb_entry->end) |
| 14161 | "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_ddb_entry->start, sw_ddb_entry-> end, hw_ddb_entry->start, hw_ddb_entry->end) |
| 14162 | pipe_name(pipe), plane + 1,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_ddb_entry->start, sw_ddb_entry-> end, hw_ddb_entry->start, hw_ddb_entry->end) |
| 14163 | sw_ddb_entry->start, sw_ddb_entry->end,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_ddb_entry->start, sw_ddb_entry-> end, hw_ddb_entry->start, hw_ddb_entry->end) |
| 14164 | hw_ddb_entry->start, hw_ddb_entry->end)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), plane + 1, sw_ddb_entry->start, sw_ddb_entry-> end, hw_ddb_entry->start, hw_ddb_entry->end); |
| 14165 | } |
| 14166 | } |
| 14167 | |
| 14168 | /* |
| 14169 | * cursor |
| 14170 | * If the cursor plane isn't active, we may not have updated it's ddb |
| 14171 | * allocation. In that case since the ddb allocation will be updated |
| 14172 | * once the plane becomes visible, we can skip this check |
| 14173 | */ |
| 14174 | if (1) { |
| 14175 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; |
| 14176 | |
| 14177 | hw_plane_wm = &hw->wm.planes[PLANE_CURSOR]; |
| 14178 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; |
| 14179 | |
| 14180 | /* Watermarks */ |
| 14181 | for (level = 0; level <= max_level; level++) { |
| 14182 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], |
| 14183 | &sw_plane_wm->wm[level]) || |
| 14184 | (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level], |
| 14185 | &sw_plane_wm->sagv_wm0))) |
| 14186 | continue; |
| 14187 | |
| 14188 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14189 | "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14190 | pipe_name(pipe), level,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14191 | sw_plane_wm->wm[level].plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14192 | sw_plane_wm->wm[level].plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14193 | sw_plane_wm->wm[level].plane_res_l,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14194 | hw_plane_wm->wm[level].plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14195 | hw_plane_wm->wm[level].plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l) |
| 14196 | hw_plane_wm->wm[level].plane_res_l)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), level, sw_plane_wm->wm[level].plane_en, sw_plane_wm ->wm[level].plane_res_b, sw_plane_wm->wm[level].plane_res_l , hw_plane_wm->wm[level].plane_en, hw_plane_wm->wm[level ].plane_res_b, hw_plane_wm->wm[level].plane_res_l); |
| 14197 | } |
| 14198 | |
| 14199 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
| 14200 | &sw_plane_wm->trans_wm)) { |
| 14201 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14202 | "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14203 | pipe_name(pipe),printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14204 | sw_plane_wm->trans_wm.plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14205 | sw_plane_wm->trans_wm.plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14206 | sw_plane_wm->trans_wm.plane_res_l,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14207 | hw_plane_wm->trans_wm.plane_en,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14208 | hw_plane_wm->trans_wm.plane_res_b,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l) |
| 14209 | hw_plane_wm->trans_wm.plane_res_l)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_plane_wm->trans_wm.plane_en, sw_plane_wm-> trans_wm.plane_res_b, sw_plane_wm->trans_wm.plane_res_l, hw_plane_wm ->trans_wm.plane_en, hw_plane_wm->trans_wm.plane_res_b, hw_plane_wm->trans_wm.plane_res_l); |
| 14210 | } |
| 14211 | |
| 14212 | /* DDB */ |
| 14213 | hw_ddb_entry = &hw->ddb_y[PLANE_CURSOR]; |
| 14214 | sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; |
| 14215 | |
| 14216 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
| 14217 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_ddb_entry->start, sw_ddb_entry->end, hw_ddb_entry ->start, hw_ddb_entry->end) |
| 14218 | "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_ddb_entry->start, sw_ddb_entry->end, hw_ddb_entry ->start, hw_ddb_entry->end) |
| 14219 | pipe_name(pipe),printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_ddb_entry->start, sw_ddb_entry->end, hw_ddb_entry ->start, hw_ddb_entry->end) |
| 14220 | sw_ddb_entry->start, sw_ddb_entry->end,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_ddb_entry->start, sw_ddb_entry->end, hw_ddb_entry ->start, hw_ddb_entry->end) |
| 14221 | hw_ddb_entry->start, hw_ddb_entry->end)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A'), sw_ddb_entry->start, sw_ddb_entry->end, hw_ddb_entry ->start, hw_ddb_entry->end); |
| 14222 | } |
| 14223 | } |
| 14224 | |
| 14225 | kfree(hw); |
| 14226 | } |
| 14227 | |
| 14228 | static void |
| 14229 | verify_connector_state(struct intel_atomic_state *state, |
| 14230 | struct intel_crtc *crtc) |
| 14231 | { |
| 14232 | struct drm_connector *connector; |
| 14233 | struct drm_connector_state *new_conn_state; |
| 14234 | int i; |
| 14235 | |
| 14236 | for_each_new_connector_in_state(&state->base, connector, new_conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (new_conn_state) = (&state->base)-> connectors[i].new_state, (void)(new_conn_state) , 1))) {} else { |
| 14237 | struct drm_encoder *encoder = connector->encoder; |
| 14238 | struct intel_crtc_state *crtc_state = NULL((void *)0); |
| 14239 | |
| 14240 | if (new_conn_state->crtc != &crtc->base) |
| 14241 | continue; |
| 14242 | |
| 14243 | if (crtc) |
| 14244 | crtc_state = intel_atomic_get_new_crtc_state(state, crtc); |
| 14245 | |
| 14246 | intel_connector_verify_state(crtc_state, new_conn_state); |
| 14247 | |
| 14248 | I915_STATE_WARN(new_conn_state->best_encoder != encoder,({ int __ret_warn_on = !!(new_conn_state->best_encoder != encoder ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("connector's atomic encoder doesn't match legacy encoder\n") ; __builtin_expect(!!(__ret), 0); })) __drm_err("connector's atomic encoder doesn't match legacy encoder\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14249 | "connector's atomic encoder doesn't match legacy encoder\n")({ int __ret_warn_on = !!(new_conn_state->best_encoder != encoder ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("connector's atomic encoder doesn't match legacy encoder\n") ; __builtin_expect(!!(__ret), 0); })) __drm_err("connector's atomic encoder doesn't match legacy encoder\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14250 | } |
| 14251 | } |
| 14252 | |
| 14253 | static void |
| 14254 | verify_encoder_state(struct drm_i915_privateinteldrm_softc *dev_priv, struct intel_atomic_state *state) |
| 14255 | { |
| 14256 | struct intel_encoder *encoder; |
| 14257 | struct drm_connector *connector; |
| 14258 | struct drm_connector_state *old_conn_state, *new_conn_state; |
| 14259 | int i; |
| 14260 | |
| 14261 | for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) { |
| 14262 | bool_Bool enabled = false0, found = false0; |
| 14263 | enum pipe pipe; |
| 14264 | |
| 14265 | drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s]\n" , encoder->base.base.id, encoder->base.name) |
| 14266 | encoder->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s]\n" , encoder->base.base.id, encoder->base.name) |
| 14267 | encoder->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s]\n" , encoder->base.base.id, encoder->base.name); |
| 14268 | |
| 14269 | for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (old_conn_state) = (&state->base)-> connectors[i].old_state, (new_conn_state) = (&state->base )->connectors[i].new_state, 1))) {} else |
| 14270 | new_conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (old_conn_state) = (&state->base)-> connectors[i].old_state, (new_conn_state) = (&state->base )->connectors[i].new_state, 1))) {} else { |
| 14271 | if (old_conn_state->best_encoder == &encoder->base) |
| 14272 | found = true1; |
| 14273 | |
| 14274 | if (new_conn_state->best_encoder != &encoder->base) |
| 14275 | continue; |
| 14276 | found = enabled = true1; |
| 14277 | |
| 14278 | I915_STATE_WARN(new_conn_state->crtc !=({ int __ret_warn_on = !!(new_conn_state->crtc != encoder-> base.crtc); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("connector's crtc doesn't match encoder crtc\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("connector's crtc doesn't match encoder crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14279 | encoder->base.crtc,({ int __ret_warn_on = !!(new_conn_state->crtc != encoder-> base.crtc); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("connector's crtc doesn't match encoder crtc\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("connector's crtc doesn't match encoder crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14280 | "connector's crtc doesn't match encoder crtc\n")({ int __ret_warn_on = !!(new_conn_state->crtc != encoder-> base.crtc); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("connector's crtc doesn't match encoder crtc\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("connector's crtc doesn't match encoder crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14281 | } |
| 14282 | |
| 14283 | if (!found) |
| 14284 | continue; |
| 14285 | |
| 14286 | I915_STATE_WARN(!!encoder->base.crtc != enabled,({ int __ret_warn_on = !!(!!encoder->base.crtc != enabled) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret ), 0); })) __drm_err("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14287 | "encoder's enabled state mismatch "({ int __ret_warn_on = !!(!!encoder->base.crtc != enabled) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret ), 0); })) __drm_err("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14288 | "(expected %i, found %i)\n",({ int __ret_warn_on = !!(!!encoder->base.crtc != enabled) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret ), 0); })) __drm_err("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14289 | !!encoder->base.crtc, enabled)({ int __ret_warn_on = !!(!!encoder->base.crtc != enabled) ; if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret ), 0); })) __drm_err("encoder's enabled state mismatch " "(expected %i, found %i)\n" , !!encoder->base.crtc, enabled); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 14290 | |
| 14291 | if (!encoder->base.crtc) { |
| 14292 | bool_Bool active; |
| 14293 | |
| 14294 | active = encoder->get_hw_state(encoder, &pipe); |
| 14295 | I915_STATE_WARN(active,({ int __ret_warn_on = !!(active); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("encoder detached but still enabled on pipe %c.\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("encoder detached but still enabled on pipe %c.\n", ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14296 | "encoder detached but still enabled on pipe %c.\n",({ int __ret_warn_on = !!(active); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("encoder detached but still enabled on pipe %c.\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("encoder detached but still enabled on pipe %c.\n", ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14297 | pipe_name(pipe))({ int __ret_warn_on = !!(active); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("encoder detached but still enabled on pipe %c.\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("encoder detached but still enabled on pipe %c.\n", ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14298 | } |
| 14299 | } |
| 14300 | } |
| 14301 | |
| 14302 | static void |
| 14303 | verify_crtc_state(struct intel_crtc *crtc, |
| 14304 | struct intel_crtc_state *old_crtc_state, |
| 14305 | struct intel_crtc_state *new_crtc_state) |
| 14306 | { |
| 14307 | struct drm_device *dev = crtc->base.dev; |
| 14308 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 14309 | struct intel_encoder *encoder; |
| 14310 | struct intel_crtc_state *pipe_config = old_crtc_state; |
| 14311 | struct drm_atomic_state *state = old_crtc_state->uapi.state; |
| 14312 | |
| 14313 | __drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi); |
| 14314 | intel_crtc_free_hw_state(old_crtc_state); |
| 14315 | intel_crtc_state_reset(old_crtc_state, crtc); |
| 14316 | old_crtc_state->uapi.state = state; |
| 14317 | |
| 14318 | drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s]\n" , crtc->base.base.id, crtc->base.name) |
| 14319 | crtc->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s]\n" , crtc->base.base.id, crtc->base.name); |
| 14320 | |
| 14321 | pipe_config->hw.enable = new_crtc_state->hw.enable; |
| 14322 | |
| 14323 | pipe_config->hw.active = |
| 14324 | dev_priv->display.get_pipe_config(crtc, pipe_config); |
| 14325 | |
| 14326 | /* we keep both pipes enabled on 830 */ |
| 14327 | if (IS_I830(dev_priv)IS_PLATFORM(dev_priv, INTEL_I830) && pipe_config->hw.active) |
| 14328 | pipe_config->hw.active = new_crtc_state->hw.active; |
| 14329 | |
| 14330 | I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,({ int __ret_warn_on = !!(new_crtc_state->hw.active != pipe_config ->hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("crtc active state doesn't match with hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, pipe_config ->hw.active); __builtin_expect(!!(__ret), 0); })) __drm_err ("crtc active state doesn't match with hw state " "(expected %i, found %i)\n" , new_crtc_state->hw.active, pipe_config->hw.active); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14331 | "crtc active state doesn't match with hw state "({ int __ret_warn_on = !!(new_crtc_state->hw.active != pipe_config ->hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("crtc active state doesn't match with hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, pipe_config ->hw.active); __builtin_expect(!!(__ret), 0); })) __drm_err ("crtc active state doesn't match with hw state " "(expected %i, found %i)\n" , new_crtc_state->hw.active, pipe_config->hw.active); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14332 | "(expected %i, found %i)\n",({ int __ret_warn_on = !!(new_crtc_state->hw.active != pipe_config ->hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("crtc active state doesn't match with hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, pipe_config ->hw.active); __builtin_expect(!!(__ret), 0); })) __drm_err ("crtc active state doesn't match with hw state " "(expected %i, found %i)\n" , new_crtc_state->hw.active, pipe_config->hw.active); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14333 | new_crtc_state->hw.active, pipe_config->hw.active)({ int __ret_warn_on = !!(new_crtc_state->hw.active != pipe_config ->hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("crtc active state doesn't match with hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, pipe_config ->hw.active); __builtin_expect(!!(__ret), 0); })) __drm_err ("crtc active state doesn't match with hw state " "(expected %i, found %i)\n" , new_crtc_state->hw.active, pipe_config->hw.active); __builtin_expect (!!(__ret_warn_on), 0); }); |
| 14334 | |
| 14335 | I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,({ int __ret_warn_on = !!(crtc->active != new_crtc_state-> hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret), 0); })) __drm_err("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14336 | "transitional active state does not match atomic hw state "({ int __ret_warn_on = !!(crtc->active != new_crtc_state-> hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret), 0); })) __drm_err("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14337 | "(expected %i, found %i)\n",({ int __ret_warn_on = !!(crtc->active != new_crtc_state-> hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret), 0); })) __drm_err("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14338 | new_crtc_state->hw.active, crtc->active)({ int __ret_warn_on = !!(crtc->active != new_crtc_state-> hw.active); if (__builtin_expect(!!(__ret_warn_on), 0)) if (! ({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret ) printf("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret), 0); })) __drm_err("transitional active state does not match atomic hw state " "(expected %i, found %i)\n", new_crtc_state->hw.active, crtc ->active); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14339 | |
| 14340 | for_each_encoder_on_crtc(dev, &crtc->base, encoder)for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *) 0)->base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*(encoder)) *)( (char *)__mptr - __builtin_offsetof (__typeof(*(encoder)), base.head) );}); &(encoder)->base .head != (&(dev)->mode_config.encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder)) *)0)->base.head ) *__mptr = ((encoder)->base.head.next); (__typeof(*(encoder )) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(encoder )), base.head) );})) if (!((encoder)->base.crtc == (&crtc ->base))) {} else { |
| 14341 | enum pipe pipe; |
| 14342 | bool_Bool active; |
| 14343 | |
| 14344 | active = encoder->get_hw_state(encoder, &pipe); |
| 14345 | I915_STATE_WARN(active != new_crtc_state->hw.active,({ int __ret_warn_on = !!(active != new_crtc_state->hw.active ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("[ENCODER:%i] active %i with crtc active %i\n", encoder-> base.base.id, active, new_crtc_state->hw.active); __builtin_expect (!!(__ret), 0); })) __drm_err("[ENCODER:%i] active %i with crtc active %i\n" , encoder->base.base.id, active, new_crtc_state->hw.active ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14346 | "[ENCODER:%i] active %i with crtc active %i\n",({ int __ret_warn_on = !!(active != new_crtc_state->hw.active ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("[ENCODER:%i] active %i with crtc active %i\n", encoder-> base.base.id, active, new_crtc_state->hw.active); __builtin_expect (!!(__ret), 0); })) __drm_err("[ENCODER:%i] active %i with crtc active %i\n" , encoder->base.base.id, active, new_crtc_state->hw.active ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14347 | encoder->base.base.id, active,({ int __ret_warn_on = !!(active != new_crtc_state->hw.active ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("[ENCODER:%i] active %i with crtc active %i\n", encoder-> base.base.id, active, new_crtc_state->hw.active); __builtin_expect (!!(__ret), 0); })) __drm_err("[ENCODER:%i] active %i with crtc active %i\n" , encoder->base.base.id, active, new_crtc_state->hw.active ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14348 | new_crtc_state->hw.active)({ int __ret_warn_on = !!(active != new_crtc_state->hw.active ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("[ENCODER:%i] active %i with crtc active %i\n", encoder-> base.base.id, active, new_crtc_state->hw.active); __builtin_expect (!!(__ret), 0); })) __drm_err("[ENCODER:%i] active %i with crtc active %i\n" , encoder->base.base.id, active, new_crtc_state->hw.active ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14349 | |
| 14350 | I915_STATE_WARN(active && crtc->pipe != pipe,({ int __ret_warn_on = !!(active && crtc->pipe != pipe ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("Encoder connected to wrong pipe %c\n", ((pipe) + 'A')); __builtin_expect (!!(__ret), 0); })) __drm_err("Encoder connected to wrong pipe %c\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14351 | "Encoder connected to wrong pipe %c\n",({ int __ret_warn_on = !!(active && crtc->pipe != pipe ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("Encoder connected to wrong pipe %c\n", ((pipe) + 'A')); __builtin_expect (!!(__ret), 0); })) __drm_err("Encoder connected to wrong pipe %c\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14352 | pipe_name(pipe))({ int __ret_warn_on = !!(active && crtc->pipe != pipe ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("Encoder connected to wrong pipe %c\n", ((pipe) + 'A')); __builtin_expect (!!(__ret), 0); })) __drm_err("Encoder connected to wrong pipe %c\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14353 | |
| 14354 | if (active) |
| 14355 | encoder->get_config(encoder, pipe_config); |
| 14356 | } |
| 14357 | |
| 14358 | intel_crtc_compute_pixel_rate(pipe_config); |
| 14359 | |
| 14360 | if (!new_crtc_state->hw.active) |
| 14361 | return; |
| 14362 | |
| 14363 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
| 14364 | |
| 14365 | if (!intel_pipe_config_compare(new_crtc_state, |
| 14366 | pipe_config, false0)) { |
| 14367 | I915_STATE_WARN(1, "pipe state doesn't match!\n")({ int __ret_warn_on = !!(1); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("pipe state doesn't match!\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pipe state doesn't match!\n"); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14368 | intel_dump_pipe_config(pipe_config, NULL((void *)0), "[hw state]"); |
| 14369 | intel_dump_pipe_config(new_crtc_state, NULL((void *)0), "[sw state]"); |
| 14370 | } |
| 14371 | } |
| 14372 | |
| 14373 | static void |
| 14374 | intel_verify_planes(struct intel_atomic_state *state) |
| 14375 | { |
| 14376 | struct intel_plane *plane; |
| 14377 | const struct intel_plane_state *plane_state; |
| 14378 | int i; |
| 14379 | |
| 14380 | for_each_new_intel_plane_in_state(state, plane,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else |
| 14381 | plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else |
| 14382 | assert_plane(plane, plane_state->planar_slave || |
| 14383 | plane_state->uapi.visible); |
| 14384 | } |
| 14385 | |
| 14386 | static void |
| 14387 | verify_single_dpll_state(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 14388 | struct intel_shared_dpll *pll, |
| 14389 | struct intel_crtc *crtc, |
| 14390 | struct intel_crtc_state *new_crtc_state) |
| 14391 | { |
| 14392 | struct intel_dpll_hw_state dpll_hw_state; |
| 14393 | unsigned int crtc_mask; |
| 14394 | bool_Bool active; |
| 14395 | |
| 14396 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state))__builtin_memset((&dpll_hw_state), (0), (sizeof(dpll_hw_state ))); |
| 14397 | |
| 14398 | drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s\n" , pll->info->name); |
| 14399 | |
| 14400 | active = pll->info->funcs->get_hw_state(dev_priv, pll, &dpll_hw_state); |
| 14401 | |
| 14402 | if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON(1 << 0))) { |
| 14403 | I915_STATE_WARN(!pll->on && pll->active_mask,({ int __ret_warn_on = !!(!pll->on && pll->active_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll in active use but not on in sw tracking\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll in active use but not on in sw tracking\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14404 | "pll in active use but not on in sw tracking\n")({ int __ret_warn_on = !!(!pll->on && pll->active_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll in active use but not on in sw tracking\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll in active use but not on in sw tracking\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14405 | I915_STATE_WARN(pll->on && !pll->active_mask,({ int __ret_warn_on = !!(pll->on && !pll->active_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll is on but not used by any active crtc\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll is on but not used by any active crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14406 | "pll is on but not used by any active crtc\n")({ int __ret_warn_on = !!(pll->on && !pll->active_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll is on but not used by any active crtc\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll is on but not used by any active crtc\n" ); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14407 | I915_STATE_WARN(pll->on != active,({ int __ret_warn_on = !!(pll->on != active); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("pll on state mismatch (expected %i, found %i)\n" , pll->on, active); __builtin_expect(!!(__ret), 0); })) __drm_err ("pll on state mismatch (expected %i, found %i)\n", pll->on , active); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14408 | "pll on state mismatch (expected %i, found %i)\n",({ int __ret_warn_on = !!(pll->on != active); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("pll on state mismatch (expected %i, found %i)\n" , pll->on, active); __builtin_expect(!!(__ret), 0); })) __drm_err ("pll on state mismatch (expected %i, found %i)\n", pll->on , active); __builtin_expect(!!(__ret_warn_on), 0); }) |
| 14409 | pll->on, active)({ int __ret_warn_on = !!(pll->on != active); if (__builtin_expect (!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams .verbose_state_checks); if (__ret) printf("pll on state mismatch (expected %i, found %i)\n" , pll->on, active); __builtin_expect(!!(__ret), 0); })) __drm_err ("pll on state mismatch (expected %i, found %i)\n", pll->on , active); __builtin_expect(!!(__ret_warn_on), 0); }); |
| 14410 | } |
| 14411 | |
| 14412 | if (!crtc) { |
| 14413 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,({ int __ret_warn_on = !!(pll->active_mask & ~pll-> state.crtc_mask); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("more active pll users than references: %x vs %x\n" , pll->active_mask, pll->state.crtc_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("more active pll users than references: %x vs %x\n" , pll->active_mask, pll->state.crtc_mask); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14414 | "more active pll users than references: %x vs %x\n",({ int __ret_warn_on = !!(pll->active_mask & ~pll-> state.crtc_mask); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("more active pll users than references: %x vs %x\n" , pll->active_mask, pll->state.crtc_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("more active pll users than references: %x vs %x\n" , pll->active_mask, pll->state.crtc_mask); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14415 | pll->active_mask, pll->state.crtc_mask)({ int __ret_warn_on = !!(pll->active_mask & ~pll-> state.crtc_mask); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("more active pll users than references: %x vs %x\n" , pll->active_mask, pll->state.crtc_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("more active pll users than references: %x vs %x\n" , pll->active_mask, pll->state.crtc_mask); __builtin_expect (!!(__ret_warn_on), 0); }); |
| 14416 | |
| 14417 | return; |
| 14418 | } |
| 14419 | |
| 14420 | crtc_mask = drm_crtc_mask(&crtc->base); |
| 14421 | |
| 14422 | if (new_crtc_state->hw.active) |
| 14423 | I915_STATE_WARN(!(pll->active_mask & crtc_mask),({ int __ret_warn_on = !!(!(pll->active_mask & crtc_mask )); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (expected pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("pll active mismatch (expected pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14424 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",({ int __ret_warn_on = !!(!(pll->active_mask & crtc_mask )); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (expected pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("pll active mismatch (expected pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14425 | pipe_name(crtc->pipe), pll->active_mask)({ int __ret_warn_on = !!(!(pll->active_mask & crtc_mask )); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (expected pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("pll active mismatch (expected pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret_warn_on), 0); }); |
| 14426 | else |
| 14427 | I915_STATE_WARN(pll->active_mask & crtc_mask,({ int __ret_warn_on = !!(pll->active_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14428 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",({ int __ret_warn_on = !!(pll->active_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14429 | pipe_name(crtc->pipe), pll->active_mask)({ int __ret_warn_on = !!(pll->active_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret), 0); })) __drm_err("pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n" , ((crtc->pipe) + 'A'), pll->active_mask); __builtin_expect (!!(__ret_warn_on), 0); }); |
| 14430 | |
| 14431 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),({ int __ret_warn_on = !!(!(pll->state.crtc_mask & crtc_mask )); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", crtc_mask , pll->state.crtc_mask); __builtin_expect(!!(__ret), 0); } )) __drm_err("pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n" , crtc_mask, pll->state.crtc_mask); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14432 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",({ int __ret_warn_on = !!(!(pll->state.crtc_mask & crtc_mask )); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", crtc_mask , pll->state.crtc_mask); __builtin_expect(!!(__ret), 0); } )) __drm_err("pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n" , crtc_mask, pll->state.crtc_mask); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14433 | crtc_mask, pll->state.crtc_mask)({ int __ret_warn_on = !!(!(pll->state.crtc_mask & crtc_mask )); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", crtc_mask , pll->state.crtc_mask); __builtin_expect(!!(__ret), 0); } )) __drm_err("pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n" , crtc_mask, pll->state.crtc_mask); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 14434 | |
| 14435 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,({ int __ret_warn_on = !!(pll->on && __builtin_memcmp ((&pll->state.hw_state), (&dpll_hw_state), (sizeof (dpll_hw_state)))); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("pll hw state mismatch\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll hw state mismatch\n"); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14436 | &dpll_hw_state,({ int __ret_warn_on = !!(pll->on && __builtin_memcmp ((&pll->state.hw_state), (&dpll_hw_state), (sizeof (dpll_hw_state)))); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("pll hw state mismatch\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll hw state mismatch\n"); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14437 | sizeof(dpll_hw_state)),({ int __ret_warn_on = !!(pll->on && __builtin_memcmp ((&pll->state.hw_state), (&dpll_hw_state), (sizeof (dpll_hw_state)))); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("pll hw state mismatch\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll hw state mismatch\n"); __builtin_expect (!!(__ret_warn_on), 0); }) |
| 14438 | "pll hw state mismatch\n")({ int __ret_warn_on = !!(pll->on && __builtin_memcmp ((&pll->state.hw_state), (&dpll_hw_state), (sizeof (dpll_hw_state)))); if (__builtin_expect(!!(__ret_warn_on), 0 )) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("pll hw state mismatch\n"); __builtin_expect (!!(__ret), 0); })) __drm_err("pll hw state mismatch\n"); __builtin_expect (!!(__ret_warn_on), 0); }); |
| 14439 | } |
| 14440 | |
| 14441 | static void |
| 14442 | verify_shared_dpll_state(struct intel_crtc *crtc, |
| 14443 | struct intel_crtc_state *old_crtc_state, |
| 14444 | struct intel_crtc_state *new_crtc_state) |
| 14445 | { |
| 14446 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 14447 | |
| 14448 | if (new_crtc_state->shared_dpll) |
| 14449 | verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state); |
| 14450 | |
| 14451 | if (old_crtc_state->shared_dpll && |
| 14452 | old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) { |
| 14453 | unsigned int crtc_mask = drm_crtc_mask(&crtc->base); |
| 14454 | struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; |
| 14455 | |
| 14456 | I915_STATE_WARN(pll->active_mask & crtc_mask,({ int __ret_warn_on = !!(pll->active_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (didn't expect pipe %c in active mask)\n" , ((crtc->pipe) + 'A')); __builtin_expect(!!(__ret), 0); } )) __drm_err("pll active mismatch (didn't expect pipe %c in active mask)\n" , ((crtc->pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14457 | "pll active mismatch (didn't expect pipe %c in active mask)\n",({ int __ret_warn_on = !!(pll->active_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (didn't expect pipe %c in active mask)\n" , ((crtc->pipe) + 'A')); __builtin_expect(!!(__ret), 0); } )) __drm_err("pll active mismatch (didn't expect pipe %c in active mask)\n" , ((crtc->pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }) |
| 14458 | pipe_name(crtc->pipe))({ int __ret_warn_on = !!(pll->active_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll active mismatch (didn't expect pipe %c in active mask)\n" , ((crtc->pipe) + 'A')); __builtin_expect(!!(__ret), 0); } )) __drm_err("pll active mismatch (didn't expect pipe %c in active mask)\n" , ((crtc->pipe) + 'A')); __builtin_expect(!!(__ret_warn_on ), 0); }); |
| 14459 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,({ int __ret_warn_on = !!(pll->state.crtc_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll enabled crtcs mismatch (found %x in enabled mask)\n", ( (crtc->pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("pll enabled crtcs mismatch (found %x in enabled mask)\n", ( (crtc->pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0 ); }) |
| 14460 | "pll enabled crtcs mismatch (found %x in enabled mask)\n",({ int __ret_warn_on = !!(pll->state.crtc_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll enabled crtcs mismatch (found %x in enabled mask)\n", ( (crtc->pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("pll enabled crtcs mismatch (found %x in enabled mask)\n", ( (crtc->pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0 ); }) |
| 14461 | pipe_name(crtc->pipe))({ int __ret_warn_on = !!(pll->state.crtc_mask & crtc_mask ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("pll enabled crtcs mismatch (found %x in enabled mask)\n", ( (crtc->pipe) + 'A')); __builtin_expect(!!(__ret), 0); })) __drm_err ("pll enabled crtcs mismatch (found %x in enabled mask)\n", ( (crtc->pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0 ); }); |
| 14462 | } |
| 14463 | } |
| 14464 | |
| 14465 | static void |
| 14466 | intel_modeset_verify_crtc(struct intel_crtc *crtc, |
| 14467 | struct intel_atomic_state *state, |
| 14468 | struct intel_crtc_state *old_crtc_state, |
| 14469 | struct intel_crtc_state *new_crtc_state) |
| 14470 | { |
| 14471 | if (!needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe) |
| 14472 | return; |
| 14473 | |
| 14474 | verify_wm_state(crtc, new_crtc_state); |
| 14475 | verify_connector_state(state, crtc); |
| 14476 | verify_crtc_state(crtc, old_crtc_state, new_crtc_state); |
| 14477 | verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state); |
| 14478 | } |
| 14479 | |
| 14480 | static void |
| 14481 | verify_disabled_dpll_state(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 14482 | { |
| 14483 | int i; |
| 14484 | |
| 14485 | for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) |
| 14486 | verify_single_dpll_state(dev_priv, |
| 14487 | &dev_priv->dpll.shared_dplls[i], |
| 14488 | NULL((void *)0), NULL((void *)0)); |
| 14489 | } |
| 14490 | |
| 14491 | static void |
| 14492 | intel_modeset_verify_disabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 14493 | struct intel_atomic_state *state) |
| 14494 | { |
| 14495 | verify_encoder_state(dev_priv, state); |
| 14496 | verify_connector_state(state, NULL((void *)0)); |
| 14497 | verify_disabled_dpll_state(dev_priv); |
| 14498 | } |
| 14499 | |
| 14500 | static void |
| 14501 | intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state) |
| 14502 | { |
| 14503 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 14504 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 14505 | const struct drm_display_mode *adjusted_mode = |
| 14506 | &crtc_state->hw.adjusted_mode; |
| 14507 | |
| 14508 | drm_calc_timestamping_constants(&crtc->base, adjusted_mode); |
| 14509 | |
| 14510 | crtc->mode_flags = crtc_state->mode_flags; |
| 14511 | |
| 14512 | /* |
| 14513 | * The scanline counter increments at the leading edge of hsync. |
| 14514 | * |
| 14515 | * On most platforms it starts counting from vtotal-1 on the |
| 14516 | * first active line. That means the scanline counter value is |
| 14517 | * always one less than what we would expect. Ie. just after |
| 14518 | * start of vblank, which also occurs at start of hsync (on the |
| 14519 | * last active line), the scanline counter will read vblank_start-1. |
| 14520 | * |
| 14521 | * On gen2 the scanline counter starts counting from 1 instead |
| 14522 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 |
| 14523 | * to keep the value positive), instead of adding one. |
| 14524 | * |
| 14525 | * On HSW+ the behaviour of the scanline counter depends on the output |
| 14526 | * type. For DP ports it behaves like most other platforms, but on HDMI |
| 14527 | * there's an extra 1 line difference. So we need to add two instead of |
| 14528 | * one to the value. |
| 14529 | * |
| 14530 | * On VLV/CHV DSI the scanline counter would appear to increment |
| 14531 | * approx. 1/3 of a scanline before start of vblank. Unfortunately |
| 14532 | * that means we can't tell whether we're in vblank or not while |
| 14533 | * we're on that particular line. We must still set scanline_offset |
| 14534 | * to 1 so that the vblank timestamps come out correct when we query |
| 14535 | * the scanline counter from within the vblank interrupt handler. |
| 14536 | * However if queried just before the start of vblank we'll get an |
| 14537 | * answer that's slightly in the future. |
| 14538 | */ |
| 14539 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) { |
| 14540 | int vtotal; |
| 14541 | |
| 14542 | vtotal = adjusted_mode->crtc_vtotal; |
| 14543 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) |
| 14544 | vtotal /= 2; |
| 14545 | |
| 14546 | crtc->scanline_offset = vtotal - 1; |
| 14547 | } else if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi) && |
| 14548 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
| 14549 | crtc->scanline_offset = 2; |
| 14550 | } else { |
| 14551 | crtc->scanline_offset = 1; |
| 14552 | } |
| 14553 | } |
| 14554 | |
| 14555 | static void intel_modeset_clear_plls(struct intel_atomic_state *state) |
| 14556 | { |
| 14557 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 14558 | struct intel_crtc_state *new_crtc_state; |
| 14559 | struct intel_crtc *crtc; |
| 14560 | int i; |
| 14561 | |
| 14562 | if (!dev_priv->display.crtc_compute_clock) |
| 14563 | return; |
| 14564 | |
| 14565 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14566 | if (!needs_modeset(new_crtc_state)) |
| 14567 | continue; |
| 14568 | |
| 14569 | intel_release_shared_dplls(state, crtc); |
| 14570 | } |
| 14571 | } |
| 14572 | |
| 14573 | /* |
| 14574 | * This implements the workaround described in the "notes" section of the mode |
| 14575 | * set sequence documentation. When going from no pipes or single pipe to |
| 14576 | * multiple pipes, and planes are enabled after the pipe, we need to wait at |
| 14577 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. |
| 14578 | */ |
| 14579 | static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state) |
| 14580 | { |
| 14581 | struct intel_crtc_state *crtc_state; |
| 14582 | struct intel_crtc *crtc; |
| 14583 | struct intel_crtc_state *first_crtc_state = NULL((void *)0); |
| 14584 | struct intel_crtc_state *other_crtc_state = NULL((void *)0); |
| 14585 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; |
| 14586 | int i; |
| 14587 | |
| 14588 | /* look at all crtc's that are going to be enabled in during modeset */ |
| 14589 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14590 | if (!crtc_state->hw.active || |
| 14591 | !needs_modeset(crtc_state)) |
| 14592 | continue; |
| 14593 | |
| 14594 | if (first_crtc_state) { |
| 14595 | other_crtc_state = crtc_state; |
| 14596 | break; |
| 14597 | } else { |
| 14598 | first_crtc_state = crtc_state; |
| 14599 | first_pipe = crtc->pipe; |
| 14600 | } |
| 14601 | } |
| 14602 | |
| 14603 | /* No workaround needed? */ |
| 14604 | if (!first_crtc_state) |
| 14605 | return 0; |
| 14606 | |
| 14607 | /* w/a possibly needed, check how many crtc's are already enabled. */ |
| 14608 | for_each_intel_crtc(state->base.dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(state->base.dev)->mode_config .crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(state->base.dev)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), base.head) );})) { |
| 14609 | crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); |
| 14610 | if (IS_ERR(crtc_state)) |
| 14611 | return PTR_ERR(crtc_state); |
| 14612 | |
| 14613 | crtc_state->hsw_workaround_pipe = INVALID_PIPE; |
| 14614 | |
| 14615 | if (!crtc_state->hw.active || |
| 14616 | needs_modeset(crtc_state)) |
| 14617 | continue; |
| 14618 | |
| 14619 | /* 2 or more enabled crtcs means no need for w/a */ |
| 14620 | if (enabled_pipe != INVALID_PIPE) |
| 14621 | return 0; |
| 14622 | |
| 14623 | enabled_pipe = crtc->pipe; |
| 14624 | } |
| 14625 | |
| 14626 | if (enabled_pipe != INVALID_PIPE) |
| 14627 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; |
| 14628 | else if (other_crtc_state) |
| 14629 | other_crtc_state->hsw_workaround_pipe = first_pipe; |
| 14630 | |
| 14631 | return 0; |
| 14632 | } |
| 14633 | |
| 14634 | u8 intel_calc_active_pipes(struct intel_atomic_state *state, |
| 14635 | u8 active_pipes) |
| 14636 | { |
| 14637 | const struct intel_crtc_state *crtc_state; |
| 14638 | struct intel_crtc *crtc; |
| 14639 | int i; |
| 14640 | |
| 14641 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14642 | if (crtc_state->hw.active) |
| 14643 | active_pipes |= BIT(crtc->pipe)(1UL << (crtc->pipe)); |
| 14644 | else |
| 14645 | active_pipes &= ~BIT(crtc->pipe)(1UL << (crtc->pipe)); |
| 14646 | } |
| 14647 | |
| 14648 | return active_pipes; |
| 14649 | } |
| 14650 | |
| 14651 | static int intel_modeset_checks(struct intel_atomic_state *state) |
| 14652 | { |
| 14653 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 14654 | |
| 14655 | state->modeset = true1; |
| 14656 | |
| 14657 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 14658 | return hsw_mode_set_planes_workaround(state); |
| 14659 | |
| 14660 | return 0; |
| 14661 | } |
| 14662 | |
| 14663 | /* |
| 14664 | * Handle calculation of various watermark data at the end of the atomic check |
| 14665 | * phase. The code here should be run after the per-crtc and per-plane 'check' |
| 14666 | * handlers to ensure that all derived state has been updated. |
| 14667 | */ |
| 14668 | static int calc_watermark_data(struct intel_atomic_state *state) |
| 14669 | { |
| 14670 | struct drm_device *dev = state->base.dev; |
| 14671 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 14672 | |
| 14673 | /* Is there platform-specific watermark information to calculate? */ |
| 14674 | if (dev_priv->display.compute_global_watermarks) |
| 14675 | return dev_priv->display.compute_global_watermarks(state); |
| 14676 | |
| 14677 | return 0; |
| 14678 | } |
| 14679 | |
| 14680 | static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state, |
| 14681 | struct intel_crtc_state *new_crtc_state) |
| 14682 | { |
| 14683 | if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true1)) |
| 14684 | return; |
| 14685 | |
| 14686 | new_crtc_state->uapi.mode_changed = false0; |
| 14687 | new_crtc_state->update_pipe = true1; |
| 14688 | } |
| 14689 | |
| 14690 | static void intel_crtc_copy_fastset(const struct intel_crtc_state *old_crtc_state, |
| 14691 | struct intel_crtc_state *new_crtc_state) |
| 14692 | { |
| 14693 | /* |
| 14694 | * If we're not doing the full modeset we want to |
| 14695 | * keep the current M/N values as they may be |
| 14696 | * sufficiently different to the computed values |
| 14697 | * to cause problems. |
| 14698 | * |
| 14699 | * FIXME: should really copy more fuzzy state here |
| 14700 | */ |
| 14701 | new_crtc_state->fdi_m_n = old_crtc_state->fdi_m_n; |
| 14702 | new_crtc_state->dp_m_n = old_crtc_state->dp_m_n; |
| 14703 | new_crtc_state->dp_m2_n2 = old_crtc_state->dp_m2_n2; |
| 14704 | new_crtc_state->has_drrs = old_crtc_state->has_drrs; |
| 14705 | } |
| 14706 | |
| 14707 | static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state, |
| 14708 | struct intel_crtc *crtc, |
| 14709 | u8 plane_ids_mask) |
| 14710 | { |
| 14711 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 14712 | struct intel_plane *plane; |
| 14713 | |
| 14714 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane), base.head) );}); &plane ->base.head != (&(&dev_priv->drm)->mode_config .plane_list); plane = ({ const __typeof( ((__typeof(*plane) * )0)->base.head ) *__mptr = (plane->base.head.next); (__typeof (*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane ), base.head) );})) if (!((plane)->pipe == (crtc)->pipe )) {} else { |
| 14715 | struct intel_plane_state *plane_state; |
| 14716 | |
| 14717 | if ((plane_ids_mask & BIT(plane->id)(1UL << (plane->id))) == 0) |
| 14718 | continue; |
| 14719 | |
| 14720 | plane_state = intel_atomic_get_plane_state(state, plane); |
| 14721 | if (IS_ERR(plane_state)) |
| 14722 | return PTR_ERR(plane_state); |
| 14723 | } |
| 14724 | |
| 14725 | return 0; |
| 14726 | } |
| 14727 | |
| 14728 | static bool_Bool active_planes_affects_min_cdclk(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 14729 | { |
| 14730 | /* See {hsw,vlv,ivb}_plane_ratio() */ |
| 14731 | return IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || |
| 14732 | IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || |
| 14733 | IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) || (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11); |
| 14734 | } |
| 14735 | |
| 14736 | static int intel_atomic_check_planes(struct intel_atomic_state *state) |
| 14737 | { |
| 14738 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 14739 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; |
| 14740 | struct intel_plane_state *plane_state; |
| 14741 | struct intel_plane *plane; |
| 14742 | struct intel_crtc *crtc; |
| 14743 | int i, ret; |
| 14744 | |
| 14745 | ret = icl_add_linked_planes(state); |
| 14746 | if (ret) |
| 14747 | return ret; |
| 14748 | |
| 14749 | for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else { |
| 14750 | ret = intel_plane_atomic_check(state, plane); |
| 14751 | if (ret) { |
| 14752 | drm_dbg_atomic(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[PLANE:%d:%s] atomic driver check failed\n" , plane->base.base.id, plane->base.name) |
| 14753 | "[PLANE:%d:%s] atomic driver check failed\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[PLANE:%d:%s] atomic driver check failed\n" , plane->base.base.id, plane->base.name) |
| 14754 | plane->base.base.id, plane->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "[PLANE:%d:%s] atomic driver check failed\n" , plane->base.base.id, plane->base.name); |
| 14755 | return ret; |
| 14756 | } |
| 14757 | } |
| 14758 | |
| 14759 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 14760 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14761 | u8 old_active_planes, new_active_planes; |
| 14762 | |
| 14763 | ret = icl_check_nv12_planes(new_crtc_state); |
| 14764 | if (ret) |
| 14765 | return ret; |
| 14766 | |
| 14767 | /* |
| 14768 | * On some platforms the number of active planes affects |
| 14769 | * the planes' minimum cdclk calculation. Add such planes |
| 14770 | * to the state before we compute the minimum cdclk. |
| 14771 | */ |
| 14772 | if (!active_planes_affects_min_cdclk(dev_priv)) |
| 14773 | continue; |
| 14774 | |
| 14775 | old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR)(1UL << (PLANE_CURSOR)); |
| 14776 | new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR)(1UL << (PLANE_CURSOR)); |
| 14777 | |
| 14778 | /* |
| 14779 | * Not only the number of planes, but if the plane configuration had |
| 14780 | * changed might already mean we need to recompute min CDCLK, |
| 14781 | * because different planes might consume different amount of Dbuf bandwidth |
| 14782 | * according to formula: Bw per plane = Pixel rate * bpp * pipe/plane scale factor |
| 14783 | */ |
| 14784 | if (old_active_planes == new_active_planes) |
| 14785 | continue; |
| 14786 | |
| 14787 | ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes); |
| 14788 | if (ret) |
| 14789 | return ret; |
| 14790 | } |
| 14791 | |
| 14792 | return 0; |
| 14793 | } |
| 14794 | |
| 14795 | static int intel_atomic_check_cdclk(struct intel_atomic_state *state, |
| 14796 | bool_Bool *need_cdclk_calc) |
| 14797 | { |
| 14798 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 14799 | const struct intel_cdclk_state *old_cdclk_state; |
| 14800 | const struct intel_cdclk_state *new_cdclk_state; |
| 14801 | struct intel_plane_state *plane_state; |
| 14802 | struct intel_bw_state *new_bw_state; |
| 14803 | struct intel_plane *plane; |
| 14804 | int min_cdclk = 0; |
| 14805 | enum pipe pipe; |
| 14806 | int ret; |
| 14807 | int i; |
| 14808 | /* |
| 14809 | * active_planes bitmask has been updated, and potentially |
| 14810 | * affected planes are part of the state. We can now |
| 14811 | * compute the minimum cdclk for each plane. |
| 14812 | */ |
| 14813 | for_each_new_intel_plane_in_state(state, plane, plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (plane_state) = ({ const __typeof( ( (struct intel_plane_state *)0)->uapi ) *__mptr = ((state)-> base.planes[i].new_state); (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}), 1); (i)++) if (!(plane)) {} else { |
| 14814 | ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc); |
| 14815 | if (ret) |
| 14816 | return ret; |
| 14817 | } |
| 14818 | |
| 14819 | old_cdclk_state = intel_atomic_get_old_cdclk_state(state)({ const __typeof( ((struct intel_cdclk_state *)0)->base ) *__mptr = ((intel_atomic_get_old_global_obj_state(state, & to_i915(state->base.dev)->cdclk.obj))); (struct intel_cdclk_state *)( (char *)__mptr - __builtin_offsetof(struct intel_cdclk_state , base) );}); |
| 14820 | new_cdclk_state = intel_atomic_get_new_cdclk_state(state)({ const __typeof( ((struct intel_cdclk_state *)0)->base ) *__mptr = ((intel_atomic_get_new_global_obj_state(state, & to_i915(state->base.dev)->cdclk.obj))); (struct intel_cdclk_state *)( (char *)__mptr - __builtin_offsetof(struct intel_cdclk_state , base) );}); |
| 14821 | |
| 14822 | if (new_cdclk_state && |
| 14823 | old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) |
| 14824 | *need_cdclk_calc = true1; |
| 14825 | |
| 14826 | ret = dev_priv->display.bw_calc_min_cdclk(state); |
| 14827 | if (ret) |
| 14828 | return ret; |
| 14829 | |
| 14830 | new_bw_state = intel_atomic_get_new_bw_state(state); |
| 14831 | |
| 14832 | if (!new_cdclk_state || !new_bw_state) |
| 14833 | return 0; |
| 14834 | |
| 14835 | for_each_pipe(dev_priv, pipe)for ((pipe) = 0; (pipe) < I915_MAX_PIPES; (pipe)++) if (!( (&(dev_priv)->__info)->pipe_mask & (1UL << (pipe)))) {} else { |
| 14836 | min_cdclk = max(new_cdclk_state->min_cdclk[pipe], min_cdclk)(((new_cdclk_state->min_cdclk[pipe])>(min_cdclk))?(new_cdclk_state ->min_cdclk[pipe]):(min_cdclk)); |
| 14837 | |
| 14838 | /* |
| 14839 | * Currently do this change only if we need to increase |
| 14840 | */ |
| 14841 | if (new_bw_state->min_cdclk > min_cdclk) |
| 14842 | *need_cdclk_calc = true1; |
| 14843 | } |
| 14844 | |
| 14845 | return 0; |
| 14846 | } |
| 14847 | |
| 14848 | static int intel_atomic_check_crtcs(struct intel_atomic_state *state) |
| 14849 | { |
| 14850 | struct intel_crtc_state *crtc_state; |
| 14851 | struct intel_crtc *crtc; |
| 14852 | int i; |
| 14853 | |
| 14854 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14855 | int ret = intel_crtc_atomic_check(state, crtc); |
| 14856 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev); |
| 14857 | if (ret) { |
| 14858 | drm_dbg_atomic(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] atomic driver check failed\n" , crtc->base.base.id, crtc->base.name) |
| 14859 | "[CRTC:%d:%s] atomic driver check failed\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] atomic driver check failed\n" , crtc->base.base.id, crtc->base.name) |
| 14860 | crtc->base.base.id, crtc->base.name)drm_dev_dbg((&i915->drm)->dev, DRM_UT_ATOMIC, "[CRTC:%d:%s] atomic driver check failed\n" , crtc->base.base.id, crtc->base.name); |
| 14861 | return ret; |
| 14862 | } |
| 14863 | } |
| 14864 | |
| 14865 | return 0; |
| 14866 | } |
| 14867 | |
| 14868 | static bool_Bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state, |
| 14869 | u8 transcoders) |
| 14870 | { |
| 14871 | const struct intel_crtc_state *new_crtc_state; |
| 14872 | struct intel_crtc *crtc; |
| 14873 | int i; |
| 14874 | |
| 14875 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14876 | if (new_crtc_state->hw.enable && |
| 14877 | transcoders & BIT(new_crtc_state->cpu_transcoder)(1UL << (new_crtc_state->cpu_transcoder)) && |
| 14878 | needs_modeset(new_crtc_state)) |
| 14879 | return true1; |
| 14880 | } |
| 14881 | |
| 14882 | return false0; |
| 14883 | } |
| 14884 | |
| 14885 | /** |
| 14886 | * intel_atomic_check - validate state object |
| 14887 | * @dev: drm device |
| 14888 | * @_state: state to validate |
| 14889 | */ |
| 14890 | static int intel_atomic_check(struct drm_device *dev, |
| 14891 | struct drm_atomic_state *_state) |
| 14892 | { |
| 14893 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 14894 | struct intel_atomic_state *state = to_intel_atomic_state(_state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (_state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state, base) );}); |
| 14895 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; |
| 14896 | struct intel_crtc *crtc; |
| 14897 | int ret, i; |
| 14898 | bool_Bool any_ms = false0; |
| 14899 | |
| 14900 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 14901 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14902 | if (new_crtc_state->inherited != old_crtc_state->inherited) |
| 14903 | new_crtc_state->uapi.mode_changed = true1; |
| 14904 | } |
| 14905 | |
| 14906 | ret = drm_atomic_helper_check_modeset(dev, &state->base); |
| 14907 | if (ret) |
| 14908 | goto fail; |
| 14909 | |
| 14910 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 14911 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14912 | if (!needs_modeset(new_crtc_state)) { |
| 14913 | /* Light copy */ |
| 14914 | intel_crtc_copy_uapi_to_hw_state_nomodeset(new_crtc_state); |
| 14915 | |
| 14916 | continue; |
| 14917 | } |
| 14918 | |
| 14919 | ret = intel_crtc_prepare_cleared_state(new_crtc_state); |
| 14920 | if (ret) |
| 14921 | goto fail; |
| 14922 | |
| 14923 | if (!new_crtc_state->hw.enable) |
| 14924 | continue; |
| 14925 | |
| 14926 | ret = intel_modeset_pipe_config(new_crtc_state); |
| 14927 | if (ret) |
| 14928 | goto fail; |
| 14929 | } |
| 14930 | |
| 14931 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 14932 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14933 | if (!needs_modeset(new_crtc_state)) |
| 14934 | continue; |
| 14935 | |
| 14936 | ret = intel_modeset_pipe_config_late(new_crtc_state); |
| 14937 | if (ret) |
| 14938 | goto fail; |
| 14939 | |
| 14940 | intel_crtc_check_fastset(old_crtc_state, new_crtc_state); |
| 14941 | } |
| 14942 | |
| 14943 | /** |
| 14944 | * Check if fastset is allowed by external dependencies like other |
| 14945 | * pipes and transcoders. |
| 14946 | * |
| 14947 | * Right now it only forces a fullmodeset when the MST master |
| 14948 | * transcoder did not changed but the pipe of the master transcoder |
| 14949 | * needs a fullmodeset so all slaves also needs to do a fullmodeset or |
| 14950 | * in case of port synced crtcs, if one of the synced crtcs |
| 14951 | * needs a full modeset, all other synced crtcs should be |
| 14952 | * forced a full modeset. |
| 14953 | */ |
| 14954 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14955 | if (!new_crtc_state->hw.enable || needs_modeset(new_crtc_state)) |
| 14956 | continue; |
| 14957 | |
| 14958 | if (intel_dp_mst_is_slave_trans(new_crtc_state)) { |
| 14959 | enum transcoder master = new_crtc_state->mst_master_transcoder; |
| 14960 | |
| 14961 | if (intel_cpu_transcoders_need_modeset(state, BIT(master)(1UL << (master)))) { |
| 14962 | new_crtc_state->uapi.mode_changed = true1; |
| 14963 | new_crtc_state->update_pipe = false0; |
| 14964 | } |
| 14965 | } |
| 14966 | |
| 14967 | if (is_trans_port_sync_mode(new_crtc_state)) { |
| 14968 | u8 trans = new_crtc_state->sync_mode_slaves_mask; |
| 14969 | |
| 14970 | if (new_crtc_state->master_transcoder != INVALID_TRANSCODER) |
| 14971 | trans |= BIT(new_crtc_state->master_transcoder)(1UL << (new_crtc_state->master_transcoder)); |
| 14972 | |
| 14973 | if (intel_cpu_transcoders_need_modeset(state, trans)) { |
| 14974 | new_crtc_state->uapi.mode_changed = true1; |
| 14975 | new_crtc_state->update_pipe = false0; |
| 14976 | } |
| 14977 | } |
| 14978 | } |
| 14979 | |
| 14980 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 14981 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 14982 | if (needs_modeset(new_crtc_state)) { |
| 14983 | any_ms = true1; |
| 14984 | continue; |
| 14985 | } |
| 14986 | |
| 14987 | if (!new_crtc_state->update_pipe) |
| 14988 | continue; |
| 14989 | |
| 14990 | intel_crtc_copy_fastset(old_crtc_state, new_crtc_state); |
| 14991 | } |
| 14992 | |
| 14993 | if (any_ms && !check_digital_port_conflicts(state)) { |
| 14994 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "rejecting conflicting digital port configuration\n" ) |
| 14995 | "rejecting conflicting digital port configuration\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "rejecting conflicting digital port configuration\n" ); |
| 14996 | ret = -EINVAL22; |
| 14997 | goto fail; |
| 14998 | } |
| 14999 | |
| 15000 | ret = drm_dp_mst_atomic_check(&state->base); |
| 15001 | if (ret) |
| 15002 | goto fail; |
| 15003 | |
| 15004 | ret = intel_atomic_check_planes(state); |
| 15005 | if (ret) |
| 15006 | goto fail; |
| 15007 | |
| 15008 | /* |
| 15009 | * distrust_bios_wm will force a full dbuf recomputation |
| 15010 | * but the hardware state will only get updated accordingly |
| 15011 | * if state->modeset==true. Hence distrust_bios_wm==true && |
| 15012 | * state->modeset==false is an invalid combination which |
| 15013 | * would cause the hardware and software dbuf state to get |
| 15014 | * out of sync. We must prevent that. |
| 15015 | * |
| 15016 | * FIXME clean up this mess and introduce better |
| 15017 | * state tracking for dbuf. |
| 15018 | */ |
| 15019 | if (dev_priv->wm.distrust_bios_wm) |
| 15020 | any_ms = true1; |
| 15021 | |
| 15022 | intel_fbc_choose_crtc(dev_priv, state); |
| 15023 | ret = calc_watermark_data(state); |
| 15024 | if (ret) |
| 15025 | goto fail; |
| 15026 | |
| 15027 | ret = intel_bw_atomic_check(state); |
| 15028 | if (ret) |
| 15029 | goto fail; |
| 15030 | |
| 15031 | ret = intel_atomic_check_cdclk(state, &any_ms); |
| 15032 | if (ret) |
| 15033 | goto fail; |
| 15034 | |
| 15035 | if (any_ms) { |
| 15036 | ret = intel_modeset_checks(state); |
| 15037 | if (ret) |
| 15038 | goto fail; |
| 15039 | |
| 15040 | ret = intel_modeset_calc_cdclk(state); |
| 15041 | if (ret) |
| 15042 | return ret; |
| 15043 | |
| 15044 | intel_modeset_clear_plls(state); |
| 15045 | } |
| 15046 | |
| 15047 | ret = intel_atomic_check_crtcs(state); |
| 15048 | if (ret) |
| 15049 | goto fail; |
| 15050 | |
| 15051 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15052 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15053 | if (!needs_modeset(new_crtc_state) && |
| 15054 | !new_crtc_state->update_pipe) |
| 15055 | continue; |
| 15056 | |
| 15057 | intel_dump_pipe_config(new_crtc_state, state, |
| 15058 | needs_modeset(new_crtc_state) ? |
| 15059 | "[modeset]" : "[fastset]"); |
| 15060 | } |
| 15061 | |
| 15062 | return 0; |
| 15063 | |
| 15064 | fail: |
| 15065 | if (ret == -EDEADLK11) |
| 15066 | return ret; |
| 15067 | |
| 15068 | /* |
| 15069 | * FIXME would probably be nice to know which crtc specifically |
| 15070 | * caused the failure, in cases where we can pinpoint it. |
| 15071 | */ |
| 15072 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15073 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15074 | intel_dump_pipe_config(new_crtc_state, state, "[failed]"); |
| 15075 | |
| 15076 | return ret; |
| 15077 | } |
| 15078 | |
| 15079 | static int intel_atomic_prepare_commit(struct intel_atomic_state *state) |
| 15080 | { |
| 15081 | struct intel_crtc_state *crtc_state; |
| 15082 | struct intel_crtc *crtc; |
| 15083 | int i, ret; |
| 15084 | |
| 15085 | ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base); |
| 15086 | if (ret < 0) |
| 15087 | return ret; |
| 15088 | |
| 15089 | for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15090 | bool_Bool mode_changed = needs_modeset(crtc_state); |
| 15091 | |
| 15092 | if (mode_changed || crtc_state->update_pipe || |
| 15093 | crtc_state->uapi.color_mgmt_changed) { |
| 15094 | intel_dsb_prepare(crtc_state); |
| 15095 | } |
| 15096 | } |
| 15097 | |
| 15098 | return 0; |
| 15099 | } |
| 15100 | |
| 15101 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
| 15102 | { |
| 15103 | struct drm_device *dev = crtc->base.dev; |
| 15104 | struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; |
| 15105 | |
| 15106 | if (!vblank->max_vblank_count) |
| 15107 | return (u32)drm_crtc_accurate_vblank_count(&crtc->base); |
| 15108 | |
| 15109 | return crtc->base.funcs->get_vblank_counter(&crtc->base); |
| 15110 | } |
| 15111 | |
| 15112 | void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, |
| 15113 | struct intel_crtc_state *crtc_state) |
| 15114 | { |
| 15115 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 15116 | |
| 15117 | if (!IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) || crtc_state->active_planes) |
| 15118 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true1); |
| 15119 | |
| 15120 | if (crtc_state->has_pch_encoder) { |
| 15121 | enum pipe pch_transcoder = |
| 15122 | intel_crtc_pch_transcoder(crtc); |
| 15123 | |
| 15124 | intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true1); |
| 15125 | } |
| 15126 | } |
| 15127 | |
| 15128 | static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state, |
| 15129 | const struct intel_crtc_state *new_crtc_state) |
| 15130 | { |
| 15131 | struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (new_crtc_state->uapi.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 15132 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 15133 | |
| 15134 | /* |
| 15135 | * Update pipe size and adjust fitter if needed: the reason for this is |
| 15136 | * that in compute_mode_changes we check the native mode (not the pfit |
| 15137 | * mode) to see if we can flip rather than do a full mode set. In the |
| 15138 | * fastboot case, we'll flip, but if we don't update the pipesrc and |
| 15139 | * pfit state, we'll end up with a big fb scanned out into the wrong |
| 15140 | * sized surface. |
| 15141 | */ |
| 15142 | intel_set_pipe_src_size(new_crtc_state); |
| 15143 | |
| 15144 | /* on skylake this is done by detaching scalers */ |
| 15145 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) { |
| 15146 | skl_detach_scalers(new_crtc_state); |
| 15147 | |
| 15148 | if (new_crtc_state->pch_pfit.enabled) |
| 15149 | skl_pfit_enable(new_crtc_state); |
| 15150 | } else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 15151 | if (new_crtc_state->pch_pfit.enabled) |
| 15152 | ilk_pfit_enable(new_crtc_state); |
| 15153 | else if (old_crtc_state->pch_pfit.enabled) |
| 15154 | ilk_pfit_disable(old_crtc_state); |
| 15155 | } |
| 15156 | |
| 15157 | /* |
| 15158 | * The register is supposedly single buffered so perhaps |
| 15159 | * not 100% correct to do this here. But SKL+ calculate |
| 15160 | * this based on the adjust pixel rate so pfit changes do |
| 15161 | * affect it and so it must be updated for fastsets. |
| 15162 | * HSW/BDW only really need this here for fastboot, after |
| 15163 | * that the value should not change without a full modeset. |
| 15164 | */ |
| 15165 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || |
| 15166 | IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 15167 | hsw_set_linetime_wm(new_crtc_state); |
| 15168 | |
| 15169 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 15170 | icl_set_pipe_chicken(crtc); |
| 15171 | } |
| 15172 | |
| 15173 | static void commit_pipe_config(struct intel_atomic_state *state, |
| 15174 | struct intel_crtc *crtc) |
| 15175 | { |
| 15176 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 15177 | const struct intel_crtc_state *old_crtc_state = |
| 15178 | intel_atomic_get_old_crtc_state(state, crtc); |
| 15179 | const struct intel_crtc_state *new_crtc_state = |
| 15180 | intel_atomic_get_new_crtc_state(state, crtc); |
| 15181 | bool_Bool modeset = needs_modeset(new_crtc_state); |
| 15182 | |
| 15183 | /* |
| 15184 | * During modesets pipe configuration was programmed as the |
| 15185 | * CRTC was enabled. |
| 15186 | */ |
| 15187 | if (!modeset) { |
| 15188 | if (new_crtc_state->uapi.color_mgmt_changed || |
| 15189 | new_crtc_state->update_pipe) |
| 15190 | intel_color_commit(new_crtc_state); |
| 15191 | |
| 15192 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 15193 | skl_detach_scalers(new_crtc_state); |
| 15194 | |
| 15195 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 15196 | bdw_set_pipemisc(new_crtc_state); |
| 15197 | |
| 15198 | if (new_crtc_state->update_pipe) |
| 15199 | intel_pipe_fastset(old_crtc_state, new_crtc_state); |
| 15200 | |
| 15201 | intel_psr2_program_trans_man_trk_ctl(new_crtc_state); |
| 15202 | } |
| 15203 | |
| 15204 | if (dev_priv->display.atomic_update_watermarks) |
| 15205 | dev_priv->display.atomic_update_watermarks(state, crtc); |
| 15206 | } |
| 15207 | |
| 15208 | static void intel_enable_crtc(struct intel_atomic_state *state, |
| 15209 | struct intel_crtc *crtc) |
| 15210 | { |
| 15211 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 15212 | const struct intel_crtc_state *new_crtc_state = |
| 15213 | intel_atomic_get_new_crtc_state(state, crtc); |
| 15214 | |
| 15215 | if (!needs_modeset(new_crtc_state)) |
| 15216 | return; |
| 15217 | |
| 15218 | intel_crtc_update_active_timings(new_crtc_state); |
| 15219 | |
| 15220 | dev_priv->display.crtc_enable(state, crtc); |
| 15221 | |
| 15222 | /* vblanks work again, re-enable pipe CRC. */ |
| 15223 | intel_crtc_enable_pipe_crc(crtc); |
| 15224 | } |
| 15225 | |
| 15226 | static void intel_update_crtc(struct intel_atomic_state *state, |
| 15227 | struct intel_crtc *crtc) |
| 15228 | { |
| 15229 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 15230 | const struct intel_crtc_state *old_crtc_state = |
| 15231 | intel_atomic_get_old_crtc_state(state, crtc); |
| 15232 | struct intel_crtc_state *new_crtc_state = |
| 15233 | intel_atomic_get_new_crtc_state(state, crtc); |
| 15234 | bool_Bool modeset = needs_modeset(new_crtc_state); |
| 15235 | |
| 15236 | if (!modeset) { |
| 15237 | if (new_crtc_state->preload_luts && |
| 15238 | (new_crtc_state->uapi.color_mgmt_changed || |
| 15239 | new_crtc_state->update_pipe)) |
| 15240 | intel_color_load_luts(new_crtc_state); |
| 15241 | |
| 15242 | intel_pre_plane_update(state, crtc); |
| 15243 | |
| 15244 | if (new_crtc_state->update_pipe) |
| 15245 | intel_encoders_update_pipe(state, crtc); |
| 15246 | } |
| 15247 | |
| 15248 | if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc) |
| 15249 | intel_fbc_disable(crtc); |
| 15250 | else |
| 15251 | intel_fbc_enable(state, crtc); |
| 15252 | |
| 15253 | /* Perform vblank evasion around commit operation */ |
| 15254 | intel_pipe_update_start(new_crtc_state); |
| 15255 | |
| 15256 | commit_pipe_config(state, crtc); |
| 15257 | |
| 15258 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 15259 | skl_update_planes_on_crtc(state, crtc); |
| 15260 | else |
| 15261 | i9xx_update_planes_on_crtc(state, crtc); |
| 15262 | |
| 15263 | intel_pipe_update_end(new_crtc_state); |
| 15264 | |
| 15265 | /* |
| 15266 | * We usually enable FIFO underrun interrupts as part of the |
| 15267 | * CRTC enable sequence during modesets. But when we inherit a |
| 15268 | * valid pipe configuration from the BIOS we need to take care |
| 15269 | * of enabling them on the CRTC's first fastset. |
| 15270 | */ |
| 15271 | if (new_crtc_state->update_pipe && !modeset && |
| 15272 | old_crtc_state->inherited) |
| 15273 | intel_crtc_arm_fifo_underrun(crtc, new_crtc_state); |
| 15274 | } |
| 15275 | |
| 15276 | |
| 15277 | static void intel_old_crtc_state_disables(struct intel_atomic_state *state, |
| 15278 | struct intel_crtc_state *old_crtc_state, |
| 15279 | struct intel_crtc_state *new_crtc_state, |
| 15280 | struct intel_crtc *crtc) |
| 15281 | { |
| 15282 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 15283 | |
| 15284 | intel_crtc_disable_planes(state, crtc); |
| 15285 | |
| 15286 | /* |
| 15287 | * We need to disable pipe CRC before disabling the pipe, |
| 15288 | * or we race against vblank off. |
| 15289 | */ |
| 15290 | intel_crtc_disable_pipe_crc(crtc); |
| 15291 | |
| 15292 | dev_priv->display.crtc_disable(state, crtc); |
| 15293 | crtc->active = false0; |
| 15294 | intel_fbc_disable(crtc); |
| 15295 | intel_disable_shared_dpll(old_crtc_state); |
| 15296 | |
| 15297 | /* FIXME unify this for all platforms */ |
| 15298 | if (!new_crtc_state->hw.active && |
| 15299 | !HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch) && |
| 15300 | dev_priv->display.initial_watermarks) |
| 15301 | dev_priv->display.initial_watermarks(state, crtc); |
| 15302 | } |
| 15303 | |
| 15304 | static void intel_commit_modeset_disables(struct intel_atomic_state *state) |
| 15305 | { |
| 15306 | struct intel_crtc_state *new_crtc_state, *old_crtc_state; |
| 15307 | struct intel_crtc *crtc; |
| 15308 | u32 handled = 0; |
| 15309 | int i; |
| 15310 | |
| 15311 | /* Only disable port sync and MST slaves */ |
| 15312 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15313 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15314 | if (!needs_modeset(new_crtc_state)) |
| 15315 | continue; |
| 15316 | |
| 15317 | if (!old_crtc_state->hw.active) |
| 15318 | continue; |
| 15319 | |
| 15320 | /* In case of Transcoder port Sync master slave CRTCs can be |
| 15321 | * assigned in any order and we need to make sure that |
| 15322 | * slave CRTCs are disabled first and then master CRTC since |
| 15323 | * Slave vblanks are masked till Master Vblanks. |
| 15324 | */ |
| 15325 | if (!is_trans_port_sync_slave(old_crtc_state) && |
| 15326 | !intel_dp_mst_is_slave_trans(old_crtc_state)) |
| 15327 | continue; |
| 15328 | |
| 15329 | intel_pre_plane_update(state, crtc); |
| 15330 | intel_old_crtc_state_disables(state, old_crtc_state, |
| 15331 | new_crtc_state, crtc); |
| 15332 | handled |= BIT(crtc->pipe)(1UL << (crtc->pipe)); |
| 15333 | } |
| 15334 | |
| 15335 | /* Disable everything else left on */ |
| 15336 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15337 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15338 | if (!needs_modeset(new_crtc_state) || |
| 15339 | (handled & BIT(crtc->pipe)(1UL << (crtc->pipe)))) |
| 15340 | continue; |
| 15341 | |
| 15342 | intel_pre_plane_update(state, crtc); |
| 15343 | if (old_crtc_state->hw.active) |
| 15344 | intel_old_crtc_state_disables(state, old_crtc_state, |
| 15345 | new_crtc_state, crtc); |
| 15346 | } |
| 15347 | } |
| 15348 | |
| 15349 | static void intel_commit_modeset_enables(struct intel_atomic_state *state) |
| 15350 | { |
| 15351 | struct intel_crtc_state *new_crtc_state; |
| 15352 | struct intel_crtc *crtc; |
| 15353 | int i; |
| 15354 | |
| 15355 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15356 | if (!new_crtc_state->hw.active) |
| 15357 | continue; |
| 15358 | |
| 15359 | intel_enable_crtc(state, crtc); |
| 15360 | intel_update_crtc(state, crtc); |
| 15361 | } |
| 15362 | } |
| 15363 | |
| 15364 | static void skl_commit_modeset_enables(struct intel_atomic_state *state) |
| 15365 | { |
| 15366 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(state->base.dev); |
| 15367 | struct intel_crtc *crtc; |
| 15368 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; |
| 15369 | struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; |
| 15370 | u8 update_pipes = 0, modeset_pipes = 0; |
| 15371 | int i; |
| 15372 | |
| 15373 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15374 | enum pipe pipe = crtc->pipe; |
| 15375 | |
| 15376 | if (!new_crtc_state->hw.active) |
| 15377 | continue; |
| 15378 | |
| 15379 | /* ignore allocations for crtc's that have been turned off. */ |
| 15380 | if (!needs_modeset(new_crtc_state)) { |
| 15381 | entries[pipe] = old_crtc_state->wm.skl.ddb; |
| 15382 | update_pipes |= BIT(pipe)(1UL << (pipe)); |
| 15383 | } else { |
| 15384 | modeset_pipes |= BIT(pipe)(1UL << (pipe)); |
| 15385 | } |
| 15386 | } |
| 15387 | |
| 15388 | /* |
| 15389 | * Whenever the number of active pipes changes, we need to make sure we |
| 15390 | * update the pipes in the right order so that their ddb allocations |
| 15391 | * never overlap with each other between CRTC updates. Otherwise we'll |
| 15392 | * cause pipe underruns and other bad stuff. |
| 15393 | * |
| 15394 | * So first lets enable all pipes that do not need a fullmodeset as |
| 15395 | * those don't have any external dependency. |
| 15396 | */ |
| 15397 | while (update_pipes) { |
| 15398 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15399 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15400 | enum pipe pipe = crtc->pipe; |
| 15401 | |
| 15402 | if ((update_pipes & BIT(pipe)(1UL << (pipe))) == 0) |
| 15403 | continue; |
| 15404 | |
| 15405 | if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, |
| 15406 | entries, I915_MAX_PIPES, pipe)) |
| 15407 | continue; |
| 15408 | |
| 15409 | entries[pipe] = new_crtc_state->wm.skl.ddb; |
| 15410 | update_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 15411 | |
| 15412 | intel_update_crtc(state, crtc); |
| 15413 | |
| 15414 | /* |
| 15415 | * If this is an already active pipe, it's DDB changed, |
| 15416 | * and this isn't the last pipe that needs updating |
| 15417 | * then we need to wait for a vblank to pass for the |
| 15418 | * new ddb allocation to take effect. |
| 15419 | */ |
| 15420 | if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, |
| 15421 | &old_crtc_state->wm.skl.ddb) && |
| 15422 | (update_pipes | modeset_pipes)) |
| 15423 | intel_wait_for_vblank(dev_priv, pipe); |
| 15424 | } |
| 15425 | } |
| 15426 | |
| 15427 | update_pipes = modeset_pipes; |
| 15428 | |
| 15429 | /* |
| 15430 | * Enable all pipes that needs a modeset and do not depends on other |
| 15431 | * pipes |
| 15432 | */ |
| 15433 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15434 | enum pipe pipe = crtc->pipe; |
| 15435 | |
| 15436 | if ((modeset_pipes & BIT(pipe)(1UL << (pipe))) == 0) |
| 15437 | continue; |
| 15438 | |
| 15439 | if (intel_dp_mst_is_slave_trans(new_crtc_state) || |
| 15440 | is_trans_port_sync_master(new_crtc_state)) |
| 15441 | continue; |
| 15442 | |
| 15443 | modeset_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 15444 | |
| 15445 | intel_enable_crtc(state, crtc); |
| 15446 | } |
| 15447 | |
| 15448 | /* |
| 15449 | * Then we enable all remaining pipes that depend on other |
| 15450 | * pipes: MST slaves and port sync masters. |
| 15451 | */ |
| 15452 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15453 | enum pipe pipe = crtc->pipe; |
| 15454 | |
| 15455 | if ((modeset_pipes & BIT(pipe)(1UL << (pipe))) == 0) |
| 15456 | continue; |
| 15457 | |
| 15458 | modeset_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 15459 | |
| 15460 | intel_enable_crtc(state, crtc); |
| 15461 | } |
| 15462 | |
| 15463 | /* |
| 15464 | * Finally we do the plane updates/etc. for all pipes that got enabled. |
| 15465 | */ |
| 15466 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15467 | enum pipe pipe = crtc->pipe; |
| 15468 | |
| 15469 | if ((update_pipes & BIT(pipe)(1UL << (pipe))) == 0) |
| 15470 | continue; |
| 15471 | |
| 15472 | drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,({ int __ret = !!((skl_ddb_allocation_overlaps(&new_crtc_state ->wm.skl.ddb, entries, I915_MAX_PIPES, pipe))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, entries, I915_MAX_PIPES, pipe)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 15473 | entries, I915_MAX_PIPES, pipe))({ int __ret = !!((skl_ddb_allocation_overlaps(&new_crtc_state ->wm.skl.ddb, entries, I915_MAX_PIPES, pipe))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, entries, I915_MAX_PIPES, pipe)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 15474 | |
| 15475 | entries[pipe] = new_crtc_state->wm.skl.ddb; |
| 15476 | update_pipes &= ~BIT(pipe)(1UL << (pipe)); |
| 15477 | |
| 15478 | intel_update_crtc(state, crtc); |
| 15479 | } |
| 15480 | |
| 15481 | drm_WARN_ON(&dev_priv->drm, modeset_pipes)({ int __ret = !!((modeset_pipes)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "modeset_pipes" ")"); __builtin_expect(!!(__ret ), 0); }); |
| 15482 | drm_WARN_ON(&dev_priv->drm, update_pipes)({ int __ret = !!((update_pipes)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "update_pipes" ")"); __builtin_expect(!!(__ret ), 0); }); |
| 15483 | } |
| 15484 | |
| 15485 | static void intel_atomic_helper_free_state(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 15486 | { |
| 15487 | struct intel_atomic_state *state, *next; |
| 15488 | struct llist_node *freed; |
| 15489 | |
| 15490 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); |
| 15491 | llist_for_each_entry_safe(state, next, freed, freed)for (state = (((freed)) ? ({ const __typeof( ((__typeof(*state ) *)0)->freed ) *__mptr = ((freed)); (__typeof(*state) *)( (char *)__mptr - __builtin_offsetof(__typeof(*state), freed) );}) : ((void *)0)); state != ((void *)0) && (next = ((state->freed.next) ? ({ const __typeof( ((__typeof(*state ) *)0)->freed ) *__mptr = (state->freed.next); (__typeof (*state) *)( (char *)__mptr - __builtin_offsetof(__typeof(*state ), freed) );}) : ((void *)0)), state); state = next) |
| 15492 | drm_atomic_state_put(&state->base); |
| 15493 | } |
| 15494 | |
| 15495 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) |
| 15496 | { |
| 15497 | struct drm_i915_privateinteldrm_softc *dev_priv = |
| 15498 | container_of(work, typeof(*dev_priv), atomic_helper.free_work)({ const __typeof( ((typeof(*dev_priv) *)0)->atomic_helper .free_work ) *__mptr = (work); (typeof(*dev_priv) *)( (char * )__mptr - __builtin_offsetof(typeof(*dev_priv), atomic_helper .free_work) );}); |
| 15499 | |
| 15500 | intel_atomic_helper_free_state(dev_priv); |
| 15501 | } |
| 15502 | |
| 15503 | static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state) |
| 15504 | { |
| 15505 | struct wait_queue_entry wait_fence, wait_reset; |
| 15506 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(intel_state->base.dev); |
| 15507 | |
| 15508 | #ifdef notyet |
| 15509 | init_wait_entry(&wait_fence, 0); |
| 15510 | init_wait_entry(&wait_reset, 0); |
| 15511 | for (;;) { |
| 15512 | prepare_to_wait(&intel_state->commit_ready.wait, |
| 15513 | &wait_fence, TASK_UNINTERRUPTIBLE0); |
| 15514 | prepare_to_wait(bit_waitqueue(&dev_priv->gt.reset.flags, |
| 15515 | I915_RESET_MODESET1), |
| 15516 | &wait_reset, TASK_UNINTERRUPTIBLE0); |
| 15517 | |
| 15518 | |
| 15519 | if (i915_sw_fence_done(&intel_state->commit_ready) || |
| 15520 | test_bit(I915_RESET_MODESET1, &dev_priv->gt.reset.flags)) |
| 15521 | break; |
| 15522 | |
| 15523 | schedule(); |
| 15524 | } |
| 15525 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); |
| 15526 | finish_wait(bit_waitqueue(&dev_priv->gt.reset.flags, |
| 15527 | I915_RESET_MODESET1), |
| 15528 | &wait_reset); |
| 15529 | #else |
| 15530 | /* XXX above recurses sch_mtx */ |
| 15531 | init_wait_entry(&wait_fence, 0); |
| 15532 | for (;;) { |
| 15533 | prepare_to_wait(&intel_state->commit_ready.wait, |
| 15534 | &wait_fence, TASK_UNINTERRUPTIBLE0); |
| 15535 | |
| 15536 | |
| 15537 | if (i915_sw_fence_done(&intel_state->commit_ready) || |
| 15538 | test_bit(I915_RESET_MODESET1, &dev_priv->gt.reset.flags)) |
| 15539 | break; |
| 15540 | |
| 15541 | schedule(); |
| 15542 | } |
| 15543 | finish_wait(&intel_state->commit_ready.wait, &wait_fence); |
| 15544 | #endif |
| 15545 | } |
| 15546 | |
| 15547 | static void intel_cleanup_dsbs(struct intel_atomic_state *state) |
| 15548 | { |
| 15549 | struct intel_crtc_state *old_crtc_state, *new_crtc_state; |
| 15550 | struct intel_crtc *crtc; |
| 15551 | int i; |
| 15552 | |
| 15553 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15554 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15555 | intel_dsb_cleanup(old_crtc_state); |
| 15556 | } |
| 15557 | |
| 15558 | static void intel_atomic_cleanup_work(struct work_struct *work) |
| 15559 | { |
| 15560 | struct intel_atomic_state *state = |
| 15561 | container_of(work, struct intel_atomic_state, base.commit_work)({ const __typeof( ((struct intel_atomic_state *)0)->base. commit_work ) *__mptr = (work); (struct intel_atomic_state *) ( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base.commit_work) );}); |
| 15562 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(state->base.dev); |
| 15563 | |
| 15564 | intel_cleanup_dsbs(state); |
| 15565 | drm_atomic_helper_cleanup_planes(&i915->drm, &state->base); |
| 15566 | drm_atomic_helper_commit_cleanup_done(&state->base); |
| 15567 | drm_atomic_state_put(&state->base); |
| 15568 | |
| 15569 | intel_atomic_helper_free_state(i915); |
| 15570 | } |
| 15571 | |
| 15572 | static void intel_atomic_commit_tail(struct intel_atomic_state *state) |
| 15573 | { |
| 15574 | struct drm_device *dev = state->base.dev; |
| 15575 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 15576 | struct intel_crtc_state *new_crtc_state, *old_crtc_state; |
| 15577 | struct intel_crtc *crtc; |
| 15578 | u64 put_domains[I915_MAX_PIPES] = {}; |
| 15579 | intel_wakeref_t wakeref = 0; |
| 15580 | int i; |
| 15581 | |
| 15582 | intel_atomic_commit_fence_wait(state); |
| 15583 | |
| 15584 | drm_atomic_helper_wait_for_dependencies(&state->base); |
| 15585 | |
| 15586 | if (state->modeset) |
| 15587 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
| 15588 | |
| 15589 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15590 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15591 | if (needs_modeset(new_crtc_state) || |
| 15592 | new_crtc_state->update_pipe) { |
| 15593 | |
| 15594 | put_domains[crtc->pipe] = |
| 15595 | modeset_get_crtc_power_domains(new_crtc_state); |
| 15596 | } |
| 15597 | } |
| 15598 | |
| 15599 | intel_commit_modeset_disables(state); |
| 15600 | |
| 15601 | /* FIXME: Eventually get rid of our crtc->config pointer */ |
| 15602 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15603 | crtc->config = new_crtc_state; |
| 15604 | |
| 15605 | if (state->modeset) { |
| 15606 | drm_atomic_helper_update_legacy_modeset_state(dev, &state->base); |
| 15607 | |
| 15608 | intel_set_cdclk_pre_plane_update(state); |
| 15609 | |
| 15610 | intel_modeset_verify_disabled(dev_priv, state); |
| 15611 | } |
| 15612 | |
| 15613 | intel_sagv_pre_plane_update(state); |
| 15614 | |
| 15615 | /* Complete the events for pipes that have now been disabled */ |
| 15616 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15617 | bool_Bool modeset = needs_modeset(new_crtc_state); |
| 15618 | |
| 15619 | /* Complete events for now disable pipes here. */ |
| 15620 | if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) { |
| 15621 | spin_lock_irq(&dev->event_lock)mtx_enter(&dev->event_lock); |
| 15622 | drm_crtc_send_vblank_event(&crtc->base, |
| 15623 | new_crtc_state->uapi.event); |
| 15624 | spin_unlock_irq(&dev->event_lock)mtx_leave(&dev->event_lock); |
| 15625 | |
| 15626 | new_crtc_state->uapi.event = NULL((void *)0); |
| 15627 | } |
| 15628 | } |
| 15629 | |
| 15630 | if (state->modeset) |
| 15631 | intel_encoders_update_prepare(state); |
| 15632 | |
| 15633 | intel_dbuf_pre_plane_update(state); |
| 15634 | |
| 15635 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
| 15636 | dev_priv->display.commit_modeset_enables(state); |
| 15637 | |
| 15638 | if (state->modeset) { |
| 15639 | intel_encoders_update_complete(state); |
| 15640 | |
| 15641 | intel_set_cdclk_post_plane_update(state); |
| 15642 | } |
| 15643 | |
| 15644 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
| 15645 | * already, but still need the state for the delayed optimization. To |
| 15646 | * fix this: |
| 15647 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. |
| 15648 | * - schedule that vblank worker _before_ calling hw_done |
| 15649 | * - at the start of commit_tail, cancel it _synchrously |
| 15650 | * - switch over to the vblank wait helper in the core after that since |
| 15651 | * we don't need out special handling any more. |
| 15652 | */ |
| 15653 | drm_atomic_helper_wait_for_flip_done(dev, &state->base); |
| 15654 | |
| 15655 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15656 | if (new_crtc_state->hw.active && |
| 15657 | !needs_modeset(new_crtc_state) && |
| 15658 | !new_crtc_state->preload_luts && |
| 15659 | (new_crtc_state->uapi.color_mgmt_changed || |
| 15660 | new_crtc_state->update_pipe)) |
| 15661 | intel_color_load_luts(new_crtc_state); |
| 15662 | } |
| 15663 | |
| 15664 | /* |
| 15665 | * Now that the vblank has passed, we can go ahead and program the |
| 15666 | * optimal watermarks on platforms that need two-step watermark |
| 15667 | * programming. |
| 15668 | * |
| 15669 | * TODO: Move this (and other cleanup) to an async worker eventually. |
| 15670 | */ |
| 15671 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15672 | new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15673 | /* |
| 15674 | * Gen2 reports pipe underruns whenever all planes are disabled. |
| 15675 | * So re-enable underrun reporting after some planes get enabled. |
| 15676 | * |
| 15677 | * We do this before .optimize_watermarks() so that we have a |
| 15678 | * chance of catching underruns with the intermediate watermarks |
| 15679 | * vs. the new plane configuration. |
| 15680 | */ |
| 15681 | if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) && planes_enabling(old_crtc_state, new_crtc_state)) |
| 15682 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true1); |
| 15683 | |
| 15684 | if (dev_priv->display.optimize_watermarks) |
| 15685 | dev_priv->display.optimize_watermarks(state, crtc); |
| 15686 | } |
| 15687 | |
| 15688 | intel_dbuf_post_plane_update(state); |
| 15689 | |
| 15690 | for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}), 1); (i)++) if (!(crtc)) {} else { |
| 15691 | intel_post_plane_update(state, crtc); |
| 15692 | |
| 15693 | if (put_domains[i]) |
| 15694 | modeset_put_power_domains(dev_priv, put_domains[i]); |
| 15695 | |
| 15696 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
| 15697 | |
| 15698 | /* |
| 15699 | * DSB cleanup is done in cleanup_work aligning with framebuffer |
| 15700 | * cleanup. So copy and reset the dsb structure to sync with |
| 15701 | * commit_done and later do dsb cleanup in cleanup_work. |
| 15702 | */ |
| 15703 | old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb)({ typeof(*&new_crtc_state->dsb) __T = *(&new_crtc_state ->dsb); *(&new_crtc_state->dsb) = (typeof(*&new_crtc_state ->dsb))0; __T; }); |
| 15704 | } |
| 15705 | |
| 15706 | /* Underruns don't always raise interrupts, so check manually */ |
| 15707 | intel_check_cpu_fifo_underruns(dev_priv); |
| 15708 | intel_check_pch_fifo_underruns(dev_priv); |
| 15709 | |
| 15710 | if (state->modeset) |
| 15711 | intel_verify_planes(state); |
| 15712 | |
| 15713 | intel_sagv_post_plane_update(state); |
| 15714 | |
| 15715 | drm_atomic_helper_commit_hw_done(&state->base); |
| 15716 | |
| 15717 | if (state->modeset) { |
| 15718 | /* As one of the primary mmio accessors, KMS has a high |
| 15719 | * likelihood of triggering bugs in unclaimed access. After we |
| 15720 | * finish modesetting, see if an error has been flagged, and if |
| 15721 | * so enable debugging for the next modeset - and hope we catch |
| 15722 | * the culprit. |
| 15723 | */ |
| 15724 | intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore); |
| 15725 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET, wakeref); |
| 15726 | } |
| 15727 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); |
| 15728 | |
| 15729 | /* |
| 15730 | * Defer the cleanup of the old state to a separate worker to not |
| 15731 | * impede the current task (userspace for blocking modesets) that |
| 15732 | * are executed inline. For out-of-line asynchronous modesets/flips, |
| 15733 | * deferring to a new worker seems overkill, but we would place a |
| 15734 | * schedule point (cond_resched()) here anyway to keep latencies |
| 15735 | * down. |
| 15736 | */ |
| 15737 | INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work); |
| 15738 | queue_work(system_highpri_wq, &state->base.commit_work); |
| 15739 | } |
| 15740 | |
| 15741 | static void intel_atomic_commit_work(struct work_struct *work) |
| 15742 | { |
| 15743 | struct intel_atomic_state *state = |
| 15744 | container_of(work, struct intel_atomic_state, base.commit_work)({ const __typeof( ((struct intel_atomic_state *)0)->base. commit_work ) *__mptr = (work); (struct intel_atomic_state *) ( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base.commit_work) );}); |
| 15745 | |
| 15746 | intel_atomic_commit_tail(state); |
| 15747 | } |
| 15748 | |
| 15749 | static int __i915_sw_fence_call__attribute__((__aligned__(4))) |
| 15750 | intel_atomic_commit_ready(struct i915_sw_fence *fence, |
| 15751 | enum i915_sw_fence_notify notify) |
| 15752 | { |
| 15753 | struct intel_atomic_state *state = |
| 15754 | container_of(fence, struct intel_atomic_state, commit_ready)({ const __typeof( ((struct intel_atomic_state *)0)->commit_ready ) *__mptr = (fence); (struct intel_atomic_state *)( (char *) __mptr - __builtin_offsetof(struct intel_atomic_state, commit_ready ) );}); |
| 15755 | |
| 15756 | switch (notify) { |
| 15757 | case FENCE_COMPLETE: |
| 15758 | /* we do blocking waits in the worker, nothing to do here */ |
| 15759 | break; |
| 15760 | case FENCE_FREE: |
| 15761 | { |
| 15762 | struct intel_atomic_helper *helper = |
| 15763 | &to_i915(state->base.dev)->atomic_helper; |
| 15764 | |
| 15765 | if (llist_add(&state->freed, &helper->free_list)) |
| 15766 | schedule_work(&helper->free_work); |
| 15767 | break; |
| 15768 | } |
| 15769 | } |
| 15770 | |
| 15771 | return NOTIFY_DONE0; |
| 15772 | } |
| 15773 | |
| 15774 | static void intel_atomic_track_fbs(struct intel_atomic_state *state) |
| 15775 | { |
| 15776 | struct intel_plane_state *old_plane_state, *new_plane_state; |
| 15777 | struct intel_plane *plane; |
| 15778 | int i; |
| 15779 | |
| 15780 | for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (old_plane_state) = ({ const __typeof ( ((struct intel_plane_state *)0)->uapi ) *__mptr = ((state )->base.planes[i].old_state); (struct intel_plane_state *) ( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}), (new_plane_state) = ({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = ((state)->base .planes[i].new_state); (struct intel_plane_state *)( (char *) __mptr - __builtin_offsetof(struct intel_plane_state, uapi) ) ;}), 1); (i)++) if (!(plane)) {} else |
| 15781 | new_plane_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_total_plane && ((plane) = ({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = ((state)->base.planes[i].ptr); ( struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}), (old_plane_state) = ({ const __typeof ( ((struct intel_plane_state *)0)->uapi ) *__mptr = ((state )->base.planes[i].old_state); (struct intel_plane_state *) ( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}), (new_plane_state) = ({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = ((state)->base .planes[i].new_state); (struct intel_plane_state *)( (char *) __mptr - __builtin_offsetof(struct intel_plane_state, uapi) ) ;}), 1); (i)++) if (!(plane)) {} else |
| 15782 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), |
| 15783 | to_intel_frontbuffer(new_plane_state->hw.fb), |
| 15784 | plane->frontbuffer_bit); |
| 15785 | } |
| 15786 | |
| 15787 | static int intel_atomic_commit(struct drm_device *dev, |
| 15788 | struct drm_atomic_state *_state, |
| 15789 | bool_Bool nonblock) |
| 15790 | { |
| 15791 | struct intel_atomic_state *state = to_intel_atomic_state(_state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (_state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state, base) );}); |
| 15792 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 15793 | int ret = 0; |
| 15794 | |
| 15795 | state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); |
| 15796 | |
| 15797 | drm_atomic_state_get(&state->base); |
| 15798 | i915_sw_fence_init(&state->commit_ready,__i915_sw_fence_init((&state->commit_ready), (intel_atomic_commit_ready ), ((void *)0), ((void *)0)) |
| 15799 | intel_atomic_commit_ready)__i915_sw_fence_init((&state->commit_ready), (intel_atomic_commit_ready ), ((void *)0), ((void *)0)); |
| 15800 | |
| 15801 | /* |
| 15802 | * The intel_legacy_cursor_update() fast path takes care |
| 15803 | * of avoiding the vblank waits for simple cursor |
| 15804 | * movement and flips. For cursor on/off and size changes, |
| 15805 | * we want to perform the vblank waits so that watermark |
| 15806 | * updates happen during the correct frames. Gen9+ have |
| 15807 | * double buffered watermarks and so shouldn't need this. |
| 15808 | * |
| 15809 | * Unset state->legacy_cursor_update before the call to |
| 15810 | * drm_atomic_helper_setup_commit() because otherwise |
| 15811 | * drm_atomic_helper_wait_for_flip_done() is a noop and |
| 15812 | * we get FIFO underruns because we didn't wait |
| 15813 | * for vblank. |
| 15814 | * |
| 15815 | * FIXME doing watermarks and fb cleanup from a vblank worker |
| 15816 | * (assuming we had any) would solve these problems. |
| 15817 | */ |
| 15818 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9 && state->base.legacy_cursor_update) { |
| 15819 | struct intel_crtc_state *new_crtc_state; |
| 15820 | struct intel_crtc *crtc; |
| 15821 | int i; |
| 15822 | |
| 15823 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15824 | if (new_crtc_state->wm.need_postvbl_update || |
| 15825 | new_crtc_state->update_wm_post) |
| 15826 | state->base.legacy_cursor_update = false0; |
| 15827 | } |
| 15828 | |
| 15829 | ret = intel_atomic_prepare_commit(state); |
| 15830 | if (ret) { |
| 15831 | drm_dbg_atomic(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "Preparing state failed with %i\n" , ret) |
| 15832 | "Preparing state failed with %i\n", ret)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_ATOMIC, "Preparing state failed with %i\n" , ret); |
| 15833 | i915_sw_fence_commit(&state->commit_ready); |
| 15834 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); |
| 15835 | return ret; |
| 15836 | } |
| 15837 | |
| 15838 | ret = drm_atomic_helper_setup_commit(&state->base, nonblock); |
| 15839 | if (!ret) |
| 15840 | ret = drm_atomic_helper_swap_state(&state->base, true1); |
| 15841 | if (!ret) |
| 15842 | intel_atomic_swap_global_state(state); |
| 15843 | |
| 15844 | if (ret) { |
| 15845 | struct intel_crtc_state *new_crtc_state; |
| 15846 | struct intel_crtc *crtc; |
| 15847 | int i; |
| 15848 | |
| 15849 | i915_sw_fence_commit(&state->commit_ready); |
| 15850 | |
| 15851 | for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc * )0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc , base) );}), (new_crtc_state) = ({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((state)->base.crtcs[i].new_state ); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc_state, uapi) );}), 1); (i)++) if (!(crtc)) {} else |
| 15852 | intel_dsb_cleanup(new_crtc_state); |
| 15853 | |
| 15854 | drm_atomic_helper_cleanup_planes(dev, &state->base); |
| 15855 | intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref); |
| 15856 | return ret; |
| 15857 | } |
| 15858 | dev_priv->wm.distrust_bios_wm = false0; |
| 15859 | intel_shared_dpll_swap_state(state); |
| 15860 | intel_atomic_track_fbs(state); |
| 15861 | |
| 15862 | drm_atomic_state_get(&state->base); |
| 15863 | INIT_WORK(&state->base.commit_work, intel_atomic_commit_work); |
| 15864 | |
| 15865 | i915_sw_fence_commit(&state->commit_ready); |
| 15866 | if (nonblock && state->modeset) { |
| 15867 | queue_work(dev_priv->modeset_wq, &state->base.commit_work); |
| 15868 | } else if (nonblock) { |
| 15869 | queue_work(dev_priv->flip_wq, &state->base.commit_work); |
| 15870 | } else { |
| 15871 | if (state->modeset) |
| 15872 | flush_workqueue(dev_priv->modeset_wq); |
| 15873 | intel_atomic_commit_tail(state); |
| 15874 | } |
| 15875 | |
| 15876 | return 0; |
| 15877 | } |
| 15878 | |
| 15879 | struct wait_rps_boost { |
| 15880 | struct wait_queue_entry wait; |
| 15881 | |
| 15882 | struct drm_crtc *crtc; |
| 15883 | struct i915_request *request; |
| 15884 | }; |
| 15885 | |
| 15886 | static int do_rps_boost(struct wait_queue_entry *_wait, |
| 15887 | unsigned mode, int sync, void *key) |
| 15888 | { |
| 15889 | struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait)({ const __typeof( ((typeof(*wait) *)0)->wait ) *__mptr = ( _wait); (typeof(*wait) *)( (char *)__mptr - __builtin_offsetof (typeof(*wait), wait) );}); |
| 15890 | struct i915_request *rq = wait->request; |
| 15891 | |
| 15892 | /* |
| 15893 | * If we missed the vblank, but the request is already running it |
| 15894 | * is reasonable to assume that it will complete before the next |
| 15895 | * vblank without our intervention, so leave RPS alone. |
| 15896 | */ |
| 15897 | if (!i915_request_started(rq)) |
| 15898 | intel_rps_boost(rq); |
| 15899 | i915_request_put(rq); |
| 15900 | |
| 15901 | drm_crtc_vblank_put(wait->crtc); |
| 15902 | |
| 15903 | list_del(&wait->wait.entry); |
| 15904 | kfree(wait); |
| 15905 | return 1; |
| 15906 | } |
| 15907 | |
| 15908 | static void add_rps_boost_after_vblank(struct drm_crtc *crtc, |
| 15909 | struct dma_fence *fence) |
| 15910 | { |
| 15911 | struct wait_rps_boost *wait; |
| 15912 | |
| 15913 | if (!dma_fence_is_i915(fence)) |
| 15914 | return; |
| 15915 | |
| 15916 | if (INTEL_GEN(to_i915(crtc->dev))((&(to_i915(crtc->dev))->__info)->gen) < 6) |
| 15917 | return; |
| 15918 | |
| 15919 | if (drm_crtc_vblank_get(crtc)) |
| 15920 | return; |
| 15921 | |
| 15922 | wait = kmalloc(sizeof(*wait), GFP_KERNEL(0x0001 | 0x0004)); |
| 15923 | if (!wait) { |
| 15924 | drm_crtc_vblank_put(crtc); |
| 15925 | return; |
| 15926 | } |
| 15927 | |
| 15928 | wait->request = to_request(dma_fence_get(fence)); |
| 15929 | wait->crtc = crtc; |
| 15930 | |
| 15931 | wait->wait.func = do_rps_boost; |
| 15932 | wait->wait.flags = 0; |
| 15933 | |
| 15934 | add_wait_queue(drm_crtc_vblank_waitqueue(crtc), &wait->wait); |
| 15935 | } |
| 15936 | |
| 15937 | static int intel_plane_pin_fb(struct intel_plane_state *plane_state) |
| 15938 | { |
| 15939 | struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane_state->uapi.plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 15940 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 15941 | struct drm_framebuffer *fb = plane_state->hw.fb; |
| 15942 | struct i915_vma *vma; |
| 15943 | |
| 15944 | if (plane->id == PLANE_CURSOR && |
| 15945 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->display.cursor_needs_physical) { |
| 15946 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 15947 | const int align = intel_cursor_alignment(dev_priv); |
| 15948 | int err; |
| 15949 | |
| 15950 | err = i915_gem_object_attach_phys(obj, align); |
| 15951 | if (err) |
| 15952 | return err; |
| 15953 | } |
| 15954 | |
| 15955 | vma = intel_pin_and_fence_fb_obj(fb, |
| 15956 | &plane_state->view, |
| 15957 | intel_plane_uses_fence(plane_state), |
| 15958 | &plane_state->flags); |
| 15959 | if (IS_ERR(vma)) |
| 15960 | return PTR_ERR(vma); |
| 15961 | |
| 15962 | plane_state->vma = vma; |
| 15963 | |
| 15964 | return 0; |
| 15965 | } |
| 15966 | |
| 15967 | static void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) |
| 15968 | { |
| 15969 | struct i915_vma *vma; |
| 15970 | |
| 15971 | vma = fetch_and_zero(&old_plane_state->vma)({ typeof(*&old_plane_state->vma) __T = *(&old_plane_state ->vma); *(&old_plane_state->vma) = (typeof(*&old_plane_state ->vma))0; __T; }); |
| 15972 | if (vma) |
| 15973 | intel_unpin_fb_vma(vma, old_plane_state->flags); |
| 15974 | } |
| 15975 | |
| 15976 | static void fb_obj_bump_render_priority(struct drm_i915_gem_object *obj) |
| 15977 | { |
| 15978 | struct i915_sched_attr attr = { |
| 15979 | .priority = I915_USER_PRIORITY(I915_PRIORITY_DISPLAY)((I915_PRIORITY_DISPLAY) << 0), |
| 15980 | }; |
| 15981 | |
| 15982 | i915_gem_object_wait_priority(obj, 0, &attr); |
| 15983 | } |
| 15984 | |
| 15985 | /** |
| 15986 | * intel_prepare_plane_fb - Prepare fb for usage on plane |
| 15987 | * @_plane: drm plane to prepare for |
| 15988 | * @_new_plane_state: the plane state being prepared |
| 15989 | * |
| 15990 | * Prepares a framebuffer for usage on a display plane. Generally this |
| 15991 | * involves pinning the underlying object and updating the frontbuffer tracking |
| 15992 | * bits. Some older platforms need special physical address handling for |
| 15993 | * cursor planes. |
| 15994 | * |
| 15995 | * Returns 0 on success, negative error code on failure. |
| 15996 | */ |
| 15997 | int |
| 15998 | intel_prepare_plane_fb(struct drm_plane *_plane, |
| 15999 | struct drm_plane_state *_new_plane_state) |
| 16000 | { |
| 16001 | struct intel_plane *plane = to_intel_plane(_plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (_plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );}); |
| 16002 | struct intel_plane_state *new_plane_state = |
| 16003 | to_intel_plane_state(_new_plane_state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (_new_plane_state); (struct intel_plane_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}); |
| 16004 | struct intel_atomic_state *state = |
| 16005 | to_intel_atomic_state(new_plane_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (new_plane_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 16006 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->base.dev); |
| 16007 | const struct intel_plane_state *old_plane_state = |
| 16008 | intel_atomic_get_old_plane_state(state, plane); |
| 16009 | struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb)((new_plane_state->hw.fb) ? to_intel_bo((new_plane_state-> hw.fb)->obj[0]) : ((void *)0)); |
| 16010 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb)((old_plane_state->hw.fb) ? to_intel_bo((old_plane_state-> hw.fb)->obj[0]) : ((void *)0)); |
| 16011 | int ret; |
| 16012 | |
| 16013 | if (old_obj) { |
| 16014 | const struct intel_crtc_state *crtc_state = |
| 16015 | intel_atomic_get_new_crtc_state(state, |
| 16016 | to_intel_crtc(old_plane_state->hw.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (old_plane_state->hw.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );})); |
| 16017 | |
| 16018 | /* Big Hammer, we also need to ensure that any pending |
| 16019 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the |
| 16020 | * current scanout is retired before unpinning the old |
| 16021 | * framebuffer. Note that we rely on userspace rendering |
| 16022 | * into the buffer attached to the pipe they are waiting |
| 16023 | * on. If not, userspace generates a GPU hang with IPEHR |
| 16024 | * point to the MI_WAIT_FOR_EVENT. |
| 16025 | * |
| 16026 | * This should only fail upon a hung GPU, in which case we |
| 16027 | * can safely continue. |
| 16028 | */ |
| 16029 | if (needs_modeset(crtc_state)) { |
| 16030 | ret = i915_sw_fence_await_reservation(&state->commit_ready, |
| 16031 | old_obj->base.resv, NULL((void *)0), |
| 16032 | false0, 0, |
| 16033 | GFP_KERNEL(0x0001 | 0x0004)); |
| 16034 | if (ret < 0) |
| 16035 | return ret; |
| 16036 | } |
| 16037 | } |
| 16038 | |
| 16039 | if (new_plane_state->uapi.fence) { /* explicit fencing */ |
| 16040 | ret = i915_sw_fence_await_dma_fence(&state->commit_ready, |
| 16041 | new_plane_state->uapi.fence, |
| 16042 | i915_fence_timeout(dev_priv), |
| 16043 | GFP_KERNEL(0x0001 | 0x0004)); |
| 16044 | if (ret < 0) |
| 16045 | return ret; |
| 16046 | } |
| 16047 | |
| 16048 | if (!obj) |
| 16049 | return 0; |
| 16050 | |
| 16051 | ret = i915_gem_object_pin_pages(obj); |
| 16052 | if (ret) |
| 16053 | return ret; |
| 16054 | |
| 16055 | ret = intel_plane_pin_fb(new_plane_state); |
| 16056 | |
| 16057 | i915_gem_object_unpin_pages(obj); |
| 16058 | if (ret) |
| 16059 | return ret; |
| 16060 | |
| 16061 | fb_obj_bump_render_priority(obj); |
| 16062 | i915_gem_object_flush_frontbuffer(obj, ORIGIN_DIRTYFB); |
| 16063 | |
| 16064 | if (!new_plane_state->uapi.fence) { /* implicit fencing */ |
| 16065 | struct dma_fence *fence; |
| 16066 | |
| 16067 | ret = i915_sw_fence_await_reservation(&state->commit_ready, |
| 16068 | obj->base.resv, NULL((void *)0), |
| 16069 | false0, |
| 16070 | i915_fence_timeout(dev_priv), |
| 16071 | GFP_KERNEL(0x0001 | 0x0004)); |
| 16072 | if (ret < 0) |
| 16073 | goto unpin_fb; |
| 16074 | |
| 16075 | fence = dma_resv_get_excl_rcu(obj->base.resv); |
| 16076 | if (fence) { |
| 16077 | add_rps_boost_after_vblank(new_plane_state->hw.crtc, |
| 16078 | fence); |
| 16079 | dma_fence_put(fence); |
| 16080 | } |
| 16081 | } else { |
| 16082 | add_rps_boost_after_vblank(new_plane_state->hw.crtc, |
| 16083 | new_plane_state->uapi.fence); |
| 16084 | } |
| 16085 | |
| 16086 | /* |
| 16087 | * We declare pageflips to be interactive and so merit a small bias |
| 16088 | * towards upclocking to deliver the frame on time. By only changing |
| 16089 | * the RPS thresholds to sample more regularly and aim for higher |
| 16090 | * clocks we can hopefully deliver low power workloads (like kodi) |
| 16091 | * that are not quite steady state without resorting to forcing |
| 16092 | * maximum clocks following a vblank miss (see do_rps_boost()). |
| 16093 | */ |
| 16094 | if (!state->rps_interactive) { |
| 16095 | intel_rps_mark_interactive(&dev_priv->gt.rps, true1); |
| 16096 | state->rps_interactive = true1; |
| 16097 | } |
| 16098 | |
| 16099 | return 0; |
| 16100 | |
| 16101 | unpin_fb: |
| 16102 | intel_plane_unpin_fb(new_plane_state); |
| 16103 | |
| 16104 | return ret; |
| 16105 | } |
| 16106 | |
| 16107 | /** |
| 16108 | * intel_cleanup_plane_fb - Cleans up an fb after plane use |
| 16109 | * @plane: drm plane to clean up for |
| 16110 | * @_old_plane_state: the state from the previous modeset |
| 16111 | * |
| 16112 | * Cleans up a framebuffer that has just been removed from a plane. |
| 16113 | */ |
| 16114 | void |
| 16115 | intel_cleanup_plane_fb(struct drm_plane *plane, |
| 16116 | struct drm_plane_state *_old_plane_state) |
| 16117 | { |
| 16118 | struct intel_plane_state *old_plane_state = |
| 16119 | to_intel_plane_state(_old_plane_state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (_old_plane_state); (struct intel_plane_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_plane_state, uapi ) );}); |
| 16120 | struct intel_atomic_state *state = |
| 16121 | to_intel_atomic_state(old_plane_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (old_plane_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
| 16122 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(plane->dev); |
| 16123 | struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb)((old_plane_state->hw.fb) ? to_intel_bo((old_plane_state-> hw.fb)->obj[0]) : ((void *)0)); |
| 16124 | |
| 16125 | if (!obj) |
| 16126 | return; |
| 16127 | |
| 16128 | if (state->rps_interactive) { |
| 16129 | intel_rps_mark_interactive(&dev_priv->gt.rps, false0); |
| 16130 | state->rps_interactive = false0; |
| 16131 | } |
| 16132 | |
| 16133 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
| 16134 | intel_plane_unpin_fb(old_plane_state); |
| 16135 | } |
| 16136 | |
| 16137 | /** |
| 16138 | * intel_plane_destroy - destroy a plane |
| 16139 | * @plane: plane to destroy |
| 16140 | * |
| 16141 | * Common destruction function for all types of planes (primary, cursor, |
| 16142 | * sprite). |
| 16143 | */ |
| 16144 | void intel_plane_destroy(struct drm_plane *plane) |
| 16145 | { |
| 16146 | drm_plane_cleanup(plane); |
| 16147 | kfree(to_intel_plane(plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );})); |
| 16148 | } |
| 16149 | |
| 16150 | static bool_Bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, |
| 16151 | u32 format, u64 modifier) |
| 16152 | { |
| 16153 | switch (modifier) { |
| 16154 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 16155 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 16156 | break; |
| 16157 | default: |
| 16158 | return false0; |
| 16159 | } |
| 16160 | |
| 16161 | switch (format) { |
| 16162 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 16163 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 16164 | case DRM_FORMAT_XRGB1555((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('1') << 16) | ((__u32)('5') << 24)): |
| 16165 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 16166 | return modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) || |
| 16167 | modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
| 16168 | default: |
| 16169 | return false0; |
| 16170 | } |
| 16171 | } |
| 16172 | |
| 16173 | static bool_Bool i965_plane_format_mod_supported(struct drm_plane *_plane, |
| 16174 | u32 format, u64 modifier) |
| 16175 | { |
| 16176 | switch (modifier) { |
| 16177 | case DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ): |
| 16178 | case I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )): |
| 16179 | break; |
| 16180 | default: |
| 16181 | return false0; |
| 16182 | } |
| 16183 | |
| 16184 | switch (format) { |
| 16185 | case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') << 16) | ((__u32)(' ') << 24)): |
| 16186 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 16187 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 16188 | case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 16189 | case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 16190 | case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 16191 | case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 16192 | case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 16193 | case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 16194 | case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') << 16) | ((__u32)('0') << 24)): |
| 16195 | case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') << 16) | ((__u32)('H') << 24)): |
| 16196 | return modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) || |
| 16197 | modifier == I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
| 16198 | default: |
| 16199 | return false0; |
| 16200 | } |
| 16201 | } |
| 16202 | |
| 16203 | static bool_Bool intel_cursor_format_mod_supported(struct drm_plane *_plane, |
| 16204 | u32 format, u64 modifier) |
| 16205 | { |
| 16206 | return modifier == DRM_FORMAT_MOD_LINEAR((((__u64)0) << 56) | ((0) & 0x00ffffffffffffffULL) ) && |
| 16207 | format == DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)); |
| 16208 | } |
| 16209 | |
| 16210 | static const struct drm_plane_funcs i965_plane_funcs = { |
| 16211 | .update_plane = drm_atomic_helper_update_plane, |
| 16212 | .disable_plane = drm_atomic_helper_disable_plane, |
| 16213 | .destroy = intel_plane_destroy, |
| 16214 | .atomic_duplicate_state = intel_plane_duplicate_state, |
| 16215 | .atomic_destroy_state = intel_plane_destroy_state, |
| 16216 | .format_mod_supported = i965_plane_format_mod_supported, |
| 16217 | }; |
| 16218 | |
| 16219 | static const struct drm_plane_funcs i8xx_plane_funcs = { |
| 16220 | .update_plane = drm_atomic_helper_update_plane, |
| 16221 | .disable_plane = drm_atomic_helper_disable_plane, |
| 16222 | .destroy = intel_plane_destroy, |
| 16223 | .atomic_duplicate_state = intel_plane_duplicate_state, |
| 16224 | .atomic_destroy_state = intel_plane_destroy_state, |
| 16225 | .format_mod_supported = i8xx_plane_format_mod_supported, |
| 16226 | }; |
| 16227 | |
| 16228 | static int |
| 16229 | intel_legacy_cursor_update(struct drm_plane *_plane, |
| 16230 | struct drm_crtc *_crtc, |
| 16231 | struct drm_framebuffer *fb, |
| 16232 | int crtc_x, int crtc_y, |
| 16233 | unsigned int crtc_w, unsigned int crtc_h, |
| 16234 | u32 src_x, u32 src_y, |
| 16235 | u32 src_w, u32 src_h, |
| 16236 | struct drm_modeset_acquire_ctx *ctx) |
| 16237 | { |
| 16238 | struct intel_plane *plane = to_intel_plane(_plane)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (_plane); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof (struct intel_plane, base) );}); |
| 16239 | struct intel_crtc *crtc = to_intel_crtc(_crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (_crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}); |
| 16240 | struct intel_plane_state *old_plane_state = |
| 16241 | to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane->base.state); (struct intel_plane_state * )( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 16242 | struct intel_plane_state *new_plane_state; |
| 16243 | struct intel_crtc_state *crtc_state = |
| 16244 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 16245 | struct intel_crtc_state *new_crtc_state; |
| 16246 | int ret; |
| 16247 | |
| 16248 | /* |
| 16249 | * When crtc is inactive or there is a modeset pending, |
| 16250 | * wait for it to complete in the slowpath |
| 16251 | */ |
| 16252 | if (!crtc_state->hw.active || needs_modeset(crtc_state) || |
| 16253 | crtc_state->update_pipe) |
| 16254 | goto slow; |
| 16255 | |
| 16256 | /* |
| 16257 | * Don't do an async update if there is an outstanding commit modifying |
| 16258 | * the plane. This prevents our async update's changes from getting |
| 16259 | * overridden by a previous synchronous update's state. |
| 16260 | */ |
| 16261 | if (old_plane_state->uapi.commit && |
| 16262 | !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done)) |
| 16263 | goto slow; |
| 16264 | |
| 16265 | /* |
| 16266 | * If any parameters change that may affect watermarks, |
| 16267 | * take the slowpath. Only changing fb or position should be |
| 16268 | * in the fastpath. |
| 16269 | */ |
| 16270 | if (old_plane_state->uapi.crtc != &crtc->base || |
| 16271 | old_plane_state->uapi.src_w != src_w || |
| 16272 | old_plane_state->uapi.src_h != src_h || |
| 16273 | old_plane_state->uapi.crtc_w != crtc_w || |
| 16274 | old_plane_state->uapi.crtc_h != crtc_h || |
| 16275 | !old_plane_state->uapi.fb != !fb) |
| 16276 | goto slow; |
| 16277 | |
| 16278 | new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base))({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (intel_plane_duplicate_state(&plane->base)) ; (struct intel_plane_state *)( (char *)__mptr - __builtin_offsetof (struct intel_plane_state, uapi) );}); |
| 16279 | if (!new_plane_state) |
| 16280 | return -ENOMEM12; |
| 16281 | |
| 16282 | new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base))({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (intel_crtc_duplicate_state(&crtc->base)); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi) );}); |
| 16283 | if (!new_crtc_state) { |
| 16284 | ret = -ENOMEM12; |
| 16285 | goto out_free; |
| 16286 | } |
| 16287 | |
| 16288 | drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb); |
| 16289 | |
| 16290 | new_plane_state->uapi.src_x = src_x; |
| 16291 | new_plane_state->uapi.src_y = src_y; |
| 16292 | new_plane_state->uapi.src_w = src_w; |
| 16293 | new_plane_state->uapi.src_h = src_h; |
| 16294 | new_plane_state->uapi.crtc_x = crtc_x; |
| 16295 | new_plane_state->uapi.crtc_y = crtc_y; |
| 16296 | new_plane_state->uapi.crtc_w = crtc_w; |
| 16297 | new_plane_state->uapi.crtc_h = crtc_h; |
| 16298 | |
| 16299 | intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state); |
| 16300 | |
| 16301 | ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state, |
| 16302 | old_plane_state, new_plane_state); |
| 16303 | if (ret) |
| 16304 | goto out_free; |
| 16305 | |
| 16306 | ret = intel_plane_pin_fb(new_plane_state); |
| 16307 | if (ret) |
| 16308 | goto out_free; |
| 16309 | |
| 16310 | intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb), |
| 16311 | ORIGIN_FLIP); |
| 16312 | intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb), |
| 16313 | to_intel_frontbuffer(new_plane_state->hw.fb), |
| 16314 | plane->frontbuffer_bit); |
| 16315 | |
| 16316 | /* Swap plane state */ |
| 16317 | plane->base.state = &new_plane_state->uapi; |
| 16318 | |
| 16319 | /* |
| 16320 | * We cannot swap crtc_state as it may be in use by an atomic commit or |
| 16321 | * page flip that's running simultaneously. If we swap crtc_state and |
| 16322 | * destroy the old state, we will cause a use-after-free there. |
| 16323 | * |
| 16324 | * Only update active_planes, which is needed for our internal |
| 16325 | * bookkeeping. Either value will do the right thing when updating |
| 16326 | * planes atomically. If the cursor was part of the atomic update then |
| 16327 | * we would have taken the slowpath. |
| 16328 | */ |
| 16329 | crtc_state->active_planes = new_crtc_state->active_planes; |
| 16330 | |
| 16331 | if (new_plane_state->uapi.visible) |
| 16332 | intel_update_plane(plane, crtc_state, new_plane_state); |
| 16333 | else |
| 16334 | intel_disable_plane(plane, crtc_state); |
| 16335 | |
| 16336 | intel_plane_unpin_fb(old_plane_state); |
| 16337 | |
| 16338 | out_free: |
| 16339 | if (new_crtc_state) |
| 16340 | intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi); |
| 16341 | if (ret) |
| 16342 | intel_plane_destroy_state(&plane->base, &new_plane_state->uapi); |
| 16343 | else |
| 16344 | intel_plane_destroy_state(&plane->base, &old_plane_state->uapi); |
| 16345 | return ret; |
| 16346 | |
| 16347 | slow: |
| 16348 | return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb, |
| 16349 | crtc_x, crtc_y, crtc_w, crtc_h, |
| 16350 | src_x, src_y, src_w, src_h, ctx); |
| 16351 | } |
| 16352 | |
| 16353 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
| 16354 | .update_plane = intel_legacy_cursor_update, |
| 16355 | .disable_plane = drm_atomic_helper_disable_plane, |
| 16356 | .destroy = intel_plane_destroy, |
| 16357 | .atomic_duplicate_state = intel_plane_duplicate_state, |
| 16358 | .atomic_destroy_state = intel_plane_destroy_state, |
| 16359 | .format_mod_supported = intel_cursor_format_mod_supported, |
| 16360 | }; |
| 16361 | |
| 16362 | static bool_Bool i9xx_plane_has_fbc(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 16363 | enum i9xx_plane_id i9xx_plane) |
| 16364 | { |
| 16365 | if (!HAS_FBC(dev_priv)((&(dev_priv)->__info)->display.has_fbc)) |
| 16366 | return false0; |
| 16367 | |
| 16368 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 16369 | return i9xx_plane == PLANE_A; /* tied to pipe A */ |
| 16370 | else if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
| 16371 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || |
| 16372 | i9xx_plane == PLANE_C; |
| 16373 | else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 16374 | return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; |
| 16375 | else |
| 16376 | return i9xx_plane == PLANE_A; |
| 16377 | } |
| 16378 | |
| 16379 | static struct intel_plane * |
| 16380 | intel_primary_plane_create(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 16381 | { |
| 16382 | struct intel_plane *plane; |
| 16383 | const struct drm_plane_funcs *plane_funcs; |
| 16384 | unsigned int supported_rotations; |
| 16385 | const u32 *formats; |
| 16386 | int num_formats; |
| 16387 | int ret, zpos; |
| 16388 | |
| 16389 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 16390 | return skl_universal_plane_create(dev_priv, pipe, |
| 16391 | PLANE_PRIMARY); |
| 16392 | |
| 16393 | plane = intel_plane_alloc(); |
| 16394 | if (IS_ERR(plane)) |
| 16395 | return plane; |
| 16396 | |
| 16397 | plane->pipe = pipe; |
| 16398 | /* |
| 16399 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS |
| 16400 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. |
| 16401 | */ |
| 16402 | if (HAS_FBC(dev_priv)((&(dev_priv)->__info)->display.has_fbc) && INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4 && |
| 16403 | INTEL_NUM_PIPES(dev_priv)(hweight8((&(dev_priv)->__info)->pipe_mask)) == 2) |
| 16404 | plane->i9xx_plane = (enum i9xx_plane_id) !pipe; |
| 16405 | else |
| 16406 | plane->i9xx_plane = (enum i9xx_plane_id) pipe; |
| 16407 | plane->id = PLANE_PRIMARY; |
| 16408 | plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id)({ extern char _ctassert[(!(8 * I915_MAX_PIPES > 32)) ? 1 : -1 ] __attribute__((__unused__)); extern char _ctassert[(!(I915_MAX_PLANES > 8)) ? 1 : -1 ] __attribute__((__unused__)); (1UL << ((plane->id) + 8 * (pipe))); }); |
| 16409 | |
| 16410 | plane->has_fbc = i9xx_plane_has_fbc(dev_priv, plane->i9xx_plane); |
| 16411 | if (plane->has_fbc) { |
| 16412 | struct intel_fbc *fbc = &dev_priv->fbc; |
| 16413 | |
| 16414 | fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; |
| 16415 | } |
| 16416 | |
| 16417 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 16418 | formats = vlv_primary_formats; |
| 16419 | num_formats = ARRAY_SIZE(vlv_primary_formats)(sizeof((vlv_primary_formats)) / sizeof((vlv_primary_formats) [0])); |
| 16420 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 16421 | /* |
| 16422 | * WaFP16GammaEnabling:ivb |
| 16423 | * "Workaround : When using the 64-bit format, the plane |
| 16424 | * output on each color channel has one quarter amplitude. |
| 16425 | * It can be brought up to full amplitude by using pipe |
| 16426 | * gamma correction or pipe color space conversion to |
| 16427 | * multiply the plane output by four." |
| 16428 | * |
| 16429 | * There is no dedicated plane gamma for the primary plane, |
| 16430 | * and using the pipe gamma/csc could conflict with other |
| 16431 | * planes, so we choose not to expose fp16 on IVB primary |
| 16432 | * planes. HSW primary planes no longer have this problem. |
| 16433 | */ |
| 16434 | if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) { |
| 16435 | formats = ivb_primary_formats; |
| 16436 | num_formats = ARRAY_SIZE(ivb_primary_formats)(sizeof((ivb_primary_formats)) / sizeof((ivb_primary_formats) [0])); |
| 16437 | } else { |
| 16438 | formats = i965_primary_formats; |
| 16439 | num_formats = ARRAY_SIZE(i965_primary_formats)(sizeof((i965_primary_formats)) / sizeof((i965_primary_formats )[0])); |
| 16440 | } |
| 16441 | } else { |
| 16442 | formats = i8xx_primary_formats; |
| 16443 | num_formats = ARRAY_SIZE(i8xx_primary_formats)(sizeof((i8xx_primary_formats)) / sizeof((i8xx_primary_formats )[0])); |
| 16444 | } |
| 16445 | |
| 16446 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 16447 | plane_funcs = &i965_plane_funcs; |
| 16448 | else |
| 16449 | plane_funcs = &i8xx_plane_funcs; |
| 16450 | |
| 16451 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 16452 | plane->min_cdclk = vlv_plane_min_cdclk; |
| 16453 | else if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 16454 | plane->min_cdclk = hsw_plane_min_cdclk; |
| 16455 | else if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) |
| 16456 | plane->min_cdclk = ivb_plane_min_cdclk; |
| 16457 | else |
| 16458 | plane->min_cdclk = i9xx_plane_min_cdclk; |
| 16459 | |
| 16460 | plane->max_stride = i9xx_plane_max_stride; |
| 16461 | plane->update_plane = i9xx_update_plane; |
| 16462 | plane->disable_plane = i9xx_disable_plane; |
| 16463 | plane->get_hw_state = i9xx_plane_get_hw_state; |
| 16464 | plane->check_plane = i9xx_plane_check; |
| 16465 | |
| 16466 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5 || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 16467 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
| 16468 | 0, plane_funcs, |
| 16469 | formats, num_formats, |
| 16470 | i9xx_format_modifiers, |
| 16471 | DRM_PLANE_TYPE_PRIMARY, |
| 16472 | "primary %c", pipe_name(pipe)((pipe) + 'A')); |
| 16473 | else |
| 16474 | ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, |
| 16475 | 0, plane_funcs, |
| 16476 | formats, num_formats, |
| 16477 | i9xx_format_modifiers, |
| 16478 | DRM_PLANE_TYPE_PRIMARY, |
| 16479 | "plane %c", |
| 16480 | plane_name(plane->i9xx_plane)((plane->i9xx_plane) + 'A')); |
| 16481 | if (ret) |
| 16482 | goto fail; |
| 16483 | |
| 16484 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && pipe == PIPE_B) { |
| 16485 | supported_rotations = |
| 16486 | DRM_MODE_ROTATE_0(1<<0) | DRM_MODE_ROTATE_180(1<<2) | |
| 16487 | DRM_MODE_REFLECT_X(1<<4); |
| 16488 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 16489 | supported_rotations = |
| 16490 | DRM_MODE_ROTATE_0(1<<0) | DRM_MODE_ROTATE_180(1<<2); |
| 16491 | } else { |
| 16492 | supported_rotations = DRM_MODE_ROTATE_0(1<<0); |
| 16493 | } |
| 16494 | |
| 16495 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 16496 | drm_plane_create_rotation_property(&plane->base, |
| 16497 | DRM_MODE_ROTATE_0(1<<0), |
| 16498 | supported_rotations); |
| 16499 | |
| 16500 | zpos = 0; |
| 16501 | drm_plane_create_zpos_immutable_property(&plane->base, zpos); |
| 16502 | |
| 16503 | drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); |
| 16504 | |
| 16505 | return plane; |
| 16506 | |
| 16507 | fail: |
| 16508 | intel_plane_free(plane); |
| 16509 | |
| 16510 | return ERR_PTR(ret); |
| 16511 | } |
| 16512 | |
| 16513 | static struct intel_plane * |
| 16514 | intel_cursor_plane_create(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 16515 | enum pipe pipe) |
| 16516 | { |
| 16517 | struct intel_plane *cursor; |
| 16518 | int ret, zpos; |
| 16519 | |
| 16520 | cursor = intel_plane_alloc(); |
| 16521 | if (IS_ERR(cursor)) |
| 16522 | return cursor; |
| 16523 | |
| 16524 | cursor->pipe = pipe; |
| 16525 | cursor->i9xx_plane = (enum i9xx_plane_id) pipe; |
| 16526 | cursor->id = PLANE_CURSOR; |
| 16527 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id)({ extern char _ctassert[(!(8 * I915_MAX_PIPES > 32)) ? 1 : -1 ] __attribute__((__unused__)); extern char _ctassert[(!(I915_MAX_PLANES > 8)) ? 1 : -1 ] __attribute__((__unused__)); (1UL << ((cursor->id) + 8 * (pipe))); }); |
| 16528 | |
| 16529 | if (IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G) || IS_I865G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I865G)) { |
| 16530 | cursor->max_stride = i845_cursor_max_stride; |
| 16531 | cursor->update_plane = i845_update_cursor; |
| 16532 | cursor->disable_plane = i845_disable_cursor; |
| 16533 | cursor->get_hw_state = i845_cursor_get_hw_state; |
| 16534 | cursor->check_plane = i845_check_cursor; |
| 16535 | } else { |
| 16536 | cursor->max_stride = i9xx_cursor_max_stride; |
| 16537 | cursor->update_plane = i9xx_update_cursor; |
| 16538 | cursor->disable_plane = i9xx_disable_cursor; |
| 16539 | cursor->get_hw_state = i9xx_cursor_get_hw_state; |
| 16540 | cursor->check_plane = i9xx_check_cursor; |
| 16541 | } |
| 16542 | |
| 16543 | cursor->cursor.base = ~0; |
| 16544 | cursor->cursor.cntl = ~0; |
| 16545 | |
| 16546 | if (IS_I845G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I845G) || IS_I865G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I865G) || HAS_CUR_FBC(dev_priv)(!((&(dev_priv)->__info)->display.has_gmch) && ((&(dev_priv)->__info)->gen) >= 7)) |
| 16547 | cursor->cursor.size = ~0; |
| 16548 | |
| 16549 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
| 16550 | 0, &intel_cursor_plane_funcs, |
| 16551 | intel_cursor_formats, |
| 16552 | ARRAY_SIZE(intel_cursor_formats)(sizeof((intel_cursor_formats)) / sizeof((intel_cursor_formats )[0])), |
| 16553 | cursor_format_modifiers, |
| 16554 | DRM_PLANE_TYPE_CURSOR, |
| 16555 | "cursor %c", pipe_name(pipe)((pipe) + 'A')); |
| 16556 | if (ret) |
| 16557 | goto fail; |
| 16558 | |
| 16559 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 16560 | drm_plane_create_rotation_property(&cursor->base, |
| 16561 | DRM_MODE_ROTATE_0(1<<0), |
| 16562 | DRM_MODE_ROTATE_0(1<<0) | |
| 16563 | DRM_MODE_ROTATE_180(1<<2)); |
| 16564 | |
| 16565 | zpos = RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->num_sprites[pipe] + 1; |
| 16566 | drm_plane_create_zpos_immutable_property(&cursor->base, zpos); |
| 16567 | |
| 16568 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) |
| 16569 | drm_plane_enable_fb_damage_clips(&cursor->base); |
| 16570 | |
| 16571 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
| 16572 | |
| 16573 | return cursor; |
| 16574 | |
| 16575 | fail: |
| 16576 | intel_plane_free(cursor); |
| 16577 | |
| 16578 | return ERR_PTR(ret); |
| 16579 | } |
| 16580 | |
| 16581 | #define INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0) \ |
| 16582 | .gamma_set = drm_atomic_helper_legacy_gamma_set, \ |
| 16583 | .set_config = drm_atomic_helper_set_config, \ |
| 16584 | .destroy = intel_crtc_destroy, \ |
| 16585 | .page_flip = drm_atomic_helper_page_flip, \ |
| 16586 | .atomic_duplicate_state = intel_crtc_duplicate_state, \ |
| 16587 | .atomic_destroy_state = intel_crtc_destroy_state, \ |
| 16588 | .set_crc_source = intel_crtc_set_crc_source((void *)0), \ |
| 16589 | .verify_crc_source = intel_crtc_verify_crc_source((void *)0), \ |
| 16590 | .get_crc_sources = intel_crtc_get_crc_sources((void *)0) |
| 16591 | |
| 16592 | static const struct drm_crtc_funcs bdw_crtc_funcs = { |
| 16593 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16594 | |
| 16595 | .get_vblank_counter = g4x_get_vblank_counter, |
| 16596 | .enable_vblank = bdw_enable_vblank, |
| 16597 | .disable_vblank = bdw_disable_vblank, |
| 16598 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16599 | }; |
| 16600 | |
| 16601 | static const struct drm_crtc_funcs ilk_crtc_funcs = { |
| 16602 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16603 | |
| 16604 | .get_vblank_counter = g4x_get_vblank_counter, |
| 16605 | .enable_vblank = ilk_enable_vblank, |
| 16606 | .disable_vblank = ilk_disable_vblank, |
| 16607 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16608 | }; |
| 16609 | |
| 16610 | static const struct drm_crtc_funcs g4x_crtc_funcs = { |
| 16611 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16612 | |
| 16613 | .get_vblank_counter = g4x_get_vblank_counter, |
| 16614 | .enable_vblank = i965_enable_vblank, |
| 16615 | .disable_vblank = i965_disable_vblank, |
| 16616 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16617 | }; |
| 16618 | |
| 16619 | static const struct drm_crtc_funcs i965_crtc_funcs = { |
| 16620 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16621 | |
| 16622 | .get_vblank_counter = i915_get_vblank_counter, |
| 16623 | .enable_vblank = i965_enable_vblank, |
| 16624 | .disable_vblank = i965_disable_vblank, |
| 16625 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16626 | }; |
| 16627 | |
| 16628 | static const struct drm_crtc_funcs i915gm_crtc_funcs = { |
| 16629 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16630 | |
| 16631 | .get_vblank_counter = i915_get_vblank_counter, |
| 16632 | .enable_vblank = i915gm_enable_vblank, |
| 16633 | .disable_vblank = i915gm_disable_vblank, |
| 16634 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16635 | }; |
| 16636 | |
| 16637 | static const struct drm_crtc_funcs i915_crtc_funcs = { |
| 16638 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16639 | |
| 16640 | .get_vblank_counter = i915_get_vblank_counter, |
| 16641 | .enable_vblank = i8xx_enable_vblank, |
| 16642 | .disable_vblank = i8xx_disable_vblank, |
| 16643 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16644 | }; |
| 16645 | |
| 16646 | static const struct drm_crtc_funcs i8xx_crtc_funcs = { |
| 16647 | INTEL_CRTC_FUNCS.gamma_set = drm_atomic_helper_legacy_gamma_set, .set_config = drm_atomic_helper_set_config, .destroy = intel_crtc_destroy, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = intel_crtc_duplicate_state, .atomic_destroy_state = intel_crtc_destroy_state , .set_crc_source = ((void *)0), .verify_crc_source = ((void * )0), .get_crc_sources = ((void *)0), |
| 16648 | |
| 16649 | /* no hw vblank counter */ |
| 16650 | .enable_vblank = i8xx_enable_vblank, |
| 16651 | .disable_vblank = i8xx_disable_vblank, |
| 16652 | .get_vblank_timestamp = intel_crtc_get_vblank_timestamp, |
| 16653 | }; |
| 16654 | |
| 16655 | static struct intel_crtc *intel_crtc_alloc(void) |
| 16656 | { |
| 16657 | struct intel_crtc_state *crtc_state; |
| 16658 | struct intel_crtc *crtc; |
| 16659 | |
| 16660 | crtc = kzalloc(sizeof(*crtc), GFP_KERNEL(0x0001 | 0x0004)); |
| 16661 | if (!crtc) |
| 16662 | return ERR_PTR(-ENOMEM12); |
| 16663 | |
| 16664 | crtc_state = intel_crtc_state_alloc(crtc); |
| 16665 | if (!crtc_state) { |
| 16666 | kfree(crtc); |
| 16667 | return ERR_PTR(-ENOMEM12); |
| 16668 | } |
| 16669 | |
| 16670 | crtc->base.state = &crtc_state->uapi; |
| 16671 | crtc->config = crtc_state; |
| 16672 | |
| 16673 | return crtc; |
| 16674 | } |
| 16675 | |
| 16676 | static void intel_crtc_free(struct intel_crtc *crtc) |
| 16677 | { |
| 16678 | intel_crtc_destroy_state(&crtc->base, crtc->base.state); |
| 16679 | kfree(crtc); |
| 16680 | } |
| 16681 | |
| 16682 | static void intel_plane_possible_crtcs_init(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 16683 | { |
| 16684 | struct intel_plane *plane; |
| 16685 | |
| 16686 | for_each_intel_plane(&dev_priv->drm, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane), base.head) );}); &plane ->base.head != (&(&dev_priv->drm)->mode_config .plane_list); plane = ({ const __typeof( ((__typeof(*plane) * )0)->base.head ) *__mptr = (plane->base.head.next); (__typeof (*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane ), base.head) );})) { |
| 16687 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
| 16688 | plane->pipe); |
| 16689 | |
| 16690 | plane->base.possible_crtcs = drm_crtc_mask(&crtc->base); |
| 16691 | } |
| 16692 | } |
| 16693 | |
| 16694 | static int intel_crtc_init(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 16695 | { |
| 16696 | struct intel_plane *primary, *cursor; |
| 16697 | const struct drm_crtc_funcs *funcs; |
| 16698 | struct intel_crtc *crtc; |
| 16699 | int sprite, ret; |
| 16700 | |
| 16701 | crtc = intel_crtc_alloc(); |
| 16702 | if (IS_ERR(crtc)) |
| 16703 | return PTR_ERR(crtc); |
| 16704 | |
| 16705 | crtc->pipe = pipe; |
| 16706 | crtc->num_scalers = RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->num_scalers[pipe]; |
| 16707 | |
| 16708 | primary = intel_primary_plane_create(dev_priv, pipe); |
| 16709 | if (IS_ERR(primary)) { |
| 16710 | ret = PTR_ERR(primary); |
| 16711 | goto fail; |
| 16712 | } |
| 16713 | crtc->plane_ids_mask |= BIT(primary->id)(1UL << (primary->id)); |
| 16714 | |
| 16715 | for_each_sprite(dev_priv, pipe, sprite)for ((sprite) = 0; (sprite) < (&(dev_priv)->__runtime )->num_sprites[(pipe)]; (sprite)++) { |
| 16716 | struct intel_plane *plane; |
| 16717 | |
| 16718 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
| 16719 | if (IS_ERR(plane)) { |
| 16720 | ret = PTR_ERR(plane); |
| 16721 | goto fail; |
| 16722 | } |
| 16723 | crtc->plane_ids_mask |= BIT(plane->id)(1UL << (plane->id)); |
| 16724 | } |
| 16725 | |
| 16726 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
| 16727 | if (IS_ERR(cursor)) { |
| 16728 | ret = PTR_ERR(cursor); |
| 16729 | goto fail; |
| 16730 | } |
| 16731 | crtc->plane_ids_mask |= BIT(cursor->id)(1UL << (cursor->id)); |
| 16732 | |
| 16733 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) { |
| 16734 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) || |
| 16735 | IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 16736 | funcs = &g4x_crtc_funcs; |
| 16737 | else if (IS_GEN(dev_priv, 4)(0 + (&(dev_priv)->__info)->gen == (4))) |
| 16738 | funcs = &i965_crtc_funcs; |
| 16739 | else if (IS_I945GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I945GM) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) |
| 16740 | funcs = &i915gm_crtc_funcs; |
| 16741 | else if (IS_GEN(dev_priv, 3)(0 + (&(dev_priv)->__info)->gen == (3))) |
| 16742 | funcs = &i915_crtc_funcs; |
| 16743 | else |
| 16744 | funcs = &i8xx_crtc_funcs; |
| 16745 | } else { |
| 16746 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 8) |
| 16747 | funcs = &bdw_crtc_funcs; |
| 16748 | else |
| 16749 | funcs = &ilk_crtc_funcs; |
| 16750 | } |
| 16751 | |
| 16752 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &crtc->base, |
| 16753 | &primary->base, &cursor->base, |
| 16754 | funcs, "pipe %c", pipe_name(pipe)((pipe) + 'A')); |
| 16755 | if (ret) |
| 16756 | goto fail; |
| 16757 | |
| 16758 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->pipe_to_crtc_mapping) ||((!(pipe >= (sizeof((dev_priv->pipe_to_crtc_mapping)) / sizeof((dev_priv->pipe_to_crtc_mapping)[0])) || dev_priv-> pipe_to_crtc_mapping[pipe] != ((void *)0))) ? (void)0 : __assert ("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 16759, "!(pipe >= (sizeof((dev_priv->pipe_to_crtc_mapping)) / sizeof((dev_priv->pipe_to_crtc_mapping)[0])) || dev_priv->pipe_to_crtc_mapping[pipe] != ((void *)0))" )) |
| 16759 | dev_priv->pipe_to_crtc_mapping[pipe] != NULL)((!(pipe >= (sizeof((dev_priv->pipe_to_crtc_mapping)) / sizeof((dev_priv->pipe_to_crtc_mapping)[0])) || dev_priv-> pipe_to_crtc_mapping[pipe] != ((void *)0))) ? (void)0 : __assert ("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 16759, "!(pipe >= (sizeof((dev_priv->pipe_to_crtc_mapping)) / sizeof((dev_priv->pipe_to_crtc_mapping)[0])) || dev_priv->pipe_to_crtc_mapping[pipe] != ((void *)0))" )); |
| 16760 | dev_priv->pipe_to_crtc_mapping[pipe] = crtc; |
| 16761 | |
| 16762 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9) { |
| 16763 | enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; |
| 16764 | |
| 16765 | BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||((!(i9xx_plane >= (sizeof((dev_priv->plane_to_crtc_mapping )) / sizeof((dev_priv->plane_to_crtc_mapping)[0])) || dev_priv ->plane_to_crtc_mapping[i9xx_plane] != ((void *)0))) ? (void )0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 16766, "!(i9xx_plane >= (sizeof((dev_priv->plane_to_crtc_mapping)) / sizeof((dev_priv->plane_to_crtc_mapping)[0])) || dev_priv->plane_to_crtc_mapping[i9xx_plane] != ((void *)0))" )) |
| 16766 | dev_priv->plane_to_crtc_mapping[i9xx_plane] != NULL)((!(i9xx_plane >= (sizeof((dev_priv->plane_to_crtc_mapping )) / sizeof((dev_priv->plane_to_crtc_mapping)[0])) || dev_priv ->plane_to_crtc_mapping[i9xx_plane] != ((void *)0))) ? (void )0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/display/intel_display.c" , 16766, "!(i9xx_plane >= (sizeof((dev_priv->plane_to_crtc_mapping)) / sizeof((dev_priv->plane_to_crtc_mapping)[0])) || dev_priv->plane_to_crtc_mapping[i9xx_plane] != ((void *)0))" )); |
| 16767 | dev_priv->plane_to_crtc_mapping[i9xx_plane] = crtc; |
| 16768 | } |
| 16769 | |
| 16770 | intel_color_init(crtc); |
| 16771 | |
| 16772 | intel_crtc_crc_init(crtc); |
| 16773 | |
| 16774 | drm_WARN_ON(&dev_priv->drm, drm_crtc_index(&crtc->base) != crtc->pipe)({ int __ret = !!((drm_crtc_index(&crtc->base) != crtc ->pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "drm_crtc_index(&crtc->base) != crtc->pipe" ")"); __builtin_expect(!!(__ret), 0); }); |
| 16775 | |
| 16776 | return 0; |
| 16777 | |
| 16778 | fail: |
| 16779 | intel_crtc_free(crtc); |
| 16780 | |
| 16781 | return ret; |
| 16782 | } |
| 16783 | |
| 16784 | int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data, |
| 16785 | struct drm_file *file) |
| 16786 | { |
| 16787 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
| 16788 | struct drm_crtc *drmmode_crtc; |
| 16789 | struct intel_crtc *crtc; |
| 16790 | |
| 16791 | drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id); |
| 16792 | if (!drmmode_crtc) |
| 16793 | return -ENOENT2; |
| 16794 | |
| 16795 | crtc = to_intel_crtc(drmmode_crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (drmmode_crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}); |
| 16796 | pipe_from_crtc_id->pipe = crtc->pipe; |
| 16797 | |
| 16798 | return 0; |
| 16799 | } |
| 16800 | |
| 16801 | static u32 intel_encoder_possible_clones(struct intel_encoder *encoder) |
| 16802 | { |
| 16803 | struct drm_device *dev = encoder->base.dev; |
| 16804 | struct intel_encoder *source_encoder; |
| 16805 | u32 possible_clones = 0; |
| 16806 | |
| 16807 | for_each_intel_encoder(dev, source_encoder)for (source_encoder = ({ const __typeof( ((__typeof(*source_encoder ) *)0)->base.head ) *__mptr = ((&(dev)->mode_config .encoder_list)->next); (__typeof(*source_encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*source_encoder), base .head) );}); &source_encoder->base.head != (&(dev) ->mode_config.encoder_list); source_encoder = ({ const __typeof ( ((__typeof(*source_encoder) *)0)->base.head ) *__mptr = ( source_encoder->base.head.next); (__typeof(*source_encoder ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*source_encoder ), base.head) );})) { |
| 16808 | if (encoders_cloneable(encoder, source_encoder)) |
| 16809 | possible_clones |= drm_encoder_mask(&source_encoder->base); |
| 16810 | } |
| 16811 | |
| 16812 | return possible_clones; |
| 16813 | } |
| 16814 | |
| 16815 | static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder) |
| 16816 | { |
| 16817 | struct drm_device *dev = encoder->base.dev; |
| 16818 | struct intel_crtc *crtc; |
| 16819 | u32 possible_crtcs = 0; |
| 16820 | |
| 16821 | for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof ( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc-> base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );})) { |
| 16822 | if (encoder->pipe_mask & BIT(crtc->pipe)(1UL << (crtc->pipe))) |
| 16823 | possible_crtcs |= drm_crtc_mask(&crtc->base); |
| 16824 | } |
| 16825 | |
| 16826 | return possible_crtcs; |
| 16827 | } |
| 16828 | |
| 16829 | static bool_Bool ilk_has_edp_a(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 16830 | { |
| 16831 | if (!IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile)) |
| 16832 | return false0; |
| 16833 | |
| 16834 | if ((intel_de_read(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) })) & DP_DETECTED(1 << 2)) == 0) |
| 16835 | return false0; |
| 16836 | |
| 16837 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5)) && (intel_de_read(dev_priv, FUSE_STRAP((const i915_reg_t){ .reg = (0x42014) })) & ILK_eDP_A_DISABLE(1 << 24))) |
| 16838 | return false0; |
| 16839 | |
| 16840 | return true1; |
| 16841 | } |
| 16842 | |
| 16843 | static bool_Bool intel_ddi_crt_present(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 16844 | { |
| 16845 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 16846 | return false0; |
| 16847 | |
| 16848 | if (IS_HSW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, (0)) || IS_BDW_ULT(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, (0))) |
| 16849 | return false0; |
| 16850 | |
| 16851 | if (HAS_PCH_LPT_H(dev_priv)(((dev_priv)->pch_id) == 0x8c00 || ((dev_priv)->pch_id) == 0x8c80) && |
| 16852 | intel_de_read(dev_priv, SFUSE_STRAP((const i915_reg_t){ .reg = (0xc2014) })) & SFUSE_STRAP_CRT_DISABLED(1 << 6)) |
| 16853 | return false0; |
| 16854 | |
| 16855 | /* DDI E can't be used if DDI A requires 4 lanes */ |
| 16856 | if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)((const i915_reg_t){ .reg = (((0x64000) + (PORT_A) * ((0x64100 ) - (0x64000)))) })) & DDI_A_4_LANES(1 << 4)) |
| 16857 | return false0; |
| 16858 | |
| 16859 | if (!dev_priv->vbt.int_crt_support) |
| 16860 | return false0; |
| 16861 | |
| 16862 | return true1; |
| 16863 | } |
| 16864 | |
| 16865 | void intel_pps_unlock_regs_wa(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 16866 | { |
| 16867 | int pps_num; |
| 16868 | int pps_idx; |
| 16869 | |
| 16870 | if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
| 16871 | return; |
| 16872 | /* |
| 16873 | * This w/a is needed at least on CPT/PPT, but to be sure apply it |
| 16874 | * everywhere where registers can be write protected. |
| 16875 | */ |
| 16876 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 16877 | pps_num = 2; |
| 16878 | else |
| 16879 | pps_num = 1; |
| 16880 | |
| 16881 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { |
| 16882 | u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (pps_idx) * 0x100) })); |
| 16883 | |
| 16884 | val = (val & ~PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) | PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )); |
| 16885 | intel_de_write(dev_priv, PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->pps_mmio_base - 0x61200 + (0x61204) + (pps_idx) * 0x100) }), val); |
| 16886 | } |
| 16887 | } |
| 16888 | |
| 16889 | static void intel_pps_init(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 16890 | { |
| 16891 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE) || IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) |
| 16892 | dev_priv->pps_mmio_base = PCH_PPS_BASE0xC7200; |
| 16893 | else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
| 16894 | dev_priv->pps_mmio_base = VLV_PPS_BASE(0x180000 + 0x61200); |
| 16895 | else |
| 16896 | dev_priv->pps_mmio_base = PPS_BASE0x61200; |
| 16897 | |
| 16898 | intel_pps_unlock_regs_wa(dev_priv); |
| 16899 | } |
| 16900 | |
| 16901 | static void intel_setup_outputs(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 16902 | { |
| 16903 | struct intel_encoder *encoder; |
| 16904 | bool_Bool dpd_is_edp = false0; |
| 16905 | |
| 16906 | intel_pps_init(dev_priv); |
| 16907 | |
| 16908 | if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__info)->pipe_mask != 0)) |
| 16909 | return; |
| 16910 | |
| 16911 | if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) { |
| 16912 | intel_ddi_init(dev_priv, PORT_A); |
| 16913 | intel_ddi_init(dev_priv, PORT_B); |
| 16914 | intel_ddi_init(dev_priv, PORT_D); /* DDI TC1 */ |
| 16915 | intel_ddi_init(dev_priv, PORT_E); /* DDI TC2 */ |
| 16916 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 12) { |
| 16917 | intel_ddi_init(dev_priv, PORT_A); |
| 16918 | intel_ddi_init(dev_priv, PORT_B); |
| 16919 | intel_ddi_init(dev_priv, PORT_D); |
| 16920 | intel_ddi_init(dev_priv, PORT_E); |
| 16921 | intel_ddi_init(dev_priv, PORT_F); |
| 16922 | intel_ddi_init(dev_priv, PORT_G); |
| 16923 | intel_ddi_init(dev_priv, PORT_H); |
| 16924 | intel_ddi_init(dev_priv, PORT_I); |
| 16925 | icl_dsi_init(dev_priv); |
| 16926 | } else if (IS_ELKHARTLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) { |
| 16927 | intel_ddi_init(dev_priv, PORT_A); |
| 16928 | intel_ddi_init(dev_priv, PORT_B); |
| 16929 | intel_ddi_init(dev_priv, PORT_C); |
| 16930 | intel_ddi_init(dev_priv, PORT_D); |
| 16931 | icl_dsi_init(dev_priv); |
| 16932 | } else if (IS_GEN(dev_priv, 11)(0 + (&(dev_priv)->__info)->gen == (11))) { |
| 16933 | intel_ddi_init(dev_priv, PORT_A); |
| 16934 | intel_ddi_init(dev_priv, PORT_B); |
| 16935 | intel_ddi_init(dev_priv, PORT_C); |
| 16936 | intel_ddi_init(dev_priv, PORT_D); |
| 16937 | intel_ddi_init(dev_priv, PORT_E); |
| 16938 | /* |
| 16939 | * On some ICL SKUs port F is not present. No strap bits for |
| 16940 | * this, so rely on VBT. |
| 16941 | * Work around broken VBTs on SKUs known to have no port F. |
| 16942 | */ |
| 16943 | if (IS_ICL_WITH_PORT_F(dev_priv)IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, (0)) && |
| 16944 | intel_bios_is_port_present(dev_priv, PORT_F)) |
| 16945 | intel_ddi_init(dev_priv, PORT_F); |
| 16946 | |
| 16947 | icl_dsi_init(dev_priv); |
| 16948 | } else if (IS_GEN9_LP(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && ((&(dev_priv)->__info)->is_lp))) { |
| 16949 | /* |
| 16950 | * FIXME: Broxton doesn't support port detection via the |
| 16951 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to |
| 16952 | * detect the ports. |
| 16953 | */ |
| 16954 | intel_ddi_init(dev_priv, PORT_A); |
| 16955 | intel_ddi_init(dev_priv, PORT_B); |
| 16956 | intel_ddi_init(dev_priv, PORT_C); |
| 16957 | |
| 16958 | vlv_dsi_init(dev_priv); |
| 16959 | } else if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) { |
| 16960 | int found; |
| 16961 | |
| 16962 | if (intel_ddi_crt_present(dev_priv)) |
| 16963 | intel_crt_init(dev_priv); |
| 16964 | |
| 16965 | /* |
| 16966 | * Haswell uses DDI functions to detect digital outputs. |
| 16967 | * On SKL pre-D0 the strap isn't connected, so we assume |
| 16968 | * it's there. |
| 16969 | */ |
| 16970 | found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)((const i915_reg_t){ .reg = (((0x64000) + (PORT_A) * ((0x64100 ) - (0x64000)))) })) & DDI_INIT_DISPLAY_DETECTED(1 << 0); |
| 16971 | /* WaIgnoreDDIAStrap: skl */ |
| 16972 | if (found || IS_GEN9_BC(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && !((&(dev_priv)->__info)->is_lp))) |
| 16973 | intel_ddi_init(dev_priv, PORT_A); |
| 16974 | |
| 16975 | /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP |
| 16976 | * register */ |
| 16977 | found = intel_de_read(dev_priv, SFUSE_STRAP((const i915_reg_t){ .reg = (0xc2014) })); |
| 16978 | |
| 16979 | if (found & SFUSE_STRAP_DDIB_DETECTED(1 << 2)) |
| 16980 | intel_ddi_init(dev_priv, PORT_B); |
| 16981 | if (found & SFUSE_STRAP_DDIC_DETECTED(1 << 1)) |
| 16982 | intel_ddi_init(dev_priv, PORT_C); |
| 16983 | if (found & SFUSE_STRAP_DDID_DETECTED(1 << 0)) |
| 16984 | intel_ddi_init(dev_priv, PORT_D); |
| 16985 | if (found & SFUSE_STRAP_DDIF_DETECTED(1 << 3)) |
| 16986 | intel_ddi_init(dev_priv, PORT_F); |
| 16987 | /* |
| 16988 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. |
| 16989 | */ |
| 16990 | if (IS_GEN9_BC(dev_priv)((0 + (&(dev_priv)->__info)->gen == (9)) && !((&(dev_priv)->__info)->is_lp)) && |
| 16991 | intel_bios_is_port_present(dev_priv, PORT_E)) |
| 16992 | intel_ddi_init(dev_priv, PORT_E); |
| 16993 | |
| 16994 | } else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 16995 | int found; |
| 16996 | |
| 16997 | /* |
| 16998 | * intel_edp_init_connector() depends on this completing first, |
| 16999 | * to prevent the registration of both eDP and LVDS and the |
| 17000 | * incorrect sharing of the PPS. |
| 17001 | */ |
| 17002 | intel_lvds_init(dev_priv); |
| 17003 | intel_crt_init(dev_priv); |
| 17004 | |
| 17005 | dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D); |
| 17006 | |
| 17007 | if (ilk_has_edp_a(dev_priv)) |
| 17008 | intel_dp_init(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), PORT_A); |
| 17009 | |
| 17010 | if (intel_de_read(dev_priv, PCH_HDMIB((const i915_reg_t){ .reg = (0xe1140) })) & SDVO_DETECTED(1 << 2)) { |
| 17011 | /* PCH SDVOB multiplex with HDMIB */ |
| 17012 | found = intel_sdvo_init(dev_priv, PCH_SDVOB((const i915_reg_t){ .reg = (0xe1140) }), PORT_B); |
| 17013 | if (!found) |
| 17014 | intel_hdmi_init(dev_priv, PCH_HDMIB((const i915_reg_t){ .reg = (0xe1140) }), PORT_B); |
| 17015 | if (!found && (intel_de_read(dev_priv, PCH_DP_B((const i915_reg_t){ .reg = (0xe4100) })) & DP_DETECTED(1 << 2))) |
| 17016 | intel_dp_init(dev_priv, PCH_DP_B((const i915_reg_t){ .reg = (0xe4100) }), PORT_B); |
| 17017 | } |
| 17018 | |
| 17019 | if (intel_de_read(dev_priv, PCH_HDMIC((const i915_reg_t){ .reg = (0xe1150) })) & SDVO_DETECTED(1 << 2)) |
| 17020 | intel_hdmi_init(dev_priv, PCH_HDMIC((const i915_reg_t){ .reg = (0xe1150) }), PORT_C); |
| 17021 | |
| 17022 | if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID((const i915_reg_t){ .reg = (0xe1160) })) & SDVO_DETECTED(1 << 2)) |
| 17023 | intel_hdmi_init(dev_priv, PCH_HDMID((const i915_reg_t){ .reg = (0xe1160) }), PORT_D); |
| 17024 | |
| 17025 | if (intel_de_read(dev_priv, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) })) & DP_DETECTED(1 << 2)) |
| 17026 | intel_dp_init(dev_priv, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) }), PORT_C); |
| 17027 | |
| 17028 | if (intel_de_read(dev_priv, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) })) & DP_DETECTED(1 << 2)) |
| 17029 | intel_dp_init(dev_priv, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) }), PORT_D); |
| 17030 | } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 17031 | bool_Bool has_edp, has_port; |
| 17032 | |
| 17033 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && dev_priv->vbt.int_crt_support) |
| 17034 | intel_crt_init(dev_priv); |
| 17035 | |
| 17036 | /* |
| 17037 | * The DP_DETECTED bit is the latched state of the DDC |
| 17038 | * SDA pin at boot. However since eDP doesn't require DDC |
| 17039 | * (no way to plug in a DP->HDMI dongle) the DDC pins for |
| 17040 | * eDP ports may have been muxed to an alternate function. |
| 17041 | * Thus we can't rely on the DP_DETECTED bit alone to detect |
| 17042 | * eDP ports. Consult the VBT as well as DP_DETECTED to |
| 17043 | * detect eDP ports. |
| 17044 | * |
| 17045 | * Sadly the straps seem to be missing sometimes even for HDMI |
| 17046 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap |
| 17047 | * and VBT for the presence of the port. Additionally we can't |
| 17048 | * trust the port type the VBT declares as we've seen at least |
| 17049 | * HDMI ports that the VBT claim are DP or eDP. |
| 17050 | */ |
| 17051 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_B); |
| 17052 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
| 17053 | if (intel_de_read(dev_priv, VLV_DP_B((const i915_reg_t){ .reg = (0x180000 + 0x64100) })) & DP_DETECTED(1 << 2) || has_port) |
| 17054 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B((const i915_reg_t){ .reg = (0x180000 + 0x64100) }), PORT_B); |
| 17055 | if ((intel_de_read(dev_priv, VLV_HDMIB((const i915_reg_t){ .reg = (0x180000 + 0x61140) })) & SDVO_DETECTED(1 << 2) || has_port) && !has_edp) |
| 17056 | intel_hdmi_init(dev_priv, VLV_HDMIB((const i915_reg_t){ .reg = (0x180000 + 0x61140) }), PORT_B); |
| 17057 | |
| 17058 | has_edp = intel_dp_is_port_edp(dev_priv, PORT_C); |
| 17059 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
| 17060 | if (intel_de_read(dev_priv, VLV_DP_C((const i915_reg_t){ .reg = (0x180000 + 0x64200) })) & DP_DETECTED(1 << 2) || has_port) |
| 17061 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C((const i915_reg_t){ .reg = (0x180000 + 0x64200) }), PORT_C); |
| 17062 | if ((intel_de_read(dev_priv, VLV_HDMIC((const i915_reg_t){ .reg = (0x180000 + 0x61160) })) & SDVO_DETECTED(1 << 2) || has_port) && !has_edp) |
| 17063 | intel_hdmi_init(dev_priv, VLV_HDMIC((const i915_reg_t){ .reg = (0x180000 + 0x61160) }), PORT_C); |
| 17064 | |
| 17065 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 17066 | /* |
| 17067 | * eDP not supported on port D, |
| 17068 | * so no need to worry about it |
| 17069 | */ |
| 17070 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); |
| 17071 | if (intel_de_read(dev_priv, CHV_DP_D((const i915_reg_t){ .reg = (0x180000 + 0x64300) })) & DP_DETECTED(1 << 2) || has_port) |
| 17072 | intel_dp_init(dev_priv, CHV_DP_D((const i915_reg_t){ .reg = (0x180000 + 0x64300) }), PORT_D); |
| 17073 | if (intel_de_read(dev_priv, CHV_HDMID((const i915_reg_t){ .reg = (0x180000 + 0x6116C) })) & SDVO_DETECTED(1 << 2) || has_port) |
| 17074 | intel_hdmi_init(dev_priv, CHV_HDMID((const i915_reg_t){ .reg = (0x180000 + 0x6116C) }), PORT_D); |
| 17075 | } |
| 17076 | |
| 17077 | vlv_dsi_init(dev_priv); |
| 17078 | } else if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 17079 | intel_lvds_init(dev_priv); |
| 17080 | intel_crt_init(dev_priv); |
| 17081 | } else if (IS_GEN_RANGE(dev_priv, 3, 4)(!!((&(dev_priv)->__info)->gen_mask & ( 0 + 0 + (((~0UL) >> (64 - (((4)) - 1) - 1)) & ((~0UL) << (((3)) - 1))))))) { |
| 17082 | bool_Bool found = false0; |
| 17083 | |
| 17084 | if (IS_MOBILE(dev_priv)((&(dev_priv)->__info)->is_mobile)) |
| 17085 | intel_lvds_init(dev_priv); |
| 17086 | |
| 17087 | intel_crt_init(dev_priv); |
| 17088 | |
| 17089 | if (intel_de_read(dev_priv, GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) })) & SDVO_DETECTED(1 << 2)) { |
| 17090 | drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "probing SDVOB\n" ); |
| 17091 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) }), PORT_B); |
| 17092 | if (!found && IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
| 17093 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "probing HDMI on SDVOB\n" ) |
| 17094 | "probing HDMI on SDVOB\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "probing HDMI on SDVOB\n" ); |
| 17095 | intel_hdmi_init(dev_priv, GEN4_HDMIB((const i915_reg_t){ .reg = (0x61140) }), PORT_B); |
| 17096 | } |
| 17097 | |
| 17098 | if (!found && IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 17099 | intel_dp_init(dev_priv, DP_B((const i915_reg_t){ .reg = (0x64100) }), PORT_B); |
| 17100 | } |
| 17101 | |
| 17102 | /* Before G4X SDVOC doesn't have its own detect register */ |
| 17103 | |
| 17104 | if (intel_de_read(dev_priv, GEN3_SDVOB((const i915_reg_t){ .reg = (0x61140) })) & SDVO_DETECTED(1 << 2)) { |
| 17105 | drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "probing SDVOC\n" ); |
| 17106 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) }), PORT_C); |
| 17107 | } |
| 17108 | |
| 17109 | if (!found && (intel_de_read(dev_priv, GEN3_SDVOC((const i915_reg_t){ .reg = (0x61160) })) & SDVO_DETECTED(1 << 2))) { |
| 17110 | |
| 17111 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
| 17112 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "probing HDMI on SDVOC\n" ) |
| 17113 | "probing HDMI on SDVOC\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "probing HDMI on SDVOC\n" ); |
| 17114 | intel_hdmi_init(dev_priv, GEN4_HDMIC((const i915_reg_t){ .reg = (0x61160) }), PORT_C); |
| 17115 | } |
| 17116 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) |
| 17117 | intel_dp_init(dev_priv, DP_C((const i915_reg_t){ .reg = (0x64200) }), PORT_C); |
| 17118 | } |
| 17119 | |
| 17120 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 )) && (intel_de_read(dev_priv, DP_D((const i915_reg_t){ .reg = (0x64300) })) & DP_DETECTED(1 << 2))) |
| 17121 | intel_dp_init(dev_priv, DP_D((const i915_reg_t){ .reg = (0x64300) }), PORT_D); |
| 17122 | |
| 17123 | if (SUPPORTS_TV(dev_priv)((&(dev_priv)->__info)->display.supports_tv)) |
| 17124 | intel_tv_init(dev_priv); |
| 17125 | } else if (IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) { |
| 17126 | if (IS_I85X(dev_priv)IS_PLATFORM(dev_priv, INTEL_I85X)) |
| 17127 | intel_lvds_init(dev_priv); |
| 17128 | |
| 17129 | intel_crt_init(dev_priv); |
| 17130 | intel_dvo_init(dev_priv); |
| 17131 | } |
| 17132 | |
| 17133 | intel_psr_init(dev_priv); |
| 17134 | |
| 17135 | for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) { |
| 17136 | encoder->base.possible_crtcs = |
| 17137 | intel_encoder_possible_crtcs(encoder); |
| 17138 | encoder->base.possible_clones = |
| 17139 | intel_encoder_possible_clones(encoder); |
| 17140 | } |
| 17141 | |
| 17142 | intel_init_pch_refclk(dev_priv); |
| 17143 | |
| 17144 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
| 17145 | } |
| 17146 | |
| 17147 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
| 17148 | { |
| 17149 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb)({ const __typeof( ((struct intel_framebuffer *)0)->base ) *__mptr = (fb); (struct intel_framebuffer *)( (char *)__mptr - __builtin_offsetof(struct intel_framebuffer, base) );}); |
| 17150 | |
| 17151 | drm_framebuffer_cleanup(fb); |
| 17152 | intel_frontbuffer_put(intel_fb->frontbuffer); |
| 17153 | |
| 17154 | kfree(intel_fb); |
| 17155 | } |
| 17156 | |
| 17157 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, |
| 17158 | struct drm_file *file, |
| 17159 | unsigned int *handle) |
| 17160 | { |
| 17161 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 17162 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(obj->base.dev); |
| 17163 | |
| 17164 | if (obj->userptr.mm) { |
| 17165 | drm_dbg(&i915->drm,drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "attempting to use a userptr for a framebuffer, denied\n" ) |
| 17166 | "attempting to use a userptr for a framebuffer, denied\n")drm_dev_dbg((&i915->drm)->dev, DRM_UT_DRIVER, "attempting to use a userptr for a framebuffer, denied\n" ); |
| 17167 | return -EINVAL22; |
| 17168 | } |
| 17169 | |
| 17170 | return drm_gem_handle_create(file, &obj->base, handle); |
| 17171 | } |
| 17172 | |
| 17173 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
| 17174 | struct drm_file *file, |
| 17175 | unsigned flags, unsigned color, |
| 17176 | struct drm_clip_rect *clips, |
| 17177 | unsigned num_clips) |
| 17178 | { |
| 17179 | struct drm_i915_gem_object *obj = intel_fb_obj(fb)((fb) ? to_intel_bo((fb)->obj[0]) : ((void *)0)); |
| 17180 | |
| 17181 | i915_gem_object_flush_if_display(obj); |
| 17182 | intel_frontbuffer_flush(to_intel_frontbuffer(fb), ORIGIN_DIRTYFB); |
| 17183 | |
| 17184 | return 0; |
| 17185 | } |
| 17186 | |
| 17187 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
| 17188 | .destroy = intel_user_framebuffer_destroy, |
| 17189 | .create_handle = intel_user_framebuffer_create_handle, |
| 17190 | .dirty = intel_user_framebuffer_dirty, |
| 17191 | }; |
| 17192 | |
| 17193 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
| 17194 | struct drm_i915_gem_object *obj, |
| 17195 | struct drm_mode_fb_cmd2 *mode_cmd) |
| 17196 | { |
| 17197 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(obj->base.dev); |
| 17198 | struct drm_framebuffer *fb = &intel_fb->base; |
| 17199 | u32 max_stride; |
| 17200 | unsigned int tiling, stride; |
| 17201 | int ret = -EINVAL22; |
| 17202 | int i; |
| 17203 | |
| 17204 | intel_fb->frontbuffer = intel_frontbuffer_get(obj); |
| 17205 | if (!intel_fb->frontbuffer) |
| 17206 | return -ENOMEM12; |
| 17207 | |
| 17208 | i915_gem_object_lock(obj, NULL((void *)0)); |
| 17209 | tiling = i915_gem_object_get_tiling(obj); |
| 17210 | stride = i915_gem_object_get_stride(obj); |
| 17211 | i915_gem_object_unlock(obj); |
| 17212 | |
| 17213 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS(1<<1)) { |
| 17214 | /* |
| 17215 | * If there's a fence, enforce that |
| 17216 | * the fb modifier and tiling mode match. |
| 17217 | */ |
| 17218 | if (tiling != I915_TILING_NONE0 && |
| 17219 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
| 17220 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "tiling_mode doesn't match fb modifier\n" ) |
| 17221 | "tiling_mode doesn't match fb modifier\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "tiling_mode doesn't match fb modifier\n" ); |
| 17222 | goto err; |
| 17223 | } |
| 17224 | } else { |
| 17225 | if (tiling == I915_TILING_X1) { |
| 17226 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED((((__u64)0x01) << 56) | ((1) & 0x00ffffffffffffffULL )); |
| 17227 | } else if (tiling == I915_TILING_Y2) { |
| 17228 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No Y tiling for legacy addfb\n" ) |
| 17229 | "No Y tiling for legacy addfb\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "No Y tiling for legacy addfb\n" ); |
| 17230 | goto err; |
| 17231 | } |
| 17232 | } |
| 17233 | |
| 17234 | if (!drm_any_plane_has_format(&dev_priv->drm, |
| 17235 | mode_cmd->pixel_format, |
| 17236 | mode_cmd->modifier[0])) { |
| 17237 | struct drm_format_name_buf format_name; |
| 17238 | |
| 17239 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unsupported pixel format %s / modifier 0x%llx\n" , drm_get_format_name(mode_cmd->pixel_format, &format_name ), mode_cmd->modifier[0]) |
| 17240 | "unsupported pixel format %s / modifier 0x%llx\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unsupported pixel format %s / modifier 0x%llx\n" , drm_get_format_name(mode_cmd->pixel_format, &format_name ), mode_cmd->modifier[0]) |
| 17241 | drm_get_format_name(mode_cmd->pixel_format,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unsupported pixel format %s / modifier 0x%llx\n" , drm_get_format_name(mode_cmd->pixel_format, &format_name ), mode_cmd->modifier[0]) |
| 17242 | &format_name),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unsupported pixel format %s / modifier 0x%llx\n" , drm_get_format_name(mode_cmd->pixel_format, &format_name ), mode_cmd->modifier[0]) |
| 17243 | mode_cmd->modifier[0])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "unsupported pixel format %s / modifier 0x%llx\n" , drm_get_format_name(mode_cmd->pixel_format, &format_name ), mode_cmd->modifier[0]); |
| 17244 | goto err; |
| 17245 | } |
| 17246 | |
| 17247 | /* |
| 17248 | * gen2/3 display engine uses the fence if present, |
| 17249 | * so the tiling mode must match the fb modifier exactly. |
| 17250 | */ |
| 17251 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 4 && |
| 17252 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { |
| 17253 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "tiling_mode must match fb modifier exactly on gen2/3\n" ) |
| 17254 | "tiling_mode must match fb modifier exactly on gen2/3\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "tiling_mode must match fb modifier exactly on gen2/3\n" ); |
| 17255 | goto err; |
| 17256 | } |
| 17257 | |
| 17258 | max_stride = intel_fb_max_stride(dev_priv, mode_cmd->pixel_format, |
| 17259 | mode_cmd->modifier[0]); |
| 17260 | if (mode_cmd->pitches[0] > max_stride) { |
| 17261 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 17262 | "%s pitch (%u) must be at most %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 17263 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 17264 | "tiled" : "linear",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride) |
| 17265 | mode_cmd->pitches[0], max_stride)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "%s pitch (%u) must be at most %d\n" , mode_cmd->modifier[0] != ((((__u64)0) << 56) | ((0 ) & 0x00ffffffffffffffULL)) ? "tiled" : "linear", mode_cmd ->pitches[0], max_stride); |
| 17266 | goto err; |
| 17267 | } |
| 17268 | |
| 17269 | /* |
| 17270 | * If there's a fence, enforce that |
| 17271 | * the fb pitch and fence stride match. |
| 17272 | */ |
| 17273 | if (tiling != I915_TILING_NONE0 && mode_cmd->pitches[0] != stride) { |
| 17274 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pitch (%d) must match tiling stride (%d)\n" , mode_cmd->pitches[0], stride) |
| 17275 | "pitch (%d) must match tiling stride (%d)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pitch (%d) must match tiling stride (%d)\n" , mode_cmd->pitches[0], stride) |
| 17276 | mode_cmd->pitches[0], stride)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "pitch (%d) must match tiling stride (%d)\n" , mode_cmd->pitches[0], stride); |
| 17277 | goto err; |
| 17278 | } |
| 17279 | |
| 17280 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
| 17281 | if (mode_cmd->offsets[0] != 0) { |
| 17282 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "plane 0 offset (0x%08x) must be 0\n" , mode_cmd->offsets[0]) |
| 17283 | "plane 0 offset (0x%08x) must be 0\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "plane 0 offset (0x%08x) must be 0\n" , mode_cmd->offsets[0]) |
| 17284 | mode_cmd->offsets[0])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "plane 0 offset (0x%08x) must be 0\n" , mode_cmd->offsets[0]); |
| 17285 | goto err; |
| 17286 | } |
| 17287 | |
| 17288 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
| 17289 | |
| 17290 | for (i = 0; i < fb->format->num_planes; i++) { |
| 17291 | u32 stride_alignment; |
| 17292 | |
| 17293 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { |
| 17294 | drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad plane %d handle\n" , i) |
| 17295 | i)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "bad plane %d handle\n" , i); |
| 17296 | goto err; |
| 17297 | } |
| 17298 | |
| 17299 | stride_alignment = intel_fb_stride_alignment(fb, i); |
| 17300 | if (fb->pitches[i] & (stride_alignment - 1)) { |
| 17301 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "plane %d pitch (%d) must be at least %u byte aligned\n" , i, fb->pitches[i], stride_alignment) |
| 17302 | "plane %d pitch (%d) must be at least %u byte aligned\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "plane %d pitch (%d) must be at least %u byte aligned\n" , i, fb->pitches[i], stride_alignment) |
| 17303 | i, fb->pitches[i], stride_alignment)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "plane %d pitch (%d) must be at least %u byte aligned\n" , i, fb->pitches[i], stride_alignment); |
| 17304 | goto err; |
| 17305 | } |
| 17306 | |
| 17307 | if (is_gen12_ccs_plane(fb, i)) { |
| 17308 | int ccs_aux_stride = gen12_ccs_aux_stride(fb, i); |
| 17309 | |
| 17310 | if (fb->pitches[i] != ccs_aux_stride) { |
| 17311 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride) |
| 17312 | "ccs aux plane %d pitch (%d) must be %d\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride) |
| 17313 | i,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride) |
| 17314 | fb->pitches[i], ccs_aux_stride)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "ccs aux plane %d pitch (%d) must be %d\n" , i, fb->pitches[i], ccs_aux_stride); |
| 17315 | goto err; |
| 17316 | } |
| 17317 | } |
| 17318 | |
| 17319 | fb->obj[i] = &obj->base; |
| 17320 | } |
| 17321 | |
| 17322 | ret = intel_fill_fb_info(dev_priv, fb); |
| 17323 | if (ret) |
| 17324 | goto err; |
| 17325 | |
| 17326 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
| 17327 | if (ret) { |
| 17328 | drm_err(&dev_priv->drm, "framebuffer init failed %d\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "framebuffer init failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 17329 | goto err; |
| 17330 | } |
| 17331 | |
| 17332 | return 0; |
| 17333 | |
| 17334 | err: |
| 17335 | intel_frontbuffer_put(intel_fb->frontbuffer); |
| 17336 | return ret; |
| 17337 | } |
| 17338 | |
| 17339 | static struct drm_framebuffer * |
| 17340 | intel_user_framebuffer_create(struct drm_device *dev, |
| 17341 | struct drm_file *filp, |
| 17342 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
| 17343 | { |
| 17344 | struct drm_framebuffer *fb; |
| 17345 | struct drm_i915_gem_object *obj; |
| 17346 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
| 17347 | |
| 17348 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
| 17349 | if (!obj) |
| 17350 | return ERR_PTR(-ENOENT2); |
| 17351 | |
| 17352 | fb = intel_framebuffer_create(obj, &mode_cmd); |
| 17353 | i915_gem_object_put(obj); |
| 17354 | |
| 17355 | return fb; |
| 17356 | } |
| 17357 | |
| 17358 | static enum drm_mode_status |
| 17359 | intel_mode_valid(struct drm_device *dev, |
| 17360 | const struct drm_display_mode *mode) |
| 17361 | { |
| 17362 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 17363 | int hdisplay_max, htotal_max; |
| 17364 | int vdisplay_max, vtotal_max; |
| 17365 | |
| 17366 | /* |
| 17367 | * Can't reject DBLSCAN here because Xorg ddxen can add piles |
| 17368 | * of DBLSCAN modes to the output's mode list when they detect |
| 17369 | * the scaling mode property on the connector. And they don't |
| 17370 | * ask the kernel to validate those modes in any way until |
| 17371 | * modeset time at which point the client gets a protocol error. |
| 17372 | * So in order to not upset those clients we silently ignore the |
| 17373 | * DBLSCAN flag on such connectors. For other connectors we will |
| 17374 | * reject modes with the DBLSCAN flag in encoder->compute_config(). |
| 17375 | * And we always reject DBLSCAN modes in connector->mode_valid() |
| 17376 | * as we never want such modes on the connector's mode list. |
| 17377 | */ |
| 17378 | |
| 17379 | if (mode->vscan > 1) |
| 17380 | return MODE_NO_VSCAN; |
| 17381 | |
| 17382 | if (mode->flags & DRM_MODE_FLAG_HSKEW(1<<9)) |
| 17383 | return MODE_H_ILLEGAL; |
| 17384 | |
| 17385 | if (mode->flags & (DRM_MODE_FLAG_CSYNC(1<<6) | |
| 17386 | DRM_MODE_FLAG_NCSYNC(1<<8) | |
| 17387 | DRM_MODE_FLAG_PCSYNC(1<<7))) |
| 17388 | return MODE_HSYNC; |
| 17389 | |
| 17390 | if (mode->flags & (DRM_MODE_FLAG_BCAST(1<<10) | |
| 17391 | DRM_MODE_FLAG_PIXMUX(1<<11) | |
| 17392 | DRM_MODE_FLAG_CLKDIV2(1<<13))) |
| 17393 | return MODE_BAD; |
| 17394 | |
| 17395 | /* Transcoder timing limits */ |
| 17396 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) { |
| 17397 | hdisplay_max = 16384; |
| 17398 | vdisplay_max = 8192; |
| 17399 | htotal_max = 16384; |
| 17400 | vtotal_max = 8192; |
| 17401 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || |
| 17402 | IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) { |
| 17403 | hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ |
| 17404 | vdisplay_max = 4096; |
| 17405 | htotal_max = 8192; |
| 17406 | vtotal_max = 8192; |
| 17407 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 3) { |
| 17408 | hdisplay_max = 4096; |
| 17409 | vdisplay_max = 4096; |
| 17410 | htotal_max = 8192; |
| 17411 | vtotal_max = 8192; |
| 17412 | } else { |
| 17413 | hdisplay_max = 2048; |
| 17414 | vdisplay_max = 2048; |
| 17415 | htotal_max = 4096; |
| 17416 | vtotal_max = 4096; |
| 17417 | } |
| 17418 | |
| 17419 | if (mode->hdisplay > hdisplay_max || |
| 17420 | mode->hsync_start > htotal_max || |
| 17421 | mode->hsync_end > htotal_max || |
| 17422 | mode->htotal > htotal_max) |
| 17423 | return MODE_H_ILLEGAL; |
| 17424 | |
| 17425 | if (mode->vdisplay > vdisplay_max || |
| 17426 | mode->vsync_start > vtotal_max || |
| 17427 | mode->vsync_end > vtotal_max || |
| 17428 | mode->vtotal > vtotal_max) |
| 17429 | return MODE_V_ILLEGAL; |
| 17430 | |
| 17431 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) { |
| 17432 | if (mode->hdisplay < 64 || |
| 17433 | mode->htotal - mode->hdisplay < 32) |
| 17434 | return MODE_H_ILLEGAL; |
| 17435 | |
| 17436 | if (mode->vtotal - mode->vdisplay < 5) |
| 17437 | return MODE_V_ILLEGAL; |
| 17438 | } else { |
| 17439 | if (mode->htotal - mode->hdisplay < 32) |
| 17440 | return MODE_H_ILLEGAL; |
| 17441 | |
| 17442 | if (mode->vtotal - mode->vdisplay < 3) |
| 17443 | return MODE_V_ILLEGAL; |
| 17444 | } |
| 17445 | |
| 17446 | return MODE_OK; |
| 17447 | } |
| 17448 | |
| 17449 | enum drm_mode_status |
| 17450 | intel_mode_valid_max_plane_size(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 17451 | const struct drm_display_mode *mode) |
| 17452 | { |
| 17453 | int plane_width_max, plane_height_max; |
| 17454 | |
| 17455 | /* |
| 17456 | * intel_mode_valid() should be |
| 17457 | * sufficient on older platforms. |
| 17458 | */ |
| 17459 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 9) |
| 17460 | return MODE_OK; |
| 17461 | |
| 17462 | /* |
| 17463 | * Most people will probably want a fullscreen |
| 17464 | * plane so let's not advertize modes that are |
| 17465 | * too big for that. |
| 17466 | */ |
| 17467 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) { |
| 17468 | plane_width_max = 5120; |
| 17469 | plane_height_max = 4320; |
| 17470 | } else { |
| 17471 | plane_width_max = 5120; |
| 17472 | plane_height_max = 4096; |
| 17473 | } |
| 17474 | |
| 17475 | if (mode->hdisplay > plane_width_max) |
| 17476 | return MODE_H_ILLEGAL; |
| 17477 | |
| 17478 | if (mode->vdisplay > plane_height_max) |
| 17479 | return MODE_V_ILLEGAL; |
| 17480 | |
| 17481 | return MODE_OK; |
| 17482 | } |
| 17483 | |
| 17484 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
| 17485 | .fb_create = intel_user_framebuffer_create, |
| 17486 | .get_format_info = intel_get_format_info, |
| 17487 | .output_poll_changed = intel_fbdev_output_poll_changed, |
| 17488 | .mode_valid = intel_mode_valid, |
| 17489 | .atomic_check = intel_atomic_check, |
| 17490 | .atomic_commit = intel_atomic_commit, |
| 17491 | .atomic_state_alloc = intel_atomic_state_alloc, |
| 17492 | .atomic_state_clear = intel_atomic_state_clear, |
| 17493 | .atomic_state_free = intel_atomic_state_free, |
| 17494 | }; |
| 17495 | |
| 17496 | /** |
| 17497 | * intel_init_display_hooks - initialize the display modesetting hooks |
| 17498 | * @dev_priv: device private |
| 17499 | */ |
| 17500 | void intel_init_display_hooks(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 17501 | { |
| 17502 | intel_init_cdclk_hooks(dev_priv); |
| 17503 | |
| 17504 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) { |
| 17505 | dev_priv->display.get_pipe_config = hsw_get_pipe_config; |
| 17506 | dev_priv->display.get_initial_plane_config = |
| 17507 | skl_get_initial_plane_config; |
| 17508 | dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; |
| 17509 | dev_priv->display.crtc_enable = hsw_crtc_enable; |
| 17510 | dev_priv->display.crtc_disable = hsw_crtc_disable; |
| 17511 | } else if (HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) { |
| 17512 | dev_priv->display.get_pipe_config = hsw_get_pipe_config; |
| 17513 | dev_priv->display.get_initial_plane_config = |
| 17514 | i9xx_get_initial_plane_config; |
| 17515 | dev_priv->display.crtc_compute_clock = |
| 17516 | hsw_crtc_compute_clock; |
| 17517 | dev_priv->display.crtc_enable = hsw_crtc_enable; |
| 17518 | dev_priv->display.crtc_disable = hsw_crtc_disable; |
| 17519 | } else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 17520 | dev_priv->display.get_pipe_config = ilk_get_pipe_config; |
| 17521 | dev_priv->display.get_initial_plane_config = |
| 17522 | i9xx_get_initial_plane_config; |
| 17523 | dev_priv->display.crtc_compute_clock = |
| 17524 | ilk_crtc_compute_clock; |
| 17525 | dev_priv->display.crtc_enable = ilk_crtc_enable; |
| 17526 | dev_priv->display.crtc_disable = ilk_crtc_disable; |
| 17527 | } else if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 17528 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 17529 | dev_priv->display.get_initial_plane_config = |
| 17530 | i9xx_get_initial_plane_config; |
| 17531 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
| 17532 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 17533 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 17534 | } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)) { |
| 17535 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 17536 | dev_priv->display.get_initial_plane_config = |
| 17537 | i9xx_get_initial_plane_config; |
| 17538 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; |
| 17539 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
| 17540 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 17541 | } else if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
| 17542 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 17543 | dev_priv->display.get_initial_plane_config = |
| 17544 | i9xx_get_initial_plane_config; |
| 17545 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; |
| 17546 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 17547 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 17548 | } else if (IS_PINEVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_PINEVIEW)) { |
| 17549 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 17550 | dev_priv->display.get_initial_plane_config = |
| 17551 | i9xx_get_initial_plane_config; |
| 17552 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; |
| 17553 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 17554 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 17555 | } else if (!IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2))) { |
| 17556 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 17557 | dev_priv->display.get_initial_plane_config = |
| 17558 | i9xx_get_initial_plane_config; |
| 17559 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
| 17560 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 17561 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 17562 | } else { |
| 17563 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
| 17564 | dev_priv->display.get_initial_plane_config = |
| 17565 | i9xx_get_initial_plane_config; |
| 17566 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; |
| 17567 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
| 17568 | dev_priv->display.crtc_disable = i9xx_crtc_disable; |
| 17569 | } |
| 17570 | |
| 17571 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) { |
| 17572 | dev_priv->display.fdi_link_train = ilk_fdi_link_train; |
| 17573 | } else if (IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6))) { |
| 17574 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
| 17575 | } else if (IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) { |
| 17576 | /* FIXME: detect B0+ stepping and use auto training */ |
| 17577 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; |
| 17578 | } |
| 17579 | |
| 17580 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 17581 | dev_priv->display.commit_modeset_enables = skl_commit_modeset_enables; |
| 17582 | else |
| 17583 | dev_priv->display.commit_modeset_enables = intel_commit_modeset_enables; |
| 17584 | |
| 17585 | } |
| 17586 | |
| 17587 | void intel_modeset_init_hw(struct drm_i915_privateinteldrm_softc *i915) |
| 17588 | { |
| 17589 | struct intel_cdclk_state *cdclk_state = |
| 17590 | to_intel_cdclk_state(i915->cdclk.obj.state)({ const __typeof( ((struct intel_cdclk_state *)0)->base ) *__mptr = ((i915->cdclk.obj.state)); (struct intel_cdclk_state *)( (char *)__mptr - __builtin_offsetof(struct intel_cdclk_state , base) );}); |
| 17591 | struct intel_dbuf_state *dbuf_state = |
| 17592 | to_intel_dbuf_state(i915->dbuf.obj.state)({ const __typeof( ((struct intel_dbuf_state *)0)->base ) * __mptr = ((i915->dbuf.obj.state)); (struct intel_dbuf_state *)( (char *)__mptr - __builtin_offsetof(struct intel_dbuf_state , base) );}); |
| 17593 | |
| 17594 | intel_update_cdclk(i915); |
| 17595 | intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK"); |
| 17596 | cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw; |
| 17597 | |
| 17598 | dbuf_state->enabled_slices = i915->dbuf.enabled_slices; |
| 17599 | } |
| 17600 | |
| 17601 | static int sanitize_watermarks_add_affected(struct drm_atomic_state *state) |
| 17602 | { |
| 17603 | struct drm_plane *plane; |
| 17604 | struct intel_crtc *crtc; |
| 17605 | |
| 17606 | for_each_intel_crtc(state->dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(state->dev)->mode_config.crtc_list )->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(state->dev)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) *__mptr = ( crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), base.head) );})) { |
| 17607 | struct intel_crtc_state *crtc_state; |
| 17608 | |
| 17609 | crtc_state = intel_atomic_get_crtc_state(state, crtc); |
| 17610 | if (IS_ERR(crtc_state)) |
| 17611 | return PTR_ERR(crtc_state); |
| 17612 | |
| 17613 | if (crtc_state->hw.active) { |
| 17614 | /* |
| 17615 | * Preserve the inherited flag to avoid |
| 17616 | * taking the full modeset path. |
| 17617 | */ |
| 17618 | crtc_state->inherited = true1; |
| 17619 | } |
| 17620 | } |
| 17621 | |
| 17622 | drm_for_each_plane(plane, state->dev)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->head ) *__mptr = ((&(state->dev)->mode_config.plane_list )->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof (__typeof(*plane), head) );}); &plane->head != (&( state->dev)->mode_config.plane_list); plane = ({ const __typeof ( ((__typeof(*plane) *)0)->head ) *__mptr = (plane->head .next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof (__typeof(*plane), head) );})) { |
| 17623 | struct drm_plane_state *plane_state; |
| 17624 | |
| 17625 | plane_state = drm_atomic_get_plane_state(state, plane); |
| 17626 | if (IS_ERR(plane_state)) |
| 17627 | return PTR_ERR(plane_state); |
| 17628 | } |
| 17629 | |
| 17630 | return 0; |
| 17631 | } |
| 17632 | |
| 17633 | /* |
| 17634 | * Calculate what we think the watermarks should be for the state we've read |
| 17635 | * out of the hardware and then immediately program those watermarks so that |
| 17636 | * we ensure the hardware settings match our internal state. |
| 17637 | * |
| 17638 | * We can calculate what we think WM's should be by creating a duplicate of the |
| 17639 | * current state (which was constructed during hardware readout) and running it |
| 17640 | * through the atomic check code to calculate new watermark values in the |
| 17641 | * state object. |
| 17642 | */ |
| 17643 | static void sanitize_watermarks(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 17644 | { |
| 17645 | struct drm_atomic_state *state; |
| 17646 | struct intel_atomic_state *intel_state; |
| 17647 | struct intel_crtc *crtc; |
| 17648 | struct intel_crtc_state *crtc_state; |
| 17649 | struct drm_modeset_acquire_ctx ctx; |
| 17650 | int ret; |
| 17651 | int i; |
| 17652 | |
| 17653 | /* Only supported on platforms that use atomic watermark design */ |
| 17654 | if (!dev_priv->display.optimize_watermarks) |
| 17655 | return; |
| 17656 | |
| 17657 | state = drm_atomic_state_alloc(&dev_priv->drm); |
| 17658 | if (drm_WARN_ON(&dev_priv->drm, !state)({ int __ret = !!((!state)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "!state" ")"); __builtin_expect(!!(__ret), 0); })) |
| 17659 | return; |
| 17660 | |
| 17661 | intel_state = to_intel_atomic_state(state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state, base) );}); |
| 17662 | |
| 17663 | drm_modeset_acquire_init(&ctx, 0); |
| 17664 | |
| 17665 | retry: |
| 17666 | state->acquire_ctx = &ctx; |
| 17667 | |
| 17668 | /* |
| 17669 | * Hardware readout is the only time we don't want to calculate |
| 17670 | * intermediate watermarks (since we don't trust the current |
| 17671 | * watermarks). |
| 17672 | */ |
| 17673 | if (!HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) |
| 17674 | intel_state->skip_intermediate_wm = true1; |
| 17675 | |
| 17676 | ret = sanitize_watermarks_add_affected(state); |
| 17677 | if (ret) |
| 17678 | goto fail; |
| 17679 | |
| 17680 | ret = intel_atomic_check(&dev_priv->drm, state); |
| 17681 | if (ret) |
| 17682 | goto fail; |
| 17683 | |
| 17684 | /* Write calculated watermark values back */ |
| 17685 | for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i)for ((i) = 0; (i) < (intel_state)->base.dev->mode_config .num_crtc && ((crtc) = ({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = ((intel_state)->base.crtcs[i].ptr ); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof (struct intel_crtc, base) );}), (crtc_state) = ({ const __typeof ( ((struct intel_crtc_state *)0)->uapi ) *__mptr = ((intel_state )->base.crtcs[i].new_state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}), 1); (i)++) if (!(crtc)) {} else { |
| 17686 | crtc_state->wm.need_postvbl_update = true1; |
| 17687 | dev_priv->display.optimize_watermarks(intel_state, crtc); |
| 17688 | |
| 17689 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );})->wm = crtc_state->wm; |
| 17690 | } |
| 17691 | |
| 17692 | fail: |
| 17693 | if (ret == -EDEADLK11) { |
| 17694 | drm_atomic_state_clear(state); |
| 17695 | drm_modeset_backoff(&ctx); |
| 17696 | goto retry; |
| 17697 | } |
| 17698 | |
| 17699 | /* |
| 17700 | * If we fail here, it means that the hardware appears to be |
| 17701 | * programmed in a way that shouldn't be possible, given our |
| 17702 | * understanding of watermark requirements. This might mean a |
| 17703 | * mistake in the hardware readout code or a mistake in the |
| 17704 | * watermark calculations for a given platform. Raise a WARN |
| 17705 | * so that this is noticeable. |
| 17706 | * |
| 17707 | * If this actually happens, we'll have to just leave the |
| 17708 | * BIOS-programmed watermarks untouched and hope for the best. |
| 17709 | */ |
| 17710 | drm_WARN(&dev_priv->drm, ret,({ int __ret = !!(ret); if (__ret) printf("%s %s: " "Could not determine valid watermarks for inherited state\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }) |
| 17711 | "Could not determine valid watermarks for inherited state\n")({ int __ret = !!(ret); if (__ret) printf("%s %s: " "Could not determine valid watermarks for inherited state\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }); |
| 17712 | |
| 17713 | drm_atomic_state_put(state); |
| 17714 | |
| 17715 | drm_modeset_drop_locks(&ctx); |
| 17716 | drm_modeset_acquire_fini(&ctx); |
| 17717 | } |
| 17718 | |
| 17719 | static void intel_update_fdi_pll_freq(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 17720 | { |
| 17721 | if (IS_GEN(dev_priv, 5)(0 + (&(dev_priv)->__info)->gen == (5))) { |
| 17722 | u32 fdi_pll_clk = |
| 17723 | intel_de_read(dev_priv, FDI_PLL_BIOS_0((const i915_reg_t){ .reg = (0x46000) })) & FDI_PLL_FB_CLOCK_MASK0xff; |
| 17724 | |
| 17725 | dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; |
| 17726 | } else if (IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6)) || IS_IVYBRIDGE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)) { |
| 17727 | dev_priv->fdi_pll_freq = 270000; |
| 17728 | } else { |
| 17729 | return; |
| 17730 | } |
| 17731 | |
| 17732 | drm_dbg(&dev_priv->drm, "FDI PLL freq=%d\n", dev_priv->fdi_pll_freq)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "FDI PLL freq=%d\n" , dev_priv->fdi_pll_freq); |
| 17733 | } |
| 17734 | |
| 17735 | static int intel_initial_commit(struct drm_device *dev) |
| 17736 | { |
| 17737 | struct drm_atomic_state *state = NULL((void *)0); |
| 17738 | struct drm_modeset_acquire_ctx ctx; |
| 17739 | struct intel_crtc *crtc; |
| 17740 | int ret = 0; |
| 17741 | |
| 17742 | state = drm_atomic_state_alloc(dev); |
| 17743 | if (!state) |
| 17744 | return -ENOMEM12; |
| 17745 | |
| 17746 | drm_modeset_acquire_init(&ctx, 0); |
| 17747 | |
| 17748 | retry: |
| 17749 | state->acquire_ctx = &ctx; |
| 17750 | |
| 17751 | for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof ( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc-> base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );})) { |
| 17752 | struct intel_crtc_state *crtc_state = |
| 17753 | intel_atomic_get_crtc_state(state, crtc); |
| 17754 | |
| 17755 | if (IS_ERR(crtc_state)) { |
| 17756 | ret = PTR_ERR(crtc_state); |
| 17757 | goto out; |
| 17758 | } |
| 17759 | |
| 17760 | if (crtc_state->hw.active) { |
| 17761 | /* |
| 17762 | * We've not yet detected sink capabilities |
| 17763 | * (audio,infoframes,etc.) and thus we don't want to |
| 17764 | * force a full state recomputation yet. We want that to |
| 17765 | * happen only for the first real commit from userspace. |
| 17766 | * So preserve the inherited flag for the time being. |
| 17767 | */ |
| 17768 | crtc_state->inherited = true1; |
| 17769 | |
| 17770 | ret = drm_atomic_add_affected_planes(state, &crtc->base); |
| 17771 | if (ret) |
| 17772 | goto out; |
| 17773 | |
| 17774 | /* |
| 17775 | * FIXME hack to force a LUT update to avoid the |
| 17776 | * plane update forcing the pipe gamma on without |
| 17777 | * having a proper LUT loaded. Remove once we |
| 17778 | * have readout for pipe gamma enable. |
| 17779 | */ |
| 17780 | crtc_state->uapi.color_mgmt_changed = true1; |
| 17781 | |
| 17782 | /* |
| 17783 | * FIXME hack to force full modeset when DSC is being |
| 17784 | * used. |
| 17785 | * |
| 17786 | * As long as we do not have full state readout and |
| 17787 | * config comparison of crtc_state->dsc, we have no way |
| 17788 | * to ensure reliable fastset. Remove once we have |
| 17789 | * readout for DSC. |
| 17790 | */ |
| 17791 | if (crtc_state->dsc.compression_enable) { |
| 17792 | ret = drm_atomic_add_affected_connectors(state, |
| 17793 | &crtc->base); |
| 17794 | if (ret) |
| 17795 | goto out; |
| 17796 | crtc_state->uapi.mode_changed = true1; |
| 17797 | drm_dbg_kms(dev, "Force full modeset for DSC\n")drm_dev_dbg((dev)->dev, DRM_UT_KMS, "Force full modeset for DSC\n" ); |
| 17798 | } |
| 17799 | } |
| 17800 | } |
| 17801 | |
| 17802 | ret = drm_atomic_commit(state); |
| 17803 | |
| 17804 | out: |
| 17805 | if (ret == -EDEADLK11) { |
| 17806 | drm_atomic_state_clear(state); |
| 17807 | drm_modeset_backoff(&ctx); |
| 17808 | goto retry; |
| 17809 | } |
| 17810 | |
| 17811 | drm_atomic_state_put(state); |
| 17812 | |
| 17813 | drm_modeset_drop_locks(&ctx); |
| 17814 | drm_modeset_acquire_fini(&ctx); |
| 17815 | |
| 17816 | return ret; |
| 17817 | } |
| 17818 | |
| 17819 | static void intel_mode_config_init(struct drm_i915_privateinteldrm_softc *i915) |
| 17820 | { |
| 17821 | struct drm_mode_config *mode_config = &i915->drm.mode_config; |
| 17822 | |
| 17823 | drm_mode_config_init(&i915->drm); |
| 17824 | INIT_LIST_HEAD(&i915->global_obj_list); |
| 17825 | |
| 17826 | mode_config->min_width = 0; |
| 17827 | mode_config->min_height = 0; |
| 17828 | |
| 17829 | mode_config->preferred_depth = 24; |
| 17830 | mode_config->prefer_shadow = 1; |
| 17831 | |
| 17832 | mode_config->allow_fb_modifiers = true1; |
| 17833 | |
| 17834 | mode_config->funcs = &intel_mode_funcs; |
| 17835 | |
| 17836 | /* |
| 17837 | * Maximum framebuffer dimensions, chosen to match |
| 17838 | * the maximum render engine surface size on gen4+. |
| 17839 | */ |
| 17840 | if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 7) { |
| 17841 | mode_config->max_width = 16384; |
| 17842 | mode_config->max_height = 16384; |
| 17843 | } else if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 4) { |
| 17844 | mode_config->max_width = 8192; |
| 17845 | mode_config->max_height = 8192; |
| 17846 | } else if (IS_GEN(i915, 3)(0 + (&(i915)->__info)->gen == (3))) { |
| 17847 | mode_config->max_width = 4096; |
| 17848 | mode_config->max_height = 4096; |
| 17849 | } else { |
| 17850 | mode_config->max_width = 2048; |
| 17851 | mode_config->max_height = 2048; |
| 17852 | } |
| 17853 | |
| 17854 | if (IS_I845G(i915)IS_PLATFORM(i915, INTEL_I845G) || IS_I865G(i915)IS_PLATFORM(i915, INTEL_I865G)) { |
| 17855 | mode_config->cursor_width = IS_I845G(i915)IS_PLATFORM(i915, INTEL_I845G) ? 64 : 512; |
| 17856 | mode_config->cursor_height = 1023; |
| 17857 | } else if (IS_I830(i915)IS_PLATFORM(i915, INTEL_I830) || IS_I85X(i915)IS_PLATFORM(i915, INTEL_I85X) || |
| 17858 | IS_I915G(i915)IS_PLATFORM(i915, INTEL_I915G) || IS_I915GM(i915)IS_PLATFORM(i915, INTEL_I915GM)) { |
| 17859 | mode_config->cursor_width = 64; |
| 17860 | mode_config->cursor_height = 64; |
| 17861 | } else { |
| 17862 | mode_config->cursor_width = 256; |
| 17863 | mode_config->cursor_height = 256; |
| 17864 | } |
| 17865 | } |
| 17866 | |
| 17867 | static void intel_mode_config_cleanup(struct drm_i915_privateinteldrm_softc *i915) |
| 17868 | { |
| 17869 | intel_atomic_global_obj_cleanup(i915); |
| 17870 | drm_mode_config_cleanup(&i915->drm); |
| 17871 | } |
| 17872 | |
| 17873 | static void plane_config_fini(struct intel_initial_plane_config *plane_config) |
| 17874 | { |
| 17875 | if (plane_config->fb) { |
| 17876 | struct drm_framebuffer *fb = &plane_config->fb->base; |
| 17877 | |
| 17878 | /* We may only have the stub and not a full framebuffer */ |
| 17879 | if (drm_framebuffer_read_refcount(fb)) |
| 17880 | drm_framebuffer_put(fb); |
| 17881 | else |
| 17882 | kfree(fb); |
| 17883 | } |
| 17884 | |
| 17885 | if (plane_config->vma) |
| 17886 | i915_vma_put(plane_config->vma); |
| 17887 | } |
| 17888 | |
| 17889 | /* part #1: call before irq install */ |
| 17890 | int intel_modeset_init_noirq(struct drm_i915_privateinteldrm_softc *i915) |
| 17891 | { |
| 17892 | int ret; |
| 17893 | |
| 17894 | if (i915_inject_probe_failure(i915)({ ((void)0); 0; })) |
| 17895 | return -ENODEV19; |
| 17896 | |
| 17897 | if (HAS_DISPLAY(i915)((&(i915)->__info)->pipe_mask != 0)) { |
| 17898 | ret = drm_vblank_init(&i915->drm, |
| 17899 | INTEL_NUM_PIPES(i915)(hweight8((&(i915)->__info)->pipe_mask))); |
| 17900 | if (ret) |
| 17901 | return ret; |
| 17902 | } |
| 17903 | |
| 17904 | intel_bios_init(i915); |
| 17905 | |
| 17906 | ret = intel_vga_register(i915); |
| 17907 | if (ret) |
| 17908 | goto cleanup_bios; |
| 17909 | |
| 17910 | /* FIXME: completely on the wrong abstraction layer */ |
| 17911 | intel_power_domains_init_hw(i915, false0); |
| 17912 | |
| 17913 | intel_csr_ucode_init(i915); |
| 17914 | |
| 17915 | i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0); |
| 17916 | i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI1 | |
| 17917 | WQ_UNBOUND4, WQ_UNBOUND_MAX_ACTIVE4); |
| 17918 | |
| 17919 | intel_mode_config_init(i915); |
| 17920 | |
| 17921 | ret = intel_cdclk_init(i915); |
| 17922 | if (ret) |
| 17923 | goto cleanup_vga_client_pw_domain_csr; |
| 17924 | |
| 17925 | ret = intel_dbuf_init(i915); |
| 17926 | if (ret) |
| 17927 | goto cleanup_vga_client_pw_domain_csr; |
| 17928 | |
| 17929 | ret = intel_bw_init(i915); |
| 17930 | if (ret) |
| 17931 | goto cleanup_vga_client_pw_domain_csr; |
| 17932 | |
| 17933 | init_llist_head(&i915->atomic_helper.free_list); |
| 17934 | INIT_WORK(&i915->atomic_helper.free_work, |
| 17935 | intel_atomic_helper_free_state_worker); |
| 17936 | |
| 17937 | intel_init_quirks(i915); |
| 17938 | |
| 17939 | intel_fbc_init(i915); |
| 17940 | |
| 17941 | return 0; |
| 17942 | |
| 17943 | cleanup_vga_client_pw_domain_csr: |
| 17944 | intel_csr_ucode_fini(i915); |
| 17945 | intel_power_domains_driver_remove(i915); |
| 17946 | intel_vga_unregister(i915); |
| 17947 | cleanup_bios: |
| 17948 | intel_bios_driver_remove(i915); |
| 17949 | |
| 17950 | return ret; |
| 17951 | } |
| 17952 | |
| 17953 | /* part #2: call after irq install, but before gem init */ |
| 17954 | int intel_modeset_init_nogem(struct drm_i915_privateinteldrm_softc *i915) |
| 17955 | { |
| 17956 | struct drm_device *dev = &i915->drm; |
| 17957 | enum pipe pipe; |
| 17958 | struct intel_crtc *crtc; |
| 17959 | int ret; |
| 17960 | |
| 17961 | intel_init_pm(i915); |
| 17962 | |
| 17963 | intel_panel_sanitize_ssc(i915); |
| 17964 | |
| 17965 | intel_gmbus_setup(i915); |
| 17966 | |
| 17967 | drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%d display pipe%s available.\n" , (hweight8((&(i915)->__info)->pipe_mask)), (hweight8 ((&(i915)->__info)->pipe_mask)) > 1 ? "s" : "") |
| 17968 | INTEL_NUM_PIPES(i915),drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%d display pipe%s available.\n" , (hweight8((&(i915)->__info)->pipe_mask)), (hweight8 ((&(i915)->__info)->pipe_mask)) > 1 ? "s" : "") |
| 17969 | INTEL_NUM_PIPES(i915) > 1 ? "s" : "")drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "%d display pipe%s available.\n" , (hweight8((&(i915)->__info)->pipe_mask)), (hweight8 ((&(i915)->__info)->pipe_mask)) > 1 ? "s" : ""); |
| 17970 | |
| 17971 | if (HAS_DISPLAY(i915)((&(i915)->__info)->pipe_mask != 0)) { |
| 17972 | for_each_pipe(i915, pipe)for ((pipe) = 0; (pipe) < I915_MAX_PIPES; (pipe)++) if (!( (&(i915)->__info)->pipe_mask & (1UL << (pipe )))) {} else { |
| 17973 | ret = intel_crtc_init(i915, pipe); |
| 17974 | if (ret) { |
| 17975 | intel_mode_config_cleanup(i915); |
| 17976 | return ret; |
| 17977 | } |
| 17978 | } |
| 17979 | } |
| 17980 | |
| 17981 | intel_plane_possible_crtcs_init(i915); |
| 17982 | intel_shared_dpll_init(dev); |
| 17983 | intel_update_fdi_pll_freq(i915); |
| 17984 | |
| 17985 | intel_update_czclk(i915); |
| 17986 | intel_modeset_init_hw(i915); |
| 17987 | |
| 17988 | intel_hdcp_component_init(i915); |
| 17989 | |
| 17990 | if (i915->max_cdclk_freq == 0) |
| 17991 | intel_update_max_cdclk(i915); |
| 17992 | |
| 17993 | /* |
| 17994 | * If the platform has HTI, we need to find out whether it has reserved |
| 17995 | * any display resources before we create our display outputs. |
| 17996 | */ |
| 17997 | if (INTEL_INFO(i915)(&(i915)->__info)->display.has_hti) |
| 17998 | i915->hti_state = intel_de_read(i915, HDPORT_STATE((const i915_reg_t){ .reg = (0x45050) })); |
| 17999 | |
| 18000 | /* Just disable it once at startup */ |
| 18001 | intel_vga_disable(i915); |
| 18002 | intel_setup_outputs(i915); |
| 18003 | |
| 18004 | drm_modeset_lock_all(dev); |
| 18005 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
| 18006 | drm_modeset_unlock_all(dev); |
| 18007 | |
| 18008 | for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof ( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc-> base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );})) { |
| 18009 | struct intel_initial_plane_config plane_config = {}; |
| 18010 | |
| 18011 | if (!crtc->active) |
| 18012 | continue; |
| 18013 | |
| 18014 | /* |
| 18015 | * Note that reserving the BIOS fb up front prevents us |
| 18016 | * from stuffing other stolen allocations like the ring |
| 18017 | * on top. This prevents some ugliness at boot time, and |
| 18018 | * can even allow for smooth boot transitions if the BIOS |
| 18019 | * fb is large enough for the active pipe configuration. |
| 18020 | */ |
| 18021 | i915->display.get_initial_plane_config(crtc, &plane_config); |
| 18022 | |
| 18023 | /* |
| 18024 | * If the fb is shared between multiple heads, we'll |
| 18025 | * just get the first one. |
| 18026 | */ |
| 18027 | intel_find_initial_plane_obj(crtc, &plane_config); |
| 18028 | |
| 18029 | plane_config_fini(&plane_config); |
| 18030 | } |
| 18031 | |
| 18032 | /* |
| 18033 | * Make sure hardware watermarks really match the state we read out. |
| 18034 | * Note that we need to do this after reconstructing the BIOS fb's |
| 18035 | * since the watermark calculation done here will use pstate->fb. |
| 18036 | */ |
| 18037 | if (!HAS_GMCH(i915)((&(i915)->__info)->display.has_gmch)) |
| 18038 | sanitize_watermarks(i915); |
| 18039 | |
| 18040 | return 0; |
| 18041 | } |
| 18042 | |
| 18043 | /* part #3: call after gem init */ |
| 18044 | int intel_modeset_init(struct drm_i915_privateinteldrm_softc *i915) |
| 18045 | { |
| 18046 | int ret; |
| 18047 | |
| 18048 | if (!HAS_DISPLAY(i915)((&(i915)->__info)->pipe_mask != 0)) |
| 18049 | return 0; |
| 18050 | |
| 18051 | /* |
| 18052 | * Force all active planes to recompute their states. So that on |
| 18053 | * mode_setcrtc after probe, all the intel_plane_state variables |
| 18054 | * are already calculated and there is no assert_plane warnings |
| 18055 | * during bootup. |
| 18056 | */ |
| 18057 | ret = intel_initial_commit(&i915->drm); |
| 18058 | if (ret) |
| 18059 | drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret)drm_dev_dbg((&i915->drm)->dev, DRM_UT_KMS, "Initial modeset failed, %d\n" , ret); |
| 18060 | |
| 18061 | intel_overlay_setup(i915); |
| 18062 | |
| 18063 | ret = intel_fbdev_init(&i915->drm); |
| 18064 | if (ret) |
| 18065 | return ret; |
| 18066 | |
| 18067 | /* Only enable hotplug handling once the fbdev is fully set up. */ |
| 18068 | intel_hpd_init(i915); |
| 18069 | |
| 18070 | intel_init_ipc(i915); |
| 18071 | |
| 18072 | intel_psr_set_force_mode_changed(i915->psr.dp); |
| 18073 | |
| 18074 | return 0; |
| 18075 | } |
| 18076 | |
| 18077 | void i830_enable_pipe(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 18078 | { |
| 18079 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 18080 | /* 640x480@60Hz, ~25175 kHz */ |
| 18081 | struct dpll clock = { |
| 18082 | .m1 = 18, |
| 18083 | .m2 = 7, |
| 18084 | .p1 = 13, |
| 18085 | .p2 = 4, |
| 18086 | .n = 2, |
| 18087 | }; |
| 18088 | u32 dpll, fp; |
| 18089 | int i; |
| 18090 | |
| 18091 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((i9xx_calc_dpll_params(48000, &clock) != 25154)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "i9xx_calc_dpll_params(48000, &clock) != 25154" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18092 | i9xx_calc_dpll_params(48000, &clock) != 25154)({ int __ret = !!((i9xx_calc_dpll_params(48000, &clock) != 25154)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "i9xx_calc_dpll_params(48000, &clock) != 25154" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18093 | |
| 18094 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling pipe %c due to force quirk (vco=%d dot=%d)\n" , ((pipe) + 'A'), clock.vco, clock.dot) |
| 18095 | "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling pipe %c due to force quirk (vco=%d dot=%d)\n" , ((pipe) + 'A'), clock.vco, clock.dot) |
| 18096 | pipe_name(pipe), clock.vco, clock.dot)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "enabling pipe %c due to force quirk (vco=%d dot=%d)\n" , ((pipe) + 'A'), clock.vco, clock.dot); |
| 18097 | |
| 18098 | fp = i9xx_dpll_compute_fp(&clock); |
| 18099 | dpll = DPLL_DVO_2X_MODE(1 << 30) | |
| 18100 | DPLL_VGA_MODE_DIS(1 << 28) | |
| 18101 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT16) | |
| 18102 | PLL_P2_DIVIDE_BY_4(1 << 23) | |
| 18103 | PLL_REF_INPUT_DREFCLK(0 << 13) | |
| 18104 | DPLL_VCO_ENABLE(1 << 31); |
| 18105 | |
| 18106 | intel_de_write(dev_priv, FP0(pipe)((const i915_reg_t){ .reg = (((0x6040) + (pipe) * ((0x6048) - (0x6040)))) }), fp); |
| 18107 | intel_de_write(dev_priv, FP1(pipe)((const i915_reg_t){ .reg = (((0x6044) + (pipe) * ((0x604c) - (0x6044)))) }), fp); |
| 18108 | |
| 18109 | intel_de_write(dev_priv, HTOTAL(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60000) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), (640 - 1) | ((800 - 1) << 16)); |
| 18110 | intel_de_write(dev_priv, HBLANK(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60004) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), (640 - 1) | ((800 - 1) << 16)); |
| 18111 | intel_de_write(dev_priv, HSYNC(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60008) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), (656 - 1) | ((752 - 1) << 16)); |
| 18112 | intel_de_write(dev_priv, VTOTAL(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x6000c) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), (480 - 1) | ((525 - 1) << 16)); |
| 18113 | intel_de_write(dev_priv, VBLANK(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60010) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), (480 - 1) | ((525 - 1) << 16)); |
| 18114 | intel_de_write(dev_priv, VSYNC(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x60014) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), (490 - 1) | ((492 - 1) << 16)); |
| 18115 | intel_de_write(dev_priv, PIPESRC(pipe)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(pipe)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x6001c) + ((&(dev_priv)->__info)-> display_mmio_offset))) }), ((640 - 1) << 16) | (480 - 1)); |
| 18116 | |
| 18117 | /* |
| 18118 | * Apparently we need to have VGA mode enabled prior to changing |
| 18119 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old |
| 18120 | * dividers, even though the register value does change. |
| 18121 | */ |
| 18122 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), dpll & ~DPLL_VGA_MODE_DIS(1 << 28)); |
| 18123 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), dpll); |
| 18124 | |
| 18125 | /* Wait for the clocks to stabilize. */ |
| 18126 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 18127 | udelay(150); |
| 18128 | |
| 18129 | /* The pixel multiplier can only be updated once the |
| 18130 | * DPLL is enabled and the clocks are stable. |
| 18131 | * |
| 18132 | * So write it again. |
| 18133 | */ |
| 18134 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), dpll); |
| 18135 | |
| 18136 | /* We do this three times for luck */ |
| 18137 | for (i = 0; i < 3 ; i++) { |
| 18138 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), dpll); |
| 18139 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 18140 | udelay(150); /* wait for warmup */ |
| 18141 | } |
| 18142 | |
| 18143 | intel_de_write(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) }), |
| 18144 | PIPECONF_ENABLE(1 << 31) | PIPECONF_PROGRESSIVE(0 << 21)); |
| 18145 | intel_de_posting_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 18146 | |
| 18147 | intel_wait_for_pipe_scanline_moving(crtc); |
| 18148 | } |
| 18149 | |
| 18150 | void i830_disable_pipe(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
| 18151 | { |
| 18152 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 18153 | |
| 18154 | drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling pipe %c due to force quirk\n" , ((pipe) + 'A')) |
| 18155 | pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "disabling pipe %c due to force quirk\n" , ((pipe) + 'A')); |
| 18156 | |
| 18157 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_A ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_A] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18158 | intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_A ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_A] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18159 | DISPLAY_PLANE_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_A ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_A] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18160 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_B ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_B] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18161 | intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_B ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_B] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18162 | DISPLAY_PLANE_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_B ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_B] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18163 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_C ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_C] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18164 | intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_C ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_C] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18165 | DISPLAY_PLANE_ENABLE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_C ] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + ( 0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & (1 << 31))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->pipe_offsets[PLANE_C] - (&(dev_priv)->__info)->pipe_offsets[PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & (1 << 31)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18166 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_A )] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & 0x27)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & 0x27" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18167 | intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_A )] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & 0x27)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_A)] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & 0x27" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18168 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_B )] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & 0x27)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_B)] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & 0x27" ")"); __builtin_expect(!!(__ret), 0); }) |
| 18169 | intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE)({ int __ret = !!((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_B )] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) })) & 0x27)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_de_read(dev_priv, ((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->cursor_offsets[(PIPE_B)] - (&(dev_priv)->__info)->cursor_offsets[PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset)) })) & 0x27" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18170 | |
| 18171 | intel_de_write(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) }), 0); |
| 18172 | intel_de_posting_read(dev_priv, PIPECONF(pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[pipe] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70008) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 18173 | |
| 18174 | intel_wait_for_pipe_scanline_stopped(crtc); |
| 18175 | |
| 18176 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), DPLL_VGA_MODE_DIS(1 << 28)); |
| 18177 | intel_de_posting_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
| 18178 | } |
| 18179 | |
| 18180 | static void |
| 18181 | intel_sanitize_plane_mapping(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 18182 | { |
| 18183 | struct intel_crtc *crtc; |
| 18184 | |
| 18185 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) |
| 18186 | return; |
| 18187 | |
| 18188 | for_each_intel_crtc(&dev_priv->drm, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(&dev_priv->drm)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) * __mptr = (crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), base.head) ); })) { |
| 18189 | struct intel_plane *plane = |
| 18190 | to_intel_plane(crtc->base.primary)({ const __typeof( ((struct intel_plane *)0)->base ) *__mptr = (crtc->base.primary); (struct intel_plane *)( (char *)__mptr - __builtin_offsetof(struct intel_plane, base) );}); |
| 18191 | struct intel_crtc *plane_crtc; |
| 18192 | enum pipe pipe; |
| 18193 | |
| 18194 | if (!plane->get_hw_state(plane, &pipe)) |
| 18195 | continue; |
| 18196 | |
| 18197 | if (pipe == crtc->pipe) |
| 18198 | continue; |
| 18199 | |
| 18200 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n" , plane->base.base.id, plane->base.name) |
| 18201 | "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n" , plane->base.base.id, plane->base.name) |
| 18202 | plane->base.base.id, plane->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n" , plane->base.base.id, plane->base.name); |
| 18203 | |
| 18204 | plane_crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 18205 | intel_plane_disable_noatomic(plane_crtc, plane); |
| 18206 | } |
| 18207 | } |
| 18208 | |
| 18209 | static bool_Bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
| 18210 | { |
| 18211 | struct drm_device *dev = crtc->base.dev; |
| 18212 | struct intel_encoder *encoder; |
| 18213 | |
| 18214 | for_each_encoder_on_crtc(dev, &crtc->base, encoder)for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *) 0)->base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*(encoder)) *)( (char *)__mptr - __builtin_offsetof (__typeof(*(encoder)), base.head) );}); &(encoder)->base .head != (&(dev)->mode_config.encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder)) *)0)->base.head ) *__mptr = ((encoder)->base.head.next); (__typeof(*(encoder )) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(encoder )), base.head) );})) if (!((encoder)->base.crtc == (&crtc ->base))) {} else |
| 18215 | return true1; |
| 18216 | |
| 18217 | return false0; |
| 18218 | } |
| 18219 | |
| 18220 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
| 18221 | { |
| 18222 | struct drm_device *dev = encoder->base.dev; |
| 18223 | struct intel_connector *connector; |
| 18224 | |
| 18225 | for_each_connector_on_encoder(dev, &encoder->base, connector)for ((connector) = ({ const __typeof( ((__typeof(*(connector) ) *)0)->base.head ) *__mptr = ((&(dev)->mode_config .connector_list)->next); (__typeof(*(connector)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(connector)), base.head ) );}); &(connector)->base.head != (&(dev)->mode_config .connector_list); (connector) = ({ const __typeof( ((__typeof (*(connector)) *)0)->base.head ) *__mptr = ((connector)-> base.head.next); (__typeof(*(connector)) *)( (char *)__mptr - __builtin_offsetof(__typeof(*(connector)), base.head) );})) if (!((connector)->base.encoder == (&encoder->base))) {} else |
| 18226 | return connector; |
| 18227 | |
| 18228 | return NULL((void *)0); |
| 18229 | } |
| 18230 | |
| 18231 | static bool_Bool has_pch_trancoder(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 18232 | enum pipe pch_transcoder) |
| 18233 | { |
| 18234 | return HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) || HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT) || |
| 18235 | (HAS_PCH_LPT_H(dev_priv)(((dev_priv)->pch_id) == 0x8c00 || ((dev_priv)->pch_id) == 0x8c80) && pch_transcoder == PIPE_A); |
| 18236 | } |
| 18237 | |
| 18238 | static void intel_sanitize_frame_start_delay(const struct intel_crtc_state *crtc_state) |
| 18239 | { |
| 18240 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 18241 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
| 18242 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
| 18243 | |
| 18244 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9 || |
| 18245 | IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) { |
| 18246 | i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder)((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP ] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4 , [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(cpu_transcoder )])) }); |
| 18247 | u32 val; |
| 18248 | |
| 18249 | if (transcoder_is_dsi(cpu_transcoder)) |
| 18250 | return; |
| 18251 | |
| 18252 | val = intel_de_read(dev_priv, reg); |
| 18253 | val &= ~HSW_FRAME_START_DELAY_MASK(3 << 27); |
| 18254 | val |= HSW_FRAME_START_DELAY(0)((0) << 27); |
| 18255 | intel_de_write(dev_priv, reg, val); |
| 18256 | } else { |
| 18257 | i915_reg_t reg = PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) }); |
| 18258 | u32 val; |
| 18259 | |
| 18260 | val = intel_de_read(dev_priv, reg); |
| 18261 | val &= ~PIPECONF_FRAME_START_DELAY_MASK(3 << 27); |
| 18262 | val |= PIPECONF_FRAME_START_DELAY(0)((0) << 27); |
| 18263 | intel_de_write(dev_priv, reg, val); |
| 18264 | } |
| 18265 | |
| 18266 | if (!crtc_state->has_pch_encoder) |
| 18267 | return; |
| 18268 | |
| 18269 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) { |
| 18270 | i915_reg_t reg = PCH_TRANSCONF(crtc->pipe)((const i915_reg_t){ .reg = (((0xf0008) + (crtc->pipe) * ( (0xf1008) - (0xf0008)))) }); |
| 18271 | u32 val; |
| 18272 | |
| 18273 | val = intel_de_read(dev_priv, reg); |
| 18274 | val &= ~TRANS_FRAME_START_DELAY_MASK(3 << 27); |
| 18275 | val |= TRANS_FRAME_START_DELAY(0)((0) << 27); |
| 18276 | intel_de_write(dev_priv, reg, val); |
| 18277 | } else { |
| 18278 | enum pipe pch_transcoder = intel_crtc_pch_transcoder(crtc); |
| 18279 | i915_reg_t reg = TRANS_CHICKEN2(pch_transcoder)((const i915_reg_t){ .reg = (((0xf0064) + (pch_transcoder) * ( (0xf1064) - (0xf0064)))) }); |
| 18280 | u32 val; |
| 18281 | |
| 18282 | val = intel_de_read(dev_priv, reg); |
| 18283 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK(3 << 27); |
| 18284 | val |= TRANS_CHICKEN2_FRAME_START_DELAY(0)((0) << 27); |
| 18285 | intel_de_write(dev_priv, reg, val); |
| 18286 | } |
| 18287 | } |
| 18288 | |
| 18289 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
| 18290 | struct drm_modeset_acquire_ctx *ctx) |
| 18291 | { |
| 18292 | struct drm_device *dev = crtc->base.dev; |
| 18293 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 18294 | struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18295 | |
| 18296 | if (crtc_state->hw.active) { |
| 18297 | struct intel_plane *plane; |
| 18298 | |
| 18299 | /* Clear any frame start delays used for debugging left by the BIOS */ |
| 18300 | intel_sanitize_frame_start_delay(crtc_state); |
| 18301 | |
| 18302 | /* Disable everything but the primary plane */ |
| 18303 | for_each_intel_plane_on_crtc(dev, crtc, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.plane_list)-> next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof (__typeof(*plane), base.head) );}); &plane->base.head != (&(dev)->mode_config.plane_list); plane = ({ const __typeof ( ((__typeof(*plane) *)0)->base.head ) *__mptr = (plane-> base.head.next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof (__typeof(*plane), base.head) );})) if (!((plane)->pipe == (crtc)->pipe)) {} else { |
| 18304 | const struct intel_plane_state *plane_state = |
| 18305 | to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane->base.state); (struct intel_plane_state * )( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 18306 | |
| 18307 | if (plane_state->uapi.visible && |
| 18308 | plane->base.type != DRM_PLANE_TYPE_PRIMARY) |
| 18309 | intel_plane_disable_noatomic(crtc, plane); |
| 18310 | } |
| 18311 | |
| 18312 | /* |
| 18313 | * Disable any background color set by the BIOS, but enable the |
| 18314 | * gamma and CSC to match how we program our planes. |
| 18315 | */ |
| 18316 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) |
| 18317 | intel_de_write(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[crtc->pipe] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70034) + ((&(dev_priv)->__info )->display_mmio_offset)) }), |
| 18318 | SKL_BOTTOM_COLOR_GAMMA_ENABLE(1 << 31) | SKL_BOTTOM_COLOR_CSC_ENABLE(1 << 30)); |
| 18319 | } |
| 18320 | |
| 18321 | /* Adjust the state of the output pipe according to whether we |
| 18322 | * have active connectors/encoders. */ |
| 18323 | if (crtc_state->hw.active && !intel_crtc_has_encoders(crtc)) |
| 18324 | intel_crtc_disable_noatomic(crtc, ctx); |
| 18325 | |
| 18326 | if (crtc_state->hw.active || HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) { |
| 18327 | /* |
| 18328 | * We start out with underrun reporting disabled to avoid races. |
| 18329 | * For correct bookkeeping mark this on active crtcs. |
| 18330 | * |
| 18331 | * Also on gmch platforms we dont have any hardware bits to |
| 18332 | * disable the underrun reporting. Which means we need to start |
| 18333 | * out with underrun reporting disabled also on inactive pipes, |
| 18334 | * since otherwise we'll complain about the garbage we read when |
| 18335 | * e.g. coming up after runtime pm. |
| 18336 | * |
| 18337 | * No protection against concurrent access is required - at |
| 18338 | * worst a fifo underrun happens which also sets this to false. |
| 18339 | */ |
| 18340 | crtc->cpu_fifo_underrun_disabled = true1; |
| 18341 | /* |
| 18342 | * We track the PCH trancoder underrun reporting state |
| 18343 | * within the crtc. With crtc for pipe A housing the underrun |
| 18344 | * reporting state for PCH transcoder A, crtc for pipe B housing |
| 18345 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, |
| 18346 | * and marking underrun reporting as disabled for the non-existing |
| 18347 | * PCH transcoders B and C would prevent enabling the south |
| 18348 | * error interrupt (see cpt_can_enable_serr_int()). |
| 18349 | */ |
| 18350 | if (has_pch_trancoder(dev_priv, crtc->pipe)) |
| 18351 | crtc->pch_fifo_underrun_disabled = true1; |
| 18352 | } |
| 18353 | } |
| 18354 | |
| 18355 | static bool_Bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state) |
| 18356 | { |
| 18357 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
| 18358 | |
| 18359 | /* |
| 18360 | * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram |
| 18361 | * the hardware when a high res displays plugged in. DPLL P |
| 18362 | * divider is zero, and the pipe timings are bonkers. We'll |
| 18363 | * try to disable everything in that case. |
| 18364 | * |
| 18365 | * FIXME would be nice to be able to sanitize this state |
| 18366 | * without several WARNs, but for now let's take the easy |
| 18367 | * road. |
| 18368 | */ |
| 18369 | return IS_GEN(dev_priv, 6)(0 + (&(dev_priv)->__info)->gen == (6)) && |
| 18370 | crtc_state->hw.active && |
| 18371 | crtc_state->shared_dpll && |
| 18372 | crtc_state->port_clock == 0; |
| 18373 | } |
| 18374 | |
| 18375 | static void intel_sanitize_encoder(struct intel_encoder *encoder) |
| 18376 | { |
| 18377 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
| 18378 | struct intel_connector *connector; |
| 18379 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (encoder->base.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 18380 | struct intel_crtc_state *crtc_state = crtc ? |
| 18381 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}) : NULL((void *)0); |
| 18382 | |
| 18383 | /* We need to check both for a crtc link (meaning that the |
| 18384 | * encoder is active and trying to read from a pipe) and the |
| 18385 | * pipe itself being active. */ |
| 18386 | bool_Bool has_active_crtc = crtc_state && |
| 18387 | crtc_state->hw.active; |
| 18388 | |
| 18389 | if (crtc_state && has_bogus_dpll_config(crtc_state)) { |
| 18390 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "BIOS has misprogrammed the hardware. Disabling pipe %c\n" , ((crtc->pipe) + 'A')) |
| 18391 | "BIOS has misprogrammed the hardware. Disabling pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "BIOS has misprogrammed the hardware. Disabling pipe %c\n" , ((crtc->pipe) + 'A')) |
| 18392 | pipe_name(crtc->pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "BIOS has misprogrammed the hardware. Disabling pipe %c\n" , ((crtc->pipe) + 'A')); |
| 18393 | has_active_crtc = false0; |
| 18394 | } |
| 18395 | |
| 18396 | connector = intel_encoder_find_connector(encoder); |
| 18397 | if (connector && !has_active_crtc) { |
| 18398 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] has active connectors but no active pipe!\n" , encoder->base.base.id, encoder->base.name) |
| 18399 | "[ENCODER:%d:%s] has active connectors but no active pipe!\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] has active connectors but no active pipe!\n" , encoder->base.base.id, encoder->base.name) |
| 18400 | encoder->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] has active connectors but no active pipe!\n" , encoder->base.base.id, encoder->base.name) |
| 18401 | encoder->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] has active connectors but no active pipe!\n" , encoder->base.base.id, encoder->base.name); |
| 18402 | |
| 18403 | /* Connector is active, but has no active pipe. This is |
| 18404 | * fallout from our resume register restoring. Disable |
| 18405 | * the encoder manually again. */ |
| 18406 | if (crtc_state) { |
| 18407 | struct drm_encoder *best_encoder; |
| 18408 | |
| 18409 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] manually disabled\n" , encoder->base.base.id, encoder->base.name) |
| 18410 | "[ENCODER:%d:%s] manually disabled\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] manually disabled\n" , encoder->base.base.id, encoder->base.name) |
| 18411 | encoder->base.base.id,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] manually disabled\n" , encoder->base.base.id, encoder->base.name) |
| 18412 | encoder->base.name)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] manually disabled\n" , encoder->base.base.id, encoder->base.name); |
| 18413 | |
| 18414 | /* avoid oopsing in case the hooks consult best_encoder */ |
| 18415 | best_encoder = connector->base.state->best_encoder; |
| 18416 | connector->base.state->best_encoder = &encoder->base; |
| 18417 | |
| 18418 | /* FIXME NULL atomic state passed! */ |
| 18419 | if (encoder->disable) |
| 18420 | encoder->disable(NULL((void *)0), encoder, crtc_state, |
| 18421 | connector->base.state); |
| 18422 | if (encoder->post_disable) |
| 18423 | encoder->post_disable(NULL((void *)0), encoder, crtc_state, |
| 18424 | connector->base.state); |
| 18425 | |
| 18426 | connector->base.state->best_encoder = best_encoder; |
| 18427 | } |
| 18428 | encoder->base.crtc = NULL((void *)0); |
| 18429 | |
| 18430 | /* Inconsistent output/port/pipe state happens presumably due to |
| 18431 | * a bug in one of the get_hw_state functions. Or someplace else |
| 18432 | * in our code, like the register restore mess on resume. Clamp |
| 18433 | * things to off as a safer default. */ |
| 18434 | |
| 18435 | connector->base.dpms = DRM_MODE_DPMS_OFF3; |
| 18436 | connector->base.encoder = NULL((void *)0); |
| 18437 | } |
| 18438 | |
| 18439 | /* notify opregion of the sanitized encoder state */ |
| 18440 | intel_opregion_notify_encoder(encoder, connector && has_active_crtc); |
| 18441 | |
| 18442 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 11) |
| 18443 | icl_sanitize_encoder_pll_mapping(encoder); |
| 18444 | } |
| 18445 | |
| 18446 | /* FIXME read out full plane state for all planes */ |
| 18447 | static void readout_plane_state(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 18448 | { |
| 18449 | struct intel_plane *plane; |
| 18450 | struct intel_crtc *crtc; |
| 18451 | |
| 18452 | for_each_intel_plane(&dev_priv->drm, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane), base.head) );}); &plane ->base.head != (&(&dev_priv->drm)->mode_config .plane_list); plane = ({ const __typeof( ((__typeof(*plane) * )0)->base.head ) *__mptr = (plane->base.head.next); (__typeof (*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane ), base.head) );})) { |
| 18453 | struct intel_plane_state *plane_state = |
| 18454 | to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane->base.state); (struct intel_plane_state * )( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 18455 | struct intel_crtc_state *crtc_state; |
| 18456 | enum pipe pipe = PIPE_A; |
| 18457 | bool_Bool visible; |
| 18458 | |
| 18459 | visible = plane->get_hw_state(plane, &pipe); |
| 18460 | |
| 18461 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 18462 | crtc_state = to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18463 | |
| 18464 | intel_set_plane_visible(crtc_state, plane_state, visible); |
| 18465 | |
| 18466 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] hw state readout: %s, pipe %c\n" , plane->base.base.id, plane->base.name, enableddisabled (visible), ((pipe) + 'A')) |
| 18467 | "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] hw state readout: %s, pipe %c\n" , plane->base.base.id, plane->base.name, enableddisabled (visible), ((pipe) + 'A')) |
| 18468 | plane->base.base.id, plane->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] hw state readout: %s, pipe %c\n" , plane->base.base.id, plane->base.name, enableddisabled (visible), ((pipe) + 'A')) |
| 18469 | enableddisabled(visible), pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] hw state readout: %s, pipe %c\n" , plane->base.base.id, plane->base.name, enableddisabled (visible), ((pipe) + 'A')); |
| 18470 | } |
| 18471 | |
| 18472 | for_each_intel_crtc(&dev_priv->drm, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(&dev_priv->drm)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) * __mptr = (crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), base.head) ); })) { |
| 18473 | struct intel_crtc_state *crtc_state = |
| 18474 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18475 | |
| 18476 | fixup_active_planes(crtc_state); |
| 18477 | } |
| 18478 | } |
| 18479 | |
| 18480 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
| 18481 | { |
| 18482 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 18483 | struct intel_cdclk_state *cdclk_state = |
| 18484 | to_intel_cdclk_state(dev_priv->cdclk.obj.state)({ const __typeof( ((struct intel_cdclk_state *)0)->base ) *__mptr = ((dev_priv->cdclk.obj.state)); (struct intel_cdclk_state *)( (char *)__mptr - __builtin_offsetof(struct intel_cdclk_state , base) );}); |
| 18485 | struct intel_dbuf_state *dbuf_state = |
| 18486 | to_intel_dbuf_state(dev_priv->dbuf.obj.state)({ const __typeof( ((struct intel_dbuf_state *)0)->base ) * __mptr = ((dev_priv->dbuf.obj.state)); (struct intel_dbuf_state *)( (char *)__mptr - __builtin_offsetof(struct intel_dbuf_state , base) );}); |
| 18487 | enum pipe pipe; |
| 18488 | struct intel_crtc *crtc; |
| 18489 | struct intel_encoder *encoder; |
| 18490 | struct intel_connector *connector; |
| 18491 | struct drm_connector_list_iter conn_iter; |
| 18492 | u8 active_pipes = 0; |
| 18493 | |
| 18494 | for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof ( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc-> base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );})) { |
| 18495 | struct intel_crtc_state *crtc_state = |
| 18496 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18497 | |
| 18498 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); |
| 18499 | intel_crtc_free_hw_state(crtc_state); |
| 18500 | intel_crtc_state_reset(crtc_state, crtc); |
| 18501 | |
| 18502 | crtc_state->hw.active = crtc_state->hw.enable = |
| 18503 | dev_priv->display.get_pipe_config(crtc, crtc_state); |
| 18504 | |
| 18505 | crtc->base.enabled = crtc_state->hw.enable; |
| 18506 | crtc->active = crtc_state->hw.active; |
| 18507 | |
| 18508 | if (crtc_state->hw.active) |
| 18509 | active_pipes |= BIT(crtc->pipe)(1UL << (crtc->pipe)); |
| 18510 | |
| 18511 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state readout: %s\n" , crtc->base.base.id, crtc->base.name, enableddisabled( crtc_state->hw.active)) |
| 18512 | "[CRTC:%d:%s] hw state readout: %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state readout: %s\n" , crtc->base.base.id, crtc->base.name, enableddisabled( crtc_state->hw.active)) |
| 18513 | crtc->base.base.id, crtc->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state readout: %s\n" , crtc->base.base.id, crtc->base.name, enableddisabled( crtc_state->hw.active)) |
| 18514 | enableddisabled(crtc_state->hw.active))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CRTC:%d:%s] hw state readout: %s\n" , crtc->base.base.id, crtc->base.name, enableddisabled( crtc_state->hw.active)); |
| 18515 | } |
| 18516 | |
| 18517 | dev_priv->active_pipes = cdclk_state->active_pipes = |
| 18518 | dbuf_state->active_pipes = active_pipes; |
| 18519 | |
| 18520 | readout_plane_state(dev_priv); |
| 18521 | |
| 18522 | intel_dpll_readout_hw_state(dev_priv); |
| 18523 | |
| 18524 | for_each_intel_encoder(dev, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );}); &encoder->base.head != (&(dev)->mode_config.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->base.head ) *__mptr = (encoder->base.head.next); (__typeof(*encoder) *)( (char * )__mptr - __builtin_offsetof(__typeof(*encoder), base.head) ) ;})) { |
| 18525 | pipe = 0; |
| 18526 | |
| 18527 | if (encoder->get_hw_state(encoder, &pipe)) { |
| 18528 | struct intel_crtc_state *crtc_state; |
| 18529 | |
| 18530 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
| 18531 | crtc_state = to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18532 | |
| 18533 | encoder->base.crtc = &crtc->base; |
| 18534 | encoder->get_config(encoder, crtc_state); |
| 18535 | } else { |
| 18536 | encoder->base.crtc = NULL((void *)0); |
| 18537 | } |
| 18538 | |
| 18539 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n" , encoder->base.base.id, encoder->base.name, enableddisabled (encoder->base.crtc), ((pipe) + 'A')) |
| 18540 | "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n" , encoder->base.base.id, encoder->base.name, enableddisabled (encoder->base.crtc), ((pipe) + 'A')) |
| 18541 | encoder->base.base.id, encoder->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n" , encoder->base.base.id, encoder->base.name, enableddisabled (encoder->base.crtc), ((pipe) + 'A')) |
| 18542 | enableddisabled(encoder->base.crtc),drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n" , encoder->base.base.id, encoder->base.name, enableddisabled (encoder->base.crtc), ((pipe) + 'A')) |
| 18543 | pipe_name(pipe))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n" , encoder->base.base.id, encoder->base.name, enableddisabled (encoder->base.crtc), ((pipe) + 'A')); |
| 18544 | } |
| 18545 | |
| 18546 | drm_connector_list_iter_begin(dev, &conn_iter); |
| 18547 | for_each_intel_connector_iter(connector, &conn_iter)while ((connector = ({ const __typeof( ((struct intel_connector *)0)->base ) *__mptr = (drm_connector_list_iter_next(& conn_iter)); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof (struct intel_connector, base) );}))) { |
| 18548 | if (connector->get_hw_state(connector)) { |
| 18549 | struct intel_crtc_state *crtc_state; |
| 18550 | struct intel_crtc *crtc; |
| 18551 | |
| 18552 | connector->base.dpms = DRM_MODE_DPMS_ON0; |
| 18553 | |
| 18554 | encoder = intel_attached_encoder(connector); |
| 18555 | connector->base.encoder = &encoder->base; |
| 18556 | |
| 18557 | crtc = to_intel_crtc(encoder->base.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (encoder->base.crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
| 18558 | crtc_state = crtc ? to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}) : NULL((void *)0); |
| 18559 | |
| 18560 | if (crtc_state && crtc_state->hw.active) { |
| 18561 | /* |
| 18562 | * This has to be done during hardware readout |
| 18563 | * because anything calling .crtc_disable may |
| 18564 | * rely on the connector_mask being accurate. |
| 18565 | */ |
| 18566 | crtc_state->uapi.connector_mask |= |
| 18567 | drm_connector_mask(&connector->base); |
| 18568 | crtc_state->uapi.encoder_mask |= |
| 18569 | drm_encoder_mask(&encoder->base); |
| 18570 | } |
| 18571 | } else { |
| 18572 | connector->base.dpms = DRM_MODE_DPMS_OFF3; |
| 18573 | connector->base.encoder = NULL((void *)0); |
| 18574 | } |
| 18575 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] hw state readout: %s\n" , connector->base.base.id, connector->base.name, enableddisabled (connector->base.encoder)) |
| 18576 | "[CONNECTOR:%d:%s] hw state readout: %s\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] hw state readout: %s\n" , connector->base.base.id, connector->base.name, enableddisabled (connector->base.encoder)) |
| 18577 | connector->base.base.id, connector->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] hw state readout: %s\n" , connector->base.base.id, connector->base.name, enableddisabled (connector->base.encoder)) |
| 18578 | enableddisabled(connector->base.encoder))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[CONNECTOR:%d:%s] hw state readout: %s\n" , connector->base.base.id, connector->base.name, enableddisabled (connector->base.encoder)); |
| 18579 | } |
| 18580 | drm_connector_list_iter_end(&conn_iter); |
| 18581 | |
| 18582 | for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof ( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc-> base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );})) { |
| 18583 | struct intel_bw_state *bw_state = |
| 18584 | to_intel_bw_state(dev_priv->bw_obj.state)({ const __typeof( ((struct intel_bw_state *)0)->base ) *__mptr = ((dev_priv->bw_obj.state)); (struct intel_bw_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_bw_state, base ) );}); |
| 18585 | struct intel_crtc_state *crtc_state = |
| 18586 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18587 | struct intel_plane *plane; |
| 18588 | int min_cdclk = 0; |
| 18589 | |
| 18590 | if (crtc_state->hw.active) { |
| 18591 | struct drm_display_mode *mode = &crtc_state->hw.mode; |
| 18592 | |
| 18593 | intel_mode_from_pipe_config(&crtc_state->hw.adjusted_mode, |
| 18594 | crtc_state); |
| 18595 | |
| 18596 | *mode = crtc_state->hw.adjusted_mode; |
| 18597 | mode->hdisplay = crtc_state->pipe_src_w; |
| 18598 | mode->vdisplay = crtc_state->pipe_src_h; |
| 18599 | |
| 18600 | /* |
| 18601 | * The initial mode needs to be set in order to keep |
| 18602 | * the atomic core happy. It wants a valid mode if the |
| 18603 | * crtc's enabled, so we do the above call. |
| 18604 | * |
| 18605 | * But we don't set all the derived state fully, hence |
| 18606 | * set a flag to indicate that a full recalculation is |
| 18607 | * needed on the next commit. |
| 18608 | */ |
| 18609 | crtc_state->inherited = true1; |
| 18610 | |
| 18611 | intel_crtc_compute_pixel_rate(crtc_state); |
| 18612 | |
| 18613 | intel_crtc_update_active_timings(crtc_state); |
| 18614 | |
| 18615 | intel_crtc_copy_hw_to_uapi_state(crtc_state); |
| 18616 | } |
| 18617 | |
| 18618 | for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)for (plane = ({ const __typeof( ((__typeof(*plane) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .plane_list)->next); (__typeof(*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane), base.head) );}); &plane ->base.head != (&(&dev_priv->drm)->mode_config .plane_list); plane = ({ const __typeof( ((__typeof(*plane) * )0)->base.head ) *__mptr = (plane->base.head.next); (__typeof (*plane) *)( (char *)__mptr - __builtin_offsetof(__typeof(*plane ), base.head) );})) if (!((plane)->pipe == (crtc)->pipe )) {} else { |
| 18619 | const struct intel_plane_state *plane_state = |
| 18620 | to_intel_plane_state(plane->base.state)({ const __typeof( ((struct intel_plane_state *)0)->uapi ) *__mptr = (plane->base.state); (struct intel_plane_state * )( (char *)__mptr - __builtin_offsetof(struct intel_plane_state , uapi) );}); |
| 18621 | |
| 18622 | /* |
| 18623 | * FIXME don't have the fb yet, so can't |
| 18624 | * use intel_plane_data_rate() :( |
| 18625 | */ |
| 18626 | if (plane_state->uapi.visible) |
| 18627 | crtc_state->data_rate[plane->id] = |
| 18628 | 4 * crtc_state->pixel_rate; |
| 18629 | /* |
| 18630 | * FIXME don't have the fb yet, so can't |
| 18631 | * use plane->min_cdclk() :( |
| 18632 | */ |
| 18633 | if (plane_state->uapi.visible && plane->min_cdclk) { |
| 18634 | if (crtc_state->double_wide || |
| 18635 | INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 10 || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) |
| 18636 | crtc_state->min_cdclk[plane->id] = |
| 18637 | DIV_ROUND_UP(crtc_state->pixel_rate, 2)(((crtc_state->pixel_rate) + ((2) - 1)) / (2)); |
| 18638 | else |
| 18639 | crtc_state->min_cdclk[plane->id] = |
| 18640 | crtc_state->pixel_rate; |
| 18641 | } |
| 18642 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] min_cdclk %d kHz\n" , plane->base.base.id, plane->base.name, crtc_state-> min_cdclk[plane->id]) |
| 18643 | "[PLANE:%d:%s] min_cdclk %d kHz\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] min_cdclk %d kHz\n" , plane->base.base.id, plane->base.name, crtc_state-> min_cdclk[plane->id]) |
| 18644 | plane->base.base.id, plane->base.name,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] min_cdclk %d kHz\n" , plane->base.base.id, plane->base.name, crtc_state-> min_cdclk[plane->id]) |
| 18645 | crtc_state->min_cdclk[plane->id])drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "[PLANE:%d:%s] min_cdclk %d kHz\n" , plane->base.base.id, plane->base.name, crtc_state-> min_cdclk[plane->id]); |
| 18646 | } |
| 18647 | |
| 18648 | if (crtc_state->hw.active) { |
| 18649 | min_cdclk = intel_crtc_compute_min_cdclk(crtc_state); |
| 18650 | if (drm_WARN_ON(dev, min_cdclk < 0)({ int __ret = !!((min_cdclk < 0)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "min_cdclk < 0" ")"); __builtin_expect(!!(__ret), 0); })) |
| 18651 | min_cdclk = 0; |
| 18652 | } |
| 18653 | |
| 18654 | cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; |
| 18655 | cdclk_state->min_voltage_level[crtc->pipe] = |
| 18656 | crtc_state->min_voltage_level; |
| 18657 | |
| 18658 | intel_bw_crtc_update(bw_state, crtc_state); |
| 18659 | |
| 18660 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
| 18661 | } |
| 18662 | } |
| 18663 | |
| 18664 | static void |
| 18665 | get_encoder_power_domains(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 18666 | { |
| 18667 | struct intel_encoder *encoder; |
| 18668 | |
| 18669 | for_each_intel_encoder(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) { |
| 18670 | struct intel_crtc_state *crtc_state; |
| 18671 | |
| 18672 | if (!encoder->get_power_domains) |
| 18673 | continue; |
| 18674 | |
| 18675 | /* |
| 18676 | * MST-primary and inactive encoders don't have a crtc state |
| 18677 | * and neither of these require any power domain references. |
| 18678 | */ |
| 18679 | if (!encoder->base.crtc) |
| 18680 | continue; |
| 18681 | |
| 18682 | crtc_state = to_intel_crtc_state(encoder->base.crtc->state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (encoder->base.crtc->state); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state , uapi) );}); |
| 18683 | encoder->get_power_domains(encoder, crtc_state); |
| 18684 | } |
| 18685 | } |
| 18686 | |
| 18687 | static void intel_early_display_was(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 18688 | { |
| 18689 | /* |
| 18690 | * Display WA #1185 WaDisableDARBFClkGating:cnl,glk,icl,ehl,tgl |
| 18691 | * Also known as Wa_14010480278. |
| 18692 | */ |
| 18693 | if (IS_GEN_RANGE(dev_priv, 10, 12)(!!((&(dev_priv)->__info)->gen_mask & ( 0 + 0 + (((~0UL) >> (64 - (((12)) - 1) - 1)) & ((~0UL) << (((10)) - 1)))))) || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) |
| 18694 | intel_de_write(dev_priv, GEN9_CLKGATE_DIS_0((const i915_reg_t){ .reg = (0x46530) }), |
| 18695 | intel_de_read(dev_priv, GEN9_CLKGATE_DIS_0((const i915_reg_t){ .reg = (0x46530) })) | DARBF_GATING_DIS(1 << 27)); |
| 18696 | |
| 18697 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) { |
| 18698 | /* |
| 18699 | * WaRsPkgCStateDisplayPMReq:hsw |
| 18700 | * System hang if this isn't done before disabling all planes! |
| 18701 | */ |
| 18702 | intel_de_write(dev_priv, CHICKEN_PAR1_1((const i915_reg_t){ .reg = (0x42080) }), |
| 18703 | intel_de_read(dev_priv, CHICKEN_PAR1_1((const i915_reg_t){ .reg = (0x42080) })) | FORCE_ARB_IDLE_PLANES(1 << 14)); |
| 18704 | } |
| 18705 | } |
| 18706 | |
| 18707 | static void ibx_sanitize_pch_hdmi_port(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 18708 | enum port port, i915_reg_t hdmi_reg) |
| 18709 | { |
| 18710 | u32 val = intel_de_read(dev_priv, hdmi_reg); |
| 18711 | |
| 18712 | if (val & SDVO_ENABLE(1 << 31) || |
| 18713 | (val & SDVO_PIPE_SEL_MASK(1 << 30)) == SDVO_PIPE_SEL(PIPE_A)((PIPE_A) << 30)) |
| 18714 | return; |
| 18715 | |
| 18716 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sanitizing transcoder select for HDMI %c\n" , ((port) + 'A')) |
| 18717 | "Sanitizing transcoder select for HDMI %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sanitizing transcoder select for HDMI %c\n" , ((port) + 'A')) |
| 18718 | port_name(port))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sanitizing transcoder select for HDMI %c\n" , ((port) + 'A')); |
| 18719 | |
| 18720 | val &= ~SDVO_PIPE_SEL_MASK(1 << 30); |
| 18721 | val |= SDVO_PIPE_SEL(PIPE_A)((PIPE_A) << 30); |
| 18722 | |
| 18723 | intel_de_write(dev_priv, hdmi_reg, val); |
| 18724 | } |
| 18725 | |
| 18726 | static void ibx_sanitize_pch_dp_port(struct drm_i915_privateinteldrm_softc *dev_priv, |
| 18727 | enum port port, i915_reg_t dp_reg) |
| 18728 | { |
| 18729 | u32 val = intel_de_read(dev_priv, dp_reg); |
| 18730 | |
| 18731 | if (val & DP_PORT_EN(1 << 31) || |
| 18732 | (val & DP_PIPE_SEL_MASK(1 << 30)) == DP_PIPE_SEL(PIPE_A)((PIPE_A) << 30)) |
| 18733 | return; |
| 18734 | |
| 18735 | drm_dbg_kms(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sanitizing transcoder select for DP %c\n" , ((port) + 'A')) |
| 18736 | "Sanitizing transcoder select for DP %c\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sanitizing transcoder select for DP %c\n" , ((port) + 'A')) |
| 18737 | port_name(port))drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Sanitizing transcoder select for DP %c\n" , ((port) + 'A')); |
| 18738 | |
| 18739 | val &= ~DP_PIPE_SEL_MASK(1 << 30); |
| 18740 | val |= DP_PIPE_SEL(PIPE_A)((PIPE_A) << 30); |
| 18741 | |
| 18742 | intel_de_write(dev_priv, dp_reg, val); |
| 18743 | } |
| 18744 | |
| 18745 | static void ibx_sanitize_pch_ports(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 18746 | { |
| 18747 | /* |
| 18748 | * The BIOS may select transcoder B on some of the PCH |
| 18749 | * ports even it doesn't enable the port. This would trip |
| 18750 | * assert_pch_dp_disabled() and assert_pch_hdmi_disabled(). |
| 18751 | * Sanitize the transcoder select bits to prevent that. We |
| 18752 | * assume that the BIOS never actually enabled the port, |
| 18753 | * because if it did we'd actually have to toggle the port |
| 18754 | * on and back off to make the transcoder A select stick |
| 18755 | * (see. intel_dp_link_down(), intel_disable_hdmi(), |
| 18756 | * intel_disable_sdvo()). |
| 18757 | */ |
| 18758 | ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B((const i915_reg_t){ .reg = (0xe4100) })); |
| 18759 | ibx_sanitize_pch_dp_port(dev_priv, PORT_C, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) })); |
| 18760 | ibx_sanitize_pch_dp_port(dev_priv, PORT_D, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) })); |
| 18761 | |
| 18762 | /* PCH SDVOB multiplex with HDMIB */ |
| 18763 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB((const i915_reg_t){ .reg = (0xe1140) })); |
| 18764 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_C, PCH_HDMIC((const i915_reg_t){ .reg = (0xe1150) })); |
| 18765 | ibx_sanitize_pch_hdmi_port(dev_priv, PORT_D, PCH_HDMID((const i915_reg_t){ .reg = (0xe1160) })); |
| 18766 | } |
| 18767 | |
| 18768 | /* Scan out the current hw modeset state, |
| 18769 | * and sanitizes it to the current state |
| 18770 | */ |
| 18771 | static void |
| 18772 | intel_modeset_setup_hw_state(struct drm_device *dev, |
| 18773 | struct drm_modeset_acquire_ctx *ctx) |
| 18774 | { |
| 18775 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 18776 | struct intel_encoder *encoder; |
| 18777 | struct intel_crtc *crtc; |
| 18778 | intel_wakeref_t wakeref; |
| 18779 | |
| 18780 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); |
| 18781 | |
| 18782 | intel_early_display_was(dev_priv); |
| 18783 | intel_modeset_readout_hw_state(dev); |
| 18784 | |
| 18785 | /* HW state is read out, now we need to sanitize this mess. */ |
| 18786 | |
| 18787 | /* Sanitize the TypeC port mode upfront, encoders depend on this */ |
| 18788 | for_each_intel_encoder(dev, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );}); &encoder->base.head != (&(dev)->mode_config.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->base.head ) *__mptr = (encoder->base.head.next); (__typeof(*encoder) *)( (char * )__mptr - __builtin_offsetof(__typeof(*encoder), base.head) ) ;})) { |
| 18789 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
| 18790 | |
| 18791 | /* We need to sanitize only the MST primary port. */ |
| 18792 | if (encoder->type != INTEL_OUTPUT_DP_MST && |
| 18793 | intel_phy_is_tc(dev_priv, phy)) |
| 18794 | intel_tc_port_sanitize(enc_to_dig_port(encoder)); |
| 18795 | } |
| 18796 | |
| 18797 | get_encoder_power_domains(dev_priv); |
| 18798 | |
| 18799 | if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX)) |
| 18800 | ibx_sanitize_pch_ports(dev_priv); |
| 18801 | |
| 18802 | /* |
| 18803 | * intel_sanitize_plane_mapping() may need to do vblank |
| 18804 | * waits, so we need vblank interrupts restored beforehand. |
| 18805 | */ |
| 18806 | for_each_intel_crtc(&dev_priv->drm, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(&dev_priv->drm)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) * __mptr = (crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), base.head) ); })) { |
| 18807 | struct intel_crtc_state *crtc_state = |
| 18808 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18809 | |
| 18810 | drm_crtc_vblank_reset(&crtc->base); |
| 18811 | |
| 18812 | if (crtc_state->hw.active) |
| 18813 | intel_crtc_vblank_on(crtc_state); |
| 18814 | } |
| 18815 | |
| 18816 | intel_sanitize_plane_mapping(dev_priv); |
| 18817 | |
| 18818 | for_each_intel_encoder(dev, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );}); &encoder->base.head != (&(dev)->mode_config.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->base.head ) *__mptr = (encoder->base.head.next); (__typeof(*encoder) *)( (char * )__mptr - __builtin_offsetof(__typeof(*encoder), base.head) ) ;})) |
| 18819 | intel_sanitize_encoder(encoder); |
| 18820 | |
| 18821 | for_each_intel_crtc(&dev_priv->drm, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(&dev_priv->drm)->mode_config .crtc_list)->next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(&dev_priv->drm)->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base.head ) * __mptr = (crtc->base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), base.head) ); })) { |
| 18822 | struct intel_crtc_state *crtc_state = |
| 18823 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18824 | |
| 18825 | intel_sanitize_crtc(crtc, ctx); |
| 18826 | intel_dump_pipe_config(crtc_state, NULL((void *)0), "[setup_hw_state]"); |
| 18827 | } |
| 18828 | |
| 18829 | intel_modeset_update_connector_atomic_state(dev); |
| 18830 | |
| 18831 | intel_dpll_sanitize_state(dev_priv); |
| 18832 | |
| 18833 | if (IS_G4X(dev_priv)(IS_PLATFORM(dev_priv, INTEL_G45) || IS_PLATFORM(dev_priv, INTEL_GM45 ))) { |
| 18834 | g4x_wm_get_hw_state(dev_priv); |
| 18835 | g4x_wm_sanitize(dev_priv); |
| 18836 | } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
| 18837 | vlv_wm_get_hw_state(dev_priv); |
| 18838 | vlv_wm_sanitize(dev_priv); |
| 18839 | } else if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 9) { |
| 18840 | skl_wm_get_hw_state(dev_priv); |
| 18841 | } else if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
| 18842 | ilk_wm_get_hw_state(dev_priv); |
| 18843 | } |
| 18844 | |
| 18845 | for_each_intel_crtc(dev, crtc)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->base .head ) *__mptr = ((&(dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );}); &crtc->base.head != (&(dev)->mode_config.crtc_list); crtc = ({ const __typeof ( ((__typeof(*crtc) *)0)->base.head ) *__mptr = (crtc-> base.head.next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), base.head) );})) { |
| 18846 | struct intel_crtc_state *crtc_state = |
| 18847 | to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
| 18848 | u64 put_domains; |
| 18849 | |
| 18850 | put_domains = modeset_get_crtc_power_domains(crtc_state); |
| 18851 | if (drm_WARN_ON(dev, put_domains)({ int __ret = !!((put_domains)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "put_domains" ")"); __builtin_expect(!!(__ret), 0); })) |
| 18852 | modeset_put_power_domains(dev_priv, put_domains); |
| 18853 | } |
| 18854 | |
| 18855 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); |
| 18856 | } |
| 18857 | |
| 18858 | void intel_display_resume(struct drm_device *dev) |
| 18859 | { |
| 18860 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
| 18861 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; |
| 18862 | struct drm_modeset_acquire_ctx ctx; |
| 18863 | int ret; |
| 18864 | |
| 18865 | dev_priv->modeset_restore_state = NULL((void *)0); |
| 18866 | if (state) |
| 18867 | state->acquire_ctx = &ctx; |
| 18868 | |
| 18869 | drm_modeset_acquire_init(&ctx, 0); |
| 18870 | |
| 18871 | while (1) { |
| 18872 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
| 18873 | if (ret != -EDEADLK11) |
| 18874 | break; |
| 18875 | |
| 18876 | drm_modeset_backoff(&ctx); |
| 18877 | } |
| 18878 | |
| 18879 | if (!ret) |
| 18880 | ret = __intel_display_resume(dev, state, &ctx); |
| 18881 | |
| 18882 | intel_enable_ipc(dev_priv); |
| 18883 | drm_modeset_drop_locks(&ctx); |
| 18884 | drm_modeset_acquire_fini(&ctx); |
| 18885 | |
| 18886 | if (ret) |
| 18887 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
| 18888 | "Restoring old state failed with %i\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Restoring old state failed with %i\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
| 18889 | if (state) |
| 18890 | drm_atomic_state_put(state); |
| 18891 | } |
| 18892 | |
| 18893 | static void intel_hpd_poll_fini(struct drm_i915_privateinteldrm_softc *i915) |
| 18894 | { |
| 18895 | struct intel_connector *connector; |
| 18896 | struct drm_connector_list_iter conn_iter; |
| 18897 | |
| 18898 | /* Kill all the work that may have been queued by hpd. */ |
| 18899 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); |
| 18900 | for_each_intel_connector_iter(connector, &conn_iter)while ((connector = ({ const __typeof( ((struct intel_connector *)0)->base ) *__mptr = (drm_connector_list_iter_next(& conn_iter)); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof (struct intel_connector, base) );}))) { |
| 18901 | #ifdef __linux__ |
| 18902 | if (connector->modeset_retry_work.func) |
| 18903 | #else |
| 18904 | if (connector->modeset_retry_work.task.t_func) |
| 18905 | #endif |
| 18906 | cancel_work_sync(&connector->modeset_retry_work); |
| 18907 | if (connector->hdcp.shim) { |
| 18908 | cancel_delayed_work_sync(&connector->hdcp.check_work); |
| 18909 | cancel_work_sync(&connector->hdcp.prop_work); |
| 18910 | } |
| 18911 | } |
| 18912 | drm_connector_list_iter_end(&conn_iter); |
| 18913 | } |
| 18914 | |
| 18915 | /* part #1: call before irq uninstall */ |
| 18916 | void intel_modeset_driver_remove(struct drm_i915_privateinteldrm_softc *i915) |
| 18917 | { |
| 18918 | flush_workqueue(i915->flip_wq); |
| 18919 | flush_workqueue(i915->modeset_wq); |
| 18920 | |
| 18921 | flush_work(&i915->atomic_helper.free_work); |
| 18922 | drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list))({ int __ret = !!((!llist_empty(&i915->atomic_helper.free_list ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& i915->drm))->dev), "", "drm_WARN_ON(" "!llist_empty(&i915->atomic_helper.free_list)" ")"); __builtin_expect(!!(__ret), 0); }); |
| 18923 | } |
| 18924 | |
| 18925 | /* part #2: call after irq uninstall */ |
| 18926 | void intel_modeset_driver_remove_noirq(struct drm_i915_privateinteldrm_softc *i915) |
| 18927 | { |
| 18928 | /* |
| 18929 | * Due to the hpd irq storm handling the hotplug work can re-arm the |
| 18930 | * poll handlers. Hence disable polling after hpd handling is shut down. |
| 18931 | */ |
| 18932 | intel_hpd_poll_fini(i915); |
| 18933 | |
| 18934 | /* |
| 18935 | * MST topology needs to be suspended so we don't have any calls to |
| 18936 | * fbdev after it's finalized. MST will be destroyed later as part of |
| 18937 | * drm_mode_config_cleanup() |
| 18938 | */ |
| 18939 | intel_dp_mst_suspend(i915); |
| 18940 | |
| 18941 | /* poll work can call into fbdev, hence clean that up afterwards */ |
| 18942 | intel_fbdev_fini(i915); |
| 18943 | |
| 18944 | intel_unregister_dsm_handler(); |
| 18945 | |
| 18946 | intel_fbc_global_disable(i915); |
| 18947 | |
| 18948 | /* flush any delayed tasks or pending work */ |
| 18949 | flush_scheduled_work()flush_workqueue(system_wq); |
| 18950 | |
| 18951 | intel_hdcp_component_fini(i915); |
| 18952 | |
| 18953 | intel_mode_config_cleanup(i915); |
| 18954 | |
| 18955 | intel_overlay_cleanup(i915); |
| 18956 | |
| 18957 | intel_gmbus_teardown(i915); |
| 18958 | |
| 18959 | destroy_workqueue(i915->flip_wq); |
| 18960 | destroy_workqueue(i915->modeset_wq); |
| 18961 | |
| 18962 | intel_fbc_cleanup_cfb(i915); |
| 18963 | } |
| 18964 | |
| 18965 | /* part #3: call after gem init */ |
| 18966 | void intel_modeset_driver_remove_nogem(struct drm_i915_privateinteldrm_softc *i915) |
| 18967 | { |
| 18968 | intel_csr_ucode_fini(i915); |
| 18969 | |
| 18970 | intel_power_domains_driver_remove(i915); |
| 18971 | |
| 18972 | intel_vga_unregister(i915); |
| 18973 | |
| 18974 | intel_bios_driver_remove(i915); |
| 18975 | } |
| 18976 | |
| 18977 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)1 |
| 18978 | |
| 18979 | struct intel_display_error_state { |
| 18980 | |
| 18981 | u32 power_well_driver; |
| 18982 | |
| 18983 | struct intel_cursor_error_state { |
| 18984 | u32 control; |
| 18985 | u32 position; |
| 18986 | u32 base; |
| 18987 | u32 size; |
| 18988 | } cursor[I915_MAX_PIPES]; |
| 18989 | |
| 18990 | struct intel_pipe_error_state { |
| 18991 | bool_Bool power_domain_on; |
| 18992 | u32 source; |
| 18993 | u32 stat; |
| 18994 | } pipe[I915_MAX_PIPES]; |
| 18995 | |
| 18996 | struct intel_plane_error_state { |
| 18997 | u32 control; |
| 18998 | u32 stride; |
| 18999 | u32 size; |
| 19000 | u32 pos; |
| 19001 | u32 addr; |
| 19002 | u32 surface; |
| 19003 | u32 tile_offset; |
| 19004 | } plane[I915_MAX_PIPES]; |
| 19005 | |
| 19006 | struct intel_transcoder_error_state { |
| 19007 | bool_Bool available; |
| 19008 | bool_Bool power_domain_on; |
| 19009 | enum transcoder cpu_transcoder; |
| 19010 | |
| 19011 | u32 conf; |
| 19012 | |
| 19013 | u32 htotal; |
| 19014 | u32 hblank; |
| 19015 | u32 hsync; |
| 19016 | u32 vtotal; |
| 19017 | u32 vblank; |
| 19018 | u32 vsync; |
| 19019 | } transcoder[5]; |
| 19020 | }; |
| 19021 | |
| 19022 | struct intel_display_error_state * |
| 19023 | intel_display_capture_error_state(struct drm_i915_privateinteldrm_softc *dev_priv) |
| 19024 | { |
| 19025 | struct intel_display_error_state *error; |
| 19026 | int transcoders[] = { |
| 19027 | TRANSCODER_A, |
| 19028 | TRANSCODER_B, |
| 19029 | TRANSCODER_C, |
| 19030 | TRANSCODER_D, |
| 19031 | TRANSCODER_EDP, |
| 19032 | }; |
| 19033 | int i; |
| 19034 | |
| 19035 | BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder))extern char _ctassert[(!((sizeof((transcoders)) / sizeof((transcoders )[0])) != (sizeof((error->transcoder)) / sizeof((error-> transcoder)[0])))) ? 1 : -1 ] __attribute__((__unused__)); |
| 19036 | |
| 19037 | if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__info)->pipe_mask != 0)) |
| 19038 | return NULL((void *)0); |
| 19039 | |
| 19040 | error = kzalloc(sizeof(*error), GFP_ATOMIC0x0002); |
| 19041 | if (error == NULL((void *)0)) |
| 19042 | return NULL((void *)0); |
| 19043 | |
| 19044 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 19045 | error->power_well_driver = intel_de_read(dev_priv, |
| 19046 | HSW_PWR_WELL_CTL2((const i915_reg_t){ .reg = (0x45404) })); |
| 19047 | |
| 19048 | for_each_pipe(dev_priv, i)for ((i) = 0; (i) < I915_MAX_PIPES; (i)++) if (!((&(dev_priv )->__info)->pipe_mask & (1UL << (i)))) {} else { |
| 19049 | error->pipe[i].power_domain_on = |
| 19050 | __intel_display_power_is_enabled(dev_priv, |
| 19051 | POWER_DOMAIN_PIPE(i)((i) + POWER_DOMAIN_PIPE_A)); |
| 19052 | if (!error->pipe[i].power_domain_on) |
| 19053 | continue; |
| 19054 | |
| 19055 | error->cursor[i].control = intel_de_read(dev_priv, CURCNTR(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(i)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70080) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19056 | error->cursor[i].position = intel_de_read(dev_priv, CURPOS(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(i)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70088) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19057 | error->cursor[i].base = intel_de_read(dev_priv, CURBASE(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> cursor_offsets[(i)] - (&(dev_priv)->__info)->cursor_offsets [PIPE_A] + (0x70084) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19058 | |
| 19059 | error->plane[i].control = intel_de_read(dev_priv, DSPCNTR(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70180) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19060 | error->plane[i].stride = intel_de_read(dev_priv, DSPSTRIDE(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70188) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19061 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) <= 3) { |
| 19062 | error->plane[i].size = intel_de_read(dev_priv, |
| 19063 | DSPSIZE(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70190) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19064 | error->plane[i].pos = intel_de_read(dev_priv, |
| 19065 | DSPPOS(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7018C) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19066 | } |
| 19067 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) <= 7 && !IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 19068 | error->plane[i].addr = intel_de_read(dev_priv, |
| 19069 | DSPADDR(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70184) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19070 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 19071 | error->plane[i].surface = intel_de_read(dev_priv, |
| 19072 | DSPSURF(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x7019C) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19073 | error->plane[i].tile_offset = intel_de_read(dev_priv, |
| 19074 | DSPTILEOFF(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x701A4) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19075 | } |
| 19076 | |
| 19077 | error->pipe[i].source = intel_de_read(dev_priv, PIPESRC(i)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(i)] - (&(dev_priv)->__info)->trans_offsets [TRANSCODER_A] + (0x6001c) + ((&(dev_priv)->__info)-> display_mmio_offset))) })); |
| 19078 | |
| 19079 | if (HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch)) |
| 19080 | error->pipe[i].stat = intel_de_read(dev_priv, |
| 19081 | PIPESTAT(i)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[i] - (&(dev_priv)->__info)->pipe_offsets [PIPE_A] + (0x70024) + ((&(dev_priv)->__info)->display_mmio_offset )) })); |
| 19082 | } |
| 19083 | |
| 19084 | for (i = 0; i < ARRAY_SIZE(error->transcoder)(sizeof((error->transcoder)) / sizeof((error->transcoder )[0])); i++) { |
| 19085 | enum transcoder cpu_transcoder = transcoders[i]; |
| 19086 | |
| 19087 | if (!HAS_TRANSCODER(dev_priv, cpu_transcoder)(((&(dev_priv)->__info)->cpu_transcoder_mask & ( 1UL << (cpu_transcoder))) != 0)) |
| 19088 | continue; |
| 19089 | |
| 19090 | error->transcoder[i].available = true1; |
| 19091 | error->transcoder[i].power_domain_on = |
| 19092 | __intel_display_power_is_enabled(dev_priv, |
| 19093 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A)); |
| 19094 | if (!error->transcoder[i].power_domain_on) |
| 19095 | continue; |
| 19096 | |
| 19097 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
| 19098 | |
| 19099 | error->transcoder[i].conf = intel_de_read(dev_priv, |
| 19100 | PIPECONF(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> pipe_offsets[cpu_transcoder] - (&(dev_priv)->__info)-> pipe_offsets[PIPE_A] + (0x70008) + ((&(dev_priv)->__info )->display_mmio_offset)) })); |
| 19101 | error->transcoder[i].htotal = intel_de_read(dev_priv, |
| 19102 | HTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60000) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 19103 | error->transcoder[i].hblank = intel_de_read(dev_priv, |
| 19104 | HBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60004) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 19105 | error->transcoder[i].hsync = intel_de_read(dev_priv, |
| 19106 | HSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60008) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 19107 | error->transcoder[i].vtotal = intel_de_read(dev_priv, |
| 19108 | VTOTAL(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x6000c) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 19109 | error->transcoder[i].vblank = intel_de_read(dev_priv, |
| 19110 | VBLANK(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60010) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 19111 | error->transcoder[i].vsync = intel_de_read(dev_priv, |
| 19112 | VSYNC(cpu_transcoder)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)-> trans_offsets[(cpu_transcoder)] - (&(dev_priv)->__info )->trans_offsets[TRANSCODER_A] + (0x60014) + ((&(dev_priv )->__info)->display_mmio_offset))) })); |
| 19113 | } |
| 19114 | |
| 19115 | return error; |
| 19116 | } |
| 19117 | |
| 19118 | #define err_printf(e, ...)i915_error_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
| 19119 | |
| 19120 | void |
| 19121 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
| 19122 | struct intel_display_error_state *error) |
| 19123 | { |
| 19124 | struct drm_i915_privateinteldrm_softc *dev_priv = m->i915; |
| 19125 | int i; |
| 19126 | |
| 19127 | if (!error) |
| 19128 | return; |
| 19129 | |
| 19130 | err_printf(m, "Num Pipes: %d\n", INTEL_NUM_PIPES(dev_priv))i915_error_printf(m, "Num Pipes: %d\n", (hweight8((&(dev_priv )->__info)->pipe_mask))); |
| 19131 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) || IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) |
| 19132 | err_printf(m, "PWR_WELL_CTL2: %08x\n",i915_error_printf(m, "PWR_WELL_CTL2: %08x\n", error->power_well_driver ) |
| 19133 | error->power_well_driver)i915_error_printf(m, "PWR_WELL_CTL2: %08x\n", error->power_well_driver ); |
| 19134 | for_each_pipe(dev_priv, i)for ((i) = 0; (i) < I915_MAX_PIPES; (i)++) if (!((&(dev_priv )->__info)->pipe_mask & (1UL << (i)))) {} else { |
| 19135 | err_printf(m, "Pipe [%d]:\n", i)i915_error_printf(m, "Pipe [%d]:\n", i); |
| 19136 | err_printf(m, " Power: %s\n",i915_error_printf(m, " Power: %s\n", onoff(error->pipe[i] .power_domain_on)) |
| 19137 | onoff(error->pipe[i].power_domain_on))i915_error_printf(m, " Power: %s\n", onoff(error->pipe[i] .power_domain_on)); |
| 19138 | err_printf(m, " SRC: %08x\n", error->pipe[i].source)i915_error_printf(m, " SRC: %08x\n", error->pipe[i].source ); |
| 19139 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat)i915_error_printf(m, " STAT: %08x\n", error->pipe[i].stat ); |
| 19140 | |
| 19141 | err_printf(m, "Plane [%d]:\n", i)i915_error_printf(m, "Plane [%d]:\n", i); |
| 19142 | err_printf(m, " CNTR: %08x\n", error->plane[i].control)i915_error_printf(m, " CNTR: %08x\n", error->plane[i].control ); |
| 19143 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride)i915_error_printf(m, " STRIDE: %08x\n", error->plane[i].stride ); |
| 19144 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) <= 3) { |
| 19145 | err_printf(m, " SIZE: %08x\n", error->plane[i].size)i915_error_printf(m, " SIZE: %08x\n", error->plane[i].size ); |
| 19146 | err_printf(m, " POS: %08x\n", error->plane[i].pos)i915_error_printf(m, " POS: %08x\n", error->plane[i].pos); |
| 19147 | } |
| 19148 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) <= 7 && !IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) |
| 19149 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr)i915_error_printf(m, " ADDR: %08x\n", error->plane[i].addr ); |
| 19150 | if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4) { |
| 19151 | err_printf(m, " SURF: %08x\n", error->plane[i].surface)i915_error_printf(m, " SURF: %08x\n", error->plane[i].surface ); |
| 19152 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset)i915_error_printf(m, " TILEOFF: %08x\n", error->plane[i]. tile_offset); |
| 19153 | } |
| 19154 | |
| 19155 | err_printf(m, "Cursor [%d]:\n", i)i915_error_printf(m, "Cursor [%d]:\n", i); |
| 19156 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control)i915_error_printf(m, " CNTR: %08x\n", error->cursor[i].control ); |
| 19157 | err_printf(m, " POS: %08x\n", error->cursor[i].position)i915_error_printf(m, " POS: %08x\n", error->cursor[i].position ); |
| 19158 | err_printf(m, " BASE: %08x\n", error->cursor[i].base)i915_error_printf(m, " BASE: %08x\n", error->cursor[i].base ); |
| 19159 | } |
| 19160 | |
| 19161 | for (i = 0; i < ARRAY_SIZE(error->transcoder)(sizeof((error->transcoder)) / sizeof((error->transcoder )[0])); i++) { |
| 19162 | if (!error->transcoder[i].available) |
| 19163 | continue; |
| 19164 | |
| 19165 | err_printf(m, "CPU transcoder: %s\n",i915_error_printf(m, "CPU transcoder: %s\n", transcoder_name( error->transcoder[i].cpu_transcoder)) |
| 19166 | transcoder_name(error->transcoder[i].cpu_transcoder))i915_error_printf(m, "CPU transcoder: %s\n", transcoder_name( error->transcoder[i].cpu_transcoder)); |
| 19167 | err_printf(m, " Power: %s\n",i915_error_printf(m, " Power: %s\n", onoff(error->transcoder [i].power_domain_on)) |
| 19168 | onoff(error->transcoder[i].power_domain_on))i915_error_printf(m, " Power: %s\n", onoff(error->transcoder [i].power_domain_on)); |
| 19169 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf)i915_error_printf(m, " CONF: %08x\n", error->transcoder[i ].conf); |
| 19170 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal)i915_error_printf(m, " HTOTAL: %08x\n", error->transcoder [i].htotal); |
| 19171 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank)i915_error_printf(m, " HBLANK: %08x\n", error->transcoder [i].hblank); |
| 19172 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync)i915_error_printf(m, " HSYNC: %08x\n", error->transcoder[ i].hsync); |
| 19173 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal)i915_error_printf(m, " VTOTAL: %08x\n", error->transcoder [i].vtotal); |
| 19174 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank)i915_error_printf(m, " VBLANK: %08x\n", error->transcoder [i].vblank); |
| 19175 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync)i915_error_printf(m, " VSYNC: %08x\n", error->transcoder[ i].vsync); |
| 19176 | } |
| 19177 | } |
| 19178 | |
| 19179 | #endif |