Bug Summary

File:dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
Warning:line 1773, column 13
Value stored to 'pptable' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name sienna_cichlid_ppt.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#define SWSMU_CODE_LAYER_L2
25
26#include <linux/firmware.h>
27#include <linux/pci.h>
28#include <linux/i2c.h>
29#include "amdgpu.h"
30#include "amdgpu_smu.h"
31#include "atomfirmware.h"
32#include "amdgpu_atomfirmware.h"
33#include "amdgpu_atombios.h"
34#include "smu_v11_0.h"
35#include "smu11_driver_if_sienna_cichlid.h"
36#include "soc15_common.h"
37#include "atom.h"
38#include "sienna_cichlid_ppt.h"
39#include "smu_v11_0_7_pptable.h"
40#include "smu_v11_0_7_ppsmc.h"
41#include "nbio/nbio_2_3_offset.h"
42#include "nbio/nbio_2_3_sh_mask.h"
43#include "thm/thm_11_0_2_offset.h"
44#include "thm/thm_11_0_2_sh_mask.h"
45#include "mp/mp_11_0_offset.h"
46#include "mp/mp_11_0_sh_mask.h"
47
48#include "asic_reg/mp/mp_11_0_sh_mask.h"
49#include "smu_cmn.h"
50
51/*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56#undef pr_err
57#undef pr_warn
58#undef pr_info
59#undef pr_debug
60
61#define to_amdgpu_device(x)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (x); (struct amdgpu_device *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_device, pm.smu_i2c) );}))
(container_of(x, struct amdgpu_device, pm.smu_i2c)({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (x); (struct amdgpu_device *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_device, pm.smu_i2c) );})
)
62
63#define FEATURE_MASK(feature)(1ULL << feature) (1ULL << feature)
64#define SMC_DPM_FEATURE( (1ULL << 0) | (1ULL << 1) | (1ULL << 3) |
(1ULL << 7) | (1ULL << 5) | (1ULL << 4) | (
1ULL << 8) | (1ULL << 6))
( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)(1ULL << 0) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)(1ULL << 1) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT)(1ULL << 3) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT)(1ULL << 7) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)(1ULL << 5) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT)(1ULL << 4) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)(1ULL << 8) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)(1ULL << 6))
73
74#define SMU_11_0_7_GFX_BUSY_THRESHOLD15 15
75
76static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
77 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1)[SMU_MSG_TestMessage] = {1, (0x1), (1)},
78 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1)[SMU_MSG_GetSmuVersion] = {1, (0x2), (1)},
79 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1)[SMU_MSG_GetDriverIfVersion] = {1, (0x3), (1)},
80 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0)[SMU_MSG_SetAllowedFeaturesMaskLow] = {1, (0x4), (0)},
81 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0)[SMU_MSG_SetAllowedFeaturesMaskHigh] = {1, (0x5), (0)},
82 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0)[SMU_MSG_EnableAllSmuFeatures] = {1, (0x6), (0)},
83 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0)[SMU_MSG_DisableAllSmuFeatures] = {1, (0x7), (0)},
84 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1)[SMU_MSG_EnableSmuFeaturesLow] = {1, (0x8), (1)},
85 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1)[SMU_MSG_EnableSmuFeaturesHigh] = {1, (0x9), (1)},
86 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1)[SMU_MSG_DisableSmuFeaturesLow] = {1, (0xA), (1)},
87 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1)[SMU_MSG_DisableSmuFeaturesHigh] = {1, (0xB), (1)},
88 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1)[SMU_MSG_GetEnabledSmuFeaturesLow] = {1, (0xC), (1)},
89 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1)[SMU_MSG_GetEnabledSmuFeaturesHigh] = {1, (0xD), (1)},
90 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1)[SMU_MSG_SetWorkloadMask] = {1, (0x22), (1)},
91 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0)[SMU_MSG_SetPptLimit] = {1, (0x32), (0)},
92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0)[SMU_MSG_SetDriverDramAddrHigh] = {1, (0xE), (0)},
93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0)[SMU_MSG_SetDriverDramAddrLow] = {1, (0xF), (0)},
94 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0)[SMU_MSG_SetToolsDramAddrHigh] = {1, (0x10), (0)},
95 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0)[SMU_MSG_SetToolsDramAddrLow] = {1, (0x11), (0)},
96 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0)[SMU_MSG_TransferTableSmu2Dram] = {1, (0x12), (0)},
97 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0)[SMU_MSG_TransferTableDram2Smu] = {1, (0x13), (0)},
98 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0)[SMU_MSG_UseDefaultPPTable] = {1, (0x14), (0)},
99 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0)[SMU_MSG_RunDcBtc] = {1, (0x36), (0)},
100 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0)[SMU_MSG_EnterBaco] = {1, (0x15), (0)},
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0)[SMU_MSG_SetSoftMinByFreq] = {1, (0x19), (0)},
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0)[SMU_MSG_SetSoftMaxByFreq] = {1, (0x1A), (0)},
103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1)[SMU_MSG_SetHardMinByFreq] = {1, (0x1B), (1)},
104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0)[SMU_MSG_SetHardMaxByFreq] = {1, (0x1C), (0)},
105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1)[SMU_MSG_GetMinDpmFreq] = {1, (0x1D), (1)},
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1)[SMU_MSG_GetMaxDpmFreq] = {1, (0x1E), (1)},
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1)[SMU_MSG_GetDpmFreqByIndex] = {1, (0x1F), (1)},
108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0)[SMU_MSG_SetGeminiMode] = {1, (0x3B), (0)},
109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0)[SMU_MSG_SetGeminiApertureHigh] = {1, (0x3C), (0)},
110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0)[SMU_MSG_SetGeminiApertureLow] = {1, (0x3D), (0)},
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0)[SMU_MSG_OverridePcieParameters] = {1, (0x20), (0)},
112 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0)[SMU_MSG_ReenableAcDcInterrupt] = {1, (0x34), (0)},
113 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0)[SMU_MSG_NotifyPowerSource] = {1, (0x35), (0)},
114 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0)[SMU_MSG_SetUclkFastSwitch] = {1, (0x23), (0)},
115 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0)[SMU_MSG_SetVideoFps] = {1, (0x25), (0)},
116 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1)[SMU_MSG_PrepareMp1ForUnload] = {1, (0x2E), (1)},
117 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0)[SMU_MSG_AllowGfxOff] = {1, (0x28), (0)},
118 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0)[SMU_MSG_DisallowGfxOff] = {1, (0x29), (0)},
119 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0)[SMU_MSG_GetPptLimit] = {1, (0x33), (0)},
120 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1)[SMU_MSG_GetDcModeMaxDpmFreq] = {1, (0x26), (1)},
121 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0)[SMU_MSG_ExitBaco] = {1, (0x16), (0)},
122 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0)[SMU_MSG_PowerUpVcn] = {1, (0x2A), (0)},
123 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0)[SMU_MSG_PowerDownVcn] = {1, (0x2B), (0)},
124 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0)[SMU_MSG_PowerUpJpeg] = {1, (0x2C), (0)},
125 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0)[SMU_MSG_PowerDownJpeg] = {1, (0x2D), (0)},
126 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0)[SMU_MSG_BacoAudioD3PME] = {1, (0x18), (0)},
127 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0)[SMU_MSG_ArmD3] = {1, (0x17), (0)},
128 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0)[SMU_MSG_Mode1Reset] = {1, (0x30), (0)},
129 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0)[SMU_MSG_SetMGpuFanBoostLimitRpm] = {1, (0x43), (0)},
130};
131
132static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
133 CLK_MAP(GFXCLK, PPCLK_GFXCLK)[SMU_GFXCLK] = {1, (PPCLK_GFXCLK)},
134 CLK_MAP(SCLK, PPCLK_GFXCLK)[SMU_SCLK] = {1, (PPCLK_GFXCLK)},
135 CLK_MAP(SOCCLK, PPCLK_SOCCLK)[SMU_SOCCLK] = {1, (PPCLK_SOCCLK)},
136 CLK_MAP(FCLK, PPCLK_FCLK)[SMU_FCLK] = {1, (PPCLK_FCLK)},
137 CLK_MAP(UCLK, PPCLK_UCLK)[SMU_UCLK] = {1, (PPCLK_UCLK)},
138 CLK_MAP(MCLK, PPCLK_UCLK)[SMU_MCLK] = {1, (PPCLK_UCLK)},
139 CLK_MAP(DCLK, PPCLK_DCLK_0)[SMU_DCLK] = {1, (PPCLK_DCLK_0)},
140 CLK_MAP(DCLK1, PPCLK_DCLK_1)[SMU_DCLK1] = {1, (PPCLK_DCLK_1)},
141 CLK_MAP(VCLK, PPCLK_VCLK_0)[SMU_VCLK] = {1, (PPCLK_VCLK_0)},
142 CLK_MAP(VCLK1, PPCLK_VCLK_1)[SMU_VCLK1] = {1, (PPCLK_VCLK_1)},
143 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK)[SMU_DCEFCLK] = {1, (PPCLK_DCEFCLK)},
144 CLK_MAP(DISPCLK, PPCLK_DISPCLK)[SMU_DISPCLK] = {1, (PPCLK_DISPCLK)},
145 CLK_MAP(PIXCLK, PPCLK_PIXCLK)[SMU_PIXCLK] = {1, (PPCLK_PIXCLK)},
146 CLK_MAP(PHYCLK, PPCLK_PHYCLK)[SMU_PHYCLK] = {1, (PPCLK_PHYCLK)},
147};
148
149static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
150 FEA_MAP(DPM_PREFETCHER)[SMU_FEATURE_DPM_PREFETCHER_BIT] = {1, 0},
151 FEA_MAP(DPM_GFXCLK)[SMU_FEATURE_DPM_GFXCLK_BIT] = {1, 1},
152 FEA_MAP(DPM_GFX_GPO)[SMU_FEATURE_DPM_GFX_GPO_BIT] = {1, 2},
153 FEA_MAP(DPM_UCLK)[SMU_FEATURE_DPM_UCLK_BIT] = {1, 3},
154 FEA_MAP(DPM_FCLK)[SMU_FEATURE_DPM_FCLK_BIT] = {1, 4},
155 FEA_MAP(DPM_SOCCLK)[SMU_FEATURE_DPM_SOCCLK_BIT] = {1, 5},
156 FEA_MAP(DPM_MP0CLK)[SMU_FEATURE_DPM_MP0CLK_BIT] = {1, 6},
157 FEA_MAP(DPM_LINK)[SMU_FEATURE_DPM_LINK_BIT] = {1, 7},
158 FEA_MAP(DPM_DCEFCLK)[SMU_FEATURE_DPM_DCEFCLK_BIT] = {1, 8},
159 FEA_MAP(DPM_XGMI)[SMU_FEATURE_DPM_XGMI_BIT] = {1, 9},
160 FEA_MAP(MEM_VDDCI_SCALING)[SMU_FEATURE_MEM_VDDCI_SCALING_BIT] = {1, 10},
161 FEA_MAP(MEM_MVDD_SCALING)[SMU_FEATURE_MEM_MVDD_SCALING_BIT] = {1, 11},
162 FEA_MAP(DS_GFXCLK)[SMU_FEATURE_DS_GFXCLK_BIT] = {1, 12},
163 FEA_MAP(DS_SOCCLK)[SMU_FEATURE_DS_SOCCLK_BIT] = {1, 13},
164 FEA_MAP(DS_FCLK)[SMU_FEATURE_DS_FCLK_BIT] = {1, 14},
165 FEA_MAP(DS_LCLK)[SMU_FEATURE_DS_LCLK_BIT] = {1, 15},
166 FEA_MAP(DS_DCEFCLK)[SMU_FEATURE_DS_DCEFCLK_BIT] = {1, 16},
167 FEA_MAP(DS_UCLK)[SMU_FEATURE_DS_UCLK_BIT] = {1, 17},
168 FEA_MAP(GFX_ULV)[SMU_FEATURE_GFX_ULV_BIT] = {1, 18},
169 FEA_MAP(FW_DSTATE)[SMU_FEATURE_FW_DSTATE_BIT] = {1, 19},
170 FEA_MAP(GFXOFF)[SMU_FEATURE_GFXOFF_BIT] = {1, 20},
171 FEA_MAP(BACO)[SMU_FEATURE_BACO_BIT] = {1, 21},
172 FEA_MAP(MM_DPM_PG)[SMU_FEATURE_MM_DPM_PG_BIT] = {1, 22},
173 FEA_MAP(RSMU_SMN_CG)[SMU_FEATURE_RSMU_SMN_CG_BIT] = {1, 44},
174 FEA_MAP(PPT)[SMU_FEATURE_PPT_BIT] = {1, 24},
175 FEA_MAP(TDC)[SMU_FEATURE_TDC_BIT] = {1, 25},
176 FEA_MAP(APCC_PLUS)[SMU_FEATURE_APCC_PLUS_BIT] = {1, 26},
177 FEA_MAP(GTHR)[SMU_FEATURE_GTHR_BIT] = {1, 27},
178 FEA_MAP(ACDC)[SMU_FEATURE_ACDC_BIT] = {1, 28},
179 FEA_MAP(VR0HOT)[SMU_FEATURE_VR0HOT_BIT] = {1, 29},
180 FEA_MAP(VR1HOT)[SMU_FEATURE_VR1HOT_BIT] = {1, 30},
181 FEA_MAP(FW_CTF)[SMU_FEATURE_FW_CTF_BIT] = {1, 31},
182 FEA_MAP(FAN_CONTROL)[SMU_FEATURE_FAN_CONTROL_BIT] = {1, 32},
183 FEA_MAP(THERMAL)[SMU_FEATURE_THERMAL_BIT] = {1, 33},
184 FEA_MAP(GFX_DCS)[SMU_FEATURE_GFX_DCS_BIT] = {1, 34},
185 FEA_MAP(RM)[SMU_FEATURE_RM_BIT] = {1, 35},
186 FEA_MAP(LED_DISPLAY)[SMU_FEATURE_LED_DISPLAY_BIT] = {1, 36},
187 FEA_MAP(GFX_SS)[SMU_FEATURE_GFX_SS_BIT] = {1, 37},
188 FEA_MAP(OUT_OF_BAND_MONITOR)[SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT] = {1, 38},
189 FEA_MAP(TEMP_DEPENDENT_VMIN)[SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT] = {1, 39},
190 FEA_MAP(MMHUB_PG)[SMU_FEATURE_MMHUB_PG_BIT] = {1, 40},
191 FEA_MAP(ATHUB_PG)[SMU_FEATURE_ATHUB_PG_BIT] = {1, 41},
192 FEA_MAP(APCC_DFLL)[SMU_FEATURE_APCC_DFLL_BIT] = {1, 42},
193};
194
195static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
196 TAB_MAP(PPTABLE)[SMU_TABLE_PPTABLE] = {1, 0},
197 TAB_MAP(WATERMARKS)[SMU_TABLE_WATERMARKS] = {1, 1},
198 TAB_MAP(AVFS_PSM_DEBUG)[SMU_TABLE_AVFS_PSM_DEBUG] = {1, 2},
199 TAB_MAP(AVFS_FUSE_OVERRIDE)[SMU_TABLE_AVFS_FUSE_OVERRIDE] = {1, 3},
200 TAB_MAP(PMSTATUSLOG)[SMU_TABLE_PMSTATUSLOG] = {1, 4},
201 TAB_MAP(SMU_METRICS)[SMU_TABLE_SMU_METRICS] = {1, 5},
202 TAB_MAP(DRIVER_SMU_CONFIG)[SMU_TABLE_DRIVER_SMU_CONFIG] = {1, 6},
203 TAB_MAP(ACTIVITY_MONITOR_COEFF)[SMU_TABLE_ACTIVITY_MONITOR_COEFF] = {1, 7},
204 TAB_MAP(OVERDRIVE)[SMU_TABLE_OVERDRIVE] = {1, 8},
205 TAB_MAP(I2C_COMMANDS)[SMU_TABLE_I2C_COMMANDS] = {1, 9},
206 TAB_MAP(PACE)[SMU_TABLE_PACE] = {1, 10},
207};
208
209static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
210 PWR_MAP(AC)[SMU_POWER_SOURCE_AC] = {1, POWER_SOURCE_AC},
211 PWR_MAP(DC)[SMU_POWER_SOURCE_DC] = {1, POWER_SOURCE_DC},
212};
213
214static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT)[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = {1, (0)},
216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT)[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = {1, (1)},
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT)[PP_SMC_POWER_PROFILE_POWERSAVING] = {1, (2)},
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT)[PP_SMC_POWER_PROFILE_VIDEO] = {1, (3)},
219 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT)[PP_SMC_POWER_PROFILE_VR] = {1, (4)},
220 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT)[PP_SMC_POWER_PROFILE_COMPUTE] = {1, (5)},
221 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT)[PP_SMC_POWER_PROFILE_CUSTOM] = {1, (6)},
222};
223
224static int
225sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
226 uint32_t *feature_mask, uint32_t num)
227{
228 struct amdgpu_device *adev = smu->adev;
229
230 if (num > 2)
231 return -EINVAL22;
232
233 memset(feature_mask, 0, sizeof(uint32_t) * num)__builtin_memset((feature_mask), (0), (sizeof(uint32_t) * num
))
;
234
235 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)(1ULL << 0)
236 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)(1ULL << 4)
237 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)(1ULL << 6)
238 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)(1ULL << 13)
239 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)(1ULL << 16)
240 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)(1ULL << 14)
241 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)(1ULL << 17)
242 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)(1ULL << 19)
243 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)(1ULL << 45)
244 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)(1ULL << 44)
245 | FEATURE_MASK(FEATURE_GFX_SS_BIT)(1ULL << 37)
246 | FEATURE_MASK(FEATURE_VR0HOT_BIT)(1ULL << 29)
247 | FEATURE_MASK(FEATURE_PPT_BIT)(1ULL << 24)
248 | FEATURE_MASK(FEATURE_TDC_BIT)(1ULL << 25)
249 | FEATURE_MASK(FEATURE_BACO_BIT)(1ULL << 21)
250 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)(1ULL << 42)
251 | FEATURE_MASK(FEATURE_FW_CTF_BIT)(1ULL << 31)
252 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)(1ULL << 32)
253 | FEATURE_MASK(FEATURE_THERMAL_BIT)(1ULL << 33)
254 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)(1ULL << 38);
255
256 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
257 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)(1ULL << 1);
258 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT)(1ULL << 2);
259 }
260
261 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
262 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)(1ULL << 3)
263 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)(1ULL << 10)
264 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)(1ULL << 11);
265
266 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT)(1ULL << 7);
268
269 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)(1ULL << 8);
271
272 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)(1ULL << 5);
274
275 if (adev->pm.pp_feature & PP_ULV_MASK)
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT)(1ULL << 18);
277
278 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)(1ULL << 12);
280
281 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT)(1ULL << 20);
283
284 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB(1 << 16))
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT)(1ULL << 41);
286
287 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB(1 << 13))
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT)(1ULL << 40);
289
290 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN(1 << 14) ||
291 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG(1 << 17))
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT)(1ULL << 22);
293
294 return 0;
295}
296
297static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
298{
299 struct smu_table_context *table_context = &smu->smu_table;
300 struct smu_11_0_7_powerplay_table *powerplay_table =
301 table_context->power_play_table;
302 struct smu_baco_context *smu_baco = &smu->smu_baco;
303
304 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO0x8 ||
305 powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO0x10)
306 smu_baco->platform_support = true1;
307
308 table_context->thermal_controller_type =
309 powerplay_table->thermal_controller_type;
310
311 return 0;
312}
313
314static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
315{
316 struct smu_table_context *table_context = &smu->smu_table;
317 PPTable_t *smc_pptable = table_context->driver_pptable;
318 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
319 int index, ret;
320
321 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1
, smc_dpm_info) / sizeof(uint16_t))
322 smc_dpm_info)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1
, smc_dpm_info) / sizeof(uint16_t))
;
323
324 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL((void *)0), NULL((void *)0), NULL((void *)0),
325 (uint8_t **)&smc_dpm_table);
326 if (ret)
327 return ret;
328
329 memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,__builtin_memcpy((smc_pptable->I2cControllers), (smc_dpm_table
->I2cControllers), (sizeof(*smc_dpm_table) - sizeof(smc_dpm_table
->table_header)))
330 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header))__builtin_memcpy((smc_pptable->I2cControllers), (smc_dpm_table
->I2cControllers), (sizeof(*smc_dpm_table) - sizeof(smc_dpm_table
->table_header)))
;
331
332 return 0;
333}
334
335static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
336{
337 struct smu_table_context *table_context = &smu->smu_table;
338 struct smu_11_0_7_powerplay_table *powerplay_table =
339 table_context->power_play_table;
340
341 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,__builtin_memcpy((table_context->driver_pptable), (&powerplay_table
->smc_pptable), (sizeof(PPTable_t)))
342 sizeof(PPTable_t))__builtin_memcpy((table_context->driver_pptable), (&powerplay_table
->smc_pptable), (sizeof(PPTable_t)))
;
343
344 return 0;
345}
346
347static int sienna_cichlid_setup_pptable(struct smu_context *smu)
348{
349 int ret = 0;
350
351 ret = smu_v11_0_setup_pptable(smu);
352 if (ret)
353 return ret;
354
355 ret = sienna_cichlid_store_powerplay_table(smu);
356 if (ret)
357 return ret;
358
359 ret = sienna_cichlid_append_powerplay_table(smu);
360 if (ret)
361 return ret;
362
363 ret = sienna_cichlid_check_powerplay_table(smu);
364 if (ret)
365 return ret;
366
367 return ret;
368}
369
370static int sienna_cichlid_tables_init(struct smu_context *smu)
371{
372 struct smu_table_context *smu_table = &smu->smu_table;
373 struct smu_table *tables = smu_table->tables;
374
375 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),do { tables[SMU_TABLE_PPTABLE].size = sizeof(PPTable_t); tables
[SMU_TABLE_PPTABLE].align = (1 << 12); tables[SMU_TABLE_PPTABLE
].domain = 0x4; } while (0)
376 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_PPTABLE].size = sizeof(PPTable_t); tables
[SMU_TABLE_PPTABLE].align = (1 << 12); tables[SMU_TABLE_PPTABLE
].domain = 0x4; } while (0)
;
377 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),do { tables[SMU_TABLE_WATERMARKS].size = sizeof(Watermarks_t)
; tables[SMU_TABLE_WATERMARKS].align = (1 << 12); tables
[SMU_TABLE_WATERMARKS].domain = 0x4; } while (0)
378 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_WATERMARKS].size = sizeof(Watermarks_t)
; tables[SMU_TABLE_WATERMARKS].align = (1 << 12); tables
[SMU_TABLE_WATERMARKS].domain = 0x4; } while (0)
;
379 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t
); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables
[SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0)
380 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t
); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables
[SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0)
;
381 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),do { tables[SMU_TABLE_I2C_COMMANDS].size = sizeof(SwI2cRequest_t
); tables[SMU_TABLE_I2C_COMMANDS].align = (1 << 12); tables
[SMU_TABLE_I2C_COMMANDS].domain = 0x4; } while (0)
382 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_I2C_COMMANDS].size = sizeof(SwI2cRequest_t
); tables[SMU_TABLE_I2C_COMMANDS].align = (1 << 12); tables
[SMU_TABLE_I2C_COMMANDS].domain = 0x4; } while (0)
;
383 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),do { tables[SMU_TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t
); tables[SMU_TABLE_OVERDRIVE].align = (1 << 12); tables
[SMU_TABLE_OVERDRIVE].domain = 0x4; } while (0)
384 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_OVERDRIVE].size = sizeof(OverDriveTable_t
); tables[SMU_TABLE_OVERDRIVE].align = (1 << 12); tables
[SMU_TABLE_OVERDRIVE].domain = 0x4; } while (0)
;
385 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,do { tables[SMU_TABLE_PMSTATUSLOG].size = 0x19000; tables[SMU_TABLE_PMSTATUSLOG
].align = (1 << 12); tables[SMU_TABLE_PMSTATUSLOG].domain
= 0x4; } while (0)
386 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_PMSTATUSLOG].size = 0x19000; tables[SMU_TABLE_PMSTATUSLOG
].align = (1 << 12); tables[SMU_TABLE_PMSTATUSLOG].domain
= 0x4; } while (0)
;
387 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t
); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 <<
12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; }
while (0)
388 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t
); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 <<
12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; }
while (0)
389 AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t
); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 <<
12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; }
while (0)
;
390
391 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL(0x0001 | 0x0004));
392 if (!smu_table->metrics_table)
393 goto err0_out;
394 smu_table->metrics_time = 0;
395
396 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
397 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL(0x0001 | 0x0004));
398 if (!smu_table->gpu_metrics_table)
399 goto err1_out;
400
401 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL(0x0001 | 0x0004));
402 if (!smu_table->watermarks_table)
403 goto err2_out;
404
405 return 0;
406
407err2_out:
408 kfree(smu_table->gpu_metrics_table);
409err1_out:
410 kfree(smu_table->metrics_table);
411err0_out:
412 return -ENOMEM12;
413}
414
415static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
416 MetricsMember_t member,
417 uint32_t *value)
418{
419 struct smu_table_context *smu_table= &smu->smu_table;
420 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
421 int ret = 0;
422
423 mutex_lock(&smu->metrics_lock)rw_enter_write(&smu->metrics_lock);
424
425 ret = smu_cmn_get_metrics_table_locked(smu,
426 NULL((void *)0),
427 false0);
428 if (ret) {
429 mutex_unlock(&smu->metrics_lock)rw_exit_write(&smu->metrics_lock);
430 return ret;
431 }
432
433 switch (member) {
434 case METRICS_CURR_GFXCLK:
435 *value = metrics->CurrClock[PPCLK_GFXCLK];
436 break;
437 case METRICS_CURR_SOCCLK:
438 *value = metrics->CurrClock[PPCLK_SOCCLK];
439 break;
440 case METRICS_CURR_UCLK:
441 *value = metrics->CurrClock[PPCLK_UCLK];
442 break;
443 case METRICS_CURR_VCLK:
444 *value = metrics->CurrClock[PPCLK_VCLK_0];
445 break;
446 case METRICS_CURR_VCLK1:
447 *value = metrics->CurrClock[PPCLK_VCLK_1];
448 break;
449 case METRICS_CURR_DCLK:
450 *value = metrics->CurrClock[PPCLK_DCLK_0];
451 break;
452 case METRICS_CURR_DCLK1:
453 *value = metrics->CurrClock[PPCLK_DCLK_1];
454 break;
455 case METRICS_CURR_DCEFCLK:
456 *value = metrics->CurrClock[PPCLK_DCEFCLK];
457 break;
458 case METRICS_CURR_FCLK:
459 *value = metrics->CurrClock[PPCLK_FCLK];
460 break;
461 case METRICS_AVERAGE_GFXCLK:
462 if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD15)
463 *value = metrics->AverageGfxclkFrequencyPostDs;
464 else
465 *value = metrics->AverageGfxclkFrequencyPreDs;
466 break;
467 case METRICS_AVERAGE_FCLK:
468 *value = metrics->AverageFclkFrequencyPostDs;
469 break;
470 case METRICS_AVERAGE_UCLK:
471 *value = metrics->AverageUclkFrequencyPostDs;
472 break;
473 case METRICS_AVERAGE_GFXACTIVITY:
474 *value = metrics->AverageGfxActivity;
475 break;
476 case METRICS_AVERAGE_MEMACTIVITY:
477 *value = metrics->AverageUclkActivity;
478 break;
479 case METRICS_AVERAGE_SOCKETPOWER:
480 *value = metrics->AverageSocketPower << 8;
481 break;
482 case METRICS_TEMPERATURE_EDGE:
483 *value = metrics->TemperatureEdge *
484 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
485 break;
486 case METRICS_TEMPERATURE_HOTSPOT:
487 *value = metrics->TemperatureHotspot *
488 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
489 break;
490 case METRICS_TEMPERATURE_MEM:
491 *value = metrics->TemperatureMem *
492 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
493 break;
494 case METRICS_TEMPERATURE_VRGFX:
495 *value = metrics->TemperatureVrGfx *
496 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
497 break;
498 case METRICS_TEMPERATURE_VRSOC:
499 *value = metrics->TemperatureVrSoc *
500 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
501 break;
502 case METRICS_THROTTLER_STATUS:
503 *value = metrics->ThrottlerStatus;
504 break;
505 case METRICS_CURR_FANSPEED:
506 *value = metrics->CurrFanSpeed;
507 break;
508 default:
509 *value = UINT_MAX0xffffffffU;
510 break;
511 }
512
513 mutex_unlock(&smu->metrics_lock)rw_exit_write(&smu->metrics_lock);
514
515 return ret;
516
517}
518
519static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
520{
521 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
522
523 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
524 GFP_KERNEL(0x0001 | 0x0004));
525 if (!smu_dpm->dpm_context)
526 return -ENOMEM12;
527
528 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
529
530 return 0;
531}
532
533static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
534{
535 int ret = 0;
536
537 ret = sienna_cichlid_tables_init(smu);
538 if (ret)
539 return ret;
540
541 ret = sienna_cichlid_allocate_dpm_context(smu);
542 if (ret)
543 return ret;
544
545 return smu_v11_0_init_smc_tables(smu);
546}
547
548static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
549{
550 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
551 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
552 struct smu_11_0_dpm_table *dpm_table;
553 struct amdgpu_device *adev = smu->adev;
554 int ret = 0;
555
556 /* socclk dpm table setup */
557 dpm_table = &dpm_context->dpm_tables.soc_table;
558 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
559 ret = smu_v11_0_set_single_dpm_table(smu,
560 SMU_SOCCLK,
561 dpm_table);
562 if (ret)
563 return ret;
564 dpm_table->is_fine_grained =
565 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
566 } else {
567 dpm_table->count = 1;
568 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
569 dpm_table->dpm_levels[0].enabled = true1;
570 dpm_table->min = dpm_table->dpm_levels[0].value;
571 dpm_table->max = dpm_table->dpm_levels[0].value;
572 }
573
574 /* gfxclk dpm table setup */
575 dpm_table = &dpm_context->dpm_tables.gfx_table;
576 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
577 ret = smu_v11_0_set_single_dpm_table(smu,
578 SMU_GFXCLK,
579 dpm_table);
580 if (ret)
581 return ret;
582 dpm_table->is_fine_grained =
583 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
584 } else {
585 dpm_table->count = 1;
586 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
587 dpm_table->dpm_levels[0].enabled = true1;
588 dpm_table->min = dpm_table->dpm_levels[0].value;
589 dpm_table->max = dpm_table->dpm_levels[0].value;
590 }
591
592 /* uclk dpm table setup */
593 dpm_table = &dpm_context->dpm_tables.uclk_table;
594 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
595 ret = smu_v11_0_set_single_dpm_table(smu,
596 SMU_UCLK,
597 dpm_table);
598 if (ret)
599 return ret;
600 dpm_table->is_fine_grained =
601 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
602 } else {
603 dpm_table->count = 1;
604 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
605 dpm_table->dpm_levels[0].enabled = true1;
606 dpm_table->min = dpm_table->dpm_levels[0].value;
607 dpm_table->max = dpm_table->dpm_levels[0].value;
608 }
609
610 /* fclk dpm table setup */
611 dpm_table = &dpm_context->dpm_tables.fclk_table;
612 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
613 ret = smu_v11_0_set_single_dpm_table(smu,
614 SMU_FCLK,
615 dpm_table);
616 if (ret)
617 return ret;
618 dpm_table->is_fine_grained =
619 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
620 } else {
621 dpm_table->count = 1;
622 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
623 dpm_table->dpm_levels[0].enabled = true1;
624 dpm_table->min = dpm_table->dpm_levels[0].value;
625 dpm_table->max = dpm_table->dpm_levels[0].value;
626 }
627
628 /* vclk0 dpm table setup */
629 dpm_table = &dpm_context->dpm_tables.vclk_table;
630 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
631 ret = smu_v11_0_set_single_dpm_table(smu,
632 SMU_VCLK,
633 dpm_table);
634 if (ret)
635 return ret;
636 dpm_table->is_fine_grained =
637 !driver_ppt->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete;
638 } else {
639 dpm_table->count = 1;
640 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
641 dpm_table->dpm_levels[0].enabled = true1;
642 dpm_table->min = dpm_table->dpm_levels[0].value;
643 dpm_table->max = dpm_table->dpm_levels[0].value;
644 }
645
646 /* vclk1 dpm table setup */
647 if (adev->vcn.num_vcn_inst > 1) {
648 dpm_table = &dpm_context->dpm_tables.vclk1_table;
649 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
650 ret = smu_v11_0_set_single_dpm_table(smu,
651 SMU_VCLK1,
652 dpm_table);
653 if (ret)
654 return ret;
655 dpm_table->is_fine_grained =
656 !driver_ppt->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete;
657 } else {
658 dpm_table->count = 1;
659 dpm_table->dpm_levels[0].value =
660 smu->smu_table.boot_values.vclk / 100;
661 dpm_table->dpm_levels[0].enabled = true1;
662 dpm_table->min = dpm_table->dpm_levels[0].value;
663 dpm_table->max = dpm_table->dpm_levels[0].value;
664 }
665 }
666
667 /* dclk0 dpm table setup */
668 dpm_table = &dpm_context->dpm_tables.dclk_table;
669 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
670 ret = smu_v11_0_set_single_dpm_table(smu,
671 SMU_DCLK,
672 dpm_table);
673 if (ret)
674 return ret;
675 dpm_table->is_fine_grained =
676 !driver_ppt->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete;
677 } else {
678 dpm_table->count = 1;
679 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
680 dpm_table->dpm_levels[0].enabled = true1;
681 dpm_table->min = dpm_table->dpm_levels[0].value;
682 dpm_table->max = dpm_table->dpm_levels[0].value;
683 }
684
685 /* dclk1 dpm table setup */
686 if (adev->vcn.num_vcn_inst > 1) {
687 dpm_table = &dpm_context->dpm_tables.dclk1_table;
688 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
689 ret = smu_v11_0_set_single_dpm_table(smu,
690 SMU_DCLK1,
691 dpm_table);
692 if (ret)
693 return ret;
694 dpm_table->is_fine_grained =
695 !driver_ppt->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete;
696 } else {
697 dpm_table->count = 1;
698 dpm_table->dpm_levels[0].value =
699 smu->smu_table.boot_values.dclk / 100;
700 dpm_table->dpm_levels[0].enabled = true1;
701 dpm_table->min = dpm_table->dpm_levels[0].value;
702 dpm_table->max = dpm_table->dpm_levels[0].value;
703 }
704 }
705
706 /* dcefclk dpm table setup */
707 dpm_table = &dpm_context->dpm_tables.dcef_table;
708 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
709 ret = smu_v11_0_set_single_dpm_table(smu,
710 SMU_DCEFCLK,
711 dpm_table);
712 if (ret)
713 return ret;
714 dpm_table->is_fine_grained =
715 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
716 } else {
717 dpm_table->count = 1;
718 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
719 dpm_table->dpm_levels[0].enabled = true1;
720 dpm_table->min = dpm_table->dpm_levels[0].value;
721 dpm_table->max = dpm_table->dpm_levels[0].value;
722 }
723
724 /* pixelclk dpm table setup */
725 dpm_table = &dpm_context->dpm_tables.pixel_table;
726 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
727 ret = smu_v11_0_set_single_dpm_table(smu,
728 SMU_PIXCLK,
729 dpm_table);
730 if (ret)
731 return ret;
732 dpm_table->is_fine_grained =
733 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
734 } else {
735 dpm_table->count = 1;
736 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
737 dpm_table->dpm_levels[0].enabled = true1;
738 dpm_table->min = dpm_table->dpm_levels[0].value;
739 dpm_table->max = dpm_table->dpm_levels[0].value;
740 }
741
742 /* displayclk dpm table setup */
743 dpm_table = &dpm_context->dpm_tables.display_table;
744 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
745 ret = smu_v11_0_set_single_dpm_table(smu,
746 SMU_DISPCLK,
747 dpm_table);
748 if (ret)
749 return ret;
750 dpm_table->is_fine_grained =
751 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
752 } else {
753 dpm_table->count = 1;
754 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
755 dpm_table->dpm_levels[0].enabled = true1;
756 dpm_table->min = dpm_table->dpm_levels[0].value;
757 dpm_table->max = dpm_table->dpm_levels[0].value;
758 }
759
760 /* phyclk dpm table setup */
761 dpm_table = &dpm_context->dpm_tables.phy_table;
762 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
763 ret = smu_v11_0_set_single_dpm_table(smu,
764 SMU_PHYCLK,
765 dpm_table);
766 if (ret)
767 return ret;
768 dpm_table->is_fine_grained =
769 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
770 } else {
771 dpm_table->count = 1;
772 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
773 dpm_table->dpm_levels[0].enabled = true1;
774 dpm_table->min = dpm_table->dpm_levels[0].value;
775 dpm_table->max = dpm_table->dpm_levels[0].value;
776 }
777
778 return 0;
779}
780
781static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool_Bool enable)
782{
783 struct amdgpu_device *adev = smu->adev;
784 int ret = 0;
785
786 if (enable) {
787 /* vcn dpm on is a prerequisite for vcn power gate messages */
788 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
789 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL((void *)0));
790 if (ret)
791 return ret;
792 if (adev->vcn.num_vcn_inst > 1) {
793 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
794 0x10000, NULL((void *)0));
795 if (ret)
796 return ret;
797 }
798 }
799 } else {
800 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
801 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL((void *)0));
802 if (ret)
803 return ret;
804 if (adev->vcn.num_vcn_inst > 1) {
805 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
806 0x10000, NULL((void *)0));
807 if (ret)
808 return ret;
809 }
810 }
811 }
812
813 return ret;
814}
815
816static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool_Bool enable)
817{
818 int ret = 0;
819
820 if (enable) {
821 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
822 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL((void *)0));
823 if (ret)
824 return ret;
825 }
826 } else {
827 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
828 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL((void *)0));
829 if (ret)
830 return ret;
831 }
832 }
833
834 return ret;
835}
836
837static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
838 enum smu_clk_type clk_type,
839 uint32_t *value)
840{
841 MetricsMember_t member_type;
842 int clk_id = 0;
843
844 clk_id = smu_cmn_to_asic_specific_index(smu,
845 CMN2ASIC_MAPPING_CLK,
846 clk_type);
847 if (clk_id < 0)
848 return clk_id;
849
850 switch (clk_id) {
851 case PPCLK_GFXCLK:
852 member_type = METRICS_CURR_GFXCLK;
853 break;
854 case PPCLK_UCLK:
855 member_type = METRICS_CURR_UCLK;
856 break;
857 case PPCLK_SOCCLK:
858 member_type = METRICS_CURR_SOCCLK;
859 break;
860 case PPCLK_FCLK:
861 member_type = METRICS_CURR_FCLK;
862 break;
863 case PPCLK_VCLK_0:
864 member_type = METRICS_CURR_VCLK;
865 break;
866 case PPCLK_VCLK_1:
867 member_type = METRICS_CURR_VCLK1;
868 break;
869 case PPCLK_DCLK_0:
870 member_type = METRICS_CURR_DCLK;
871 break;
872 case PPCLK_DCLK_1:
873 member_type = METRICS_CURR_DCLK1;
874 break;
875 case PPCLK_DCEFCLK:
876 member_type = METRICS_CURR_DCEFCLK;
877 break;
878 default:
879 return -EINVAL22;
880 }
881
882 return sienna_cichlid_get_smu_metrics_data(smu,
883 member_type,
884 value);
885
886}
887
888static bool_Bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
889{
890 PPTable_t *pptable = smu->smu_table.driver_pptable;
891 DpmDescriptor_t *dpm_desc = NULL((void *)0);
892 uint32_t clk_index = 0;
893
894 clk_index = smu_cmn_to_asic_specific_index(smu,
895 CMN2ASIC_MAPPING_CLK,
896 clk_type);
897 dpm_desc = &pptable->DpmDescriptor[clk_index];
898
899 /* 0 - Fine grained DPM, 1 - Discrete DPM */
900 return dpm_desc->SnapToDiscrete == 0 ? true1 : false0;
901}
902
903static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
904 enum smu_clk_type clk_type, char *buf)
905{
906 struct amdgpu_device *adev = smu->adev;
907 struct smu_table_context *table_context = &smu->smu_table;
908 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
909 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
910 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
911 int i, size = 0, ret = 0;
912 uint32_t cur_value = 0, value = 0, count = 0;
913 uint32_t freq_values[3] = {0};
914 uint32_t mark_index = 0;
915 uint32_t gen_speed, lane_width;
916
917 switch (clk_type) {
918 case SMU_GFXCLK:
919 case SMU_SCLK:
920 case SMU_SOCCLK:
921 case SMU_MCLK:
922 case SMU_UCLK:
923 case SMU_FCLK:
924 case SMU_DCEFCLK:
925 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
926 if (ret)
927 goto print_clk_out;
928
929 /* no need to disable gfxoff when retrieving the current gfxclk */
930 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
931 amdgpu_gfx_off_ctrl(adev, false0);
932
933 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
934 if (ret)
935 goto print_clk_out;
936
937 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
938 for (i = 0; i < count; i++) {
939 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
940 if (ret)
941 goto print_clk_out;
942
943 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %uMhz %s\n", i, value,
944 cur_value == value ? "*" : "");
945 }
946 } else {
947 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
948 if (ret)
949 goto print_clk_out;
950 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
951 if (ret)
952 goto print_clk_out;
953
954 freq_values[1] = cur_value;
955 mark_index = cur_value == freq_values[0] ? 0 :
956 cur_value == freq_values[2] ? 2 : 1;
957
958 count = 3;
959 if (mark_index != 1) {
960 count = 2;
961 freq_values[1] = freq_values[2];
962 }
963
964 for (i = 0; i < count; i++) {
965 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %uMhz %s\n", i, freq_values[i],
966 cur_value == freq_values[i] ? "*" : "");
967 }
968
969 }
970 break;
971 case SMU_PCIE:
972 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
973 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
974 for (i = 0; i < NUM_LINK_LEVELS2; i++)
975 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %s %s %dMhz %s\n", i,
976 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
977 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
978 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
979 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
980 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
981 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
982 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
983 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
984 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
985 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
986 pptable->LclkFreq[i],
987 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
988 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
989 "*" : "");
990 break;
991 default:
992 break;
993 }
994
995print_clk_out:
996 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
997 amdgpu_gfx_off_ctrl(adev, true1);
998
999 return size;
1000}
1001
1002static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1003 enum smu_clk_type clk_type, uint32_t mask)
1004{
1005 struct amdgpu_device *adev = smu->adev;
1006 int ret = 0, size = 0;
1007 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1008
1009 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1010 soft_max_level = mask ? (fls(mask) - 1) : 0;
1011
1012 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1013 amdgpu_gfx_off_ctrl(adev, false0);
1014
1015 switch (clk_type) {
1016 case SMU_GFXCLK:
1017 case SMU_SCLK:
1018 case SMU_SOCCLK:
1019 case SMU_MCLK:
1020 case SMU_UCLK:
1021 case SMU_FCLK:
1022 /* There is only 2 levels for fine grained DPM */
1023 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1024 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1025 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1026 }
1027
1028 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1029 if (ret)
1030 goto forec_level_out;
1031
1032 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1033 if (ret)
1034 goto forec_level_out;
1035
1036 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1037 if (ret)
1038 goto forec_level_out;
1039 break;
1040 case SMU_DCEFCLK:
1041 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n")do { } while(0);
1042 break;
1043 default:
1044 break;
1045 }
1046
1047forec_level_out:
1048 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1049 amdgpu_gfx_off_ctrl(adev, true1);
1050
1051 return size;
1052}
1053
1054static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1055{
1056 struct smu_11_0_dpm_context *dpm_context =
1057 smu->smu_dpm.dpm_context;
1058 struct smu_11_0_dpm_table *gfx_table =
1059 &dpm_context->dpm_tables.gfx_table;
1060 struct smu_11_0_dpm_table *mem_table =
1061 &dpm_context->dpm_tables.uclk_table;
1062 struct smu_11_0_dpm_table *soc_table =
1063 &dpm_context->dpm_tables.soc_table;
1064 struct smu_umd_pstate_table *pstate_table =
1065 &smu->pstate_table;
1066
1067 pstate_table->gfxclk_pstate.min = gfx_table->min;
1068 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1069
1070 pstate_table->uclk_pstate.min = mem_table->min;
1071 pstate_table->uclk_pstate.peak = mem_table->max;
1072
1073 pstate_table->socclk_pstate.min = soc_table->min;
1074 pstate_table->socclk_pstate.peak = soc_table->max;
1075
1076 return 0;
1077}
1078
1079static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1080{
1081 int ret = 0;
1082 uint32_t max_freq = 0;
1083
1084 /* Sienna_Cichlid do not support to change display num currently */
1085 return 0;
1086#if 0
1087 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL((void *)0));
1088 if (ret)
1089 return ret;
1090#endif
1091
1092 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1093 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL((void *)0), &max_freq);
1094 if (ret)
1095 return ret;
1096 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1097 if (ret)
1098 return ret;
1099 }
1100
1101 return ret;
1102}
1103
1104static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1105{
1106 int ret = 0;
1107
1108 if ((smu->watermarks_bitmap & WATERMARKS_EXIST(1 << 0)) &&
1109 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1110 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1111#if 0
1112 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1113 smu->display_config->num_display,
1114 NULL((void *)0));
1115#endif
1116 if (ret)
1117 return ret;
1118 }
1119
1120 return ret;
1121}
1122
1123static int sienna_cichlid_get_gpu_power(struct smu_context *smu, uint32_t *value)
1124{
1125 if (!value)
1126 return -EINVAL22;
1127
1128 return sienna_cichlid_get_smu_metrics_data(smu,
1129 METRICS_AVERAGE_SOCKETPOWER,
1130 value);
1131}
1132
1133static int sienna_cichlid_get_current_activity_percent(struct smu_context *smu,
1134 enum amd_pp_sensors sensor,
1135 uint32_t *value)
1136{
1137 int ret = 0;
1138
1139 if (!value)
1140 return -EINVAL22;
1141
1142 switch (sensor) {
1143 case AMDGPU_PP_SENSOR_GPU_LOAD:
1144 ret = sienna_cichlid_get_smu_metrics_data(smu,
1145 METRICS_AVERAGE_GFXACTIVITY,
1146 value);
1147 break;
1148 case AMDGPU_PP_SENSOR_MEM_LOAD:
1149 ret = sienna_cichlid_get_smu_metrics_data(smu,
1150 METRICS_AVERAGE_MEMACTIVITY,
1151 value);
1152 break;
1153 default:
1154 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n")printf("drm:pid%d:%s *ERROR* " "Invalid sensor for retrieving clock activity\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1155 return -EINVAL22;
1156 }
1157
1158 return ret;
1159}
1160
1161static bool_Bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1162{
1163 int ret = 0;
1164 uint32_t feature_mask[2];
1165 uint64_t feature_enabled;
1166
1167 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1168 if (ret)
1169 return false0;
1170
1171 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1172
1173 return !!(feature_enabled & SMC_DPM_FEATURE( (1ULL << 0) | (1ULL << 1) | (1ULL << 3) |
(1ULL << 7) | (1ULL << 5) | (1ULL << 4) | (
1ULL << 8) | (1ULL << 6))
);
1174}
1175
1176static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1177 uint32_t *speed)
1178{
1179 if (!speed)
1180 return -EINVAL22;
1181
1182 return sienna_cichlid_get_smu_metrics_data(smu,
1183 METRICS_CURR_FANSPEED,
1184 speed);
1185}
1186
1187static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1188{
1189 PPTable_t *pptable = smu->smu_table.driver_pptable;
1190
1191 smu->fan_max_rpm = pptable->FanMaximumRpm;
1192
1193 return 0;
1194}
1195
1196static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1197{
1198 DpmActivityMonitorCoeffInt_t activity_monitor;
1199 uint32_t i, size = 0;
1200 int16_t workload_type = 0;
1201 static const char *profile_name[] = {
1202 "BOOTUP_DEFAULT",
1203 "3D_FULL_SCREEN",
1204 "POWER_SAVING",
1205 "VIDEO",
1206 "VR",
1207 "COMPUTE",
1208 "CUSTOM"};
1209 static const char *title[] = {
1210 "PROFILE_INDEX(NAME)",
1211 "CLOCK_TYPE(NAME)",
1212 "FPS",
1213 "MinFreqType",
1214 "MinActiveFreqType",
1215 "MinActiveFreq",
1216 "BoosterFreqType",
1217 "BoosterFreq",
1218 "PD_Data_limit_c",
1219 "PD_Data_error_coeff",
1220 "PD_Data_error_rate_coeff"};
1221 int result = 0;
1222
1223 if (!buf)
1224 return -EINVAL22;
1225
1226 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1227 title[0], title[1], title[2], title[3], title[4], title[5],
1228 title[6], title[7], title[8], title[9], title[10]);
1229
1230 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1231 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1232 workload_type = smu_cmn_to_asic_specific_index(smu,
1233 CMN2ASIC_MAPPING_WORKLOAD,
1234 i);
1235 if (workload_type < 0)
1236 return -EINVAL22;
1237
1238 result = smu_cmn_update_table(smu,
1239 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1240 (void *)(&activity_monitor), false0);
1241 if (result) {
1242 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to get activity monitor!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1243 return result;
1244 }
1245
1246 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%2d %14s%s:\n",
1247 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1248
1249 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1250 " ",
1251 0,
1252 "GFXCLK",
1253 activity_monitor.Gfx_FPS,
1254 activity_monitor.Gfx_MinFreqStep,
1255 activity_monitor.Gfx_MinActiveFreqType,
1256 activity_monitor.Gfx_MinActiveFreq,
1257 activity_monitor.Gfx_BoosterFreqType,
1258 activity_monitor.Gfx_BoosterFreq,
1259 activity_monitor.Gfx_PD_Data_limit_c,
1260 activity_monitor.Gfx_PD_Data_error_coeff,
1261 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1262
1263 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1264 " ",
1265 1,
1266 "SOCCLK",
1267 activity_monitor.Fclk_FPS,
1268 activity_monitor.Fclk_MinFreqStep,
1269 activity_monitor.Fclk_MinActiveFreqType,
1270 activity_monitor.Fclk_MinActiveFreq,
1271 activity_monitor.Fclk_BoosterFreqType,
1272 activity_monitor.Fclk_BoosterFreq,
1273 activity_monitor.Fclk_PD_Data_limit_c,
1274 activity_monitor.Fclk_PD_Data_error_coeff,
1275 activity_monitor.Fclk_PD_Data_error_rate_coeff);
1276
1277 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1278 " ",
1279 2,
1280 "MEMLK",
1281 activity_monitor.Mem_FPS,
1282 activity_monitor.Mem_MinFreqStep,
1283 activity_monitor.Mem_MinActiveFreqType,
1284 activity_monitor.Mem_MinActiveFreq,
1285 activity_monitor.Mem_BoosterFreqType,
1286 activity_monitor.Mem_BoosterFreq,
1287 activity_monitor.Mem_PD_Data_limit_c,
1288 activity_monitor.Mem_PD_Data_error_coeff,
1289 activity_monitor.Mem_PD_Data_error_rate_coeff);
1290 }
1291
1292 return size;
1293}
1294
1295static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1296{
1297 DpmActivityMonitorCoeffInt_t activity_monitor;
1298 int workload_type, ret = 0;
1299
1300 smu->power_profile_mode = input[size];
1301
1302 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1303 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode)printf("drm:pid%d:%s *ERROR* " "Invalid power profile mode %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , smu->
power_profile_mode)
;
1304 return -EINVAL22;
1305 }
1306
1307 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1308
1309 ret = smu_cmn_update_table(smu,
1310 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT6,
1311 (void *)(&activity_monitor), false0);
1312 if (ret) {
1313 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to get activity monitor!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1314 return ret;
1315 }
1316
1317 switch (input[0]) {
1318 case 0: /* Gfxclk */
1319 activity_monitor.Gfx_FPS = input[1];
1320 activity_monitor.Gfx_MinFreqStep = input[2];
1321 activity_monitor.Gfx_MinActiveFreqType = input[3];
1322 activity_monitor.Gfx_MinActiveFreq = input[4];
1323 activity_monitor.Gfx_BoosterFreqType = input[5];
1324 activity_monitor.Gfx_BoosterFreq = input[6];
1325 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1326 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1327 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1328 break;
1329 case 1: /* Socclk */
1330 activity_monitor.Fclk_FPS = input[1];
1331 activity_monitor.Fclk_MinFreqStep = input[2];
1332 activity_monitor.Fclk_MinActiveFreqType = input[3];
1333 activity_monitor.Fclk_MinActiveFreq = input[4];
1334 activity_monitor.Fclk_BoosterFreqType = input[5];
1335 activity_monitor.Fclk_BoosterFreq = input[6];
1336 activity_monitor.Fclk_PD_Data_limit_c = input[7];
1337 activity_monitor.Fclk_PD_Data_error_coeff = input[8];
1338 activity_monitor.Fclk_PD_Data_error_rate_coeff = input[9];
1339 break;
1340 case 2: /* Memlk */
1341 activity_monitor.Mem_FPS = input[1];
1342 activity_monitor.Mem_MinFreqStep = input[2];
1343 activity_monitor.Mem_MinActiveFreqType = input[3];
1344 activity_monitor.Mem_MinActiveFreq = input[4];
1345 activity_monitor.Mem_BoosterFreqType = input[5];
1346 activity_monitor.Mem_BoosterFreq = input[6];
1347 activity_monitor.Mem_PD_Data_limit_c = input[7];
1348 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1349 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1350 break;
1351 }
1352
1353 ret = smu_cmn_update_table(smu,
1354 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT6,
1355 (void *)(&activity_monitor), true1);
1356 if (ret) {
1357 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to set activity monitor!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1358 return ret;
1359 }
1360 }
1361
1362 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1363 workload_type = smu_cmn_to_asic_specific_index(smu,
1364 CMN2ASIC_MAPPING_WORKLOAD,
1365 smu->power_profile_mode);
1366 if (workload_type < 0)
1367 return -EINVAL22;
1368 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1369 1 << workload_type, NULL((void *)0));
1370
1371 return ret;
1372}
1373
1374static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1375{
1376 struct smu_clocks min_clocks = {0};
1377 struct pp_display_clock_request clock_req;
1378 int ret = 0;
1379
1380 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1381 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1382 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1383
1384 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1385 clock_req.clock_type = amd_pp_dcef_clock;
1386 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1387
1388 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1389 if (!ret) {
1390 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1391 ret = smu_cmn_send_smc_msg_with_param(smu,
1392 SMU_MSG_SetMinDeepSleepDcefclk,
1393 min_clocks.dcef_clock_in_sr/100,
1394 NULL((void *)0));
1395 if (ret) {
1396 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to set divider for DCEFCLK Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1397 return ret;
1398 }
1399 }
1400 } else {
1401 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!")do { } while(0);
1402 }
1403 }
1404
1405 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1406 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1407 if (ret) {
1408 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Set hard min uclk failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1409 return ret;
1410 }
1411 }
1412
1413 return 0;
1414}
1415
1416static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1417 struct pp_smu_wm_range_sets *clock_ranges)
1418{
1419 Watermarks_t *table = smu->smu_table.watermarks_table;
1420 int ret = 0;
1421 int i;
1422
1423 if (clock_ranges) {
1424 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES4 ||
1425 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES4)
1426 return -EINVAL22;
1427
1428 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1429 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1430 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1431 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1432 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1433 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1434 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1435 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1436 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1437
1438 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1439 clock_ranges->reader_wm_sets[i].wm_inst;
1440 }
1441
1442 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1443 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1444 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1445 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1446 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1447 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1448 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1449 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1450 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1451
1452 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1453 clock_ranges->writer_wm_sets[i].wm_inst;
1454 }
1455
1456 smu->watermarks_bitmap |= WATERMARKS_EXIST(1 << 0);
1457 }
1458
1459 if ((smu->watermarks_bitmap & WATERMARKS_EXIST(1 << 0)) &&
1460 !(smu->watermarks_bitmap & WATERMARKS_LOADED(1 << 1))) {
1461 ret = smu_cmn_write_watermarks_table(smu);
1462 if (ret) {
1463 dev_err(smu->adev->dev, "Failed to update WMTABLE!")printf("drm:pid%d:%s *ERROR* " "Failed to update WMTABLE!", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1464 return ret;
1465 }
1466 smu->watermarks_bitmap |= WATERMARKS_LOADED(1 << 1);
1467 }
1468
1469 return 0;
1470}
1471
1472static int sienna_cichlid_thermal_get_temperature(struct smu_context *smu,
1473 enum amd_pp_sensors sensor,
1474 uint32_t *value)
1475{
1476 int ret = 0;
1477
1478 if (!value)
1479 return -EINVAL22;
1480
1481 switch (sensor) {
1482 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1483 ret = sienna_cichlid_get_smu_metrics_data(smu,
1484 METRICS_TEMPERATURE_HOTSPOT,
1485 value);
1486 break;
1487 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1488 ret = sienna_cichlid_get_smu_metrics_data(smu,
1489 METRICS_TEMPERATURE_EDGE,
1490 value);
1491 break;
1492 case AMDGPU_PP_SENSOR_MEM_TEMP:
1493 ret = sienna_cichlid_get_smu_metrics_data(smu,
1494 METRICS_TEMPERATURE_MEM,
1495 value);
1496 break;
1497 default:
1498 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n")printf("drm:pid%d:%s *ERROR* " "Invalid sensor for retrieving temp\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1499 return -EINVAL22;
1500 }
1501
1502 return ret;
1503}
1504
1505static int sienna_cichlid_read_sensor(struct smu_context *smu,
1506 enum amd_pp_sensors sensor,
1507 void *data, uint32_t *size)
1508{
1509 int ret = 0;
1510 struct smu_table_context *table_context = &smu->smu_table;
1511 PPTable_t *pptable = table_context->driver_pptable;
1512
1513 if(!data || !size)
1514 return -EINVAL22;
1515
1516 mutex_lock(&smu->sensor_lock)rw_enter_write(&smu->sensor_lock);
1517 switch (sensor) {
1518 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1519 *(uint32_t *)data = pptable->FanMaximumRpm;
1520 *size = 4;
1521 break;
1522 case AMDGPU_PP_SENSOR_MEM_LOAD:
1523 case AMDGPU_PP_SENSOR_GPU_LOAD:
1524 ret = sienna_cichlid_get_current_activity_percent(smu, sensor, (uint32_t *)data);
1525 *size = 4;
1526 break;
1527 case AMDGPU_PP_SENSOR_GPU_POWER:
1528 ret = sienna_cichlid_get_gpu_power(smu, (uint32_t *)data);
1529 *size = 4;
1530 break;
1531 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1532 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1533 case AMDGPU_PP_SENSOR_MEM_TEMP:
1534 ret = sienna_cichlid_thermal_get_temperature(smu, sensor, (uint32_t *)data);
1535 *size = 4;
1536 break;
1537 case AMDGPU_PP_SENSOR_GFX_MCLK:
1538 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1539 *(uint32_t *)data *= 100;
1540 *size = 4;
1541 break;
1542 case AMDGPU_PP_SENSOR_GFX_SCLK:
1543 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1544 *(uint32_t *)data *= 100;
1545 *size = 4;
1546 break;
1547 case AMDGPU_PP_SENSOR_VDDGFX:
1548 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1549 *size = 4;
1550 break;
1551 default:
1552 ret = -EOPNOTSUPP45;
1553 break;
1554 }
1555 mutex_unlock(&smu->sensor_lock)rw_exit_write(&smu->sensor_lock);
1556
1557 return ret;
1558}
1559
1560static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1561{
1562 uint32_t num_discrete_levels = 0;
1563 uint16_t *dpm_levels = NULL((void *)0);
1564 uint16_t i = 0;
1565 struct smu_table_context *table_context = &smu->smu_table;
1566 PPTable_t *driver_ppt = NULL((void *)0);
1567
1568 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1569 return -EINVAL22;
1570
1571 driver_ppt = table_context->driver_pptable;
1572 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
1573 dpm_levels = driver_ppt->FreqTableUclk;
1574
1575 if (num_discrete_levels == 0 || dpm_levels == NULL((void *)0))
1576 return -EINVAL22;
1577
1578 *num_states = num_discrete_levels;
1579 for (i = 0; i < num_discrete_levels; i++) {
1580 /* convert to khz */
1581 *clocks_in_khz = (*dpm_levels) * 1000;
1582 clocks_in_khz++;
1583 dpm_levels++;
1584 }
1585
1586 return 0;
1587}
1588
1589static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1590 struct smu_temperature_range *range)
1591{
1592 struct smu_table_context *table_context = &smu->smu_table;
1593 struct smu_11_0_7_powerplay_table *powerplay_table =
1594 table_context->power_play_table;
1595 PPTable_t *pptable = smu->smu_table.driver_pptable;
1596
1597 if (!range)
1598 return -EINVAL22;
1599
1600 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range))__builtin_memcpy((range), (&smu11_thermal_policy[0]), (sizeof
(struct smu_temperature_range)))
;
1601
1602 range->max = pptable->TemperatureLimit[TEMP_EDGE] *
1603 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
1604 range->edge_emergency_max = (pptable->TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE5) *
1605 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
1606 range->hotspot_crit_max = pptable->TemperatureLimit[TEMP_HOTSPOT] *
1607 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
1608 range->hotspot_emergency_max = (pptable->TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT5) *
1609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
1610 range->mem_crit_max = pptable->TemperatureLimit[TEMP_MEM] *
1611 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
1612 range->mem_emergency_max = (pptable->TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM5)*
1613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
1614 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1615
1616 return 0;
1617}
1618
1619static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1620 bool_Bool disable_memory_clock_switch)
1621{
1622 int ret = 0;
1623 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1624 (struct smu_11_0_max_sustainable_clocks *)
1625 smu->smu_table.max_sustainable_clocks;
1626 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1627 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1628
1629 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1630 return 0;
1631
1632 if(disable_memory_clock_switch)
1633 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1634 else
1635 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1636
1637 if(!ret)
1638 smu->disable_uclk_switch = disable_memory_clock_switch;
1639
1640 return ret;
1641}
1642
1643static int sienna_cichlid_get_power_limit(struct smu_context *smu)
1644{
1645 struct smu_11_0_7_powerplay_table *powerplay_table =
1646 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1647 PPTable_t *pptable = smu->smu_table.driver_pptable;
1648 uint32_t power_limit, od_percent;
1649
1650 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1651 /* the last hope to figure out the ppt limit */
1652 if (!pptable) {
1653 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!")printf("drm:pid%d:%s *ERROR* " "Cannot get PPT limit due to pptable missing!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1654 return -EINVAL22;
1655 }
1656 power_limit =
1657 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1658 }
1659 smu->current_power_limit = power_limit;
1660
1661 if (smu->od_enabled) {
1662 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE])((__uint32_t)(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE
]))
;
1663
1664 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit)do { } while(0);
1665
1666 power_limit *= (100 + od_percent);
1667 power_limit /= 100;
1668 }
1669 smu->max_power_limit = power_limit;
1670
1671 return 0;
1672}
1673
1674static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1675 uint32_t pcie_gen_cap,
1676 uint32_t pcie_width_cap)
1677{
1678 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1679 PPTable_t *pptable = smu->smu_table.driver_pptable;
1680 uint32_t smu_pcie_arg;
1681 int ret, i;
1682
1683 /* lclk dpm table setup */
1684 for (i = 0; i < MAX_PCIE_CONF2; i++) {
1685 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
1686 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
1687 }
1688
1689 for (i = 0; i < NUM_LINK_LEVELS2; i++) {
1690 smu_pcie_arg = (i << 16) |
1691 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ?
1692 (pptable->PcieGenSpeed[i] << 8) :
1693 (pcie_gen_cap << 8)) |
1694 ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
1695 pptable->PcieLaneCount[i] :
1696 pcie_width_cap);
1697
1698 ret = smu_cmn_send_smc_msg_with_param(smu,
1699 SMU_MSG_OverridePcieParameters,
1700 smu_pcie_arg,
1701 NULL((void *)0));
1702
1703 if (ret)
1704 return ret;
1705
1706 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
1707 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1708 if (pptable->PcieLaneCount[i] > pcie_width_cap)
1709 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1710 }
1711
1712 return 0;
1713}
1714
1715static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1716 enum smu_clk_type clk_type,
1717 uint32_t *min, uint32_t *max)
1718{
1719 struct amdgpu_device *adev = smu->adev;
1720 int ret;
1721
1722 if (clk_type == SMU_GFXCLK)
1723 amdgpu_gfx_off_ctrl(adev, false0);
1724 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1725 if (clk_type == SMU_GFXCLK)
1726 amdgpu_gfx_off_ctrl(adev, true1);
1727
1728 return ret;
1729}
1730
1731static int sienna_cichlid_run_btc(struct smu_context *smu)
1732{
1733 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL((void *)0));
1734}
1735
1736static bool_Bool sienna_cichlid_is_baco_supported(struct smu_context *smu)
1737{
1738 struct amdgpu_device *adev = smu->adev;
1739 uint32_t val;
1740
1741 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) || (!smu_v11_0_baco_is_support(smu)))
1742 return false0;
1743
1744 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0)amdgpu_device_rreg(adev, (adev->reg_offset[NBIO_HWIP][0][2
] + 0x0000), 0)
;
1745 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK0x00000080L) ? true1 : false0;
1746}
1747
1748static bool_Bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
1749{
1750 struct amdgpu_device *adev = smu->adev;
1751 uint32_t val;
1752 u32 smu_version;
1753
1754 /**
1755 * SRIOV env will not support SMU mode1 reset
1756 * PM FW support mode1 reset from 58.26
1757 */
1758 smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
1759 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) || (smu_version < 0x003a1a00))
1760 return false0;
1761
1762 /**
1763 * mode1 reset relies on PSP, so we should check if
1764 * PSP is alive.
1765 */
1766 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81)amdgpu_device_rreg(adev, (adev->reg_offset[MP0_HWIP][0][0]
+ 0x0091), 0)
;
1767 return val != 0x0;
1768}
1769
1770static void sienna_cichlid_dump_pptable(struct smu_context *smu)
1771{
1772 struct smu_table_context *table_context = &smu->smu_table;
1773 PPTable_t *pptable = table_context->driver_pptable;
Value stored to 'pptable' during its initialization is never read
1774 int i;
1775
1776 dev_info(smu->adev->dev, "Dumped PPTable:\n")do { } while(0);
1777
1778 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version)do { } while(0);
1779 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0])do { } while(0);
1780 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1])do { } while(0);
1781
1782 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1783 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i])do { } while(0);
1784 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i])do { } while(0);
1785 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i])do { } while(0);
1786 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i])do { } while(0);
1787 }
1788
1789 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
1790 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i])do { } while(0);
1791 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i])do { } while(0);
1792 }
1793
1794 for (i = 0; i < TEMP_COUNT; i++) {
1795 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i])do { } while(0);
1796 }
1797
1798 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit)do { } while(0);
1799 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig)do { } while(0);
1800 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0])do { } while(0);
1801 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1])do { } while(0);
1802 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2])do { } while(0);
1803
1804 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit)do { } while(0);
1805 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS2; i++) {
1806 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i])do { } while(0);
1807 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i])do { } while(0);
1808 }
1809 dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", pptable->PaddingAPCC[0])do { } while(0);
1810 dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", pptable->PaddingAPCC[1])do { } while(0);
1811 dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", pptable->PaddingAPCC[2])do { } while(0);
1812 dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", pptable->PaddingAPCC[3])do { } while(0);
1813
1814 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask)do { } while(0);
1815
1816 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask)do { } while(0);
1817
1818 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc)do { } while(0);
1819 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx)do { } while(0);
1820 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx)do { } while(0);
1821 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc)do { } while(0);
1822
1823 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin)do { } while(0);
1824 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin)do { } while(0);
1825
1826 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold)do { } while(0);
1827 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0])do { } while(0);
1828 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1])do { } while(0);
1829 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2])do { } while(0);
1830
1831 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx)do { } while(0);
1832 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc)do { } while(0);
1833 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx)do { } while(0);
1834 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc)do { } while(0);
1835
1836 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx)do { } while(0);
1837 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc)do { } while(0);
1838
1839 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin)do { } while(0);
1840 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin)do { } while(0);
1841 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp)do { } while(0);
1842 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp)do { } while(0);
1843 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp)do { } while(0);
1844 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp)do { } while(0);
1845 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis)do { } while(0);
1846 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis)do { } while(0);
1847
1848 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"do { } while(0)
1849 " .VoltageMode = 0x%02x\n"do { } while(0)
1850 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1851 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1852 " .padding = 0x%02x\n"do { } while(0)
1853 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1854 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1855 " .SsFmin = 0x%04x\n"do { } while(0)
1856 " .Padding_16 = 0x%04x\n",do { } while(0)
1857 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,do { } while(0)
1858 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,do { } while(0)
1859 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,do { } while(0)
1860 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,do { } while(0)
1861 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,do { } while(0)
1862 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,do { } while(0)
1863 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,do { } while(0)
1864 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,do { } while(0)
1865 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,do { } while(0)
1866 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,do { } while(0)
1867 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16)do { } while(0);
1868
1869 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"do { } while(0)
1870 " .VoltageMode = 0x%02x\n"do { } while(0)
1871 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1872 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1873 " .padding = 0x%02x\n"do { } while(0)
1874 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1875 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1876 " .SsFmin = 0x%04x\n"do { } while(0)
1877 " .Padding_16 = 0x%04x\n",do { } while(0)
1878 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,do { } while(0)
1879 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,do { } while(0)
1880 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,do { } while(0)
1881 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,do { } while(0)
1882 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,do { } while(0)
1883 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,do { } while(0)
1884 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,do { } while(0)
1885 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,do { } while(0)
1886 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,do { } while(0)
1887 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,do { } while(0)
1888 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16)do { } while(0);
1889
1890 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"do { } while(0)
1891 " .VoltageMode = 0x%02x\n"do { } while(0)
1892 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1893 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1894 " .padding = 0x%02x\n"do { } while(0)
1895 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1896 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1897 " .SsFmin = 0x%04x\n"do { } while(0)
1898 " .Padding_16 = 0x%04x\n",do { } while(0)
1899 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,do { } while(0)
1900 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,do { } while(0)
1901 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,do { } while(0)
1902 pptable->DpmDescriptor[PPCLK_UCLK].Padding,do { } while(0)
1903 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,do { } while(0)
1904 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,do { } while(0)
1905 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,do { } while(0)
1906 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,do { } while(0)
1907 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,do { } while(0)
1908 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,do { } while(0)
1909 pptable->DpmDescriptor[PPCLK_UCLK].Padding16)do { } while(0);
1910
1911 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"do { } while(0)
1912 " .VoltageMode = 0x%02x\n"do { } while(0)
1913 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1914 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1915 " .padding = 0x%02x\n"do { } while(0)
1916 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1917 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1918 " .SsFmin = 0x%04x\n"do { } while(0)
1919 " .Padding_16 = 0x%04x\n",do { } while(0)
1920 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,do { } while(0)
1921 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,do { } while(0)
1922 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,do { } while(0)
1923 pptable->DpmDescriptor[PPCLK_FCLK].Padding,do { } while(0)
1924 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,do { } while(0)
1925 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,do { } while(0)
1926 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,do { } while(0)
1927 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,do { } while(0)
1928 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,do { } while(0)
1929 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,do { } while(0)
1930 pptable->DpmDescriptor[PPCLK_FCLK].Padding16)do { } while(0);
1931
1932 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"do { } while(0)
1933 " .VoltageMode = 0x%02x\n"do { } while(0)
1934 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1935 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1936 " .padding = 0x%02x\n"do { } while(0)
1937 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1938 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1939 " .SsFmin = 0x%04x\n"do { } while(0)
1940 " .Padding_16 = 0x%04x\n",do { } while(0)
1941 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,do { } while(0)
1942 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,do { } while(0)
1943 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,do { } while(0)
1944 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,do { } while(0)
1945 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,do { } while(0)
1946 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,do { } while(0)
1947 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,do { } while(0)
1948 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,do { } while(0)
1949 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,do { } while(0)
1950 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,do { } while(0)
1951 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16)do { } while(0);
1952
1953 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"do { } while(0)
1954 " .VoltageMode = 0x%02x\n"do { } while(0)
1955 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1956 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1957 " .padding = 0x%02x\n"do { } while(0)
1958 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1959 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1960 " .SsFmin = 0x%04x\n"do { } while(0)
1961 " .Padding_16 = 0x%04x\n",do { } while(0)
1962 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,do { } while(0)
1963 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,do { } while(0)
1964 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,do { } while(0)
1965 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,do { } while(0)
1966 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,do { } while(0)
1967 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,do { } while(0)
1968 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,do { } while(0)
1969 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,do { } while(0)
1970 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,do { } while(0)
1971 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,do { } while(0)
1972 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16)do { } while(0);
1973
1974 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"do { } while(0)
1975 " .VoltageMode = 0x%02x\n"do { } while(0)
1976 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1977 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1978 " .padding = 0x%02x\n"do { } while(0)
1979 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1980 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1981 " .SsFmin = 0x%04x\n"do { } while(0)
1982 " .Padding_16 = 0x%04x\n",do { } while(0)
1983 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,do { } while(0)
1984 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,do { } while(0)
1985 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,do { } while(0)
1986 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,do { } while(0)
1987 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,do { } while(0)
1988 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,do { } while(0)
1989 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,do { } while(0)
1990 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,do { } while(0)
1991 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,do { } while(0)
1992 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,do { } while(0)
1993 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16)do { } while(0);
1994
1995 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"do { } while(0)
1996 " .VoltageMode = 0x%02x\n"do { } while(0)
1997 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1998 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1999 " .padding = 0x%02x\n"do { } while(0)
2000 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
2001 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
2002 " .SsFmin = 0x%04x\n"do { } while(0)
2003 " .Padding_16 = 0x%04x\n",do { } while(0)
2004 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,do { } while(0)
2005 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,do { } while(0)
2006 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,do { } while(0)
2007 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,do { } while(0)
2008 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,do { } while(0)
2009 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,do { } while(0)
2010 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,do { } while(0)
2011 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,do { } while(0)
2012 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,do { } while(0)
2013 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,do { } while(0)
2014 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16)do { } while(0);
2015
2016 dev_info(smu->adev->dev, "FreqTableGfx\n")do { } while(0);
2017 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS16; i++)
2018 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i])do { } while(0);
2019
2020 dev_info(smu->adev->dev, "FreqTableVclk\n")do { } while(0);
2021 for (i = 0; i < NUM_VCLK_DPM_LEVELS8; i++)
2022 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i])do { } while(0);
2023
2024 dev_info(smu->adev->dev, "FreqTableDclk\n")do { } while(0);
2025 for (i = 0; i < NUM_DCLK_DPM_LEVELS8; i++)
2026 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i])do { } while(0);
2027
2028 dev_info(smu->adev->dev, "FreqTableSocclk\n")do { } while(0);
2029 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS8; i++)
2030 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i])do { } while(0);
2031
2032 dev_info(smu->adev->dev, "FreqTableUclk\n")do { } while(0);
2033 for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++)
2034 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i])do { } while(0);
2035
2036 dev_info(smu->adev->dev, "FreqTableFclk\n")do { } while(0);
2037 for (i = 0; i < NUM_FCLK_DPM_LEVELS8; i++)
2038 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i])do { } while(0);
2039
2040 dev_info(smu->adev->dev, "Paddingclks[0] = 0x%x\n", pptable->Paddingclks[0])do { } while(0);
2041 dev_info(smu->adev->dev, "Paddingclks[1] = 0x%x\n", pptable->Paddingclks[1])do { } while(0);
2042 dev_info(smu->adev->dev, "Paddingclks[2] = 0x%x\n", pptable->Paddingclks[2])do { } while(0);
2043 dev_info(smu->adev->dev, "Paddingclks[3] = 0x%x\n", pptable->Paddingclks[3])do { } while(0);
2044 dev_info(smu->adev->dev, "Paddingclks[4] = 0x%x\n", pptable->Paddingclks[4])do { } while(0);
2045 dev_info(smu->adev->dev, "Paddingclks[5] = 0x%x\n", pptable->Paddingclks[5])do { } while(0);
2046 dev_info(smu->adev->dev, "Paddingclks[6] = 0x%x\n", pptable->Paddingclks[6])do { } while(0);
2047 dev_info(smu->adev->dev, "Paddingclks[7] = 0x%x\n", pptable->Paddingclks[7])do { } while(0);
2048 dev_info(smu->adev->dev, "Paddingclks[8] = 0x%x\n", pptable->Paddingclks[8])do { } while(0);
2049 dev_info(smu->adev->dev, "Paddingclks[9] = 0x%x\n", pptable->Paddingclks[9])do { } while(0);
2050 dev_info(smu->adev->dev, "Paddingclks[10] = 0x%x\n", pptable->Paddingclks[10])do { } while(0);
2051 dev_info(smu->adev->dev, "Paddingclks[11] = 0x%x\n", pptable->Paddingclks[11])do { } while(0);
2052 dev_info(smu->adev->dev, "Paddingclks[12] = 0x%x\n", pptable->Paddingclks[12])do { } while(0);
2053 dev_info(smu->adev->dev, "Paddingclks[13] = 0x%x\n", pptable->Paddingclks[13])do { } while(0);
2054 dev_info(smu->adev->dev, "Paddingclks[14] = 0x%x\n", pptable->Paddingclks[14])do { } while(0);
2055 dev_info(smu->adev->dev, "Paddingclks[15] = 0x%x\n", pptable->Paddingclks[15])do { } while(0);
2056
2057 dev_info(smu->adev->dev, "DcModeMaxFreq\n")do { } while(0);
2058 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK])do { } while(0);
2059 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK])do { } while(0);
2060 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK])do { } while(0);
2061 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK])do { } while(0);
2062 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0])do { } while(0);
2063 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0])do { } while(0);
2064 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1])do { } while(0);
2065 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1])do { } while(0);
2066
2067 dev_info(smu->adev->dev, "FreqTableUclkDiv\n")do { } while(0);
2068 for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++)
2069 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i])do { } while(0);
2070
2071 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq)do { } while(0);
2072 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding)do { } while(0);
2073
2074 dev_info(smu->adev->dev, "Mp0clkFreq\n")do { } while(0);
2075 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++)
2076 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i])do { } while(0);
2077
2078 dev_info(smu->adev->dev, "Mp0DpmVoltage\n")do { } while(0);
2079 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++)
2080 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i])do { } while(0);
2081
2082 dev_info(smu->adev->dev, "MemVddciVoltage\n")do { } while(0);
2083 for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++)
2084 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i])do { } while(0);
2085
2086 dev_info(smu->adev->dev, "MemMvddVoltage\n")do { } while(0);
2087 for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++)
2088 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i])do { } while(0);
2089
2090 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry)do { } while(0);
2091 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit)do { } while(0);
2092 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle)do { } while(0);
2093 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource)do { } while(0);
2094 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding)do { } while(0);
2095
2096 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask)do { } while(0);
2097
2098 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask)do { } while(0);
2099 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask)do { } while(0);
2100 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0])do { } while(0);
2101 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow)do { } while(0);
2102 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0])do { } while(0);
2103 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1])do { } while(0);
2104 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2])do { } while(0);
2105 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3])do { } while(0);
2106 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt)do { } while(0);
2107 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt)do { } while(0);
2108 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt)do { } while(0);
2109
2110 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage)do { } while(0);
2111 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime)do { } while(0);
2112 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime)do { } while(0);
2113 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum)do { } while(0);
2114 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis)do { } while(0);
2115 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout)do { } while(0);
2116
2117 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0])do { } while(0);
2118 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1])do { } while(0);
2119 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2])do { } while(0);
2120 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3])do { } while(0);
2121 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4])do { } while(0);
2122
2123 dev_info(smu->adev->dev, "FlopsPerByteTable\n")do { } while(0);
2124 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS16; i++)
2125 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i])do { } while(0);
2126
2127 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv)do { } while(0);
2128 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0])do { } while(0);
2129 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1])do { } while(0);
2130 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2])do { } while(0);
2131
2132 dev_info(smu->adev->dev, "UclkDpmPstates\n")do { } while(0);
2133 for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++)
2134 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i])do { } while(0);
2135
2136 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n")do { } while(0);
2137 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",do { } while(0)
2138 pptable->UclkDpmSrcFreqRange.Fmin)do { } while(0);
2139 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",do { } while(0)
2140 pptable->UclkDpmSrcFreqRange.Fmax)do { } while(0);
2141 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n")do { } while(0);
2142 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",do { } while(0)
2143 pptable->UclkDpmTargFreqRange.Fmin)do { } while(0);
2144 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",do { } while(0)
2145 pptable->UclkDpmTargFreqRange.Fmax)do { } while(0);
2146 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq)do { } while(0);
2147 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding)do { } while(0);
2148
2149 dev_info(smu->adev->dev, "PcieGenSpeed\n")do { } while(0);
2150 for (i = 0; i < NUM_LINK_LEVELS2; i++)
2151 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i])do { } while(0);
2152
2153 dev_info(smu->adev->dev, "PcieLaneCount\n")do { } while(0);
2154 for (i = 0; i < NUM_LINK_LEVELS2; i++)
2155 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i])do { } while(0);
2156
2157 dev_info(smu->adev->dev, "LclkFreq\n")do { } while(0);
2158 for (i = 0; i < NUM_LINK_LEVELS2; i++)
2159 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i])do { } while(0);
2160
2161 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp)do { } while(0);
2162 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp)do { } while(0);
2163
2164 dev_info(smu->adev->dev, "FanGain\n")do { } while(0);
2165 for (i = 0; i < TEMP_COUNT; i++)
2166 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i])do { } while(0);
2167
2168 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin)do { } while(0);
2169 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm)do { } while(0);
2170 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm)do { } while(0);
2171 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm)do { } while(0);
2172 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm)do { } while(0);
2173 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature)do { } while(0);
2174 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk)do { } while(0);
2175 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16)do { } while(0);
2176 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect)do { } while(0);
2177 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding)do { } while(0);
2178 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable)do { } while(0);
2179 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev)do { } while(0);
2180
2181 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta)do { } while(0);
2182 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta)do { } while(0);
2183 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta)do { } while(0);
2184 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved)do { } while(0);
2185
2186 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX])do { } while(0);
2187 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC])do { } while(0);
2188 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect)do { } while(0);
2189 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs)do { } while(0);
2190
2191 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2192 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,do { } while(0)
2193 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,do { } while(0)
2194 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c)do { } while(0);
2195 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2196 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,do { } while(0)
2197 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,do { } while(0)
2198 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c)do { } while(0);
2199 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2200 pptable->dBtcGbGfxPll.a,do { } while(0)
2201 pptable->dBtcGbGfxPll.b,do { } while(0)
2202 pptable->dBtcGbGfxPll.c)do { } while(0);
2203 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2204 pptable->dBtcGbGfxDfll.a,do { } while(0)
2205 pptable->dBtcGbGfxDfll.b,do { } while(0)
2206 pptable->dBtcGbGfxDfll.c)do { } while(0);
2207 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2208 pptable->dBtcGbSoc.a,do { } while(0)
2209 pptable->dBtcGbSoc.b,do { } while(0)
2210 pptable->dBtcGbSoc.c)do { } while(0);
2211 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",do { } while(0)
2212 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,do { } while(0)
2213 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b)do { } while(0);
2214 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",do { } while(0)
2215 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,do { } while(0)
2216 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b)do { } while(0);
2217
2218 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n")do { } while(0);
2219 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS5; i++) {
2220 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",do { } while(0)
2221 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i])do { } while(0);
2222 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",do { } while(0)
2223 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i])do { } while(0);
2224 }
2225
2226 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2227 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,do { } while(0)
2228 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,do { } while(0)
2229 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c)do { } while(0);
2230 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2231 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,do { } while(0)
2232 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,do { } while(0)
2233 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c)do { } while(0);
2234
2235 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX])do { } while(0);
2236 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC])do { } while(0);
2237
2238 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX])do { } while(0);
2239 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC])do { } while(0);
2240 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0])do { } while(0);
2241 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1])do { } while(0);
2242
2243 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX])do { } while(0);
2244 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC])do { } while(0);
2245 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX])do { } while(0);
2246 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC])do { } while(0);
2247
2248 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX])do { } while(0);
2249 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC])do { } while(0);
2250
2251 dev_info(smu->adev->dev, "XgmiDpmPstates\n")do { } while(0);
2252 for (i = 0; i < NUM_XGMI_LEVELS2; i++)
2253 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i])do { } while(0);
2254 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0])do { } while(0);
2255 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1])do { } while(0);
2256
2257 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides)do { } while(0);
2258 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2259 pptable->ReservedEquation0.a,do { } while(0)
2260 pptable->ReservedEquation0.b,do { } while(0)
2261 pptable->ReservedEquation0.c)do { } while(0);
2262 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2263 pptable->ReservedEquation1.a,do { } while(0)
2264 pptable->ReservedEquation1.b,do { } while(0)
2265 pptable->ReservedEquation1.c)do { } while(0);
2266 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2267 pptable->ReservedEquation2.a,do { } while(0)
2268 pptable->ReservedEquation2.b,do { } while(0)
2269 pptable->ReservedEquation2.c)do { } while(0);
2270 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
2271 pptable->ReservedEquation3.a,do { } while(0)
2272 pptable->ReservedEquation3.b,do { } while(0)
2273 pptable->ReservedEquation3.c)do { } while(0);
2274
2275 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0])do { } while(0);
2276 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1])do { } while(0);
2277 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2])do { } while(0);
2278 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3])do { } while(0);
2279 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4])do { } while(0);
2280 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5])do { } while(0);
2281 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6])do { } while(0);
2282 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7])do { } while(0);
2283 dev_info(smu->adev->dev, "SkuReserved[8] = 0x%x\n", pptable->SkuReserved[8])do { } while(0);
2284
2285 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0])do { } while(0);
2286 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1])do { } while(0);
2287 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2])do { } while(0);
2288 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3])do { } while(0);
2289 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4])do { } while(0);
2290 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5])do { } while(0);
2291
2292 for (i = 0; i < NUM_I2C_CONTROLLERS16; i++) {
2293 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i)do { } while(0);
2294 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",do { } while(0)
2295 pptable->I2cControllers[i].Enabled)do { } while(0);
2296 dev_info(smu->adev->dev, " .Speed = 0x%x\n",do { } while(0)
2297 pptable->I2cControllers[i].Speed)do { } while(0);
2298 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",do { } while(0)
2299 pptable->I2cControllers[i].SlaveAddress)do { } while(0);
2300 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",do { } while(0)
2301 pptable->I2cControllers[i].ControllerPort)do { } while(0);
2302 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",do { } while(0)
2303 pptable->I2cControllers[i].ControllerName)do { } while(0);
2304 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",do { } while(0)
2305 pptable->I2cControllers[i].ThermalThrotter)do { } while(0);
2306 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",do { } while(0)
2307 pptable->I2cControllers[i].I2cProtocol)do { } while(0);
2308 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",do { } while(0)
2309 pptable->I2cControllers[i].PaddingConfig)do { } while(0);
2310 }
2311
2312 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl)do { } while(0);
2313 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda)do { } while(0);
2314 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr)do { } while(0);
2315 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0])do { } while(0);
2316
2317 dev_info(smu->adev->dev, "Board Parameters:\n")do { } while(0);
2318 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping)do { } while(0);
2319 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping)do { } while(0);
2320 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping)do { } while(0);
2321 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping)do { } while(0);
2322 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask)do { } while(0);
2323 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask)do { } while(0);
2324 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask)do { } while(0);
2325 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask)do { } while(0);
2326
2327 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent)do { } while(0);
2328 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset)do { } while(0);
2329 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx)do { } while(0);
2330
2331 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent)do { } while(0);
2332 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset)do { } while(0);
2333 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc)do { } while(0);
2334
2335 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent)do { } while(0);
2336 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset)do { } while(0);
2337 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0)do { } while(0);
2338
2339 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent)do { } while(0);
2340 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset)do { } while(0);
2341 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1)do { } while(0);
2342
2343 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio)do { } while(0);
2344
2345 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio)do { } while(0);
2346 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity)do { } while(0);
2347 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio)do { } while(0);
2348 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity)do { } while(0);
2349 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio)do { } while(0);
2350 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity)do { } while(0);
2351 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio)do { } while(0);
2352 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity)do { } while(0);
2353 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0)do { } while(0);
2354 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1)do { } while(0);
2355 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2)do { } while(0);
2356 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask)do { } while(0);
2357 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie)do { } while(0);
2358 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError)do { } while(0);
2359 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0])do { } while(0);
2360 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1])do { } while(0);
2361
2362 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled)do { } while(0);
2363 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent)do { } while(0);
2364 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq)do { } while(0);
2365
2366 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled)do { } while(0);
2367 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent)do { } while(0);
2368 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq)do { } while(0);
2369
2370 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding)do { } while(0);
2371 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq)do { } while(0);
2372
2373 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled)do { } while(0);
2374 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent)do { } while(0);
2375 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq)do { } while(0);
2376
2377 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled)do { } while(0);
2378 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth)do { } while(0);
2379 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0])do { } while(0);
2380 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1])do { } while(0);
2381 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2])do { } while(0);
2382
2383 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower)do { } while(0);
2384 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding)do { } while(0);
2385
2386 dev_info(smu->adev->dev, "XgmiLinkSpeed\n")do { } while(0);
2387 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
2388 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i])do { } while(0);
2389 dev_info(smu->adev->dev, "XgmiLinkWidth\n")do { } while(0);
2390 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
2391 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i])do { } while(0);
2392 dev_info(smu->adev->dev, "XgmiFclkFreq\n")do { } while(0);
2393 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
2394 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i])do { } while(0);
2395 dev_info(smu->adev->dev, "XgmiSocVoltage\n")do { } while(0);
2396 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
2397 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i])do { } while(0);
2398
2399 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled)do { } while(0);
2400 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled)do { } while(0);
2401 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0])do { } while(0);
2402 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1])do { } while(0);
2403
2404 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0])do { } while(0);
2405 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1])do { } while(0);
2406 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2])do { } while(0);
2407 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3])do { } while(0);
2408 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4])do { } while(0);
2409 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5])do { } while(0);
2410 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6])do { } while(0);
2411 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7])do { } while(0);
2412 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8])do { } while(0);
2413 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9])do { } while(0);
2414 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10])do { } while(0);
2415
2416 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0])do { } while(0);
2417 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1])do { } while(0);
2418 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2])do { } while(0);
2419 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3])do { } while(0);
2420 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4])do { } while(0);
2421 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5])do { } while(0);
2422 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6])do { } while(0);
2423 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7])do { } while(0);
2424}
2425
2426static void sienna_cichlid_fill_i2c_req(SwI2cRequest_t *req, bool_Bool write,
2427 uint8_t address, uint32_t numbytes,
2428 uint8_t *data)
2429{
2430 int i;
2431
2432 req->I2CcontrollerPort = 0;
2433 req->I2CSpeed = 2;
2434 req->SlaveAddress = address;
2435 req->NumCmds = numbytes;
2436
2437 for (i = 0; i < numbytes; i++) {
2438 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
2439
2440 /* First 2 bytes are always write for lower 2b EEPROM address */
2441 if (i < 2)
2442 cmd->CmdConfig = CMDCONFIG_READWRITE_MASK(1 << 2);
2443 else
2444 cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK(1 << 2) : 0;
2445
2446
2447 /* Add RESTART for read after address filled */
2448 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK(1 << 1) : 0;
2449
2450 /* Add STOP in the end */
2451 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK(1 << 0) : 0;
2452
2453 /* Fill with data regardless if read or write to simplify code */
2454 cmd->ReadWriteData = data[i];
2455 }
2456}
2457
2458static int sienna_cichlid_i2c_read_data(struct i2c_adapter *control,
2459 uint8_t address,
2460 uint8_t *data,
2461 uint32_t numbytes)
2462{
2463 uint32_t i, ret = 0;
2464 SwI2cRequest_t req;
2465 struct amdgpu_device *adev = to_amdgpu_device(control)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (control); (struct amdgpu_device *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_device, pm.smu_i2c) );}))
;
2466 struct smu_table_context *smu_table = &adev->smu.smu_table;
2467 struct smu_table *table = &smu_table->driver_table;
2468
2469 if (numbytes > MAX_SW_I2C_COMMANDS24) {
2470 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 24)
2471 numbytes, MAX_SW_I2C_COMMANDS)printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 24)
;
2472 return -EINVAL22;
2473 }
2474
2475 memset(&req, 0, sizeof(req))__builtin_memset((&req), (0), (sizeof(req)));
2476 sienna_cichlid_fill_i2c_req(&req, false0, address, numbytes, data);
2477
2478 mutex_lock(&adev->smu.mutex)rw_enter_write(&adev->smu.mutex);
2479 /* Now read data starting with that address */
2480 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
2481 true1);
2482 mutex_unlock(&adev->smu.mutex)rw_exit_write(&adev->smu.mutex);
2483
2484 if (!ret) {
2485 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
2486
2487 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
2488 for (i = 0; i < numbytes; i++)
2489 data[i] = res->SwI2cCmds[i].ReadWriteData;
2490
2491 dev_dbg(adev->dev, "sienna_cichlid_i2c_read_data, address = %x, bytes = %d, data :",do { } while(0)
2492 (uint16_t)address, numbytes)do { } while(0);
2493
2494 print_hex_dump(KERN_DEBUG"\0017", "data: ", DUMP_PREFIX_NONE,
2495 8, 1, data, numbytes, false0);
2496 } else
2497 dev_err(adev->dev, "sienna_cichlid_i2c_read_data - error occurred :%x", ret)printf("drm:pid%d:%s *ERROR* " "sienna_cichlid_i2c_read_data - error occurred :%x"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
2498
2499 return ret;
2500}
2501
2502static int sienna_cichlid_i2c_write_data(struct i2c_adapter *control,
2503 uint8_t address,
2504 uint8_t *data,
2505 uint32_t numbytes)
2506{
2507 uint32_t ret;
2508 SwI2cRequest_t req;
2509 struct amdgpu_device *adev = to_amdgpu_device(control)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (control); (struct amdgpu_device *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_device, pm.smu_i2c) );}))
;
2510
2511 if (numbytes > MAX_SW_I2C_COMMANDS24) {
2512 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 24)
2513 numbytes, MAX_SW_I2C_COMMANDS)printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 24)
;
2514 return -EINVAL22;
2515 }
2516
2517 memset(&req, 0, sizeof(req))__builtin_memset((&req), (0), (sizeof(req)));
2518 sienna_cichlid_fill_i2c_req(&req, true1, address, numbytes, data);
2519
2520 mutex_lock(&adev->smu.mutex)rw_enter_write(&adev->smu.mutex);
2521 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true1);
2522 mutex_unlock(&adev->smu.mutex)rw_exit_write(&adev->smu.mutex);
2523
2524 if (!ret) {
2525 dev_dbg(adev->dev, "sienna_cichlid_i2c_write(), address = %x, bytes = %d , data: ",do { } while(0)
2526 (uint16_t)address, numbytes)do { } while(0);
2527
2528 print_hex_dump(KERN_DEBUG"\0017", "data: ", DUMP_PREFIX_NONE,
2529 8, 1, data, numbytes, false0);
2530 /*
2531 * According to EEPROM spec there is a MAX of 10 ms required for
2532 * EEPROM to flush internal RX buffer after STOP was issued at the
2533 * end of write transaction. During this time the EEPROM will not be
2534 * responsive to any more commands - so wait a bit more.
2535 */
2536 drm_msleep(10)mdelay(10);
2537
2538 } else
2539 dev_err(adev->dev, "sienna_cichlid_i2c_write- error occurred :%x", ret)printf("drm:pid%d:%s *ERROR* " "sienna_cichlid_i2c_write- error occurred :%x"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
2540
2541 return ret;
2542}
2543
2544static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
2545 struct i2c_msg *msgs, int num)
2546{
2547 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2548 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS24] = { 0 };
2549
2550 for (i = 0; i < num; i++) {
2551 /*
2552 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2553 * once and hence the data needs to be spliced into chunks and sent each
2554 * chunk separately
2555 */
2556 data_size = msgs[i].len - 2;
2557 data_chunk_size = MAX_SW_I2C_COMMANDS24 - 2;
2558 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2559 data_ptr = msgs[i].buf + 2;
2560
2561 for (j = 0; j < data_size / data_chunk_size; j++) {
2562 /* Insert the EEPROM dest addess, bits 0-15 */
2563 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2564 data_chunk[1] = (next_eeprom_addr & 0xff);
2565
2566 if (msgs[i].flags & I2C_M_RD0x0001) {
2567 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2568 (uint8_t)msgs[i].addr,
2569 data_chunk, MAX_SW_I2C_COMMANDS24);
2570
2571 memcpy(data_ptr, data_chunk + 2, data_chunk_size)__builtin_memcpy((data_ptr), (data_chunk + 2), (data_chunk_size
))
;
2572 } else {
2573
2574 memcpy(data_chunk + 2, data_ptr, data_chunk_size)__builtin_memcpy((data_chunk + 2), (data_ptr), (data_chunk_size
))
;
2575
2576 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2577 (uint8_t)msgs[i].addr,
2578 data_chunk, MAX_SW_I2C_COMMANDS24);
2579 }
2580
2581 if (ret) {
2582 num = -EIO5;
2583 goto fail;
2584 }
2585
2586 next_eeprom_addr += data_chunk_size;
2587 data_ptr += data_chunk_size;
2588 }
2589
2590 if (data_size % data_chunk_size) {
2591 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2592 data_chunk[1] = (next_eeprom_addr & 0xff);
2593
2594 if (msgs[i].flags & I2C_M_RD0x0001) {
2595 ret = sienna_cichlid_i2c_read_data(i2c_adap,
2596 (uint8_t)msgs[i].addr,
2597 data_chunk, (data_size % data_chunk_size) + 2);
2598
2599 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size)__builtin_memcpy((data_ptr), (data_chunk + 2), (data_size % data_chunk_size
))
;
2600 } else {
2601 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size)__builtin_memcpy((data_chunk + 2), (data_ptr), (data_size % data_chunk_size
))
;
2602
2603 ret = sienna_cichlid_i2c_write_data(i2c_adap,
2604 (uint8_t)msgs[i].addr,
2605 data_chunk, (data_size % data_chunk_size) + 2);
2606 }
2607
2608 if (ret) {
2609 num = -EIO5;
2610 goto fail;
2611 }
2612 }
2613 }
2614
2615fail:
2616 return num;
2617}
2618
2619static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
2620{
2621 return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0;
2622}
2623
2624
2625static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
2626 .master_xfer = sienna_cichlid_i2c_xfer,
2627 .functionality = sienna_cichlid_i2c_func,
2628};
2629
2630static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2631{
2632 struct amdgpu_device *adev = to_amdgpu_device(control)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (control); (struct amdgpu_device *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_device, pm.smu_i2c) );}))
;
2633 int res;
2634
2635#ifdef __linux__
2636 control->owner = THIS_MODULE((void *)0);
2637 control->class = I2C_CLASS_SPD;
2638 control->dev.parent = &adev->pdev->dev;
2639#endif
2640 control->algo = &sienna_cichlid_i2c_algo;
2641 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2642
2643 res = i2c_add_adapter(control)0;
2644 if (res)
2645 DRM_ERROR("Failed to register hw i2c, err: %d\n", res)__drm_err("Failed to register hw i2c, err: %d\n", res);
2646
2647 return res;
2648}
2649
2650static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2651{
2652 i2c_del_adapter(control);
2653}
2654
2655static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
2656 void **table)
2657{
2658 struct smu_table_context *smu_table = &smu->smu_table;
2659 struct gpu_metrics_v1_0 *gpu_metrics =
2660 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2661 SmuMetrics_t metrics;
2662 int ret = 0;
2663
2664 ret = smu_cmn_get_metrics_table(smu,
2665 &metrics,
2666 true1);
2667 if (ret)
2668 return ret;
2669
2670 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2671
2672 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2673 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2674 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2675 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2676 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2677 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2678
2679 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2680 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2681 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2682
2683 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2684 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2685
2686 if (metrics.AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD15)
2687 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
2688 else
2689 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
2690 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
2691 gpu_metrics->average_vclk0_frequency = metrics.AverageVclk0Frequency;
2692 gpu_metrics->average_dclk0_frequency = metrics.AverageDclk0Frequency;
2693 gpu_metrics->average_vclk1_frequency = metrics.AverageVclk1Frequency;
2694 gpu_metrics->average_dclk1_frequency = metrics.AverageDclk1Frequency;
2695
2696 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2697 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2698 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2699 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK_0];
2700 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK_0];
2701 gpu_metrics->current_vclk1 = metrics.CurrClock[PPCLK_VCLK_1];
2702 gpu_metrics->current_dclk1 = metrics.CurrClock[PPCLK_DCLK_1];
2703
2704 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2705
2706 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2707
2708 gpu_metrics->pcie_link_width =
2709 smu_v11_0_get_current_pcie_link_width(smu);
2710 gpu_metrics->pcie_link_speed =
2711 smu_v11_0_get_current_pcie_link_speed(smu);
2712
2713 *table = (void *)gpu_metrics;
2714
2715 return sizeof(struct gpu_metrics_v1_0);
2716}
2717
2718static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
2719{
2720 struct smu_table_context *table_context = &smu->smu_table;
2721 PPTable_t *smc_pptable = table_context->driver_pptable;
2722
2723 /*
2724 * Skip the MGpuFanBoost setting for those ASICs
2725 * which do not support it
2726 */
2727 if (!smc_pptable->MGpuFanBoostLimitRpm)
2728 return 0;
2729
2730 return smu_cmn_send_smc_msg_with_param(smu,
2731 SMU_MSG_SetMGpuFanBoostLimitRpm,
2732 0,
2733 NULL((void *)0));
2734}
2735
2736static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
2737 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
2738 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
2739 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
2740 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
2741 .i2c_init = sienna_cichlid_i2c_control_init,
2742 .i2c_fini = sienna_cichlid_i2c_control_fini,
2743 .print_clk_levels = sienna_cichlid_print_clk_levels,
2744 .force_clk_levels = sienna_cichlid_force_clk_levels,
2745 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
2746 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
2747 .display_config_changed = sienna_cichlid_display_config_changed,
2748 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
2749 .is_dpm_running = sienna_cichlid_is_dpm_running,
2750 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
2751 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
2752 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
2753 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
2754 .read_sensor = sienna_cichlid_read_sensor,
2755 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
2756 .set_performance_level = smu_v11_0_set_performance_level,
2757 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
2758 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
2759 .get_power_limit = sienna_cichlid_get_power_limit,
2760 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
2761 .dump_pptable = sienna_cichlid_dump_pptable,
2762 .init_microcode = smu_v11_0_init_microcode,
2763 .load_microcode = smu_v11_0_load_microcode,
2764 .init_smc_tables = sienna_cichlid_init_smc_tables,
2765 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2766 .init_power = smu_v11_0_init_power,
2767 .fini_power = smu_v11_0_fini_power,
2768 .check_fw_status = smu_v11_0_check_fw_status,
2769 .setup_pptable = sienna_cichlid_setup_pptable,
2770 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2771 .check_fw_version = smu_v11_0_check_fw_version,
2772 .write_pptable = smu_cmn_write_pptable,
2773 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2774 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2775 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2776 .system_features_control = smu_v11_0_system_features_control,
2777 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2778 .send_smc_msg = smu_cmn_send_smc_msg,
2779 .init_display_count = NULL((void *)0),
2780 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2781 .get_enabled_mask = smu_cmn_get_enabled_mask,
2782 .feature_is_enabled = smu_cmn_feature_is_enabled,
2783 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2784 .notify_display_change = NULL((void *)0),
2785 .set_power_limit = smu_v11_0_set_power_limit,
2786 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2787 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2788 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2789 .set_min_dcef_deep_sleep = NULL((void *)0),
2790 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2791 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2792 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2793 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2794 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2795 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2796 .gfx_off_control = smu_v11_0_gfx_off_control,
2797 .register_irq_handler = smu_v11_0_register_irq_handler,
2798 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2799 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2800 .baco_is_support= sienna_cichlid_is_baco_supported,
2801 .baco_get_state = smu_v11_0_baco_get_state,
2802 .baco_set_state = smu_v11_0_baco_set_state,
2803 .baco_enter = smu_v11_0_baco_enter,
2804 .baco_exit = smu_v11_0_baco_exit,
2805 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
2806 .mode1_reset = smu_v11_0_mode1_reset,
2807 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
2808 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2809 .run_btc = sienna_cichlid_run_btc,
2810 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2811 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2812 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
2813 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
2814 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2815 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2816 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
2817 .interrupt_work = smu_v11_0_interrupt_work,
2818};
2819
2820void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
2821{
2822 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
2823 smu->message_map = sienna_cichlid_message_map;
2824 smu->clock_map = sienna_cichlid_clk_map;
2825 smu->feature_map = sienna_cichlid_feature_mask_map;
2826 smu->table_map = sienna_cichlid_table_map;
2827 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
2828 smu->workload_map = sienna_cichlid_workload_map;
2829}