File: | dev/pci/drm/i915/display/intel_dvo.c |
Warning: | line 539, column 4 Value stored to 'encoder_type' is never read |
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1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
3 | * Copyright © 2006-2007 Intel Corporation |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a |
6 | * copy of this software and associated documentation files (the "Software"), |
7 | * to deal in the Software without restriction, including without limitation |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
9 | * and/or sell copies of the Software, and to permit persons to whom the |
10 | * Software is furnished to do so, subject to the following conditions: |
11 | * |
12 | * The above copyright notice and this permission notice (including the next |
13 | * paragraph) shall be included in all copies or substantial portions of the |
14 | * Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. |
23 | * |
24 | * Authors: |
25 | * Eric Anholt <eric@anholt.net> |
26 | */ |
27 | |
28 | #include <linux/i2c.h> |
29 | #include <linux/slab.h> |
30 | |
31 | #include <drm/drm_atomic_helper.h> |
32 | #include <drm/drm_crtc.h> |
33 | |
34 | #include "i915_drv.h" |
35 | #include "intel_connector.h" |
36 | #include "intel_display_types.h" |
37 | #include "intel_dvo.h" |
38 | #include "intel_dvo_dev.h" |
39 | #include "intel_gmbus.h" |
40 | #include "intel_panel.h" |
41 | |
42 | #define INTEL_DVO_CHIP_NONE0 0 |
43 | #define INTEL_DVO_CHIP_LVDS1 1 |
44 | #define INTEL_DVO_CHIP_TMDS2 2 |
45 | #define INTEL_DVO_CHIP_TVOUT4 4 |
46 | #define INTEL_DVO_CHIP_LVDS_NO_FIXED5 5 |
47 | |
48 | #define SIL164_ADDR0x38 0x38 |
49 | #define CH7xxx_ADDR0x76 0x76 |
50 | #define TFP410_ADDR0x38 0x38 |
51 | #define NS2501_ADDR0x38 0x38 |
52 | |
53 | static const struct intel_dvo_device intel_dvo_devices[] = { |
54 | { |
55 | .type = INTEL_DVO_CHIP_TMDS2, |
56 | .name = "sil164", |
57 | .dvo_reg = DVOC((const i915_reg_t){ .reg = (0x61160) }), |
58 | .dvo_srcdim_reg = DVOC_SRCDIM((const i915_reg_t){ .reg = (0x61164) }), |
59 | .slave_addr = SIL164_ADDR0x38, |
60 | .dev_ops = &sil164_ops, |
61 | }, |
62 | { |
63 | .type = INTEL_DVO_CHIP_TMDS2, |
64 | .name = "ch7xxx", |
65 | .dvo_reg = DVOC((const i915_reg_t){ .reg = (0x61160) }), |
66 | .dvo_srcdim_reg = DVOC_SRCDIM((const i915_reg_t){ .reg = (0x61164) }), |
67 | .slave_addr = CH7xxx_ADDR0x76, |
68 | .dev_ops = &ch7xxx_ops, |
69 | }, |
70 | { |
71 | .type = INTEL_DVO_CHIP_TMDS2, |
72 | .name = "ch7xxx", |
73 | .dvo_reg = DVOC((const i915_reg_t){ .reg = (0x61160) }), |
74 | .dvo_srcdim_reg = DVOC_SRCDIM((const i915_reg_t){ .reg = (0x61164) }), |
75 | .slave_addr = 0x75, /* For some ch7010 */ |
76 | .dev_ops = &ch7xxx_ops, |
77 | }, |
78 | { |
79 | .type = INTEL_DVO_CHIP_LVDS1, |
80 | .name = "ivch", |
81 | .dvo_reg = DVOA((const i915_reg_t){ .reg = (0x61120) }), |
82 | .dvo_srcdim_reg = DVOA_SRCDIM((const i915_reg_t){ .reg = (0x61124) }), |
83 | .slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */ |
84 | .dev_ops = &ivch_ops, |
85 | }, |
86 | { |
87 | .type = INTEL_DVO_CHIP_TMDS2, |
88 | .name = "tfp410", |
89 | .dvo_reg = DVOC((const i915_reg_t){ .reg = (0x61160) }), |
90 | .dvo_srcdim_reg = DVOC_SRCDIM((const i915_reg_t){ .reg = (0x61164) }), |
91 | .slave_addr = TFP410_ADDR0x38, |
92 | .dev_ops = &tfp410_ops, |
93 | }, |
94 | { |
95 | .type = INTEL_DVO_CHIP_LVDS1, |
96 | .name = "ch7017", |
97 | .dvo_reg = DVOC((const i915_reg_t){ .reg = (0x61160) }), |
98 | .dvo_srcdim_reg = DVOC_SRCDIM((const i915_reg_t){ .reg = (0x61164) }), |
99 | .slave_addr = 0x75, |
100 | .gpio = GMBUS_PIN_DPB5, |
101 | .dev_ops = &ch7017_ops, |
102 | }, |
103 | { |
104 | .type = INTEL_DVO_CHIP_LVDS_NO_FIXED5, |
105 | .name = "ns2501", |
106 | .dvo_reg = DVOB((const i915_reg_t){ .reg = (0x61140) }), |
107 | .dvo_srcdim_reg = DVOB_SRCDIM((const i915_reg_t){ .reg = (0x61144) }), |
108 | .slave_addr = NS2501_ADDR0x38, |
109 | .dev_ops = &ns2501_ops, |
110 | }, |
111 | }; |
112 | |
113 | struct intel_dvo { |
114 | struct intel_encoder base; |
115 | |
116 | struct intel_dvo_device dev; |
117 | |
118 | struct intel_connector *attached_connector; |
119 | |
120 | bool_Bool panel_wants_dither; |
121 | }; |
122 | |
123 | static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder) |
124 | { |
125 | return container_of(encoder, struct intel_dvo, base)({ const __typeof( ((struct intel_dvo *)0)->base ) *__mptr = (encoder); (struct intel_dvo *)( (char *)__mptr - __builtin_offsetof (struct intel_dvo, base) );}); |
126 | } |
127 | |
128 | static struct intel_dvo *intel_attached_dvo(struct intel_connector *connector) |
129 | { |
130 | return enc_to_dvo(intel_attached_encoder(connector)); |
131 | } |
132 | |
133 | static bool_Bool intel_dvo_connector_get_hw_state(struct intel_connector *connector) |
134 | { |
135 | struct drm_device *dev = connector->base.dev; |
136 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
137 | struct intel_dvo *intel_dvo = intel_attached_dvo(connector); |
138 | u32 tmp; |
139 | |
140 | tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); |
141 | |
142 | if (!(tmp & DVO_ENABLE(1 << 31))) |
143 | return false0; |
144 | |
145 | return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev); |
146 | } |
147 | |
148 | static bool_Bool intel_dvo_get_hw_state(struct intel_encoder *encoder, |
149 | enum pipe *pipe) |
150 | { |
151 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
152 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
153 | u32 tmp; |
154 | |
155 | tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); |
156 | |
157 | *pipe = (tmp & DVO_PIPE_SEL_MASK(1 << 30)) >> DVO_PIPE_SEL_SHIFT30; |
158 | |
159 | return tmp & DVO_ENABLE(1 << 31); |
160 | } |
161 | |
162 | static void intel_dvo_get_config(struct intel_encoder *encoder, |
163 | struct intel_crtc_state *pipe_config) |
164 | { |
165 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
166 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
167 | u32 tmp, flags = 0; |
168 | |
169 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO)(1UL << (INTEL_OUTPUT_DVO)); |
170 | |
171 | tmp = intel_de_read(dev_priv, intel_dvo->dev.dvo_reg); |
172 | if (tmp & DVO_HSYNC_ACTIVE_HIGH(1 << 3)) |
173 | flags |= DRM_MODE_FLAG_PHSYNC(1<<0); |
174 | else |
175 | flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
176 | if (tmp & DVO_VSYNC_ACTIVE_HIGH(1 << 4)) |
177 | flags |= DRM_MODE_FLAG_PVSYNC(1<<2); |
178 | else |
179 | flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
180 | |
181 | pipe_config->hw.adjusted_mode.flags |= flags; |
182 | |
183 | pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; |
184 | } |
185 | |
186 | static void intel_disable_dvo(struct intel_atomic_state *state, |
187 | struct intel_encoder *encoder, |
188 | const struct intel_crtc_state *old_crtc_state, |
189 | const struct drm_connector_state *old_conn_state) |
190 | { |
191 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
192 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
193 | i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; |
194 | u32 temp = intel_de_read(dev_priv, dvo_reg); |
195 | |
196 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false0); |
197 | intel_de_write(dev_priv, dvo_reg, temp & ~DVO_ENABLE(1 << 31)); |
198 | intel_de_read(dev_priv, dvo_reg); |
199 | } |
200 | |
201 | static void intel_enable_dvo(struct intel_atomic_state *state, |
202 | struct intel_encoder *encoder, |
203 | const struct intel_crtc_state *pipe_config, |
204 | const struct drm_connector_state *conn_state) |
205 | { |
206 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
207 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
208 | i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; |
209 | u32 temp = intel_de_read(dev_priv, dvo_reg); |
210 | |
211 | intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, |
212 | &pipe_config->hw.mode, |
213 | &pipe_config->hw.adjusted_mode); |
214 | |
215 | intel_de_write(dev_priv, dvo_reg, temp | DVO_ENABLE(1 << 31)); |
216 | intel_de_read(dev_priv, dvo_reg); |
217 | |
218 | intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true1); |
219 | } |
220 | |
221 | static enum drm_mode_status |
222 | intel_dvo_mode_valid(struct drm_connector *connector, |
223 | struct drm_display_mode *mode) |
224 | { |
225 | struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
226 | const struct drm_display_mode *fixed_mode = |
227 | to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})->panel.fixed_mode; |
228 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
229 | int target_clock = mode->clock; |
230 | |
231 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)) |
232 | return MODE_NO_DBLESCAN; |
233 | |
234 | /* XXX: Validate clock range */ |
235 | |
236 | if (fixed_mode) { |
237 | if (mode->hdisplay > fixed_mode->hdisplay) |
238 | return MODE_PANEL; |
239 | if (mode->vdisplay > fixed_mode->vdisplay) |
240 | return MODE_PANEL; |
241 | |
242 | target_clock = fixed_mode->clock; |
243 | } |
244 | |
245 | if (target_clock > max_dotclk) |
246 | return MODE_CLOCK_HIGH; |
247 | |
248 | return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode); |
249 | } |
250 | |
251 | static int intel_dvo_compute_config(struct intel_encoder *encoder, |
252 | struct intel_crtc_state *pipe_config, |
253 | struct drm_connector_state *conn_state) |
254 | { |
255 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
256 | const struct drm_display_mode *fixed_mode = |
257 | intel_dvo->attached_connector->panel.fixed_mode; |
258 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
259 | |
260 | /* |
261 | * If we have timings from the BIOS for the panel, put them in |
262 | * to the adjusted mode. The CRTC will be set up for this mode, |
263 | * with the panel scaling set up to source from the H/VDisplay |
264 | * of the original mode. |
265 | */ |
266 | if (fixed_mode) |
267 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
268 | |
269 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)) |
270 | return -EINVAL22; |
271 | |
272 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
273 | |
274 | return 0; |
275 | } |
276 | |
277 | static void intel_dvo_pre_enable(struct intel_atomic_state *state, |
278 | struct intel_encoder *encoder, |
279 | const struct intel_crtc_state *pipe_config, |
280 | const struct drm_connector_state *conn_state) |
281 | { |
282 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
283 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
284 | const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
285 | struct intel_dvo *intel_dvo = enc_to_dvo(encoder); |
286 | enum pipe pipe = crtc->pipe; |
287 | u32 dvo_val; |
288 | i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg; |
289 | i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg; |
290 | |
291 | /* Save the data order, since I don't know what it should be set to. */ |
292 | dvo_val = intel_de_read(dev_priv, dvo_reg) & |
293 | (DVO_PRESERVE_MASK(0x7 << 24) | DVO_DATA_ORDER_GBRG(1 << 6)); |
294 | dvo_val |= DVO_DATA_ORDER_FP(1 << 14) | DVO_BORDER_ENABLE(1 << 7) | |
295 | DVO_BLANK_ACTIVE_HIGH(1 << 2); |
296 | |
297 | dvo_val |= DVO_PIPE_SEL(pipe)((pipe) << 30); |
298 | dvo_val |= DVO_PIPE_STALL(1 << 28); |
299 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
300 | dvo_val |= DVO_HSYNC_ACTIVE_HIGH(1 << 3); |
301 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
302 | dvo_val |= DVO_VSYNC_ACTIVE_HIGH(1 << 4); |
303 | |
304 | /*I915_WRITE(DVOB_SRCDIM, |
305 | (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) | |
306 | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/ |
307 | intel_de_write(dev_priv, dvo_srcdim_reg, |
308 | (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT12) | (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT0)); |
309 | /*I915_WRITE(DVOB, dvo_val);*/ |
310 | intel_de_write(dev_priv, dvo_reg, dvo_val); |
311 | } |
312 | |
313 | static enum drm_connector_status |
314 | intel_dvo_detect(struct drm_connector *connector, bool_Bool force) |
315 | { |
316 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->dev); |
317 | struct intel_dvo *intel_dvo = intel_attached_dvo(to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})); |
318 | |
319 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",__drm_dbg(DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector->base .id, connector->name) |
320 | connector->base.id, connector->name)__drm_dbg(DRM_UT_KMS, "[CONNECTOR:%d:%s]\n", connector->base .id, connector->name); |
321 | |
322 | if (!INTEL_DISPLAY_ENABLED(i915)(({ int __ret = !!((!((&(i915)->__info)->pipe_mask != 0))); if (__ret) printf("%s %s: " "%s", dev_driver_string((( &(i915)->drm))->dev), "", "drm_WARN_ON(" "!((&(i915)->__info)->pipe_mask != 0)" ")"); __builtin_expect(!!(__ret), 0); }), !(i915)->params .disable_display)) |
323 | return connector_status_disconnected; |
324 | |
325 | return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev); |
326 | } |
327 | |
328 | static int intel_dvo_get_modes(struct drm_connector *connector) |
329 | { |
330 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->dev); |
331 | const struct drm_display_mode *fixed_mode = |
332 | to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );})->panel.fixed_mode; |
333 | int num_modes; |
334 | |
335 | /* |
336 | * We should probably have an i2c driver get_modes function for those |
337 | * devices which will have a fixed set of modes determined by the chip |
338 | * (TV-out, for example), but for now with just TMDS and LVDS, |
339 | * that's not the case. |
340 | */ |
341 | num_modes = intel_ddc_get_modes(connector, |
342 | intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC4)); |
343 | if (num_modes) |
344 | return num_modes; |
345 | |
346 | if (fixed_mode) { |
347 | struct drm_display_mode *mode; |
348 | |
349 | mode = drm_mode_duplicate(connector->dev, fixed_mode); |
350 | if (mode) { |
351 | drm_mode_probed_add(connector, mode); |
352 | num_modes++; |
353 | } |
354 | } |
355 | |
356 | return num_modes; |
357 | } |
358 | |
359 | static const struct drm_connector_funcs intel_dvo_connector_funcs = { |
360 | .detect = intel_dvo_detect, |
361 | .late_register = intel_connector_register, |
362 | .early_unregister = intel_connector_unregister, |
363 | .destroy = intel_connector_destroy, |
364 | .fill_modes = drm_helper_probe_single_connector_modes, |
365 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
366 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
367 | }; |
368 | |
369 | static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = { |
370 | .mode_valid = intel_dvo_mode_valid, |
371 | .get_modes = intel_dvo_get_modes, |
372 | }; |
373 | |
374 | static void intel_dvo_enc_destroy(struct drm_encoder *encoder) |
375 | { |
376 | struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );})); |
377 | |
378 | if (intel_dvo->dev.dev_ops->destroy) |
379 | intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev); |
380 | |
381 | intel_encoder_destroy(encoder); |
382 | } |
383 | |
384 | static const struct drm_encoder_funcs intel_dvo_enc_funcs = { |
385 | .destroy = intel_dvo_enc_destroy, |
386 | }; |
387 | |
388 | /* |
389 | * Attempts to get a fixed panel timing for LVDS (currently only the i830). |
390 | * |
391 | * Other chips with DVO LVDS will need to extend this to deal with the LVDS |
392 | * chip being on DVOB/C and having multiple pipes. |
393 | */ |
394 | static struct drm_display_mode * |
395 | intel_dvo_get_current_mode(struct intel_encoder *encoder) |
396 | { |
397 | struct drm_display_mode *mode; |
398 | |
399 | mode = intel_encoder_current_mode(encoder); |
400 | if (mode) { |
401 | DRM_DEBUG_KMS("using current (BIOS) mode: ")__drm_dbg(DRM_UT_KMS, "using current (BIOS) mode: "); |
402 | drm_mode_debug_printmodeline(mode); |
403 | mode->type |= DRM_MODE_TYPE_PREFERRED(1<<3); |
404 | } |
405 | |
406 | return mode; |
407 | } |
408 | |
409 | static enum port intel_dvo_port(i915_reg_t dvo_reg) |
410 | { |
411 | if (i915_mmio_reg_equal(dvo_reg, DVOA((const i915_reg_t){ .reg = (0x61120) }))) |
412 | return PORT_A; |
413 | else if (i915_mmio_reg_equal(dvo_reg, DVOB((const i915_reg_t){ .reg = (0x61140) }))) |
414 | return PORT_B; |
415 | else |
416 | return PORT_C; |
417 | } |
418 | |
419 | void intel_dvo_init(struct drm_i915_privateinteldrm_softc *dev_priv) |
420 | { |
421 | struct intel_encoder *intel_encoder; |
422 | struct intel_dvo *intel_dvo; |
423 | struct intel_connector *intel_connector; |
424 | int i; |
425 | int encoder_type = DRM_MODE_ENCODER_NONE0; |
426 | |
427 | intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL(0x0001 | 0x0004)); |
428 | if (!intel_dvo) |
429 | return; |
430 | |
431 | intel_connector = intel_connector_alloc(); |
432 | if (!intel_connector) { |
433 | kfree(intel_dvo); |
434 | return; |
435 | } |
436 | |
437 | intel_dvo->attached_connector = intel_connector; |
438 | |
439 | intel_encoder = &intel_dvo->base; |
440 | |
441 | intel_encoder->disable = intel_disable_dvo; |
442 | intel_encoder->enable = intel_enable_dvo; |
443 | intel_encoder->get_hw_state = intel_dvo_get_hw_state; |
444 | intel_encoder->get_config = intel_dvo_get_config; |
445 | intel_encoder->compute_config = intel_dvo_compute_config; |
446 | intel_encoder->pre_enable = intel_dvo_pre_enable; |
447 | intel_connector->get_hw_state = intel_dvo_connector_get_hw_state; |
448 | |
449 | /* Now, try to find a controller */ |
450 | for (i = 0; i < ARRAY_SIZE(intel_dvo_devices)(sizeof((intel_dvo_devices)) / sizeof((intel_dvo_devices)[0]) ); i++) { |
451 | struct drm_connector *connector = &intel_connector->base; |
452 | const struct intel_dvo_device *dvo = &intel_dvo_devices[i]; |
453 | struct i2c_adapter *i2c; |
454 | int gpio; |
455 | bool_Bool dvoinit; |
456 | enum pipe pipe; |
457 | u32 dpll[I915_MAX_PIPES]; |
458 | enum port port; |
459 | |
460 | /* |
461 | * Allow the I2C driver info to specify the GPIO to be used in |
462 | * special cases, but otherwise default to what's defined |
463 | * in the spec. |
464 | */ |
465 | if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio)) |
466 | gpio = dvo->gpio; |
467 | else if (dvo->type == INTEL_DVO_CHIP_LVDS1) |
468 | gpio = GMBUS_PIN_SSC1; |
469 | else |
470 | gpio = GMBUS_PIN_DPB5; |
471 | |
472 | /* |
473 | * Set up the I2C bus necessary for the chip we're probing. |
474 | * It appears that everything is on GPIOE except for panels |
475 | * on i830 laptops, which are on GPIOB (DVOA). |
476 | */ |
477 | i2c = intel_gmbus_get_adapter(dev_priv, gpio); |
478 | |
479 | intel_dvo->dev = *dvo; |
480 | |
481 | /* |
482 | * GMBUS NAK handling seems to be unstable, hence let the |
483 | * transmitter detection run in bit banging mode for now. |
484 | */ |
485 | intel_gmbus_force_bit(i2c, true1); |
486 | |
487 | /* |
488 | * ns2501 requires the DVO 2x clock before it will |
489 | * respond to i2c accesses, so make sure we have |
490 | * have the clock enabled before we attempt to |
491 | * initialize the device. |
492 | */ |
493 | for_each_pipe(dev_priv, pipe)for ((pipe) = 0; (pipe) < I915_MAX_PIPES; (pipe)++) if (!( (&(dev_priv)->__info)->pipe_mask & (1UL << (pipe)))) {} else { |
494 | dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) })); |
495 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), |
496 | dpll[pipe] | DPLL_DVO_2X_MODE(1 << 30)); |
497 | } |
498 | |
499 | dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c); |
500 | |
501 | /* restore the DVO 2x clock state to original */ |
502 | for_each_pipe(dev_priv, pipe)for ((pipe) = 0; (pipe) < I915_MAX_PIPES; (pipe)++) if (!( (&(dev_priv)->__info)->pipe_mask & (1UL << (pipe)))) {} else { |
503 | intel_de_write(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display_mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display_mmio_offset) + 0x6030) })[(pipe)])) }), dpll[pipe]); |
504 | } |
505 | |
506 | intel_gmbus_force_bit(i2c, false0); |
507 | |
508 | if (!dvoinit) |
509 | continue; |
510 | |
511 | port = intel_dvo_port(dvo->dvo_reg); |
512 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
513 | &intel_dvo_enc_funcs, encoder_type, |
514 | "DVO %c", port_name(port)((port) + 'A')); |
515 | |
516 | intel_encoder->type = INTEL_OUTPUT_DVO; |
517 | intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; |
518 | intel_encoder->port = port; |
519 | intel_encoder->pipe_mask = ~0; |
520 | |
521 | if (dvo->type != INTEL_DVO_CHIP_LVDS1) |
522 | intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) | |
523 | (1 << INTEL_OUTPUT_DVO); |
524 | |
525 | switch (dvo->type) { |
526 | case INTEL_DVO_CHIP_TMDS2: |
527 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT(1 << 1) | |
528 | DRM_CONNECTOR_POLL_DISCONNECT(1 << 2); |
529 | drm_connector_init(&dev_priv->drm, connector, |
530 | &intel_dvo_connector_funcs, |
531 | DRM_MODE_CONNECTOR_DVII2); |
532 | encoder_type = DRM_MODE_ENCODER_TMDS2; |
533 | break; |
534 | case INTEL_DVO_CHIP_LVDS_NO_FIXED5: |
535 | case INTEL_DVO_CHIP_LVDS1: |
536 | drm_connector_init(&dev_priv->drm, connector, |
537 | &intel_dvo_connector_funcs, |
538 | DRM_MODE_CONNECTOR_LVDS7); |
539 | encoder_type = DRM_MODE_ENCODER_LVDS3; |
Value stored to 'encoder_type' is never read | |
540 | break; |
541 | } |
542 | |
543 | drm_connector_helper_add(connector, |
544 | &intel_dvo_connector_helper_funcs); |
545 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; |
546 | connector->interlace_allowed = false0; |
547 | connector->doublescan_allowed = false0; |
548 | |
549 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
550 | if (dvo->type == INTEL_DVO_CHIP_LVDS1) { |
551 | /* |
552 | * For our LVDS chipsets, we should hopefully be able |
553 | * to dig the fixed panel mode out of the BIOS data. |
554 | * However, it's in a different format from the BIOS |
555 | * data on chipsets with integrated LVDS (stored in AIM |
556 | * headers, likely), so for now, just get the current |
557 | * mode being output through DVO. |
558 | */ |
559 | intel_panel_init(&intel_connector->panel, |
560 | intel_dvo_get_current_mode(intel_encoder), |
561 | NULL((void *)0)); |
562 | intel_dvo->panel_wants_dither = true1; |
563 | } |
564 | |
565 | return; |
566 | } |
567 | |
568 | kfree(intel_dvo); |
569 | kfree(intel_connector); |
570 | } |