/usr/src/sys/dev/pci/drm/radeon/ni.c

Bug Summary

File:	dev/pci/drm/radeon/ni.c
Warning:	line 790, column 6 Access to field 'size' results in a dereference of a null pointer (loaded from field 'me_fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ni.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/radeon/ni.c

/usr/src/sys/dev/pci/drm/radeon/ni.c

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1/*
* Copyright 2010 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Alex Deucher
*/

25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/slab.h>

30#include <drm/radeon_drm.h>

32#include "atom.h"
33#include "cayman_blit_shaders.h"
34#include "clearstate_cayman.h"
35#include "ni_reg.h"
36#include "nid.h"
37#include "radeon.h"
38#include "radeon_asic.h"
39#include "radeon_audio.h"
40#include "radeon_ucode.h"

42/*
* Indirect registers accessor
*/
45u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
46{
unsigned long flags;
u32 r;

spin_lock_irqsave(&rdev->smc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->smc_idx_lock); } while
 (0);
WREG32(TN_SMC_IND_INDEX_0, (reg))r100_mm_wreg(rdev, (0x200), ((reg)), 0);
r = RREG32(TN_SMC_IND_DATA_0)r100_mm_rreg(rdev, (0x204), 0);
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->smc_idx_lock); } while
 (0);
return r;
55}

57void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
58{
unsigned long flags;

spin_lock_irqsave(&rdev->smc_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->smc_idx_lock); } while
 (0);
WREG32(TN_SMC_IND_INDEX_0, (reg))r100_mm_wreg(rdev, (0x200), ((reg)), 0);
WREG32(TN_SMC_IND_DATA_0, (v))r100_mm_wreg(rdev, (0x204), ((v)), 0);
spin_unlock_irqrestore(&rdev->smc_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->smc_idx_lock); } while
 (0);
65}

67static const u32 tn_rlc_save_restore_register_list[] =
68{
0x98fc,
0x98f0,
0x9834,
0x9838,
0x9870,
0x9874,
0x8a14,
0x8b24,
0x8bcc,
0x8b10,
0x8c30,
0x8d00,
0x8d04,
0x8c00,
0x8c04,
0x8c10,
0x8c14,
0x8d8c,
0x8cf0,
0x8e38,
0x9508,
0x9688,
0x9608,
0x960c,
0x9610,
0x9614,
0x88c4,
0x8978,
0x88d4,
0x900c,
0x9100,
0x913c,
0x90e8,
0x9354,
0xa008,
0x98f8,
0x9148,
0x914c,
0x3f94,
0x98f4,
0x9b7c,
0x3f8c,
0x8950,
0x8954,
0x8a18,
0x8b28,
0x9144,
0x3f90,
0x915c,
0x9160,
0x9178,
0x917c,
0x9180,
0x918c,
0x9190,
0x9194,
0x9198,
0x919c,
0x91a8,
0x91ac,
0x91b0,
0x91b4,
0x91b8,
0x91c4,
0x91c8,
0x91cc,
0x91d0,
0x91d4,
0x91e0,
0x91e4,
0x91ec,
0x91f0,
0x91f4,
0x9200,
0x9204,
0x929c,
0x8030,
0x9150,
0x9a60,
0x920c,
0x9210,
0x9228,
0x922c,
0x9244,
0x9248,
0x91e8,
0x9294,
0x9208,
0x9224,
0x9240,
0x9220,
0x923c,
0x9258,
0x9744,
0xa200,
0xa204,
0xa208,
0xa20c,
0x8d58,
0x9030,
0x9034,
0x9038,
0x903c,
0x9040,
0x9654,
0x897c,
0xa210,
0xa214,
0x9868,
0xa02c,
0x9664,
0x9698,
0x949c,
0x8e10,
0x8e18,
0x8c50,
0x8c58,
0x8c60,
0x8c68,
0x89b4,
0x9830,
0x802c,
191};

193extern bool_Bool evergreen_is_display_hung(struct radeon_device *rdev);
194extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
195extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
196extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
197extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
198extern void evergreen_mc_program(struct radeon_device *rdev);
199extern void evergreen_irq_suspend(struct radeon_device *rdev);
200extern int evergreen_mc_init(struct radeon_device *rdev);
201extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
202extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
203extern void evergreen_program_aspm(struct radeon_device *rdev);
204extern void sumo_rlc_fini(struct radeon_device *rdev);
205extern int sumo_rlc_init(struct radeon_device *rdev);
206extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);

208/* Firmware Names */
209MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
210MODULE_FIRMWARE("radeon/BARTS_me.bin");
211MODULE_FIRMWARE("radeon/BARTS_mc.bin");
212MODULE_FIRMWARE("radeon/BARTS_smc.bin");
213MODULE_FIRMWARE("radeon/BTC_rlc.bin");
214MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
215MODULE_FIRMWARE("radeon/TURKS_me.bin");
216MODULE_FIRMWARE("radeon/TURKS_mc.bin");
217MODULE_FIRMWARE("radeon/TURKS_smc.bin");
218MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
219MODULE_FIRMWARE("radeon/CAICOS_me.bin");
220MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
221MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
222MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
223MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
224MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
225MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
226MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
227MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
228MODULE_FIRMWARE("radeon/ARUBA_me.bin");
229MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");


232static const u32 cayman_golden_registers2[] =
233{
0x3e5c, 0xffffffff, 0x00000000,
0x3e48, 0xffffffff, 0x00000000,
0x3e4c, 0xffffffff, 0x00000000,
0x3e64, 0xffffffff, 0x00000000,
0x3e50, 0xffffffff, 0x00000000,
0x3e60, 0xffffffff, 0x00000000
240};

242static const u32 cayman_golden_registers[] =
243{
0x5eb4, 0xffffffff, 0x00000002,
0x5e78, 0x8f311ff1, 0x001000f0,
0x3f90, 0xffff0000, 0xff000000,
0x9148, 0xffff0000, 0xff000000,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0xc78, 0x00000080, 0x00000080,
0xbd4, 0x70073777, 0x00011003,
0xd02c, 0xbfffff1f, 0x08421000,
0xd0b8, 0x73773777, 0x02011003,
0x5bc0, 0x00200000, 0x50100000,
0x98f8, 0x33773777, 0x02011003,
0x98fc, 0xffffffff, 0x76541032,
0x7030, 0x31000311, 0x00000011,
0x2f48, 0x33773777, 0x42010001,
0x6b28, 0x00000010, 0x00000012,
0x7728, 0x00000010, 0x00000012,
0x10328, 0x00000010, 0x00000012,
0x10f28, 0x00000010, 0x00000012,
0x11b28, 0x00000010, 0x00000012,
0x12728, 0x00000010, 0x00000012,
0x240c, 0x000007ff, 0x00000000,
0x8a14, 0xf000001f, 0x00000007,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b10, 0x0000ff0f, 0x00000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x10c, 0x00000001, 0x00010003,
0xa02c, 0xffffffff, 0x0000009b,
0x913c, 0x0000010f, 0x01000100,
0x8c04, 0xf8ff00ff, 0x40600060,
0x28350, 0x00000f01, 0x00000000,
0x9508, 0x3700001f, 0x00000002,
0x960c, 0xffffffff, 0x54763210,
0x88c4, 0x001f3ae3, 0x00000082,
0x88d0, 0xffffffff, 0x0f40df40,
0x88d4, 0x0000001f, 0x00000010,
0x8974, 0xffffffff, 0x00000000
281};

283static const u32 dvst_golden_registers2[] =
284{
0x8f8, 0xffffffff, 0,
0x8fc, 0x00380000, 0,
0x8f8, 0xffffffff, 1,
0x8fc, 0x0e000000, 0
289};

291static const u32 dvst_golden_registers[] =
292{
0x690, 0x3fff3fff, 0x20c00033,
0x918c, 0x0fff0fff, 0x00010006,
0x91a8, 0x0fff0fff, 0x00010006,
0x9150, 0xffffdfff, 0x6e944040,
0x917c, 0x0fff0fff, 0x00030002,
0x9198, 0x0fff0fff, 0x00030002,
0x915c, 0x0fff0fff, 0x00010000,
0x3f90, 0xffff0001, 0xff000000,
0x9178, 0x0fff0fff, 0x00070000,
0x9194, 0x0fff0fff, 0x00070000,
0x9148, 0xffff0001, 0xff000000,
0x9190, 0x0fff0fff, 0x00090008,
0x91ac, 0x0fff0fff, 0x00090008,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x929c, 0x00000fff, 0x00000001,
0x55e4, 0xff607fff, 0xfc000100,
0x8a18, 0xff000fff, 0x00000100,
0x8b28, 0xff000fff, 0x00000100,
0x9144, 0xfffc0fff, 0x00000100,
0x6ed8, 0x00010101, 0x00010000,
0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400,
0x9838, 0xfffffffe, 0x00000000,
0xd0c0, 0xff000fff, 0x00000100,
0xd02c, 0xbfffff1f, 0x08421000,
0xd0b8, 0x73773777, 0x12010001,
0x5bb0, 0x000000f0, 0x00000070,
0x98f8, 0x73773777, 0x12010001,
0x98fc, 0xffffffff, 0x00000010,
0x9b7c, 0x00ff0000, 0x00fc0000,
0x8030, 0x00001f0f, 0x0000100a,
0x2f48, 0x73773777, 0x12010001,
0x2408, 0x00030000, 0x000c007f,
0x8a14, 0xf000003f, 0x00000007,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b10, 0x0000ff0f, 0x00000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x4d8, 0x00000fff, 0x00000100,
0xa008, 0xffffffff, 0x00010000,
0x913c, 0xffff03ff, 0x01000100,
0x8c00, 0x000000ff, 0x00000003,
0x8c04, 0xf8ff00ff, 0x40600060,
0x8cf0, 0x1fff1fff, 0x08e00410,
0x28350, 0x00000f01, 0x00000000,
0x9508, 0xf700071f, 0x00000002,
0x960c, 0xffffffff, 0x54763210,
0x20ef8, 0x01ff01ff, 0x00000002,
0x20e98, 0xfffffbff, 0x00200000,
0x2015c, 0xffffffff, 0x00000f40,
0x88c4, 0x001f3ae3, 0x00000082,
0x8978, 0x3fffffff, 0x04050140,
0x88d4, 0x0000001f, 0x00000010,
0x8974, 0xffffffff, 0x00000000
347};

349static const u32 scrapper_golden_registers[] =
350{
0x690, 0x3fff3fff, 0x20c00033,
0x918c, 0x0fff0fff, 0x00010006,
0x918c, 0x0fff0fff, 0x00010006,
0x91a8, 0x0fff0fff, 0x00010006,
0x91a8, 0x0fff0fff, 0x00010006,
0x9150, 0xffffdfff, 0x6e944040,
0x9150, 0xffffdfff, 0x6e944040,
0x917c, 0x0fff0fff, 0x00030002,
0x917c, 0x0fff0fff, 0x00030002,
0x9198, 0x0fff0fff, 0x00030002,
0x9198, 0x0fff0fff, 0x00030002,
0x915c, 0x0fff0fff, 0x00010000,
0x915c, 0x0fff0fff, 0x00010000,
0x3f90, 0xffff0001, 0xff000000,
0x3f90, 0xffff0001, 0xff000000,
0x9178, 0x0fff0fff, 0x00070000,
0x9178, 0x0fff0fff, 0x00070000,
0x9194, 0x0fff0fff, 0x00070000,
0x9194, 0x0fff0fff, 0x00070000,
0x9148, 0xffff0001, 0xff000000,
0x9148, 0xffff0001, 0xff000000,
0x9190, 0x0fff0fff, 0x00090008,
0x9190, 0x0fff0fff, 0x00090008,
0x91ac, 0x0fff0fff, 0x00090008,
0x91ac, 0x0fff0fff, 0x00090008,
0x3f94, 0xffff0000, 0xff000000,
0x3f94, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x914c, 0xffff0000, 0xff000000,
0x929c, 0x00000fff, 0x00000001,
0x929c, 0x00000fff, 0x00000001,
0x55e4, 0xff607fff, 0xfc000100,
0x8a18, 0xff000fff, 0x00000100,
0x8a18, 0xff000fff, 0x00000100,
0x8b28, 0xff000fff, 0x00000100,
0x8b28, 0xff000fff, 0x00000100,
0x9144, 0xfffc0fff, 0x00000100,
0x9144, 0xfffc0fff, 0x00000100,
0x6ed8, 0x00010101, 0x00010000,
0x9830, 0xffffffff, 0x00000000,
0x9830, 0xffffffff, 0x00000000,
0x9834, 0xf00fffff, 0x00000400,
0x9834, 0xf00fffff, 0x00000400,
0x9838, 0xfffffffe, 0x00000000,
0x9838, 0xfffffffe, 0x00000000,
0xd0c0, 0xff000fff, 0x00000100,
0xd02c, 0xbfffff1f, 0x08421000,
0xd02c, 0xbfffff1f, 0x08421000,
0xd0b8, 0x73773777, 0x12010001,
0xd0b8, 0x73773777, 0x12010001,
0x5bb0, 0x000000f0, 0x00000070,
0x98f8, 0x73773777, 0x12010001,
0x98f8, 0x73773777, 0x12010001,
0x98fc, 0xffffffff, 0x00000010,
0x98fc, 0xffffffff, 0x00000010,
0x9b7c, 0x00ff0000, 0x00fc0000,
0x9b7c, 0x00ff0000, 0x00fc0000,
0x8030, 0x00001f0f, 0x0000100a,
0x8030, 0x00001f0f, 0x0000100a,
0x2f48, 0x73773777, 0x12010001,
0x2f48, 0x73773777, 0x12010001,
0x2408, 0x00030000, 0x000c007f,
0x8a14, 0xf000003f, 0x00000007,
0x8a14, 0xf000003f, 0x00000007,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b24, 0x3fff3fff, 0x00ff0fff,
0x8b10, 0x0000ff0f, 0x00000000,
0x8b10, 0x0000ff0f, 0x00000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x28a4c, 0x07ffffff, 0x06000000,
0x4d8, 0x00000fff, 0x00000100,
0x4d8, 0x00000fff, 0x00000100,
0xa008, 0xffffffff, 0x00010000,
0xa008, 0xffffffff, 0x00010000,
0x913c, 0xffff03ff, 0x01000100,
0x913c, 0xffff03ff, 0x01000100,
0x90e8, 0x001fffff, 0x010400c0,
0x8c00, 0x000000ff, 0x00000003,
0x8c00, 0x000000ff, 0x00000003,
0x8c04, 0xf8ff00ff, 0x40600060,
0x8c04, 0xf8ff00ff, 0x40600060,
0x8c30, 0x0000000f, 0x00040005,
0x8cf0, 0x1fff1fff, 0x08e00410,
0x8cf0, 0x1fff1fff, 0x08e00410,
0x900c, 0x00ffffff, 0x0017071f,
0x28350, 0x00000f01, 0x00000000,
0x28350, 0x00000f01, 0x00000000,
0x9508, 0xf700071f, 0x00000002,
0x9508, 0xf700071f, 0x00000002,
0x9688, 0x00300000, 0x0017000f,
0x960c, 0xffffffff, 0x54763210,
0x960c, 0xffffffff, 0x54763210,
0x20ef8, 0x01ff01ff, 0x00000002,
0x20e98, 0xfffffbff, 0x00200000,
0x2015c, 0xffffffff, 0x00000f40,
0x88c4, 0x001f3ae3, 0x00000082,
0x88c4, 0x001f3ae3, 0x00000082,
0x8978, 0x3fffffff, 0x04050140,
0x8978, 0x3fffffff, 0x04050140,
0x88d4, 0x0000001f, 0x00000010,
0x88d4, 0x0000001f, 0x00000010,
0x8974, 0xffffffff, 0x00000000,
0x8974, 0xffffffff, 0x00000000
454};

456static void ni_init_golden_registers(struct radeon_device *rdev)
457{
switch (rdev->family) {
10
←
Control jumps to the 'default' case at line 502→
case CHIP_CAYMAN:
radeon_program_register_sequence(rdev,
				 cayman_golden_registers,
				 (const u32)ARRAY_SIZE(cayman_golden_registers)(sizeof((cayman_golden_registers)) / sizeof((cayman_golden_registers
)[0])));
radeon_program_register_sequence(rdev,
				 cayman_golden_registers2,
				 (const u32)ARRAY_SIZE(cayman_golden_registers2)(sizeof((cayman_golden_registers2)) / sizeof((cayman_golden_registers2
)[0])));
break;
case CHIP_ARUBA:
if ((rdev->pdev->device == 0x9900) ||
    (rdev->pdev->device == 0x9901) ||
    (rdev->pdev->device == 0x9903) ||
    (rdev->pdev->device == 0x9904) ||
    (rdev->pdev->device == 0x9905) ||
    (rdev->pdev->device == 0x9906) ||
    (rdev->pdev->device == 0x9907) ||
    (rdev->pdev->device == 0x9908) ||
    (rdev->pdev->device == 0x9909) ||
    (rdev->pdev->device == 0x990A) ||
    (rdev->pdev->device == 0x990B) ||
    (rdev->pdev->device == 0x990C) ||
    (rdev->pdev->device == 0x990D) ||
    (rdev->pdev->device == 0x990E) ||
    (rdev->pdev->device == 0x990F) ||
    (rdev->pdev->device == 0x9910) ||
    (rdev->pdev->device == 0x9913) ||
    (rdev->pdev->device == 0x9917) ||
    (rdev->pdev->device == 0x9918)) {
	radeon_program_register_sequence(rdev,
					 dvst_golden_registers,
					 (const u32)ARRAY_SIZE(dvst_golden_registers)(sizeof((dvst_golden_registers)) / sizeof((dvst_golden_registers
)[0])));
	radeon_program_register_sequence(rdev,
					 dvst_golden_registers2,
					 (const u32)ARRAY_SIZE(dvst_golden_registers2)(sizeof((dvst_golden_registers2)) / sizeof((dvst_golden_registers2
)[0])));
} else {
	radeon_program_register_sequence(rdev,
					 scrapper_golden_registers,
					 (const u32)ARRAY_SIZE(scrapper_golden_registers)(sizeof((scrapper_golden_registers)) / sizeof((scrapper_golden_registers
)[0])));
	radeon_program_register_sequence(rdev,
					 dvst_golden_registers2,
					 (const u32)ARRAY_SIZE(dvst_golden_registers2)(sizeof((dvst_golden_registers2)) / sizeof((dvst_golden_registers2
)[0])));
}
break;
default:
break;
11
←
 Execution continues on line 458→
}
505}
12
←
Returning without writing to 'rdev->family', which participates in a condition later→
13
←
Returning without writing to 'rdev->me_fw'→

507#define BTC_IO_MC_REGS_SIZE29 29

509static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE29][2] = {
{0x00000077, 0xff010100},
{0x00000078, 0x00000000},
{0x00000079, 0x00001434},
{0x0000007a, 0xcc08ec08},
{0x0000007b, 0x00040000},
{0x0000007c, 0x000080c0},
{0x0000007d, 0x09000000},
{0x0000007e, 0x00210404},
{0x00000081, 0x08a8e800},
{0x00000082, 0x00030444},
{0x00000083, 0x00000000},
{0x00000085, 0x00000001},
{0x00000086, 0x00000002},
{0x00000087, 0x48490000},
{0x00000088, 0x20244647},
{0x00000089, 0x00000005},
{0x0000008b, 0x66030000},
{0x0000008c, 0x00006603},
{0x0000008d, 0x00000100},
{0x0000008f, 0x00001c0a},
{0x00000090, 0xff000001},
{0x00000094, 0x00101101},
{0x00000095, 0x00000fff},
{0x00000096, 0x00116fff},
{0x00000097, 0x60010000},
{0x00000098, 0x10010000},
{0x00000099, 0x00006000},
{0x0000009a, 0x00001000},
{0x0000009f, 0x00946a00}
539};

541static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE29][2] = {
{0x00000077, 0xff010100},
{0x00000078, 0x00000000},
{0x00000079, 0x00001434},
{0x0000007a, 0xcc08ec08},
{0x0000007b, 0x00040000},
{0x0000007c, 0x000080c0},
{0x0000007d, 0x09000000},
{0x0000007e, 0x00210404},
{0x00000081, 0x08a8e800},
{0x00000082, 0x00030444},
{0x00000083, 0x00000000},
{0x00000085, 0x00000001},
{0x00000086, 0x00000002},
{0x00000087, 0x48490000},
{0x00000088, 0x20244647},
{0x00000089, 0x00000005},
{0x0000008b, 0x66030000},
{0x0000008c, 0x00006603},
{0x0000008d, 0x00000100},
{0x0000008f, 0x00001c0a},
{0x00000090, 0xff000001},
{0x00000094, 0x00101101},
{0x00000095, 0x00000fff},
{0x00000096, 0x00116fff},
{0x00000097, 0x60010000},
{0x00000098, 0x10010000},
{0x00000099, 0x00006000},
{0x0000009a, 0x00001000},
{0x0000009f, 0x00936a00}
571};

573static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE29][2] = {
{0x00000077, 0xff010100},
{0x00000078, 0x00000000},
{0x00000079, 0x00001434},
{0x0000007a, 0xcc08ec08},
{0x0000007b, 0x00040000},
{0x0000007c, 0x000080c0},
{0x0000007d, 0x09000000},
{0x0000007e, 0x00210404},
{0x00000081, 0x08a8e800},
{0x00000082, 0x00030444},
{0x00000083, 0x00000000},
{0x00000085, 0x00000001},
{0x00000086, 0x00000002},
{0x00000087, 0x48490000},
{0x00000088, 0x20244647},
{0x00000089, 0x00000005},
{0x0000008b, 0x66030000},
{0x0000008c, 0x00006603},
{0x0000008d, 0x00000100},
{0x0000008f, 0x00001c0a},
{0x00000090, 0xff000001},
{0x00000094, 0x00101101},
{0x00000095, 0x00000fff},
{0x00000096, 0x00116fff},
{0x00000097, 0x60010000},
{0x00000098, 0x10010000},
{0x00000099, 0x00006000},
{0x0000009a, 0x00001000},
{0x0000009f, 0x00916a00}
603};

605static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE29][2] = {
{0x00000077, 0xff010100},
{0x00000078, 0x00000000},
{0x00000079, 0x00001434},
{0x0000007a, 0xcc08ec08},
{0x0000007b, 0x00040000},
{0x0000007c, 0x000080c0},
{0x0000007d, 0x09000000},
{0x0000007e, 0x00210404},
{0x00000081, 0x08a8e800},
{0x00000082, 0x00030444},
{0x00000083, 0x00000000},
{0x00000085, 0x00000001},
{0x00000086, 0x00000002},
{0x00000087, 0x48490000},
{0x00000088, 0x20244647},
{0x00000089, 0x00000005},
{0x0000008b, 0x66030000},
{0x0000008c, 0x00006603},
{0x0000008d, 0x00000100},
{0x0000008f, 0x00001c0a},
{0x00000090, 0xff000001},
{0x00000094, 0x00101101},
{0x00000095, 0x00000fff},
{0x00000096, 0x00116fff},
{0x00000097, 0x60010000},
{0x00000098, 0x10010000},
{0x00000099, 0x00006000},
{0x0000009a, 0x00001000},
{0x0000009f, 0x00976b00}
635};

637int ni_mc_load_microcode(struct radeon_device *rdev)
638{
const __be32 *fw_data;
u32 mem_type, running, blackout = 0;
u32 *io_mc_regs;
int i, ucode_size, regs_size;

if (!rdev->mc_fw)
return -EINVAL22;

switch (rdev->family) {
case CHIP_BARTS:
io_mc_regs = (u32 *)&barts_io_mc_regs;
ucode_size = BTC_MC_UCODE_SIZE6024;
regs_size = BTC_IO_MC_REGS_SIZE29;
break;
case CHIP_TURKS:
io_mc_regs = (u32 *)&turks_io_mc_regs;
ucode_size = BTC_MC_UCODE_SIZE6024;
regs_size = BTC_IO_MC_REGS_SIZE29;
break;
case CHIP_CAICOS:
default:
io_mc_regs = (u32 *)&caicos_io_mc_regs;
ucode_size = BTC_MC_UCODE_SIZE6024;
regs_size = BTC_IO_MC_REGS_SIZE29;
break;
case CHIP_CAYMAN:
io_mc_regs = (u32 *)&cayman_io_mc_regs;
ucode_size = CAYMAN_MC_UCODE_SIZE6037;
regs_size = BTC_IO_MC_REGS_SIZE29;
break;
}

mem_type = (RREG32(MC_SEQ_MISC0)r100_mm_rreg(rdev, (0x2a00), 0) & MC_SEQ_MISC0_GDDR5_MASK0xf0000000) >> MC_SEQ_MISC0_GDDR5_SHIFT28;
running = RREG32(MC_SEQ_SUP_CNTL)r100_mm_rreg(rdev, (0x28c8), 0) & RUN_MASK(1 << 0);

if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE5) && (running == 0)) {
if (running) {
	blackout = RREG32(MC_SHARED_BLACKOUT_CNTL)r100_mm_rreg(rdev, (0x20ac), 0);
	WREG32(MC_SHARED_BLACKOUT_CNTL, 1)r100_mm_wreg(rdev, (0x20ac), (1), 0);
}

/* reset the engine and set to writable */
WREG32(MC_SEQ_SUP_CNTL, 0x00000008)r100_mm_wreg(rdev, (0x28c8), (0x00000008), 0);
WREG32(MC_SEQ_SUP_CNTL, 0x00000010)r100_mm_wreg(rdev, (0x28c8), (0x00000010), 0);

/* load mc io regs */
for (i = 0; i < regs_size; i++) {
	WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)])r100_mm_wreg(rdev, (0x2a44), (io_mc_regs[(i << 1)]), 0);
	WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1])r100_mm_wreg(rdev, (0x2a48), (io_mc_regs[(i << 1) + 1])
, 0);
}
/* load the MC ucode */
fw_data = (const __be32 *)rdev->mc_fw->data;
for (i = 0; i < ucode_size; i++)
	WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0x28cc), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);

/* put the engine back into the active state */
WREG32(MC_SEQ_SUP_CNTL, 0x00000008)r100_mm_wreg(rdev, (0x28c8), (0x00000008), 0);
WREG32(MC_SEQ_SUP_CNTL, 0x00000004)r100_mm_wreg(rdev, (0x28c8), (0x00000004), 0);
WREG32(MC_SEQ_SUP_CNTL, 0x00000001)r100_mm_wreg(rdev, (0x28c8), (0x00000001), 0);

/* wait for training to complete */
for (i = 0; i < rdev->usec_timeout; i++) {
	if (RREG32(MC_IO_PAD_CNTL_D0)r100_mm_rreg(rdev, (0x29d0), 0) & MEM_FALL_OUT_CMD(1 << 8))
		break;
	udelay(1);
}

if (running)
	WREG32(MC_SHARED_BLACKOUT_CNTL, blackout)r100_mm_wreg(rdev, (0x20ac), (blackout), 0);
}

return 0;
711}

713int ni_init_microcode(struct radeon_device *rdev)
714{
const char *chip_name;
const char *rlc_chip_name;
size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
size_t smc_req_size = 0;
char fw_name[30];
int err;

DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");

switch (rdev->family) {
25
←
Control jumps to 'case CHIP_ARUBA:'  at line 761→
case CHIP_BARTS:
chip_name = "BARTS";
rlc_chip_name = "BTC";
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE1120 * 4;
me_req_size = EVERGREEN_PM4_UCODE_SIZE1376 * 4;
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE768 * 4;
mc_req_size = BTC_MC_UCODE_SIZE6024 * 4;
smc_req_size = roundup2(BARTS_SMC_UCODE_SIZE, 4)(((0x6107) + ((4) - 1)) & (~((__typeof(0x6107))(4) - 1)));
break;
case CHIP_TURKS:
chip_name = "TURKS";
rlc_chip_name = "BTC";
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE1120 * 4;
me_req_size = EVERGREEN_PM4_UCODE_SIZE1376 * 4;
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE768 * 4;
mc_req_size = BTC_MC_UCODE_SIZE6024 * 4;
smc_req_size = roundup2(TURKS_SMC_UCODE_SIZE, 4)(((0x605b) + ((4) - 1)) & (~((__typeof(0x605b))(4) - 1)));
break;
case CHIP_CAICOS:
chip_name = "CAICOS";
rlc_chip_name = "BTC";
pfp_req_size = EVERGREEN_PFP_UCODE_SIZE1120 * 4;
me_req_size = EVERGREEN_PM4_UCODE_SIZE1376 * 4;
rlc_req_size = EVERGREEN_RLC_UCODE_SIZE768 * 4;
mc_req_size = BTC_MC_UCODE_SIZE6024 * 4;
smc_req_size = roundup2(CAICOS_SMC_UCODE_SIZE, 4)(((0x5fbd) + ((4) - 1)) & (~((__typeof(0x5fbd))(4) - 1)));
break;
case CHIP_CAYMAN:
chip_name = "CAYMAN";
rlc_chip_name = "CAYMAN";
pfp_req_size = CAYMAN_PFP_UCODE_SIZE2176 * 4;
me_req_size = CAYMAN_PM4_UCODE_SIZE2176 * 4;
rlc_req_size = CAYMAN_RLC_UCODE_SIZE1024 * 4;
mc_req_size = CAYMAN_MC_UCODE_SIZE6037 * 4;
smc_req_size = roundup2(CAYMAN_SMC_UCODE_SIZE, 4)(((0x79ec) + ((4) - 1)) & (~((__typeof(0x79ec))(4) - 1)));
break;
case CHIP_ARUBA:
chip_name = "ARUBA";
rlc_chip_name = "ARUBA";
/* pfp/me same size as CAYMAN */
pfp_req_size = CAYMAN_PFP_UCODE_SIZE2176 * 4;
me_req_size = CAYMAN_PM4_UCODE_SIZE2176 * 4;
rlc_req_size = ARUBA_RLC_UCODE_SIZE1536 * 4;
mc_req_size = 0;
break;
26
←
 Execution continues on line 773→
default: BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/radeon/ni.c"
, 770); } while (0);
}

DRM_INFO("Loading %s Microcode\n", chip_name)printk("\0016" "[" "drm" "] " "Loading %s Microcode\n", chip_name
);

snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
27
←
Calling 'request_firmware'→
31
←
Returning from 'request_firmware'→
if (err31.1
'err' is 0
1
'err' is 0
)
32
←
Taking false branch→
goto out;
if (rdev->pfp_fw->size != pfp_req_size) {
33
←
Assuming 'pfp_req_size' is equal to field 'size'→
34
←
Taking false branch→
pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "ni_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->pfp_fw->size, fw_name)
       rdev->pfp_fw->size, fw_name)printk("\0013" "ni_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->pfp_fw->size, fw_name);
err = -EINVAL22;
goto out;
}

snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
35
←
Calling 'request_firmware'→
39
←
Returning from 'request_firmware'→
if (err)
40
←
Assuming 'err' is 0→
41
←
Taking false branch→
goto out;
if (rdev->me_fw->size != me_req_size) {
42
←
Access to field 'size' results in a dereference of a null pointer (loaded from field 'me_fw')
pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "ni_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->me_fw->size, fw_name)
       rdev->me_fw->size, fw_name)printk("\0013" "ni_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->me_fw->size, fw_name);
err = -EINVAL22;
}

snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
if (err)
goto out;
if (rdev->rlc_fw->size != rlc_req_size) {
pr_err("ni_rlc: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "ni_rlc: Bogus length %zu in firmware \"%s\"\n"
, rdev->rlc_fw->size, fw_name)
       rdev->rlc_fw->size, fw_name)printk("\0013" "ni_rlc: Bogus length %zu in firmware \"%s\"\n"
, rdev->rlc_fw->size, fw_name);
err = -EINVAL22;
}

/* no MC ucode on TN */
if (!(rdev->flags & RADEON_IS_IGP)) {
snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
if (err)
	goto out;
if (rdev->mc_fw->size != mc_req_size) {
	pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "ni_mc: Bogus length %zu in firmware \"%s\"\n"
, rdev->mc_fw->size, fw_name)
	       rdev->mc_fw->size, fw_name)printk("\0013" "ni_mc: Bogus length %zu in firmware \"%s\"\n"
, rdev->mc_fw->size, fw_name);
	err = -EINVAL22;
}
}

if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
if (err) {
	pr_err("smc: error loading firmware \"%s\"\n", fw_name)printk("\0013" "smc: error loading firmware \"%s\"\n", fw_name
);
	release_firmware(rdev->smc_fw);
	rdev->smc_fw = NULL((void *)0);
	err = 0;
} else if (rdev->smc_fw->size != smc_req_size) {
	pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "ni_mc: Bogus length %zu in firmware \"%s\"\n"
, rdev->mc_fw->size, fw_name)
	       rdev->mc_fw->size, fw_name)printk("\0013" "ni_mc: Bogus length %zu in firmware \"%s\"\n"
, rdev->mc_fw->size, fw_name);
	err = -EINVAL22;
}
}

834out:
if (err) {
if (err != -EINVAL22)
	pr_err("ni_cp: Failed to load firmware \"%s\"\n",printk("\0013" "ni_cp: Failed to load firmware \"%s\"\n", fw_name
)
	       fw_name)printk("\0013" "ni_cp: Failed to load firmware \"%s\"\n", fw_name
);
release_firmware(rdev->pfp_fw);
rdev->pfp_fw = NULL((void *)0);
release_firmware(rdev->me_fw);
rdev->me_fw = NULL((void *)0);
release_firmware(rdev->rlc_fw);
rdev->rlc_fw = NULL((void *)0);
release_firmware(rdev->mc_fw);
rdev->mc_fw = NULL((void *)0);
}
return err;
849}

851/**
* cayman_get_allowed_info_register - fetch the register for the info ioctl
*
* @rdev: radeon_device pointer
* @reg: register offset in bytes
* @val: register value
*
* Returns 0 for success or -EINVAL for an invalid register
*
*/
861int cayman_get_allowed_info_register(struct radeon_device *rdev,
		     u32 reg, u32 *val)
863{
switch (reg) {
case GRBM_STATUS0x8010:
case GRBM_STATUS_SE00x8014:
case GRBM_STATUS_SE10x8018:
case SRBM_STATUS0x0E50:
case SRBM_STATUS20x0EC4:
case (DMA_STATUS_REG0xd034 + DMA0_REGISTER_OFFSET0x0):
case (DMA_STATUS_REG0xd034 + DMA1_REGISTER_OFFSET0x800):
case UVD_STATUS0xf6bc:
*val = RREG32(reg)r100_mm_rreg(rdev, (reg), 0);
return 0;
default:
return -EINVAL22;
}
878}

880int tn_get_temp(struct radeon_device *rdev)
881{
u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP)tn_smc_rreg(rdev, (0x1F390)) & 0x7ff;
int actual_temp = (temp / 8) - 49;

return actual_temp * 1000;
886}

888/*
* Core functions
*/
891static void cayman_gpu_init(struct radeon_device *rdev)
892{
u32 gb_addr_config = 0;
u32 mc_shared_chmap, mc_arb_ramcfg;
u32 cgts_tcc_disable;
u32 sx_debug_1;
u32 smx_dc_ctl0;
u32 cgts_sm_ctrl_reg;
u32 hdp_host_path_cntl;
u32 tmp;
u32 disabled_rb_mask;
int i, j;

switch (rdev->family) {
case CHIP_CAYMAN:
rdev->config.cayman.max_shader_engines = 2;
rdev->config.cayman.max_pipes_per_simd = 4;
rdev->config.cayman.max_tile_pipes = 8;
rdev->config.cayman.max_simds_per_se = 12;
rdev->config.cayman.max_backends_per_se = 4;
rdev->config.cayman.max_texture_channel_caches = 8;
rdev->config.cayman.max_gprs = 256;
rdev->config.cayman.max_threads = 256;
rdev->config.cayman.max_gs_threads = 32;
rdev->config.cayman.max_stack_entries = 512;
rdev->config.cayman.sx_num_of_sets = 8;
rdev->config.cayman.sx_max_export_size = 256;
rdev->config.cayman.sx_max_export_pos_size = 64;
rdev->config.cayman.sx_max_export_smx_size = 192;
rdev->config.cayman.max_hw_contexts = 8;
rdev->config.cayman.sq_num_cf_insts = 2;

rdev->config.cayman.sc_prim_fifo_size = 0x100;
rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN0x02011003;
break;
case CHIP_ARUBA:
default:
rdev->config.cayman.max_shader_engines = 1;
rdev->config.cayman.max_pipes_per_simd = 4;
rdev->config.cayman.max_tile_pipes = 2;
if ((rdev->pdev->device == 0x9900) ||
    (rdev->pdev->device == 0x9901) ||
    (rdev->pdev->device == 0x9905) ||
    (rdev->pdev->device == 0x9906) ||
    (rdev->pdev->device == 0x9907) ||
    (rdev->pdev->device == 0x9908) ||
    (rdev->pdev->device == 0x9909) ||
    (rdev->pdev->device == 0x990B) ||
    (rdev->pdev->device == 0x990C) ||
    (rdev->pdev->device == 0x990F) ||
    (rdev->pdev->device == 0x9910) ||
    (rdev->pdev->device == 0x9917) ||
    (rdev->pdev->device == 0x9999) ||
    (rdev->pdev->device == 0x999C)) {
	rdev->config.cayman.max_simds_per_se = 6;
	rdev->config.cayman.max_backends_per_se = 2;
	rdev->config.cayman.max_hw_contexts = 8;
	rdev->config.cayman.sx_max_export_size = 256;
	rdev->config.cayman.sx_max_export_pos_size = 64;
	rdev->config.cayman.sx_max_export_smx_size = 192;
} else if ((rdev->pdev->device == 0x9903) ||
	   (rdev->pdev->device == 0x9904) ||
	   (rdev->pdev->device == 0x990A) ||
	   (rdev->pdev->device == 0x990D) ||
	   (rdev->pdev->device == 0x990E) ||
	   (rdev->pdev->device == 0x9913) ||
	   (rdev->pdev->device == 0x9918) ||
	   (rdev->pdev->device == 0x999D)) {
	rdev->config.cayman.max_simds_per_se = 4;
	rdev->config.cayman.max_backends_per_se = 2;
	rdev->config.cayman.max_hw_contexts = 8;
	rdev->config.cayman.sx_max_export_size = 256;
	rdev->config.cayman.sx_max_export_pos_size = 64;
	rdev->config.cayman.sx_max_export_smx_size = 192;
} else if ((rdev->pdev->device == 0x9919) ||
	   (rdev->pdev->device == 0x9990) ||
	   (rdev->pdev->device == 0x9991) ||
	   (rdev->pdev->device == 0x9994) ||
	   (rdev->pdev->device == 0x9995) ||
	   (rdev->pdev->device == 0x9996) ||
	   (rdev->pdev->device == 0x999A) ||
	   (rdev->pdev->device == 0x99A0)) {
	rdev->config.cayman.max_simds_per_se = 3;
	rdev->config.cayman.max_backends_per_se = 1;
	rdev->config.cayman.max_hw_contexts = 4;
	rdev->config.cayman.sx_max_export_size = 128;
	rdev->config.cayman.sx_max_export_pos_size = 32;
	rdev->config.cayman.sx_max_export_smx_size = 96;
} else {
	rdev->config.cayman.max_simds_per_se = 2;
	rdev->config.cayman.max_backends_per_se = 1;
	rdev->config.cayman.max_hw_contexts = 4;
	rdev->config.cayman.sx_max_export_size = 128;
	rdev->config.cayman.sx_max_export_pos_size = 32;
	rdev->config.cayman.sx_max_export_smx_size = 96;
}
rdev->config.cayman.max_texture_channel_caches = 2;
rdev->config.cayman.max_gprs = 256;
rdev->config.cayman.max_threads = 256;
rdev->config.cayman.max_gs_threads = 32;
rdev->config.cayman.max_stack_entries = 512;
rdev->config.cayman.sx_num_of_sets = 8;
rdev->config.cayman.sq_num_cf_insts = 2;

rdev->config.cayman.sc_prim_fifo_size = 0x40;
rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN0x12010001;
break;
}

/* Initialize HDP */
for (i = 0, j = 0; i < 32; i++, j += 0x18) {
WREG32((0x2c14 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c14 + j)), (0x00000000), 0);
WREG32((0x2c18 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c18 + j)), (0x00000000), 0);
WREG32((0x2c1c + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c1c + j)), (0x00000000), 0);
WREG32((0x2c20 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c20 + j)), (0x00000000), 0);
WREG32((0x2c24 + j), 0x00000000)r100_mm_wreg(rdev, ((0x2c24 + j)), (0x00000000), 0);
}

WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff))r100_mm_wreg(rdev, (0x8000), (((0xff) << 0)), 0);
WREG32(SRBM_INT_CNTL, 0x1)r100_mm_wreg(rdev, (0xEA0), (0x1), 0);
WREG32(SRBM_INT_ACK, 0x1)r100_mm_wreg(rdev, (0xEA8), (0x1), 0);

evergreen_fix_pci_max_read_req_size(rdev);

mc_shared_chmap = RREG32(MC_SHARED_CHMAP)r100_mm_rreg(rdev, (0x2004), 0);
mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG)r100_mm_rreg(rdev, (0x2760), 0);

tmp = (mc_arb_ramcfg & NOOFCOLS_MASK0x000000C0) >> NOOFCOLS_SHIFT6;
rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
if (rdev->config.cayman.mem_row_size_in_kb > 4)
rdev->config.cayman.mem_row_size_in_kb = 4;
/* XXX use MC settings? */
rdev->config.cayman.shader_engine_tile_size = 32;
rdev->config.cayman.num_gpus = 1;
rdev->config.cayman.multi_gpu_tile_size = 64;

tmp = (gb_addr_config & NUM_PIPES_MASK0x00000007) >> NUM_PIPES_SHIFT0;
rdev->config.cayman.num_tile_pipes = (1 << tmp);
tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK0x00000070) >> PIPE_INTERLEAVE_SIZE_SHIFT4;
rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK0x00003000) >> NUM_SHADER_ENGINES_SHIFT12;
rdev->config.cayman.num_shader_engines = tmp + 1;
tmp = (gb_addr_config & NUM_GPUS_MASK0x00700000) >> NUM_GPUS_SHIFT20;
rdev->config.cayman.num_gpus = tmp + 1;
tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK0x03000000) >> MULTI_GPU_TILE_SIZE_SHIFT24;
rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
tmp = (gb_addr_config & ROW_SIZE_MASK0x30000000) >> ROW_SIZE_SHIFT28;
rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;


/* setup tiling info dword.  gb_addr_config is not adequate since it does
* not have bank info, so create a custom tiling dword.
* bits 3:0   num_pipes
* bits 7:4   num_banks
* bits 11:8  group_size
* bits 15:12 row_size
*/
rdev->config.cayman.tile_config = 0;
switch (rdev->config.cayman.num_tile_pipes) {
case 1:
default:
rdev->config.cayman.tile_config |= (0 << 0);
break;
case 2:
rdev->config.cayman.tile_config |= (1 << 0);
break;
case 4:
rdev->config.cayman.tile_config |= (2 << 0);
break;
case 8:
rdev->config.cayman.tile_config |= (3 << 0);
break;
}

/* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
if (rdev->flags & RADEON_IS_IGP)
rdev->config.cayman.tile_config |= 1 << 4;
else {
switch ((mc_arb_ramcfg & NOOFBANK_MASK0x00000003) >> NOOFBANK_SHIFT0) {
case 0: /* four banks */
	rdev->config.cayman.tile_config |= 0 << 4;
	break;
case 1: /* eight banks */
	rdev->config.cayman.tile_config |= 1 << 4;
	break;
case 2: /* sixteen banks */
default:
	rdev->config.cayman.tile_config |= 2 << 4;
	break;
}
}
rdev->config.cayman.tile_config |=
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK0x00000070) >> PIPE_INTERLEAVE_SIZE_SHIFT4) << 8;
rdev->config.cayman.tile_config |=
((gb_addr_config & ROW_SIZE_MASK0x30000000) >> ROW_SIZE_SHIFT28) << 12;

tmp = 0;
for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
u32 rb_disable_bitmap;

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i))r100_mm_wreg(rdev, (0x802C), ((1 << 30) | ((i) <<
 16)), 0);
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i))r100_mm_wreg(rdev, (0x3FC4), ((1 << 30) | ((i) <<
 16)), 0);
rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE)r100_mm_rreg(rdev, (0x98F4), 0) & 0x00ff0000) >> 16;
tmp <<= 4;
tmp |= rb_disable_bitmap;
}
/* enabled rb are just the one not disabled :) */
disabled_rb_mask = tmp;
tmp = 0;
for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
tmp |= (1 << i);
/* if all the backends are disabled, fix it up here */
if ((disabled_rb_mask & tmp) == tmp) {
for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
	disabled_rb_mask &= ~(1 << i);
}

for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
u32 simd_disable_bitmap;

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i))r100_mm_wreg(rdev, (0x802C), ((1 << 30) | ((i) <<
 16)), 0);
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i))r100_mm_wreg(rdev, (0x3FC4), ((1 << 30) | ((i) <<
 16)), 0);
simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG)r100_mm_rreg(rdev, (0x8950), 0) & 0xffff0000) >> 16;
simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
tmp <<= 16;
tmp |= simd_disable_bitmap;
}
rdev->config.cayman.active_simds = hweight32(~tmp);

WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES)r100_mm_wreg(rdev, (0x802C), ((1 << 30) | (1 << 31
)), 0);
WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES)r100_mm_wreg(rdev, (0x3FC4), ((1 << 30) | (1 << 31
)), 0);

WREG32(GB_ADDR_CONFIG, gb_addr_config)r100_mm_wreg(rdev, (0x98F8), (gb_addr_config), 0);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config)r100_mm_wreg(rdev, (0xBD4), (gb_addr_config), 0);
if (ASIC_IS_DCE6(rdev)((rdev->family >= CHIP_ARUBA)))
WREG32(DMIF_ADDR_CALC, gb_addr_config)r100_mm_wreg(rdev, (0xC00), (gb_addr_config), 0);
WREG32(HDP_ADDR_CONFIG, gb_addr_config)r100_mm_wreg(rdev, (0x2F48), (gb_addr_config), 0);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config)r100_mm_wreg(rdev, (0xd0b8 + 0x0), (gb_addr_config), 0);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config)r100_mm_wreg(rdev, (0xd0b8 + 0x800), (gb_addr_config), 0);
WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config)r100_mm_wreg(rdev, (0xEF4C), (gb_addr_config), 0);
WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config)r100_mm_wreg(rdev, (0xEF50), (gb_addr_config), 0);
WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config)r100_mm_wreg(rdev, (0xEF54), (gb_addr_config), 0);

if ((rdev->config.cayman.max_backends_per_se == 1) &&
   (rdev->flags & RADEON_IS_IGP)) {
if ((disabled_rb_mask & 3) == 2) {
	/* RB1 disabled, RB0 enabled */
	tmp = 0x00000000;
} else {
	/* RB0 disabled, RB1 enabled */
	tmp = 0x11111111;
}
} else {
tmp = gb_addr_config & NUM_PIPES_MASK0x00000007;
tmp = r6xx_remap_render_backend(rdev, tmp,
				rdev->config.cayman.max_backends_per_se *
				rdev->config.cayman.max_shader_engines,
				CAYMAN_MAX_BACKENDS8, disabled_rb_mask);
}
rdev->config.cayman.backend_map = tmp;
WREG32(GB_BACKEND_MAP, tmp)r100_mm_wreg(rdev, (0x98FC), (tmp), 0);

cgts_tcc_disable = 0xffff0000;
for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
cgts_tcc_disable &= ~(1 << (16 + i));
WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable)r100_mm_wreg(rdev, (0x9148), (cgts_tcc_disable), 0);
WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable)r100_mm_wreg(rdev, (0x3F90), (cgts_tcc_disable), 0);
WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable)r100_mm_wreg(rdev, (0x3F94), (cgts_tcc_disable), 0);
WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable)r100_mm_wreg(rdev, (0x914C), (cgts_tcc_disable), 0);

/* reprogram the shader complex */
cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG)r100_mm_rreg(rdev, (0x9150), 0);
for (i = 0; i < 16; i++)
WREG32(CGTS_SM_CTRL_REG, OVERRIDE)r100_mm_wreg(rdev, (0x9150), ((1 << 21)), 0);
WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg)r100_mm_wreg(rdev, (0x9150), (cgts_sm_ctrl_reg), 0);

/* set HW defaults for 3D engine */
WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60))r100_mm_wreg(rdev, (0x8764), (((0x30) << 0) | ((0x60) <<
 8)), 0);

sx_debug_1 = RREG32(SX_DEBUG_1)r100_mm_rreg(rdev, (0x9058), 0);
sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS(1 << 16);
WREG32(SX_DEBUG_1, sx_debug_1)r100_mm_wreg(rdev, (0x9058), (sx_debug_1), 0);

smx_dc_ctl0 = RREG32(SMX_DC_CTL0)r100_mm_rreg(rdev, (0xA020), 0);
smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff)((0x1ff) << 1);
smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets)((rdev->config.cayman.sx_num_of_sets) << 1);
WREG32(SMX_DC_CTL0, smx_dc_ctl0)r100_mm_wreg(rdev, (0xA020), (smx_dc_ctl0), 0);

WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE)r100_mm_wreg(rdev, (0x913C), (((4) << 0) | (1 << 8
)), 0);

/* need to be explicitly zero-ed */
WREG32(VGT_OFFCHIP_LDS_BASE, 0)r100_mm_wreg(rdev, (0x89b4), (0), 0);
WREG32(SQ_LSTMP_RING_BASE, 0)r100_mm_wreg(rdev, (0x8e10), (0), 0);
WREG32(SQ_HSTMP_RING_BASE, 0)r100_mm_wreg(rdev, (0x8e18), (0), 0);
WREG32(SQ_ESTMP_RING_BASE, 0)r100_mm_wreg(rdev, (0x8c50), (0), 0);
WREG32(SQ_GSTMP_RING_BASE, 0)r100_mm_wreg(rdev, (0x8c58), (0), 0);
WREG32(SQ_VSTMP_RING_BASE, 0)r100_mm_wreg(rdev, (0x8c60), (0), 0);
WREG32(SQ_PSTMP_RING_BASE, 0)r100_mm_wreg(rdev, (0x8c68), (0), 0);

WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO)r100_mm_wreg(rdev, (0x9508), ((1 << 1)), 0);

WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |r100_mm_wreg(rdev, (0x900C), (((((rdev->config.cayman.sx_max_export_size
 / 4) - 1) << 0) | (((rdev->config.cayman.sx_max_export_pos_size
 / 4) - 1) << 8) | (((rdev->config.cayman.sx_max_export_smx_size
 / 4) - 1) << 16))), 0)
			POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |r100_mm_wreg(rdev, (0x900C), (((((rdev->config.cayman.sx_max_export_size
 / 4) - 1) << 0) | (((rdev->config.cayman.sx_max_export_pos_size
 / 4) - 1) << 8) | (((rdev->config.cayman.sx_max_export_smx_size
 / 4) - 1) << 16))), 0)
			SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)))r100_mm_wreg(rdev, (0x900C), (((((rdev->config.cayman.sx_max_export_size
 / 4) - 1) << 0) | (((rdev->config.cayman.sx_max_export_pos_size
 / 4) - 1) << 8) | (((rdev->config.cayman.sx_max_export_smx_size
 / 4) - 1) << 16))), 0);

WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |r100_mm_wreg(rdev, (0x8BCC), ((((rdev->config.cayman.sc_prim_fifo_size
) << 0) | ((rdev->config.cayman.sc_hiz_tile_fifo_size
) << 12) | ((rdev->config.cayman.sc_earlyz_tile_fifo_size
) << 20))), 0)
		 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |r100_mm_wreg(rdev, (0x8BCC), ((((rdev->config.cayman.sc_prim_fifo_size
) << 0) | ((rdev->config.cayman.sc_hiz_tile_fifo_size
) << 12) | ((rdev->config.cayman.sc_earlyz_tile_fifo_size
) << 20))), 0)
		 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)))r100_mm_wreg(rdev, (0x8BCC), ((((rdev->config.cayman.sc_prim_fifo_size
) << 0) | ((rdev->config.cayman.sc_hiz_tile_fifo_size
) << 12) | ((rdev->config.cayman.sc_earlyz_tile_fifo_size
) << 20))), 0);


WREG32(VGT_NUM_INSTANCES, 1)r100_mm_wreg(rdev, (0x8974), (1), 0);

WREG32(CP_PERFMON_CNTL, 0)r100_mm_wreg(rdev, (0x87FC), (0), 0);

WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |r100_mm_wreg(rdev, (0x8CF0), ((((16 * rdev->config.cayman.
sq_num_cf_insts) << 0) | ((0x4) << 8) | ((0xe0) <<
 16) | ((0x8) << 24))), 0)
		  FETCH_FIFO_HIWATER(0x4) |r100_mm_wreg(rdev, (0x8CF0), ((((16 * rdev->config.cayman.
sq_num_cf_insts) << 0) | ((0x4) << 8) | ((0xe0) <<
 16) | ((0x8) << 24))), 0)
		  DONE_FIFO_HIWATER(0xe0) |r100_mm_wreg(rdev, (0x8CF0), ((((16 * rdev->config.cayman.
sq_num_cf_insts) << 0) | ((0x4) << 8) | ((0xe0) <<
 16) | ((0x8) << 24))), 0)
		  ALU_UPDATE_FIFO_HIWATER(0x8)))r100_mm_wreg(rdev, (0x8CF0), ((((16 * rdev->config.cayman.
sq_num_cf_insts) << 0) | ((0x4) << 8) | ((0xe0) <<
 16) | ((0x8) << 24))), 0);

WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4))r100_mm_wreg(rdev, (0x8C04), (((4) << 28)), 0);
WREG32(SQ_CONFIG, (VC_ENABLE |r100_mm_wreg(rdev, (0x8C00), (((1 << 0) | (1 << 1
) | ((0) << 2) | ((0) << 4) | ((1) << 6))),
 0)
	   EXPORT_SRC_C |r100_mm_wreg(rdev, (0x8C00), (((1 << 0) | (1 << 1
) | ((0) << 2) | ((0) << 4) | ((1) << 6))),
 0)
	   GFX_PRIO(0) |r100_mm_wreg(rdev, (0x8C00), (((1 << 0) | (1 << 1
) | ((0) << 2) | ((0) << 4) | ((1) << 6))),
 0)
	   CS1_PRIO(0) |r100_mm_wreg(rdev, (0x8C00), (((1 << 0) | (1 << 1
) | ((0) << 2) | ((0) << 4) | ((1) << 6))),
 0)
	   CS2_PRIO(1)))r100_mm_wreg(rdev, (0x8C00), (((1 << 0) | (1 << 1
) | ((0) << 2) | ((0) << 4) | ((1) << 6))),
 0);
WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE)r100_mm_wreg(rdev, (0x8D8C), ((1 << 8)), 0);

WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |r100_mm_wreg(rdev, (0x8B24), ((((4095) << 0) | ((255) <<
 16))), 0)
			  FORCE_EOV_MAX_REZ_CNT(255)))r100_mm_wreg(rdev, (0x8B24), ((((4095) << 0) | ((255) <<
 16))), 0);

WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |r100_mm_wreg(rdev, (0x88C4), (((2) << 0) | ((3) <<
 6)), 0)
      AUTO_INVLD_EN(ES_AND_GS_AUTO))r100_mm_wreg(rdev, (0x88C4), (((2) << 0) | ((3) <<
 6)), 0);

WREG32(VGT_GS_VERTEX_REUSE, 16)r100_mm_wreg(rdev, (0x88D4), (16), 0);
WREG32(PA_SC_LINE_STIPPLE_STATE, 0)r100_mm_wreg(rdev, (0x8B10), (0), 0);

WREG32(CB_PERF_CTR0_SEL_0, 0)r100_mm_wreg(rdev, (0x9A20), (0), 0);
WREG32(CB_PERF_CTR0_SEL_1, 0)r100_mm_wreg(rdev, (0x9A24), (0), 0);
WREG32(CB_PERF_CTR1_SEL_0, 0)r100_mm_wreg(rdev, (0x9A28), (0), 0);
WREG32(CB_PERF_CTR1_SEL_1, 0)r100_mm_wreg(rdev, (0x9A2C), (0), 0);
WREG32(CB_PERF_CTR2_SEL_0, 0)r100_mm_wreg(rdev, (0x9A30), (0), 0);
WREG32(CB_PERF_CTR2_SEL_1, 0)r100_mm_wreg(rdev, (0x9A34), (0), 0);
WREG32(CB_PERF_CTR3_SEL_0, 0)r100_mm_wreg(rdev, (0x9A38), (0), 0);
WREG32(CB_PERF_CTR3_SEL_1, 0)r100_mm_wreg(rdev, (0x9A3C), (0), 0);

tmp = RREG32(HDP_MISC_CNTL)r100_mm_rreg(rdev, (0x2F4C), 0);
tmp |= HDP_FLUSH_INVALIDATE_CACHE(1 << 0);
WREG32(HDP_MISC_CNTL, tmp)r100_mm_wreg(rdev, (0x2F4C), (tmp), 0);

hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x2C00), 0);
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl)r100_mm_wreg(rdev, (0x2C00), (hdp_host_path_cntl), 0);

WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3))r100_mm_wreg(rdev, (0x8A14), ((1 << 0) | ((3) << 1
)), 0);

udelay(50);

/* set clockgating golden values on TN */
if (rdev->family == CHIP_ARUBA) {
tmp = RREG32_CG(CG_CGTT_LOCAL_0)eg_cg_rreg(rdev, (0x00));
tmp &= ~0x00380000;
WREG32_CG(CG_CGTT_LOCAL_0, tmp)eg_cg_wreg(rdev, (0x00), (tmp));
tmp = RREG32_CG(CG_CGTT_LOCAL_1)eg_cg_rreg(rdev, (0x01));
tmp &= ~0x0e000000;
WREG32_CG(CG_CGTT_LOCAL_1, tmp)eg_cg_wreg(rdev, (0x01), (tmp));
}
1260}

1262/*
* GART
*/
1265void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1266{
/* flush hdp cache */
WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1)r100_mm_wreg(rdev, (0x5480), (0x1), 0);

/* bits 0-7 are the VM contexts0-7 */
WREG32(VM_INVALIDATE_REQUEST, 1)r100_mm_wreg(rdev, (0x1478), (1), 0);
1272}

1274static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1275{
int i, r;

if (rdev->gart.robj == NULL((void *)0)) {
dev_err(rdev->dev, "No VRAM object for PCIE GART.\n")printf("drm:pid%d:%s *ERROR* " "No VRAM object for PCIE GART.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
}
r = radeon_gart_table_vram_pin(rdev);
if (r)
return r;
/* Setup TLB control */
WREG32(MC_VM_MX_L1_TLB_CNTL,r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0)
      (0xA << 7) |r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0)
      ENABLE_L1_TLB |r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0)
      ENABLE_L1_FRAGMENT_PROCESSING |r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0)
      SYSTEM_ACCESS_MODE_NOT_IN_SYS |r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0)
      ENABLE_ADVANCED_DRIVER_MODEL |r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0)
      SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU)r100_mm_wreg(rdev, (0x2064), ((0xA << 7) | (1 << 0
) | (1 << 1) | (3 << 3) | (1 << 6) | (0 <<
 5)), 0);
/* Setup L2 cache */
WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
 | (1 << 9) | (1 << 10) | (((7) & 7) <<
 14) | (((1) & 3) << 18)), 0)
      ENABLE_L2_FRAGMENT_PROCESSING |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
 | (1 << 9) | (1 << 10) | (((7) & 7) <<
 14) | (((1) & 3) << 18)), 0)
      ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
 | (1 << 9) | (1 << 10) | (((7) & 7) <<
 14) | (((1) & 3) << 18)), 0)
      ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
 | (1 << 9) | (1 << 10) | (((7) & 7) <<
 14) | (((1) & 3) << 18)), 0)
      EFFECTIVE_L2_QUEUE_SIZE(7) |r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
 | (1 << 9) | (1 << 10) | (((7) & 7) <<
 14) | (((1) & 3) << 18)), 0)
      CONTEXT1_IDENTITY_ACCESS_MODE(1))r100_mm_wreg(rdev, (0x1400), ((1 << 0) | (1 << 1)
 | (1 << 9) | (1 << 10) | (((7) & 7) <<
 14) | (((1) & 3) << 18)), 0);
WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE)r100_mm_wreg(rdev, (0x1404), ((1 << 0) | (1 << 1)
), 0);
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |r100_mm_wreg(rdev, (0x1408), ((1 << 20) | ((6) <<
 0) | ((6) << 15)), 0)
      BANK_SELECT(6) |r100_mm_wreg(rdev, (0x1408), ((1 << 20) | ((6) <<
 0) | ((6) << 15)), 0)
      L2_CACHE_BIGK_FRAGMENT_SIZE(6))r100_mm_wreg(rdev, (0x1408), ((1 << 20) | ((6) <<
 0) | ((6) << 15)), 0);
/* setup context0 */
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12)r100_mm_wreg(rdev, (0x155C), (rdev->mc.gtt_start >> 12
), 0);
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12)r100_mm_wreg(rdev, (0x157C), (rdev->mc.gtt_end >> 12
), 0);
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12)r100_mm_wreg(rdev, (0x153C), (rdev->gart.table_addr >>
 12), 0);
WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,r100_mm_wreg(rdev, (0x1518), ((u32)(rdev->dummy_page.addr >>
 12)), 0)
	(u32)(rdev->dummy_page.addr >> 12))r100_mm_wreg(rdev, (0x1518), ((u32)(rdev->dummy_page.addr >>
 12)), 0);
WREG32(VM_CONTEXT0_CNTL2, 0)r100_mm_wreg(rdev, (0x1430), (0), 0);
WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |r100_mm_wreg(rdev, (0x1410), ((1 << 0) | (((0) & 3)
 << 1) | (1 << 4)), 0)
		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT)r100_mm_wreg(rdev, (0x1410), ((1 << 0) | (((0) & 3)
 << 1) | (1 << 4)), 0);

WREG32(0x15D4, 0)r100_mm_wreg(rdev, (0x15D4), (0), 0);
WREG32(0x15D8, 0)r100_mm_wreg(rdev, (0x15D8), (0), 0);
WREG32(0x15DC, 0)r100_mm_wreg(rdev, (0x15DC), (0), 0);

/* empty context1-7 */
/* Assign the pt base to something valid for now; the pts used for
* the VMs are determined by the application and setup and assigned
* on the fly in the vm part of radeon_gart.c
*/
for (i = 1; i < 8; i++) {
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0)r100_mm_wreg(rdev, (0x155C + (i << 2)), (0), 0);
WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),r100_mm_wreg(rdev, (0x157C + (i << 2)), (rdev->vm_manager
.max_pfn - 1), 0)
	rdev->vm_manager.max_pfn - 1)r100_mm_wreg(rdev, (0x157C + (i << 2)), (rdev->vm_manager
.max_pfn - 1), 0);
WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),r100_mm_wreg(rdev, (0x153C + (i << 2)), (rdev->vm_manager
.saved_table_addr[i]), 0)
       rdev->vm_manager.saved_table_addr[i])r100_mm_wreg(rdev, (0x153C + (i << 2)), (rdev->vm_manager
.saved_table_addr[i]), 0);
}

/* enable context1-7 */
WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,r100_mm_wreg(rdev, (0x151c), ((u32)(rdev->dummy_page.addr >>
 12)), 0)
      (u32)(rdev->dummy_page.addr >> 12))r100_mm_wreg(rdev, (0x151c), ((u32)(rdev->dummy_page.addr >>
 12)), 0);
WREG32(VM_CONTEXT1_CNTL2, 4)r100_mm_wreg(rdev, (0x1434), (4), 0);
WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		VALID_PROTECTION_FAULT_ENABLE_DEFAULT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		READ_PROTECTION_FAULT_ENABLE_INTERRUPT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		READ_PROTECTION_FAULT_ENABLE_DEFAULT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0)
		WRITE_PROTECTION_FAULT_ENABLE_DEFAULT)r100_mm_wreg(rdev, (0x1414), ((1 << 0) | (((1) & 3)
 << 1) | (((radeon_vm_block_size - 9) & 0xF) <<
 24) | (1 << 3) | (1 << 4) | (1 << 6) | (1 <<
 7) | (1 << 9) | (1 << 10) | (1 << 12) | (1
 << 13) | (1 << 15) | (1 << 16) | (1 <<
 18) | (1 << 19)), 0);

cayman_pcie_gart_tlb_flush(rdev);
DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
 long)rdev->gart.table_addr)
 (unsigned)(rdev->mc.gtt_size >> 20),printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
 long)rdev->gart.table_addr)
 (unsigned long long)rdev->gart.table_addr)printk("\0016" "[" "drm" "] " "PCIE GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
 long)rdev->gart.table_addr);
rdev->gart.ready = true1;
return 0;
1356}

1358static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1359{
unsigned i;

for (i = 1; i < 8; ++i) {
rdev->vm_manager.saved_table_addr[i] = RREG32(r100_mm_rreg(rdev, (0x153C + (i << 2)), 0)
	VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2))r100_mm_rreg(rdev, (0x153C + (i << 2)), 0);
}

/* Disable all tables */
WREG32(VM_CONTEXT0_CNTL, 0)r100_mm_wreg(rdev, (0x1410), (0), 0);
WREG32(VM_CONTEXT1_CNTL, 0)r100_mm_wreg(rdev, (0x1414), (0), 0);
/* Setup TLB control */
WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |r100_mm_wreg(rdev, (0x2064), ((1 << 1) | (3 << 3)
 | (0 << 5)), 0)
      SYSTEM_ACCESS_MODE_NOT_IN_SYS |r100_mm_wreg(rdev, (0x2064), ((1 << 1) | (3 << 3)
 | (0 << 5)), 0)
      SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU)r100_mm_wreg(rdev, (0x2064), ((1 << 1) | (3 << 3)
 | (0 << 5)), 0);
/* Setup L2 cache */
WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |r100_mm_wreg(rdev, (0x1400), ((1 << 9) | (1 << 10
) | (((7) & 7) << 14) | (((1) & 3) << 18)
), 0)
      ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |r100_mm_wreg(rdev, (0x1400), ((1 << 9) | (1 << 10
) | (((7) & 7) << 14) | (((1) & 3) << 18)
), 0)
      EFFECTIVE_L2_QUEUE_SIZE(7) |r100_mm_wreg(rdev, (0x1400), ((1 << 9) | (1 << 10
) | (((7) & 7) << 14) | (((1) & 3) << 18)
), 0)
      CONTEXT1_IDENTITY_ACCESS_MODE(1))r100_mm_wreg(rdev, (0x1400), ((1 << 9) | (1 << 10
) | (((7) & 7) << 14) | (((1) & 3) << 18)
), 0);
WREG32(VM_L2_CNTL2, 0)r100_mm_wreg(rdev, (0x1404), (0), 0);
WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |r100_mm_wreg(rdev, (0x1408), ((1 << 20) | ((6) <<
 15)), 0)
      L2_CACHE_BIGK_FRAGMENT_SIZE(6))r100_mm_wreg(rdev, (0x1408), ((1 << 20) | ((6) <<
 15)), 0);
radeon_gart_table_vram_unpin(rdev);
1383}

1385static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1386{
cayman_pcie_gart_disable(rdev);
radeon_gart_table_vram_free(rdev);
radeon_gart_fini(rdev);
1390}

1392void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
	      int ring, u32 cp_int_cntl)
1394{
WREG32(SRBM_GFX_CNTL, RINGID(ring))r100_mm_wreg(rdev, (0x0E44), ((((ring) & 0x3) << 0)
), 0);
WREG32(CP_INT_CNTL, cp_int_cntl)r100_mm_wreg(rdev, (0xC124), (cp_int_cntl), 0);
1397}

1399/*
* CP.
*/
1402void cayman_fence_ring_emit(struct radeon_device *rdev,
	    struct radeon_fence *fence)
1404{
struct radeon_ring *ring = &rdev->ring[fence->ring];
u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA(1 << 20) | PACKET3_TC_ACTION_ENA(1 << 23) |
PACKET3_SH_ACTION_ENA(1 << 27);

/* flush read cache over gart for this vmid */
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)((3 << 30) | (((0x43) & 0xFF) << 8) | ((3) &
 0x3FFF) << 16));
radeon_ring_write(ring, PACKET3_ENGINE_ME(1 << 31) | cp_coher_cntl);
radeon_ring_write(ring, 0xFFFFFFFF);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 10); /* poll interval */
/* EVENT_WRITE_EOP - flush caches, send int */
radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)((3 << 30) | (((0x47) & 0xFF) << 8) | ((4) &
 0x3FFF) << 16));
radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS)(((0x14 << 0)) << 0) | EVENT_INDEX(5)((5) << 8));
radeon_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
radeon_ring_write(ring, (upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)) & 0xff) | DATA_SEL(1)((1) << 29) | INT_SEL(2)((2) << 24));
radeon_ring_write(ring, fence->seq);
radeon_ring_write(ring, 0);
1423}

1425void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1426{
struct radeon_ring *ring = &rdev->ring[ib->ring];
unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA(1 << 20) | PACKET3_TC_ACTION_ENA(1 << 23) |
PACKET3_SH_ACTION_ENA(1 << 27);

/* set to DX10/11 mode */
radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)((3 << 30) | (((0x18) & 0xFF) << 8) | ((0) &
 0x3FFF) << 16));
radeon_ring_write(ring, 1);

if (ring->rptr_save_reg) {
uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
 0x3FFF) << 16));
radeon_ring_write(ring, ((ring->rptr_save_reg - 
			  PACKET3_SET_CONFIG_REG_START0x00008000) >> 2));
radeon_ring_write(ring, next_rptr);
}

radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x32) & 0xFF) << 8) | ((2) &
 0x3FFF) << 16));
radeon_ring_write(ring,
1446#ifdef __BIG_ENDIAN
	  (2 << 0) |
1448#endif
	  (ib->gpu_addr & 0xFFFFFFFC));
radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)) & 0xFF);
radeon_ring_write(ring, ib->length_dw | (vm_id << 24));

/* flush read cache over gart for this vmid */
radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)((3 << 30) | (((0x43) & 0xFF) << 8) | ((3) &
 0x3FFF) << 16));
radeon_ring_write(ring, PACKET3_ENGINE_ME(1 << 31) | cp_coher_cntl);
radeon_ring_write(ring, 0xFFFFFFFF);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */
1459}

1461static void cayman_cp_enable(struct radeon_device *rdev, bool_Bool enable)
1462{
if (enable)
WREG32(CP_ME_CNTL, 0)r100_mm_wreg(rdev, (0x86D8), (0), 0);
else {
if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX0)
	radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT))r100_mm_wreg(rdev, (0x86D8), (((1 << 28) | (1 << 26
))), 0);
WREG32(SCRATCH_UMSK, 0)r100_mm_wreg(rdev, (0x8540), (0), 0);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ready = false0;
}
1472}

1474u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
	struct radeon_ring *ring)
1476{
u32 rptr;

if (rdev->wb.enabled)
rptr = rdev->wb.wb[ring->rptr_offs/4];
else {
if (ring->idx == RADEON_RING_TYPE_GFX_INDEX0)
	rptr = RREG32(CP_RB0_RPTR)r100_mm_rreg(rdev, (0x8700), 0);
else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX1)
	rptr = RREG32(CP_RB1_RPTR)r100_mm_rreg(rdev, (0x86fc), 0);
else
	rptr = RREG32(CP_RB2_RPTR)r100_mm_rreg(rdev, (0x86f8), 0);
}

return rptr;
1491}

1493u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
	struct radeon_ring *ring)
1495{
u32 wptr;

if (ring->idx == RADEON_RING_TYPE_GFX_INDEX0)
wptr = RREG32(CP_RB0_WPTR)r100_mm_rreg(rdev, (0xC114), 0);
else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX1)
wptr = RREG32(CP_RB1_WPTR)r100_mm_rreg(rdev, (0xC190), 0);
else
wptr = RREG32(CP_RB2_WPTR)r100_mm_rreg(rdev, (0xC1A4), 0);

return wptr;
1506}

1508void cayman_gfx_set_wptr(struct radeon_device *rdev,
	 struct radeon_ring *ring)
1510{
if (ring->idx == RADEON_RING_TYPE_GFX_INDEX0) {
WREG32(CP_RB0_WPTR, ring->wptr)r100_mm_wreg(rdev, (0xC114), (ring->wptr), 0);
(void)RREG32(CP_RB0_WPTR)r100_mm_rreg(rdev, (0xC114), 0);
} else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX1) {
WREG32(CP_RB1_WPTR, ring->wptr)r100_mm_wreg(rdev, (0xC190), (ring->wptr), 0);
(void)RREG32(CP_RB1_WPTR)r100_mm_rreg(rdev, (0xC190), 0);
} else {
WREG32(CP_RB2_WPTR, ring->wptr)r100_mm_wreg(rdev, (0xC1A4), (ring->wptr), 0);
(void)RREG32(CP_RB2_WPTR)r100_mm_rreg(rdev, (0xC1A4), 0);
}
1521}

1523static int cayman_cp_load_microcode(struct radeon_device *rdev)
1524{
const __be32 *fw_data;
int i;

if (!rdev->me_fw || !rdev->pfp_fw)
return -EINVAL22;

cayman_cp_enable(rdev, false0);

fw_data = (const __be32 *)rdev->pfp_fw->data;
WREG32(CP_PFP_UCODE_ADDR, 0)r100_mm_wreg(rdev, (0xC150), (0), 0);
for (i = 0; i < CAYMAN_PFP_UCODE_SIZE2176; i++)
WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0xC154), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);
WREG32(CP_PFP_UCODE_ADDR, 0)r100_mm_wreg(rdev, (0xC150), (0), 0);

fw_data = (const __be32 *)rdev->me_fw->data;
WREG32(CP_ME_RAM_WADDR, 0)r100_mm_wreg(rdev, (0xC15C), (0), 0);
for (i = 0; i < CAYMAN_PM4_UCODE_SIZE2176; i++)
WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++))r100_mm_wreg(rdev, (0xC160), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(fw_data++)) ? (__uint32_t)(((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff) << 24 | ((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff00) << 8 | ((__uint32_t)(*(__uint32_t
 *)(fw_data++)) & 0xff0000) >> 8 | ((__uint32_t)(*(
__uint32_t *)(fw_data++)) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(fw_data++)))), 0);

WREG32(CP_PFP_UCODE_ADDR, 0)r100_mm_wreg(rdev, (0xC150), (0), 0);
WREG32(CP_ME_RAM_WADDR, 0)r100_mm_wreg(rdev, (0xC15C), (0), 0);
WREG32(CP_ME_RAM_RADDR, 0)r100_mm_wreg(rdev, (0xC158), (0), 0);
return 0;
1548}

1550static int cayman_cp_start(struct radeon_device *rdev)
1551{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
int r, i;

r = radeon_ring_lock(rdev, ring, 7);
if (r) {
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r)__drm_err("radeon: cp failed to lock ring (%d).\n", r);
return r;
}
radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)((3 << 30) | (((0x44) & 0xFF) << 8) | ((5) &
 0x3FFF) << 16));
radeon_ring_write(ring, 0x1);
radeon_ring_write(ring, 0x0);
radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)((1) << 16));
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 0);
radeon_ring_unlock_commit(rdev, ring, false0);

cayman_cp_enable(rdev, true1);

r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
if (r) {
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r)__drm_err("radeon: cp failed to lock ring (%d).\n", r);
return r;
}

/* setup clear context state */
radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
 0x3FFF) << 16));
radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE(2 << 28));

for (i = 0; i < cayman_default_size; i++)
radeon_ring_write(ring, cayman_default_state[i]);

radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
 0x3FFF) << 16));
radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE(3 << 28));

/* set clear context state */
radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) &
 0x3FFF) << 16));
radeon_ring_write(ring, 0);

/* SQ_VTX_BASE_VTX_LOC */
radeon_ring_write(ring, 0xc0026f00);
radeon_ring_write(ring, 0x00000000);
radeon_ring_write(ring, 0x00000000);
radeon_ring_write(ring, 0x00000000);

/* Clear consts */
radeon_ring_write(ring, 0xc0036f00);
radeon_ring_write(ring, 0x00000bc4);
radeon_ring_write(ring, 0xffffffff);
radeon_ring_write(ring, 0xffffffff);
radeon_ring_write(ring, 0xffffffff);

radeon_ring_write(ring, 0xc0026900);
radeon_ring_write(ring, 0x00000316);
radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
radeon_ring_write(ring, 0x00000010); /*  */

radeon_ring_unlock_commit(rdev, ring, false0);

/* XXX init other rings */

return 0;
1614}

1616static void cayman_cp_fini(struct radeon_device *rdev)
1617{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
cayman_cp_enable(rdev, false0);
radeon_ring_fini(rdev, ring);
radeon_scratch_free(rdev, ring->rptr_save_reg);
1622}

1624static int cayman_cp_resume(struct radeon_device *rdev)
1625{
static const int ridx[] = {
RADEON_RING_TYPE_GFX_INDEX0,
CAYMAN_RING_TYPE_CP1_INDEX1,
CAYMAN_RING_TYPE_CP2_INDEX2
};
static const unsigned cp_rb_cntl[] = {
CP_RB0_CNTL0xC104,
CP_RB1_CNTL0xC184,
CP_RB2_CNTL0xC198,
};
static const unsigned cp_rb_rptr_addr[] = {
CP_RB0_RPTR_ADDR0xC10C,
CP_RB1_RPTR_ADDR0xC188,
CP_RB2_RPTR_ADDR0xC19C
};
static const unsigned cp_rb_rptr_addr_hi[] = {
CP_RB0_RPTR_ADDR_HI0xC110,
CP_RB1_RPTR_ADDR_HI0xC18C,
CP_RB2_RPTR_ADDR_HI0xC1A0
};
static const unsigned cp_rb_base[] = {
CP_RB0_BASE0xC100,
CP_RB1_BASE0xC180,
CP_RB2_BASE0xC194
};
static const unsigned cp_rb_rptr[] = {
CP_RB0_RPTR0x8700,
CP_RB1_RPTR0x86fc,
CP_RB2_RPTR0x86f8
};
static const unsigned cp_rb_wptr[] = {
CP_RB0_WPTR0xC114,
CP_RB1_WPTR0xC190,
CP_RB2_WPTR0xC1A4
};
struct radeon_ring *ring;
int i, r;

/* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |r100_mm_wreg(rdev, (0x8020), (((1 << 0) | (1 << 5
) | (1 << 9) | (1 << 14) | (1 << 8) | (1 <<
 10))), 0)
		 SOFT_RESET_PA |r100_mm_wreg(rdev, (0x8020), (((1 << 0) | (1 << 5
) | (1 << 9) | (1 << 14) | (1 << 8) | (1 <<
 10))), 0)
		 SOFT_RESET_SH |r100_mm_wreg(rdev, (0x8020), (((1 << 0) | (1 << 5
) | (1 << 9) | (1 << 14) | (1 << 8) | (1 <<
 10))), 0)
		 SOFT_RESET_VGT |r100_mm_wreg(rdev, (0x8020), (((1 << 0) | (1 << 5
) | (1 << 9) | (1 << 14) | (1 << 8) | (1 <<
 10))), 0)
		 SOFT_RESET_SPI |r100_mm_wreg(rdev, (0x8020), (((1 << 0) | (1 << 5
) | (1 << 9) | (1 << 14) | (1 << 8) | (1 <<
 10))), 0)
		 SOFT_RESET_SX))r100_mm_wreg(rdev, (0x8020), (((1 << 0) | (1 << 5
) | (1 << 9) | (1 << 14) | (1 << 8) | (1 <<
 10))), 0);
RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
mdelay(15);
WREG32(GRBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x8020), (0), 0);
RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);

WREG32(CP_SEM_WAIT_TIMER, 0x0)r100_mm_wreg(rdev, (0x85BC), (0x0), 0);
WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0)r100_mm_wreg(rdev, (0x85C8), (0x0), 0);

/* Set the write pointer delay */
WREG32(CP_RB_WPTR_DELAY, 0)r100_mm_wreg(rdev, (0x8704), (0), 0);

WREG32(CP_DEBUG, (1 << 27))r100_mm_wreg(rdev, (0xC1FC), ((1 << 27)), 0);

/* set the wb address whether it's enabled or not */
WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF)r100_mm_wreg(rdev, (0x8544), (((rdev->wb.gpu_addr + 0) >>
 8) & 0xFFFFFFFF), 0);
WREG32(SCRATCH_UMSK, 0xff)r100_mm_wreg(rdev, (0x8540), (0xff), 0);

for (i = 0; i < 3; ++i) {
uint32_t rb_cntl;
uint64_t addr;

/* Set ring buffer size */
ring = &rdev->ring[ridx[i]];
rb_cntl = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8)drm_order(4096/8) << 8;
1696#ifdef __BIG_ENDIAN
rb_cntl |= BUF_SWAP_32BIT(2 << 16);
1698#endif
WREG32(cp_rb_cntl[i], rb_cntl)r100_mm_wreg(rdev, (cp_rb_cntl[i]), (rb_cntl), 0);

/* set the wb address whether it's enabled or not */
addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET1024;
WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC)r100_mm_wreg(rdev, (cp_rb_rptr_addr[i]), (addr & 0xFFFFFFFC
), 0);
WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF)r100_mm_wreg(rdev, (cp_rb_rptr_addr_hi[i]), (((u32)(((addr) >>
 16) >> 16)) & 0xFF), 0);
}

/* set the rb base addr, this causes an internal reset of ALL rings */
for (i = 0; i < 3; ++i) {
ring = &rdev->ring[ridx[i]];
WREG32(cp_rb_base[i], ring->gpu_addr >> 8)r100_mm_wreg(rdev, (cp_rb_base[i]), (ring->gpu_addr >>
 8), 0);
}

for (i = 0; i < 3; ++i) {
/* Initialize the ring buffer's read and write pointers */
ring = &rdev->ring[ridx[i]];
WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA)do { uint32_t tmp_ = r100_mm_rreg(rdev, (cp_rb_cntl[i]), 0); tmp_
 &= (~(1 << 31)); tmp_ |= (((1 << 31)) & ~
(~(1 << 31))); r100_mm_wreg(rdev, (cp_rb_cntl[i]), (tmp_
), 0); } while (0);

ring->wptr = 0;
WREG32(cp_rb_rptr[i], 0)r100_mm_wreg(rdev, (cp_rb_rptr[i]), (0), 0);
WREG32(cp_rb_wptr[i], ring->wptr)r100_mm_wreg(rdev, (cp_rb_wptr[i]), (ring->wptr), 0);

mdelay(1);
WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA)do { uint32_t tmp_ = r100_mm_rreg(rdev, (cp_rb_cntl[i]), 0); tmp_
 &= (~(1 << 31)); tmp_ |= ((0) & ~(~(1 <<
 31))); r100_mm_wreg(rdev, (cp_rb_cntl[i]), (tmp_), 0); } while
 (0);
}

/* start the rings */
cayman_cp_start(rdev);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ready = true1;
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX1].ready = false0;
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX2].ready = false0;
/* this only test cp0 */
r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX])(rdev)->asic->ring[(0)]->ring_test((rdev), (&rdev
->ring[0]));
if (r) {
rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ready = false0;
rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX1].ready = false0;
rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX2].ready = false0;
return r;
}

if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX0)
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

return 0;
1744}

1746u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1747{
u32 reset_mask = 0;
u32 tmp;

/* GRBM_STATUS */
tmp = RREG32(GRBM_STATUS)r100_mm_rreg(rdev, (0x8010), 0);
if (tmp & (PA_BUSY(1 << 25) | SC_BUSY(1 << 24) |
   SH_BUSY(1 << 21) | SX_BUSY(1 << 20) |
   TA_BUSY(1 << 14) | VGT_BUSY(1 << 17) |
   DB_BUSY(1 << 26) | CB_BUSY(1 << 30) |
   GDS_BUSY(1 << 15) | SPI_BUSY(1 << 22) |
   IA_BUSY(1 << 19) | IA_BUSY_NO_DMA(1 << 18)))
reset_mask |= RADEON_RESET_GFX(1 << 0);

if (tmp & (CF_RQ_PENDING(1 << 7) | PF_RQ_PENDING(1 << 8) |
   CP_BUSY(1 << 29) | CP_COHERENCY_BUSY(1 << 28)))
reset_mask |= RADEON_RESET_CP(1 << 3);

if (tmp & GRBM_EE_BUSY(1 << 10))
reset_mask |= RADEON_RESET_GRBM(1 << 4) | RADEON_RESET_GFX(1 << 0) | RADEON_RESET_CP(1 << 3);

/* DMA_STATUS_REG 0 */
tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET)r100_mm_rreg(rdev, (0xd034 + 0x0), 0);
if (!(tmp & DMA_IDLE(1 << 0)))
reset_mask |= RADEON_RESET_DMA(1 << 2);

/* DMA_STATUS_REG 1 */
tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET)r100_mm_rreg(rdev, (0xd034 + 0x800), 0);
if (!(tmp & DMA_IDLE(1 << 0)))
reset_mask |= RADEON_RESET_DMA1(1 << 5);

/* SRBM_STATUS2 */
tmp = RREG32(SRBM_STATUS2)r100_mm_rreg(rdev, (0x0EC4), 0);
if (tmp & DMA_BUSY(1 << 5))
reset_mask |= RADEON_RESET_DMA(1 << 2);

if (tmp & DMA1_BUSY(1 << 6))
reset_mask |= RADEON_RESET_DMA1(1 << 5);

/* SRBM_STATUS */
tmp = RREG32(SRBM_STATUS)r100_mm_rreg(rdev, (0x0E50), 0);
if (tmp & (RLC_RQ_PENDING(1 << 3) | RLC_BUSY(1 << 15)))
reset_mask |= RADEON_RESET_RLC(1 << 6);

if (tmp & IH_BUSY(1 << 17))
reset_mask |= RADEON_RESET_IH(1 << 8);

if (tmp & SEM_BUSY(1 << 14))
reset_mask |= RADEON_RESET_SEM(1 << 7);

if (tmp & GRBM_RQ_PENDING(1 << 5))
reset_mask |= RADEON_RESET_GRBM(1 << 4);

if (tmp & VMC_BUSY(1 << 8))
reset_mask |= RADEON_RESET_VMC(1 << 9);

if (tmp & (MCB_BUSY(1 << 9) | MCB_NON_DISPLAY_BUSY(1 << 10) |
   MCC_BUSY(1 << 11) | MCD_BUSY(1 << 12)))
reset_mask |= RADEON_RESET_MC(1 << 10);

if (evergreen_is_display_hung(rdev))
reset_mask |= RADEON_RESET_DISPLAY(1 << 11);

/* VM_L2_STATUS */
tmp = RREG32(VM_L2_STATUS)r100_mm_rreg(rdev, (0x140C), 0);
if (tmp & L2_BUSY(1 << 0))
reset_mask |= RADEON_RESET_VMC(1 << 9);

/* Skip MC reset as it's mostly likely not hung, just busy */
if (reset_mask & RADEON_RESET_MC(1 << 10)) {
DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask)__drm_dbg(DRM_UT_CORE, "MC busy: 0x%08X, clearing.\n", reset_mask
);
reset_mask &= ~RADEON_RESET_MC(1 << 10);
}

return reset_mask;
1822}

1824static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1825{
struct evergreen_mc_save save;
u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
u32 tmp;

if (reset_mask == 0)
return;

dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask)do { } while(0);

evergreen_print_gpu_status_regs(rdev);
dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",do { } while(0)
 RREG32(0x14F8))do { } while(0);
dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",do { } while(0)
 RREG32(0x14D8))do { } while(0);
dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",do { } while(0)
 RREG32(0x14FC))do { } while(0);
dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",do { } while(0)
 RREG32(0x14DC))do { } while(0);

/* Disable CP parsing/prefetching */
WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT)r100_mm_wreg(rdev, (0x86D8), ((1 << 28) | (1 << 26
)), 0);

if (reset_mask & RADEON_RESET_DMA(1 << 2)) {
/* dma0 */
tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET)r100_mm_rreg(rdev, (0xd000 + 0x0), 0);
tmp &= ~DMA_RB_ENABLE(1 << 0);
WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp)r100_mm_wreg(rdev, (0xd000 + 0x0), (tmp), 0);
}

if (reset_mask & RADEON_RESET_DMA1(1 << 5)) {
/* dma1 */
tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET)r100_mm_rreg(rdev, (0xd000 + 0x800), 0);
tmp &= ~DMA_RB_ENABLE(1 << 0);
WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp)r100_mm_wreg(rdev, (0xd000 + 0x800), (tmp), 0);
}

udelay(50);

evergreen_mc_stop(rdev, &save);
if (evergreen_mc_wait_for_idle(rdev)) {
dev_warn(rdev->dev, "Wait for MC idle timedout !\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timedout !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

if (reset_mask & (RADEON_RESET_GFX(1 << 0) | RADEON_RESET_COMPUTE(1 << 1))) {
grbm_soft_reset = SOFT_RESET_CB(1 << 1) |
	SOFT_RESET_DB(1 << 3) |
	SOFT_RESET_GDS(1 << 4) |
	SOFT_RESET_PA(1 << 5) |
	SOFT_RESET_SC(1 << 6) |
	SOFT_RESET_SPI(1 << 8) |
	SOFT_RESET_SH(1 << 9) |
	SOFT_RESET_SX(1 << 10) |
	SOFT_RESET_TC(1 << 11) |
	SOFT_RESET_TA(1 << 12) |
	SOFT_RESET_VGT(1 << 14) |
	SOFT_RESET_IA(1 << 15);
}

if (reset_mask & RADEON_RESET_CP(1 << 3)) {
grbm_soft_reset |= SOFT_RESET_CP(1 << 0) | SOFT_RESET_VGT(1 << 14);

srbm_soft_reset |= SOFT_RESET_GRBM(1 << 8);
}

if (reset_mask & RADEON_RESET_DMA(1 << 2))
srbm_soft_reset |= SOFT_RESET_DMA(1 << 20);

if (reset_mask & RADEON_RESET_DMA1(1 << 5))
srbm_soft_reset |= SOFT_RESET_DMA1(1 << 6);

if (reset_mask & RADEON_RESET_DISPLAY(1 << 11))
srbm_soft_reset |= SOFT_RESET_DC(1 << 5);

if (reset_mask & RADEON_RESET_RLC(1 << 6))
srbm_soft_reset |= SOFT_RESET_RLC(1 << 13);

if (reset_mask & RADEON_RESET_SEM(1 << 7))
srbm_soft_reset |= SOFT_RESET_SEM(1 << 15);

if (reset_mask & RADEON_RESET_IH(1 << 8))
srbm_soft_reset |= SOFT_RESET_IH(1 << 10);

if (reset_mask & RADEON_RESET_GRBM(1 << 4))
srbm_soft_reset |= SOFT_RESET_GRBM(1 << 8);

if (reset_mask & RADEON_RESET_VMC(1 << 9))
srbm_soft_reset |= SOFT_RESET_VMC(1 << 17);

if (!(rdev->flags & RADEON_IS_IGP)) {
if (reset_mask & RADEON_RESET_MC(1 << 10))
	srbm_soft_reset |= SOFT_RESET_MC(1 << 11);
}

if (grbm_soft_reset) {
tmp = RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
tmp |= grbm_soft_reset;
dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
WREG32(GRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0x8020), (tmp), 0);
tmp = RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);

udelay(50);

tmp &= ~grbm_soft_reset;
WREG32(GRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0x8020), (tmp), 0);
tmp = RREG32(GRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x8020), 0);
}

if (srbm_soft_reset) {
tmp = RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0E60), 0);
tmp |= srbm_soft_reset;
dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
WREG32(SRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0x0E60), (tmp), 0);
tmp = RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0E60), 0);

udelay(50);

tmp &= ~srbm_soft_reset;
WREG32(SRBM_SOFT_RESET, tmp)r100_mm_wreg(rdev, (0x0E60), (tmp), 0);
tmp = RREG32(SRBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0E60), 0);
}

/* Wait a little for things to settle down */
udelay(50);

evergreen_mc_resume(rdev, &save);
udelay(50);

evergreen_print_gpu_status_regs(rdev);
1954}

1956int cayman_asic_reset(struct radeon_device *rdev, bool_Bool hard)
1957{
u32 reset_mask;

if (hard) {
evergreen_gpu_pci_config_reset(rdev);
return 0;
}

reset_mask = cayman_gpu_check_soft_reset(rdev);

if (reset_mask)
r600_set_bios_scratch_engine_hung(rdev, true1);

cayman_gpu_soft_reset(rdev, reset_mask);

reset_mask = cayman_gpu_check_soft_reset(rdev);

if (reset_mask)
evergreen_gpu_pci_config_reset(rdev);

r600_set_bios_scratch_engine_hung(rdev, false0);

return 0;
1980}

1982/**
* cayman_gfx_is_lockup - Check if the GFX engine is locked up
*
* @rdev: radeon_device pointer
* @ring: radeon_ring structure holding ring information
*
* Check if the GFX engine is locked up.
* Returns true if the engine appears to be locked up, false if not.
*/
1991bool_Bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1992{
u32 reset_mask = cayman_gpu_check_soft_reset(rdev);

if (!(reset_mask & (RADEON_RESET_GFX(1 << 0) |
	    RADEON_RESET_COMPUTE(1 << 1) |
	    RADEON_RESET_CP(1 << 3)))) {
radeon_ring_lockup_update(rdev, ring);
return false0;
}
return radeon_ring_test_lockup(rdev, ring);
2002}

2004static void cayman_uvd_init(struct radeon_device *rdev)
2005{
int r;

if (!rdev->has_uvd)
return;

r = radeon_uvd_init(rdev);
if (r) {
dev_err(rdev->dev, "failed UVD (%d) init.\n", r)printf("drm:pid%d:%s *ERROR* " "failed UVD (%d) init.\n", ({struct
 cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__ , r);
/*
 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
 * to early fails uvd_v2_2_resume() and thus nothing happens
 * there. So it is pointless to try to go through that code
 * hence why we disable uvd here.
 */
rdev->has_uvd = false0;
return;
}
rdev->ring[R600_RING_TYPE_UVD_INDEX5].ring_obj = NULL((void *)0);
r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX5], 4096);
2025}

2027static void cayman_uvd_start(struct radeon_device *rdev)
2028{
int r;

if (!rdev->has_uvd)
return;

r = uvd_v2_2_resume(rdev);
if (r) {
dev_err(rdev->dev, "failed UVD resume (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed UVD resume (%d).\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
goto error;
}
r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX5);
if (r) {
dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing UVD fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
goto error;
}
return;

2046error:
rdev->ring[R600_RING_TYPE_UVD_INDEX5].ring_size = 0;
2048}

2050static void cayman_uvd_resume(struct radeon_device *rdev)
2051{
struct radeon_ring *ring;
int r;

if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX5].ring_size)
return;

ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX5];
r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)((0 << 30) | (((0xEFFC) >> 2) & 0xFFFF) | ((0
) & 0x3FFF) << 16));
if (r) {
dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing UVD ring (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return;
}
r = uvd_v1_0_init(rdev);
if (r) {
dev_err(rdev->dev, "failed initializing UVD (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing UVD (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return;
}
2069}

2071static void cayman_vce_init(struct radeon_device *rdev)
2072{
int r;

/* Only set for CHIP_ARUBA */
if (!rdev->has_vce)
return;

r = radeon_vce_init(rdev);
if (r) {
dev_err(rdev->dev, "failed VCE (%d) init.\n", r)printf("drm:pid%d:%s *ERROR* " "failed VCE (%d) init.\n", ({struct
 cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__ , r);
/*
 * At this point rdev->vce.vcpu_bo is NULL which trickles down
 * to early fails cayman_vce_start() and thus nothing happens
 * there. So it is pointless to try to go through that code
 * hence why we disable vce here.
 */
rdev->has_vce = false0;
return;
}
rdev->ring[TN_RING_TYPE_VCE1_INDEX6].ring_obj = NULL((void *)0);
r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX6], 4096);
rdev->ring[TN_RING_TYPE_VCE2_INDEX7].ring_obj = NULL((void *)0);
r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX7], 4096);
2095}

2097static void cayman_vce_start(struct radeon_device *rdev)
2098{
int r;

if (!rdev->has_vce)
return;

r = radeon_vce_resume(rdev);
if (r) {
dev_err(rdev->dev, "failed VCE resume (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed VCE resume (%d).\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
goto error;
}
r = vce_v1_0_resume(rdev);
if (r) {
dev_err(rdev->dev, "failed VCE resume (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed VCE resume (%d).\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
goto error;
}
r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX6);
if (r) {
dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing VCE1 fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
goto error;
}
r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX7);
if (r) {
dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing VCE2 fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
goto error;
}
return;

2126error:
rdev->ring[TN_RING_TYPE_VCE1_INDEX6].ring_size = 0;
rdev->ring[TN_RING_TYPE_VCE2_INDEX7].ring_size = 0;
2129}

2131static void cayman_vce_resume(struct radeon_device *rdev)
2132{
struct radeon_ring *ring;
int r;

if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX6].ring_size)
return;

ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX6];
r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
if (r) {
dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing VCE1 ring (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return;
}
ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX7];
r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
if (r) {
dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing VCE1 ring (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return;
}
r = vce_v1_0_init(rdev);
if (r) {
dev_err(rdev->dev, "failed initializing VCE (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing VCE (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return;
}
2156}

2158static int cayman_startup(struct radeon_device *rdev)
2159{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
int r;

/* enable pcie gen2 link */
evergreen_pcie_gen2_enable(rdev);
/* enable aspm */
evergreen_program_aspm(rdev);

/* scratch needs to be initialized before MC */
r = r600_vram_scratch_init(rdev);
if (r)
return r;

evergreen_mc_program(rdev);

if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
r = ni_mc_load_microcode(rdev);
if (r) {
	DRM_ERROR("Failed to load MC firmware!\n")__drm_err("Failed to load MC firmware!\n");
	return r;
}
}

r = cayman_pcie_gart_enable(rdev);
if (r)
return r;
cayman_gpu_init(rdev);

/* allocate rlc buffers */
if (rdev->flags & RADEON_IS_IGP) {
rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
rdev->rlc.reg_list_size =
	(u32)ARRAY_SIZE(tn_rlc_save_restore_register_list)(sizeof((tn_rlc_save_restore_register_list)) / sizeof((tn_rlc_save_restore_register_list
)[0]));
rdev->rlc.cs_data = cayman_cs_data;
r = sumo_rlc_init(rdev);
if (r) {
	DRM_ERROR("Failed to init rlc BOs!\n")__drm_err("Failed to init rlc BOs!\n");
	return r;
}
}

/* allocate wb buffer */
r = radeon_wb_init(rdev);
if (r)
return r;

r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX0);
if (r) {
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

cayman_uvd_start(rdev);
cayman_vce_start(rdev);

r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX1);
if (r) {
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX2);
if (r) {
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX3);
if (r) {
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing DMA fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX4);
if (r) {
dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing DMA fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

/* Enable IRQ */
if (!rdev->irq.installed) {
r = radeon_irq_kms_init(rdev);
if (r)
	return r;
}

r = r600_irq_init(rdev);
if (r) {
DRM_ERROR("radeon: IH init failed (%d).\n", r)__drm_err("radeon: IH init failed (%d).\n", r);
radeon_irq_kms_fini(rdev);
return r;
}
evergreen_irq_set(rdev);

r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET1024,
	     RADEON_CP_PACKET20x80000000);
if (r)
return r;

ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX3];
r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET1792,
	     DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)((((0xf) & 0xF) << 28) | (((0) & 0x1) << 23
) | (((0) & 0x1) << 22) | (((0) & 0xFFFFF) <<
 0)));
if (r)
return r;

ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX4];
r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET2304,
	     DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)((((0xf) & 0xF) << 28) | (((0) & 0x1) << 23
) | (((0) & 0x1) << 22) | (((0) & 0xFFFFF) <<
 0)));
if (r)
return r;

r = cayman_cp_load_microcode(rdev);
if (r)
return r;
r = cayman_cp_resume(rdev);
if (r)
return r;

r = cayman_dma_resume(rdev);
if (r)
return r;

cayman_uvd_resume(rdev);
cayman_vce_resume(rdev);

r = radeon_ib_pool_init(rdev);
if (r) {
dev_err(rdev->dev, "IB initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "IB initialization failed (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

r = radeon_vm_manager_init(rdev);
if (r) {
dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "vm manager initialization failed (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

r = radeon_audio_init(rdev);
if (r)
return r;

return 0;
2302}

2304int cayman_resume(struct radeon_device *rdev)
2305{
int r;

/* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
* posting will perform necessary task to bring back GPU into good
* shape.
*/
/* post card */
atom_asic_init(rdev->mode_info.atom_context);

/* init golden registers */
ni_init_golden_registers(rdev);

if (rdev->pm.pm_method == PM_METHOD_DPM)
radeon_pm_resume(rdev);

rdev->accel_working = true1;
r = cayman_startup(rdev);
if (r) {
DRM_ERROR("cayman startup failed on resume\n")__drm_err("cayman startup failed on resume\n");
rdev->accel_working = false0;
return r;
}
return r;
2329}

2331int cayman_suspend(struct radeon_device *rdev)
2332{
radeon_pm_suspend(rdev);
radeon_audio_fini(rdev);
radeon_vm_manager_fini(rdev);
cayman_cp_enable(rdev, false0);
cayman_dma_stop(rdev);
if (rdev->has_uvd) {
uvd_v1_0_fini(rdev);
radeon_uvd_suspend(rdev);
}
evergreen_irq_suspend(rdev);
radeon_wb_disable(rdev);
cayman_pcie_gart_disable(rdev);
return 0;
2346}

2348/* Plan is to move initialization in that function and use
* helper function so that radeon_device_init pretty much
* do nothing more than calling asic specific function. This
* should also allow to remove a bunch of callback function
* like vram_info.
*/
2354int cayman_init(struct radeon_device *rdev)
2355{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
int r;

/* Read BIOS */
if (!radeon_get_bios(rdev)) {
1
Assuming the condition is false→
2
←
Taking false branch→
if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
	return -EINVAL22;
}
/* Must be an ATOMBIOS */
if (!rdev->is_atom_bios) {
3
←
Assuming field 'is_atom_bios' is true→
4
←
Taking false branch→
dev_err(rdev->dev, "Expecting atombios for cayman GPU\n")printf("drm:pid%d:%s *ERROR* " "Expecting atombios for cayman GPU\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
}
r = radeon_atombios_init(rdev);
if (r)
5
←
Assuming 'r' is 0→
6
←
Taking false branch→
return r;

/* Post card if necessary */
if (!radeon_card_posted(rdev)) {
7
←
Assuming the condition is false→
8
←
Taking false branch→
if (!rdev->bios) {
	dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n")printf("drm:pid%d:%s *ERROR* " "Card not posted and no BIOS - ignoring\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
	return -EINVAL22;
}
DRM_INFO("GPU not posted. posting now...\n")printk("\0016" "[" "drm" "] " "GPU not posted. posting now...\n"
);
atom_asic_init(rdev->mode_info.atom_context);
}
/* init golden registers */
ni_init_golden_registers(rdev);
9
←
Calling 'ni_init_golden_registers'→
14
←
Returning from 'ni_init_golden_registers'→
/* Initialize scratch registers */
r600_scratch_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
/* Initialize clocks */
radeon_get_clock_info(rdev->ddev);
/* Fence driver */
r = radeon_fence_driver_init(rdev);
if (r)
15
←
Assuming 'r' is 0→
16
←
Taking false branch→
return r;
/* initialize memory controller */
r = evergreen_mc_init(rdev);
if (r)
17
←
Assuming 'r' is 0→
18
←
Taking false branch→
return r;
/* Memory manager */
r = radeon_bo_init(rdev);
if (r)
19
←
Assuming 'r' is 0→
20
←
Taking false branch→
return r;

if (rdev->flags & RADEON_IS_IGP) {
21
←
Assuming the condition is true→
22
←
Taking true branch→
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
23
←
Assuming field 'me_fw' is null→
	r = ni_init_microcode(rdev);
24
←
Calling 'ni_init_microcode'→
	if (r) {
		DRM_ERROR("Failed to load firmware!\n")__drm_err("Failed to load firmware!\n");
		return r;
	}
}
} else {
if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
	r = ni_init_microcode(rdev);
	if (r) {
		DRM_ERROR("Failed to load firmware!\n")__drm_err("Failed to load firmware!\n");
		return r;
	}
}
}

/* Initialize power management */
radeon_pm_init(rdev);

ring->ring_obj = NULL((void *)0);
r600_ring_init(rdev, ring, 1024 * 1024);

ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX3];
ring->ring_obj = NULL((void *)0);
r600_ring_init(rdev, ring, 64 * 1024);

ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX4];
ring->ring_obj = NULL((void *)0);
r600_ring_init(rdev, ring, 64 * 1024);

cayman_uvd_init(rdev);
cayman_vce_init(rdev);

rdev->ih.ring_obj = NULL((void *)0);
r600_ih_ring_init(rdev, 64 * 1024);

r = r600_pcie_gart_init(rdev);
if (r)
return r;

rdev->accel_working = true1;
r = cayman_startup(rdev);
if (r) {
dev_err(rdev->dev, "disabling GPU acceleration\n")printf("drm:pid%d:%s *ERROR* " "disabling GPU acceleration\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
cayman_cp_fini(rdev);
cayman_dma_fini(rdev);
r600_irq_fini(rdev);
if (rdev->flags & RADEON_IS_IGP)
	sumo_rlc_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_vm_manager_fini(rdev);
radeon_irq_kms_fini(rdev);
cayman_pcie_gart_fini(rdev);
rdev->accel_working = false0;
}

/* Don't start up if the MC ucode is missing.
* The default clocks and voltages before the MC ucode
* is loaded are not suffient for advanced operations.
*
* We can skip this check for TN, because there is no MC
* ucode.
*/
if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
DRM_ERROR("radeon: MC ucode required for NI+.\n")__drm_err("radeon: MC ucode required for NI+.\n");
return -EINVAL22;
}

return 0;
2475}

2477void cayman_fini(struct radeon_device *rdev)
2478{
radeon_pm_fini(rdev);
cayman_cp_fini(rdev);
cayman_dma_fini(rdev);
r600_irq_fini(rdev);
if (rdev->flags & RADEON_IS_IGP)
sumo_rlc_fini(rdev);
radeon_wb_fini(rdev);
radeon_vm_manager_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev);
uvd_v1_0_fini(rdev);
radeon_uvd_fini(rdev);
if (rdev->has_vce)
radeon_vce_fini(rdev);
cayman_pcie_gart_fini(rdev);
r600_vram_scratch_fini(rdev);
radeon_gem_fini(rdev);
radeon_fence_driver_fini(rdev);
radeon_bo_fini(rdev);
radeon_atombios_fini(rdev);
kfree(rdev->bios);
rdev->bios = NULL((void *)0);
2501}

2503/*
* vm
*/
2506int cayman_vm_init(struct radeon_device *rdev)
2507{
/* number of VMs */
rdev->vm_manager.nvm = 8;
/* base offset of vram pages */
if (rdev->flags & RADEON_IS_IGP) {
u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET)r100_mm_rreg(rdev, (0x2068), 0);
tmp <<= 22;
rdev->vm_manager.vram_base_offset = tmp;
} else
rdev->vm_manager.vram_base_offset = 0;
return 0;
2518}

2520void cayman_vm_fini(struct radeon_device *rdev)
2521{
2522}

2524/**
* cayman_vm_decode_fault - print human readable fault info
*
* @rdev: radeon_device pointer
* @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
* @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
*
* Print human readable fault information (cayman/TN).
*/
2533void cayman_vm_decode_fault(struct radeon_device *rdev,
	    u32 status, u32 addr)
2535{
u32 mc_id = (status & MEMORY_CLIENT_ID_MASK(0xff << 12)) >> MEMORY_CLIENT_ID_SHIFT12;
u32 vmid = (status & FAULT_VMID_MASK(0x7 << 25)) >> FAULT_VMID_SHIFT25;
u32 protections = (status & PROTECTIONS_MASK(0xf << 0)) >> PROTECTIONS_SHIFT0;
char *block;

switch (mc_id) {
case 32:
case 16:
case 96:
case 80:
case 160:
case 144:
case 224:
case 208:
block = "CB";
break;
case 33:
case 17:
case 97:
case 81:
case 161:
case 145:
case 225:
case 209:
block = "CB_FMASK";
break;
case 34:
case 18:
case 98:
case 82:
case 162:
case 146:
case 226:
case 210:
block = "CB_CMASK";
break;
case 35:
case 19:
case 99:
case 83:
case 163:
case 147:
case 227:
case 211:
block = "CB_IMMED";
break;
case 36:
case 20:
case 100:
case 84:
case 164:
case 148:
case 228:
case 212:
block = "DB";
break;
case 37:
case 21:
case 101:
case 85:
case 165:
case 149:
case 229:
case 213:
block = "DB_HTILE";
break;
case 38:
case 22:
case 102:
case 86:
case 166:
case 150:
case 230:
case 214:
block = "SX";
break;
case 39:
case 23:
case 103:
case 87:
case 167:
case 151:
case 231:
case 215:
block = "DB_STEN";
break;
case 40:
case 24:
case 104:
case 88:
case 232:
case 216:
case 168:
case 152:
block = "TC_TFETCH";
break;
case 41:
case 25:
case 105:
case 89:
case 233:
case 217:
case 169:
case 153:
block = "TC_VFETCH";
break;
case 42:
case 26:
case 106:
case 90:
case 234:
case 218:
case 170:
case 154:
block = "VC";
break;
case 112:
block = "CP";
break;
case 113:
case 114:
block = "SH";
break;
case 115:
block = "VGT";
break;
case 178:
block = "IH";
break;
case 51:
block = "RLC";
break;
case 55:
block = "DMA";
break;
case 56:
block = "HDP";
break;
default:
block = "unknown";
break;
}

printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
      protections, vmid, addr,
      (status & MEMORY_CLIENT_RW_MASK(1 << 24)) ? "write" : "read",
      block, mc_id);
2683}

2685/**
* cayman_vm_flush - vm flush using the CP
*
* @rdev: radeon_device pointer
*
* Update the page table base and flush the VM TLB
* using the CP (cayman-si).
*/
2693void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
     unsigned vm_id, uint64_t pd_addr)
2695{
radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)((0 << 30) | (((0x153C + (vm_id << 2)) >> 2
) & 0xFFFF) | ((0) & 0x3FFF) << 16));
radeon_ring_write(ring, pd_addr >> 12);

/* flush hdp cache */
radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)((0 << 30) | (((0x5480) >> 2) & 0xFFFF) | ((0
) & 0x3FFF) << 16));
radeon_ring_write(ring, 0x1);

/* bits 0-7 are the VM contexts0-7 */
radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)((0 << 30) | (((0x1478) >> 2) & 0xFFFF) | ((0
) & 0x3FFF) << 16));
radeon_ring_write(ring, 1 << vm_id);

/* wait for the invalidate to complete */
radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)((3 << 30) | (((0x3C) & 0xFF) << 8) | ((5) &
 0x3FFF) << 16));
radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0)((0) << 0) |  /* always */
		 WAIT_REG_MEM_ENGINE(0)((0) << 8))); /* me */
radeon_ring_write(ring, VM_INVALIDATE_REQUEST0x1478 >> 2);
radeon_ring_write(ring, 0);
radeon_ring_write(ring, 0); /* ref */
radeon_ring_write(ring, 0); /* mask */
radeon_ring_write(ring, 0x20); /* poll interval */

/* sync PFP to ME, otherwise we might get invalid PFP reads */
radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)((3 << 30) | (((0x42) & 0xFF) << 8) | ((0) &
 0x3FFF) << 16));
radeon_ring_write(ring, 0x0);
2720}

2722int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
2723{
struct atom_clock_dividers dividers;
int r, i;

r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM2,
			   ecclk, false0, &dividers);
if (r)
return r;

for (i = 0; i < 100; i++) {
if (RREG32(CG_ECLK_STATUS)r100_mm_rreg(rdev, (0x624), 0) & ECLK_STATUS(1 << 0))
	break;
mdelay(10);
}
if (i == 100)
return -ETIMEDOUT60;

WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK))do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x620), 0); tmp_ &=
 (~((1 << 8)|0x7f)); tmp_ |= ((dividers.post_div) &
 ~(~((1 << 8)|0x7f))); r100_mm_wreg(rdev, (0x620), (tmp_
), 0); } while (0);

for (i = 0; i < 100; i++) {
if (RREG32(CG_ECLK_STATUS)r100_mm_rreg(rdev, (0x624), 0) & ECLK_STATUS(1 << 0))
	break;
mdelay(10);
}
if (i == 100)
return -ETIMEDOUT60;

return 0;
2751}

←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2 
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5 
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11 
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var))	((type)(__uintptr_t)(const void *)(var))
14#endif
15 
16struct firmware {
17	size_t size;
18	const u8 *data;
19};
20 
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23    struct device *device)
24{
25	int r;
26	struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27	    M_WAITOK0x0001 | M_ZERO0x0008);
28	r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29	if (r != 0) {
28
←
Assuming 'r' is equal to 0→
29
←
Taking false branch→
36
←
Assuming 'r' is not equal to 0→
37
←
Taking true branch→
30		free(f, M_DRM145, sizeof(struct firmware));
31		*fw = NULL((void *)0);
38
←
Null pointer value stored to field 'me_fw'→
32		return -r;
33	} else  {
34		*fw = f;
35		return 0;
30
←
Returning zero, which participates in a condition later→
36	}
37}
38 
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41    struct device *device)
42{
43	return request_firmware(fw, name, device);
44}
45 
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47 
48static inline void
49release_firmware(const struct firmware *fw)
50{
51	if (fw)
52		free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53	free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55 
56#endif