File: | dev/pci/drm/amd/amdgpu/gfx_v8_0.c |
Warning: | line 1071, column 2 Value stored to 'err' is never read |
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1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | * |
22 | */ |
23 | |
24 | #include <linux/delay.h> |
25 | #include <linux/kernel.h> |
26 | #include <linux/firmware.h> |
27 | #include <linux/module.h> |
28 | #include <linux/pci.h> |
29 | |
30 | #include "amdgpu.h" |
31 | #include "amdgpu_gfx.h" |
32 | #include "vi.h" |
33 | #include "vi_structs.h" |
34 | #include "vid.h" |
35 | #include "amdgpu_ucode.h" |
36 | #include "amdgpu_atombios.h" |
37 | #include "atombios_i2c.h" |
38 | #include "clearstate_vi.h" |
39 | |
40 | #include "gmc/gmc_8_2_d.h" |
41 | #include "gmc/gmc_8_2_sh_mask.h" |
42 | |
43 | #include "oss/oss_3_0_d.h" |
44 | #include "oss/oss_3_0_sh_mask.h" |
45 | |
46 | #include "bif/bif_5_0_d.h" |
47 | #include "bif/bif_5_0_sh_mask.h" |
48 | #include "gca/gfx_8_0_d.h" |
49 | #include "gca/gfx_8_0_enum.h" |
50 | #include "gca/gfx_8_0_sh_mask.h" |
51 | |
52 | #include "dce/dce_10_0_d.h" |
53 | #include "dce/dce_10_0_sh_mask.h" |
54 | |
55 | #include "smu/smu_7_1_3_d.h" |
56 | |
57 | #include "ivsrcid/ivsrcid_vislands30.h" |
58 | |
59 | #define GFX8_NUM_GFX_RINGS1 1 |
60 | #define GFX8_MEC_HPD_SIZE4096 4096 |
61 | |
62 | #define TOPAZ_GB_ADDR_CONFIG_GOLDEN0x22010001 0x22010001 |
63 | #define CARRIZO_GB_ADDR_CONFIG_GOLDEN0x22010001 0x22010001 |
64 | #define POLARIS11_GB_ADDR_CONFIG_GOLDEN0x22011002 0x22011002 |
65 | #define TONGA_GB_ADDR_CONFIG_GOLDEN0x22011003 0x22011003 |
66 | |
67 | #define ARRAY_MODE(x)((x) << 0x2) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT0x2) |
68 | #define PIPE_CONFIG(x)((x) << 0x6) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT0x6) |
69 | #define TILE_SPLIT(x)((x) << 0xb) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT0xb) |
70 | #define MICRO_TILE_MODE_NEW(x)((x) << 0x16) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT0x16) |
71 | #define SAMPLE_SPLIT(x)((x) << 0x19) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT0x19) |
72 | #define BANK_WIDTH(x)((x) << 0x0) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT0x0) |
73 | #define BANK_HEIGHT(x)((x) << 0x2) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT0x2) |
74 | #define MACRO_TILE_ASPECT(x)((x) << 0x4) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT0x4) |
75 | #define NUM_BANKS(x)((x) << 0x6) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT0x6) |
76 | |
77 | #define RLC_CGTT_MGCG_OVERRIDE__CPF_MASK0x00000001L 0x00000001L |
78 | #define RLC_CGTT_MGCG_OVERRIDE__RLC_MASK0x00000002L 0x00000002L |
79 | #define RLC_CGTT_MGCG_OVERRIDE__MGCG_MASK0x00000004L 0x00000004L |
80 | #define RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK0x00000008L 0x00000008L |
81 | #define RLC_CGTT_MGCG_OVERRIDE__CGLS_MASK0x00000010L 0x00000010L |
82 | #define RLC_CGTT_MGCG_OVERRIDE__GRBM_MASK0x00000020L 0x00000020L |
83 | |
84 | /* BPM SERDES CMD */ |
85 | #define SET_BPM_SERDES_CMD1 1 |
86 | #define CLE_BPM_SERDES_CMD0 0 |
87 | |
88 | /* BPM Register Address*/ |
89 | enum { |
90 | BPM_REG_CGLS_EN = 0, /* Enable/Disable CGLS */ |
91 | BPM_REG_CGLS_ON, /* ON/OFF CGLS: shall be controlled by RLC FW */ |
92 | BPM_REG_CGCG_OVERRIDE, /* Set/Clear CGCG Override */ |
93 | BPM_REG_MGCG_OVERRIDE, /* Set/Clear MGCG Override */ |
94 | BPM_REG_FGCG_OVERRIDE, /* Set/Clear FGCG Override */ |
95 | BPM_REG_FGCG_MAX |
96 | }; |
97 | |
98 | #define RLC_FormatDirectRegListLength14 14 |
99 | |
100 | MODULE_FIRMWARE("amdgpu/carrizo_ce.bin"); |
101 | MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin"); |
102 | MODULE_FIRMWARE("amdgpu/carrizo_me.bin"); |
103 | MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); |
104 | MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); |
105 | MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); |
106 | |
107 | MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); |
108 | MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); |
109 | MODULE_FIRMWARE("amdgpu/stoney_me.bin"); |
110 | MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); |
111 | MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); |
112 | |
113 | MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); |
114 | MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); |
115 | MODULE_FIRMWARE("amdgpu/tonga_me.bin"); |
116 | MODULE_FIRMWARE("amdgpu/tonga_mec.bin"); |
117 | MODULE_FIRMWARE("amdgpu/tonga_mec2.bin"); |
118 | MODULE_FIRMWARE("amdgpu/tonga_rlc.bin"); |
119 | |
120 | MODULE_FIRMWARE("amdgpu/topaz_ce.bin"); |
121 | MODULE_FIRMWARE("amdgpu/topaz_pfp.bin"); |
122 | MODULE_FIRMWARE("amdgpu/topaz_me.bin"); |
123 | MODULE_FIRMWARE("amdgpu/topaz_mec.bin"); |
124 | MODULE_FIRMWARE("amdgpu/topaz_rlc.bin"); |
125 | |
126 | MODULE_FIRMWARE("amdgpu/fiji_ce.bin"); |
127 | MODULE_FIRMWARE("amdgpu/fiji_pfp.bin"); |
128 | MODULE_FIRMWARE("amdgpu/fiji_me.bin"); |
129 | MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); |
130 | MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); |
131 | MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); |
132 | |
133 | MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); |
134 | MODULE_FIRMWARE("amdgpu/polaris10_ce_2.bin"); |
135 | MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); |
136 | MODULE_FIRMWARE("amdgpu/polaris10_pfp_2.bin"); |
137 | MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); |
138 | MODULE_FIRMWARE("amdgpu/polaris10_me_2.bin"); |
139 | MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); |
140 | MODULE_FIRMWARE("amdgpu/polaris10_mec_2.bin"); |
141 | MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); |
142 | MODULE_FIRMWARE("amdgpu/polaris10_mec2_2.bin"); |
143 | MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); |
144 | |
145 | MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); |
146 | MODULE_FIRMWARE("amdgpu/polaris11_ce_2.bin"); |
147 | MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); |
148 | MODULE_FIRMWARE("amdgpu/polaris11_pfp_2.bin"); |
149 | MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); |
150 | MODULE_FIRMWARE("amdgpu/polaris11_me_2.bin"); |
151 | MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); |
152 | MODULE_FIRMWARE("amdgpu/polaris11_mec_2.bin"); |
153 | MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); |
154 | MODULE_FIRMWARE("amdgpu/polaris11_mec2_2.bin"); |
155 | MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); |
156 | |
157 | MODULE_FIRMWARE("amdgpu/polaris12_ce.bin"); |
158 | MODULE_FIRMWARE("amdgpu/polaris12_ce_2.bin"); |
159 | MODULE_FIRMWARE("amdgpu/polaris12_pfp.bin"); |
160 | MODULE_FIRMWARE("amdgpu/polaris12_pfp_2.bin"); |
161 | MODULE_FIRMWARE("amdgpu/polaris12_me.bin"); |
162 | MODULE_FIRMWARE("amdgpu/polaris12_me_2.bin"); |
163 | MODULE_FIRMWARE("amdgpu/polaris12_mec.bin"); |
164 | MODULE_FIRMWARE("amdgpu/polaris12_mec_2.bin"); |
165 | MODULE_FIRMWARE("amdgpu/polaris12_mec2.bin"); |
166 | MODULE_FIRMWARE("amdgpu/polaris12_mec2_2.bin"); |
167 | MODULE_FIRMWARE("amdgpu/polaris12_rlc.bin"); |
168 | |
169 | MODULE_FIRMWARE("amdgpu/vegam_ce.bin"); |
170 | MODULE_FIRMWARE("amdgpu/vegam_pfp.bin"); |
171 | MODULE_FIRMWARE("amdgpu/vegam_me.bin"); |
172 | MODULE_FIRMWARE("amdgpu/vegam_mec.bin"); |
173 | MODULE_FIRMWARE("amdgpu/vegam_mec2.bin"); |
174 | MODULE_FIRMWARE("amdgpu/vegam_rlc.bin"); |
175 | |
176 | static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = |
177 | { |
178 | {mmGDS_VMID0_BASE0x3300, mmGDS_VMID0_SIZE0x3301, mmGDS_GWS_VMID00x3320, mmGDS_OA_VMID00x3330}, |
179 | {mmGDS_VMID1_BASE0x3302, mmGDS_VMID1_SIZE0x3303, mmGDS_GWS_VMID10x3321, mmGDS_OA_VMID10x3331}, |
180 | {mmGDS_VMID2_BASE0x3304, mmGDS_VMID2_SIZE0x3305, mmGDS_GWS_VMID20x3322, mmGDS_OA_VMID20x3332}, |
181 | {mmGDS_VMID3_BASE0x3306, mmGDS_VMID3_SIZE0x3307, mmGDS_GWS_VMID30x3323, mmGDS_OA_VMID30x3333}, |
182 | {mmGDS_VMID4_BASE0x3308, mmGDS_VMID4_SIZE0x3309, mmGDS_GWS_VMID40x3324, mmGDS_OA_VMID40x3334}, |
183 | {mmGDS_VMID5_BASE0x330a, mmGDS_VMID5_SIZE0x330b, mmGDS_GWS_VMID50x3325, mmGDS_OA_VMID50x3335}, |
184 | {mmGDS_VMID6_BASE0x330c, mmGDS_VMID6_SIZE0x330d, mmGDS_GWS_VMID60x3326, mmGDS_OA_VMID60x3336}, |
185 | {mmGDS_VMID7_BASE0x330e, mmGDS_VMID7_SIZE0x330f, mmGDS_GWS_VMID70x3327, mmGDS_OA_VMID70x3337}, |
186 | {mmGDS_VMID8_BASE0x3310, mmGDS_VMID8_SIZE0x3311, mmGDS_GWS_VMID80x3328, mmGDS_OA_VMID80x3338}, |
187 | {mmGDS_VMID9_BASE0x3312, mmGDS_VMID9_SIZE0x3313, mmGDS_GWS_VMID90x3329, mmGDS_OA_VMID90x3339}, |
188 | {mmGDS_VMID10_BASE0x3314, mmGDS_VMID10_SIZE0x3315, mmGDS_GWS_VMID100x332a, mmGDS_OA_VMID100x333a}, |
189 | {mmGDS_VMID11_BASE0x3316, mmGDS_VMID11_SIZE0x3317, mmGDS_GWS_VMID110x332b, mmGDS_OA_VMID110x333b}, |
190 | {mmGDS_VMID12_BASE0x3318, mmGDS_VMID12_SIZE0x3319, mmGDS_GWS_VMID120x332c, mmGDS_OA_VMID120x333c}, |
191 | {mmGDS_VMID13_BASE0x331a, mmGDS_VMID13_SIZE0x331b, mmGDS_GWS_VMID130x332d, mmGDS_OA_VMID130x333d}, |
192 | {mmGDS_VMID14_BASE0x331c, mmGDS_VMID14_SIZE0x331d, mmGDS_GWS_VMID140x332e, mmGDS_OA_VMID140x333e}, |
193 | {mmGDS_VMID15_BASE0x331e, mmGDS_VMID15_SIZE0x331f, mmGDS_GWS_VMID150x332f, mmGDS_OA_VMID150x333f} |
194 | }; |
195 | |
196 | static const u32 golden_settings_tonga_a11[] = |
197 | { |
198 | mmCB_HW_CONTROL0x2684, 0xfffdf3cf, 0x00007208, |
199 | mmCB_HW_CONTROL_30x2683, 0x00000040, 0x00000040, |
200 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
201 | mmGB_GPU_ID0x2640, 0x0000000f, 0x00000000, |
202 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
203 | mmPA_SC_FIFO_DEPTH_CNTL0x2295, 0x000003ff, 0x000000fc, |
204 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
205 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0000003c, |
206 | mmSQ_RANDOM_WAVE_PRI0x2303, 0x001fffff, 0x000006fd, |
207 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
208 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
209 | mmTCC_EXE_DISABLE0x2b84, 0x00000002, 0x00000002, |
210 | mmTCP_ADDR_CONFIG0x2b05, 0x000003ff, 0x000002fb, |
211 | mmTCP_CHAN_STEER_HI0x2b04, 0xffffffff, 0x0000543b, |
212 | mmTCP_CHAN_STEER_LO0x2b03, 0xffffffff, 0xa9210876, |
213 | mmVGT_RESET_DEBUG0x2232, 0x00000004, 0x00000004, |
214 | }; |
215 | |
216 | static const u32 tonga_golden_common_all[] = |
217 | { |
218 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
219 | mmPA_SC_RASTER_CONFIG0xa0d4, 0xffffffff, 0x16000012, |
220 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0xffffffff, 0x0000002A, |
221 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22011003, |
222 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
223 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
224 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
225 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF |
226 | }; |
227 | |
228 | static const u32 tonga_mgcg_cgcg_init[] = |
229 | { |
230 | mmRLC_CGTT_MGCG_OVERRIDE0xec48, 0xffffffff, 0xffffffff, |
231 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
232 | mmCB_CGTT_SCLK_CTRL0xf0a8, 0xffffffff, 0x00000100, |
233 | mmCGTT_BCI_CLK_CTRL0xf082, 0xffffffff, 0x00000100, |
234 | mmCGTT_CP_CLK_CTRL0xf0b0, 0xffffffff, 0x00000100, |
235 | mmCGTT_CPC_CLK_CTRL0xf0b2, 0xffffffff, 0x00000100, |
236 | mmCGTT_CPF_CLK_CTRL0xf0b1, 0xffffffff, 0x40000100, |
237 | mmCGTT_GDS_CLK_CTRL0xf0a0, 0xffffffff, 0x00000100, |
238 | mmCGTT_IA_CLK_CTRL0xf085, 0xffffffff, 0x06000100, |
239 | mmCGTT_PA_CLK_CTRL0xf088, 0xffffffff, 0x00000100, |
240 | mmCGTT_WD_CLK_CTRL0xf086, 0xffffffff, 0x06000100, |
241 | mmCGTT_PC_CLK_CTRL0xf081, 0xffffffff, 0x00000100, |
242 | mmCGTT_RLC_CLK_CTRL0xf0b8, 0xffffffff, 0x00000100, |
243 | mmCGTT_SC_CLK_CTRL0xf089, 0xffffffff, 0x00000100, |
244 | mmCGTT_SPI_CLK_CTRL0xf080, 0xffffffff, 0x00000100, |
245 | mmCGTT_SQ_CLK_CTRL0xf08c, 0xffffffff, 0x00000100, |
246 | mmCGTT_SQG_CLK_CTRL0xf08d, 0xffffffff, 0x00000100, |
247 | mmCGTT_SX_CLK_CTRL00xf094, 0xffffffff, 0x00000100, |
248 | mmCGTT_SX_CLK_CTRL10xf095, 0xffffffff, 0x00000100, |
249 | mmCGTT_SX_CLK_CTRL20xf096, 0xffffffff, 0x00000100, |
250 | mmCGTT_SX_CLK_CTRL30xf097, 0xffffffff, 0x00000100, |
251 | mmCGTT_SX_CLK_CTRL40xf098, 0xffffffff, 0x00000100, |
252 | mmCGTT_TCI_CLK_CTRL0xf09f, 0xffffffff, 0x00000100, |
253 | mmCGTT_TCP_CLK_CTRL0xf09e, 0xffffffff, 0x00000100, |
254 | mmCGTT_VGT_CLK_CTRL0xf084, 0xffffffff, 0x06000100, |
255 | mmDB_CGTT_CLK_CTRL_00xf0a4, 0xffffffff, 0x00000100, |
256 | mmTA_CGTT_CTRL0xf09d, 0xffffffff, 0x00000100, |
257 | mmTCA_CGTT_SCLK_CTRL0xf0ad, 0xffffffff, 0x00000100, |
258 | mmTCC_CGTT_SCLK_CTRL0xf0ac, 0xffffffff, 0x00000100, |
259 | mmTD_CGTT_CTRL0xf09c, 0xffffffff, 0x00000100, |
260 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
261 | mmCGTS_CU0_SP0_CTRL_REG0xf008, 0xffffffff, 0x00010000, |
262 | mmCGTS_CU0_LDS_SQ_CTRL_REG0xf009, 0xffffffff, 0x00030002, |
263 | mmCGTS_CU0_TA_SQC_CTRL_REG0xf00a, 0xffffffff, 0x00040007, |
264 | mmCGTS_CU0_SP1_CTRL_REG0xf00b, 0xffffffff, 0x00060005, |
265 | mmCGTS_CU0_TD_TCP_CTRL_REG0xf00c, 0xffffffff, 0x00090008, |
266 | mmCGTS_CU1_SP0_CTRL_REG0xf00d, 0xffffffff, 0x00010000, |
267 | mmCGTS_CU1_LDS_SQ_CTRL_REG0xf00e, 0xffffffff, 0x00030002, |
268 | mmCGTS_CU1_TA_CTRL_REG0xf00f, 0xffffffff, 0x00040007, |
269 | mmCGTS_CU1_SP1_CTRL_REG0xf010, 0xffffffff, 0x00060005, |
270 | mmCGTS_CU1_TD_TCP_CTRL_REG0xf011, 0xffffffff, 0x00090008, |
271 | mmCGTS_CU2_SP0_CTRL_REG0xf012, 0xffffffff, 0x00010000, |
272 | mmCGTS_CU2_LDS_SQ_CTRL_REG0xf013, 0xffffffff, 0x00030002, |
273 | mmCGTS_CU2_TA_CTRL_REG0xf014, 0xffffffff, 0x00040007, |
274 | mmCGTS_CU2_SP1_CTRL_REG0xf015, 0xffffffff, 0x00060005, |
275 | mmCGTS_CU2_TD_TCP_CTRL_REG0xf016, 0xffffffff, 0x00090008, |
276 | mmCGTS_CU3_SP0_CTRL_REG0xf017, 0xffffffff, 0x00010000, |
277 | mmCGTS_CU3_LDS_SQ_CTRL_REG0xf018, 0xffffffff, 0x00030002, |
278 | mmCGTS_CU3_TA_CTRL_REG0xf019, 0xffffffff, 0x00040007, |
279 | mmCGTS_CU3_SP1_CTRL_REG0xf01a, 0xffffffff, 0x00060005, |
280 | mmCGTS_CU3_TD_TCP_CTRL_REG0xf01b, 0xffffffff, 0x00090008, |
281 | mmCGTS_CU4_SP0_CTRL_REG0xf01c, 0xffffffff, 0x00010000, |
282 | mmCGTS_CU4_LDS_SQ_CTRL_REG0xf01d, 0xffffffff, 0x00030002, |
283 | mmCGTS_CU4_TA_SQC_CTRL_REG0xf01e, 0xffffffff, 0x00040007, |
284 | mmCGTS_CU4_SP1_CTRL_REG0xf01f, 0xffffffff, 0x00060005, |
285 | mmCGTS_CU4_TD_TCP_CTRL_REG0xf020, 0xffffffff, 0x00090008, |
286 | mmCGTS_CU5_SP0_CTRL_REG0xf021, 0xffffffff, 0x00010000, |
287 | mmCGTS_CU5_LDS_SQ_CTRL_REG0xf022, 0xffffffff, 0x00030002, |
288 | mmCGTS_CU5_TA_CTRL_REG0xf023, 0xffffffff, 0x00040007, |
289 | mmCGTS_CU5_SP1_CTRL_REG0xf024, 0xffffffff, 0x00060005, |
290 | mmCGTS_CU5_TD_TCP_CTRL_REG0xf025, 0xffffffff, 0x00090008, |
291 | mmCGTS_CU6_SP0_CTRL_REG0xf026, 0xffffffff, 0x00010000, |
292 | mmCGTS_CU6_LDS_SQ_CTRL_REG0xf027, 0xffffffff, 0x00030002, |
293 | mmCGTS_CU6_TA_CTRL_REG0xf028, 0xffffffff, 0x00040007, |
294 | mmCGTS_CU6_SP1_CTRL_REG0xf029, 0xffffffff, 0x00060005, |
295 | mmCGTS_CU6_TD_TCP_CTRL_REG0xf02a, 0xffffffff, 0x00090008, |
296 | mmCGTS_CU7_SP0_CTRL_REG0xf02b, 0xffffffff, 0x00010000, |
297 | mmCGTS_CU7_LDS_SQ_CTRL_REG0xf02c, 0xffffffff, 0x00030002, |
298 | mmCGTS_CU7_TA_CTRL_REG0xf02d, 0xffffffff, 0x00040007, |
299 | mmCGTS_CU7_SP1_CTRL_REG0xf02e, 0xffffffff, 0x00060005, |
300 | mmCGTS_CU7_TD_TCP_CTRL_REG0xf02f, 0xffffffff, 0x00090008, |
301 | mmCGTS_SM_CTRL_REG0xf000, 0xffffffff, 0x96e00200, |
302 | mmCP_RB_WPTR_POLL_CNTL0x21c2, 0xffffffff, 0x00900100, |
303 | mmRLC_CGCG_CGLS_CTRL0xec49, 0xffffffff, 0x0020003c, |
304 | mmCP_MEM_SLP_CNTL0x3079, 0x00000001, 0x00000001, |
305 | }; |
306 | |
307 | static const u32 golden_settings_vegam_a11[] = |
308 | { |
309 | mmCB_HW_CONTROL0x2684, 0x0001f3cf, 0x00007208, |
310 | mmCB_HW_CONTROL_20x2686, 0x0f000000, 0x0d000000, |
311 | mmCB_HW_CONTROL_30x2683, 0x000001ff, 0x00000040, |
312 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
313 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
314 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
315 | mmPA_SC_RASTER_CONFIG0xa0d4, 0x3f3fffff, 0x3a00161a, |
316 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0x0000003f, 0x0000002e, |
317 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0001003c, |
318 | mmRLC_CGCG_CGLS_CTRL_3D0xec9d, 0xffffffff, 0x0001003c, |
319 | mmSQ_CONFIG0x2300, 0x07f80000, 0x01180000, |
320 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
321 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
322 | mmTCP_ADDR_CONFIG0x2b05, 0x000003ff, 0x000000f7, |
323 | mmTCP_CHAN_STEER_HI0x2b04, 0xffffffff, 0x00000000, |
324 | mmTCP_CHAN_STEER_LO0x2b03, 0xffffffff, 0x32761054, |
325 | mmVGT_RESET_DEBUG0x2232, 0x00000004, 0x00000004, |
326 | }; |
327 | |
328 | static const u32 vegam_golden_common_all[] = |
329 | { |
330 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
331 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22011003, |
332 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
333 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
334 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
335 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF, |
336 | }; |
337 | |
338 | static const u32 golden_settings_polaris11_a11[] = |
339 | { |
340 | mmCB_HW_CONTROL0x2684, 0x0000f3cf, 0x00007208, |
341 | mmCB_HW_CONTROL_20x2686, 0x0f000000, 0x0f000000, |
342 | mmCB_HW_CONTROL_30x2683, 0x000001ff, 0x00000040, |
343 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
344 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
345 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
346 | mmPA_SC_RASTER_CONFIG0xa0d4, 0x3f3fffff, 0x16000012, |
347 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0x0000003f, 0x00000000, |
348 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0001003c, |
349 | mmRLC_CGCG_CGLS_CTRL_3D0xec9d, 0xffffffff, 0x0001003c, |
350 | mmSQ_CONFIG0x2300, 0x07f80000, 0x01180000, |
351 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
352 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
353 | mmTCP_ADDR_CONFIG0x2b05, 0x000003ff, 0x000000f3, |
354 | mmTCP_CHAN_STEER_HI0x2b04, 0xffffffff, 0x00000000, |
355 | mmTCP_CHAN_STEER_LO0x2b03, 0xffffffff, 0x00003210, |
356 | mmVGT_RESET_DEBUG0x2232, 0x00000004, 0x00000004, |
357 | }; |
358 | |
359 | static const u32 polaris11_golden_common_all[] = |
360 | { |
361 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
362 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22011002, |
363 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
364 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
365 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
366 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF, |
367 | }; |
368 | |
369 | static const u32 golden_settings_polaris10_a11[] = |
370 | { |
371 | mmATC_MISC_CG0xcd4, 0x000c0fc0, 0x000c0200, |
372 | mmCB_HW_CONTROL0x2684, 0x0001f3cf, 0x00007208, |
373 | mmCB_HW_CONTROL_20x2686, 0x0f000000, 0x0f000000, |
374 | mmCB_HW_CONTROL_30x2683, 0x000001ff, 0x00000040, |
375 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
376 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
377 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
378 | mmPA_SC_RASTER_CONFIG0xa0d4, 0x3f3fffff, 0x16000012, |
379 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0x0000003f, 0x0000002a, |
380 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0001003c, |
381 | mmRLC_CGCG_CGLS_CTRL_3D0xec9d, 0xffffffff, 0x0001003c, |
382 | mmSQ_CONFIG0x2300, 0x07f80000, 0x07180000, |
383 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
384 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
385 | mmTCP_ADDR_CONFIG0x2b05, 0x000003ff, 0x000000f7, |
386 | mmTCP_CHAN_STEER_HI0x2b04, 0xffffffff, 0x00000000, |
387 | mmVGT_RESET_DEBUG0x2232, 0x00000004, 0x00000004, |
388 | }; |
389 | |
390 | static const u32 polaris10_golden_common_all[] = |
391 | { |
392 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
393 | mmPA_SC_RASTER_CONFIG0xa0d4, 0xffffffff, 0x16000012, |
394 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0xffffffff, 0x0000002A, |
395 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22011003, |
396 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
397 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
398 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
399 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF, |
400 | }; |
401 | |
402 | static const u32 fiji_golden_common_all[] = |
403 | { |
404 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
405 | mmPA_SC_RASTER_CONFIG0xa0d4, 0xffffffff, 0x3a00161a, |
406 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0xffffffff, 0x0000002e, |
407 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22011003, |
408 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
409 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
410 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
411 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF, |
412 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
413 | mmSPI_CONFIG_CNTL_10x244f, 0x0000000f, 0x00000009, |
414 | }; |
415 | |
416 | static const u32 golden_settings_fiji_a10[] = |
417 | { |
418 | mmCB_HW_CONTROL_30x2683, 0x000001ff, 0x00000040, |
419 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
420 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
421 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
422 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0001003c, |
423 | mmSQ_RANDOM_WAVE_PRI0x2303, 0x001fffff, 0x000006fd, |
424 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
425 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
426 | mmTCC_EXE_DISABLE0x2b84, 0x00000002, 0x00000002, |
427 | mmTCP_ADDR_CONFIG0x2b05, 0x000003ff, 0x000000ff, |
428 | mmVGT_RESET_DEBUG0x2232, 0x00000004, 0x00000004, |
429 | }; |
430 | |
431 | static const u32 fiji_mgcg_cgcg_init[] = |
432 | { |
433 | mmRLC_CGTT_MGCG_OVERRIDE0xec48, 0xffffffff, 0xffffffff, |
434 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
435 | mmCB_CGTT_SCLK_CTRL0xf0a8, 0xffffffff, 0x00000100, |
436 | mmCGTT_BCI_CLK_CTRL0xf082, 0xffffffff, 0x00000100, |
437 | mmCGTT_CP_CLK_CTRL0xf0b0, 0xffffffff, 0x00000100, |
438 | mmCGTT_CPC_CLK_CTRL0xf0b2, 0xffffffff, 0x00000100, |
439 | mmCGTT_CPF_CLK_CTRL0xf0b1, 0xffffffff, 0x40000100, |
440 | mmCGTT_GDS_CLK_CTRL0xf0a0, 0xffffffff, 0x00000100, |
441 | mmCGTT_IA_CLK_CTRL0xf085, 0xffffffff, 0x06000100, |
442 | mmCGTT_PA_CLK_CTRL0xf088, 0xffffffff, 0x00000100, |
443 | mmCGTT_WD_CLK_CTRL0xf086, 0xffffffff, 0x06000100, |
444 | mmCGTT_PC_CLK_CTRL0xf081, 0xffffffff, 0x00000100, |
445 | mmCGTT_RLC_CLK_CTRL0xf0b8, 0xffffffff, 0x00000100, |
446 | mmCGTT_SC_CLK_CTRL0xf089, 0xffffffff, 0x00000100, |
447 | mmCGTT_SPI_CLK_CTRL0xf080, 0xffffffff, 0x00000100, |
448 | mmCGTT_SQ_CLK_CTRL0xf08c, 0xffffffff, 0x00000100, |
449 | mmCGTT_SQG_CLK_CTRL0xf08d, 0xffffffff, 0x00000100, |
450 | mmCGTT_SX_CLK_CTRL00xf094, 0xffffffff, 0x00000100, |
451 | mmCGTT_SX_CLK_CTRL10xf095, 0xffffffff, 0x00000100, |
452 | mmCGTT_SX_CLK_CTRL20xf096, 0xffffffff, 0x00000100, |
453 | mmCGTT_SX_CLK_CTRL30xf097, 0xffffffff, 0x00000100, |
454 | mmCGTT_SX_CLK_CTRL40xf098, 0xffffffff, 0x00000100, |
455 | mmCGTT_TCI_CLK_CTRL0xf09f, 0xffffffff, 0x00000100, |
456 | mmCGTT_TCP_CLK_CTRL0xf09e, 0xffffffff, 0x00000100, |
457 | mmCGTT_VGT_CLK_CTRL0xf084, 0xffffffff, 0x06000100, |
458 | mmDB_CGTT_CLK_CTRL_00xf0a4, 0xffffffff, 0x00000100, |
459 | mmTA_CGTT_CTRL0xf09d, 0xffffffff, 0x00000100, |
460 | mmTCA_CGTT_SCLK_CTRL0xf0ad, 0xffffffff, 0x00000100, |
461 | mmTCC_CGTT_SCLK_CTRL0xf0ac, 0xffffffff, 0x00000100, |
462 | mmTD_CGTT_CTRL0xf09c, 0xffffffff, 0x00000100, |
463 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
464 | mmCGTS_SM_CTRL_REG0xf000, 0xffffffff, 0x96e00200, |
465 | mmCP_RB_WPTR_POLL_CNTL0x21c2, 0xffffffff, 0x00900100, |
466 | mmRLC_CGCG_CGLS_CTRL0xec49, 0xffffffff, 0x0020003c, |
467 | mmCP_MEM_SLP_CNTL0x3079, 0x00000001, 0x00000001, |
468 | }; |
469 | |
470 | static const u32 golden_settings_iceland_a11[] = |
471 | { |
472 | mmCB_HW_CONTROL_30x2683, 0x00000040, 0x00000040, |
473 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
474 | mmDB_DEBUG30x260e, 0xc0000000, 0xc0000000, |
475 | mmGB_GPU_ID0x2640, 0x0000000f, 0x00000000, |
476 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
477 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
478 | mmPA_SC_RASTER_CONFIG0xa0d4, 0x3f3fffff, 0x00000002, |
479 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0x0000003f, 0x00000000, |
480 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0000003c, |
481 | mmSQ_RANDOM_WAVE_PRI0x2303, 0x001fffff, 0x000006fd, |
482 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
483 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
484 | mmTCC_EXE_DISABLE0x2b84, 0x00000002, 0x00000002, |
485 | mmTCP_ADDR_CONFIG0x2b05, 0x000003ff, 0x000000f1, |
486 | mmTCP_CHAN_STEER_HI0x2b04, 0xffffffff, 0x00000000, |
487 | mmTCP_CHAN_STEER_LO0x2b03, 0xffffffff, 0x00000010, |
488 | }; |
489 | |
490 | static const u32 iceland_golden_common_all[] = |
491 | { |
492 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
493 | mmPA_SC_RASTER_CONFIG0xa0d4, 0xffffffff, 0x00000002, |
494 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0xffffffff, 0x00000000, |
495 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22010001, |
496 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
497 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
498 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
499 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF |
500 | }; |
501 | |
502 | static const u32 iceland_mgcg_cgcg_init[] = |
503 | { |
504 | mmRLC_CGTT_MGCG_OVERRIDE0xec48, 0xffffffff, 0xffffffff, |
505 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
506 | mmCB_CGTT_SCLK_CTRL0xf0a8, 0xffffffff, 0x00000100, |
507 | mmCGTT_BCI_CLK_CTRL0xf082, 0xffffffff, 0x00000100, |
508 | mmCGTT_CP_CLK_CTRL0xf0b0, 0xffffffff, 0xc0000100, |
509 | mmCGTT_CPC_CLK_CTRL0xf0b2, 0xffffffff, 0xc0000100, |
510 | mmCGTT_CPF_CLK_CTRL0xf0b1, 0xffffffff, 0xc0000100, |
511 | mmCGTT_GDS_CLK_CTRL0xf0a0, 0xffffffff, 0x00000100, |
512 | mmCGTT_IA_CLK_CTRL0xf085, 0xffffffff, 0x06000100, |
513 | mmCGTT_PA_CLK_CTRL0xf088, 0xffffffff, 0x00000100, |
514 | mmCGTT_WD_CLK_CTRL0xf086, 0xffffffff, 0x06000100, |
515 | mmCGTT_PC_CLK_CTRL0xf081, 0xffffffff, 0x00000100, |
516 | mmCGTT_RLC_CLK_CTRL0xf0b8, 0xffffffff, 0x00000100, |
517 | mmCGTT_SC_CLK_CTRL0xf089, 0xffffffff, 0x00000100, |
518 | mmCGTT_SPI_CLK_CTRL0xf080, 0xffffffff, 0x00000100, |
519 | mmCGTT_SQ_CLK_CTRL0xf08c, 0xffffffff, 0x00000100, |
520 | mmCGTT_SQG_CLK_CTRL0xf08d, 0xffffffff, 0x00000100, |
521 | mmCGTT_SX_CLK_CTRL00xf094, 0xffffffff, 0x00000100, |
522 | mmCGTT_SX_CLK_CTRL10xf095, 0xffffffff, 0x00000100, |
523 | mmCGTT_SX_CLK_CTRL20xf096, 0xffffffff, 0x00000100, |
524 | mmCGTT_SX_CLK_CTRL30xf097, 0xffffffff, 0x00000100, |
525 | mmCGTT_SX_CLK_CTRL40xf098, 0xffffffff, 0x00000100, |
526 | mmCGTT_TCI_CLK_CTRL0xf09f, 0xffffffff, 0xff000100, |
527 | mmCGTT_TCP_CLK_CTRL0xf09e, 0xffffffff, 0x00000100, |
528 | mmCGTT_VGT_CLK_CTRL0xf084, 0xffffffff, 0x06000100, |
529 | mmDB_CGTT_CLK_CTRL_00xf0a4, 0xffffffff, 0x00000100, |
530 | mmTA_CGTT_CTRL0xf09d, 0xffffffff, 0x00000100, |
531 | mmTCA_CGTT_SCLK_CTRL0xf0ad, 0xffffffff, 0x00000100, |
532 | mmTCC_CGTT_SCLK_CTRL0xf0ac, 0xffffffff, 0x00000100, |
533 | mmTD_CGTT_CTRL0xf09c, 0xffffffff, 0x00000100, |
534 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
535 | mmCGTS_CU0_SP0_CTRL_REG0xf008, 0xffffffff, 0x00010000, |
536 | mmCGTS_CU0_LDS_SQ_CTRL_REG0xf009, 0xffffffff, 0x00030002, |
537 | mmCGTS_CU0_TA_SQC_CTRL_REG0xf00a, 0xffffffff, 0x0f840f87, |
538 | mmCGTS_CU0_SP1_CTRL_REG0xf00b, 0xffffffff, 0x00060005, |
539 | mmCGTS_CU0_TD_TCP_CTRL_REG0xf00c, 0xffffffff, 0x00090008, |
540 | mmCGTS_CU1_SP0_CTRL_REG0xf00d, 0xffffffff, 0x00010000, |
541 | mmCGTS_CU1_LDS_SQ_CTRL_REG0xf00e, 0xffffffff, 0x00030002, |
542 | mmCGTS_CU1_TA_CTRL_REG0xf00f, 0xffffffff, 0x00040007, |
543 | mmCGTS_CU1_SP1_CTRL_REG0xf010, 0xffffffff, 0x00060005, |
544 | mmCGTS_CU1_TD_TCP_CTRL_REG0xf011, 0xffffffff, 0x00090008, |
545 | mmCGTS_CU2_SP0_CTRL_REG0xf012, 0xffffffff, 0x00010000, |
546 | mmCGTS_CU2_LDS_SQ_CTRL_REG0xf013, 0xffffffff, 0x00030002, |
547 | mmCGTS_CU2_TA_CTRL_REG0xf014, 0xffffffff, 0x00040007, |
548 | mmCGTS_CU2_SP1_CTRL_REG0xf015, 0xffffffff, 0x00060005, |
549 | mmCGTS_CU2_TD_TCP_CTRL_REG0xf016, 0xffffffff, 0x00090008, |
550 | mmCGTS_CU3_SP0_CTRL_REG0xf017, 0xffffffff, 0x00010000, |
551 | mmCGTS_CU3_LDS_SQ_CTRL_REG0xf018, 0xffffffff, 0x00030002, |
552 | mmCGTS_CU3_TA_CTRL_REG0xf019, 0xffffffff, 0x00040007, |
553 | mmCGTS_CU3_SP1_CTRL_REG0xf01a, 0xffffffff, 0x00060005, |
554 | mmCGTS_CU3_TD_TCP_CTRL_REG0xf01b, 0xffffffff, 0x00090008, |
555 | mmCGTS_CU4_SP0_CTRL_REG0xf01c, 0xffffffff, 0x00010000, |
556 | mmCGTS_CU4_LDS_SQ_CTRL_REG0xf01d, 0xffffffff, 0x00030002, |
557 | mmCGTS_CU4_TA_SQC_CTRL_REG0xf01e, 0xffffffff, 0x0f840f87, |
558 | mmCGTS_CU4_SP1_CTRL_REG0xf01f, 0xffffffff, 0x00060005, |
559 | mmCGTS_CU4_TD_TCP_CTRL_REG0xf020, 0xffffffff, 0x00090008, |
560 | mmCGTS_CU5_SP0_CTRL_REG0xf021, 0xffffffff, 0x00010000, |
561 | mmCGTS_CU5_LDS_SQ_CTRL_REG0xf022, 0xffffffff, 0x00030002, |
562 | mmCGTS_CU5_TA_CTRL_REG0xf023, 0xffffffff, 0x00040007, |
563 | mmCGTS_CU5_SP1_CTRL_REG0xf024, 0xffffffff, 0x00060005, |
564 | mmCGTS_CU5_TD_TCP_CTRL_REG0xf025, 0xffffffff, 0x00090008, |
565 | mmCGTS_SM_CTRL_REG0xf000, 0xffffffff, 0x96e00200, |
566 | mmCP_RB_WPTR_POLL_CNTL0x21c2, 0xffffffff, 0x00900100, |
567 | mmRLC_CGCG_CGLS_CTRL0xec49, 0xffffffff, 0x0020003c, |
568 | }; |
569 | |
570 | static const u32 cz_golden_settings_a11[] = |
571 | { |
572 | mmCB_HW_CONTROL_30x2683, 0x00000040, 0x00000040, |
573 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
574 | mmGB_GPU_ID0x2640, 0x0000000f, 0x00000000, |
575 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x00000001, |
576 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
577 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0000003c, |
578 | mmSQ_RANDOM_WAVE_PRI0x2303, 0x001fffff, 0x000006fd, |
579 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x00010000, |
580 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
581 | mmTCC_EXE_DISABLE0x2b84, 0x00000002, 0x00000002, |
582 | mmTCP_ADDR_CONFIG0x2b05, 0x0000000f, 0x000000f3, |
583 | mmTCP_CHAN_STEER_LO0x2b03, 0xffffffff, 0x00001302 |
584 | }; |
585 | |
586 | static const u32 cz_golden_common_all[] = |
587 | { |
588 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
589 | mmPA_SC_RASTER_CONFIG0xa0d4, 0xffffffff, 0x00000002, |
590 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0xffffffff, 0x00000000, |
591 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x22010001, |
592 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
593 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
594 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
595 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF |
596 | }; |
597 | |
598 | static const u32 cz_mgcg_cgcg_init[] = |
599 | { |
600 | mmRLC_CGTT_MGCG_OVERRIDE0xec48, 0xffffffff, 0xffffffff, |
601 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
602 | mmCB_CGTT_SCLK_CTRL0xf0a8, 0xffffffff, 0x00000100, |
603 | mmCGTT_BCI_CLK_CTRL0xf082, 0xffffffff, 0x00000100, |
604 | mmCGTT_CP_CLK_CTRL0xf0b0, 0xffffffff, 0x00000100, |
605 | mmCGTT_CPC_CLK_CTRL0xf0b2, 0xffffffff, 0x00000100, |
606 | mmCGTT_CPF_CLK_CTRL0xf0b1, 0xffffffff, 0x00000100, |
607 | mmCGTT_GDS_CLK_CTRL0xf0a0, 0xffffffff, 0x00000100, |
608 | mmCGTT_IA_CLK_CTRL0xf085, 0xffffffff, 0x06000100, |
609 | mmCGTT_PA_CLK_CTRL0xf088, 0xffffffff, 0x00000100, |
610 | mmCGTT_WD_CLK_CTRL0xf086, 0xffffffff, 0x06000100, |
611 | mmCGTT_PC_CLK_CTRL0xf081, 0xffffffff, 0x00000100, |
612 | mmCGTT_RLC_CLK_CTRL0xf0b8, 0xffffffff, 0x00000100, |
613 | mmCGTT_SC_CLK_CTRL0xf089, 0xffffffff, 0x00000100, |
614 | mmCGTT_SPI_CLK_CTRL0xf080, 0xffffffff, 0x00000100, |
615 | mmCGTT_SQ_CLK_CTRL0xf08c, 0xffffffff, 0x00000100, |
616 | mmCGTT_SQG_CLK_CTRL0xf08d, 0xffffffff, 0x00000100, |
617 | mmCGTT_SX_CLK_CTRL00xf094, 0xffffffff, 0x00000100, |
618 | mmCGTT_SX_CLK_CTRL10xf095, 0xffffffff, 0x00000100, |
619 | mmCGTT_SX_CLK_CTRL20xf096, 0xffffffff, 0x00000100, |
620 | mmCGTT_SX_CLK_CTRL30xf097, 0xffffffff, 0x00000100, |
621 | mmCGTT_SX_CLK_CTRL40xf098, 0xffffffff, 0x00000100, |
622 | mmCGTT_TCI_CLK_CTRL0xf09f, 0xffffffff, 0x00000100, |
623 | mmCGTT_TCP_CLK_CTRL0xf09e, 0xffffffff, 0x00000100, |
624 | mmCGTT_VGT_CLK_CTRL0xf084, 0xffffffff, 0x06000100, |
625 | mmDB_CGTT_CLK_CTRL_00xf0a4, 0xffffffff, 0x00000100, |
626 | mmTA_CGTT_CTRL0xf09d, 0xffffffff, 0x00000100, |
627 | mmTCA_CGTT_SCLK_CTRL0xf0ad, 0xffffffff, 0x00000100, |
628 | mmTCC_CGTT_SCLK_CTRL0xf0ac, 0xffffffff, 0x00000100, |
629 | mmTD_CGTT_CTRL0xf09c, 0xffffffff, 0x00000100, |
630 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
631 | mmCGTS_CU0_SP0_CTRL_REG0xf008, 0xffffffff, 0x00010000, |
632 | mmCGTS_CU0_LDS_SQ_CTRL_REG0xf009, 0xffffffff, 0x00030002, |
633 | mmCGTS_CU0_TA_SQC_CTRL_REG0xf00a, 0xffffffff, 0x00040007, |
634 | mmCGTS_CU0_SP1_CTRL_REG0xf00b, 0xffffffff, 0x00060005, |
635 | mmCGTS_CU0_TD_TCP_CTRL_REG0xf00c, 0xffffffff, 0x00090008, |
636 | mmCGTS_CU1_SP0_CTRL_REG0xf00d, 0xffffffff, 0x00010000, |
637 | mmCGTS_CU1_LDS_SQ_CTRL_REG0xf00e, 0xffffffff, 0x00030002, |
638 | mmCGTS_CU1_TA_CTRL_REG0xf00f, 0xffffffff, 0x00040007, |
639 | mmCGTS_CU1_SP1_CTRL_REG0xf010, 0xffffffff, 0x00060005, |
640 | mmCGTS_CU1_TD_TCP_CTRL_REG0xf011, 0xffffffff, 0x00090008, |
641 | mmCGTS_CU2_SP0_CTRL_REG0xf012, 0xffffffff, 0x00010000, |
642 | mmCGTS_CU2_LDS_SQ_CTRL_REG0xf013, 0xffffffff, 0x00030002, |
643 | mmCGTS_CU2_TA_CTRL_REG0xf014, 0xffffffff, 0x00040007, |
644 | mmCGTS_CU2_SP1_CTRL_REG0xf015, 0xffffffff, 0x00060005, |
645 | mmCGTS_CU2_TD_TCP_CTRL_REG0xf016, 0xffffffff, 0x00090008, |
646 | mmCGTS_CU3_SP0_CTRL_REG0xf017, 0xffffffff, 0x00010000, |
647 | mmCGTS_CU3_LDS_SQ_CTRL_REG0xf018, 0xffffffff, 0x00030002, |
648 | mmCGTS_CU3_TA_CTRL_REG0xf019, 0xffffffff, 0x00040007, |
649 | mmCGTS_CU3_SP1_CTRL_REG0xf01a, 0xffffffff, 0x00060005, |
650 | mmCGTS_CU3_TD_TCP_CTRL_REG0xf01b, 0xffffffff, 0x00090008, |
651 | mmCGTS_CU4_SP0_CTRL_REG0xf01c, 0xffffffff, 0x00010000, |
652 | mmCGTS_CU4_LDS_SQ_CTRL_REG0xf01d, 0xffffffff, 0x00030002, |
653 | mmCGTS_CU4_TA_SQC_CTRL_REG0xf01e, 0xffffffff, 0x00040007, |
654 | mmCGTS_CU4_SP1_CTRL_REG0xf01f, 0xffffffff, 0x00060005, |
655 | mmCGTS_CU4_TD_TCP_CTRL_REG0xf020, 0xffffffff, 0x00090008, |
656 | mmCGTS_CU5_SP0_CTRL_REG0xf021, 0xffffffff, 0x00010000, |
657 | mmCGTS_CU5_LDS_SQ_CTRL_REG0xf022, 0xffffffff, 0x00030002, |
658 | mmCGTS_CU5_TA_CTRL_REG0xf023, 0xffffffff, 0x00040007, |
659 | mmCGTS_CU5_SP1_CTRL_REG0xf024, 0xffffffff, 0x00060005, |
660 | mmCGTS_CU5_TD_TCP_CTRL_REG0xf025, 0xffffffff, 0x00090008, |
661 | mmCGTS_CU6_SP0_CTRL_REG0xf026, 0xffffffff, 0x00010000, |
662 | mmCGTS_CU6_LDS_SQ_CTRL_REG0xf027, 0xffffffff, 0x00030002, |
663 | mmCGTS_CU6_TA_CTRL_REG0xf028, 0xffffffff, 0x00040007, |
664 | mmCGTS_CU6_SP1_CTRL_REG0xf029, 0xffffffff, 0x00060005, |
665 | mmCGTS_CU6_TD_TCP_CTRL_REG0xf02a, 0xffffffff, 0x00090008, |
666 | mmCGTS_CU7_SP0_CTRL_REG0xf02b, 0xffffffff, 0x00010000, |
667 | mmCGTS_CU7_LDS_SQ_CTRL_REG0xf02c, 0xffffffff, 0x00030002, |
668 | mmCGTS_CU7_TA_CTRL_REG0xf02d, 0xffffffff, 0x00040007, |
669 | mmCGTS_CU7_SP1_CTRL_REG0xf02e, 0xffffffff, 0x00060005, |
670 | mmCGTS_CU7_TD_TCP_CTRL_REG0xf02f, 0xffffffff, 0x00090008, |
671 | mmCGTS_SM_CTRL_REG0xf000, 0xffffffff, 0x96e00200, |
672 | mmCP_RB_WPTR_POLL_CNTL0x21c2, 0xffffffff, 0x00900100, |
673 | mmRLC_CGCG_CGLS_CTRL0xec49, 0xffffffff, 0x0020003f, |
674 | mmCP_MEM_SLP_CNTL0x3079, 0x00000001, 0x00000001, |
675 | }; |
676 | |
677 | static const u32 stoney_golden_settings_a11[] = |
678 | { |
679 | mmDB_DEBUG20x260d, 0xf00fffff, 0x00000400, |
680 | mmGB_GPU_ID0x2640, 0x0000000f, 0x00000000, |
681 | mmPA_SC_ENHANCE0x22fc, 0xffffffff, 0x20000001, |
682 | mmPA_SC_LINE_STIPPLE_STATE0xc281, 0x0000ff0f, 0x00000000, |
683 | mmRLC_CGCG_CGLS_CTRL0xec49, 0x00000003, 0x0001003c, |
684 | mmTA_CNTL_AUX0x2542, 0x000f000f, 0x000b0000, |
685 | mmTCC_CTRL0x2b80, 0x00100000, 0xf31fff7f, |
686 | mmTCC_EXE_DISABLE0x2b84, 0x00000002, 0x00000002, |
687 | mmTCP_ADDR_CONFIG0x2b05, 0x0000000f, 0x000000f1, |
688 | mmTCP_CHAN_STEER_LO0x2b03, 0xffffffff, 0x10101010, |
689 | }; |
690 | |
691 | static const u32 stoney_golden_common_all[] = |
692 | { |
693 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
694 | mmPA_SC_RASTER_CONFIG0xa0d4, 0xffffffff, 0x00000000, |
695 | mmPA_SC_RASTER_CONFIG_10xa0d5, 0xffffffff, 0x00000000, |
696 | mmGB_ADDR_CONFIG0x263e, 0xffffffff, 0x12010001, |
697 | mmSPI_RESOURCE_RESERVE_CU_00x31dc, 0xffffffff, 0x00000800, |
698 | mmSPI_RESOURCE_RESERVE_CU_10x31dd, 0xffffffff, 0x00000800, |
699 | mmSPI_RESOURCE_RESERVE_EN_CU_00x31e6, 0xffffffff, 0x00FF7FBF, |
700 | mmSPI_RESOURCE_RESERVE_EN_CU_10x31e7, 0xffffffff, 0x00FF7FAF, |
701 | }; |
702 | |
703 | static const u32 stoney_mgcg_cgcg_init[] = |
704 | { |
705 | mmGRBM_GFX_INDEX0xc200, 0xffffffff, 0xe0000000, |
706 | mmRLC_CGCG_CGLS_CTRL0xec49, 0xffffffff, 0x0020003f, |
707 | mmCP_MEM_SLP_CNTL0x3079, 0xffffffff, 0x00020201, |
708 | mmRLC_MEM_SLP_CNTL0xec06, 0xffffffff, 0x00020201, |
709 | mmCGTS_SM_CTRL_REG0xf000, 0xffffffff, 0x96940200, |
710 | }; |
711 | |
712 | |
713 | static const char * const sq_edc_source_names[] = { |
714 | "SQ_EDC_INFO_SOURCE_INVALID: No EDC error has occurred", |
715 | "SQ_EDC_INFO_SOURCE_INST: EDC source is Instruction Fetch", |
716 | "SQ_EDC_INFO_SOURCE_SGPR: EDC source is SGPR or SQC data return", |
717 | "SQ_EDC_INFO_SOURCE_VGPR: EDC source is VGPR", |
718 | "SQ_EDC_INFO_SOURCE_LDS: EDC source is LDS", |
719 | "SQ_EDC_INFO_SOURCE_GDS: EDC source is GDS", |
720 | "SQ_EDC_INFO_SOURCE_TA: EDC source is TA", |
721 | }; |
722 | |
723 | static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); |
724 | static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); |
725 | static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); |
726 | static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev); |
727 | static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev); |
728 | static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev); |
729 | static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring); |
730 | static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring); |
731 | |
732 | static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) |
733 | { |
734 | switch (adev->asic_type) { |
735 | case CHIP_TOPAZ: |
736 | amdgpu_device_program_register_sequence(adev, |
737 | iceland_mgcg_cgcg_init, |
738 | ARRAY_SIZE(iceland_mgcg_cgcg_init)(sizeof((iceland_mgcg_cgcg_init)) / sizeof((iceland_mgcg_cgcg_init )[0]))); |
739 | amdgpu_device_program_register_sequence(adev, |
740 | golden_settings_iceland_a11, |
741 | ARRAY_SIZE(golden_settings_iceland_a11)(sizeof((golden_settings_iceland_a11)) / sizeof((golden_settings_iceland_a11 )[0]))); |
742 | amdgpu_device_program_register_sequence(adev, |
743 | iceland_golden_common_all, |
744 | ARRAY_SIZE(iceland_golden_common_all)(sizeof((iceland_golden_common_all)) / sizeof((iceland_golden_common_all )[0]))); |
745 | break; |
746 | case CHIP_FIJI: |
747 | amdgpu_device_program_register_sequence(adev, |
748 | fiji_mgcg_cgcg_init, |
749 | ARRAY_SIZE(fiji_mgcg_cgcg_init)(sizeof((fiji_mgcg_cgcg_init)) / sizeof((fiji_mgcg_cgcg_init) [0]))); |
750 | amdgpu_device_program_register_sequence(adev, |
751 | golden_settings_fiji_a10, |
752 | ARRAY_SIZE(golden_settings_fiji_a10)(sizeof((golden_settings_fiji_a10)) / sizeof((golden_settings_fiji_a10 )[0]))); |
753 | amdgpu_device_program_register_sequence(adev, |
754 | fiji_golden_common_all, |
755 | ARRAY_SIZE(fiji_golden_common_all)(sizeof((fiji_golden_common_all)) / sizeof((fiji_golden_common_all )[0]))); |
756 | break; |
757 | |
758 | case CHIP_TONGA: |
759 | amdgpu_device_program_register_sequence(adev, |
760 | tonga_mgcg_cgcg_init, |
761 | ARRAY_SIZE(tonga_mgcg_cgcg_init)(sizeof((tonga_mgcg_cgcg_init)) / sizeof((tonga_mgcg_cgcg_init )[0]))); |
762 | amdgpu_device_program_register_sequence(adev, |
763 | golden_settings_tonga_a11, |
764 | ARRAY_SIZE(golden_settings_tonga_a11)(sizeof((golden_settings_tonga_a11)) / sizeof((golden_settings_tonga_a11 )[0]))); |
765 | amdgpu_device_program_register_sequence(adev, |
766 | tonga_golden_common_all, |
767 | ARRAY_SIZE(tonga_golden_common_all)(sizeof((tonga_golden_common_all)) / sizeof((tonga_golden_common_all )[0]))); |
768 | break; |
769 | case CHIP_VEGAM: |
770 | amdgpu_device_program_register_sequence(adev, |
771 | golden_settings_vegam_a11, |
772 | ARRAY_SIZE(golden_settings_vegam_a11)(sizeof((golden_settings_vegam_a11)) / sizeof((golden_settings_vegam_a11 )[0]))); |
773 | amdgpu_device_program_register_sequence(adev, |
774 | vegam_golden_common_all, |
775 | ARRAY_SIZE(vegam_golden_common_all)(sizeof((vegam_golden_common_all)) / sizeof((vegam_golden_common_all )[0]))); |
776 | break; |
777 | case CHIP_POLARIS11: |
778 | case CHIP_POLARIS12: |
779 | amdgpu_device_program_register_sequence(adev, |
780 | golden_settings_polaris11_a11, |
781 | ARRAY_SIZE(golden_settings_polaris11_a11)(sizeof((golden_settings_polaris11_a11)) / sizeof((golden_settings_polaris11_a11 )[0]))); |
782 | amdgpu_device_program_register_sequence(adev, |
783 | polaris11_golden_common_all, |
784 | ARRAY_SIZE(polaris11_golden_common_all)(sizeof((polaris11_golden_common_all)) / sizeof((polaris11_golden_common_all )[0]))); |
785 | break; |
786 | case CHIP_POLARIS10: |
787 | amdgpu_device_program_register_sequence(adev, |
788 | golden_settings_polaris10_a11, |
789 | ARRAY_SIZE(golden_settings_polaris10_a11)(sizeof((golden_settings_polaris10_a11)) / sizeof((golden_settings_polaris10_a11 )[0]))); |
790 | amdgpu_device_program_register_sequence(adev, |
791 | polaris10_golden_common_all, |
792 | ARRAY_SIZE(polaris10_golden_common_all)(sizeof((polaris10_golden_common_all)) / sizeof((polaris10_golden_common_all )[0]))); |
793 | WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C)adev->smc_wreg(adev, (0xc05000dc), (0x0000001C)); |
794 | if (adev->pdev->revision == 0xc7 && |
795 | ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || |
796 | (adev->pdev->subsystem_device == 0x4a8 && adev->pdev->subsystem_vendor == 0x1043) || |
797 | (adev->pdev->subsystem_device == 0x9480 && adev->pdev->subsystem_vendor == 0x1682))) { |
798 | amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1E, 0xDD); |
799 | amdgpu_atombios_i2c_channel_trans(adev, 0x10, 0x96, 0x1F, 0xD0); |
800 | } |
801 | break; |
802 | case CHIP_CARRIZO: |
803 | amdgpu_device_program_register_sequence(adev, |
804 | cz_mgcg_cgcg_init, |
805 | ARRAY_SIZE(cz_mgcg_cgcg_init)(sizeof((cz_mgcg_cgcg_init)) / sizeof((cz_mgcg_cgcg_init)[0]) )); |
806 | amdgpu_device_program_register_sequence(adev, |
807 | cz_golden_settings_a11, |
808 | ARRAY_SIZE(cz_golden_settings_a11)(sizeof((cz_golden_settings_a11)) / sizeof((cz_golden_settings_a11 )[0]))); |
809 | amdgpu_device_program_register_sequence(adev, |
810 | cz_golden_common_all, |
811 | ARRAY_SIZE(cz_golden_common_all)(sizeof((cz_golden_common_all)) / sizeof((cz_golden_common_all )[0]))); |
812 | break; |
813 | case CHIP_STONEY: |
814 | amdgpu_device_program_register_sequence(adev, |
815 | stoney_mgcg_cgcg_init, |
816 | ARRAY_SIZE(stoney_mgcg_cgcg_init)(sizeof((stoney_mgcg_cgcg_init)) / sizeof((stoney_mgcg_cgcg_init )[0]))); |
817 | amdgpu_device_program_register_sequence(adev, |
818 | stoney_golden_settings_a11, |
819 | ARRAY_SIZE(stoney_golden_settings_a11)(sizeof((stoney_golden_settings_a11)) / sizeof((stoney_golden_settings_a11 )[0]))); |
820 | amdgpu_device_program_register_sequence(adev, |
821 | stoney_golden_common_all, |
822 | ARRAY_SIZE(stoney_golden_common_all)(sizeof((stoney_golden_common_all)) / sizeof((stoney_golden_common_all )[0]))); |
823 | break; |
824 | default: |
825 | break; |
826 | } |
827 | } |
828 | |
829 | static void gfx_v8_0_scratch_init(struct amdgpu_device *adev) |
830 | { |
831 | adev->gfx.scratch.num_reg = 8; |
832 | adev->gfx.scratch.reg_base = mmSCRATCH_REG00xc040; |
833 | adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; |
834 | } |
835 | |
836 | static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring) |
837 | { |
838 | struct amdgpu_device *adev = ring->adev; |
839 | uint32_t scratch; |
840 | uint32_t tmp = 0; |
841 | unsigned i; |
842 | int r; |
843 | |
844 | r = amdgpu_gfx_scratch_get(adev, &scratch); |
845 | if (r) |
846 | return r; |
847 | |
848 | WREG32(scratch, 0xCAFEDEAD)amdgpu_device_wreg(adev, (scratch), (0xCAFEDEAD), 0); |
849 | r = amdgpu_ring_alloc(ring, 3); |
850 | if (r) |
851 | goto error_free_scratch; |
852 | |
853 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) & 0x3FFF) << 16)); |
854 | amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START0x0000c000)); |
855 | amdgpu_ring_write(ring, 0xDEADBEEF); |
856 | amdgpu_ring_commit(ring); |
857 | |
858 | for (i = 0; i < adev->usec_timeout; i++) { |
859 | tmp = RREG32(scratch)amdgpu_device_rreg(adev, (scratch), 0); |
860 | if (tmp == 0xDEADBEEF) |
861 | break; |
862 | udelay(1); |
863 | } |
864 | |
865 | if (i >= adev->usec_timeout) |
866 | r = -ETIMEDOUT60; |
867 | |
868 | error_free_scratch: |
869 | amdgpu_gfx_scratch_free(adev, scratch); |
870 | return r; |
871 | } |
872 | |
873 | static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) |
874 | { |
875 | struct amdgpu_device *adev = ring->adev; |
876 | struct amdgpu_ib ib; |
877 | struct dma_fence *f = NULL((void *)0); |
878 | |
879 | unsigned int index; |
880 | uint64_t gpu_addr; |
881 | uint32_t tmp; |
882 | long r; |
883 | |
884 | r = amdgpu_device_wb_get(adev, &index); |
885 | if (r) |
886 | return r; |
887 | |
888 | gpu_addr = adev->wb.gpu_addr + (index * 4); |
889 | adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD)((__uint32_t)(0xCAFEDEAD)); |
890 | memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib))); |
891 | r = amdgpu_ib_get(adev, NULL((void *)0), 16, |
892 | AMDGPU_IB_POOL_DIRECT, &ib); |
893 | if (r) |
894 | goto err1; |
895 | |
896 | ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
897 | ib.ptr[1] = WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20); |
898 | ib.ptr[2] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
899 | ib.ptr[3] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
900 | ib.ptr[4] = 0xDEADBEEF; |
901 | ib.length_dw = 5; |
902 | |
903 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f); |
904 | if (r) |
905 | goto err2; |
906 | |
907 | r = dma_fence_wait_timeout(f, false0, timeout); |
908 | if (r == 0) { |
909 | r = -ETIMEDOUT60; |
910 | goto err2; |
911 | } else if (r < 0) { |
912 | goto err2; |
913 | } |
914 | |
915 | tmp = adev->wb.wb[index]; |
916 | if (tmp == 0xDEADBEEF) |
917 | r = 0; |
918 | else |
919 | r = -EINVAL22; |
920 | |
921 | err2: |
922 | amdgpu_ib_free(adev, &ib, NULL((void *)0)); |
923 | dma_fence_put(f); |
924 | err1: |
925 | amdgpu_device_wb_free(adev, index); |
926 | return r; |
927 | } |
928 | |
929 | |
930 | static void gfx_v8_0_free_microcode(struct amdgpu_device *adev) |
931 | { |
932 | release_firmware(adev->gfx.pfp_fw); |
933 | adev->gfx.pfp_fw = NULL((void *)0); |
934 | release_firmware(adev->gfx.me_fw); |
935 | adev->gfx.me_fw = NULL((void *)0); |
936 | release_firmware(adev->gfx.ce_fw); |
937 | adev->gfx.ce_fw = NULL((void *)0); |
938 | release_firmware(adev->gfx.rlc_fw); |
939 | adev->gfx.rlc_fw = NULL((void *)0); |
940 | release_firmware(adev->gfx.mec_fw); |
941 | adev->gfx.mec_fw = NULL((void *)0); |
942 | if ((adev->asic_type != CHIP_STONEY) && |
943 | (adev->asic_type != CHIP_TOPAZ)) |
944 | release_firmware(adev->gfx.mec2_fw); |
945 | adev->gfx.mec2_fw = NULL((void *)0); |
946 | |
947 | kfree(adev->gfx.rlc.register_list_format); |
948 | } |
949 | |
950 | static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) |
951 | { |
952 | const char *chip_name; |
953 | char fw_name[30]; |
954 | int err; |
955 | struct amdgpu_firmware_info *info = NULL((void *)0); |
956 | const struct common_firmware_header *header = NULL((void *)0); |
957 | const struct gfx_firmware_header_v1_0 *cp_hdr; |
958 | const struct rlc_firmware_header_v2_0 *rlc_hdr; |
959 | unsigned int *tmp = NULL((void *)0), i; |
960 | |
961 | DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n"); |
962 | |
963 | switch (adev->asic_type) { |
964 | case CHIP_TOPAZ: |
965 | chip_name = "topaz"; |
966 | break; |
967 | case CHIP_TONGA: |
968 | chip_name = "tonga"; |
969 | break; |
970 | case CHIP_CARRIZO: |
971 | chip_name = "carrizo"; |
972 | break; |
973 | case CHIP_FIJI: |
974 | chip_name = "fiji"; |
975 | break; |
976 | case CHIP_STONEY: |
977 | chip_name = "stoney"; |
978 | break; |
979 | case CHIP_POLARIS10: |
980 | chip_name = "polaris10"; |
981 | break; |
982 | case CHIP_POLARIS11: |
983 | chip_name = "polaris11"; |
984 | break; |
985 | case CHIP_POLARIS12: |
986 | chip_name = "polaris12"; |
987 | break; |
988 | case CHIP_VEGAM: |
989 | chip_name = "vegam"; |
990 | break; |
991 | default: |
992 | BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c" , 992); } while (0); |
993 | } |
994 | |
995 | if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { |
996 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp_2.bin", chip_name); |
997 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
998 | if (err == -ENOENT2) { |
999 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); |
1000 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
1001 | } |
1002 | } else { |
1003 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); |
1004 | err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); |
1005 | } |
1006 | if (err) |
1007 | goto out; |
1008 | err = amdgpu_ucode_validate(adev->gfx.pfp_fw); |
1009 | if (err) |
1010 | goto out; |
1011 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; |
1012 | adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version)); |
1013 | adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version)); |
1014 | |
1015 | if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { |
1016 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me_2.bin", chip_name); |
1017 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
1018 | if (err == -ENOENT2) { |
1019 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); |
1020 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
1021 | } |
1022 | } else { |
1023 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); |
1024 | err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); |
1025 | } |
1026 | if (err) |
1027 | goto out; |
1028 | err = amdgpu_ucode_validate(adev->gfx.me_fw); |
1029 | if (err) |
1030 | goto out; |
1031 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; |
1032 | adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version)); |
1033 | |
1034 | adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version)); |
1035 | |
1036 | if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { |
1037 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce_2.bin", chip_name); |
1038 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
1039 | if (err == -ENOENT2) { |
1040 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); |
1041 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
1042 | } |
1043 | } else { |
1044 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); |
1045 | err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); |
1046 | } |
1047 | if (err) |
1048 | goto out; |
1049 | err = amdgpu_ucode_validate(adev->gfx.ce_fw); |
1050 | if (err) |
1051 | goto out; |
1052 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; |
1053 | adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version)); |
1054 | adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version)); |
1055 | |
1056 | /* |
1057 | * Support for MCBP/Virtualization in combination with chained IBs is |
1058 | * formal released on feature version #46 |
1059 | */ |
1060 | if (adev->gfx.ce_feature_version >= 46 && |
1061 | adev->gfx.pfp_feature_version >= 46) { |
1062 | adev->virt.chained_ib_support = true1; |
1063 | DRM_INFO("Chained IB support enabled!\n")printk("\0016" "[" "drm" "] " "Chained IB support enabled!\n" ); |
1064 | } else |
1065 | adev->virt.chained_ib_support = false0; |
1066 | |
1067 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); |
1068 | err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); |
1069 | if (err) |
1070 | goto out; |
1071 | err = amdgpu_ucode_validate(adev->gfx.rlc_fw); |
Value stored to 'err' is never read | |
1072 | rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; |
1073 | adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version)((__uint32_t)(rlc_hdr->header.ucode_version)); |
1074 | adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version)((__uint32_t)(rlc_hdr->ucode_feature_version)); |
1075 | |
1076 | adev->gfx.rlc.save_and_restore_offset = |
1077 | le32_to_cpu(rlc_hdr->save_and_restore_offset)((__uint32_t)(rlc_hdr->save_and_restore_offset)); |
1078 | adev->gfx.rlc.clear_state_descriptor_offset = |
1079 | le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)((__uint32_t)(rlc_hdr->clear_state_descriptor_offset)); |
1080 | adev->gfx.rlc.avail_scratch_ram_locations = |
1081 | le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)((__uint32_t)(rlc_hdr->avail_scratch_ram_locations)); |
1082 | adev->gfx.rlc.reg_restore_list_size = |
1083 | le32_to_cpu(rlc_hdr->reg_restore_list_size)((__uint32_t)(rlc_hdr->reg_restore_list_size)); |
1084 | adev->gfx.rlc.reg_list_format_start = |
1085 | le32_to_cpu(rlc_hdr->reg_list_format_start)((__uint32_t)(rlc_hdr->reg_list_format_start)); |
1086 | adev->gfx.rlc.reg_list_format_separate_start = |
1087 | le32_to_cpu(rlc_hdr->reg_list_format_separate_start)((__uint32_t)(rlc_hdr->reg_list_format_separate_start)); |
1088 | adev->gfx.rlc.starting_offsets_start = |
1089 | le32_to_cpu(rlc_hdr->starting_offsets_start)((__uint32_t)(rlc_hdr->starting_offsets_start)); |
1090 | adev->gfx.rlc.reg_list_format_size_bytes = |
1091 | le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)((__uint32_t)(rlc_hdr->reg_list_format_size_bytes)); |
1092 | adev->gfx.rlc.reg_list_size_bytes = |
1093 | le32_to_cpu(rlc_hdr->reg_list_size_bytes)((__uint32_t)(rlc_hdr->reg_list_size_bytes)); |
1094 | |
1095 | adev->gfx.rlc.register_list_format = |
1096 | kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + |
1097 | adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL(0x0001 | 0x0004)); |
1098 | |
1099 | if (!adev->gfx.rlc.register_list_format) { |
1100 | err = -ENOMEM12; |
1101 | goto out; |
1102 | } |
1103 | |
1104 | tmp = (unsigned int *)((uintptr_t)rlc_hdr + |
1105 | le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)((__uint32_t)(rlc_hdr->reg_list_format_array_offset_bytes) )); |
1106 | for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++) |
1107 | adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i])((__uint32_t)(tmp[i])); |
1108 | |
1109 | adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; |
1110 | |
1111 | tmp = (unsigned int *)((uintptr_t)rlc_hdr + |
1112 | le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)((__uint32_t)(rlc_hdr->reg_list_array_offset_bytes))); |
1113 | for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++) |
1114 | adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i])((__uint32_t)(tmp[i])); |
1115 | |
1116 | if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { |
1117 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec_2.bin", chip_name); |
1118 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
1119 | if (err == -ENOENT2) { |
1120 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); |
1121 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
1122 | } |
1123 | } else { |
1124 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); |
1125 | err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); |
1126 | } |
1127 | if (err) |
1128 | goto out; |
1129 | err = amdgpu_ucode_validate(adev->gfx.mec_fw); |
1130 | if (err) |
1131 | goto out; |
1132 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
1133 | adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version)); |
1134 | adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version)); |
1135 | |
1136 | if ((adev->asic_type != CHIP_STONEY) && |
1137 | (adev->asic_type != CHIP_TOPAZ)) { |
1138 | if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { |
1139 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2_2.bin", chip_name); |
1140 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
1141 | if (err == -ENOENT2) { |
1142 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); |
1143 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
1144 | } |
1145 | } else { |
1146 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); |
1147 | err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); |
1148 | } |
1149 | if (!err) { |
1150 | err = amdgpu_ucode_validate(adev->gfx.mec2_fw); |
1151 | if (err) |
1152 | goto out; |
1153 | cp_hdr = (const struct gfx_firmware_header_v1_0 *) |
1154 | adev->gfx.mec2_fw->data; |
1155 | adev->gfx.mec2_fw_version = |
1156 | le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version)); |
1157 | adev->gfx.mec2_feature_version = |
1158 | le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version)); |
1159 | } else { |
1160 | err = 0; |
1161 | adev->gfx.mec2_fw = NULL((void *)0); |
1162 | } |
1163 | } |
1164 | |
1165 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; |
1166 | info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; |
1167 | info->fw = adev->gfx.pfp_fw; |
1168 | header = (const struct common_firmware_header *)info->fw->data; |
1169 | adev->firmware.fw_size += |
1170 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
1171 | |
1172 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; |
1173 | info->ucode_id = AMDGPU_UCODE_ID_CP_ME; |
1174 | info->fw = adev->gfx.me_fw; |
1175 | header = (const struct common_firmware_header *)info->fw->data; |
1176 | adev->firmware.fw_size += |
1177 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
1178 | |
1179 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; |
1180 | info->ucode_id = AMDGPU_UCODE_ID_CP_CE; |
1181 | info->fw = adev->gfx.ce_fw; |
1182 | header = (const struct common_firmware_header *)info->fw->data; |
1183 | adev->firmware.fw_size += |
1184 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
1185 | |
1186 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; |
1187 | info->ucode_id = AMDGPU_UCODE_ID_RLC_G; |
1188 | info->fw = adev->gfx.rlc_fw; |
1189 | header = (const struct common_firmware_header *)info->fw->data; |
1190 | adev->firmware.fw_size += |
1191 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
1192 | |
1193 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; |
1194 | info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; |
1195 | info->fw = adev->gfx.mec_fw; |
1196 | header = (const struct common_firmware_header *)info->fw->data; |
1197 | adev->firmware.fw_size += |
1198 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
1199 | |
1200 | /* we need account JT in */ |
1201 | cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; |
1202 | adev->firmware.fw_size += |
1203 | roundup2(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE)(((((__uint32_t)(cp_hdr->jt_size)) << 2) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size )) << 2))((1 << 12)) - 1))); |
1204 | |
1205 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
1206 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_STORAGE]; |
1207 | info->ucode_id = AMDGPU_UCODE_ID_STORAGE; |
1208 | info->fw = adev->gfx.mec_fw; |
1209 | adev->firmware.fw_size += |
1210 | roundup2(le32_to_cpu(64 * PAGE_SIZE), PAGE_SIZE)(((((__uint32_t)(64 * (1 << 12)))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(64 * (1 << 12)) )))((1 << 12)) - 1))); |
1211 | } |
1212 | |
1213 | if (adev->gfx.mec2_fw) { |
1214 | info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; |
1215 | info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; |
1216 | info->fw = adev->gfx.mec2_fw; |
1217 | header = (const struct common_firmware_header *)info->fw->data; |
1218 | adev->firmware.fw_size += |
1219 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
1220 | } |
1221 | |
1222 | out: |
1223 | if (err) { |
1224 | dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx8: Failed to load firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1225 | "gfx8: Failed to load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx8: Failed to load firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ) |
1226 | fw_name)printf("drm:pid%d:%s *ERROR* " "gfx8: Failed to load firmware \"%s\"\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name ); |
1227 | release_firmware(adev->gfx.pfp_fw); |
1228 | adev->gfx.pfp_fw = NULL((void *)0); |
1229 | release_firmware(adev->gfx.me_fw); |
1230 | adev->gfx.me_fw = NULL((void *)0); |
1231 | release_firmware(adev->gfx.ce_fw); |
1232 | adev->gfx.ce_fw = NULL((void *)0); |
1233 | release_firmware(adev->gfx.rlc_fw); |
1234 | adev->gfx.rlc_fw = NULL((void *)0); |
1235 | release_firmware(adev->gfx.mec_fw); |
1236 | adev->gfx.mec_fw = NULL((void *)0); |
1237 | release_firmware(adev->gfx.mec2_fw); |
1238 | adev->gfx.mec2_fw = NULL((void *)0); |
1239 | } |
1240 | return err; |
1241 | } |
1242 | |
1243 | static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, |
1244 | volatile u32 *buffer) |
1245 | { |
1246 | u32 count = 0, i; |
1247 | const struct cs_section_def *sect = NULL((void *)0); |
1248 | const struct cs_extent_def *ext = NULL((void *)0); |
1249 | |
1250 | if (adev->gfx.rlc.cs_data == NULL((void *)0)) |
1251 | return; |
1252 | if (buffer == NULL((void *)0)) |
1253 | return; |
1254 | |
1255 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16))); |
1256 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE)((__uint32_t)((2 << 28))); |
1257 | |
1258 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1))((__uint32_t)(((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) & 0x3FFF) << 16))); |
1259 | buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000)); |
1260 | buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000)); |
1261 | |
1262 | for (sect = adev->gfx.rlc.cs_data; sect->section != NULL((void *)0); ++sect) { |
1263 | for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) { |
1264 | if (sect->id == SECT_CONTEXT) { |
1265 | buffer[count++] = |
1266 | cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->reg_count) & 0x3FFF) << 16))); |
1267 | buffer[count++] = cpu_to_le32(ext->reg_index -((__uint32_t)(ext->reg_index - 0x0000a000)) |
1268 | PACKET3_SET_CONTEXT_REG_START)((__uint32_t)(ext->reg_index - 0x0000a000)); |
1269 | for (i = 0; i < ext->reg_count; i++) |
1270 | buffer[count++] = cpu_to_le32(ext->extent[i])((__uint32_t)(ext->extent[i])); |
1271 | } else { |
1272 | return; |
1273 | } |
1274 | } |
1275 | } |
1276 | |
1277 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) << 8) | ((2) & 0x3FFF) << 16))); |
1278 | buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG -((__uint32_t)(0xa0d4 - 0x0000a000)) |
1279 | PACKET3_SET_CONTEXT_REG_START)((__uint32_t)(0xa0d4 - 0x0000a000)); |
1280 | buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config)((__uint32_t)(adev->gfx.config.rb_config[0][0].raster_config )); |
1281 | buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config_1)((__uint32_t)(adev->gfx.config.rb_config[0][0].raster_config_1 )); |
1282 | |
1283 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16))); |
1284 | buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE)((__uint32_t)((3 << 28))); |
1285 | |
1286 | buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0))((__uint32_t)(((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) & 0x3FFF) << 16))); |
1287 | buffer[count++] = cpu_to_le32(0)((__uint32_t)(0)); |
1288 | } |
1289 | |
1290 | static int gfx_v8_0_cp_jump_table_num(struct amdgpu_device *adev) |
1291 | { |
1292 | if (adev->asic_type == CHIP_CARRIZO) |
1293 | return 5; |
1294 | else |
1295 | return 4; |
1296 | } |
1297 | |
1298 | static int gfx_v8_0_rlc_init(struct amdgpu_device *adev) |
1299 | { |
1300 | const struct cs_section_def *cs_data; |
1301 | int r; |
1302 | |
1303 | adev->gfx.rlc.cs_data = vi_cs_data; |
1304 | |
1305 | cs_data = adev->gfx.rlc.cs_data; |
1306 | |
1307 | if (cs_data) { |
1308 | /* init clear state block */ |
1309 | r = amdgpu_gfx_rlc_init_csb(adev); |
1310 | if (r) |
1311 | return r; |
1312 | } |
1313 | |
1314 | if ((adev->asic_type == CHIP_CARRIZO) || |
1315 | (adev->asic_type == CHIP_STONEY)) { |
1316 | adev->gfx.rlc.cp_table_size = roundup2(96 * 5 * 4, 2048)(((96 * 5 * 4) + ((2048) - 1)) & (~((__typeof(96 * 5 * 4) )(2048) - 1))) + (64 * 1024); /* JT + GDS */ |
1317 | r = amdgpu_gfx_rlc_init_cpt(adev); |
1318 | if (r) |
1319 | return r; |
1320 | } |
1321 | |
1322 | /* init spm vmid with 0xf */ |
1323 | if (adev->gfx.rlc.funcs->update_spm_vmid) |
1324 | adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); |
1325 | |
1326 | return 0; |
1327 | } |
1328 | |
1329 | static void gfx_v8_0_mec_fini(struct amdgpu_device *adev) |
1330 | { |
1331 | amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL((void *)0), NULL((void *)0)); |
1332 | } |
1333 | |
1334 | static int gfx_v8_0_mec_init(struct amdgpu_device *adev) |
1335 | { |
1336 | int r; |
1337 | u32 *hpd; |
1338 | size_t mec_hpd_size; |
1339 | |
1340 | bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES128); |
1341 | |
1342 | /* take ownership of the relevant compute queues */ |
1343 | amdgpu_gfx_compute_queue_acquire(adev); |
1344 | |
1345 | mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE4096; |
1346 | if (mec_hpd_size) { |
1347 | r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE(1 << 12), |
1348 | AMDGPU_GEM_DOMAIN_VRAM0x4, |
1349 | &adev->gfx.mec.hpd_eop_obj, |
1350 | &adev->gfx.mec.hpd_eop_gpu_addr, |
1351 | (void **)&hpd); |
1352 | if (r) { |
1353 | dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create HDP EOP bo failed\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r); |
1354 | return r; |
1355 | } |
1356 | |
1357 | memset(hpd, 0, mec_hpd_size)__builtin_memset((hpd), (0), (mec_hpd_size)); |
1358 | |
1359 | amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); |
1360 | amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); |
1361 | } |
1362 | |
1363 | return 0; |
1364 | } |
1365 | |
1366 | static const u32 vgpr_init_compute_shader[] = |
1367 | { |
1368 | 0x7e000209, 0x7e020208, |
1369 | 0x7e040207, 0x7e060206, |
1370 | 0x7e080205, 0x7e0a0204, |
1371 | 0x7e0c0203, 0x7e0e0202, |
1372 | 0x7e100201, 0x7e120200, |
1373 | 0x7e140209, 0x7e160208, |
1374 | 0x7e180207, 0x7e1a0206, |
1375 | 0x7e1c0205, 0x7e1e0204, |
1376 | 0x7e200203, 0x7e220202, |
1377 | 0x7e240201, 0x7e260200, |
1378 | 0x7e280209, 0x7e2a0208, |
1379 | 0x7e2c0207, 0x7e2e0206, |
1380 | 0x7e300205, 0x7e320204, |
1381 | 0x7e340203, 0x7e360202, |
1382 | 0x7e380201, 0x7e3a0200, |
1383 | 0x7e3c0209, 0x7e3e0208, |
1384 | 0x7e400207, 0x7e420206, |
1385 | 0x7e440205, 0x7e460204, |
1386 | 0x7e480203, 0x7e4a0202, |
1387 | 0x7e4c0201, 0x7e4e0200, |
1388 | 0x7e500209, 0x7e520208, |
1389 | 0x7e540207, 0x7e560206, |
1390 | 0x7e580205, 0x7e5a0204, |
1391 | 0x7e5c0203, 0x7e5e0202, |
1392 | 0x7e600201, 0x7e620200, |
1393 | 0x7e640209, 0x7e660208, |
1394 | 0x7e680207, 0x7e6a0206, |
1395 | 0x7e6c0205, 0x7e6e0204, |
1396 | 0x7e700203, 0x7e720202, |
1397 | 0x7e740201, 0x7e760200, |
1398 | 0x7e780209, 0x7e7a0208, |
1399 | 0x7e7c0207, 0x7e7e0206, |
1400 | 0xbf8a0000, 0xbf810000, |
1401 | }; |
1402 | |
1403 | static const u32 sgpr_init_compute_shader[] = |
1404 | { |
1405 | 0xbe8a0100, 0xbe8c0102, |
1406 | 0xbe8e0104, 0xbe900106, |
1407 | 0xbe920108, 0xbe940100, |
1408 | 0xbe960102, 0xbe980104, |
1409 | 0xbe9a0106, 0xbe9c0108, |
1410 | 0xbe9e0100, 0xbea00102, |
1411 | 0xbea20104, 0xbea40106, |
1412 | 0xbea60108, 0xbea80100, |
1413 | 0xbeaa0102, 0xbeac0104, |
1414 | 0xbeae0106, 0xbeb00108, |
1415 | 0xbeb20100, 0xbeb40102, |
1416 | 0xbeb60104, 0xbeb80106, |
1417 | 0xbeba0108, 0xbebc0100, |
1418 | 0xbebe0102, 0xbec00104, |
1419 | 0xbec20106, 0xbec40108, |
1420 | 0xbec60100, 0xbec80102, |
1421 | 0xbee60004, 0xbee70005, |
1422 | 0xbeea0006, 0xbeeb0007, |
1423 | 0xbee80008, 0xbee90009, |
1424 | 0xbefc0000, 0xbf8a0000, |
1425 | 0xbf810000, 0x00000000, |
1426 | }; |
1427 | |
1428 | static const u32 vgpr_init_regs[] = |
1429 | { |
1430 | mmCOMPUTE_STATIC_THREAD_MGMT_SE00x2e16, 0xffffffff, |
1431 | mmCOMPUTE_RESOURCE_LIMITS0x2e15, 0x1000000, /* CU_GROUP_COUNT=1 */ |
1432 | mmCOMPUTE_NUM_THREAD_X0x2e07, 256*4, |
1433 | mmCOMPUTE_NUM_THREAD_Y0x2e08, 1, |
1434 | mmCOMPUTE_NUM_THREAD_Z0x2e09, 1, |
1435 | mmCOMPUTE_PGM_RSRC10x2e12, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */ |
1436 | mmCOMPUTE_PGM_RSRC20x2e13, 20, |
1437 | mmCOMPUTE_USER_DATA_00x2e40, 0xedcedc00, |
1438 | mmCOMPUTE_USER_DATA_10x2e41, 0xedcedc01, |
1439 | mmCOMPUTE_USER_DATA_20x2e42, 0xedcedc02, |
1440 | mmCOMPUTE_USER_DATA_30x2e43, 0xedcedc03, |
1441 | mmCOMPUTE_USER_DATA_40x2e44, 0xedcedc04, |
1442 | mmCOMPUTE_USER_DATA_50x2e45, 0xedcedc05, |
1443 | mmCOMPUTE_USER_DATA_60x2e46, 0xedcedc06, |
1444 | mmCOMPUTE_USER_DATA_70x2e47, 0xedcedc07, |
1445 | mmCOMPUTE_USER_DATA_80x2e48, 0xedcedc08, |
1446 | mmCOMPUTE_USER_DATA_90x2e49, 0xedcedc09, |
1447 | }; |
1448 | |
1449 | static const u32 sgpr1_init_regs[] = |
1450 | { |
1451 | mmCOMPUTE_STATIC_THREAD_MGMT_SE00x2e16, 0x0f, |
1452 | mmCOMPUTE_RESOURCE_LIMITS0x2e15, 0x1000000, /* CU_GROUP_COUNT=1 */ |
1453 | mmCOMPUTE_NUM_THREAD_X0x2e07, 256*5, |
1454 | mmCOMPUTE_NUM_THREAD_Y0x2e08, 1, |
1455 | mmCOMPUTE_NUM_THREAD_Z0x2e09, 1, |
1456 | mmCOMPUTE_PGM_RSRC10x2e12, 0x240, /* SGPRS=9 (80 GPRS) */ |
1457 | mmCOMPUTE_PGM_RSRC20x2e13, 20, |
1458 | mmCOMPUTE_USER_DATA_00x2e40, 0xedcedc00, |
1459 | mmCOMPUTE_USER_DATA_10x2e41, 0xedcedc01, |
1460 | mmCOMPUTE_USER_DATA_20x2e42, 0xedcedc02, |
1461 | mmCOMPUTE_USER_DATA_30x2e43, 0xedcedc03, |
1462 | mmCOMPUTE_USER_DATA_40x2e44, 0xedcedc04, |
1463 | mmCOMPUTE_USER_DATA_50x2e45, 0xedcedc05, |
1464 | mmCOMPUTE_USER_DATA_60x2e46, 0xedcedc06, |
1465 | mmCOMPUTE_USER_DATA_70x2e47, 0xedcedc07, |
1466 | mmCOMPUTE_USER_DATA_80x2e48, 0xedcedc08, |
1467 | mmCOMPUTE_USER_DATA_90x2e49, 0xedcedc09, |
1468 | }; |
1469 | |
1470 | static const u32 sgpr2_init_regs[] = |
1471 | { |
1472 | mmCOMPUTE_STATIC_THREAD_MGMT_SE00x2e16, 0xf0, |
1473 | mmCOMPUTE_RESOURCE_LIMITS0x2e15, 0x1000000, |
1474 | mmCOMPUTE_NUM_THREAD_X0x2e07, 256*5, |
1475 | mmCOMPUTE_NUM_THREAD_Y0x2e08, 1, |
1476 | mmCOMPUTE_NUM_THREAD_Z0x2e09, 1, |
1477 | mmCOMPUTE_PGM_RSRC10x2e12, 0x240, /* SGPRS=9 (80 GPRS) */ |
1478 | mmCOMPUTE_PGM_RSRC20x2e13, 20, |
1479 | mmCOMPUTE_USER_DATA_00x2e40, 0xedcedc00, |
1480 | mmCOMPUTE_USER_DATA_10x2e41, 0xedcedc01, |
1481 | mmCOMPUTE_USER_DATA_20x2e42, 0xedcedc02, |
1482 | mmCOMPUTE_USER_DATA_30x2e43, 0xedcedc03, |
1483 | mmCOMPUTE_USER_DATA_40x2e44, 0xedcedc04, |
1484 | mmCOMPUTE_USER_DATA_50x2e45, 0xedcedc05, |
1485 | mmCOMPUTE_USER_DATA_60x2e46, 0xedcedc06, |
1486 | mmCOMPUTE_USER_DATA_70x2e47, 0xedcedc07, |
1487 | mmCOMPUTE_USER_DATA_80x2e48, 0xedcedc08, |
1488 | mmCOMPUTE_USER_DATA_90x2e49, 0xedcedc09, |
1489 | }; |
1490 | |
1491 | static const u32 sec_ded_counter_registers[] = |
1492 | { |
1493 | mmCPC_EDC_ATC_CNT0x3190, |
1494 | mmCPC_EDC_SCRATCH_CNT0x318e, |
1495 | mmCPC_EDC_UCODE_CNT0x318f, |
1496 | mmCPF_EDC_ATC_CNT0x318a, |
1497 | mmCPF_EDC_ROQ_CNT0x3189, |
1498 | mmCPF_EDC_TAG_CNT0x3188, |
1499 | mmCPG_EDC_ATC_CNT0x318c, |
1500 | mmCPG_EDC_DMA_CNT0x318d, |
1501 | mmCPG_EDC_TAG_CNT0x318b, |
1502 | mmDC_EDC_CSINVOC_CNT0x3192, |
1503 | mmDC_EDC_RESTORE_CNT0x3193, |
1504 | mmDC_EDC_STATE_CNT0x3191, |
1505 | mmGDS_EDC_CNT0x25c5, |
1506 | mmGDS_EDC_GRBM_CNT0x25c6, |
1507 | mmGDS_EDC_OA_DED0x25c7, |
1508 | mmSPI_EDC_CNT0x2444, |
1509 | mmSQC_ATC_EDC_GATCL1_CNT0x23b3, |
1510 | mmSQC_EDC_CNT0x23a0, |
1511 | mmSQ_EDC_DED_CNT0x23a2, |
1512 | mmSQ_EDC_INFO0x23a3, |
1513 | mmSQ_EDC_SEC_CNT0x23a1, |
1514 | mmTCC_EDC_CNT0x2b82, |
1515 | mmTCP_ATC_EDC_GATCL1_CNT0x32b1, |
1516 | mmTCP_EDC_CNT0x2b17, |
1517 | mmTD_EDC_CNT0x252e |
1518 | }; |
1519 | |
1520 | static int gfx_v8_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) |
1521 | { |
1522 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[0]; |
1523 | struct amdgpu_ib ib; |
1524 | struct dma_fence *f = NULL((void *)0); |
1525 | int r, i; |
1526 | u32 tmp; |
1527 | unsigned total_size, vgpr_offset, sgpr_offset; |
1528 | u64 gpu_addr; |
1529 | |
1530 | /* only supported on CZ */ |
1531 | if (adev->asic_type != CHIP_CARRIZO) |
1532 | return 0; |
1533 | |
1534 | /* bail if the compute ring is not ready */ |
1535 | if (!ring->sched.ready) |
1536 | return 0; |
1537 | |
1538 | tmp = RREG32(mmGB_EDC_MODE)amdgpu_device_rreg(adev, (0x307e), 0); |
1539 | WREG32(mmGB_EDC_MODE, 0)amdgpu_device_wreg(adev, (0x307e), (0), 0); |
1540 | |
1541 | total_size = |
1542 | (((ARRAY_SIZE(vgpr_init_regs)(sizeof((vgpr_init_regs)) / sizeof((vgpr_init_regs)[0])) / 2) * 3) + 4 + 5 + 2) * 4; |
1543 | total_size += |
1544 | (((ARRAY_SIZE(sgpr1_init_regs)(sizeof((sgpr1_init_regs)) / sizeof((sgpr1_init_regs)[0])) / 2) * 3) + 4 + 5 + 2) * 4; |
1545 | total_size += |
1546 | (((ARRAY_SIZE(sgpr2_init_regs)(sizeof((sgpr2_init_regs)) / sizeof((sgpr2_init_regs)[0])) / 2) * 3) + 4 + 5 + 2) * 4; |
1547 | total_size = roundup2(total_size, 256)(((total_size) + ((256) - 1)) & (~((__typeof(total_size)) (256) - 1))); |
1548 | vgpr_offset = total_size; |
1549 | total_size += roundup2(sizeof(vgpr_init_compute_shader), 256)(((sizeof(vgpr_init_compute_shader)) + ((256) - 1)) & (~( (__typeof(sizeof(vgpr_init_compute_shader)))(256) - 1))); |
1550 | sgpr_offset = total_size; |
1551 | total_size += sizeof(sgpr_init_compute_shader); |
1552 | |
1553 | /* allocate an indirect buffer to put the commands in */ |
1554 | memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib))); |
1555 | r = amdgpu_ib_get(adev, NULL((void *)0), total_size, |
1556 | AMDGPU_IB_POOL_DIRECT, &ib); |
1557 | if (r) { |
1558 | DRM_ERROR("amdgpu: failed to get ib (%d).\n", r)__drm_err("amdgpu: failed to get ib (%d).\n", r); |
1559 | return r; |
1560 | } |
1561 | |
1562 | /* load the compute shaders */ |
1563 | for (i = 0; i < ARRAY_SIZE(vgpr_init_compute_shader)(sizeof((vgpr_init_compute_shader)) / sizeof((vgpr_init_compute_shader )[0])); i++) |
1564 | ib.ptr[i + (vgpr_offset / 4)] = vgpr_init_compute_shader[i]; |
1565 | |
1566 | for (i = 0; i < ARRAY_SIZE(sgpr_init_compute_shader)(sizeof((sgpr_init_compute_shader)) / sizeof((sgpr_init_compute_shader )[0])); i++) |
1567 | ib.ptr[i + (sgpr_offset / 4)] = sgpr_init_compute_shader[i]; |
1568 | |
1569 | /* init the ib length to 0 */ |
1570 | ib.length_dw = 0; |
1571 | |
1572 | /* VGPR */ |
1573 | /* write the register state for the compute dispatch */ |
1574 | for (i = 0; i < ARRAY_SIZE(vgpr_init_regs)(sizeof((vgpr_init_regs)) / sizeof((vgpr_init_regs)[0])); i += 2) { |
1575 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) & 0x3FFF) << 16); |
1576 | ib.ptr[ib.length_dw++] = vgpr_init_regs[i] - PACKET3_SET_SH_REG_START0x00002c00; |
1577 | ib.ptr[ib.length_dw++] = vgpr_init_regs[i + 1]; |
1578 | } |
1579 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
1580 | gpu_addr = (ib.gpu_addr + (u64)vgpr_offset) >> 8; |
1581 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) & 0x3FFF) << 16); |
1582 | ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO0x2e0c - PACKET3_SET_SH_REG_START0x00002c00; |
1583 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
1584 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
1585 | |
1586 | /* write dispatch packet */ |
1587 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
1588 | ib.ptr[ib.length_dw++] = 8; /* x */ |
1589 | ib.ptr[ib.length_dw++] = 1; /* y */ |
1590 | ib.ptr[ib.length_dw++] = 1; /* z */ |
1591 | ib.ptr[ib.length_dw++] = |
1592 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x1) | (0x1 & ((1) << 0x0))); |
1593 | |
1594 | /* write CS partial flush packet */ |
1595 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) & 0x3FFF) << 16); |
1596 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8); |
1597 | |
1598 | /* SGPR1 */ |
1599 | /* write the register state for the compute dispatch */ |
1600 | for (i = 0; i < ARRAY_SIZE(sgpr1_init_regs)(sizeof((sgpr1_init_regs)) / sizeof((sgpr1_init_regs)[0])); i += 2) { |
1601 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) & 0x3FFF) << 16); |
1602 | ib.ptr[ib.length_dw++] = sgpr1_init_regs[i] - PACKET3_SET_SH_REG_START0x00002c00; |
1603 | ib.ptr[ib.length_dw++] = sgpr1_init_regs[i + 1]; |
1604 | } |
1605 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
1606 | gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; |
1607 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) & 0x3FFF) << 16); |
1608 | ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO0x2e0c - PACKET3_SET_SH_REG_START0x00002c00; |
1609 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
1610 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
1611 | |
1612 | /* write dispatch packet */ |
1613 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
1614 | ib.ptr[ib.length_dw++] = 8; /* x */ |
1615 | ib.ptr[ib.length_dw++] = 1; /* y */ |
1616 | ib.ptr[ib.length_dw++] = 1; /* z */ |
1617 | ib.ptr[ib.length_dw++] = |
1618 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x1) | (0x1 & ((1) << 0x0))); |
1619 | |
1620 | /* write CS partial flush packet */ |
1621 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) & 0x3FFF) << 16); |
1622 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8); |
1623 | |
1624 | /* SGPR2 */ |
1625 | /* write the register state for the compute dispatch */ |
1626 | for (i = 0; i < ARRAY_SIZE(sgpr2_init_regs)(sizeof((sgpr2_init_regs)) / sizeof((sgpr2_init_regs)[0])); i += 2) { |
1627 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1)((3 << 30) | (((0x76) & 0xFF) << 8) | ((1) & 0x3FFF) << 16); |
1628 | ib.ptr[ib.length_dw++] = sgpr2_init_regs[i] - PACKET3_SET_SH_REG_START0x00002c00; |
1629 | ib.ptr[ib.length_dw++] = sgpr2_init_regs[i + 1]; |
1630 | } |
1631 | /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */ |
1632 | gpu_addr = (ib.gpu_addr + (u64)sgpr_offset) >> 8; |
1633 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)((3 << 30) | (((0x76) & 0xFF) << 8) | ((2) & 0x3FFF) << 16); |
1634 | ib.ptr[ib.length_dw++] = mmCOMPUTE_PGM_LO0x2e0c - PACKET3_SET_SH_REG_START0x00002c00; |
1635 | ib.ptr[ib.length_dw++] = lower_32_bits(gpu_addr)((u32)(gpu_addr)); |
1636 | ib.ptr[ib.length_dw++] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)); |
1637 | |
1638 | /* write dispatch packet */ |
1639 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3)((3 << 30) | (((0x15) & 0xFF) << 8) | ((3) & 0x3FFF) << 16); |
1640 | ib.ptr[ib.length_dw++] = 8; /* x */ |
1641 | ib.ptr[ib.length_dw++] = 1; /* y */ |
1642 | ib.ptr[ib.length_dw++] = 1; /* z */ |
1643 | ib.ptr[ib.length_dw++] = |
1644 | REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1)(((0) & ~0x1) | (0x1 & ((1) << 0x0))); |
1645 | |
1646 | /* write CS partial flush packet */ |
1647 | ib.ptr[ib.length_dw++] = PACKET3(PACKET3_EVENT_WRITE, 0)((3 << 30) | (((0x46) & 0xFF) << 8) | ((0) & 0x3FFF) << 16); |
1648 | ib.ptr[ib.length_dw++] = EVENT_TYPE(7)((7) << 0) | EVENT_INDEX(4)((4) << 8); |
1649 | |
1650 | /* shedule the ib on the ring */ |
1651 | r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f); |
1652 | if (r) { |
1653 | DRM_ERROR("amdgpu: ib submit failed (%d).\n", r)__drm_err("amdgpu: ib submit failed (%d).\n", r); |
1654 | goto fail; |
1655 | } |
1656 | |
1657 | /* wait for the GPU to finish processing the IB */ |
1658 | r = dma_fence_wait(f, false0); |
1659 | if (r) { |
1660 | DRM_ERROR("amdgpu: fence wait failed (%d).\n", r)__drm_err("amdgpu: fence wait failed (%d).\n", r); |
1661 | goto fail; |
1662 | } |
1663 | |
1664 | tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, DED_MODE, 2)(((tmp) & ~0x300000) | (0x300000 & ((2) << 0x14 ))); |
1665 | tmp = REG_SET_FIELD(tmp, GB_EDC_MODE, PROP_FED, 1)(((tmp) & ~0x20000000) | (0x20000000 & ((1) << 0x1d ))); |
1666 | WREG32(mmGB_EDC_MODE, tmp)amdgpu_device_wreg(adev, (0x307e), (tmp), 0); |
1667 | |
1668 | tmp = RREG32(mmCC_GC_EDC_CONFIG)amdgpu_device_rreg(adev, (0x3098), 0); |
1669 | tmp = REG_SET_FIELD(tmp, CC_GC_EDC_CONFIG, DIS_EDC, 0)(((tmp) & ~0x2) | (0x2 & ((0) << 0x1))) | 1; |
1670 | WREG32(mmCC_GC_EDC_CONFIG, tmp)amdgpu_device_wreg(adev, (0x3098), (tmp), 0); |
1671 | |
1672 | |
1673 | /* read back registers to clear the counters */ |
1674 | for (i = 0; i < ARRAY_SIZE(sec_ded_counter_registers)(sizeof((sec_ded_counter_registers)) / sizeof((sec_ded_counter_registers )[0])); i++) |
1675 | RREG32(sec_ded_counter_registers[i])amdgpu_device_rreg(adev, (sec_ded_counter_registers[i]), 0); |
1676 | |
1677 | fail: |
1678 | amdgpu_ib_free(adev, &ib, NULL((void *)0)); |
1679 | dma_fence_put(f); |
1680 | |
1681 | return r; |
1682 | } |
1683 | |
1684 | static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) |
1685 | { |
1686 | u32 gb_addr_config; |
1687 | u32 mc_arb_ramcfg; |
1688 | u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; |
1689 | u32 tmp; |
1690 | int ret; |
1691 | |
1692 | switch (adev->asic_type) { |
1693 | case CHIP_TOPAZ: |
1694 | adev->gfx.config.max_shader_engines = 1; |
1695 | adev->gfx.config.max_tile_pipes = 2; |
1696 | adev->gfx.config.max_cu_per_sh = 6; |
1697 | adev->gfx.config.max_sh_per_se = 1; |
1698 | adev->gfx.config.max_backends_per_se = 2; |
1699 | adev->gfx.config.max_texture_channel_caches = 2; |
1700 | adev->gfx.config.max_gprs = 256; |
1701 | adev->gfx.config.max_gs_threads = 32; |
1702 | adev->gfx.config.max_hw_contexts = 8; |
1703 | |
1704 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1705 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1706 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1707 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1708 | gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN0x22010001; |
1709 | break; |
1710 | case CHIP_FIJI: |
1711 | adev->gfx.config.max_shader_engines = 4; |
1712 | adev->gfx.config.max_tile_pipes = 16; |
1713 | adev->gfx.config.max_cu_per_sh = 16; |
1714 | adev->gfx.config.max_sh_per_se = 1; |
1715 | adev->gfx.config.max_backends_per_se = 4; |
1716 | adev->gfx.config.max_texture_channel_caches = 16; |
1717 | adev->gfx.config.max_gprs = 256; |
1718 | adev->gfx.config.max_gs_threads = 32; |
1719 | adev->gfx.config.max_hw_contexts = 8; |
1720 | |
1721 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1722 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1723 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1724 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1725 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN0x22011003; |
1726 | break; |
1727 | case CHIP_POLARIS11: |
1728 | case CHIP_POLARIS12: |
1729 | ret = amdgpu_atombios_get_gfx_info(adev); |
1730 | if (ret) |
1731 | return ret; |
1732 | adev->gfx.config.max_gprs = 256; |
1733 | adev->gfx.config.max_gs_threads = 32; |
1734 | adev->gfx.config.max_hw_contexts = 8; |
1735 | |
1736 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1737 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1738 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1739 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1740 | gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN0x22011002; |
1741 | break; |
1742 | case CHIP_POLARIS10: |
1743 | case CHIP_VEGAM: |
1744 | ret = amdgpu_atombios_get_gfx_info(adev); |
1745 | if (ret) |
1746 | return ret; |
1747 | adev->gfx.config.max_gprs = 256; |
1748 | adev->gfx.config.max_gs_threads = 32; |
1749 | adev->gfx.config.max_hw_contexts = 8; |
1750 | |
1751 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1752 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1753 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1754 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1755 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN0x22011003; |
1756 | break; |
1757 | case CHIP_TONGA: |
1758 | adev->gfx.config.max_shader_engines = 4; |
1759 | adev->gfx.config.max_tile_pipes = 8; |
1760 | adev->gfx.config.max_cu_per_sh = 8; |
1761 | adev->gfx.config.max_sh_per_se = 1; |
1762 | adev->gfx.config.max_backends_per_se = 2; |
1763 | adev->gfx.config.max_texture_channel_caches = 8; |
1764 | adev->gfx.config.max_gprs = 256; |
1765 | adev->gfx.config.max_gs_threads = 32; |
1766 | adev->gfx.config.max_hw_contexts = 8; |
1767 | |
1768 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1769 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1770 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1771 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1772 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN0x22011003; |
1773 | break; |
1774 | case CHIP_CARRIZO: |
1775 | adev->gfx.config.max_shader_engines = 1; |
1776 | adev->gfx.config.max_tile_pipes = 2; |
1777 | adev->gfx.config.max_sh_per_se = 1; |
1778 | adev->gfx.config.max_backends_per_se = 2; |
1779 | adev->gfx.config.max_cu_per_sh = 8; |
1780 | adev->gfx.config.max_texture_channel_caches = 2; |
1781 | adev->gfx.config.max_gprs = 256; |
1782 | adev->gfx.config.max_gs_threads = 32; |
1783 | adev->gfx.config.max_hw_contexts = 8; |
1784 | |
1785 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1786 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1787 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1788 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1789 | gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN0x22010001; |
1790 | break; |
1791 | case CHIP_STONEY: |
1792 | adev->gfx.config.max_shader_engines = 1; |
1793 | adev->gfx.config.max_tile_pipes = 2; |
1794 | adev->gfx.config.max_sh_per_se = 1; |
1795 | adev->gfx.config.max_backends_per_se = 1; |
1796 | adev->gfx.config.max_cu_per_sh = 3; |
1797 | adev->gfx.config.max_texture_channel_caches = 2; |
1798 | adev->gfx.config.max_gprs = 256; |
1799 | adev->gfx.config.max_gs_threads = 16; |
1800 | adev->gfx.config.max_hw_contexts = 8; |
1801 | |
1802 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1803 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1804 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1805 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1806 | gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN0x22010001; |
1807 | break; |
1808 | default: |
1809 | adev->gfx.config.max_shader_engines = 2; |
1810 | adev->gfx.config.max_tile_pipes = 4; |
1811 | adev->gfx.config.max_cu_per_sh = 2; |
1812 | adev->gfx.config.max_sh_per_se = 1; |
1813 | adev->gfx.config.max_backends_per_se = 2; |
1814 | adev->gfx.config.max_texture_channel_caches = 4; |
1815 | adev->gfx.config.max_gprs = 256; |
1816 | adev->gfx.config.max_gs_threads = 32; |
1817 | adev->gfx.config.max_hw_contexts = 8; |
1818 | |
1819 | adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; |
1820 | adev->gfx.config.sc_prim_fifo_size_backend = 0x100; |
1821 | adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; |
1822 | adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; |
1823 | gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN0x22011003; |
1824 | break; |
1825 | } |
1826 | |
1827 | adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG)amdgpu_device_rreg(adev, (0x9d8), 0); |
1828 | mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; |
1829 | |
1830 | adev->gfx.config.num_banks = REG_GET_FIELD(mc_arb_ramcfg,(((mc_arb_ramcfg) & 0x3) >> 0x0) |
1831 | MC_ARB_RAMCFG, NOOFBANK)(((mc_arb_ramcfg) & 0x3) >> 0x0); |
1832 | adev->gfx.config.num_ranks = REG_GET_FIELD(mc_arb_ramcfg,(((mc_arb_ramcfg) & 0x4) >> 0x2) |
1833 | MC_ARB_RAMCFG, NOOFRANKS)(((mc_arb_ramcfg) & 0x4) >> 0x2); |
1834 | |
1835 | adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; |
1836 | adev->gfx.config.mem_max_burst_length_bytes = 256; |
1837 | if (adev->flags & AMD_IS_APU) { |
1838 | /* Get memory bank mapping mode. */ |
1839 | tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING)amdgpu_device_rreg(adev, (0xa11), 0); |
1840 | dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP)(((tmp) & 0xf) >> 0x0); |
1841 | dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP)(((tmp) & 0xf0) >> 0x4); |
1842 | |
1843 | tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING)amdgpu_device_rreg(adev, (0xa12), 0); |
1844 | dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP)(((tmp) & 0xf) >> 0x0); |
1845 | dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP)(((tmp) & 0xf0) >> 0x4); |
1846 | |
1847 | /* Validate settings in case only one DIMM installed. */ |
1848 | if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) |
1849 | dimm00_addr_map = 0; |
1850 | if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) |
1851 | dimm01_addr_map = 0; |
1852 | if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) |
1853 | dimm10_addr_map = 0; |
1854 | if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) |
1855 | dimm11_addr_map = 0; |
1856 | |
1857 | /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ |
1858 | /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ |
1859 | if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) |
1860 | adev->gfx.config.mem_row_size_in_kb = 2; |
1861 | else |
1862 | adev->gfx.config.mem_row_size_in_kb = 1; |
1863 | } else { |
1864 | tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS)(((mc_arb_ramcfg) & 0xc0) >> 0x6); |
1865 | adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; |
1866 | if (adev->gfx.config.mem_row_size_in_kb > 4) |
1867 | adev->gfx.config.mem_row_size_in_kb = 4; |
1868 | } |
1869 | |
1870 | adev->gfx.config.shader_engine_tile_size = 32; |
1871 | adev->gfx.config.num_gpus = 1; |
1872 | adev->gfx.config.multi_gpu_tile_size = 64; |
1873 | |
1874 | /* fix up row size */ |
1875 | switch (adev->gfx.config.mem_row_size_in_kb) { |
1876 | case 1: |
1877 | default: |
1878 | gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0)(((gb_addr_config) & ~0x30000000) | (0x30000000 & ((0 ) << 0x1c))); |
1879 | break; |
1880 | case 2: |
1881 | gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1)(((gb_addr_config) & ~0x30000000) | (0x30000000 & ((1 ) << 0x1c))); |
1882 | break; |
1883 | case 4: |
1884 | gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2)(((gb_addr_config) & ~0x30000000) | (0x30000000 & ((2 ) << 0x1c))); |
1885 | break; |
1886 | } |
1887 | adev->gfx.config.gb_addr_config = gb_addr_config; |
1888 | |
1889 | return 0; |
1890 | } |
1891 | |
1892 | static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, |
1893 | int mec, int pipe, int queue) |
1894 | { |
1895 | int r; |
1896 | unsigned irq_type; |
1897 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; |
1898 | unsigned int hw_prio; |
1899 | |
1900 | ring = &adev->gfx.compute_ring[ring_id]; |
1901 | |
1902 | /* mec0 is me1 */ |
1903 | ring->me = mec + 1; |
1904 | ring->pipe = pipe; |
1905 | ring->queue = queue; |
1906 | |
1907 | ring->ring_obj = NULL((void *)0); |
1908 | ring->use_doorbell = true1; |
1909 | ring->doorbell_index = adev->doorbell_index.mec_ring0 + ring_id; |
1910 | ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr |
1911 | + (ring_id * GFX8_MEC_HPD_SIZE4096); |
1912 | snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); |
1913 | |
1914 | irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP |
1915 | + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) |
1916 | + ring->pipe; |
1917 | |
1918 | hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, |
1919 | ring->queue) ? |
1920 | AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_RING_PRIO_DEFAULT1; |
1921 | /* type-2 packets are deprecated on MEC, use type-3 instead */ |
1922 | r = amdgpu_ring_init(adev, ring, 1024, |
1923 | &adev->gfx.eop_irq, irq_type, hw_prio); |
1924 | if (r) |
1925 | return r; |
1926 | |
1927 | |
1928 | return 0; |
1929 | } |
1930 | |
1931 | static void gfx_v8_0_sq_irq_work_func(struct work_struct *work); |
1932 | |
1933 | static int gfx_v8_0_sw_init(void *handle) |
1934 | { |
1935 | int i, j, k, r, ring_id; |
1936 | struct amdgpu_ring *ring; |
1937 | struct amdgpu_kiq *kiq; |
1938 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
1939 | |
1940 | switch (adev->asic_type) { |
1941 | case CHIP_TONGA: |
1942 | case CHIP_CARRIZO: |
1943 | case CHIP_FIJI: |
1944 | case CHIP_POLARIS10: |
1945 | case CHIP_POLARIS11: |
1946 | case CHIP_POLARIS12: |
1947 | case CHIP_VEGAM: |
1948 | adev->gfx.mec.num_mec = 2; |
1949 | break; |
1950 | case CHIP_TOPAZ: |
1951 | case CHIP_STONEY: |
1952 | default: |
1953 | adev->gfx.mec.num_mec = 1; |
1954 | break; |
1955 | } |
1956 | |
1957 | adev->gfx.mec.num_pipe_per_mec = 4; |
1958 | adev->gfx.mec.num_queue_per_pipe = 8; |
1959 | |
1960 | /* EOP Event */ |
1961 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_CP_END_OF_PIPE0x000000b5, &adev->gfx.eop_irq); |
1962 | if (r) |
1963 | return r; |
1964 | |
1965 | /* Privileged reg */ |
1966 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT0x000000b8, |
1967 | &adev->gfx.priv_reg_irq); |
1968 | if (r) |
1969 | return r; |
1970 | |
1971 | /* Privileged inst */ |
1972 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT0x000000b9, |
1973 | &adev->gfx.priv_inst_irq); |
1974 | if (r) |
1975 | return r; |
1976 | |
1977 | /* Add CP EDC/ECC irq */ |
1978 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_CP_ECC_ERROR0x000000c5, |
1979 | &adev->gfx.cp_ecc_error_irq); |
1980 | if (r) |
1981 | return r; |
1982 | |
1983 | /* SQ interrupts. */ |
1984 | r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY0, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG0x000000ef, |
1985 | &adev->gfx.sq_irq); |
1986 | if (r) { |
1987 | DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r)__drm_err("amdgpu_irq_add() for SQ failed: %d\n", r); |
1988 | return r; |
1989 | } |
1990 | |
1991 | INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func); |
1992 | |
1993 | adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE0x00000000L; |
1994 | |
1995 | gfx_v8_0_scratch_init(adev); |
1996 | |
1997 | r = gfx_v8_0_init_microcode(adev); |
1998 | if (r) { |
1999 | DRM_ERROR("Failed to load gfx firmware!\n")__drm_err("Failed to load gfx firmware!\n"); |
2000 | return r; |
2001 | } |
2002 | |
2003 | r = adev->gfx.rlc.funcs->init(adev); |
2004 | if (r) { |
2005 | DRM_ERROR("Failed to init rlc BOs!\n")__drm_err("Failed to init rlc BOs!\n"); |
2006 | return r; |
2007 | } |
2008 | |
2009 | r = gfx_v8_0_mec_init(adev); |
2010 | if (r) { |
2011 | DRM_ERROR("Failed to init MEC BOs!\n")__drm_err("Failed to init MEC BOs!\n"); |
2012 | return r; |
2013 | } |
2014 | |
2015 | /* set up the gfx ring */ |
2016 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) { |
2017 | ring = &adev->gfx.gfx_ring[i]; |
2018 | ring->ring_obj = NULL((void *)0); |
2019 | snprintf(ring->name, sizeof(ring->name), "gfx"); |
2020 | /* no gfx doorbells on iceland */ |
2021 | if (adev->asic_type != CHIP_TOPAZ) { |
2022 | ring->use_doorbell = true1; |
2023 | ring->doorbell_index = adev->doorbell_index.gfx_ring0; |
2024 | } |
2025 | |
2026 | r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, |
2027 | AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP, |
2028 | AMDGPU_RING_PRIO_DEFAULT1); |
2029 | if (r) |
2030 | return r; |
2031 | } |
2032 | |
2033 | |
2034 | /* set up the compute queues - allocate horizontally across pipes */ |
2035 | ring_id = 0; |
2036 | for (i = 0; i < adev->gfx.mec.num_mec; ++i) { |
2037 | for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { |
2038 | for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { |
2039 | if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) |
2040 | continue; |
2041 | |
2042 | r = gfx_v8_0_compute_ring_init(adev, |
2043 | ring_id, |
2044 | i, k, j); |
2045 | if (r) |
2046 | return r; |
2047 | |
2048 | ring_id++; |
2049 | } |
2050 | } |
2051 | } |
2052 | |
2053 | r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE4096); |
2054 | if (r) { |
2055 | DRM_ERROR("Failed to init KIQ BOs!\n")__drm_err("Failed to init KIQ BOs!\n"); |
2056 | return r; |
2057 | } |
2058 | |
2059 | kiq = &adev->gfx.kiq; |
2060 | r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); |
2061 | if (r) |
2062 | return r; |
2063 | |
2064 | /* create MQD for all compute queues as well as KIQ for SRIOV case */ |
2065 | r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation)); |
2066 | if (r) |
2067 | return r; |
2068 | |
2069 | adev->gfx.ce_ram_size = 0x8000; |
2070 | |
2071 | r = gfx_v8_0_gpu_early_init(adev); |
2072 | if (r) |
2073 | return r; |
2074 | |
2075 | return 0; |
2076 | } |
2077 | |
2078 | static int gfx_v8_0_sw_fini(void *handle) |
2079 | { |
2080 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
2081 | int i; |
2082 | |
2083 | for (i = 0; i < adev->gfx.num_gfx_rings; i++) |
2084 | amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); |
2085 | for (i = 0; i < adev->gfx.num_compute_rings; i++) |
2086 | amdgpu_ring_fini(&adev->gfx.compute_ring[i]); |
2087 | |
2088 | amdgpu_gfx_mqd_sw_fini(adev); |
2089 | amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); |
2090 | amdgpu_gfx_kiq_fini(adev); |
2091 | |
2092 | gfx_v8_0_mec_fini(adev); |
2093 | amdgpu_gfx_rlc_fini(adev); |
2094 | amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, |
2095 | &adev->gfx.rlc.clear_state_gpu_addr, |
2096 | (void **)&adev->gfx.rlc.cs_ptr); |
2097 | if ((adev->asic_type == CHIP_CARRIZO) || |
2098 | (adev->asic_type == CHIP_STONEY)) { |
2099 | amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, |
2100 | &adev->gfx.rlc.cp_table_gpu_addr, |
2101 | (void **)&adev->gfx.rlc.cp_table_ptr); |
2102 | } |
2103 | gfx_v8_0_free_microcode(adev); |
2104 | |
2105 | return 0; |
2106 | } |
2107 | |
2108 | static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) |
2109 | { |
2110 | uint32_t *modearray, *mod2array; |
2111 | const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array)(sizeof((adev->gfx.config.tile_mode_array)) / sizeof((adev ->gfx.config.tile_mode_array)[0])); |
2112 | const u32 num_secondary_tile_mode_states = ARRAY_SIZE(adev->gfx.config.macrotile_mode_array)(sizeof((adev->gfx.config.macrotile_mode_array)) / sizeof( (adev->gfx.config.macrotile_mode_array)[0])); |
2113 | u32 reg_offset; |
2114 | |
2115 | modearray = adev->gfx.config.tile_mode_array; |
2116 | mod2array = adev->gfx.config.macrotile_mode_array; |
2117 | |
2118 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
2119 | modearray[reg_offset] = 0; |
2120 | |
2121 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
2122 | mod2array[reg_offset] = 0; |
2123 | |
2124 | switch (adev->asic_type) { |
2125 | case CHIP_TOPAZ: |
2126 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2127 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2128 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
2129 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2130 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2131 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2132 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
2133 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2134 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2135 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2136 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
2137 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2138 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2139 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2140 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
2141 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2142 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2143 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2144 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2145 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2146 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2147 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2148 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2149 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2150 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2151 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2152 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2153 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2154 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
2155 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6)); |
2156 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2157 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2158 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2159 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2160 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2161 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2162 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2163 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2164 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2165 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2166 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2167 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2168 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2169 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2170 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2171 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2172 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2173 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2174 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2175 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2176 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
2177 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2178 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2179 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2180 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2181 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2182 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2183 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2184 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2185 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2186 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2187 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2188 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2189 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2190 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2191 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2192 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2193 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2194 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2195 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2196 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
2197 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2198 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2199 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2200 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2201 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2202 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2203 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2204 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2205 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2206 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2207 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2208 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
2209 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2210 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2211 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2212 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
2213 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2214 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2215 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2216 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2217 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2218 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2219 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2220 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2221 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2222 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2223 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2224 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2225 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
2226 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2227 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2228 | |
2229 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
2230 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2231 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2232 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2233 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
2234 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2235 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2236 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2237 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
2238 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2239 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2240 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2241 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2242 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2243 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2244 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2245 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2246 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2247 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2248 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2249 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2250 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2251 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2252 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2253 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2254 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2255 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2256 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2257 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
2258 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
2259 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2260 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2261 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
2262 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2263 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2264 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2265 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
2266 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2267 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2268 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2269 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
2270 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2271 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2272 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2273 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2274 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2275 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2276 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2277 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2278 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2279 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2280 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2281 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2282 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2283 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2284 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2285 | |
2286 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
2287 | if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && |
2288 | reg_offset != 23) |
2289 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
2290 | |
2291 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
2292 | if (reg_offset != 7) |
2293 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
2294 | |
2295 | break; |
2296 | case CHIP_FIJI: |
2297 | case CHIP_VEGAM: |
2298 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2299 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2300 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
2301 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2302 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2303 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2304 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
2305 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2306 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2307 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2308 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
2309 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2310 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2311 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2312 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
2313 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2314 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2315 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2316 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2317 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2318 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2319 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2320 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2321 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2322 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2323 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2324 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2325 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2326 | modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2327 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2328 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2329 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2330 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
2331 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6)); |
2332 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2333 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2334 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2335 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2336 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2337 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2338 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2339 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2340 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2341 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2342 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2343 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2344 | modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2345 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2346 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2347 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2348 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2349 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2350 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2351 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2352 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2353 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2354 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2355 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2356 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
2357 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2358 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2359 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2360 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2361 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2362 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2363 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2364 | modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2365 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2366 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2367 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2368 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2369 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2370 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2371 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2372 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2373 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2374 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2375 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2376 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2377 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2378 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2379 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2380 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
2381 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2382 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2383 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2384 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2385 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2386 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2387 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2388 | modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2389 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2390 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2391 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2392 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2393 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2394 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2395 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2396 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
2397 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2398 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2399 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2400 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
2401 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2402 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2403 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2404 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2405 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2406 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2407 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2408 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2409 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2410 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2411 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2412 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2413 | PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16)((ADDR_SURF_P16_32x32_16x16) << 0x6) | |
2414 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2415 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2416 | modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2417 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2418 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2419 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2420 | |
2421 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2422 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2423 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2424 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2425 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2426 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2427 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2428 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2429 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2430 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2431 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2432 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2433 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2434 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2435 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2436 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2437 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2438 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2439 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2440 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2441 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2442 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2443 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2444 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2445 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2446 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2447 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2448 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2449 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2450 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
2451 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2452 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2453 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2454 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2455 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2456 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2457 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2458 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2459 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2460 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2461 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2462 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2463 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2464 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2465 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2466 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2467 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2468 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2469 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2470 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2471 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2472 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2473 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2474 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2475 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2476 | NUM_BANKS(ADDR_SURF_4_BANK)((ADDR_SURF_4_BANK) << 0x6)); |
2477 | |
2478 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
2479 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
2480 | |
2481 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
2482 | if (reg_offset != 7) |
2483 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
2484 | |
2485 | break; |
2486 | case CHIP_TONGA: |
2487 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2488 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2489 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
2490 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2491 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2492 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2493 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
2494 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2495 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2496 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2497 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
2498 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2499 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2500 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2501 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
2502 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2503 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2504 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2505 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2506 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2507 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2508 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2509 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2510 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2511 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2512 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2513 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2514 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2515 | modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2516 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2517 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2518 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2519 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
2520 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6)); |
2521 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2522 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2523 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2524 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2525 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2526 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2527 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2528 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2529 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2530 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2531 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2532 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2533 | modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2534 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2535 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2536 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2537 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2538 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2539 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2540 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2541 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2542 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2543 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2544 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2545 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
2546 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2547 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2548 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2549 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2550 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2551 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2552 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2553 | modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2554 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2555 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2556 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2557 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2558 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2559 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2560 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2561 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2562 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2563 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2564 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2565 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2566 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2567 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2568 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2569 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
2570 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2571 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2572 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2573 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2574 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2575 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2576 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2577 | modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2578 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2579 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2580 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2581 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2582 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2583 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2584 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2585 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
2586 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2587 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2588 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2589 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
2590 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2591 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2592 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2593 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2594 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2595 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2596 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2597 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2598 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2599 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2600 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2601 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2602 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2603 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2604 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2605 | modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2606 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2607 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2608 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2609 | |
2610 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2611 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2612 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2613 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2614 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2615 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2616 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2617 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2618 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2619 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2620 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2621 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2622 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2623 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2624 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2625 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2626 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2627 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2628 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2629 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2630 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2631 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2632 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2633 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2634 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2635 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2636 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2637 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2638 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2639 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
2640 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2641 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2642 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2643 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2644 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2645 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2646 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2647 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2648 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2649 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2650 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2651 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2652 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2653 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2654 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2655 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2656 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2657 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2658 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2659 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2660 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2661 | NUM_BANKS(ADDR_SURF_4_BANK)((ADDR_SURF_4_BANK) << 0x6)); |
2662 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2663 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2664 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2665 | NUM_BANKS(ADDR_SURF_4_BANK)((ADDR_SURF_4_BANK) << 0x6)); |
2666 | |
2667 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
2668 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
2669 | |
2670 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
2671 | if (reg_offset != 7) |
2672 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
2673 | |
2674 | break; |
2675 | case CHIP_POLARIS11: |
2676 | case CHIP_POLARIS12: |
2677 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2678 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2679 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
2680 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2681 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2682 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2683 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
2684 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2685 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2686 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2687 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
2688 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2689 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2690 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2691 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
2692 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2693 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2694 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2695 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2696 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2697 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2698 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2699 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2700 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2701 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2702 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2703 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2704 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2705 | modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2706 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2707 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2708 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2709 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
2710 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6)); |
2711 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2712 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2713 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2714 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2715 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2716 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2717 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2718 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2719 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2720 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2721 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2722 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2723 | modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2724 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2725 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2726 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2727 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2728 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2729 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2730 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2731 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2732 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2733 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2734 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2735 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
2736 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2737 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2738 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2739 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2740 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2741 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2742 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2743 | modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2744 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2745 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2746 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2747 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2748 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2749 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2750 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2751 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2752 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2753 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2754 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2755 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2756 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2757 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2758 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2759 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
2760 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2761 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2762 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2763 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2764 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2765 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2766 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2767 | modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2768 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2769 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2770 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2771 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2772 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2773 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2774 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2775 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
2776 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2777 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2778 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2779 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
2780 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2781 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2782 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2783 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2784 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2785 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2786 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2787 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2788 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2789 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2790 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2791 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2792 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2793 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2794 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2795 | modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2796 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2797 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2798 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2799 | |
2800 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2801 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2802 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2803 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2804 | |
2805 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2806 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2807 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2808 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2809 | |
2810 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2811 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2812 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2813 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2814 | |
2815 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2816 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2817 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2818 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2819 | |
2820 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2821 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2822 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2823 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2824 | |
2825 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2826 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2827 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2828 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2829 | |
2830 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2831 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2832 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2833 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2834 | |
2835 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
2836 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
2837 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2838 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2839 | |
2840 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
2841 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2842 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2843 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2844 | |
2845 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2846 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
2847 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2848 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2849 | |
2850 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2851 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
2852 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
2853 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2854 | |
2855 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2856 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2857 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2858 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
2859 | |
2860 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2861 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2862 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
2863 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
2864 | |
2865 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
2866 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
2867 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
2868 | NUM_BANKS(ADDR_SURF_4_BANK)((ADDR_SURF_4_BANK) << 0x6)); |
2869 | |
2870 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
2871 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
2872 | |
2873 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
2874 | if (reg_offset != 7) |
2875 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
2876 | |
2877 | break; |
2878 | case CHIP_POLARIS10: |
2879 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2880 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2881 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
2882 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2883 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2884 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2885 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
2886 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2887 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2888 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2889 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
2890 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2891 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2892 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2893 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
2894 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2895 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2896 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2897 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2898 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2899 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2900 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2901 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2902 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2903 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2904 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2905 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2906 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2907 | modearray[7] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2908 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2909 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
2910 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
2911 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
2912 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6)); |
2913 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2914 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2915 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2916 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2917 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2918 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2919 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2920 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2921 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2922 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2923 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2924 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2925 | modearray[12] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2926 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2927 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
2928 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2929 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2930 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2931 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2932 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2933 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2934 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2935 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2936 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2937 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
2938 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2939 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2940 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2941 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2942 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2943 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2944 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2945 | modearray[17] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2946 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2947 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2948 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2949 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2950 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2951 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2952 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2953 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
2954 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2955 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2956 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2957 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2958 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2959 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2960 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2961 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
2962 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2963 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2964 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2965 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2966 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2967 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2968 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2969 | modearray[23] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
2970 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2971 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2972 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2973 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
2974 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2975 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
2976 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2977 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
2978 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2979 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2980 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2981 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
2982 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2983 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
2984 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
2985 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
2986 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2987 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2988 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2989 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
2990 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2991 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2992 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
2993 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2994 | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16)((ADDR_SURF_P8_32x32_16x16) << 0x6) | |
2995 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
2996 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
2997 | modearray[30] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
2998 | PIPE_CONFIG(ADDR_SURF_P4_16x16)((ADDR_SURF_P4_16x16) << 0x6) | |
2999 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3000 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3001 | |
3002 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3003 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3004 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3005 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3006 | |
3007 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3008 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3009 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3010 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3011 | |
3012 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3013 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3014 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3015 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3016 | |
3017 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3018 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3019 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3020 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3021 | |
3022 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3023 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3024 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3025 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3026 | |
3027 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3028 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3029 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
3030 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3031 | |
3032 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3033 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3034 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
3035 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3036 | |
3037 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3038 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
3039 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3040 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3041 | |
3042 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3043 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3044 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3045 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3046 | |
3047 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3048 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3049 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3050 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3051 | |
3052 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3053 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3054 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3055 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3056 | |
3057 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3058 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3059 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
3060 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3061 | |
3062 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3063 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3064 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
3065 | NUM_BANKS(ADDR_SURF_4_BANK)((ADDR_SURF_4_BANK) << 0x6)); |
3066 | |
3067 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3068 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3069 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1)((ADDR_SURF_MACRO_ASPECT_1) << 0x4) | |
3070 | NUM_BANKS(ADDR_SURF_4_BANK)((ADDR_SURF_4_BANK) << 0x6)); |
3071 | |
3072 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
3073 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
3074 | |
3075 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
3076 | if (reg_offset != 7) |
3077 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
3078 | |
3079 | break; |
3080 | case CHIP_STONEY: |
3081 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3082 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3083 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
3084 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3085 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3086 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3087 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
3088 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3089 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3090 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3091 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
3092 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3093 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3094 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3095 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
3096 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3097 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3098 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3099 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
3100 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3101 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3102 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3103 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
3104 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3105 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3106 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3107 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
3108 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3109 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
3110 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6)); |
3111 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3112 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3113 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
3114 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3115 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3116 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3117 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
3118 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3119 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3120 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3121 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
3122 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3123 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3124 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3125 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3126 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3127 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3128 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3129 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3130 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3131 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
3132 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3133 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3134 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3135 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3136 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3137 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3138 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3139 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
3140 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3141 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3142 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3143 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
3144 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3145 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3146 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3147 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
3148 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3149 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3150 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3151 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
3152 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3153 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3154 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3155 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
3156 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3157 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3158 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3159 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
3160 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3161 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3162 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3163 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
3164 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3165 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3166 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3167 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
3168 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3169 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3170 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3171 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3172 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3173 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3174 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3175 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3176 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3177 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3178 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3179 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3180 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3181 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3182 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3183 | |
3184 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3185 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3186 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3187 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3188 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3189 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3190 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3191 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3192 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3193 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3194 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3195 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3196 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3197 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3198 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3199 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3200 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3201 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3202 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3203 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3204 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3205 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3206 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3207 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3208 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3209 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3210 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3211 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3212 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
3213 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
3214 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3215 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3216 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
3217 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3218 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3219 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3220 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
3221 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3222 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3223 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3224 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
3225 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3226 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3227 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3228 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3229 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3230 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3231 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3232 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3233 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3234 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3235 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3236 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3237 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3238 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3239 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3240 | |
3241 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
3242 | if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && |
3243 | reg_offset != 23) |
3244 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
3245 | |
3246 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
3247 | if (reg_offset != 7) |
3248 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
3249 | |
3250 | break; |
3251 | default: |
3252 | dev_warn(adev->dev,printf("drm:pid%d:%s *WARNING* " "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> asic_type) |
3253 | "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n",printf("drm:pid%d:%s *WARNING* " "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> asic_type) |
3254 | adev->asic_type)printf("drm:pid%d:%s *WARNING* " "Unknown chip type (%d) in function gfx_v8_0_tiling_mode_table_init() falling through to CHIP_CARRIZO\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> asic_type); |
3255 | fallthroughdo {} while (0); |
3256 | |
3257 | case CHIP_CARRIZO: |
3258 | modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3259 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3260 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)((ADDR_SURF_TILE_SPLIT_64B) << 0xb) | |
3261 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3262 | modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3263 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3264 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B)((ADDR_SURF_TILE_SPLIT_128B) << 0xb) | |
3265 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3266 | modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3267 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3268 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B)((ADDR_SURF_TILE_SPLIT_256B) << 0xb) | |
3269 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3270 | modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3271 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3272 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B)((ADDR_SURF_TILE_SPLIT_512B) << 0xb) | |
3273 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3274 | modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3275 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3276 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
3277 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3278 | modearray[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3279 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3280 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
3281 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3282 | modearray[6] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3283 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3284 | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB)((ADDR_SURF_TILE_SPLIT_2KB) << 0xb) | |
3285 | MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)((ADDR_SURF_DEPTH_MICRO_TILING) << 0x16)); |
3286 | modearray[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED)((ARRAY_LINEAR_ALIGNED) << 0x2) | |
3287 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6)); |
3288 | modearray[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3289 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3290 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
3291 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3292 | modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3293 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3294 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
3295 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3296 | modearray[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3297 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3298 | MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)((ADDR_SURF_DISPLAY_MICRO_TILING) << 0x16) | |
3299 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3300 | modearray[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3301 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3302 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3303 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3304 | modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3305 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3306 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3307 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3308 | modearray[15] = (ARRAY_MODE(ARRAY_3D_TILED_THIN1)((ARRAY_3D_TILED_THIN1) << 0x2) | |
3309 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3310 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3311 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3312 | modearray[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3313 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3314 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3315 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3316 | modearray[18] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
3317 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3318 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3319 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3320 | modearray[19] = (ARRAY_MODE(ARRAY_1D_TILED_THICK)((ARRAY_1D_TILED_THICK) << 0x2) | |
3321 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3322 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3323 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3324 | modearray[20] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
3325 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3326 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3327 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3328 | modearray[21] = (ARRAY_MODE(ARRAY_3D_TILED_THICK)((ARRAY_3D_TILED_THICK) << 0x2) | |
3329 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3330 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3331 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3332 | modearray[22] = (ARRAY_MODE(ARRAY_PRT_TILED_THICK)((ARRAY_PRT_TILED_THICK) << 0x2) | |
3333 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3334 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3335 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3336 | modearray[24] = (ARRAY_MODE(ARRAY_2D_TILED_THICK)((ARRAY_2D_TILED_THICK) << 0x2) | |
3337 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3338 | MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)((ADDR_SURF_THIN_MICRO_TILING) << 0x16) | |
3339 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3340 | modearray[25] = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK)((ARRAY_2D_TILED_XTHICK) << 0x2) | |
3341 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3342 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3343 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3344 | modearray[26] = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK)((ARRAY_3D_TILED_XTHICK) << 0x2) | |
3345 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3346 | MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING)((ADDR_SURF_THICK_MICRO_TILING) << 0x16) | |
3347 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)((ADDR_SURF_SAMPLE_SPLIT_1) << 0x19)); |
3348 | modearray[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1)((ARRAY_1D_TILED_THIN1) << 0x2) | |
3349 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3350 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3351 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3352 | modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1)((ARRAY_2D_TILED_THIN1) << 0x2) | |
3353 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3354 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3355 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)((ADDR_SURF_SAMPLE_SPLIT_2) << 0x19)); |
3356 | modearray[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1)((ARRAY_PRT_TILED_THIN1) << 0x2) | |
3357 | PIPE_CONFIG(ADDR_SURF_P2)((ADDR_SURF_P2) << 0x6) | |
3358 | MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)((ADDR_SURF_ROTATED_MICRO_TILING) << 0x16) | |
3359 | SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)((ADDR_SURF_SAMPLE_SPLIT_8) << 0x19)); |
3360 | |
3361 | mod2array[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3362 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3363 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3364 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3365 | mod2array[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3366 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3367 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3368 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3369 | mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3370 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3371 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3372 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3373 | mod2array[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3374 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3375 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3376 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3377 | mod2array[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3378 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3379 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3380 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3381 | mod2array[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3382 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3383 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3384 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3385 | mod2array[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3386 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3387 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3388 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3389 | mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
3390 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8)((ADDR_SURF_BANK_HEIGHT_8) << 0x2) | |
3391 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3392 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3393 | mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4)((ADDR_SURF_BANK_WIDTH_4) << 0x0) | |
3394 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3395 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3396 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3397 | mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
3398 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4)((ADDR_SURF_BANK_HEIGHT_4) << 0x2) | |
3399 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3400 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3401 | mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2)((ADDR_SURF_BANK_WIDTH_2) << 0x0) | |
3402 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3403 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3404 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3405 | mod2array[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3406 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2)((ADDR_SURF_BANK_HEIGHT_2) << 0x2) | |
3407 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3408 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3409 | mod2array[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3410 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3411 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4)((ADDR_SURF_MACRO_ASPECT_4) << 0x4) | |
3412 | NUM_BANKS(ADDR_SURF_16_BANK)((ADDR_SURF_16_BANK) << 0x6)); |
3413 | mod2array[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1)((ADDR_SURF_BANK_WIDTH_1) << 0x0) | |
3414 | BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1)((ADDR_SURF_BANK_HEIGHT_1) << 0x2) | |
3415 | MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2)((ADDR_SURF_MACRO_ASPECT_2) << 0x4) | |
3416 | NUM_BANKS(ADDR_SURF_8_BANK)((ADDR_SURF_8_BANK) << 0x6)); |
3417 | |
3418 | for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) |
3419 | if (reg_offset != 7 && reg_offset != 12 && reg_offset != 17 && |
3420 | reg_offset != 23) |
3421 | WREG32(mmGB_TILE_MODE0 + reg_offset, modearray[reg_offset])amdgpu_device_wreg(adev, (0x2644 + reg_offset), (modearray[reg_offset ]), 0); |
3422 | |
3423 | for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) |
3424 | if (reg_offset != 7) |
3425 | WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset])amdgpu_device_wreg(adev, (0x2664 + reg_offset), (mod2array[reg_offset ]), 0); |
3426 | |
3427 | break; |
3428 | } |
3429 | } |
3430 | |
3431 | static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, |
3432 | u32 se_num, u32 sh_num, u32 instance) |
3433 | { |
3434 | u32 data; |
3435 | |
3436 | if (instance == 0xffffffff) |
3437 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1)(((0) & ~0x40000000) | (0x40000000 & ((1) << 0x1e ))); |
3438 | else |
3439 | data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance)(((0) & ~0xff) | (0xff & ((instance) << 0x0))); |
3440 | |
3441 | if (se_num == 0xffffffff) |
3442 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1)(((data) & ~0x80000000) | (0x80000000 & ((1) << 0x1f))); |
3443 | else |
3444 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num)(((data) & ~0xff0000) | (0xff0000 & ((se_num) << 0x10))); |
3445 | |
3446 | if (sh_num == 0xffffffff) |
3447 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1)(((data) & ~0x20000000) | (0x20000000 & ((1) << 0x1d))); |
3448 | else |
3449 | data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num)(((data) & ~0xff00) | (0xff00 & ((sh_num) << 0x8 ))); |
3450 | |
3451 | WREG32(mmGRBM_GFX_INDEX, data)amdgpu_device_wreg(adev, (0xc200), (data), 0); |
3452 | } |
3453 | |
3454 | static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev, |
3455 | u32 me, u32 pipe, u32 q, u32 vm) |
3456 | { |
3457 | vi_srbm_select(adev, me, pipe, q, vm); |
3458 | } |
3459 | |
3460 | static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev) |
3461 | { |
3462 | u32 data, mask; |
3463 | |
3464 | data = RREG32(mmCC_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (0x263d), 0) | |
3465 | RREG32(mmGC_USER_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (0x26df), 0); |
3466 | |
3467 | data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE)(((data) & 0xff0000) >> 0x10); |
3468 | |
3469 | mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / |
3470 | adev->gfx.config.max_sh_per_se); |
3471 | |
3472 | return (~data) & mask; |
3473 | } |
3474 | |
3475 | static void |
3476 | gfx_v8_0_raster_config(struct amdgpu_device *adev, u32 *rconf, u32 *rconf1) |
3477 | { |
3478 | switch (adev->asic_type) { |
3479 | case CHIP_FIJI: |
3480 | case CHIP_VEGAM: |
3481 | *rconf |= RB_MAP_PKR0(2)((2) << 0) | RB_MAP_PKR1(2)((2) << 2) | |
3482 | RB_XSEL2(1)((1) << 4) | PKR_MAP(2)((2) << 8) | |
3483 | PKR_XSEL(1)((1) << 10) | PKR_YSEL(1)((1) << 12) | |
3484 | SE_MAP(2)((2) << 24) | SE_XSEL(2)((2) << 26) | SE_YSEL(3)((3) << 28); |
3485 | *rconf1 |= SE_PAIR_MAP(2)((2) << 0) | SE_PAIR_XSEL(3)((3) << 2) | |
3486 | SE_PAIR_YSEL(2)((2) << 4); |
3487 | break; |
3488 | case CHIP_TONGA: |
3489 | case CHIP_POLARIS10: |
3490 | *rconf |= RB_MAP_PKR0(2)((2) << 0) | RB_XSEL2(1)((1) << 4) | SE_MAP(2)((2) << 24) | |
3491 | SE_XSEL(1)((1) << 26) | SE_YSEL(1)((1) << 28); |
3492 | *rconf1 |= SE_PAIR_MAP(2)((2) << 0) | SE_PAIR_XSEL(2)((2) << 2) | |
3493 | SE_PAIR_YSEL(2)((2) << 4); |
3494 | break; |
3495 | case CHIP_TOPAZ: |
3496 | case CHIP_CARRIZO: |
3497 | *rconf |= RB_MAP_PKR0(2)((2) << 0); |
3498 | *rconf1 |= 0x0; |
3499 | break; |
3500 | case CHIP_POLARIS11: |
3501 | case CHIP_POLARIS12: |
3502 | *rconf |= RB_MAP_PKR0(2)((2) << 0) | RB_XSEL2(1)((1) << 4) | SE_MAP(2)((2) << 24) | |
3503 | SE_XSEL(1)((1) << 26) | SE_YSEL(1)((1) << 28); |
3504 | *rconf1 |= 0x0; |
3505 | break; |
3506 | case CHIP_STONEY: |
3507 | *rconf |= 0x0; |
3508 | *rconf1 |= 0x0; |
3509 | break; |
3510 | default: |
3511 | DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type)__drm_err("unknown asic: 0x%x\n", adev->asic_type); |
3512 | break; |
3513 | } |
3514 | } |
3515 | |
3516 | static void |
3517 | gfx_v8_0_write_harvested_raster_configs(struct amdgpu_device *adev, |
3518 | u32 raster_config, u32 raster_config_1, |
3519 | unsigned rb_mask, unsigned num_rb) |
3520 | { |
3521 | unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1)({ unsigned __max_a = (adev->gfx.config.max_sh_per_se); unsigned __max_b = (1); __max_a > __max_b ? __max_a : __max_b; }); |
3522 | unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1)({ unsigned __max_a = (adev->gfx.config.max_shader_engines ); unsigned __max_b = (1); __max_a > __max_b ? __max_a : __max_b ; }); |
3523 | unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2)({ unsigned __min_a = (num_rb / num_se / sh_per_se); unsigned __min_b = (2); __min_a < __min_b ? __min_a : __min_b; }); |
3524 | unsigned rb_per_se = num_rb / num_se; |
3525 | unsigned se_mask[4]; |
3526 | unsigned se; |
3527 | |
3528 | se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; |
3529 | se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; |
3530 | se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; |
3531 | se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; |
3532 | |
3533 | WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4))({ int __ret = !!(!(num_se == 1 || num_se == 2 || num_se == 4 )); if (__ret) printf("WARNING %s failed at %s:%d\n", "!(num_se == 1 || num_se == 2 || num_se == 4)" , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c", 3533); __builtin_expect (!!(__ret), 0); }); |
3534 | WARN_ON(!(sh_per_se == 1 || sh_per_se == 2))({ int __ret = !!(!(sh_per_se == 1 || sh_per_se == 2)); if (__ret ) printf("WARNING %s failed at %s:%d\n", "!(sh_per_se == 1 || sh_per_se == 2)" , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c", 3534); __builtin_expect (!!(__ret), 0); }); |
3535 | WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2))({ int __ret = !!(!(rb_per_pkr == 1 || rb_per_pkr == 2)); if ( __ret) printf("WARNING %s failed at %s:%d\n", "!(rb_per_pkr == 1 || rb_per_pkr == 2)" , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c", 3535); __builtin_expect (!!(__ret), 0); }); |
3536 | |
3537 | if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || |
3538 | (!se_mask[2] && !se_mask[3]))) { |
3539 | raster_config_1 &= ~SE_PAIR_MAP_MASK(0x3 << 0); |
3540 | |
3541 | if (!se_mask[0] && !se_mask[1]) { |
3542 | raster_config_1 |= |
3543 | SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_3)((RASTER_CONFIG_SE_PAIR_MAP_3) << 0); |
3544 | } else { |
3545 | raster_config_1 |= |
3546 | SE_PAIR_MAP(RASTER_CONFIG_SE_PAIR_MAP_0)((RASTER_CONFIG_SE_PAIR_MAP_0) << 0); |
3547 | } |
3548 | } |
3549 | |
3550 | for (se = 0; se < num_se; se++) { |
3551 | unsigned raster_config_se = raster_config; |
3552 | unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se); |
3553 | unsigned pkr1_mask = pkr0_mask << rb_per_pkr; |
3554 | int idx = (se / 2) * 2; |
3555 | |
3556 | if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { |
3557 | raster_config_se &= ~SE_MAP_MASK(0x3 << 24); |
3558 | |
3559 | if (!se_mask[idx]) { |
3560 | raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_3)((RASTER_CONFIG_SE_MAP_3) << 24); |
3561 | } else { |
3562 | raster_config_se |= SE_MAP(RASTER_CONFIG_SE_MAP_0)((RASTER_CONFIG_SE_MAP_0) << 24); |
3563 | } |
3564 | } |
3565 | |
3566 | pkr0_mask &= rb_mask; |
3567 | pkr1_mask &= rb_mask; |
3568 | if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) { |
3569 | raster_config_se &= ~PKR_MAP_MASK(0x3 << 8); |
3570 | |
3571 | if (!pkr0_mask) { |
3572 | raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_3)((RASTER_CONFIG_PKR_MAP_3) << 8); |
3573 | } else { |
3574 | raster_config_se |= PKR_MAP(RASTER_CONFIG_PKR_MAP_0)((RASTER_CONFIG_PKR_MAP_0) << 8); |
3575 | } |
3576 | } |
3577 | |
3578 | if (rb_per_se >= 2) { |
3579 | unsigned rb0_mask = 1 << (se * rb_per_se); |
3580 | unsigned rb1_mask = rb0_mask << 1; |
3581 | |
3582 | rb0_mask &= rb_mask; |
3583 | rb1_mask &= rb_mask; |
3584 | if (!rb0_mask || !rb1_mask) { |
3585 | raster_config_se &= ~RB_MAP_PKR0_MASK(0x3 << 0); |
3586 | |
3587 | if (!rb0_mask) { |
3588 | raster_config_se |= |
3589 | RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_3)((RASTER_CONFIG_RB_MAP_3) << 0); |
3590 | } else { |
3591 | raster_config_se |= |
3592 | RB_MAP_PKR0(RASTER_CONFIG_RB_MAP_0)((RASTER_CONFIG_RB_MAP_0) << 0); |
3593 | } |
3594 | } |
3595 | |
3596 | if (rb_per_se > 2) { |
3597 | rb0_mask = 1 << (se * rb_per_se + rb_per_pkr); |
3598 | rb1_mask = rb0_mask << 1; |
3599 | rb0_mask &= rb_mask; |
3600 | rb1_mask &= rb_mask; |
3601 | if (!rb0_mask || !rb1_mask) { |
3602 | raster_config_se &= ~RB_MAP_PKR1_MASK(0x3 << 2); |
3603 | |
3604 | if (!rb0_mask) { |
3605 | raster_config_se |= |
3606 | RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_3)((RASTER_CONFIG_RB_MAP_3) << 2); |
3607 | } else { |
3608 | raster_config_se |= |
3609 | RB_MAP_PKR1(RASTER_CONFIG_RB_MAP_0)((RASTER_CONFIG_RB_MAP_0) << 2); |
3610 | } |
3611 | } |
3612 | } |
3613 | } |
3614 | |
3615 | /* GRBM_GFX_INDEX has a different offset on VI */ |
3616 | gfx_v8_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff); |
3617 | WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se)amdgpu_device_wreg(adev, (0xa0d4), (raster_config_se), 0); |
3618 | WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1)amdgpu_device_wreg(adev, (0xa0d5), (raster_config_1), 0); |
3619 | } |
3620 | |
3621 | /* GRBM_GFX_INDEX has a different offset on VI */ |
3622 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
3623 | } |
3624 | |
3625 | static void gfx_v8_0_setup_rb(struct amdgpu_device *adev) |
3626 | { |
3627 | int i, j; |
3628 | u32 data; |
3629 | u32 raster_config = 0, raster_config_1 = 0; |
3630 | u32 active_rbs = 0; |
3631 | u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / |
3632 | adev->gfx.config.max_sh_per_se; |
3633 | unsigned num_rb_pipes; |
3634 | |
3635 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
3636 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
3637 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
3638 | gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); |
3639 | data = gfx_v8_0_get_rb_active_bitmap(adev); |
3640 | active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * |
3641 | rb_bitmap_width_per_sh); |
3642 | } |
3643 | } |
3644 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
3645 | |
3646 | adev->gfx.config.backend_enable_mask = active_rbs; |
3647 | adev->gfx.config.num_rbs = hweight32(active_rbs); |
3648 | |
3649 | num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *({ unsigned __min_a = (adev->gfx.config.max_backends_per_se * adev->gfx.config.max_shader_engines); unsigned __min_b = (16); __min_a < __min_b ? __min_a : __min_b; }) |
3650 | adev->gfx.config.max_shader_engines, 16)({ unsigned __min_a = (adev->gfx.config.max_backends_per_se * adev->gfx.config.max_shader_engines); unsigned __min_b = (16); __min_a < __min_b ? __min_a : __min_b; }); |
3651 | |
3652 | gfx_v8_0_raster_config(adev, &raster_config, &raster_config_1); |
3653 | |
3654 | if (!adev->gfx.config.backend_enable_mask || |
3655 | adev->gfx.config.num_rbs >= num_rb_pipes) { |
3656 | WREG32(mmPA_SC_RASTER_CONFIG, raster_config)amdgpu_device_wreg(adev, (0xa0d4), (raster_config), 0); |
3657 | WREG32(mmPA_SC_RASTER_CONFIG_1, raster_config_1)amdgpu_device_wreg(adev, (0xa0d5), (raster_config_1), 0); |
3658 | } else { |
3659 | gfx_v8_0_write_harvested_raster_configs(adev, raster_config, raster_config_1, |
3660 | adev->gfx.config.backend_enable_mask, |
3661 | num_rb_pipes); |
3662 | } |
3663 | |
3664 | /* cache the values for userspace */ |
3665 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
3666 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
3667 | gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); |
3668 | adev->gfx.config.rb_config[i][j].rb_backend_disable = |
3669 | RREG32(mmCC_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (0x263d), 0); |
3670 | adev->gfx.config.rb_config[i][j].user_rb_backend_disable = |
3671 | RREG32(mmGC_USER_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (0x26df), 0); |
3672 | adev->gfx.config.rb_config[i][j].raster_config = |
3673 | RREG32(mmPA_SC_RASTER_CONFIG)amdgpu_device_rreg(adev, (0xa0d4), 0); |
3674 | adev->gfx.config.rb_config[i][j].raster_config_1 = |
3675 | RREG32(mmPA_SC_RASTER_CONFIG_1)amdgpu_device_rreg(adev, (0xa0d5), 0); |
3676 | } |
3677 | } |
3678 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
3679 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
3680 | } |
3681 | |
3682 | /** |
3683 | * gfx_v8_0_init_compute_vmid - gart enable |
3684 | * |
3685 | * @adev: amdgpu_device pointer |
3686 | * |
3687 | * Initialize compute vmid sh_mem registers |
3688 | * |
3689 | */ |
3690 | #define DEFAULT_SH_MEM_BASES(0x6000) (0x6000) |
3691 | static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) |
3692 | { |
3693 | int i; |
3694 | uint32_t sh_mem_config; |
3695 | uint32_t sh_mem_bases; |
3696 | |
3697 | /* |
3698 | * Configure apertures: |
3699 | * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) |
3700 | * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) |
3701 | * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) |
3702 | */ |
3703 | sh_mem_bases = DEFAULT_SH_MEM_BASES(0x6000) | (DEFAULT_SH_MEM_BASES(0x6000) << 16); |
3704 | |
3705 | sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 << |
3706 | SH_MEM_CONFIG__ADDRESS_MODE__SHIFT0x0 | |
3707 | SH_MEM_ALIGNMENT_MODE_UNALIGNED << |
3708 | SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT0x3 | |
3709 | MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT0x5 | |
3710 | SH_MEM_CONFIG__PRIVATE_ATC_MASK0x4; |
3711 | |
3712 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
3713 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) { |
3714 | vi_srbm_select(adev, 0, 0, 0, i); |
3715 | /* CP and shaders */ |
3716 | WREG32(mmSH_MEM_CONFIG, sh_mem_config)amdgpu_device_wreg(adev, (0x230d), (sh_mem_config), 0); |
3717 | WREG32(mmSH_MEM_APE1_BASE, 1)amdgpu_device_wreg(adev, (0x230b), (1), 0); |
3718 | WREG32(mmSH_MEM_APE1_LIMIT, 0)amdgpu_device_wreg(adev, (0x230c), (0), 0); |
3719 | WREG32(mmSH_MEM_BASES, sh_mem_bases)amdgpu_device_wreg(adev, (0x230a), (sh_mem_bases), 0); |
3720 | } |
3721 | vi_srbm_select(adev, 0, 0, 0, 0); |
3722 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
3723 | |
3724 | /* Initialize all compute VMIDs to have no GDS, GWS, or OA |
3725 | acccess. These should be enabled by FW for target VMIDs. */ |
3726 | for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) { |
3727 | WREG32(amdgpu_gds_reg_offset[i].mem_base, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[i].mem_base), (0), 0); |
3728 | WREG32(amdgpu_gds_reg_offset[i].mem_size, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[i].mem_size), (0), 0); |
3729 | WREG32(amdgpu_gds_reg_offset[i].gws, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[i].gws), (0), 0); |
3730 | WREG32(amdgpu_gds_reg_offset[i].oa, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[i].oa), (0), 0 ); |
3731 | } |
3732 | } |
3733 | |
3734 | static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev) |
3735 | { |
3736 | int vmid; |
3737 | |
3738 | /* |
3739 | * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA |
3740 | * access. Compute VMIDs should be enabled by FW for target VMIDs, |
3741 | * the driver can enable them for graphics. VMID0 should maintain |
3742 | * access so that HWS firmware can save/restore entries. |
3743 | */ |
3744 | for (vmid = 1; vmid < 16; vmid++) { |
3745 | WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[vmid].mem_base ), (0), 0); |
3746 | WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[vmid].mem_size ), (0), 0); |
3747 | WREG32(amdgpu_gds_reg_offset[vmid].gws, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[vmid].gws), ( 0), 0); |
3748 | WREG32(amdgpu_gds_reg_offset[vmid].oa, 0)amdgpu_device_wreg(adev, (amdgpu_gds_reg_offset[vmid].oa), (0 ), 0); |
3749 | } |
3750 | } |
3751 | |
3752 | static void gfx_v8_0_config_init(struct amdgpu_device *adev) |
3753 | { |
3754 | switch (adev->asic_type) { |
3755 | default: |
3756 | adev->gfx.config.double_offchip_lds_buf = 1; |
3757 | break; |
3758 | case CHIP_CARRIZO: |
3759 | case CHIP_STONEY: |
3760 | adev->gfx.config.double_offchip_lds_buf = 0; |
3761 | break; |
3762 | } |
3763 | } |
3764 | |
3765 | static void gfx_v8_0_constants_init(struct amdgpu_device *adev) |
3766 | { |
3767 | u32 tmp, sh_static_mem_cfg; |
3768 | int i; |
3769 | |
3770 | WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF)amdgpu_device_wreg(adev, (0x2000), ((amdgpu_device_rreg(adev, (0x2000), 0) & ~0xff) | (0xFF) << 0x0), 0); |
3771 | WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config)amdgpu_device_wreg(adev, (0x263e), (adev->gfx.config.gb_addr_config ), 0); |
3772 | WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config)amdgpu_device_wreg(adev, (0xbd2), (adev->gfx.config.gb_addr_config ), 0); |
3773 | WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config)amdgpu_device_wreg(adev, (0x303), (adev->gfx.config.gb_addr_config ), 0); |
3774 | |
3775 | gfx_v8_0_tiling_mode_table_init(adev); |
3776 | gfx_v8_0_setup_rb(adev); |
3777 | gfx_v8_0_get_cu_info(adev); |
3778 | gfx_v8_0_config_init(adev); |
3779 | |
3780 | /* XXX SH_MEM regs */ |
3781 | /* where to put LDS, scratch, GPUVM in FSA64 space */ |
3782 | sh_static_mem_cfg = REG_SET_FIELD(0, SH_STATIC_MEM_CONFIG,(((0) & ~0x1) | (0x1 & ((1) << 0x0))) |
3783 | SWIZZLE_ENABLE, 1)(((0) & ~0x1) | (0x1 & ((1) << 0x0))); |
3784 | sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,(((sh_static_mem_cfg) & ~0x6) | (0x6 & ((1) << 0x1 ))) |
3785 | ELEMENT_SIZE, 1)(((sh_static_mem_cfg) & ~0x6) | (0x6 & ((1) << 0x1 ))); |
3786 | sh_static_mem_cfg = REG_SET_FIELD(sh_static_mem_cfg, SH_STATIC_MEM_CONFIG,(((sh_static_mem_cfg) & ~0x18) | (0x18 & ((3) << 0x3))) |
3787 | INDEX_STRIDE, 3)(((sh_static_mem_cfg) & ~0x18) | (0x18 & ((3) << 0x3))); |
3788 | WREG32(mmSH_STATIC_MEM_CONFIG, sh_static_mem_cfg)amdgpu_device_wreg(adev, (0x2581), (sh_static_mem_cfg), 0); |
3789 | |
3790 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
3791 | for (i = 0; i < adev->vm_manager.id_mgr[0].num_ids; i++) { |
3792 | vi_srbm_select(adev, 0, 0, 0, i); |
3793 | /* CP and shaders */ |
3794 | if (i == 0) { |
3795 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC)(((0) & ~0xe0) | (0xe0 & ((MTYPE_UC) << 0x5))); |
3796 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC)(((tmp) & ~0x700) | (0x700 & ((MTYPE_UC) << 0x8 ))); |
3797 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,(((tmp) & ~0x18) | (0x18 & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))) |
3798 | SH_MEM_ALIGNMENT_MODE_UNALIGNED)(((tmp) & ~0x18) | (0x18 & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))); |
3799 | WREG32(mmSH_MEM_CONFIG, tmp)amdgpu_device_wreg(adev, (0x230d), (tmp), 0); |
3800 | WREG32(mmSH_MEM_BASES, 0)amdgpu_device_wreg(adev, (0x230a), (0), 0); |
3801 | } else { |
3802 | tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC)(((0) & ~0xe0) | (0xe0 & ((MTYPE_NC) << 0x5))); |
3803 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC)(((tmp) & ~0x700) | (0x700 & ((MTYPE_UC) << 0x8 ))); |
3804 | tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,(((tmp) & ~0x18) | (0x18 & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))) |
3805 | SH_MEM_ALIGNMENT_MODE_UNALIGNED)(((tmp) & ~0x18) | (0x18 & ((SH_MEM_ALIGNMENT_MODE_UNALIGNED ) << 0x3))); |
3806 | WREG32(mmSH_MEM_CONFIG, tmp)amdgpu_device_wreg(adev, (0x230d), (tmp), 0); |
3807 | tmp = adev->gmc.shared_aperture_start >> 48; |
3808 | WREG32(mmSH_MEM_BASES, tmp)amdgpu_device_wreg(adev, (0x230a), (tmp), 0); |
3809 | } |
3810 | |
3811 | WREG32(mmSH_MEM_APE1_BASE, 1)amdgpu_device_wreg(adev, (0x230b), (1), 0); |
3812 | WREG32(mmSH_MEM_APE1_LIMIT, 0)amdgpu_device_wreg(adev, (0x230c), (0), 0); |
3813 | } |
3814 | vi_srbm_select(adev, 0, 0, 0, 0); |
3815 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
3816 | |
3817 | gfx_v8_0_init_compute_vmid(adev); |
3818 | gfx_v8_0_init_gds_vmid(adev); |
3819 | |
3820 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
3821 | /* |
3822 | * making sure that the following register writes will be broadcasted |
3823 | * to all the shaders |
3824 | */ |
3825 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
3826 | |
3827 | WREG32(mmPA_SC_FIFO_SIZE,amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3828 | (adev->gfx.config.sc_prim_fifo_size_frontend <<amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3829 | PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3830 | (adev->gfx.config.sc_prim_fifo_size_backend <<amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3831 | PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3832 | (adev->gfx.config.sc_hiz_tile_fifo_size <<amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3833 | PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3834 | (adev->gfx.config.sc_earlyz_tile_fifo_size <<amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0) |
3835 | PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))amdgpu_device_wreg(adev, (0x22f3), ((adev->gfx.config.sc_prim_fifo_size_frontend << 0x0) | (adev->gfx.config.sc_prim_fifo_size_backend << 0x6) | (adev->gfx.config.sc_hiz_tile_fifo_size << 0xf) | (adev->gfx.config.sc_earlyz_tile_fifo_size << 0x17)), 0); |
3836 | |
3837 | tmp = RREG32(mmSPI_ARB_PRIORITY)amdgpu_device_rreg(adev, (0x31c0), 0); |
3838 | tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS0, 2)(((tmp) & ~0x7) | (0x7 & ((2) << 0x0))); |
3839 | tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS1, 2)(((tmp) & ~0x38) | (0x38 & ((2) << 0x3))); |
3840 | tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS2, 2)(((tmp) & ~0x1c0) | (0x1c0 & ((2) << 0x6))); |
3841 | tmp = REG_SET_FIELD(tmp, SPI_ARB_PRIORITY, PIPE_ORDER_TS3, 2)(((tmp) & ~0xe00) | (0xe00 & ((2) << 0x9))); |
3842 | WREG32(mmSPI_ARB_PRIORITY, tmp)amdgpu_device_wreg(adev, (0x31c0), (tmp), 0); |
3843 | |
3844 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
3845 | |
3846 | } |
3847 | |
3848 | static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev) |
3849 | { |
3850 | u32 i, j, k; |
3851 | u32 mask; |
3852 | |
3853 | mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex); |
3854 | for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { |
3855 | for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { |
3856 | gfx_v8_0_select_se_sh(adev, i, j, 0xffffffff); |
3857 | for (k = 0; k < adev->usec_timeout; k++) { |
3858 | if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY)amdgpu_device_rreg(adev, (0xec61), 0) == 0) |
3859 | break; |
3860 | udelay(1); |
3861 | } |
3862 | if (k == adev->usec_timeout) { |
3863 | gfx_v8_0_select_se_sh(adev, 0xffffffff, |
3864 | 0xffffffff, 0xffffffff); |
3865 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
3866 | DRM_INFO("Timeout wait for RLC serdes %u,%u\n",printk("\0016" "[" "drm" "] " "Timeout wait for RLC serdes %u,%u\n" , i, j) |
3867 | i, j)printk("\0016" "[" "drm" "] " "Timeout wait for RLC serdes %u,%u\n" , i, j); |
3868 | return; |
3869 | } |
3870 | } |
3871 | } |
3872 | gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); |
3873 | mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex); |
3874 | |
3875 | mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK0xffff | |
3876 | RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK0x10000 | |
3877 | RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK0x40000 | |
3878 | RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK0x80000; |
3879 | for (k = 0; k < adev->usec_timeout; k++) { |
3880 | if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY)amdgpu_device_rreg(adev, (0xec62), 0) & mask) == 0) |
3881 | break; |
3882 | udelay(1); |
3883 | } |
3884 | } |
3885 | |
3886 | static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, |
3887 | bool_Bool enable) |
3888 | { |
3889 | u32 tmp = RREG32(mmCP_INT_CNTL_RING0)amdgpu_device_rreg(adev, (0x306a), 0); |
3890 | |
3891 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x80000) | (0x80000 & ((enable ? 1 : 0) << 0x13))); |
3892 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x100000) | (0x100000 & ((enable ? 1 : 0) << 0x14))); |
3893 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x40000) | (0x40000 & ((enable ? 1 : 0) << 0x12))); |
3894 | tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0)(((tmp) & ~0x200000) | (0x200000 & ((enable ? 1 : 0) << 0x15))); |
3895 | |
3896 | WREG32(mmCP_INT_CNTL_RING0, tmp)amdgpu_device_wreg(adev, (0x306a), (tmp), 0); |
3897 | } |
3898 | |
3899 | static void gfx_v8_0_init_csb(struct amdgpu_device *adev) |
3900 | { |
3901 | adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); |
3902 | /* csib */ |
3903 | WREG32(mmRLC_CSIB_ADDR_HI,amdgpu_device_wreg(adev, (0xeca3), (adev->gfx.rlc.clear_state_gpu_addr >> 32), 0) |
3904 | adev->gfx.rlc.clear_state_gpu_addr >> 32)amdgpu_device_wreg(adev, (0xeca3), (adev->gfx.rlc.clear_state_gpu_addr >> 32), 0); |
3905 | WREG32(mmRLC_CSIB_ADDR_LO,amdgpu_device_wreg(adev, (0xeca2), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0) |
3906 | adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)amdgpu_device_wreg(adev, (0xeca2), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0); |
3907 | WREG32(mmRLC_CSIB_LENGTH,amdgpu_device_wreg(adev, (0xeca4), (adev->gfx.rlc.clear_state_size ), 0) |
3908 | adev->gfx.rlc.clear_state_size)amdgpu_device_wreg(adev, (0xeca4), (adev->gfx.rlc.clear_state_size ), 0); |
3909 | } |
3910 | |
3911 | static void gfx_v8_0_parse_ind_reg_list(int *register_list_format, |
3912 | int ind_offset, |
3913 | int list_size, |
3914 | int *unique_indices, |
3915 | int *indices_count, |
3916 | int max_indices, |
3917 | int *ind_start_offsets, |
3918 | int *offset_count, |
3919 | int max_offset) |
3920 | { |
3921 | int indices; |
3922 | bool_Bool new_entry = true1; |
3923 | |
3924 | for (; ind_offset < list_size; ind_offset++) { |
3925 | |
3926 | if (new_entry) { |
3927 | new_entry = false0; |
3928 | ind_start_offsets[*offset_count] = ind_offset; |
3929 | *offset_count = *offset_count + 1; |
3930 | BUG_ON(*offset_count >= max_offset)((!(*offset_count >= max_offset)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c", 3930, "!(*offset_count >= max_offset)" )); |
3931 | } |
3932 | |
3933 | if (register_list_format[ind_offset] == 0xFFFFFFFF) { |
3934 | new_entry = true1; |
3935 | continue; |
3936 | } |
3937 | |
3938 | ind_offset += 2; |
3939 | |
3940 | /* look for the matching indice */ |
3941 | for (indices = 0; |
3942 | indices < *indices_count; |
3943 | indices++) { |
3944 | if (unique_indices[indices] == |
3945 | register_list_format[ind_offset]) |
3946 | break; |
3947 | } |
3948 | |
3949 | if (indices >= *indices_count) { |
3950 | unique_indices[*indices_count] = |
3951 | register_list_format[ind_offset]; |
3952 | indices = *indices_count; |
3953 | *indices_count = *indices_count + 1; |
3954 | BUG_ON(*indices_count >= max_indices)((!(*indices_count >= max_indices)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c", 3954, "!(*indices_count >= max_indices)" )); |
3955 | } |
3956 | |
3957 | register_list_format[ind_offset] = indices; |
3958 | } |
3959 | } |
3960 | |
3961 | static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) |
3962 | { |
3963 | int i, temp, data; |
3964 | int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0}; |
3965 | int indices_count = 0; |
3966 | int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; |
3967 | int offset_count = 0; |
3968 | |
3969 | int list_size; |
3970 | unsigned int *register_list_format = |
3971 | kmemdup(adev->gfx.rlc.register_list_format, |
3972 | adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL(0x0001 | 0x0004)); |
3973 | if (!register_list_format) |
3974 | return -ENOMEM12; |
3975 | |
3976 | gfx_v8_0_parse_ind_reg_list(register_list_format, |
3977 | RLC_FormatDirectRegListLength14, |
3978 | adev->gfx.rlc.reg_list_format_size_bytes >> 2, |
3979 | unique_indices, |
3980 | &indices_count, |
3981 | ARRAY_SIZE(unique_indices)(sizeof((unique_indices)) / sizeof((unique_indices)[0])), |
3982 | indirect_start_offsets, |
3983 | &offset_count, |
3984 | ARRAY_SIZE(indirect_start_offsets)(sizeof((indirect_start_offsets)) / sizeof((indirect_start_offsets )[0]))); |
3985 | |
3986 | /* save and restore list */ |
3987 | WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1)amdgpu_device_wreg(adev, (0xec80), ((amdgpu_device_rreg(adev, (0xec80), 0) & ~0x2) | (1) << 0x1), 0); |
3988 | |
3989 | WREG32(mmRLC_SRM_ARAM_ADDR, 0)amdgpu_device_wreg(adev, (0xec83), (0), 0); |
3990 | for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++) |
3991 | WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i])amdgpu_device_wreg(adev, (0xec84), (adev->gfx.rlc.register_restore [i]), 0); |
3992 | |
3993 | /* indirect list */ |
3994 | WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start)amdgpu_device_wreg(adev, (0xec6c), (adev->gfx.rlc.reg_list_format_start ), 0); |
3995 | for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++) |
3996 | WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i])amdgpu_device_wreg(adev, (0xec6d), (register_list_format[i]), 0); |
3997 | |
3998 | list_size = adev->gfx.rlc.reg_list_size_bytes >> 2; |
3999 | list_size = list_size >> 1; |
4000 | WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size)amdgpu_device_wreg(adev, (0xec6c), (adev->gfx.rlc.reg_restore_list_size ), 0); |
4001 | WREG32(mmRLC_GPM_SCRATCH_DATA, list_size)amdgpu_device_wreg(adev, (0xec6d), (list_size), 0); |
4002 | |
4003 | /* starting offsets starts */ |
4004 | WREG32(mmRLC_GPM_SCRATCH_ADDR,amdgpu_device_wreg(adev, (0xec6c), (adev->gfx.rlc.starting_offsets_start ), 0) |
4005 | adev->gfx.rlc.starting_offsets_start)amdgpu_device_wreg(adev, (0xec6c), (adev->gfx.rlc.starting_offsets_start ), 0); |
4006 | for (i = 0; i < ARRAY_SIZE(indirect_start_offsets)(sizeof((indirect_start_offsets)) / sizeof((indirect_start_offsets )[0])); i++) |
4007 | WREG32(mmRLC_GPM_SCRATCH_DATA,amdgpu_device_wreg(adev, (0xec6d), (indirect_start_offsets[i] ), 0) |
4008 | indirect_start_offsets[i])amdgpu_device_wreg(adev, (0xec6d), (indirect_start_offsets[i] ), 0); |
4009 | |
4010 | /* unique indices */ |
4011 | temp = mmRLC_SRM_INDEX_CNTL_ADDR_00xec8b; |
4012 | data = mmRLC_SRM_INDEX_CNTL_DATA_00xec93; |
4013 | for (i = 0; i < ARRAY_SIZE(unique_indices)(sizeof((unique_indices)) / sizeof((unique_indices)[0])); i++) { |
4014 | if (unique_indices[i] != 0) { |
4015 | WREG32(temp + i, unique_indices[i] & 0x3FFFF)amdgpu_device_wreg(adev, (temp + i), (unique_indices[i] & 0x3FFFF), 0); |
4016 | WREG32(data + i, unique_indices[i] >> 20)amdgpu_device_wreg(adev, (data + i), (unique_indices[i] >> 20), 0); |
4017 | } |
4018 | } |
4019 | kfree(register_list_format); |
4020 | |
4021 | return 0; |
4022 | } |
4023 | |
4024 | static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) |
4025 | { |
4026 | WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1)amdgpu_device_wreg(adev, (0xec80), ((amdgpu_device_rreg(adev, (0xec80), 0) & ~0x1) | (1) << 0x0), 0); |
4027 | } |
4028 | |
4029 | static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev) |
4030 | { |
4031 | uint32_t data; |
4032 | |
4033 | WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60)amdgpu_device_wreg(adev, (0x21c2), ((amdgpu_device_rreg(adev, (0x21c2), 0) & ~0xffff0000) | (0x60) << 0x10), 0); |
4034 | |
4035 | data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10)(((0) & ~0xff) | (0xff & ((0x10) << 0x0))); |
4036 | data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10)(((data) & ~0xff00) | (0xff00 & ((0x10) << 0x8) )); |
4037 | data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10)(((data) & ~0xff0000) | (0xff0000 & ((0x10) << 0x10 ))); |
4038 | data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10)(((data) & ~0xff000000) | (0xff000000 & ((0x10) << 0x18))); |
4039 | WREG32(mmRLC_PG_DELAY, data)amdgpu_device_wreg(adev, (0xec4d), (data), 0); |
4040 | |
4041 | WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3)amdgpu_device_wreg(adev, (0xec1f), ((amdgpu_device_rreg(adev, (0xec1f), 0) & ~0xff00) | (0x3) << 0x8), 0); |
4042 | WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0)amdgpu_device_wreg(adev, (0xec55), ((amdgpu_device_rreg(adev, (0xec55), 0) & ~0x7fff8) | (0x55f0) << 0x3), 0); |
4043 | |
4044 | } |
4045 | |
4046 | static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev, |
4047 | bool_Bool enable) |
4048 | { |
4049 | WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0)amdgpu_device_wreg(adev, (0xec43), ((amdgpu_device_rreg(adev, (0xec43), 0) & ~0x20000) | (enable ? 1 : 0) << 0x11 ), 0); |
4050 | } |
4051 | |
4052 | static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev, |
4053 | bool_Bool enable) |
4054 | { |
4055 | WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0)amdgpu_device_wreg(adev, (0xec43), ((amdgpu_device_rreg(adev, (0xec43), 0) & ~0x40000) | (enable ? 1 : 0) << 0x12 ), 0); |
4056 | } |
4057 | |
4058 | static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool_Bool enable) |
4059 | { |
4060 | WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1)amdgpu_device_wreg(adev, (0xec43), ((amdgpu_device_rreg(adev, (0xec43), 0) & ~0x8000) | (enable ? 0 : 1) << 0xf) , 0); |
4061 | } |
4062 | |
4063 | static void gfx_v8_0_init_pg(struct amdgpu_device *adev) |
4064 | { |
4065 | if ((adev->asic_type == CHIP_CARRIZO) || |
4066 | (adev->asic_type == CHIP_STONEY)) { |
4067 | gfx_v8_0_init_csb(adev); |
4068 | gfx_v8_0_init_save_restore_list(adev); |
4069 | gfx_v8_0_enable_save_restore_machine(adev); |
4070 | WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8)amdgpu_device_wreg(adev, (0xec1e), (adev->gfx.rlc.cp_table_gpu_addr >> 8), 0); |
4071 | gfx_v8_0_init_power_gating(adev); |
4072 | WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask)amdgpu_device_wreg(adev, (0xec53), (adev->gfx.cu_info.ao_cu_mask ), 0); |
4073 | } else if ((adev->asic_type == CHIP_POLARIS11) || |
4074 | (adev->asic_type == CHIP_POLARIS12) || |
4075 | (adev->asic_type == CHIP_VEGAM)) { |
4076 | gfx_v8_0_init_csb(adev); |
4077 | gfx_v8_0_init_save_restore_list(adev); |
4078 | gfx_v8_0_enable_save_restore_machine(adev); |
4079 | gfx_v8_0_init_power_gating(adev); |
4080 | } |
4081 | |
4082 | } |
4083 | |
4084 | static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev) |
4085 | { |
4086 | WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0)amdgpu_device_wreg(adev, (0xec00), ((amdgpu_device_rreg(adev, (0xec00), 0) & ~0x1) | (0) << 0x0), 0); |
4087 | |
4088 | gfx_v8_0_enable_gui_idle_interrupt(adev, false0); |
4089 | gfx_v8_0_wait_for_rlc_serdes(adev); |
4090 | } |
4091 | |
4092 | static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev) |
4093 | { |
4094 | WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)amdgpu_device_wreg(adev, (0x2008), ((amdgpu_device_rreg(adev, (0x2008), 0) & ~0x4) | (1) << 0x2), 0); |
4095 | udelay(50); |
4096 | |
4097 | WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0)amdgpu_device_wreg(adev, (0x2008), ((amdgpu_device_rreg(adev, (0x2008), 0) & ~0x4) | (0) << 0x2), 0); |
4098 | udelay(50); |
4099 | } |
4100 | |
4101 | static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) |
4102 | { |
4103 | WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1)amdgpu_device_wreg(adev, (0xec00), ((amdgpu_device_rreg(adev, (0xec00), 0) & ~0x1) | (1) << 0x0), 0); |
4104 | |
4105 | /* carrizo do enable cp interrupt after cp inited */ |
4106 | if (!(adev->flags & AMD_IS_APU)) |
4107 | gfx_v8_0_enable_gui_idle_interrupt(adev, true1); |
4108 | |
4109 | udelay(50); |
4110 | } |
4111 | |
4112 | static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) |
4113 | { |
4114 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
4115 | gfx_v8_0_init_csb(adev); |
4116 | return 0; |
4117 | } |
4118 | |
4119 | adev->gfx.rlc.funcs->stop(adev); |
4120 | adev->gfx.rlc.funcs->reset(adev); |
4121 | gfx_v8_0_init_pg(adev); |
4122 | adev->gfx.rlc.funcs->start(adev); |
4123 | |
4124 | return 0; |
4125 | } |
4126 | |
4127 | static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool_Bool enable) |
4128 | { |
4129 | u32 tmp = RREG32(mmCP_ME_CNTL)amdgpu_device_rreg(adev, (0x21b6), 0); |
4130 | |
4131 | if (enable) { |
4132 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0)(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c ))); |
4133 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0)(((tmp) & ~0x4000000) | (0x4000000 & ((0) << 0x1a ))); |
4134 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0)(((tmp) & ~0x1000000) | (0x1000000 & ((0) << 0x18 ))); |
4135 | } else { |
4136 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1)(((tmp) & ~0x10000000) | (0x10000000 & ((1) << 0x1c ))); |
4137 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1)(((tmp) & ~0x4000000) | (0x4000000 & ((1) << 0x1a ))); |
4138 | tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1)(((tmp) & ~0x1000000) | (0x1000000 & ((1) << 0x18 ))); |
4139 | } |
4140 | WREG32(mmCP_ME_CNTL, tmp)amdgpu_device_wreg(adev, (0x21b6), (tmp), 0); |
4141 | udelay(50); |
4142 | } |
4143 | |
4144 | static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev) |
4145 | { |
4146 | u32 count = 0; |
4147 | const struct cs_section_def *sect = NULL((void *)0); |
4148 | const struct cs_extent_def *ext = NULL((void *)0); |
4149 | |
4150 | /* begin clear state */ |
4151 | count += 2; |
4152 | /* context control state */ |
4153 | count += 3; |
4154 | |
4155 | for (sect = vi_cs_data; sect->section != NULL((void *)0); ++sect) { |
4156 | for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) { |
4157 | if (sect->id == SECT_CONTEXT) |
4158 | count += 2 + ext->reg_count; |
4159 | else |
4160 | return 0; |
4161 | } |
4162 | } |
4163 | /* pa_sc_raster_config/pa_sc_raster_config1 */ |
4164 | count += 4; |
4165 | /* end clear state */ |
4166 | count += 2; |
4167 | /* clear state */ |
4168 | count += 2; |
4169 | |
4170 | return count; |
4171 | } |
4172 | |
4173 | static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) |
4174 | { |
4175 | struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; |
4176 | const struct cs_section_def *sect = NULL((void *)0); |
4177 | const struct cs_extent_def *ext = NULL((void *)0); |
4178 | int r, i; |
4179 | |
4180 | /* init the CP */ |
4181 | WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1)amdgpu_device_wreg(adev, (0x30ae), (adev->gfx.config.max_hw_contexts - 1), 0); |
4182 | WREG32(mmCP_ENDIAN_SWAP, 0)amdgpu_device_wreg(adev, (0x3050), (0), 0); |
4183 | WREG32(mmCP_DEVICE_ID, 1)amdgpu_device_wreg(adev, (0x304b), (1), 0); |
4184 | |
4185 | gfx_v8_0_cp_gfx_enable(adev, true1); |
4186 | |
4187 | r = amdgpu_ring_alloc(ring, gfx_v8_0_get_csb_size(adev) + 4); |
4188 | if (r) { |
4189 | DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r); |
4190 | return r; |
4191 | } |
4192 | |
4193 | /* clear state buffer */ |
4194 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
4195 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE(2 << 28)); |
4196 | |
4197 | amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) & 0x3FFF) << 16)); |
4198 | amdgpu_ring_write(ring, 0x80000000); |
4199 | amdgpu_ring_write(ring, 0x80000000); |
4200 | |
4201 | for (sect = vi_cs_data; sect->section != NULL((void *)0); ++sect) { |
4202 | for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) { |
4203 | if (sect->id == SECT_CONTEXT) { |
4204 | amdgpu_ring_write(ring, |
4205 | PACKET3(PACKET3_SET_CONTEXT_REG,((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext-> reg_count) & 0x3FFF) << 16) |
4206 | ext->reg_count)((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext-> reg_count) & 0x3FFF) << 16)); |
4207 | amdgpu_ring_write(ring, |
4208 | ext->reg_index - PACKET3_SET_CONTEXT_REG_START0x0000a000); |
4209 | for (i = 0; i < ext->reg_count; i++) |
4210 | amdgpu_ring_write(ring, ext->extent[i]); |
4211 | } |
4212 | } |
4213 | } |
4214 | |
4215 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)((3 << 30) | (((0x69) & 0xFF) << 8) | ((2) & 0x3FFF) << 16)); |
4216 | amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG0xa0d4 - PACKET3_SET_CONTEXT_REG_START0x0000a000); |
4217 | amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config); |
4218 | amdgpu_ring_write(ring, adev->gfx.config.rb_config[0][0].raster_config_1); |
4219 | |
4220 | amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
4221 | amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE(3 << 28)); |
4222 | |
4223 | amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) & 0x3FFF) << 16)); |
4224 | amdgpu_ring_write(ring, 0); |
4225 | |
4226 | /* init the CE partitions */ |
4227 | amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)((3 << 30) | (((0x11) & 0xFF) << 8) | ((2) & 0x3FFF) << 16)); |
4228 | amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)((3) << 0)); |
4229 | amdgpu_ring_write(ring, 0x8000); |
4230 | amdgpu_ring_write(ring, 0x8000); |
4231 | |
4232 | amdgpu_ring_commit(ring); |
4233 | |
4234 | return 0; |
4235 | } |
4236 | static void gfx_v8_0_set_cpg_door_bell(struct amdgpu_device *adev, struct amdgpu_ring *ring) |
4237 | { |
4238 | u32 tmp; |
4239 | /* no gfx doorbells on iceland */ |
4240 | if (adev->asic_type == CHIP_TOPAZ) |
4241 | return; |
4242 | |
4243 | tmp = RREG32(mmCP_RB_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (0x3059), 0); |
4244 | |
4245 | if (ring->use_doorbell) { |
4246 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x7ffffc) | (0x7ffffc & ((ring->doorbell_index ) << 0x2))) |
4247 | DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x7ffffc) | (0x7ffffc & ((ring->doorbell_index ) << 0x2))); |
4248 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x80000000) | (0x80000000 & ((0) << 0x1f ))) |
4249 | DOORBELL_HIT, 0)(((tmp) & ~0x80000000) | (0x80000000 & ((0) << 0x1f ))); |
4250 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000) | (0x40000000 & ((1) << 0x1e ))) |
4251 | DOORBELL_EN, 1)(((tmp) & ~0x40000000) | (0x40000000 & ((1) << 0x1e ))); |
4252 | } else { |
4253 | tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0)(((tmp) & ~0x40000000) | (0x40000000 & ((0) << 0x1e ))); |
4254 | } |
4255 | |
4256 | WREG32(mmCP_RB_DOORBELL_CONTROL, tmp)amdgpu_device_wreg(adev, (0x3059), (tmp), 0); |
4257 | |
4258 | if (adev->flags & AMD_IS_APU) |
4259 | return; |
4260 | |
4261 | tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x7ffffc) | (0x7ffffc & ((adev->doorbell_index .gfx_ring0) << 0x2))) |
4262 | DOORBELL_RANGE_LOWER,(((0) & ~0x7ffffc) | (0x7ffffc & ((adev->doorbell_index .gfx_ring0) << 0x2))) |
4263 | adev->doorbell_index.gfx_ring0)(((0) & ~0x7ffffc) | (0x7ffffc & ((adev->doorbell_index .gfx_ring0) << 0x2))); |
4264 | WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp)amdgpu_device_wreg(adev, (0x305a), (tmp), 0); |
4265 | |
4266 | WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, (0x305b), (0x7ffffc), 0) |
4267 | CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK)amdgpu_device_wreg(adev, (0x305b), (0x7ffffc), 0); |
4268 | } |
4269 | |
4270 | static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev) |
4271 | { |
4272 | struct amdgpu_ring *ring; |
4273 | u32 tmp; |
4274 | u32 rb_bufsz; |
4275 | u64 rb_addr, rptr_addr, wptr_gpu_addr; |
4276 | |
4277 | /* Set the write pointer delay */ |
4278 | WREG32(mmCP_RB_WPTR_DELAY, 0)amdgpu_device_wreg(adev, (0x21c1), (0), 0); |
4279 | |
4280 | /* set the RB to use vmid 0 */ |
4281 | WREG32(mmCP_RB_VMID, 0)amdgpu_device_wreg(adev, (0x3051), (0), 0); |
4282 | |
4283 | /* Set ring buffer size */ |
4284 | ring = &adev->gfx.gfx_ring[0]; |
4285 | rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8); |
4286 | tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x3f) | (0x3f & ((rb_bufsz) << 0x0))); |
4287 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x3f00) | (0x3f00 & ((rb_bufsz - 2) << 0x8))); |
4288 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3)(((tmp) & ~0x18000) | (0x18000 & ((3) << 0xf))); |
4289 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1)(((tmp) & ~0xc00000) | (0xc00000 & ((1) << 0x16 ))); |
4290 | #ifdef __BIG_ENDIAN |
4291 | tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1)(((tmp) & ~0x60000) | (0x60000 & ((1) << 0x11)) ); |
4292 | #endif |
4293 | WREG32(mmCP_RB0_CNTL, tmp)amdgpu_device_wreg(adev, (0x3041), (tmp), 0); |
4294 | |
4295 | /* Initialize the ring buffer's read and write pointers */ |
4296 | WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK)amdgpu_device_wreg(adev, (0x3041), (tmp | 0x80000000), 0); |
4297 | ring->wptr = 0; |
4298 | WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, (0x3045), (((u32)(ring->wptr))), 0 ); |
4299 | |
4300 | /* set the wb address wether it's enabled or not */ |
4301 | rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); |
4302 | WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr))amdgpu_device_wreg(adev, (0x3043), (((u32)(rptr_addr))), 0); |
4303 | WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF)amdgpu_device_wreg(adev, (0x3044), (((u32)(((rptr_addr) >> 16) >> 16)) & 0xFF), 0); |
4304 | |
4305 | wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); |
4306 | WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, (0x3046), (((u32)(wptr_gpu_addr))), 0 ); |
4307 | WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, (0x3047), (((u32)(((wptr_gpu_addr) >> 16) >> 16))), 0); |
4308 | mdelay(1); |
4309 | WREG32(mmCP_RB0_CNTL, tmp)amdgpu_device_wreg(adev, (0x3041), (tmp), 0); |
4310 | |
4311 | rb_addr = ring->gpu_addr >> 8; |
4312 | WREG32(mmCP_RB0_BASE, rb_addr)amdgpu_device_wreg(adev, (0x3040), (rb_addr), 0); |
4313 | WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr))amdgpu_device_wreg(adev, (0x30b1), (((u32)(((rb_addr) >> 16) >> 16))), 0); |
4314 | |
4315 | gfx_v8_0_set_cpg_door_bell(adev, ring); |
4316 | /* start the ring */ |
4317 | amdgpu_ring_clear_ring(ring); |
4318 | gfx_v8_0_cp_gfx_start(adev); |
4319 | ring->sched.ready = true1; |
4320 | |
4321 | return 0; |
4322 | } |
4323 | |
4324 | static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool_Bool enable) |
4325 | { |
4326 | if (enable) { |
4327 | WREG32(mmCP_MEC_CNTL, 0)amdgpu_device_wreg(adev, (0x208d), (0), 0); |
4328 | } else { |
4329 | WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK))amdgpu_device_wreg(adev, (0x208d), ((0x40000000 | 0x10000000) ), 0); |
4330 | adev->gfx.kiq.ring.sched.ready = false0; |
4331 | } |
4332 | udelay(50); |
4333 | } |
4334 | |
4335 | /* KIQ functions */ |
4336 | static void gfx_v8_0_kiq_setting(struct amdgpu_ring *ring) |
4337 | { |
4338 | uint32_t tmp; |
4339 | struct amdgpu_device *adev = ring->adev; |
4340 | |
4341 | /* tell RLC which is KIQ queue */ |
4342 | tmp = RREG32(mmRLC_CP_SCHEDULERS)amdgpu_device_rreg(adev, (0xecaa), 0); |
4343 | tmp &= 0xffffff00; |
4344 | tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); |
4345 | WREG32(mmRLC_CP_SCHEDULERS, tmp)amdgpu_device_wreg(adev, (0xecaa), (tmp), 0); |
4346 | tmp |= 0x80; |
4347 | WREG32(mmRLC_CP_SCHEDULERS, tmp)amdgpu_device_wreg(adev, (0xecaa), (tmp), 0); |
4348 | } |
4349 | |
4350 | static int gfx_v8_0_kiq_kcq_enable(struct amdgpu_device *adev) |
4351 | { |
4352 | struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; |
4353 | uint64_t queue_mask = 0; |
4354 | int r, i; |
4355 | |
4356 | for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES128; ++i) { |
4357 | if (!test_bit(i, adev->gfx.mec.queue_bitmap)) |
4358 | continue; |
4359 | |
4360 | /* This situation may be hit in the future if a new HW |
4361 | * generation exposes more than 64 queues. If so, the |
4362 | * definition of queue_mask needs updating */ |
4363 | if (WARN_ON(i >= (sizeof(queue_mask)*8))({ int __ret = !!(i >= (sizeof(queue_mask)*8)); if (__ret) printf("WARNING %s failed at %s:%d\n", "i >= (sizeof(queue_mask)*8)" , "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v8_0.c", 4363); __builtin_expect (!!(__ret), 0); })) { |
4364 | DRM_ERROR("Invalid KCQ enabled: %d\n", i)__drm_err("Invalid KCQ enabled: %d\n", i); |
4365 | break; |
4366 | } |
4367 | |
4368 | queue_mask |= (1ull << i); |
4369 | } |
4370 | |
4371 | r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); |
4372 | if (r) { |
4373 | DRM_ERROR("Failed to lock KIQ (%d).\n", r)__drm_err("Failed to lock KIQ (%d).\n", r); |
4374 | return r; |
4375 | } |
4376 | /* set resources */ |
4377 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)((3 << 30) | (((0xA0) & 0xFF) << 8) | ((6) & 0x3FFF) << 16)); |
4378 | amdgpu_ring_write(kiq_ring, 0); /* vmid_mask:0 queue_type:0 (KIQ) */ |
4379 | amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)((u32)(queue_mask))); /* queue mask lo */ |
4380 | amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)((u32)(((queue_mask) >> 16) >> 16))); /* queue mask hi */ |
4381 | amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ |
4382 | amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ |
4383 | amdgpu_ring_write(kiq_ring, 0); /* oac mask */ |
4384 | amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ |
4385 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
4386 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
4387 | uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); |
4388 | uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); |
4389 | |
4390 | /* map queues */ |
4391 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)((3 << 30) | (((0xA2) & 0xFF) << 8) | ((5) & 0x3FFF) << 16)); |
4392 | /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ |
4393 | amdgpu_ring_write(kiq_ring, |
4394 | PACKET3_MAP_QUEUES_NUM_QUEUES(1)((1) << 29)); |
4395 | amdgpu_ring_write(kiq_ring, |
4396 | PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2) | |
4397 | PACKET3_MAP_QUEUES_QUEUE(ring->queue)((ring->queue) << 26) | |
4398 | PACKET3_MAP_QUEUES_PIPE(ring->pipe)((ring->pipe) << 29) | |
4399 | PACKET3_MAP_QUEUES_ME(ring->me == 1 ? 0 : 1)((ring->me == 1 ? 0 : 1) << 31)); /* doorbell */ |
4400 | amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)((u32)(mqd_addr))); |
4401 | amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)((u32)(((mqd_addr) >> 16) >> 16))); |
4402 | amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)((u32)(wptr_addr))); |
4403 | amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)((u32)(((wptr_addr) >> 16) >> 16))); |
4404 | } |
4405 | |
4406 | amdgpu_ring_commit(kiq_ring); |
4407 | |
4408 | return 0; |
4409 | } |
4410 | |
4411 | static int gfx_v8_0_deactivate_hqd(struct amdgpu_device *adev, u32 req) |
4412 | { |
4413 | int i, r = 0; |
4414 | |
4415 | if (RREG32(mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (0x3247), 0) & CP_HQD_ACTIVE__ACTIVE_MASK0x1) { |
4416 | WREG32_FIELD(CP_HQD_DEQUEUE_REQUEST, DEQUEUE_REQ, req)amdgpu_device_wreg(adev, (0x325d), ((amdgpu_device_rreg(adev, (0x325d), 0) & ~0x7) | (req) << 0x0), 0); |
4417 | for (i = 0; i < adev->usec_timeout; i++) { |
4418 | if (!(RREG32(mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (0x3247), 0) & CP_HQD_ACTIVE__ACTIVE_MASK0x1)) |
4419 | break; |
4420 | udelay(1); |
4421 | } |
4422 | if (i == adev->usec_timeout) |
4423 | r = -ETIMEDOUT60; |
4424 | } |
4425 | WREG32(mmCP_HQD_DEQUEUE_REQUEST, 0)amdgpu_device_wreg(adev, (0x325d), (0), 0); |
4426 | WREG32(mmCP_HQD_PQ_RPTR, 0)amdgpu_device_wreg(adev, (0x324f), (0), 0); |
4427 | WREG32(mmCP_HQD_PQ_WPTR, 0)amdgpu_device_wreg(adev, (0x3255), (0), 0); |
4428 | |
4429 | return r; |
4430 | } |
4431 | |
4432 | static void gfx_v8_0_mqd_set_priority(struct amdgpu_ring *ring, struct vi_mqd *mqd) |
4433 | { |
4434 | struct amdgpu_device *adev = ring->adev; |
4435 | |
4436 | if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { |
4437 | if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe, |
4438 | ring->queue)) { |
4439 | mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; |
4440 | mqd->cp_hqd_queue_priority = |
4441 | AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM15; |
4442 | } |
4443 | } |
4444 | } |
4445 | |
4446 | static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring) |
4447 | { |
4448 | struct amdgpu_device *adev = ring->adev; |
4449 | struct vi_mqd *mqd = ring->mqd_ptr; |
4450 | uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; |
4451 | uint32_t tmp; |
4452 | |
4453 | mqd->header = 0xC0310800; |
4454 | mqd->compute_pipelinestat_enable = 0x00000001; |
4455 | mqd->compute_static_thread_mgmt_se0 = 0xffffffff; |
4456 | mqd->compute_static_thread_mgmt_se1 = 0xffffffff; |
4457 | mqd->compute_static_thread_mgmt_se2 = 0xffffffff; |
4458 | mqd->compute_static_thread_mgmt_se3 = 0xffffffff; |
4459 | mqd->compute_misc_reserved = 0x00000003; |
4460 | mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr((u32)(ring->mqd_gpu_addr + __builtin_offsetof(struct vi_mqd_allocation , dynamic_cu_mask))) |
4461 | + offsetof(struct vi_mqd_allocation, dynamic_cu_mask))((u32)(ring->mqd_gpu_addr + __builtin_offsetof(struct vi_mqd_allocation , dynamic_cu_mask))); |
4462 | mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr((u32)(((ring->mqd_gpu_addr + __builtin_offsetof(struct vi_mqd_allocation , dynamic_cu_mask)) >> 16) >> 16)) |
4463 | + offsetof(struct vi_mqd_allocation, dynamic_cu_mask))((u32)(((ring->mqd_gpu_addr + __builtin_offsetof(struct vi_mqd_allocation , dynamic_cu_mask)) >> 16) >> 16)); |
4464 | eop_base_addr = ring->eop_gpu_addr >> 8; |
4465 | mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; |
4466 | mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr)((u32)(((eop_base_addr) >> 16) >> 16)); |
4467 | |
4468 | /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ |
4469 | tmp = RREG32(mmCP_HQD_EOP_CONTROL)amdgpu_device_rreg(adev, (0x326c), 0); |
4470 | tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,(((tmp) & ~0x3f) | (0x3f & (((drm_order(4096 / 4) - 1 )) << 0x0))) |
4471 | (order_base_2(GFX8_MEC_HPD_SIZE / 4) - 1))(((tmp) & ~0x3f) | (0x3f & (((drm_order(4096 / 4) - 1 )) << 0x0))); |
4472 | |
4473 | mqd->cp_hqd_eop_control = tmp; |
4474 | |
4475 | /* enable doorbell? */ |
4476 | tmp = REG_SET_FIELD(RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL),(((amdgpu_device_rreg(adev, (0x3254), 0)) & ~0x40000000) | (0x40000000 & ((ring->use_doorbell ? 1 : 0) << 0x1e ))) |
4477 | CP_HQD_PQ_DOORBELL_CONTROL,(((amdgpu_device_rreg(adev, (0x3254), 0)) & ~0x40000000) | (0x40000000 & ((ring->use_doorbell ? 1 : 0) << 0x1e ))) |
4478 | DOORBELL_EN,(((amdgpu_device_rreg(adev, (0x3254), 0)) & ~0x40000000) | (0x40000000 & ((ring->use_doorbell ? 1 : 0) << 0x1e ))) |
4479 | ring->use_doorbell ? 1 : 0)(((amdgpu_device_rreg(adev, (0x3254), 0)) & ~0x40000000) | (0x40000000 & ((ring->use_doorbell ? 1 : 0) << 0x1e ))); |
4480 | |
4481 | mqd->cp_hqd_pq_doorbell_control = tmp; |
4482 | |
4483 | /* set the pointer to the MQD */ |
4484 | mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; |
4485 | mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr)((u32)(((ring->mqd_gpu_addr) >> 16) >> 16)); |
4486 | |
4487 | /* set MQD vmid to 0 */ |
4488 | tmp = RREG32(mmCP_MQD_CONTROL)amdgpu_device_rreg(adev, (0x3267), 0); |
4489 | tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0)(((tmp) & ~0xf) | (0xf & ((0) << 0x0))); |
4490 | mqd->cp_mqd_control = tmp; |
4491 | |
4492 | /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ |
4493 | hqd_gpu_addr = ring->gpu_addr >> 8; |
4494 | mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; |
4495 | mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16)); |
4496 | |
4497 | /* set up the HQD, this is similar to CP_RB0_CNTL */ |
4498 | tmp = RREG32(mmCP_HQD_PQ_CONTROL)amdgpu_device_rreg(adev, (0x3256), 0); |
4499 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,(((tmp) & ~0x3f) | (0x3f & (((drm_order(ring->ring_size / 4) - 1)) << 0x0))) |
4500 | (order_base_2(ring->ring_size / 4) - 1))(((tmp) & ~0x3f) | (0x3f & (((drm_order(ring->ring_size / 4) - 1)) << 0x0))); |
4501 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,(((tmp) & ~0x3f00) | (0x3f00 & ((((drm_order(4096 / 4 ) - 1) << 8)) << 0x8))) |
4502 | ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8))(((tmp) & ~0x3f00) | (0x3f00 & ((((drm_order(4096 / 4 ) - 1) << 8)) << 0x8))); |
4503 | #ifdef __BIG_ENDIAN |
4504 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1)(((tmp) & ~0x60000) | (0x60000 & ((1) << 0x11)) ); |
4505 | #endif |
4506 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0)(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c ))); |
4507 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0)(((tmp) & ~0x20000000) | (0x20000000 & ((0) << 0x1d ))); |
4508 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x40000000) | (0x40000000 & ((1) << 0x1e ))); |
4509 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1)(((tmp) & ~0x80000000) | (0x80000000 & ((1) << 0x1f ))); |
4510 | mqd->cp_hqd_pq_control = tmp; |
4511 | |
4512 | /* set the wb address whether it's enabled or not */ |
4513 | wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); |
4514 | mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; |
4515 | mqd->cp_hqd_pq_rptr_report_addr_hi = |
4516 | upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff; |
4517 | |
4518 | /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ |
4519 | wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); |
4520 | mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; |
4521 | mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff; |
4522 | |
4523 | tmp = 0; |
4524 | /* enable the doorbell if requested */ |
4525 | if (ring->use_doorbell) { |
4526 | tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (0x3254), 0); |
4527 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x7ffffc) | (0x7ffffc & ((ring->doorbell_index ) << 0x2))) |
4528 | DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x7ffffc) | (0x7ffffc & ((ring->doorbell_index ) << 0x2))); |
4529 | |
4530 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000) | (0x40000000 & ((1) << 0x1e ))) |
4531 | DOORBELL_EN, 1)(((tmp) & ~0x40000000) | (0x40000000 & ((1) << 0x1e ))); |
4532 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c ))) |
4533 | DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000) | (0x10000000 & ((0) << 0x1c ))); |
4534 | tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000) | (0x80000000 & ((0) << 0x1f ))) |
4535 | DOORBELL_HIT, 0)(((tmp) & ~0x80000000) | (0x80000000 & ((0) << 0x1f ))); |
4536 | } |
4537 | |
4538 | mqd->cp_hqd_pq_doorbell_control = tmp; |
4539 | |
4540 | /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ |
4541 | ring->wptr = 0; |
4542 | mqd->cp_hqd_pq_wptr = ring->wptr; |
4543 | mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR)amdgpu_device_rreg(adev, (0x324f), 0); |
4544 | |
4545 | /* set the vmid for the queue */ |
4546 | mqd->cp_hqd_vmid = 0; |
4547 | |
4548 | tmp = RREG32(mmCP_HQD_PERSISTENT_STATE)amdgpu_device_rreg(adev, (0x3249), 0); |
4549 | tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53)(((tmp) & ~0x3ff00) | (0x3ff00 & ((0x53) << 0x8 ))); |
4550 | mqd->cp_hqd_persistent_state = tmp; |
4551 | |
4552 | /* set MTYPE */ |
4553 | tmp = RREG32(mmCP_HQD_IB_CONTROL)amdgpu_device_rreg(adev, (0x325a), 0); |
4554 | tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3)(((tmp) & ~0x300000) | (0x300000 & ((3) << 0x14 ))); |
4555 | tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MTYPE, 3)(((tmp) & ~0x18000000) | (0x18000000 & ((3) << 0x1b ))); |
4556 | mqd->cp_hqd_ib_control = tmp; |
4557 | |
4558 | tmp = RREG32(mmCP_HQD_IQ_TIMER)amdgpu_device_rreg(adev, (0x325b), 0); |
4559 | tmp = REG_SET_FIELD(tmp, CP_HQD_IQ_TIMER, MTYPE, 3)(((tmp) & ~0x18000000) | (0x18000000 & ((3) << 0x1b ))); |
4560 | mqd->cp_hqd_iq_timer = tmp; |
4561 | |
4562 | tmp = RREG32(mmCP_HQD_CTX_SAVE_CONTROL)amdgpu_device_rreg(adev, (0x3272), 0); |
4563 | tmp = REG_SET_FIELD(tmp, CP_HQD_CTX_SAVE_CONTROL, MTYPE, 3)(((tmp) & ~0x6) | (0x6 & ((3) << 0x1))); |
4564 | mqd->cp_hqd_ctx_save_control = tmp; |
4565 | |
4566 | /* defaults */ |
4567 | mqd->cp_hqd_eop_rptr = RREG32(mmCP_HQD_EOP_RPTR)amdgpu_device_rreg(adev, (0x326d), 0); |
4568 | mqd->cp_hqd_eop_wptr = RREG32(mmCP_HQD_EOP_WPTR)amdgpu_device_rreg(adev, (0x326e), 0); |
4569 | mqd->cp_hqd_ctx_save_base_addr_lo = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO)amdgpu_device_rreg(adev, (0x3270), 0); |
4570 | mqd->cp_hqd_ctx_save_base_addr_hi = RREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI)amdgpu_device_rreg(adev, (0x3271), 0); |
4571 | mqd->cp_hqd_cntl_stack_offset = RREG32(mmCP_HQD_CNTL_STACK_OFFSET)amdgpu_device_rreg(adev, (0x3273), 0); |
4572 | mqd->cp_hqd_cntl_stack_size = RREG32(mmCP_HQD_CNTL_STACK_SIZE)amdgpu_device_rreg(adev, (0x3274), 0); |
4573 | mqd->cp_hqd_wg_state_offset = RREG32(mmCP_HQD_WG_STATE_OFFSET)amdgpu_device_rreg(adev, (0x3275), 0); |
4574 | mqd->cp_hqd_ctx_save_size = RREG32(mmCP_HQD_CTX_SAVE_SIZE)amdgpu_device_rreg(adev, (0x3276), 0); |
4575 | mqd->cp_hqd_eop_done_events = RREG32(mmCP_HQD_EOP_EVENTS)amdgpu_device_rreg(adev, (0x326f), 0); |
4576 | mqd->cp_hqd_error = RREG32(mmCP_HQD_ERROR)amdgpu_device_rreg(adev, (0x3278), 0); |
4577 | mqd->cp_hqd_eop_wptr_mem = RREG32(mmCP_HQD_EOP_WPTR_MEM)amdgpu_device_rreg(adev, (0x3279), 0); |
4578 | mqd->cp_hqd_eop_dones = RREG32(mmCP_HQD_EOP_DONES)amdgpu_device_rreg(adev, (0x327a), 0); |
4579 | |
4580 | /* set static priority for a queue/ring */ |
4581 | gfx_v8_0_mqd_set_priority(ring, mqd); |
4582 | mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM)amdgpu_device_rreg(adev, (0x324c), 0); |
4583 | |
4584 | /* map_queues packet doesn't need activate the queue, |
4585 | * so only kiq need set this field. |
4586 | */ |
4587 | if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) |
4588 | mqd->cp_hqd_active = 1; |
4589 | |
4590 | return 0; |
4591 | } |
4592 | |
4593 | static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, |
4594 | struct vi_mqd *mqd) |
4595 | { |
4596 | uint32_t mqd_reg; |
4597 | uint32_t *mqd_data; |
4598 | |
4599 | /* HQD registers extend from mmCP_MQD_BASE_ADDR to mmCP_HQD_ERROR */ |
4600 | mqd_data = &mqd->cp_mqd_base_addr_lo; |
4601 | |
4602 | /* disable wptr polling */ |
4603 | WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0)amdgpu_device_wreg(adev, (0x3083), ((amdgpu_device_rreg(adev, (0x3083), 0) & ~0x80000000) | (0) << 0x1f), 0); |
4604 | |
4605 | /* program all HQD registers */ |
4606 | for (mqd_reg = mmCP_HQD_VMID0x3248; mqd_reg <= mmCP_HQD_EOP_CONTROL0x326c; mqd_reg++) |
4607 | WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR])amdgpu_device_wreg(adev, (mqd_reg), (mqd_data[mqd_reg - 0x3245 ]), 0); |
4608 | |
4609 | /* Tonga errata: EOP RPTR/WPTR should be left unmodified. |
4610 | * This is safe since EOP RPTR==WPTR for any inactive HQD |
4611 | * on ASICs that do not support context-save. |
4612 | * EOP writes/reads can start anywhere in the ring. |
4613 | */ |
4614 | if (adev->asic_type != CHIP_TONGA) { |
4615 | WREG32(mmCP_HQD_EOP_RPTR, mqd->cp_hqd_eop_rptr)amdgpu_device_wreg(adev, (0x326d), (mqd->cp_hqd_eop_rptr), 0); |
4616 | WREG32(mmCP_HQD_EOP_WPTR, mqd->cp_hqd_eop_wptr)amdgpu_device_wreg(adev, (0x326e), (mqd->cp_hqd_eop_wptr), 0); |
4617 | WREG32(mmCP_HQD_EOP_WPTR_MEM, mqd->cp_hqd_eop_wptr_mem)amdgpu_device_wreg(adev, (0x3279), (mqd->cp_hqd_eop_wptr_mem ), 0); |
4618 | } |
4619 | |
4620 | for (mqd_reg = mmCP_HQD_EOP_EVENTS0x326f; mqd_reg <= mmCP_HQD_ERROR0x3278; mqd_reg++) |
4621 | WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR])amdgpu_device_wreg(adev, (mqd_reg), (mqd_data[mqd_reg - 0x3245 ]), 0); |
4622 | |
4623 | /* activate the HQD */ |
4624 | for (mqd_reg = mmCP_MQD_BASE_ADDR0x3245; mqd_reg <= mmCP_HQD_ACTIVE0x3247; mqd_reg++) |
4625 | WREG32(mqd_reg, mqd_data[mqd_reg - mmCP_MQD_BASE_ADDR])amdgpu_device_wreg(adev, (mqd_reg), (mqd_data[mqd_reg - 0x3245 ]), 0); |
4626 | |
4627 | return 0; |
4628 | } |
4629 | |
4630 | static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring) |
4631 | { |
4632 | struct amdgpu_device *adev = ring->adev; |
4633 | struct vi_mqd *mqd = ring->mqd_ptr; |
4634 | int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS8; |
4635 | |
4636 | gfx_v8_0_kiq_setting(ring); |
4637 | |
4638 | if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ |
4639 | /* reset MQD to a clean status */ |
4640 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
4641 | memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx] ), (sizeof(struct vi_mqd_allocation))); |
4642 | |
4643 | /* reset ring buffer */ |
4644 | ring->wptr = 0; |
4645 | amdgpu_ring_clear_ring(ring); |
4646 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
4647 | vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
4648 | gfx_v8_0_mqd_commit(adev, mqd); |
4649 | vi_srbm_select(adev, 0, 0, 0, 0); |
4650 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
4651 | } else { |
4652 | memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation))__builtin_memset(((void *)mqd), (0), (sizeof(struct vi_mqd_allocation ))); |
4653 | ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; |
4654 | ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; |
4655 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
4656 | vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
4657 | gfx_v8_0_mqd_init(ring); |
4658 | gfx_v8_0_mqd_commit(adev, mqd); |
4659 | vi_srbm_select(adev, 0, 0, 0, 0); |
4660 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
4661 | |
4662 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
4663 | memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd ), (sizeof(struct vi_mqd_allocation))); |
4664 | } |
4665 | |
4666 | return 0; |
4667 | } |
4668 | |
4669 | static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring) |
4670 | { |
4671 | struct amdgpu_device *adev = ring->adev; |
4672 | struct vi_mqd *mqd = ring->mqd_ptr; |
4673 | int mqd_idx = ring - &adev->gfx.compute_ring[0]; |
4674 | |
4675 | if (!amdgpu_in_reset(adev) && !adev->in_suspend) { |
4676 | memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation))__builtin_memset(((void *)mqd), (0), (sizeof(struct vi_mqd_allocation ))); |
4677 | ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; |
4678 | ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; |
4679 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
4680 | vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
4681 | gfx_v8_0_mqd_init(ring); |
4682 | vi_srbm_select(adev, 0, 0, 0, 0); |
4683 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
4684 | |
4685 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
4686 | memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct vi_mqd_allocation))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd ), (sizeof(struct vi_mqd_allocation))); |
4687 | } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ |
4688 | /* reset MQD to a clean status */ |
4689 | if (adev->gfx.mec.mqd_backup[mqd_idx]) |
4690 | memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct vi_mqd_allocation))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx] ), (sizeof(struct vi_mqd_allocation))); |
4691 | /* reset ring buffer */ |
4692 | ring->wptr = 0; |
4693 | amdgpu_ring_clear_ring(ring); |
4694 | } else { |
4695 | amdgpu_ring_clear_ring(ring); |
4696 | } |
4697 | return 0; |
4698 | } |
4699 | |
4700 | static void gfx_v8_0_set_mec_doorbell_range(struct amdgpu_device *adev) |
4701 | { |
4702 | if (adev->asic_type > CHIP_TONGA) { |
4703 | WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, adev->doorbell_index.kiq << 2)amdgpu_device_wreg(adev, (0x305c), (adev->doorbell_index.kiq << 2), 0); |
4704 | WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, adev->doorbell_index.mec_ring7 << 2)amdgpu_device_wreg(adev, (0x305d), (adev->doorbell_index.mec_ring7 << 2), 0); |
4705 | } |
4706 | /* enable doorbells */ |
4707 | WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1)amdgpu_device_wreg(adev, (0x30b8), ((amdgpu_device_rreg(adev, (0x30b8), 0) & ~0x2) | (1) << 0x1), 0); |
4708 | } |
4709 | |
4710 | static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev) |
4711 | { |
4712 | struct amdgpu_ring *ring; |
4713 | int r; |
4714 | |
4715 | ring = &adev->gfx.kiq.ring; |
4716 | |
4717 | r = amdgpu_bo_reserve(ring->mqd_obj, false0); |
4718 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
4719 | return r; |
4720 | |
4721 | r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); |
4722 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
4723 | return r; |
4724 | |
4725 | gfx_v8_0_kiq_init_queue(ring); |
4726 | amdgpu_bo_kunmap(ring->mqd_obj); |
4727 | ring->mqd_ptr = NULL((void *)0); |
4728 | amdgpu_bo_unreserve(ring->mqd_obj); |
4729 | ring->sched.ready = true1; |
4730 | return 0; |
4731 | } |
4732 | |
4733 | static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev) |
4734 | { |
4735 | struct amdgpu_ring *ring = NULL((void *)0); |
4736 | int r = 0, i; |
4737 | |
4738 | gfx_v8_0_cp_compute_enable(adev, true1); |
4739 | |
4740 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
4741 | ring = &adev->gfx.compute_ring[i]; |
4742 | |
4743 | r = amdgpu_bo_reserve(ring->mqd_obj, false0); |
4744 | if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) |
4745 | goto done; |
4746 | r = amdgpu_bo_kmap(ring->mqd_obj, &ring->mqd_ptr); |
4747 | if (!r) { |
4748 | r = gfx_v8_0_kcq_init_queue(ring); |
4749 | amdgpu_bo_kunmap(ring->mqd_obj); |
4750 | ring->mqd_ptr = NULL((void *)0); |
4751 | } |
4752 | amdgpu_bo_unreserve(ring->mqd_obj); |
4753 | if (r) |
4754 | goto done; |
4755 | } |
4756 | |
4757 | gfx_v8_0_set_mec_doorbell_range(adev); |
4758 | |
4759 | r = gfx_v8_0_kiq_kcq_enable(adev); |
4760 | if (r) |
4761 | goto done; |
4762 | |
4763 | done: |
4764 | return r; |
4765 | } |
4766 | |
4767 | static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev) |
4768 | { |
4769 | int r, i; |
4770 | struct amdgpu_ring *ring; |
4771 | |
4772 | /* collect all the ring_tests here, gfx, kiq, compute */ |
4773 | ring = &adev->gfx.gfx_ring[0]; |
4774 | r = amdgpu_ring_test_helper(ring); |
4775 | if (r) |
4776 | return r; |
4777 | |
4778 | ring = &adev->gfx.kiq.ring; |
4779 | r = amdgpu_ring_test_helper(ring); |
4780 | if (r) |
4781 | return r; |
4782 | |
4783 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
4784 | ring = &adev->gfx.compute_ring[i]; |
4785 | amdgpu_ring_test_helper(ring); |
4786 | } |
4787 | |
4788 | return 0; |
4789 | } |
4790 | |
4791 | static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) |
4792 | { |
4793 | int r; |
4794 | |
4795 | if (!(adev->flags & AMD_IS_APU)) |
4796 | gfx_v8_0_enable_gui_idle_interrupt(adev, false0); |
4797 | |
4798 | r = gfx_v8_0_kiq_resume(adev); |
4799 | if (r) |
4800 | return r; |
4801 | |
4802 | r = gfx_v8_0_cp_gfx_resume(adev); |
4803 | if (r) |
4804 | return r; |
4805 | |
4806 | r = gfx_v8_0_kcq_resume(adev); |
4807 | if (r) |
4808 | return r; |
4809 | |
4810 | r = gfx_v8_0_cp_test_all_rings(adev); |
4811 | if (r) |
4812 | return r; |
4813 | |
4814 | gfx_v8_0_enable_gui_idle_interrupt(adev, true1); |
4815 | |
4816 | return 0; |
4817 | } |
4818 | |
4819 | static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool_Bool enable) |
4820 | { |
4821 | gfx_v8_0_cp_gfx_enable(adev, enable); |
4822 | gfx_v8_0_cp_compute_enable(adev, enable); |
4823 | } |
4824 | |
4825 | static int gfx_v8_0_hw_init(void *handle) |
4826 | { |
4827 | int r; |
4828 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4829 | |
4830 | gfx_v8_0_init_golden_registers(adev); |
4831 | gfx_v8_0_constants_init(adev); |
4832 | |
4833 | r = adev->gfx.rlc.funcs->resume(adev); |
4834 | if (r) |
4835 | return r; |
4836 | |
4837 | r = gfx_v8_0_cp_resume(adev); |
4838 | |
4839 | return r; |
4840 | } |
4841 | |
4842 | static int gfx_v8_0_kcq_disable(struct amdgpu_device *adev) |
4843 | { |
4844 | int r, i; |
4845 | struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; |
4846 | |
4847 | r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); |
4848 | if (r) |
4849 | DRM_ERROR("Failed to lock KIQ (%d).\n", r)__drm_err("Failed to lock KIQ (%d).\n", r); |
4850 | |
4851 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
4852 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
4853 | |
4854 | amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)((3 << 30) | (((0xA3) & 0xFF) << 8) | ((4) & 0x3FFF) << 16)); |
4855 | amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ |
4856 | PACKET3_UNMAP_QUEUES_ACTION(1)((1) << 0) | /* RESET_QUEUES */ |
4857 | PACKET3_UNMAP_QUEUES_QUEUE_SEL(0)((0) << 4) | |
4858 | PACKET3_UNMAP_QUEUES_ENGINE_SEL(0)((0) << 26) | |
4859 | PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)((1) << 29)); |
4860 | amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)((ring->doorbell_index) << 2)); |
4861 | amdgpu_ring_write(kiq_ring, 0); |
4862 | amdgpu_ring_write(kiq_ring, 0); |
4863 | amdgpu_ring_write(kiq_ring, 0); |
4864 | } |
4865 | r = amdgpu_ring_test_helper(kiq_ring); |
4866 | if (r) |
4867 | DRM_ERROR("KCQ disable failed\n")__drm_err("KCQ disable failed\n"); |
4868 | |
4869 | return r; |
4870 | } |
4871 | |
4872 | static bool_Bool gfx_v8_0_is_idle(void *handle) |
4873 | { |
4874 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4875 | |
4876 | if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)(((amdgpu_device_rreg(adev, (0x2004), 0)) & 0x80000000) >> 0x1f) |
4877 | || RREG32(mmGRBM_STATUS2)amdgpu_device_rreg(adev, (0x2002), 0) != 0x8) |
4878 | return false0; |
4879 | else |
4880 | return true1; |
4881 | } |
4882 | |
4883 | static bool_Bool gfx_v8_0_rlc_is_idle(void *handle) |
4884 | { |
4885 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4886 | |
4887 | if (RREG32(mmGRBM_STATUS2)amdgpu_device_rreg(adev, (0x2002), 0) != 0x8) |
4888 | return false0; |
4889 | else |
4890 | return true1; |
4891 | } |
4892 | |
4893 | static int gfx_v8_0_wait_for_rlc_idle(void *handle) |
4894 | { |
4895 | unsigned int i; |
4896 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4897 | |
4898 | for (i = 0; i < adev->usec_timeout; i++) { |
4899 | if (gfx_v8_0_rlc_is_idle(handle)) |
4900 | return 0; |
4901 | |
4902 | udelay(1); |
4903 | } |
4904 | return -ETIMEDOUT60; |
4905 | } |
4906 | |
4907 | static int gfx_v8_0_wait_for_idle(void *handle) |
4908 | { |
4909 | unsigned int i; |
4910 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4911 | |
4912 | for (i = 0; i < adev->usec_timeout; i++) { |
4913 | if (gfx_v8_0_is_idle(handle)) |
4914 | return 0; |
4915 | |
4916 | udelay(1); |
4917 | } |
4918 | return -ETIMEDOUT60; |
4919 | } |
4920 | |
4921 | static int gfx_v8_0_hw_fini(void *handle) |
4922 | { |
4923 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4924 | |
4925 | amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); |
4926 | amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); |
4927 | |
4928 | amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); |
4929 | |
4930 | amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); |
4931 | |
4932 | /* disable KCQ to avoid CPC touch memory not valid anymore */ |
4933 | gfx_v8_0_kcq_disable(adev); |
4934 | |
4935 | if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
4936 | pr_debug("For SRIOV client, shouldn't do anything.\n")do { } while(0); |
4937 | return 0; |
4938 | } |
4939 | amdgpu_gfx_rlc_enter_safe_mode(adev); |
4940 | if (!gfx_v8_0_wait_for_idle(adev)) |
4941 | gfx_v8_0_cp_enable(adev, false0); |
4942 | else |
4943 | pr_err("cp is busy, skip halt cp\n")printk("\0013" "amdgpu: " "cp is busy, skip halt cp\n"); |
4944 | if (!gfx_v8_0_wait_for_rlc_idle(adev)) |
4945 | adev->gfx.rlc.funcs->stop(adev); |
4946 | else |
4947 | pr_err("rlc is busy, skip halt rlc\n")printk("\0013" "amdgpu: " "rlc is busy, skip halt rlc\n"); |
4948 | amdgpu_gfx_rlc_exit_safe_mode(adev); |
4949 | |
4950 | return 0; |
4951 | } |
4952 | |
4953 | static int gfx_v8_0_suspend(void *handle) |
4954 | { |
4955 | return gfx_v8_0_hw_fini(handle); |
4956 | } |
4957 | |
4958 | static int gfx_v8_0_resume(void *handle) |
4959 | { |
4960 | return gfx_v8_0_hw_init(handle); |
4961 | } |
4962 | |
4963 | static bool_Bool gfx_v8_0_check_soft_reset(void *handle) |
4964 | { |
4965 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
4966 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; |
4967 | u32 tmp; |
4968 | |
4969 | /* GRBM_STATUS */ |
4970 | tmp = RREG32(mmGRBM_STATUS)amdgpu_device_rreg(adev, (0x2004), 0); |
4971 | if (tmp & (GRBM_STATUS__PA_BUSY_MASK0x2000000 | GRBM_STATUS__SC_BUSY_MASK0x1000000 | |
4972 | GRBM_STATUS__BCI_BUSY_MASK0x800000 | GRBM_STATUS__SX_BUSY_MASK0x100000 | |
4973 | GRBM_STATUS__TA_BUSY_MASK0x4000 | GRBM_STATUS__VGT_BUSY_MASK0x20000 | |
4974 | GRBM_STATUS__DB_BUSY_MASK0x4000000 | GRBM_STATUS__CB_BUSY_MASK0x40000000 | |
4975 | GRBM_STATUS__GDS_BUSY_MASK0x8000 | GRBM_STATUS__SPI_BUSY_MASK0x400000 | |
4976 | GRBM_STATUS__IA_BUSY_MASK0x80000 | GRBM_STATUS__IA_BUSY_NO_DMA_MASK0x40000 | |
4977 | GRBM_STATUS__CP_BUSY_MASK0x20000000 | GRBM_STATUS__CP_COHERENCY_BUSY_MASK0x10000000)) { |
4978 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x1) | (0x1 & ((1) << 0x0 ))) |
4979 | GRBM_SOFT_RESET, SOFT_RESET_CP, 1)(((grbm_soft_reset) & ~0x1) | (0x1 & ((1) << 0x0 ))); |
4980 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x10000) | (0x10000 & ((1) << 0x10))) |
4981 | GRBM_SOFT_RESET, SOFT_RESET_GFX, 1)(((grbm_soft_reset) & ~0x10000) | (0x10000 & ((1) << 0x10))); |
4982 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,(((srbm_soft_reset) & ~0x100) | (0x100 & ((1) << 0x8))) |
4983 | SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1)(((srbm_soft_reset) & ~0x100) | (0x100 & ((1) << 0x8))); |
4984 | } |
4985 | |
4986 | /* GRBM_STATUS2 */ |
4987 | tmp = RREG32(mmGRBM_STATUS2)amdgpu_device_rreg(adev, (0x2002), 0); |
4988 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)(((tmp) & 0x1000000) >> 0x18)) |
4989 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x4) | (0x4 & ((1) << 0x2 ))) |
4990 | GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)(((grbm_soft_reset) & ~0x4) | (0x4 & ((1) << 0x2 ))); |
4991 | |
4992 | if (REG_GET_FIELD(tmp, GRBM_STATUS2, CPF_BUSY)(((tmp) & 0x10000000) >> 0x1c) || |
4993 | REG_GET_FIELD(tmp, GRBM_STATUS2, CPC_BUSY)(((tmp) & 0x20000000) >> 0x1d) || |
4994 | REG_GET_FIELD(tmp, GRBM_STATUS2, CPG_BUSY)(((tmp) & 0x40000000) >> 0x1e)) { |
4995 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x20000) | (0x20000 & ((1) << 0x11))) |
4996 | SOFT_RESET_CPF, 1)(((grbm_soft_reset) & ~0x20000) | (0x20000 & ((1) << 0x11))); |
4997 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x40000) | (0x40000 & ((1) << 0x12))) |
4998 | SOFT_RESET_CPC, 1)(((grbm_soft_reset) & ~0x40000) | (0x40000 & ((1) << 0x12))); |
4999 | grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x80000) | (0x80000 & ((1) << 0x13))) |
5000 | SOFT_RESET_CPG, 1)(((grbm_soft_reset) & ~0x80000) | (0x80000 & ((1) << 0x13))); |
5001 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,(((srbm_soft_reset) & ~0x100) | (0x100 & ((1) << 0x8))) |
5002 | SOFT_RESET_GRBM, 1)(((srbm_soft_reset) & ~0x100) | (0x100 & ((1) << 0x8))); |
5003 | } |
5004 | |
5005 | /* SRBM_STATUS */ |
5006 | tmp = RREG32(mmSRBM_STATUS)amdgpu_device_rreg(adev, (0x394), 0); |
5007 | if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING)(((tmp) & 0x20) >> 0x5)) |
5008 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,(((srbm_soft_reset) & ~0x100) | (0x100 & ((1) << 0x8))) |
5009 | SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1)(((srbm_soft_reset) & ~0x100) | (0x100 & ((1) << 0x8))); |
5010 | if (REG_GET_FIELD(tmp, SRBM_STATUS, SEM_BUSY)(((tmp) & 0x4000) >> 0xe)) |
5011 | srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,(((srbm_soft_reset) & ~0x8000) | (0x8000 & ((1) << 0xf))) |
5012 | SRBM_SOFT_RESET, SOFT_RESET_SEM, 1)(((srbm_soft_reset) & ~0x8000) | (0x8000 & ((1) << 0xf))); |
5013 | |
5014 | if (grbm_soft_reset || srbm_soft_reset) { |
5015 | adev->gfx.grbm_soft_reset = grbm_soft_reset; |
5016 | adev->gfx.srbm_soft_reset = srbm_soft_reset; |
5017 | return true1; |
5018 | } else { |
5019 | adev->gfx.grbm_soft_reset = 0; |
5020 | adev->gfx.srbm_soft_reset = 0; |
5021 | return false0; |
5022 | } |
5023 | } |
5024 | |
5025 | static int gfx_v8_0_pre_soft_reset(void *handle) |
5026 | { |
5027 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
5028 | u32 grbm_soft_reset = 0; |
5029 | |
5030 | if ((!adev->gfx.grbm_soft_reset) && |
5031 | (!adev->gfx.srbm_soft_reset)) |
5032 | return 0; |
5033 | |
5034 | grbm_soft_reset = adev->gfx.grbm_soft_reset; |
5035 | |
5036 | /* stop the rlc */ |
5037 | adev->gfx.rlc.funcs->stop(adev); |
5038 | |
5039 | if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP)(((grbm_soft_reset) & 0x1) >> 0x0) || |
5040 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_GFX)(((grbm_soft_reset) & 0x10000) >> 0x10)) |
5041 | /* Disable GFX parsing/prefetching */ |
5042 | gfx_v8_0_cp_gfx_enable(adev, false0); |
5043 | |
5044 | if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP)(((grbm_soft_reset) & 0x1) >> 0x0) || |
5045 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF)(((grbm_soft_reset) & 0x20000) >> 0x11) || |
5046 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC)(((grbm_soft_reset) & 0x40000) >> 0x12) || |
5047 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)(((grbm_soft_reset) & 0x80000) >> 0x13)) { |
5048 | int i; |
5049 | |
5050 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
5051 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
5052 | |
5053 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
5054 | vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
5055 | gfx_v8_0_deactivate_hqd(adev, 2); |
5056 | vi_srbm_select(adev, 0, 0, 0, 0); |
5057 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |
5058 | } |
5059 | /* Disable MEC parsing/prefetching */ |
5060 | gfx_v8_0_cp_compute_enable(adev, false0); |
5061 | } |
5062 | |
5063 | return 0; |
5064 | } |
5065 | |
5066 | static int gfx_v8_0_soft_reset(void *handle) |
5067 | { |
5068 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
5069 | u32 grbm_soft_reset = 0, srbm_soft_reset = 0; |
5070 | u32 tmp; |
5071 | |
5072 | if ((!adev->gfx.grbm_soft_reset) && |
5073 | (!adev->gfx.srbm_soft_reset)) |
5074 | return 0; |
5075 | |
5076 | grbm_soft_reset = adev->gfx.grbm_soft_reset; |
5077 | srbm_soft_reset = adev->gfx.srbm_soft_reset; |
5078 | |
5079 | if (grbm_soft_reset || srbm_soft_reset) { |
5080 | tmp = RREG32(mmGMCON_DEBUG)amdgpu_device_rreg(adev, (0xd5f), 0); |
5081 | tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 1)(((tmp) & ~0x1) | (0x1 & ((1) << 0x0))); |
5082 | tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 1)(((tmp) & ~0x2) | (0x2 & ((1) << 0x1))); |
5083 | WREG32(mmGMCON_DEBUG, tmp)amdgpu_device_wreg(adev, (0xd5f), (tmp), 0); |
5084 | udelay(50); |
5085 | } |
5086 | |
5087 | if (grbm_soft_reset) { |
5088 | tmp = RREG32(mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x2008), 0); |
5089 | tmp |= grbm_soft_reset; |
5090 | dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0); |
5091 | WREG32(mmGRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x2008), (tmp), 0); |
5092 | tmp = RREG32(mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x2008), 0); |
5093 | |
5094 | udelay(50); |
5095 | |
5096 | tmp &= ~grbm_soft_reset; |
5097 | WREG32(mmGRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x2008), (tmp), 0); |
5098 | tmp = RREG32(mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x2008), 0); |
5099 | } |
5100 | |
5101 | if (srbm_soft_reset) { |
5102 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
5103 | tmp |= srbm_soft_reset; |
5104 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0); |
5105 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); |
5106 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
5107 | |
5108 | udelay(50); |
5109 | |
5110 | tmp &= ~srbm_soft_reset; |
5111 | WREG32(mmSRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, (0x398), (tmp), 0); |
5112 | tmp = RREG32(mmSRBM_SOFT_RESET)amdgpu_device_rreg(adev, (0x398), 0); |
5113 | } |
5114 | |
5115 | if (grbm_soft_reset || srbm_soft_reset) { |
5116 | tmp = RREG32(mmGMCON_DEBUG)amdgpu_device_rreg(adev, (0xd5f), 0); |
5117 | tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_STALL, 0)(((tmp) & ~0x1) | (0x1 & ((0) << 0x0))); |
5118 | tmp = REG_SET_FIELD(tmp, GMCON_DEBUG, GFX_CLEAR, 0)(((tmp) & ~0x2) | (0x2 & ((0) << 0x1))); |
5119 | WREG32(mmGMCON_DEBUG, tmp)amdgpu_device_wreg(adev, (0xd5f), (tmp), 0); |
5120 | } |
5121 | |
5122 | /* Wait a little for things to settle down */ |
5123 | udelay(50); |
5124 | |
5125 | return 0; |
5126 | } |
5127 | |
5128 | static int gfx_v8_0_post_soft_reset(void *handle) |
5129 | { |
5130 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
5131 | u32 grbm_soft_reset = 0; |
5132 | |
5133 | if ((!adev->gfx.grbm_soft_reset) && |
5134 | (!adev->gfx.srbm_soft_reset)) |
5135 | return 0; |
5136 | |
5137 | grbm_soft_reset = adev->gfx.grbm_soft_reset; |
5138 | |
5139 | if (REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CP)(((grbm_soft_reset) & 0x1) >> 0x0) || |
5140 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPF)(((grbm_soft_reset) & 0x20000) >> 0x11) || |
5141 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPC)(((grbm_soft_reset) & 0x40000) >> 0x12) || |
5142 | REG_GET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET, SOFT_RESET_CPG)(((grbm_soft_reset) & 0x80000) >> 0x13)) { |
5143 | int i; |
5144 | |
5145 | for (i = 0; i < adev->gfx.num_compute_rings; i++) { |
5146 | struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; |
5147 | |
5148 | mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex); |
5149 | vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0); |
5150 | gfx_v8_0_deactivate_hqd(adev, 2); |
5151 | vi_srbm_select(adev, 0, 0, 0, 0); |
5152 | mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex); |