Bug Summary

File:dev/pci/drm/amd/amdgpu/gfx_v10_0.c
Warning:line 3708, column 52
Access to field 'data' results in a dereference of a null pointer (loaded from field 'pfp_fw')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name gfx_v10_0.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c

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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "amdgpu.h"
30#include "amdgpu_gfx.h"
31#include "amdgpu_psp.h"
32#include "amdgpu_smu.h"
33#include "nv.h"
34#include "nvd.h"
35
36#include "gc/gc_10_1_0_offset.h"
37#include "gc/gc_10_1_0_sh_mask.h"
38#include "smuio/smuio_11_0_0_offset.h"
39#include "smuio/smuio_11_0_0_sh_mask.h"
40#include "navi10_enum.h"
41#include "hdp/hdp_5_0_0_offset.h"
42#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
43
44#include "soc15.h"
45#include "soc15d.h"
46#include "soc15_common.h"
47#include "clearstate_gfx10.h"
48#include "v10_structs.h"
49#include "gfx_v10_0.h"
50#include "nbio_v2_3.h"
51
52/**
53 * Navi10 has two graphic rings to share each graphic pipe.
54 * 1. Primary ring
55 * 2. Async ring
56 */
57#define GFX10_NUM_GFX_RINGS_NV1X1 1
58#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid1 1
59#define GFX10_MEC_HPD_SIZE2048 2048
60
61#define F32_CE_PROGRAM_RAM_SIZE65536 65536
62#define RLCG_UCODE_LOADING_START_ADDRESS0x00002000L 0x00002000L
63
64#define mmCGTT_GS_NGG_CLK_CTRL0x5087 0x5087
65#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX1 1
66#define mmCGTT_SPI_RA0_CLK_CTRL0x507a 0x507a
67#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX1 1
68#define mmCGTT_SPI_RA1_CLK_CTRL0x507b 0x507b
69#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX1 1
70
71#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT0x8 0x8
72#define GB_ADDR_CONFIG__NUM_PKRS_MASK0x00000700L 0x00000700L
73
74#define mmCP_MEC_CNTL_Sienna_Cichlid0x0f55 0x0f55
75#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX0 0
76#define mmRLC_SAFE_MODE_Sienna_Cichlid0x4ca0 0x4ca0
77#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX1 1
78#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid0x4ca1 0x4ca1
79#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX1 1
80#define mmSPI_CONFIG_CNTL_Sienna_Cichlid0x11ec 0x11ec
81#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX0 0
82#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid0x0fc1 0x0fc1
83#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX0 0
84#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid0x0fc2 0x0fc2
85#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX0 0
86#define mmVGT_TF_RING_SIZE_Sienna_Cichlid0x0fc3 0x0fc3
87#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX0 0
88#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid0x0fc4 0x0fc4
89#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX0 0
90#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid0x0fc5 0x0fc5
91#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX0 0
92#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid0x0fc6 0x0fc6
93#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX0 0
94#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT0x1a 0x1a
95#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK0x04000000L 0x04000000L
96#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK0x00000FFCL 0x00000FFCL
97#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT0x2 0x2
98#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK0x00000FFCL 0x00000FFCL
99#define mmGCR_GENERAL_CNTL_Sienna_Cichlid0x1580 0x1580
100#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX0 0
101
102#define mmCP_HYP_PFP_UCODE_ADDR0x5814 0x5814
103#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX1 1
104#define mmCP_HYP_PFP_UCODE_DATA0x5815 0x5815
105#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX1 1
106#define mmCP_HYP_CE_UCODE_ADDR0x5818 0x5818
107#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX1 1
108#define mmCP_HYP_CE_UCODE_DATA0x5819 0x5819
109#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX1 1
110#define mmCP_HYP_ME_UCODE_ADDR0x5816 0x5816
111#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX1 1
112#define mmCP_HYP_ME_UCODE_DATA0x5817 0x5817
113#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX1 1
114
115//CC_GC_SA_UNIT_DISABLE
116#define mmCC_GC_SA_UNIT_DISABLE0x0fe9 0x0fe9
117#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX0 0
118#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8 0x8
119#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L 0x0000FF00L
120//GC_USER_SA_UNIT_DISABLE
121#define mmGC_USER_SA_UNIT_DISABLE0x0fea 0x0fea
122#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX0 0
123#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8 0x8
124#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L 0x0000FF00L
125//PA_SC_ENHANCE_3
126#define mmPA_SC_ENHANCE_30x1085 0x1085
127#define mmPA_SC_ENHANCE_3_BASE_IDX0 0
128#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT0x3 0x3
129#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK0x00000008L 0x00000008L
130
131#define mmCGTT_SPI_CS_CLK_CTRL0x507c 0x507c
132#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX1 1
133
134MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
135MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
136MODULE_FIRMWARE("amdgpu/navi10_me.bin");
137MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
138MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
139MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
140
141MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
142MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
143MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
144MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
145MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
146MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
147MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
148MODULE_FIRMWARE("amdgpu/navi14_me.bin");
149MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
150MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
151MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
152
153MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
154MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
155MODULE_FIRMWARE("amdgpu/navi12_me.bin");
156MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
157MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
158MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
159
160MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
161MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
162MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
163MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
164MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
165MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
166
167MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
168MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
169MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
170MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
171MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
172MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
173
174static const struct soc15_reg_golden golden_settings_gc_10_1[] =
175{
176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014){ GC_HWIP, 0, 0, 0x1422, 0xffffffff, 0x00400014 },
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100){ GC_HWIP, 0, 1, 0x50b1, 0xfcff8fff, 0xf8000100 },
178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100){ GC_HWIP, 0, 1, 0x5080, 0xcd000000, 0x0d000100 },
179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100){ GC_HWIP, 0, 1, 0x508c, 0x60000ff0, 0x60000100 },
180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100){ GC_HWIP, 0, 1, 0x508d, 0x40000000, 0x40000100 },
181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5084, 0xffff8fff, 0xffff8100 },
182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100){ GC_HWIP, 0, 1, 0x5086, 0xfeff8fff, 0xfeff8100 },
183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xe4e4e4e4 },
184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000){ GC_HWIP, 0, 1, 0x2d94, 0x00000002, 0x00000000 },
185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x000007ff, 0x000005ff },
186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0x20000000, 0x20000000 },
187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420){ GC_HWIP, 0, 0, 0x13ad, 0xffffffff, 0x00000420 },
188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0x00000200, 0x00000200 },
189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000){ GC_HWIP, 0, 0, 0x13af, 0x07900000, 0x04900000 },
190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f){ GC_HWIP, 0, 0, 0x13d2, 0x0000ffff, 0x0000003f },
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860204 },
192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1583, 0x1ff0ffff, 0x00000500 },
193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe){ GC_HWIP, 0, 0, 0x1004, 0x000007ff, 0x000001fe },
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d10, 0xffffffff, 0xe4e4e4e4 },
195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x10321032 },
196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x02310231 },
197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0x10000000, 0x10000100 },
200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f){ GC_HWIP, 0, 1, 0x2e01, 0xffffffff, 0x1402002f },
201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188){ GC_HWIP, 0, 1, 0x2e0c, 0xffff9fff, 0x00001188 },
202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x3fffffff, 0x08000009 },
204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000){ GC_HWIP, 0, 0, 0x109d, 0x00400000, 0x04440000 },
205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000800, 0x00000820 },
206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffffffff, 0xffff3101 },
208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0x001f0000, 0x00070104 },
209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x508e, 0xffffffff, 0xffffffff },
210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000100, 0x00000130 },
211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010){ GC_HWIP, 0, 0, 0x18a2, 0x60000010, 0x479c0010 },
214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100){ GC_HWIP, 0, 1, 0x50c3, 0xfeff0fff, 0x40000100 },
215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000){ GC_HWIP, 0, 0, 0x1588, 0x00c00000, 0x00c00000 }
216};
217
218static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
219{
220 /* Pending on emulation bring up */
221};
222
223static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
224{
225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xe0000000, 0x0 },
226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x28 },
228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x20 },
240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc8 },
244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xcc },
248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd0 },
252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd4 },
256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4 },
268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8 },
272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x0 },
276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x88 },
288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8c },
292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb0 },
296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb4 },
300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb8 },
304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xbc },
308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc0 },
312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc4 },
316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x90 },
320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x94 },
324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x98 },
328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x9c },
332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa0 },
336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa4 },
340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa8 },
344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xac },
348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x10 },
352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc },
356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x18 },
360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x38 },
364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x3c },
368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x40 },
372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x44 },
376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x48 },
380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4c },
384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x70 },
388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x74 },
392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x78 },
396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x7c },
400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x80 },
404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x84 },
408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x50 },
412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x54 },
416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x58 },
420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x5c },
424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x60 },
428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x64 },
432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x68 },
436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x6c },
440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x1c },
444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x14 },
448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x12 },
450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1 },
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1 },
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x30 },
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x34 },
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x2c },
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19){ GC_HWIP, 0, 1, 0x3c8c, 0x000000FF, 0x19 },
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20){ GC_HWIP, 0, 1, 0x3c8d, 0x000000FF, 0x20 },
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x5 },
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0xa },
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x14 },
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x19 },
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33){ GC_HWIP, 0, 1, 0x3c8b, 0x000000FF, 0x33 },
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xFFFFFFFF, 0xe0000000 }
1277};
1278
1279static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1280{
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014){ GC_HWIP, 0, 0, 0x1422, 0xffffffff, 0x003c0014 },
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5087, 0xffff8fff, 0xffff8100 },
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100){ GC_HWIP, 0, 1, 0x5085, 0xffff0fff, 0xffff0100 },
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100){ GC_HWIP, 0, 1, 0x5080, 0xcd000000, 0x0d000100 },
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100){ GC_HWIP, 0, 1, 0x508c, 0xf8ff0fff, 0x60000100 },
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100){ GC_HWIP, 0, 1, 0x508d, 0x40000ff0, 0x40000100 },
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5084, 0xffff8fff, 0xffff8100 },
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5086, 0xffff8fff, 0xffff8100 },
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xe4e4e4e4 },
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000){ GC_HWIP, 0, 1, 0x2d94, 0x00000002, 0x00000000 },
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x800007ff, 0x000005ff },
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0xffffffff, 0x20000000 },
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420){ GC_HWIP, 0, 0, 0x13ad, 0xffffffff, 0x00000420 },
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0x00000200, 0x00000200 },
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x04900000 },
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f){ GC_HWIP, 0, 0, 0x13d2, 0x0000ffff, 0x0000003f },
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860204 },
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1583, 0x1ff0ffff, 0x00000500 },
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe){ GC_HWIP, 0, 0, 0x1004, 0x000007ff, 0x000001fe },
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d10, 0xffffffff, 0xe4e4e4e4 },
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffe7 },
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffe7 },
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0xffff0fff, 0x10000100 },
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f){ GC_HWIP, 0, 1, 0x2e01, 0xffffffff, 0x1402002f },
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188){ GC_HWIP, 0, 1, 0x2e0c, 0xffffbfff, 0x00000188 },
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x3fffffff, 0x08000009 },
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000){ GC_HWIP, 0, 0, 0x109d, 0x00400000, 0x04440000 },
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000800, 0x00000820 },
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffffffff, 0xffff3101 },
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105){ GC_HWIP, 0, 0, 0x11ef, 0x001f0000, 0x00070105 },
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x508e, 0xffffffff, 0xffffffff },
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000133, 0x00000130 },
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010){ GC_HWIP, 0, 0, 0x18a2, 0x60000010, 0x479c0010 },
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000){ GC_HWIP, 0, 0, 0x1588, 0x00c00000, 0x00c00000 },
1319};
1320
1321static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1322{
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014){ GC_HWIP, 0, 0, 0x1422, 0x003e001f, 0x003c0014 },
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5087, 0xffff8fff, 0xffff8100 },
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100){ GC_HWIP, 0, 1, 0x5085, 0xffff0fff, 0xffff0100 },
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100){ GC_HWIP, 0, 1, 0x5080, 0xff7f0fff, 0x0d000100 },
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100){ GC_HWIP, 0, 1, 0x508c, 0xffffcfff, 0x60000100 },
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100){ GC_HWIP, 0, 1, 0x508d, 0xffff0fff, 0x40000100 },
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5084, 0xffff8fff, 0xffff8100 },
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5086, 0xffff8fff, 0xffff8100 },
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xe4e4e4e4 },
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000){ GC_HWIP, 0, 1, 0x2d94, 0x00000003, 0x00000000 },
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x800007ff, 0x000005ff },
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0xffffffff, 0x20000000 },
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420){ GC_HWIP, 0, 0, 0x13ad, 0xffffffff, 0x00000420 },
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000200 },
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x04900000 },
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f){ GC_HWIP, 0, 0, 0x13d2, 0x0000ffff, 0x0000003f },
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860204 },
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044){ GC_HWIP, 0, 0, 0x13de, 0x0c1800ff, 0x00000044 },
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1583, 0x1ff0ffff, 0x00000500 },
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe){ GC_HWIP, 0, 0, 0x1004, 0x00007fff, 0x000001fe },
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d10, 0xffffffff, 0xe4e4e4e4 },
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x10321032 },
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x02310231 },
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0xffff0fff, 0x10000100 },
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f){ GC_HWIP, 0, 1, 0x2e01, 0xffffffff, 0x1402002f },
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188){ GC_HWIP, 0, 1, 0x2e0c, 0xffffbfff, 0x00000188 },
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02){ GC_HWIP, 0, 0, 0x106c, 0xffffffff, 0x842a4c02 },
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x3fffffff, 0x08000009 },
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000){ GC_HWIP, 0, 0, 0x109d, 0xffffffff, 0x04440000 },
1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000820, 0x00000820 },
1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffffffff, 0xffff3101 },
1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0x001f0000, 0x00070104 },
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x508e, 0xffffffff, 0xffffffff },
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000133, 0x00000130 },
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010){ GC_HWIP, 0, 0, 0x18a2, 0xffdf80ff, 0x479c0010 },
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000){ GC_HWIP, 0, 0, 0x1588, 0xffffffff, 0x00c00000 }
1365};
1366
1367static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1368{
1369 static void *scratch_reg0;
1370 static void *scratch_reg1;
1371 static void *scratch_reg2;
1372 static void *scratch_reg3;
1373 static void *spare_int;
1374 static uint32_t grbm_cntl;
1375 static uint32_t grbm_idx;
1376 uint32_t i = 0;
1377 uint32_t retries = 50000;
1378
1379 scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX1] + mmSCRATCH_REG00x2040)*4;
1380 scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX1] + mmSCRATCH_REG10x2041)*4;
1381 scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX1] + mmSCRATCH_REG20x2042)*4;
1382 scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX1] + mmSCRATCH_REG30x2043)*4;
1383 spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX1] + mmRLC_SPARE_INT0x4ccc)*4;
1384
1385 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX0] + mmGRBM_GFX_CNTL0x0dc2;
1386 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX1] + mmGRBM_GFX_INDEX0x2200;
1387
1388 if (amdgpu_sriov_runtime(adev)((adev)->virt.caps & (1 << 4))) {
1389 pr_err("shouldn't call rlcg write register during runtime\n")printk("\0013" "amdgpu: " "shouldn't call rlcg write register during runtime\n"
);
1390 return;
1391 }
1392
1393 writel(v, scratch_reg0)iowrite32(v, scratch_reg0);
1394 writel(offset | 0x80000000, scratch_reg1)iowrite32(offset | 0x80000000, scratch_reg1);
1395 writel(1, spare_int)iowrite32(1, spare_int);
1396 for (i = 0; i < retries; i++) {
1397 u32 tmp;
1398
1399 tmp = readl(scratch_reg1)ioread32(scratch_reg1);
1400 if (!(tmp & 0x80000000))
1401 break;
1402
1403 udelay(10);
1404 }
1405
1406 if (i >= retries)
1407 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset)printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, offset);
1408}
1409
1410static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1411{
1412 /* Pending on emulation bring up */
1413};
1414
1415static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1416{
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xE0000000L, 0x0 },
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x28 },
1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x20 },
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x80 },
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x84 },
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x88 },
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8c },
1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4 },
1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8 },
1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x0 },
1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
1466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
1468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
1470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x60 },
1472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x64 },
1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x68 },
1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x6c },
1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x70 },
1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x74 },
1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x78 },
1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x7c },
1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x10 },
1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc },
1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x18 },
1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x38 },
1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x3c },
1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x40 },
1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x44 },
1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x48 },
1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4c },
1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x50 },
1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x54 },
1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x58 },
1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x5c },
1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x1c },
1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x14 },
1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe4 },
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1a0 },
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1a4 },
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1b0 },
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1b4 },
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1a8 },
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1ac },
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1b8 },
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1bc },
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1c8 },
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1cc },
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1c0 },
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1c4 },
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x30 },
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x34 },
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x2c },
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26){ GC_HWIP, 0, 1, 0x3c8c, 0x000000FF, 0x26 },
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28){ GC_HWIP, 0, 1, 0x3c8d, 0x000000FF, 0x28 },
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0xf },
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x15 },
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x1f },
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x25 },
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b){ GC_HWIP, 0, 1, 0x3c8b, 0x000000FF, 0x3b },
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xFFFFFFFF, 0xe0000000 }
2037};
2038
2039static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2040{
2041 /* Pending on emulation bring up */
2042};
2043
2044static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2045{
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xe0000000L, 0x0 },
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x28 },
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x20 },
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc8 },
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xcc },
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd0 },
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd4 },
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4 },
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8 },
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x0 },
2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x88 },
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8c },
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb0 },
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb4 },
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb8 },
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xbc },
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc0 },
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc4 },
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x90 },
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x94 },
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x1 },
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x98 },
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x9c },
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa0 },
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x1 },
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa4 },
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa8 },
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xac },
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x10 },
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc },
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x18 },
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x38 },
2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x3c },
2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x40 },
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x44 },
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x48 },
2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4c },
2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x70 },
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x74 },
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x78 },
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x7c },
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x80 },
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x84 },
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x50 },
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x54 },
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x58 },
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x5c },
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x60 },
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x64 },
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x68 },
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x6c },
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x1c },
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x14 },
2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x30 },
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x34 },
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x2c },
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f){ GC_HWIP, 0, 1, 0x3c8c, 0x000000FF, 0x1f },
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22){ GC_HWIP, 0, 1, 0x3c8d, 0x000000FF, 0x22 },
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x1 },
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x6 },
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x10 },
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x15 },
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35){ GC_HWIP, 0, 1, 0x3c8b, 0x000000FF, 0x35 },
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xFFFFFFFF, 0xe0000000 }
3098};
3099
3100static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3101{
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0x78000000, 0x78000100 },
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507d, 0xff7f0fff, 0x78000100 },
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0xff7f0fff, 0x30000100 },
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0xff7f0fff, 0x7e000100 },
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c000 },
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000){ GC_HWIP, 0, 0, 0x13bf, 0x7fff0f1f, 0x00b80000 },
3110 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100){ GC_HWIP, 0, 0, 0x189b, 0xffffffff, 0x10100100 },
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088){ GC_HWIP, 0, 0, 0x189c, 0xffffffff, 0x17000088 },
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400){ GC_HWIP, 0, 0, 0x0fe5, 0x003fffff, 0x00280400 },
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x10f80988 },
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x00000020, 0x00000020 },
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0xffffffff, 0x00070104 },
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070){ GC_HWIP, 0, 0, 0x10a0, 0xe07df47f, 0x00180070 },
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c0, 0xf0f001ff, 0x00000000 },
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c1, 0xf0f001ff, 0x00000000 },
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ca, 0xf0f001ff, 0x00000000 },
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cb, 0xf0f001ff, 0x00000000 },
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cc, 0xf0f001ff, 0x00000000 },
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cd, 0xf0f001ff, 0x00000000 },
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ce, 0xf0f001ff, 0x00000000 },
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cf, 0xf0f001ff, 0x00000000 },
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c2, 0xf0f001ff, 0x00000000 },
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c3, 0xf0f001ff, 0x00000000 },
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c4, 0xf0f001ff, 0x00000000 },
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c5, 0xf0f001ff, 0x00000000 },
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c6, 0xf0f001ff, 0x00000000 },
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c7, 0xf0f001ff, 0x00000000 },
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c8, 0xf0f001ff, 0x00000000 },
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c9, 0xf0f001ff, 0x00000000 },
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020){ GC_HWIP, 0, 0, 0x11b8, 0x00010000, 0x00010020 },
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000){ GC_HWIP, 0, 0, 0x1588, 0xffbfffff, 0x00a00000 }
3143};
3144
3145static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3146{
3147 /* Pending on emulation bring up */
3148};
3149
3150static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3151{
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507d, 0xff7f0fff, 0x78000100 },
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0xff7f0fff, 0x30000100 },
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0xff7f0fff, 0x7e000100 },
3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c000 },
3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000){ GC_HWIP, 0, 0, 0x13bf, 0x7fff0f1f, 0x00b80000 },
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400){ GC_HWIP, 0, 0, 0x0fe5, 0x003fffff, 0x00280400 },
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0xffffffff, 0x00070104 },
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004){ GC_HWIP, 0, 0, 0x11db, 0x000000ff, 0x00000004 },
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070){ GC_HWIP, 0, 0, 0x10a0, 0xe07df47f, 0x00180070 },
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c0, 0xf0f001ff, 0x00000000 },
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c1, 0xf0f001ff, 0x00000000 },
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ca, 0xf0f001ff, 0x00000000 },
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cb, 0xf0f001ff, 0x00000000 },
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cc, 0xf0f001ff, 0x00000000 },
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cd, 0xf0f001ff, 0x00000000 },
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ce, 0xf0f001ff, 0x00000000 },
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cf, 0xf0f001ff, 0x00000000 },
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c2, 0xf0f001ff, 0x00000000 },
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c3, 0xf0f001ff, 0x00000000 },
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c4, 0xf0f001ff, 0x00000000 },
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c5, 0xf0f001ff, 0x00000000 },
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c6, 0xf0f001ff, 0x00000000 },
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c7, 0xf0f001ff, 0x00000000 },
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c8, 0xf0f001ff, 0x00000000 },
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c9, 0xf0f001ff, 0x00000000 },
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000){ GC_HWIP, 0, 0, 0x1588, 0xffbfffff, 0x00a00000 },
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff){ GC_HWIP, 0, 0, 0x1009, 0x00000fff, 0x000003ff }
3190};
3191
3192#define DEFAULT_SH_MEM_CONFIG((SH_MEM_ADDRESS_MODE_64 << 0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED
<< 0x2) | (SH_MEM_RETRY_MODE_ALL << 0xc) | (3 <<
0xe)) \
3193 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT0x0) | \
3194 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT0x2) | \
3195 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT0xc) | \
3196 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT0xe))
3197
3198
3199static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3200static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3201static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3202static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3203static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3204 struct amdgpu_cu_info *cu_info);
3205static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3206static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3207 u32 sh_num, u32 instance);
3208static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3209
3210static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3211static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3212static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3213static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3214static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool_Bool resume);
3215static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool_Bool resume);
3216static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool_Bool start, bool_Bool secure);
3217static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3218static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3219
3220static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3221{
3222 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)((3 << 30) | (((0xA0) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
3223 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0)((0) << 0) |
3224 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)((0) << 29)); /* vmid_mask:0 queue_type:0 (KIQ) */
3225 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)((u32)(queue_mask))); /* queue mask lo */
3226 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)((u32)(((queue_mask) >> 16) >> 16))); /* queue mask hi */
3227 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3228 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3229 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3230 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3231}
3232
3233static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3234 struct amdgpu_ring *ring)
3235{
3236 struct amdgpu_device *adev = kiq_ring->adev;
3237 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3238 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3239 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3240
3241 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)((3 << 30) | (((0xA2) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
3242 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3243 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3244 PACKET3_MAP_QUEUES_QUEUE_SEL(0)((0) << 4) | /* Queue_Sel */
3245 PACKET3_MAP_QUEUES_VMID(0)((0) << 8) | /* VMID */
3246 PACKET3_MAP_QUEUES_QUEUE(ring->queue)((ring->queue) << 13) |
3247 PACKET3_MAP_QUEUES_PIPE(ring->pipe)((ring->pipe) << 16) |
3248 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1))(((ring->me == 1 ? 0 : 1)) << 18) |
3249 PACKET3_MAP_QUEUES_QUEUE_TYPE(0)((0) << 21) | /*queue_type: normal compute queue */
3250 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0)((0) << 24) | /* alloc format: all_on_one_pipe */
3251 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) |
3252 PACKET3_MAP_QUEUES_NUM_QUEUES(1)((1) << 29)); /* num_queues: must be 1 */
3253 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2));
3254 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)((u32)(mqd_addr)));
3255 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)((u32)(((mqd_addr) >> 16) >> 16)));
3256 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)((u32)(wptr_addr)));
3257 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)((u32)(((wptr_addr) >> 16) >> 16)));
3258}
3259
3260static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3261 struct amdgpu_ring *ring,
3262 enum amdgpu_unmap_queues_action action,
3263 u64 gpu_addr, u64 seq)
3264{
3265 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3266
3267 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)((3 << 30) | (((0xA3) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
3268 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3269 PACKET3_UNMAP_QUEUES_ACTION(action)((action) << 0) |
3270 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0)((0) << 4) |
3271 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) |
3272 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)((1) << 29));
3273 amdgpu_ring_write(kiq_ring,
3274 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)((ring->doorbell_index) << 2));
3275
3276 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3277 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)((u32)(gpu_addr)));
3278 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)));
3279 amdgpu_ring_write(kiq_ring, seq);
3280 } else {
3281 amdgpu_ring_write(kiq_ring, 0);
3282 amdgpu_ring_write(kiq_ring, 0);
3283 amdgpu_ring_write(kiq_ring, 0);
3284 }
3285}
3286
3287static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3288 struct amdgpu_ring *ring,
3289 u64 addr,
3290 u64 seq)
3291{
3292 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3293
3294 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)((3 << 30) | (((0xA4) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
3295 amdgpu_ring_write(kiq_ring,
3296 PACKET3_QUERY_STATUS_CONTEXT_ID(0)((0) << 0) |
3297 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0)((0) << 28) |
3298 PACKET3_QUERY_STATUS_COMMAND(2)((2) << 30));
3299 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3300 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2) |
3301 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)((eng_sel) << 25));
3302 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)((u32)(addr)));
3303 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
3304 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)((u32)(seq)));
3305 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
3306}
3307
3308static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3309 uint16_t pasid, uint32_t flush_type,
3310 bool_Bool all_hub)
3311{
3312 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)((3 << 30) | (((0x98) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
3313 amdgpu_ring_write(kiq_ring,
3314 PACKET3_INVALIDATE_TLBS_DST_SEL(1)((1) << 0) |
3315 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub)((all_hub) << 4) |
3316 PACKET3_INVALIDATE_TLBS_PASID(pasid)((pasid) << 5) |
3317 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)((flush_type) << 29));
3318}
3319
3320static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3321 .kiq_set_resources = gfx10_kiq_set_resources,
3322 .kiq_map_queues = gfx10_kiq_map_queues,
3323 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3324 .kiq_query_status = gfx10_kiq_query_status,
3325 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3326 .set_resources_size = 8,
3327 .map_queues_size = 7,
3328 .unmap_queues_size = 6,
3329 .query_status_size = 7,
3330 .invalidate_tlbs_size = 2,
3331};
3332
3333static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3334{
3335 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3336}
3337
3338static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3339{
3340 switch (adev->asic_type) {
3341 case CHIP_NAVI10:
3342 soc15_program_register_sequence(adev,
3343 golden_settings_gc_rlc_spm_10_0_nv10,
3344 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)(sizeof((golden_settings_gc_rlc_spm_10_0_nv10)) / sizeof((golden_settings_gc_rlc_spm_10_0_nv10
)[0])));
3345 break;
3346 case CHIP_NAVI14:
3347 soc15_program_register_sequence(adev,
3348 golden_settings_gc_rlc_spm_10_1_nv14,
3349 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)(sizeof((golden_settings_gc_rlc_spm_10_1_nv14)) / sizeof((golden_settings_gc_rlc_spm_10_1_nv14
)[0])));
3350 break;
3351 case CHIP_NAVI12:
3352 soc15_program_register_sequence(adev,
3353 golden_settings_gc_rlc_spm_10_1_2_nv12,
3354 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)(sizeof((golden_settings_gc_rlc_spm_10_1_2_nv12)) / sizeof((golden_settings_gc_rlc_spm_10_1_2_nv12
)[0])));
3355 break;
3356 default:
3357 break;
3358 }
3359}
3360
3361static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3362{
3363 switch (adev->asic_type) {
3364 case CHIP_NAVI10:
3365 soc15_program_register_sequence(adev,
3366 golden_settings_gc_10_1,
3367 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)(sizeof((golden_settings_gc_10_1)) / sizeof((golden_settings_gc_10_1
)[0])));
3368 soc15_program_register_sequence(adev,
3369 golden_settings_gc_10_0_nv10,
3370 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)(sizeof((golden_settings_gc_10_0_nv10)) / sizeof((golden_settings_gc_10_0_nv10
)[0])));
3371 break;
3372 case CHIP_NAVI14:
3373 soc15_program_register_sequence(adev,
3374 golden_settings_gc_10_1_1,
3375 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)(sizeof((golden_settings_gc_10_1_1)) / sizeof((golden_settings_gc_10_1_1
)[0])));
3376 soc15_program_register_sequence(adev,
3377 golden_settings_gc_10_1_nv14,
3378 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)(sizeof((golden_settings_gc_10_1_nv14)) / sizeof((golden_settings_gc_10_1_nv14
)[0])));
3379 break;
3380 case CHIP_NAVI12:
3381 soc15_program_register_sequence(adev,
3382 golden_settings_gc_10_1_2,
3383 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)(sizeof((golden_settings_gc_10_1_2)) / sizeof((golden_settings_gc_10_1_2
)[0])));
3384 soc15_program_register_sequence(adev,
3385 golden_settings_gc_10_1_2_nv12,
3386 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)(sizeof((golden_settings_gc_10_1_2_nv12)) / sizeof((golden_settings_gc_10_1_2_nv12
)[0])));
3387 break;
3388 case CHIP_SIENNA_CICHLID:
3389 soc15_program_register_sequence(adev,
3390 golden_settings_gc_10_3,
3391 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)(sizeof((golden_settings_gc_10_3)) / sizeof((golden_settings_gc_10_3
)[0])));
3392 soc15_program_register_sequence(adev,
3393 golden_settings_gc_10_3_sienna_cichlid,
3394 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)(sizeof((golden_settings_gc_10_3_sienna_cichlid)) / sizeof((golden_settings_gc_10_3_sienna_cichlid
)[0])));
3395 break;
3396 case CHIP_NAVY_FLOUNDER:
3397 soc15_program_register_sequence(adev,
3398 golden_settings_gc_10_3_2,
3399 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)(sizeof((golden_settings_gc_10_3_2)) / sizeof((golden_settings_gc_10_3_2
)[0])));
3400 break;
3401
3402 default:
3403 break;
3404 }
3405 gfx_v10_0_init_spm_golden_registers(adev);
3406}
3407
3408static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3409{
3410 adev->gfx.scratch.num_reg = 8;
3411 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0)(adev->reg_offset[GC_HWIP][0][1] + 0x2040);
3412 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3413}
12
←
Returning without writing to 'adev->asic_type', which participates in a condition later
→
13
←
Returning without writing to 'adev->gfx.pfp_fw'
→
3414
3415static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3416 bool_Bool wc, uint32_t reg, uint32_t val)
3417{
3418 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
3419 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel)((eng_sel) << 30) |
3420 WRITE_DATA_DST_SEL(0)((0) << 8) | (wc ? WR_CONFIRM(1 << 20) : 0));
3421 amdgpu_ring_write(ring, reg);
3422 amdgpu_ring_write(ring, 0);
3423 amdgpu_ring_write(ring, val);
3424}
3425
3426static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3427 int mem_space, int opt, uint32_t addr0,
3428 uint32_t addr1, uint32_t ref, uint32_t mask,
3429 uint32_t inv)
3430{
3431 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)((3 << 30) | (((0x3C) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
3432 amdgpu_ring_write(ring,
3433 /* memory (1) or register (0) */
3434 (WAIT_REG_MEM_MEM_SPACE(mem_space)((mem_space) << 4) |
3435 WAIT_REG_MEM_OPERATION(opt)((opt) << 6) | /* wait */
3436 WAIT_REG_MEM_FUNCTION(3)((3) << 0) | /* equal */
3437 WAIT_REG_MEM_ENGINE(eng_sel)((eng_sel) << 8)));
3438
3439 if (mem_space)
3440 BUG_ON(addr0 & 0x3)((!(addr0 & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 3440, "!(addr0 & 0x3)")); /* Dword align */
3441 amdgpu_ring_write(ring, addr0);
3442 amdgpu_ring_write(ring, addr1);
3443 amdgpu_ring_write(ring, ref);
3444 amdgpu_ring_write(ring, mask);
3445 amdgpu_ring_write(ring, inv); /* poll interval */
3446}
3447
3448static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3449{
3450 struct amdgpu_device *adev = ring->adev;
3451 uint32_t scratch;
3452 uint32_t tmp = 0;
3453 unsigned i;
3454 int r;
3455
3456 r = amdgpu_gfx_scratch_get(adev, &scratch);
3457 if (r) {
3458 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r)__drm_err("amdgpu: cp failed to get scratch reg (%d).\n", r);
3459 return r;
3460 }
3461
3462 WREG32(scratch, 0xCAFEDEAD)amdgpu_device_wreg(adev, (scratch), (0xCAFEDEAD), 0);
3463
3464 r = amdgpu_ring_alloc(ring, 3);
3465 if (r) {
3466 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",__drm_err("amdgpu: cp failed to lock ring %d (%d).\n", ring->
idx, r)
3467 ring->idx, r)__drm_err("amdgpu: cp failed to lock ring %d (%d).\n", ring->
idx, r);
3468 amdgpu_gfx_scratch_free(adev, scratch);
3469 return r;
3470 }
3471
3472 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
3473 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START0x0000c000));
3474 amdgpu_ring_write(ring, 0xDEADBEEF);
3475 amdgpu_ring_commit(ring);
3476
3477 for (i = 0; i < adev->usec_timeout; i++) {
3478 tmp = RREG32(scratch)amdgpu_device_rreg(adev, (scratch), 0);
3479 if (tmp == 0xDEADBEEF)
3480 break;
3481 if (amdgpu_emu_mode == 1)
3482 drm_msleep(1)mdelay(1);
3483 else
3484 udelay(1);
3485 }
3486
3487 if (i >= adev->usec_timeout)
3488 r = -ETIMEDOUT60;
3489
3490 amdgpu_gfx_scratch_free(adev, scratch);
3491
3492 return r;
3493}
3494
3495static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3496{
3497 struct amdgpu_device *adev = ring->adev;
3498 struct amdgpu_ib ib;
3499 struct dma_fence *f = NULL((void *)0);
3500 unsigned index;
3501 uint64_t gpu_addr;
3502 uint32_t tmp;
3503 long r;
3504
3505 r = amdgpu_device_wb_get(adev, &index);
3506 if (r)
3507 return r;
3508
3509 gpu_addr = adev->wb.gpu_addr + (index * 4);
3510 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD)((__uint32_t)(0xCAFEDEAD));
3511 memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
3512 r = amdgpu_ib_get(adev, NULL((void *)0), 16,
3513 AMDGPU_IB_POOL_DIRECT, &ib);
3514 if (r)
3515 goto err1;
3516
3517 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16);
3518 ib.ptr[1] = WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20);
3519 ib.ptr[2] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
3520 ib.ptr[3] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
3521 ib.ptr[4] = 0xDEADBEEF;
3522 ib.length_dw = 5;
3523
3524 r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
3525 if (r)
3526 goto err2;
3527
3528 r = dma_fence_wait_timeout(f, false0, timeout);
3529 if (r == 0) {
3530 r = -ETIMEDOUT60;
3531 goto err2;
3532 } else if (r < 0) {
3533 goto err2;
3534 }
3535
3536 tmp = adev->wb.wb[index];
3537 if (tmp == 0xDEADBEEF)
3538 r = 0;
3539 else
3540 r = -EINVAL22;
3541err2:
3542 amdgpu_ib_free(adev, &ib, NULL((void *)0));
3543 dma_fence_put(f);
3544err1:
3545 amdgpu_device_wb_free(adev, index);
3546 return r;
3547}
3548
3549static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3550{
3551 release_firmware(adev->gfx.pfp_fw);
3552 adev->gfx.pfp_fw = NULL((void *)0);
3553 release_firmware(adev->gfx.me_fw);
3554 adev->gfx.me_fw = NULL((void *)0);
3555 release_firmware(adev->gfx.ce_fw);
3556 adev->gfx.ce_fw = NULL((void *)0);
3557 release_firmware(adev->gfx.rlc_fw);
3558 adev->gfx.rlc_fw = NULL((void *)0);
3559 release_firmware(adev->gfx.mec_fw);
3560 adev->gfx.mec_fw = NULL((void *)0);
3561 release_firmware(adev->gfx.mec2_fw);
3562 adev->gfx.mec2_fw = NULL((void *)0);
3563
3564 kfree(adev->gfx.rlc.register_list_format);
3565}
3566
3567static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3568{
3569 adev->gfx.cp_fw_write_wait = false0;
3570
3571 switch (adev->asic_type) {
3572 case CHIP_NAVI10:
3573 case CHIP_NAVI12:
3574 case CHIP_NAVI14:
3575 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3576 (adev->gfx.me_feature_version >= 27) &&
3577 (adev->gfx.pfp_fw_version >= 0x00000068) &&
3578 (adev->gfx.pfp_feature_version >= 27) &&
3579 (adev->gfx.mec_fw_version >= 0x0000005b) &&
3580 (adev->gfx.mec_feature_version >= 27))
3581 adev->gfx.cp_fw_write_wait = true1;
3582 break;
3583 case CHIP_SIENNA_CICHLID:
3584 case CHIP_NAVY_FLOUNDER:
3585 adev->gfx.cp_fw_write_wait = true1;
3586 break;
3587 default:
3588 break;
3589 }
3590
3591 if (!adev->gfx.cp_fw_write_wait)
3592 DRM_WARN_ONCE("CP firmware version too old, please update!")({ static int __warned; if (!__warned) { printk("\0014" "[" "drm"
"] " "CP firmware version too old, please update!"); __warned
= 1; } });
3593}
3594
3595
3596static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3597{
3598 const struct rlc_firmware_header_v2_1 *rlc_hdr;
3599
3600 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3601 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver)((__uint32_t)(rlc_hdr->save_restore_list_cntl_ucode_ver));
3602 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver)((__uint32_t)(rlc_hdr->save_restore_list_cntl_feature_ver)
);
3603 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes)((__uint32_t)(rlc_hdr->save_restore_list_cntl_size_bytes));
3604 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes)((__uint32_t)(rlc_hdr->save_restore_list_cntl_offset_bytes
));
3605 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver)((__uint32_t)(rlc_hdr->save_restore_list_gpm_ucode_ver));
3606 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver)((__uint32_t)(rlc_hdr->save_restore_list_gpm_feature_ver));
3607 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes)((__uint32_t)(rlc_hdr->save_restore_list_gpm_size_bytes));
3608 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes)((__uint32_t)(rlc_hdr->save_restore_list_gpm_offset_bytes)
);
3609 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver)((__uint32_t)(rlc_hdr->save_restore_list_srm_ucode_ver));
3610 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver)((__uint32_t)(rlc_hdr->save_restore_list_srm_feature_ver));
3611 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes)((__uint32_t)(rlc_hdr->save_restore_list_srm_size_bytes));
3612 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes)((__uint32_t)(rlc_hdr->save_restore_list_srm_offset_bytes)
);
3613 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3614 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length)((__uint32_t)(rlc_hdr->reg_list_format_direct_reg_list_length
));
3615}
3616
3617static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3618{
3619 const struct rlc_firmware_header_v2_2 *rlc_hdr;
3620
3621 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3622 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes)((__uint32_t)(rlc_hdr->rlc_iram_ucode_size_bytes));
3623 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes)((__uint32_t)(rlc_hdr->rlc_iram_ucode_offset_bytes));
3624 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes)((__uint32_t)(rlc_hdr->rlc_dram_ucode_size_bytes));
3625 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes)((__uint32_t)(rlc_hdr->rlc_dram_ucode_offset_bytes));
3626}
3627
3628static bool_Bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3629{
3630 bool_Bool ret = false0;
3631
3632 switch (adev->pdev->revision) {
3633 case 0xc2:
3634 case 0xc3:
3635 ret = true1;
3636 break;
3637 default:
3638 ret = false0;
3639 break;
3640 }
3641
3642 return ret ;
3643}
3644
3645static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3646{
3647 switch (adev->asic_type) {
3648 case CHIP_NAVI10:
3649 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3650 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3651 break;
3652 case CHIP_NAVY_FLOUNDER:
3653 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3654 break;
3655 default:
3656 break;
3657 }
3658}
3659
3660static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3661{
3662 const char *chip_name;
3663 char fw_name[40];
3664 char wks[10];
3665 int err;
3666 struct amdgpu_firmware_info *info = NULL((void *)0);
3667 const struct common_firmware_header *header = NULL((void *)0);
3668 const struct gfx_firmware_header_v1_0 *cp_hdr;
3669 const struct rlc_firmware_header_v2_0 *rlc_hdr;
3670 unsigned int *tmp = NULL((void *)0);
3671 unsigned int i = 0;
3672 uint16_t version_major;
3673 uint16_t version_minor;
3674
3675 DRM_DEBUG("\n")__drm_dbg(DRM_UT_CORE, "\n");
3676
3677 memset(wks, 0, sizeof(wks))__builtin_memset((wks), (0), (sizeof(wks)));
3678 switch (adev->asic_type) {
17
←
Control jumps to 'case CHIP_NAVY_FLOUNDER:' at line 3694
→
3679 case CHIP_NAVI10:
3680 chip_name = "navi10";
3681 break;
3682 case CHIP_NAVI14:
3683 chip_name = "navi14";
3684 if (!(adev->pdev->device == 0x7340 &&
3685 adev->pdev->revision != 0x00))
3686 snprintf(wks, sizeof(wks), "_wks");
3687 break;
3688 case CHIP_NAVI12:
3689 chip_name = "navi12";
3690 break;
3691 case CHIP_SIENNA_CICHLID:
3692 chip_name = "sienna_cichlid";
3693 break;
3694 case CHIP_NAVY_FLOUNDER:
3695 chip_name = "navy_flounder";
3696 break;
18
←
 Execution continues on line 3701
→
3697 default:
3698 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 3698); } while (0);
3699 }
3700
3701 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3702 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
19
←
Calling 'request_firmware'
→
23
←
Returning from 'request_firmware'
→
3703 if (err)
24
←
Assuming 'err' is 0
→
25
←
Taking false branch
→
3704 goto out;
3705 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3706 if (err)
26
←
Assuming 'err' is 0
→
27
←
Taking false branch
→
3707 goto out;
3708 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
28
←
Access to field 'data' results in a dereference of a null pointer (loaded from field 'pfp_fw')
3709 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
3710 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
3711
3712 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3713 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3714 if (err)
3715 goto out;
3716 err = amdgpu_ucode_validate(adev->gfx.me_fw);
3717 if (err)
3718 goto out;
3719 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3720 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
3721 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
3722
3723 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3724 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3725 if (err)
3726 goto out;
3727 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3728 if (err)
3729 goto out;
3730 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3731 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
3732 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
3733
3734 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
3735 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3736 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3737 if (err)
3738 goto out;
3739 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3740 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3741 version_major = le16_to_cpu(rlc_hdr->header.header_version_major)((__uint16_t)(rlc_hdr->header.header_version_major));
3742 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor)((__uint16_t)(rlc_hdr->header.header_version_minor));
3743
3744 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version)((__uint32_t)(rlc_hdr->header.ucode_version));
3745 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version)((__uint32_t)(rlc_hdr->ucode_feature_version));
3746 adev->gfx.rlc.save_and_restore_offset =
3747 le32_to_cpu(rlc_hdr->save_and_restore_offset)((__uint32_t)(rlc_hdr->save_and_restore_offset));
3748 adev->gfx.rlc.clear_state_descriptor_offset =
3749 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)((__uint32_t)(rlc_hdr->clear_state_descriptor_offset));
3750 adev->gfx.rlc.avail_scratch_ram_locations =
3751 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)((__uint32_t)(rlc_hdr->avail_scratch_ram_locations));
3752 adev->gfx.rlc.reg_restore_list_size =
3753 le32_to_cpu(rlc_hdr->reg_restore_list_size)((__uint32_t)(rlc_hdr->reg_restore_list_size));
3754 adev->gfx.rlc.reg_list_format_start =
3755 le32_to_cpu(rlc_hdr->reg_list_format_start)((__uint32_t)(rlc_hdr->reg_list_format_start));
3756 adev->gfx.rlc.reg_list_format_separate_start =
3757 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)((__uint32_t)(rlc_hdr->reg_list_format_separate_start));
3758 adev->gfx.rlc.starting_offsets_start =
3759 le32_to_cpu(rlc_hdr->starting_offsets_start)((__uint32_t)(rlc_hdr->starting_offsets_start));
3760 adev->gfx.rlc.reg_list_format_size_bytes =
3761 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)((__uint32_t)(rlc_hdr->reg_list_format_size_bytes));
3762 adev->gfx.rlc.reg_list_size_bytes =
3763 le32_to_cpu(rlc_hdr->reg_list_size_bytes)((__uint32_t)(rlc_hdr->reg_list_size_bytes));
3764 adev->gfx.rlc.register_list_format =
3765 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3766 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL(0x0001 | 0x0004));
3767 if (!adev->gfx.rlc.register_list_format) {
3768 err = -ENOMEM12;
3769 goto out;
3770 }
3771
3772 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3773 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)((__uint32_t)(rlc_hdr->reg_list_format_array_offset_bytes)
));
3774 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3775 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i])((__uint32_t)(tmp[i]));
3776
3777 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3778
3779 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3780 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)((__uint32_t)(rlc_hdr->reg_list_array_offset_bytes)));
3781 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3782 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i])((__uint32_t)(tmp[i]));
3783
3784 if (version_major == 2) {
3785 if (version_minor >= 1)
3786 gfx_v10_0_init_rlc_ext_microcode(adev);
3787 if (version_minor == 2)
3788 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3789 }
3790 }
3791
3792 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3793 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3794 if (err)
3795 goto out;
3796 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3797 if (err)
3798 goto out;
3799 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3800 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
3801 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
3802
3803 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3804 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3805 if (!err) {
3806 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3807 if (err)
3808 goto out;
3809 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3810 adev->gfx.mec2_fw->data;
3811 adev->gfx.mec2_fw_version =
3812 le32_to_cpu(cp_hdr->header.ucode_version)((__uint32_t)(cp_hdr->header.ucode_version));
3813 adev->gfx.mec2_feature_version =
3814 le32_to_cpu(cp_hdr->ucode_feature_version)((__uint32_t)(cp_hdr->ucode_feature_version));
3815 } else {
3816 err = 0;
3817 adev->gfx.mec2_fw = NULL((void *)0);
3818 }
3819
3820 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3821 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3822 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3823 info->fw = adev->gfx.pfp_fw;
3824 header = (const struct common_firmware_header *)info->fw->data;
3825 adev->firmware.fw_size +=
3826 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
3827
3828 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3829 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3830 info->fw = adev->gfx.me_fw;
3831 header = (const struct common_firmware_header *)info->fw->data;
3832 adev->firmware.fw_size +=
3833 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
3834
3835 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3836 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3837 info->fw = adev->gfx.ce_fw;
3838 header = (const struct common_firmware_header *)info->fw->data;
3839 adev->firmware.fw_size +=
3840 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
3841
3842 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3843 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3844 info->fw = adev->gfx.rlc_fw;
3845 if (info->fw) {
3846 header = (const struct common_firmware_header *)info->fw->data;
3847 adev->firmware.fw_size +=
3848 roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 <<
12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes
))))((1 << 12)) - 1)));
3849 }
3850 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3851 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3852 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3853 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3854 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3855 info->fw = adev->gfx.rlc_fw;
3856 adev->firmware.fw_size +=
3857 roundup2(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.save_restore_list_cntl_size_bytes) + (((1
<< 12)) - 1)) & (~((__typeof(adev->gfx.rlc.save_restore_list_cntl_size_bytes
))((1 << 12)) - 1)));
3858
3859 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3860 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3861 info->fw = adev->gfx.rlc_fw;
3862 adev->firmware.fw_size +=
3863 roundup2(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.save_restore_list_gpm_size_bytes) + (((1 <<
12)) - 1)) & (~((__typeof(adev->gfx.rlc.save_restore_list_gpm_size_bytes
))((1 << 12)) - 1)));
3864
3865 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3866 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3867 info->fw = adev->gfx.rlc_fw;
3868 adev->firmware.fw_size +=
3869 roundup2(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.save_restore_list_srm_size_bytes) + (((1 <<
12)) - 1)) & (~((__typeof(adev->gfx.rlc.save_restore_list_srm_size_bytes
))((1 << 12)) - 1)));
3870
3871 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
3872 adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
3873 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
3874 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
3875 info->fw = adev->gfx.rlc_fw;
3876 adev->firmware.fw_size +=
3877 roundup2(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.rlc_iram_ucode_size_bytes) + (((1 <<
12)) - 1)) & (~((__typeof(adev->gfx.rlc.rlc_iram_ucode_size_bytes
))((1 << 12)) - 1)));
3878
3879 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
3880 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
3881 info->fw = adev->gfx.rlc_fw;
3882 adev->firmware.fw_size +=
3883 roundup2(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE)(((adev->gfx.rlc.rlc_dram_ucode_size_bytes) + (((1 <<
12)) - 1)) & (~((__typeof(adev->gfx.rlc.rlc_dram_ucode_size_bytes
))((1 << 12)) - 1)));
3884 }
3885 }
3886
3887 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3888 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3889 info->fw = adev->gfx.mec_fw;
3890 header = (const struct common_firmware_header *)info->fw->data;
3891 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3892 adev->firmware.fw_size +=
3893 roundup2(le32_to_cpu(header->ucode_size_bytes) -(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)))
3894 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)));
3895
3896 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3897 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3898 info->fw = adev->gfx.mec_fw;
3899 adev->firmware.fw_size +=
3900 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE)(((((__uint32_t)(cp_hdr->jt_size)) * 4) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size)
) * 4))((1 << 12)) - 1)));
3901
3902 if (adev->gfx.mec2_fw) {
3903 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3904 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3905 info->fw = adev->gfx.mec2_fw;
3906 header = (const struct common_firmware_header *)info->fw->data;
3907 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3908 adev->firmware.fw_size +=
3909 roundup2(le32_to_cpu(header->ucode_size_bytes) -(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)))
3910 le32_to_cpu(cp_hdr->jt_size) * 4,(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)))
3911 PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4) + (((1 << 12)) - 1)) & (
~((__typeof(((__uint32_t)(header->ucode_size_bytes)) - ((__uint32_t
)(cp_hdr->jt_size)) * 4))((1 << 12)) - 1)));
3912 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3913 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3914 info->fw = adev->gfx.mec2_fw;
3915 adev->firmware.fw_size +=
3916 roundup2(le32_to_cpu(cp_hdr->jt_size) * 4,(((((__uint32_t)(cp_hdr->jt_size)) * 4) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size)
) * 4))((1 << 12)) - 1)))
3917 PAGE_SIZE)(((((__uint32_t)(cp_hdr->jt_size)) * 4) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(cp_hdr->jt_size)
) * 4))((1 << 12)) - 1)));
3918 }
3919 }
3920
3921 gfx_v10_0_check_fw_write_wait(adev);
3922out:
3923 if (err) {
3924 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx10: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
3925 "gfx10: Failed to load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx10: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
3926 fw_name)printf("drm:pid%d:%s *ERROR* " "gfx10: Failed to load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
);
3927 release_firmware(adev->gfx.pfp_fw);
3928 adev->gfx.pfp_fw = NULL((void *)0);
3929 release_firmware(adev->gfx.me_fw);
3930 adev->gfx.me_fw = NULL((void *)0);
3931 release_firmware(adev->gfx.ce_fw);
3932 adev->gfx.ce_fw = NULL((void *)0);
3933 release_firmware(adev->gfx.rlc_fw);
3934 adev->gfx.rlc_fw = NULL((void *)0);
3935 release_firmware(adev->gfx.mec_fw);
3936 adev->gfx.mec_fw = NULL((void *)0);
3937 release_firmware(adev->gfx.mec2_fw);
3938 adev->gfx.mec2_fw = NULL((void *)0);
3939 }
3940
3941 gfx_v10_0_check_gfxoff_flag(adev);
3942
3943 return err;
3944}
3945
3946static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3947{
3948 u32 count = 0;
3949 const struct cs_section_def *sect = NULL((void *)0);
3950 const struct cs_extent_def *ext = NULL((void *)0);
3951
3952 /* begin clear state */
3953 count += 2;
3954 /* context control state */
3955 count += 3;
3956
3957 for (sect = gfx10_cs_data; sect->section != NULL((void *)0); ++sect) {
3958 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
3959 if (sect->id == SECT_CONTEXT)
3960 count += 2 + ext->reg_count;
3961 else
3962 return 0;
3963 }
3964 }
3965
3966 /* set PA_SC_TILE_STEERING_OVERRIDE */
3967 count += 3;
3968 /* end clear state */
3969 count += 2;
3970 /* clear state */
3971 count += 2;
3972
3973 return count;
3974}
3975
3976static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3977 volatile u32 *buffer)
3978{
3979 u32 count = 0, i;
3980 const struct cs_section_def *sect = NULL((void *)0);
3981 const struct cs_extent_def *ext = NULL((void *)0);
3982 int ctx_reg_offset;
3983
3984 if (adev->gfx.rlc.cs_data == NULL((void *)0))
3985 return;
3986 if (buffer == NULL((void *)0))
3987 return;
3988
3989 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
3990 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE)((__uint32_t)((2 << 28)));
3991
3992 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1))((__uint32_t)(((3 << 30) | (((0x28) & 0xFF) <<
8) | ((1) & 0x3FFF) << 16)));
3993 buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000));
3994 buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000));
3995
3996 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL((void *)0); ++sect) {
3997 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
3998 if (sect->id == SECT_CONTEXT) {
3999 buffer[count++] =
4000 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) <<
8) | ((ext->reg_count) & 0x3FFF) << 16)));
4001 buffer[count++] = cpu_to_le32(ext->reg_index -((__uint32_t)(ext->reg_index - 0x0000a000))
4002 PACKET3_SET_CONTEXT_REG_START)((__uint32_t)(ext->reg_index - 0x0000a000));
4003 for (i = 0; i < ext->reg_count; i++)
4004 buffer[count++] = cpu_to_le32(ext->extent[i])((__uint32_t)(ext->extent[i]));
4005 } else {
4006 return;
4007 }
4008 }
4009 }
4010
4011 ctx_reg_offset =
4012 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE)(adev->reg_offset[GC_HWIP][0][1] + 0x00d7) - PACKET3_SET_CONTEXT_REG_START0x0000a000;
4013 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) <<
8) | ((1) & 0x3FFF) << 16)));
4014 buffer[count++] = cpu_to_le32(ctx_reg_offset)((__uint32_t)(ctx_reg_offset));
4015 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override)((__uint32_t)(adev->gfx.config.pa_sc_tile_steering_override
));
4016
4017 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
4018 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE)((__uint32_t)((3 << 28)));
4019
4020 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0))((__uint32_t)(((3 << 30) | (((0x12) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
4021 buffer[count++] = cpu_to_le32(0)((__uint32_t)(0));
4022}
4023
4024static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4025{
4026 /* clear state block */
4027 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4028 &adev->gfx.rlc.clear_state_gpu_addr,
4029 (void **)&adev->gfx.rlc.cs_ptr);
4030
4031 /* jump table block */
4032 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4033 &adev->gfx.rlc.cp_table_gpu_addr,
4034 (void **)&adev->gfx.rlc.cp_table_ptr);
4035}
4036
4037static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4038{
4039 const struct cs_section_def *cs_data;
4040 int r;
4041
4042 adev->gfx.rlc.cs_data = gfx10_cs_data;
4043
4044 cs_data = adev->gfx.rlc.cs_data;
4045
4046 if (cs_data) {
4047 /* init clear state block */
4048 r = amdgpu_gfx_rlc_init_csb(adev);
4049 if (r)
4050 return r;
4051 }
4052
4053 /* init spm vmid with 0xf */
4054 if (adev->gfx.rlc.funcs->update_spm_vmid)
4055 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4056
4057 return 0;
4058}
4059
4060static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4061{
4062 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL((void *)0), NULL((void *)0));
4063 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL((void *)0), NULL((void *)0));
4064}
4065
4066static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4067{
4068 int r;
4069
4070 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES128);
4071
4072 amdgpu_gfx_graphics_queue_acquire(adev);
4073
4074 r = gfx_v10_0_init_microcode(adev);
16
←
Calling 'gfx_v10_0_init_microcode'
→
4075 if (r)
4076 DRM_ERROR("Failed to load gfx firmware!\n")__drm_err("Failed to load gfx firmware!\n");
4077
4078 return r;
4079}
4080
4081static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4082{
4083 int r;
4084 u32 *hpd;
4085 const __le32 *fw_data = NULL((void *)0);
4086 unsigned fw_size;
4087 u32 *fw = NULL((void *)0);
4088 size_t mec_hpd_size;
4089
4090 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL((void *)0);
4091
4092 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES128);
4093
4094 /* take ownership of the relevant compute queues */
4095 amdgpu_gfx_compute_queue_acquire(adev);
4096 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE2048;
4097
4098 if (mec_hpd_size) {
4099 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE(1 << 12),
4100 AMDGPU_GEM_DOMAIN_GTT0x2,
4101 &adev->gfx.mec.hpd_eop_obj,
4102 &adev->gfx.mec.hpd_eop_gpu_addr,
4103 (void **)&hpd);
4104 if (r) {
4105 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create HDP EOP bo failed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
4106 gfx_v10_0_mec_fini(adev);
4107 return r;
4108 }
4109
4110 memset(hpd, 0, mec_hpd_size)__builtin_memset((hpd), (0), (mec_hpd_size));
4111
4112 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4113 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4114 }
4115
4116 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4117 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4118
4119 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4120 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes)));
4121 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes)((__uint32_t)(mec_hdr->header.ucode_size_bytes));
4122
4123 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4124 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
4125 &adev->gfx.mec.mec_fw_obj,
4126 &adev->gfx.mec.mec_fw_gpu_addr,
4127 (void **)&fw);
4128 if (r) {
4129 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create mec fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
4130 gfx_v10_0_mec_fini(adev);
4131 return r;
4132 }
4133
4134 memcpy(fw, fw_data, fw_size)__builtin_memcpy((fw), (fw_data), (fw_size));
4135
4136 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4137 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4138 }
4139
4140 return 0;
4141}
4142
4143static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4144{
4145 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (address << 0x10)),
0)
4146 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (address << 0x10)),
0)
4147 (address << SQ_IND_INDEX__INDEX__SHIFT))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (address << 0x10)),
0);
4148 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1119), 0);
4149}
4150
4151static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4152 uint32_t thread, uint32_t regno,
4153 uint32_t num, uint32_t *out)
4154{
4155 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L)), 0)
4156 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L)), 0)
4157 (regno << SQ_IND_INDEX__INDEX__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L)), 0)
4158 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L)), 0)
4159 (SQ_IND_INDEX__AUTO_INCR_MASK))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1118)), ((wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L)), 0);
4160 while (num--)
4161 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1119), 0);
4162}
4163
4164static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4165{
4166 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4167 * field when performing a select_se_sh so it should be
4168 * zero here */
4169 WARN_ON(simd != 0)({ int __ret = !!(simd != 0); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "simd != 0", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4169); __builtin_expect(!!(__ret), 0); });
4170
4171 /* type 2 wave data */
4172 dst[(*no_fields)++] = 2;
4173 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS0x0102);
4174 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO0x0108);
4175 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI0x0109);
4176 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO0x027e);
4177 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI0x027f);
4178 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID10x0117);
4179 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID20x0118);
4180 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW00x010a);
4181 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC0x0105);
4182 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC0x0106);
4183 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS0x0103);
4184 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS0x0107);
4185 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS20x011c);
4186 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG10x010d);
4187 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M00x027c);
4188}
4189
4190static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4191 uint32_t wave, uint32_t start,
4192 uint32_t size, uint32_t *dst)
4193{
4194 WARN_ON(simd != 0)({ int __ret = !!(simd != 0); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "simd != 0", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4194); __builtin_expect(!!(__ret), 0); });
4195
4196 wave_read_regs(
4197 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET0x00000200, size,
4198 dst);
4199}
4200
4201static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4202 uint32_t wave, uint32_t thread,
4203 uint32_t start, uint32_t size,
4204 uint32_t *dst)
4205{
4206 wave_read_regs(
4207 adev, wave, thread,
4208 start + SQIND_WAVE_VGPRS_OFFSET0x00000400, size, dst);
4209}
4210
4211static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4212 u32 me, u32 pipe, u32 q, u32 vm)
4213 {
4214 nv_grbm_select(adev, me, pipe, q, vm);
4215 }
4216
4217
4218static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4219 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4220 .select_se_sh = &gfx_v10_0_select_se_sh,
4221 .read_wave_data = &gfx_v10_0_read_wave_data,
4222 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4223 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4224 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4225 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4226};
4227
4228static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4229{
4230 u32 gb_addr_config;
4231
4232 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4233
4234 switch (adev->asic_type) {
4235 case CHIP_NAVI10:
4236 case CHIP_NAVI14:
4237 case CHIP_NAVI12:
4238 adev->gfx.config.max_hw_contexts = 8;
4239 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4240 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4241 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4242 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4243 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x13de), 0);
4244 break;
4245 case CHIP_SIENNA_CICHLID:
4246 case CHIP_NAVY_FLOUNDER:
4247 adev->gfx.config.max_hw_contexts = 8;
4248 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4249 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4250 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4251 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4252 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x13de), 0);
4253 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4254 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS)(((gb_addr_config) & 0x00000700L) >> 0x8);
4255 break;
4256 default:
4257 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4257); } while (0);
4258 break;
4259 }
4260
4261 adev->gfx.config.gb_addr_config = gb_addr_config;
4262
4263 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4264 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0)
4265 GB_ADDR_CONFIG, NUM_PIPES)(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0);
4266
4267 adev->gfx.config.max_tile_pipes =
4268 adev->gfx.config.gb_addr_config_fields.num_pipes;
4269
4270 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4271 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6)
4272 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS)(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6);
4273 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4274 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a)
4275 GB_ADDR_CONFIG, NUM_RB_PER_SE)(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a);
4276 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4277 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13)
4278 GB_ADDR_CONFIG, NUM_SHADER_ENGINES)(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13);
4279 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4280 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3)
4281 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3));
4282}
4283
4284static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4285 int me, int pipe, int queue)
4286{
4287 int r;
4288 struct amdgpu_ring *ring;
4289 unsigned int irq_type;
4290
4291 ring = &adev->gfx.gfx_ring[ring_id];
4292
4293 ring->me = me;
4294 ring->pipe = pipe;
4295 ring->queue = queue;
4296
4297 ring->ring_obj = NULL((void *)0);
4298 ring->use_doorbell = true1;
4299
4300 if (!ring_id)
4301 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4302 else
4303 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4304 snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4305
4306 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4307 r = amdgpu_ring_init(adev, ring, 1024,
4308 &adev->gfx.eop_irq, irq_type,
4309 AMDGPU_RING_PRIO_DEFAULT1);
4310 if (r)
4311 return r;
4312 return 0;
4313}
4314
4315static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4316 int mec, int pipe, int queue)
4317{
4318 int r;
4319 unsigned irq_type;
4320 struct amdgpu_ring *ring;
4321 unsigned int hw_prio;
4322
4323 ring = &adev->gfx.compute_ring[ring_id];
4324
4325 /* mec0 is me1 */
4326 ring->me = mec + 1;
4327 ring->pipe = pipe;
4328 ring->queue = queue;
4329
4330 ring->ring_obj = NULL((void *)0);
4331 ring->use_doorbell = true1;
4332 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4333 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4334 + (ring_id * GFX10_MEC_HPD_SIZE2048);
4335 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4336
4337 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4338 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4339 + ring->pipe;
4340 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
4341 ring->queue) ?
4342 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4343 /* type-2 packets are deprecated on MEC, use type-3 instead */
4344 r = amdgpu_ring_init(adev, ring, 1024,
4345 &adev->gfx.eop_irq, irq_type, hw_prio);
4346 if (r)
4347 return r;
4348
4349 return 0;
4350}
4351
4352static int gfx_v10_0_sw_init(void *handle)
4353{
4354 int i, j, k, r, ring_id = 0;
4355 struct amdgpu_kiq *kiq;
4356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4357
4358 switch (adev->asic_type) {
1
Control jumps to the 'default' case at line 4378
→
4359 case CHIP_NAVI10:
4360 case CHIP_NAVI14:
4361 case CHIP_NAVI12:
4362 adev->gfx.me.num_me = 1;
4363 adev->gfx.me.num_pipe_per_me = 1;
4364 adev->gfx.me.num_queue_per_pipe = 1;
4365 adev->gfx.mec.num_mec = 2;
4366 adev->gfx.mec.num_pipe_per_mec = 4;
4367 adev->gfx.mec.num_queue_per_pipe = 8;
4368 break;
4369 case CHIP_SIENNA_CICHLID:
4370 case CHIP_NAVY_FLOUNDER:
4371 adev->gfx.me.num_me = 1;
4372 adev->gfx.me.num_pipe_per_me = 1;
4373 adev->gfx.me.num_queue_per_pipe = 1;
4374 adev->gfx.mec.num_mec = 2;
4375 adev->gfx.mec.num_pipe_per_mec = 4;
4376 adev->gfx.mec.num_queue_per_pipe = 4;
4377 break;
4378 default:
4379 adev->gfx.me.num_me = 1;
4380 adev->gfx.me.num_pipe_per_me = 1;
4381 adev->gfx.me.num_queue_per_pipe = 1;
4382 adev->gfx.mec.num_mec = 1;
4383 adev->gfx.mec.num_pipe_per_mec = 4;
4384 adev->gfx.mec.num_queue_per_pipe = 8;
4385 break;
2
←
 Execution continues on line 4389
→
4386 }
4387
4388 /* KIQ event */
4389 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4390 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT178,
4391 &adev->gfx.kiq.irq);
4392 if (r)
3
←
Assuming 'r' is 0
→
4
←
Taking false branch
→
4393 return r;
4394
4395 /* EOP Event */
4396 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4397 GFX_10_1__SRCID__CP_EOP_INTERRUPT181,
4398 &adev->gfx.eop_irq);
4399 if (r)
5
←
Assuming 'r' is 0
→
6
←
Taking false branch
→
4400 return r;
4401
4402 /* Privileged reg */
4403 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT184,
4404 &adev->gfx.priv_reg_irq);
4405 if (r)
7
←
Assuming 'r' is 0
→
8
←
Taking false branch
→
4406 return r;
4407
4408 /* Privileged inst */
4409 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT185,
4410 &adev->gfx.priv_inst_irq);
4411 if (r)
9
←
Assuming 'r' is 0
→
10
←
Taking false branch
→
4412 return r;
4413
4414 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE0x00000000L;
4415
4416 gfx_v10_0_scratch_init(adev);
11
←
Calling 'gfx_v10_0_scratch_init'
→
14
←
Returning from 'gfx_v10_0_scratch_init'
→
4417
4418 r = gfx_v10_0_me_init(adev);
15
←
Calling 'gfx_v10_0_me_init'
→
4419 if (r)
4420 return r;
4421
4422 r = gfx_v10_0_rlc_init(adev);
4423 if (r) {
4424 DRM_ERROR("Failed to init rlc BOs!\n")__drm_err("Failed to init rlc BOs!\n");
4425 return r;
4426 }
4427
4428 r = gfx_v10_0_mec_init(adev);
4429 if (r) {
4430 DRM_ERROR("Failed to init MEC BOs!\n")__drm_err("Failed to init MEC BOs!\n");
4431 return r;
4432 }
4433
4434 /* set up the gfx ring */
4435 for (i = 0; i < adev->gfx.me.num_me; i++) {
4436 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4437 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4438 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4439 continue;
4440
4441 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4442 i, k, j);
4443 if (r)
4444 return r;
4445 ring_id++;
4446 }
4447 }
4448 }
4449
4450 ring_id = 0;
4451 /* set up the compute queues - allocate horizontally across pipes */
4452 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4453 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4454 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4455 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4456 j))
4457 continue;
4458
4459 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4460 i, k, j);
4461 if (r)
4462 return r;
4463
4464 ring_id++;
4465 }
4466 }
4467 }
4468
4469 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE2048);
4470 if (r) {
4471 DRM_ERROR("Failed to init KIQ BOs!\n")__drm_err("Failed to init KIQ BOs!\n");
4472 return r;
4473 }
4474
4475 kiq = &adev->gfx.kiq;
4476 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4477 if (r)
4478 return r;
4479
4480 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4481 if (r)
4482 return r;
4483
4484 /* allocate visible FB for rlc auto-loading fw */
4485 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4486 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4487 if (r)
4488 return r;
4489 }
4490
4491 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE65536;
4492
4493 gfx_v10_0_gpu_early_init(adev);
4494
4495 return 0;
4496}
4497
4498static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4499{
4500 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4501 &adev->gfx.pfp.pfp_fw_gpu_addr,
4502 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4503}
4504
4505static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4506{
4507 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4508 &adev->gfx.ce.ce_fw_gpu_addr,
4509 (void **)&adev->gfx.ce.ce_fw_ptr);
4510}
4511
4512static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4513{
4514 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4515 &adev->gfx.me.me_fw_gpu_addr,
4516 (void **)&adev->gfx.me.me_fw_ptr);
4517}
4518
4519static int gfx_v10_0_sw_fini(void *handle)
4520{
4521 int i;
4522 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4523
4524 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4525 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4526 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4527 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4528
4529 amdgpu_gfx_mqd_sw_fini(adev);
4530 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4531 amdgpu_gfx_kiq_fini(adev);
4532
4533 gfx_v10_0_pfp_fini(adev);
4534 gfx_v10_0_ce_fini(adev);
4535 gfx_v10_0_me_fini(adev);
4536 gfx_v10_0_rlc_fini(adev);
4537 gfx_v10_0_mec_fini(adev);
4538
4539 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4540 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4541
4542 gfx_v10_0_free_microcode(adev);
4543
4544 return 0;
4545}
4546
4547static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4548 u32 sh_num, u32 instance)
4549{
4550 u32 data;
4551
4552 if (instance == 0xffffffff)
4553 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,(((0) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e
)))
4554 INSTANCE_BROADCAST_WRITES, 1)(((0) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e
)));
4555 else
4556 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,(((0) & ~0x000000FFL) | (0x000000FFL & ((instance) <<
0x0)))
4557 instance)(((0) & ~0x000000FFL) | (0x000000FFL & ((instance) <<
0x0)));
4558
4559 if (se_num == 0xffffffff)
4560 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,(((data) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)))
4561 1)(((data) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)));
4562 else
4563 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num)(((data) & ~0x00FF0000L) | (0x00FF0000L & ((se_num) <<
0x10)));
4564
4565 if (sh_num == 0xffffffff)
4566 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,(((data) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)))
4567 1)(((data) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
4568 else
4569 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((sh_num) <<
0x8)));
4570
4571 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2200)), (data), 0);
4572}
4573
4574static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4575{
4576 u32 data, mask;
4577
4578 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x13dd), 0);
4579 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x147f), 0);
4580
4581 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK0x00FF0000L;
4582 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT0x10;
4583
4584 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4585 adev->gfx.config.max_sh_per_se);
4586
4587 return (~data) & mask;
4588}
4589
4590static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4591{
4592 int i, j;
4593 u32 data;
4594 u32 active_rbs = 0;
4595 u32 bitmap;
4596 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4597 adev->gfx.config.max_sh_per_se;
4598
4599 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
4600 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4601 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4602 bitmap = i * adev->gfx.config.max_sh_per_se + j;
4603 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4604 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4605 continue;
4606 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4607 data = gfx_v10_0_get_rb_active_bitmap(adev);
4608 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4609 rb_bitmap_width_per_sh);
4610 }
4611 }
4612 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4613 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
4614
4615 adev->gfx.config.backend_enable_mask = active_rbs;
4616 adev->gfx.config.num_rbs = hweight32(active_rbs);
4617}
4618
4619static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4620{
4621 uint32_t num_sc;
4622 uint32_t enabled_rb_per_sh;
4623 uint32_t active_rb_bitmap;
4624 uint32_t num_rb_per_sc;
4625 uint32_t num_packer_per_sc;
4626 uint32_t pa_sc_tile_steering_override;
4627
4628 /* for ASICs that integrates GFX v10.3
4629 * pa_sc_tile_steering_override should be set to 0 */
4630 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4631 adev->asic_type == CHIP_NAVY_FLOUNDER)
4632 return 0;
4633
4634 /* init num_sc */
4635 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4636 adev->gfx.config.num_sc_per_sh;
4637 /* init num_rb_per_sc */
4638 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4639 enabled_rb_per_sh = hweight32(active_rb_bitmap);
4640 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4641 /* init num_packer_per_sc */
4642 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4643
4644 pa_sc_tile_steering_override = 0;
4645 pa_sc_tile_steering_override |=
4646 (order_base_2(num_sc)drm_order(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT0xc) &
4647 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK0x00003000L;
4648 pa_sc_tile_steering_override |=
4649 (order_base_2(num_rb_per_sc)drm_order(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT0x10) &
4650 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK0x00030000L;
4651 pa_sc_tile_steering_override |=
4652 (order_base_2(num_packer_per_sc)drm_order(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT0x14) &
4653 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK0x00100000L;
4654
4655 return pa_sc_tile_steering_override;
4656}
4657
4658#define DEFAULT_SH_MEM_BASES(0x6000) (0x6000)
4659
4660static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4661{
4662 int i;
4663 uint32_t sh_mem_bases;
4664
4665 /*
4666 * Configure apertures:
4667 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
4668 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
4669 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
4670 */
4671 sh_mem_bases = DEFAULT_SH_MEM_BASES(0x6000) | (DEFAULT_SH_MEM_BASES(0x6000) << 16);
4672
4673 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
4674 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) {
4675 nv_grbm_select(adev, 0, 0, 0, i);
4676 /* CP and shaders */
4677 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10ad)), (((SH_MEM_ADDRESS_MODE_64 << 0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED
<< 0x2) | (SH_MEM_RETRY_MODE_ALL << 0xc) | (3 <<
0xe))), 0);
4678 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10aa)), (sh_mem_bases), 0);
4679 }
4680 nv_grbm_select(adev, 0, 0, 0, 0);
4681 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
4682
4683 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4684 acccess. These should be enabled by FW for target VMIDs. */
4685 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) {
4686 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20a0) + 2 * i), (0), 0);
4687 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20a1) + 2 * i), (0), 0);
4688 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20c0) + i), (0), 0);
4689 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20d0) + i), (0), 0);
4690 }
4691}
4692
4693static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4694{
4695 int vmid;
4696
4697 /*
4698 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4699 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4700 * the driver can enable them for graphics. VMID0 should maintain
4701 * access so that HWS firmware can save/restore entries.
4702 */
4703 for (vmid = 1; vmid < 16; vmid++) {
4704 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20a0) + 2 * vmid), (0), 0);
4705 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20a1) + 2 * vmid), (0), 0);
4706 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20c0) + vmid), (0), 0);
4707 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x20d0) + vmid), (0), 0);
4708 }
4709}
4710
4711
4712static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4713{
4714 int i, j, k;
4715 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4716 u32 tmp, wgp_active_bitmap = 0;
4717 u32 gcrd_targets_disable_tcp = 0;
4718 u32 utcl_invreq_disable = 0;
4719 /*
4720 * GCRD_TARGETS_DISABLE field contains
4721 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4722 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4723 */
4724 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4725 2 * max_wgp_per_sh + /* TCP */
4726 max_wgp_per_sh + /* SQC */
4727 4); /* GL1C */
4728 /*
4729 * UTCL1_UTCL0_INVREQ_DISABLE field contains
4730 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4731 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4732 */
4733 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4734 2 * max_wgp_per_sh + /* TCP */
4735 2 * max_wgp_per_sh + /* SQC */
4736 4 + /* RMI */
4737 1); /* SQG */
4738
4739 if (adev->asic_type == CHIP_NAVI10 ||
4740 adev->asic_type == CHIP_NAVI14 ||
4741 adev->asic_type == CHIP_NAVI12) {
4742 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
4743 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4744 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4745 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4746 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4747 /*
4748 * Set corresponding TCP bits for the inactive WGPs in
4749 * GCRD_SA_TARGETS_DISABLE
4750 */
4751 gcrd_targets_disable_tcp = 0;
4752 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4753 utcl_invreq_disable = 0;
4754
4755 for (k = 0; k < max_wgp_per_sh; k++) {
4756 if (!(wgp_active_bitmap & (1 << k))) {
4757 gcrd_targets_disable_tcp |= 3 << (2 * k);
4758 utcl_invreq_disable |= (3 << (2 * k)) |
4759 (3 << (2 * (max_wgp_per_sh + k)));
4760 }
4761 }
4762
4763 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x158a), 0);
4764 /* only override TCP & SQC bits */
4765 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4766 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4767 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x158a)), (tmp), 0);
4768
4769 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x158b), 0);
4770 /* only override TCP bits */
4771 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4772 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4773 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x158b)), (tmp), 0);
4774 }
4775 }
4776
4777 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4778 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
4779 }
4780}
4781
4782static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4783{
4784 /* TCCs are global (not instanced). */
4785 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x500a), 0) |
4786 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x500b), 0);
4787
4788 adev->gfx.config.tcc_disabled_mask =
4789 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE)(((tcc_disable) & 0xFFFF0000L) >> 0x10) |
4790 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE)(((tcc_disable) & 0x0000FF00L) >> 0x8) << 16);
4791}
4792
4793static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4794{
4795 u32 tmp;
4796 int i;
4797
4798 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da0), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x0da0), 0) & ~0x000000FFL) | (0xff) << 0x0
), 0);
4799
4800 gfx_v10_0_setup_rb(adev);
4801 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4802 gfx_v10_0_get_tcc_info(adev);
4803 adev->gfx.config.pa_sc_tile_steering_override =
4804 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4805
4806 /* XXX SH_MEM regs */
4807 /* where to put LDS, scratch, GPUVM in FSA64 space */
4808 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
4809 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_00].num_ids; i++) {
4810 nv_grbm_select(adev, 0, 0, 0, i);
4811 /* CP and shaders */
4812 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10ad)), (((SH_MEM_ADDRESS_MODE_64 << 0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED
<< 0x2) | (SH_MEM_RETRY_MODE_ALL << 0xc) | (3 <<
0xe))), 0);
4813 if (i != 0) {
4814 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc
.private_aperture_start >> 48)) << 0x0)))
4815 (adev->gmc.private_aperture_start >> 48))(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc
.private_aperture_start >> 48)) << 0x0)));
4816 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev->
gmc.shared_aperture_start >> 48)) << 0x10)))
4817 (adev->gmc.shared_aperture_start >> 48))(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev->
gmc.shared_aperture_start >> 48)) << 0x10)));
4818 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x10aa)), (tmp), 0);
4819 }
4820 }
4821 nv_grbm_select(adev, 0, 0, 0, 0);
4822
4823 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
4824
4825 gfx_v10_0_init_compute_vmid(adev);
4826 gfx_v10_0_init_gds_vmid(adev);
4827
4828}
4829
4830static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4831 bool_Bool enable)
4832{
4833 u32 tmp;
4834
4835 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
4836 return;
4837
4838 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), 0);
4839
4840 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,(((tmp) & ~0x00080000L) | (0x00080000L & ((enable ? 1
: 0) << 0x13)))
4841 enable ? 1 : 0)(((tmp) & ~0x00080000L) | (0x00080000L & ((enable ? 1
: 0) << 0x13)));
4842 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,(((tmp) & ~0x00100000L) | (0x00100000L & ((enable ? 1
: 0) << 0x14)))
4843 enable ? 1 : 0)(((tmp) & ~0x00100000L) | (0x00100000L & ((enable ? 1
: 0) << 0x14)));
4844 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,(((tmp) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)))
4845 enable ? 1 : 0)(((tmp) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)));
4846 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,(((tmp) & ~0x00200000L) | (0x00200000L & ((enable ? 1
: 0) << 0x15)))
4847 enable ? 1 : 0)(((tmp) & ~0x00200000L) | (0x00200000L & ((enable ? 1
: 0) << 0x15)));
4848
4849 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e0a)), (tmp), 0);
4850}
4851
4852static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4853{
4854 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4855
4856 /* csib */
4857 if (adev->asic_type == CHIP_NAVI12) {
4858 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca3; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (adev->gfx.rlc.clear_state_gpu_addr >> 32
), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (adev->gfx.rlc.clear_state_gpu_addr >> 32), 0); } }
while (0); } while (0)
4859 adev->gfx.rlc.clear_state_gpu_addr >> 32)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca3; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (adev->gfx.rlc.clear_state_gpu_addr >> 32
), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (adev->gfx.rlc.clear_state_gpu_addr >> 32), 0); } }
while (0); } while (0);
4860 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca2; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc
), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0
); } } while (0); } while (0)
4861 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca2; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc
), 0); amdgpu_device_wreg(adev, (r1), ((target_reg | 0x80000000
)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1), 0); for (
i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg(adev
, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10); }
if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc), 0
); } } while (0); } while (0);
4862 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca4; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (adev->gfx.rlc.clear_state_size), 0); amdgpu_device_wreg
(adev, (r1), ((target_reg | 0x80000000)), 0); amdgpu_device_wreg
(adev, (spare_int), (0x1), 0); for (i = 0; i < retries; i++
) { u32 tmp = amdgpu_device_rreg(adev, (r1), 0); if (!(tmp &
0x80000000)) break; udelay(10); } if (i >= retries) printk
("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (adev->gfx.rlc.clear_state_size), 0); } } while (0); } while
(0);
4863 } else {
4864 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca3)), (adev->gfx.rlc.clear_state_gpu_addr >> 32
), 0)
4865 adev->gfx.rlc.clear_state_gpu_addr >> 32)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca3)), (adev->gfx.rlc.clear_state_gpu_addr >> 32
), 0);
4866 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca2)), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc
), 0)
4867 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca2)), (adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc
), 0);
4868 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca4)), (adev->gfx.rlc.clear_state_size), 0);
4869 }
4870 return 0;
4871}
4872
4873void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4874{
4875 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), 0);
4876
4877 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0)(((tmp) & ~0x00000001L) | (0x00000001L & ((0) <<
0x0)));
4878 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c00)), (tmp), 0);
4879}
4880
4881static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4882{
4883 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da8), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x0da8), 0) & ~0x00000004L) | (1) << 0x2)
, 0);
4884 udelay(50);
4885 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da8), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x0da8), 0) & ~0x00000004L) | (0) << 0x2)
, 0);
4886 udelay(50);
4887}
4888
4889static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4890 bool_Bool enable)
4891{
4892 uint32_t rlc_pg_cntl;
4893
4894 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c43), 0);
4895
4896 if (!enable) {
4897 /* RLC_PG_CNTL[23] = 0 (default)
4898 * RLC will wait for handshake acks with SMU
4899 * GFXOFF will be enabled
4900 * RLC_PG_CNTL[23] = 1
4901 * RLC will not issue any message to SMU
4902 * hence no handshake between SMU & RLC
4903 * GFXOFF will be disabled
4904 */
4905 rlc_pg_cntl |= 0x800000;
4906 } else
4907 rlc_pg_cntl &= ~0x800000;
4908 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (rlc_pg_cntl), 0);
4909}
4910
4911static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4912{
4913 /* TODO: enable rlc & smu handshake until smu
4914 * and gfxoff feature works as expected */
4915 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4916 gfx_v10_0_rlc_smu_handshake_cntl(adev, false0);
4917
4918 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][1] + 0x4c00), 0) & ~0x00000001L) | (1) << 0x0)
, 0);
4919 udelay(50);
4920}
4921
4922static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4923{
4924 uint32_t tmp;
4925
4926 /* enable Save Restore Machine */
4927 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL))amdgpu_device_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c80)), 0);
4928 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK0x00000002L;
4929 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK0x00000001L;
4930 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c80)), (tmp), 0);
4931}
4932
4933static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4934{
4935 const struct rlc_firmware_header_v2_0 *hdr;
4936 const __le32 *fw_data;
4937 unsigned i, fw_size;
4938
4939 if (!adev->gfx.rlc_fw)
4940 return -EINVAL22;
4941
4942 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4943 amdgpu_ucode_print_rlc_hdr(&hdr->header);
4944
4945 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4946 le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)));
4947 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4;
4948
4949 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b61)), (0x00002000L), 0)
4950 RLCG_UCODE_LOADING_START_ADDRESS)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b61)), (0x00002000L), 0);
4951
4952 for (i = 0; i < fw_size; i++)
4953 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b62)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0)
4954 le32_to_cpup(fw_data++))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b62)), (((__uint32_t)(*(__uint32_t *)(fw_data++)))), 0);
4955
4956 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b61)), (adev->gfx.rlc_fw_version), 0);
4957
4958 return 0;
4959}
4960
4961static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4962{
4963 int r;
4964
4965 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4966
4967 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4968 if (r)
4969 return r;
4970
4971 gfx_v10_0_init_csb(adev);
4972
4973 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) /* enable RLC SRM */
4974 gfx_v10_0_rlc_enable_srm(adev);
4975 } else {
4976 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
4977 gfx_v10_0_init_csb(adev);
4978 return 0;
4979 }
4980
4981 adev->gfx.rlc.funcs->stop(adev);
4982
4983 /* disable CG */
4984 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c49)), (0), 0);
4985
4986 /* disable PG */
4987 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c43)), (0), 0);
4988
4989 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4990 /* legacy rlc firmware loading */
4991 r = gfx_v10_0_rlc_load_microcode(adev);
4992 if (r)
4993 return r;
4994 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4995 /* rlc backdoor autoload firmware */
4996 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4997 if (r)
4998 return r;
4999 }
5000
5001 gfx_v10_0_init_csb(adev);
5002
5003 adev->gfx.rlc.funcs->start(adev);
5004
5005 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5006 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5007 if (r)
5008 return r;
5009 }
5010 }
5011 return 0;
5012}
5013
5014static struct {
5015 FIRMWARE_ID id;
5016 unsigned int offset;
5017 unsigned int size;
5018} rlc_autoload_info[FIRMWARE_ID_MAX];
5019
5020static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5021{
5022 int ret;
5023 RLC_TABLE_OF_CONTENT *rlc_toc;
5024
5025 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE(1 << 12),
5026 AMDGPU_GEM_DOMAIN_GTT0x2,
5027 &adev->gfx.rlc.rlc_toc_bo,
5028 &adev->gfx.rlc.rlc_toc_gpu_addr,
5029 (void **)&adev->gfx.rlc.rlc_toc_buf);
5030 if (ret) {
5031 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create rlc toc bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret);
5032 return ret;
5033 }
5034
5035 /* Copy toc from psp sos fw to rlc toc buffer */
5036 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size)__builtin_memcpy((adev->gfx.rlc.rlc_toc_buf), (adev->psp
.toc_start_addr), (adev->psp.toc_bin_size));
5037
5038 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5039 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5040 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5041 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5042 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5043 /* Offset needs 4KB alignment */
5044 rlc_toc->offset = roundup2(rlc_toc->offset * 4, PAGE_SIZE)(((rlc_toc->offset * 4) + (((1 << 12)) - 1)) & (
~((__typeof(rlc_toc->offset * 4))((1 << 12)) - 1)));
5045 }
5046
5047 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5048 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5049 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5050
5051 rlc_toc++;
5052 }
5053
5054 return 0;
5055}
5056
5057static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5058{
5059 uint32_t total_size = 0;
5060 FIRMWARE_ID id;
5061 int ret;
5062
5063 ret = gfx_v10_0_parse_rlc_toc(adev);
5064 if (ret) {
5065 dev_err(adev->dev, "failed to parse rlc toc\n")printf("drm:pid%d:%s *ERROR* " "failed to parse rlc toc\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5066 return 0;
5067 }
5068
5069 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5070 total_size += rlc_autoload_info[id].size;
5071
5072 /* In case the offset in rlc toc ucode is aligned */
5073 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5074 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5075 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5076
5077 return total_size;
5078}
5079
5080static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5081{
5082 int r;
5083 uint32_t total_size;
5084
5085 total_size = gfx_v10_0_calc_toc_total_size(adev);
5086
5087 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE(1 << 12),
5088 AMDGPU_GEM_DOMAIN_GTT0x2,
5089 &adev->gfx.rlc.rlc_autoload_bo,
5090 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5091 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5092 if (r) {
5093 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create fw autoload bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5094 return r;
5095 }
5096
5097 return 0;
5098}
5099
5100static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5101{
5102 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5103 &adev->gfx.rlc.rlc_toc_gpu_addr,
5104 (void **)&adev->gfx.rlc.rlc_toc_buf);
5105 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5106 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5107 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5108}
5109
5110static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5111 FIRMWARE_ID id,
5112 const void *fw_data,
5113 uint32_t fw_size)
5114{
5115 uint32_t toc_offset;
5116 uint32_t toc_fw_size;
5117 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5118
5119 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5120 return;
5121
5122 toc_offset = rlc_autoload_info[id].offset;
5123 toc_fw_size = rlc_autoload_info[id].size;
5124
5125 if (fw_size == 0)
5126 fw_size = toc_fw_size;
5127
5128 if (fw_size > toc_fw_size)
5129 fw_size = toc_fw_size;
5130
5131 memcpy(ptr + toc_offset, fw_data, fw_size)__builtin_memcpy((ptr + toc_offset), (fw_data), (fw_size));
5132
5133 if (fw_size < toc_fw_size)
5134 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size)__builtin_memset((ptr + toc_offset + fw_size), (0), (toc_fw_size
- fw_size));
5135}
5136
5137static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5138{
5139 void *data;
5140 uint32_t size;
5141
5142 data = adev->gfx.rlc.rlc_toc_buf;
5143 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5144
5145 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5146 FIRMWARE_ID_RLC_TOC,
5147 data, size);
5148}
5149
5150static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5151{
5152 const __le32 *fw_data;
5153 uint32_t fw_size;
5154 const struct gfx_firmware_header_v1_0 *cp_hdr;
5155 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5156
5157 /* pfp ucode */
5158 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5159 adev->gfx.pfp_fw->data;
5160 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5161 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5162 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes));
5163 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5164 FIRMWARE_ID_CP_PFP,
5165 fw_data, fw_size);
5166
5167 /* ce ucode */
5168 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5169 adev->gfx.ce_fw->data;
5170 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5171 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5172 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes));
5173 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5174 FIRMWARE_ID_CP_CE,
5175 fw_data, fw_size);
5176
5177 /* me ucode */
5178 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5179 adev->gfx.me_fw->data;
5180 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5181 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5182 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes));
5183 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5184 FIRMWARE_ID_CP_ME,
5185 fw_data, fw_size);
5186
5187 /* rlc ucode */
5188 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5189 adev->gfx.rlc_fw->data;
5190 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5191 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)((__uint32_t)(rlc_hdr->header.ucode_array_offset_bytes)));
5192 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes)((__uint32_t)(rlc_hdr->header.ucode_size_bytes));
5193 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5194 FIRMWARE_ID_RLC_G_UCODE,
5195 fw_data, fw_size);
5196
5197 /* mec1 ucode */
5198 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5199 adev->gfx.mec_fw->data;
5200 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5201 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5202 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes)) -
5203 cp_hdr->jt_size * 4;
5204 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5205 FIRMWARE_ID_CP_MEC,
5206 fw_data, fw_size);
5207 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5208}
5209
5210/* Temporarily put sdma part here */
5211static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5212{
5213 const __le32 *fw_data;
5214 uint32_t fw_size;
5215 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5216 int i;
5217
5218 for (i = 0; i < adev->sdma.num_instances; i++) {
5219 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5220 adev->sdma.instance[i].fw->data;
5221 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5222 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)((__uint32_t)(sdma_hdr->header.ucode_array_offset_bytes)));
5223 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes)((__uint32_t)(sdma_hdr->header.ucode_size_bytes));
5224
5225 if (i == 0) {
5226 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5227 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5228 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5229 FIRMWARE_ID_SDMA0_JT,
5230 (uint32_t *)fw_data +
5231 sdma_hdr->jt_offset,
5232 sdma_hdr->jt_size * 4);
5233 } else if (i == 1) {
5234 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5235 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5236 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5237 FIRMWARE_ID_SDMA1_JT,
5238 (uint32_t *)fw_data +
5239 sdma_hdr->jt_offset,
5240 sdma_hdr->jt_size * 4);
5241 }
5242 }
5243}
5244
5245static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5246{
5247 uint32_t rlc_g_offset, rlc_g_size, tmp;
5248 uint64_t gpu_addr;
5249
5250 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5251 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5252 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5253
5254 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5255 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5256 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5257
5258 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b5e)), (((u32)(((gpu_addr) >> 16) >> 16))),
0);
5259 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b5d)), (((u32)(gpu_addr))), 0);
5260 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5b5c)), (rlc_g_size), 0);
5261
5262 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5b54), 0);
5263 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK0x00000001L |
5264 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK0x00000002L))) {
5265 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n")__drm_err("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5266 return -EINVAL22;
5267 }
5268
5269 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), 0);
5270 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK0x00000001L) {
5271 DRM_ERROR("RLC ROM should halt itself\n")__drm_err("RLC ROM should halt itself\n");
5272 return -EINVAL22;
5273 }
5274
5275 return 0;
5276}
5277
5278static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5279{
5280 uint32_t usec_timeout = 50000; /* wait for 50ms */
5281 uint32_t tmp;
5282 int i;
5283 uint64_t addr;
5284
5285 /* Trigger an invalidation of the L1 instruction caches */
5286 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5847), 0);
5287 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5288 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5847)), (tmp), 0);
5289
5290 /* Wait for invalidation complete */
5291 for (i = 0; i < usec_timeout; i++) {
5292 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5847), 0);
5293 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5294 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5295 break;
5296 udelay(1);
5297 }
5298
5299 if (i >= usec_timeout) {
5300 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5301 return -EINVAL22;
5302 }
5303
5304 /* Program me ucode address into intruction cache address register */
5305 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5306 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5307 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5844)), (((u32)(addr)) & 0xFFFFF000), 0)
5308 lower_32_bits(addr) & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5844)), (((u32)(addr)) & 0xFFFFF000), 0);
5309 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5845)), (((u32)(((addr) >> 16) >> 16))), 0)
5310 upper_32_bits(addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5845)), (((u32)(((addr) >> 16) >> 16))), 0);
5311
5312 return 0;
5313}
5314
5315static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5316{
5317 uint32_t usec_timeout = 50000; /* wait for 50ms */
5318 uint32_t tmp;
5319 int i;
5320 uint64_t addr;
5321
5322 /* Trigger an invalidation of the L1 instruction caches */
5323 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584b), 0);
5324 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5325 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584b)), (tmp), 0);
5326
5327 /* Wait for invalidation complete */
5328 for (i = 0; i < usec_timeout; i++) {
5329 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584b), 0);
5330 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5331 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5332 break;
5333 udelay(1);
5334 }
5335
5336 if (i >= usec_timeout) {
5337 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5338 return -EINVAL22;
5339 }
5340
5341 /* Program ce ucode address into intruction cache address register */
5342 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5343 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5344 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5848)), (((u32)(addr)) & 0xFFFFF000), 0)
5345 lower_32_bits(addr) & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5848)), (((u32)(addr)) & 0xFFFFF000), 0);
5346 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5849)), (((u32)(((addr) >> 16) >> 16))), 0)
5347 upper_32_bits(addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5849)), (((u32)(((addr) >> 16) >> 16))), 0);
5348
5349 return 0;
5350}
5351
5352static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5353{
5354 uint32_t usec_timeout = 50000; /* wait for 50ms */
5355 uint32_t tmp;
5356 int i;
5357 uint64_t addr;
5358
5359 /* Trigger an invalidation of the L1 instruction caches */
5360 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5843), 0);
5361 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5362 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5843)), (tmp), 0);
5363
5364 /* Wait for invalidation complete */
5365 for (i = 0; i < usec_timeout; i++) {
5366 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5843), 0);
5367 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5368 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5369 break;
5370 udelay(1);
5371 }
5372
5373 if (i >= usec_timeout) {
5374 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5375 return -EINVAL22;
5376 }
5377
5378 /* Program pfp ucode address into intruction cache address register */
5379 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5380 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5381 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5840)), (((u32)(addr)) & 0xFFFFF000), 0)
5382 lower_32_bits(addr) & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5840)), (((u32)(addr)) & 0xFFFFF000), 0);
5383 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5841)), (((u32)(((addr) >> 16) >> 16))), 0)
5384 upper_32_bits(addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5841)), (((u32)(((addr) >> 16) >> 16))), 0);
5385
5386 return 0;
5387}
5388
5389static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5390{
5391 uint32_t usec_timeout = 50000; /* wait for 50ms */
5392 uint32_t tmp;
5393 int i;
5394 uint64_t addr;
5395
5396 /* Trigger an invalidation of the L1 instruction caches */
5397 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584f), 0);
5398 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5399 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584f)), (tmp), 0);
5400
5401 /* Wait for invalidation complete */
5402 for (i = 0; i < usec_timeout; i++) {
5403 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584f), 0);
5404 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5405 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5406 break;
5407 udelay(1);
5408 }
5409
5410 if (i >= usec_timeout) {
5411 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5412 return -EINVAL22;
5413 }
5414
5415 /* Program mec1 ucode address into intruction cache address register */
5416 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5417 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5418 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584c)), (((u32)(addr)) & 0xFFFFF000), 0)
5419 lower_32_bits(addr) & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584c)), (((u32)(addr)) & 0xFFFFF000), 0);
5420 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584d)), (((u32)(((addr) >> 16) >> 16))), 0)
5421 upper_32_bits(addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584d)), (((u32)(((addr) >> 16) >> 16))), 0);
5422
5423 return 0;
5424}
5425
5426static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5427{
5428 uint32_t cp_status;
5429 uint32_t bootload_status;
5430 int i, r;
5431
5432 for (i = 0; i < adev->usec_timeout; i++) {
5433 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0f40), 0);
5434 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4e8d), 0);
5435 if ((cp_status == 0) &&
5436 (REG_GET_FIELD(bootload_status,(((bootload_status) & 0x80000000L) >> 0x1f)
5437 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE)(((bootload_status) & 0x80000000L) >> 0x1f) == 1)) {
5438 break;
5439 }
5440 udelay(1);
5441 }
5442
5443 if (i >= adev->usec_timeout) {
5444 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n")printf("drm:pid%d:%s *ERROR* " "rlc autoload: gc ucode autoload timeout\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5445 return -ETIMEDOUT60;
5446 }
5447
5448 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5449 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5450 if (r)
5451 return r;
5452
5453 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5454 if (r)
5455 return r;
5456
5457 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5458 if (r)
5459 return r;
5460
5461 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5462 if (r)
5463 return r;
5464 }
5465
5466 return 0;
5467}
5468
5469static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool_Bool enable)
5470{
5471 int i;
5472 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0f56), 0);
5473
5474 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((enable ? 0
: 1) << 0x1c)));
5475 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1)(((tmp) & ~0x04000000L) | (0x04000000L & ((enable ? 0
: 1) << 0x1a)));
5476 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((enable ? 0
: 1) << 0x18)));
5477
5478 if (adev->asic_type == CHIP_NAVI12) {
5479 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0f56; do { if (((((adev))->virt.caps & (1 <<
2)) && !(((adev))->virt.caps & (1 << 4)
))) { uint32_t i = 0; uint32_t retries = 50000; uint32_t r0 =
adev->reg_offset[GC_HWIP][0][1] + 0x2040; uint32_t r1 = adev
->reg_offset[GC_HWIP][0][1] + 0x2041; uint32_t spare_int =
adev->reg_offset[GC_HWIP][0][1] + 0x4ccc; amdgpu_device_wreg
(adev, (r0), (tmp), 0); amdgpu_device_wreg(adev, (r1), ((target_reg
| 0x80000000)), 0); amdgpu_device_wreg(adev, (spare_int), (0x1
), 0); for (i = 0; i < retries; i++) { u32 tmp = amdgpu_device_rreg
(adev, (r1), 0); if (!(tmp & 0x80000000)) break; udelay(10
); } if (i >= retries) printk("\0013" "amdgpu: " "timeout: rlcg program reg:0x%05x failed !\n"
, target_reg); } else { amdgpu_device_wreg(adev, (target_reg)
, (tmp), 0); } } while (0); } while (0);
5480 } else {
5481 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f56)), (tmp), 0);
5482 }
5483
5484 for (i = 0; i < adev->usec_timeout; i++) {
5485 if (RREG32_SOC15(GC, 0, mmCP_STAT)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0f40), 0) == 0)
5486 break;
5487 udelay(1);
5488 }
5489
5490 if (i >= adev->usec_timeout)
5491 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt")__drm_err("failed to %s cp gfx\n", enable ? "unhalt" : "halt"
);
5492
5493 return 0;
5494}
5495
5496static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5497{
5498 int r;
5499 const struct gfx_firmware_header_v1_0 *pfp_hdr;
5500 const __le32 *fw_data;
5501 unsigned i, fw_size;
5502 uint32_t tmp;
5503 uint32_t usec_timeout = 50000; /* wait for 50ms */
5504
5505 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5506 adev->gfx.pfp_fw->data;
5507
5508 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5509
5510 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5511 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(pfp_hdr->header.ucode_array_offset_bytes)));
5512 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes)((__uint32_t)(pfp_hdr->header.ucode_size_bytes));
5513
5514 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5515 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
5516 &adev->gfx.pfp.pfp_fw_obj,
5517 &adev->gfx.pfp.pfp_fw_gpu_addr,
5518 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5519 if (r) {
5520 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create pfp fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5521 gfx_v10_0_pfp_fini(adev);
5522 return r;
5523 }
5524
5525 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size)__builtin_memcpy((adev->gfx.pfp.pfp_fw_ptr), (fw_data), (fw_size
));
5526
5527 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5528 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5529
5530 /* Trigger an invalidation of the L1 instruction caches */
5531 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5843), 0);
5532 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5533 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5843)), (tmp), 0);
5534
5535 /* Wait for invalidation complete */
5536 for (i = 0; i < usec_timeout; i++) {
5537 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5843), 0);
5538 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5539 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5540 break;
5541 udelay(1);
5542 }
5543
5544 if (i >= usec_timeout) {
5545 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5546 return -EINVAL22;
5547 }
5548
5549 if (amdgpu_emu_mode == 1)
5550 adev->nbio.funcs->hdp_flush(adev, NULL((void *)0));
5551
5552 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5842), 0);
5553 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
5554 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
5555 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
5556 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
5557 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5842)), (tmp), 0);
5558 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5840)), (adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000
), 0)
5559 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5840)), (adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000
), 0);
5560 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5841)), (((u32)(((adev->gfx.pfp.pfp_fw_gpu_addr) >>
16) >> 16))), 0)
5561 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5841)), (((u32)(((adev->gfx.pfp.pfp_fw_gpu_addr) >>
16) >> 16))), 0);
5562
5563 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5814)), (0), 0);
5564
5565 for (i = 0; i < pfp_hdr->jt_size; i++)
5566 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5815)), (((__uint32_t)(*(__uint32_t *)(fw_data + pfp_hdr
->jt_offset + i)))), 0)
5567 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5815)), (((__uint32_t)(*(__uint32_t *)(fw_data + pfp_hdr
->jt_offset + i)))), 0);
5568
5569 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5814)), (adev->gfx.pfp_fw_version), 0);
5570
5571 return 0;
5572}
5573
5574static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5575{
5576 int r;
5577 const struct gfx_firmware_header_v1_0 *ce_hdr;
5578 const __le32 *fw_data;
5579 unsigned i, fw_size;
5580 uint32_t tmp;
5581 uint32_t usec_timeout = 50000; /* wait for 50ms */
5582
5583 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5584 adev->gfx.ce_fw->data;
5585
5586 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5587
5588 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5589 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)((__uint32_t)(ce_hdr->header.ucode_array_offset_bytes)));
5590 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes)((__uint32_t)(ce_hdr->header.ucode_size_bytes));
5591
5592 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5593 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
5594 &adev->gfx.ce.ce_fw_obj,
5595 &adev->gfx.ce.ce_fw_gpu_addr,
5596 (void **)&adev->gfx.ce.ce_fw_ptr);
5597 if (r) {
5598 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create ce fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5599 gfx_v10_0_ce_fini(adev);
5600 return r;
5601 }
5602
5603 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size)__builtin_memcpy((adev->gfx.ce.ce_fw_ptr), (fw_data), (fw_size
));
5604
5605 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5606 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5607
5608 /* Trigger an invalidation of the L1 instruction caches */
5609 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584b), 0);
5610 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5611 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584b)), (tmp), 0);
5612
5613 /* Wait for invalidation complete */
5614 for (i = 0; i < usec_timeout; i++) {
5615 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584b), 0);
5616 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5617 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5618 break;
5619 udelay(1);
5620 }
5621
5622 if (i >= usec_timeout) {
5623 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5624 return -EINVAL22;
5625 }
5626
5627 if (amdgpu_emu_mode == 1)
5628 adev->nbio.funcs->hdp_flush(adev, NULL((void *)0));
5629
5630 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584a), 0);
5631 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
5632 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
5633 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
5634 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
5635 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5848)), (adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000
), 0)
5636 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5848)), (adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000
), 0);
5637 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5849)), (((u32)(((adev->gfx.ce.ce_fw_gpu_addr) >>
16) >> 16))), 0)
5638 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5849)), (((u32)(((adev->gfx.ce.ce_fw_gpu_addr) >>
16) >> 16))), 0);
5639
5640 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5818)), (0), 0);
5641
5642 for (i = 0; i < ce_hdr->jt_size; i++)
5643 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5819)), (((__uint32_t)(*(__uint32_t *)(fw_data + ce_hdr->
jt_offset + i)))), 0)
5644 le32_to_cpup(fw_data + ce_hdr->jt_offset + i))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5819)), (((__uint32_t)(*(__uint32_t *)(fw_data + ce_hdr->
jt_offset + i)))), 0);
5645
5646 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5818)), (adev->gfx.ce_fw_version), 0);
5647
5648 return 0;
5649}
5650
5651static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5652{
5653 int r;
5654 const struct gfx_firmware_header_v1_0 *me_hdr;
5655 const __le32 *fw_data;
5656 unsigned i, fw_size;
5657 uint32_t tmp;
5658 uint32_t usec_timeout = 50000; /* wait for 50ms */
5659
5660 me_hdr = (const struct gfx_firmware_header_v1_0 *)
5661 adev->gfx.me_fw->data;
5662
5663 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5664
5665 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5666 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)((__uint32_t)(me_hdr->header.ucode_array_offset_bytes)));
5667 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes)((__uint32_t)(me_hdr->header.ucode_size_bytes));
5668
5669 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5670 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
5671 &adev->gfx.me.me_fw_obj,
5672 &adev->gfx.me.me_fw_gpu_addr,
5673 (void **)&adev->gfx.me.me_fw_ptr);
5674 if (r) {
5675 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create me fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5676 gfx_v10_0_me_fini(adev);
5677 return r;
5678 }
5679
5680 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size)__builtin_memcpy((adev->gfx.me.me_fw_ptr), (fw_data), (fw_size
));
5681
5682 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5683 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5684
5685 /* Trigger an invalidation of the L1 instruction caches */
5686 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5847), 0);
5687 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5688 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5847)), (tmp), 0);
5689
5690 /* Wait for invalidation complete */
5691 for (i = 0; i < usec_timeout; i++) {
5692 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5847), 0);
5693 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5694 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5695 break;
5696 udelay(1);
5697 }
5698
5699 if (i >= usec_timeout) {
5700 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5701 return -EINVAL22;
5702 }
5703
5704 if (amdgpu_emu_mode == 1)
5705 adev->nbio.funcs->hdp_flush(adev, NULL((void *)0));
5706
5707 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x5846), 0);
5708 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
5709 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
5710 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
5711 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
5712 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5844)), (adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000
), 0)
5713 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5844)), (adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000
), 0);
5714 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5845)), (((u32)(((adev->gfx.me.me_fw_gpu_addr) >>
16) >> 16))), 0)
5715 upper_32_bits(adev->gfx.me.me_fw_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5845)), (((u32)(((adev->gfx.me.me_fw_gpu_addr) >>
16) >> 16))), 0);
5716
5717 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5816)), (0), 0);
5718
5719 for (i = 0; i < me_hdr->jt_size; i++)
5720 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5817)), (((__uint32_t)(*(__uint32_t *)(fw_data + me_hdr->
jt_offset + i)))), 0)
5721 le32_to_cpup(fw_data + me_hdr->jt_offset + i))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5817)), (((__uint32_t)(*(__uint32_t *)(fw_data + me_hdr->
jt_offset + i)))), 0);
5722
5723 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5816)), (adev->gfx.me_fw_version), 0);
5724
5725 return 0;
5726}
5727
5728static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5729{
5730 int r;
5731
5732 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5733 return -EINVAL22;
5734
5735 gfx_v10_0_cp_gfx_enable(adev, false0);
5736
5737 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5738 if (r) {
5739 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to load pfp fw\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5740 return r;
5741 }
5742
5743 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5744 if (r) {
5745 dev_err(adev->dev, "(%d) failed to load ce fw\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to load ce fw\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5746 return r;
5747 }
5748
5749 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5750 if (r) {
5751 dev_err(adev->dev, "(%d) failed to load me fw\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to load me fw\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5752 return r;
5753 }
5754
5755 return 0;
5756}
5757
5758static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5759{
5760 struct amdgpu_ring *ring;
5761 const struct cs_section_def *sect = NULL((void *)0);
5762 const struct cs_extent_def *ext = NULL((void *)0);
5763 int r, i;
5764 int ctx_reg_offset;
5765
5766 /* init the CP */
5767 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e4e)), (adev->gfx.config.max_hw_contexts - 1), 0)
5768 adev->gfx.config.max_hw_contexts - 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e4e)), (adev->gfx.config.max_hw_contexts - 1), 0);
5769 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1deb)), (1), 0);
5770
5771 gfx_v10_0_cp_gfx_enable(adev, true1);
5772
5773 ring = &adev->gfx.gfx_ring[0];
5774 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5775 if (r) {
5776 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r);
5777 return r;
5778 }
5779
5780 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5781 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE(2 << 28));
5782
5783 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
5784 amdgpu_ring_write(ring, 0x80000000);
5785 amdgpu_ring_write(ring, 0x80000000);
5786
5787 for (sect = gfx10_cs_data; sect->section != NULL((void *)0); ++sect) {
5788 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
5789 if (sect->id == SECT_CONTEXT) {
5790 amdgpu_ring_write(ring,
5791 PACKET3(PACKET3_SET_CONTEXT_REG,((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->
reg_count) & 0x3FFF) << 16)
5792 ext->reg_count)((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->
reg_count) & 0x3FFF) << 16));
5793 amdgpu_ring_write(ring, ext->reg_index -
5794 PACKET3_SET_CONTEXT_REG_START0x0000a000);
5795 for (i = 0; i < ext->reg_count; i++)
5796 amdgpu_ring_write(ring, ext->extent[i]);
5797 }
5798 }
5799 }
5800
5801 ctx_reg_offset =
5802 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE)(adev->reg_offset[GC_HWIP][0][1] + 0x00d7) - PACKET3_SET_CONTEXT_REG_START0x0000a000;
5803 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)((3 << 30) | (((0x69) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
5804 amdgpu_ring_write(ring, ctx_reg_offset);
5805 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5806
5807 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5808 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE(3 << 28));
5809
5810 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5811 amdgpu_ring_write(ring, 0);
5812
5813 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)((3 << 30) | (((0x11) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
5814 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)((3) << 0));
5815 amdgpu_ring_write(ring, 0x8000);
5816 amdgpu_ring_write(ring, 0x8000);
5817
5818 amdgpu_ring_commit(ring);
5819
5820 /* submit cs packet to copy state 0 to next available state */
5821 if (adev->gfx.num_gfx_rings > 1) {
5822 /* maximum supported gfx ring is 2 */
5823 ring = &adev->gfx.gfx_ring[1];
5824 r = amdgpu_ring_alloc(ring, 2);
5825 if (r) {
5826 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r);
5827 return r;
5828 }
5829
5830 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
5831 amdgpu_ring_write(ring, 0);
5832
5833 amdgpu_ring_commit(ring);
5834 }
5835 return 0;
5836}
5837
5838static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5839 CP_PIPE_ID pipe)
5840{
5841 u32 tmp;
5842
5843 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0dc2), 0);
5844 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe)(((tmp) & ~0x00000003L) | (0x00000003L & ((pipe) <<
0x0)));
5845
5846 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0dc2)), (tmp), 0);
5847}
5848
5849static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5850 struct amdgpu_ring *ring)
5851{
5852 u32 tmp;
5853
5854 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e8d), 0);
5855 if (ring->use_doorbell) {
5856 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
5857 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
5858 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
5859 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
5860 } else {
5861 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
5862 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
5863 }
5864 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8d)), (tmp), 0);
5865 switch (adev->asic_type) {
5866 case CHIP_SIENNA_CICHLID:
5867 case CHIP_NAVY_FLOUNDER:
5868 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x00000FFCL) | (0x00000FFCL & ((ring->doorbell_index
) << 0x2)))
5869 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index)(((0) & ~0x00000FFCL) | (0x00000FFCL & ((ring->doorbell_index
) << 0x2)));
5870 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfa)), (tmp), 0);
5871
5872 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfb)), (0x00000FFCL), 0)
5873 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfb)), (0x00000FFCL), 0);
5874 break;
5875 default:
5876 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
5877 DOORBELL_RANGE_LOWER, ring->doorbell_index)(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
5878 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfa)), (tmp), 0);
5879
5880 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfb)), (0x0FFFFFFCL), 0)
5881 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfb)), (0x0FFFFFFCL), 0);
5882 break;
5883 }
5884}
5885
5886static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5887{
5888 struct amdgpu_ring *ring;
5889 u32 tmp;
5890 u32 rb_bufsz;
5891 u64 rb_addr, rptr_addr, wptr_gpu_addr;
5892 u32 i;
5893
5894 /* Set the write pointer delay */
5895 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f61)), (0), 0);
5896
5897 /* set the RB to use vmid 0 */
5898 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df1)), (0), 0);
5899
5900 /* Init gfx ring 0 for pipe 0 */
5901 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
5902 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5903
5904 /* Set ring buffer size */
5905 ring = &adev->gfx.gfx_ring[0];
5906 rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
5907 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
5908 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
5909#ifdef __BIG_ENDIAN
5910 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1)(((tmp) & ~0x00030000L) | (0x00030000L & ((1) <<
0x10)));
5911#endif
5912 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1de1)), (tmp), 0);
5913
5914 /* Initialize the ring buffer's write pointers */
5915 ring->wptr = 0;
5916 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df4)), (((u32)(ring->wptr))), 0);
5917 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df5)), (((u32)(((ring->wptr) >> 16) >> 16
))), 0);
5918
5919 /* set the wb address wether it's enabled or not */
5920 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5921 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1de3)), (((u32)(rptr_addr))), 0);
5922 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1de4)), (((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL), 0)
5923 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1de4)), (((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL), 0);
5924
5925 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5926 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8b)), (((u32)(wptr_gpu_addr))), 0)
5927 lower_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8b)), (((u32)(wptr_gpu_addr))), 0);
5928 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8c)), (((u32)(((wptr_gpu_addr) >> 16) >> 16
))), 0)
5929 upper_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8c)), (((u32)(((wptr_gpu_addr) >> 16) >> 16
))), 0);
5930
5931 mdelay(1);
5932 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1de1)), (tmp), 0);
5933
5934 rb_addr = ring->gpu_addr >> 8;
5935 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1de0)), (rb_addr), 0);
5936 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e51)), (((u32)(((rb_addr) >> 16) >> 16))), 0
);
5937
5938 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1f40)), (1), 0);
5939
5940 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5941 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
5942
5943 /* Init gfx ring 1 for pipe 1 */
5944 if (adev->gfx.num_gfx_rings > 1) {
5945 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
5946 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5947 /* maximum supported gfx ring is 2 */
5948 ring = &adev->gfx.gfx_ring[1];
5949 rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
5950 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
5951 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
5952 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e01)), (tmp), 0);
5953 /* Initialize the ring buffer's write pointers */
5954 ring->wptr = 0;
5955 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df6)), (((u32)(ring->wptr))), 0);
5956 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df7)), (((u32)(((ring->wptr) >> 16) >> 16
))), 0);
5957 /* Set the wb address wether it's enabled or not */
5958 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5959 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e02)), (((u32)(rptr_addr))), 0);
5960 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e03)), (((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL), 0)
5961 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e03)), (((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL), 0);
5962 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5963 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8b)), (((u32)(wptr_gpu_addr))), 0)
5964 lower_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8b)), (((u32)(wptr_gpu_addr))), 0);
5965 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8c)), (((u32)(((wptr_gpu_addr) >> 16) >> 16
))), 0)
5966 upper_32_bits(wptr_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8c)), (((u32)(((wptr_gpu_addr) >> 16) >> 16
))), 0);
5967
5968 mdelay(1);
5969 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e01)), (tmp), 0);
5970
5971 rb_addr = ring->gpu_addr >> 8;
5972 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e00)), (rb_addr), 0);
5973 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e52)), (((u32)(((rb_addr) >> 16) >> 16))), 0
);
5974 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1f41)), (1), 0);
5975
5976 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5977 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
5978 }
5979 /* Switch to pipe 0 */
5980 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
5981 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5982 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
5983
5984 /* start the ring */
5985 gfx_v10_0_cp_gfx_start(adev);
5986
5987 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5988 ring = &adev->gfx.gfx_ring[i];
5989 ring->sched.ready = true1;
5990 }
5991
5992 return 0;
5993}
5994
5995static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool_Bool enable)
5996{
5997 if (enable) {
5998 switch (adev->asic_type) {
5999 case CHIP_SIENNA_CICHLID:
6000 case CHIP_NAVY_FLOUNDER:
6001 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f55)), (0), 0);
6002 break;
6003 default:
6004 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0e2d)), (0), 0);
6005 break;
6006 }
6007 } else {
6008 switch (adev->asic_type) {
6009 case CHIP_SIENNA_CICHLID:
6010 case CHIP_NAVY_FLOUNDER:
6011 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f55)), ((0x40000000L | 0x10000000L)), 0)
6012 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f55)), ((0x40000000L | 0x10000000L)), 0)
6013 CP_MEC_CNTL__MEC_ME2_HALT_MASK))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f55)), ((0x40000000L | 0x10000000L)), 0);
6014 break;
6015 default:
6016 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0e2d)), ((0x40000000L | 0x10000000L)), 0)
6017 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0e2d)), ((0x40000000L | 0x10000000L)), 0)
6018 CP_MEC_CNTL__MEC_ME2_HALT_MASK))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0e2d)), ((0x40000000L | 0x10000000L)), 0);
6019 break;
6020 }
6021 adev->gfx.kiq.ring.sched.ready = false0;
6022 }
6023 udelay(50);
6024}
6025
6026static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6027{
6028 const struct gfx_firmware_header_v1_0 *mec_hdr;
6029 const __le32 *fw_data;
6030 unsigned i;
6031 u32 tmp;
6032 u32 usec_timeout = 50000; /* Wait for 50 ms */
6033
6034 if (!adev->gfx.mec_fw)
6035 return -EINVAL22;
6036
6037 gfx_v10_0_cp_compute_enable(adev, false0);
6038
6039 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6040 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6041
6042 fw_data = (const __le32 *)
6043 (adev->gfx.mec_fw->data +
6044 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes)));
6045
6046 /* Trigger an invalidation of the L1 instruction caches */
6047 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584f), 0);
6048 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
6049 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584f)), (tmp), 0);
6050
6051 /* Wait for invalidation complete */
6052 for (i = 0; i < usec_timeout; i++) {
6053 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584f), 0);
6054 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
6055 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
6056 break;
6057 udelay(1);
6058 }
6059
6060 if (i >= usec_timeout) {
6061 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
6062 return -EINVAL22;
6063 }
6064
6065 if (amdgpu_emu_mode == 1)
6066 adev->nbio.funcs->hdp_flush(adev, NULL((void *)0));
6067
6068 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x584e), 0);
6069 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
6070 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
6071 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
6072 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584e)), (tmp), 0);
6073
6074 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584c)), (adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000
), 0)
6075 0xFFFFF000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584c)), (adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000
), 0);
6076 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584d)), (((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >>
16) >> 16))), 0)
6077 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x584d)), (((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >>
16) >> 16))), 0);
6078
6079 /* MEC1 */
6080 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581a)), (0), 0);
6081
6082 for (i = 0; i < mec_hdr->jt_size; i++)
6083 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581b)), (((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr
->jt_offset + i)))), 0)
6084 le32_to_cpup(fw_data + mec_hdr->jt_offset + i))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581b)), (((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr
->jt_offset + i)))), 0);
6085
6086 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x581a)), (adev->gfx.mec_fw_version), 0);
6087
6088 /*
6089 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6090 * different microcode than MEC1.
6091 */
6092
6093 return 0;
6094}
6095
6096static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6097{
6098 uint32_t tmp;
6099 struct amdgpu_device *adev = ring->adev;
6100
6101 /* tell RLC which is KIQ queue */
6102 switch (adev->asic_type) {
6103 case CHIP_SIENNA_CICHLID:
6104 case CHIP_NAVY_FLOUNDER:
6105 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4ca1), 0);
6106 tmp &= 0xffffff00;
6107 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6108 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca1)), (tmp), 0);
6109 tmp |= 0x80;
6110 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca1)), (tmp), 0);
6111 break;
6112 default:
6113 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4caa), 0);
6114 tmp &= 0xffffff00;
6115 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6116 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4caa)), (tmp), 0);
6117 tmp |= 0x80;
6118 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4caa)), (tmp), 0);
6119 break;
6120 }
6121}
6122
6123static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6124{
6125 struct amdgpu_device *adev = ring->adev;
6126 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6127 uint64_t hqd_gpu_addr, wb_gpu_addr;
6128 uint32_t tmp;
6129 uint32_t rb_bufsz;
6130
6131 /* set up gfx hqd wptr */
6132 mqd->cp_gfx_hqd_wptr = 0;
6133 mqd->cp_gfx_hqd_wptr_hi = 0;
6134
6135 /* set the pointer to the MQD */
6136 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6137 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr)((u32)(((ring->mqd_gpu_addr) >> 16) >> 16));
6138
6139 /* set up mqd control */
6140 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e9a), 0);
6141 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6142 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x00000100L) | (0x00000100L & ((1) <<
0x8)));
6143 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
6144 mqd->cp_gfx_mqd_control = tmp;
6145
6146 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6147 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e81), 0);
6148 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6149 mqd->cp_gfx_hqd_vmid = 0;
6150
6151 /* set up default queue priority level
6152 * 0x0 = low priority, 0x1 = high priority */
6153 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e84), 0);
6154 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6155 mqd->cp_gfx_hqd_queue_priority = tmp;
6156
6157 /* set up time quantum */
6158 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e85), 0);
6159 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
6160 mqd->cp_gfx_hqd_quantum = tmp;
6161
6162 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6163 hqd_gpu_addr = ring->gpu_addr >> 8;
6164 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6165 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16));
6166
6167 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6168 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6169 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6170 mqd->cp_gfx_hqd_rptr_addr_hi =
6171 upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6172
6173 /* set up rb_wptr_poll addr */
6174 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6175 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6176 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6177
6178 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6179 rb_bufsz = order_base_2(ring->ring_size / 4)drm_order(ring->ring_size / 4) - 1;
6180 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e8f), 0);
6181 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz)(((tmp) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
6182 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
6183#ifdef __BIG_ENDIAN
6184 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1)(((tmp) & ~0x00030000L) | (0x00030000L & ((1) <<
0x10)));
6185#endif
6186 mqd->cp_gfx_hqd_cntl = tmp;
6187
6188 /* set up cp_doorbell_control */
6189 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e8d), 0);
6190 if (ring->use_doorbell) {
6191 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
6192 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
6193 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
6194 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6195 } else
6196 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
6197 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
6198 mqd->cp_rb_doorbell_control = tmp;
6199
6200 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6201 ring->wptr = 0;
6202 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e88), 0);
6203
6204 /* active the queue */
6205 mqd->cp_gfx_hqd_active = 1;
6206
6207 return 0;
6208}
6209
6210#ifdef BRING_UP_DEBUG
6211static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6212{
6213 struct amdgpu_device *adev = ring->adev;
6214 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6215
6216 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6217 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e91)), (mqd->cp_gfx_hqd_wptr), 0);
6218 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e92)), (mqd->cp_gfx_hqd_wptr_hi), 0);
6219
6220 /* set GFX_MQD_BASE */
6221 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fa9)), (mqd->cp_mqd_base_addr), 0);
6222 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1faa)), (mqd->cp_mqd_base_addr_hi), 0);
6223
6224 /* set GFX_MQD_CONTROL */
6225 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e9a)), (mqd->cp_gfx_mqd_control), 0);
6226
6227 /* set GFX_HQD_VMID to 0 */
6228 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e81)), (mqd->cp_gfx_hqd_vmid), 0);
6229
6230 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e84)), (mqd->cp_gfx_hqd_queue_priority), 0)
6231 mqd->cp_gfx_hqd_queue_priority)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e84)), (mqd->cp_gfx_hqd_queue_priority), 0);
6232 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e85)), (mqd->cp_gfx_hqd_quantum), 0);
6233
6234 /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6235 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e86)), (mqd->cp_gfx_hqd_base), 0);
6236 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e87)), (mqd->cp_gfx_hqd_base_hi), 0);
6237
6238 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6239 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e89)), (mqd->cp_gfx_hqd_rptr_addr), 0);
6240 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8a)), (mqd->cp_gfx_hqd_rptr_addr_hi), 0);
6241
6242 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6243 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8f)), (mqd->cp_gfx_hqd_cntl), 0);
6244
6245 /* set RB_WPTR_POLL_ADDR */
6246 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8b)), (mqd->cp_rb_wptr_poll_addr_lo), 0);
6247 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8c)), (mqd->cp_rb_wptr_poll_addr_hi), 0);
6248
6249 /* set RB_DOORBELL_CONTROL */
6250 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e8d)), (mqd->cp_rb_doorbell_control), 0);
6251
6252 /* active the queue */
6253 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e80)), (mqd->cp_gfx_hqd_active), 0);
6254
6255 return 0;
6256}
6257#endif
6258
6259static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6260{
6261 struct amdgpu_device *adev = ring->adev;
6262 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6263 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6264
6265 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6266 memset((void *)mqd, 0, sizeof(*mqd))__builtin_memset(((void *)mqd), (0), (sizeof(*mqd)));
6267 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6268 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6269 gfx_v10_0_gfx_mqd_init(ring);
6270#ifdef BRING_UP_DEBUG
6271 gfx_v10_0_gfx_queue_init_register(ring);
6272#endif
6273 nv_grbm_select(adev, 0, 0, 0, 0);
6274 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6275 if (adev->gfx.me.mqd_backup[mqd_idx])
6276 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd))__builtin_memcpy((adev->gfx.me.mqd_backup[mqd_idx]), (mqd)
, (sizeof(*mqd)));
6277 } else if (amdgpu_in_reset(adev)) {
6278 /* reset mqd with the backup copy */
6279 if (adev->gfx.me.mqd_backup[mqd_idx])
6280 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd))__builtin_memcpy((mqd), (adev->gfx.me.mqd_backup[mqd_idx])
, (sizeof(*mqd)));
6281 /* reset the ring */
6282 ring->wptr = 0;
6283 adev->wb.wb[ring->wptr_offs] = 0;
6284 amdgpu_ring_clear_ring(ring);
6285#ifdef BRING_UP_DEBUG
6286 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6287 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6288 gfx_v10_0_gfx_queue_init_register(ring);
6289 nv_grbm_select(adev, 0, 0, 0, 0);
6290 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6291#endif
6292 } else {
6293 amdgpu_ring_clear_ring(ring);
6294 }
6295
6296 return 0;
6297}
6298
6299#ifndef BRING_UP_DEBUG
6300static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6301{
6302 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6303 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6304 int r, i;
6305
6306 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6307 return -EINVAL22;
6308
6309 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6310 adev->gfx.num_gfx_rings);
6311 if (r) {
6312 DRM_ERROR("Failed to lock KIQ (%d).\n", r)__drm_err("Failed to lock KIQ (%d).\n", r);
6313 return r;
6314 }
6315
6316 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6317 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6318
6319 return amdgpu_ring_test_helper(kiq_ring);
6320}
6321#endif
6322
6323static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6324{
6325 int r, i;
6326 struct amdgpu_ring *ring;
6327
6328 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6329 ring = &adev->gfx.gfx_ring[i];
6330
6331 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
6332 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6333 goto done;
6334
6335 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6336 if (!r) {
6337 r = gfx_v10_0_gfx_init_queue(ring);
6338 amdgpu_bo_kunmap(ring->mqd_obj);
6339 ring->mqd_ptr = NULL((void *)0);
6340 }
6341 amdgpu_bo_unreserve(ring->mqd_obj);
6342 if (r)
6343 goto done;
6344 }
6345#ifndef BRING_UP_DEBUG
6346 r = gfx_v10_0_kiq_enable_kgq(adev);
6347 if (r)
6348 goto done;
6349#endif
6350 r = gfx_v10_0_cp_gfx_start(adev);
6351 if (r)
6352 goto done;
6353
6354 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6355 ring = &adev->gfx.gfx_ring[i];
6356 ring->sched.ready = true1;
6357 }
6358done:
6359 return r;
6360}
6361
6362static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6363{
6364 struct amdgpu_device *adev = ring->adev;
6365
6366 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6367 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->pipe,
6368 ring->queue)) {
6369 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6370 mqd->cp_hqd_queue_priority =
6371 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM15;
6372 }
6373 }
6374}
6375
6376static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6377{
6378 struct amdgpu_device *adev = ring->adev;
6379 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6380 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6381 uint32_t tmp;
6382
6383 mqd->header = 0xC0310800;
6384 mqd->compute_pipelinestat_enable = 0x00000001;
6385 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6386 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6387 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6388 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6389 mqd->compute_misc_reserved = 0x00000003;
6390
6391 eop_base_addr = ring->eop_gpu_addr >> 8;
6392 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6393 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr)((u32)(((eop_base_addr) >> 16) >> 16));
6394
6395 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6396 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fd0), 0);
6397 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(2048 / 4) - 1)) << 0x0)))
6398 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(2048 / 4) - 1)) << 0x0)));
6399
6400 mqd->cp_hqd_eop_control = tmp;
6401
6402 /* enable doorbell? */
6403 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fb8), 0);
6404
6405 if (ring->use_doorbell) {
6406 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
6407 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
6408 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
6409 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6410 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)))
6411 DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
6412 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)))
6413 DOORBELL_HIT, 0)(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)));
6414 } else {
6415 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
6416 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
6417 }
6418
6419 mqd->cp_hqd_pq_doorbell_control = tmp;
6420
6421 /* disable the queue if it's active */
6422 ring->wptr = 0;
6423 mqd->cp_hqd_dequeue_request = 0;
6424 mqd->cp_hqd_pq_rptr = 0;
6425 mqd->cp_hqd_pq_wptr_lo = 0;
6426 mqd->cp_hqd_pq_wptr_hi = 0;
6427
6428 /* set the pointer to the MQD */
6429 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6430 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr)((u32)(((ring->mqd_gpu_addr) >> 16) >> 16));
6431
6432 /* set MQD vmid to 0 */
6433 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fcb), 0);
6434 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6435 mqd->cp_mqd_control = tmp;
6436
6437 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6438 hqd_gpu_addr = ring->gpu_addr >> 8;
6439 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6440 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16));
6441
6442 /* set up the HQD, this is similar to CP_RB0_CNTL */
6443 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fba), 0);
6444 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(ring->ring_size / 4) - 1)) << 0x0)))
6445 (order_base_2(ring->ring_size / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(ring->ring_size / 4) - 1)) << 0x0)));
6446 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,(((tmp) & ~0x00003F00L) | (0x00003F00L & ((((drm_order
(4096 / 4) - 1) << 8)) << 0x8)))
6447 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8))(((tmp) & ~0x00003F00L) | (0x00003F00L & ((((drm_order
(4096 / 4) - 1) << 8)) << 0x8)));
6448#ifdef __BIG_ENDIAN
6449 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1)(((tmp) & ~0x00030000L) | (0x00030000L & ((1) <<
0x10)));
6450#endif
6451 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
6452 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
6453 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6454 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1)(((tmp) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)));
6455 mqd->cp_hqd_pq_control = tmp;
6456
6457 /* set the wb address whether it's enabled or not */
6458 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6459 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6460 mqd->cp_hqd_pq_rptr_report_addr_hi =
6461 upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6462
6463 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6464 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6465 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6466 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6467
6468 tmp = 0;
6469 /* enable the doorbell if requested */
6470 if (ring->use_doorbell) {
6471 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fb8), 0);
6472 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
6473 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
6474
6475 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
6476 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6477 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)))
6478 DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
6479 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)))
6480 DOORBELL_HIT, 0)(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)));
6481 }
6482
6483 mqd->cp_hqd_pq_doorbell_control = tmp;
6484
6485 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6486 ring->wptr = 0;
6487 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fb3), 0);
6488
6489 /* set the vmid for the queue */
6490 mqd->cp_hqd_vmid = 0;
6491
6492 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fad), 0);
6493 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53)(((tmp) & ~0x0003FF00L) | (0x0003FF00L & ((0x53) <<
0x8)));
6494 mqd->cp_hqd_persistent_state = tmp;
6495
6496 /* set MIN_IB_AVAIL_SIZE */
6497 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fbe), 0);
6498 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3)(((tmp) & ~0x00300000L) | (0x00300000L & ((3) <<
0x14)));
6499 mqd->cp_hqd_ib_control = tmp;
6500
6501 /* set static priority for a compute queue/ring */
6502 gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6503
6504 /* map_queues packet doesn't need activate the queue,
6505 * so only kiq need set this field.
6506 */
6507 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6508 mqd->cp_hqd_active = 1;
6509
6510 return 0;
6511}
6512
6513static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6514{
6515 struct amdgpu_device *adev = ring->adev;
6516 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6517 int j;
6518
6519 /* inactivate the queue */
6520 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
6521 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fab)), (0), 0);
6522
6523 /* disable wptr polling */
6524 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e23), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e23), 0) & ~0x80000000L) | (0) << 0x1f
), 0);
6525
6526 /* write the EOP addr */
6527 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fce)), (mqd->cp_hqd_eop_base_addr_lo), 0)
6528 mqd->cp_hqd_eop_base_addr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fce)), (mqd->cp_hqd_eop_base_addr_lo), 0);
6529 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fcf)), (mqd->cp_hqd_eop_base_addr_hi), 0)
6530 mqd->cp_hqd_eop_base_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fcf)), (mqd->cp_hqd_eop_base_addr_hi), 0);
6531
6532 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6533 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fd0)), (mqd->cp_hqd_eop_control), 0)
6534 mqd->cp_hqd_eop_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fd0)), (mqd->cp_hqd_eop_control), 0);
6535
6536 /* enable doorbell? */
6537 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb8)), (mqd->cp_hqd_pq_doorbell_control), 0)
6538 mqd->cp_hqd_pq_doorbell_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb8)), (mqd->cp_hqd_pq_doorbell_control), 0);
6539
6540 /* disable the queue if it's active */
6541 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fab), 0) & 1) {
6542 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fc1)), (1), 0);
6543 for (j = 0; j < adev->usec_timeout; j++) {
6544 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1fab), 0) & 1))
6545 break;
6546 udelay(1);
6547 }
6548 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fc1)), (mqd->cp_hqd_dequeue_request), 0)
6549 mqd->cp_hqd_dequeue_request)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fc1)), (mqd->cp_hqd_dequeue_request), 0);
6550 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb3)), (mqd->cp_hqd_pq_rptr), 0)
6551 mqd->cp_hqd_pq_rptr)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb3)), (mqd->cp_hqd_pq_rptr), 0);
6552 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fdf)), (mqd->cp_hqd_pq_wptr_lo), 0)
6553 mqd->cp_hqd_pq_wptr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fdf)), (mqd->cp_hqd_pq_wptr_lo), 0);
6554 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fe0)), (mqd->cp_hqd_pq_wptr_hi), 0)
6555 mqd->cp_hqd_pq_wptr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fe0)), (mqd->cp_hqd_pq_wptr_hi), 0);
6556 }
6557
6558 /* set the pointer to the MQD */
6559 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fa9)), (mqd->cp_mqd_base_addr_lo), 0)
6560 mqd->cp_mqd_base_addr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fa9)), (mqd->cp_mqd_base_addr_lo), 0);
6561 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1faa)), (mqd->cp_mqd_base_addr_hi), 0)
6562 mqd->cp_mqd_base_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1faa)), (mqd->cp_mqd_base_addr_hi), 0);
6563
6564 /* set MQD vmid to 0 */
6565 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fcb)), (mqd->cp_mqd_control), 0)
6566 mqd->cp_mqd_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fcb)), (mqd->cp_mqd_control), 0);
6567
6568 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6569 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb1)), (mqd->cp_hqd_pq_base_lo), 0)
6570 mqd->cp_hqd_pq_base_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb1)), (mqd->cp_hqd_pq_base_lo), 0);
6571 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb2)), (mqd->cp_hqd_pq_base_hi), 0)
6572 mqd->cp_hqd_pq_base_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb2)), (mqd->cp_hqd_pq_base_hi), 0);
6573
6574 /* set up the HQD, this is similar to CP_RB0_CNTL */
6575 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fba)), (mqd->cp_hqd_pq_control), 0)
6576 mqd->cp_hqd_pq_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fba)), (mqd->cp_hqd_pq_control), 0);
6577
6578 /* set the wb address whether it's enabled or not */
6579 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb4)), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0)
6580 mqd->cp_hqd_pq_rptr_report_addr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb4)), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0);
6581 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb5)), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0)
6582 mqd->cp_hqd_pq_rptr_report_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb5)), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0);
6583
6584 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6585 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb6)), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0)
6586 mqd->cp_hqd_pq_wptr_poll_addr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb6)), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0);
6587 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb7)), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0)
6588 mqd->cp_hqd_pq_wptr_poll_addr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb7)), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0);
6589
6590 /* enable the doorbell if requested */
6591 if (ring->use_doorbell) {
6592 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfc)), ((adev->doorbell_index.kiq * 2) << 2), 0
)
6593 (adev->doorbell_index.kiq * 2) << 2)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfc)), ((adev->doorbell_index.kiq * 2) << 2), 0
);
6594 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfd)), ((adev->doorbell_index.userqueue_end * 2) <<
2), 0)
6595 (adev->doorbell_index.userqueue_end * 2) << 2)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1dfd)), ((adev->doorbell_index.userqueue_end * 2) <<
2), 0);
6596 }
6597
6598 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb8)), (mqd->cp_hqd_pq_doorbell_control), 0)
6599 mqd->cp_hqd_pq_doorbell_control)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fb8)), (mqd->cp_hqd_pq_doorbell_control), 0);
6600
6601 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6602 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fdf)), (mqd->cp_hqd_pq_wptr_lo), 0)
6603 mqd->cp_hqd_pq_wptr_lo)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fdf)), (mqd->cp_hqd_pq_wptr_lo), 0);
6604 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fe0)), (mqd->cp_hqd_pq_wptr_hi), 0)
6605 mqd->cp_hqd_pq_wptr_hi)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fe0)), (mqd->cp_hqd_pq_wptr_hi), 0);
6606
6607 /* set the vmid for the queue */
6608 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fac)), (mqd->cp_hqd_vmid), 0);
6609
6610 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fad)), (mqd->cp_hqd_persistent_state), 0)
6611 mqd->cp_hqd_persistent_state)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fad)), (mqd->cp_hqd_persistent_state), 0);
6612
6613 /* activate the queue */
6614 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fab)), (mqd->cp_hqd_active), 0)
6615 mqd->cp_hqd_active)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1fab)), (mqd->cp_hqd_active), 0);
6616
6617 if (ring->use_doorbell)
6618 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e58), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e58), 0) & ~0x00000002L) | (1) << 0x1)
, 0);
6619
6620 return 0;
6621}
6622
6623static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6624{
6625 struct amdgpu_device *adev = ring->adev;
6626 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6627 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS8;
6628
6629 gfx_v10_0_kiq_setting(ring);
6630
6631 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6632 /* reset MQD to a clean status */
6633 if (adev->gfx.mec.mqd_backup[mqd_idx])
6634 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx]
), (sizeof(*mqd)));
6635
6636 /* reset ring buffer */
6637 ring->wptr = 0;
6638 amdgpu_ring_clear_ring(ring);
6639
6640 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6641 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6642 gfx_v10_0_kiq_init_register(ring);
6643 nv_grbm_select(adev, 0, 0, 0, 0);
6644 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6645 } else {
6646 memset((void *)mqd, 0, sizeof(*mqd))__builtin_memset(((void *)mqd), (0), (sizeof(*mqd)));
6647 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6648 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6649 gfx_v10_0_compute_mqd_init(ring);
6650 gfx_v10_0_kiq_init_register(ring);
6651 nv_grbm_select(adev, 0, 0, 0, 0);
6652 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6653
6654 if (adev->gfx.mec.mqd_backup[mqd_idx])
6655 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd
), (sizeof(*mqd)));
6656 }
6657
6658 return 0;
6659}
6660
6661static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6662{
6663 struct amdgpu_device *adev = ring->adev;
6664 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6665 int mqd_idx = ring - &adev->gfx.compute_ring[0];
6666
6667 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6668 memset((void *)mqd, 0, sizeof(*mqd))__builtin_memset(((void *)mqd), (0), (sizeof(*mqd)));
6669 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6670 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6671 gfx_v10_0_compute_mqd_init(ring);
6672 nv_grbm_select(adev, 0, 0, 0, 0);
6673 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6674
6675 if (adev->gfx.mec.mqd_backup[mqd_idx])
6676 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd
), (sizeof(*mqd)));
6677 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6678 /* reset MQD to a clean status */
6679 if (adev->gfx.mec.mqd_backup[mqd_idx])
6680 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx]
), (sizeof(*mqd)));
6681
6682 /* reset ring buffer */
6683 ring->wptr = 0;
6684 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0)({ typeof(*((atomic64_t *)&adev->wb.wb[ring->wptr_offs
])) __tmp = ((0)); *(volatile typeof(*((atomic64_t *)&adev
->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t *)&
adev->wb.wb[ring->wptr_offs])) = __tmp; __tmp; });
6685 amdgpu_ring_clear_ring(ring);
6686 } else {
6687 amdgpu_ring_clear_ring(ring);
6688 }
6689
6690 return 0;
6691}
6692
6693static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6694{
6695 struct amdgpu_ring *ring;
6696 int r;
6697
6698 ring = &adev->gfx.kiq.ring;
6699
6700 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
6701 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6702 return r;
6703
6704 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6705 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6706 return r;
6707
6708 gfx_v10_0_kiq_init_queue(ring);
6709 amdgpu_bo_kunmap(ring->mqd_obj);
6710 ring->mqd_ptr = NULL((void *)0);
6711 amdgpu_bo_unreserve(ring->mqd_obj);
6712 ring->sched.ready = true1;
6713 return 0;
6714}
6715
6716static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6717{
6718 struct amdgpu_ring *ring = NULL((void *)0);
6719 int r = 0, i;
6720
6721 gfx_v10_0_cp_compute_enable(adev, true1);
6722
6723 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6724 ring = &adev->gfx.compute_ring[i];
6725
6726 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
6727 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6728 goto done;
6729 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6730 if (!r) {
6731 r = gfx_v10_0_kcq_init_queue(ring);
6732 amdgpu_bo_kunmap(ring->mqd_obj);
6733 ring->mqd_ptr = NULL((void *)0);
6734 }
6735 amdgpu_bo_unreserve(ring->mqd_obj);
6736 if (r)
6737 goto done;
6738 }
6739
6740 r = amdgpu_gfx_enable_kcq(adev);
6741done:
6742 return r;
6743}
6744
6745static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6746{
6747 int r, i;
6748 struct amdgpu_ring *ring;
6749
6750 if (!(adev->flags & AMD_IS_APU))
6751 gfx_v10_0_enable_gui_idle_interrupt(adev, false0);
6752
6753 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6754 /* legacy firmware loading */
6755 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6756 if (r)
6757 return r;
6758
6759 r = gfx_v10_0_cp_compute_load_microcode(adev);
6760 if (r)
6761 return r;
6762 }
6763
6764 r = gfx_v10_0_kiq_resume(adev);
6765 if (r)
6766 return r;
6767
6768 r = gfx_v10_0_kcq_resume(adev);
6769 if (r)
6770 return r;
6771
6772 if (!amdgpu_async_gfx_ring) {
6773 r = gfx_v10_0_cp_gfx_resume(adev);
6774 if (r)
6775 return r;
6776 } else {
6777 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6778 if (r)
6779 return r;
6780 }
6781
6782 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6783 ring = &adev->gfx.gfx_ring[i];
6784 r = amdgpu_ring_test_helper(ring);
6785 if (r)
6786 return r;
6787 }
6788
6789 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6790 ring = &adev->gfx.compute_ring[i];
6791 r = amdgpu_ring_test_helper(ring);
6792 if (r)
6793 return r;
6794 }
6795
6796 return 0;
6797}
6798
6799static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool_Bool enable)
6800{
6801 gfx_v10_0_cp_gfx_enable(adev, enable);
6802 gfx_v10_0_cp_compute_enable(adev, enable);
6803}
6804
6805static bool_Bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6806{
6807 uint32_t data, pattern = 0xDEADBEEF;
6808
6809 /* check if mmVGT_ESGS_RING_SIZE_UMD
6810 * has been remapped to mmVGT_ESGS_RING_SIZE */
6811 switch (adev->asic_type) {
6812 case CHIP_SIENNA_CICHLID:
6813 case CHIP_NAVY_FLOUNDER:
6814 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0fc1), 0);
6815 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0fc1)), (0), 0);
6816 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2240)), (pattern), 0);
6817
6818 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0fc1), 0) == pattern) {
6819 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2240)), (data), 0);
6820 return true1;
6821 } else {
6822 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0fc1)), (data), 0);
6823 return false0;
6824 }
6825 break;
6826 default:
6827 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0fd2), 0);
6828 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0fd2)), (0), 0);
6829 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2240)), (pattern), 0);
6830
6831 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0fd2), 0) == pattern) {
6832 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2240)), (data), 0);
6833 return true1;
6834 } else {
6835 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0fd2)), (data), 0);
6836 return false0;
6837 }
6838 break;
6839 }
6840}
6841
6842static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6843{
6844 uint32_t data;
6845
6846 /* initialize cam_index to 0
6847 * index will auto-inc after each data writting */
6848 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a04)), (0), 0);
6849
6850 switch (adev->asic_type) {
6851 case CHIP_SIENNA_CICHLID:
6852 case CHIP_NAVY_FLOUNDER:
6853 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6854 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224e) <<
6855 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6856 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc3) <<
6857 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6858 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6859 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6860
6861 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6862 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2250) <<
6863 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6864 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc5) <<
6865 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6866 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6867 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6868
6869 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6870 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2261) <<
6871 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6872 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc6) <<
6873 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6874 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6875 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6876
6877 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6878 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224f) <<
6879 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6880 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc4) <<
6881 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6882 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6883 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6884
6885 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6886 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2240) <<
6887 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6888 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc1) <<
6889 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6890 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6891 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6892
6893 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6894 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2241) <<
6895 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6896 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc2) <<
6897 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6898 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6899 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6900
6901 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6902 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP)(adev->reg_offset[GC_HWIP][0][1] + 0x2440) <<
6903 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6904 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x11ec) <<
6905 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6906 break;
6907 default:
6908 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6909 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224e) <<
6910 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6911 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x1002) <<
6912 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6913 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6914 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6915
6916 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6917 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2250) <<
6918 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6919 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE)(adev->reg_offset[GC_HWIP][0][0] + 0x100e) <<
6920 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6921 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6922 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6923
6924 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6925 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2261) <<
6926 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6927 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI)(adev->reg_offset[GC_HWIP][0][0] + 0x1018) <<
6928 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6929 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6930 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6931
6932 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6933 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224f) <<
6934 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6935 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM)(adev->reg_offset[GC_HWIP][0][0] + 0x100c) <<
6936 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6937 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6938 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6939
6940 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6941 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2240) <<
6942 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6943 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x0fd2) <<
6944 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6945 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6946 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6947
6948 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6949 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2241) <<
6950 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6951 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x0fd3) <<
6952 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6953 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6954 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6955
6956 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6957 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP)(adev->reg_offset[GC_HWIP][0][1] + 0x2440) <<
6958 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
6959 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x11e0) <<
6960 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
6961 break;
6962 }
6963
6964 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a06)), (0), 0);
6965 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5a05)), (data), 0);
6966}
6967
6968static int gfx_v10_0_hw_init(void *handle)
6969{
6970 int r;
6971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6972
6973 if (!amdgpu_emu_mode)
6974 gfx_v10_0_init_golden_registers(adev);
6975
6976 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6977 /**
6978 * For gfx 10, rlc firmware loading relies on smu firmware is
6979 * loaded firstly, so in direct type, it has to load smc ucode
6980 * here before rlc.
6981 */
6982 if (adev->smu.ppt_funcs != NULL((void *)0)) {
6983 r = smu_load_microcode(&adev->smu);
6984 if (r)
6985 return r;
6986
6987 r = smu_check_fw_status(&adev->smu);
6988 if (r) {
6989 pr_err("SMC firmware status is not correct\n")printk("\0013" "amdgpu: " "SMC firmware status is not correct\n"
);
6990 return r;
6991 }
6992 }
6993 }
6994
6995 /* if GRBM CAM not remapped, set up the remapping */
6996 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6997 gfx_v10_0_setup_grbm_cam_remapping(adev);
6998
6999 gfx_v10_0_constants_init(adev);
7000
7001 r = gfx_v10_0_rlc_resume(adev);
7002 if (r)
7003 return r;
7004
7005 /*
7006 * init golden registers and rlc resume may override some registers,
7007 * reconfig them here
7008 */
7009 gfx_v10_0_tcp_harvest(adev);
7010
7011 r = gfx_v10_0_cp_resume(adev);
7012 if (r)
7013 return r;
7014
7015 if (adev->asic_type == CHIP_SIENNA_CICHLID)
7016 gfx_v10_3_program_pbb_mode(adev);
7017
7018 return r;
7019}
7020
7021#ifndef BRING_UP_DEBUG
7022static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7023{
7024 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7025 struct amdgpu_ring *kiq_ring = &kiq->ring;
7026 int i;
7027
7028 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7029 return -EINVAL22;
7030
7031 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7032 adev->gfx.num_gfx_rings))
7033 return -ENOMEM12;
7034
7035 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7036 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7037 PREEMPT_QUEUES, 0, 0);
7038
7039 return amdgpu_ring_test_helper(kiq_ring);
7040}
7041#endif
7042
7043static int gfx_v10_0_hw_fini(void *handle)
7044{
7045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7046 int r;
7047 uint32_t tmp;
7048
7049 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7050 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7051
7052 if (!adev->in_pci_err_recovery) {
7053#ifndef BRING_UP_DEBUG
7054 if (amdgpu_async_gfx_ring) {
7055 r = gfx_v10_0_kiq_disable_kgq(adev);
7056 if (r)
7057 DRM_ERROR("KGQ disable failed\n")__drm_err("KGQ disable failed\n");
7058 }
7059#endif
7060 if (amdgpu_gfx_disable_kcq(adev))
7061 DRM_ERROR("KCQ disable failed\n")__drm_err("KCQ disable failed\n");
7062 }
7063
7064 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
7065 gfx_v10_0_cp_gfx_enable(adev, false0);
7066 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7067 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4caa), 0);
7068 tmp &= 0xffffff00;
7069 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4caa)), (tmp), 0);
7070
7071 return 0;
7072 }
7073 gfx_v10_0_cp_enable(adev, false0);
7074 gfx_v10_0_enable_gui_idle_interrupt(adev, false0);
7075
7076 return 0;
7077}
7078
7079static int gfx_v10_0_suspend(void *handle)
7080{
7081 return gfx_v10_0_hw_fini(handle);
7082}
7083
7084static int gfx_v10_0_resume(void *handle)
7085{
7086 return gfx_v10_0_hw_init(handle);
7087}
7088
7089static bool_Bool gfx_v10_0_is_idle(void *handle)
7090{
7091 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7092
7093 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0da4), 0)) & 0x80000000L) >> 0x1f)
7094 GRBM_STATUS, GUI_ACTIVE)(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0da4), 0)) & 0x80000000L) >> 0x1f))
7095 return false0;
7096 else
7097 return true1;
7098}
7099
7100static int gfx_v10_0_wait_for_idle(void *handle)
7101{
7102 unsigned i;
7103 u32 tmp;
7104 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7105
7106 for (i = 0; i < adev->usec_timeout; i++) {
7107 /* read MC_STATUS */
7108 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da4), 0) &
7109 GRBM_STATUS__GUI_ACTIVE_MASK0x80000000L;
7110
7111 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)(((tmp) & 0x80000000L) >> 0x1f))
7112 return 0;
7113 udelay(1);
7114 }
7115 return -ETIMEDOUT60;
7116}
7117
7118static int gfx_v10_0_soft_reset(void *handle)
7119{
7120 u32 grbm_soft_reset = 0;
7121 u32 tmp;
7122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7123
7124 /* GRBM_STATUS */
7125 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da4), 0);
7126 if (tmp & (GRBM_STATUS__PA_BUSY_MASK0x02000000L | GRBM_STATUS__SC_BUSY_MASK0x01000000L |
7127 GRBM_STATUS__BCI_BUSY_MASK0x00800000L | GRBM_STATUS__SX_BUSY_MASK0x00100000L |
7128 GRBM_STATUS__TA_BUSY_MASK0x00004000L | GRBM_STATUS__DB_BUSY_MASK0x04000000L |
7129 GRBM_STATUS__CB_BUSY_MASK0x40000000L | GRBM_STATUS__GDS_BUSY_MASK0x00008000L |
7130 GRBM_STATUS__SPI_BUSY_MASK0x00400000L | GRBM_STATUS__GE_BUSY_NO_DMA_MASK0x00010000L)) {
7131 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7132 GRBM_SOFT_RESET, SOFT_RESET_CP,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7133 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)));
7134 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)))
7135 GRBM_SOFT_RESET, SOFT_RESET_GFX,(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)))
7136 1)(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)));
7137 }
7138
7139 if (tmp & (GRBM_STATUS__CP_BUSY_MASK0x20000000L | GRBM_STATUS__CP_COHERENCY_BUSY_MASK0x10000000L)) {
7140 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7141 GRBM_SOFT_RESET, SOFT_RESET_CP,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7142 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)));
7143 }
7144
7145 /* GRBM_STATUS2 */
7146 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da2), 0);
7147 switch (adev->asic_type) {
7148 case CHIP_SIENNA_CICHLID:
7149 case CHIP_NAVY_FLOUNDER:
7150 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)(((tmp) & 0x04000000L) >> 0x1a))
7151 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7152 GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7153 SOFT_RESET_RLC,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7154 1)(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
7155 break;
7156 default:
7157 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)(((tmp) & 0x01000000L) >> 0x18))
7158 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7159 GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7160 SOFT_RESET_RLC,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7161 1)(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
7162 break;
7163 }
7164
7165 if (grbm_soft_reset) {
7166 /* stop the rlc */
7167 gfx_v10_0_rlc_stop(adev);
7168
7169 /* Disable GFX parsing/prefetching */
7170 gfx_v10_0_cp_gfx_enable(adev, false0);
7171
7172 /* Disable MEC parsing/prefetching */
7173 gfx_v10_0_cp_compute_enable(adev, false0);
7174
7175 if (grbm_soft_reset) {
7176 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da8), 0);
7177 tmp |= grbm_soft_reset;
7178 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
7179 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0da8)), (tmp), 0);
7180 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da8), 0);
7181
7182 udelay(50);
7183
7184 tmp &= ~grbm_soft_reset;
7185 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0da8)), (tmp), 0);
7186 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0da8), 0);
7187 }
7188
7189 /* Wait a little for things to settle down */
7190 udelay(50);
7191 }
7192 return 0;
7193}
7194
7195static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7196{
7197 uint64_t clock;
7198
7199 amdgpu_gfx_off_ctrl(adev, false0);
7200 mutex_lock(&adev->gfx.gpu_clock_mutex)rw_enter_write(&adev->gfx.gpu_clock_mutex);
7201 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][
1] + 0x0103), 0) |
7202 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][
1] + 0x0102), 0) << 32ULL);
7203 mutex_unlock(&adev->gfx.gpu_clock_mutex)rw_exit_write(&adev->gfx.gpu_clock_mutex);
7204 amdgpu_gfx_off_ctrl(adev, true1);
7205 return clock;
7206}
7207
7208static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7209 uint32_t vmid,
7210 uint32_t gds_base, uint32_t gds_size,
7211 uint32_t gws_base, uint32_t gws_size,
7212 uint32_t oa_base, uint32_t oa_size)
7213{
7214 struct amdgpu_device *adev = ring->adev;
7215
7216 /* GDS Base */
7217 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7218 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE)(adev->reg_offset[GC_HWIP][0][0] + 0x20a0) + 2 * vmid,
7219 gds_base);
7220
7221 /* GDS Size */
7222 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7223 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x20a1) + 2 * vmid,
7224 gds_size);
7225
7226 /* GWS */
7227 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7228 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x20c0) + vmid,
7229 gws_size << GDS_GWS_VMID0__SIZE__SHIFT0x10 | gws_base);
7230
7231 /* OA */
7232 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7233 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x20d0) + vmid,
7234 (1 << (oa_size + oa_base)) - (1 << oa_base));
7235}
7236
7237static int gfx_v10_0_early_init(void *handle)
7238{
7239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7240
7241 switch (adev->asic_type) {
7242 case CHIP_NAVI10:
7243 case CHIP_NAVI14:
7244 case CHIP_NAVI12:
7245 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X1;
7246 break;
7247 case CHIP_SIENNA_CICHLID:
7248 case CHIP_NAVY_FLOUNDER:
7249 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid1;
7250 break;
7251 default:
7252 break;
7253 }
7254
7255 adev->gfx.num_compute_rings = amdgpu_num_kcq;
7256
7257 gfx_v10_0_set_kiq_pm4_funcs(adev);
7258 gfx_v10_0_set_ring_funcs(adev);
7259 gfx_v10_0_set_irq_funcs(adev);
7260 gfx_v10_0_set_gds_init(adev);
7261 gfx_v10_0_set_rlc_funcs(adev);
7262
7263 return 0;
7264}
7265
7266static int gfx_v10_0_late_init(void *handle)
7267{
7268 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7269 int r;
7270
7271 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7272 if (r)
7273 return r;
7274
7275 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7276 if (r)
7277 return r;
7278
7279 return 0;
7280}
7281
7282static bool_Bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7283{
7284 uint32_t rlc_cntl;
7285
7286 /* if RLC is not enabled, do nothing */
7287 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c00), 0);
7288 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)(((rlc_cntl) & 0x00000001L) >> 0x0)) ? true1 : false0;
7289}
7290
7291static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7292{
7293 uint32_t data;
7294 unsigned i;
7295
7296 data = RLC_SAFE_MODE__CMD_MASK0x00000001L;
7297 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT0x1);
7298
7299 switch (adev->asic_type) {
7300 case CHIP_SIENNA_CICHLID:
7301 case CHIP_NAVY_FLOUNDER:
7302 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca0)), (data), 0);
7303
7304 /* wait for RLC_SAFE_MODE */
7305 for (i = 0; i < adev->usec_timeout; i++) {
7306 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca0), 0)) & 0x00000001L) >> 0x0)
7307 RLC_SAFE_MODE, CMD)(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca0), 0)) & 0x00000001L) >> 0x0))
7308 break;
7309 udelay(1);
7310 }
7311 break;
7312 default:
7313 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c05)), (data), 0);
7314
7315 /* wait for RLC_SAFE_MODE */
7316 for (i = 0; i < adev->usec_timeout; i++) {
7317 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c05), 0)) & 0x00000001L) >> 0x0)
7318 RLC_SAFE_MODE, CMD)(((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c05), 0)) & 0x00000001L) >> 0x0))
7319 break;
7320 udelay(1);
7321 }
7322 break;
7323 }
7324}
7325
7326static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7327{
7328 uint32_t data;
7329
7330 data = RLC_SAFE_MODE__CMD_MASK0x00000001L;
7331 switch (adev->asic_type) {
7332 case CHIP_SIENNA_CICHLID:
7333 case CHIP_NAVY_FLOUNDER:
7334 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca0)), (data), 0);
7335 break;
7336 default:
7337 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c05)), (data), 0);
7338 break;
7339 }
7340}
7341
7342static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7343 bool_Bool enable)
7344{
7345 uint32_t data, def;
7346
7347 /* It is disabled by HW by default */
7348 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG(1 << 0))) {
7349 /* 0 - Disable some blocks' MGCG */
7350 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x2200)), (0xe0000000), 0);
7351 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5086)), (0xff000000), 0);
7352 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5084)), (0xff000000), 0);
7353 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x5085)), (0xff000000), 0);
7354
7355 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7356 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
7357 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L |
7358 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L |
7359 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L |
7360 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK0x00010000L);
7361
7362 if (def != data)
7363 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
7364
7365 /* MGLS is a global flag to control all MGLS in GFX */
7366 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS(1 << 1)) {
7367 /* 2 - RLC memory Light sleep */
7368 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS(1 << 7)) {
7369 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c06), 0);
7370 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L;
7371 if (def != data)
7372 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c06)), (data), 0);
7373 }
7374 /* 3 - CP memory Light sleep */
7375 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS(1 << 6)) {
7376 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e19), 0);
7377 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L;
7378 if (def != data)
7379 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e19)), (data), 0);
7380 }
7381 }
7382 } else {
7383 /* 1 - MGCG_OVERRIDE */
7384 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
7385 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L |
7386 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L |
7387 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L |
7388 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L);
7389 if (def != data)
7390 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
7391
7392 /* 2 - disable MGLS in CP */
7393 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e19), 0);
7394 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L) {
7395 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L;
7396 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e19)), (data), 0);
7397 }
7398
7399 /* 3 - disable MGLS in RLC */
7400 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c06), 0);
7401 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L) {
7402 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L;
7403 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c06)), (data), 0);
7404 }
7405
7406 }
7407}
7408
7409static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7410 bool_Bool enable)
7411{
7412 uint32_t data, def;
7413
7414 /* Enable 3D CGCG/CGLS */
7415 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG(1 << 20))) {
7416 /* write cmd to clear cgcg/cgls ov */
7417 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
7418 /* unset CGCG override */
7419 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK0x00000080L;
7420 /* update CGCG and CGLS override bits */
7421 if (def != data)
7422 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
7423 /* enable 3Dcgcg FSM(0x0000363f) */
7424 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4cc5), 0);
7425 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
7426 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L;
7427 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS(1 << 21))
7428 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT0x2) |
7429 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L;
7430 if (def != data)
7431 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cc5)), (data), 0);
7432
7433 /* set IDLE_POLL_COUNT(0x00900100) */
7434 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0f62), 0);
7435 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT0x0) |
7436 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
7437 if (def != data)
7438 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f62)), (data), 0);
7439 } else {
7440 /* Disable CGCG/CGLS */
7441 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4cc5), 0);
7442 /* disable cgcg, cgls should be disabled */
7443 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L |
7444 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L);
7445 /* disable cgcg and cgls in FSM */
7446 if (def != data)
7447 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4cc5)), (data), 0);
7448 }
7449}
7450
7451static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7452 bool_Bool enable)
7453{
7454 uint32_t def, data;
7455
7456 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG(1 << 2))) {
7457 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c48), 0);
7458 /* unset CGCG override */
7459 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK0x00000008L;
7460 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1 << 3))
7461 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK0x00000010L;
7462 else
7463 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK0x00000010L;
7464 /* update CGCG and CGLS override bits */
7465 if (def != data)
7466 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c48)), (data), 0);
7467
7468 /* enable cgcg FSM(0x0000363F) */
7469 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c49), 0);
7470 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
7471 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L;
7472 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1 << 3))
7473 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT0x2) |
7474 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L;
7475 if (def != data)
7476 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c49)), (data), 0);
7477
7478 /* set IDLE_POLL_COUNT(0x00900100) */
7479 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0f62), 0);
7480 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT0x0) |
7481 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
7482 if (def != data)
7483 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x0f62)), (data), 0);
7484 } else {
7485 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][1] +
0x4c49), 0);
7486 /* reset CGCG/CGLS bits */
7487 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L);
7488 /* disable cgcg and cgls in FSM */
7489 if (def != data)
7490 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c49)), (data), 0);
7491 }
7492}
7493
7494static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7495 bool_Bool enable)
7496{
7497 amdgpu_gfx_rlc_enter_safe_mode(adev);
7498
7499 if (enable) {
7500 /* CGCG/CGLS should be enabled after MGCG/MGLS
7501 * === MGCG + MGLS ===
7502 */
7503 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7504 /* === CGCG /CGLS for GFX 3D Only === */
7505 gfx_v10_0_update_3d_clock_gating(adev, enable);
7506 /* === CGCG + CGLS === */
7507 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7508 } else {
7509 /* CGCG/CGLS should be disabled before MGCG/MGLS
7510 * === CGCG + CGLS ===
7511 */
7512 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7513 /* === CGCG /CGLS for GFX 3D Only === */
7514 gfx_v10_0_update_3d_clock_gating(adev, enable);
7515 /* === MGCG + MGLS === */
7516 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7517 }
7518
7519 if (adev->cg_flags &
7520 (AMD_CG_SUPPORT_GFX_MGCG(1 << 0) |
7521 AMD_CG_SUPPORT_GFX_CGLS(1 << 3) |
7522 AMD_CG_SUPPORT_GFX_CGCG(1 << 2) |
7523 AMD_CG_SUPPORT_GFX_3D_CGCG(1 << 20) |
7524 AMD_CG_SUPPORT_GFX_3D_CGLS(1 << 21)))
7525 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7526
7527 amdgpu_gfx_rlc_exit_safe_mode(adev);
7528
7529 return 0;
7530}
7531
7532static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7533{
7534 u32 reg, data;
7535
7536 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL)(adev->reg_offset[GC_HWIP][0][1] + 0x4c71);
7537 if (amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF))
7538 data = RREG32_NO_KIQ(reg)amdgpu_device_rreg(adev, (reg), (1<<1));
7539 else
7540 data = RREG32(reg)amdgpu_device_rreg(adev, (reg), 0);
7541
7542 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK0x0000000FL;
7543 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK0x0000000FL) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT0x0;
7544
7545 if (amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF))
7546 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c71)), (data), (1<<1));
7547 else
7548 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1]
+ 0x4c71)), (data), 0);
7549}
7550
7551static bool_Bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7552 uint32_t offset,
7553 struct soc15_reg_rlcg *entries, int arr_size)
7554{
7555 int i;
7556 uint32_t reg;
7557
7558 if (!entries)
7559 return false0;
7560
7561 for (i = 0; i < arr_size; i++) {
7562 const struct soc15_reg_rlcg *entry;
7563
7564 entry = &entries[i];
7565 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7566 if (offset == reg)
7567 return true1;
7568 }
7569
7570 return false0;
7571}
7572
7573static bool_Bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7574{
7575 return gfx_v10_0_check_rlcg_range(adev, offset, NULL((void *)0), 0);
7576}
7577
7578static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7579 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7580 .set_safe_mode = gfx_v10_0_set_safe_mode,
7581 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7582 .init = gfx_v10_0_rlc_init,
7583 .get_csb_size = gfx_v10_0_get_csb_size,
7584 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7585 .resume = gfx_v10_0_rlc_resume,
7586 .stop = gfx_v10_0_rlc_stop,
7587 .reset = gfx_v10_0_rlc_reset,
7588 .start = gfx_v10_0_rlc_start,
7589 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7590};
7591
7592static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7593 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7594 .set_safe_mode = gfx_v10_0_set_safe_mode,
7595 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7596 .init = gfx_v10_0_rlc_init,
7597 .get_csb_size = gfx_v10_0_get_csb_size,
7598 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7599 .resume = gfx_v10_0_rlc_resume,
7600 .stop = gfx_v10_0_rlc_stop,
7601 .reset = gfx_v10_0_rlc_reset,
7602 .start = gfx_v10_0_rlc_start,
7603 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7604 .rlcg_wreg = gfx_v10_rlcg_wreg,
7605 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7606};
7607
7608static int gfx_v10_0_set_powergating_state(void *handle,
7609 enum amd_powergating_state state)
7610{
7611 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7612 bool_Bool enable = (state == AMD_PG_STATE_GATE);
7613
7614 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
7615 return 0;
7616
7617 switch (adev->asic_type) {
7618 case CHIP_NAVI10:
7619 case CHIP_NAVI14:
7620 case CHIP_NAVI12:
7621 case CHIP_SIENNA_CICHLID:
7622 case CHIP_NAVY_FLOUNDER:
7623 amdgpu_gfx_off_ctrl(adev, enable);
7624 break;
7625 default:
7626 break;
7627 }
7628 return 0;
7629}
7630
7631static int gfx_v10_0_set_clockgating_state(void *handle,
7632 enum amd_clockgating_state state)
7633{
7634 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7635
7636 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
7637 return 0;
7638
7639 switch (adev->asic_type) {
7640 case CHIP_NAVI10:
7641 case CHIP_NAVI14:
7642 case CHIP_NAVI12:
7643 case CHIP_SIENNA_CICHLID:
7644 case CHIP_NAVY_FLOUNDER:
7645 gfx_v10_0_update_gfx_clock_gating(adev,
7646 state == AMD_CG_STATE_GATE);
7647 break;
7648 default:
7649 break;
7650 }
7651 return 0;
7652}
7653
7654static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7655{
7656 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7657 int data;
7658
7659 /* AMD_CG_SUPPORT_GFX_MGCG */
7660 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c48
)));
7661 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L))
7662 *flags |= AMD_CG_SUPPORT_GFX_MGCG(1 << 0);
7663
7664 /* AMD_CG_SUPPORT_GFX_CGCG */
7665 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c49
)));
7666 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L)
7667 *flags |= AMD_CG_SUPPORT_GFX_CGCG(1 << 2);
7668
7669 /* AMD_CG_SUPPORT_GFX_CGLS */
7670 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L)
7671 *flags |= AMD_CG_SUPPORT_GFX_CGLS(1 << 3);
7672
7673 /* AMD_CG_SUPPORT_GFX_RLC_LS */
7674 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c06
)));
7675 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L)
7676 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS(1 << 7) | AMD_CG_SUPPORT_GFX_MGLS(1 << 1);
7677
7678 /* AMD_CG_SUPPORT_GFX_CP_LS */
7679 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e19
)));
7680 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L)
7681 *flags |= AMD_CG_SUPPORT_GFX_CP_LS(1 << 6) | AMD_CG_SUPPORT_GFX_MGLS(1 << 1);
7682
7683 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7684 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4cc5
)));
7685 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L)
7686 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG(1 << 20);
7687
7688 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7689 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L)
7690 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS(1 << 21);
7691}
7692
7693static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7694{
7695 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7696}
7697
7698static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7699{
7700 struct amdgpu_device *adev = ring->adev;
7701 u64 wptr;
7702
7703 /* XXX check if swapping is necessary on BE */
7704 if (ring->use_doorbell) {
7705 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs])({ typeof(*((atomic64_t *)&adev->wb.wb[ring->wptr_offs
])) __tmp = *(volatile typeof(*((atomic64_t *)&adev->wb
.wb[ring->wptr_offs])) *)&(*((atomic64_t *)&adev->
wb.wb[ring->wptr_offs])); membar_datadep_consumer(); __tmp
; });
7706 } else {
7707 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1df4), 0);
7708 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1df5), 0) << 32;
7709 }
7710
7711 return wptr;
7712}
7713
7714static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7715{
7716 struct amdgpu_device *adev = ring->adev;
7717
7718 if (ring->use_doorbell) {
7719 /* XXX check if swapping is necessary on BE */
7720 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr)({ typeof(*((atomic64_t *)&adev->wb.wb[ring->wptr_offs
])) __tmp = ((ring->wptr)); *(volatile typeof(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) = __tmp; __tmp; }
);
7721 WDOORBELL64(ring->doorbell_index, ring->wptr)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr));
7722 } else {
7723 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df4)), (((u32)(ring->wptr))), 0);
7724 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr))amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1df5)), (((u32)(((ring->wptr) >> 16) >> 16
))), 0);
7725 }
7726}
7727
7728static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7729{
7730 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7731}
7732
7733static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7734{
7735 u64 wptr;
7736
7737 /* XXX check if swapping is necessary on BE */
7738 if (ring->use_doorbell)
7739 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs])({ typeof(*((atomic64_t *)&ring->adev->wb.wb[ring->
wptr_offs])) __tmp = *(volatile typeof(*((atomic64_t *)&ring
->adev->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t
*)&ring->adev->wb.wb[ring->wptr_offs])); membar_datadep_consumer
(); __tmp; });
7740 else
7741 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 7741); } while (0);
7742 return wptr;
7743}
7744
7745static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7746{
7747 struct amdgpu_device *adev = ring->adev;
7748
7749 /* XXX check if swapping is necessary on BE */
7750 if (ring->use_doorbell) {
7751 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr)({ typeof(*((atomic64_t *)&adev->wb.wb[ring->wptr_offs
])) __tmp = ((ring->wptr)); *(volatile typeof(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) *)&(*((atomic64_t
*)&adev->wb.wb[ring->wptr_offs])) = __tmp; __tmp; }
);
7752 WDOORBELL64(ring->doorbell_index, ring->wptr)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr));
7753 } else {
7754 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 7754); } while (0); /* only DOORBELL method supported on gfx10 now */
7755 }
7756}
7757
7758static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7759{
7760 struct amdgpu_device *adev = ring->adev;
7761 u32 ref_and_mask, reg_mem_engine;
7762 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7763
7764 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7765 switch (ring->me) {
7766 case 1:
7767 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7768 break;
7769 case 2:
7770 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7771 break;
7772 default:
7773 return;
7774 }
7775 reg_mem_engine = 0;
7776 } else {
7777 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7778 reg_mem_engine = 1; /* pfp */
7779 }
7780
7781 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7782 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7783 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7784 ref_and_mask, ref_and_mask, 0x20);
7785}
7786
7787static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7788 struct amdgpu_job *job,
7789 struct amdgpu_ib *ib,
7790 uint32_t flags)
7791{
7792 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
7793 u32 header, control = 0;
7794
7795 if (ib->flags & AMDGPU_IB_FLAG_CE(1<<0))
7796 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2)((3 << 30) | (((0x33) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
7797 else
7798 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x3F) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
7799
7800 control |= ib->length_dw | (vmid << 24);
7801
7802 if ((amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT(1<<2))) {
7803 control |= INDIRECT_BUFFER_PRE_ENB(1)((1) << 21);
7804
7805 if (flags & AMDGPU_IB_PREEMPTED(1 << 3))
7806 control |= INDIRECT_BUFFER_PRE_RESUME(1)((1) << 30);
7807
7808 if (!(ib->flags & AMDGPU_IB_FLAG_CE(1<<0)) && vmid)
7809 gfx_v10_0_ring_emit_de_meta(ring,
7810 (!amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) && flags & AMDGPU_IB_PREEMPTED(1 << 3)) ? true1 : false0);
7811 }
7812
7813 amdgpu_ring_write(ring, header);
7814 BUG_ON(ib->gpu_addr & 0x3)((!(ib->gpu_addr & 0x3)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 7814, "!(ib->gpu_addr & 0x3)"
)); /* Dword align */
7815 amdgpu_ring_write(ring,
7816#ifdef __BIG_ENDIAN
7817 (2 << 0) |
7818#endif
7819 lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
7820 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
7821 amdgpu_ring_write(ring, control);
7822}
7823
7824static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7825 struct amdgpu_job *job,
7826 struct amdgpu_ib *ib,
7827 uint32_t flags)
7828{
7829 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
7830 u32 control = INDIRECT_BUFFER_VALID(1 << 23) | ib->length_dw | (vmid << 24);
7831
7832 /* Currently, there is a high possibility to get wave ID mismatch
7833 * between ME and GDS, leading to a hw deadlock, because ME generates
7834 * different wave IDs than the GDS expects. This situation happens
7835 * randomly when at least 5 compute pipes use GDS ordered append.
7836 * The wave IDs generated by ME are also wrong after suspend/resume.
7837 * Those are probably bugs somewhere else in the kernel driver.
7838 *
7839 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7840 * GDS to 0 for this ring (me/pipe).
7841 */
7842 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID(1 << 4)) {
7843 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
7844 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID0x20e8);
7845 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7846 }
7847
7848 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x3F) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
7849 BUG_ON(ib->gpu_addr & 0x3)((!(ib->gpu_addr & 0x3)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 7849, "!(ib->gpu_addr & 0x3)"
)); /* Dword align */
7850 amdgpu_ring_write(ring,
7851#ifdef __BIG_ENDIAN
7852 (2 << 0) |
7853#endif
7854 lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
7855 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
7856 amdgpu_ring_write(ring, control);
7857}
7858
7859static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7860 u64 seq, unsigned flags)
7861{
7862 bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0);
7863 bool_Bool int_sel = flags & AMDGPU_FENCE_FLAG_INT(1 << 1);
7864
7865 /* RELEASE_MEM - flush caches, send int */
7866 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)((3 << 30) | (((0x49) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
7867 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ(1 << 22) |
7868 PACKET3_RELEASE_MEM_GCR_GL2_WB(1 << 21) |
7869 PACKET3_RELEASE_MEM_GCR_GLM_INV(1 << 13) | /* must be set with GLM_WB */
7870 PACKET3_RELEASE_MEM_GCR_GLM_WB(1 << 12) |
7871 PACKET3_RELEASE_MEM_CACHE_POLICY(3)((3) << 25) |
7872 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT)((CACHE_FLUSH_AND_INV_TS_EVENT) << 0) |
7873 PACKET3_RELEASE_MEM_EVENT_INDEX(5)((5) << 8)));
7874 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1)((write64bit ? 2 : 1) << 29) |
7875 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)((int_sel ? 2 : 0) << 24)));
7876
7877 /*
7878 * the address should be Qword aligned if 64bit write, Dword
7879 * aligned if only send 32bit data low (discard data high)
7880 */
7881 if (write64bit)
7882 BUG_ON(addr & 0x7)((!(addr & 0x7)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 7882, "!(addr & 0x7)"));
7883 else
7884 BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 7884, "!(addr & 0x3)"));
7885 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
7886 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
7887 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
7888 amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
7889 amdgpu_ring_write(ring, 0);
7890}
7891
7892static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7893{
7894 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7895 uint32_t seq = ring->fence_drv.sync_seq;
7896 uint64_t addr = ring->fence_drv.gpu_addr;
7897
7898 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr)((u32)(addr)),
7899 upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)), seq, 0xffffffff, 4);
7900}
7901
7902static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7903 unsigned vmid, uint64_t pd_addr)
7904{
7905 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring
), (vmid), (pd_addr));
7906
7907 /* compute doesn't have PFP */
7908 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7909 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7910 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)((3 << 30) | (((0x42) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
7911 amdgpu_ring_write(ring, 0x0);
7912 }
7913}
7914
7915static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7916 u64 seq, unsigned int flags)
7917{
7918 struct amdgpu_device *adev = ring->adev;
7919
7920 /* we only allocate 32bit for each seq wb address */
7921 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT)((!(flags & (1 << 0))) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 7921, "!(flags & (1 << 0))"
));
7922
7923 /* write fence seq to the "addr" */
7924 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
7925 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0)((0) << 30) |
7926 WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20)));
7927 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
7928 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
7929 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
7930
7931 if (flags & AMDGPU_FENCE_FLAG_INT(1 << 1)) {
7932 /* set register to trigger INT */
7933 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
7934 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0)((0) << 30) |
7935 WRITE_DATA_DST_SEL(0)((0) << 8) | WR_CONFIRM(1 << 20)));
7936 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)(adev->reg_offset[GC_HWIP][0][0] + 0x1e55));
7937 amdgpu_ring_write(ring, 0);
7938 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7939 }
7940}
7941
7942static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7943{
7944 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)((3 << 30) | (((0x8B) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
7945 amdgpu_ring_write(ring, 0);
7946}
7947
7948static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7949 uint32_t flags)
7950{
7951 uint32_t dw2 = 0;
7952
7953 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)))
7954 gfx_v10_0_ring_emit_ce_meta(ring,
7955 (!amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) && flags & AMDGPU_IB_PREEMPTED(1 << 3)) ? true1 : false0);
7956
7957 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7958 if (flags & AMDGPU_HAVE_CTX_SWITCH(1 << 2)) {
7959 /* set load_global_config & load_global_uconfig */
7960 dw2 |= 0x8001;
7961 /* set load_cs_sh_regs */
7962 dw2 |= 0x01000000;
7963 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7964 dw2 |= 0x10002;
7965
7966 /* set load_ce_ram if preamble presented */
7967 if (AMDGPU_PREAMBLE_IB_PRESENT(1 << 0) & flags)
7968 dw2 |= 0x10000000;
7969 } else {
7970 /* still load_ce_ram if this is the first time preamble presented
7971 * although there is no context switch happens.
7972 */
7973 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST(1 << 1) & flags)
7974 dw2 |= 0x10000000;
7975 }
7976
7977 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
7978 amdgpu_ring_write(ring, dw2);
7979 amdgpu_ring_write(ring, 0);
7980}
7981
7982static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7983{
7984 unsigned ret;
7985
7986 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)((3 << 30) | (((0x22) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
7987 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)((u32)(ring->cond_exe_gpu_addr)));
7988 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)((u32)(((ring->cond_exe_gpu_addr) >> 16) >> 16
)));
7989 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7990 ret = ring->wptr & ring->buf_mask;
7991 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7992
7993 return ret;
7994}
7995
7996static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7997{
7998 unsigned cur;
7999 BUG_ON(offset > ring->buf_mask)((!(offset > ring->buf_mask)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 7999, "!(offset > ring->buf_mask)"
));
8000 BUG_ON(ring->ring[offset] != 0x55aa55aa)((!(ring->ring[offset] != 0x55aa55aa)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8000, "!(ring->ring[offset] != 0x55aa55aa)"));
8001
8002 cur = (ring->wptr - 1) & ring->buf_mask;
8003 if (likely(cur > offset)__builtin_expect(!!(cur > offset), 1))
8004 ring->ring[offset] = cur - offset;
8005 else
8006 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8007}
8008
8009static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8010{
8011 int i, r = 0;
8012 struct amdgpu_device *adev = ring->adev;
8013 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8014 struct amdgpu_ring *kiq_ring = &kiq->ring;
8015 unsigned long flags;
8016
8017 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8018 return -EINVAL22;
8019
8020 spin_lock_irqsave(&kiq->ring_lock, flags)do { flags = 0; mtx_enter(&kiq->ring_lock); } while (0
);
8021
8022 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8023 spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while
(0);
8024 return -ENOMEM12;
8025 }
8026
8027 /* assert preemption condition */
8028 amdgpu_ring_set_preempt_cond_exec(ring, false0);
8029
8030 /* assert IB preemption, emit the trailing fence */
8031 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8032 ring->trail_fence_gpu_addr,
8033 ++ring->trail_seq);
8034 amdgpu_ring_commit(kiq_ring);
8035
8036 spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while
(0);
8037
8038 /* poll the trailing fence */
8039 for (i = 0; i < adev->usec_timeout; i++) {
8040 if (ring->trail_seq ==
8041 le32_to_cpu(*(ring->trail_fence_cpu_addr))((__uint32_t)(*(ring->trail_fence_cpu_addr))))
8042 break;
8043 udelay(1);
8044 }
8045
8046 if (i >= adev->usec_timeout) {
8047 r = -EINVAL22;
8048 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx)__drm_err("ring %d failed to preempt ib\n", ring->idx);
8049 }
8050
8051 /* deassert preemption condition */
8052 amdgpu_ring_set_preempt_cond_exec(ring, true1);
8053 return r;
8054}
8055
8056static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool_Bool resume)
8057{
8058 struct amdgpu_device *adev = ring->adev;
8059 struct v10_ce_ib_state ce_payload = {0};
8060 uint64_t csa_addr;
8061 int cnt;
8062
8063 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8064 csa_addr = amdgpu_csa_vaddr(ring->adev);
8065
8066 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)((3 << 30) | (((0x37) & 0xFF) << 8) | ((cnt) &
0x3FFF) << 16));
8067 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2)((2) << 30) |
8068 WRITE_DATA_DST_SEL(8)((8) << 8) |
8069 WR_CONFIRM(1 << 20)) |
8070 WRITE_DATA_CACHE_POLICY(0)((0) << 25));
8071 amdgpu_ring_write(ring, lower_32_bits(csa_addr +((u32)(csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, ce_payload)))
8072 offsetof(struct v10_gfx_meta_data, ce_payload))((u32)(csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, ce_payload))));
8073 amdgpu_ring_write(ring, upper_32_bits(csa_addr +((u32)(((csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, ce_payload)) >> 16) >> 16))
8074 offsetof(struct v10_gfx_meta_data, ce_payload))((u32)(((csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, ce_payload)) >> 16) >> 16)));
8075
8076 if (resume)
8077 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8078 offsetof(struct v10_gfx_meta_data,__builtin_offsetof(struct v10_gfx_meta_data, ce_payload)
8079 ce_payload)__builtin_offsetof(struct v10_gfx_meta_data, ce_payload),
8080 sizeof(ce_payload) >> 2);
8081 else
8082 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8083 sizeof(ce_payload) >> 2);
8084}
8085
8086static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool_Bool resume)
8087{
8088 struct amdgpu_device *adev = ring->adev;
8089 struct v10_de_ib_state de_payload = {0};
8090 uint64_t csa_addr, gds_addr;
8091 int cnt;
8092
8093 csa_addr = amdgpu_csa_vaddr(ring->adev);
8094 gds_addr = roundup2(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,(((csa_addr + (128 * 1024) - adev->gds.gds_size) + (((1 <<
12)) - 1)) & (~((__typeof(csa_addr + (128 * 1024) - adev
->gds.gds_size))((1 << 12)) - 1)))
8095 PAGE_SIZE)(((csa_addr + (128 * 1024) - adev->gds.gds_size) + (((1 <<
12)) - 1)) & (~((__typeof(csa_addr + (128 * 1024) - adev
->gds.gds_size))((1 << 12)) - 1)));
8096 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr)((u32)(gds_addr));
8097 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr)((u32)(((gds_addr) >> 16) >> 16));
8098
8099 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8100 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)((3 << 30) | (((0x37) & 0xFF) << 8) | ((cnt) &
0x3FFF) << 16));
8101 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1)((1) << 30) |
8102 WRITE_DATA_DST_SEL(8)((8) << 8) |
8103 WR_CONFIRM(1 << 20)) |
8104 WRITE_DATA_CACHE_POLICY(0)((0) << 25));
8105 amdgpu_ring_write(ring, lower_32_bits(csa_addr +((u32)(csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, de_payload)))
8106 offsetof(struct v10_gfx_meta_data, de_payload))((u32)(csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, de_payload))));
8107 amdgpu_ring_write(ring, upper_32_bits(csa_addr +((u32)(((csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, de_payload)) >> 16) >> 16))
8108 offsetof(struct v10_gfx_meta_data, de_payload))((u32)(((csa_addr + __builtin_offsetof(struct v10_gfx_meta_data
, de_payload)) >> 16) >> 16)));
8109
8110 if (resume)
8111 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8112 offsetof(struct v10_gfx_meta_data,__builtin_offsetof(struct v10_gfx_meta_data, de_payload)
8113 de_payload)__builtin_offsetof(struct v10_gfx_meta_data, de_payload),
8114 sizeof(de_payload) >> 2);
8115 else
8116 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8117 sizeof(de_payload) >> 2);
8118}
8119
8120static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool_Bool start,
8121 bool_Bool secure)
8122{
8123 uint32_t v = secure ? FRAME_TMZ(1 << 0) : 0;
8124
8125 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)((3 << 30) | (((0x90) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
8126 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)((start ? 0 : 1) << 28));
8127}
8128
8129static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8130 uint32_t reg_val_offs)
8131{
8132 struct amdgpu_device *adev = ring->adev;
8133
8134 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)((3 << 30) | (((0x40) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
8135 amdgpu_ring_write(ring, 0 | /* src: register*/
8136 (5 << 8) | /* dst: memory */
8137 (1 << 20)); /* write confirm */
8138 amdgpu_ring_write(ring, reg);
8139 amdgpu_ring_write(ring, 0);
8140 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +((u32)(adev->wb.gpu_addr + reg_val_offs * 4))
8141 reg_val_offs * 4)((u32)(adev->wb.gpu_addr + reg_val_offs * 4)));
8142 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16))
8143 reg_val_offs * 4)((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16)));
8144}
8145
8146static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8147 uint32_t val)
8148{
8149 uint32_t cmd = 0;
8150
8151 switch (ring->funcs->type) {
8152 case AMDGPU_RING_TYPE_GFX:
8153 cmd = WRITE_DATA_ENGINE_SEL(1)((1) << 30) | WR_CONFIRM(1 << 20);
8154 break;
8155 case AMDGPU_RING_TYPE_KIQ:
8156 cmd = (1 << 16); /* no inc addr */
8157 break;
8158 default:
8159 cmd = WR_CONFIRM(1 << 20);
8160 break;
8161 }
8162 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
8163 amdgpu_ring_write(ring, cmd);
8164 amdgpu_ring_write(ring, reg);
8165 amdgpu_ring_write(ring, 0);
8166 amdgpu_ring_write(ring, val);
8167}
8168
8169static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8170 uint32_t val, uint32_t mask)
8171{
8172 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8173}
8174
8175static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8176 uint32_t reg0, uint32_t reg1,
8177 uint32_t ref, uint32_t mask)
8178{
8179 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8180 struct amdgpu_device *adev = ring->adev;
8181 bool_Bool fw_version_ok = false0;
8182
8183 fw_version_ok = adev->gfx.cp_fw_write_wait;
8184
8185 if (fw_version_ok)
8186 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8187 ref, mask, 0x20);
8188 else
8189 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8190 ref, mask);
8191}
8192
8193static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8194 unsigned vmid)
8195{
8196 struct amdgpu_device *adev = ring->adev;
8197 uint32_t value = 0;
8198
8199 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03)(((value) & ~0x0000000FL) | (0x0000000FL & ((0x03) <<
0x0)));
8200 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01)(((value) & ~0x00000070L) | (0x00000070L & ((0x01) <<
0x4)));
8201 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1)(((value) & ~0x00000080L) | (0x00000080L & ((1) <<
0x7)));
8202 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid)(((value) & ~0xF0000000L) | (0xF0000000L & ((vmid) <<
0x1c)));
8203 WREG32_SOC15(GC, 0, mmSQ_CMD, value)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x111b)), (value), 0);
8204}
8205
8206static void
8207gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8208 uint32_t me, uint32_t pipe,
8209 enum amdgpu_interrupt_state state)
8210{
8211 uint32_t cp_int_cntl, cp_int_cntl_reg;
8212
8213 if (!me) {
8214 switch (pipe) {
8215 case 0:
8216 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)(adev->reg_offset[GC_HWIP][0][0] + 0x1e0a);
8217 break;
8218 case 1:
8219 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1)(adev->reg_offset[GC_HWIP][0][0] + 0x1e0b);
8220 break;
8221 default:
8222 DRM_DEBUG("invalid pipe %d\n", pipe)__drm_dbg(DRM_UT_CORE, "invalid pipe %d\n", pipe);
8223 return;
8224 }
8225 } else {
8226 DRM_DEBUG("invalid me %d\n", me)__drm_dbg(DRM_UT_CORE, "invalid me %d\n", me);
8227 return;
8228 }
8229
8230 switch (state) {
8231 case AMDGPU_IRQ_STATE_DISABLE:
8232 cp_int_cntl = RREG32(cp_int_cntl_reg)amdgpu_device_rreg(adev, (cp_int_cntl_reg), 0);
8233 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((0)
<< 0x1a)))
8234 TIME_STAMP_INT_ENABLE, 0)(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((0)
<< 0x1a)));
8235 WREG32(cp_int_cntl_reg, cp_int_cntl)amdgpu_device_wreg(adev, (cp_int_cntl_reg), (cp_int_cntl), 0);
8236 break;
8237 case AMDGPU_IRQ_STATE_ENABLE:
8238 cp_int_cntl = RREG32(cp_int_cntl_reg)amdgpu_device_rreg(adev, (cp_int_cntl_reg), 0);
8239 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((1)
<< 0x1a)))
8240 TIME_STAMP_INT_ENABLE, 1)(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((1)
<< 0x1a)));
8241 WREG32(cp_int_cntl_reg, cp_int_cntl)amdgpu_device_wreg(adev, (cp_int_cntl_reg), (cp_int_cntl), 0);
8242 break;
8243 default:
8244 break;
8245 }
8246}
8247
8248static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8249 int me, int pipe,
8250 enum amdgpu_interrupt_state state)
8251{
8252 u32 mec_int_cntl, mec_int_cntl_reg;
8253
8254 /*
8255 * amdgpu controls only the first MEC. That's why this function only
8256 * handles the setting of interrupts for this specific MEC. All other
8257 * pipes' interrupts are set by amdkfd.
8258 */
8259
8260 if (me == 1) {
8261 switch (pipe) {
8262 case 0:
8263 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e25);
8264 break;
8265 case 1:
8266 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e26);
8267 break;
8268 case 2:
8269 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e27);
8270 break;
8271 case 3:
8272 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e28);
8273 break;
8274 default:
8275 DRM_DEBUG("invalid pipe %d\n", pipe)__drm_dbg(DRM_UT_CORE, "invalid pipe %d\n", pipe);
8276 return;
8277 }
8278 } else {
8279 DRM_DEBUG("invalid me %d\n", me)__drm_dbg(DRM_UT_CORE, "invalid me %d\n", me);
8280 return;
8281 }
8282
8283 switch (state) {
8284 case AMDGPU_IRQ_STATE_DISABLE:
8285 mec_int_cntl = RREG32(mec_int_cntl_reg)amdgpu_device_rreg(adev, (mec_int_cntl_reg), 0);
8286 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)))
8287 TIME_STAMP_INT_ENABLE, 0)(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)));
8288 WREG32(mec_int_cntl_reg, mec_int_cntl)amdgpu_device_wreg(adev, (mec_int_cntl_reg), (mec_int_cntl), 0
);
8289 break;
8290 case AMDGPU_IRQ_STATE_ENABLE:
8291 mec_int_cntl = RREG32(mec_int_cntl_reg)amdgpu_device_rreg(adev, (mec_int_cntl_reg), 0);
8292 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)))
8293 TIME_STAMP_INT_ENABLE, 1)(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)));
8294 WREG32(mec_int_cntl_reg, mec_int_cntl)amdgpu_device_wreg(adev, (mec_int_cntl_reg), (mec_int_cntl), 0
);
8295 break;
8296 default:
8297 break;
8298 }
8299}
8300
8301static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8302 struct amdgpu_irq_src *src,
8303 unsigned type,
8304 enum amdgpu_interrupt_state state)
8305{
8306 switch (type) {
8307 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8308 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8309 break;
8310 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8311 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8312 break;
8313 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8314 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8315 break;
8316 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8317 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8318 break;
8319 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8320 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8321 break;
8322 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8323 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8324 break;
8325 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8326 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8327 break;
8328 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8329 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8330 break;
8331 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8332 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8333 break;
8334 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8335 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8336 break;
8337 default:
8338 break;
8339 }
8340 return 0;
8341}
8342
8343static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8344 struct amdgpu_irq_src *source,
8345 struct amdgpu_iv_entry *entry)
8346{
8347 int i;
8348 u8 me_id, pipe_id, queue_id;
8349 struct amdgpu_ring *ring;
8350
8351 DRM_DEBUG("IH: CP EOP\n")__drm_dbg(DRM_UT_CORE, "IH: CP EOP\n");
8352 me_id = (entry->ring_id & 0x0c) >> 2;
8353 pipe_id = (entry->ring_id & 0x03) >> 0;
8354 queue_id = (entry->ring_id & 0x70) >> 4;
8355
8356 switch (me_id) {
8357 case 0:
8358 if (pipe_id == 0)
8359 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8360 else
8361 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8362 break;
8363 case 1:
8364 case 2:
8365 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8366 ring = &adev->gfx.compute_ring[i];
8367 /* Per-queue interrupt is supported for MEC starting from VI.
8368 * The interrupt can only be enabled/disabled per pipe instead of per queue.
8369 */
8370 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8371 amdgpu_fence_process(ring);
8372 }
8373 break;
8374 }
8375 return 0;
8376}
8377
8378static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8379 struct amdgpu_irq_src *source,
8380 unsigned type,
8381 enum amdgpu_interrupt_state state)
8382{
8383 switch (state) {
8384 case AMDGPU_IRQ_STATE_DISABLE:
8385 case AMDGPU_IRQ_STATE_ENABLE:
8386 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), 0) & ~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x17), 0)
8387 PRIV_REG_INT_ENABLE,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), 0) & ~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x17), 0)
8388 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), 0) & ~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x17), 0);
8389 break;
8390 default:
8391 break;
8392 }
8393
8394 return 0;
8395}
8396
8397static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8398 struct amdgpu_irq_src *source,
8399 unsigned type,
8400 enum amdgpu_interrupt_state state)
8401{
8402 switch (state) {
8403 case AMDGPU_IRQ_STATE_DISABLE:
8404 case AMDGPU_IRQ_STATE_ENABLE:
8405 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), 0) & ~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x16), 0)
8406 PRIV_INSTR_INT_ENABLE,amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), 0) & ~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x16), 0)
8407 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e0a), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), 0) & ~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE
? 1 : 0) << 0x16), 0);
8408 default:
8409 break;
8410 }
8411
8412 return 0;
8413}
8414
8415static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8416 struct amdgpu_iv_entry *entry)
8417{
8418 u8 me_id, pipe_id, queue_id;
8419 struct amdgpu_ring *ring;
8420 int i;
8421
8422 me_id = (entry->ring_id & 0x0c) >> 2;
8423 pipe_id = (entry->ring_id & 0x03) >> 0;
8424 queue_id = (entry->ring_id & 0x70) >> 4;
8425
8426 switch (me_id) {
8427 case 0:
8428 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8429 ring = &adev->gfx.gfx_ring[i];
8430 /* we only enabled 1 gfx queue per pipe for now */
8431 if (ring->me == me_id && ring->pipe == pipe_id)
8432 drm_sched_fault(&ring->sched);
8433 }
8434 break;
8435 case 1:
8436 case 2:
8437 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8438 ring = &adev->gfx.compute_ring[i];
8439 if (ring->me == me_id && ring->pipe == pipe_id &&
8440 ring->queue == queue_id)
8441 drm_sched_fault(&ring->sched);
8442 }
8443 break;
8444 default:
8445 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8445); } while (0);
8446 }
8447}
8448
8449static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8450 struct amdgpu_irq_src *source,
8451 struct amdgpu_iv_entry *entry)
8452{
8453 DRM_ERROR("Illegal register access in command stream\n")__drm_err("Illegal register access in command stream\n");
8454 gfx_v10_0_handle_priv_fault(adev, entry);
8455 return 0;
8456}
8457
8458static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8459 struct amdgpu_irq_src *source,
8460 struct amdgpu_iv_entry *entry)
8461{
8462 DRM_ERROR("Illegal instruction in command stream\n")__drm_err("Illegal instruction in command stream\n");
8463 gfx_v10_0_handle_priv_fault(adev, entry);
8464 return 0;
8465}
8466
8467static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8468 struct amdgpu_irq_src *src,
8469 unsigned int type,
8470 enum amdgpu_interrupt_state state)
8471{
8472 uint32_t tmp, target;
8473 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8474
8475 if (ring->me == 1)
8476 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e25);
8477 else
8478 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e29);
8479 target += ring->pipe;
8480
8481 switch (type) {
8482 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8483 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8484 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e54), 0);
8485 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)))
8486 GENERIC2_INT_ENABLE, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
8487 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e54)), (tmp), 0);
8488
8489 tmp = RREG32(target)amdgpu_device_rreg(adev, (target), 0);
8490 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)))
8491 GENERIC2_INT_ENABLE, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
8492 WREG32(target, tmp)amdgpu_device_wreg(adev, (target), (tmp), 0);
8493 } else {
8494 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1e54), 0);
8495 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)))
8496 GENERIC2_INT_ENABLE, 1)(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
8497 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1e54)), (tmp), 0);
8498
8499 tmp = RREG32(target)amdgpu_device_rreg(adev, (target), 0);
8500 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)))
8501 GENERIC2_INT_ENABLE, 1)(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
8502 WREG32(target, tmp)amdgpu_device_wreg(adev, (target), (tmp), 0);
8503 }
8504 break;
8505 default:
8506 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8506); } while (0); /* kiq only support GENERIC2_INT now */
8507 break;
8508 }
8509 return 0;
8510}
8511
8512static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8513 struct amdgpu_irq_src *source,
8514 struct amdgpu_iv_entry *entry)
8515{
8516 u8 me_id, pipe_id, queue_id;
8517 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8518
8519 me_id = (entry->ring_id & 0x0c) >> 2;
8520 pipe_id = (entry->ring_id & 0x03) >> 0;
8521 queue_id = (entry->ring_id & 0x70) >> 4;
8522 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",__drm_dbg(DRM_UT_CORE, "IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n"
, me_id, pipe_id, queue_id)
8523 me_id, pipe_id, queue_id)__drm_dbg(DRM_UT_CORE, "IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n"
, me_id, pipe_id, queue_id);
8524
8525 amdgpu_fence_process(ring);
8526 return 0;
8527}
8528
8529static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8530{
8531 const unsigned int gcr_cntl =
8532 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1)((1) << 14) |
8533 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1)((1) << 15) |
8534 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1)((1) << 5) |
8535 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1)((1) << 4) |
8536 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1)((1) << 9) |
8537 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1)((1) << 8) |
8538 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1)((1) << 7) |
8539 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1)((1) << 0);
8540
8541 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8542 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)((3 << 30) | (((0x58) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
8543 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8544 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
8545 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
8546 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8547 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
8548 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8549 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8550}
8551
8552static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8553 .name = "gfx_v10_0",
8554 .early_init = gfx_v10_0_early_init,
8555 .late_init = gfx_v10_0_late_init,
8556 .sw_init = gfx_v10_0_sw_init,
8557 .sw_fini = gfx_v10_0_sw_fini,
8558 .hw_init = gfx_v10_0_hw_init,
8559 .hw_fini = gfx_v10_0_hw_fini,
8560 .suspend = gfx_v10_0_suspend,
8561 .resume = gfx_v10_0_resume,
8562 .is_idle = gfx_v10_0_is_idle,
8563 .wait_for_idle = gfx_v10_0_wait_for_idle,
8564 .soft_reset = gfx_v10_0_soft_reset,
8565 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8566 .set_powergating_state = gfx_v10_0_set_powergating_state,
8567 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8568};
8569
8570static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8571 .type = AMDGPU_RING_TYPE_GFX,
8572 .align_mask = 0xff,
8573 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
8574 .support_64bit_ptrs = true1,
8575 .vmhub = AMDGPU_GFXHUB_00,
8576 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8577 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8578 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8579 .emit_frame_size = /* totally 242 maximum if 16 IBs */
8580 5 + /* COND_EXEC */
8581 7 + /* PIPELINE_SYNC */
8582 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
8583 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
8584 2 + /* VM_FLUSH */
8585 8 + /* FENCE for VM_FLUSH */
8586 20 + /* GDS switch */
8587 4 + /* double SWITCH_BUFFER,
8588 * the first COND_EXEC jump to the place
8589 * just prior to this double SWITCH_BUFFER
8590 */
8591 5 + /* COND_EXEC */
8592 7 + /* HDP_flush */
8593 4 + /* VGT_flush */
8594 14 + /* CE_META */
8595 31 + /* DE_META */
8596 3 + /* CNTX_CTRL */
8597 5 + /* HDP_INVL */
8598 8 + 8 + /* FENCE x2 */
8599 2 + /* SWITCH_BUFFER */
8600 8, /* gfx_v10_0_emit_mem_sync */
8601 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8602 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8603 .emit_fence = gfx_v10_0_ring_emit_fence,
8604 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8605 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8606 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8607 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8608 .test_ring = gfx_v10_0_ring_test_ring,
8609 .test_ib = gfx_v10_0_ring_test_ib,
8610 .insert_nop = amdgpu_ring_insert_nop,
8611 .pad_ib = amdgpu_ring_generic_pad_ib,
8612 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8613 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8614 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8615 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8616 .preempt_ib = gfx_v10_0_ring_preempt_ib,
8617 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8618 .emit_wreg = gfx_v10_0_ring_emit_wreg,
8619 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8620 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8621 .soft_recovery = gfx_v10_0_ring_soft_recovery,
8622 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8623};
8624
8625static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8626 .type = AMDGPU_RING_TYPE_COMPUTE,
8627 .align_mask = 0xff,
8628 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
8629 .support_64bit_ptrs = true1,
8630 .vmhub = AMDGPU_GFXHUB_00,
8631 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8632 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8633 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8634 .emit_frame_size =
8635 20 + /* gfx_v10_0_ring_emit_gds_switch */
8636 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8637 5 + /* hdp invalidate */
8638 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8639 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
8640 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
8641 2 + /* gfx_v10_0_ring_emit_vm_flush */
8642 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8643 8, /* gfx_v10_0_emit_mem_sync */
8644 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8645 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8646 .emit_fence = gfx_v10_0_ring_emit_fence,
8647 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8648 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8649 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8650 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8651 .test_ring = gfx_v10_0_ring_test_ring,
8652 .test_ib = gfx_v10_0_ring_test_ib,
8653 .insert_nop = amdgpu_ring_insert_nop,
8654 .pad_ib = amdgpu_ring_generic_pad_ib,
8655 .emit_wreg = gfx_v10_0_ring_emit_wreg,
8656 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8657 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8658 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8659};
8660
8661static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8662 .type = AMDGPU_RING_TYPE_KIQ,
8663 .align_mask = 0xff,
8664 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
8665 .support_64bit_ptrs = true1,
8666 .vmhub = AMDGPU_GFXHUB_00,
8667 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8668 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8669 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8670 .emit_frame_size =
8671 20 + /* gfx_v10_0_ring_emit_gds_switch */
8672 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8673 5 + /*hdp invalidate */
8674 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8675 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
8676 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
8677 2 + /* gfx_v10_0_ring_emit_vm_flush */
8678 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8679 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8680 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8681 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8682 .test_ring = gfx_v10_0_ring_test_ring,
8683 .test_ib = gfx_v10_0_ring_test_ib,
8684 .insert_nop = amdgpu_ring_insert_nop,
8685 .pad_ib = amdgpu_ring_generic_pad_ib,
8686 .emit_rreg = gfx_v10_0_ring_emit_rreg,
8687 .emit_wreg = gfx_v10_0_ring_emit_wreg,
8688 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8689 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8690};
8691
8692static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8693{
8694 int i;
8695
8696 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8697
8698 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8699 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8700
8701 for (i = 0; i < adev->gfx.num_compute_rings; i++)
8702 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8703}
8704
8705static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8706 .set = gfx_v10_0_set_eop_interrupt_state,
8707 .process = gfx_v10_0_eop_irq,
8708};
8709
8710static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8711 .set = gfx_v10_0_set_priv_reg_fault_state,
8712 .process = gfx_v10_0_priv_reg_irq,
8713};
8714
8715static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8716 .set = gfx_v10_0_set_priv_inst_fault_state,
8717 .process = gfx_v10_0_priv_inst_irq,
8718};
8719
8720static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8721 .set = gfx_v10_0_kiq_set_interrupt_state,
8722 .process = gfx_v10_0_kiq_irq,
8723};
8724
8725static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8726{
8727 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8728 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8729
8730 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8731 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8732
8733 adev->gfx.priv_reg_irq.num_types = 1;
8734 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8735
8736 adev->gfx.priv_inst_irq.num_types = 1;
8737 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8738}
8739
8740static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8741{
8742 switch (adev->asic_type) {
8743 case CHIP_NAVI10:
8744 case CHIP_NAVI14:
8745 case CHIP_SIENNA_CICHLID:
8746 case CHIP_NAVY_FLOUNDER:
8747 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8748 break;
8749 case CHIP_NAVI12:
8750 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8751 break;
8752 default:
8753 break;
8754 }
8755}
8756
8757static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8758{
8759 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8760 adev->gfx.config.max_sh_per_se *
8761 adev->gfx.config.max_shader_engines;
8762
8763 adev->gds.gds_size = 0x10000;
8764 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8765 adev->gds.gws_size = 64;
8766 adev->gds.oa_size = 16;
8767}
8768
8769static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8770 u32 bitmap)
8771{
8772 u32 data;
8773
8774 if (!bitmap)
8775 return;
8776
8777 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT0x10;
8778 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK0xFFFF0000L;
8779
8780 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data)amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0]
+ 0x1010)), (data), 0);
8781}
8782
8783static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8784{
8785 u32 data, wgp_bitmask;
8786 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x100f), 0);
8787 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1010), 0);
8788
8789 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK0xFFFF0000L;
8790 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT0x10;
8791
8792 wgp_bitmask =
8793 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8794
8795 return (~data) & wgp_bitmask;
8796}
8797
8798static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8799{
8800 u32 wgp_idx, wgp_active_bitmap;
8801 u32 cu_bitmap_per_wgp, cu_active_bitmap;
8802
8803 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8804 cu_active_bitmap = 0;
8805
8806 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8807 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8808 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8809 if (wgp_active_bitmap & (1 << wgp_idx))
8810 cu_active_bitmap |= cu_bitmap_per_wgp;
8811 }
8812
8813 return cu_active_bitmap;
8814}
8815
8816static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8817 struct amdgpu_cu_info *cu_info)
8818{
8819 int i, j, k, counter, active_cu_number = 0;
8820 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8821 unsigned disable_masks[4 * 2];
8822
8823 if (!adev || !cu_info)
8824 return -EINVAL22;
8825
8826 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8827
8828 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
8829 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8830 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8831 bitmap = i * adev->gfx.config.max_sh_per_se + j;
8832 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
8833 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
8834 continue;
8835 mask = 1;
8836 ao_bitmap = 0;
8837 counter = 0;
8838 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8839 if (i < 4 && j < 2)
8840 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8841 adev, disable_masks[i * 2 + j]);
8842 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8843 cu_info->bitmap[i][j] = bitmap;
8844
8845 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8846 if (bitmap & mask) {
8847 if (counter < adev->gfx.config.max_cu_per_sh)
8848 ao_bitmap |= mask;
8849 counter++;
8850 }
8851 mask <<= 1;
8852 }
8853 active_cu_number += counter;
8854 if (i < 2 && j < 2)
8855 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8856 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8857 }
8858 }
8859 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8860 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
8861
8862 cu_info->number = active_cu_number;
8863 cu_info->ao_cu_mask = ao_cu_mask;
8864 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8865
8866 return 0;
8867}
8868
8869static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
8870{
8871 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
8872
8873 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0fe9), 0);
8874 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L;
8875 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8;
8876
8877 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE)amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x0fea), 0);
8878 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L;
8879 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8;
8880
8881 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
8882 adev->gfx.config.max_shader_engines);
8883 disabled_sa = efuse_setting | vbios_setting;
8884 disabled_sa &= max_sa_mask;
8885
8886 return disabled_sa;
8887}
8888
8889static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
8890{
8891 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
8892 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
8893
8894 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
8895
8896 max_sa_per_se = adev->gfx.config.max_sh_per_se;
8897 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
8898 max_shader_engines = adev->gfx.config.max_shader_engines;
8899
8900 for (se_index = 0; max_shader_engines > se_index; se_index++) {
8901 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
8902 disabled_sa_per_se &= max_sa_per_se_mask;
8903 if (disabled_sa_per_se == max_sa_per_se_mask) {
8904 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1)amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP][0][0] +
0x1085), ((amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1085), 0) & ~0x00000008L) | (1) << 0x3)
, 0);
8905 break;
8906 }
8907 }
8908}
8909
8910const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8911{
8912 .type = AMD_IP_BLOCK_TYPE_GFX,
8913 .major = 10,
8914 .minor = 0,
8915 .rev = 0,
8916 .funcs = &gfx_v10_0_ip_funcs,
8917};
←

/usr/src/sys/dev/pci/drm/include/linux/firmware.h

1/* Public domain. */
2
3#ifndef _LINUX_FIRMWARE_H
4#define _LINUX_FIRMWARE_H
5
6#include <sys/types.h>
7#include <sys/malloc.h>
8#include <sys/device.h>
9#include <linux/types.h>
10#include <linux/gfp.h>
11
12#ifndef __DECONST
13#define __DECONST(type, var)((type)(__uintptr_t)(const void *)(var)) ((type)(__uintptr_t)(const void *)(var))
14#endif
15
16struct firmware {
17 size_t size;
18 const u8 *data;
19};
20
21static inline int
22request_firmware(const struct firmware **fw, const char *name,
23 struct device *device)
24{
25 int r;
26 struct firmware *f = malloc(sizeof(struct firmware), M_DRM145,
27 M_WAITOK0x0001 | M_ZERO0x0008);
28 r = loadfirmware(name, __DECONST(u_char **, &f->data)((u_char **)(__uintptr_t)(const void *)(&f->data)), &f->size);
29 if (r != 0) {
20
←
Assuming 'r' is not equal to 0
→
21
←
Taking true branch
→
30 free(f, M_DRM145, sizeof(struct firmware));
31 *fw = NULL((void *)0);
22
←
Null pointer value stored to field 'pfp_fw'
→
32 return -r;
33 } else {
34 *fw = f;
35 return 0;
36 }
37}
38
39static inline int
40request_firmware_direct(const struct firmware **fw, const char *name,
41 struct device *device)
42{
43 return request_firmware(fw, name, device);
44}
45
46#define request_firmware_nowait(a, b, c, d, e, f, g)-22 -EINVAL22
47
48static inline void
49release_firmware(const struct firmware *fw)
50{
51 if (fw)
52 free(__DECONST(u_char *, fw->data)((u_char *)(__uintptr_t)(const void *)(fw->data)), M_DEVBUF2, fw->size);
53 free(__DECONST(struct firmware *, fw)((struct firmware *)(__uintptr_t)(const void *)(fw)), M_DRM145, sizeof(*fw));
54}
55
56#endif