Bug Summary

File:dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
Warning:line 1407, column 13
Value stored to 'pptable' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name arcturus_ppt.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#define SWSMU_CODE_LAYER_L2
25
26#include <linux/firmware.h>
27#include "amdgpu.h"
28#include "amdgpu_smu.h"
29#include "atomfirmware.h"
30#include "amdgpu_atomfirmware.h"
31#include "amdgpu_atombios.h"
32#include "smu_v11_0.h"
33#include "smu11_driver_if_arcturus.h"
34#include "soc15_common.h"
35#include "atom.h"
36#include "power_state.h"
37#include "arcturus_ppt.h"
38#include "smu_v11_0_pptable.h"
39#include "arcturus_ppsmc.h"
40#include "nbio/nbio_7_4_offset.h"
41#include "nbio/nbio_7_4_sh_mask.h"
42#include "thm/thm_11_0_2_offset.h"
43#include "thm/thm_11_0_2_sh_mask.h"
44#include "amdgpu_xgmi.h"
45#include <linux/i2c.h>
46#include <linux/pci.h>
47#include "amdgpu_ras.h"
48#include "smu_cmn.h"
49
50/*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55#undef pr_err
56#undef pr_warn
57#undef pr_info
58#undef pr_debug
59
60#define to_amdgpu_device(x)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (x); (struct amdgpu_device *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_device, pm.smu_i2c) );}))
(container_of(x, struct amdgpu_device, pm.smu_i2c)({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (x); (struct amdgpu_device *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_device, pm.smu_i2c) );})
)
61
62#define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature)[smu_feature] = {1, (arcturus_feature)} \
63 [smu_feature] = {1, (arcturus_feature)}
64
65#define SMU_FEATURES_LOW_MASK0x00000000FFFFFFFF 0x00000000FFFFFFFF
66#define SMU_FEATURES_LOW_SHIFT0 0
67#define SMU_FEATURES_HIGH_MASK0xFFFFFFFF00000000 0xFFFFFFFF00000000
68#define SMU_FEATURES_HIGH_SHIFT32 32
69
70#define SMC_DPM_FEATURE( (1 << 0 ) | (1 << 1 ) | (1 << 2 ) | (1 <<
3 ) | (1 << 5 ) | (1 << 4 ) | (1 << 6 ))
( \
71 FEATURE_DPM_PREFETCHER_MASK(1 << 0 ) | \
72 FEATURE_DPM_GFXCLK_MASK(1 << 1 ) | \
73 FEATURE_DPM_UCLK_MASK(1 << 2 ) | \
74 FEATURE_DPM_SOCCLK_MASK(1 << 3 ) | \
75 FEATURE_DPM_MP0CLK_MASK(1 << 5 ) | \
76 FEATURE_DPM_FCLK_MASK(1 << 4 ) | \
77 FEATURE_DPM_XGMI_MASK(1 << 6 ))
78
79/* possible frequency drift (1Mhz) */
80#define EPSILON1 1
81
82#define smnPCIE_ESM_CTRL0x111003D0 0x111003D0
83
84static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
85 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0)[SMU_MSG_TestMessage] = {1, (0x1), (0)},
86 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1)[SMU_MSG_GetSmuVersion] = {1, (0x2), (1)},
87 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1)[SMU_MSG_GetDriverIfVersion] = {1, (0x3), (1)},
88 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0)[SMU_MSG_SetAllowedFeaturesMaskLow] = {1, (0x4), (0)},
89 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0)[SMU_MSG_SetAllowedFeaturesMaskHigh] = {1, (0x5), (0)},
90 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0)[SMU_MSG_EnableAllSmuFeatures] = {1, (0x6), (0)},
91 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0)[SMU_MSG_DisableAllSmuFeatures] = {1, (0x7), (0)},
92 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1)[SMU_MSG_EnableSmuFeaturesLow] = {1, (0x8), (1)},
93 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1)[SMU_MSG_EnableSmuFeaturesHigh] = {1, (0x9), (1)},
94 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0)[SMU_MSG_DisableSmuFeaturesLow] = {1, (0xA), (0)},
95 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0)[SMU_MSG_DisableSmuFeaturesHigh] = {1, (0xB), (0)},
96 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 0)[SMU_MSG_GetEnabledSmuFeaturesLow] = {1, (0xC), (0)},
97 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 0)[SMU_MSG_GetEnabledSmuFeaturesHigh] = {1, (0xD), (0)},
98 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1)[SMU_MSG_SetDriverDramAddrHigh] = {1, (0xE), (1)},
99 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1)[SMU_MSG_SetDriverDramAddrLow] = {1, (0xF), (1)},
100 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0)[SMU_MSG_SetToolsDramAddrHigh] = {1, (0x10), (0)},
101 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0)[SMU_MSG_SetToolsDramAddrLow] = {1, (0x11), (0)},
102 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1)[SMU_MSG_TransferTableSmu2Dram] = {1, (0x12), (1)},
103 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0)[SMU_MSG_TransferTableDram2Smu] = {1, (0x13), (0)},
104 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0)[SMU_MSG_UseDefaultPPTable] = {1, (0x14), (0)},
105 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0)[SMU_MSG_UseBackupPPTable] = {1, (0x15), (0)},
106 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0)[SMU_MSG_SetSystemVirtualDramAddrHigh] = {1, (0x16), (0)},
107 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0)[SMU_MSG_SetSystemVirtualDramAddrLow] = {1, (0x17), (0)},
108 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0)[SMU_MSG_EnterBaco] = {1, (0x18), (0)},
109 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0)[SMU_MSG_ExitBaco] = {1, (0x19), (0)},
110 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0)[SMU_MSG_ArmD3] = {1, (0x1A), (0)},
111 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0)[SMU_MSG_SetSoftMinByFreq] = {1, (0x1B), (0)},
112 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 0)[SMU_MSG_SetSoftMaxByFreq] = {1, (0x1C), (0)},
113 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0)[SMU_MSG_SetHardMinByFreq] = {1, (0x1D), (0)},
114 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0)[SMU_MSG_SetHardMaxByFreq] = {1, (0x1E), (0)},
115 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 0)[SMU_MSG_GetMinDpmFreq] = {1, (0x1F), (0)},
116 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 0)[SMU_MSG_GetMaxDpmFreq] = {1, (0x20), (0)},
117 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1)[SMU_MSG_GetDpmFreqByIndex] = {1, (0x21), (1)},
118 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1)[SMU_MSG_SetWorkloadMask] = {1, (0x22), (1)},
119 MSG_MAP(SetDfSwitchType, PPSMC_MSG_SetDfSwitchType, 0)[SMU_MSG_SetDfSwitchType] = {1, (0x23), (0)},
120 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0)[SMU_MSG_GetVoltageByDpm] = {1, (0x24), (0)},
121 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0)[SMU_MSG_GetVoltageByDpmOverdrive] = {1, (0x25), (0)},
122 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0)[SMU_MSG_SetPptLimit] = {1, (0x26), (0)},
123 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1)[SMU_MSG_GetPptLimit] = {1, (0x27), (1)},
124 MSG_MAP(PowerUpVcn0, PPSMC_MSG_PowerUpVcn0, 0)[SMU_MSG_PowerUpVcn0] = {1, (0x28), (0)},
125 MSG_MAP(PowerDownVcn0, PPSMC_MSG_PowerDownVcn0, 0)[SMU_MSG_PowerDownVcn0] = {1, (0x29), (0)},
126 MSG_MAP(PowerUpVcn1, PPSMC_MSG_PowerUpVcn1, 0)[SMU_MSG_PowerUpVcn1] = {1, (0x2A), (0)},
127 MSG_MAP(PowerDownVcn1, PPSMC_MSG_PowerDownVcn1, 0)[SMU_MSG_PowerDownVcn1] = {1, (0x2B), (0)},
128 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0)[SMU_MSG_PrepareMp1ForUnload] = {1, (0x2C), (0)},
129 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0)[SMU_MSG_PrepareMp1ForReset] = {1, (0x2D), (0)},
130 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0)[SMU_MSG_PrepareMp1ForShutdown] = {1, (0x2E), (0)},
131 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 0)[SMU_MSG_SoftReset] = {1, (0x2F), (0)},
132 MSG_MAP(RunAfllBtc, PPSMC_MSG_RunAfllBtc, 0)[SMU_MSG_RunAfllBtc] = {1, (0x30), (0)},
133 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0)[SMU_MSG_RunDcBtc] = {1, (0x31), (0)},
134 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0)[SMU_MSG_DramLogSetDramAddrHigh] = {1, (0x33), (0)},
135 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0)[SMU_MSG_DramLogSetDramAddrLow] = {1, (0x34), (0)},
136 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0)[SMU_MSG_DramLogSetDramSize] = {1, (0x35), (0)},
137 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0)[SMU_MSG_GetDebugData] = {1, (0x36), (0)},
138 MSG_MAP(WaflTest, PPSMC_MSG_WaflTest, 0)[SMU_MSG_WaflTest] = {1, (0x37), (0)},
139 MSG_MAP(SetXgmiMode, PPSMC_MSG_SetXgmiMode, 0)[SMU_MSG_SetXgmiMode] = {1, (0x38), (0)},
140 MSG_MAP(SetMemoryChannelEnable, PPSMC_MSG_SetMemoryChannelEnable, 0)[SMU_MSG_SetMemoryChannelEnable] = {1, (0x39), (0)},
141 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0)[SMU_MSG_DFCstateControl] = {1, (0x3B), (0)},
142 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0)[SMU_MSG_GmiPwrDnControl] = {1, (0x3D), (0)},
143 MSG_MAP(ReadSerialNumTop32, PPSMC_MSG_ReadSerialNumTop32, 1)[SMU_MSG_ReadSerialNumTop32] = {1, (0x40), (1)},
144 MSG_MAP(ReadSerialNumBottom32, PPSMC_MSG_ReadSerialNumBottom32, 1)[SMU_MSG_ReadSerialNumBottom32] = {1, (0x41), (1)},
145};
146
147static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
148 CLK_MAP(GFXCLK, PPCLK_GFXCLK)[SMU_GFXCLK] = {1, (PPCLK_GFXCLK)},
149 CLK_MAP(SCLK, PPCLK_GFXCLK)[SMU_SCLK] = {1, (PPCLK_GFXCLK)},
150 CLK_MAP(SOCCLK, PPCLK_SOCCLK)[SMU_SOCCLK] = {1, (PPCLK_SOCCLK)},
151 CLK_MAP(FCLK, PPCLK_FCLK)[SMU_FCLK] = {1, (PPCLK_FCLK)},
152 CLK_MAP(UCLK, PPCLK_UCLK)[SMU_UCLK] = {1, (PPCLK_UCLK)},
153 CLK_MAP(MCLK, PPCLK_UCLK)[SMU_MCLK] = {1, (PPCLK_UCLK)},
154 CLK_MAP(DCLK, PPCLK_DCLK)[SMU_DCLK] = {1, (PPCLK_DCLK)},
155 CLK_MAP(VCLK, PPCLK_VCLK)[SMU_VCLK] = {1, (PPCLK_VCLK)},
156};
157
158static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
159 FEA_MAP(DPM_PREFETCHER)[SMU_FEATURE_DPM_PREFETCHER_BIT] = {1, 0},
160 FEA_MAP(DPM_GFXCLK)[SMU_FEATURE_DPM_GFXCLK_BIT] = {1, 1},
161 FEA_MAP(DPM_UCLK)[SMU_FEATURE_DPM_UCLK_BIT] = {1, 2},
162 FEA_MAP(DPM_SOCCLK)[SMU_FEATURE_DPM_SOCCLK_BIT] = {1, 3},
163 FEA_MAP(DPM_FCLK)[SMU_FEATURE_DPM_FCLK_BIT] = {1, 4},
164 FEA_MAP(DPM_MP0CLK)[SMU_FEATURE_DPM_MP0CLK_BIT] = {1, 5},
165 ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT)[SMU_FEATURE_XGMI_BIT] = {1, (6)},
166 FEA_MAP(DS_GFXCLK)[SMU_FEATURE_DS_GFXCLK_BIT] = {1, 7},
167 FEA_MAP(DS_SOCCLK)[SMU_FEATURE_DS_SOCCLK_BIT] = {1, 8},
168 FEA_MAP(DS_LCLK)[SMU_FEATURE_DS_LCLK_BIT] = {1, 9},
169 FEA_MAP(DS_FCLK)[SMU_FEATURE_DS_FCLK_BIT] = {1, 10},
170 FEA_MAP(DS_UCLK)[SMU_FEATURE_DS_UCLK_BIT] = {1, 11},
171 FEA_MAP(GFX_ULV)[SMU_FEATURE_GFX_ULV_BIT] = {1, 12},
172 ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT)[SMU_FEATURE_VCN_PG_BIT] = {1, (13)},
173 FEA_MAP(RSMU_SMN_CG)[SMU_FEATURE_RSMU_SMN_CG_BIT] = {1, 14},
174 FEA_MAP(WAFL_CG)[SMU_FEATURE_WAFL_CG_BIT] = {1, 15},
175 FEA_MAP(PPT)[SMU_FEATURE_PPT_BIT] = {1, 16},
176 FEA_MAP(TDC)[SMU_FEATURE_TDC_BIT] = {1, 17},
177 FEA_MAP(APCC_PLUS)[SMU_FEATURE_APCC_PLUS_BIT] = {1, 18},
178 FEA_MAP(VR0HOT)[SMU_FEATURE_VR0HOT_BIT] = {1, 19},
179 FEA_MAP(VR1HOT)[SMU_FEATURE_VR1HOT_BIT] = {1, 20},
180 FEA_MAP(FW_CTF)[SMU_FEATURE_FW_CTF_BIT] = {1, 21},
181 FEA_MAP(FAN_CONTROL)[SMU_FEATURE_FAN_CONTROL_BIT] = {1, 22},
182 FEA_MAP(THERMAL)[SMU_FEATURE_THERMAL_BIT] = {1, 23},
183 FEA_MAP(OUT_OF_BAND_MONITOR)[SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT] = {1, 24},
184 FEA_MAP(TEMP_DEPENDENT_VMIN)[SMU_FEATURE_TEMP_DEPENDENT_VMIN_BIT] = {1, 25},
185};
186
187static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
188 TAB_MAP(PPTABLE)[SMU_TABLE_PPTABLE] = {1, 0},
189 TAB_MAP(AVFS)[SMU_TABLE_AVFS] = {1, 1},
190 TAB_MAP(AVFS_PSM_DEBUG)[SMU_TABLE_AVFS_PSM_DEBUG] = {1, 2},
191 TAB_MAP(AVFS_FUSE_OVERRIDE)[SMU_TABLE_AVFS_FUSE_OVERRIDE] = {1, 3},
192 TAB_MAP(PMSTATUSLOG)[SMU_TABLE_PMSTATUSLOG] = {1, 4},
193 TAB_MAP(SMU_METRICS)[SMU_TABLE_SMU_METRICS] = {1, 5},
194 TAB_MAP(DRIVER_SMU_CONFIG)[SMU_TABLE_DRIVER_SMU_CONFIG] = {1, 6},
195 TAB_MAP(OVERDRIVE)[SMU_TABLE_OVERDRIVE] = {1, 7},
196 TAB_MAP(I2C_COMMANDS)[SMU_TABLE_I2C_COMMANDS] = {1, 9},
197 TAB_MAP(ACTIVITY_MONITOR_COEFF)[SMU_TABLE_ACTIVITY_MONITOR_COEFF] = {1, 10},
198};
199
200static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
201 PWR_MAP(AC)[SMU_POWER_SOURCE_AC] = {1, POWER_SOURCE_AC},
202 PWR_MAP(DC)[SMU_POWER_SOURCE_DC] = {1, POWER_SOURCE_DC},
203};
204
205static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT)[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = {1, (0)},
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT)[PP_SMC_POWER_PROFILE_POWERSAVING] = {1, (1)},
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT)[PP_SMC_POWER_PROFILE_VIDEO] = {1, (2)},
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT)[PP_SMC_POWER_PROFILE_COMPUTE] = {1, (3)},
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT)[PP_SMC_POWER_PROFILE_CUSTOM] = {1, (4)},
211};
212
213static int arcturus_tables_init(struct smu_context *smu)
214{
215 struct smu_table_context *smu_table = &smu->smu_table;
216 struct smu_table *tables = smu_table->tables;
217
218 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),do { tables[SMU_TABLE_PPTABLE].size = sizeof(PPTable_t); tables
[SMU_TABLE_PPTABLE].align = (1 << 12); tables[SMU_TABLE_PPTABLE
].domain = 0x4; } while (0)
219 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_PPTABLE].size = sizeof(PPTable_t); tables
[SMU_TABLE_PPTABLE].align = (1 << 12); tables[SMU_TABLE_PPTABLE
].domain = 0x4; } while (0)
;
220
221 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,do { tables[SMU_TABLE_PMSTATUSLOG].size = 0x19000; tables[SMU_TABLE_PMSTATUSLOG
].align = (1 << 12); tables[SMU_TABLE_PMSTATUSLOG].domain
= 0x4; } while (0)
222 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_PMSTATUSLOG].size = 0x19000; tables[SMU_TABLE_PMSTATUSLOG
].align = (1 << 12); tables[SMU_TABLE_PMSTATUSLOG].domain
= 0x4; } while (0)
;
223
224 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t
); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables
[SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0)
225 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_SMU_METRICS].size = sizeof(SmuMetrics_t
); tables[SMU_TABLE_SMU_METRICS].align = (1 << 12); tables
[SMU_TABLE_SMU_METRICS].domain = 0x4; } while (0)
;
226
227 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),do { tables[SMU_TABLE_I2C_COMMANDS].size = sizeof(SwI2cRequest_t
); tables[SMU_TABLE_I2C_COMMANDS].align = (1 << 12); tables
[SMU_TABLE_I2C_COMMANDS].domain = 0x4; } while (0)
228 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_I2C_COMMANDS].size = sizeof(SwI2cRequest_t
); tables[SMU_TABLE_I2C_COMMANDS].align = (1 << 12); tables
[SMU_TABLE_I2C_COMMANDS].domain = 0x4; } while (0)
;
229
230 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t
); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 <<
12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; }
while (0)
231 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t
); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 <<
12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; }
while (0)
232 AMDGPU_GEM_DOMAIN_VRAM)do { tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].size = sizeof(DpmActivityMonitorCoeffInt_t
); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].align = (1 <<
12); tables[SMU_TABLE_ACTIVITY_MONITOR_COEFF].domain = 0x4; }
while (0)
;
233
234 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL(0x0001 | 0x0004));
235 if (!smu_table->metrics_table)
236 return -ENOMEM12;
237 smu_table->metrics_time = 0;
238
239 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_0);
240 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL(0x0001 | 0x0004));
241 if (!smu_table->gpu_metrics_table) {
242 kfree(smu_table->metrics_table);
243 return -ENOMEM12;
244 }
245
246 return 0;
247}
248
249static int arcturus_allocate_dpm_context(struct smu_context *smu)
250{
251 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
252
253 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
254 GFP_KERNEL(0x0001 | 0x0004));
255 if (!smu_dpm->dpm_context)
256 return -ENOMEM12;
257 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
258
259 smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
260 GFP_KERNEL(0x0001 | 0x0004));
261 if (!smu_dpm->dpm_current_power_state)
262 return -ENOMEM12;
263
264 smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
265 GFP_KERNEL(0x0001 | 0x0004));
266 if (!smu_dpm->dpm_request_power_state)
267 return -ENOMEM12;
268
269 return 0;
270}
271
272static int arcturus_init_smc_tables(struct smu_context *smu)
273{
274 int ret = 0;
275
276 ret = arcturus_tables_init(smu);
277 if (ret)
278 return ret;
279
280 ret = arcturus_allocate_dpm_context(smu);
281 if (ret)
282 return ret;
283
284 return smu_v11_0_init_smc_tables(smu);
285}
286
287static int
288arcturus_get_allowed_feature_mask(struct smu_context *smu,
289 uint32_t *feature_mask, uint32_t num)
290{
291 if (num > 2)
292 return -EINVAL22;
293
294 /* pptable will handle the features to enable */
295 memset(feature_mask, 0xFF, sizeof(uint32_t) * num)__builtin_memset((feature_mask), (0xFF), (sizeof(uint32_t) * num
))
;
296
297 return 0;
298}
299
300static int arcturus_set_default_dpm_table(struct smu_context *smu)
301{
302 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
303 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
304 struct smu_11_0_dpm_table *dpm_table = NULL((void *)0);
305 int ret = 0;
306
307 /* socclk dpm table setup */
308 dpm_table = &dpm_context->dpm_tables.soc_table;
309 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
310 ret = smu_v11_0_set_single_dpm_table(smu,
311 SMU_SOCCLK,
312 dpm_table);
313 if (ret)
314 return ret;
315 dpm_table->is_fine_grained =
316 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
317 } else {
318 dpm_table->count = 1;
319 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
320 dpm_table->dpm_levels[0].enabled = true1;
321 dpm_table->min = dpm_table->dpm_levels[0].value;
322 dpm_table->max = dpm_table->dpm_levels[0].value;
323 }
324
325 /* gfxclk dpm table setup */
326 dpm_table = &dpm_context->dpm_tables.gfx_table;
327 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
328 ret = smu_v11_0_set_single_dpm_table(smu,
329 SMU_GFXCLK,
330 dpm_table);
331 if (ret)
332 return ret;
333 dpm_table->is_fine_grained =
334 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
335 } else {
336 dpm_table->count = 1;
337 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
338 dpm_table->dpm_levels[0].enabled = true1;
339 dpm_table->min = dpm_table->dpm_levels[0].value;
340 dpm_table->max = dpm_table->dpm_levels[0].value;
341 }
342
343 /* memclk dpm table setup */
344 dpm_table = &dpm_context->dpm_tables.uclk_table;
345 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
346 ret = smu_v11_0_set_single_dpm_table(smu,
347 SMU_UCLK,
348 dpm_table);
349 if (ret)
350 return ret;
351 dpm_table->is_fine_grained =
352 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
353 } else {
354 dpm_table->count = 1;
355 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
356 dpm_table->dpm_levels[0].enabled = true1;
357 dpm_table->min = dpm_table->dpm_levels[0].value;
358 dpm_table->max = dpm_table->dpm_levels[0].value;
359 }
360
361 /* fclk dpm table setup */
362 dpm_table = &dpm_context->dpm_tables.fclk_table;
363 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
364 ret = smu_v11_0_set_single_dpm_table(smu,
365 SMU_FCLK,
366 dpm_table);
367 if (ret)
368 return ret;
369 dpm_table->is_fine_grained =
370 !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
371 } else {
372 dpm_table->count = 1;
373 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
374 dpm_table->dpm_levels[0].enabled = true1;
375 dpm_table->min = dpm_table->dpm_levels[0].value;
376 dpm_table->max = dpm_table->dpm_levels[0].value;
377 }
378
379 return 0;
380}
381
382static int arcturus_check_powerplay_table(struct smu_context *smu)
383{
384 struct smu_table_context *table_context = &smu->smu_table;
385 struct smu_11_0_powerplay_table *powerplay_table =
386 table_context->power_play_table;
387 struct smu_baco_context *smu_baco = &smu->smu_baco;
388
389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO0x8 ||
390 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO0x10)
391 smu_baco->platform_support = true1;
392
393 table_context->thermal_controller_type =
394 powerplay_table->thermal_controller_type;
395
396 return 0;
397}
398
399static int arcturus_store_powerplay_table(struct smu_context *smu)
400{
401 struct smu_table_context *table_context = &smu->smu_table;
402 struct smu_11_0_powerplay_table *powerplay_table =
403 table_context->power_play_table;
404
405 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,__builtin_memcpy((table_context->driver_pptable), (&powerplay_table
->smc_pptable), (sizeof(PPTable_t)))
406 sizeof(PPTable_t))__builtin_memcpy((table_context->driver_pptable), (&powerplay_table
->smc_pptable), (sizeof(PPTable_t)))
;
407
408 return 0;
409}
410
411static int arcturus_append_powerplay_table(struct smu_context *smu)
412{
413 struct smu_table_context *table_context = &smu->smu_table;
414 PPTable_t *smc_pptable = table_context->driver_pptable;
415 struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
416 int index, ret;
417
418 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1
, smc_dpm_info) / sizeof(uint16_t))
419 smc_dpm_info)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1
, smc_dpm_info) / sizeof(uint16_t))
;
420
421 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL((void *)0), NULL((void *)0), NULL((void *)0),
422 (uint8_t **)&smc_dpm_table);
423 if (ret)
424 return ret;
425
426 dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",do { } while(0)
427 smc_dpm_table->table_header.format_revision,do { } while(0)
428 smc_dpm_table->table_header.content_revision)do { } while(0);
429
430 if ((smc_dpm_table->table_header.format_revision == 4) &&
431 (smc_dpm_table->table_header.content_revision == 6))
432 memcpy(&smc_pptable->MaxVoltageStepGfx,__builtin_memcpy((&smc_pptable->MaxVoltageStepGfx), (&
smc_dpm_table->maxvoltagestepgfx), (sizeof(*smc_dpm_table)
- __builtin_offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx
)))
433 &smc_dpm_table->maxvoltagestepgfx,__builtin_memcpy((&smc_pptable->MaxVoltageStepGfx), (&
smc_dpm_table->maxvoltagestepgfx), (sizeof(*smc_dpm_table)
- __builtin_offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx
)))
434 sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx))__builtin_memcpy((&smc_pptable->MaxVoltageStepGfx), (&
smc_dpm_table->maxvoltagestepgfx), (sizeof(*smc_dpm_table)
- __builtin_offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx
)))
;
435
436 return 0;
437}
438
439static int arcturus_setup_pptable(struct smu_context *smu)
440{
441 int ret = 0;
442
443 ret = smu_v11_0_setup_pptable(smu);
444 if (ret)
445 return ret;
446
447 ret = arcturus_store_powerplay_table(smu);
448 if (ret)
449 return ret;
450
451 ret = arcturus_append_powerplay_table(smu);
452 if (ret)
453 return ret;
454
455 ret = arcturus_check_powerplay_table(smu);
456 if (ret)
457 return ret;
458
459 return ret;
460}
461
462static int arcturus_run_btc(struct smu_context *smu)
463{
464 int ret = 0;
465
466 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL((void *)0));
467 if (ret) {
468 dev_err(smu->adev->dev, "RunAfllBtc failed!\n")printf("drm:pid%d:%s *ERROR* " "RunAfllBtc failed!\n", ({struct
cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__)
;
469 return ret;
470 }
471
472 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL((void *)0));
473}
474
475static int arcturus_populate_umd_state_clk(struct smu_context *smu)
476{
477 struct smu_11_0_dpm_context *dpm_context =
478 smu->smu_dpm.dpm_context;
479 struct smu_11_0_dpm_table *gfx_table =
480 &dpm_context->dpm_tables.gfx_table;
481 struct smu_11_0_dpm_table *mem_table =
482 &dpm_context->dpm_tables.uclk_table;
483 struct smu_11_0_dpm_table *soc_table =
484 &dpm_context->dpm_tables.soc_table;
485 struct smu_umd_pstate_table *pstate_table =
486 &smu->pstate_table;
487
488 pstate_table->gfxclk_pstate.min = gfx_table->min;
489 pstate_table->gfxclk_pstate.peak = gfx_table->max;
490
491 pstate_table->uclk_pstate.min = mem_table->min;
492 pstate_table->uclk_pstate.peak = mem_table->max;
493
494 pstate_table->socclk_pstate.min = soc_table->min;
495 pstate_table->socclk_pstate.peak = soc_table->max;
496
497 if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL0x3 &&
498 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL0x2 &&
499 soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL0x3) {
500 pstate_table->gfxclk_pstate.standard =
501 gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL0x3].value;
502 pstate_table->uclk_pstate.standard =
503 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL0x2].value;
504 pstate_table->socclk_pstate.standard =
505 soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL0x3].value;
506 } else {
507 pstate_table->gfxclk_pstate.standard =
508 pstate_table->gfxclk_pstate.min;
509 pstate_table->uclk_pstate.standard =
510 pstate_table->uclk_pstate.min;
511 pstate_table->socclk_pstate.standard =
512 pstate_table->socclk_pstate.min;
513 }
514
515 return 0;
516}
517
518static int arcturus_get_clk_table(struct smu_context *smu,
519 struct pp_clock_levels_with_latency *clocks,
520 struct smu_11_0_dpm_table *dpm_table)
521{
522 int i, count;
523
524 count = (dpm_table->count > MAX_NUM_CLOCKS16) ? MAX_NUM_CLOCKS16 : dpm_table->count;
525 clocks->num_levels = count;
526
527 for (i = 0; i < count; i++) {
528 clocks->data[i].clocks_in_khz =
529 dpm_table->dpm_levels[i].value * 1000;
530 clocks->data[i].latency_in_us = 0;
531 }
532
533 return 0;
534}
535
536static int arcturus_freqs_in_same_level(int32_t frequency1,
537 int32_t frequency2)
538{
539 return (abs(frequency1 - frequency2) <= EPSILON1);
540}
541
542static int arcturus_get_smu_metrics_data(struct smu_context *smu,
543 MetricsMember_t member,
544 uint32_t *value)
545{
546 struct smu_table_context *smu_table= &smu->smu_table;
547 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
548 int ret = 0;
549
550 mutex_lock(&smu->metrics_lock)rw_enter_write(&smu->metrics_lock);
551
552 ret = smu_cmn_get_metrics_table_locked(smu,
553 NULL((void *)0),
554 false0);
555 if (ret) {
556 mutex_unlock(&smu->metrics_lock)rw_exit_write(&smu->metrics_lock);
557 return ret;
558 }
559
560 switch (member) {
561 case METRICS_CURR_GFXCLK:
562 *value = metrics->CurrClock[PPCLK_GFXCLK];
563 break;
564 case METRICS_CURR_SOCCLK:
565 *value = metrics->CurrClock[PPCLK_SOCCLK];
566 break;
567 case METRICS_CURR_UCLK:
568 *value = metrics->CurrClock[PPCLK_UCLK];
569 break;
570 case METRICS_CURR_VCLK:
571 *value = metrics->CurrClock[PPCLK_VCLK];
572 break;
573 case METRICS_CURR_DCLK:
574 *value = metrics->CurrClock[PPCLK_DCLK];
575 break;
576 case METRICS_CURR_FCLK:
577 *value = metrics->CurrClock[PPCLK_FCLK];
578 break;
579 case METRICS_AVERAGE_GFXCLK:
580 *value = metrics->AverageGfxclkFrequency;
581 break;
582 case METRICS_AVERAGE_SOCCLK:
583 *value = metrics->AverageSocclkFrequency;
584 break;
585 case METRICS_AVERAGE_UCLK:
586 *value = metrics->AverageUclkFrequency;
587 break;
588 case METRICS_AVERAGE_VCLK:
589 *value = metrics->AverageVclkFrequency;
590 break;
591 case METRICS_AVERAGE_DCLK:
592 *value = metrics->AverageDclkFrequency;
593 break;
594 case METRICS_AVERAGE_GFXACTIVITY:
595 *value = metrics->AverageGfxActivity;
596 break;
597 case METRICS_AVERAGE_MEMACTIVITY:
598 *value = metrics->AverageUclkActivity;
599 break;
600 case METRICS_AVERAGE_VCNACTIVITY:
601 *value = metrics->VcnActivityPercentage;
602 break;
603 case METRICS_AVERAGE_SOCKETPOWER:
604 *value = metrics->AverageSocketPower << 8;
605 break;
606 case METRICS_TEMPERATURE_EDGE:
607 *value = metrics->TemperatureEdge *
608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
609 break;
610 case METRICS_TEMPERATURE_HOTSPOT:
611 *value = metrics->TemperatureHotspot *
612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
613 break;
614 case METRICS_TEMPERATURE_MEM:
615 *value = metrics->TemperatureHBM *
616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
617 break;
618 case METRICS_TEMPERATURE_VRGFX:
619 *value = metrics->TemperatureVrGfx *
620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
621 break;
622 case METRICS_TEMPERATURE_VRSOC:
623 *value = metrics->TemperatureVrSoc *
624 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
625 break;
626 case METRICS_TEMPERATURE_VRMEM:
627 *value = metrics->TemperatureVrMem *
628 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
629 break;
630 case METRICS_THROTTLER_STATUS:
631 *value = metrics->ThrottlerStatus;
632 break;
633 case METRICS_CURR_FANSPEED:
634 *value = metrics->CurrFanSpeed;
635 break;
636 default:
637 *value = UINT_MAX0xffffffffU;
638 break;
639 }
640
641 mutex_unlock(&smu->metrics_lock)rw_exit_write(&smu->metrics_lock);
642
643 return ret;
644}
645
646static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
647 enum smu_clk_type clk_type,
648 uint32_t *value)
649{
650 MetricsMember_t member_type;
651 int clk_id = 0;
652
653 if (!value)
654 return -EINVAL22;
655
656 clk_id = smu_cmn_to_asic_specific_index(smu,
657 CMN2ASIC_MAPPING_CLK,
658 clk_type);
659 if (clk_id < 0)
660 return -EINVAL22;
661
662 switch (clk_id) {
663 case PPCLK_GFXCLK:
664 /*
665 * CurrClock[clk_id] can provide accurate
666 * output only when the dpm feature is enabled.
667 * We can use Average_* for dpm disabled case.
668 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
669 */
670 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
671 member_type = METRICS_CURR_GFXCLK;
672 else
673 member_type = METRICS_AVERAGE_GFXCLK;
674 break;
675 case PPCLK_UCLK:
676 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
677 member_type = METRICS_CURR_UCLK;
678 else
679 member_type = METRICS_AVERAGE_UCLK;
680 break;
681 case PPCLK_SOCCLK:
682 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
683 member_type = METRICS_CURR_SOCCLK;
684 else
685 member_type = METRICS_AVERAGE_SOCCLK;
686 break;
687 case PPCLK_VCLK:
688 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
689 member_type = METRICS_CURR_VCLK;
690 else
691 member_type = METRICS_AVERAGE_VCLK;
692 break;
693 case PPCLK_DCLK:
694 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
695 member_type = METRICS_CURR_DCLK;
696 else
697 member_type = METRICS_AVERAGE_DCLK;
698 break;
699 case PPCLK_FCLK:
700 member_type = METRICS_CURR_FCLK;
701 break;
702 default:
703 return -EINVAL22;
704 }
705
706 return arcturus_get_smu_metrics_data(smu,
707 member_type,
708 value);
709}
710
711static int arcturus_print_clk_levels(struct smu_context *smu,
712 enum smu_clk_type type, char *buf)
713{
714 int i, now, size = 0;
715 int ret = 0;
716 struct pp_clock_levels_with_latency clocks;
717 struct smu_11_0_dpm_table *single_dpm_table;
718 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
719 struct smu_11_0_dpm_context *dpm_context = NULL((void *)0);
720
721 if (amdgpu_ras_intr_triggered())
722 return snprintf(buf, PAGE_SIZE(1 << 12), "unavailable\n");
723
724 dpm_context = smu_dpm->dpm_context;
725
726 switch (type) {
727 case SMU_SCLK:
728 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
729 if (ret) {
730 dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get current gfx clk Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
731 return ret;
732 }
733
734 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
735 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
736 if (ret) {
737 dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get gfx clk levels Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
738 return ret;
739 }
740
741 /*
742 * For DPM disabled case, there will be only one clock level.
743 * And it's safe to assume that is always the current clock.
744 */
745 for (i = 0; i < clocks.num_levels; i++)
746 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %uMhz %s\n", i,
747 clocks.data[i].clocks_in_khz / 1000,
748 (clocks.num_levels == 1) ? "*" :
749 (arcturus_freqs_in_same_level(
750 clocks.data[i].clocks_in_khz / 1000,
751 now) ? "*" : ""));
752 break;
753
754 case SMU_MCLK:
755 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
756 if (ret) {
757 dev_err(smu->adev->dev, "Attempt to get current mclk Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get current mclk Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
758 return ret;
759 }
760
761 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
762 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
763 if (ret) {
764 dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get memory clk levels Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
765 return ret;
766 }
767
768 for (i = 0; i < clocks.num_levels; i++)
769 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %uMhz %s\n",
770 i, clocks.data[i].clocks_in_khz / 1000,
771 (clocks.num_levels == 1) ? "*" :
772 (arcturus_freqs_in_same_level(
773 clocks.data[i].clocks_in_khz / 1000,
774 now) ? "*" : ""));
775 break;
776
777 case SMU_SOCCLK:
778 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
779 if (ret) {
780 dev_err(smu->adev->dev, "Attempt to get current socclk Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get current socclk Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
781 return ret;
782 }
783
784 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
785 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
786 if (ret) {
787 dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get socclk levels Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
788 return ret;
789 }
790
791 for (i = 0; i < clocks.num_levels; i++)
792 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %uMhz %s\n",
793 i, clocks.data[i].clocks_in_khz / 1000,
794 (clocks.num_levels == 1) ? "*" :
795 (arcturus_freqs_in_same_level(
796 clocks.data[i].clocks_in_khz / 1000,
797 now) ? "*" : ""));
798 break;
799
800 case SMU_FCLK:
801 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
802 if (ret) {
803 dev_err(smu->adev->dev, "Attempt to get current fclk Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get current fclk Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
804 return ret;
805 }
806
807 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
808 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
809 if (ret) {
810 dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!")printf("drm:pid%d:%s *ERROR* " "Attempt to get fclk levels Failed!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
811 return ret;
812 }
813
814 for (i = 0; i < single_dpm_table->count; i++)
815 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%d: %uMhz %s\n",
816 i, single_dpm_table->dpm_levels[i].value,
817 (clocks.num_levels == 1) ? "*" :
818 (arcturus_freqs_in_same_level(
819 clocks.data[i].clocks_in_khz / 1000,
820 now) ? "*" : ""));
821 break;
822
823 default:
824 break;
825 }
826
827 return size;
828}
829
830static int arcturus_upload_dpm_level(struct smu_context *smu,
831 bool_Bool max,
832 uint32_t feature_mask,
833 uint32_t level)
834{
835 struct smu_11_0_dpm_context *dpm_context =
836 smu->smu_dpm.dpm_context;
837 uint32_t freq;
838 int ret = 0;
839
840 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
841 (feature_mask & FEATURE_DPM_GFXCLK_MASK(1 << 1 ))) {
842 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
843 ret = smu_cmn_send_smc_msg_with_param(smu,
844 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
845 (PPCLK_GFXCLK << 16) | (freq & 0xffff),
846 NULL((void *)0));
847 if (ret) {
848 dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",printf("drm:pid%d:%s *ERROR* " "Failed to set soft %s gfxclk !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , max ? "max"
: "min")
849 max ? "max" : "min")printf("drm:pid%d:%s *ERROR* " "Failed to set soft %s gfxclk !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , max ? "max"
: "min")
;
850 return ret;
851 }
852 }
853
854 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
855 (feature_mask & FEATURE_DPM_UCLK_MASK(1 << 2 ))) {
856 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
857 ret = smu_cmn_send_smc_msg_with_param(smu,
858 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
859 (PPCLK_UCLK << 16) | (freq & 0xffff),
860 NULL((void *)0));
861 if (ret) {
862 dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",printf("drm:pid%d:%s *ERROR* " "Failed to set soft %s memclk !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , max ? "max"
: "min")
863 max ? "max" : "min")printf("drm:pid%d:%s *ERROR* " "Failed to set soft %s memclk !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , max ? "max"
: "min")
;
864 return ret;
865 }
866 }
867
868 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
869 (feature_mask & FEATURE_DPM_SOCCLK_MASK(1 << 3 ))) {
870 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
871 ret = smu_cmn_send_smc_msg_with_param(smu,
872 (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
873 (PPCLK_SOCCLK << 16) | (freq & 0xffff),
874 NULL((void *)0));
875 if (ret) {
876 dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",printf("drm:pid%d:%s *ERROR* " "Failed to set soft %s socclk !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , max ? "max"
: "min")
877 max ? "max" : "min")printf("drm:pid%d:%s *ERROR* " "Failed to set soft %s socclk !\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , max ? "max"
: "min")
;
878 return ret;
879 }
880 }
881
882 return ret;
883}
884
885static int arcturus_force_clk_levels(struct smu_context *smu,
886 enum smu_clk_type type, uint32_t mask)
887{
888 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
889 struct smu_11_0_dpm_table *single_dpm_table = NULL((void *)0);
890 uint32_t soft_min_level, soft_max_level;
891 uint32_t smu_version;
892 int ret = 0;
893
894 ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
895 if (ret) {
896 dev_err(smu->adev->dev, "Failed to get smu version!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get smu version!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
897 return ret;
898 }
899
900 if ((smu_version >= 0x361200) &&
901 (smu_version <= 0x361a00)) {
902 dev_err(smu->adev->dev, "Forcing clock level is not supported with "printf("drm:pid%d:%s *ERROR* " "Forcing clock level is not supported with "
"54.18 - 54.26(included) SMU firmwares\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__)
903 "54.18 - 54.26(included) SMU firmwares\n")printf("drm:pid%d:%s *ERROR* " "Forcing clock level is not supported with "
"54.18 - 54.26(included) SMU firmwares\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__)
;
904 return -EOPNOTSUPP45;
905 }
906
907 soft_min_level = mask ? (ffs(mask) - 1) : 0;
908 soft_max_level = mask ? (fls(mask) - 1) : 0;
909
910 switch (type) {
911 case SMU_SCLK:
912 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
913 if (soft_max_level >= single_dpm_table->count) {
914 dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",printf("drm:pid%d:%s *ERROR* " "Clock level specified %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , soft_max_level
, single_dpm_table->count - 1)
915 soft_max_level, single_dpm_table->count - 1)printf("drm:pid%d:%s *ERROR* " "Clock level specified %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , soft_max_level
, single_dpm_table->count - 1)
;
916 ret = -EINVAL22;
917 break;
918 }
919
920 ret = arcturus_upload_dpm_level(smu,
921 false0,
922 FEATURE_DPM_GFXCLK_MASK(1 << 1 ),
923 soft_min_level);
924 if (ret) {
925 dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n")printf("drm:pid%d:%s *ERROR* " "Failed to upload boot level to lowest!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
926 break;
927 }
928
929 ret = arcturus_upload_dpm_level(smu,
930 true1,
931 FEATURE_DPM_GFXCLK_MASK(1 << 1 ),
932 soft_max_level);
933 if (ret)
934 dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n")printf("drm:pid%d:%s *ERROR* " "Failed to upload dpm max level to highest!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
935
936 break;
937
938 case SMU_MCLK:
939 case SMU_SOCCLK:
940 case SMU_FCLK:
941 /*
942 * Should not arrive here since Arcturus does not
943 * support mclk/socclk/fclk softmin/softmax settings
944 */
945 ret = -EINVAL22;
946 break;
947
948 default:
949 break;
950 }
951
952 return ret;
953}
954
955static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
956 struct smu_temperature_range *range)
957{
958 struct smu_table_context *table_context = &smu->smu_table;
959 struct smu_11_0_powerplay_table *powerplay_table =
960 table_context->power_play_table;
961 PPTable_t *pptable = smu->smu_table.driver_pptable;
962
963 if (!range)
964 return -EINVAL22;
965
966 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range))__builtin_memcpy((range), (&smu11_thermal_policy[0]), (sizeof
(struct smu_temperature_range)))
;
967
968 range->max = pptable->TedgeLimit *
969 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
970 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE5) *
971 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
972 range->hotspot_crit_max = pptable->ThotspotLimit *
973 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
974 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT5) *
975 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
976 range->mem_crit_max = pptable->TmemLimit *
977 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
978 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM5)*
979 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES1000;
980 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
981
982 return 0;
983}
984
985static int arcturus_get_current_activity_percent(struct smu_context *smu,
986 enum amd_pp_sensors sensor,
987 uint32_t *value)
988{
989 int ret = 0;
990
991 if (!value)
992 return -EINVAL22;
993
994 switch (sensor) {
995 case AMDGPU_PP_SENSOR_GPU_LOAD:
996 ret = arcturus_get_smu_metrics_data(smu,
997 METRICS_AVERAGE_GFXACTIVITY,
998 value);
999 break;
1000 case AMDGPU_PP_SENSOR_MEM_LOAD:
1001 ret = arcturus_get_smu_metrics_data(smu,
1002 METRICS_AVERAGE_MEMACTIVITY,
1003 value);
1004 break;
1005 default:
1006 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n")printf("drm:pid%d:%s *ERROR* " "Invalid sensor for retrieving clock activity\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1007 return -EINVAL22;
1008 }
1009
1010 return ret;
1011}
1012
1013static int arcturus_get_gpu_power(struct smu_context *smu, uint32_t *value)
1014{
1015 if (!value)
1016 return -EINVAL22;
1017
1018 return arcturus_get_smu_metrics_data(smu,
1019 METRICS_AVERAGE_SOCKETPOWER,
1020 value);
1021}
1022
1023static int arcturus_thermal_get_temperature(struct smu_context *smu,
1024 enum amd_pp_sensors sensor,
1025 uint32_t *value)
1026{
1027 int ret = 0;
1028
1029 if (!value)
1030 return -EINVAL22;
1031
1032 switch (sensor) {
1033 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1034 ret = arcturus_get_smu_metrics_data(smu,
1035 METRICS_TEMPERATURE_HOTSPOT,
1036 value);
1037 break;
1038 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1039 ret = arcturus_get_smu_metrics_data(smu,
1040 METRICS_TEMPERATURE_EDGE,
1041 value);
1042 break;
1043 case AMDGPU_PP_SENSOR_MEM_TEMP:
1044 ret = arcturus_get_smu_metrics_data(smu,
1045 METRICS_TEMPERATURE_MEM,
1046 value);
1047 break;
1048 default:
1049 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n")printf("drm:pid%d:%s *ERROR* " "Invalid sensor for retrieving temp\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1050 return -EINVAL22;
1051 }
1052
1053 return ret;
1054}
1055
1056static int arcturus_read_sensor(struct smu_context *smu,
1057 enum amd_pp_sensors sensor,
1058 void *data, uint32_t *size)
1059{
1060 struct smu_table_context *table_context = &smu->smu_table;
1061 PPTable_t *pptable = table_context->driver_pptable;
1062 int ret = 0;
1063
1064 if (amdgpu_ras_intr_triggered())
1065 return 0;
1066
1067 if (!data || !size)
1068 return -EINVAL22;
1069
1070 mutex_lock(&smu->sensor_lock)rw_enter_write(&smu->sensor_lock);
1071 switch (sensor) {
1072 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1073 *(uint32_t *)data = pptable->FanMaximumRpm;
1074 *size = 4;
1075 break;
1076 case AMDGPU_PP_SENSOR_MEM_LOAD:
1077 case AMDGPU_PP_SENSOR_GPU_LOAD:
1078 ret = arcturus_get_current_activity_percent(smu,
1079 sensor,
1080 (uint32_t *)data);
1081 *size = 4;
1082 break;
1083 case AMDGPU_PP_SENSOR_GPU_POWER:
1084 ret = arcturus_get_gpu_power(smu, (uint32_t *)data);
1085 *size = 4;
1086 break;
1087 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1088 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1089 case AMDGPU_PP_SENSOR_MEM_TEMP:
1090 ret = arcturus_thermal_get_temperature(smu, sensor,
1091 (uint32_t *)data);
1092 *size = 4;
1093 break;
1094 case AMDGPU_PP_SENSOR_GFX_MCLK:
1095 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1096 /* the output clock frequency in 10K unit */
1097 *(uint32_t *)data *= 100;
1098 *size = 4;
1099 break;
1100 case AMDGPU_PP_SENSOR_GFX_SCLK:
1101 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1102 *(uint32_t *)data *= 100;
1103 *size = 4;
1104 break;
1105 case AMDGPU_PP_SENSOR_VDDGFX:
1106 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1107 *size = 4;
1108 break;
1109 default:
1110 ret = -EOPNOTSUPP45;
1111 break;
1112 }
1113 mutex_unlock(&smu->sensor_lock)rw_exit_write(&smu->sensor_lock);
1114
1115 return ret;
1116}
1117
1118static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1119 uint32_t *speed)
1120{
1121 if (!speed)
1122 return -EINVAL22;
1123
1124 switch (smu_v11_0_get_fan_control_mode(smu)) {
1125 case AMD_FAN_CTRL_AUTO:
1126 return arcturus_get_smu_metrics_data(smu,
1127 METRICS_CURR_FANSPEED,
1128 speed);
1129 default:
1130 return smu_v11_0_get_fan_speed_rpm(smu, speed);
1131 }
1132}
1133
1134static int arcturus_get_fan_parameters(struct smu_context *smu)
1135{
1136 PPTable_t *pptable = smu->smu_table.driver_pptable;
1137
1138 smu->fan_max_rpm = pptable->FanMaximumRpm;
1139
1140 return 0;
1141}
1142
1143static int arcturus_get_power_limit(struct smu_context *smu)
1144{
1145 struct smu_11_0_powerplay_table *powerplay_table =
1146 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1147 PPTable_t *pptable = smu->smu_table.driver_pptable;
1148 uint32_t power_limit, od_percent;
1149
1150 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1151 /* the last hope to figure out the ppt limit */
1152 if (!pptable) {
1153 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!")printf("drm:pid%d:%s *ERROR* " "Cannot get PPT limit due to pptable missing!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1154 return -EINVAL22;
1155 }
1156 power_limit =
1157 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1158 }
1159 smu->current_power_limit = power_limit;
1160
1161 if (smu->od_enabled) {
1162 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE])((__uint32_t)(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE
]))
;
1163
1164 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit)do { } while(0);
1165
1166 power_limit *= (100 + od_percent);
1167 power_limit /= 100;
1168 }
1169 smu->max_power_limit = power_limit;
1170
1171 return 0;
1172}
1173
1174static int arcturus_get_power_profile_mode(struct smu_context *smu,
1175 char *buf)
1176{
1177 DpmActivityMonitorCoeffInt_t activity_monitor;
1178 static const char *profile_name[] = {
1179 "BOOTUP_DEFAULT",
1180 "3D_FULL_SCREEN",
1181 "POWER_SAVING",
1182 "VIDEO",
1183 "VR",
1184 "COMPUTE",
1185 "CUSTOM"};
1186 static const char *title[] = {
1187 "PROFILE_INDEX(NAME)",
1188 "CLOCK_TYPE(NAME)",
1189 "FPS",
1190 "UseRlcBusy",
1191 "MinActiveFreqType",
1192 "MinActiveFreq",
1193 "BoosterFreqType",
1194 "BoosterFreq",
1195 "PD_Data_limit_c",
1196 "PD_Data_error_coeff",
1197 "PD_Data_error_rate_coeff"};
1198 uint32_t i, size = 0;
1199 int16_t workload_type = 0;
1200 int result = 0;
1201 uint32_t smu_version;
1202
1203 if (!buf)
1204 return -EINVAL22;
1205
1206 result = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
1207 if (result)
1208 return result;
1209
1210 if (smu_version >= 0x360d00)
1211 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1212 title[0], title[1], title[2], title[3], title[4], title[5],
1213 title[6], title[7], title[8], title[9], title[10]);
1214 else
1215 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%16s\n",
1216 title[0]);
1217
1218 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1219 /*
1220 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1221 * Not all profile modes are supported on arcturus.
1222 */
1223 workload_type = smu_cmn_to_asic_specific_index(smu,
1224 CMN2ASIC_MAPPING_WORKLOAD,
1225 i);
1226 if (workload_type < 0)
1227 continue;
1228
1229 if (smu_version >= 0x360d00) {
1230 result = smu_cmn_update_table(smu,
1231 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1232 workload_type,
1233 (void *)(&activity_monitor),
1234 false0);
1235 if (result) {
1236 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to get activity monitor!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1237 return result;
1238 }
1239 }
1240
1241 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%2d %14s%s\n",
1242 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1243
1244 if (smu_version >= 0x360d00) {
1245 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1246 " ",
1247 0,
1248 "GFXCLK",
1249 activity_monitor.Gfx_FPS,
1250 activity_monitor.Gfx_UseRlcBusy,
1251 activity_monitor.Gfx_MinActiveFreqType,
1252 activity_monitor.Gfx_MinActiveFreq,
1253 activity_monitor.Gfx_BoosterFreqType,
1254 activity_monitor.Gfx_BoosterFreq,
1255 activity_monitor.Gfx_PD_Data_limit_c,
1256 activity_monitor.Gfx_PD_Data_error_coeff,
1257 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1258
1259 size += snprintf(buf + size, PAGE_SIZE(1 << 12) - size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1260 " ",
1261 1,
1262 "UCLK",
1263 activity_monitor.Mem_FPS,
1264 activity_monitor.Mem_UseRlcBusy,
1265 activity_monitor.Mem_MinActiveFreqType,
1266 activity_monitor.Mem_MinActiveFreq,
1267 activity_monitor.Mem_BoosterFreqType,
1268 activity_monitor.Mem_BoosterFreq,
1269 activity_monitor.Mem_PD_Data_limit_c,
1270 activity_monitor.Mem_PD_Data_error_coeff,
1271 activity_monitor.Mem_PD_Data_error_rate_coeff);
1272 }
1273 }
1274
1275 return size;
1276}
1277
1278static int arcturus_set_power_profile_mode(struct smu_context *smu,
1279 long *input,
1280 uint32_t size)
1281{
1282 DpmActivityMonitorCoeffInt_t activity_monitor;
1283 int workload_type = 0;
1284 uint32_t profile_mode = input[size];
1285 int ret = 0;
1286 uint32_t smu_version;
1287
1288 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1289 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode)printf("drm:pid%d:%s *ERROR* " "Invalid power profile mode %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , profile_mode
)
;
1290 return -EINVAL22;
1291 }
1292
1293 ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
1294 if (ret)
1295 return ret;
1296
1297 if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1298 (smu_version >=0x360d00)) {
1299 ret = smu_cmn_update_table(smu,
1300 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1301 WORKLOAD_PPLIB_CUSTOM_BIT4,
1302 (void *)(&activity_monitor),
1303 false0);
1304 if (ret) {
1305 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to get activity monitor!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1306 return ret;
1307 }
1308
1309 switch (input[0]) {
1310 case 0: /* Gfxclk */
1311 activity_monitor.Gfx_FPS = input[1];
1312 activity_monitor.Gfx_UseRlcBusy = input[2];
1313 activity_monitor.Gfx_MinActiveFreqType = input[3];
1314 activity_monitor.Gfx_MinActiveFreq = input[4];
1315 activity_monitor.Gfx_BoosterFreqType = input[5];
1316 activity_monitor.Gfx_BoosterFreq = input[6];
1317 activity_monitor.Gfx_PD_Data_limit_c = input[7];
1318 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1319 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1320 break;
1321 case 1: /* Uclk */
1322 activity_monitor.Mem_FPS = input[1];
1323 activity_monitor.Mem_UseRlcBusy = input[2];
1324 activity_monitor.Mem_MinActiveFreqType = input[3];
1325 activity_monitor.Mem_MinActiveFreq = input[4];
1326 activity_monitor.Mem_BoosterFreqType = input[5];
1327 activity_monitor.Mem_BoosterFreq = input[6];
1328 activity_monitor.Mem_PD_Data_limit_c = input[7];
1329 activity_monitor.Mem_PD_Data_error_coeff = input[8];
1330 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1331 break;
1332 }
1333
1334 ret = smu_cmn_update_table(smu,
1335 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1336 WORKLOAD_PPLIB_CUSTOM_BIT4,
1337 (void *)(&activity_monitor),
1338 true1);
1339 if (ret) {
1340 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Failed to set activity monitor!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__
)
;
1341 return ret;
1342 }
1343 }
1344
1345 /*
1346 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1347 * Not all profile modes are supported on arcturus.
1348 */
1349 workload_type = smu_cmn_to_asic_specific_index(smu,
1350 CMN2ASIC_MAPPING_WORKLOAD,
1351 profile_mode);
1352 if (workload_type < 0) {
1353 dev_err(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode)printf("drm:pid%d:%s *ERROR* " "Unsupported power profile mode %d on arcturus\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , profile_mode
)
;
1354 return -EINVAL22;
1355 }
1356
1357 ret = smu_cmn_send_smc_msg_with_param(smu,
1358 SMU_MSG_SetWorkloadMask,
1359 1 << workload_type,
1360 NULL((void *)0));
1361 if (ret) {
1362 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type)printf("drm:pid%d:%s *ERROR* " "Fail to set workload type %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , workload_type
)
;
1363 return ret;
1364 }
1365
1366 smu->power_profile_mode = profile_mode;
1367
1368 return 0;
1369}
1370
1371static int arcturus_set_performance_level(struct smu_context *smu,
1372 enum amd_dpm_forced_level level)
1373{
1374 uint32_t smu_version;
1375 int ret;
1376
1377 ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
1378 if (ret) {
1379 dev_err(smu->adev->dev, "Failed to get smu version!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get smu version!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1380 return ret;
1381 }
1382
1383 switch (level) {
1384 case AMD_DPM_FORCED_LEVEL_HIGH:
1385 case AMD_DPM_FORCED_LEVEL_LOW:
1386 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1387 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1388 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1389 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1390 if ((smu_version >= 0x361200) &&
1391 (smu_version <= 0x361a00)) {
1392 dev_err(smu->adev->dev, "Forcing clock level is not supported with "printf("drm:pid%d:%s *ERROR* " "Forcing clock level is not supported with "
"54.18 - 54.26(included) SMU firmwares\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__)
1393 "54.18 - 54.26(included) SMU firmwares\n")printf("drm:pid%d:%s *ERROR* " "Forcing clock level is not supported with "
"54.18 - 54.26(included) SMU firmwares\n", ({struct cpu_info
*__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__)
;
1394 return -EOPNOTSUPP45;
1395 }
1396 break;
1397 default:
1398 break;
1399 }
1400
1401 return smu_v11_0_set_performance_level(smu, level);
1402}
1403
1404static void arcturus_dump_pptable(struct smu_context *smu)
1405{
1406 struct smu_table_context *table_context = &smu->smu_table;
1407 PPTable_t *pptable = table_context->driver_pptable;
Value stored to 'pptable' during its initialization is never read
1408 int i;
1409
1410 dev_info(smu->adev->dev, "Dumped PPTable:\n")do { } while(0);
1411
1412 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version)do { } while(0);
1413
1414 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0])do { } while(0);
1415 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1])do { } while(0);
1416
1417 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1418 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i])do { } while(0);
1419 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i])do { } while(0);
1420 }
1421
1422 dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc)do { } while(0);
1423 dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau)do { } while(0);
1424 dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx)do { } while(0);
1425 dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau)do { } while(0);
1426
1427 dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit)do { } while(0);
1428 dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit)do { } while(0);
1429 dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit)do { } while(0);
1430 dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit)do { } while(0);
1431 dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit)do { } while(0);
1432 dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit)do { } while(0);
1433 dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit)do { } while(0);
1434
1435 dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit)do { } while(0);
1436 dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold)do { } while(0);
1437
1438 dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask)do { } while(0);
1439
1440 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx)do { } while(0);
1441 dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding)do { } while(0);
1442
1443 dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass)do { } while(0);
1444 dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0])do { } while(0);
1445 dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1])do { } while(0);
1446 dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2])do { } while(0);
1447
1448 dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx)do { } while(0);
1449 dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc)do { } while(0);
1450 dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx)do { } while(0);
1451 dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc)do { } while(0);
1452
1453 dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx)do { } while(0);
1454 dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc)do { } while(0);
1455
1456 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"do { } while(0)
1457 " .VoltageMode = 0x%02x\n"do { } while(0)
1458 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1459 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1460 " .padding = 0x%02x\n"do { } while(0)
1461 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1462 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1463 " .SsFmin = 0x%04x\n"do { } while(0)
1464 " .Padding_16 = 0x%04x\n",do { } while(0)
1465 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,do { } while(0)
1466 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,do { } while(0)
1467 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,do { } while(0)
1468 pptable->DpmDescriptor[PPCLK_GFXCLK].padding,do { } while(0)
1469 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,do { } while(0)
1470 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,do { } while(0)
1471 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,do { } while(0)
1472 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,do { } while(0)
1473 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,do { } while(0)
1474 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,do { } while(0)
1475 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16)do { } while(0);
1476
1477 dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"do { } while(0)
1478 " .VoltageMode = 0x%02x\n"do { } while(0)
1479 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1480 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1481 " .padding = 0x%02x\n"do { } while(0)
1482 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1483 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1484 " .SsFmin = 0x%04x\n"do { } while(0)
1485 " .Padding_16 = 0x%04x\n",do { } while(0)
1486 pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,do { } while(0)
1487 pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,do { } while(0)
1488 pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,do { } while(0)
1489 pptable->DpmDescriptor[PPCLK_VCLK].padding,do { } while(0)
1490 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,do { } while(0)
1491 pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,do { } while(0)
1492 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,do { } while(0)
1493 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,do { } while(0)
1494 pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,do { } while(0)
1495 pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,do { } while(0)
1496 pptable->DpmDescriptor[PPCLK_VCLK].Padding16)do { } while(0);
1497
1498 dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"do { } while(0)
1499 " .VoltageMode = 0x%02x\n"do { } while(0)
1500 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1501 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1502 " .padding = 0x%02x\n"do { } while(0)
1503 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1504 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1505 " .SsFmin = 0x%04x\n"do { } while(0)
1506 " .Padding_16 = 0x%04x\n",do { } while(0)
1507 pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,do { } while(0)
1508 pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,do { } while(0)
1509 pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,do { } while(0)
1510 pptable->DpmDescriptor[PPCLK_DCLK].padding,do { } while(0)
1511 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,do { } while(0)
1512 pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,do { } while(0)
1513 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,do { } while(0)
1514 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,do { } while(0)
1515 pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,do { } while(0)
1516 pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,do { } while(0)
1517 pptable->DpmDescriptor[PPCLK_DCLK].Padding16)do { } while(0);
1518
1519 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"do { } while(0)
1520 " .VoltageMode = 0x%02x\n"do { } while(0)
1521 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1522 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1523 " .padding = 0x%02x\n"do { } while(0)
1524 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1525 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1526 " .SsFmin = 0x%04x\n"do { } while(0)
1527 " .Padding_16 = 0x%04x\n",do { } while(0)
1528 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,do { } while(0)
1529 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,do { } while(0)
1530 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,do { } while(0)
1531 pptable->DpmDescriptor[PPCLK_SOCCLK].padding,do { } while(0)
1532 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,do { } while(0)
1533 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,do { } while(0)
1534 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,do { } while(0)
1535 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,do { } while(0)
1536 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,do { } while(0)
1537 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,do { } while(0)
1538 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16)do { } while(0);
1539
1540 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"do { } while(0)
1541 " .VoltageMode = 0x%02x\n"do { } while(0)
1542 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1543 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1544 " .padding = 0x%02x\n"do { } while(0)
1545 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1546 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1547 " .SsFmin = 0x%04x\n"do { } while(0)
1548 " .Padding_16 = 0x%04x\n",do { } while(0)
1549 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,do { } while(0)
1550 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,do { } while(0)
1551 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,do { } while(0)
1552 pptable->DpmDescriptor[PPCLK_UCLK].padding,do { } while(0)
1553 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,do { } while(0)
1554 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,do { } while(0)
1555 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,do { } while(0)
1556 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,do { } while(0)
1557 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,do { } while(0)
1558 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,do { } while(0)
1559 pptable->DpmDescriptor[PPCLK_UCLK].Padding16)do { } while(0);
1560
1561 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"do { } while(0)
1562 " .VoltageMode = 0x%02x\n"do { } while(0)
1563 " .SnapToDiscrete = 0x%02x\n"do { } while(0)
1564 " .NumDiscreteLevels = 0x%02x\n"do { } while(0)
1565 " .padding = 0x%02x\n"do { } while(0)
1566 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"do { } while(0)
1567 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"do { } while(0)
1568 " .SsFmin = 0x%04x\n"do { } while(0)
1569 " .Padding_16 = 0x%04x\n",do { } while(0)
1570 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,do { } while(0)
1571 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,do { } while(0)
1572 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,do { } while(0)
1573 pptable->DpmDescriptor[PPCLK_FCLK].padding,do { } while(0)
1574 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,do { } while(0)
1575 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,do { } while(0)
1576 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,do { } while(0)
1577 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,do { } while(0)
1578 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,do { } while(0)
1579 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,do { } while(0)
1580 pptable->DpmDescriptor[PPCLK_FCLK].Padding16)do { } while(0);
1581
1582
1583 dev_info(smu->adev->dev, "FreqTableGfx\n")do { } while(0);
1584 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS16; i++)
1585 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableGfx[i])do { } while(0);
1586
1587 dev_info(smu->adev->dev, "FreqTableVclk\n")do { } while(0);
1588 for (i = 0; i < NUM_VCLK_DPM_LEVELS8; i++)
1589 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableVclk[i])do { } while(0);
1590
1591 dev_info(smu->adev->dev, "FreqTableDclk\n")do { } while(0);
1592 for (i = 0; i < NUM_DCLK_DPM_LEVELS8; i++)
1593 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableDclk[i])do { } while(0);
1594
1595 dev_info(smu->adev->dev, "FreqTableSocclk\n")do { } while(0);
1596 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS8; i++)
1597 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableSocclk[i])do { } while(0);
1598
1599 dev_info(smu->adev->dev, "FreqTableUclk\n")do { } while(0);
1600 for (i = 0; i < NUM_UCLK_DPM_LEVELS4; i++)
1601 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableUclk[i])do { } while(0);
1602
1603 dev_info(smu->adev->dev, "FreqTableFclk\n")do { } while(0);
1604 for (i = 0; i < NUM_FCLK_DPM_LEVELS8; i++)
1605 dev_info(smu->adev->dev, " .[%02d] = %d\n", i, pptable->FreqTableFclk[i])do { } while(0);
1606
1607 dev_info(smu->adev->dev, "Mp0clkFreq\n")do { } while(0);
1608 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++)
1609 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0clkFreq[i])do { } while(0);
1610
1611 dev_info(smu->adev->dev, "Mp0DpmVoltage\n")do { } while(0);
1612 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS2; i++)
1613 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i])do { } while(0);
1614
1615 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle)do { } while(0);
1616 dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate)do { } while(0);
1617 dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0])do { } while(0);
1618 dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1])do { } while(0);
1619 dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2])do { } while(0);
1620 dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3])do { } while(0);
1621 dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq)do { } while(0);
1622 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource)do { } while(0);
1623 dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456)do { } while(0);
1624
1625 dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm)do { } while(0);
1626 dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature)do { } while(0);
1627 dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature)do { } while(0);
1628 dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit)do { } while(0);
1629
1630 dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp)do { } while(0);
1631 dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp)do { } while(0);
1632
1633 dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge)do { } while(0);
1634 dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot)do { } while(0);
1635 dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx)do { } while(0);
1636 dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc)do { } while(0);
1637 dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem)do { } while(0);
1638 dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm)do { } while(0);
1639
1640 dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin)do { } while(0);
1641 dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm)do { } while(0);
1642 dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm)do { } while(0);
1643 dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm)do { } while(0);
1644 dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature)do { } while(0);
1645 dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk)do { } while(0);
1646 dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable)do { } while(0);
1647 dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev)do { } while(0);
1648 dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect)do { } while(0);
1649
1650 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta)do { } while(0);
1651 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta)do { } while(0);
1652 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta)do { } while(0);
1653 dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved)do { } while(0);
1654
1655 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX])do { } while(0);
1656 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC])do { } while(0);
1657 dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0])do { } while(0);
1658 dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1])do { } while(0);
1659
1660 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1661 pptable->dBtcGbGfxPll.a,do { } while(0)
1662 pptable->dBtcGbGfxPll.b,do { } while(0)
1663 pptable->dBtcGbGfxPll.c)do { } while(0);
1664 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1665 pptable->dBtcGbGfxAfll.a,do { } while(0)
1666 pptable->dBtcGbGfxAfll.b,do { } while(0)
1667 pptable->dBtcGbGfxAfll.c)do { } while(0);
1668 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1669 pptable->dBtcGbSoc.a,do { } while(0)
1670 pptable->dBtcGbSoc.b,do { } while(0)
1671 pptable->dBtcGbSoc.c)do { } while(0);
1672
1673 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",do { } while(0)
1674 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,do { } while(0)
1675 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b)do { } while(0);
1676 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",do { } while(0)
1677 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,do { } while(0)
1678 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b)do { } while(0);
1679
1680 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1681 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,do { } while(0)
1682 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,do { } while(0)
1683 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c)do { } while(0);
1684 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1685 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,do { } while(0)
1686 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,do { } while(0)
1687 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c)do { } while(0);
1688
1689 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX])do { } while(0);
1690 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC])do { } while(0);
1691
1692 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX])do { } while(0);
1693 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC])do { } while(0);
1694 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0])do { } while(0);
1695 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1])do { } while(0);
1696
1697 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX])do { } while(0);
1698 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC])do { } while(0);
1699 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX])do { } while(0);
1700 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC])do { } while(0);
1701
1702 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX])do { } while(0);
1703 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC])do { } while(0);
1704
1705 dev_info(smu->adev->dev, "XgmiDpmPstates\n")do { } while(0);
1706 for (i = 0; i < NUM_XGMI_LEVELS2; i++)
1707 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiDpmPstates[i])do { } while(0);
1708 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0])do { } while(0);
1709 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1])do { } while(0);
1710
1711 dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin)do { } while(0);
1712 dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin)do { } while(0);
1713 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp)do { } while(0);
1714 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp)do { } while(0);
1715 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp)do { } while(0);
1716 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp)do { } while(0);
1717 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis)do { } while(0);
1718 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis)do { } while(0);
1719
1720 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides)do { } while(0);
1721 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1722 pptable->ReservedEquation0.a,do { } while(0)
1723 pptable->ReservedEquation0.b,do { } while(0)
1724 pptable->ReservedEquation0.c)do { } while(0);
1725 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1726 pptable->ReservedEquation1.a,do { } while(0)
1727 pptable->ReservedEquation1.b,do { } while(0)
1728 pptable->ReservedEquation1.c)do { } while(0);
1729 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1730 pptable->ReservedEquation2.a,do { } while(0)
1731 pptable->ReservedEquation2.b,do { } while(0)
1732 pptable->ReservedEquation2.c)do { } while(0);
1733 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",do { } while(0)
1734 pptable->ReservedEquation3.a,do { } while(0)
1735 pptable->ReservedEquation3.b,do { } while(0)
1736 pptable->ReservedEquation3.c)do { } while(0);
1737
1738 dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx)do { } while(0);
1739 dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv)do { } while(0);
1740
1741 dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig)do { } while(0);
1742 dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1)do { } while(0);
1743 dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2)do { } while(0);
1744
1745 dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow)do { } while(0);
1746 dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh)do { } while(0);
1747
1748 dev_info(smu->adev->dev, "Board Parameters:\n")do { } while(0);
1749 dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx)do { } while(0);
1750 dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc)do { } while(0);
1751
1752 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping)do { } while(0);
1753 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping)do { } while(0);
1754 dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping)do { } while(0);
1755 dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping)do { } while(0);
1756
1757 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask)do { } while(0);
1758 dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent)do { } while(0);
1759
1760 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent)do { } while(0);
1761 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset)do { } while(0);
1762 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx)do { } while(0);
1763
1764 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent)do { } while(0);
1765 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset)do { } while(0);
1766 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc)do { } while(0);
1767
1768 dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent)do { } while(0);
1769 dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset)do { } while(0);
1770 dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem)do { } while(0);
1771
1772 dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent)do { } while(0);
1773 dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset)do { } while(0);
1774 dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput)do { } while(0);
1775
1776 dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio)do { } while(0);
1777 dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity)do { } while(0);
1778 dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio)do { } while(0);
1779 dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity)do { } while(0);
1780
1781 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled)do { } while(0);
1782 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent)do { } while(0);
1783 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq)do { } while(0);
1784
1785 dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled)do { } while(0);
1786 dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent)do { } while(0);
1787 dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq)do { } while(0);
1788
1789 dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled)do { } while(0);
1790 dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent)do { } while(0);
1791 dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq)do { } while(0);
1792
1793 dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled)do { } while(0);
1794 dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent)do { } while(0);
1795 dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq)do { } while(0);
1796
1797 for (i = 0; i < NUM_I2C_CONTROLLERS8; i++) {
1798 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i)do { } while(0);
1799 dev_info(smu->adev->dev, " .Enabled = %d\n",do { } while(0)
1800 pptable->I2cControllers[i].Enabled)do { } while(0);
1801 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",do { } while(0)
1802 pptable->I2cControllers[i].SlaveAddress)do { } while(0);
1803 dev_info(smu->adev->dev, " .ControllerPort = %d\n",do { } while(0)
1804 pptable->I2cControllers[i].ControllerPort)do { } while(0);
1805 dev_info(smu->adev->dev, " .ControllerName = %d\n",do { } while(0)
1806 pptable->I2cControllers[i].ControllerName)do { } while(0);
1807 dev_info(smu->adev->dev, " .ThermalThrottler = %d\n",do { } while(0)
1808 pptable->I2cControllers[i].ThermalThrotter)do { } while(0);
1809 dev_info(smu->adev->dev, " .I2cProtocol = %d\n",do { } while(0)
1810 pptable->I2cControllers[i].I2cProtocol)do { } while(0);
1811 dev_info(smu->adev->dev, " .Speed = %d\n",do { } while(0)
1812 pptable->I2cControllers[i].Speed)do { } while(0);
1813 }
1814
1815 dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled)do { } while(0);
1816 dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth)do { } while(0);
1817
1818 dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower)do { } while(0);
1819
1820 dev_info(smu->adev->dev, "XgmiLinkSpeed\n")do { } while(0);
1821 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
1822 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i])do { } while(0);
1823 dev_info(smu->adev->dev, "XgmiLinkWidth\n")do { } while(0);
1824 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
1825 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiLinkWidth[i])do { } while(0);
1826 dev_info(smu->adev->dev, "XgmiFclkFreq\n")do { } while(0);
1827 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
1828 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiFclkFreq[i])do { } while(0);
1829 dev_info(smu->adev->dev, "XgmiSocVoltage\n")do { } while(0);
1830 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS4; i++)
1831 dev_info(smu->adev->dev, " .[%d] = %d\n", i, pptable->XgmiSocVoltage[i])do { } while(0);
1832
1833}
1834
1835static bool_Bool arcturus_is_dpm_running(struct smu_context *smu)
1836{
1837 int ret = 0;
1838 uint32_t feature_mask[2];
1839 uint64_t feature_enabled;
1840
1841 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1842 if (ret)
1843 return false0;
1844
1845 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1846
1847 return !!(feature_enabled & SMC_DPM_FEATURE( (1 << 0 ) | (1 << 1 ) | (1 << 2 ) | (1 <<
3 ) | (1 << 5 ) | (1 << 4 ) | (1 << 6 ))
);
1848}
1849
1850static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool_Bool enable)
1851{
1852 int ret = 0;
1853
1854 if (enable) {
1855 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1856 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1857 if (ret) {
1858 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n")printf("drm:pid%d:%s *ERROR* " "[EnableVCNDPM] failed!\n", ({
struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1859 return ret;
1860 }
1861 }
1862 } else {
1863 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1864 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1865 if (ret) {
1866 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n")printf("drm:pid%d:%s *ERROR* " "[DisableVCNDPM] failed!\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1867 return ret;
1868 }
1869 }
1870 }
1871
1872 return ret;
1873}
1874
1875static void arcturus_fill_i2c_req(SwI2cRequest_t *req, bool_Bool write,
1876 uint8_t address, uint32_t numbytes,
1877 uint8_t *data)
1878{
1879 int i;
1880
1881 req->I2CcontrollerPort = 0;
1882 req->I2CSpeed = 2;
1883 req->SlaveAddress = address;
1884 req->NumCmds = numbytes;
1885
1886 for (i = 0; i < numbytes; i++) {
1887 SwI2cCmd_t *cmd = &req->SwI2cCmds[i];
1888
1889 /* First 2 bytes are always write for lower 2b EEPROM address */
1890 if (i < 2)
1891 cmd->Cmd = 1;
1892 else
1893 cmd->Cmd = write;
1894
1895
1896 /* Add RESTART for read after address filled */
1897 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK(1 << 1) : 0;
1898
1899 /* Add STOP in the end */
1900 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK(1 << 0) : 0;
1901
1902 /* Fill with data regardless if read or write to simplify code */
1903 cmd->RegisterAddr = data[i];
1904 }
1905}
1906
1907static int arcturus_i2c_read_data(struct i2c_adapter *control,
1908 uint8_t address,
1909 uint8_t *data,
1910 uint32_t numbytes)
1911{
1912 uint32_t i, ret = 0;
1913 SwI2cRequest_t req;
1914 struct amdgpu_device *adev = to_amdgpu_device(control)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (control); (struct amdgpu_device *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_device, pm.smu_i2c) );}))
;
1915 struct smu_table_context *smu_table = &adev->smu.smu_table;
1916 struct smu_table *table = &smu_table->driver_table;
1917
1918 if (numbytes > MAX_SW_I2C_COMMANDS8) {
1919 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 8)
1920 numbytes, MAX_SW_I2C_COMMANDS)printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 8)
;
1921 return -EINVAL22;
1922 }
1923
1924 memset(&req, 0, sizeof(req))__builtin_memset((&req), (0), (sizeof(req)));
1925 arcturus_fill_i2c_req(&req, false0, address, numbytes, data);
1926
1927 mutex_lock(&adev->smu.mutex)rw_enter_write(&adev->smu.mutex);
1928 /* Now read data starting with that address */
1929 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1930 true1);
1931 mutex_unlock(&adev->smu.mutex)rw_exit_write(&adev->smu.mutex);
1932
1933 if (!ret) {
1934 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1935
1936 /* Assume SMU fills res.SwI2cCmds[i].Data with read bytes */
1937 for (i = 0; i < numbytes; i++)
1938 data[i] = res->SwI2cCmds[i].Data;
1939
1940 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",do { } while(0)
1941 (uint16_t)address, numbytes)do { } while(0);
1942
1943 print_hex_dump(KERN_DEBUG"\0017", "data: ", DUMP_PREFIX_NONE,
1944 8, 1, data, numbytes, false0);
1945 } else
1946 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret)printf("drm:pid%d:%s *ERROR* " "arcturus_i2c_read_data - error occurred :%x"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1947
1948 return ret;
1949}
1950
1951static int arcturus_i2c_write_data(struct i2c_adapter *control,
1952 uint8_t address,
1953 uint8_t *data,
1954 uint32_t numbytes)
1955{
1956 uint32_t ret;
1957 SwI2cRequest_t req;
1958 struct amdgpu_device *adev = to_amdgpu_device(control)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (control); (struct amdgpu_device *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_device, pm.smu_i2c) );}))
;
1959
1960 if (numbytes > MAX_SW_I2C_COMMANDS8) {
1961 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 8)
1962 numbytes, MAX_SW_I2C_COMMANDS)printf("drm:pid%d:%s *ERROR* " "numbytes requested %d is over max allowed %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , numbytes
, 8)
;
1963 return -EINVAL22;
1964 }
1965
1966 memset(&req, 0, sizeof(req))__builtin_memset((&req), (0), (sizeof(req)));
1967 arcturus_fill_i2c_req(&req, true1, address, numbytes, data);
1968
1969 mutex_lock(&adev->smu.mutex)rw_enter_write(&adev->smu.mutex);
1970 ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true1);
1971 mutex_unlock(&adev->smu.mutex)rw_exit_write(&adev->smu.mutex);
1972
1973 if (!ret) {
1974 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",do { } while(0)
1975 (uint16_t)address, numbytes)do { } while(0);
1976
1977 print_hex_dump(KERN_DEBUG"\0017", "data: ", DUMP_PREFIX_NONE,
1978 8, 1, data, numbytes, false0);
1979 /*
1980 * According to EEPROM spec there is a MAX of 10 ms required for
1981 * EEPROM to flush internal RX buffer after STOP was issued at the
1982 * end of write transaction. During this time the EEPROM will not be
1983 * responsive to any more commands - so wait a bit more.
1984 */
1985 drm_msleep(10)mdelay(10);
1986
1987 } else
1988 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret)printf("drm:pid%d:%s *ERROR* " "arcturus_i2c_write- error occurred :%x"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1989
1990 return ret;
1991}
1992
1993static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
1994 struct i2c_msg *msgs, int num)
1995{
1996 uint32_t i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1997 uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS8] = { 0 };
1998
1999 for (i = 0; i < num; i++) {
2000 /*
2001 * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2002 * once and hence the data needs to be spliced into chunks and sent each
2003 * chunk separately
2004 */
2005 data_size = msgs[i].len - 2;
2006 data_chunk_size = MAX_SW_I2C_COMMANDS8 - 2;
2007 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2008 data_ptr = msgs[i].buf + 2;
2009
2010 for (j = 0; j < data_size / data_chunk_size; j++) {
2011 /* Insert the EEPROM dest addess, bits 0-15 */
2012 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2013 data_chunk[1] = (next_eeprom_addr & 0xff);
2014
2015 if (msgs[i].flags & I2C_M_RD0x0001) {
2016 ret = arcturus_i2c_read_data(i2c_adap,
2017 (uint8_t)msgs[i].addr,
2018 data_chunk, MAX_SW_I2C_COMMANDS8);
2019
2020 memcpy(data_ptr, data_chunk + 2, data_chunk_size)__builtin_memcpy((data_ptr), (data_chunk + 2), (data_chunk_size
))
;
2021 } else {
2022
2023 memcpy(data_chunk + 2, data_ptr, data_chunk_size)__builtin_memcpy((data_chunk + 2), (data_ptr), (data_chunk_size
))
;
2024
2025 ret = arcturus_i2c_write_data(i2c_adap,
2026 (uint8_t)msgs[i].addr,
2027 data_chunk, MAX_SW_I2C_COMMANDS8);
2028 }
2029
2030 if (ret) {
2031 num = -EIO5;
2032 goto fail;
2033 }
2034
2035 next_eeprom_addr += data_chunk_size;
2036 data_ptr += data_chunk_size;
2037 }
2038
2039 if (data_size % data_chunk_size) {
2040 data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2041 data_chunk[1] = (next_eeprom_addr & 0xff);
2042
2043 if (msgs[i].flags & I2C_M_RD0x0001) {
2044 ret = arcturus_i2c_read_data(i2c_adap,
2045 (uint8_t)msgs[i].addr,
2046 data_chunk, (data_size % data_chunk_size) + 2);
2047
2048 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size)__builtin_memcpy((data_ptr), (data_chunk + 2), (data_size % data_chunk_size
))
;
2049 } else {
2050 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size)__builtin_memcpy((data_chunk + 2), (data_ptr), (data_size % data_chunk_size
))
;
2051
2052 ret = arcturus_i2c_write_data(i2c_adap,
2053 (uint8_t)msgs[i].addr,
2054 data_chunk, (data_size % data_chunk_size) + 2);
2055 }
2056
2057 if (ret) {
2058 num = -EIO5;
2059 goto fail;
2060 }
2061 }
2062 }
2063
2064fail:
2065 return num;
2066}
2067
2068static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2069{
2070 return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0;
2071}
2072
2073
2074static const struct i2c_algorithm arcturus_i2c_algo = {
2075 .master_xfer = arcturus_i2c_xfer,
2076 .functionality = arcturus_i2c_func,
2077};
2078
2079static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2080{
2081 struct amdgpu_device *adev = to_amdgpu_device(control)(({ const __typeof( ((struct amdgpu_device *)0)->pm.smu_i2c
) *__mptr = (control); (struct amdgpu_device *)( (char *)__mptr
- __builtin_offsetof(struct amdgpu_device, pm.smu_i2c) );}))
;
2082 int res;
2083
2084#ifdef __linux__
2085 control->owner = THIS_MODULE((void *)0);
2086 control->class = I2C_CLASS_SPD;
2087 control->dev.parent = &adev->pdev->dev;
2088#endif
2089 control->algo = &arcturus_i2c_algo;
2090 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2091
2092 res = i2c_add_adapter(control)0;
2093 if (res)
2094 DRM_ERROR("Failed to register hw i2c, err: %d\n", res)__drm_err("Failed to register hw i2c, err: %d\n", res);
2095
2096 return res;
2097}
2098
2099static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2100{
2101 i2c_del_adapter(control);
2102}
2103
2104static void arcturus_get_unique_id(struct smu_context *smu)
2105{
2106 struct amdgpu_device *adev = smu->adev;
2107 uint32_t top32 = 0, bottom32 = 0, smu_version;
2108 uint64_t id;
2109
2110 if (smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version)) {
2111 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n")printf("drm:pid%d:%s *WARNING* " "Failed to get smu version, cannot get unique_id or serial_number\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
2112 return;
2113 }
2114
2115 /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2116 if (smu_version < 0x361700) {
2117 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n")printf("drm:pid%d:%s *WARNING* " "ReadSerial is only supported by PMFW 54.23.0 and onwards\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
2118 return;
2119 }
2120
2121 /* Get the SN to turn into a Unique ID */
2122 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2123 smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2124
2125 id = ((uint64_t)bottom32 << 32) | top32;
2126 adev->unique_id = id;
2127 /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2128 * 16-digit HEX string for convenience and backwards-compatibility
2129 */
2130 snprintf(adev->serial, sizeof(adev->serial), "%llx", id);
2131}
2132
2133static bool_Bool arcturus_is_baco_supported(struct smu_context *smu)
2134{
2135 struct amdgpu_device *adev = smu->adev;
2136 uint32_t val;
2137
2138 if (!smu_v11_0_baco_is_support(smu) || amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
2139 return false0;
2140
2141 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0)amdgpu_device_rreg(adev, (adev->reg_offset[NBIO_HWIP][0][2
] + 0x0000), 0)
;
2142 return (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK0x00000080L) ? true1 : false0;
2143}
2144
2145static int arcturus_set_df_cstate(struct smu_context *smu,
2146 enum pp_df_cstate state)
2147{
2148 uint32_t smu_version;
2149 int ret;
2150
2151 ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
2152 if (ret) {
2153 dev_err(smu->adev->dev, "Failed to get smu version!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get smu version!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
2154 return ret;
2155 }
2156
2157 /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2158 if (smu_version < 0x360F00) {
2159 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n")printf("drm:pid%d:%s *ERROR* " "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
2160 return -EINVAL22;
2161 }
2162
2163 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL((void *)0));
2164}
2165
2166static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool_Bool en)
2167{
2168 uint32_t smu_version;
2169 int ret;
2170
2171 ret = smu_cmn_get_smc_version(smu, NULL((void *)0), &smu_version);
2172 if (ret) {
2173 dev_err(smu->adev->dev, "Failed to get smu version!\n")printf("drm:pid%d:%s *ERROR* " "Failed to get smu version!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
2174 return ret;
2175 }
2176
2177 /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2178 if (smu_version < 0x00361700) {
2179 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n")printf("drm:pid%d:%s *ERROR* " "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
2180 return -EINVAL22;
2181 }
2182
2183 if (en)
2184 return smu_cmn_send_smc_msg_with_param(smu,
2185 SMU_MSG_GmiPwrDnControl,
2186 1,
2187 NULL((void *)0));
2188
2189 return smu_cmn_send_smc_msg_with_param(smu,
2190 SMU_MSG_GmiPwrDnControl,
2191 0,
2192 NULL((void *)0));
2193}
2194
2195static const struct throttling_logging_label {
2196 uint32_t feature_mask;
2197 const char *label;
2198} logging_label[] = {
2199 {(1U << THROTTLER_TEMP_HOTSPOT_BIT2), "GPU"},
2200 {(1U << THROTTLER_TEMP_MEM_BIT3), "HBM"},
2201 {(1U << THROTTLER_TEMP_VR_GFX_BIT4), "VR of GFX rail"},
2202 {(1U << THROTTLER_TEMP_VR_MEM_BIT5), "VR of HBM rail"},
2203 {(1U << THROTTLER_TEMP_VR_SOC_BIT6), "VR of SOC rail"},
2204 {(1U << THROTTLER_VRHOT0_BIT16), "VR0 HOT"},
2205 {(1U << THROTTLER_VRHOT1_BIT17), "VR1 HOT"},
2206};
2207static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2208{
2209 int ret;
2210 int throttler_idx, throtting_events = 0, buf_idx = 0;
2211 struct amdgpu_device *adev = smu->adev;
2212 uint32_t throttler_status;
2213 char log_buf[256];
2214
2215 ret = arcturus_get_smu_metrics_data(smu,
2216 METRICS_THROTTLER_STATUS,
2217 &throttler_status);
2218 if (ret)
2219 return;
2220
2221 memset(log_buf, 0, sizeof(log_buf))__builtin_memset((log_buf), (0), (sizeof(log_buf)));
2222 for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label)(sizeof((logging_label)) / sizeof((logging_label)[0]));
2223 throttler_idx++) {
2224 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2225 throtting_events++;
2226 buf_idx += snprintf(log_buf + buf_idx,
2227 sizeof(log_buf) - buf_idx,
2228 "%s%s",
2229 throtting_events > 1 ? " and " : "",
2230 logging_label[throttler_idx].label);
2231 if (buf_idx >= sizeof(log_buf)) {
2232 dev_err(adev->dev, "buffer overflow!\n")printf("drm:pid%d:%s *ERROR* " "buffer overflow!\n", ({struct
cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__)
;
2233 log_buf[sizeof(log_buf) - 1] = '\0';
2234 break;
2235 }
2236 }
2237 }
2238
2239 dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",printf("drm:pid%d:%s *WARNING* " "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , log_buf
)
2240 log_buf)printf("drm:pid%d:%s *WARNING* " "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , log_buf
)
;
2241 kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2242}
2243
2244static int arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2245{
2246 struct amdgpu_device *adev = smu->adev;
2247 uint32_t esm_ctrl;
2248
2249 /* TODO: confirm this on real target */
2250 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL)adev->pcie_rreg(adev, (0x111003D0));
2251 if ((esm_ctrl >> 15) & 0x1FFFF)
2252 return (((esm_ctrl >> 8) & 0x3F) + 128);
2253
2254 return smu_v11_0_get_current_pcie_link_speed(smu);
2255}
2256
2257static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2258 void **table)
2259{
2260 struct smu_table_context *smu_table = &smu->smu_table;
2261 struct gpu_metrics_v1_0 *gpu_metrics =
2262 (struct gpu_metrics_v1_0 *)smu_table->gpu_metrics_table;
2263 SmuMetrics_t metrics;
2264 int ret = 0;
2265
2266 ret = smu_cmn_get_metrics_table(smu,
2267 &metrics,
2268 true1);
2269 if (ret)
2270 return ret;
2271
2272 smu_v11_0_init_gpu_metrics_v1_0(gpu_metrics);
2273
2274 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2275 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2276 gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2277 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2278 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2279 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2280
2281 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2282 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2283 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2284
2285 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2286 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2287
2288 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2289 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2290 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2291 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2292 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2293
2294 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2295 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2296 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2297 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2298 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2299
2300 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2301
2302 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2303
2304 gpu_metrics->pcie_link_width =
2305 smu_v11_0_get_current_pcie_link_width(smu);
2306 gpu_metrics->pcie_link_speed =
2307 arcturus_get_current_pcie_link_speed(smu);
2308
2309 *table = (void *)gpu_metrics;
2310
2311 return sizeof(struct gpu_metrics_v1_0);
2312}
2313
2314static const struct pptable_funcs arcturus_ppt_funcs = {
2315 /* init dpm */
2316 .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2317 /* btc */
2318 .run_btc = arcturus_run_btc,
2319 /* dpm/clk tables */
2320 .set_default_dpm_table = arcturus_set_default_dpm_table,
2321 .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2322 .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2323 .print_clk_levels = arcturus_print_clk_levels,
2324 .force_clk_levels = arcturus_force_clk_levels,
2325 .read_sensor = arcturus_read_sensor,
2326 .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2327 .get_power_profile_mode = arcturus_get_power_profile_mode,
2328 .set_power_profile_mode = arcturus_set_power_profile_mode,
2329 .set_performance_level = arcturus_set_performance_level,
2330 /* debug (internal used) */
2331 .dump_pptable = arcturus_dump_pptable,
2332 .get_power_limit = arcturus_get_power_limit,
2333 .is_dpm_running = arcturus_is_dpm_running,
2334 .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2335 .i2c_init = arcturus_i2c_control_init,
2336 .i2c_fini = arcturus_i2c_control_fini,
2337 .get_unique_id = arcturus_get_unique_id,
2338 .init_microcode = smu_v11_0_init_microcode,
2339 .load_microcode = smu_v11_0_load_microcode,
2340 .fini_microcode = smu_v11_0_fini_microcode,
2341 .init_smc_tables = arcturus_init_smc_tables,
2342 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2343 .init_power = smu_v11_0_init_power,
2344 .fini_power = smu_v11_0_fini_power,
2345 .check_fw_status = smu_v11_0_check_fw_status,
2346 /* pptable related */
2347 .setup_pptable = arcturus_setup_pptable,
2348 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2349 .check_fw_version = smu_v11_0_check_fw_version,
2350 .write_pptable = smu_cmn_write_pptable,
2351 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2352 .set_tool_table_location = smu_v11_0_set_tool_table_location,
2353 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2354 .system_features_control = smu_v11_0_system_features_control,
2355 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2356 .send_smc_msg = smu_cmn_send_smc_msg,
2357 .init_display_count = NULL((void *)0),
2358 .set_allowed_mask = smu_v11_0_set_allowed_mask,
2359 .get_enabled_mask = smu_cmn_get_enabled_mask,
2360 .feature_is_enabled = smu_cmn_feature_is_enabled,
2361 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2362 .notify_display_change = NULL((void *)0),
2363 .set_power_limit = smu_v11_0_set_power_limit,
2364 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2365 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2366 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2367 .set_min_dcef_deep_sleep = NULL((void *)0),
2368 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2369 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2370 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2371 .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2372 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
2373 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2374 .gfx_off_control = smu_v11_0_gfx_off_control,
2375 .register_irq_handler = smu_v11_0_register_irq_handler,
2376 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2377 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2378 .baco_is_support= arcturus_is_baco_supported,
2379 .baco_get_state = smu_v11_0_baco_get_state,
2380 .baco_set_state = smu_v11_0_baco_set_state,
2381 .baco_enter = smu_v11_0_baco_enter,
2382 .baco_exit = smu_v11_0_baco_exit,
2383 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2384 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2385 .set_df_cstate = arcturus_set_df_cstate,
2386 .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2387 .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2388 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2389 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2390 .get_gpu_metrics = arcturus_get_gpu_metrics,
2391 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2392 .deep_sleep_control = smu_v11_0_deep_sleep_control,
2393 .get_fan_parameters = arcturus_get_fan_parameters,
2394 .interrupt_work = smu_v11_0_interrupt_work,
2395};
2396
2397void arcturus_set_ppt_funcs(struct smu_context *smu)
2398{
2399 smu->ppt_funcs = &arcturus_ppt_funcs;
2400 smu->message_map = arcturus_message_map;
2401 smu->clock_map = arcturus_clk_map;
2402 smu->feature_map = arcturus_feature_mask_map;
2403 smu->table_map = arcturus_table_map;
2404 smu->pwr_src_map = arcturus_pwr_src_map;
2405 smu->workload_map = arcturus_workload_map;
2406}