File: | dev/pci/drm/amd/pm/swsmu/smu11/smu_v11_0.c |
Warning: | line 226, column 2 Value stored to 'smu_debug' is never read |
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1 | /* |
2 | * Copyright 2019 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | */ |
22 | |
23 | #include <linux/firmware.h> |
24 | #include <linux/module.h> |
25 | #include <linux/pci.h> |
26 | #include <linux/reboot.h> |
27 | |
28 | #define SMU_11_0_PARTIAL_PPTABLE |
29 | #define SWSMU_CODE_LAYER_L3 |
30 | |
31 | #include "amdgpu.h" |
32 | #include "amdgpu_smu.h" |
33 | #include "atomfirmware.h" |
34 | #include "amdgpu_atomfirmware.h" |
35 | #include "amdgpu_atombios.h" |
36 | #include "smu_v11_0.h" |
37 | #include "soc15_common.h" |
38 | #include "atom.h" |
39 | #include "amdgpu_ras.h" |
40 | #include "smu_cmn.h" |
41 | |
42 | #include "asic_reg/thm/thm_11_0_2_offset.h" |
43 | #include "asic_reg/thm/thm_11_0_2_sh_mask.h" |
44 | #include "asic_reg/mp/mp_11_0_offset.h" |
45 | #include "asic_reg/mp/mp_11_0_sh_mask.h" |
46 | #include "asic_reg/smuio/smuio_11_0_0_offset.h" |
47 | #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h" |
48 | |
49 | /* |
50 | * DO NOT use these for err/warn/info/debug messages. |
51 | * Use dev_err, dev_warn, dev_info and dev_dbg instead. |
52 | * They are more MGPU friendly. |
53 | */ |
54 | #undef pr_err |
55 | #undef pr_warn |
56 | #undef pr_info |
57 | #undef pr_debug |
58 | |
59 | MODULE_FIRMWARE("amdgpu/arcturus_smc.bin"); |
60 | MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); |
61 | MODULE_FIRMWARE("amdgpu/navi14_smc.bin"); |
62 | MODULE_FIRMWARE("amdgpu/navi12_smc.bin"); |
63 | MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin"); |
64 | MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin"); |
65 | |
66 | #define SMU11_VOLTAGE_SCALE4 4 |
67 | |
68 | #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS500 500 //500ms |
69 | |
70 | #define LINK_WIDTH_MAX6 6 |
71 | #define LINK_SPEED_MAX3 3 |
72 | |
73 | #define smnPCIE_LC_LINK_WIDTH_CNTL0x11140288 0x11140288 |
74 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK0x00000070L 0x00000070L |
75 | #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT0x4 0x4 |
76 | #define smnPCIE_LC_SPEED_CNTL0x11140290 0x11140290 |
77 | #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK0xC000 0xC000 |
78 | #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT0xE 0xE |
79 | |
80 | static int link_width[] = {0, 1, 2, 4, 8, 12, 16}; |
81 | static int link_speed[] = {25, 50, 80, 160}; |
82 | |
83 | int smu_v11_0_init_microcode(struct smu_context *smu) |
84 | { |
85 | struct amdgpu_device *adev = smu->adev; |
86 | const char *chip_name; |
87 | char fw_name[30]; |
88 | int err = 0; |
89 | const struct smc_firmware_header_v1_0 *hdr; |
90 | const struct common_firmware_header *header; |
91 | struct amdgpu_firmware_info *ucode = NULL((void *)0); |
92 | |
93 | switch (adev->asic_type) { |
94 | case CHIP_ARCTURUS: |
95 | chip_name = "arcturus"; |
96 | break; |
97 | case CHIP_NAVI10: |
98 | chip_name = "navi10"; |
99 | break; |
100 | case CHIP_NAVI14: |
101 | chip_name = "navi14"; |
102 | break; |
103 | case CHIP_NAVI12: |
104 | chip_name = "navi12"; |
105 | break; |
106 | case CHIP_SIENNA_CICHLID: |
107 | chip_name = "sienna_cichlid"; |
108 | break; |
109 | case CHIP_NAVY_FLOUNDER: |
110 | chip_name = "navy_flounder"; |
111 | break; |
112 | default: |
113 | dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type)printf("drm:pid%d:%s *ERROR* " "Unsupported ASIC type %d\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , adev-> asic_type); |
114 | return -EINVAL22; |
115 | } |
116 | |
117 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name); |
118 | |
119 | err = request_firmware(&adev->pm.fw, fw_name, adev->dev); |
120 | if (err) |
121 | goto out; |
122 | err = amdgpu_ucode_validate(adev->pm.fw); |
123 | if (err) |
124 | goto out; |
125 | |
126 | hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; |
127 | amdgpu_ucode_print_smc_hdr(&hdr->header); |
128 | adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version)); |
129 | |
130 | if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { |
131 | ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC]; |
132 | ucode->ucode_id = AMDGPU_UCODE_ID_SMC; |
133 | ucode->fw = adev->pm.fw; |
134 | header = (const struct common_firmware_header *)ucode->fw->data; |
135 | adev->firmware.fw_size += |
136 | roundup2(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE)(((((__uint32_t)(header->ucode_size_bytes))) + (((1 << 12)) - 1)) & (~((__typeof(((__uint32_t)(header->ucode_size_bytes ))))((1 << 12)) - 1))); |
137 | } |
138 | |
139 | out: |
140 | if (err) { |
141 | DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",__drm_err("smu_v11_0: Failed to load firmware \"%s\"\n", fw_name ) |
142 | fw_name)__drm_err("smu_v11_0: Failed to load firmware \"%s\"\n", fw_name ); |
143 | release_firmware(adev->pm.fw); |
144 | adev->pm.fw = NULL((void *)0); |
145 | } |
146 | return err; |
147 | } |
148 | |
149 | void smu_v11_0_fini_microcode(struct smu_context *smu) |
150 | { |
151 | struct amdgpu_device *adev = smu->adev; |
152 | |
153 | release_firmware(adev->pm.fw); |
154 | adev->pm.fw = NULL((void *)0); |
155 | adev->pm.fw_version = 0; |
156 | } |
157 | |
158 | int smu_v11_0_load_microcode(struct smu_context *smu) |
159 | { |
160 | struct amdgpu_device *adev = smu->adev; |
161 | const uint32_t *src; |
162 | const struct smc_firmware_header_v1_0 *hdr; |
163 | uint32_t addr_start = MP1_SRAM0x03c00004; |
164 | uint32_t i; |
165 | uint32_t smc_fw_size; |
166 | uint32_t mp1_fw_flags; |
167 | |
168 | hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; |
169 | src = (const uint32_t *)(adev->pm.fw->data + |
170 | le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes))); |
171 | smc_fw_size = hdr->header.ucode_size_bytes; |
172 | |
173 | for (i = 1; i < smc_fw_size/4 - 1; i++) { |
174 | WREG32_PCIE(addr_start, src[i])adev->pcie_wreg(adev, (addr_start), (src[i])); |
175 | addr_start += 4; |
176 | } |
177 | |
178 | WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),adev->pcie_wreg(adev, (0x03b00000 | (0x3010b14 & 0xffffffff )), (1 & 0x00000001L)) |
179 | 1 & MP1_SMN_PUB_CTRL__RESET_MASK)adev->pcie_wreg(adev, (0x03b00000 | (0x3010b14 & 0xffffffff )), (1 & 0x00000001L)); |
180 | WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),adev->pcie_wreg(adev, (0x03b00000 | (0x3010b14 & 0xffffffff )), (1 & ~0x00000001L)) |
181 | 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK)adev->pcie_wreg(adev, (0x03b00000 | (0x3010b14 & 0xffffffff )), (1 & ~0x00000001L)); |
182 | |
183 | for (i = 0; i < adev->usec_timeout; i++) { |
184 | mp1_fw_flags = RREG32_PCIE(MP1_Public |adev->pcie_rreg(adev, (0x03b00000 | (0x3010024 & 0xffffffff ))) |
185 | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))adev->pcie_rreg(adev, (0x03b00000 | (0x3010024 & 0xffffffff ))); |
186 | if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK0x00000001L) >> |
187 | MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT0x0) |
188 | break; |
189 | udelay(1); |
190 | } |
191 | |
192 | if (i == adev->usec_timeout) |
193 | return -ETIME60; |
194 | |
195 | return 0; |
196 | } |
197 | |
198 | int smu_v11_0_check_fw_status(struct smu_context *smu) |
199 | { |
200 | struct amdgpu_device *adev = smu->adev; |
201 | uint32_t mp1_fw_flags; |
202 | |
203 | mp1_fw_flags = RREG32_PCIE(MP1_Public |adev->pcie_rreg(adev, (0x03b00000 | (0x3010024 & 0xffffffff ))) |
204 | (smnMP1_FIRMWARE_FLAGS & 0xffffffff))adev->pcie_rreg(adev, (0x03b00000 | (0x3010024 & 0xffffffff ))); |
205 | |
206 | if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK0x00000001L) >> |
207 | MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT0x0) |
208 | return 0; |
209 | |
210 | return -EIO5; |
211 | } |
212 | |
213 | int smu_v11_0_check_fw_version(struct smu_context *smu) |
214 | { |
215 | uint32_t if_version = 0xff, smu_version = 0xff; |
216 | uint16_t smu_major; |
217 | uint8_t smu_minor, smu_debug; |
218 | int ret = 0; |
219 | |
220 | ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version); |
221 | if (ret) |
222 | return ret; |
223 | |
224 | smu_major = (smu_version >> 16) & 0xffff; |
225 | smu_minor = (smu_version >> 8) & 0xff; |
226 | smu_debug = (smu_version >> 0) & 0xff; |
Value stored to 'smu_debug' is never read | |
227 | |
228 | switch (smu->adev->asic_type) { |
229 | case CHIP_ARCTURUS: |
230 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT0x17; |
231 | break; |
232 | case CHIP_NAVI10: |
233 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV100x36; |
234 | break; |
235 | case CHIP_NAVI12: |
236 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV120x36; |
237 | break; |
238 | case CHIP_NAVI14: |
239 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV140x36; |
240 | break; |
241 | case CHIP_SIENNA_CICHLID: |
242 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid0x39; |
243 | break; |
244 | case CHIP_NAVY_FLOUNDER: |
245 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder0x5; |
246 | break; |
247 | default: |
248 | dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type)printf("drm:pid%d:%s *ERROR* " "smu unsupported asic type:%d.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , smu-> adev->asic_type); |
249 | smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV0xFFFFFFFF; |
250 | break; |
251 | } |
252 | |
253 | /* |
254 | * 1. if_version mismatch is not critical as our fw is designed |
255 | * to be backward compatible. |
256 | * 2. New fw usually brings some optimizations. But that's visible |
257 | * only on the paired driver. |
258 | * Considering above, we just leave user a warning message instead |
259 | * of halt driver loading. |
260 | */ |
261 | if (if_version != smu->smc_driver_if_version) { |
262 | dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "do { } while(0) |
263 | "smu fw version = 0x%08x (%d.%d.%d)\n",do { } while(0) |
264 | smu->smc_driver_if_version, if_version,do { } while(0) |
265 | smu_version, smu_major, smu_minor, smu_debug)do { } while(0); |
266 | dev_warn(smu->adev->dev, "SMU driver if version not matched\n")printf("drm:pid%d:%s *WARNING* " "SMU driver if version not matched\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
267 | } |
268 | |
269 | return ret; |
270 | } |
271 | |
272 | static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size) |
273 | { |
274 | struct amdgpu_device *adev = smu->adev; |
275 | uint32_t ppt_offset_bytes; |
276 | const struct smc_firmware_header_v2_0 *v2; |
277 | |
278 | v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data; |
279 | |
280 | ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes)((__uint32_t)(v2->ppt_offset_bytes)); |
281 | *size = le32_to_cpu(v2->ppt_size_bytes)((__uint32_t)(v2->ppt_size_bytes)); |
282 | *table = (uint8_t *)v2 + ppt_offset_bytes; |
283 | |
284 | return 0; |
285 | } |
286 | |
287 | static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table, |
288 | uint32_t *size, uint32_t pptable_id) |
289 | { |
290 | struct amdgpu_device *adev = smu->adev; |
291 | const struct smc_firmware_header_v2_1 *v2_1; |
292 | struct smc_soft_pptable_entry *entries; |
293 | uint32_t pptable_count = 0; |
294 | int i = 0; |
295 | |
296 | v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data; |
297 | entries = (struct smc_soft_pptable_entry *) |
298 | ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset)((__uint32_t)(v2_1->pptable_entry_offset))); |
299 | pptable_count = le32_to_cpu(v2_1->pptable_count)((__uint32_t)(v2_1->pptable_count)); |
300 | for (i = 0; i < pptable_count; i++) { |
301 | if (le32_to_cpu(entries[i].id)((__uint32_t)(entries[i].id)) == pptable_id) { |
302 | *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes)((__uint32_t)(entries[i].ppt_offset_bytes))); |
303 | *size = le32_to_cpu(entries[i].ppt_size_bytes)((__uint32_t)(entries[i].ppt_size_bytes)); |
304 | break; |
305 | } |
306 | } |
307 | |
308 | if (i == pptable_count) |
309 | return -EINVAL22; |
310 | |
311 | return 0; |
312 | } |
313 | |
314 | int smu_v11_0_setup_pptable(struct smu_context *smu) |
315 | { |
316 | struct amdgpu_device *adev = smu->adev; |
317 | const struct smc_firmware_header_v1_0 *hdr; |
318 | int ret, index; |
319 | uint32_t size = 0; |
320 | uint16_t atom_table_size; |
321 | uint8_t frev, crev; |
322 | void *table; |
323 | uint16_t version_major, version_minor; |
324 | |
325 | if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
326 | hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data; |
327 | version_major = le16_to_cpu(hdr->header.header_version_major)((__uint16_t)(hdr->header.header_version_major)); |
328 | version_minor = le16_to_cpu(hdr->header.header_version_minor)((__uint16_t)(hdr->header.header_version_minor)); |
329 | if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) || |
330 | adev->asic_type == CHIP_NAVY_FLOUNDER) { |
331 | dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id)do { } while(0); |
332 | switch (version_minor) { |
333 | case 0: |
334 | ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size); |
335 | break; |
336 | case 1: |
337 | ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size, |
338 | smu->smu_table.boot_values.pp_table_id); |
339 | break; |
340 | default: |
341 | ret = -EINVAL22; |
342 | break; |
343 | } |
344 | if (ret) |
345 | return ret; |
346 | goto out; |
347 | } |
348 | } |
349 | |
350 | dev_info(adev->dev, "use vbios provided pptable\n")do { } while(0); |
351 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , powerplayinfo) / sizeof(uint16_t)) |
352 | powerplayinfo)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , powerplayinfo) / sizeof(uint16_t)); |
353 | |
354 | ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev, |
355 | (uint8_t **)&table); |
356 | if (ret) |
357 | return ret; |
358 | size = atom_table_size; |
359 | |
360 | out: |
361 | if (!smu->smu_table.power_play_table) |
362 | smu->smu_table.power_play_table = table; |
363 | if (!smu->smu_table.power_play_table_size) |
364 | smu->smu_table.power_play_table_size = size; |
365 | |
366 | return 0; |
367 | } |
368 | |
369 | int smu_v11_0_init_smc_tables(struct smu_context *smu) |
370 | { |
371 | struct smu_table_context *smu_table = &smu->smu_table; |
372 | struct smu_table *tables = smu_table->tables; |
373 | int ret = 0; |
374 | |
375 | smu_table->driver_pptable = |
376 | kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL(0x0001 | 0x0004)); |
377 | if (!smu_table->driver_pptable) { |
378 | ret = -ENOMEM12; |
379 | goto err0_out; |
380 | } |
381 | |
382 | smu_table->max_sustainable_clocks = |
383 | kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL(0x0001 | 0x0004)); |
384 | if (!smu_table->max_sustainable_clocks) { |
385 | ret = -ENOMEM12; |
386 | goto err1_out; |
387 | } |
388 | |
389 | /* Arcturus does not support OVERDRIVE */ |
390 | if (tables[SMU_TABLE_OVERDRIVE].size) { |
391 | smu_table->overdrive_table = |
392 | kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL(0x0001 | 0x0004)); |
393 | if (!smu_table->overdrive_table) { |
394 | ret = -ENOMEM12; |
395 | goto err2_out; |
396 | } |
397 | |
398 | smu_table->boot_overdrive_table = |
399 | kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL(0x0001 | 0x0004)); |
400 | if (!smu_table->boot_overdrive_table) { |
401 | ret = -ENOMEM12; |
402 | goto err3_out; |
403 | } |
404 | } |
405 | |
406 | return 0; |
407 | |
408 | err3_out: |
409 | kfree(smu_table->overdrive_table); |
410 | err2_out: |
411 | kfree(smu_table->max_sustainable_clocks); |
412 | err1_out: |
413 | kfree(smu_table->driver_pptable); |
414 | err0_out: |
415 | return ret; |
416 | } |
417 | |
418 | int smu_v11_0_fini_smc_tables(struct smu_context *smu) |
419 | { |
420 | struct smu_table_context *smu_table = &smu->smu_table; |
421 | struct smu_dpm_context *smu_dpm = &smu->smu_dpm; |
422 | |
423 | kfree(smu_table->gpu_metrics_table); |
424 | kfree(smu_table->boot_overdrive_table); |
425 | kfree(smu_table->overdrive_table); |
426 | kfree(smu_table->max_sustainable_clocks); |
427 | kfree(smu_table->driver_pptable); |
428 | smu_table->gpu_metrics_table = NULL((void *)0); |
429 | smu_table->boot_overdrive_table = NULL((void *)0); |
430 | smu_table->overdrive_table = NULL((void *)0); |
431 | smu_table->max_sustainable_clocks = NULL((void *)0); |
432 | smu_table->driver_pptable = NULL((void *)0); |
433 | kfree(smu_table->hardcode_pptable); |
434 | smu_table->hardcode_pptable = NULL((void *)0); |
435 | |
436 | kfree(smu_table->metrics_table); |
437 | kfree(smu_table->watermarks_table); |
438 | smu_table->metrics_table = NULL((void *)0); |
439 | smu_table->watermarks_table = NULL((void *)0); |
440 | smu_table->metrics_time = 0; |
441 | |
442 | kfree(smu_dpm->dpm_context); |
443 | kfree(smu_dpm->golden_dpm_context); |
444 | kfree(smu_dpm->dpm_current_power_state); |
445 | kfree(smu_dpm->dpm_request_power_state); |
446 | smu_dpm->dpm_context = NULL((void *)0); |
447 | smu_dpm->golden_dpm_context = NULL((void *)0); |
448 | smu_dpm->dpm_context_size = 0; |
449 | smu_dpm->dpm_current_power_state = NULL((void *)0); |
450 | smu_dpm->dpm_request_power_state = NULL((void *)0); |
451 | |
452 | return 0; |
453 | } |
454 | |
455 | int smu_v11_0_init_power(struct smu_context *smu) |
456 | { |
457 | struct smu_power_context *smu_power = &smu->smu_power; |
458 | |
459 | smu_power->power_context = kzalloc(sizeof(struct smu_11_0_dpm_context), |
460 | GFP_KERNEL(0x0001 | 0x0004)); |
461 | if (!smu_power->power_context) |
462 | return -ENOMEM12; |
463 | smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context); |
464 | |
465 | return 0; |
466 | } |
467 | |
468 | int smu_v11_0_fini_power(struct smu_context *smu) |
469 | { |
470 | struct smu_power_context *smu_power = &smu->smu_power; |
471 | |
472 | kfree(smu_power->power_context); |
473 | smu_power->power_context = NULL((void *)0); |
474 | smu_power->power_context_size = 0; |
475 | |
476 | return 0; |
477 | } |
478 | |
479 | static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev, |
480 | uint8_t clk_id, |
481 | uint8_t syspll_id, |
482 | uint32_t *clk_freq) |
483 | { |
484 | struct atom_get_smu_clock_info_parameters_v3_1 input = {0}; |
485 | struct atom_get_smu_clock_info_output_parameters_v3_1 *output; |
486 | int ret, index; |
487 | |
488 | input.clk_id = clk_id; |
489 | input.syspll_id = syspll_id; |
490 | input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; |
491 | index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,(__builtin_offsetof(struct atom_master_list_of_command_functions_v2_1 , getsmuclockinfo) / sizeof(uint16_t)) |
492 | getsmuclockinfo)(__builtin_offsetof(struct atom_master_list_of_command_functions_v2_1 , getsmuclockinfo) / sizeof(uint16_t)); |
493 | |
494 | ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index, |
495 | (uint32_t *)&input); |
496 | if (ret) |
497 | return -EINVAL22; |
498 | |
499 | output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input; |
500 | *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz)((__uint32_t)(output->atom_smu_outputclkfreq.smu_clock_freq_hz )) / 10000; |
501 | |
502 | return 0; |
503 | } |
504 | |
505 | int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu) |
506 | { |
507 | int ret, index; |
508 | uint16_t size; |
509 | uint8_t frev, crev; |
510 | struct atom_common_table_header *header; |
511 | struct atom_firmware_info_v3_3 *v_3_3; |
512 | struct atom_firmware_info_v3_1 *v_3_1; |
513 | |
514 | index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , firmwareinfo) / sizeof(uint16_t)) |
515 | firmwareinfo)(__builtin_offsetof(struct atom_master_list_of_data_tables_v2_1 , firmwareinfo) / sizeof(uint16_t)); |
516 | |
517 | ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev, |
518 | (uint8_t **)&header); |
519 | if (ret) |
520 | return ret; |
521 | |
522 | if (header->format_revision != 3) { |
523 | dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n")printf("drm:pid%d:%s *ERROR* " "unknown atom_firmware_info version! for smu11\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
524 | return -EINVAL22; |
525 | } |
526 | |
527 | switch (header->content_revision) { |
528 | case 0: |
529 | case 1: |
530 | case 2: |
531 | v_3_1 = (struct atom_firmware_info_v3_1 *)header; |
532 | smu->smu_table.boot_values.revision = v_3_1->firmware_revision; |
533 | smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz; |
534 | smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; |
535 | smu->smu_table.boot_values.socclk = 0; |
536 | smu->smu_table.boot_values.dcefclk = 0; |
537 | smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv; |
538 | smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv; |
539 | smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv; |
540 | smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv; |
541 | smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id; |
542 | smu->smu_table.boot_values.pp_table_id = 0; |
543 | break; |
544 | case 3: |
545 | default: |
546 | v_3_3 = (struct atom_firmware_info_v3_3 *)header; |
547 | smu->smu_table.boot_values.revision = v_3_3->firmware_revision; |
548 | smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz; |
549 | smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; |
550 | smu->smu_table.boot_values.socclk = 0; |
551 | smu->smu_table.boot_values.dcefclk = 0; |
552 | smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv; |
553 | smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv; |
554 | smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv; |
555 | smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv; |
556 | smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id; |
557 | smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id; |
558 | } |
559 | |
560 | smu->smu_table.boot_values.format_revision = header->format_revision; |
561 | smu->smu_table.boot_values.content_revision = header->content_revision; |
562 | |
563 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
564 | (uint8_t)SMU11_SYSPLL0_SOCCLK_ID, |
565 | (uint8_t)0, |
566 | &smu->smu_table.boot_values.socclk); |
567 | |
568 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
569 | (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID, |
570 | (uint8_t)0, |
571 | &smu->smu_table.boot_values.dcefclk); |
572 | |
573 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
574 | (uint8_t)SMU11_SYSPLL0_ECLK_ID, |
575 | (uint8_t)0, |
576 | &smu->smu_table.boot_values.eclk); |
577 | |
578 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
579 | (uint8_t)SMU11_SYSPLL0_VCLK_ID, |
580 | (uint8_t)0, |
581 | &smu->smu_table.boot_values.vclk); |
582 | |
583 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
584 | (uint8_t)SMU11_SYSPLL0_DCLK_ID, |
585 | (uint8_t)0, |
586 | &smu->smu_table.boot_values.dclk); |
587 | |
588 | if ((smu->smu_table.boot_values.format_revision == 3) && |
589 | (smu->smu_table.boot_values.content_revision >= 2)) |
590 | smu_v11_0_atom_get_smu_clockinfo(smu->adev, |
591 | (uint8_t)SMU11_SYSPLL1_0_FCLK_ID, |
592 | (uint8_t)SMU11_SYSPLL1_2_ID, |
593 | &smu->smu_table.boot_values.fclk); |
594 | |
595 | return 0; |
596 | } |
597 | |
598 | int smu_v11_0_notify_memory_pool_location(struct smu_context *smu) |
599 | { |
600 | struct smu_table_context *smu_table = &smu->smu_table; |
601 | struct smu_table *memory_pool = &smu_table->memory_pool; |
602 | int ret = 0; |
603 | uint64_t address; |
604 | uint32_t address_low, address_high; |
605 | |
606 | if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL((void *)0)) |
607 | return ret; |
608 | |
609 | address = (uintptr_t)memory_pool->cpu_addr; |
610 | address_high = (uint32_t)upper_32_bits(address)((u32)(((address) >> 16) >> 16)); |
611 | address_low = (uint32_t)lower_32_bits(address)((u32)(address)); |
612 | |
613 | ret = smu_cmn_send_smc_msg_with_param(smu, |
614 | SMU_MSG_SetSystemVirtualDramAddrHigh, |
615 | address_high, |
616 | NULL((void *)0)); |
617 | if (ret) |
618 | return ret; |
619 | ret = smu_cmn_send_smc_msg_with_param(smu, |
620 | SMU_MSG_SetSystemVirtualDramAddrLow, |
621 | address_low, |
622 | NULL((void *)0)); |
623 | if (ret) |
624 | return ret; |
625 | |
626 | address = memory_pool->mc_address; |
627 | address_high = (uint32_t)upper_32_bits(address)((u32)(((address) >> 16) >> 16)); |
628 | address_low = (uint32_t)lower_32_bits(address)((u32)(address)); |
629 | |
630 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh, |
631 | address_high, NULL((void *)0)); |
632 | if (ret) |
633 | return ret; |
634 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow, |
635 | address_low, NULL((void *)0)); |
636 | if (ret) |
637 | return ret; |
638 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize, |
639 | (uint32_t)memory_pool->size, NULL((void *)0)); |
640 | if (ret) |
641 | return ret; |
642 | |
643 | return ret; |
644 | } |
645 | |
646 | int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk) |
647 | { |
648 | int ret; |
649 | |
650 | ret = smu_cmn_send_smc_msg_with_param(smu, |
651 | SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL((void *)0)); |
652 | if (ret) |
653 | dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!")printf("drm:pid%d:%s *ERROR* " "SMU11 attempt to set divider for DCEFCLK Failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
654 | |
655 | return ret; |
656 | } |
657 | |
658 | int smu_v11_0_set_driver_table_location(struct smu_context *smu) |
659 | { |
660 | struct smu_table *driver_table = &smu->smu_table.driver_table; |
661 | int ret = 0; |
662 | |
663 | if (driver_table->mc_address) { |
664 | ret = smu_cmn_send_smc_msg_with_param(smu, |
665 | SMU_MSG_SetDriverDramAddrHigh, |
666 | upper_32_bits(driver_table->mc_address)((u32)(((driver_table->mc_address) >> 16) >> 16 )), |
667 | NULL((void *)0)); |
668 | if (!ret) |
669 | ret = smu_cmn_send_smc_msg_with_param(smu, |
670 | SMU_MSG_SetDriverDramAddrLow, |
671 | lower_32_bits(driver_table->mc_address)((u32)(driver_table->mc_address)), |
672 | NULL((void *)0)); |
673 | } |
674 | |
675 | return ret; |
676 | } |
677 | |
678 | int smu_v11_0_set_tool_table_location(struct smu_context *smu) |
679 | { |
680 | int ret = 0; |
681 | struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG]; |
682 | |
683 | if (tool_table->mc_address) { |
684 | ret = smu_cmn_send_smc_msg_with_param(smu, |
685 | SMU_MSG_SetToolsDramAddrHigh, |
686 | upper_32_bits(tool_table->mc_address)((u32)(((tool_table->mc_address) >> 16) >> 16) ), |
687 | NULL((void *)0)); |
688 | if (!ret) |
689 | ret = smu_cmn_send_smc_msg_with_param(smu, |
690 | SMU_MSG_SetToolsDramAddrLow, |
691 | lower_32_bits(tool_table->mc_address)((u32)(tool_table->mc_address)), |
692 | NULL((void *)0)); |
693 | } |
694 | |
695 | return ret; |
696 | } |
697 | |
698 | int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) |
699 | { |
700 | struct amdgpu_device *adev = smu->adev; |
701 | |
702 | /* Navy_Flounder do not support to change display num currently */ |
703 | if (adev->asic_type == CHIP_NAVY_FLOUNDER) |
704 | return 0; |
705 | |
706 | return smu_cmn_send_smc_msg_with_param(smu, |
707 | SMU_MSG_NumOfDisplays, |
708 | count, |
709 | NULL((void *)0)); |
710 | } |
711 | |
712 | |
713 | int smu_v11_0_set_allowed_mask(struct smu_context *smu) |
714 | { |
715 | struct smu_feature *feature = &smu->smu_feature; |
716 | int ret = 0; |
717 | uint32_t feature_mask[2]; |
718 | |
719 | if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX)(find_first_bit(feature->allowed, (64)) == (64)) || feature->feature_num < 64) |
720 | goto failed; |
721 | |
722 | bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64); |
723 | |
724 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh, |
725 | feature_mask[1], NULL((void *)0)); |
726 | if (ret) |
727 | goto failed; |
728 | |
729 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow, |
730 | feature_mask[0], NULL((void *)0)); |
731 | if (ret) |
732 | goto failed; |
733 | |
734 | failed: |
735 | return ret; |
736 | } |
737 | |
738 | int smu_v11_0_system_features_control(struct smu_context *smu, |
739 | bool_Bool en) |
740 | { |
741 | struct smu_feature *feature = &smu->smu_feature; |
742 | uint32_t feature_mask[2]; |
743 | int ret = 0; |
744 | |
745 | ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures : |
746 | SMU_MSG_DisableAllSmuFeatures), NULL((void *)0)); |
747 | if (ret) |
748 | return ret; |
749 | |
750 | bitmap_zero(feature->enabled, feature->feature_num); |
751 | bitmap_zero(feature->supported, feature->feature_num); |
752 | |
753 | if (en) { |
754 | ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); |
755 | if (ret) |
756 | return ret; |
757 | |
758 | bitmap_copy(feature->enabled, (unsigned long *)&feature_mask, |
759 | feature->feature_num); |
760 | bitmap_copy(feature->supported, (unsigned long *)&feature_mask, |
761 | feature->feature_num); |
762 | } |
763 | |
764 | return ret; |
765 | } |
766 | |
767 | int smu_v11_0_notify_display_change(struct smu_context *smu) |
768 | { |
769 | int ret = 0; |
770 | |
771 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) && |
772 | smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM6) |
773 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL((void *)0)); |
774 | |
775 | return ret; |
776 | } |
777 | |
778 | static int |
779 | smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock, |
780 | enum smu_clk_type clock_select) |
781 | { |
782 | int ret = 0; |
783 | int clk_id; |
784 | |
785 | if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) || |
786 | (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0)) |
787 | return 0; |
788 | |
789 | clk_id = smu_cmn_to_asic_specific_index(smu, |
790 | CMN2ASIC_MAPPING_CLK, |
791 | clock_select); |
792 | if (clk_id < 0) |
793 | return -EINVAL22; |
794 | |
795 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq, |
796 | clk_id << 16, clock); |
797 | if (ret) { |
798 | dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!")printf("drm:pid%d:%s *ERROR* " "[GetMaxSustainableClock] Failed to get max DC clock from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
799 | return ret; |
800 | } |
801 | |
802 | if (*clock != 0) |
803 | return 0; |
804 | |
805 | /* if DC limit is zero, return AC limit */ |
806 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, |
807 | clk_id << 16, clock); |
808 | if (ret) { |
809 | dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!")printf("drm:pid%d:%s *ERROR* " "[GetMaxSustainableClock] failed to get max AC clock from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
810 | return ret; |
811 | } |
812 | |
813 | return 0; |
814 | } |
815 | |
816 | int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu) |
817 | { |
818 | struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks = |
819 | smu->smu_table.max_sustainable_clocks; |
820 | int ret = 0; |
821 | |
822 | max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; |
823 | max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100; |
824 | max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; |
825 | max_sustainable_clocks->display_clock = 0xFFFFFFFF; |
826 | max_sustainable_clocks->phy_clock = 0xFFFFFFFF; |
827 | max_sustainable_clocks->pixel_clock = 0xFFFFFFFF; |
828 | |
829 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
830 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
831 | &(max_sustainable_clocks->uclock), |
832 | SMU_UCLK); |
833 | if (ret) { |
834 | dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max UCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ) |
835 | __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max UCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
836 | return ret; |
837 | } |
838 | } |
839 | |
840 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) { |
841 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
842 | &(max_sustainable_clocks->soc_clock), |
843 | SMU_SOCCLK); |
844 | if (ret) { |
845 | dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max SOCCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ) |
846 | __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max SOCCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
847 | return ret; |
848 | } |
849 | } |
850 | |
851 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) { |
852 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
853 | &(max_sustainable_clocks->dcef_clock), |
854 | SMU_DCEFCLK); |
855 | if (ret) { |
856 | dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max DCEFCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ) |
857 | __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max DCEFCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
858 | return ret; |
859 | } |
860 | |
861 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
862 | &(max_sustainable_clocks->display_clock), |
863 | SMU_DISPCLK); |
864 | if (ret) { |
865 | dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max DISPCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ) |
866 | __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max DISPCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
867 | return ret; |
868 | } |
869 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
870 | &(max_sustainable_clocks->phy_clock), |
871 | SMU_PHYCLK); |
872 | if (ret) { |
873 | dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max PHYCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ) |
874 | __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max PHYCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
875 | return ret; |
876 | } |
877 | ret = smu_v11_0_get_max_sustainable_clock(smu, |
878 | &(max_sustainable_clocks->pixel_clock), |
879 | SMU_PIXCLK); |
880 | if (ret) { |
881 | dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max PIXCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ) |
882 | __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get max PIXCLK from SMC!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
883 | return ret; |
884 | } |
885 | } |
886 | |
887 | if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock) |
888 | max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock; |
889 | |
890 | return 0; |
891 | } |
892 | |
893 | int smu_v11_0_get_current_power_limit(struct smu_context *smu, |
894 | uint32_t *power_limit) |
895 | { |
896 | int power_src; |
897 | int ret = 0; |
898 | |
899 | if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) |
900 | return -EINVAL22; |
901 | |
902 | power_src = smu_cmn_to_asic_specific_index(smu, |
903 | CMN2ASIC_MAPPING_PWR, |
904 | smu->adev->pm.ac_power ? |
905 | SMU_POWER_SOURCE_AC : |
906 | SMU_POWER_SOURCE_DC); |
907 | if (power_src < 0) |
908 | return -EINVAL22; |
909 | |
910 | ret = smu_cmn_send_smc_msg_with_param(smu, |
911 | SMU_MSG_GetPptLimit, |
912 | power_src << 16, |
913 | power_limit); |
914 | if (ret) |
915 | dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] get PPT limit failed!", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
916 | |
917 | return ret; |
918 | } |
919 | |
920 | int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n) |
921 | { |
922 | int ret = 0; |
923 | |
924 | if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) { |
925 | dev_err(smu->adev->dev, "Setting new power limit is not supported!\n")printf("drm:pid%d:%s *ERROR* " "Setting new power limit is not supported!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
926 | return -EOPNOTSUPP45; |
927 | } |
928 | |
929 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL((void *)0)); |
930 | if (ret) { |
931 | dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] Set power limit Failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
932 | return ret; |
933 | } |
934 | |
935 | smu->current_power_limit = n; |
936 | |
937 | return 0; |
938 | } |
939 | |
940 | static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu) |
941 | { |
942 | return smu_cmn_send_smc_msg(smu, |
943 | SMU_MSG_ReenableAcDcInterrupt, |
944 | NULL((void *)0)); |
945 | } |
946 | |
947 | static int smu_v11_0_process_pending_interrupt(struct smu_context *smu) |
948 | { |
949 | int ret = 0; |
950 | |
951 | if (smu->dc_controlled_by_gpio && |
952 | smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) |
953 | ret = smu_v11_0_ack_ac_dc_interrupt(smu); |
954 | |
955 | return ret; |
956 | } |
957 | |
958 | void smu_v11_0_interrupt_work(struct smu_context *smu) |
959 | { |
960 | if (smu_v11_0_ack_ac_dc_interrupt(smu)) |
961 | dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n")printf("drm:pid%d:%s *ERROR* " "Ack AC/DC interrupt Failed!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
962 | } |
963 | |
964 | int smu_v11_0_enable_thermal_alert(struct smu_context *smu) |
965 | { |
966 | int ret = 0; |
967 | |
968 | if (smu->smu_table.thermal_controller_type) { |
969 | ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0); |
970 | if (ret) |
971 | return ret; |
972 | } |
973 | |
974 | /* |
975 | * After init there might have been missed interrupts triggered |
976 | * before driver registers for interrupt (Ex. AC/DC). |
977 | */ |
978 | return smu_v11_0_process_pending_interrupt(smu); |
979 | } |
980 | |
981 | int smu_v11_0_disable_thermal_alert(struct smu_context *smu) |
982 | { |
983 | return amdgpu_irq_put(smu->adev, &smu->irq_source, 0); |
984 | } |
985 | |
986 | static uint16_t convert_to_vddc(uint8_t vid) |
987 | { |
988 | return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE4); |
989 | } |
990 | |
991 | int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value) |
992 | { |
993 | struct amdgpu_device *adev = smu->adev; |
994 | uint32_t vdd = 0, val_vid = 0; |
995 | |
996 | if (!value) |
997 | return -EINVAL22; |
998 | val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0)amdgpu_device_rreg(adev, (adev->reg_offset[SMUIO_HWIP][0][ 0] + 0x0004), 0) & |
999 | SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK0x01FF0000L) >> |
1000 | SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT0x10; |
1001 | |
1002 | vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid); |
1003 | |
1004 | *value = vdd; |
1005 | |
1006 | return 0; |
1007 | |
1008 | } |
1009 | |
1010 | int |
1011 | smu_v11_0_display_clock_voltage_request(struct smu_context *smu, |
1012 | struct pp_display_clock_request |
1013 | *clock_req) |
1014 | { |
1015 | enum amd_pp_clock_type clk_type = clock_req->clock_type; |
1016 | int ret = 0; |
1017 | enum smu_clk_type clk_select = 0; |
1018 | uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000; |
1019 | |
1020 | if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) || |
1021 | smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { |
1022 | switch (clk_type) { |
1023 | case amd_pp_dcef_clock: |
1024 | clk_select = SMU_DCEFCLK; |
1025 | break; |
1026 | case amd_pp_disp_clock: |
1027 | clk_select = SMU_DISPCLK; |
1028 | break; |
1029 | case amd_pp_pixel_clock: |
1030 | clk_select = SMU_PIXCLK; |
1031 | break; |
1032 | case amd_pp_phy_clock: |
1033 | clk_select = SMU_PHYCLK; |
1034 | break; |
1035 | case amd_pp_mem_clock: |
1036 | clk_select = SMU_UCLK; |
1037 | break; |
1038 | default: |
1039 | dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__)do { } while(0); |
1040 | ret = -EINVAL22; |
1041 | break; |
1042 | } |
1043 | |
1044 | if (ret) |
1045 | goto failed; |
1046 | |
1047 | if (clk_select == SMU_UCLK && smu->disable_uclk_switch) |
1048 | return 0; |
1049 | |
1050 | ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); |
1051 | |
1052 | if(clk_select == SMU_UCLK) |
1053 | smu->hard_min_uclk_req_from_dal = clk_freq; |
1054 | } |
1055 | |
1056 | failed: |
1057 | return ret; |
1058 | } |
1059 | |
1060 | int smu_v11_0_gfx_off_control(struct smu_context *smu, bool_Bool enable) |
1061 | { |
1062 | int ret = 0; |
1063 | struct amdgpu_device *adev = smu->adev; |
1064 | |
1065 | switch (adev->asic_type) { |
1066 | case CHIP_NAVI10: |
1067 | case CHIP_NAVI14: |
1068 | case CHIP_NAVI12: |
1069 | case CHIP_SIENNA_CICHLID: |
1070 | case CHIP_NAVY_FLOUNDER: |
1071 | if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) |
1072 | return 0; |
1073 | if (enable) |
1074 | ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL((void *)0)); |
1075 | else |
1076 | ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL((void *)0)); |
1077 | break; |
1078 | default: |
1079 | break; |
1080 | } |
1081 | |
1082 | return ret; |
1083 | } |
1084 | |
1085 | uint32_t |
1086 | smu_v11_0_get_fan_control_mode(struct smu_context *smu) |
1087 | { |
1088 | if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT)) |
1089 | return AMD_FAN_CTRL_MANUAL; |
1090 | else |
1091 | return AMD_FAN_CTRL_AUTO; |
1092 | } |
1093 | |
1094 | static int |
1095 | smu_v11_0_auto_fan_control(struct smu_context *smu, bool_Bool auto_fan_control) |
1096 | { |
1097 | int ret = 0; |
1098 | |
1099 | if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT)) |
1100 | return 0; |
1101 | |
1102 | ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control); |
1103 | if (ret) |
1104 | dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",printf("drm:pid%d:%s *ERROR* " "[%s]%s smc FAN CONTROL feature failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ , (auto_fan_control ? "Start" : "Stop")) |
1105 | __func__, (auto_fan_control ? "Start" : "Stop"))printf("drm:pid%d:%s *ERROR* " "[%s]%s smc FAN CONTROL feature failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ , (auto_fan_control ? "Start" : "Stop")); |
1106 | |
1107 | return ret; |
1108 | } |
1109 | |
1110 | static int |
1111 | smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode) |
1112 | { |
1113 | struct amdgpu_device *adev = smu->adev; |
1114 | |
1115 | WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0069)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0069), 0)) & ~0x000000FFL) | (0x000000FFL & ((0) << 0x0)))), 0) |
1116 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0069)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0069), 0)) & ~0x000000FFL) | (0x000000FFL & ((0) << 0x0)))), 0) |
1117 | CG_FDO_CTRL2, TMIN, 0))amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0069)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0069), 0)) & ~0x000000FFL) | (0x000000FFL & ((0) << 0x0)))), 0); |
1118 | WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0069)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0069), 0)) & ~0x00003800L) | (0x00003800L & ((mode) << 0xb)))), 0) |
1119 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0069)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0069), 0)) & ~0x00003800L) | (0x00003800L & ((mode) << 0xb)))), 0) |
1120 | CG_FDO_CTRL2, FDO_PWM_MODE, mode))amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0069)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0069), 0)) & ~0x00003800L) | (0x00003800L & ((mode) << 0xb)))), 0); |
1121 | |
1122 | return 0; |
1123 | } |
1124 | |
1125 | int |
1126 | smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed) |
1127 | { |
1128 | struct amdgpu_device *adev = smu->adev; |
1129 | uint32_t duty100, duty; |
1130 | uint64_t tmp64; |
1131 | |
1132 | if (speed > 100) |
1133 | speed = 100; |
1134 | |
1135 | if (smu_v11_0_auto_fan_control(smu, 0)) |
1136 | return -EINVAL22; |
1137 | |
1138 | duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),(((amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0068), 0)) & 0x000000FFL) >> 0x0) |
1139 | CG_FDO_CTRL1, FMAX_DUTY100)(((amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x0068), 0)) & 0x000000FFL) >> 0x0); |
1140 | if (!duty100) |
1141 | return -EINVAL22; |
1142 | |
1143 | tmp64 = (uint64_t)speed * duty100; |
1144 | do_div(tmp64, 100)({ uint32_t __base = (100); uint32_t __rem = ((uint64_t)(tmp64 )) % __base; (tmp64) = ((uint64_t)(tmp64)) / __base; __rem; } ); |
1145 | duty = (uint32_t)tmp64; |
1146 | |
1147 | WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0067)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0067), 0)) & ~0x000000FFL) | (0x000000FFL & ((duty) << 0x0)))), 0) |
1148 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0067)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0067), 0)) & ~0x000000FFL) | (0x000000FFL & ((duty) << 0x0)))), 0) |
1149 | CG_FDO_CTRL0, FDO_STATIC_DUTY, duty))amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0067)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x0067), 0)) & ~0x000000FFL) | (0x000000FFL & ((duty) << 0x0)))), 0); |
1150 | |
1151 | return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC1); |
1152 | } |
1153 | |
1154 | int |
1155 | smu_v11_0_set_fan_control_mode(struct smu_context *smu, |
1156 | uint32_t mode) |
1157 | { |
1158 | int ret = 0; |
1159 | |
1160 | switch (mode) { |
1161 | case AMD_FAN_CTRL_NONE: |
1162 | ret = smu_v11_0_set_fan_speed_percent(smu, 100); |
1163 | break; |
1164 | case AMD_FAN_CTRL_MANUAL: |
1165 | ret = smu_v11_0_auto_fan_control(smu, 0); |
1166 | break; |
1167 | case AMD_FAN_CTRL_AUTO: |
1168 | ret = smu_v11_0_auto_fan_control(smu, 1); |
1169 | break; |
1170 | default: |
1171 | break; |
1172 | } |
1173 | |
1174 | if (ret) { |
1175 | dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__)printf("drm:pid%d:%s *ERROR* " "[%s]Set fan control mode failed!" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
1176 | return -EINVAL22; |
1177 | } |
1178 | |
1179 | return ret; |
1180 | } |
1181 | |
1182 | int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu, |
1183 | uint32_t speed) |
1184 | { |
1185 | struct amdgpu_device *adev = smu->adev; |
1186 | int ret; |
1187 | uint32_t tach_period, crystal_clock_freq; |
1188 | |
1189 | if (!speed) |
1190 | return -EINVAL22; |
1191 | |
1192 | ret = smu_v11_0_auto_fan_control(smu, 0); |
1193 | if (ret) |
1194 | return ret; |
1195 | |
1196 | /* |
1197 | * crystal_clock_freq div by 4 is required since the fan control |
1198 | * module refers to 25MHz |
1199 | */ |
1200 | |
1201 | crystal_clock_freq = amdgpu_asic_get_xclk(adev)(adev)->asic_funcs->get_xclk((adev)) / 4; |
1202 | tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed); |
1203 | WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x006a)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x006a), 0)) & ~0xFFFFFFF8L) | (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0) |
1204 | REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x006a)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x006a), 0)) & ~0xFFFFFFF8L) | (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0) |
1205 | CG_TACH_CTRL, TARGET_PERIOD,amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x006a)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x006a), 0)) & ~0xFFFFFFF8L) | (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0) |
1206 | tach_period))amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x006a)), ((((amdgpu_device_rreg(adev, (adev->reg_offset [THM_HWIP][0][0] + 0x006a), 0)) & ~0xFFFFFFF8L) | (0xFFFFFFF8L & ((tach_period) << 0x3)))), 0); |
1207 | |
1208 | ret = smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM5); |
1209 | |
1210 | return ret; |
1211 | } |
1212 | |
1213 | int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu, |
1214 | uint32_t *speed) |
1215 | { |
1216 | struct amdgpu_device *adev = smu->adev; |
1217 | uint32_t tach_period, crystal_clock_freq; |
1218 | uint64_t tmp64; |
1219 | |
1220 | tach_period = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),(((amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x006a), 0)) & 0xFFFFFFF8L) >> 0x3) |
1221 | CG_TACH_CTRL, TARGET_PERIOD)(((amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0] [0] + 0x006a), 0)) & 0xFFFFFFF8L) >> 0x3); |
1222 | if (!tach_period) |
1223 | return -EINVAL22; |
1224 | |
1225 | crystal_clock_freq = amdgpu_asic_get_xclk(adev)(adev)->asic_funcs->get_xclk((adev)); |
1226 | |
1227 | tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000; |
1228 | do_div(tmp64, (tach_period * 8))({ uint32_t __base = ((tach_period * 8)); uint32_t __rem = (( uint64_t)(tmp64)) % __base; (tmp64) = ((uint64_t)(tmp64)) / __base ; __rem; }); |
1229 | *speed = (uint32_t)tmp64; |
1230 | |
1231 | return 0; |
1232 | } |
1233 | |
1234 | int smu_v11_0_set_xgmi_pstate(struct smu_context *smu, |
1235 | uint32_t pstate) |
1236 | { |
1237 | return smu_cmn_send_smc_msg_with_param(smu, |
1238 | SMU_MSG_SetXgmiMode, |
1239 | pstate ? XGMI_MODE_PSTATE_D01 : XGMI_MODE_PSTATE_D30, |
1240 | NULL((void *)0)); |
1241 | } |
1242 | |
1243 | static int smu_v11_0_set_irq_state(struct amdgpu_device *adev, |
1244 | struct amdgpu_irq_src *source, |
1245 | unsigned tyep, |
1246 | enum amdgpu_interrupt_state state) |
1247 | { |
1248 | struct smu_context *smu = &adev->smu; |
1249 | uint32_t low, high; |
1250 | uint32_t val = 0; |
1251 | |
1252 | switch (state) { |
1253 | case AMDGPU_IRQ_STATE_DISABLE: |
1254 | /* For THM irqs */ |
1255 | val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0][0] + 0x000b), 0); |
1256 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1)(((val) & ~0x01000000L) | (0x01000000L & ((1) << 0x18))); |
1257 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1)(((val) & ~0x02000000L) | (0x02000000L & ((1) << 0x19))); |
1258 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val)amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x000b)), (val), 0); |
1259 | |
1260 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0)amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x000a)), (0), 0); |
1261 | |
1262 | /* For MP1 SW irqs */ |
1263 | val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[MP1_HWIP][0][0] + 0x02c3), 0); |
1264 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1)(((val) & ~0x00000001L) | (0x00000001L & ((1) << 0x0))); |
1265 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val)amdgpu_device_wreg(adev, ((adev->reg_offset[MP1_HWIP][0][0 ] + 0x02c3)), (val), 0); |
1266 | |
1267 | break; |
1268 | case AMDGPU_IRQ_STATE_ENABLE: |
1269 | /* For THM irqs */ |
1270 | low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,(((0)>(smu->thermal_range.min / 1000))?(0):(smu->thermal_range .min / 1000)) |
1271 | smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES)(((0)>(smu->thermal_range.min / 1000))?(0):(smu->thermal_range .min / 1000)); |
1272 | high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,(((255)<(smu->thermal_range.software_shutdown_temp))?(255 ):(smu->thermal_range.software_shutdown_temp)) |
1273 | smu->thermal_range.software_shutdown_temp)(((255)<(smu->thermal_range.software_shutdown_temp))?(255 ):(smu->thermal_range.software_shutdown_temp)); |
1274 | |
1275 | val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0][0] + 0x000b), 0); |
1276 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5)(((val) & ~0xE0000000L) | (0xE0000000L & ((5) << 0x1d))); |
1277 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1)(((val) & ~0x10000000L) | (0x10000000L & ((1) << 0x1c))); |
1278 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0)(((val) & ~0x01000000L) | (0x01000000L & ((0) << 0x18))); |
1279 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0)(((val) & ~0x02000000L) | (0x02000000L & ((0) << 0x19))); |
1280 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff))(((val) & ~0x000000FFL) | (0x000000FFL & (((high & 0xff)) << 0x0))); |
1281 | val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff))(((val) & ~0x0000FF00L) | (0x0000FF00L & (((low & 0xff)) << 0x8))); |
1282 | val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK0x04000000L); |
1283 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val)amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x000b)), (val), 0); |
1284 | |
1285 | val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT0x3); |
1286 | val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT0x4); |
1287 | val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT0x5); |
1288 | WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val)amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x000a)), (val), 0); |
1289 | |
1290 | /* For MP1 SW irqs */ |
1291 | val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT)amdgpu_device_rreg(adev, (adev->reg_offset[MP1_HWIP][0][0] + 0x02c2), 0); |
1292 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE)(((val) & ~0x000000FFL) | (0x000000FFL & ((0xFE) << 0x0))); |
1293 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0)(((val) & ~0x00000100L) | (0x00000100L & ((0) << 0x8))); |
1294 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val)amdgpu_device_wreg(adev, ((adev->reg_offset[MP1_HWIP][0][0 ] + 0x02c2)), (val), 0); |
1295 | |
1296 | val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[MP1_HWIP][0][0] + 0x02c3), 0); |
1297 | val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0)(((val) & ~0x00000001L) | (0x00000001L & ((0) << 0x0))); |
1298 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val)amdgpu_device_wreg(adev, ((adev->reg_offset[MP1_HWIP][0][0 ] + 0x02c3)), (val), 0); |
1299 | |
1300 | break; |
1301 | default: |
1302 | break; |
1303 | } |
1304 | |
1305 | return 0; |
1306 | } |
1307 | |
1308 | #define THM_11_0__SRCID__THM_DIG_THERM_L2H0 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */ |
1309 | #define THM_11_0__SRCID__THM_DIG_THERM_H2L1 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */ |
1310 | |
1311 | #define SMUIO_11_0__SRCID__SMUIO_GPIO1983 83 |
1312 | |
1313 | static int smu_v11_0_irq_process(struct amdgpu_device *adev, |
1314 | struct amdgpu_irq_src *source, |
1315 | struct amdgpu_iv_entry *entry) |
1316 | { |
1317 | struct smu_context *smu = &adev->smu; |
1318 | uint32_t client_id = entry->client_id; |
1319 | uint32_t src_id = entry->src_id; |
1320 | /* |
1321 | * ctxid is used to distinguish different |
1322 | * events for SMCToHost interrupt. |
1323 | */ |
1324 | uint32_t ctxid = entry->src_data[0]; |
1325 | uint32_t data; |
1326 | |
1327 | if (client_id == SOC15_IH_CLIENTID_THM) { |
1328 | switch (src_id) { |
1329 | case THM_11_0__SRCID__THM_DIG_THERM_L2H0: |
1330 | dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU over temperature range(SW CTF) detected!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1331 | /* |
1332 | * SW CTF just occurred. |
1333 | * Try to do a graceful shutdown to prevent further damage. |
1334 | */ |
1335 | dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: System is going to shutdown due to GPU SW CTF!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1336 | orderly_poweroff(true1); |
1337 | break; |
1338 | case THM_11_0__SRCID__THM_DIG_THERM_H2L1: |
1339 | dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU under temperature range detected\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1340 | break; |
1341 | default: |
1342 | dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU under temperature range unknown src id (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , src_id ) |
1343 | src_id)printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU under temperature range unknown src id (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , src_id ); |
1344 | break; |
1345 | } |
1346 | } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) { |
1347 | dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1348 | /* |
1349 | * HW CTF just occurred. Shutdown to prevent further damage. |
1350 | */ |
1351 | dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: System is going to shutdown due to GPU HW CTF!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1352 | orderly_poweroff(true1); |
1353 | } else if (client_id == SOC15_IH_CLIENTID_MP1) { |
1354 | if (src_id == 0xfe) { |
1355 | /* ACK SMUToHost interrupt */ |
1356 | data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL)amdgpu_device_rreg(adev, (adev->reg_offset[MP1_HWIP][0][0] + 0x02c3), 0); |
1357 | data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1)(((data) & ~0x00000100L) | (0x00000100L & ((1) << 0x8))); |
1358 | WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[MP1_HWIP][0][0 ] + 0x02c3)), (data), 0); |
1359 | |
1360 | switch (ctxid) { |
1361 | case 0x3: |
1362 | dev_dbg(adev->dev, "Switched to AC mode!\n")do { } while(0); |
1363 | schedule_work(&smu->interrupt_work); |
1364 | break; |
1365 | case 0x4: |
1366 | dev_dbg(adev->dev, "Switched to DC mode!\n")do { } while(0); |
1367 | schedule_work(&smu->interrupt_work); |
1368 | break; |
1369 | case 0x7: |
1370 | /* |
1371 | * Increment the throttle interrupt counter |
1372 | */ |
1373 | atomic64_inc(&smu->throttle_int_counter)__sync_fetch_and_add_8(&smu->throttle_int_counter, 1); |
1374 | |
1375 | if (!atomic_read(&adev->throttling_logging_enabled)({ typeof(*(&adev->throttling_logging_enabled)) __tmp = *(volatile typeof(*(&adev->throttling_logging_enabled )) *)&(*(&adev->throttling_logging_enabled)); membar_datadep_consumer (); __tmp; })) |
1376 | return 0; |
1377 | |
1378 | if (__ratelimit(&adev->throttling_logging_rs)(1)) |
1379 | schedule_work(&smu->throttling_logging_work); |
1380 | |
1381 | break; |
1382 | } |
1383 | } |
1384 | } |
1385 | |
1386 | return 0; |
1387 | } |
1388 | |
1389 | static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs = |
1390 | { |
1391 | .set = smu_v11_0_set_irq_state, |
1392 | .process = smu_v11_0_irq_process, |
1393 | }; |
1394 | |
1395 | int smu_v11_0_register_irq_handler(struct smu_context *smu) |
1396 | { |
1397 | struct amdgpu_device *adev = smu->adev; |
1398 | struct amdgpu_irq_src *irq_src = &smu->irq_source; |
1399 | int ret = 0; |
1400 | |
1401 | irq_src->num_types = 1; |
1402 | irq_src->funcs = &smu_v11_0_irq_funcs; |
1403 | |
1404 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, |
1405 | THM_11_0__SRCID__THM_DIG_THERM_L2H0, |
1406 | irq_src); |
1407 | if (ret) |
1408 | return ret; |
1409 | |
1410 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM, |
1411 | THM_11_0__SRCID__THM_DIG_THERM_H2L1, |
1412 | irq_src); |
1413 | if (ret) |
1414 | return ret; |
1415 | |
1416 | /* Register CTF(GPIO_19) interrupt */ |
1417 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO, |
1418 | SMUIO_11_0__SRCID__SMUIO_GPIO1983, |
1419 | irq_src); |
1420 | if (ret) |
1421 | return ret; |
1422 | |
1423 | ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1, |
1424 | 0xfe, |
1425 | irq_src); |
1426 | if (ret) |
1427 | return ret; |
1428 | |
1429 | return ret; |
1430 | } |
1431 | |
1432 | int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu, |
1433 | struct pp_smu_nv_clock_table *max_clocks) |
1434 | { |
1435 | struct smu_table_context *table_context = &smu->smu_table; |
1436 | struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL((void *)0); |
1437 | |
1438 | if (!max_clocks || !table_context->max_sustainable_clocks) |
1439 | return -EINVAL22; |
1440 | |
1441 | sustainable_clocks = table_context->max_sustainable_clocks; |
1442 | |
1443 | max_clocks->dcfClockInKhz = |
1444 | (unsigned int) sustainable_clocks->dcef_clock * 1000; |
1445 | max_clocks->displayClockInKhz = |
1446 | (unsigned int) sustainable_clocks->display_clock * 1000; |
1447 | max_clocks->phyClockInKhz = |
1448 | (unsigned int) sustainable_clocks->phy_clock * 1000; |
1449 | max_clocks->pixelClockInKhz = |
1450 | (unsigned int) sustainable_clocks->pixel_clock * 1000; |
1451 | max_clocks->uClockInKhz = |
1452 | (unsigned int) sustainable_clocks->uclock * 1000; |
1453 | max_clocks->socClockInKhz = |
1454 | (unsigned int) sustainable_clocks->soc_clock * 1000; |
1455 | max_clocks->dscClockInKhz = 0; |
1456 | max_clocks->dppClockInKhz = 0; |
1457 | max_clocks->fabricClockInKhz = 0; |
1458 | |
1459 | return 0; |
1460 | } |
1461 | |
1462 | int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu) |
1463 | { |
1464 | return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL((void *)0)); |
1465 | } |
1466 | |
1467 | static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq) |
1468 | { |
1469 | return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL((void *)0)); |
1470 | } |
1471 | |
1472 | bool_Bool smu_v11_0_baco_is_support(struct smu_context *smu) |
1473 | { |
1474 | struct smu_baco_context *smu_baco = &smu->smu_baco; |
1475 | |
1476 | if (!smu_baco->platform_support) |
1477 | return false0; |
1478 | |
1479 | /* Arcturus does not support this bit mask */ |
1480 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) && |
1481 | !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) |
1482 | return false0; |
1483 | |
1484 | return true1; |
1485 | } |
1486 | |
1487 | enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu) |
1488 | { |
1489 | struct smu_baco_context *smu_baco = &smu->smu_baco; |
1490 | enum smu_baco_state baco_state; |
1491 | |
1492 | mutex_lock(&smu_baco->mutex)rw_enter_write(&smu_baco->mutex); |
1493 | baco_state = smu_baco->state; |
1494 | mutex_unlock(&smu_baco->mutex)rw_exit_write(&smu_baco->mutex); |
1495 | |
1496 | return baco_state; |
1497 | } |
1498 | |
1499 | int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) |
1500 | { |
1501 | struct smu_baco_context *smu_baco = &smu->smu_baco; |
1502 | struct amdgpu_device *adev = smu->adev; |
1503 | struct amdgpu_ras *ras = amdgpu_ras_get_context(adev)((adev)->psp.ras.ras); |
1504 | uint32_t data; |
1505 | int ret = 0; |
1506 | |
1507 | if (smu_v11_0_baco_get_state(smu) == state) |
1508 | return 0; |
1509 | |
1510 | mutex_lock(&smu_baco->mutex)rw_enter_write(&smu_baco->mutex); |
1511 | |
1512 | if (state == SMU_BACO_STATE_ENTER) { |
1513 | if (!ras || !ras->supported) { |
1514 | data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL)amdgpu_device_rreg(adev, (adev->reg_offset[THM_HWIP][0][0] + 0x0081), 0); |
1515 | data |= 0x80000000; |
1516 | WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data)amdgpu_device_wreg(adev, ((adev->reg_offset[THM_HWIP][0][0 ] + 0x0081)), (data), 0); |
1517 | |
1518 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL((void *)0)); |
1519 | } else { |
1520 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL((void *)0)); |
1521 | } |
1522 | } else { |
1523 | ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL((void *)0)); |
1524 | if (ret) |
1525 | goto out; |
1526 | |
1527 | /* clear vbios scratch 6 and 7 for coming asic reinit */ |
1528 | WREG32(adev->bios_scratch_reg_offset + 6, 0)amdgpu_device_wreg(adev, (adev->bios_scratch_reg_offset + 6 ), (0), 0); |
1529 | WREG32(adev->bios_scratch_reg_offset + 7, 0)amdgpu_device_wreg(adev, (adev->bios_scratch_reg_offset + 7 ), (0), 0); |
1530 | } |
1531 | if (ret) |
1532 | goto out; |
1533 | |
1534 | smu_baco->state = state; |
1535 | out: |
1536 | mutex_unlock(&smu_baco->mutex)rw_exit_write(&smu_baco->mutex); |
1537 | return ret; |
1538 | } |
1539 | |
1540 | int smu_v11_0_baco_enter(struct smu_context *smu) |
1541 | { |
1542 | struct amdgpu_device *adev = smu->adev; |
1543 | int ret = 0; |
1544 | |
1545 | /* Arcturus does not need this audio workaround */ |
1546 | if (adev->asic_type != CHIP_ARCTURUS) { |
1547 | ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO); |
1548 | if (ret) |
1549 | return ret; |
1550 | } |
1551 | |
1552 | ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER); |
1553 | if (ret) |
1554 | return ret; |
1555 | |
1556 | drm_msleep(10)mdelay(10); |
1557 | |
1558 | return ret; |
1559 | } |
1560 | |
1561 | int smu_v11_0_baco_exit(struct smu_context *smu) |
1562 | { |
1563 | return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT); |
1564 | } |
1565 | |
1566 | int smu_v11_0_mode1_reset(struct smu_context *smu) |
1567 | { |
1568 | int ret = 0; |
1569 | |
1570 | ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL((void *)0)); |
1571 | if (!ret) |
1572 | drm_msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS)mdelay(500); |
1573 | |
1574 | return ret; |
1575 | } |
1576 | |
1577 | int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, |
1578 | uint32_t *min, uint32_t *max) |
1579 | { |
1580 | int ret = 0, clk_id = 0; |
1581 | uint32_t param = 0; |
1582 | uint32_t clock_limit; |
1583 | |
1584 | if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) { |
1585 | switch (clk_type) { |
1586 | case SMU_MCLK: |
1587 | case SMU_UCLK: |
1588 | clock_limit = smu->smu_table.boot_values.uclk; |
1589 | break; |
1590 | case SMU_GFXCLK: |
1591 | case SMU_SCLK: |
1592 | clock_limit = smu->smu_table.boot_values.gfxclk; |
1593 | break; |
1594 | case SMU_SOCCLK: |
1595 | clock_limit = smu->smu_table.boot_values.socclk; |
1596 | break; |
1597 | default: |
1598 | clock_limit = 0; |
1599 | break; |
1600 | } |
1601 | |
1602 | /* clock in Mhz unit */ |
1603 | if (min) |
1604 | *min = clock_limit / 100; |
1605 | if (max) |
1606 | *max = clock_limit / 100; |
1607 | |
1608 | return 0; |
1609 | } |
1610 | |
1611 | clk_id = smu_cmn_to_asic_specific_index(smu, |
1612 | CMN2ASIC_MAPPING_CLK, |
1613 | clk_type); |
1614 | if (clk_id < 0) { |
1615 | ret = -EINVAL22; |
1616 | goto failed; |
1617 | } |
1618 | param = (clk_id & 0xffff) << 16; |
1619 | |
1620 | if (max) { |
1621 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max); |
1622 | if (ret) |
1623 | goto failed; |
1624 | } |
1625 | |
1626 | if (min) { |
1627 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min); |
1628 | if (ret) |
1629 | goto failed; |
1630 | } |
1631 | |
1632 | failed: |
1633 | return ret; |
1634 | } |
1635 | |
1636 | int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, |
1637 | enum smu_clk_type clk_type, |
1638 | uint32_t min, |
1639 | uint32_t max) |
1640 | { |
1641 | struct amdgpu_device *adev = smu->adev; |
1642 | int ret = 0, clk_id = 0; |
1643 | uint32_t param; |
1644 | |
1645 | if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) |
1646 | return 0; |
1647 | |
1648 | clk_id = smu_cmn_to_asic_specific_index(smu, |
1649 | CMN2ASIC_MAPPING_CLK, |
1650 | clk_type); |
1651 | if (clk_id < 0) |
1652 | return clk_id; |
1653 | |
1654 | if (clk_type == SMU_GFXCLK) |
1655 | amdgpu_gfx_off_ctrl(adev, false0); |
1656 | |
1657 | if (max > 0) { |
1658 | param = (uint32_t)((clk_id << 16) | (max & 0xffff)); |
1659 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq, |
1660 | param, NULL((void *)0)); |
1661 | if (ret) |
1662 | goto out; |
1663 | } |
1664 | |
1665 | if (min > 0) { |
1666 | param = (uint32_t)((clk_id << 16) | (min & 0xffff)); |
1667 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq, |
1668 | param, NULL((void *)0)); |
1669 | if (ret) |
1670 | goto out; |
1671 | } |
1672 | |
1673 | out: |
1674 | if (clk_type == SMU_GFXCLK) |
1675 | amdgpu_gfx_off_ctrl(adev, true1); |
1676 | |
1677 | return ret; |
1678 | } |
1679 | |
1680 | int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu, |
1681 | enum smu_clk_type clk_type, |
1682 | uint32_t min, |
1683 | uint32_t max) |
1684 | { |
1685 | int ret = 0, clk_id = 0; |
1686 | uint32_t param; |
1687 | |
1688 | if (min <= 0 && max <= 0) |
1689 | return -EINVAL22; |
1690 | |
1691 | if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) |
1692 | return 0; |
1693 | |
1694 | clk_id = smu_cmn_to_asic_specific_index(smu, |
1695 | CMN2ASIC_MAPPING_CLK, |
1696 | clk_type); |
1697 | if (clk_id < 0) |
1698 | return clk_id; |
1699 | |
1700 | if (max > 0) { |
1701 | param = (uint32_t)((clk_id << 16) | (max & 0xffff)); |
1702 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq, |
1703 | param, NULL((void *)0)); |
1704 | if (ret) |
1705 | return ret; |
1706 | } |
1707 | |
1708 | if (min > 0) { |
1709 | param = (uint32_t)((clk_id << 16) | (min & 0xffff)); |
1710 | ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq, |
1711 | param, NULL((void *)0)); |
1712 | if (ret) |
1713 | return ret; |
1714 | } |
1715 | |
1716 | return ret; |
1717 | } |
1718 | |
1719 | int smu_v11_0_set_performance_level(struct smu_context *smu, |
1720 | enum amd_dpm_forced_level level) |
1721 | { |
1722 | struct smu_11_0_dpm_context *dpm_context = |
1723 | smu->smu_dpm.dpm_context; |
1724 | struct smu_11_0_dpm_table *gfx_table = |
1725 | &dpm_context->dpm_tables.gfx_table; |
1726 | struct smu_11_0_dpm_table *mem_table = |
1727 | &dpm_context->dpm_tables.uclk_table; |
1728 | struct smu_11_0_dpm_table *soc_table = |
1729 | &dpm_context->dpm_tables.soc_table; |
1730 | struct smu_umd_pstate_table *pstate_table = |
1731 | &smu->pstate_table; |
1732 | struct amdgpu_device *adev = smu->adev; |
1733 | uint32_t sclk_min = 0, sclk_max = 0; |
1734 | uint32_t mclk_min = 0, mclk_max = 0; |
1735 | uint32_t socclk_min = 0, socclk_max = 0; |
1736 | int ret = 0; |
1737 | |
1738 | switch (level) { |
1739 | case AMD_DPM_FORCED_LEVEL_HIGH: |
1740 | sclk_min = sclk_max = gfx_table->max; |
1741 | mclk_min = mclk_max = mem_table->max; |
1742 | socclk_min = socclk_max = soc_table->max; |
1743 | break; |
1744 | case AMD_DPM_FORCED_LEVEL_LOW: |
1745 | sclk_min = sclk_max = gfx_table->min; |
1746 | mclk_min = mclk_max = mem_table->min; |
1747 | socclk_min = socclk_max = soc_table->min; |
1748 | break; |
1749 | case AMD_DPM_FORCED_LEVEL_AUTO: |
1750 | sclk_min = gfx_table->min; |
1751 | sclk_max = gfx_table->max; |
1752 | mclk_min = mem_table->min; |
1753 | mclk_max = mem_table->max; |
1754 | socclk_min = soc_table->min; |
1755 | socclk_max = soc_table->max; |
1756 | break; |
1757 | case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: |
1758 | sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard; |
1759 | mclk_min = mclk_max = pstate_table->uclk_pstate.standard; |
1760 | socclk_min = socclk_max = pstate_table->socclk_pstate.standard; |
1761 | break; |
1762 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: |
1763 | sclk_min = sclk_max = pstate_table->gfxclk_pstate.min; |
1764 | break; |
1765 | case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: |
1766 | mclk_min = mclk_max = pstate_table->uclk_pstate.min; |
1767 | break; |
1768 | case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: |
1769 | sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak; |
1770 | mclk_min = mclk_max = pstate_table->uclk_pstate.peak; |
1771 | socclk_min = socclk_max = pstate_table->socclk_pstate.peak; |
1772 | break; |
1773 | case AMD_DPM_FORCED_LEVEL_MANUAL: |
1774 | case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: |
1775 | return 0; |
1776 | default: |
1777 | dev_err(adev->dev, "Invalid performance level %d\n", level)printf("drm:pid%d:%s *ERROR* " "Invalid performance level %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , level); |
1778 | return -EINVAL22; |
1779 | } |
1780 | |
1781 | /* |
1782 | * Separate MCLK and SOCCLK soft min/max settings are not allowed |
1783 | * on Arcturus. |
1784 | */ |
1785 | if (adev->asic_type == CHIP_ARCTURUS) { |
1786 | mclk_min = mclk_max = 0; |
1787 | socclk_min = socclk_max = 0; |
1788 | } |
1789 | |
1790 | if (sclk_min && sclk_max) { |
1791 | ret = smu_v11_0_set_soft_freq_limited_range(smu, |
1792 | SMU_GFXCLK, |
1793 | sclk_min, |
1794 | sclk_max); |
1795 | if (ret) |
1796 | return ret; |
1797 | } |
1798 | |
1799 | if (mclk_min && mclk_max) { |
1800 | ret = smu_v11_0_set_soft_freq_limited_range(smu, |
1801 | SMU_MCLK, |
1802 | mclk_min, |
1803 | mclk_max); |
1804 | if (ret) |
1805 | return ret; |
1806 | } |
1807 | |
1808 | if (socclk_min && socclk_max) { |
1809 | ret = smu_v11_0_set_soft_freq_limited_range(smu, |
1810 | SMU_SOCCLK, |
1811 | socclk_min, |
1812 | socclk_max); |
1813 | if (ret) |
1814 | return ret; |
1815 | } |
1816 | |
1817 | return ret; |
1818 | } |
1819 | |
1820 | int smu_v11_0_set_power_source(struct smu_context *smu, |
1821 | enum smu_power_src_type power_src) |
1822 | { |
1823 | int pwr_source; |
1824 | |
1825 | pwr_source = smu_cmn_to_asic_specific_index(smu, |
1826 | CMN2ASIC_MAPPING_PWR, |
1827 | (uint32_t)power_src); |
1828 | if (pwr_source < 0) |
1829 | return -EINVAL22; |
1830 | |
1831 | return smu_cmn_send_smc_msg_with_param(smu, |
1832 | SMU_MSG_NotifyPowerSource, |
1833 | pwr_source, |
1834 | NULL((void *)0)); |
1835 | } |
1836 | |
1837 | int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu, |
1838 | enum smu_clk_type clk_type, |
1839 | uint16_t level, |
1840 | uint32_t *value) |
1841 | { |
1842 | int ret = 0, clk_id = 0; |
1843 | uint32_t param; |
1844 | |
1845 | if (!value) |
1846 | return -EINVAL22; |
1847 | |
1848 | if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) |
1849 | return 0; |
1850 | |
1851 | clk_id = smu_cmn_to_asic_specific_index(smu, |
1852 | CMN2ASIC_MAPPING_CLK, |
1853 | clk_type); |
1854 | if (clk_id < 0) |
1855 | return clk_id; |
1856 | |
1857 | param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff)); |
1858 | |
1859 | ret = smu_cmn_send_smc_msg_with_param(smu, |
1860 | SMU_MSG_GetDpmFreqByIndex, |
1861 | param, |
1862 | value); |
1863 | if (ret) |
1864 | return ret; |
1865 | |
1866 | /* |
1867 | * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM |
1868 | * now, we un-support it |
1869 | */ |
1870 | *value = *value & 0x7fffffff; |
1871 | |
1872 | return ret; |
1873 | } |
1874 | |
1875 | int smu_v11_0_get_dpm_level_count(struct smu_context *smu, |
1876 | enum smu_clk_type clk_type, |
1877 | uint32_t *value) |
1878 | { |
1879 | return smu_v11_0_get_dpm_freq_by_index(smu, |
1880 | clk_type, |
1881 | 0xff, |
1882 | value); |
1883 | } |
1884 | |
1885 | int smu_v11_0_set_single_dpm_table(struct smu_context *smu, |
1886 | enum smu_clk_type clk_type, |
1887 | struct smu_11_0_dpm_table *single_dpm_table) |
1888 | { |
1889 | int ret = 0; |
1890 | uint32_t clk; |
1891 | int i; |
1892 | |
1893 | ret = smu_v11_0_get_dpm_level_count(smu, |
1894 | clk_type, |
1895 | &single_dpm_table->count); |
1896 | if (ret) { |
1897 | dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get dpm levels!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
1898 | return ret; |
1899 | } |
1900 | |
1901 | for (i = 0; i < single_dpm_table->count; i++) { |
1902 | ret = smu_v11_0_get_dpm_freq_by_index(smu, |
1903 | clk_type, |
1904 | i, |
1905 | &clk); |
1906 | if (ret) { |
1907 | dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__)printf("drm:pid%d:%s *ERROR* " "[%s] failed to get dpm freq by index!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , __func__ ); |
1908 | return ret; |
1909 | } |
1910 | |
1911 | single_dpm_table->dpm_levels[i].value = clk; |
1912 | single_dpm_table->dpm_levels[i].enabled = true1; |
1913 | |
1914 | if (i == 0) |
1915 | single_dpm_table->min = clk; |
1916 | else if (i == single_dpm_table->count - 1) |
1917 | single_dpm_table->max = clk; |
1918 | } |
1919 | |
1920 | return 0; |
1921 | } |
1922 | |
1923 | int smu_v11_0_get_dpm_level_range(struct smu_context *smu, |
1924 | enum smu_clk_type clk_type, |
1925 | uint32_t *min_value, |
1926 | uint32_t *max_value) |
1927 | { |
1928 | uint32_t level_count = 0; |
1929 | int ret = 0; |
1930 | |
1931 | if (!min_value && !max_value) |
1932 | return -EINVAL22; |
1933 | |
1934 | if (min_value) { |
1935 | /* by default, level 0 clock value as min value */ |
1936 | ret = smu_v11_0_get_dpm_freq_by_index(smu, |
1937 | clk_type, |
1938 | 0, |
1939 | min_value); |
1940 | if (ret) |
1941 | return ret; |
1942 | } |
1943 | |
1944 | if (max_value) { |
1945 | ret = smu_v11_0_get_dpm_level_count(smu, |
1946 | clk_type, |
1947 | &level_count); |
1948 | if (ret) |
1949 | return ret; |
1950 | |
1951 | ret = smu_v11_0_get_dpm_freq_by_index(smu, |
1952 | clk_type, |
1953 | level_count - 1, |
1954 | max_value); |
1955 | if (ret) |
1956 | return ret; |
1957 | } |
1958 | |
1959 | return ret; |
1960 | } |
1961 | |
1962 | int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu) |
1963 | { |
1964 | struct amdgpu_device *adev = smu->adev; |
1965 | |
1966 | return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL)adev->pcie_rreg(adev, (0x11140288)) & |
1967 | PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK0x00000070L) |
1968 | >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT0x4; |
1969 | } |
1970 | |
1971 | int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu) |
1972 | { |
1973 | uint32_t width_level; |
1974 | |
1975 | width_level = smu_v11_0_get_current_pcie_link_width_level(smu); |
1976 | if (width_level > LINK_WIDTH_MAX6) |
1977 | width_level = 0; |
1978 | |
1979 | return link_width[width_level]; |
1980 | } |
1981 | |
1982 | int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu) |
1983 | { |
1984 | struct amdgpu_device *adev = smu->adev; |
1985 | |
1986 | return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL)adev->pcie_rreg(adev, (0x11140290)) & |
1987 | PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK0xC000) |
1988 | >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT0xE; |
1989 | } |
1990 | |
1991 | int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu) |
1992 | { |
1993 | uint32_t speed_level; |
1994 | |
1995 | speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu); |
1996 | if (speed_level > LINK_SPEED_MAX3) |
1997 | speed_level = 0; |
1998 | |
1999 | return link_speed[speed_level]; |
2000 | } |
2001 | |
2002 | void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics) |
2003 | { |
2004 | memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0))__builtin_memset((gpu_metrics), (0xFF), (sizeof(struct gpu_metrics_v1_0 ))); |
2005 | |
2006 | gpu_metrics->common_header.structure_size = |
2007 | sizeof(struct gpu_metrics_v1_0); |
2008 | gpu_metrics->common_header.format_revision = 1; |
2009 | gpu_metrics->common_header.content_revision = 0; |
2010 | |
2011 | gpu_metrics->system_clock_counter = ktime_get_boottime_ns()ktime_get_ns(); |
2012 | } |
2013 | |
2014 | int smu_v11_0_gfx_ulv_control(struct smu_context *smu, |
2015 | bool_Bool enablement) |
2016 | { |
2017 | int ret = 0; |
2018 | |
2019 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT)) |
2020 | ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement); |
2021 | |
2022 | return ret; |
2023 | } |
2024 | |
2025 | int smu_v11_0_deep_sleep_control(struct smu_context *smu, |
2026 | bool_Bool enablement) |
2027 | { |
2028 | struct amdgpu_device *adev = smu->adev; |
2029 | int ret = 0; |
2030 | |
2031 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) { |
2032 | ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement); |
2033 | if (ret) { |
2034 | dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s *ERROR* " "Failed to %s GFXCLK DS!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable"); |
2035 | return ret; |
2036 | } |
2037 | } |
2038 | |
2039 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) { |
2040 | ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement); |
2041 | if (ret) { |
2042 | dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s *ERROR* " "Failed to %s SOCCLK DS!\n", ( {struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable"); |
2043 | return ret; |
2044 | } |
2045 | } |
2046 | |
2047 | if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) { |
2048 | ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement); |
2049 | if (ret) { |
2050 | dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable")printf("drm:pid%d:%s *ERROR* " "Failed to %s LCLK DS!\n", ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci ) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci; })->ci_curproc->p_p->ps_pid, __func__ , enablement ? "enable" : "disable"); |
2051 | return ret; |
2052 | } |
2053 | } |
2054 | |
2055 | return ret; |
2056 | } |