File: | dev/pci/drm/radeon/rv740_dpm.c |
Warning: | line 253, column 36 Division by zero |
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1 | /* | |||
2 | * Copyright 2011 Advanced Micro Devices, Inc. | |||
3 | * | |||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |||
5 | * copy of this software and associated documentation files (the "Software"), | |||
6 | * to deal in the Software without restriction, including without limitation | |||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |||
8 | * and/or sell copies of the Software, and to permit persons to whom the | |||
9 | * Software is furnished to do so, subject to the following conditions: | |||
10 | * | |||
11 | * The above copyright notice and this permission notice shall be included in | |||
12 | * all copies or substantial portions of the Software. | |||
13 | * | |||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |||
20 | * OTHER DEALINGS IN THE SOFTWARE. | |||
21 | * | |||
22 | * Authors: Alex Deucher | |||
23 | */ | |||
24 | ||||
25 | #include "radeon.h" | |||
26 | #include "rv740d.h" | |||
27 | #include "r600_dpm.h" | |||
28 | #include "rv770_dpm.h" | |||
29 | #include "atom.h" | |||
30 | ||||
31 | struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); | |||
32 | ||||
33 | u32 rv740_get_decoded_reference_divider(u32 encoded_ref) | |||
34 | { | |||
35 | u32 ref = 0; | |||
36 | ||||
37 | switch (encoded_ref) { | |||
38 | case 0: | |||
39 | ref = 1; | |||
40 | break; | |||
41 | case 16: | |||
42 | ref = 2; | |||
43 | break; | |||
44 | case 17: | |||
45 | ref = 3; | |||
46 | break; | |||
47 | case 18: | |||
48 | ref = 2; | |||
49 | break; | |||
50 | case 19: | |||
51 | ref = 3; | |||
52 | break; | |||
53 | case 20: | |||
54 | ref = 4; | |||
55 | break; | |||
56 | case 21: | |||
57 | ref = 5; | |||
58 | break; | |||
59 | default: | |||
60 | DRM_ERROR("Invalid encoded Reference Divider\n")__drm_err("Invalid encoded Reference Divider\n"); | |||
61 | ref = 0; | |||
62 | break; | |||
63 | } | |||
64 | ||||
65 | return ref; | |||
66 | } | |||
67 | ||||
68 | struct dll_speed_setting { | |||
69 | u16 min; | |||
70 | u16 max; | |||
71 | u32 dll_speed; | |||
72 | }; | |||
73 | ||||
74 | static struct dll_speed_setting dll_speed_table[16] = | |||
75 | { | |||
76 | { 270, 320, 0x0f }, | |||
77 | { 240, 270, 0x0e }, | |||
78 | { 200, 240, 0x0d }, | |||
79 | { 180, 200, 0x0c }, | |||
80 | { 160, 180, 0x0b }, | |||
81 | { 140, 160, 0x0a }, | |||
82 | { 120, 140, 0x09 }, | |||
83 | { 110, 120, 0x08 }, | |||
84 | { 95, 110, 0x07 }, | |||
85 | { 85, 95, 0x06 }, | |||
86 | { 78, 85, 0x05 }, | |||
87 | { 70, 78, 0x04 }, | |||
88 | { 65, 70, 0x03 }, | |||
89 | { 60, 65, 0x02 }, | |||
90 | { 42, 60, 0x01 }, | |||
91 | { 00, 42, 0x00 } | |||
92 | }; | |||
93 | ||||
94 | u32 rv740_get_dll_speed(bool_Bool is_gddr5, u32 memory_clock) | |||
95 | { | |||
96 | int i; | |||
97 | u32 factor; | |||
98 | u16 data_rate; | |||
99 | ||||
100 | if (is_gddr5) | |||
101 | factor = 4; | |||
102 | else | |||
103 | factor = 2; | |||
104 | ||||
105 | data_rate = (u16)(memory_clock * factor / 1000); | |||
106 | ||||
107 | if (data_rate < dll_speed_table[0].max) { | |||
108 | for (i = 0; i < 16; i++) { | |||
109 | if (data_rate > dll_speed_table[i].min && | |||
110 | data_rate <= dll_speed_table[i].max) | |||
111 | return dll_speed_table[i].dll_speed; | |||
112 | } | |||
113 | } | |||
114 | ||||
115 | DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n")__drm_dbg(DRM_UT_KMS, "Target MCLK greater than largest MCLK in DLL speed table\n" ); | |||
116 | ||||
117 | return 0x0f; | |||
118 | } | |||
119 | ||||
120 | int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, | |||
121 | RV770_SMC_SCLK_VALUE *sclk) | |||
122 | { | |||
123 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |||
124 | struct atom_clock_dividers dividers; | |||
125 | u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; | |||
126 | u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; | |||
127 | u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; | |||
128 | u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; | |||
129 | u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; | |||
130 | u64 tmp; | |||
131 | u32 reference_clock = rdev->clock.spll.reference_freq; | |||
132 | u32 reference_divider; | |||
133 | u32 fbdiv; | |||
134 | int ret; | |||
135 | ||||
136 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM2, | |||
137 | engine_clock, false0, ÷rs); | |||
138 | if (ret) | |||
139 | return ret; | |||
140 | ||||
141 | reference_divider = 1 + dividers.ref_div; | |||
142 | ||||
143 | tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; | |||
144 | do_div(tmp, reference_clock)({ uint32_t __base = (reference_clock); uint32_t __rem = ((uint64_t )(tmp)) % __base; (tmp) = ((uint64_t)(tmp)) / __base; __rem; } ); | |||
145 | fbdiv = (u32) tmp; | |||
146 | ||||
147 | spll_func_cntl &= ~(SPLL_PDIV_A_MASK(0x7f << 20) | SPLL_REF_DIV_MASK(0x3f << 4)); | |||
148 | spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div)((dividers.ref_div) << 4); | |||
149 | spll_func_cntl |= SPLL_PDIV_A(dividers.post_div)((dividers.post_div) << 20); | |||
150 | ||||
151 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK(0x1ff << 0); | |||
152 | spll_func_cntl_2 |= SCLK_MUX_SEL(2)((2) << 0); | |||
153 | ||||
154 | spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK(0x3ffffff << 0); | |||
155 | spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv)((fbdiv) << 0); | |||
156 | spll_func_cntl_3 |= SPLL_DITHEN(1 << 28); | |||
157 | ||||
158 | if (pi->sclk_ss) { | |||
159 | struct radeon_atom_ss ss; | |||
160 | u32 vco_freq = engine_clock * dividers.post_div; | |||
161 | ||||
162 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, | |||
163 | ASIC_INTERNAL_ENGINE_SS2, vco_freq)) { | |||
164 | u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); | |||
165 | u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); | |||
166 | ||||
167 | cg_spll_spread_spectrum &= ~CLK_S_MASK(0xfff << 4); | |||
168 | cg_spll_spread_spectrum |= CLK_S(clk_s)((clk_s) << 4); | |||
169 | cg_spll_spread_spectrum |= SSEN(1 << 0); | |||
170 | ||||
171 | cg_spll_spread_spectrum_2 &= ~CLK_V_MASK(0x3ffffff << 0); | |||
172 | cg_spll_spread_spectrum_2 |= CLK_V(clk_v)((clk_v) << 0); | |||
173 | } | |||
174 | } | |||
175 | ||||
176 | sclk->sclk_value = cpu_to_be32(engine_clock)(__uint32_t)(__builtin_constant_p(engine_clock) ? (__uint32_t )(((__uint32_t)(engine_clock) & 0xff) << 24 | ((__uint32_t )(engine_clock) & 0xff00) << 8 | ((__uint32_t)(engine_clock ) & 0xff0000) >> 8 | ((__uint32_t)(engine_clock) & 0xff000000) >> 24) : __swap32md(engine_clock)); | |||
177 | sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl)(__uint32_t)(__builtin_constant_p(spll_func_cntl) ? (__uint32_t )(((__uint32_t)(spll_func_cntl) & 0xff) << 24 | ((__uint32_t )(spll_func_cntl) & 0xff00) << 8 | ((__uint32_t)(spll_func_cntl ) & 0xff0000) >> 8 | ((__uint32_t)(spll_func_cntl) & 0xff000000) >> 24) : __swap32md(spll_func_cntl)); | |||
178 | sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2)(__uint32_t)(__builtin_constant_p(spll_func_cntl_2) ? (__uint32_t )(((__uint32_t)(spll_func_cntl_2) & 0xff) << 24 | ( (__uint32_t)(spll_func_cntl_2) & 0xff00) << 8 | ((__uint32_t )(spll_func_cntl_2) & 0xff0000) >> 8 | ((__uint32_t )(spll_func_cntl_2) & 0xff000000) >> 24) : __swap32md (spll_func_cntl_2)); | |||
179 | sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3)(__uint32_t)(__builtin_constant_p(spll_func_cntl_3) ? (__uint32_t )(((__uint32_t)(spll_func_cntl_3) & 0xff) << 24 | ( (__uint32_t)(spll_func_cntl_3) & 0xff00) << 8 | ((__uint32_t )(spll_func_cntl_3) & 0xff0000) >> 8 | ((__uint32_t )(spll_func_cntl_3) & 0xff000000) >> 24) : __swap32md (spll_func_cntl_3)); | |||
180 | sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum)(__uint32_t)(__builtin_constant_p(cg_spll_spread_spectrum) ? ( __uint32_t)(((__uint32_t)(cg_spll_spread_spectrum) & 0xff ) << 24 | ((__uint32_t)(cg_spll_spread_spectrum) & 0xff00 ) << 8 | ((__uint32_t)(cg_spll_spread_spectrum) & 0xff0000 ) >> 8 | ((__uint32_t)(cg_spll_spread_spectrum) & 0xff000000 ) >> 24) : __swap32md(cg_spll_spread_spectrum)); | |||
181 | sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2)(__uint32_t)(__builtin_constant_p(cg_spll_spread_spectrum_2) ? (__uint32_t)(((__uint32_t)(cg_spll_spread_spectrum_2) & 0xff ) << 24 | ((__uint32_t)(cg_spll_spread_spectrum_2) & 0xff00) << 8 | ((__uint32_t)(cg_spll_spread_spectrum_2 ) & 0xff0000) >> 8 | ((__uint32_t)(cg_spll_spread_spectrum_2 ) & 0xff000000) >> 24) : __swap32md(cg_spll_spread_spectrum_2 )); | |||
182 | ||||
183 | return 0; | |||
184 | } | |||
185 | ||||
186 | int rv740_populate_mclk_value(struct radeon_device *rdev, | |||
187 | u32 engine_clock, u32 memory_clock, | |||
188 | RV7XX_SMC_MCLK_VALUE *mclk) | |||
189 | { | |||
190 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |||
191 | u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; | |||
192 | u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; | |||
193 | u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; | |||
194 | u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; | |||
195 | u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; | |||
196 | u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; | |||
197 | u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; | |||
198 | u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; | |||
199 | struct atom_clock_dividers dividers; | |||
200 | u32 ibias; | |||
201 | u32 dll_speed; | |||
202 | int ret; | |||
203 | ||||
204 | ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM1, | |||
205 | memory_clock, false0, ÷rs); | |||
206 | if (ret) | |||
| ||||
207 | return ret; | |||
208 | ||||
209 | ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); | |||
210 | ||||
211 | mpll_ad_func_cntl &= ~(CLKR_MASK(0x1f << 7) | | |||
212 | YCLK_POST_DIV_MASK(3 << 17) | | |||
213 | CLKF_MASK(0x7f << 0) | | |||
214 | CLKFRAC_MASK(0x1f << 12) | | |||
215 | IBIAS_MASK(0x3ff << 20)); | |||
216 | mpll_ad_func_cntl |= CLKR(dividers.ref_div)((dividers.ref_div) << 7); | |||
217 | mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div)((dividers.post_div) << 17); | |||
218 | mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div)((dividers.whole_fb_div) << 0); | |||
219 | mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div)((dividers.frac_fb_div) << 12); | |||
220 | mpll_ad_func_cntl |= IBIAS(ibias)((ibias) << 20); | |||
221 | ||||
222 | if (dividers.vco_mode) | |||
223 | mpll_ad_func_cntl_2 |= VCO_MODE(1 << 29); | |||
224 | else | |||
225 | mpll_ad_func_cntl_2 &= ~VCO_MODE(1 << 29); | |||
226 | ||||
227 | if (pi->mem_gddr5) { | |||
228 | mpll_dq_func_cntl &= ~(CLKR_MASK(0x1f << 7) | | |||
229 | YCLK_POST_DIV_MASK(3 << 17) | | |||
230 | CLKF_MASK(0x7f << 0) | | |||
231 | CLKFRAC_MASK(0x1f << 12) | | |||
232 | IBIAS_MASK(0x3ff << 20)); | |||
233 | mpll_dq_func_cntl |= CLKR(dividers.ref_div)((dividers.ref_div) << 7); | |||
234 | mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div)((dividers.post_div) << 17); | |||
235 | mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div)((dividers.whole_fb_div) << 0); | |||
236 | mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div)((dividers.frac_fb_div) << 12); | |||
237 | mpll_dq_func_cntl |= IBIAS(ibias)((ibias) << 20); | |||
238 | ||||
239 | if (dividers.vco_mode) | |||
240 | mpll_dq_func_cntl_2 |= VCO_MODE(1 << 29); | |||
241 | else | |||
242 | mpll_dq_func_cntl_2 &= ~VCO_MODE(1 << 29); | |||
243 | } | |||
244 | ||||
245 | if (pi->mclk_ss) { | |||
246 | struct radeon_atom_ss ss; | |||
247 | u32 vco_freq = memory_clock * dividers.post_div; | |||
248 | ||||
249 | if (radeon_atombios_get_asic_ss_info(rdev, &ss, | |||
250 | ASIC_INTERNAL_MEMORY_SS1, vco_freq)) { | |||
251 | u32 reference_clock = rdev->clock.mpll.reference_freq; | |||
252 | u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); | |||
253 | u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); | |||
| ||||
254 | u32 clk_v = 0x40000 * ss.percentage * | |||
255 | (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); | |||
256 | ||||
257 | mpll_ss1 &= ~CLKV_MASK(0x3ffffff << 0); | |||
258 | mpll_ss1 |= CLKV(clk_v)((clk_v) << 0); | |||
259 | ||||
260 | mpll_ss2 &= ~CLKS_MASK(0xfff << 0); | |||
261 | mpll_ss2 |= CLKS(clk_s)((clk_s) << 0); | |||
262 | } | |||
263 | } | |||
264 | ||||
265 | dll_speed = rv740_get_dll_speed(pi->mem_gddr5, | |||
266 | memory_clock); | |||
267 | ||||
268 | mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK(0x1f << 0); | |||
269 | mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed)((dll_speed) << 0); | |||
270 | ||||
271 | mclk->mclk770.mclk_value = cpu_to_be32(memory_clock)(__uint32_t)(__builtin_constant_p(memory_clock) ? (__uint32_t )(((__uint32_t)(memory_clock) & 0xff) << 24 | ((__uint32_t )(memory_clock) & 0xff00) << 8 | ((__uint32_t)(memory_clock ) & 0xff0000) >> 8 | ((__uint32_t)(memory_clock) & 0xff000000) >> 24) : __swap32md(memory_clock)); | |||
272 | mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl)(__uint32_t)(__builtin_constant_p(mpll_ad_func_cntl) ? (__uint32_t )(((__uint32_t)(mpll_ad_func_cntl) & 0xff) << 24 | ( (__uint32_t)(mpll_ad_func_cntl) & 0xff00) << 8 | (( __uint32_t)(mpll_ad_func_cntl) & 0xff0000) >> 8 | ( (__uint32_t)(mpll_ad_func_cntl) & 0xff000000) >> 24 ) : __swap32md(mpll_ad_func_cntl)); | |||
273 | mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2)(__uint32_t)(__builtin_constant_p(mpll_ad_func_cntl_2) ? (__uint32_t )(((__uint32_t)(mpll_ad_func_cntl_2) & 0xff) << 24 | ((__uint32_t)(mpll_ad_func_cntl_2) & 0xff00) << 8 | ((__uint32_t)(mpll_ad_func_cntl_2) & 0xff0000) >> 8 | ((__uint32_t)(mpll_ad_func_cntl_2) & 0xff000000) >> 24) : __swap32md(mpll_ad_func_cntl_2)); | |||
274 | mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl)(__uint32_t)(__builtin_constant_p(mpll_dq_func_cntl) ? (__uint32_t )(((__uint32_t)(mpll_dq_func_cntl) & 0xff) << 24 | ( (__uint32_t)(mpll_dq_func_cntl) & 0xff00) << 8 | (( __uint32_t)(mpll_dq_func_cntl) & 0xff0000) >> 8 | ( (__uint32_t)(mpll_dq_func_cntl) & 0xff000000) >> 24 ) : __swap32md(mpll_dq_func_cntl)); | |||
275 | mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2)(__uint32_t)(__builtin_constant_p(mpll_dq_func_cntl_2) ? (__uint32_t )(((__uint32_t)(mpll_dq_func_cntl_2) & 0xff) << 24 | ((__uint32_t)(mpll_dq_func_cntl_2) & 0xff00) << 8 | ((__uint32_t)(mpll_dq_func_cntl_2) & 0xff0000) >> 8 | ((__uint32_t)(mpll_dq_func_cntl_2) & 0xff000000) >> 24) : __swap32md(mpll_dq_func_cntl_2)); | |||
276 | mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl)(__uint32_t)(__builtin_constant_p(mclk_pwrmgt_cntl) ? (__uint32_t )(((__uint32_t)(mclk_pwrmgt_cntl) & 0xff) << 24 | ( (__uint32_t)(mclk_pwrmgt_cntl) & 0xff00) << 8 | ((__uint32_t )(mclk_pwrmgt_cntl) & 0xff0000) >> 8 | ((__uint32_t )(mclk_pwrmgt_cntl) & 0xff000000) >> 24) : __swap32md (mclk_pwrmgt_cntl)); | |||
277 | mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl)(__uint32_t)(__builtin_constant_p(dll_cntl) ? (__uint32_t)((( __uint32_t)(dll_cntl) & 0xff) << 24 | ((__uint32_t) (dll_cntl) & 0xff00) << 8 | ((__uint32_t)(dll_cntl) & 0xff0000) >> 8 | ((__uint32_t)(dll_cntl) & 0xff000000 ) >> 24) : __swap32md(dll_cntl)); | |||
278 | mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1)(__uint32_t)(__builtin_constant_p(mpll_ss1) ? (__uint32_t)((( __uint32_t)(mpll_ss1) & 0xff) << 24 | ((__uint32_t) (mpll_ss1) & 0xff00) << 8 | ((__uint32_t)(mpll_ss1) & 0xff0000) >> 8 | ((__uint32_t)(mpll_ss1) & 0xff000000 ) >> 24) : __swap32md(mpll_ss1)); | |||
279 | mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2)(__uint32_t)(__builtin_constant_p(mpll_ss2) ? (__uint32_t)((( __uint32_t)(mpll_ss2) & 0xff) << 24 | ((__uint32_t) (mpll_ss2) & 0xff00) << 8 | ((__uint32_t)(mpll_ss2) & 0xff0000) >> 8 | ((__uint32_t)(mpll_ss2) & 0xff000000 ) >> 24) : __swap32md(mpll_ss2)); | |||
280 | ||||
281 | return 0; | |||
282 | } | |||
283 | ||||
284 | void rv740_read_clock_registers(struct radeon_device *rdev) | |||
285 | { | |||
286 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |||
287 | ||||
288 | pi->clk_regs.rv770.cg_spll_func_cntl = | |||
289 | RREG32(CG_SPLL_FUNC_CNTL)r100_mm_rreg(rdev, (0x600), 0); | |||
290 | pi->clk_regs.rv770.cg_spll_func_cntl_2 = | |||
291 | RREG32(CG_SPLL_FUNC_CNTL_2)r100_mm_rreg(rdev, (0x604), 0); | |||
292 | pi->clk_regs.rv770.cg_spll_func_cntl_3 = | |||
293 | RREG32(CG_SPLL_FUNC_CNTL_3)r100_mm_rreg(rdev, (0x608), 0); | |||
294 | pi->clk_regs.rv770.cg_spll_spread_spectrum = | |||
295 | RREG32(CG_SPLL_SPREAD_SPECTRUM)r100_mm_rreg(rdev, (0x790), 0); | |||
296 | pi->clk_regs.rv770.cg_spll_spread_spectrum_2 = | |||
297 | RREG32(CG_SPLL_SPREAD_SPECTRUM_2)r100_mm_rreg(rdev, (0x794), 0); | |||
298 | ||||
299 | pi->clk_regs.rv770.mpll_ad_func_cntl = | |||
300 | RREG32(MPLL_AD_FUNC_CNTL)r100_mm_rreg(rdev, (0x624), 0); | |||
301 | pi->clk_regs.rv770.mpll_ad_func_cntl_2 = | |||
302 | RREG32(MPLL_AD_FUNC_CNTL_2)r100_mm_rreg(rdev, (0x628), 0); | |||
303 | pi->clk_regs.rv770.mpll_dq_func_cntl = | |||
304 | RREG32(MPLL_DQ_FUNC_CNTL)r100_mm_rreg(rdev, (0x62c), 0); | |||
305 | pi->clk_regs.rv770.mpll_dq_func_cntl_2 = | |||
306 | RREG32(MPLL_DQ_FUNC_CNTL_2)r100_mm_rreg(rdev, (0x630), 0); | |||
307 | pi->clk_regs.rv770.mclk_pwrmgt_cntl = | |||
308 | RREG32(MCLK_PWRMGT_CNTL)r100_mm_rreg(rdev, (0x648), 0); | |||
309 | pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL)r100_mm_rreg(rdev, (0x64c), 0); | |||
310 | pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1)r100_mm_rreg(rdev, (0x85c), 0); | |||
311 | pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2)r100_mm_rreg(rdev, (0x860), 0); | |||
312 | } | |||
313 | ||||
314 | int rv740_populate_smc_acpi_state(struct radeon_device *rdev, | |||
315 | RV770_SMC_STATETABLE *table) | |||
316 | { | |||
317 | struct rv7xx_power_info *pi = rv770_get_pi(rdev); | |||
318 | u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; | |||
319 | u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; | |||
320 | u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; | |||
321 | u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; | |||
322 | u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; | |||
323 | u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; | |||
324 | u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; | |||
325 | u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; | |||
326 | u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; | |||
327 | ||||
328 | table->ACPIState = table->initialState; | |||
329 | ||||
330 | table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC0x01; | |||
331 | ||||
332 | if (pi->acpi_vddc) { | |||
333 | rv770_populate_vddc_value(rdev, pi->acpi_vddc, | |||
334 | &table->ACPIState.levels[0].vddc); | |||
335 | table->ACPIState.levels[0].gen2PCIE = | |||
336 | pi->pcie_gen2 ? | |||
337 | pi->acpi_pcie_gen2 : 0; | |||
338 | table->ACPIState.levels[0].gen2XSP = | |||
339 | pi->acpi_pcie_gen2; | |||
340 | } else { | |||
341 | rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, | |||
342 | &table->ACPIState.levels[0].vddc); | |||
343 | table->ACPIState.levels[0].gen2PCIE = 0; | |||
344 | } | |||
345 | ||||
346 | mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB(1 << 24) | RESET_EN(1 << 25); | |||
347 | ||||
348 | mpll_dq_func_cntl_2 |= BYPASS(1 << 19) | BIAS_GEN_PDNB(1 << 24) | RESET_EN(1 << 25); | |||
349 | ||||
350 | mclk_pwrmgt_cntl |= (MRDCKA0_RESET(1 << 16) | | |||
351 | MRDCKA1_RESET(1 << 17) | | |||
352 | MRDCKB0_RESET(1 << 18) | | |||
353 | MRDCKB1_RESET(1 << 19) | | |||
354 | MRDCKC0_RESET(1 << 20) | | |||
355 | MRDCKC1_RESET(1 << 21) | | |||
356 | MRDCKD0_RESET(1 << 22) | | |||
357 | MRDCKD1_RESET(1 << 23)); | |||
358 | ||||
359 | dll_cntl |= (MRDCKA0_BYPASS(1 << 24) | | |||
360 | MRDCKA1_BYPASS(1 << 25) | | |||
361 | MRDCKB0_BYPASS(1 << 26) | | |||
362 | MRDCKB1_BYPASS(1 << 27) | | |||
363 | MRDCKC0_BYPASS(1 << 28) | | |||
364 | MRDCKC1_BYPASS(1 << 29) | | |||
365 | MRDCKD0_BYPASS(1 << 30) | | |||
366 | MRDCKD1_BYPASS(1 << 31)); | |||
367 | ||||
368 | spll_func_cntl |= SPLL_RESET(1 << 0) | SPLL_SLEEP(1 << 1) | SPLL_BYPASS_EN(1 << 3); | |||
369 | ||||
370 | spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK(0x1ff << 0); | |||
371 | spll_func_cntl_2 |= SCLK_MUX_SEL(4)((4) << 0); | |||
372 | ||||
373 | table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl)(__uint32_t)(__builtin_constant_p(mpll_ad_func_cntl) ? (__uint32_t )(((__uint32_t)(mpll_ad_func_cntl) & 0xff) << 24 | ( (__uint32_t)(mpll_ad_func_cntl) & 0xff00) << 8 | (( __uint32_t)(mpll_ad_func_cntl) & 0xff0000) >> 8 | ( (__uint32_t)(mpll_ad_func_cntl) & 0xff000000) >> 24 ) : __swap32md(mpll_ad_func_cntl)); | |||
374 | table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2)(__uint32_t)(__builtin_constant_p(mpll_ad_func_cntl_2) ? (__uint32_t )(((__uint32_t)(mpll_ad_func_cntl_2) & 0xff) << 24 | ((__uint32_t)(mpll_ad_func_cntl_2) & 0xff00) << 8 | ((__uint32_t)(mpll_ad_func_cntl_2) & 0xff0000) >> 8 | ((__uint32_t)(mpll_ad_func_cntl_2) & 0xff000000) >> 24) : __swap32md(mpll_ad_func_cntl_2)); | |||
375 | table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl)(__uint32_t)(__builtin_constant_p(mpll_dq_func_cntl) ? (__uint32_t )(((__uint32_t)(mpll_dq_func_cntl) & 0xff) << 24 | ( (__uint32_t)(mpll_dq_func_cntl) & 0xff00) << 8 | (( __uint32_t)(mpll_dq_func_cntl) & 0xff0000) >> 8 | ( (__uint32_t)(mpll_dq_func_cntl) & 0xff000000) >> 24 ) : __swap32md(mpll_dq_func_cntl)); | |||
376 | table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2)(__uint32_t)(__builtin_constant_p(mpll_dq_func_cntl_2) ? (__uint32_t )(((__uint32_t)(mpll_dq_func_cntl_2) & 0xff) << 24 | ((__uint32_t)(mpll_dq_func_cntl_2) & 0xff00) << 8 | ((__uint32_t)(mpll_dq_func_cntl_2) & 0xff0000) >> 8 | ((__uint32_t)(mpll_dq_func_cntl_2) & 0xff000000) >> 24) : __swap32md(mpll_dq_func_cntl_2)); | |||
377 | table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl)(__uint32_t)(__builtin_constant_p(mclk_pwrmgt_cntl) ? (__uint32_t )(((__uint32_t)(mclk_pwrmgt_cntl) & 0xff) << 24 | ( (__uint32_t)(mclk_pwrmgt_cntl) & 0xff00) << 8 | ((__uint32_t )(mclk_pwrmgt_cntl) & 0xff0000) >> 8 | ((__uint32_t )(mclk_pwrmgt_cntl) & 0xff000000) >> 24) : __swap32md (mclk_pwrmgt_cntl)); | |||
378 | table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl)(__uint32_t)(__builtin_constant_p(dll_cntl) ? (__uint32_t)((( __uint32_t)(dll_cntl) & 0xff) << 24 | ((__uint32_t) (dll_cntl) & 0xff00) << 8 | ((__uint32_t)(dll_cntl) & 0xff0000) >> 8 | ((__uint32_t)(dll_cntl) & 0xff000000 ) >> 24) : __swap32md(dll_cntl)); | |||
379 | ||||
380 | table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; | |||
381 | ||||
382 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl)(__uint32_t)(__builtin_constant_p(spll_func_cntl) ? (__uint32_t )(((__uint32_t)(spll_func_cntl) & 0xff) << 24 | ((__uint32_t )(spll_func_cntl) & 0xff00) << 8 | ((__uint32_t)(spll_func_cntl ) & 0xff0000) >> 8 | ((__uint32_t)(spll_func_cntl) & 0xff000000) >> 24) : __swap32md(spll_func_cntl)); | |||
383 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2)(__uint32_t)(__builtin_constant_p(spll_func_cntl_2) ? (__uint32_t )(((__uint32_t)(spll_func_cntl_2) & 0xff) << 24 | ( (__uint32_t)(spll_func_cntl_2) & 0xff00) << 8 | ((__uint32_t )(spll_func_cntl_2) & 0xff0000) >> 8 | ((__uint32_t )(spll_func_cntl_2) & 0xff000000) >> 24) : __swap32md (spll_func_cntl_2)); | |||
384 | table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3)(__uint32_t)(__builtin_constant_p(spll_func_cntl_3) ? (__uint32_t )(((__uint32_t)(spll_func_cntl_3) & 0xff) << 24 | ( (__uint32_t)(spll_func_cntl_3) & 0xff00) << 8 | ((__uint32_t )(spll_func_cntl_3) & 0xff0000) >> 8 | ((__uint32_t )(spll_func_cntl_3) & 0xff000000) >> 24) : __swap32md (spll_func_cntl_3)); | |||
385 | ||||
386 | table->ACPIState.levels[0].sclk.sclk_value = 0; | |||
387 | ||||
388 | table->ACPIState.levels[1] = table->ACPIState.levels[0]; | |||
389 | table->ACPIState.levels[2] = table->ACPIState.levels[0]; | |||
390 | ||||
391 | rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); | |||
392 | ||||
393 | return 0; | |||
394 | } | |||
395 | ||||
396 | void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, | |||
397 | bool_Bool enable) | |||
398 | { | |||
399 | if (enable) | |||
400 | WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x61c), 0); tmp_ &= (~(1 << 24)); tmp_ |= (((1 << 24)) & ~(~(1 << 24))); r100_mm_wreg(rdev, (0x61c), (tmp_), 0); } while (0); | |||
401 | else | |||
402 | WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x61c), 0); tmp_ &= (~(1 << 24)); tmp_ |= ((0) & ~(~(1 << 24))); r100_mm_wreg(rdev, (0x61c), (tmp_), 0); } while (0); | |||
403 | } | |||
404 | ||||
405 | u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) | |||
406 | { | |||
407 | u8 mc_para_index; | |||
408 | ||||
409 | if ((memory_clock < 10000) || (memory_clock > 47500)) | |||
410 | mc_para_index = 0x00; | |||
411 | else | |||
412 | mc_para_index = (u8)((memory_clock - 10000) / 2500); | |||
413 | ||||
414 | return mc_para_index; | |||
415 | } |