/usr/src/sys/dev/pci/if

Bug Summary

File:	dev/pci/if_igc.c
Warning:	line 1019, column 20 Assigned value is garbage or undefined
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name if_igc.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/if_igc.c
1/*	$OpenBSD: if_igc.c,v 1.6 2022/01/09 23:28:19 patrick Exp $	*/
2/*-
* SPDX-License-Identifier: BSD-2-Clause
*
* Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org>
* All rights reserved.
* Copyright (c) 2021 Rubicon Communications, LLC (Netgate)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/

31#include "bpfilter.h"
32#include "vlan.h"

34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/sockio.h>
37#include <sys/mbuf.h>
38#include <sys/malloc.h>
39#include <sys/kernel.h>
40#include <sys/socket.h>
41#include <sys/device.h>
42#include <sys/endian.h>
43#include <sys/intrmap.h>

45#include <net/if.h>
46#include <net/if_media.h>
47#include <net/toeplitz.h>

49#include <netinet/in.h>
50#include <netinet/if_ether.h>

52#if NBPFILTER1 > 0
53#include <net/bpf.h>
54#endif

56#include <machine/bus.h>
57#include <machine/intr.h>

59#include <dev/pci/pcivar.h>
60#include <dev/pci/pcireg.h>
61#include <dev/pci/pcidevs.h>
62#include <dev/pci/if_igc.h>
63#include <dev/pci/igc_hw.h>

65const struct pci_matchid igc_devices[] = {
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I220_V0x15f7 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I221_V0x125e },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_BLANK_NVM0x15fd },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_I0x15f8 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_IT0x0d9f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_K0x3100 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_K20x3101 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_LM0x15f2 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_LMVP0x5502 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I225_V0x15f3 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I226_BLANK_NVM0x125f },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I226_IT0x125d },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I226_LM0x125b },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I226_K0x5504 },
{ PCI_VENDOR_INTEL0x8086, PCI_PRODUCT_INTEL_I226_V0x125c }
81};

83/*********************************************************************
*  Function Prototypes
*********************************************************************/
86int	igc_match(struct device *, void *, void *);
87void	igc_attach(struct device *, struct device *, void *);
88int	igc_detach(struct device *, int);

90void	igc_identify_hardware(struct igc_softc *);
91int	igc_allocate_pci_resources(struct igc_softc *);
92int	igc_allocate_queues(struct igc_softc *);
93void	igc_free_pci_resources(struct igc_softc *);
94void	igc_reset(struct igc_softc *);
95void	igc_init_dmac(struct igc_softc *, uint32_t);
96int	igc_allocate_msix(struct igc_softc *);
97void	igc_setup_msix(struct igc_softc *);
98int	igc_dma_malloc(struct igc_softc *, bus_size_t, struct igc_dma_alloc *);
99void	igc_dma_free(struct igc_softc *, struct igc_dma_alloc *);
100void	igc_setup_interface(struct igc_softc *);

102void	igc_init(void *);
103void	igc_start(struct ifqueue *);
104int	igc_txeof(struct tx_ring *);
105void	igc_stop(struct igc_softc *);
106int	igc_ioctl(struct ifnet *, u_long, caddr_t);
107int	igc_rxrinfo(struct igc_softc *, struct if_rxrinfo *);
108int	igc_rxfill(struct rx_ring *);
109void	igc_rxrefill(void *);
110int	igc_rxeof(struct rx_ring *);
111void	igc_rx_checksum(uint32_t, struct mbuf *, uint32_t);
112void	igc_watchdog(struct ifnet *);
113void	igc_media_status(struct ifnet *, struct ifmediareq *);
114int	igc_media_change(struct ifnet *);
115void	igc_iff(struct igc_softc *);
116void	igc_update_link_status(struct igc_softc *);
117int	igc_get_buf(struct rx_ring *, int);

119void	igc_configure_queues(struct igc_softc *);
120void	igc_set_queues(struct igc_softc *, uint32_t, uint32_t, int);
121void	igc_enable_queue(struct igc_softc *, uint32_t);
122void	igc_enable_intr(struct igc_softc *);
123void	igc_disable_intr(struct igc_softc *);
124int	igc_intr_link(void *);
125int	igc_intr_queue(void *);

127int	igc_allocate_transmit_buffers(struct tx_ring *);
128int	igc_setup_transmit_structures(struct igc_softc *);
129int	igc_setup_transmit_ring(struct tx_ring *);
130void	igc_initialize_transmit_unit(struct igc_softc *);
131void	igc_free_transmit_structures(struct igc_softc *);
132void	igc_free_transmit_buffers(struct tx_ring *);
133int	igc_allocate_receive_buffers(struct rx_ring *);
134int	igc_setup_receive_structures(struct igc_softc *);
135int	igc_setup_receive_ring(struct rx_ring *);
136void	igc_initialize_receive_unit(struct igc_softc *);
137void	igc_free_receive_structures(struct igc_softc *);
138void	igc_free_receive_buffers(struct rx_ring *);
139void	igc_initialize_rss_mapping(struct igc_softc *);

141void	igc_get_hw_control(struct igc_softc *);
142void	igc_release_hw_control(struct igc_softc *);
143int	igc_is_valid_ether_addr(uint8_t *);

145/*********************************************************************
*  OpenBSD Device Interface Entry Points
*********************************************************************/

149struct cfdriver igc_cd = {
NULL((void *)0), "igc", DV_IFNET
151};

153struct cfattach igc_ca = {
sizeof(struct igc_softc), igc_match, igc_attach, igc_detach
155};

157/*********************************************************************
*  Device identification routine
*
*  igc_match determines if the driver should be loaded on
*  adapter based on PCI vendor/device id of the adapter.
*
*  return 0 on success, positive on failure
*********************************************************************/
165int
166igc_match(struct device *parent, void *match, void *aux)
167{
return pci_matchbyid((struct pci_attach_args *)aux, igc_devices,
   nitems(igc_devices)(sizeof((igc_devices)) / sizeof((igc_devices)[0])));
170}

172/*********************************************************************
*  Device initialization routine
*
*  The attach entry point is called when the driver is being loaded.
*  This routine identifies the type of hardware, allocates all resources
*  and initializes the hardware.
*
*  return 0 on success, positive on failure
*********************************************************************/
181void
182igc_attach(struct device *parent, struct device *self, void *aux)
183{
struct pci_attach_args *pa = (struct pci_attach_args *)aux;
struct igc_softc *sc = (struct igc_softc *)self;
struct igc_hw *hw = &sc->hw;

sc->osdep.os_sc = sc;
sc->osdep.os_pa = *pa;

/* Determine hardware and mac info */
igc_identify_hardware(sc);

sc->num_tx_desc = IGC_DEFAULT_TXD1024;
sc->num_rx_desc = IGC_DEFAULT_RXD1024;

/* Setup PCI resources */
if (igc_allocate_pci_resources(sc))
 goto err_pci;

/* Allocate TX/RX queues */
if (igc_allocate_queues(sc))
 goto err_pci;

/* Do shared code initialization */
if (igc_setup_init_funcs(hw, true1)) {
printf(": Setup of shared code failed\n");
goto err_pci;
}

hw->mac.autoneg = DO_AUTO_NEG1;
hw->phy.autoneg_wait_to_complete = false0;
hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT(0x0001 | 0x0002 | 0x0004 | 0x0008 | 0x0020 | 0x0080);

/* Copper options. */
if (hw->phy.media_type == igc_media_type_copper)
hw->phy.mdix = AUTO_ALL_MODES0;

/* Set the max frame size. */
sc->hw.mac.max_frame_size = 9234;

/* Allocate multicast array memory. */
sc->mta = mallocarray(ETHER_ADDR_LEN6, MAX_NUM_MULTICAST_ADDRESSES128,
   M_DEVBUF2, M_NOWAIT0x0002);
if (sc->mta == NULL((void *)0)) {
printf(": Can not allocate multicast setup array\n");
goto err_late;
}

/* Check SOL/IDER usage. */
if (igc_check_reset_block(hw))
printf(": PHY reset is blocked due to SOL/IDER session\n");

/* Enable Energy Efficient Ethernet. */
sc->hw.dev_spec._i225.eee_disable = true1;

igc_reset_hw(hw);

/* Make sure we have a good EEPROM before we read from it. */
if (igc_validate_nvm_checksum(hw) < 0) {
/*
 * Some PCI-E parts fail the first check due to
 * the link being in sleep state, call it again,
 * if it fails a second time its a real issue.
 */
if (igc_validate_nvm_checksum(hw) < 0) {
	printf(": The EEPROM checksum is not valid\n");
	goto err_late;
}
}

/* Copy the permanent MAC address out of the EEPROM. */
if (igc_read_mac_addr(hw) < 0) {
printf(": EEPROM read error while reading MAC address\n");
goto err_late;
}

if (!igc_is_valid_ether_addr(hw->mac.addr)) {
printf(": Invalid MAC address\n");
goto err_late;
}

memcpy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN)__builtin_memcpy((sc->sc_ac.ac_enaddr), (sc->hw.mac.addr
), (6));

if (igc_allocate_msix(sc))
goto err_late;

/* Setup OS specific network interface. */
igc_setup_interface(sc);

igc_reset(sc);
hw->mac.get_link_status = true1;
igc_update_link_status(sc);

/* The driver can now take control from firmware. */
igc_get_hw_control(sc);

printf(", address %s\n", ether_sprintf(sc->hw.mac.addr));
return;

281err_late:
igc_release_hw_control(sc);
283err_pci:
igc_free_pci_resources(sc);
free(sc->mta, M_DEVBUF2, ETHER_ADDR_LEN6 * MAX_NUM_MULTICAST_ADDRESSES128);
286}

288/*********************************************************************
*  Device removal routine
*
*  The detach entry point is called when the driver is being removed.
*  This routine stops the adapter and deallocates all the resources
*  that were allocated for driver operation.
*
*  return 0 on success, positive on failure
*********************************************************************/
297int
298igc_detach(struct device *self, int flags)
299{
struct igc_softc *sc = (struct igc_softc *)self;
struct ifnet *ifp = &sc->sc_ac.ac_if;

igc_stop(sc);

igc_phy_hw_reset(&sc->hw);
igc_release_hw_control(sc);

ether_ifdetach(ifp);
if_detach(ifp);

igc_free_pci_resources(sc);

igc_free_transmit_structures(sc);
igc_free_receive_structures(sc);
free(sc->mta, M_DEVBUF2, ETHER_ADDR_LEN6 * MAX_NUM_MULTICAST_ADDRESSES128);

return 0;
318}

320void
321igc_identify_hardware(struct igc_softc *sc)
322{
struct igc_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;

/* Save off the information about this board. */
sc->hw.device_id = PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff);

/* Do shared code init and setup. */
if (igc_set_mac_type(&sc->hw)) {
printf(": Setup init failure\n");
return;
      }
334}

336int
337igc_allocate_pci_resources(struct igc_softc *sc)
338{
struct igc_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
pcireg_t memtype;

memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, IGC_PCIREG0x10);
if (pci_mapreg_map(pa, IGC_PCIREG0x10, memtype, 0, &os->os_memt,
   &os->os_memh, &os->os_membase, &os->os_memsize, 0)) {
printf(": unable to map registers\n");
return ENXIO6;
}
sc->hw.hw_addr = (uint8_t *)os->os_membase;
sc->hw.back = os;

igc_setup_msix(sc);

return 0;
355}

357int
358igc_allocate_queues(struct igc_softc *sc)
359{
struct igc_queue *iq;
struct tx_ring *txr;
struct rx_ring *rxr;
int i, rsize, rxconf, tsize, txconf;

/* Allocate the top level queue structs. */
sc->queues = mallocarray(sc->sc_nqueues, sizeof(struct igc_queue),
   M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (sc->queues == NULL((void *)0)) {
printf("%s: unable to allocate queue\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}

/* Allocate the TX ring. */
sc->tx_rings = mallocarray(sc->sc_nqueues, sizeof(struct tx_ring),
   M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (sc->tx_rings == NULL((void *)0)) {
printf("%s: unable to allocate TX ring\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto fail;
}

/* Allocate the RX ring. */
sc->rx_rings = mallocarray(sc->sc_nqueues, sizeof(struct rx_ring),
   M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (sc->rx_rings == NULL((void *)0)) {
printf("%s: unable to allocate RX ring\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
goto rx_fail;
}

txconf = rxconf = 0;

/* Set up the TX queues. */
tsize = roundup2(sc->num_tx_desc * sizeof(union igc_adv_tx_desc),(((sc->num_tx_desc * sizeof(union igc_adv_tx_desc)) + (128
) - 1) & ~((128) - 1))
   IGC_DBA_ALIGN)(((sc->num_tx_desc * sizeof(union igc_adv_tx_desc)) + (128
) - 1) & ~((128) - 1));
for (i = 0; i < sc->sc_nqueues; i++, txconf++) {
txr = &sc->tx_rings[i];
txr->sc = sc;
txr->me = i;

if (igc_dma_malloc(sc, tsize, &txr->txdma)) {
	printf("%s: unable to allocate TX descriptor\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto err_tx_desc;
}
txr->tx_base = (union igc_adv_tx_desc *)txr->txdma.dma_vaddr;
bzero((void *)txr->tx_base, tsize)__builtin_bzero(((void *)txr->tx_base), (tsize));
}

/* Set up the RX queues. */
rsize = roundup2(sc->num_rx_desc * sizeof(union igc_adv_rx_desc),(((sc->num_rx_desc * sizeof(union igc_adv_rx_desc)) + (128
) - 1) & ~((128) - 1))
   IGC_DBA_ALIGN)(((sc->num_rx_desc * sizeof(union igc_adv_rx_desc)) + (128
) - 1) & ~((128) - 1));
for (i = 0; i < sc->sc_nqueues; i++, rxconf++) {
rxr = &sc->rx_rings[i];
rxr->sc = sc;
rxr->me = i;
timeout_set(&rxr->rx_refill, igc_rxrefill, rxr);

if (igc_dma_malloc(sc, rsize, &rxr->rxdma)) {
	printf("%s: unable to allocate RX descriptor\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto err_rx_desc;
}
rxr->rx_base = (union igc_adv_rx_desc *)rxr->rxdma.dma_vaddr;
bzero((void *)rxr->rx_base, rsize)__builtin_bzero(((void *)rxr->rx_base), (rsize));
}

/* Set up the queue holding structs. */
for (i = 0; i < sc->sc_nqueues; i++) {
iq = &sc->queues[i];
iq->sc = sc;
iq->txr = &sc->tx_rings[i];
iq->rxr = &sc->rx_rings[i];
snprintf(iq->name, sizeof(iq->name), "%s:%d", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
}

return 0;

437err_rx_desc:
for (rxr = sc->rx_rings; rxconf > 0; rxr++, rxconf--)
igc_dma_free(sc, &rxr->rxdma);
440err_tx_desc:
for (txr = sc->tx_rings; txconf > 0; txr++, txconf--)
igc_dma_free(sc, &txr->txdma);
free(sc->rx_rings, M_DEVBUF2, sc->sc_nqueues * sizeof(struct rx_ring));
sc->rx_rings = NULL((void *)0);
445rx_fail:
free(sc->tx_rings, M_DEVBUF2, sc->sc_nqueues * sizeof(struct tx_ring));
sc->tx_rings = NULL((void *)0);
448fail:
return ENOMEM12;
450}

452void
453igc_free_pci_resources(struct igc_softc *sc)
454{
struct igc_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
struct igc_queue *iq = sc->queues;
int i;

/* Release all msix queue resources. */
for (i = 0; i < sc->sc_nqueues; i++, iq++) {
if (iq->tag)
	pci_intr_disestablish(pa->pa_pc, iq->tag);
iq->tag = NULL((void *)0);
}

if (sc->tag)
pci_intr_disestablish(pa->pa_pc, sc->tag);
sc->tag = NULL((void *)0);
if (os->os_membase != 0)
bus_space_unmap(os->os_memt, os->os_memh, os->os_memsize);
os->os_membase = 0;
473}

475/*********************************************************************
*
*  Initialize the hardware to a configuration as specified by the
*  adapter structure.
*
**********************************************************************/
481void
482igc_reset(struct igc_softc *sc)
483{
struct igc_hw *hw = &sc->hw;
uint32_t pba;
uint16_t rx_buffer_size;

/* Let the firmware know the OS is in control */
igc_get_hw_control(sc);

/*
* Packet Buffer Allocation (PBA)
* Writing PBA sets the receive portion of the buffer
* the remainder is used for the transmit buffer.
*/
pba = IGC_PBA_34K0x0022;

/*
* These parameters control the automatic generation (Tx) and
* response (Rx) to Ethernet PAUSE frames.
* - High water mark should allow for at least two frames to be
*   received after sending an XOFF.
* - Low water mark works best when it is very near the high water mark.
*   This allows the receiver to restart by sending XON when it has
*   drained a bit. Here we use an arbitrary value of 1500 which will
*   restart after one full frame is pulled from the buffer. There
*   could be several smaller frames in the buffer and if so they will
*   not trigger the XON until their total number reduces the buffer
*   by 1500.
* - The pause time is fairly large at 1000 x 512ns = 512 usec.
*/
rx_buffer_size = (pba & 0xffff) << 10;
hw->fc.high_water = rx_buffer_size -
   roundup2(sc->hw.mac.max_frame_size, 1024)(((sc->hw.mac.max_frame_size) + (1024) - 1) & ~((1024)
 - 1));
/* 16-byte granularity */
hw->fc.low_water = hw->fc.high_water - 16;

if (sc->fc) /* locally set flow control value? */
hw->fc.requested_mode = sc->fc;
else
hw->fc.requested_mode = igc_fc_full;

hw->fc.pause_time = IGC_FC_PAUSE_TIME0x0680;

hw->fc.send_xon = true1;

/* Issue a global reset */
igc_reset_hw(hw);
IGC_WRITE_REG(hw, IGC_WUC, 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05800)
, (0)));

/* and a re-init */
if (igc_init_hw(hw) < 0) {
printf(": Hardware Initialization Failed\n");
return;
}

/* Setup DMA Coalescing */
igc_init_dmac(sc, pba);

IGC_WRITE_REG(hw, IGC_VET, ETHERTYPE_VLAN)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00038)
, (0x8100)));
igc_get_phy_info(hw);
igc_check_for_link(hw);
543}

545/*********************************************************************
*
*  Initialize the DMA Coalescing feature
*
**********************************************************************/
550void
551igc_init_dmac(struct igc_softc *sc, uint32_t pba)
552{
struct igc_hw *hw = &sc->hw;
uint32_t dmac, reg = ~IGC_DMACR_DMAC_EN0x80000000;
uint16_t hwm, max_frame_size;
int status;

max_frame_size = sc->hw.mac.max_frame_size;

if (sc->dmac == 0) { /* Disabling it */
IGC_WRITE_REG(hw, IGC_DMACR, reg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02508)
, (reg)));
return;
} else
printf(": DMA Coalescing enabled\n");

/* Set starting threshold */
IGC_WRITE_REG(hw, IGC_DMCTXTH, 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x03550)
, (0)));

hwm = 64 * pba - max_frame_size / 16;
if (hwm < 64 * (pba - 6))
hwm = 64 * (pba - 6);
reg = IGC_READ_REG(hw, IGC_FCRTC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02170)
));
reg &= ~IGC_FCRTC_RTH_COAL_MASK0x0003FFF0;
reg |= ((hwm << IGC_FCRTC_RTH_COAL_SHIFT4)
& IGC_FCRTC_RTH_COAL_MASK0x0003FFF0);
IGC_WRITE_REG(hw, IGC_FCRTC, reg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02170)
, (reg)));

dmac = pba - max_frame_size / 512;
if (dmac < pba - 10)
dmac = pba - 10;
reg = IGC_READ_REG(hw, IGC_DMACR)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02508)
));
reg &= ~IGC_DMACR_DMACTHR_MASK0x00FF0000;
reg |= ((dmac << IGC_DMACR_DMACTHR_SHIFT16)
& IGC_DMACR_DMACTHR_MASK0x00FF0000);

/* transition to L0x or L1 if available..*/
reg |= (IGC_DMACR_DMAC_EN0x80000000 | IGC_DMACR_DMAC_LX_MASK0x30000000);

/* Check if status is 2.5Gb backplane connection
* before configuration of watchdog timer, which is
* in msec values in 12.8usec intervals
* watchdog timer= msec values in 32usec intervals
* for non 2.5Gb connection
*/
status = IGC_READ_REG(hw, IGC_STATUS)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00008)
));
if ((status & IGC_STATUS_2P5_SKU0x00001000) &&
   (!(status & IGC_STATUS_2P5_SKU_OVER0x00002000)))
reg |= ((sc->dmac * 5) >> 6);
else
reg |= (sc->dmac >> 5);

IGC_WRITE_REG(hw, IGC_DMACR, reg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02508)
, (reg)));

IGC_WRITE_REG(hw, IGC_DMCRTRH, 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05DD0)
, (0)));

/* Set the interval before transition */
reg = IGC_READ_REG(hw, IGC_DMCTLX)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02514)
));
reg |= IGC_DMCTLX_DCFLUSH_DIS0x80000000;

/*
** in 2.5Gb connection, TTLX unit is 0.4 usec
** which is 0x4*2 = 0xA. But delay is still 4 usec
*/
status = IGC_READ_REG(hw, IGC_STATUS)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00008)
));
if ((status & IGC_STATUS_2P5_SKU0x00001000) &&
   (!(status & IGC_STATUS_2P5_SKU_OVER0x00002000)))
reg |= 0xA;
else
reg |= 0x4;

IGC_WRITE_REG(hw, IGC_DMCTLX, reg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x02514)
, (reg)));

/* free space in tx packet buffer to wake from DMA coal */
IGC_WRITE_REG(hw, IGC_DMCTXTH, (IGC_TXPBSIZE -((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x03550)
, ((20408 - (2 * max_frame_size)) >> 6)))
   (2 * max_frame_size)) >> 6)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x03550)
, ((20408 - (2 * max_frame_size)) >> 6)));

/* make low power state decision controlled by DMA coal */
reg = IGC_READ_REG(hw, IGC_PCIEMISC)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05BB8)
));
reg &= ~IGC_PCIEMISC_LX_DECISION0x00000080;
IGC_WRITE_REG(hw, IGC_PCIEMISC, reg)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05BB8)
, (reg)));
631}

633int
634igc_allocate_msix(struct igc_softc *sc)
635{
struct igc_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
struct igc_queue *iq;
pci_intr_handle_t ih;
int i, error = 0;

for (i = 0, iq = sc->queues; i < sc->sc_nqueues; i++, iq++) {
if (pci_intr_map_msix(pa, i, &ih)) {
	printf("%s: unable to map msi-x vector %d\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
	error = ENOMEM12;
	goto fail;
}

iq->tag = pci_intr_establish_cpu(pa->pa_pc, ih,
    IPL_NET0x7 | IPL_MPSAFE0x100, intrmap_cpu(sc->sc_intrmap, i),
    igc_intr_queue, iq, iq->name);
if (iq->tag == NULL((void *)0)) {
	printf("%s: unable to establish interrupt %d\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
	error = ENOMEM12;
	goto fail;
}

iq->msix = i;
iq->eims = 1 << i;
}

/* Now the link status/control last MSI-X vector. */
if (pci_intr_map_msix(pa, i, &ih)) {
printf("%s: unable to map link vector\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ENOMEM12;
goto fail;
}

sc->tag = pci_intr_establish(pa->pa_pc, ih, IPL_NET0x7 | IPL_MPSAFE0x100,
   igc_intr_link, sc, sc->sc_dev.dv_xname);
if (sc->tag == NULL((void *)0)) {
printf("%s: unable to establish link interrupt\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ENOMEM12;
goto fail;
}

sc->linkvec = i;
printf(", %s, %d queue%s", pci_intr_string(pa->pa_pc, ih),
   i, (i > 1) ? "s" : "");

return 0;
684fail:
for (iq = sc->queues; i > 0; i--, iq++) {
if (iq->tag == NULL((void *)0))
	continue;
pci_intr_disestablish(pa->pa_pc, iq->tag);
iq->tag = NULL((void *)0);
}

return error;
693}

695void
696igc_setup_msix(struct igc_softc *sc)
697{
struct igc_osdep *os = &sc->osdep;
struct pci_attach_args *pa = &os->os_pa;
int nmsix;

nmsix = pci_intr_msix_count(pa);
if (nmsix <= 1)
printf(": not enough msi-x vectors\n");

/* Give one vector to events. */
nmsix--;

sc->sc_intrmap = intrmap_create(&sc->sc_dev, nmsix, IGC_MAX_VECTORS8,
   INTRMAP_POWEROF2(1 << 0));
sc->sc_nqueues = intrmap_count(sc->sc_intrmap);
712}

714int
715igc_dma_malloc(struct igc_softc *sc, bus_size_t size, struct igc_dma_alloc *dma)
716{
struct igc_osdep *os = &sc->osdep;

dma->dma_tag = os->os_pa.pa_dmat;

if (bus_dmamap_create(dma->dma_tag, size, 1, size, 0, BUS_DMA_NOWAIT,(*(dma->dma_tag)->_dmamap_create)((dma->dma_tag), (size
), (1), (size), (0), (0x0001), (&dma->dma_map))
   &dma->dma_map)(*(dma->dma_tag)->_dmamap_create)((dma->dma_tag), (size
), (1), (size), (0), (0x0001), (&dma->dma_map)))
return 1;
if (bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg,(*(dma->dma_tag)->_dmamem_alloc)((dma->dma_tag), (size
), ((1 << 12)), (0), (&dma->dma_seg), (1), (&
dma->dma_nseg), (0x0001))
   1, &dma->dma_nseg, BUS_DMA_NOWAIT)(*(dma->dma_tag)->_dmamem_alloc)((dma->dma_tag), (size
), ((1 << 12)), (0), (&dma->dma_seg), (1), (&
dma->dma_nseg), (0x0001)))
goto destroy;
if (bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size,(*(dma->dma_tag)->_dmamem_map)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg), (size), (&dma->dma_vaddr
), (0x0001))
   &dma->dma_vaddr, BUS_DMA_NOWAIT)(*(dma->dma_tag)->_dmamem_map)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg), (size), (&dma->dma_vaddr
), (0x0001)))
goto free;
if (bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size,(*(dma->dma_tag)->_dmamap_load)((dma->dma_tag), (dma
->dma_map), (dma->dma_vaddr), (size), (((void *)0)), (0x0001
))
   NULL, BUS_DMA_NOWAIT)(*(dma->dma_tag)->_dmamap_load)((dma->dma_tag), (dma
->dma_map), (dma->dma_vaddr), (size), (((void *)0)), (0x0001
)))
goto unmap;

dma->dma_size = size;

return 0;
737unmap:
bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size)(*(dma->dma_tag)->_dmamem_unmap)((dma->dma_tag), (dma
->dma_vaddr), (size));
739free:
bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg)(*(dma->dma_tag)->_dmamem_free)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg));
741destroy:
bus_dmamap_destroy(dma->dma_tag, dma->dma_map)(*(dma->dma_tag)->_dmamap_destroy)((dma->dma_tag), (
dma->dma_map));
dma->dma_map = NULL((void *)0);
dma->dma_tag = NULL((void *)0);
return 1;
746}

748void
749igc_dma_free(struct igc_softc *sc, struct igc_dma_alloc *dma)
750{
if (dma->dma_tag == NULL((void *)0))
return;

if (dma->dma_map != NULL((void *)0)) {
bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0,(*(dma->dma_tag)->_dmamap_sync)((dma->dma_tag), (dma
->dma_map), (0), (dma->dma_map->dm_mapsize), (0x02 |
 0x08))
    dma->dma_map->dm_mapsize,(*(dma->dma_tag)->_dmamap_sync)((dma->dma_tag), (dma
->dma_map), (0), (dma->dma_map->dm_mapsize), (0x02 |
 0x08))
    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)(*(dma->dma_tag)->_dmamap_sync)((dma->dma_tag), (dma
->dma_map), (0), (dma->dma_map->dm_mapsize), (0x02 |
 0x08));
bus_dmamap_unload(dma->dma_tag, dma->dma_map)(*(dma->dma_tag)->_dmamap_unload)((dma->dma_tag), (dma
->dma_map));
bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size)(*(dma->dma_tag)->_dmamem_unmap)((dma->dma_tag), (dma
->dma_vaddr), (dma->dma_size));
bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg)(*(dma->dma_tag)->_dmamem_free)((dma->dma_tag), (&
dma->dma_seg), (dma->dma_nseg));
bus_dmamap_destroy(dma->dma_tag, dma->dma_map)(*(dma->dma_tag)->_dmamap_destroy)((dma->dma_tag), (
dma->dma_map));
dma->dma_map = NULL((void *)0);
}
764}

766/*********************************************************************
*
*  Setup networking device structure and register an interface.
*
**********************************************************************/
771void
772igc_setup_interface(struct igc_softc *sc)
773{
struct ifnet *ifp = &sc->sc_ac.ac_if;
int i;

ifp->if_softc = sc;
strlcpy(ifp->if_xname, DEVNAME(sc)((sc)->sc_dev.dv_xname), IFNAMSIZ16);
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_xflags = IFXF_MPSAFE0x1;
ifp->if_ioctl = igc_ioctl;
ifp->if_qstart = igc_start;
ifp->if_watchdog = igc_watchdog;
ifp->if_hardmtu = sc->hw.mac.max_frame_size - ETHER_HDR_LEN((6 * 2) + 2) -
   ETHER_CRC_LEN4;
ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1)((&ifp->if_snd)->ifq_maxlen = (sc->num_tx_desc -
 1));

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010;

790#ifdef notyet
791#if NVLAN1 > 0
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
793#endif

ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_CSUM_TCPv40x00000002 | IFCAP_CSUM_UDPv40x00000004;
796#endif

/* Initialize ifmedia structures. */
ifmedia_init(&sc->media, IFM_IMASK0xff00000000000000ULL, igc_media_change, igc_media_status);
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16, 0, NULL((void *)0));
ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34, 0, NULL((void *)0));

ifmedia_add(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0));
ifmedia_set(&sc->media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);

if_attach(ifp);
ether_ifattach(ifp);

if_attach_queues(ifp, sc->sc_nqueues);
if_attach_iqueues(ifp, sc->sc_nqueues);
for (i = 0; i < sc->sc_nqueues; i++) {
struct ifqueue *ifq = ifp->if_ifqs[i];
struct ifiqueue *ifiq = ifp->if_iqs[i];
struct tx_ring *txr = &sc->tx_rings[i];
struct rx_ring *rxr = &sc->rx_rings[i];

ifq->ifq_softc_ifq_ptr._ifq_softc = txr;
txr->ifq = ifq;

ifiq->ifiq_softc_ifiq_ptr._ifiq_softc = rxr;
rxr->ifiq = ifiq;
}
828}

830void
831igc_init(void *arg)
832{
struct igc_softc *sc = (struct igc_softc *)arg;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct rx_ring *rxr;
uint32_t ctrl = 0;
int i, s;

s = splnet()splraise(0x7);

igc_stop(sc);

/* Get the latest mac address, user can use a LAA. */
bcopy(sc->sc_ac.ac_enaddr, sc->hw.mac.addr, ETHER_ADDR_LEN6);

/* Put the address into the receive address array. */
igc_rar_set(&sc->hw, sc->hw.mac.addr, 0);

/* Initialize the hardware. */
igc_reset(sc);
igc_update_link_status(sc);

/* Setup VLAN support, basic and offload if available. */
IGC_WRITE_REG(&sc->hw, IGC_VET, ETHERTYPE_VLAN)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x00038), (0x8100)));

/* Prepare transmit descriptors and buffers. */
if (igc_setup_transmit_structures(sc)) {
printf("%s: Could not setup transmit structures\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
igc_stop(sc);
splx(s)spllower(s);
return;
}
igc_initialize_transmit_unit(sc);

sc->rx_mbuf_sz = MCLBYTES(1 << 11) + ETHER_ALIGN2;
/* Prepare receive descriptors and buffers. */
if (igc_setup_receive_structures(sc)) {
printf("%s: Could not setup receive structures\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
igc_stop(sc);
splx(s)spllower(s);
return;
      }
igc_initialize_receive_unit(sc);

if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020) {
ctrl = IGC_READ_REG(&sc->hw, IGC_CTRL)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x00000)));
ctrl |= IGC_CTRL_VME0x40000000;
IGC_WRITE_REG(&sc->hw, IGC_CTRL, ctrl)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x00000), (ctrl)));
}

/* Setup multicast table. */
igc_iff(sc);

igc_clear_hw_cntrs_base_generic(&sc->hw);

igc_configure_queues(sc);

/* This clears any pending interrupts */
IGC_READ_REG(&sc->hw, IGC_ICR)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x01500)));
IGC_WRITE_REG(&sc->hw, IGC_ICS, IGC_ICS_LSC)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x01504), (0x00000004)));

/* The driver can now take control from firmware. */
igc_get_hw_control(sc);

/* Set Energy Efficient Ethernet. */
igc_set_eee_i225(&sc->hw, true1, true1, true1);

for (i = 0; i < sc->sc_nqueues; i++) {
rxr = &sc->rx_rings[i];
igc_rxfill(rxr);
if (if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive) == 0) {
	printf("%s: Unable to fill any rx descriptors\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	igc_stop(sc);
	splx(s)spllower(s);
}
IGC_WRITE_REG(&sc->hw, IGC_RDT(i),((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (((i) < 4 ? (0x02818 + ((i) * 0x100)) : (0x0C018
 + ((i) * 0x40)))), ((rxr->last_desc_filled + 1) % sc->
num_rx_desc)))
    (rxr->last_desc_filled + 1) % sc->num_rx_desc)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (((i) < 4 ? (0x02818 + ((i) * 0x100)) : (0x0C018
 + ((i) * 0x40)))), ((rxr->last_desc_filled + 1) % sc->
num_rx_desc)));
}

igc_enable_intr(sc);

ifp->if_flags |= IFF_RUNNING0x40;
for (i = 0; i < sc->sc_nqueues; i++)
ifq_clr_oactive(ifp->if_ifqs[i]);

splx(s)spllower(s);
920}

922static inline int
923igc_load_mbuf(bus_dma_tag_t dmat, bus_dmamap_t map, struct mbuf *m)
924{
int error;

error = bus_dmamap_load_mbuf(dmat, map, m,(*(dmat)->_dmamap_load_mbuf)((dmat), (map), (m), (0x0100 |
 0x0001))
   BUS_DMA_STREAMING | BUS_DMA_NOWAIT)(*(dmat)->_dmamap_load_mbuf)((dmat), (map), (m), (0x0100 |
 0x0001));
if (error != EFBIG27)
return (error);

error = m_defrag(m, M_DONTWAIT0x0002);
if (error != 0)
return (error);

return (bus_dmamap_load_mbuf(dmat, map, m,(*(dmat)->_dmamap_load_mbuf)((dmat), (map), (m), (0x0100 |
 0x0001))
   BUS_DMA_STREAMING | BUS_DMA_NOWAIT)(*(dmat)->_dmamap_load_mbuf)((dmat), (map), (m), (0x0100 |
 0x0001)));
938}

940void
941igc_start(struct ifqueue *ifq)
942{
struct ifnet *ifp = ifq->ifq_if;
struct igc_softc *sc = ifp->if_softc;
struct tx_ring *txr = ifq->ifq_softc_ifq_ptr._ifq_softc;
union igc_adv_tx_desc *txdesc;
struct igc_tx_buf *txbuf;
bus_dmamap_t map;
struct mbuf *m;
unsigned int prod, free, last, i;
1
'last' declared without an initial value→
unsigned int mask;
uint32_t cmd_type_len;
uint32_t olinfo_status;
int post = 0;
955#if NBPFILTER1 > 0
caddr_t if_bpf;
957#endif

if (!sc->link_active) {
2
←
Assuming field 'link_active' is not equal to 0→
3
←
Taking false branch→
ifq_purge(ifq);
return;
}

prod = txr->next_avail_desc;
free = txr->next_to_clean;
if (free <= prod)
4
←
Assuming 'free' is > 'prod'→
5
←
Taking false branch→
free += sc->num_tx_desc;
free -= prod;

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x08))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x08));

mask = sc->num_tx_desc - 1;

for (;;) {
6
←
Loop condition is true.  Entering loop body→
if (free <= IGC_MAX_SCATTER40) {
7
←
Assuming 'free' is > IGC_MAX_SCATTER→
8
←
Taking false branch→
	ifq_set_oactive(ifq);
	break;
}

m = ifq_dequeue(ifq);
if (m == NULL((void *)0))
9
←
Assuming 'm' is not equal to NULL→
10
←
Taking false branch→
	break;

txbuf = &txr->tx_buffers[prod];
map = txbuf->map;

if (igc_load_mbuf(txr->txdma.dma_tag, map, m) != 0) {
11
←
Assuming the condition is false→
12
←
Taking false branch→
	ifq->ifq_errors++;
	m_freem(m);
	continue;
}

olinfo_status = m->m_pkthdrM_dat.MH.MH_pkthdr.len << IGC_ADVTXD_PAYLEN_SHIFT14;

bus_dmamap_sync(txr->txdma.dma_tag, map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (map), (0), (map->dm_mapsize), (0x04))
    map->dm_mapsize, BUS_DMASYNC_PREWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (map), (0), (map->dm_mapsize), (0x04));

for (i = 0; i < map->dm_nsegs; i++) {
13
←
Assuming 'i' is >= field 'dm_nsegs'→
14
←
Loop condition is false. Execution continues on line 1018→
	txdesc = &txr->tx_base[prod];

	cmd_type_len = IGC_ADVTXD_DCMD_IFCS0x02000000 | IGC_ADVTXD_DTYP_DATA0x00300000 |
	    IGC_ADVTXD_DCMD_DEXT0x20000000 | map->dm_segs[i].ds_len;
	if (i == map->dm_nsegs - 1)
		cmd_type_len |= IGC_ADVTXD_DCMD_EOP0x01000000 |
		    IGC_ADVTXD_DCMD_RS0x08000000;

	htolem64(&txdesc->read.buffer_addr, map->dm_segs[i].ds_addr)(*(__uint64_t *)(&txdesc->read.buffer_addr) = ((__uint64_t
)(map->dm_segs[i].ds_addr)));
	htolem32(&txdesc->read.cmd_type_len, cmd_type_len)(*(__uint32_t *)(&txdesc->read.cmd_type_len) = ((__uint32_t
)(cmd_type_len)));
	htolem32(&txdesc->read.olinfo_status, olinfo_status)(*(__uint32_t *)(&txdesc->read.olinfo_status) = ((__uint32_t
)(olinfo_status)));

	last = prod;

	prod++;
	prod &= mask;
}

txbuf->m_head = m;
txbuf->eop_index = last;
15
←
Assigned value is garbage or undefined

1021#if NBPFILTER1 > 0
if_bpf = ifp->if_bpf;
if (if_bpf)
	bpf_mtap_ether(if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
1025#endif

free -= i;
post = 1;
}

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x04))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x04));

if (post) {
txr->next_avail_desc = prod;
IGC_WRITE_REG(&sc->hw, IGC_TDT(txr->me), prod)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (((txr->me) < 4 ? (0x03818 + ((txr->
me) * 0x100)) : (0x0E018 + ((txr->me) * 0x40)))), (prod)));
}
1038}

1040int
1041igc_txeof(struct tx_ring *txr)
1042{
struct igc_softc *sc = txr->sc;
struct ifqueue *ifq = txr->ifq;
union igc_adv_tx_desc *txdesc;
struct igc_tx_buf *txbuf;
bus_dmamap_t map;
unsigned int cons, prod, last;
unsigned int mask;
int done = 0;

prod = txr->next_avail_desc;
cons = txr->next_to_clean;

if (cons == prod)
return (0);

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x02))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x02));

mask = sc->num_tx_desc - 1;

do {
txbuf = &txr->tx_buffers[cons];
last = txbuf->eop_index;
txdesc = &txr->tx_base[last];

if (!(txdesc->wb.status & htole32(IGC_TXD_STAT_DD)((__uint32_t)(0x00000001))))
	break;

map = txbuf->map;

bus_dmamap_sync(txr->txdma.dma_tag, map, 0, map->dm_mapsize,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (map), (0), (map->dm_mapsize), (0x08))
    BUS_DMASYNC_POSTWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (map), (0), (map->dm_mapsize), (0x08));
bus_dmamap_unload(txr->txdma.dma_tag, map)(*(txr->txdma.dma_tag)->_dmamap_unload)((txr->txdma.
dma_tag), (map));
m_freem(txbuf->m_head);

txbuf->m_head = NULL((void *)0);
txbuf->eop_index = -1;

cons = last + 1;
cons &= mask;

done = 1;
} while (cons != prod);

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01))
   txr->txdma.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01));

txr->next_to_clean = cons;

if (ifq_is_oactive(ifq))
ifq_restart(ifq);

return (done);
1096}

1098/*********************************************************************
*
*  This routine disables all traffic on the adapter by issuing a
*  global reset on the MAC.
*
**********************************************************************/
1104void
1105igc_stop(struct igc_softc *sc)
1106{
struct ifnet *ifp = &sc->sc_ac.ac_if;
int i;

/* Tell the stack that the interface is no longer active. */
      ifp->if_flags &= ~IFF_RUNNING0x40;

igc_disable_intr(sc);

igc_reset_hw(&sc->hw);
IGC_WRITE_REG(&sc->hw, IGC_WUC, 0)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x05800), (0)));

intr_barrier(sc->tag);
      for (i = 0; i < sc->sc_nqueues; i++) {
              struct ifqueue *ifq = ifp->if_ifqs[i];
              ifq_barrier(ifq);
              ifq_clr_oactive(ifq);

              if (sc->queues[i].tag != NULL((void *)0))
                      intr_barrier(sc->queues[i].tag);
              timeout_del(&sc->rx_rings[i].rx_refill);
      }

      igc_free_transmit_structures(sc);
      igc_free_receive_structures(sc);

igc_update_link_status(sc);
1133}

1135/*********************************************************************
*  Ioctl entry point
*
*  igc_ioctl is called when the user wants to configure the
*  interface.
*
*  return 0 on success, positive on failure
**********************************************************************/
1143int
1144igc_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data)
1145{
struct igc_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *)data;
int s, error = 0;

s = splnet()splraise(0x7);

switch (cmd) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
if (!(ifp->if_flags & IFF_RUNNING0x40))
	igc_init(sc);
break;
case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else
		igc_init(sc);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		igc_stop(sc);
}
break;
case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
error = ifmedia_ioctl(ifp, ifr, &sc->media, cmd);
break;
case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((170))):
error = igc_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data);
break;
default:
error = ether_ioctl(ifp, &sc->sc_ac, cmd, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40) {
	igc_disable_intr(sc);
	igc_iff(sc);
	igc_enable_intr(sc);
}
error = 0;
}

splx(s)spllower(s);
return error;
1191}

1193int
1194igc_rxrinfo(struct igc_softc *sc, struct if_rxrinfo *ifri)
1195{
struct if_rxring_info *ifr;
struct rx_ring *rxr;
int error, i, n = 0;

if ((ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_DEVBUF2,
   M_WAITOK0x0001 | M_ZERO0x0008)) == NULL((void *)0))
return ENOMEM12;

for (i = 0; i < sc->sc_nqueues; i++) {
rxr = &sc->rx_rings[i];
ifr[n].ifr_size = MCLBYTES(1 << 11);
snprintf(ifr[n].ifr_name, sizeof(ifr[n].ifr_name), "%d", i);
ifr[n].ifr_info = rxr->rx_ring;
n++;
}

error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr);
free(ifr, M_DEVBUF2, sc->sc_nqueues * sizeof(*ifr));

return error;
1216}

1218int
1219igc_rxfill(struct rx_ring *rxr)
1220{
struct igc_softc *sc = rxr->sc;
int i, post = 0;
u_int slots;

bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x08)) 
   rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x08));

i = rxr->last_desc_filled;
for (slots = if_rxr_get(&rxr->rx_ring, sc->num_rx_desc); slots > 0;
   slots--) {
if (++i == sc->num_rx_desc)
	i = 0;

if (igc_get_buf(rxr, i) != 0)
	break;

rxr->last_desc_filled = i;
post = 1;
}

bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x04))
   rxr->rxdma.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x04));

if_rxr_put(&rxr->rx_ring, slots)do { (&rxr->rx_ring)->rxr_alive -= (slots); } while
 (0);

return post;
1247}

1249void
1250igc_rxrefill(void *xrxr)
1251{
struct rx_ring *rxr = xrxr;
struct igc_softc *sc = rxr->sc;

if (igc_rxfill(rxr)) {
IGC_WRITE_REG(&sc->hw, IGC_RDT(rxr->me),((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (((rxr->me) < 4 ? (0x02818 + ((rxr->
me) * 0x100)) : (0x0C018 + ((rxr->me) * 0x40)))), ((rxr->
last_desc_filled + 1) % sc->num_rx_desc)))
    (rxr->last_desc_filled + 1) % sc->num_rx_desc)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (((rxr->me) < 4 ? (0x02818 + ((rxr->
me) * 0x100)) : (0x0C018 + ((rxr->me) * 0x40)))), ((rxr->
last_desc_filled + 1) % sc->num_rx_desc)));
}
else if (if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive) == 0)
timeout_add(&rxr->rx_refill, 1);
1261}

1263/*********************************************************************
*
*  This routine executes in interrupt context. It replenishes
*  the mbufs in the descriptor and sends data which has been
*  dma'ed into host memory to upper layer.
*
*********************************************************************/
1270int
1271igc_rxeof(struct rx_ring *rxr)
1272{
struct igc_softc *sc = rxr->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct mbuf *mp, *m;
struct igc_rx_buf *rxbuf, *nxbuf;
union igc_adv_rx_desc *rxdesc;
uint32_t ptype, staterr = 0;
uint16_t len, vtag;
uint8_t eop = 0;
int i, nextp;

if (!ISSET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) & (0x40)))
return 0;

i = rxr->next_to_check;
while (if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive) > 0) {
uint32_t hash;
uint16_t hashtype;

bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x02))
    i * sizeof(union igc_adv_rx_desc),(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x02))
    sizeof(union igc_adv_rx_desc), BUS_DMASYNC_POSTREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x02));

rxdesc = &rxr->rx_base[i];
staterr = letoh32(rxdesc->wb.upper.status_error)((__uint32_t)(rxdesc->wb.upper.status_error));
if (!ISSET(staterr, IGC_RXD_STAT_DD)((staterr) & (0x01))) {
	bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x01))
	    i * sizeof(union igc_adv_rx_desc),(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x01))
	    sizeof(union igc_adv_rx_desc), BUS_DMASYNC_PREREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x01));
	break;
}

/* Zero out the receive descriptors status. */
rxdesc->wb.upper.status_error = 0;
rxbuf = &rxr->rx_buffers[i];

/* Pull the mbuf off the ring. */
bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
))
    rxbuf->map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
));
bus_dmamap_unload(rxr->rxdma.dma_tag, rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_unload)((rxr->rxdma.
dma_tag), (rxbuf->map));

mp = rxbuf->buf;
len = letoh16(rxdesc->wb.upper.length)((__uint16_t)(rxdesc->wb.upper.length));
vtag = letoh16(rxdesc->wb.upper.vlan)((__uint16_t)(rxdesc->wb.upper.vlan));
eop = ((staterr & IGC_RXD_STAT_EOP0x02) == IGC_RXD_STAT_EOP0x02);
ptype = letoh32(rxdesc->wb.lower.lo_dword.data)((__uint32_t)(rxdesc->wb.lower.lo_dword.data)) &
    IGC_PKTTYPE_MASK0x0000FFF0;
hash = letoh32(rxdesc->wb.lower.hi_dword.rss)((__uint32_t)(rxdesc->wb.lower.hi_dword.rss));
hashtype = le16toh(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info)((__uint16_t)(rxdesc->wb.lower.lo_dword.hs_rss.pkt_info)) &
    IGC_RXDADV_RSSTYPE_MASK0x0000000F;    

if (staterr & IGC_RXDEXT_STATERR_RXE0x80000000) {
	if (rxbuf->fmp) {
		m_freem(rxbuf->fmp);
		rxbuf->fmp = NULL((void *)0);
	}

	m_freem(mp);
	rxbuf->buf = NULL((void *)0);
	goto next_desc;
}

if (mp == NULL((void *)0)) {
	panic("%s: igc_rxeof: NULL mbuf in slot %d "
	    "(nrx %d, filled %d)", DEVNAME(sc)((sc)->sc_dev.dv_xname), i,
	    if_rxr_inuse(&rxr->rx_ring)((&rxr->rx_ring)->rxr_alive), rxr->last_desc_filled);
}

if (!eop) {
	/*
	 * Figure out the next descriptor of this frame.
	 */
	nextp = i + 1;
	if (nextp == sc->num_rx_desc)
		nextp = 0;
	nxbuf = &rxr->rx_buffers[nextp];
	/* prefetch(nxbuf); */
}

mp->m_lenm_hdr.mh_len = len;

m = rxbuf->fmp;
rxbuf->buf = rxbuf->fmp = NULL((void *)0);

if (m != NULL((void *)0))
	m->m_pkthdrM_dat.MH.MH_pkthdr.len += mp->m_lenm_hdr.mh_len;
else {
	m = mp;
	m->m_pkthdrM_dat.MH.MH_pkthdr.len = mp->m_lenm_hdr.mh_len;
1362#if NVLAN1 > 0
	if (staterr & IGC_RXD_STAT_VP0x08) {
		m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag = vtag;
		m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
	}
1367#endif
}

/* Pass the head pointer on */
if (eop == 0) {
	nxbuf->fmp = m;
	m = NULL((void *)0);
	mp->m_nextm_hdr.mh_next = nxbuf->buf;
} else {
	igc_rx_checksum(staterr, m, ptype);

	if (hashtype != IGC_RXDADV_RSSTYPE_NONE0x00000000) {
		m->m_pkthdrM_dat.MH.MH_pkthdr.ph_flowid = hash;
		SET(m->m_pkthdr.csum_flags, M_FLOWID)((m->M_dat.MH.MH_pkthdr.csum_flags) |= (0x4000));
	}

	ml_enqueue(&ml, m);
}
1385next_desc:
if_rxr_put(&rxr->rx_ring, 1)do { (&rxr->rx_ring)->rxr_alive -= (1); } while (0);
bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x01))
    i * sizeof(union igc_adv_rx_desc),(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x01))
    sizeof(union igc_adv_rx_desc), BUS_DMASYNC_PREREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (i * sizeof(union igc_adv_rx_desc
)), (sizeof(union igc_adv_rx_desc)), (0x01));

/* Advance our pointers to the next descriptor. */
if (++i == sc->num_rx_desc)
	i = 0;
}
rxr->next_to_check = i;

if (ifiq_input(rxr->ifiq, &ml))
if_rxr_livelocked(&rxr->rx_ring);

if (!(staterr & IGC_RXD_STAT_DD0x01))
return 0;

return 1;
1404}

1406/*********************************************************************
*
*  Verify that the hardware indicated that the checksum is valid.
*  Inform the stack about the status of checksum so that stack
*  doesn't spend time verifying the checksum.
*
*********************************************************************/
1413void
1414igc_rx_checksum(uint32_t staterr, struct mbuf *m, uint32_t ptype)
1415{
uint16_t status = (uint16_t)staterr;
uint8_t errors = (uint8_t)(staterr >> 24);

if (status & IGC_RXD_STAT_IPCS0x40) {
if (!(errors & IGC_RXD_ERR_IPE0x40)) {
	/* IP Checksum Good */
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = M_IPV4_CSUM_IN_OK0x0008;
} else
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags = 0;
}

if (status & (IGC_RXD_STAT_TCPCS0x20 | IGC_RXD_STAT_UDPCS0x10)) {
if (!(errors & IGC_RXD_ERR_TCPE0x20))
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |=
	    M_TCP_CSUM_IN_OK0x0020 | M_UDP_CSUM_IN_OK0x0080;
}
1432}

1434void
1435igc_watchdog(struct ifnet * ifp)
1436{
1437}

1439/*********************************************************************
*
*  Media Ioctl callback
*
*  This routine is called whenever the user queries the status of
*  the interface using ifconfig.
*
**********************************************************************/
1447void
1448igc_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1449{
struct igc_softc *sc = ifp->if_softc;

igc_update_link_status(sc);

ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
ifmr->ifm_active = IFM_ETHER0x0000000000000100ULL;

if (!sc->link_active) {
ifmr->ifm_active |= IFM_NONE2ULL;
return;
}

ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;

switch (sc->link_speed) {
case 10:
ifmr->ifm_active |= IFM_10_T3;
break;
case 100:
ifmr->ifm_active |= IFM_100_TX6;
              break;
case 1000:
ifmr->ifm_active |= IFM_1000_T16;
break;
case 2500:
              ifmr->ifm_active |= IFM_2500_T34;
              break;
}

if (sc->link_duplex == FULL_DUPLEX2)
ifmr->ifm_active |= IFM_FDX0x0000010000000000ULL;
else
ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL;
1483}

1485/*********************************************************************
*
*  Media Ioctl callback
*
*  This routine is called when the user changes speed/duplex using
*  media/mediopt option with ifconfig.
*
**********************************************************************/
1493int
1494igc_media_change(struct ifnet *ifp)
1495{
struct igc_softc *sc = ifp->if_softc;
struct ifmedia *ifm = &sc->media;

if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
return (EINVAL22);

sc->hw.mac.autoneg = DO_AUTO_NEG1;

switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) {
case IFM_AUTO0ULL:
sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT(0x0001 | 0x0002 | 0x0004 | 0x0008 | 0x0020 | 0x0080);
break;
      case IFM_2500_T34:
              sc->hw.phy.autoneg_advertised = ADVERTISE_2500_FULL0x0080;
              break;
case IFM_1000_T16:
sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL0x0020;
break;
case IFM_100_TX6:
if ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_HDX0x0000020000000000ULL)
	sc->hw.phy.autoneg_advertised = ADVERTISE_100_HALF0x0004;
else
	sc->hw.phy.autoneg_advertised = ADVERTISE_100_FULL0x0008;
break;
case IFM_10_T3:
if ((ifm->ifm_media & IFM_GMASK0x00ffff0000000000ULL) == IFM_HDX0x0000020000000000ULL)
	sc->hw.phy.autoneg_advertised = ADVERTISE_10_HALF0x0001;
else
	sc->hw.phy.autoneg_advertised = ADVERTISE_10_FULL0x0002;
break;
default:
return EINVAL22;
}

igc_init(sc);

return 0;
1533}

1535void
1536igc_iff(struct igc_softc *sc)
1537{
struct ifnet *ifp = &sc->sc_ac.ac_if;
      struct arpcom *ac = &sc->sc_ac;
struct ether_multi *enm;
struct ether_multistep step;
uint32_t reg_rctl = 0;
uint8_t *mta;
int mcnt = 0;

mta = sc->mta;
      bzero(mta, sizeof(uint8_t) * ETHER_ADDR_LEN *__builtin_bzero((mta), (sizeof(uint8_t) * 6 * 128))
   MAX_NUM_MULTICAST_ADDRESSES)__builtin_bzero((mta), (sizeof(uint8_t) * 6 * 128));

reg_rctl = IGC_READ_REG(&sc->hw, IGC_RCTL)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x00100)));
reg_rctl &= ~(IGC_RCTL_UPE0x00000008 | IGC_RCTL_MPE0x00000010);
ifp->if_flags &= ~IFF_ALLMULTI0x200;

if (ifp->if_flags & IFF_PROMISC0x100 || ac->ac_multirangecnt > 0 ||
   ac->ac_multicnt > MAX_NUM_MULTICAST_ADDRESSES128) {
ifp->if_flags |= IFF_ALLMULTI0x200;
reg_rctl |= IGC_RCTL_MPE0x00000010;
if (ifp->if_flags & IFF_PROMISC0x100)
	reg_rctl |= IGC_RCTL_UPE0x00000008;
} else {
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
	bcopy(enm->enm_addrlo,
	    &mta[mcnt * ETHER_ADDR_LEN6], ETHER_ADDR_LEN6);
	mcnt++;

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}

igc_update_mc_addr_list(&sc->hw, mta, mcnt);
}

IGC_WRITE_REG(&sc->hw, IGC_RCTL, reg_rctl)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x00100), (reg_rctl)));
1574}

1576void
1577igc_update_link_status(struct igc_softc *sc)
1578{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct igc_hw *hw = &sc->hw;
int link_state;

if (IGC_READ_REG(&sc->hw, IGC_STATUS)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x00008))) & IGC_STATUS_LU0x00000002) {
if (sc->link_active == 0) {
	igc_get_speed_and_duplex(hw, &sc->link_speed,
	    &sc->link_duplex);
	sc->link_active = 1;
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(sc->link_speed)((((sc->link_speed) * 1000ULL) * 1000ULL));
}
link_state = (sc->link_duplex == FULL_DUPLEX2) ?
    LINK_STATE_FULL_DUPLEX6 : LINK_STATE_HALF_DUPLEX5;
} else {
if (sc->link_active == 1) {
	ifp->if_baudrateif_data.ifi_baudrate = sc->link_speed = 0;
	sc->link_duplex = 0;
	sc->link_active = 0;
}
link_state = LINK_STATE_DOWN2;
}
if (ifp->if_link_stateif_data.ifi_link_state != link_state) {
ifp->if_link_stateif_data.ifi_link_state = link_state;
if_link_state_change(ifp);
}
1604}

1606/*********************************************************************
*
*  Get a buffer from system mbuf buffer pool.
*
**********************************************************************/
1611int
1612igc_get_buf(struct rx_ring *rxr, int i)
1613{
struct igc_softc *sc = rxr->sc;
struct igc_rx_buf *rxbuf;
struct mbuf *m;
union igc_adv_rx_desc *rxdesc;
int error;

rxbuf = &rxr->rx_buffers[i];
rxdesc = &rxr->rx_base[i];
if (rxbuf->buf) {
printf("%s: slot %d already has an mbuf\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
return ENOBUFS55;
}

m = MCLGETL(NULL, M_DONTWAIT, sc->rx_mbuf_sz)m_clget((((void *)0)), (0x0002), (sc->rx_mbuf_sz));
if (!m)
return ENOBUFS55;

m->m_datam_hdr.mh_data += (m->m_extM_dat.MH.MH_dat.MH_ext.ext_size - sc->rx_mbuf_sz);
m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = sc->rx_mbuf_sz;

error = bus_dmamap_load_mbuf(rxr->rxdma.dma_tag, rxbuf->map, m,(*(rxr->rxdma.dma_tag)->_dmamap_load_mbuf)((rxr->rxdma
.dma_tag), (rxbuf->map), (m), (0x0001))
   BUS_DMA_NOWAIT)(*(rxr->rxdma.dma_tag)->_dmamap_load_mbuf)((rxr->rxdma
.dma_tag), (rxbuf->map), (m), (0x0001));
if (error) {
m_freem(m);
return error;
}

bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x01
))
   rxbuf->map->dm_mapsize, BUS_DMASYNC_PREREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x01
));
rxbuf->buf = m;

rxdesc->read.pkt_addr = htole64(rxbuf->map->dm_segs[0].ds_addr)((__uint64_t)(rxbuf->map->dm_segs[0].ds_addr));

return 0;
1648}

1650void
1651igc_configure_queues(struct igc_softc *sc)
1652{
struct igc_hw *hw = &sc->hw;
struct igc_queue *iq = sc->queues;
uint32_t ivar, newitr = 0;
int i;

/* First turn on RSS capability */
IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE | IGC_GPIE_EIAME |((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01514)
, (0x00000010 | 0x40000000 | 0x80000000 | 0x00000001)))
   IGC_GPIE_PBA | IGC_GPIE_NSICR)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01514)
, (0x00000010 | 0x40000000 | 0x80000000 | 0x00000001)));

/* Set the starting interrupt rate */
newitr = (4000000 / MAX_INTS_PER_SEC8000) & 0x7FFC;

newitr |= IGC_EITR_CNT_IGNR0x80000000;

/* Turn on MSI-X */
for (i = 0; i < sc->sc_nqueues; i++, iq++) {
/* RX entries */
igc_set_queues(sc, i, iq->msix, 0);
/* TX entries */
igc_set_queues(sc, i, iq->msix, 1);
sc->msix_queuesmask |= iq->eims;
IGC_WRITE_REG(hw, IGC_EITR(iq->msix), newitr)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), ((0x01680
 + (0x4 * (iq->msix)))), (newitr)));
}

/* And for the link interrupt */
ivar = (sc->linkvec | IGC_IVAR_VALID0x80) << 8;
sc->msix_linkmask = 1 << sc->linkvec;
IGC_WRITE_REG(hw, IGC_IVAR_MISC, ivar)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01740)
, (ivar)));
1681}

1683void
1684igc_set_queues(struct igc_softc *sc, uint32_t entry, uint32_t vector, int type)
1685{
struct igc_hw *hw = &sc->hw;
uint32_t ivar, index;

index = entry >> 1;
ivar = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, index)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), ((0x01700
 + ((index) << 2)))));
if (type) {
if (entry & 1) {
	ivar &= 0x00FFFFFF;
	ivar |= (vector | IGC_IVAR_VALID0x80) << 24;
} else {
	ivar &= 0xFFFF00FF;
	ivar |= (vector | IGC_IVAR_VALID0x80) << 8;
}
} else {
if (entry & 1) {
	ivar &= 0xFF00FFFF;
	ivar |= (vector | IGC_IVAR_VALID0x80) << 16;
} else {
	ivar &= 0xFFFFFF00;
	ivar |= vector | IGC_IVAR_VALID0x80;
}
}
IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, index, ivar)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), ((0x01700
 + ((index) << 2))), (ivar)));
1709}

1711void
1712igc_enable_queue(struct igc_softc *sc, uint32_t eims)
1713{
IGC_WRITE_REG(&sc->hw, IGC_EIMS, eims)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x01524), (eims)));
1715}

1717void
1718igc_enable_intr(struct igc_softc *sc)
1719{
struct igc_hw *hw = &sc->hw;
uint32_t mask;

mask = (sc->msix_queuesmask | sc->msix_linkmask);
IGC_WRITE_REG(hw, IGC_EIAC, mask)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0152C)
, (mask)));
IGC_WRITE_REG(hw, IGC_EIAM, mask)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01530)
, (mask)));
IGC_WRITE_REG(hw, IGC_EIMS, mask)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01524)
, (mask)));
IGC_WRITE_REG(hw, IGC_IMS, IGC_IMS_LSC)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01508)
, (0x00000004)));
IGC_WRITE_FLUSH(hw)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00008)
));
1729}

1731void
1732igc_disable_intr(struct igc_softc *sc)
1733{
struct igc_hw *hw = &sc->hw;

IGC_WRITE_REG(hw, IGC_EIMC, 0xffffffff)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x01528)
, (0xffffffff)));
IGC_WRITE_REG(hw, IGC_EIAC, 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0152C)
, (0)));
IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x0150C)
, (0xffffffff)));
IGC_WRITE_FLUSH(hw)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00008)
));
1740}

1742int
1743igc_intr_link(void *arg)
1744{
struct igc_softc *sc = (struct igc_softc *)arg;
uint32_t reg_icr = IGC_READ_REG(&sc->hw, IGC_ICR)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x01500)));

if (reg_icr & IGC_ICR_LSC0x00000004) {
KERNEL_LOCK()_kernel_lock();
sc->hw.mac.get_link_status = true1;
igc_update_link_status(sc);
KERNEL_UNLOCK()_kernel_unlock();
}

IGC_WRITE_REG(&sc->hw, IGC_IMS, IGC_IMS_LSC)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x01508), (0x00000004)));
IGC_WRITE_REG(&sc->hw, IGC_EIMS, sc->msix_linkmask)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x01524), (sc->msix_linkmask)));

return 1;
1759}

1761int
1762igc_intr_queue(void *arg)
1763{
struct igc_queue *iq = arg;
struct igc_softc *sc = iq->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct rx_ring *rxr = iq->rxr;
struct tx_ring *txr = iq->txr;

if (ifp->if_flags & IFF_RUNNING0x40) {
igc_txeof(txr);
igc_rxeof(rxr);
igc_rxrefill(rxr);
}

igc_enable_queue(sc, iq->eims);

return 1;
1779}

1781/*********************************************************************
*
*  Allocate memory for tx_buffer structures. The tx_buffer stores all
*  the information needed to transmit a packet on the wire.
*
**********************************************************************/
1787int
1788igc_allocate_transmit_buffers(struct tx_ring *txr)
1789{
struct igc_softc *sc = txr->sc;
struct igc_tx_buf *txbuf;
int error, i;

txr->tx_buffers = mallocarray(sc->num_tx_desc,
   sizeof(struct igc_tx_buf), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (txr->tx_buffers == NULL((void *)0)) {
printf("%s: Unable to allocate tx_buffer memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ENOMEM12;
goto fail;
}
txr->txtag = txr->txdma.dma_tag;

/* Create the descriptor buffer dma maps. */
for (i = 0; i < sc->num_tx_desc; i++) {
txbuf = &txr->tx_buffers[i];
error = bus_dmamap_create(txr->txdma.dma_tag, IGC_TSO_SIZE,(*(txr->txdma.dma_tag)->_dmamap_create)((txr->txdma.
dma_tag), (65535), (40), ((1 << 12)), (0), (0x0001), (&
txbuf->map))
    IGC_MAX_SCATTER, PAGE_SIZE, 0, BUS_DMA_NOWAIT, &txbuf->map)(*(txr->txdma.dma_tag)->_dmamap_create)((txr->txdma.
dma_tag), (65535), (40), ((1 << 12)), (0), (0x0001), (&
txbuf->map));
if (error != 0) {
	printf("%s: Unable to create TX DMA map\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto fail;
}
}

return 0;
1817fail:
return error;
1819}


1822/*********************************************************************
*
*  Allocate and initialize transmit structures.
*
**********************************************************************/
1827int
1828igc_setup_transmit_structures(struct igc_softc *sc)
1829{
struct tx_ring *txr = sc->tx_rings;
int i;

for (i = 0; i < sc->sc_nqueues; i++, txr++) {
if (igc_setup_transmit_ring(txr))
	goto fail;
}

return 0;
1839fail:
igc_free_transmit_structures(sc);
return ENOBUFS55;
1842}

1844/*********************************************************************
*
*  Initialize a transmit ring.
*
**********************************************************************/
1849int
1850igc_setup_transmit_ring(struct tx_ring *txr)
1851{
struct igc_softc *sc = txr->sc;

/* Now allocate transmit buffers for the ring. */
if (igc_allocate_transmit_buffers(txr))
return ENOMEM12;

/* Clear the old ring contents */
bzero((void *)txr->tx_base,__builtin_bzero(((void *)txr->tx_base), ((sizeof(union igc_adv_tx_desc
)) * sc->num_tx_desc))
   (sizeof(union igc_adv_tx_desc)) * sc->num_tx_desc)__builtin_bzero(((void *)txr->tx_base), ((sizeof(union igc_adv_tx_desc
)) * sc->num_tx_desc));

/* Reset indices. */
txr->next_avail_desc = 0;
txr->next_to_clean = 0;

bus_dmamap_sync(txr->txdma.dma_tag, txr->txdma.dma_map, 0,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   txr->txdma.dma_map->dm_mapsize,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txr->txdma.dma_map), (0), (txr->txdma.dma_map->dm_mapsize
), (0x01 | 0x04));

return 0;
1871}

1873/*********************************************************************
*
*  Enable transmit unit.
*
**********************************************************************/
1878void
1879igc_initialize_transmit_unit(struct igc_softc *sc)
1880{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct tx_ring *txr;
struct igc_hw *hw = &sc->hw;
uint64_t bus_addr;
uint32_t tctl, txdctl = 0;
      int i;

/* Setup the Base and Length of the TX descriptor ring. */
for (i = 0; i < sc->sc_nqueues; i++) {
txr = &sc->tx_rings[i];

bus_addr = txr->txdma.dma_map->dm_segs[0].ds_addr;

/* Base and len of TX ring */
IGC_WRITE_REG(hw, IGC_TDLEN(i),((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03808 + ((i) * 0x100)) : (0x0E008 + ((i) * 0x40)))), (
sc->num_tx_desc * sizeof(union igc_adv_tx_desc))))
    sc->num_tx_desc * sizeof(union igc_adv_tx_desc))((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03808 + ((i) * 0x100)) : (0x0E008 + ((i) * 0x40)))), (
sc->num_tx_desc * sizeof(union igc_adv_tx_desc))));
IGC_WRITE_REG(hw, IGC_TDBAH(i), (uint32_t)(bus_addr >> 32))((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03804 + ((i) * 0x100)) : (0x0E004 + ((i) * 0x40)))), (
(uint32_t)(bus_addr >> 32))));
IGC_WRITE_REG(hw, IGC_TDBAL(i), (uint32_t)bus_addr)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03800 + ((i) * 0x100)) : (0x0E000 + ((i) * 0x40)))), (
(uint32_t)bus_addr)));

/* Init the HEAD/TAIL indices */
IGC_WRITE_REG(hw, IGC_TDT(i), 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03818 + ((i) * 0x100)) : (0x0E018 + ((i) * 0x40)))), (
0)));
IGC_WRITE_REG(hw, IGC_TDH(i), 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03810 + ((i) * 0x100)) : (0x0E010 + ((i) * 0x40)))), (
0)));

txr->watchdog_timer = 0;

txdctl = 0;		/* Clear txdctl */
txdctl |= 0x1f;		/* PTHRESH */
txdctl |= 1 << 8;	/* HTHRESH */
txdctl |= 1 << 16;	/* WTHRESH */
txdctl |= 1 << 22;	/* Reserved bit 22 must always be 1 */
txdctl |= IGC_TXDCTL_GRAN0x01000000;
txdctl |= 1 << 25;	/* LWTHRESH */

IGC_WRITE_REG(hw, IGC_TXDCTL(i), txdctl)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x03828 + ((i) * 0x100)) : (0x0E028 + ((i) * 0x40)))), (
txdctl)));
}
ifp->if_timer = 0;

/* Program the Transmit Control Register */
tctl = IGC_READ_REG(&sc->hw, IGC_TCTL)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x00400)));
tctl &= ~IGC_TCTL_CT0x00000ff0;
tctl |= (IGC_TCTL_PSP0x00000008 | IGC_TCTL_RTLC0x01000000 | IGC_TCTL_EN0x00000002 |
   (IGC_COLLISION_THRESHOLD15 << IGC_CT_SHIFT4));

/* This write will effectively turn on the transmit unit. */
IGC_WRITE_REG(&sc->hw, IGC_TCTL, tctl)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x00400), (tctl)));
1926}

1928/*********************************************************************
*
*  Free all transmit rings.
*
**********************************************************************/
1933void
1934igc_free_transmit_structures(struct igc_softc *sc)
1935{
struct tx_ring *txr = sc->tx_rings;
int i;

for (i = 0; i < sc->sc_nqueues; i++, txr++)
igc_free_transmit_buffers(txr);
1941}

1943/*********************************************************************
*
*  Free transmit ring related data structures.
*
**********************************************************************/
1948void
1949igc_free_transmit_buffers(struct tx_ring *txr)
1950{
struct igc_softc *sc = txr->sc;
struct igc_tx_buf *txbuf;
int i;

if (txr->tx_buffers == NULL((void *)0))
return;

txbuf = txr->tx_buffers;
for (i = 0; i < sc->num_tx_desc; i++, txbuf++) {
if (txbuf->map != NULL((void *)0) && txbuf->map->dm_nsegs > 0) {
	bus_dmamap_sync(txr->txdma.dma_tag, txbuf->map,(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txbuf->map), (0), (txbuf->map->dm_mapsize), (0x08
))
	    0, txbuf->map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(txr->txdma.dma_tag)->_dmamap_sync)((txr->txdma.dma_tag
), (txbuf->map), (0), (txbuf->map->dm_mapsize), (0x08
));
	bus_dmamap_unload(txr->txdma.dma_tag, txbuf->map)(*(txr->txdma.dma_tag)->_dmamap_unload)((txr->txdma.
dma_tag), (txbuf->map));
}
if (txbuf->m_head != NULL((void *)0)) {
	m_freem(txbuf->m_head);
	txbuf->m_head = NULL((void *)0);
}
if (txbuf->map != NULL((void *)0)) {
	bus_dmamap_destroy(txr->txdma.dma_tag, txbuf->map)(*(txr->txdma.dma_tag)->_dmamap_destroy)((txr->txdma
.dma_tag), (txbuf->map));
	txbuf->map = NULL((void *)0);
}
}

if (txr->tx_buffers != NULL((void *)0))
free(txr->tx_buffers, M_DEVBUF2,
    sc->num_tx_desc * sizeof(struct igc_tx_buf));
txr->tx_buffers = NULL((void *)0);
txr->txtag = NULL((void *)0);
1980}

1982/*********************************************************************
*
*  Allocate memory for rx_buffer structures. Since we use one
*  rx_buffer per received packet, the maximum number of rx_buffer's
*  that we'll need is equal to the number of receive descriptors
*  that we've allocated.
*
**********************************************************************/
1990int
1991igc_allocate_receive_buffers(struct rx_ring *rxr)
1992{
struct igc_softc *sc = rxr->sc;
struct igc_rx_buf *rxbuf;
int i, error;

rxr->rx_buffers = mallocarray(sc->num_rx_desc,
   sizeof(struct igc_rx_buf), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (rxr->rx_buffers == NULL((void *)0)) {
printf("%s: Unable to allocate rx_buffer memory\n",
    DEVNAME(sc)((sc)->sc_dev.dv_xname));
error = ENOMEM12;
goto fail;
}

rxbuf = rxr->rx_buffers;
for (i = 0; i < sc->num_rx_desc; i++, rxbuf++) {
error = bus_dmamap_create(rxr->rxdma.dma_tag,(*(rxr->rxdma.dma_tag)->_dmamap_create)((rxr->rxdma.
dma_tag), (9216), (1), (9216), (0), (0x0001), (&rxbuf->
map))
    MAX_JUMBO_FRAME_SIZE, 1, MAX_JUMBO_FRAME_SIZE, 0,(*(rxr->rxdma.dma_tag)->_dmamap_create)((rxr->rxdma.
dma_tag), (9216), (1), (9216), (0), (0x0001), (&rxbuf->
map))
    BUS_DMA_NOWAIT, &rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_create)((rxr->rxdma.
dma_tag), (9216), (1), (9216), (0), (0x0001), (&rxbuf->
map));
if (error) {
	printf("%s: Unable to create RX DMA map\n",
	    DEVNAME(sc)((sc)->sc_dev.dv_xname));
	goto fail;
}
}
bus_dmamap_sync(rxr->rxdma.dma_tag, rxr->rxdma.dma_map, 0,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   rxr->rxdma.dma_map->dm_mapsize,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x01 | 0x04))
   BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxr->rxdma.dma_map), (0), (rxr->rxdma.dma_map->dm_mapsize
), (0x01 | 0x04));

return 0;
2022fail:
return error;
2024}

2026/*********************************************************************
*
*  Allocate and initialize receive structures.
*
**********************************************************************/
2031int
2032igc_setup_receive_structures(struct igc_softc *sc)
2033{
struct rx_ring *rxr = sc->rx_rings;
int i;

for (i = 0; i < sc->sc_nqueues; i++, rxr++) {
if (igc_setup_receive_ring(rxr))
	goto fail;
}

return 0;
2043fail:
igc_free_receive_structures(sc);
return ENOBUFS55;
2046}

2048/*********************************************************************
*
*  Initialize a receive ring and its buffers.
*
**********************************************************************/
2053int
2054igc_setup_receive_ring(struct rx_ring *rxr)
2055{
struct igc_softc *sc = rxr->sc;
struct ifnet *ifp = &sc->sc_ac.ac_if;
int rsize;

rsize = roundup2(sc->num_rx_desc * sizeof(union igc_adv_rx_desc),(((sc->num_rx_desc * sizeof(union igc_adv_rx_desc)) + (128
) - 1) & ~((128) - 1))
   IGC_DBA_ALIGN)(((sc->num_rx_desc * sizeof(union igc_adv_rx_desc)) + (128
) - 1) & ~((128) - 1));

/* Clear the ring contents. */
bzero((void *)rxr->rx_base, rsize)__builtin_bzero(((void *)rxr->rx_base), (rsize));

if (igc_allocate_receive_buffers(rxr))
return ENOMEM12;

/* Setup our descriptor indices. */
rxr->next_to_check = 0;
rxr->last_desc_filled = sc->num_rx_desc - 1;

if_rxr_init(&rxr->rx_ring, 2 * ((ifp->if_hardmtu / MCLBYTES(1 << 11)) + 1),
   sc->num_rx_desc - 1);

return 0;
2077}

2079/*********************************************************************
*
*  Enable receive unit.
*
**********************************************************************/
2084void
2085igc_initialize_receive_unit(struct igc_softc *sc)
2086{
      struct rx_ring *rxr = sc->rx_rings;
      struct igc_hw *hw = &sc->hw;
uint32_t rctl, rxcsum, srrctl = 0;
int i;

/*
* Make sure receives are disabled while setting
* up the descriptor ring.
*/
rctl = IGC_READ_REG(hw, IGC_RCTL)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00100)
));
IGC_WRITE_REG(hw, IGC_RCTL, rctl & ~IGC_RCTL_EN)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00100)
, (rctl & ~0x00000002)));

/* Setup the Receive Control Register */
rctl &= ~(3 << IGC_RCTL_MO_SHIFT12);
rctl |= IGC_RCTL_EN0x00000002 | IGC_RCTL_BAM0x00008000 | IGC_RCTL_LBM_NO0x00000000 |
   IGC_RCTL_RDMTS_HALF0x00000000 | (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT12);

/* Do not store bad packets */
rctl &= ~IGC_RCTL_SBP0x00000004;

/* Enable Long Packet receive */
if (sc->hw.mac.max_frame_size != ETHER_MAX_LEN1518)
rctl |= IGC_RCTL_LPE0x00000020;

/* Strip the CRC */
rctl |= IGC_RCTL_SECRC0x04000000;

/*
* Set the interrupt throttling rate. Value is calculated
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
*/
IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x000C4)
, ((1000000000/(8000 * 256)))));

rxcsum = IGC_READ_REG(hw, IGC_RXCSUM)((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05000)
));
rxcsum &= ~IGC_RXCSUM_PCSD0x00002000;

if (sc->sc_nqueues > 1)
rxcsum |= IGC_RXCSUM_PCSD0x00002000;

IGC_WRITE_REG(hw, IGC_RXCSUM, rxcsum)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05000)
, (rxcsum)));

if (sc->sc_nqueues > 1)
igc_initialize_rss_mapping(sc);

2131#if 0
srrctl |= 4096 >> IGC_SRRCTL_BSIZEPKT_SHIFT10;
rctl |= IGC_RCTL_SZ_40960x00030000 | IGC_RCTL_BSEX0x02000000;
2134#endif

srrctl |= 2048 >> IGC_SRRCTL_BSIZEPKT_SHIFT10;
rctl |= IGC_RCTL_SZ_20480x00000000;

/*
* If TX flow control is disabled and there's > 1 queue defined,
* enable DROP.
*
* This drops frames rather than hanging the RX MAC for all queues.
*/
if ((sc->sc_nqueues > 1) && (sc->fc == igc_fc_none ||
   sc->fc == igc_fc_rx_pause)) {
srrctl |= IGC_SRRCTL_DROP_EN0x80000000;
}

/* Setup the Base and Length of the RX descriptor rings. */
for (i = 0; i < sc->sc_nqueues; i++, rxr++) {
IGC_WRITE_REG(hw, IGC_RXDCTL(i), 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02828 + ((i) * 0x100)) : (0x0C028 + ((i) * 0x40)))), (
0)));
uint64_t bus_addr = rxr->rxdma.dma_map->dm_segs[0].ds_addr;
uint32_t rxdctl;

srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF0x02000000;

IGC_WRITE_REG(hw, IGC_RDLEN(i),((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02808 + ((i) * 0x100)) : (0x0C008 + ((i) * 0x40)))), (
sc->num_rx_desc * sizeof(union igc_adv_rx_desc))))
    sc->num_rx_desc * sizeof(union igc_adv_rx_desc))((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02808 + ((i) * 0x100)) : (0x0C008 + ((i) * 0x40)))), (
sc->num_rx_desc * sizeof(union igc_adv_rx_desc))));
IGC_WRITE_REG(hw, IGC_RDBAH(i), (uint32_t)(bus_addr >> 32))((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02804 + ((i) * 0x100)) : (0x0C004 + ((i) * 0x40)))), (
(uint32_t)(bus_addr >> 32))));
IGC_WRITE_REG(hw, IGC_RDBAL(i), (uint32_t)bus_addr)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02800 + ((i) * 0x100)) : (0x0C000 + ((i) * 0x40)))), (
(uint32_t)bus_addr)));
IGC_WRITE_REG(hw, IGC_SRRCTL(i), srrctl)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x0280C + ((i) * 0x100)) : (0x0C00C + ((i) * 0x40)))), (
srrctl)));

/* Setup the Head and Tail Descriptor Pointers */
IGC_WRITE_REG(hw, IGC_RDH(i), 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02810 + ((i) * 0x100)) : (0x0C010 + ((i) * 0x40)))), (
0)));
IGC_WRITE_REG(hw, IGC_RDT(i), 0)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02818 + ((i) * 0x100)) : (0x0C018 + ((i) * 0x40)))), (
0)));

/* Enable this Queue */
rxdctl = IGC_READ_REG(hw, IGC_RXDCTL(i))((((struct igc_osdep *)(hw)->back)->os_memt)->read_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02828 + ((i) * 0x100)) : (0x0C028 + ((i) * 0x40))))));
rxdctl |= IGC_RXDCTL_QUEUE_ENABLE0x02000000;
rxdctl &= 0xFFF00000;
rxdctl |= IGC_RX_PTHRESH8;
rxdctl |= IGC_RX_HTHRESH8 << 8;
rxdctl |= IGC_RX_WTHRESH4 << 16;
IGC_WRITE_REG(hw, IGC_RXDCTL(i), rxdctl)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((i) <
? (0x02828 + ((i) * 0x100)) : (0x0C028 + ((i) * 0x40)))), (
rxdctl)));
}

/* Make sure VLAN Filters are off */
rctl &= ~IGC_RCTL_VFE0x00040000;

/* Write out the settings */
IGC_WRITE_REG(hw, IGC_RCTL, rctl)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x00100)
, (rctl)));
2183}

2185/*********************************************************************
*
*  Free all receive rings.
*
**********************************************************************/
2190void
2191igc_free_receive_structures(struct igc_softc *sc)
2192{
struct rx_ring *rxr;
int i;

for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++)
if_rxr_init(&rxr->rx_ring, 0, 0);

for (i = 0, rxr = sc->rx_rings; i < sc->sc_nqueues; i++, rxr++)
igc_free_receive_buffers(rxr);
2201}

2203/*********************************************************************
*
*  Free receive ring data structures
*
**********************************************************************/
2208void
2209igc_free_receive_buffers(struct rx_ring *rxr)
2210{
struct igc_softc *sc = rxr->sc;
struct igc_rx_buf *rxbuf;
int i;

if (rxr->rx_buffers != NULL((void *)0)) {
for (i = 0; i < sc->num_rx_desc; i++) {
	rxbuf = &rxr->rx_buffers[i];
	if (rxbuf->buf != NULL((void *)0)) {
		bus_dmamap_sync(rxr->rxdma.dma_tag, rxbuf->map,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
))
		    0, rxbuf->map->dm_mapsize,(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
))
		    BUS_DMASYNC_POSTREAD)(*(rxr->rxdma.dma_tag)->_dmamap_sync)((rxr->rxdma.dma_tag
), (rxbuf->map), (0), (rxbuf->map->dm_mapsize), (0x02
));
		bus_dmamap_unload(rxr->rxdma.dma_tag,(*(rxr->rxdma.dma_tag)->_dmamap_unload)((rxr->rxdma.
dma_tag), (rxbuf->map))
		    rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_unload)((rxr->rxdma.
dma_tag), (rxbuf->map));
		m_freem(rxbuf->buf);
		rxbuf->buf = NULL((void *)0);
	}
	bus_dmamap_destroy(rxr->rxdma.dma_tag, rxbuf->map)(*(rxr->rxdma.dma_tag)->_dmamap_destroy)((rxr->rxdma
.dma_tag), (rxbuf->map));
	rxbuf->map = NULL((void *)0);
}
free(rxr->rx_buffers, M_DEVBUF2,
    sc->num_rx_desc * sizeof(struct igc_rx_buf));
rxr->rx_buffers = NULL((void *)0);
}
2234}

2236/*
* Initialise the RSS mapping for NICs that support multiple transmit/
* receive rings.
*/
2240void
2241igc_initialize_rss_mapping(struct igc_softc *sc)
2242{
struct igc_hw *hw = &sc->hw;
uint32_t rss_key[10], mrqc, reta, shift = 0;
int i, queue_id;

/*
* The redirection table controls which destination
* queue each bucket redirects traffic to.
* Each DWORD represents four queues, with the LSB
* being the first queue in the DWORD.
*
* This just allocates buckets to queues using round-robin
* allocation.
*
* NOTE: It Just Happens to line up with the default
* RSS allocation method.
*/

/* Warning FM follows */
reta = 0;
for (i = 0; i < 128; i++) {
queue_id = (i % sc->sc_nqueues);
/* Adjust if required */
queue_id = queue_id << shift;

/*
 * The low 8 bits are for hash value (n+0);
 * The next 8 bits are for hash value (n+1), etc.
 */
reta = reta >> 8;
reta = reta | ( ((uint32_t) queue_id) << 24);
if ((i & 3) == 3) {
	IGC_WRITE_REG(hw, IGC_RETA(i >> 2), reta)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), ((0x05C00
 + ((i >> 2) * 4))), (reta)));
	reta = 0;
}
}

/*
* MRQC: Multiple Receive Queues Command
* Set queuing to RSS control, number depends on the device.
*/
mrqc = IGC_MRQC_ENABLE_RSS_4Q0x00000002;

/* Set up random bits */
      stoeplitz_to_key(&rss_key, sizeof(rss_key));

/* Now fill our hash function seeds */
for (i = 0; i < 10; i++)
IGC_WRITE_REG_ARRAY(hw, IGC_RSSRK(0), i, rss_key[i])((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (((0x05C80
 + ((0) * 4)) + ((i) << 2))), (rss_key[i])));

/*
* Configure the RSS fields to hash upon.
*/
mrqc |= (IGC_MRQC_RSS_FIELD_IPV40x00020000 | IGC_MRQC_RSS_FIELD_IPV4_TCP0x00010000);
mrqc |= (IGC_MRQC_RSS_FIELD_IPV60x00100000 | IGC_MRQC_RSS_FIELD_IPV6_TCP0x00200000);
mrqc |= IGC_MRQC_RSS_FIELD_IPV6_TCP_EX0x00040000;

IGC_WRITE_REG(hw, IGC_MRQC, mrqc)((((struct igc_osdep *)(hw)->back)->os_memt)->write_4
((((struct igc_osdep *)(hw)->back)->os_memh), (0x05818)
, (mrqc)));
2300}

2302/*
* igc_get_hw_control sets the {CTRL_EXT|FWSM}:DRV_LOAD bit.
* For ASF and Pass Through versions of f/w this means
* that the driver is loaded. For AMT version type f/w
* this means that the network i/f is open.
*/
2308void
2309igc_get_hw_control(struct igc_softc *sc)
2310{
uint32_t ctrl_ext;

ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x00018)));
IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x00018), (ctrl_ext | 0x10000000)));
2315}

2317/*
* igc_release_hw_control resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
* For ASF and Pass Through versions of f/w this means that
* the driver is no longer loaded. For AMT versions of the
* f/w this means that the network i/f is closed.
*/
2323void
2324igc_release_hw_control(struct igc_softc *sc)
2325{
uint32_t ctrl_ext;

ctrl_ext = IGC_READ_REG(&sc->hw, IGC_CTRL_EXT)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->read_4((((struct igc_osdep *)(&sc->hw)->back)
->os_memh), (0x00018)));
IGC_WRITE_REG(&sc->hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD)((((struct igc_osdep *)(&sc->hw)->back)->os_memt
)->write_4((((struct igc_osdep *)(&sc->hw)->back
)->os_memh), (0x00018), (ctrl_ext & ~0x10000000)));
2330}

2332int
2333igc_is_valid_ether_addr(uint8_t *addr)
2334{
char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };

if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN6))) {
return 0;
}

return 1;
2342}