Bug Summary

File:dev/pci/drm/i915/i915_drv.c
Warning:line 486, column 15
Value stored to 'mask_size' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name i915_drv.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/i915_drv.c
1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/acpi.h>
31#include <linux/device.h>
32#include <linux/oom.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vga_switcheroo.h>
40#include <linux/vt.h>
41#include <acpi/video.h>
42
43#include <drm/drm_atomic_helper.h>
44#include <drm/drm_ioctl.h>
45#include <drm/drm_irq.h>
46#include <drm/drm_managed.h>
47#include <drm/drm_probe_helper.h>
48
49#include "display/intel_acpi.h"
50#include "display/intel_audio.h"
51#include "display/intel_bw.h"
52#include "display/intel_cdclk.h"
53#include "display/intel_csr.h"
54#include "display/intel_display_debugfs.h"
55#include "display/intel_display_types.h"
56#include "display/intel_dp.h"
57#include "display/intel_fbdev.h"
58#include "display/intel_hotplug.h"
59#include "display/intel_overlay.h"
60#include "display/intel_pipe_crc.h"
61#include "display/intel_sprite.h"
62#include "display/intel_vga.h"
63
64#include "gem/i915_gem_context.h"
65#include "gem/i915_gem_ioctls.h"
66#include "gem/i915_gem_mman.h"
67#include "gt/intel_gt.h"
68#include "gt/intel_gt_pm.h"
69#include "gt/intel_rc6.h"
70
71#include "i915_debugfs.h"
72#include "i915_drv.h"
73#include "i915_ioc32.h"
74#include "i915_irq.h"
75#include "i915_memcpy.h"
76#include "i915_perf.h"
77#include "i915_query.h"
78#include "i915_suspend.h"
79#include "i915_switcheroo.h"
80#include "i915_sysfs.h"
81#include "i915_trace.h"
82#include "i915_vgpu.h"
83#include "intel_dram.h"
84#include "intel_gvt.h"
85#include "intel_memory_region.h"
86#include "intel_pm.h"
87#include "vlv_suspend.h"
88
89static struct drm_driver driver;
90
91#ifdef __linux__
92static int i915_get_bridge_dev(struct drm_i915_privateinteldrm_softc *dev_priv)
93{
94 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
95
96 dev_priv->bridge_dev =
97 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)((0) << 3 | (0)));
98 if (!dev_priv->bridge_dev) {
99 drm_err(&dev_priv->drm, "bridge device not found\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "bridge device not found\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
100 return -1;
101 }
102 return 0;
103}
104#else
105int i915_get_bridge_dev(struct drm_i915_privateinteldrm_softc *dev_priv)
106{
107 struct drm_device *dev = &dev_priv->drm;
108
109 dev_priv->bridge_dev = malloc(sizeof(*dev_priv->bridge_dev),
110 M_DEVBUF2, M_WAITOK0x0001);
111 dev_priv->bridge_dev->pc = dev->pdev->pc;
112 dev_priv->bridge_dev->tag = pci_make_tag(dev->pdev->pc, 0, 0, 0);
113 return 0;
114}
115#endif
116
117/* Allocate space for the MCH regs if needed, return nonzero on error */
118static int
119intel_alloc_mchbar_resource(struct drm_i915_privateinteldrm_softc *dev_priv)
120{
121 int reg = INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4 ? MCHBAR_I9650x48 : MCHBAR_I9150x44;
122 u32 temp_lo, temp_hi = 0;
123 u64 mchbar_addr;
124 int ret;
125
126 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
127 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
128 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
129 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
130
131 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
132#ifdef CONFIG_PNP
133 if (mchbar_addr &&
134 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE(4 * 4096)))
135 return 0;
136#endif
137
138#ifdef __linux__
139 /* Get some space for it */
140 dev_priv->mch_res.name = "i915 MCHBAR";
141 dev_priv->mch_res.flags = IORESOURCE_MEM;
142 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
143 &dev_priv->mch_res,
144 MCHBAR_SIZE(4 * 4096), MCHBAR_SIZE(4 * 4096),
145 PCIBIOS_MIN_MEM,
146 0, pcibios_align_resource,
147 dev_priv->bridge_dev);
148 if (ret) {
149 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "failed bus alloc: %d\n"
, ret)
;
150 dev_priv->mch_res.start = 0;
151 return ret;
152 }
153#else
154 if (dev_priv->memex == NULL((void *)0) || extent_alloc(dev_priv->memex,extent_alloc_subregion((dev_priv->memex), (dev_priv->memex
)->ex_start, (dev_priv->memex)->ex_end, ((4 * 4096))
, ((4 * 4096)), (0), (0), (0), (&dev_priv->mch_res.start
))
155 MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &dev_priv->mch_res.start)extent_alloc_subregion((dev_priv->memex), (dev_priv->memex
)->ex_start, (dev_priv->memex)->ex_end, ((4 * 4096))
, ((4 * 4096)), (0), (0), (0), (&dev_priv->mch_res.start
))
) {
156 return -ENOMEM12;
157 }
158#endif
159
160 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4)
161 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
162 upper_32_bits(dev_priv->mch_res.start)((u32)(((dev_priv->mch_res.start) >> 16) >> 16
))
);
163
164 pci_write_config_dword(dev_priv->bridge_dev, reg,
165 lower_32_bits(dev_priv->mch_res.start)((u32)(dev_priv->mch_res.start)));
166 return 0;
167}
168
169/* Setup MCHBAR if possible, return true if we should disable it again */
170static void
171intel_setup_mchbar(struct drm_i915_privateinteldrm_softc *dev_priv)
172{
173 int mchbar_reg = INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4 ? MCHBAR_I9650x48 : MCHBAR_I9150x44;
174 u32 temp;
175 bool_Bool enabled;
176
177 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
178 return;
179
180 dev_priv->mchbar_need_disable = false0;
181
182 if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) {
183 pci_read_config_dword(dev_priv->bridge_dev, DEVEN0x54, &temp);
184 enabled = !!(temp & DEVEN_MCHBAR_EN(1 << 28));
185 } else {
186 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
187 enabled = temp & 1;
188 }
189
190 /* If it's already enabled, don't have to do anything */
191 if (enabled)
192 return;
193
194 if (intel_alloc_mchbar_resource(dev_priv))
195 return;
196
197 dev_priv->mchbar_need_disable = true1;
198
199 /* Space is allocated or reserved, so enable it. */
200 if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) {
201 pci_write_config_dword(dev_priv->bridge_dev, DEVEN0x54,
202 temp | DEVEN_MCHBAR_EN(1 << 28));
203 } else {
204 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
205 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
206 }
207}
208
209static void
210intel_teardown_mchbar(struct drm_i915_privateinteldrm_softc *dev_priv)
211{
212 int mchbar_reg = INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 4 ? MCHBAR_I9650x48 : MCHBAR_I9150x44;
213
214 if (dev_priv->mchbar_need_disable) {
215 if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) {
216 u32 deven_val;
217
218 pci_read_config_dword(dev_priv->bridge_dev, DEVEN0x54,
219 &deven_val);
220 deven_val &= ~DEVEN_MCHBAR_EN(1 << 28);
221 pci_write_config_dword(dev_priv->bridge_dev, DEVEN0x54,
222 deven_val);
223 } else {
224 u32 mchbar_val;
225
226 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
227 &mchbar_val);
228 mchbar_val &= ~1;
229 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
230 mchbar_val);
231 }
232 }
233
234 if (dev_priv->mch_res.start)
235#ifdef __linux__
236 release_resource(&dev_priv->mch_res);
237#else
238 extent_free(dev_priv->memex, dev_priv->mch_res.start,
239 MCHBAR_SIZE(4 * 4096), 0);
240#endif
241}
242
243static int i915_workqueues_init(struct drm_i915_privateinteldrm_softc *dev_priv)
244{
245 /*
246 * The i915 workqueue is primarily used for batched retirement of
247 * requests (and thus managing bo) once the task has been completed
248 * by the GPU. i915_retire_requests() is called directly when we
249 * need high-priority retirement, such as waiting for an explicit
250 * bo.
251 *
252 * It is also used for periodic low-priority events, such as
253 * idle-timers and recording error state.
254 *
255 * All tasks on the workqueue are expected to acquire the dev mutex
256 * so there is no point in running more than one instance of the
257 * workqueue at any time. Use an ordered one.
258 */
259 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
260 if (dev_priv->wq == NULL((void *)0))
261 goto out_err;
262
263 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
264 if (dev_priv->hotplug.dp_wq == NULL((void *)0))
265 goto out_free_wq;
266
267 return 0;
268
269out_free_wq:
270 destroy_workqueue(dev_priv->wq);
271out_err:
272 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to allocate workqueues.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
273
274 return -ENOMEM12;
275}
276
277static void i915_workqueues_cleanup(struct drm_i915_privateinteldrm_softc *dev_priv)
278{
279 destroy_workqueue(dev_priv->hotplug.dp_wq);
280 destroy_workqueue(dev_priv->wq);
281}
282
283/*
284 * We don't keep the workarounds for pre-production hardware, so we expect our
285 * driver to fail on these machines in one way or another. A little warning on
286 * dmesg may help both the user and the bug triagers.
287 *
288 * Our policy for removing pre-production workarounds is to keep the
289 * current gen workarounds as a guide to the bring-up of the next gen
290 * (workarounds have a habit of persisting!). Anything older than that
291 * should be removed along with the complications they introduce.
292 */
293static void intel_detect_preproduction_hw(struct drm_i915_privateinteldrm_softc *dev_priv)
294{
295 bool_Bool pre = false0;
296
297 pre |= IS_HSW_EARLY_SDV(dev_priv)(IS_PLATFORM(dev_priv, INTEL_HASWELL) && (((&(dev_priv
)->__runtime)->device_id) & 0xFF00) == 0x0C00)
;
298 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)(IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && (((dev_priv)
->drm.pdev->revision) >= (0) && ((dev_priv)->
drm.pdev->revision) <= (0x5)))
;
299 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST)(IS_PLATFORM(dev_priv, INTEL_BROXTON) && (((dev_priv)
->drm.pdev->revision) >= (0) && ((dev_priv)->
drm.pdev->revision) <= (0x8)))
;
300 pre |= IS_KBL_GT_REVID(dev_priv, 0, KBL_REVID_A0)(IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && kbl_revids[
((dev_priv)->drm.pdev->revision)].gt_stepping >= 0 &&
kbl_revids[((dev_priv)->drm.pdev->revision)].gt_stepping
<= KBL_REVID_A0)
;
301 pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2)(IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) && (((dev_priv
)->drm.pdev->revision) >= (0) && ((dev_priv)
->drm.pdev->revision) <= (0x2)))
;
302
303 if (pre) {
304 drm_err(&dev_priv->drm, "This is a pre-production stepping. "printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "This is a pre-production stepping. "
"It may not be fully functional.\n", ({struct cpu_info *__ci
; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__)
305 "It may not be fully functional.\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "This is a pre-production stepping. "
"It may not be fully functional.\n", ({struct cpu_info *__ci
; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__)
;
306 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
307 }
308}
309
310static void sanitize_gpu(struct drm_i915_privateinteldrm_softc *i915)
311{
312 if (!INTEL_INFO(i915)(&(i915)->__info)->gpu_reset_clobbers_display)
313 __intel_gt_reset(&i915->gt, ALL_ENGINES((intel_engine_mask_t)~0ul));
314}
315
316/**
317 * i915_driver_early_probe - setup state not requiring device access
318 * @dev_priv: device private
319 *
320 * Initialize everything that is a "SW-only" state, that is state not
321 * requiring accessing the device or exposing the driver via kernel internal
322 * or userspace interfaces. Example steps belonging here: lock initialization,
323 * system memory allocation, setting up device specific attributes and
324 * function hooks not requiring accessing the device.
325 */
326static int i915_driver_early_probe(struct drm_i915_privateinteldrm_softc *dev_priv)
327{
328 int ret = 0;
329
330 if (i915_inject_probe_failure(dev_priv)({ ((void)0); 0; }))
331 return -ENODEV19;
332
333 intel_device_info_subplatform_init(dev_priv);
334
335 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
336 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
337
338 mtx_init(&dev_priv->irq_lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&dev_priv
->irq_lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9
) ? 0x9 : ((0x9)))); } while (0)
;
339 mtx_init(&dev_priv->gpu_error.lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&dev_priv
->gpu_error.lock), ((((0x9)) > 0x0 && ((0x9)) <
0x9) ? 0x9 : ((0x9)))); } while (0)
;
340 rw_init(&dev_priv->backlight_lock, "blight")_rw_init_flags(&dev_priv->backlight_lock, "blight", 0,
((void *)0))
;
341
342 rw_init(&dev_priv->sb_lock, "sb")_rw_init_flags(&dev_priv->sb_lock, "sb", 0, ((void *)0
))
;
343 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
344
345 rw_init(&dev_priv->av_mutex, "avm")_rw_init_flags(&dev_priv->av_mutex, "avm", 0, ((void *
)0))
;
346 rw_init(&dev_priv->wm.wm_mutex, "wmm")_rw_init_flags(&dev_priv->wm.wm_mutex, "wmm", 0, ((void
*)0))
;
347 rw_init(&dev_priv->pps_mutex, "ppsm")_rw_init_flags(&dev_priv->pps_mutex, "ppsm", 0, ((void
*)0))
;
348 rw_init(&dev_priv->hdcp_comp_mutex, "hdcpc")_rw_init_flags(&dev_priv->hdcp_comp_mutex, "hdcpc", 0,
((void *)0))
;
349
350 i915_memcpy_init_early(dev_priv);
351 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
352
353 ret = i915_workqueues_init(dev_priv);
354 if (ret < 0)
355 return ret;
356
357 ret = vlv_suspend_init(dev_priv);
358 if (ret < 0)
359 goto err_workqueues;
360
361 intel_wopcm_init_early(&dev_priv->wopcm);
362
363 intel_gt_init_early(&dev_priv->gt, dev_priv);
364
365 i915_gem_init_early(dev_priv);
366
367 /* This must be called before any calls to HAS_PCH_* */
368 intel_detect_pch(dev_priv);
369
370 intel_pm_setup(dev_priv);
371 ret = intel_power_domains_init(dev_priv);
372 if (ret < 0)
373 goto err_gem;
374 intel_irq_init(dev_priv);
375 intel_init_display_hooks(dev_priv);
376 intel_init_clock_gating_hooks(dev_priv);
377 intel_init_audio_hooks(dev_priv);
378
379 intel_detect_preproduction_hw(dev_priv);
380
381 return 0;
382
383err_gem:
384 i915_gem_cleanup_early(dev_priv);
385 intel_gt_driver_late_release(&dev_priv->gt);
386 vlv_suspend_cleanup(dev_priv);
387err_workqueues:
388 i915_workqueues_cleanup(dev_priv);
389 return ret;
390}
391
392/**
393 * i915_driver_late_release - cleanup the setup done in
394 * i915_driver_early_probe()
395 * @dev_priv: device private
396 */
397static void i915_driver_late_release(struct drm_i915_privateinteldrm_softc *dev_priv)
398{
399 intel_irq_fini(dev_priv);
400 intel_power_domains_cleanup(dev_priv);
401 i915_gem_cleanup_early(dev_priv);
402 intel_gt_driver_late_release(&dev_priv->gt);
403 vlv_suspend_cleanup(dev_priv);
404 i915_workqueues_cleanup(dev_priv);
405
406 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
407 mutex_destroy(&dev_priv->sb_lock);
408
409 i915_params_free(&dev_priv->params);
410}
411
412/**
413 * i915_driver_mmio_probe - setup device MMIO
414 * @dev_priv: device private
415 *
416 * Setup minimal device state necessary for MMIO accesses later in the
417 * initialization sequence. The setup here should avoid any other device-wide
418 * side effects or exposing the driver via kernel internal or user space
419 * interfaces.
420 */
421static int i915_driver_mmio_probe(struct drm_i915_privateinteldrm_softc *dev_priv)
422{
423 int ret;
424
425 if (i915_inject_probe_failure(dev_priv)({ ((void)0); 0; }))
426 return -ENODEV19;
427
428 if (i915_get_bridge_dev(dev_priv))
429 return -EIO5;
430
431 ret = intel_uncore_init_mmio(&dev_priv->uncore);
432 if (ret < 0)
433 goto err_bridge;
434
435 /* Try to make sure MCHBAR is enabled before poking at it */
436 intel_setup_mchbar(dev_priv);
437
438 ret = intel_gt_init_mmio(&dev_priv->gt);
439 if (ret)
440 goto err_uncore;
441
442 /* As early as possible, scrub existing GPU state before clobbering */
443 sanitize_gpu(dev_priv);
444
445 return 0;
446
447err_uncore:
448 intel_teardown_mchbar(dev_priv);
449 intel_uncore_fini_mmio(&dev_priv->uncore);
450err_bridge:
451 pci_dev_put(dev_priv->bridge_dev);
452
453 return ret;
454}
455
456/**
457 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
458 * @dev_priv: device private
459 */
460static void i915_driver_mmio_release(struct drm_i915_privateinteldrm_softc *dev_priv)
461{
462 intel_teardown_mchbar(dev_priv);
463 intel_uncore_fini_mmio(&dev_priv->uncore);
464 pci_dev_put(dev_priv->bridge_dev);
465}
466
467static void intel_sanitize_options(struct drm_i915_privateinteldrm_softc *dev_priv)
468{
469 intel_gvt_sanitize_options(dev_priv);
470}
471
472/**
473 * i915_set_dma_info - set all relevant PCI dma info as configured for the
474 * platform
475 * @i915: valid i915 instance
476 *
477 * Set the dma max segment size, device and coherent masks. The dma mask set
478 * needs to occur before i915_ggtt_probe_hw.
479 *
480 * A couple of platforms have special needs. Address them as well.
481 *
482 */
483static int i915_set_dma_info(struct drm_i915_privateinteldrm_softc *i915)
484{
485 struct pci_dev *pdev = i915->drm.pdev;
486 unsigned int mask_size = INTEL_INFO(i915)(&(i915)->__info)->dma_mask_size;
Value stored to 'mask_size' during its initialization is never read
487 int ret;
488
489 GEM_BUG_ON(!mask_size)((void)0);
490
491 /*
492 * We don't have a max segment size, so set it to the max so sg's
493 * debugging layer doesn't complain
494 */
495 dma_set_max_seg_size(&pdev->dev, UINT_MAX)0;
496
497 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size))0;
498 if (ret)
499 goto mask_err;
500
501 /* overlay on gen2 is broken and can't address above 1G */
502 if (IS_GEN(i915, 2)(0 + (&(i915)->__info)->gen == (2)))
503 mask_size = 30;
504
505 /*
506 * 965GM sometimes incorrectly writes to hardware status page (HWS)
507 * using 32bit addressing, overwriting memory if HWS is located
508 * above 4GB.
509 *
510 * The documentation also mentions an issue with undefined
511 * behaviour if any general state is accessed within a page above 4GB,
512 * which also needs to be handled carefully.
513 */
514 if (IS_I965G(i915)IS_PLATFORM(i915, INTEL_I965G) || IS_I965GM(i915)IS_PLATFORM(i915, INTEL_I965GM))
515 mask_size = 32;
516
517 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size))0;
518 if (ret)
519 goto mask_err;
520
521 return 0;
522
523mask_err:
524 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Can't set DMA mask/consistent mask (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
525 return ret;
526}
527
528/**
529 * i915_driver_hw_probe - setup state requiring device access
530 * @dev_priv: device private
531 *
532 * Setup state that requires accessing the device, but doesn't require
533 * exposing the driver via kernel internal or userspace interfaces.
534 */
535static int i915_driver_hw_probe(struct drm_i915_privateinteldrm_softc *dev_priv)
536{
537 struct pci_dev *pdev = dev_priv->drm.pdev;
538 int ret;
539
540 if (i915_inject_probe_failure(dev_priv)({ ((void)0); 0; }))
541 return -ENODEV19;
542
543 intel_device_info_runtime_init(dev_priv);
544
545 if (HAS_PPGTT(dev_priv)(((&(dev_priv)->__info)->ppgtt_type) != INTEL_PPGTT_NONE
)
) {
546 if (intel_vgpu_active(dev_priv) &&
547 !intel_vgpu_has_full_ppgtt(dev_priv)) {
548 i915_report_error(dev_priv,__i915_printk(dev_priv, "\0013", "incompatible vGPU found, support for isolated ppGTT required\n"
)
549 "incompatible vGPU found, support for isolated ppGTT required\n")__i915_printk(dev_priv, "\0013", "incompatible vGPU found, support for isolated ppGTT required\n"
)
;
550 return -ENXIO6;
551 }
552 }
553
554 if (HAS_EXECLISTS(dev_priv)((&(dev_priv)->__info)->has_logical_ring_contexts)) {
555 /*
556 * Older GVT emulation depends upon intercepting CSB mmio,
557 * which we no longer use, preferring to use the HWSP cache
558 * instead.
559 */
560 if (intel_vgpu_active(dev_priv) &&
561 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
562 i915_report_error(dev_priv,__i915_printk(dev_priv, "\0013", "old vGPU host found, support for HWSP emulation required\n"
)
563 "old vGPU host found, support for HWSP emulation required\n")__i915_printk(dev_priv, "\0013", "old vGPU host found, support for HWSP emulation required\n"
)
;
564 return -ENXIO6;
565 }
566 }
567
568 intel_sanitize_options(dev_priv);
569
570 /* needs to be done before ggtt probe */
571 intel_dram_edram_detect(dev_priv);
572
573 ret = i915_set_dma_info(dev_priv);
574 if (ret)
575 return ret;
576
577 i915_perf_init(dev_priv);
578
579 ret = i915_ggtt_probe_hw(dev_priv);
580 if (ret)
581 goto err_perf;
582
583 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
584 if (ret)
585 goto err_ggtt;
586
587 ret = i915_ggtt_init_hw(dev_priv);
588 if (ret)
589 goto err_ggtt;
590
591 ret = intel_memory_regions_hw_probe(dev_priv);
592 if (ret)
593 goto err_ggtt;
594
595 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
596
597 ret = i915_ggtt_enable_hw(dev_priv);
598 if (ret) {
599 drm_err(&dev_priv->drm, "failed to enable GGTT\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to enable GGTT\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
600 goto err_mem_regions;
601 }
602
603 pci_set_master(pdev);
604
605 intel_gt_init_workarounds(dev_priv);
606
607 /* On the 945G/GM, the chipset reports the MSI capability on the
608 * integrated graphics even though the support isn't actually there
609 * according to the published specs. It doesn't appear to function
610 * correctly in testing on 945G.
611 * This may be a side effect of MSI having been made available for PEG
612 * and the registers being closely associated.
613 *
614 * According to chipset errata, on the 965GM, MSI interrupts may
615 * be lost or delayed, and was defeatured. MSI interrupts seem to
616 * get lost on g4x as well, and interrupt delivery seems to stay
617 * properly dead afterwards. So we'll just disable them for all
618 * pre-gen5 chipsets.
619 *
620 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
621 * interrupts even when in MSI mode. This results in spurious
622 * interrupt warnings if the legacy irq no. is shared with another
623 * device. The kernel then disables that interrupt source and so
624 * prevents the other device from working properly.
625 */
626 if (INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) >= 5) {
627 if (pci_enable_msi(pdev)0 < 0)
628 drm_dbg(&dev_priv->drm, "can't enable MSI")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "can't enable MSI"
)
;
629 }
630
631 ret = intel_gvt_init(dev_priv);
632 if (ret)
633 goto err_msi;
634
635 intel_opregion_setup(dev_priv);
636 /*
637 * Fill the dram structure to get the system raw bandwidth and
638 * dram info. This will be used for memory latency calculation.
639 */
640 intel_dram_detect(dev_priv);
641
642 intel_bw_init_hw(dev_priv);
643
644 return 0;
645
646err_msi:
647 if (pdev->msi_enabled)
648 pci_disable_msi(pdev);
649err_mem_regions:
650 intel_memory_regions_driver_release(dev_priv);
651err_ggtt:
652 i915_ggtt_driver_release(dev_priv);
653err_perf:
654 i915_perf_fini(dev_priv);
655 return ret;
656}
657
658/**
659 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
660 * @dev_priv: device private
661 */
662static void i915_driver_hw_remove(struct drm_i915_privateinteldrm_softc *dev_priv)
663{
664 struct pci_dev *pdev = dev_priv->drm.pdev;
665
666 i915_perf_fini(dev_priv);
667
668 if (pdev->msi_enabled)
669 pci_disable_msi(pdev);
670}
671
672/**
673 * i915_driver_register - register the driver with the rest of the system
674 * @dev_priv: device private
675 *
676 * Perform any steps necessary to make the driver available via kernel
677 * internal or userspace interfaces.
678 */
679static void i915_driver_register(struct drm_i915_privateinteldrm_softc *dev_priv)
680{
681 struct drm_device *dev = &dev_priv->drm;
682
683 i915_gem_driver_register(dev_priv);
684 i915_pmu_register(dev_priv);
685
686 intel_vgpu_register(dev_priv);
687
688 /* Reveal our presence to userspace */
689 if (drm_dev_register(dev, 0) == 0) {
690 i915_debugfs_register(dev_priv);
691 intel_display_debugfs_register(dev_priv);
692 i915_setup_sysfs(dev_priv);
693
694 /* Depends on sysfs having been initialized */
695 i915_perf_register(dev_priv);
696 } else
697 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register driver for userspace access!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
698 "Failed to register driver for userspace access!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register driver for userspace access!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
699
700 if (HAS_DISPLAY(dev_priv)((&(dev_priv)->__info)->pipe_mask != 0)) {
701 /* Must be done after probing outputs */
702 intel_opregion_register(dev_priv);
703 acpi_video_register();
704 }
705
706 intel_gt_driver_register(&dev_priv->gt);
707
708 intel_audio_init(dev_priv);
709
710 /*
711 * Some ports require correctly set-up hpd registers for detection to
712 * work properly (leading to ghost connected connector status), e.g. VGA
713 * on gm45. Hence we can only set up the initial fbdev config after hpd
714 * irqs are fully enabled. We do it last so that the async config
715 * cannot run before the connectors are registered.
716 */
717 intel_fbdev_initial_config_async(dev);
718
719 /*
720 * We need to coordinate the hotplugs with the asynchronous fbdev
721 * configuration, for which we use the fbdev->async_cookie.
722 */
723 if (HAS_DISPLAY(dev_priv)((&(dev_priv)->__info)->pipe_mask != 0))
724 drm_kms_helper_poll_init(dev);
725
726 intel_power_domains_enable(dev_priv);
727 intel_runtime_pm_enable(&dev_priv->runtime_pm);
728
729 intel_register_dsm_handler();
730
731 if (i915_switcheroo_register(dev_priv))
732 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register vga switcheroo!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
733}
734
735/**
736 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
737 * @dev_priv: device private
738 */
739static void i915_driver_unregister(struct drm_i915_privateinteldrm_softc *dev_priv)
740{
741 i915_switcheroo_unregister(dev_priv);
742
743 intel_unregister_dsm_handler();
744
745 intel_runtime_pm_disable(&dev_priv->runtime_pm);
746 intel_power_domains_disable(dev_priv);
747
748 intel_fbdev_unregister(dev_priv);
749 intel_audio_deinit(dev_priv);
750
751 /*
752 * After flushing the fbdev (incl. a late async config which will
753 * have delayed queuing of a hotplug event), then flush the hotplug
754 * events.
755 */
756 drm_kms_helper_poll_fini(&dev_priv->drm);
757
758 intel_gt_driver_unregister(&dev_priv->gt);
759 acpi_video_unregister();
760 intel_opregion_unregister(dev_priv);
761
762 i915_perf_unregister(dev_priv);
763 i915_pmu_unregister(dev_priv);
764
765 i915_teardown_sysfs(dev_priv);
766 drm_dev_unplug(&dev_priv->drm);
767
768 i915_gem_driver_unregister(dev_priv);
769}
770
771static void i915_welcome_messages(struct drm_i915_privateinteldrm_softc *dev_priv)
772{
773 if (drm_debug_enabled(DRM_UT_DRIVER)) {
774 struct drm_printer p = drm_debug_printer("i915 device info:");
775
776 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
777 INTEL_DEVID(dev_priv)((&(dev_priv)->__runtime)->device_id),
778 INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision),
779 intel_platform_name(INTEL_INFO(dev_priv)(&(dev_priv)->__info)->platform),
780 intel_subplatform(RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime),
781 INTEL_INFO(dev_priv)(&(dev_priv)->__info)->platform),
782 INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen));
783
784 intel_device_info_print_static(INTEL_INFO(dev_priv)(&(dev_priv)->__info), &p);
785 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime), &p);
786 intel_gt_info_print(&dev_priv->gt.info, &p);
787 }
788
789 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)0)
790 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n")do { } while(0);
791 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)0)
792 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n")do { } while(0);
793 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)0)
794 drm_info(&dev_priv->drm,do { } while(0)
795 "DRM_I915_DEBUG_RUNTIME_PM enabled\n")do { } while(0);
796}
797
798static struct drm_i915_privateinteldrm_softc *
799i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
800{
801 STUB()do { printf("%s: stub\n", __func__); } while(0);
802 return ERR_PTR(-ENOSYS78);
803#ifdef notyet
804 const struct intel_device_info *match_info =
805 (struct intel_device_info *)ent->driver_data;
806 struct intel_device_info *device_info;
807 struct drm_i915_privateinteldrm_softc *i915;
808
809 i915 = devm_drm_dev_alloc(&pdev->dev, &driver,((struct inteldrm_softc *) __devm_drm_dev_alloc(&pdev->
dev, &driver, sizeof(struct inteldrm_softc), __builtin_offsetof
(struct inteldrm_softc, drm)))
810 struct drm_i915_private, drm)((struct inteldrm_softc *) __devm_drm_dev_alloc(&pdev->
dev, &driver, sizeof(struct inteldrm_softc), __builtin_offsetof
(struct inteldrm_softc, drm)))
;
811 if (IS_ERR(i915))
812 return i915;
813
814 i915->drm.pdev = pdev;
815 pci_set_drvdata(pdev, i915);
816
817 /* Device parameters start as a copy of module parameters. */
818 i915_params_copy(&i915->params, &i915_modparams);
819
820 /* Setup the write-once "constant" device info */
821 device_info = mkwrite_device_info(i915);
822 memcpy(device_info, match_info, sizeof(*device_info))__builtin_memcpy((device_info), (match_info), (sizeof(*device_info
)))
;
823 RUNTIME_INFO(i915)(&(i915)->__runtime)->device_id = pdev->device;
824
825 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask))((!(device_info->gen > (8 * sizeof(device_info->gen_mask
)))) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/i915/i915_drv.c"
, 825, "!(device_info->gen > (8 * sizeof(device_info->gen_mask)))"
))
;
826
827 return i915;
828#endif
829}
830
831#ifdef __linux__
832
833/**
834 * i915_driver_probe - setup chip and create an initial config
835 * @pdev: PCI device
836 * @ent: matching PCI ID entry
837 *
838 * The driver probe routine has to do several things:
839 * - drive output discovery via intel_modeset_init()
840 * - initialize the memory manager
841 * - allocate initial config memory
842 * - setup the DRM framebuffer with the allocated memory
843 */
844int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
845{
846 const struct intel_device_info *match_info =
847 (struct intel_device_info *)ent->driver_data;
848 struct drm_i915_privateinteldrm_softc *i915;
849 int ret;
850
851 i915 = i915_driver_create(pdev, ent);
852 if (IS_ERR(i915))
853 return PTR_ERR(i915);
854
855 /* Disable nuclear pageflip by default on pre-ILK */
856 if (!i915->params.nuclear_pageflip && match_info->gen < 5)
857 i915->drm.driver_features &= ~DRIVER_ATOMIC;
858
859 /*
860 * Check if we support fake LMEM -- for now we only unleash this for
861 * the live selftests(test-and-exit).
862 */
863#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)0
864 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)0) {
865 if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 9 && i915_selftest.live < 0 &&
866 i915->params.fake_lmem_start) {
867 mkwrite_device_info(i915)->memory_regions =
868 REGION_SMEM(1UL << (INTEL_REGION_SMEM)) | REGION_LMEM(1UL << (INTEL_REGION_LMEM)) | REGION_STOLEN(1UL << (INTEL_REGION_STOLEN));
869 mkwrite_device_info(i915)->is_dgfx = true1;
870 GEM_BUG_ON(!HAS_LMEM(i915))((void)0);
871 GEM_BUG_ON(!IS_DGFX(i915))((void)0);
872 }
873 }
874#endif
875
876 ret = pci_enable_device(pdev)0;
877 if (ret)
878 goto out_fini;
879
880 ret = i915_driver_early_probe(i915);
881 if (ret < 0)
882 goto out_pci_disable;
883
884 disable_rpm_wakeref_asserts(&i915->runtime_pm);
885
886 intel_vgpu_detect(i915);
887
888 ret = i915_driver_mmio_probe(i915);
889 if (ret < 0)
890 goto out_runtime_pm_put;
891
892 ret = i915_driver_hw_probe(i915);
893 if (ret < 0)
894 goto out_cleanup_mmio;
895
896 ret = intel_modeset_init_noirq(i915);
897 if (ret < 0)
898 goto out_cleanup_hw;
899
900 ret = intel_irq_install(i915);
901 if (ret)
902 goto out_cleanup_modeset;
903
904 ret = intel_modeset_init_nogem(i915);
905 if (ret)
906 goto out_cleanup_irq;
907
908 ret = i915_gem_init(i915);
909 if (ret)
910 goto out_cleanup_modeset2;
911
912 ret = intel_modeset_init(i915);
913 if (ret)
914 goto out_cleanup_gem;
915
916 i915_driver_register(i915);
917
918 enable_rpm_wakeref_asserts(&i915->runtime_pm);
919
920 i915_welcome_messages(i915);
921
922 i915->do_release = true1;
923
924 return 0;
925
926out_cleanup_gem:
927 i915_gem_suspend(i915);
928 i915_gem_driver_remove(i915);
929 i915_gem_driver_release(i915);
930out_cleanup_modeset2:
931 /* FIXME clean up the error path */
932 intel_modeset_driver_remove(i915);
933 intel_irq_uninstall(i915);
934 intel_modeset_driver_remove_noirq(i915);
935 goto out_cleanup_modeset;
936out_cleanup_irq:
937 intel_irq_uninstall(i915);
938out_cleanup_modeset:
939 intel_modeset_driver_remove_nogem(i915);
940out_cleanup_hw:
941 i915_driver_hw_remove(i915);
942 intel_memory_regions_driver_release(i915);
943 i915_ggtt_driver_release(i915);
944out_cleanup_mmio:
945 i915_driver_mmio_release(i915);
946out_runtime_pm_put:
947 enable_rpm_wakeref_asserts(&i915->runtime_pm);
948 i915_driver_late_release(i915);
949out_pci_disable:
950 pci_disable_device(pdev);
951out_fini:
952 i915_probe_error(i915, "Device initialization failed (%d)\n", ret)__i915_printk(i915, 0 ? "\0017" : "\0013", "Device initialization failed (%d)\n"
, ret)
;
953 return ret;
954}
955
956#else /* !__linux__ */
957
958void inteldrm_init_backlight(struct inteldrm_softc *);
959
960/**
961 * i915_driver_probe - setup chip and create an initial config
962 * @pdev: PCI device
963 * @ent: matching PCI ID entry
964 *
965 * The driver probe routine has to do several things:
966 * - drive output discovery via intel_modeset_init()
967 * - initialize the memory manager
968 * - allocate initial config memory
969 * - setup the DRM framebuffer with the allocated memory
970 */
971int i915_driver_probe(struct drm_i915_privateinteldrm_softc *i915, const struct pci_device_id *ent)
972{
973 const struct intel_device_info *match_info =
974 (struct intel_device_info *)ent->driver_data;
975#ifdef __linux__
976 struct drm_i915_privateinteldrm_softc *i915;
977#endif
978 int ret;
979
980#ifdef __linux
981 i915 = i915_driver_create(pdev, ent);
982 if (IS_ERR(i915))
983 return PTR_ERR(i915);
984#endif
985
986 /* Disable nuclear pageflip by default on pre-ILK */
987 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
988 i915->drm.driver_features &= ~DRIVER_ATOMIC;
989
990 /*
991 * Check if we support fake LMEM -- for now we only unleash this for
992 * the live selftests(test-and-exit).
993 */
994#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)0
995 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)0) {
996 if (INTEL_GEN(i915)((&(i915)->__info)->gen) >= 9 && i915_selftest.live < 0 &&
997 i915_modparams.fake_lmem_start) {
998 mkwrite_device_info(i915)->memory_regions =
999 REGION_SMEM(1UL << (INTEL_REGION_SMEM)) | REGION_LMEM(1UL << (INTEL_REGION_LMEM)) | REGION_STOLEN(1UL << (INTEL_REGION_STOLEN));
1000 mkwrite_device_info(i915)->is_dgfx = true1;
1001 GEM_BUG_ON(!HAS_LMEM(i915))((void)0);
1002 GEM_BUG_ON(!IS_DGFX(i915))((void)0);
1003 }
1004 }
1005#endif
1006
1007 ret = pci_enable_device(pdev)0;
1008 if (ret)
1009 goto out_fini;
1010
1011 ret = i915_driver_early_probe(i915);
1012 if (ret < 0)
1013 goto out_pci_disable;
1014
1015 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1016
1017 intel_vgpu_detect(i915);
1018
1019 ret = i915_driver_mmio_probe(i915);
1020 if (ret < 0)
1021 goto out_runtime_pm_put;
1022
1023 ret = i915_driver_hw_probe(i915);
1024 if (ret < 0)
1025 goto out_cleanup_mmio;
1026
1027 ret = intel_modeset_init_noirq(i915);
1028 if (ret < 0)
1029 goto out_cleanup_hw;
1030
1031 ret = intel_irq_install(i915);
1032 if (ret)
1033 goto out_cleanup_modeset;
1034
1035 ret = intel_modeset_init_nogem(i915);
1036 if (ret)
1037 goto out_cleanup_irq;
1038
1039 ret = i915_gem_init(i915);
1040 if (ret)
1041 goto out_cleanup_modeset2;
1042
1043 ret = intel_modeset_init(i915);
1044 if (ret)
1045 goto out_cleanup_gem;
1046
1047 i915_driver_register(i915);
1048
1049#ifdef __OpenBSD__1
1050 inteldrm_init_backlight(i915);
1051#endif
1052
1053 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1054
1055 i915_welcome_messages(i915);
1056
1057 i915->do_release = true1;
1058
1059 return 0;
1060
1061out_cleanup_gem:
1062 i915_gem_suspend(i915);
1063 i915_gem_driver_remove(i915);
1064 i915_gem_driver_release(i915);
1065out_cleanup_modeset2:
1066 /* FIXME clean up the error path */
1067 intel_modeset_driver_remove(i915);
1068 intel_irq_uninstall(i915);
1069 intel_modeset_driver_remove_noirq(i915);
1070 goto out_cleanup_modeset;
1071out_cleanup_irq:
1072 intel_irq_uninstall(i915);
1073out_cleanup_modeset:
1074 intel_modeset_driver_remove_nogem(i915);
1075out_cleanup_hw:
1076 i915_driver_hw_remove(i915);
1077 intel_memory_regions_driver_release(i915);
1078 i915_ggtt_driver_release(i915);
1079out_cleanup_mmio:
1080 i915_driver_mmio_release(i915);
1081out_runtime_pm_put:
1082 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1083 i915_driver_late_release(i915);
1084out_pci_disable:
1085 pci_disable_device(pdev);
1086out_fini:
1087 i915_probe_error(i915, "Device initialization failed (%d)\n", ret)__i915_printk(i915, 0 ? "\0017" : "\0013", "Device initialization failed (%d)\n"
, ret)
;
1088 return ret;
1089}
1090
1091#endif /* !__linux__ */
1092
1093void i915_driver_remove(struct drm_i915_privateinteldrm_softc *i915)
1094{
1095 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1096
1097 i915_driver_unregister(i915);
1098
1099 /* Flush any external code that still may be under the RCU lock */
1100 synchronize_rcu();
1101
1102 i915_gem_suspend(i915);
1103
1104 drm_atomic_helper_shutdown(&i915->drm);
1105
1106 intel_gvt_driver_remove(i915);
1107
1108 intel_modeset_driver_remove(i915);
1109
1110 intel_irq_uninstall(i915);
1111
1112 intel_modeset_driver_remove_noirq(i915);
1113
1114 i915_reset_error_state(i915);
1115 i915_gem_driver_remove(i915);
1116
1117 intel_modeset_driver_remove_nogem(i915);
1118
1119 i915_driver_hw_remove(i915);
1120
1121 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1122}
1123
1124static void i915_driver_release(struct drm_device *dev)
1125{
1126 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1127 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1128
1129 if (!dev_priv->do_release)
1130 return;
1131
1132 disable_rpm_wakeref_asserts(rpm);
1133
1134 i915_gem_driver_release(dev_priv);
1135
1136 intel_memory_regions_driver_release(dev_priv);
1137 i915_ggtt_driver_release(dev_priv);
1138 i915_gem_drain_freed_objects(dev_priv);
1139
1140 i915_driver_mmio_release(dev_priv);
1141
1142 enable_rpm_wakeref_asserts(rpm);
1143 intel_runtime_pm_driver_release(rpm);
1144
1145 i915_driver_late_release(dev_priv);
1146}
1147
1148static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1149{
1150 struct drm_i915_privateinteldrm_softc *i915 = to_i915(dev);
1151 int ret;
1152
1153 ret = i915_gem_open(i915, file);
1154 if (ret)
1155 return ret;
1156
1157 return 0;
1158}
1159
1160/**
1161 * i915_driver_lastclose - clean up after all DRM clients have exited
1162 * @dev: DRM device
1163 *
1164 * Take care of cleaning up after all DRM clients have exited. In the
1165 * mode setting case, we want to restore the kernel's initial mode (just
1166 * in case the last client left us in a bad state).
1167 *
1168 * Additionally, in the non-mode setting case, we'll tear down the GTT
1169 * and DMA structures, since the kernel won't be using them, and clea
1170 * up any GEM state.
1171 */
1172static void i915_driver_lastclose(struct drm_device *dev)
1173{
1174 intel_fbdev_restore_mode(dev);
1175 vga_switcheroo_process_delayed_switch();
1176}
1177
1178static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1179{
1180 struct drm_i915_file_private *file_priv = file->driver_priv;
1181
1182 i915_gem_context_close(file);
1183
1184 kfree_rcu(file_priv, rcu)do { free((void *)file_priv, 145, 0); } while(0);
1185
1186 /* Catch up with all the deferred frees from "this" client */
1187 i915_gem_flush_free_objects(to_i915(dev));
1188}
1189
1190static void intel_suspend_encoders(struct drm_i915_privateinteldrm_softc *dev_priv)
1191{
1192 struct drm_device *dev = &dev_priv->drm;
1193 struct intel_encoder *encoder;
1194
1195 drm_modeset_lock_all(dev);
1196 for_each_intel_encoder(dev, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->
base.head ) *__mptr = ((&(dev)->mode_config.encoder_list
)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*encoder), base.head) );}); &encoder->base.head
!= (&(dev)->mode_config.encoder_list); encoder = ({ const
__typeof( ((__typeof(*encoder) *)0)->base.head ) *__mptr =
(encoder->base.head.next); (__typeof(*encoder) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) )
;}))
1197 if (encoder->suspend)
1198 encoder->suspend(encoder);
1199 drm_modeset_unlock_all(dev);
1200}
1201
1202static bool_Bool suspend_to_idle(struct drm_i915_privateinteldrm_softc *dev_priv)
1203{
1204#if IS_ENABLED(CONFIG_ACPI_SLEEP)0
1205 if (acpi_target_system_state() < ACPI_STATE_S33)
1206 return true1;
1207#endif
1208 return false0;
1209}
1210
1211static int i915_drm_prepare(struct drm_device *dev)
1212{
1213 struct drm_i915_privateinteldrm_softc *i915 = to_i915(dev);
1214
1215 /*
1216 * NB intel_display_suspend() may issue new requests after we've
1217 * ostensibly marked the GPU as ready-to-sleep here. We need to
1218 * split out that work and pull it forward so that after point,
1219 * the GPU is not woken again.
1220 */
1221 i915_gem_suspend(i915);
1222
1223 return 0;
1224}
1225
1226static int i915_drm_suspend(struct drm_device *dev)
1227{
1228 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1229 struct pci_dev *pdev = dev_priv->drm.pdev;
1230 pci_power_t opregion_target_state;
1231
1232 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1233
1234 /* We do a lot of poking in a lot of registers, make sure they work
1235 * properly. */
1236 intel_power_domains_disable(dev_priv);
1237
1238 drm_kms_helper_poll_disable(dev);
1239
1240 pci_save_state(pdev);
1241
1242 intel_display_suspend(dev);
1243
1244 intel_dp_mst_suspend(dev_priv);
1245
1246 intel_runtime_pm_disable_interrupts(dev_priv);
1247 intel_hpd_cancel_work(dev_priv);
1248
1249 intel_suspend_encoders(dev_priv);
1250
1251 intel_suspend_hw(dev_priv);
1252
1253 i915_ggtt_suspend(&dev_priv->ggtt);
1254
1255 i915_save_state(dev_priv);
1256
1257 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1258 intel_opregion_suspend(dev_priv, opregion_target_state);
1259
1260 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED1, true1);
1261
1262 dev_priv->suspend_count++;
1263
1264 intel_csr_ucode_suspend(dev_priv);
1265
1266 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1267
1268 return 0;
1269}
1270
1271static enum i915_drm_suspend_mode
1272get_suspend_mode(struct drm_i915_privateinteldrm_softc *dev_priv, bool_Bool hibernate)
1273{
1274 if (hibernate)
1275 return I915_DRM_SUSPEND_HIBERNATE;
1276
1277 if (suspend_to_idle(dev_priv))
1278 return I915_DRM_SUSPEND_IDLE;
1279
1280 return I915_DRM_SUSPEND_MEM;
1281}
1282
1283static int i915_drm_suspend_late(struct drm_device *dev, bool_Bool hibernation)
1284{
1285 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1286 struct pci_dev *pdev = dev_priv->drm.pdev;
1287 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1288 int ret;
1289
1290 disable_rpm_wakeref_asserts(rpm);
1291
1292 i915_gem_suspend_late(dev_priv);
1293
1294 intel_uncore_suspend(&dev_priv->uncore);
1295
1296 intel_power_domains_suspend(dev_priv,
1297 get_suspend_mode(dev_priv, hibernation));
1298
1299 intel_display_power_suspend_late(dev_priv);
1300
1301 ret = vlv_suspend_complete(dev_priv);
1302 if (ret) {
1303 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspend complete failed: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1304 intel_power_domains_resume(dev_priv);
1305
1306 goto out;
1307 }
1308
1309 pci_disable_device(pdev);
1310 /*
1311 * During hibernation on some platforms the BIOS may try to access
1312 * the device even though it's already in D3 and hang the machine. So
1313 * leave the device in D0 on those platforms and hope the BIOS will
1314 * power down the device properly. The issue was seen on multiple old
1315 * GENs with different BIOS vendors, so having an explicit blacklist
1316 * is inpractical; apply the workaround on everything pre GEN6. The
1317 * platforms where the issue was seen:
1318 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1319 * Fujitsu FSC S7110
1320 * Acer Aspire 1830T
1321 */
1322 if (!(hibernation && INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen) < 6))
1323 pci_set_power_state(pdev, PCI_D3hot);
1324
1325out:
1326 enable_rpm_wakeref_asserts(rpm);
1327 if (!dev_priv->uncore.user_forcewake_count)
1328 intel_runtime_pm_driver_release(rpm);
1329
1330 return ret;
1331}
1332
1333#ifdef __linux__
1334int i915_suspend_switcheroo(struct drm_i915_privateinteldrm_softc *i915, pm_message_t state)
1335{
1336 int error;
1337
1338 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&({ static int __warned; int __ret = !!((state.event != PM_EVENT_SUSPEND
&& state.event != PM_EVENT_FREEZE)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
i915->drm))->dev), "", "drm_WARN_ON_ONCE(" "state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
1339 state.event != PM_EVENT_FREEZE)({ static int __warned; int __ret = !!((state.event != PM_EVENT_SUSPEND
&& state.event != PM_EVENT_FREEZE)); if (__ret &&
!__warned) { printf("%s %s: " "%s", dev_driver_string(((&
i915->drm))->dev), "", "drm_WARN_ON_ONCE(" "state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
)
1340 return -EINVAL22;
1341
1342 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1343 return 0;
1344
1345 error = i915_drm_suspend(&i915->drm);
1346 if (error)
1347 return error;
1348
1349 return i915_drm_suspend_late(&i915->drm, false0);
1350}
1351#endif
1352
1353static int i915_drm_resume(struct drm_device *dev)
1354{
1355 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1356 int ret;
1357
1358 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1359
1360 sanitize_gpu(dev_priv);
1361
1362 ret = i915_ggtt_enable_hw(dev_priv);
1363 if (ret)
1364 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to re-enable GGTT\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1365
1366 i915_ggtt_resume(&dev_priv->ggtt);
1367
1368 intel_csr_ucode_resume(dev_priv);
1369
1370 i915_restore_state(dev_priv);
1371 intel_pps_unlock_regs_wa(dev_priv);
1372
1373 intel_init_pch_refclk(dev_priv);
1374
1375 /*
1376 * Interrupts have to be enabled before any batches are run. If not the
1377 * GPU will hang. i915_gem_init_hw() will initiate batches to
1378 * update/restore the context.
1379 *
1380 * drm_mode_config_reset() needs AUX interrupts.
1381 *
1382 * Modeset enabling in intel_modeset_init_hw() also needs working
1383 * interrupts.
1384 */
1385 intel_runtime_pm_enable_interrupts(dev_priv);
1386
1387 drm_mode_config_reset(dev);
1388
1389 i915_gem_resume(dev_priv);
1390
1391 intel_modeset_init_hw(dev_priv);
1392 intel_init_clock_gating(dev_priv);
1393
1394 spin_lock_irq(&dev_priv->irq_lock)mtx_enter(&dev_priv->irq_lock);
1395 if (dev_priv->display.hpd_irq_setup)
1396 dev_priv->display.hpd_irq_setup(dev_priv);
1397 spin_unlock_irq(&dev_priv->irq_lock)mtx_leave(&dev_priv->irq_lock);
1398
1399 intel_dp_mst_resume(dev_priv);
1400
1401 intel_display_resume(dev);
1402
1403 drm_kms_helper_poll_enable(dev);
1404
1405 /*
1406 * ... but also need to make sure that hotplug processing
1407 * doesn't cause havoc. Like in the driver load code we don't
1408 * bother with the tiny race here where we might lose hotplug
1409 * notifications.
1410 * */
1411 intel_hpd_init(dev_priv);
1412
1413 intel_opregion_resume(dev_priv);
1414
1415 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING0, false0);
1416
1417 intel_power_domains_enable(dev_priv);
1418
1419 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1420
1421 return 0;
1422}
1423
1424static int i915_drm_resume_early(struct drm_device *dev)
1425{
1426 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1427 struct pci_dev *pdev = dev_priv->drm.pdev;
1428 int ret;
1429
1430 /*
1431 * We have a resume ordering issue with the snd-hda driver also
1432 * requiring our device to be power up. Due to the lack of a
1433 * parent/child relationship we currently solve this with an early
1434 * resume hook.
1435 *
1436 * FIXME: This should be solved with a special hdmi sink device or
1437 * similar so that power domains can be employed.
1438 */
1439
1440 /*
1441 * Note that we need to set the power state explicitly, since we
1442 * powered off the device during freeze and the PCI core won't power
1443 * it back up for us during thaw. Powering off the device during
1444 * freeze is not a hard requirement though, and during the
1445 * suspend/resume phases the PCI core makes sure we get here with the
1446 * device powered on. So in case we change our freeze logic and keep
1447 * the device powered we can also remove the following set power state
1448 * call.
1449 */
1450 ret = pci_set_power_state(pdev, PCI_D0);
1451 if (ret) {
1452 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to set PCI D0 power state (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
1453 "failed to set PCI D0 power state (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to set PCI D0 power state (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1454 return ret;
1455 }
1456
1457 /*
1458 * Note that pci_enable_device() first enables any parent bridge
1459 * device and only then sets the power state for this device. The
1460 * bridge enabling is a nop though, since bridge devices are resumed
1461 * first. The order of enabling power and enabling the device is
1462 * imposed by the PCI core as described above, so here we preserve the
1463 * same order for the freeze/thaw phases.
1464 *
1465 * TODO: eventually we should remove pci_disable_device() /
1466 * pci_enable_enable_device() from suspend/resume. Due to how they
1467 * depend on the device enable refcount we can't anyway depend on them
1468 * disabling/enabling the device.
1469 */
1470 if (pci_enable_device(pdev)0)
1471 return -EIO5;
1472
1473 pci_set_master(pdev);
1474
1475 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1476
1477 ret = vlv_resume_prepare(dev_priv, false0);
1478 if (ret)
1479 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Resume prepare failed: %d, continuing anyway\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
1480 "Resume prepare failed: %d, continuing anyway\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Resume prepare failed: %d, continuing anyway\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1481
1482 intel_uncore_resume_early(&dev_priv->uncore);
1483
1484 intel_gt_check_and_clear_faults(&dev_priv->gt);
1485
1486 intel_display_power_resume_early(dev_priv);
1487
1488 intel_power_domains_resume(dev_priv);
1489
1490 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1491
1492 return ret;
1493}
1494
1495int i915_resume_switcheroo(struct drm_i915_privateinteldrm_softc *i915)
1496{
1497 int ret;
1498
1499 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1500 return 0;
1501
1502 ret = i915_drm_resume_early(&i915->drm);
1503 if (ret)
1504 return ret;
1505
1506 return i915_drm_resume(&i915->drm);
1507}
1508
1509static int i915_pm_prepare(struct device *kdev)
1510{
1511 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1512
1513 if (!i915) {
1514 dev_err(kdev, "DRM not initialized, aborting suspend.\n")printf("drm:pid%d:%s *ERROR* " "DRM not initialized, aborting suspend.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1515 return -ENODEV19;
1516 }
1517
1518 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1519 return 0;
1520
1521 return i915_drm_prepare(&i915->drm);
1522}
1523
1524static int i915_pm_suspend(struct device *kdev)
1525{
1526 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1527
1528 if (!i915) {
1529 dev_err(kdev, "DRM not initialized, aborting suspend.\n")printf("drm:pid%d:%s *ERROR* " "DRM not initialized, aborting suspend.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1530 return -ENODEV19;
1531 }
1532
1533 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1534 return 0;
1535
1536 return i915_drm_suspend(&i915->drm);
1537}
1538
1539static int i915_pm_suspend_late(struct device *kdev)
1540{
1541 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1542
1543 /*
1544 * We have a suspend ordering issue with the snd-hda driver also
1545 * requiring our device to be power up. Due to the lack of a
1546 * parent/child relationship we currently solve this with an late
1547 * suspend hook.
1548 *
1549 * FIXME: This should be solved with a special hdmi sink device or
1550 * similar so that power domains can be employed.
1551 */
1552 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1553 return 0;
1554
1555 return i915_drm_suspend_late(&i915->drm, false0);
1556}
1557
1558static int i915_pm_poweroff_late(struct device *kdev)
1559{
1560 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1561
1562 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1563 return 0;
1564
1565 return i915_drm_suspend_late(&i915->drm, true1);
1566}
1567
1568static int i915_pm_resume_early(struct device *kdev)
1569{
1570 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1571
1572 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1573 return 0;
1574
1575 return i915_drm_resume_early(&i915->drm);
1576}
1577
1578static int i915_pm_resume(struct device *kdev)
1579{
1580 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1581
1582 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1583 return 0;
1584
1585 return i915_drm_resume(&i915->drm);
1586}
1587
1588/* freeze: before creating the hibernation_image */
1589static int i915_pm_freeze(struct device *kdev)
1590{
1591 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1592 int ret;
1593
1594 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1595 ret = i915_drm_suspend(&i915->drm);
1596 if (ret)
1597 return ret;
1598 }
1599
1600 ret = i915_gem_freeze(i915);
1601 if (ret)
1602 return ret;
1603
1604 return 0;
1605}
1606
1607static int i915_pm_freeze_late(struct device *kdev)
1608{
1609 struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev);
1610 int ret;
1611
1612 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1613 ret = i915_drm_suspend_late(&i915->drm, true1);
1614 if (ret)
1615 return ret;
1616 }
1617
1618 ret = i915_gem_freeze_late(i915);
1619 if (ret)
1620 return ret;
1621
1622 return 0;
1623}
1624
1625/* thaw: called after creating the hibernation image, but before turning off. */
1626static int i915_pm_thaw_early(struct device *kdev)
1627{
1628 return i915_pm_resume_early(kdev);
1629}
1630
1631static int i915_pm_thaw(struct device *kdev)
1632{
1633 return i915_pm_resume(kdev);
1634}
1635
1636/* restore: called after loading the hibernation image. */
1637static int i915_pm_restore_early(struct device *kdev)
1638{
1639 return i915_pm_resume_early(kdev);
1640}
1641
1642static int i915_pm_restore(struct device *kdev)
1643{
1644 return i915_pm_resume(kdev);
1645}
1646
1647#ifdef __linux__
1648
1649static int intel_runtime_suspend(struct device *kdev)
1650{
1651 struct drm_i915_privateinteldrm_softc *dev_priv = kdev_to_i915(kdev);
1652 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1653 int ret;
1654
1655 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))({ static int __warned; int __ret = !!((!((&(dev_priv)->
__info)->has_runtime_pm))); if (__ret && !__warned
) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON_ONCE(" "!((&(dev_priv)->__info)->has_runtime_pm)"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
)
1656 return -ENODEV19;
1657
1658 drm_dbg_kms(&dev_priv->drm, "Suspending device\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Suspending device\n"
)
;
1659
1660 disable_rpm_wakeref_asserts(rpm);
1661
1662 /*
1663 * We are safe here against re-faults, since the fault handler takes
1664 * an RPM reference.
1665 */
1666 i915_gem_runtime_suspend(dev_priv);
1667
1668 intel_gt_runtime_suspend(&dev_priv->gt);
1669
1670 intel_runtime_pm_disable_interrupts(dev_priv);
1671
1672 intel_uncore_suspend(&dev_priv->uncore);
1673
1674 intel_display_power_suspend(dev_priv);
1675
1676 ret = vlv_suspend_complete(dev_priv);
1677 if (ret) {
1678 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime suspend failed, disabling it (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
1679 "Runtime suspend failed, disabling it (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime suspend failed, disabling it (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1680 intel_uncore_runtime_resume(&dev_priv->uncore);
1681
1682 intel_runtime_pm_enable_interrupts(dev_priv);
1683
1684 intel_gt_runtime_resume(&dev_priv->gt);
1685
1686 enable_rpm_wakeref_asserts(rpm);
1687
1688 return ret;
1689 }
1690
1691 enable_rpm_wakeref_asserts(rpm);
1692 intel_runtime_pm_driver_release(rpm);
1693
1694 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1695 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unclaimed access detected prior to suspending\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
1696 "Unclaimed access detected prior to suspending\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unclaimed access detected prior to suspending\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
1697
1698 rpm->suspended = true1;
1699
1700 /*
1701 * FIXME: We really should find a document that references the arguments
1702 * used below!
1703 */
1704 if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) {
1705 /*
1706 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1707 * being detected, and the call we do at intel_runtime_resume()
1708 * won't be able to restore them. Since PCI_D3hot matches the
1709 * actual specification and appears to be working, use it.
1710 */
1711 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1712 } else {
1713 /*
1714 * current versions of firmware which depend on this opregion
1715 * notification have repurposed the D1 definition to mean
1716 * "runtime suspended" vs. what you would normally expect (D3)
1717 * to distinguish it from notifications that might be sent via
1718 * the suspend path.
1719 */
1720 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1721 }
1722
1723 assert_forcewakes_inactive(&dev_priv->uncore);
1724
1725 if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
1726 intel_hpd_poll_init(dev_priv);
1727
1728 drm_dbg_kms(&dev_priv->drm, "Device suspended\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Device suspended\n"
)
;
1729 return 0;
1730}
1731
1732static int intel_runtime_resume(struct device *kdev)
1733{
1734 struct drm_i915_privateinteldrm_softc *dev_priv = kdev_to_i915(kdev);
1735 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1736 int ret;
1737
1738 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))({ static int __warned; int __ret = !!((!((&(dev_priv)->
__info)->has_runtime_pm))); if (__ret && !__warned
) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv->
drm))->dev), "", "drm_WARN_ON_ONCE(" "!((&(dev_priv)->__info)->has_runtime_pm)"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
)
1739 return -ENODEV19;
1740
1741 drm_dbg_kms(&dev_priv->drm, "Resuming device\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Resuming device\n"
)
;
1742
1743 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count))({ static int __warned; int __ret = !!((({ typeof(*(&rpm->
wakeref_count)) __tmp = *(volatile typeof(*(&rpm->wakeref_count
)) *)&(*(&rpm->wakeref_count)); membar_datadep_consumer
(); __tmp; }))); if (__ret && !__warned) { printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON_ONCE(" "({ typeof(*(&rpm->wakeref_count)) __tmp = *(volatile typeof(*(&rpm->wakeref_count)) *)&(*(&rpm->wakeref_count)); membar_datadep_consumer(); __tmp; })"
")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })
;
1744 disable_rpm_wakeref_asserts(rpm);
1745
1746 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1747 rpm->suspended = false0;
1748 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1749 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unclaimed access during suspend, bios?\n"
)
1750 "Unclaimed access during suspend, bios?\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "Unclaimed access during suspend, bios?\n"
)
;
1751
1752 intel_display_power_resume(dev_priv);
1753
1754 ret = vlv_resume_prepare(dev_priv, true1);
1755
1756 intel_uncore_runtime_resume(&dev_priv->uncore);
1757
1758 intel_runtime_pm_enable_interrupts(dev_priv);
1759
1760 /*
1761 * No point of rolling back things in case of an error, as the best
1762 * we can do is to hope that things will still work (and disable RPM).
1763 */
1764 intel_gt_runtime_resume(&dev_priv->gt);
1765
1766 /*
1767 * On VLV/CHV display interrupts are part of the display
1768 * power well, so hpd is reinitialized from there. For
1769 * everyone else do it here.
1770 */
1771 if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW))
1772 intel_hpd_init(dev_priv);
1773
1774 intel_enable_ipc(dev_priv);
1775
1776 enable_rpm_wakeref_asserts(rpm);
1777
1778 if (ret)
1779 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime resume failed, disabling it (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
1780 "Runtime resume failed, disabling it (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime resume failed, disabling it (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret)
;
1781 else
1782 drm_dbg_kms(&dev_priv->drm, "Device resumed\n")drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_KMS, "Device resumed\n"
)
;
1783
1784 return ret;
1785}
1786
1787const struct dev_pm_ops i915_pm_ops = {
1788 /*
1789 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1790 * PMSG_RESUME]
1791 */
1792 .prepare = i915_pm_prepare,
1793 .suspend = i915_pm_suspend,
1794 .suspend_late = i915_pm_suspend_late,
1795 .resume_early = i915_pm_resume_early,
1796 .resume = i915_pm_resume,
1797
1798 /*
1799 * S4 event handlers
1800 * @freeze, @freeze_late : called (1) before creating the
1801 * hibernation image [PMSG_FREEZE] and
1802 * (2) after rebooting, before restoring
1803 * the image [PMSG_QUIESCE]
1804 * @thaw, @thaw_early : called (1) after creating the hibernation
1805 * image, before writing it [PMSG_THAW]
1806 * and (2) after failing to create or
1807 * restore the image [PMSG_RECOVER]
1808 * @poweroff, @poweroff_late: called after writing the hibernation
1809 * image, before rebooting [PMSG_HIBERNATE]
1810 * @restore, @restore_early : called after rebooting and restoring the
1811 * hibernation image [PMSG_RESTORE]
1812 */
1813 .freeze = i915_pm_freeze,
1814 .freeze_late = i915_pm_freeze_late,
1815 .thaw_early = i915_pm_thaw_early,
1816 .thaw = i915_pm_thaw,
1817 .poweroff = i915_pm_suspend,
1818 .poweroff_late = i915_pm_poweroff_late,
1819 .restore_early = i915_pm_restore_early,
1820 .restore = i915_pm_restore,
1821
1822 /* S0ix (via runtime suspend) event handlers */
1823 .runtime_suspend = intel_runtime_suspend,
1824 .runtime_resume = intel_runtime_resume,
1825};
1826
1827static const struct file_operations i915_driver_fops = {
1828 .owner = THIS_MODULE((void *)0),
1829 .open = drm_open,
1830 .release = drm_release_noglobal,
1831 .unlocked_ioctl = drm_ioctl,
1832 .mmap = i915_gem_mmap,
1833 .poll = drm_poll,
1834 .read = drm_read,
1835 .compat_ioctl = i915_ioc32_compat_ioctl((void *)0),
1836 .llseek = noop_llseek,
1837};
1838
1839#endif /* __linux__ */
1840
1841static int
1842i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *file)
1844{
1845 return -ENODEV19;
1846}
1847
1848static const struct drm_ioctl_desc i915_ioctls[] = {
1849 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_init_t) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x00)
))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_init_t) & 0x1fff) << 16) | (((
'd')) << 8) | ((0x40 + 0x00))), .func = drm_noop, .flags
= DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_INIT" }
,
1850 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x01)))) & 0xff) - 0x40
] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x01))), .func = drm_noop
, .flags = DRM_AUTH, .name = "I915_FLUSH" }
,
1851 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x02)))) & 0xff) - 0x40
] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x02))), .func = drm_noop
, .flags = DRM_AUTH, .name = "I915_FLIP" }
,
1852 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_batchbuffer_t
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x03)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_batchbuffer_t) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x03))), .func = drm_noop
, .flags = DRM_AUTH, .name = "I915_BATCHBUFFER" }
,
1853 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(drm_i915_irq_emit_t) & 0x1fff) << 16) | (((
'd')) << 8) | ((0x40 + 0x04)))) & 0xff) - 0x40] = {
.cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(drm_i915_irq_emit_t) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x04))), .func = drm_noop, .
flags = DRM_AUTH, .name = "I915_IRQ_EMIT" }
,
1854 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_irq_wait_t)
& 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x05)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_irq_wait_t) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x05))), .func = drm_noop, .
flags = DRM_AUTH, .name = "I915_IRQ_WAIT" }
,
1855 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(drm_i915_getparam_t) & 0x1fff) << 16) | (((
'd')) << 8) | ((0x40 + 0x06)))) & 0xff) - 0x40] = {
.cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(drm_i915_getparam_t) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x06))), .func = i915_getparam_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GETPARAM" }
,
1856 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_setparam_t)
& 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x07)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_setparam_t) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x07))), .func = drm_noop, .
flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_SETPARAM"
}
,
1857 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(drm_i915_mem_alloc_t) & 0x1fff) << 16) | ((
('d')) << 8) | ((0x40 + 0x08)))) & 0xff) - 0x40] = {
.cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(drm_i915_mem_alloc_t) & 0x1fff) << 16)
| ((('d')) << 8) | ((0x40 + 0x08))), .func = drm_noop,
.flags = DRM_AUTH, .name = "I915_ALLOC" }
,
1858 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_free_t)
& 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x09)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_mem_free_t) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x09))), .func = drm_noop, .
flags = DRM_AUTH, .name = "I915_FREE" }
,
1859 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_init_heap_t
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x0a)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_mem_init_heap_t) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x0a))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_INIT_HEAP"
}
,
1860 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_cmdbuffer_t
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x0b)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_cmdbuffer_t) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x0b))), .func = drm_noop, .
flags = DRM_AUTH, .name = "I915_CMDBUFFER" }
,
1861 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_destroy_heap_t
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x0c)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_mem_destroy_heap_t) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x0c))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_DESTROY_HEAP"
}
,
1862 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_vblank_pipe_t
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x0d)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(drm_i915_vblank_pipe_t) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x0d))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_SET_VBLANK_PIPE"
}
,
1863 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH)[((((unsigned long)0x40000000 | ((sizeof(drm_i915_vblank_pipe_t
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x0e)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x40000000
| ((sizeof(drm_i915_vblank_pipe_t) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x0e))), .func = drm_noop
, .flags = DRM_AUTH, .name = "I915_GET_VBLANK_PIPE" }
,
1864 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(drm_i915_vblank_swap_t) & 0x1fff) << 16) | (
(('d')) << 8) | ((0x40 + 0x0f)))) & 0xff) - 0x40] =
{ .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(drm_i915_vblank_swap_t) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x0f))), .func = drm_noop
, .flags = DRM_AUTH, .name = "I915_VBLANK_SWAP" }
,
1865 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_init
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x11)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_init) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x11))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_HWS_ADDR"
}
,
1866 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_init
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x13)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_init) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x13))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_GEM_INIT"
}
,
1867 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_execbuffer
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x14)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_execbuffer) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x14))), .func = i915_gem_execbuffer_ioctl
, .flags = DRM_AUTH, .name = "I915_GEM_EXECBUFFER" }
,
1868 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_execbuffer2) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x29)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_execbuffer2) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x29)
)), .func = i915_gem_execbuffer2_ioctl, .flags = DRM_RENDER_ALLOW
, .name = "I915_GEM_EXECBUFFER2_WR" }
,
1869 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_pin) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x15)))) & 0xff) - 0x40]
= { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_pin) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x15))), .func = i915_gem_reject_pin_ioctl
, .flags = DRM_AUTH|DRM_ROOT_ONLY, .name = "I915_GEM_PIN" }
,
1870 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_unpin
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x16)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_unpin) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x16))), .func = i915_gem_reject_pin_ioctl
, .flags = DRM_AUTH|DRM_ROOT_ONLY, .name = "I915_GEM_UNPIN" }
,
1871 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_busy) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x17)))) & 0xff) - 0x40]
= { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_busy) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x17))), .func = i915_gem_busy_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_BUSY" }
,
1872 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_caching
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x2f)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_caching) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x2f))), .func = i915_gem_set_caching_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SET_CACHING" }
,
1873 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_caching) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x30)))) & 0xff) - 0x40
] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_caching) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x30))), .func = i915_gem_get_caching_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_GET_CACHING" }
,
1874 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x18)))) & 0xff) - 0x40
] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x18))), .func = i915_gem_throttle_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_THROTTLE" }
,
1875 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x19)))) & 0xff) - 0x40
] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x19))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_GEM_ENTERVT"
}
,
1876 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x1a)))) & 0xff) - 0x40
] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x1a))), .func = drm_noop
, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_GEM_LEAVEVT"
}
,
1877 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_create) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x1b)))) & 0xff) - 0x40
] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_create) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x1b))), .func = i915_gem_create_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_CREATE" }
,
1878 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_pread
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x1c)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_pread) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x1c))), .func = i915_gem_pread_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_PREAD" }
,
1879 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_pwrite
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x1d)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_pwrite) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x1d))), .func = i915_gem_pwrite_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_PWRITE" }
,
1880 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_mmap) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x1e)))) & 0xff) - 0x40]
= { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_mmap) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x1e))), .func = i915_gem_mmap_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_MMAP" }
,
1881 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_mmap_offset) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x24)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_mmap_offset) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x24)
)), .func = i915_gem_mmap_offset_ioctl, .flags = DRM_RENDER_ALLOW
, .name = "I915_GEM_MMAP_OFFSET" }
,
1882 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_set_domain
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x1f)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_set_domain) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x1f))), .func = i915_gem_set_domain_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SET_DOMAIN" }
,
1883 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_sw_finish
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x20)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_sw_finish) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x20))), .func = i915_gem_sw_finish_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SW_FINISH" }
,
1884 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_set_tiling) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x21)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_set_tiling) & 0x1fff
) << 16) | ((('d')) << 8) | ((0x40 + 0x21))), .func
= i915_gem_set_tiling_ioctl, .flags = DRM_RENDER_ALLOW, .name
= "I915_GEM_SET_TILING" }
,
1885 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_get_tiling) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x22)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_get_tiling) & 0x1fff
) << 16) | ((('d')) << 8) | ((0x40 + 0x22))), .func
= i915_gem_get_tiling_ioctl, .flags = DRM_RENDER_ALLOW, .name
= "I915_GEM_GET_TILING" }
,
1886 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x40000000 | ((sizeof(struct drm_i915_gem_get_aperture
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x23)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x40000000
| ((sizeof(struct drm_i915_gem_get_aperture) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x23))), .func = i915_gem_get_aperture_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_GET_APERTURE" }
,
1887 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_get_pipe_from_crtc_id) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x25)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_get_pipe_from_crtc_id)
& 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x25))), .func = intel_get_pipe_from_crtc_id_ioctl, .flags =
0, .name = "I915_GET_PIPE_FROM_CRTC_ID" }
,
1888 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_madvise) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x26)))) & 0xff) - 0x40
] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_madvise) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x26))), .func = i915_gem_madvise_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_MADVISE" }
,
1889 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER)[((((unsigned long)0x80000000 | ((sizeof(struct drm_intel_overlay_put_image
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x27)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_intel_overlay_put_image) & 0x1fff)
<< 16) | ((('d')) << 8) | ((0x40 + 0x27))), .func
= intel_overlay_put_image_ioctl, .flags = DRM_MASTER, .name =
"I915_OVERLAY_PUT_IMAGE" }
,
1890 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_intel_overlay_attrs) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x28)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_intel_overlay_attrs) & 0x1fff
) << 16) | ((('d')) << 8) | ((0x40 + 0x28))), .func
= intel_overlay_attrs_ioctl, .flags = DRM_MASTER, .name = "I915_OVERLAY_ATTRS"
}
,
1891 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_intel_sprite_colorkey) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x2b)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_intel_sprite_colorkey) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2b)
)), .func = intel_sprite_set_colorkey_ioctl, .flags = DRM_MASTER
, .name = "I915_SET_SPRITE_COLORKEY" }
,
1892 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_intel_sprite_colorkey) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x2a)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_intel_sprite_colorkey) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2a)
)), .func = drm_noop, .flags = DRM_MASTER, .name = "I915_GET_SPRITE_COLORKEY"
}
,
1893 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_wait) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x2c)))) & 0xff) - 0x40]
= { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_wait) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x2c))), .func = i915_gem_wait_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_WAIT" }
,
1894 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_context_create_ext) & 0x1fff)
<< 16) | ((('d')) << 8) | ((0x40 + 0x2d)))) &
0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned
long)0x40000000) | ((sizeof(struct drm_i915_gem_context_create_ext
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x2d))), .func = i915_gem_context_create_ioctl, .flags = DRM_RENDER_ALLOW
, .name = "I915_GEM_CONTEXT_CREATE_EXT" }
,
1895 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_context_destroy
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x2e)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_context_destroy) & 0x1fff
) << 16) | ((('d')) << 8) | ((0x40 + 0x2e))), .func
= i915_gem_context_destroy_ioctl, .flags = DRM_RENDER_ALLOW,
.name = "I915_GEM_CONTEXT_DESTROY" }
,
1896 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_reg_read) & 0x1fff) << 16) |
((('d')) << 8) | ((0x40 + 0x31)))) & 0xff) - 0x40]
= { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_reg_read) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x31))), .func = i915_reg_read_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_REG_READ" }
,
1897 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_reset_stats) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x32)))) & 0xff) - 0x40
] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_reset_stats) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x32))), .func = i915_gem_context_reset_stats_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GET_RESET_STATS" }
,
1898 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_userptr) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x33)))) & 0xff) - 0x40
] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_gem_userptr) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x33))), .func = i915_gem_userptr_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_USERPTR" }
,
1899 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_context_param) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x34)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_context_param) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x34)
)), .func = i915_gem_context_getparam_ioctl, .flags = DRM_RENDER_ALLOW
, .name = "I915_GEM_CONTEXT_GETPARAM" }
,
1900 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_context_param) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x35)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_context_param) &
0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x35)
)), .func = i915_gem_context_setparam_ioctl, .flags = DRM_RENDER_ALLOW
, .name = "I915_GEM_CONTEXT_SETPARAM" }
,
1901 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_perf_open_param
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x36)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_perf_open_param) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x36))), .func = i915_perf_open_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_PERF_OPEN" }
,
1902 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_perf_oa_config
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x37)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_perf_oa_config) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x37))), .func = i915_perf_add_config_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_PERF_ADD_CONFIG" }
,
1903 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(__u64) & 0x1fff)
<< 16) | ((('d')) << 8) | ((0x40 + 0x38)))) &
0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof
(__u64) & 0x1fff) << 16) | ((('d')) << 8) | (
(0x40 + 0x38))), .func = i915_perf_remove_config_ioctl, .flags
= DRM_RENDER_ALLOW, .name = "I915_PERF_REMOVE_CONFIG" }
,
1904 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_query) & 0x1fff) << 16) | (
(('d')) << 8) | ((0x40 + 0x39)))) & 0xff) - 0x40] =
{ .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000
) | ((sizeof(struct drm_i915_query) & 0x1fff) << 16
) | ((('d')) << 8) | ((0x40 + 0x39))), .func = i915_query_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_QUERY" }
,
1905 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | (
(sizeof(struct drm_i915_gem_vm_control) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x3a)))) & 0xff) -
0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)
0x40000000) | ((sizeof(struct drm_i915_gem_vm_control) & 0x1fff
) << 16) | ((('d')) << 8) | ((0x40 + 0x3a))), .func
= i915_gem_vm_create_ioctl, .flags = DRM_RENDER_ALLOW, .name
= "I915_GEM_VM_CREATE" }
,
1906 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_vm_control
) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 +
0x3b)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000
| ((sizeof(struct drm_i915_gem_vm_control) & 0x1fff) <<
16) | ((('d')) << 8) | ((0x40 + 0x3b))), .func = i915_gem_vm_destroy_ioctl
, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_VM_DESTROY" }
,
1907};
1908
1909static struct drm_driver driver = {
1910 /* Don't use MTRRs here; the Xserver or userspace app should
1911 * deal with them for Intel hardware.
1912 */
1913 .driver_features =
1914 DRIVER_GEM |
1915 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1916 DRIVER_SYNCOBJ_TIMELINE,
1917 .release = i915_driver_release,
1918 .open = i915_driver_open,
1919 .lastclose = i915_driver_lastclose,
1920 .postclose = i915_driver_postclose,
1921
1922 .gem_close_object = i915_gem_close_object,
1923 .gem_free_object_unlocked = i915_gem_free_object,
1924
1925 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1926 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1927 .gem_prime_export = i915_gem_prime_export,
1928 .gem_prime_import = i915_gem_prime_import,
1929
1930 .dumb_create = i915_gem_dumb_create,
1931 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1932
1933#ifdef __OpenBSD__1
1934 .mmap = i915_gem_mmap,
1935 .gem_fault = i915_gem_fault,
1936#endif
1937
1938 .ioctls = i915_ioctls,
1939 .num_ioctls = ARRAY_SIZE(i915_ioctls)(sizeof((i915_ioctls)) / sizeof((i915_ioctls)[0])),
1940#ifdef __linux__
1941 .fops = &i915_driver_fops,
1942#endif
1943 .name = DRIVER_NAME"i915",
1944 .desc = DRIVER_DESC"Intel Graphics",
1945 .date = DRIVER_DATE"20200917",
1946 .major = DRIVER_MAJOR1,
1947 .minor = DRIVER_MINOR6,
1948 .patchlevel = DRIVER_PATCHLEVEL0,
1949};
1950
1951#ifdef __OpenBSD__1
1952
1953#include <drm/drm_agpsupport.h>
1954#include <drm/drm_utils.h>
1955
1956#include "i915_globals.h"
1957
1958#ifdef __amd64__1
1959#include "efifb.h"
1960#include <machine/biosvar.h>
1961#endif
1962
1963#if NEFIFB1 > 0
1964#include <machine/efifbvar.h>
1965#endif
1966
1967#include "intagp.h"
1968
1969#if NINTAGP1 > 0
1970int intagpsubmatch(struct device *, void *, void *);
1971int intagp_print(void *, const char *);
1972
1973/*
1974 * some functions are only called once on init regardless of how many times
1975 * inteldrm attaches in linux this is handled via module_init()/module_exit()
1976 */
1977int inteldrm_refcnt;
1978
1979int
1980intagpsubmatch(struct device *parent, void *match, void *aux)
1981{
1982 extern struct cfdriver intagp_cd;
1983 struct cfdata *cf = match;
1984
1985 /* only allow intagp to attach */
1986 if (cf->cf_driver == &intagp_cd)
1987 return ((*cf->cf_attach->ca_match)(parent, match, aux));
1988 return (0);
1989}
1990
1991int
1992intagp_print(void *vaa, const char *pnp)
1993{
1994 if (pnp)
1995 printf("intagp at %s", pnp);
1996 return (UNCONF1);
1997}
1998#endif
1999
2000int inteldrm_wsioctl(void *, u_long, caddr_t, int, struct proc *);
2001paddr_t inteldrm_wsmmap(void *, off_t, int);
2002int inteldrm_alloc_screen(void *, const struct wsscreen_descr *,
2003 void **, int *, int *, uint32_t *);
2004void inteldrm_free_screen(void *, void *);
2005int inteldrm_show_screen(void *, void *, int,
2006 void (*)(void *, int, int), void *);
2007void inteldrm_doswitch(void *);
2008void inteldrm_enter_ddb(void *, void *);
2009int inteldrm_load_font(void *, void *, struct wsdisplay_font *);
2010int inteldrm_list_font(void *, struct wsdisplay_font *);
2011int inteldrm_getchar(void *, int, int, struct wsdisplay_charcell *);
2012void inteldrm_burner(void *, u_int, u_int);
2013void inteldrm_burner_cb(void *);
2014void inteldrm_scrollback(void *, void *, int lines);
2015extern const struct pci_device_id pciidlist[];
2016
2017struct wsscreen_descr inteldrm_stdscreen = {
2018 "std",
2019 0, 0,
2020 0,
2021 0, 0,
2022 WSSCREEN_UNDERLINE16 | WSSCREEN_HILIT4 |
2023 WSSCREEN_REVERSE2 | WSSCREEN_WSCOLORS1
2024};
2025
2026const struct wsscreen_descr *inteldrm_scrlist[] = {
2027 &inteldrm_stdscreen,
2028};
2029
2030struct wsscreen_list inteldrm_screenlist = {
2031 nitems(inteldrm_scrlist)(sizeof((inteldrm_scrlist)) / sizeof((inteldrm_scrlist)[0])), inteldrm_scrlist
2032};
2033
2034struct wsdisplay_accessops inteldrm_accessops = {
2035 .ioctl = inteldrm_wsioctl,
2036 .mmap = inteldrm_wsmmap,
2037 .alloc_screen = inteldrm_alloc_screen,
2038 .free_screen = inteldrm_free_screen,
2039 .show_screen = inteldrm_show_screen,
2040 .enter_ddb = inteldrm_enter_ddb,
2041 .getchar = inteldrm_getchar,
2042 .load_font = inteldrm_load_font,
2043 .list_font = inteldrm_list_font,
2044 .scrollback = inteldrm_scrollback,
2045 .burn_screen = inteldrm_burner
2046};
2047
2048int
2049inteldrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p)
2050{
2051 struct inteldrm_softc *dev_priv = v;
2052 struct backlight_device *bd = dev_priv->backlight;
2053 struct rasops_info *ri = &dev_priv->ro;
2054 struct wsdisplay_fbinfo *wdf;
2055 struct wsdisplay_param *dp = (struct wsdisplay_param *)data;
2056
2057 switch (cmd) {
2058 case WSDISPLAYIO_GTYPE((unsigned long)0x40000000 | ((sizeof(u_int) & 0x1fff) <<
16) | ((('W')) << 8) | ((64)))
:
2059 *(u_int *)data = WSDISPLAY_TYPE_INTELDRM69;
2060 return 0;
2061 case WSDISPLAYIO_GINFO((unsigned long)0x40000000 | ((sizeof(struct wsdisplay_fbinfo
) & 0x1fff) << 16) | ((('W')) << 8) | ((65)))
:
2062 wdf = (struct wsdisplay_fbinfo *)data;
2063 wdf->width = ri->ri_width;
2064 wdf->height = ri->ri_height;
2065 wdf->depth = ri->ri_depth;
2066 wdf->cmsize = 0;
2067 return 0;
2068 case WSDISPLAYIO_GETPARAM(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct wsdisplay_param) & 0x1fff) << 16) | ((('W')
) << 8) | ((89)))
:
2069 if (ws_get_param && ws_get_param(dp) == 0)
2070 return 0;
2071
2072 if (bd == NULL((void *)0))
2073 return -1;
2074
2075 switch (dp->param) {
2076 case WSDISPLAYIO_PARAM_BRIGHTNESS2:
2077 dp->min = 0;
2078 dp->max = bd->props.max_brightness;
2079 dp->curval = bd->ops->get_brightness(bd);
2080 return (dp->max > dp->min) ? 0 : -1;
2081 }
2082 break;
2083 case WSDISPLAYIO_SETPARAM(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct wsdisplay_param) & 0x1fff) << 16) | ((('W')
) << 8) | ((90)))
:
2084 if (ws_set_param && ws_set_param(dp) == 0)
2085 return 0;
2086
2087 if (bd == NULL((void *)0) || dp->curval > bd->props.max_brightness)
2088 return -1;
2089
2090 switch (dp->param) {
2091 case WSDISPLAYIO_PARAM_BRIGHTNESS2:
2092 bd->props.brightness = dp->curval;
2093 backlight_update_status(bd);
2094 return 0;
2095 }
2096 break;
2097 }
2098
2099 return (-1);
2100}
2101
2102paddr_t
2103inteldrm_wsmmap(void *v, off_t off, int prot)
2104{
2105 return (-1);
2106}
2107
2108int
2109inteldrm_alloc_screen(void *v, const struct wsscreen_descr *type,
2110 void **cookiep, int *curxp, int *curyp, uint32_t *attrp)
2111{
2112 struct inteldrm_softc *dev_priv = v;
2113 struct rasops_info *ri = &dev_priv->ro;
2114
2115 return rasops_alloc_screen(ri, cookiep, curxp, curyp, attrp);
2116}
2117
2118void
2119inteldrm_free_screen(void *v, void *cookie)
2120{
2121 struct inteldrm_softc *dev_priv = v;
2122 struct rasops_info *ri = &dev_priv->ro;
2123
2124 return rasops_free_screen(ri, cookie);
2125}
2126
2127int
2128inteldrm_show_screen(void *v, void *cookie, int waitok,
2129 void (*cb)(void *, int, int), void *cbarg)
2130{
2131 struct inteldrm_softc *dev_priv = v;
2132 struct rasops_info *ri = &dev_priv->ro;
2133
2134 if (cookie == ri->ri_active)
2135 return (0);
2136
2137 dev_priv->switchcb = cb;
2138 dev_priv->switchcbarg = cbarg;
2139 dev_priv->switchcookie = cookie;
2140 if (cb) {
2141 task_add(systq, &dev_priv->switchtask);
2142 return (EAGAIN35);
2143 }
2144
2145 inteldrm_doswitch(v);
2146
2147 return (0);
2148}
2149
2150void
2151inteldrm_doswitch(void *v)
2152{
2153 struct inteldrm_softc *dev_priv = v;
2154 struct rasops_info *ri = &dev_priv->ro;
2155 struct drm_device *dev = &dev_priv->drm;
2156
2157 rasops_show_screen(ri, dev_priv->switchcookie, 0, NULL((void *)0), NULL((void *)0));
2158 intel_fbdev_restore_mode(dev);
2159
2160 if (dev_priv->switchcb)
2161 (*dev_priv->switchcb)(dev_priv->switchcbarg, 0, 0);
2162}
2163
2164void
2165inteldrm_enter_ddb(void *v, void *cookie)
2166{
2167 struct inteldrm_softc *dev_priv = v;
2168 struct rasops_info *ri = &dev_priv->ro;
2169 struct drm_device *dev = &dev_priv->drm;
2170
2171 if (cookie == ri->ri_active)
2172 return;
2173
2174 rasops_show_screen(ri, cookie, 0, NULL((void *)0), NULL((void *)0));
2175 intel_fbdev_restore_mode(dev);
2176}
2177
2178int
2179inteldrm_getchar(void *v, int row, int col, struct wsdisplay_charcell *cell)
2180{
2181 struct inteldrm_softc *dev_priv = v;
2182 struct rasops_info *ri = &dev_priv->ro;
2183
2184 return rasops_getchar(ri, row, col, cell);
2185}
2186
2187int
2188inteldrm_load_font(void *v, void *cookie, struct wsdisplay_font *font)
2189{
2190 struct inteldrm_softc *dev_priv = v;
2191 struct rasops_info *ri = &dev_priv->ro;
2192
2193 return rasops_load_font(ri, cookie, font);
2194}
2195
2196int
2197inteldrm_list_font(void *v, struct wsdisplay_font *font)
2198{
2199 struct inteldrm_softc *dev_priv = v;
2200 struct rasops_info *ri = &dev_priv->ro;
2201
2202 return rasops_list_font(ri, font);
2203}
2204
2205void
2206inteldrm_burner(void *v, u_int on, u_int flags)
2207{
2208 struct inteldrm_softc *dev_priv = v;
2209
2210 task_del(systq, &dev_priv->burner_task);
2211
2212 if (on)
2213 dev_priv->burner_fblank = FB_BLANK_UNBLANK0;
2214 else {
2215 if (flags & WSDISPLAY_BURN_VBLANK0x0001)
2216 dev_priv->burner_fblank = FB_BLANK_VSYNC_SUSPEND3;
2217 else
2218 dev_priv->burner_fblank = FB_BLANK_NORMAL1;
2219 }
2220
2221 /*
2222 * Setting the DPMS mode may sleep while waiting for the display
2223 * to come back on so hand things off to a taskq.
2224 */
2225 task_add(systq, &dev_priv->burner_task);
2226}
2227
2228void
2229inteldrm_burner_cb(void *arg1)
2230{
2231 struct inteldrm_softc *dev_priv = arg1;
2232 struct drm_fb_helper *helper = &dev_priv->fbdev->helper;
2233
2234 drm_fb_helper_blank(dev_priv->burner_fblank, helper->fbdev);
2235}
2236
2237int
2238inteldrm_backlight_update_status(struct backlight_device *bd)
2239{
2240 struct wsdisplay_param dp;
2241
2242 dp.param = WSDISPLAYIO_PARAM_BRIGHTNESS2;
2243 dp.curval = bd->props.brightness;
2244 ws_set_param(&dp);
2245 return 0;
2246}
2247
2248int
2249inteldrm_backlight_get_brightness(struct backlight_device *bd)
2250{
2251 struct wsdisplay_param dp;
2252
2253 dp.param = WSDISPLAYIO_PARAM_BRIGHTNESS2;
2254 ws_get_param(&dp);
2255 return dp.curval;
2256}
2257
2258const struct backlight_ops inteldrm_backlight_ops = {
2259 .update_status = inteldrm_backlight_update_status,
2260 .get_brightness = inteldrm_backlight_get_brightness
2261};
2262
2263void
2264inteldrm_scrollback(void *v, void *cookie, int lines)
2265{
2266 struct inteldrm_softc *dev_priv = v;
2267 struct rasops_info *ri = &dev_priv->ro;
2268
2269 rasops_scrollback(ri, cookie, lines);
2270}
2271
2272int inteldrm_match(struct device *, void *, void *);
2273void inteldrm_attach(struct device *, struct device *, void *);
2274int inteldrm_detach(struct device *, int);
2275int inteldrm_activate(struct device *, int);
2276void inteldrm_attachhook(struct device *);
2277
2278struct cfattach inteldrm_ca = {
2279 sizeof(struct inteldrm_softc), inteldrm_match, inteldrm_attach,
2280 inteldrm_detach, inteldrm_activate
2281};
2282
2283struct cfdriver inteldrm_cd = {
2284 0, "inteldrm", DV_DULL
2285};
2286
2287int inteldrm_intr(void *);
2288
2289/*
2290 * Set if the mountroot hook has a fatal error.
2291 */
2292int inteldrm_fatal_error;
2293
2294int
2295inteldrm_match(struct device *parent, void *match, void *aux)
2296{
2297 struct pci_attach_args *pa = aux;
2298 const struct pci_device_id *id;
2299 struct intel_device_info *info;
2300
2301 if (inteldrm_fatal_error)
2302 return 0;
2303
2304 id = drm_find_description(PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff),
2305 PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff), pciidlist);
2306 if (id != NULL((void *)0)) {
2307 info = (struct intel_device_info *)id->driver_data;
2308 if (info->require_force_probe == 0 &&
2309 pa->pa_function == 0)
2310 return 20;
2311 }
2312
2313 return 0;
2314}
2315
2316int drm_gem_init(struct drm_device *);
2317
2318void
2319inteldrm_attach(struct device *parent, struct device *self, void *aux)
2320{
2321 struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self;
2322 struct drm_device *dev;
2323 struct pci_attach_args *pa = aux;
2324 const struct pci_device_id *id;
2325 struct intel_device_info *info, *device_info;
2326 extern int vga_console_attached;
2327 int mmio_bar, mmio_size, mmio_type;
2328 int ret;
2329
2330 dev_priv->pc = pa->pa_pc;
2331 dev_priv->tag = pa->pa_tag;
2332 dev_priv->dmat = pa->pa_dmat;
2333 dev_priv->bst = pa->pa_memt;
2334 dev_priv->memex = pa->pa_memex;
2335 dev_priv->vga_regs = &dev_priv->bar;
2336
2337 if (PCI_CLASS(pa->pa_class)(((pa->pa_class) >> 24) & 0xff) == PCI_CLASS_DISPLAY0x03 &&
2338 PCI_SUBCLASS(pa->pa_class)(((pa->pa_class) >> 16) & 0xff) == PCI_SUBCLASS_DISPLAY_VGA0x00 &&
2339 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04)
2340 & (PCI_COMMAND_IO_ENABLE0x00000001 | PCI_COMMAND_MEM_ENABLE0x00000002))
2341 == (PCI_COMMAND_IO_ENABLE0x00000001 | PCI_COMMAND_MEM_ENABLE0x00000002)) {
2342 dev_priv->primary = 1;
2343 dev_priv->console = vga_is_console(pa->pa_iot, -1);;
2344 vga_console_attached = 1;
2345 }
2346
2347#if NEFIFB1 > 0
2348 if (efifb_is_primary(pa)) {
2349 dev_priv->primary = 1;
2350 dev_priv->console = efifb_is_console(pa);
2351 efifb_detach();
2352 }
2353#endif
2354
2355 printf("\n");
2356
2357 dev = drm_attach_pci(&driver, pa, 0, dev_priv->primary,
2358 self, &dev_priv->drm);
2359
2360 id = drm_find_description(PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff),
2361 PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff), pciidlist);
2362 dev_priv->id = id;
2363 info = (struct intel_device_info *)id->driver_data;
2364
2365 /* Setup the write-once "constant" device info */
2366 device_info = mkwrite_device_info(dev_priv);
2367 memcpy(device_info, info, sizeof(*device_info))__builtin_memcpy((device_info), (info), (sizeof(*device_info)
))
;
2368 RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->device_id = dev->pdev->device;
2369
2370 mmio_bar = IS_GEN(dev_priv, 2)(0 + (&(dev_priv)->__info)->gen == (2)) ? 0x14 : 0x10;
2371 /* Before gen4, the registers and the GTT are behind different BARs.
2372 * However, from gen4 onwards, the registers and the GTT are shared
2373 * in the same BAR, so we want to restrict this ioremap from
2374 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
2375 * the register BAR remains the same size for all the earlier
2376 * generations up to Ironlake.
2377 */
2378 if (info->gen < 5)
2379 mmio_size = 512*1024;
2380 else
2381 mmio_size = 2*1024*1024;
2382
2383 mmio_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, mmio_bar);
2384 if (pci_mapreg_map(pa, mmio_bar, mmio_type, BUS_SPACE_MAP_LINEAR0x0002,
2385 &dev_priv->vga_regs->bst, &dev_priv->vga_regs->bsh,
2386 &dev_priv->vga_regs->base, &dev_priv->vga_regs->size, mmio_size)) {
2387 printf("%s: can't map registers\n",
2388 dev_priv->sc_dev.dv_xname);
2389 return;
2390 }
2391 dev_priv->uncore.regs = bus_space_vaddr(dev_priv->vga_regs->bst,((dev_priv->vga_regs->bst)->vaddr((dev_priv->vga_regs
->bsh)))
2392 dev_priv->vga_regs->bsh)((dev_priv->vga_regs->bst)->vaddr((dev_priv->vga_regs
->bsh)))
;
2393 if (dev_priv->uncore.regs == NULL((void *)0)) {
2394 printf("%s: bus_space_vaddr registers failed\n",
2395 dev_priv->sc_dev.dv_xname);
2396 return;
2397 }
2398
2399#if NINTAGP1 > 0
2400 if (info->gen <= 5) {
2401 config_found_sm(self, aux, intagp_print, intagpsubmatch);
2402 dev->agp = drm_agp_init();
2403 if (dev->agp) {
2404 if (drm_mtrr_add(dev->agp->info.ai_aperture_base,
2405 dev->agp->info.ai_aperture_size, DRM_MTRR_WC(1<<1)) == 0)
2406 dev->agp->mtrr = 1;
2407 }
2408 }
2409#endif
2410
2411 if (info->gen < 5)
2412 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED0x20;
2413
2414 if (pci_intr_map_msi(pa, &dev_priv->ih) != 0 &&
2415 pci_intr_map(pa, &dev_priv->ih) != 0) {
2416 printf("%s: couldn't map interrupt\n",
2417 dev_priv->sc_dev.dv_xname);
2418 return;
2419 }
2420
2421 printf("%s: %s, %s, gen %d\n", dev_priv->sc_dev.dv_xname,
2422 pci_intr_string(dev_priv->pc, dev_priv->ih),
2423 intel_platform_name(INTEL_INFO(dev_priv)(&(dev_priv)->__info)->platform),
2424 INTEL_GEN(dev_priv)((&(dev_priv)->__info)->gen));
2425
2426 dev_priv->irqh = pci_intr_establish(dev_priv->pc, dev_priv->ih,
2427 IPL_TTY0x9, inteldrm_intr, dev_priv, dev_priv->sc_dev.dv_xname);
2428 if (dev_priv->irqh == NULL((void *)0)) {
2429 printf("%s: couldn't establish interrupt\n",
2430 dev_priv->sc_dev.dv_xname);
2431 return;
2432 }
2433 dev->pdev->irq = -1;
2434
2435 config_mountroot(self, inteldrm_attachhook);
2436}
2437
2438void
2439inteldrm_forcedetach(struct inteldrm_softc *dev_priv)
2440{
2441 struct pci_softc *psc = (struct pci_softc *)dev_priv->sc_dev.dv_parent;
2442 pcitag_t tag = dev_priv->tag;
2443 extern int vga_console_attached;
2444
2445 if (dev_priv->primary) {
2446 vga_console_attached = 0;
2447#if NEFIFB1 > 0
2448 efifb_reattach();
2449#endif
2450 }
2451
2452#ifdef notyet
2453 config_detach(&dev_priv->sc_dev, 0);
2454 pci_probe_device(psc, tag, NULL((void *)0), NULL((void *)0));
2455#endif
2456}
2457
2458void
2459inteldrm_attachhook(struct device *self)
2460{
2461 struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self;
2462 struct rasops_info *ri = &dev_priv->ro;
2463 struct wsemuldisplaydev_attach_args aa;
2464 const struct pci_device_id *id = dev_priv->id;
2465 struct drm_device *dev = &dev_priv->drm;
2466 int orientation_quirk;
2467
2468 if (inteldrm_refcnt == 0) {
2469 /* from i915_init() in i915_pci.c */
2470 if (i915_globals_init() != 0)
2471 goto fail;
2472 }
2473 inteldrm_refcnt++;
2474
2475 if (i915_driver_probe(dev_priv, id))
2476 goto fail;
2477
2478 if (ri->ri_bits == NULL((void *)0))
2479 goto fail;
2480
2481 printf("%s: %dx%d, %dbpp\n", dev_priv->sc_dev.dv_xname,
2482 ri->ri_width, ri->ri_height, ri->ri_depth);
2483
2484 ri->ri_flg = RI_CENTER0x0040 | RI_WRONLY0x1000 | RI_VCONS0x0800 | RI_CLEAR0x0010;
2485
2486 orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width,
2487 ri->ri_height);
2488 if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP)
2489 ri->ri_flg |= RI_ROTATE_CCW0x0200;
2490 else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP)
2491 ri->ri_flg |= RI_ROTATE_CW0x0100;
2492
2493 ri->ri_hw = dev_priv;
2494 rasops_init(ri, 160, 160);
2495
2496 task_set(&dev_priv->switchtask, inteldrm_doswitch, dev_priv);
2497 task_set(&dev_priv->burner_task, inteldrm_burner_cb, dev_priv);
2498
2499 inteldrm_stdscreen.capabilities = ri->ri_caps;
2500 inteldrm_stdscreen.nrows = ri->ri_rows;
2501 inteldrm_stdscreen.ncols = ri->ri_cols;
2502 inteldrm_stdscreen.textops = &ri->ri_ops;
2503 inteldrm_stdscreen.fontwidth = ri->ri_font->fontwidth;
2504 inteldrm_stdscreen.fontheight = ri->ri_font->fontheight;
2505
2506 aa.console = dev_priv->console;
2507 aa.primary = dev_priv->primary;
2508 aa.scrdata = &inteldrm_screenlist;
2509 aa.accessops = &inteldrm_accessops;
2510 aa.accesscookie = dev_priv;
2511 aa.defaultscreens = 0;
2512
2513 if (dev_priv->console) {
2514 uint32_t defattr;
2515
2516 /*
2517 * Clear the entire screen if we're doing rotation to
2518 * make sure no unrotated content survives.
2519 */
2520 if (ri->ri_flg & (RI_ROTATE_CW0x0100 | RI_ROTATE_CCW0x0200))
2521 memset(ri->ri_bits, 0, ri->ri_height * ri->ri_stride)__builtin_memset((ri->ri_bits), (0), (ri->ri_height * ri
->ri_stride))
;
2522
2523 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr);
2524 wsdisplay_cnattach(&inteldrm_stdscreen, ri->ri_active,
2525 0, 0, defattr);
2526 }
2527
2528 config_found_sm(self, &aa, wsemuldisplaydevprint,
2529 wsemuldisplaydevsubmatch);
2530 return;
2531
2532fail:
2533 inteldrm_fatal_error = 1;
2534 inteldrm_forcedetach(dev_priv);
2535}
2536
2537int
2538inteldrm_detach(struct device *self, int flags)
2539{
2540 return 0;
2541}
2542
2543int
2544inteldrm_activate(struct device *self, int act)
2545{
2546 struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self;
2547 struct drm_device *dev = &dev_priv->drm;
2548 int rv = 0;
2549
2550 if (dev->dev == NULL((void *)0))
2551 return (0);
2552
2553 /*
2554 * On hibernate resume activate is called before inteldrm_attachhook().
2555 * Do not try to call i915_drm_suspend() when
2556 * i915_load_modeset_init()/i915_gem_init() have not been called.
2557 */
2558 if (dev_priv->modeset_wq == NULL((void *)0))
2559 return 0;
2560
2561 switch (act) {
2562 case DVACT_QUIESCE2:
2563 rv = config_suspend(dev->dev, act);
2564 i915_drm_prepare(dev);
2565 i915_drm_suspend(dev);
2566 i915_drm_suspend_late(dev, false0);
2567 break;
2568 case DVACT_SUSPEND3:
2569 if (dev->agp)
2570 config_suspend(dev->agp->agpdev->sc_chipc, act);
2571 break;
2572 case DVACT_RESUME4:
2573 if (dev->agp)
2574 config_suspend(dev->agp->agpdev->sc_chipc, act);
2575 break;
2576 case DVACT_WAKEUP5:
2577 i915_drm_resume_early(dev);
2578 i915_drm_resume(dev);
2579 intel_fbdev_restore_mode(dev);
2580 rv = config_suspend(dev->dev, act);
2581 break;
2582 }
2583
2584 return (rv);
2585}
2586
2587void
2588inteldrm_native_backlight(struct inteldrm_softc *dev_priv)
2589{
2590 struct drm_device *dev = &dev_priv->drm;
2591 struct drm_connector_list_iter conn_iter;
2592 struct drm_connector *connector;
2593
2594 drm_connector_list_iter_begin(dev, &conn_iter);
2595 drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter
)))
{
2596 struct intel_connector *intel_connector;
2597 struct intel_panel *panel;
2598 struct backlight_device *bd;
2599
2600 if (connector->registration_state != DRM_CONNECTOR_REGISTERED)
2601 continue;
2602
2603 intel_connector = to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) *
__mptr = (connector); (struct intel_connector *)( (char *)__mptr
- __builtin_offsetof(struct intel_connector, base) );})
;
2604 panel = &intel_connector->panel;
2605 bd = panel->backlight.device;
2606
2607 if (!panel->backlight.present || bd == NULL((void *)0))
2608 continue;
2609
2610 dev->registered = false0;
2611 connector->registration_state = DRM_CONNECTOR_UNREGISTERED;
2612
2613 connector->backlight_device = bd;
2614 connector->backlight_property = drm_property_create_range(dev,
2615 0, "Backlight", 0, bd->props.max_brightness);
2616 drm_object_attach_property(&connector->base,
2617 connector->backlight_property, bd->props.brightness);
2618
2619 connector->registration_state = DRM_CONNECTOR_REGISTERED;
2620 dev->registered = true1;
2621
2622 /*
2623 * Use backlight from the first connector that has one
2624 * for wscons(4).
2625 */
2626 if (dev_priv->backlight == NULL((void *)0))
2627 dev_priv->backlight = bd;
2628 }
2629 drm_connector_list_iter_end(&conn_iter);
2630}
2631
2632void
2633inteldrm_firmware_backlight(struct inteldrm_softc *dev_priv,
2634 struct wsdisplay_param *dp)
2635{
2636 struct drm_device *dev = &dev_priv->drm;
2637 struct drm_connector_list_iter conn_iter;
2638 struct drm_connector *connector;
2639 struct backlight_properties props;
2640 struct backlight_device *bd;
2641
2642 memset(&props, 0, sizeof(props))__builtin_memset((&props), (0), (sizeof(props)));
2643 props.type = BACKLIGHT_FIRMWARE1;
2644 props.brightness = dp->curval;
2645 bd = backlight_device_register(dev->dev->dv_xname, NULL((void *)0), NULL((void *)0),
2646 &inteldrm_backlight_ops, &props);
2647
2648 drm_connector_list_iter_begin(dev, &conn_iter);
2649 drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter
)))
{
2650 if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS7 &&
2651 connector->connector_type != DRM_MODE_CONNECTOR_eDP14 &&
2652 connector->connector_type != DRM_MODE_CONNECTOR_DSI16)
2653 continue;
2654
2655 if (connector->registration_state != DRM_CONNECTOR_REGISTERED)
2656 continue;
2657
2658 dev->registered = false0;
2659 connector->registration_state = DRM_CONNECTOR_UNREGISTERED;
2660
2661 connector->backlight_device = bd;
2662 connector->backlight_property = drm_property_create_range(dev,
2663 0, "Backlight", dp->min, dp->max);
2664 drm_object_attach_property(&connector->base,
2665 connector->backlight_property, dp->curval);
2666
2667 connector->registration_state = DRM_CONNECTOR_REGISTERED;
2668 dev->registered = true1;
2669 }
2670 drm_connector_list_iter_end(&conn_iter);
2671}
2672
2673void
2674inteldrm_init_backlight(struct inteldrm_softc *dev_priv)
2675{
2676 struct drm_device *dev = &dev_priv->drm;
2677 struct wsdisplay_param dp;
2678
2679 dp.param = WSDISPLAYIO_PARAM_BRIGHTNESS2;
2680 if (ws_get_param && ws_get_param(&dp) == 0)
2681 inteldrm_firmware_backlight(dev_priv, &dp);
2682 else
2683 inteldrm_native_backlight(dev_priv);
2684}
2685
2686int
2687inteldrm_intr(void *arg)
2688{
2689 struct inteldrm_softc *dev_priv = arg;
2690
2691 if (dev_priv->irq_handler)
2692 return dev_priv->irq_handler(0, dev_priv);
2693
2694 return 0;
2695}
2696
2697#endif