Bug Summary

File:dev/pci/drm/i915/display/intel_dpio_phy.c
Warning:line 1065, column 2
Value stored to 'val' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name intel_dpio_phy.c -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -D CONFIG_DRM_AMD_DC_DCN3_0 -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /usr/obj/sys/arch/amd64/compile/GENERIC.MP/scan-build/2022-01-12-131800-47421-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_dpio_phy.c
1/*
2 * Copyright © 2014-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24#include "display/intel_dp.h"
25
26#include "intel_display_types.h"
27#include "intel_dpio_phy.h"
28#include "intel_sideband.h"
29
30/**
31 * DOC: DPIO
32 *
33 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
34 * ports. DPIO is the name given to such a display PHY. These PHYs
35 * don't follow the standard programming model using direct MMIO
36 * registers, and instead their registers must be accessed trough IOSF
37 * sideband. VLV has one such PHY for driving ports B and C, and CHV
38 * adds another PHY for driving port D. Each PHY responds to specific
39 * IOSF-SB port.
40 *
41 * Each display PHY is made up of one or two channels. Each channel
42 * houses a common lane part which contains the PLL and other common
43 * logic. CH0 common lane also contains the IOSF-SB logic for the
44 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
45 * must be running when any DPIO registers are accessed.
46 *
47 * In addition to having their own registers, the PHYs are also
48 * controlled through some dedicated signals from the display
49 * controller. These include PLL reference clock enable, PLL enable,
50 * and CRI clock selection, for example.
51 *
52 * Eeach channel also has two splines (also called data lanes), and
53 * each spline is made up of one Physical Access Coding Sub-Layer
54 * (PCS) block and two TX lanes. So each channel has two PCS blocks
55 * and four TX lanes. The TX lanes are used as DP lanes or TMDS
56 * data/clock pairs depending on the output type.
57 *
58 * Additionally the PHY also contains an AUX lane with AUX blocks
59 * for each channel. This is used for DP AUX communication, but
60 * this fact isn't really relevant for the driver since AUX is
61 * controlled from the display controller side. No DPIO registers
62 * need to be accessed during AUX communication,
63 *
64 * Generally on VLV/CHV the common lane corresponds to the pipe and
65 * the spline (PCS/TX) corresponds to the port.
66 *
67 * For dual channel PHY (VLV/CHV):
68 *
69 * pipe A == CMN/PLL/REF CH0
70 *
71 * pipe B == CMN/PLL/REF CH1
72 *
73 * port B == PCS/TX CH0
74 *
75 * port C == PCS/TX CH1
76 *
77 * This is especially important when we cross the streams
78 * ie. drive port B with pipe B, or port C with pipe A.
79 *
80 * For single channel PHY (CHV):
81 *
82 * pipe C == CMN/PLL/REF CH0
83 *
84 * port D == PCS/TX CH0
85 *
86 * On BXT the entire PHY channel corresponds to the port. That means
87 * the PLL is also now associated with the port rather than the pipe,
88 * and so the clock needs to be routed to the appropriate transcoder.
89 * Port A PLL is directly connected to transcoder EDP and port B/C
90 * PLLs can be routed to any transcoder A/B/C.
91 *
92 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
93 * digital port D (CHV) or port A (BXT). ::
94 *
95 *
96 * Dual channel PHY (VLV/CHV/BXT)
97 * ---------------------------------
98 * | CH0 | CH1 |
99 * | CMN/PLL/REF | CMN/PLL/REF |
100 * |---------------|---------------| Display PHY
101 * | PCS01 | PCS23 | PCS01 | PCS23 |
102 * |-------|-------|-------|-------|
103 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
104 * ---------------------------------
105 * | DDI0 | DDI1 | DP/HDMI ports
106 * ---------------------------------
107 *
108 * Single channel PHY (CHV/BXT)
109 * -----------------
110 * | CH0 |
111 * | CMN/PLL/REF |
112 * |---------------| Display PHY
113 * | PCS01 | PCS23 |
114 * |-------|-------|
115 * |TX0|TX1|TX2|TX3|
116 * -----------------
117 * | DDI2 | DP/HDMI port
118 * -----------------
119 */
120
121/**
122 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
123 */
124struct bxt_ddi_phy_info {
125 /**
126 * @dual_channel: true if this phy has a second channel.
127 */
128 bool_Bool dual_channel;
129
130 /**
131 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
132 * Otherwise the GRC value will be copied from the phy indicated by
133 * this field.
134 */
135 enum dpio_phy rcomp_phy;
136
137 /**
138 * @reset_delay: delay in us to wait before setting the common reset
139 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
140 */
141 int reset_delay;
142
143 /**
144 * @pwron_mask: Mask with the appropriate bit set that would cause the
145 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
146 */
147 u32 pwron_mask;
148
149 /**
150 * @channel: struct containing per channel information.
151 */
152 struct {
153 /**
154 * @channel.port: which port maps to this channel.
155 */
156 enum port port;
157 } channel[2];
158};
159
160static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
161 [DPIO_PHY0] = {
162 .dual_channel = true1,
163 .rcomp_phy = DPIO_PHY1,
164 .pwron_mask = BIT(0)(1UL << (0)),
165
166 .channel = {
167 [DPIO_CH0] = { .port = PORT_B },
168 [DPIO_CH1] = { .port = PORT_C },
169 }
170 },
171 [DPIO_PHY1] = {
172 .dual_channel = false0,
173 .rcomp_phy = -1,
174 .pwron_mask = BIT(1)(1UL << (1)),
175
176 .channel = {
177 [DPIO_CH0] = { .port = PORT_A },
178 }
179 },
180};
181
182static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
183 [DPIO_PHY0] = {
184 .dual_channel = false0,
185 .rcomp_phy = DPIO_PHY1,
186 .pwron_mask = BIT(0)(1UL << (0)),
187 .reset_delay = 20,
188
189 .channel = {
190 [DPIO_CH0] = { .port = PORT_B },
191 }
192 },
193 [DPIO_PHY1] = {
194 .dual_channel = false0,
195 .rcomp_phy = -1,
196 .pwron_mask = BIT(3)(1UL << (3)),
197 .reset_delay = 20,
198
199 .channel = {
200 [DPIO_CH0] = { .port = PORT_A },
201 }
202 },
203 [DPIO_PHY2] = {
204 .dual_channel = false0,
205 .rcomp_phy = DPIO_PHY1,
206 .pwron_mask = BIT(1)(1UL << (1)),
207 .reset_delay = 20,
208
209 .channel = {
210 [DPIO_CH0] = { .port = PORT_C },
211 }
212 },
213};
214
215static const struct bxt_ddi_phy_info *
216bxt_get_phy_list(struct drm_i915_privateinteldrm_softc *dev_priv, int *count)
217{
218 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
219 *count = ARRAY_SIZE(glk_ddi_phy_info)(sizeof((glk_ddi_phy_info)) / sizeof((glk_ddi_phy_info)[0]));
220 return glk_ddi_phy_info;
221 } else {
222 *count = ARRAY_SIZE(bxt_ddi_phy_info)(sizeof((bxt_ddi_phy_info)) / sizeof((bxt_ddi_phy_info)[0]));
223 return bxt_ddi_phy_info;
224 }
225}
226
227static const struct bxt_ddi_phy_info *
228bxt_get_phy_info(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy)
229{
230 int count;
231 const struct bxt_ddi_phy_info *phy_list =
232 bxt_get_phy_list(dev_priv, &count);
233
234 return &phy_list[phy];
235}
236
237void bxt_port_to_phy_channel(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port,
238 enum dpio_phy *phy, enum dpio_channel *ch)
239{
240 const struct bxt_ddi_phy_info *phy_info, *phys;
241 int i, count;
242
243 phys = bxt_get_phy_list(dev_priv, &count);
244
245 for (i = 0; i < count; i++) {
246 phy_info = &phys[i];
247
248 if (port == phy_info->channel[DPIO_CH0].port) {
249 *phy = i;
250 *ch = DPIO_CH0;
251 return;
252 }
253
254 if (phy_info->dual_channel &&
255 port == phy_info->channel[DPIO_CH1].port) {
256 *phy = i;
257 *ch = DPIO_CH1;
258 return;
259 }
260 }
261
262 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",({ int __ret = !!(1); if (__ret) printf("%s %s: " "PHY not found for PORT %c"
, dev_driver_string((&dev_priv->drm)->dev), "", ((port
) + 'A')); __builtin_expect(!!(__ret), 0); })
263 port_name(port))({ int __ret = !!(1); if (__ret) printf("%s %s: " "PHY not found for PORT %c"
, dev_driver_string((&dev_priv->drm)->dev), "", ((port
) + 'A')); __builtin_expect(!!(__ret), 0); })
;
264 *phy = DPIO_PHY0;
265 *ch = DPIO_CH0;
266}
267
268void bxt_ddi_phy_set_signal_level(struct drm_i915_privateinteldrm_softc *dev_priv,
269 enum port port, u32 margin, u32 scale,
270 u32 enable, u32 deemphasis)
271{
272 u32 val;
273 enum dpio_phy phy;
274 enum dpio_channel ch;
275
276 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
277
278 /*
279 * While we write to the group register to program all lanes at once we
280 * can read only lane registers and we pick lanes 0/1 for that.
281 */
282 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C428) - 0x6C000) + ((ch)) * (((
0x6C828) - 0x6C000) - ((0x6C428) - 0x6C000))))) })
);
283 val &= ~(TX2_SWING_CALC_INIT(1 << 31) | TX1_SWING_CALC_INIT(1 << 30));
284 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC28) - 0x6C000) + ((ch)) * (((
0x6CE28) - 0x6C000) - ((0x6CC28) - 0x6C000))))) })
, val);
285
286 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C508) - 0x6C000) + ((ch)) * (((
0x6C908) - 0x6C000) - ((0x6C508) - 0x6C000))))) })
);
287 val &= ~(MARGIN_000(0xFF << 16) | UNIQ_TRANS_SCALE(0xFF << 8));
288 val |= margin << MARGIN_000_SHIFT16 | scale << UNIQ_TRANS_SCALE_SHIFT8;
289 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD08) - 0x6C000) + ((ch)) * (((
0x6CF08) - 0x6C000) - ((0x6CD08) - 0x6C000))))) })
, val);
290
291 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C50C) - 0x6C000) + ((ch)) * (((
0x6C90C) - 0x6C000) - ((0x6C50C) - 0x6C000))))) })
);
292 val &= ~SCALE_DCOMP_METHOD(1 << 26);
293 if (enable)
294 val |= SCALE_DCOMP_METHOD(1 << 26);
295
296 if ((val & UNIQUE_TRANGE_EN_METHOD(1 << 27)) && !(val & SCALE_DCOMP_METHOD(1 << 26)))
297 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Disabled scaling while ouniqetrangenmethod was set"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
298 "Disabled scaling while ouniqetrangenmethod was set")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Disabled scaling while ouniqetrangenmethod was set"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
;
299
300 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD0C) - 0x6C000) + ((ch)) * (((
0x6CF0C) - 0x6C000) - ((0x6CD0C) - 0x6C000))))) })
, val);
301
302 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C510) - 0x6C000) + ((ch)) * (((
0x6C910) - 0x6C000) - ((0x6C510) - 0x6C000))))) })
);
303 val &= ~DE_EMPHASIS(0xFF << 24);
304 val |= deemphasis << DEEMPH_SHIFT24;
305 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CD10) - 0x6C000) + ((ch)) * (((
0x6CF10) - 0x6C000) - ((0x6CD10) - 0x6C000))))) })
, val);
306
307 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C428) - 0x6C000) + ((ch)) * (((
0x6C828) - 0x6C000) - ((0x6C428) - 0x6C000))))) })
);
308 val |= TX2_SWING_CALC_INIT(1 << 31) | TX1_SWING_CALC_INIT(1 << 30);
309 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6CC28) - 0x6C000) + ((ch)) * (((
0x6CE28) - 0x6C000) - ((0x6CC28) - 0x6C000))))) })
, val);
310}
311
312bool_Bool bxt_ddi_phy_is_enabled(struct drm_i915_privateinteldrm_softc *dev_priv,
313 enum dpio_phy phy)
314{
315 const struct bxt_ddi_phy_info *phy_info;
316
317 phy_info = bxt_get_phy_info(dev_priv, phy);
318
319 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) })) & phy_info->pwron_mask))
320 return false0;
321
322 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C000)) })
) &
323 (PHY_POWER_GOOD(1 << 16) | PHY_RESERVED(1 << 7))) != PHY_POWER_GOOD(1 << 16)) {
324 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d powered, but power hasn't settled\n"
, phy)
325 "DDI PHY %d powered, but power hasn't settled\n", phy)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d powered, but power hasn't settled\n"
, phy)
;
326
327 return false0;
328 }
329
330 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
) & COMMON_RESET_DIS(1 << 31))) {
331 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d powered, but still in reset\n"
, phy)
332 "DDI PHY %d powered, but still in reset\n", phy)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d powered, but still in reset\n"
, phy)
;
333
334 return false0;
335 }
336
337 return true1;
338}
339
340static u32 bxt_get_grc(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy)
341{
342 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C198)) })
);
343
344 return (val & GRC_CODE_MASK(0xFF << 24)) >> GRC_CODE_SHIFT24;
345}
346
347static void bxt_phy_wait_grc_done(struct drm_i915_privateinteldrm_softc *dev_priv,
348 enum dpio_phy phy)
349{
350 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C18C)) })
,
351 GRC_DONE(1 << 22), 10))
352 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout waiting for PHY%d GRC\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , phy)
353 phy)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout waiting for PHY%d GRC\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , phy)
;
354}
355
356static void _bxt_ddi_phy_init(struct drm_i915_privateinteldrm_softc *dev_priv,
357 enum dpio_phy phy)
358{
359 const struct bxt_ddi_phy_info *phy_info;
360 u32 val;
361
362 phy_info = bxt_get_phy_info(dev_priv, phy);
363
364 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
365 /* Still read out the GRC value for state verification */
366 if (phy_info->rcomp_phy != -1)
367 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
368
369 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
370 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d already enabled, "
"won't reprogram it\n", phy)
371 "won't reprogram it\n", phy)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d already enabled, "
"won't reprogram it\n", phy)
;
372 return;
373 }
374
375 drm_dbg(&dev_priv->drm,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d enabled with invalid state, "
"force reprogramming it\n", phy)
376 "DDI PHY %d enabled with invalid state, "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d enabled with invalid state, "
"force reprogramming it\n", phy)
377 "force reprogramming it\n", phy)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d enabled with invalid state, "
"force reprogramming it\n", phy)
;
378 }
379
380 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }));
381 val |= phy_info->pwron_mask;
382 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }), val);
383
384 /*
385 * The PHY registers start out inaccessible and respond to reads with
386 * all 1s. Eventually they become accessible as they power up, then
387 * the reserved bit will give the default 0. Poll on the reserved bit
388 * becoming 0 to find when the PHY is accessible.
389 * The flag should get set in 100us according to the HW team, but
390 * use 1ms due to occasional timeouts observed with that.
391 */
392 if (intel_wait_for_register_fw(&dev_priv->uncore,
393 BXT_PORT_CL1CM_DW0(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C000)) })
,
394 PHY_RESERVED(1 << 7) | PHY_POWER_GOOD(1 << 16),
395 PHY_POWER_GOOD(1 << 16),
396 1))
397 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout during PHY%d power on\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , phy)
398 phy)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "timeout during PHY%d power on\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , phy)
;
399
400 /* Program PLL Rcomp code offset */
401 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C024)) })
);
402 val &= ~IREF0RC_OFFSET_MASK(0xFF << 8);
403 val |= 0xE4 << IREF0RC_OFFSET_SHIFT8;
404 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C024)) })
, val);
405
406 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C028)) })
);
407 val &= ~IREF1RC_OFFSET_MASK(0xFF << 8);
408 val |= 0xE4 << IREF1RC_OFFSET_SHIFT8;
409 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C028)) })
, val);
410
411 /* Program power gating */
412 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C070)) })
);
413 val |= OCL1_POWER_DOWN_EN(1 << 23) | DW28_OLDO_DYN_PWR_DOWN_EN(1 << 22) |
414 SUS_CLK_CONFIG0x3;
415 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C070)) })
, val);
416
417 if (phy_info->dual_channel) {
418 val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C358)) })
);
419 val |= DW6_OLDO_DYN_PWR_DOWN_EN(1 << 28);
420 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C358)) })
, val);
421 }
422
423 if (phy_info->rcomp_phy != -1) {
424 u32 grc_code;
425
426 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
427
428 /*
429 * PHY0 isn't connected to an RCOMP resistor so copy over
430 * the corresponding calibrated value from PHY1, and disable
431 * the automatic calibration on PHY0.
432 */
433 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
434 phy_info->rcomp_phy);
435 grc_code = val << GRC_CODE_FAST_SHIFT16 |
436 val << GRC_CODE_SLOW_SHIFT8 |
437 val;
438 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C198)) })
, grc_code);
439
440 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C1A0)) })
);
441 val |= GRC_DIS(1 << 15) | GRC_RDY_OVRD(1 << 1);
442 intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C1A0)) })
, val);
443 }
444
445 if (phy_info->reset_delay)
446 udelay(phy_info->reset_delay);
447
448 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
);
449 val |= COMMON_RESET_DIS(1 << 31);
450 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
, val);
451}
452
453void bxt_ddi_phy_uninit(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy)
454{
455 const struct bxt_ddi_phy_info *phy_info;
456 u32 val;
457
458 phy_info = bxt_get_phy_info(dev_priv, phy);
459
460 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
);
461 val &= ~COMMON_RESET_DIS(1 << 31);
462 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x64C90, 0x64C80
, 0x64CA0 })[(phy)])) })
, val);
463
464 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }));
465 val &= ~phy_info->pwron_mask;
466 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }), val);
467}
468
469void bxt_ddi_phy_init(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy)
470{
471 const struct bxt_ddi_phy_info *phy_info =
472 bxt_get_phy_info(dev_priv, phy);
473 enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
474 bool_Bool was_enabled;
475
476 lockdep_assert_held(&dev_priv->power_domains.lock)do { (void)(&dev_priv->power_domains.lock); } while(0);
477
478 was_enabled = true1;
479 if (rcomp_phy != -1)
480 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
481
482 /*
483 * We need to copy the GRC calibration value from rcomp_phy,
484 * so make sure it's powered up.
485 */
486 if (!was_enabled)
487 _bxt_ddi_phy_init(dev_priv, rcomp_phy);
488
489 _bxt_ddi_phy_init(dev_priv, phy);
490
491 if (!was_enabled)
492 bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
493}
494
495static bool_Bool __printf(6, 7)__attribute__((__format__(__kprintf__,6,7)))
496__phy_reg_verify_state(struct drm_i915_privateinteldrm_softc *dev_priv, enum dpio_phy phy,
497 i915_reg_t reg, u32 mask, u32 expected,
498 const char *reg_fmt, ...)
499{
500 struct va_format vaf;
501 va_list args;
502 u32 val;
503
504 val = intel_de_read(dev_priv, reg);
505 if ((val & mask) == expected)
506 return true1;
507
508 va_start(args, reg_fmt)__builtin_va_start((args), reg_fmt);
509 vaf.fmt = reg_fmt;
510 vaf.va = &args;
511
512 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d reg %pV [%08x] state mismatch: "
"current %08x, expected %08x (mask %08x)\n", phy, &vaf, reg
.reg, val, (val & ~mask) | expected, mask)
513 "current %08x, expected %08x (mask %08x)\n",drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d reg %pV [%08x] state mismatch: "
"current %08x, expected %08x (mask %08x)\n", phy, &vaf, reg
.reg, val, (val & ~mask) | expected, mask)
514 phy, &vaf, reg.reg, val, (val & ~mask) | expected,drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d reg %pV [%08x] state mismatch: "
"current %08x, expected %08x (mask %08x)\n", phy, &vaf, reg
.reg, val, (val & ~mask) | expected, mask)
515 mask)drm_dev_dbg((&dev_priv->drm)->dev, DRM_UT_DRIVER, "DDI PHY %d reg %pV [%08x] state mismatch: "
"current %08x, expected %08x (mask %08x)\n", phy, &vaf, reg
.reg, val, (val & ~mask) | expected, mask)
;
516
517 va_end(args)__builtin_va_end((args));
518
519 return false0;
520}
521
522bool_Bool bxt_ddi_phy_verify_state(struct drm_i915_privateinteldrm_softc *dev_priv,
523 enum dpio_phy phy)
524{
525 const struct bxt_ddi_phy_info *phy_info;
526 u32 mask;
527 bool_Bool ok;
528
529 phy_info = bxt_get_phy_info(dev_priv, phy);
530
531#define _CHK(reg, mask, exp, fmt, ...) \
532 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
533 ## __VA_ARGS__)
534
535 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
536 return false0;
537
538 ok = true1;
539
540 /* PLL Rcomp code offset */
541 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C024)) })
,
542 IREF0RC_OFFSET_MASK(0xFF << 8), 0xe4 << IREF0RC_OFFSET_SHIFT8,
543 "BXT_PORT_CL1CM_DW9(%d)", phy);
544 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C028)) })
,
545 IREF1RC_OFFSET_MASK(0xFF << 8), 0xe4 << IREF1RC_OFFSET_SHIFT8,
546 "BXT_PORT_CL1CM_DW10(%d)", phy);
547
548 /* Power gating */
549 mask = OCL1_POWER_DOWN_EN(1 << 23) | DW28_OLDO_DYN_PWR_DOWN_EN(1 << 22) | SUS_CLK_CONFIG0x3;
550 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C070)) })
, mask, mask,
551 "BXT_PORT_CL1CM_DW28(%d)", phy);
552
553 if (phy_info->dual_channel)
554 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C358)) })
,
555 DW6_OLDO_DYN_PWR_DOWN_EN(1 << 28), DW6_OLDO_DYN_PWR_DOWN_EN(1 << 28),
556 "BXT_PORT_CL2CM_DW6(%d)", phy);
557
558 if (phy_info->rcomp_phy != -1) {
559 u32 grc_code = dev_priv->bxt_phy_grc;
560
561 grc_code = grc_code << GRC_CODE_FAST_SHIFT16 |
562 grc_code << GRC_CODE_SLOW_SHIFT8 |
563 grc_code;
564 mask = GRC_CODE_FAST_MASK(0xFF << 16) | GRC_CODE_SLOW_MASK(0xFF << 8) |
565 GRC_CODE_NOM_MASK0xFF;
566 ok &= _CHK(BXT_PORT_REF_DW6(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C198)) })
, mask, grc_code,
567 "BXT_PORT_REF_DW6(%d)", phy);
568
569 mask = GRC_DIS(1 << 15) | GRC_RDY_OVRD(1 << 1);
570 ok &= _CHK(BXT_PORT_REF_DW8(phy)((const i915_reg_t){ .reg = ((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[((phy))]) - 0x6C000 + (0x6C1A0)) })
, mask, mask,
571 "BXT_PORT_REF_DW8(%d)", phy);
572 }
573
574 return ok;
575#undef _CHK
576}
577
578u8
579bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
580{
581 switch (lane_count) {
582 case 1:
583 return 0;
584 case 2:
585 return BIT(2)(1UL << (2)) | BIT(0)(1UL << (0));
586 case 4:
587 return BIT(3)(1UL << (3)) | BIT(2)(1UL << (2)) | BIT(0)(1UL << (0));
588 default:
589 MISSING_CASE(lane_count)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "lane_count", (long)(lane_count)); __builtin_expect(!!(__ret
), 0); })
;
590
591 return 0;
592 }
593}
594
595void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
596 u8 lane_lat_optim_mask)
597{
598 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
599 enum port port = encoder->port;
600 enum dpio_phy phy;
601 enum dpio_channel ch;
602 int lane;
603
604 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
605
606 for (lane = 0; lane < 4; lane++) {
607 u32 val = intel_de_read(dev_priv,
608 BXT_PORT_TX_DW14_LN(phy, ch, lane)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) })
);
609
610 /*
611 * Note that on CHV this flag is called UPAR, but has
612 * the same function.
613 */
614 val &= ~LATENCY_OPTIM(1 << 30);
615 if (lane_lat_optim_mask & BIT(lane)(1UL << (lane)))
616 val |= LATENCY_OPTIM(1 << 30);
617
618 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) })
,
619 val);
620 }
621}
622
623u8
624bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
625{
626 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
627 enum port port = encoder->port;
628 enum dpio_phy phy;
629 enum dpio_channel ch;
630 int lane;
631 u8 mask;
632
633 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
634
635 mask = 0;
636 for (lane = 0; lane < 4; lane++) {
637 u32 val = intel_de_read(dev_priv,
638 BXT_PORT_TX_DW14_LN(phy, ch, lane)((const i915_reg_t){ .reg = (((((const u32 []){ 0x6C000, 0x162000
, 0x163000 })[(phy)]) + (((0x6C538) - 0x6C000) + ((ch)) * (((
0x6C938) - 0x6C000) - ((0x6C538) - 0x6C000)))) + (((lane) >>
1) * 0x200 + ((lane) & 1) * 0x80)) })
);
639
640 if (val & LATENCY_OPTIM(1 << 30))
641 mask |= BIT(lane)(1UL << (lane));
642 }
643
644 return mask;
645}
646
647
648void chv_set_phy_signal_level(struct intel_encoder *encoder,
649 u32 deemph_reg_value, u32 margin_reg_value,
650 bool_Bool uniq_trans_scale)
651{
652 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
653 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
654 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (encoder->base.crtc); (struct intel_crtc *)( (char *)__mptr
- __builtin_offsetof(struct intel_crtc, base) );})
;
655 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
656 enum pipe pipe = intel_crtc->pipe;
657 u32 val;
658 int i;
659
660 vlv_dpio_get(dev_priv);
661
662 /* Clear calc init */
663 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)((0x0228) + (ch) * ((0x2628) - (0x0228))));
664 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2(1 << 30) | DPIO_PCS_SWING_CALC_TX1_TX3(1 << 31));
665 val &= ~(DPIO_PCS_TX1DEEMP_MASK(0xf << 16) | DPIO_PCS_TX2DEEMP_MASK(0xf << 24));
666 val |= DPIO_PCS_TX1DEEMP_9P5(0 << 16) | DPIO_PCS_TX2DEEMP_9P5(0 << 24);
667 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch)((0x0228) + (ch) * ((0x2628) - (0x0228))), val);
668
669 if (intel_crtc->config->lane_count > 2) {
670 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)((0x0428) + (ch) * ((0x2828) - (0x0428))));
671 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2(1 << 30) | DPIO_PCS_SWING_CALC_TX1_TX3(1 << 31));
672 val &= ~(DPIO_PCS_TX1DEEMP_MASK(0xf << 16) | DPIO_PCS_TX2DEEMP_MASK(0xf << 24));
673 val |= DPIO_PCS_TX1DEEMP_9P5(0 << 16) | DPIO_PCS_TX2DEEMP_9P5(0 << 24);
674 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch)((0x0428) + (ch) * ((0x2828) - (0x0428))), val);
675 }
676
677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)((0x224) + (ch) * ((0x2624) - (0x224))));
678 val &= ~(DPIO_PCS_TX1MARGIN_MASK(0x7 << 10) | DPIO_PCS_TX2MARGIN_MASK(0x7 << 13));
679 val |= DPIO_PCS_TX1MARGIN_000(0 << 10) | DPIO_PCS_TX2MARGIN_000(0 << 13);
680 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch)((0x224) + (ch) * ((0x2624) - (0x224))), val);
681
682 if (intel_crtc->config->lane_count > 2) {
683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)((0x424) + (ch) * ((0x2824) - (0x424))));
684 val &= ~(DPIO_PCS_TX1MARGIN_MASK(0x7 << 10) | DPIO_PCS_TX2MARGIN_MASK(0x7 << 13));
685 val |= DPIO_PCS_TX1MARGIN_000(0 << 10) | DPIO_PCS_TX2MARGIN_000(0 << 13);
686 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch)((0x424) + (ch) * ((0x2824) - (0x424))), val);
687 }
688
689 /* Program swing deemph */
690 for (i = 0; i < intel_crtc->config->lane_count; i++) {
691 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0x90)));
692 val &= ~DPIO_SWING_DEEMPH9P5_MASK(0xff << 24);
693 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT24;
694 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0x90)), val);
695 }
696
697 /* Program swing margin */
698 for (i = 0; i < intel_crtc->config->lane_count; i++) {
699 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0x88)));
700
701 val &= ~DPIO_SWING_MARGIN000_MASK(0xff << 16);
702 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT16;
703
704 /*
705 * Supposedly this value shouldn't matter when unique transition
706 * scale is disabled, but in fact it does matter. Let's just
707 * always program the same value and hope it's OK.
708 */
709 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT8);
710 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT8;
711
712 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0x88)), val);
713 }
714
715 /*
716 * The document said it needs to set bit 27 for ch0 and bit 26
717 * for ch1. Might be a typo in the doc.
718 * For now, for this unique transition scale selection, set bit
719 * 27 for ch0 and ch1.
720 */
721 for (i = 0; i < intel_crtc->config->lane_count; i++) {
722 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0x8c)));
723 if (uniq_trans_scale)
724 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN(1 << 27);
725 else
726 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN(1 << 27);
727 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0x8c)), val);
728 }
729
730 /* Start swing calculation */
731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)((0x0228) + (ch) * ((0x2628) - (0x0228))));
732 val |= DPIO_PCS_SWING_CALC_TX0_TX2(1 << 30) | DPIO_PCS_SWING_CALC_TX1_TX3(1 << 31);
733 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch)((0x0228) + (ch) * ((0x2628) - (0x0228))), val);
734
735 if (intel_crtc->config->lane_count > 2) {
736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)((0x0428) + (ch) * ((0x2828) - (0x0428))));
737 val |= DPIO_PCS_SWING_CALC_TX0_TX2(1 << 30) | DPIO_PCS_SWING_CALC_TX1_TX3(1 << 31);
738 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch)((0x0428) + (ch) * ((0x2828) - (0x0428))), val);
739 }
740
741 vlv_dpio_put(dev_priv);
742}
743
744void chv_data_lane_soft_reset(struct intel_encoder *encoder,
745 const struct intel_crtc_state *crtc_state,
746 bool_Bool reset)
747{
748 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
749 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
751 enum pipe pipe = crtc->pipe;
752 u32 val;
753
754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)((0x200) + (ch) * ((0x2600) - (0x200))));
755 if (reset)
756 val &= ~(DPIO_PCS_TX_LANE2_RESET(1 << 16) | DPIO_PCS_TX_LANE1_RESET(1 << 7));
757 else
758 val |= DPIO_PCS_TX_LANE2_RESET(1 << 16) | DPIO_PCS_TX_LANE1_RESET(1 << 7);
759 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch)((0x200) + (ch) * ((0x2600) - (0x200))), val);
760
761 if (crtc_state->lane_count > 2) {
762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)((0x400) + (ch) * ((0x2800) - (0x400))));
763 if (reset)
764 val &= ~(DPIO_PCS_TX_LANE2_RESET(1 << 16) | DPIO_PCS_TX_LANE1_RESET(1 << 7));
765 else
766 val |= DPIO_PCS_TX_LANE2_RESET(1 << 16) | DPIO_PCS_TX_LANE1_RESET(1 << 7);
767 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch)((0x400) + (ch) * ((0x2800) - (0x400))), val);
768 }
769
770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)((0x204) + (ch) * ((0x2604) - (0x204))));
771 val |= CHV_PCS_REQ_SOFTRESET_EN(1 << 23);
772 if (reset)
773 val &= ~DPIO_PCS_CLK_SOFT_RESET(1 << 5);
774 else
775 val |= DPIO_PCS_CLK_SOFT_RESET(1 << 5);
776 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch)((0x204) + (ch) * ((0x2604) - (0x204))), val);
777
778 if (crtc_state->lane_count > 2) {
779 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)((0x404) + (ch) * ((0x2804) - (0x404))));
780 val |= CHV_PCS_REQ_SOFTRESET_EN(1 << 23);
781 if (reset)
782 val &= ~DPIO_PCS_CLK_SOFT_RESET(1 << 5);
783 else
784 val |= DPIO_PCS_CLK_SOFT_RESET(1 << 5);
785 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch)((0x404) + (ch) * ((0x2804) - (0x404))), val);
786 }
787}
788
789void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
790 const struct intel_crtc_state *crtc_state)
791{
792 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
793 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
795 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
796 enum pipe pipe = crtc->pipe;
797 unsigned int lane_mask =
798 intel_dp_unused_lane_mask(crtc_state->lane_count);
799 u32 val;
800
801 /*
802 * Must trick the second common lane into life.
803 * Otherwise we can't even access the PLL.
804 */
805 if (ch == DPIO_CH0 && pipe == PIPE_B)
806 dig_port->release_cl2_override =
807 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true1);
808
809 chv_phy_powergate_lanes(encoder, true1, lane_mask);
810
811 vlv_dpio_get(dev_priv);
812
813 /* Assert data lane reset */
814 chv_data_lane_soft_reset(encoder, crtc_state, true1);
815
816 /* program left/right clock distribution */
817 if (pipe != PIPE_B) {
818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH00x8114);
819 val &= ~(CHV_BUFLEFTENA1_MASK(3 << 22) | CHV_BUFRIGHTENA1_MASK(3 << 20));
820 if (ch == DPIO_CH0)
821 val |= CHV_BUFLEFTENA1_FORCE(3 << 22);
822 if (ch == DPIO_CH1)
823 val |= CHV_BUFRIGHTENA1_FORCE(3 << 20);
824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH00x8114, val);
825 } else {
826 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH10x8084);
827 val &= ~(CHV_BUFLEFTENA2_MASK(3 << 17) | CHV_BUFRIGHTENA2_MASK(3 << 19));
828 if (ch == DPIO_CH0)
829 val |= CHV_BUFLEFTENA2_FORCE(3 << 17);
830 if (ch == DPIO_CH1)
831 val |= CHV_BUFRIGHTENA2_FORCE(3 << 19);
832 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH10x8084, val);
833 }
834
835 /* program clock channel usage */
836 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)((0x0220) + (ch) * ((0x2620) - (0x0220))));
837 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE(1 << 20);
838 if (pipe != PIPE_B)
839 val &= ~CHV_PCS_USEDCLKCHANNEL(1 << 21);
840 else
841 val |= CHV_PCS_USEDCLKCHANNEL(1 << 21);
842 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch)((0x0220) + (ch) * ((0x2620) - (0x0220))), val);
843
844 if (crtc_state->lane_count > 2) {
845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)((0x0420) + (ch) * ((0x2820) - (0x0420))));
846 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE(1 << 20);
847 if (pipe != PIPE_B)
848 val &= ~CHV_PCS_USEDCLKCHANNEL(1 << 21);
849 else
850 val |= CHV_PCS_USEDCLKCHANNEL(1 << 21);
851 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch)((0x0420) + (ch) * ((0x2820) - (0x0420))), val);
852 }
853
854 /*
855 * This a a bit weird since generally CL
856 * matches the pipe, but here we need to
857 * pick the CL based on the port.
858 */
859 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)((0x814c) + (ch) * ((0x8098) - (0x814c))));
860 if (pipe != PIPE_B)
861 val &= ~CHV_CMN_USEDCLKCHANNEL(1 << 13);
862 else
863 val |= CHV_CMN_USEDCLKCHANNEL(1 << 13);
864 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch)((0x814c) + (ch) * ((0x8098) - (0x814c))), val);
865
866 vlv_dpio_put(dev_priv);
867}
868
869void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
870 const struct intel_crtc_state *crtc_state)
871{
872 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
873 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
874 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
876 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
877 enum pipe pipe = crtc->pipe;
878 int data, i, stagger;
879 u32 val;
880
881 vlv_dpio_get(dev_priv);
882
883 /* allow hardware to manage TX FIFO reset source */
884 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)((0x022c) + (ch) * ((0x262c) - (0x022c))));
885 val &= ~DPIO_LANEDESKEW_STRAP_OVRD(1 << 3);
886 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch)((0x022c) + (ch) * ((0x262c) - (0x022c))), val);
887
888 if (crtc_state->lane_count > 2) {
889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)((0x042c) + (ch) * ((0x282c) - (0x042c))));
890 val &= ~DPIO_LANEDESKEW_STRAP_OVRD(1 << 3);
891 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch)((0x042c) + (ch) * ((0x282c) - (0x042c))), val);
892 }
893
894 /* Program Tx lane latency optimal setting*/
895 for (i = 0; i < crtc_state->lane_count; i++) {
896 /* Set the upar bit */
897 if (crtc_state->lane_count == 1)
898 data = 0x0;
899 else
900 data = (i == 1) ? 0x0 : 0x1;
901 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i)((ch ? 0x2400 : 0) + (i) * 0x200 + (0xb8)),
902 data << DPIO_UPAR_SHIFT30);
903 }
904
905 /* Data lane stagger programming */
906 if (crtc_state->port_clock > 270000)
907 stagger = 0x18;
908 else if (crtc_state->port_clock > 135000)
909 stagger = 0xd;
910 else if (crtc_state->port_clock > 67500)
911 stagger = 0x7;
912 else if (crtc_state->port_clock > 33750)
913 stagger = 0x4;
914 else
915 stagger = 0x2;
916
917 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)((0x022c) + (ch) * ((0x262c) - (0x022c))));
918 val |= DPIO_TX2_STAGGER_MASK(0x1f)((0x1f) << 24);
919 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch)((0x022c) + (ch) * ((0x262c) - (0x022c))), val);
920
921 if (crtc_state->lane_count > 2) {
922 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)((0x042c) + (ch) * ((0x282c) - (0x042c))));
923 val |= DPIO_TX2_STAGGER_MASK(0x1f)((0x1f) << 24);
924 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch)((0x042c) + (ch) * ((0x282c) - (0x042c))), val);
925 }
926
927 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch)((0x0230) + (ch) * ((0x2630) - (0x0230))),
928 DPIO_LANESTAGGER_STRAP(stagger)((stagger) << 0) |
929 DPIO_LANESTAGGER_STRAP_OVRD(1 << 6) |
930 DPIO_TX1_STAGGER_MASK(0x1f)((0x1f) << 8) |
931 DPIO_TX1_STAGGER_MULT(6)((6) << 16) |
932 DPIO_TX2_STAGGER_MULT(0)((0) << 20));
933
934 if (crtc_state->lane_count > 2) {
935 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch)((0x0430) + (ch) * ((0x2830) - (0x0430))),
936 DPIO_LANESTAGGER_STRAP(stagger)((stagger) << 0) |
937 DPIO_LANESTAGGER_STRAP_OVRD(1 << 6) |
938 DPIO_TX1_STAGGER_MASK(0x1f)((0x1f) << 8) |
939 DPIO_TX1_STAGGER_MULT(7)((7) << 16) |
940 DPIO_TX2_STAGGER_MULT(5)((5) << 20));
941 }
942
943 /* Deassert data lane reset */
944 chv_data_lane_soft_reset(encoder, crtc_state, false0);
945
946 vlv_dpio_put(dev_priv);
947}
948
949void chv_phy_release_cl2_override(struct intel_encoder *encoder)
950{
951 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
952 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
953
954 if (dig_port->release_cl2_override) {
955 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false0);
956 dig_port->release_cl2_override = false0;
957 }
958}
959
960void chv_phy_post_pll_disable(struct intel_encoder *encoder,
961 const struct intel_crtc_state *old_crtc_state)
962{
963 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
964 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
*)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
->pipe;
965 u32 val;
966
967 vlv_dpio_get(dev_priv);
968
969 /* disable left/right clock distribution */
970 if (pipe != PIPE_B) {
971 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH00x8114);
972 val &= ~(CHV_BUFLEFTENA1_MASK(3 << 22) | CHV_BUFRIGHTENA1_MASK(3 << 20));
973 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH00x8114, val);
974 } else {
975 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH10x8084);
976 val &= ~(CHV_BUFLEFTENA2_MASK(3 << 17) | CHV_BUFRIGHTENA2_MASK(3 << 19));
977 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH10x8084, val);
978 }
979
980 vlv_dpio_put(dev_priv);
981
982 /*
983 * Leave the power down bit cleared for at least one
984 * lane so that chv_powergate_phy_ch() will power
985 * on something when the channel is otherwise unused.
986 * When the port is off and the override is removed
987 * the lanes power down anyway, so otherwise it doesn't
988 * really matter what the state of power down bits is
989 * after this.
990 */
991 chv_phy_powergate_lanes(encoder, false0, 0x0);
992}
993
994void vlv_set_phy_signal_level(struct intel_encoder *encoder,
995 u32 demph_reg_value, u32 preemph_reg_value,
996 u32 uniqtranscale_reg_value, u32 tx3_demph)
997{
998 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
999 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (encoder->base.crtc); (struct intel_crtc *)( (char *)__mptr
- __builtin_offsetof(struct intel_crtc, base) );})
;
1000 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1001 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1002 enum pipe pipe = intel_crtc->pipe;
1003
1004 vlv_dpio_get(dev_priv);
1005
1006 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port)((0x8294) + (port) * ((0x8494) - (0x8294))), 0x00000000);
1007 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port)((0x8290) + (port) * ((0x8490) - (0x8290))), demph_reg_value);
1008 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port)((0x8288) + (port) * ((0x8488) - (0x8288))),
1009 uniqtranscale_reg_value);
1010 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port)((0x828c) + (port) * ((0x848c) - (0x828c))), 0x0C782040);
1011
1012 if (tx3_demph)
1013 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port)((0x690) + (port) * ((0x2a90) - (0x690))), tx3_demph);
1014
1015 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port)((0x822c) + (port) * ((0x842c) - (0x822c))), 0x00030000);
1016 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port)((0x8224) + (port) * ((0x8424) - (0x8224))), preemph_reg_value);
1017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port)((0x8294) + (port) * ((0x8494) - (0x8294))), DPIO_TX_OCALINIT_EN(1 << 31));
1018
1019 vlv_dpio_put(dev_priv);
1020}
1021
1022void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1023 const struct intel_crtc_state *crtc_state)
1024{
1025 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1026 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1027 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1028 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1029 enum pipe pipe = crtc->pipe;
1030
1031 /* Program Tx lane resets to default */
1032 vlv_dpio_get(dev_priv);
1033
1034 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port)((0x8200) + (port) * ((0x8400) - (0x8200))),
1035 DPIO_PCS_TX_LANE2_RESET(1 << 16) |
1036 DPIO_PCS_TX_LANE1_RESET(1 << 7));
1037 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port)((0x8204) + (port) * ((0x8404) - (0x8204))),
1038 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN(1 << 22) |
1039 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN(1 << 21) |
1040 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT(6)) |
1041 DPIO_PCS_CLK_SOFT_RESET(1 << 5));
1042
1043 /* Fix up inter-pair skew failure */
1044 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port)((0x8230) + (port) * ((0x8430) - (0x8230))), 0x00750f00);
1045 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port)((0x82ac) + (port) * ((0x84ac) - (0x82ac))), 0x00001500);
1046 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port)((0x82b8) + (port) * ((0x84b8) - (0x82b8))), 0x40400000);
1047
1048 vlv_dpio_put(dev_priv);
1049}
1050
1051void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1052 const struct intel_crtc_state *crtc_state)
1053{
1054 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1055 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1056 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1057 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1058 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1059 enum pipe pipe = crtc->pipe;
1060 u32 val;
1061
1062 vlv_dpio_get(dev_priv);
1063
1064 /* Enable clock channels for this port */
1065 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)((0x0220) + (port) * ((0x2620) - (0x0220))));
Value stored to 'val' is never read
1066 val = 0;
1067 if (pipe)
1068 val |= (1<<21);
1069 else
1070 val &= ~(1<<21);
1071 val |= 0x001000c4;
1072 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port)((0x8220) + (port) * ((0x8420) - (0x8220))), val);
1073
1074 /* Program lane clock */
1075 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port)((0x8238) + (port) * ((0x8438) - (0x8238))), 0x00760018);
1076 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port)((0x825c) + (port) * ((0x845c) - (0x825c))), 0x00400888);
1077
1078 vlv_dpio_put(dev_priv);
1079}
1080
1081void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1082 const struct intel_crtc_state *old_crtc_state)
1083{
1084 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1085 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1086 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
*)__mptr - __builtin_offsetof(struct intel_crtc, base) );})
;
1087 enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1088 enum pipe pipe = crtc->pipe;
1089
1090 vlv_dpio_get(dev_priv);
1091 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port)((0x8200) + (port) * ((0x8400) - (0x8200))), 0x00000000);
1092 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port)((0x8204) + (port) * ((0x8404) - (0x8204))), 0x00e00060);
1093 vlv_dpio_put(dev_priv);
1094}