/usr/src/sys/dev/ic/athn.c

Bug Summary

File:	dev/ic/athn.c
Warning:	line 223, column 41 The result of the left shift is undefined because the left operand is negative
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name athn.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/ic/athn.c
1/*	$OpenBSD: athn.c,v 1.111 2021/04/15 18:25:43 stsp Exp $	*/

3/*-
* Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
* Copyright (c) 2008-2010 Atheros Communications Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/

20/*
* Driver for Atheros 802.11a/g/n chipsets.
*/

24#include "athn_usb.h"
25#include "bpfilter.h"

27#include <sys/param.h>
28#include <sys/sockio.h>
29#include <sys/mbuf.h>
30#include <sys/kernel.h>
31#include <sys/socket.h>
32#include <sys/systm.h>
33#include <sys/malloc.h>
34#include <sys/queue.h>
35#include <sys/timeout.h>
36#include <sys/conf.h>
37#include <sys/device.h>
38#include <sys/stdint.h>	/* uintptr_t */
39#include <sys/endian.h>

41#include <machine/bus.h>
42#include <machine/intr.h>

44#if NBPFILTER1 > 0
45#include <net/bpf.h>
46#endif
47#include <net/if.h>
48#include <net/if_dl.h>
49#include <net/if_media.h>

51#include <netinet/in.h>
52#include <netinet/if_ether.h>

54#include <net80211/ieee80211_var.h>
55#include <net80211/ieee80211_amrr.h>
56#include <net80211/ieee80211_ra.h>
57#include <net80211/ieee80211_radiotap.h>

59#include <dev/ic/athnreg.h>
60#include <dev/ic/athnvar.h>

62#ifdef ATHN_DEBUG
63int athn_debug = 0;
64#endif

66void		athn_radiotap_attach(struct athn_softc *);
67void		athn_get_chanlist(struct athn_softc *);
68const char *	athn_get_mac_name(struct athn_softc *);
69const char *	athn_get_rf_name(struct athn_softc *);
70void		athn_led_init(struct athn_softc *);
71void		athn_set_led(struct athn_softc *, int);
72void		athn_btcoex_init(struct athn_softc *);
73void		athn_btcoex_enable(struct athn_softc *);
74void		athn_btcoex_disable(struct athn_softc *);
75void		athn_set_rxfilter(struct athn_softc *, uint32_t);
76void		athn_get_chipid(struct athn_softc *);
77int		athn_reset_power_on(struct athn_softc *);
78int		athn_reset(struct athn_softc *, int);
79void		athn_init_pll(struct athn_softc *,
    const struct ieee80211_channel *);
81int		athn_set_power_awake(struct athn_softc *);
82void		athn_set_power_sleep(struct athn_softc *);
83void		athn_write_serdes(struct athn_softc *,
    const struct athn_serdes *);
85void		athn_config_pcie(struct athn_softc *);
86void		athn_config_nonpcie(struct athn_softc *);
87int		athn_set_chan(struct athn_softc *, struct ieee80211_channel *,
    struct ieee80211_channel *);
89int		athn_switch_chan(struct athn_softc *,
    struct ieee80211_channel *, struct ieee80211_channel *);
91void		athn_get_delta_slope(uint32_t, uint32_t *, uint32_t *);
92void		athn_reset_key(struct athn_softc *, int);
93int		athn_set_key(struct ieee80211com *, struct ieee80211_node *,
    struct ieee80211_key *);
95void		athn_delete_key(struct ieee80211com *, struct ieee80211_node *,
    struct ieee80211_key *);
97void		athn_iter_calib(void *, struct ieee80211_node *);
98int		athn_cap_noisefloor(struct athn_softc *, int);
99int		athn_nf_hist_mid(int *, int);
100void		athn_filter_noisefloor(struct athn_softc *);
101void		athn_start_noisefloor_calib(struct athn_softc *, int);
102void		athn_calib_to(void *);
103int		athn_init_calib(struct athn_softc *,
    struct ieee80211_channel *, struct ieee80211_channel *);
105uint8_t		athn_chan2fbin(struct ieee80211_channel *);
106int		athn_interpolate(int, int, int, int, int);
107void		athn_get_pier_ival(uint8_t, const uint8_t *, int, int *,
    int *);
109void		athn_init_dma(struct athn_softc *);
110void		athn_rx_start(struct athn_softc *);
111void		athn_inc_tx_trigger_level(struct athn_softc *);
112int		athn_stop_rx_dma(struct athn_softc *);
113int		athn_rx_abort(struct athn_softc *);
114void		athn_tx_reclaim(struct athn_softc *, int);
115int		athn_tx_pending(struct athn_softc *, int);
116void		athn_stop_tx_dma(struct athn_softc *, int);
117int		athn_txtime(struct athn_softc *, int, int, u_int);
118void		athn_set_sta_timers(struct athn_softc *);
119void		athn_set_hostap_timers(struct athn_softc *);
120void		athn_set_opmode(struct athn_softc *);
121void		athn_set_bss(struct athn_softc *, struct ieee80211_node *);
122void		athn_enable_interrupts(struct athn_softc *);
123void		athn_disable_interrupts(struct athn_softc *);
124void		athn_init_qos(struct athn_softc *);
125int		athn_hw_reset(struct athn_softc *, struct ieee80211_channel *,
    struct ieee80211_channel *, int);
127struct		ieee80211_node *athn_node_alloc(struct ieee80211com *);
128void		athn_newassoc(struct ieee80211com *, struct ieee80211_node *,
    int);
130int		athn_media_change(struct ifnet *);
131void		athn_next_scan(void *);
132int		athn_newstate(struct ieee80211com *, enum ieee80211_state,
    int);
134void		athn_updateedca(struct ieee80211com *);
135int		athn_clock_rate(struct athn_softc *);
136int		athn_chan_sifs(struct ieee80211_channel *);
137void		athn_setsifs(struct athn_softc *);
138int		athn_acktimeout(struct ieee80211_channel *, int);
139void		athn_setacktimeout(struct athn_softc *,
    struct ieee80211_channel *, int);
141void		athn_setctstimeout(struct athn_softc *,
    struct ieee80211_channel *, int);
143void		athn_setclockrate(struct athn_softc *);
144void		athn_updateslot(struct ieee80211com *);
145void		athn_start(struct ifnet *);
146void		athn_watchdog(struct ifnet *);
147void		athn_set_multi(struct athn_softc *);
148int		athn_ioctl(struct ifnet *, u_long, caddr_t);
149int		athn_init(struct ifnet *);
150void		athn_stop(struct ifnet *, int);
151void		athn_init_tx_queues(struct athn_softc *);
152int32_t		athn_ani_get_rssi(struct athn_softc *);
153void		athn_ani_ofdm_err_trigger(struct athn_softc *);
154void		athn_ani_cck_err_trigger(struct athn_softc *);
155void		athn_ani_lower_immunity(struct athn_softc *);
156void		athn_ani_restart(struct athn_softc *);
157void		athn_ani_monitor(struct athn_softc *);

159/* Extern functions. */
160int		ar5416_attach(struct athn_softc *);
161int		ar9280_attach(struct athn_softc *);
162int		ar9285_attach(struct athn_softc *);
163int		ar9287_attach(struct athn_softc *);
164int		ar9380_attach(struct athn_softc *);
165int		ar5416_init_calib(struct athn_softc *,
    struct ieee80211_channel *, struct ieee80211_channel *);
167int		ar9285_init_calib(struct athn_softc *,
    struct ieee80211_channel *, struct ieee80211_channel *);
169int		ar9003_init_calib(struct athn_softc *);
170void		ar9285_pa_calib(struct athn_softc *);
171void		ar9271_pa_calib(struct athn_softc *);
172void		ar9287_1_3_enable_async_fifo(struct athn_softc *);
173void		ar9287_1_3_setup_async_fifo(struct athn_softc *);
174void		ar9003_reset_txsring(struct athn_softc *);

176struct cfdriver athn_cd = {
NULL((void *)0), "athn", DV_IFNET
178};

180void
181athn_config_ht(struct athn_softc *sc)
182{
struct ieee80211com *ic = &sc->sc_ic;
int i, ntxstreams, nrxstreams;

if ((sc->flags & ATHN_FLAG_11N(1 << 11)) == 0)
13
←
Assuming the condition is false→
14
←
Taking false branch→
return;

/* Set HT capabilities. */
ic->ic_htcaps = (IEEE80211_HTCAP_SMPS_DIS3 <<
   IEEE80211_HTCAP_SMPS_SHIFT2);
192#ifdef notyet
ic->ic_htcaps |= IEEE80211_HTCAP_CBW20_400x00000002 |
   IEEE80211_HTCAP_SGI400x00000040 |
   IEEE80211_HTCAP_DSSSCCK400x00001000;
196#endif
ic->ic_htxcaps = 0;
198#ifdef notyet
if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140) || AR_SREV_9287_10_OR_LATER(sc)((sc)->mac_ver >= 0x180))
ic->ic_htcaps |= IEEE80211_HTCAP_SGI200x00000020;
if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
ic->ic_htcaps |= IEEE80211_HTCAP_LDPC0x00000001;
if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080)) {
ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC0x00000080;
ic->ic_htcaps |= 1 << IEEE80211_HTCAP_RXSTBC_SHIFT8;
}
207#endif
ntxstreams = sc->ntxchains;
nrxstreams = sc->nrxchains;
if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
15
←
Assuming field 'mac_ver' is < 448→
ntxstreams = MIN(ntxstreams, 2)(((ntxstreams)<(2))?(ntxstreams):(2));
16
←
Taking true branch→
17
←
Assuming 'ntxstreams' is < 2→
18
←
'?' condition is true→
nrxstreams = MIN(nrxstreams, 2)(((nrxstreams)<(2))?(nrxstreams):(2));
19
←
Assuming 'nrxstreams' is < 2→
20
←
'?' condition is true→
}
/* Set supported HT rates. */
if (ic->ic_userflags & IEEE80211_F_NOMIMO0x00000008)
21
←
Assuming the condition is false→
22
←
Taking false branch→
ntxstreams = nrxstreams = 1;
memset(ic->ic_sup_mcs, 0, sizeof(ic->ic_sup_mcs))__builtin_memset((ic->ic_sup_mcs), (0), (sizeof(ic->ic_sup_mcs
)));
for (i = 0; i < nrxstreams; i++)
23
←
Assuming 'i' is < 'nrxstreams'→
24
←
Loop condition is true.  Entering loop body→
25
←
Loop condition is false. Execution continues on line 220→
ic->ic_sup_mcs[i] = 0xff;
ic->ic_tx_mcs_set = IEEE80211_TX_MCS_SET_DEFINED0x01;
if (ntxstreams != nrxstreams) {
26
←
Assuming 'ntxstreams' is not equal to 'nrxstreams'→
27
←
Taking true branch→
ic->ic_tx_mcs_set |= IEEE80211_TX_RX_MCS_NOT_EQUAL0x02;
ic->ic_tx_mcs_set |= (ntxstreams - 1) << 2;
28
←
The result of the left shift is undefined because the left operand is negative
}
225}

227int
228athn_attach(struct athn_softc *sc)
229{
struct ieee80211com *ic = &sc->sc_ic;
struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
int error;

/* Read hardware revision. */
athn_get_chipid(sc);

if ((error = athn_reset_power_on(sc)) != 0) {
printf("%s: could not reset chip\n", sc->sc_dev.dv_xname);
return (error);
}

if ((error = athn_set_power_awake(sc)) != 0) {
printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname);
return (error);
}

if (AR_SREV_5416(sc)((sc)->mac_ver == 0x00d || (sc)->mac_ver == 0x00c) || AR_SREV_9160(sc)((sc)->mac_ver == 0x040))
error = ar5416_attach(sc);
else if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080))
error = ar9280_attach(sc);
else if (AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0))
error = ar9285_attach(sc);
253#if NATHN_USB1 > 0
else if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140))
error = ar9285_attach(sc);
256#endif
else if (AR_SREV_9287(sc)((sc)->mac_ver == 0x180))
error = ar9287_attach(sc);
else if (AR_SREV_9380(sc)((sc)->mac_ver == 0x1c0) || AR_SREV_9485(sc)((sc)->mac_ver == 0x240))
error = ar9380_attach(sc);
else
error = ENOTSUP91;
if (error != 0) {
printf("%s: could not attach chip\n", sc->sc_dev.dv_xname);
return (error);
}

/* We can put the chip in sleep state now. */
athn_set_power_sleep(sc);

if (!(sc->flags & ATHN_FLAG_USB(1 << 1))) {
error = sc->ops.dma_alloc(sc);
if (error != 0) {
	printf("%s: could not allocate DMA resources\n",
	    sc->sc_dev.dv_xname);
	return (error);
}
/* Steal one Tx buffer for beacons. */
sc->bcnbuf = SIMPLEQ_FIRST(&sc->txbufs)((&sc->txbufs)->sqh_first);
SIMPLEQ_REMOVE_HEAD(&sc->txbufs, bf_list)do { if (((&sc->txbufs)->sqh_first = (&sc->txbufs
)->sqh_first->bf_list.sqe_next) == ((void *)0)) (&sc
->txbufs)->sqh_last = &(&sc->txbufs)->sqh_first
; } while (0);
}

if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5)) {
DPRINTF(("found RF switch connected to GPIO pin %d\n",
    sc->rfsilent_pin));
}
DPRINTF(("%d key cache entries\n", sc->kc_entries));
/*
* In HostAP mode, the number of STAs that we can handle is
* limited by the number of entries in the HW key cache.
* TKIP keys would consume 2 entries in this cache but we
* only use the hardware crypto engine for CCMP.
*/
ic->ic_max_nnodes = sc->kc_entries - IEEE80211_WEP_NKID4;
if (ic->ic_max_nnodes > IEEE80211_CACHE_SIZE512)
ic->ic_max_nnodes = IEEE80211_CACHE_SIZE512;

DPRINTF(("using %s loop power control\n",
   (sc->flags & ATHN_FLAG_OLPC) ? "open" : "closed"));

DPRINTF(("txchainmask=0x%x rxchainmask=0x%x\n",
   sc->txchainmask, sc->rxchainmask));
/* Count the number of bits set (in lowest 3 bits). */
sc->ntxchains =
   ((sc->txchainmask >> 2) & 1) +
   ((sc->txchainmask >> 1) & 1) +
   ((sc->txchainmask >> 0) & 1);
sc->nrxchains =
   ((sc->rxchainmask >> 2) & 1) +
   ((sc->rxchainmask >> 1) & 1) +
   ((sc->rxchainmask >> 0) & 1);

if (AR_SINGLE_CHIP(sc)((sc)->mac_ver >= 0x080)) {
printf("%s: %s rev %d (%dT%dR), ROM rev %d, address %s\n",
    sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev,
    sc->ntxchains, sc->nrxchains, sc->eep_rev,
    ether_sprintf(ic->ic_myaddr));
} else {
printf("%s: MAC %s rev %d, RF %s (%dT%dR), ROM rev %d, "
    "address %s\n",
    sc->sc_dev.dv_xname, athn_get_mac_name(sc), sc->mac_rev,
    athn_get_rf_name(sc), sc->ntxchains, sc->nrxchains,
    sc->eep_rev, ether_sprintf(ic->ic_myaddr));
}

timeout_set(&sc->scan_to, athn_next_scan, sc);
timeout_set(&sc->calib_to, athn_calib_to, sc);

sc->amrr.amrr_min_success_threshold =  1;
sc->amrr.amrr_max_success_threshold = 15;

ic->ic_phytype = IEEE80211_T_OFDM;	/* not only, but not used */
ic->ic_opmode = IEEE80211_M_STA;	/* default to BSS mode */
ic->ic_state = IEEE80211_S_INIT;

/* Set device capabilities. */
ic->ic_caps =
   IEEE80211_C_WEP0x00000001 |		/* WEP. */
   IEEE80211_C_RSN0x00001000 |		/* WPA/RSN. */
340#ifndef IEEE80211_STA_ONLY
   IEEE80211_C_HOSTAP0x00000008 |	/* Host AP mode supported. */
   IEEE80211_C_APPMGT0x00000020 |	/* Host AP power saving supported. */
343#endif
   IEEE80211_C_MONITOR0x00000200 |	/* Monitor mode supported. */
   IEEE80211_C_SHSLOT0x00000080 |	/* Short slot time supported. */
   IEEE80211_C_SHPREAMBLE0x00000100 |	/* Short preamble supported. */
   IEEE80211_C_PMGT0x00000004;		/* Power saving supported. */

athn_config_ht(sc);

/* Set supported rates. */
if (sc->flags & ATHN_FLAG_11G(1 << 10)) {
ic->ic_sup_rates[IEEE80211_MODE_11B] =
    ieee80211_std_rateset_11b;
ic->ic_sup_rates[IEEE80211_MODE_11G] =
    ieee80211_std_rateset_11g;
}
if (sc->flags & ATHN_FLAG_11A(1 << 9)) {
ic->ic_sup_rates[IEEE80211_MODE_11A] =
    ieee80211_std_rateset_11a;
}

/* Get the list of authorized/supported channels. */
athn_get_chanlist(sc);

/* IBSS channel undefined for now. */
ic->ic_ibss_chan = &ic->ic_channels[0];

ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_ioctl = athn_ioctl;
ifp->if_start = athn_start;
ifp->if_watchdog = athn_watchdog;
memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ)__builtin_memcpy((ifp->if_xname), (sc->sc_dev.dv_xname)
, (16));

if_attach(ifp);
ieee80211_ifattach(ifp);
ic->ic_node_alloc = athn_node_alloc;
ic->ic_newassoc = athn_newassoc;
ic->ic_updateslot = athn_updateslot;
ic->ic_updateedca = athn_updateedca;
ic->ic_set_key = athn_set_key;
ic->ic_delete_key = athn_delete_key;

/* Override 802.11 state transition machine. */
sc->sc_newstate = ic->ic_newstate;
ic->ic_newstate = athn_newstate;
ieee80211_media_init(ifp, athn_media_change, ieee80211_media_status);

390#if NBPFILTER1 > 0
athn_radiotap_attach(sc);
392#endif

return (0);
395}

397void
398athn_detach(struct athn_softc *sc)
399{
struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;
int qid;

timeout_del(&sc->scan_to);
timeout_del(&sc->calib_to);

if (!(sc->flags & ATHN_FLAG_USB(1 << 1))) {
for (qid = 0; qid < ATHN_QID_COUNT8; qid++)
	athn_tx_reclaim(sc, qid);

/* Free Tx/Rx DMA resources. */
sc->ops.dma_free(sc);
}
/* Free ROM copy. */
if (sc->eep != NULL((void *)0))
free(sc->eep, M_DEVBUF2, 0);

ieee80211_ifdetach(ifp);
if_detach(ifp);
419}

421#if NBPFILTER1 > 0
422/*
* Attach the interface to 802.11 radiotap.
*/
425void
426athn_radiotap_attach(struct athn_softc *sc)
427{
bpfattach(&sc->sc_drvbpf, &sc->sc_ic.ic_ific_ac.ac_if, DLT_IEEE802_11_RADIO127,
   sizeof(struct ieee80211_frame) + IEEE80211_RADIOTAP_HDRLEN64);

sc->sc_rxtap_len = sizeof(sc->sc_rxtapu);
sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_len = htole16(sc->sc_rxtap_len)((__uint16_t)(sc->sc_rxtap_len));
sc->sc_rxtapsc_rxtapu.th.wr_ihdr.it_present = htole32(ATHN_RX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_TSFT | 1 <<
 IEEE80211_RADIOTAP_FLAGS | 1 << IEEE80211_RADIOTAP_RATE
 | 1 << IEEE80211_RADIOTAP_CHANNEL | 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL
 | 1 << IEEE80211_RADIOTAP_ANTENNA)));

sc->sc_txtap_len = sizeof(sc->sc_txtapu);
sc->sc_txtapsc_txtapu.th.wt_ihdr.it_len = htole16(sc->sc_txtap_len)((__uint16_t)(sc->sc_txtap_len));
sc->sc_txtapsc_txtapu.th.wt_ihdr.it_present = htole32(ATHN_TX_RADIOTAP_PRESENT)((__uint32_t)((1 << IEEE80211_RADIOTAP_FLAGS | 1 <<
 IEEE80211_RADIOTAP_RATE | 1 << IEEE80211_RADIOTAP_CHANNEL
)));
438}
439#endif

441void
442athn_get_chanlist(struct athn_softc *sc)
443{
struct ieee80211com *ic = &sc->sc_ic;
uint8_t chan;
int i;

if (sc->flags & ATHN_FLAG_11G(1 << 10)) {
for (i = 1; i <= 14; i++) {
	chan = i;
	ic->ic_channels[chan].ic_freq =
	    ieee80211_ieee2mhz(chan, IEEE80211_CHAN_2GHZ0x0080);
	ic->ic_channels[chan].ic_flags =
	    IEEE80211_CHAN_CCK0x0020 | IEEE80211_CHAN_OFDM0x0040 |
	    IEEE80211_CHAN_DYN0x0400 | IEEE80211_CHAN_2GHZ0x0080;
	if (sc->flags & ATHN_FLAG_11N(1 << 11))
		ic->ic_channels[chan].ic_flags |=
		    IEEE80211_CHAN_HT0x2000;
}
}
if (sc->flags & ATHN_FLAG_11A(1 << 9)) {
for (i = 0; i < nitems(athn_5ghz_chans)(sizeof((athn_5ghz_chans)) / sizeof((athn_5ghz_chans)[0])); i++) {
	chan = athn_5ghz_chans[i];
	ic->ic_channels[chan].ic_freq =
	    ieee80211_ieee2mhz(chan, IEEE80211_CHAN_5GHZ0x0100);
	ic->ic_channels[chan].ic_flags = IEEE80211_CHAN_A(0x0100 | 0x0040);
	if (sc->flags & ATHN_FLAG_11N(1 << 11))
		ic->ic_channels[chan].ic_flags |=
		    IEEE80211_CHAN_HT0x2000;
}
}
472}

474void
475athn_rx_start(struct athn_softc *sc)
476{
struct ieee80211com *ic = &sc->sc_ic;
uint32_t rfilt;

/* Setup Rx DMA descriptors. */
sc->ops.rx_enable(sc);

/* Set Rx filter. */
rfilt = AR_RX_FILTER_UCAST0x00000001 | AR_RX_FILTER_BCAST0x00000004 | AR_RX_FILTER_MCAST0x00000002;
/* Want Compressed Block Ack Requests. */
rfilt |= AR_RX_FILTER_COMPR_BAR0x00000400;
rfilt |= AR_RX_FILTER_BEACON0x00000010;
if (ic->ic_opmode != IEEE80211_M_STA) {
rfilt |= AR_RX_FILTER_PROBEREQ0x00000080;
if (ic->ic_opmode == IEEE80211_M_MONITOR)
	rfilt |= AR_RX_FILTER_PROM0x00000020;
492#ifndef IEEE80211_STA_ONLY
if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080) &&
    ic->ic_opmode == IEEE80211_M_HOSTAP)
	rfilt |= AR_RX_FILTER_PSPOLL0x00004000;
496#endif
}
athn_set_rxfilter(sc, rfilt);

/* Set BSSID mask. */
AR_WRITE(sc, AR_BSSMSKL, 0xffffffff)(sc)->ops.write((sc), (0x80e0), (0xffffffff));
AR_WRITE(sc, AR_BSSMSKU, 0xffff)(sc)->ops.write((sc), (0x80e4), (0xffff));

athn_set_opmode(sc);

/* Set multicast filter. */
AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff)(sc)->ops.write((sc), (0x8040), (0xffffffff));
AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff)(sc)->ops.write((sc), (0x8044), (0xffffffff));

AR_WRITE(sc, AR_FILT_OFDM, 0)(sc)->ops.write((sc), (0x8124), (0));
AR_WRITE(sc, AR_FILT_CCK, 0)(sc)->ops.write((sc), (0x8128), (0));
AR_WRITE(sc, AR_MIBC, 0)(sc)->ops.write((sc), (0x0040), (0));
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING)(sc)->ops.write((sc), (0x8130), (0x00020000));
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING)(sc)->ops.write((sc), (0x8138), (0x02000000));

/* XXX ANI. */
AR_WRITE(sc, AR_PHY_ERR_1, 0)(sc)->ops.write((sc), (0x812c), (0));
AR_WRITE(sc, AR_PHY_ERR_2, 0)(sc)->ops.write((sc), (0x8134), (0));

/* Disable HW crypto for now. */
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) | (0x00000008 | 0x00000010)));

/* Start PCU Rx. */
AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) & ~(0x00000020 | 0x02000000)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
526}

528void
529athn_set_rxfilter(struct athn_softc *sc, uint32_t rfilt)
530{
AR_WRITE(sc, AR_RX_FILTER, rfilt)(sc)->ops.write((sc), (0x803c), (rfilt));

533#ifdef notyet
reg = AR_READ(sc, AR_PHY_ERR)(sc)->ops.read((sc), (0x810c));
reg &= (AR_PHY_ERR_RADAR0x00000020 | AR_PHY_ERR_OFDM_TIMING0x00020000 |
   AR_PHY_ERR_CCK_TIMING0x02000000);
AR_WRITE(sc, AR_PHY_ERR, reg)(sc)->ops.write((sc), (0x810c), (reg));
if (reg != 0)
AR_SETBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA)(sc)->ops.write((sc), (0x0034), ((sc)->ops.read((sc), (
0x0034)) | (0x00000010)));
else
AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA)(sc)->ops.write((sc), (0x0034), ((sc)->ops.read((sc), (
0x0034)) & ~(0x00000010)));
542#else
AR_WRITE(sc, AR_PHY_ERR, 0)(sc)->ops.write((sc), (0x810c), (0));
AR_CLRBITS(sc, AR_RXCFG, AR_RXCFG_ZLFDMA)(sc)->ops.write((sc), (0x0034), ((sc)->ops.read((sc), (
0x0034)) & ~(0x00000010)));
545#endif
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
547}

549int
550athn_intr(void *xsc)
551{
struct athn_softc *sc = xsc;
struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;

if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) !=
   (IFF_UP0x1 | IFF_RUNNING0x40))
return (0);

return (sc->ops.intr(sc));
560}

562void
563athn_get_chipid(struct athn_softc *sc)
564{
uint32_t reg;

reg = AR_READ(sc, AR_SREV)(sc)->ops.read((sc), (0x4020));
if (MS(reg, AR_SREV_ID)(((uint32_t)(reg) & 0x000000ff) >> 0) == 0xff) {
sc->mac_ver = MS(reg, AR_SREV_VERSION2)(((uint32_t)(reg) & 0xfffc0000) >> 12);
sc->mac_rev = MS(reg, AR_SREV_REVISION2)(((uint32_t)(reg) & 0x00000f00) >> 8);
if (!(reg & AR_SREV_TYPE2_HOST_MODE0x00002000))
	sc->flags |= ATHN_FLAG_PCIE(1 << 0);
} else {
sc->mac_ver = MS(reg, AR_SREV_VERSION)(((uint32_t)(reg) & 0x000000f0) >> 4);
sc->mac_rev = MS(reg, AR_SREV_REVISION)(((uint32_t)(reg) & 0x00000007) >> 0);
if (sc->mac_ver == AR_SREV_VERSION_5416_PCIE0x00c)
	sc->flags |= ATHN_FLAG_PCIE(1 << 0);
}
579}

581const char *
582athn_get_mac_name(struct athn_softc *sc)
583{
switch (sc->mac_ver) {
case AR_SREV_VERSION_5416_PCI0x00d:
return ("AR5416");
case AR_SREV_VERSION_5416_PCIE0x00c:
return ("AR5418");
case AR_SREV_VERSION_91600x040:
return ("AR9160");
case AR_SREV_VERSION_92800x080:
return ("AR9280");
case AR_SREV_VERSION_92850x0c0:
return ("AR9285");
case AR_SREV_VERSION_92710x140:
return ("AR9271");
case AR_SREV_VERSION_92870x180:
return ("AR9287");
case AR_SREV_VERSION_93800x1c0:
return ("AR9380");
case AR_SREV_VERSION_94850x240:
return ("AR9485");
}
return ("unknown");
605}

607/*
* Return RF chip name (not for single-chip solutions).
*/
610const char *
611athn_get_rf_name(struct athn_softc *sc)
612{
KASSERT(!AR_SINGLE_CHIP(sc))((!((sc)->mac_ver >= 0x080)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/ic/athn.c", 613, "!AR_SINGLE_CHIP(sc)"));

switch (sc->rf_rev) {
case AR_RAD5133_SREV_MAJOR0xc0:	/* Dual-band 3T3R. */
return ("AR5133");
case AR_RAD2133_SREV_MAJOR0xd0:	/* Single-band 3T3R. */
return ("AR2133");
case AR_RAD5122_SREV_MAJOR0xe0:	/* Dual-band 2T2R. */
return ("AR5122");
case AR_RAD2122_SREV_MAJOR0xf0:	/* Single-band 2T2R. */
return ("AR2122");
}
return ("unknown");
626}

628int
629athn_reset_power_on(struct athn_softc *sc)
630{
int ntries;

/* Set force wake. */
AR_WRITE(sc, AR_RTC_FORCE_WAKE,(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002))
   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT)(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002));

if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
/* Make sure no DMA is active by doing an AHB reset. */
AR_WRITE(sc, AR_RC, AR_RC_AHB)(sc)->ops.write((sc), (0x4000), (0x00000001));
}
/* RTC reset and clear. */
AR_WRITE(sc, AR_RTC_RESET, 0)(sc)->ops.write((sc), (0x7040), (0));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
DELAY(2)(*delay_func)(2);
if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
AR_WRITE(sc, AR_RC, 0)(sc)->ops.write((sc), (0x4000), (0));
AR_WRITE(sc, AR_RTC_RESET, 1)(sc)->ops.write((sc), (0x7040), (1));

/* Poll until RTC is ON. */
for (ntries = 0; ntries < 1000; ntries++) {
if ((AR_READ(sc, AR_RTC_STATUS)(sc)->ops.read((sc), (0x7044)) & AR_RTC_STATUS_M0x0000000f) ==
    AR_RTC_STATUS_ON0x00000002)
	break;
DELAY(10)(*delay_func)(10);
}
if (ntries == 1000) {
DPRINTF(("RTC not waking up\n"));
return (ETIMEDOUT60);
}
return (athn_reset(sc, 0));
661}

663int
664athn_reset(struct athn_softc *sc, int cold)
665{
int ntries;

/* Set force wake. */
AR_WRITE(sc, AR_RTC_FORCE_WAKE,(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002))
   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT)(sc)->ops.write((sc), (0x704c), (0x00000001 | 0x00000002));

if (AR_READ(sc, AR_INTR_SYNC_CAUSE)(sc)->ops.read((sc), (0x4028)) &
   (AR_INTR_SYNC_LOCAL_TIMEOUT0x00002000 | AR_INTR_SYNC_RADM_CPL_TIMEOUT0x00001000)) {
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0)(sc)->ops.write((sc), (0x402c), (0));
AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |(sc)->ops.write((sc), (0x4000), (0x00000100 | (!((sc)->
mac_ver >= 0x1c0) ? 0x00000001 : 0)))
    (!AR_SREV_9380_10_OR_LATER(sc) ? AR_RC_AHB : 0))(sc)->ops.write((sc), (0x4000), (0x00000100 | (!((sc)->
mac_ver >= 0x1c0) ? 0x00000001 : 0)));
} else if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
AR_WRITE(sc, AR_RC, AR_RC_AHB)(sc)->ops.write((sc), (0x4000), (0x00000001));

AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |(sc)->ops.write((sc), (0x7000), (0x00000001 | (cold ? 0x00000002
 : 0)))
   (cold ? AR_RTC_RC_MAC_COLD : 0))(sc)->ops.write((sc), (0x7000), (0x00000001 | (cold ? 0x00000002
 : 0)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
DELAY(50)(*delay_func)(50);
AR_WRITE(sc, AR_RTC_RC, 0)(sc)->ops.write((sc), (0x7000), (0));
for (ntries = 0; ntries < 1000; ntries++) {
if (!(AR_READ(sc, AR_RTC_RC)(sc)->ops.read((sc), (0x7000)) &
      (AR_RTC_RC_MAC_WARM0x00000001 | AR_RTC_RC_MAC_COLD0x00000002)))
	break;
DELAY(10)(*delay_func)(10);
}
if (ntries == 1000) {
DPRINTF(("RTC stuck in MAC reset\n"));
return (ETIMEDOUT60);
}
AR_WRITE(sc, AR_RC, 0)(sc)->ops.write((sc), (0x4000), (0));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
return (0);
698}

700int
701athn_set_power_awake(struct athn_softc *sc)
702{
int ntries, error;

/* Do a Power-On-Reset if shutdown. */
if ((AR_READ(sc, AR_RTC_STATUS)(sc)->ops.read((sc), (0x7044)) & AR_RTC_STATUS_M0x0000000f) ==
   AR_RTC_STATUS_SHUTDOWN0x00000001) {
if ((error = athn_reset_power_on(sc)) != 0)
	return (error);
if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
	athn_init_pll(sc, NULL((void *)0));
}
AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN)(sc)->ops.write((sc), (0x704c), ((sc)->ops.read((sc), (
0x704c)) | (0x00000001)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
DELAY(50)(*delay_func)(50);	/* Give chip the chance to awake. */

/* Poll until RTC is ON. */
for (ntries = 0; ntries < 4000; ntries++) {
if ((AR_READ(sc, AR_RTC_STATUS)(sc)->ops.read((sc), (0x7044)) & AR_RTC_STATUS_M0x0000000f) ==
    AR_RTC_STATUS_ON0x00000002)
	break;
DELAY(50)(*delay_func)(50);
AR_SETBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN)(sc)->ops.write((sc), (0x704c), ((sc)->ops.read((sc), (
0x704c)) | (0x00000001)));
}
if (ntries == 4000) {
DPRINTF(("RTC not waking up\n"));
return (ETIMEDOUT60);
}

AR_CLRBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV)(sc)->ops.write((sc), (0x8004), ((sc)->ops.read((sc), (
0x8004)) & ~(0x00040000)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
return (0);
733}

735void
736athn_set_power_sleep(struct athn_softc *sc)
737{
AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PWR_SAV)(sc)->ops.write((sc), (0x8004), ((sc)->ops.read((sc), (
0x8004)) | (0x00040000)));
/* Allow the MAC to go to sleep. */
AR_CLRBITS(sc, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN)(sc)->ops.write((sc), (0x704c), ((sc)->ops.read((sc), (
0x704c)) & ~(0x00000001)));
if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF)(sc)->ops.write((sc), (0x4000), (0x00000001 | 0x00000100));
/*
* NB: Clearing RTC_RESET_EN when setting the chip to sleep mode
* results in high power consumption on AR5416 chipsets.
*/
if (!AR_SREV_5416(sc)((sc)->mac_ver == 0x00d || (sc)->mac_ver == 0x00c) && !AR_SREV_9271(sc)((sc)->mac_ver == 0x140))
AR_CLRBITS(sc, AR_RTC_RESET, AR_RTC_RESET_EN)(sc)->ops.write((sc), (0x7040), ((sc)->ops.read((sc), (
0x7040)) & ~(0x00000001)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
750}

752void
753athn_init_pll(struct athn_softc *sc, const struct ieee80211_channel *c)
754{
uint32_t pll;

if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
if (AR_SREV_9485(sc)((sc)->mac_ver == 0x240))
	AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666)(sc)->ops.write((sc), (0x703c), (0x886666));
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x5)(((uint32_t)(0x5) << 10) & 0x00003c00);
pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c)(((uint32_t)(0x2c) << 0) & 0x000003ff);
} else if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080)) {
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05)(((uint32_t)(0x05) << 10) & 0x00003c00);
if (c != NULL((void *)0) && IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0)) {
	if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK(1 << 4))
		pll = 0x142c;
	else if (AR_SREV_9280_20(sc)(((sc)->mac_ver == 0x080) && (sc)->mac_rev >=
 1))
 		pll = 0x2850;
	else
		pll |= SM(AR_RTC_9160_PLL_DIV, 0x28)(((uint32_t)(0x28) << 0) & 0x000003ff);
} else
	pll |= SM(AR_RTC_9160_PLL_DIV, 0x2c)(((uint32_t)(0x2c) << 0) & 0x000003ff);
} else if (AR_SREV_9160_10_OR_LATER(sc)((sc)->mac_ver >= 0x040)) {
pll = SM(AR_RTC_9160_PLL_REFDIV, 0x05)(((uint32_t)(0x05) << 10) & 0x00003c00);
if (c != NULL((void *)0) && IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0))
	pll |= SM(AR_RTC_9160_PLL_DIV, 0x50)(((uint32_t)(0x50) << 0) & 0x000003ff);
else
	pll |= SM(AR_RTC_9160_PLL_DIV, 0x58)(((uint32_t)(0x58) << 0) & 0x000003ff);
} else {
pll = AR_RTC_PLL_REFDIV_50x000000c0 | AR_RTC_PLL_DIV20x00000020;
if (c != NULL((void *)0) && IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0))
	pll |= SM(AR_RTC_PLL_DIV, 0x0a)(((uint32_t)(0x0a) << 0) & 0x0000001f);
else
	pll |= SM(AR_RTC_PLL_DIV, 0x0b)(((uint32_t)(0x0b) << 0) & 0x0000001f);
}
DPRINTFN(5, ("AR_RTC_PLL_CONTROL=0x%08x\n", pll));
AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll)(sc)->ops.write((sc), (0x7014), (pll));
if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) {
/* Switch core clock to 117MHz. */
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
DELAY(500)(*delay_func)(500);
AR_WRITE(sc, AR9271_CLOCK_CONTROL, 0x304)(sc)->ops.write((sc), (0x050040), (0x304));
}
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
DELAY(100)(*delay_func)(100);
AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK)(sc)->ops.write((sc), (0x7048), (0x00000002));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
798}

800void
801athn_write_serdes(struct athn_softc *sc, const struct athn_serdes *serdes)
802{
int i;

/* Write sequence to Serializer/Deserializer. */
for (i = 0; i < serdes->nvals; i++)
AR_WRITE(sc, serdes->regs[i], serdes->vals[i])(sc)->ops.write((sc), (serdes->regs[i]), (serdes->vals
[i]));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
809}

811void
812athn_config_pcie(struct athn_softc *sc)
813{
/* Disable PLL when in L0s as well as receiver clock when in L1. */
athn_write_serdes(sc, sc->serdes);

DELAY(1000)(*delay_func)(1000);
/* Allow forcing of PCIe core into L1 state. */
AR_SETBITS(sc, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA)(sc)->ops.write((sc), (0x4014), ((sc)->ops.read((sc), (
0x4014)) | (0x00080000)));

821#ifndef ATHN_PCIE_WAEN
AR_WRITE(sc, AR_WA, sc->workaround)(sc)->ops.write((sc), (0x4004), (sc->workaround));
823#else
AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN)(sc)->ops.write((sc), (0x4004), (ATHN_PCIE_WAEN));
825#endif
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
827}

829/*
* Serializer/Deserializer programming for non-PCIe devices.
*/
832static const uint32_t ar_nonpcie_serdes_regs[] = {
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES0x4040,
AR_PCIE_SERDES20x4044,
843};

845static const uint32_t ar_nonpcie_serdes_vals[] = {
0x9248fc00,
0x24924924,
0x28000029,
0x57160824,
0x25980579,
0x00000000,
0x1aaabe40,
0xbe105554,
0x000e1007,
0x00000000
856};

858static const struct athn_serdes ar_nonpcie_serdes = {
nitems(ar_nonpcie_serdes_vals)(sizeof((ar_nonpcie_serdes_vals)) / sizeof((ar_nonpcie_serdes_vals
)[0])),
ar_nonpcie_serdes_regs,
ar_nonpcie_serdes_vals
862};

864void
865athn_config_nonpcie(struct athn_softc *sc)
866{
athn_write_serdes(sc, &ar_nonpcie_serdes);
868}

870int
871athn_set_chan(struct athn_softc *sc, struct ieee80211_channel *c,
  struct ieee80211_channel *extc)
873{
struct athn_ops *ops = &sc->ops;
int error, qid;

/* Check that Tx is stopped, otherwise RF Bus grant will not work. */
for (qid = 0; qid < ATHN_QID_COUNT8; qid++)
if (athn_tx_pending(sc, qid))
	return (EBUSY16);

/* Request RF Bus grant. */
if ((error = ops->rf_bus_request(sc)) != 0)
return (error);

ops->set_phy(sc, c, extc);

/* Change the synthesizer. */
if ((error = ops->set_synth(sc, c, extc)) != 0)
return (error);

sc->curchan = c;
sc->curchanext = extc;

/* Set transmit power values for new channel. */
ops->set_txpower(sc, c, extc);

/* Release the RF Bus grant. */
ops->rf_bus_release(sc);

/* Write delta slope coeffs for modes where OFDM may be used. */
if (sc->sc_ic.ic_curmode != IEEE80211_MODE_11B)
ops->set_delta_slope(sc, c, extc);

ops->spur_mitigate(sc, c, extc);

return (0);
908}

910int
911athn_switch_chan(struct athn_softc *sc, struct ieee80211_channel *c,
  struct ieee80211_channel *extc)
913{
int error, qid;

/* Disable interrupts. */
athn_disable_interrupts(sc);

/* Stop all Tx queues. */
for (qid = 0; qid < ATHN_QID_COUNT8; qid++)
athn_stop_tx_dma(sc, qid);
for (qid = 0; qid < ATHN_QID_COUNT8; qid++)
athn_tx_reclaim(sc, qid);

/* Stop Rx. */
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) | (0x00000020 | 0x02000000)));
AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC)(sc)->ops.write((sc), (0x0040), (0x00000002));
AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC)(sc)->ops.write((sc), (0x0040), (0x00000004));
AR_WRITE(sc, AR_FILT_OFDM, 0)(sc)->ops.write((sc), (0x8124), (0));
AR_WRITE(sc, AR_FILT_CCK, 0)(sc)->ops.write((sc), (0x8128), (0));
athn_set_rxfilter(sc, 0);
error = athn_stop_rx_dma(sc);
if (error != 0)
goto reset;

936#ifdef notyet
/* AR9280 needs a full reset. */
if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080))
939#endif
goto reset;

/* If band or bandwidth changes, we need to do a full reset. */
if (c->ic_flags != sc->curchan->ic_flags ||
   ((extc != NULL((void *)0)) ^ (sc->curchanext != NULL((void *)0)))) {
DPRINTFN(2, ("channel band switch\n"));
goto reset;
}
error = athn_set_power_awake(sc);
if (error != 0)
goto reset;

error = athn_set_chan(sc, c, extc);
if (error != 0) {
reset:		/* Error found, try a full reset. */
DPRINTFN(3, ("needs a full reset\n"));
error = athn_hw_reset(sc, c, extc, 0);
if (error != 0)	/* Hopeless case. */
	return (error);
}
athn_rx_start(sc);

/* Re-enable interrupts. */
athn_enable_interrupts(sc);
return (0);
965}

967void
968athn_get_delta_slope(uint32_t coeff, uint32_t *exponent, uint32_t *mantissa)
969{
970#define COEFF_SCALE_SHIFT	24
uint32_t exp, man;

/* exponent = 14 - floor(log2(coeff)) */
for (exp = 31; exp > 0; exp--)
if (coeff & (1 << exp))
	break;
exp = 14 - (exp - COEFF_SCALE_SHIFT);

/* mantissa = floor(coeff * 2^exponent + 0.5) */
man = coeff + (1 << (COEFF_SCALE_SHIFT - exp - 1));

*mantissa = man >> (COEFF_SCALE_SHIFT - exp);
*exponent = exp - 16;
984#undef COEFF_SCALE_SHIFT
985}

987void
988athn_reset_key(struct athn_softc *sc, int entry)
989{
/*
* NB: Key cache registers access special memory area that requires
* two 32-bit writes to actually update the values in the internal
* memory.  Consequently, writes must be grouped by pair.
*
* All writes to registers with an offset of 0x0 or 0x8 write to a
* temporary register. A write to a register with an offset of 0x4
* or 0xc writes concatenates the written value with the value in
* the temporary register and writes the result to key cache memory.
* The actual written memory area is 50 bits wide.
*/
AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 0)), (0)
);
AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 4)), (0)
);

AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 8)), (0)
);
AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 12)), (0
));

AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 16)), (0
));
AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 20)), (7
));

AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 24)), (0
));
AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 28)), (0
));

AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
1014}

1016int
1017athn_set_key(struct ieee80211com *ic, struct ieee80211_node *ni,
  struct ieee80211_key *k)
1019{
struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
const uint8_t *key, *addr;
uintptr_t entry;
uint32_t lo, hi, unicast;

if (k->k_cipher != IEEE80211_CIPHER_CCMP) {
/* Use software crypto for ciphers other than CCMP. */
return ieee80211_set_key(ic, ni, k);
}

if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001)) {
1031#ifndef IEEE80211_STA_ONLY
if (ic->ic_opmode == IEEE80211_M_HOSTAP)
	entry = IEEE80211_WEP_NKID4 + IEEE80211_AID(ni->ni_associd)((ni->ni_associd) &~ 0xc000);
else
1035#endif
	entry = IEEE80211_WEP_NKID4;
if (entry >= sc->kc_entries - IEEE80211_WEP_NKID4)
	return ENOSPC28;
} else {
entry = k->k_id;
if (entry >= IEEE80211_WEP_NKID4)
	return ENOSPC28;
}
k->k_priv = (void *)entry;

/* NB: See note about key cache registers access above. */
key = k->k_key;

AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 0)), (((
&key[ 0])[0] | (&key[ 0])[1] << 8 | (&key[ 0
])[2] << 16 | (&key[ 0])[3] << 24)));
AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 4)), (((
&key[ 4])[0] | (&key[ 4])[1] << 8)));

AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 8)), (((
&key[ 6])[0] | (&key[ 6])[1] << 8 | (&key[ 6
])[2] << 16 | (&key[ 6])[3] << 24)));
AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 12)), ((
(&key[10])[0] | (&key[10])[1] << 8)));

AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]))(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 16)), ((
(&key[12])[0] | (&key[12])[1] << 8 | (&key[
12])[2] << 16 | (&key[12])[3] << 24)));
AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CCM)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 20)), (6
));

unicast = AR_KEYTABLE_VALID0x00008000;
if (!(k->k_flags & IEEE80211_KEY_GROUP0x00000001)) {
addr = ni->ni_macaddr;
lo = LE_READ_4(&addr[0])((&addr[0])[0] | (&addr[0])[1] << 8 | (&addr
[0])[2] << 16 | (&addr[0])[3] << 24);
hi = LE_READ_2(&addr[4])((&addr[4])[0] | (&addr[4])[1] << 8);
lo = lo >> 1 | hi << 31;
hi = hi >> 1;
} else {
1066#ifndef IEEE80211_STA_ONLY
if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
	uint8_t groupaddr[ETHER_ADDR_LEN6];
	IEEE80211_ADDR_COPY(groupaddr, ic->ic_myaddr)__builtin_memcpy((groupaddr), (ic->ic_myaddr), (6));
	groupaddr[0] |= 0x01;
	lo = LE_READ_4(&groupaddr[0])((&groupaddr[0])[0] | (&groupaddr[0])[1] << 8 |
 (&groupaddr[0])[2] << 16 | (&groupaddr[0])[3] <<
 24);
	hi = LE_READ_2(&groupaddr[4])((&groupaddr[4])[0] | (&groupaddr[4])[1] << 8);
	lo = lo >> 1 | hi << 31;
	hi = hi >> 1;
	/*
	 * KEYTABLE_VALID indicates that the address
	 * is a unicast address which must match the
	 * transmitter address when decrypting frames.
	 * Not setting KEYTABLE_VALID allows hardware to
	 * use this key for multicast frame decryption.
	 */
	unicast = 0;
} else
1084#endif
	lo = hi = 0;
}
AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 24)), (lo
));
AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | unicast)(sc)->ops.write((sc), (((0x8800 + (entry) * 32) + 28)), (hi
 | unicast));

AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

/* Enable HW crypto. */
AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_ENCRYPT_DIS | AR_DIAG_DECRYPT_DIS)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) & ~(0x00000008 | 0x00000010)));

AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
return (0);
1097}

1099void
1100athn_delete_key(struct ieee80211com *ic, struct ieee80211_node *ni,
  struct ieee80211_key *k)
1102{
struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
uintptr_t entry;

if (k->k_cipher == IEEE80211_CIPHER_CCMP) {
entry = (uintptr_t)k->k_priv;
athn_reset_key(sc, entry);
explicit_bzero(k, sizeof(*k));
} else
ieee80211_delete_key(ic, ni, k);
1112}

1114void
1115athn_led_init(struct athn_softc *sc)
1116{
struct athn_ops *ops = &sc->ops;

ops->gpio_config_output(sc, sc->led_pin, AR_GPIO_OUTPUT_MUX_AS_OUTPUT0);
/* LED off, active low. */
athn_set_led(sc, 0);
1122}

1124void
1125athn_set_led(struct athn_softc *sc, int on)
1126{
struct athn_ops *ops = &sc->ops;

sc->led_state = on;
ops->gpio_write(sc, sc->led_pin, !sc->led_state);
1131}

1133#ifdef ATHN_BT_COEXISTENCE
1134void
1135athn_btcoex_init(struct athn_softc *sc)
1136{
struct athn_ops *ops = &sc->ops;
uint32_t reg;

if (sc->flags & ATHN_FLAG_BTCOEX2WIRE(1 << 7)) {
/* Connect bt_active to baseband. */
AR_CLRBITS(sc, sc->gpio_input_en_off,(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) & ~(0x00000004
 | 0x00000008)))
    AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) & ~(0x00000004
 | 0x00000008)))
    AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) & ~(0x00000004
 | 0x00000008)));
AR_SETBITS(sc, sc->gpio_input_en_off,(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) | (0x00001000)))
    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) | (0x00001000)));

reg = AR_READ(sc, AR_GPIO_INPUT_MUX1)(sc)->ops.read((sc), (AR_GPIO_INPUT_MUX1));
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) &
 0x000f0000))
    AR_GPIO_BTACTIVE_PIN)(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) &
 0x000f0000));
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg)(sc)->ops.write((sc), (AR_GPIO_INPUT_MUX1), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN6);
} else {	/* 3-wire. */
AR_SETBITS(sc, sc->gpio_input_en_off,(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) | (0x00000400 | 0x00001000
)))
    AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB |(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) | (0x00000400 | 0x00001000
)))
    AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) | (0x00000400 | 0x00001000
)));

reg = AR_READ(sc, AR_GPIO_INPUT_MUX1)(sc)->ops.read((sc), (AR_GPIO_INPUT_MUX1));
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_ACTIVE,(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) &
 0x000f0000))
    AR_GPIO_BTACTIVE_PIN)(((reg) & ~0x000f0000) | (((uint32_t)(6) << 16) &
 0x000f0000));
reg = RW(reg, AR_GPIO_INPUT_MUX1_BT_PRIORITY,(((reg) & ~0x00000f00) | (((uint32_t)(7) << 8) &
 0x00000f00))
    AR_GPIO_BTPRIORITY_PIN)(((reg) & ~0x00000f00) | (((uint32_t)(7) << 8) &
 0x00000f00));
AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg)(sc)->ops.write((sc), (AR_GPIO_INPUT_MUX1), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

ops->gpio_config_input(sc, AR_GPIO_BTACTIVE_PIN6);
ops->gpio_config_input(sc, AR_GPIO_BTPRIORITY_PIN7);
}
1171}

1173void
1174athn_btcoex_enable(struct athn_softc *sc)
1175{
struct athn_ops *ops = &sc->ops;
uint32_t reg;

if (sc->flags & ATHN_FLAG_BTCOEX3WIRE(1 << 8)) {
AR_WRITE(sc, AR_BT_COEX_MODE,(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000))
    SM(AR_BT_MODE, AR_BT_MODE_SLOTTED) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000))
    SM(AR_BT_PRIORITY_TIME, 2) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000))
    SM(AR_BT_FIRST_SLOT_TIME, 5) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000))
    SM(AR_BT_QCU_THRESH, ATHN_QID_AC_BE) |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000))
    AR_BT_TXSTATE_EXTEND | AR_BT_TX_FRAME_EXTEND |(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000))
    AR_BT_QUIET | AR_BT_RX_CLEAR_POLARITY)(sc)->ops.write((sc), (0x8170), ((((uint32_t)(2) << 10
) & 0x00000c00) | (((uint32_t)(2) << 18) & 0x00fc0000
) | (((uint32_t)(5) << 24) & 0xff000000) | (((uint32_t
)(0) << 13) & 0x0001e000) | 0x00000100 | 0x00000200
 | 0x00001000 | 0x00020000));
AR_WRITE(sc, AR_BT_COEX_WEIGHT,(sc)->ops.write((sc), (0x8174), ((((uint32_t)(0xff55) <<
 0) & 0x0000ffff) | (((uint32_t)(0xaaa8) << 16) &
 0xffff0000)))
    SM(AR_BTCOEX_BT_WGHT, AR_STOMP_LOW_BT_WGHT) |(sc)->ops.write((sc), (0x8174), ((((uint32_t)(0xff55) <<
 0) & 0x0000ffff) | (((uint32_t)(0xaaa8) << 16) &
 0xffff0000)))
    SM(AR_BTCOEX_WL_WGHT, AR_STOMP_LOW_WL_WGHT))(sc)->ops.write((sc), (0x8174), ((((uint32_t)(0xff55) <<
 0) & 0x0000ffff) | (((uint32_t)(0xaaa8) << 16) &
 0xffff0000)));
AR_WRITE(sc, AR_BT_COEX_MODE2,(sc)->ops.write((sc), (0x817c), ((((uint32_t)(50) <<
 0) & 0x000000ff) | 0x00010000 | 0x00100000))
    SM(AR_BT_BCN_MISS_THRESH, 50) |(sc)->ops.write((sc), (0x817c), ((((uint32_t)(50) <<
 0) & 0x000000ff) | 0x00010000 | 0x00100000))
    AR_BT_HOLD_RX_CLEAR | AR_BT_DISABLE_BT_ANT)(sc)->ops.write((sc), (0x817c), ((((uint32_t)(50) <<
 0) & 0x000000ff) | 0x00010000 | 0x00100000));

AR_SETBITS(sc, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE)(sc)->ops.write((sc), (0x80fc), ((sc)->ops.read((sc), (
0x80fc)) | (0x00020000)));
AR_CLRBITS(sc, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX)(sc)->ops.write((sc), (0x8120), ((sc)->ops.read((sc), (
0x8120)) & ~(0x00100000)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN5,
    AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL4);

} else {	/* 2-wire. */
ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN5,
    AR_GPIO_OUTPUT_MUX_AS_TX_FRAME3);
}
reg = AR_READ(sc, AR_GPIO_PDPU)(sc)->ops.read((sc), (AR_GPIO_PDPU));
reg &= ~(0x3 << (AR_GPIO_WLANACTIVE_PIN5 * 2));
reg |= 0x2 << (AR_GPIO_WLANACTIVE_PIN5 * 2);
AR_WRITE(sc, AR_GPIO_PDPU, reg)(sc)->ops.write((sc), (AR_GPIO_PDPU), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

/* Disable PCIe Active State Power Management (ASPM). */
if (sc->sc_disable_aspm != NULL((void *)0))
sc->sc_disable_aspm(sc);

/* XXX Start periodic timer. */
1216}

1218void
1219athn_btcoex_disable(struct athn_softc *sc)
1220{
struct athn_ops *ops = &sc->ops;

ops->gpio_write(sc, AR_GPIO_WLANACTIVE_PIN5, 0);

ops->gpio_config_output(sc, AR_GPIO_WLANACTIVE_PIN5,
   AR_GPIO_OUTPUT_MUX_AS_OUTPUT0);

if (sc->flags & ATHN_FLAG_BTCOEX3WIRE(1 << 8)) {
AR_WRITE(sc, AR_BT_COEX_MODE,(sc)->ops.write((sc), (0x8170), ((((uint32_t)(3) << 10
) & 0x00000c00) | 0x00001000))
    SM(AR_BT_MODE, AR_BT_MODE_DISABLED) | AR_BT_QUIET)(sc)->ops.write((sc), (0x8170), ((((uint32_t)(3) << 10
) & 0x00000c00) | 0x00001000));
AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0)(sc)->ops.write((sc), (0x8174), (0));
AR_WRITE(sc, AR_BT_COEX_MODE2, 0)(sc)->ops.write((sc), (0x817c), (0));
/* XXX Stop periodic timer. */
}
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
/* XXX Restore ASPM setting? */
1237}
1238#endif

1240void
1241athn_iter_calib(void *arg, struct ieee80211_node *ni)
1242{
struct athn_softc *sc = arg;
struct athn_node *an = (struct athn_node *)ni;

if ((ni->ni_flags & IEEE80211_NODE_HT0x0400) == 0)
ieee80211_amrr_choose(&sc->amrr, ni, &an->amn);
1248}

1250int
1251athn_cap_noisefloor(struct athn_softc *sc, int nf)
1252{
int16_t min, max;

if (nf == 0 || nf == -1) /* invalid measurement */
return AR_DEFAULT_NOISE_FLOOR(-100);

if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)(((sc->sc_ic.ic_bss->ni_chan)->ic_flags & 0x0080
) != 0)) {
min = sc->cca_min_2g;
max = sc->cca_max_2g;
} else {
min = sc->cca_min_5g;
max = sc->cca_max_5g;
}

if (nf < min)
return min;
if (nf > max)
return max;

return nf;
1272}

1274int
1275athn_nf_hist_mid(int *nf_vals, int nvalid)
1276{
int nf_sorted[ATHN_NF_CAL_HIST_MAX5];
int i, j, nf;

if (nvalid <= 1)
return nf_vals[0];

for (i = 0; i < nvalid; i++)
nf_sorted[i] = nf_vals[i];

for (i = 0; i < nvalid; i++) {
for (j = 1; j < nvalid - i; j++) {
	if (nf_sorted[j] > nf_sorted[j - 1]) {
		nf = nf_sorted[j];
		nf_sorted[j] = nf_sorted[j - 1];
		nf_sorted[j - 1] = nf;
	}
}
}

return nf_sorted[nvalid / 2];
1297}

1299void
1300athn_filter_noisefloor(struct athn_softc *sc)
1301{
int nf_vals[ATHN_NF_CAL_HIST_MAX5];
int nf_ext_vals[ATHN_NF_CAL_HIST_MAX5];
int i, cur, n;

for (i = 0; i < sc->nrxchains; i++) {
if (sc->nf_hist_cur > 0)
	cur = sc->nf_hist_cur - 1;
else
	cur = ATHN_NF_CAL_HIST_MAX5 - 1;
for (n = 0; n < sc->nf_hist_nvalid; n++) {
	nf_vals[n] = sc->nf_hist[cur].nf[i];
	nf_ext_vals[n] = sc->nf_hist[cur].nf_ext[i];
	if (++cur >= ATHN_NF_CAL_HIST_MAX5)
		cur = 0;
}
sc->nf_priv[i] = athn_cap_noisefloor(sc,
    athn_nf_hist_mid(nf_vals, sc->nf_hist_nvalid));
sc->nf_ext_priv[i] = athn_cap_noisefloor(sc,
    athn_nf_hist_mid(nf_ext_vals, sc->nf_hist_nvalid));
}
1322}

1324void
1325athn_start_noisefloor_calib(struct athn_softc *sc, int reset_history)
1326{
extern int ticks;

if (reset_history)
sc->nf_hist_nvalid = 0;

sc->nf_calib_pending = 1;
sc->nf_calib_ticks = ticks;

sc->ops.noisefloor_calib(sc);
1336}

1338void
1339athn_calib_to(void *arg)
1340{
extern int ticks;
struct athn_softc *sc = arg;
struct athn_ops *ops = &sc->ops;
struct ieee80211com *ic = &sc->sc_ic;
int s;

s = splnet()splraise(0x4);

/* Do periodic (every 4 minutes) PA calibration. */
if (AR_SREV_9285_11_OR_LATER(sc)((sc)->mac_ver > 0x0c0 || (((sc)->mac_ver == 0x0c0) &&
 (sc)->mac_rev >= 1)) &&
   !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0) &&
   (ticks - (sc->pa_calib_ticks + 240 * hz)) >= 0) {
sc->pa_calib_ticks = ticks;
if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140))
	ar9271_pa_calib(sc);
else
	ar9285_pa_calib(sc);
}

/* Do periodic (every 4 minutes) NF calibration. */
if (sc->nf_calib_pending && ops->get_noisefloor(sc)) {
if (sc->nf_hist_nvalid < ATHN_NF_CAL_HIST_MAX5)
	sc->nf_hist_nvalid++;
athn_filter_noisefloor(sc);
ops->apply_noisefloor(sc);
sc->nf_calib_pending = 0;
}
if (ticks - (sc->nf_calib_ticks + 240 * hz) >= 0)
athn_start_noisefloor_calib(sc, 0);

/* Do periodic (every 30 seconds) temperature compensation. */
if ((sc->flags & ATHN_FLAG_OLPC(1 << 2)) &&
   ticks >= sc->olpc_ticks + 30 * hz) {
sc->olpc_ticks = ticks;
ops->olpc_temp_compensation(sc);
}

1378#ifdef notyet
/* XXX ANI. */
athn_ani_monitor(sc);
1381#endif

/* Do periodic (every 30 seconds) ADC/IQ calibration. */
if (sc->cur_calib_mask != 0) {
ops->next_calib(sc);
sc->iqcal_ticks = ticks;
} else if (sc->sup_calib_mask != 0 &&
   ticks >= sc->iqcal_ticks + 30 * hz) {
memset(&sc->calib, 0, sizeof(sc->calib))__builtin_memset((&sc->calib), (0), (sizeof(sc->calib
)));
sc->cur_calib_mask = sc->sup_calib_mask;
ops->do_calib(sc);
sc->iqcal_ticks = ticks;
}

if (ic->ic_fixed_rate == -1) {
if (ic->ic_opmode == IEEE80211_M_STA)
	athn_iter_calib(sc, ic->ic_bss);
else
	ieee80211_iterate_nodes(ic, athn_iter_calib, sc);
}
timeout_add_msec(&sc->calib_to, 500);
splx(s)spllower(s);
1403}

1405int
1406athn_init_calib(struct athn_softc *sc, struct ieee80211_channel *c,
  struct ieee80211_channel *extc)
1408{
struct athn_ops *ops = &sc->ops;
int error;

if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
error = ar9003_init_calib(sc);
else if (AR_SREV_9285_10_OR_LATER(sc)((sc)->mac_ver >= 0x0c0))
error = ar9285_init_calib(sc, c, extc);
else
error = ar5416_init_calib(sc, c, extc);
if (error != 0)
return (error);

if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
/* Do PA calibration. */
if (AR_SREV_9285_11_OR_LATER(sc)((sc)->mac_ver > 0x0c0 || (((sc)->mac_ver == 0x0c0) &&
 (sc)->mac_rev >= 1))) {
	extern int ticks;
	sc->pa_calib_ticks = ticks;
	if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140))
		ar9271_pa_calib(sc);
	else
		ar9285_pa_calib(sc);
}
}

/* Do noisefloor calibration. */
ops->init_noisefloor_calib(sc);

if (AR_SREV_9160_10_OR_LATER(sc)((sc)->mac_ver >= 0x040)) {
/* Support IQ calibration. */
sc->sup_calib_mask = ATHN_CAL_IQ(1 << 0);
if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
	/* Support temperature compensation calibration. */
	sc->sup_calib_mask |= ATHN_CAL_TEMP(1 << 3);
} else if (IEEE80211_IS_CHAN_5GHZ(c)(((c)->ic_flags & 0x0100) != 0) || extc != NULL((void *)0)) {
	/*
	 * ADC gain calibration causes uplink throughput
	 * drops in HT40 mode on AR9287.
	 */
	if (!AR_SREV_9287(sc)((sc)->mac_ver == 0x180)) {
		/* Support ADC gain calibration. */
		sc->sup_calib_mask |= ATHN_CAL_ADC_GAIN(1 << 1);
	}
	/* Support ADC DC offset calibration. */
	sc->sup_calib_mask |= ATHN_CAL_ADC_DC(1 << 2);
}
}
return (0);
1456}

1458/*
* Adaptive noise immunity.
*/
1461int32_t
1462athn_ani_get_rssi(struct athn_softc *sc)
1463{
return (0);	/* XXX */
1465}

1467void
1468athn_ani_ofdm_err_trigger(struct athn_softc *sc)
1469{
struct athn_ani *ani = &sc->ani;
struct athn_ops *ops = &sc->ops;
int32_t rssi;

/* First, raise noise immunity level, up to max. */
if (ani->noise_immunity_level < 4) {
ani->noise_immunity_level++;
ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
return;
}

/* Then, raise our spur immunity level, up to max. */
if (ani->spur_immunity_level < 7) {
ani->spur_immunity_level++;
ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
return;
}

1488#ifndef IEEE80211_STA_ONLY
if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
if (ani->firstep_level < 2) {
	ani->firstep_level++;
	ops->set_firstep_level(sc, ani->firstep_level);
}
return;
}
1496#endif
rssi = athn_ani_get_rssi(sc);
if (rssi > ATHN_ANI_RSSI_THR_HIGH40) {
/*
 * Beacon RSSI is high, turn off OFDM weak signal detection
 * or raise first step level as last resort.
 */
if (ani->ofdm_weak_signal) {
	ani->ofdm_weak_signal = 0;
	ops->disable_ofdm_weak_signal(sc);
	ani->spur_immunity_level = 0;
	ops->set_spur_immunity_level(sc, 0);
} else if (ani->firstep_level < 2) {
	ani->firstep_level++;
	ops->set_firstep_level(sc, ani->firstep_level);
}
} else if (rssi > ATHN_ANI_RSSI_THR_LOW7) {
/*
 * Beacon RSSI is in mid range, we need OFDM weak signal
 * detection but we can raise first step level.
 */
if (!ani->ofdm_weak_signal) {
	ani->ofdm_weak_signal = 1;
	ops->enable_ofdm_weak_signal(sc);
}
if (ani->firstep_level < 2) {
	ani->firstep_level++;
	ops->set_firstep_level(sc, ani->firstep_level);
}
} else if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)(((sc->sc_ic.ic_bss->ni_chan)->ic_flags & 0x0080
) != 0)) {
/*
 * Beacon RSSI is low, if in b/g mode, turn off OFDM weak
 * signal detection and zero first step level to maximize
 * CCK sensitivity.
 */
if (ani->ofdm_weak_signal) {
	ani->ofdm_weak_signal = 0;
	ops->disable_ofdm_weak_signal(sc);
}
if (ani->firstep_level > 0) {
	ani->firstep_level = 0;
	ops->set_firstep_level(sc, 0);
}
}
1540}

1542void
1543athn_ani_cck_err_trigger(struct athn_softc *sc)
1544{
struct athn_ani *ani = &sc->ani;
struct athn_ops *ops = &sc->ops;
int32_t rssi;

/* Raise noise immunity level, up to max. */
if (ani->noise_immunity_level < 4) {
ani->noise_immunity_level++;
ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
return;
}

1556#ifndef IEEE80211_STA_ONLY
if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
if (ani->firstep_level < 2) {
	ani->firstep_level++;
	ops->set_firstep_level(sc, ani->firstep_level);
}
return;
}
1564#endif
rssi = athn_ani_get_rssi(sc);
if (rssi > ATHN_ANI_RSSI_THR_LOW7) {
/*
 * Beacon RSSI is in mid or high range, raise first step
 * level.
 */
if (ani->firstep_level < 2) {
	ani->firstep_level++;
	ops->set_firstep_level(sc, ani->firstep_level);
}
} else if (IEEE80211_IS_CHAN_2GHZ(sc->sc_ic.ic_bss->ni_chan)(((sc->sc_ic.ic_bss->ni_chan)->ic_flags & 0x0080
) != 0)) {
/*
 * Beacon RSSI is low, zero first step level to maximize
 * CCK sensitivity.
 */
if (ani->firstep_level > 0) {
	ani->firstep_level = 0;
	ops->set_firstep_level(sc, 0);
}
}
1585}

1587void
1588athn_ani_lower_immunity(struct athn_softc *sc)
1589{
struct athn_ani *ani = &sc->ani;
struct athn_ops *ops = &sc->ops;
int32_t rssi;

1594#ifndef IEEE80211_STA_ONLY
if (sc->sc_ic.ic_opmode == IEEE80211_M_HOSTAP) {
if (ani->firstep_level > 0) {
	ani->firstep_level--;
	ops->set_firstep_level(sc, ani->firstep_level);
}
return;
}
1602#endif
rssi = athn_ani_get_rssi(sc);
if (rssi > ATHN_ANI_RSSI_THR_HIGH40) {
/*
 * Beacon RSSI is high, leave OFDM weak signal detection
 * off or it may oscillate.
 */
} else if (rssi > ATHN_ANI_RSSI_THR_LOW7) {
/*
 * Beacon RSSI is in mid range, turn on OFDM weak signal
 * detection or lower first step level.
 */
if (!ani->ofdm_weak_signal) {
	ani->ofdm_weak_signal = 1;
	ops->enable_ofdm_weak_signal(sc);
	return;
}
if (ani->firstep_level > 0) {
	ani->firstep_level--;
	ops->set_firstep_level(sc, ani->firstep_level);
	return;
}
} else {
/* Beacon RSSI is low, lower first step level. */
if (ani->firstep_level > 0) {
	ani->firstep_level--;
	ops->set_firstep_level(sc, ani->firstep_level);
	return;
}
}
/*
* Lower spur immunity level down to zero, or if all else fails,
* lower noise immunity level down to zero.
*/
if (ani->spur_immunity_level > 0) {
ani->spur_immunity_level--;
ops->set_spur_immunity_level(sc, ani->spur_immunity_level);
} else if (ani->noise_immunity_level > 0) {
ani->noise_immunity_level--;
ops->set_noise_immunity_level(sc, ani->noise_immunity_level);
}
1643}

1645void
1646athn_ani_restart(struct athn_softc *sc)
1647{
struct athn_ani *ani = &sc->ani;

AR_WRITE(sc, AR_PHY_ERR_1, 0)(sc)->ops.write((sc), (0x812c), (0));
AR_WRITE(sc, AR_PHY_ERR_2, 0)(sc)->ops.write((sc), (0x8134), (0));
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING)(sc)->ops.write((sc), (0x8130), (0x00020000));
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING)(sc)->ops.write((sc), (0x8138), (0x02000000));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

ani->listen_time = 0;
ani->ofdm_phy_err_count = 0;
ani->cck_phy_err_count = 0;
1659}

1661void
1662athn_ani_monitor(struct athn_softc *sc)
1663{
struct athn_ani *ani = &sc->ani;
uint32_t cyccnt, txfcnt, rxfcnt, phy1, phy2;
int32_t cycdelta, txfdelta, rxfdelta;
int32_t listen_time;

txfcnt = AR_READ(sc, AR_TFCNT)(sc)->ops.read((sc), (0x80ec));	/* Tx frame count. */
rxfcnt = AR_READ(sc, AR_RFCNT)(sc)->ops.read((sc), (0x80f0));	/* Rx frame count. */
cyccnt = AR_READ(sc, AR_CCCNT)(sc)->ops.read((sc), (0x80f8));	/* Cycle count. */

if (ani->cyccnt != 0 && ani->cyccnt <= cyccnt) {
cycdelta = cyccnt - ani->cyccnt;
txfdelta = txfcnt - ani->txfcnt;
rxfdelta = rxfcnt - ani->rxfcnt;

listen_time = (cycdelta - txfdelta - rxfdelta) /
    (athn_clock_rate(sc) * 1000);
} else
listen_time = 0;

ani->cyccnt = cyccnt;
ani->txfcnt = txfcnt;
ani->rxfcnt = rxfcnt;

if (listen_time < 0) {
athn_ani_restart(sc);
return;
}
ani->listen_time += listen_time;

phy1 = AR_READ(sc, AR_PHY_ERR_1)(sc)->ops.read((sc), (0x812c));
phy2 = AR_READ(sc, AR_PHY_ERR_2)(sc)->ops.read((sc), (0x8134));

if (phy1 < ani->ofdm_phy_err_base) {
AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base)(sc)->ops.write((sc), (0x812c), (ani->ofdm_phy_err_base
));
AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING)(sc)->ops.write((sc), (0x8130), (0x00020000));
}
if (phy2 < ani->cck_phy_err_base) {
AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base)(sc)->ops.write((sc), (0x8134), (ani->cck_phy_err_base)
);
AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING)(sc)->ops.write((sc), (0x8138), (0x02000000));
}
if (phy1 < ani->ofdm_phy_err_base || phy2 < ani->cck_phy_err_base) {
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
return;
}
ani->ofdm_phy_err_count = phy1 - ani->ofdm_phy_err_base;
ani->cck_phy_err_count = phy2 - ani->cck_phy_err_base;

if (ani->listen_time > 5 * ATHN_ANI_PERIOD100) {
/* Check to see if we need to lower immunity. */
if (ani->ofdm_phy_err_count <=
    ani->listen_time * ani->ofdm_trig_low / 1000 &&
    ani->cck_phy_err_count <=
    ani->listen_time * ani->cck_trig_low / 1000)
	athn_ani_lower_immunity(sc);
athn_ani_restart(sc);

} else if (ani->listen_time > ATHN_ANI_PERIOD100) {
/* Check to see if we need to raise immunity. */
if (ani->ofdm_phy_err_count >
    ani->listen_time * ani->ofdm_trig_high / 1000) {
	athn_ani_ofdm_err_trigger(sc);
	athn_ani_restart(sc);
} else if (ani->cck_phy_err_count >
    ani->listen_time * ani->cck_trig_high / 1000) {
	athn_ani_cck_err_trigger(sc);
	athn_ani_restart(sc);
}
}
1732}

1734uint8_t
1735athn_chan2fbin(struct ieee80211_channel *c)
1736{
if (IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0))
return (c->ic_freq - 2300);
else
return ((c->ic_freq - 4800) / 5);
1741}

1743int
1744athn_interpolate(int x, int x1, int y1, int x2, int y2)
1745{
if (x1 == x2)	/* Prevents division by zero. */
return (y1);
/* Linear interpolation. */
return (y1 + ((x - x1) * (y2 - y1)) / (x2 - x1));
1750}

1752void
1753athn_get_pier_ival(uint8_t fbin, const uint8_t *pierfreq, int npiers,
  int *lo, int *hi)
1755{
int i;

for (i = 0; i < npiers; i++)
if (pierfreq[i] == AR_BCHAN_UNUSED0xff ||
    pierfreq[i] > fbin)
	break;
*hi = i;
*lo = *hi - 1;
if (*lo == -1)
*lo = *hi;
else if (*hi == npiers || pierfreq[*hi] == AR_BCHAN_UNUSED0xff)
*hi = *lo;
1768}

1770void
1771athn_init_dma(struct athn_softc *sc)
1772{
uint32_t reg;

if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
/* Set AHB not to do cacheline prefetches. */
AR_SETBITS(sc, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN)(sc)->ops.write((sc), (0x4024), ((sc)->ops.read((sc), (
0x4024)) | (0x00000004)));
}
reg = AR_READ(sc, AR_TXCFG)(sc)->ops.read((sc), (0x0030));
/* Let MAC DMA reads be in 128-byte chunks. */
reg = RW(reg, AR_TXCFG_DMASZ, AR_DMASZ_128B)(((reg) & ~0x00000007) | (((uint32_t)(5) << 0) &
 0x00000007));

/* Set initial Tx trigger level. */
if (AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0) || AR_SREV_9271(sc)((sc)->mac_ver == 0x140))
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_256B)(((reg) & ~0x000003f0) | (((uint32_t)((256 / 64)) <<
 4) & 0x000003f0));
else if (!AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
reg = RW(reg, AR_TXCFG_FTRIG, AR_TXCFG_FTRIG_512B)(((reg) & ~0x000003f0) | (((uint32_t)((512 / 64)) <<
 4) & 0x000003f0));
AR_WRITE(sc, AR_TXCFG, reg)(sc)->ops.write((sc), (0x0030), (reg));

/* Let MAC DMA writes be in 128-byte chunks. */
reg = AR_READ(sc, AR_RXCFG)(sc)->ops.read((sc), (0x0034));
reg = RW(reg, AR_RXCFG_DMASZ, AR_DMASZ_128B)(((reg) & ~0x00000007) | (((uint32_t)(5) << 0) &
 0x00000007));
AR_WRITE(sc, AR_RXCFG, reg)(sc)->ops.write((sc), (0x0034), (reg));

/* Setup Rx FIFO threshold to hold off Tx activities. */
AR_WRITE(sc, AR_RXFIFO_CFG, 512)(sc)->ops.write((sc), (0x8114), (512));

/* Reduce the number of entries in PCU TXBUF to avoid wrap around. */
if (AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0)) {
AR_WRITE(sc, AR_PCU_TXBUF_CTRL,(sc)->ops.write((sc), (0x8340), ((1792 / 2)))
    AR9285_PCU_TXBUF_CTRL_USABLE_SIZE)(sc)->ops.write((sc), (0x8340), ((1792 / 2)));
} else if (!AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) {
AR_WRITE(sc, AR_PCU_TXBUF_CTRL,(sc)->ops.write((sc), (0x8340), (1792))
    AR_PCU_TXBUF_CTRL_USABLE_SIZE)(sc)->ops.write((sc), (0x8340), (1792));
}
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

/* Reset Tx status ring. */
if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
ar9003_reset_txsring(sc);
1811}

1813void
1814athn_inc_tx_trigger_level(struct athn_softc *sc)
1815{
uint32_t reg, ftrig;

reg = AR_READ(sc, AR_TXCFG)(sc)->ops.read((sc), (0x0030));
ftrig = MS(reg, AR_TXCFG_FTRIG)(((uint32_t)(reg) & 0x000003f0) >> 4);
/*
* NB: The AR9285 and all single-stream parts have an issue that
* limits the size of the PCU Tx FIFO to 2KB instead of 4KB.
*/
if (ftrig == ((AR_SREV_9285(sc)((sc)->mac_ver == 0x0c0) || AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) ? 0x1f : 0x3f))
return;		/* Already at max. */
reg = RW(reg, AR_TXCFG_FTRIG, ftrig + 1)(((reg) & ~0x000003f0) | (((uint32_t)(ftrig + 1) <<
 4) & 0x000003f0));
AR_WRITE(sc, AR_TXCFG, reg)(sc)->ops.write((sc), (0x0030), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
1829}

1831int
1832athn_stop_rx_dma(struct athn_softc *sc)
1833{
int ntries;

AR_WRITE(sc, AR_CR, AR_CR_RXD)(sc)->ops.write((sc), (0x0008), (0x00000020));
/* Wait for Rx enable bit to go low. */
for (ntries = 0; ntries < 100; ntries++) {
if (!(AR_READ(sc, AR_CR)(sc)->ops.read((sc), (0x0008)) & AR_CR_RXE(((sc)->mac_ver > 0x1c0 || (((sc)->mac_ver == 0x1c0)
 && (sc)->mac_rev >= 2)) ? 0x000c : 0x0004)))
	return (0);
DELAY(100)(*delay_func)(100);
}
DPRINTF(("Rx DMA failed to stop\n"));
return (ETIMEDOUT60);
1845}

1847int
1848athn_rx_abort(struct athn_softc *sc)
1849{
int ntries;

AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) | (0x00000020 | 0x02000000)));
for (ntries = 0; ntries < 1000; ntries++) {
if (MS(AR_READ(sc, AR_OBS_BUS_1), AR_OBS_BUS_1_RX_STATE)(((uint32_t)((sc)->ops.read((sc), (0x806c))) & 0x01f00000
) >> 20) == 0)
	return (0);
DELAY(10)(*delay_func)(10);
}
DPRINTF(("Rx failed to go idle in 10ms\n"));
AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) & ~(0x00000020 | 0x02000000)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
return (ETIMEDOUT60);
1862}

1864void
1865athn_tx_reclaim(struct athn_softc *sc, int qid)
1866{
struct athn_txq *txq = &sc->txq[qid];
struct athn_tx_buf *bf;

/* Reclaim all buffers queued in the specified Tx queue. */
/* NB: Tx DMA must be stopped. */
while ((bf = SIMPLEQ_FIRST(&txq->head)((&txq->head)->sqh_first)) != NULL((void *)0)) {
SIMPLEQ_REMOVE_HEAD(&txq->head, bf_list)do { if (((&txq->head)->sqh_first = (&txq->head
)->sqh_first->bf_list.sqe_next) == ((void *)0)) (&txq
->head)->sqh_last = &(&txq->head)->sqh_first
; } while (0);

bus_dmamap_sync(sc->sc_dmat, bf->bf_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (bf->
bf_map), (0), (bf->bf_map->dm_mapsize), (0x08))
    bf->bf_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (bf->
bf_map), (0), (bf->bf_map->dm_mapsize), (0x08));
bus_dmamap_unload(sc->sc_dmat, bf->bf_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (bf->
bf_map));
m_freem(bf->bf_m);
bf->bf_m = NULL((void *)0);
bf->bf_ni = NULL((void *)0);	/* Nodes already freed! */

/* Link Tx buffer back to global free list. */
SIMPLEQ_INSERT_TAIL(&sc->txbufs, bf, bf_list)do { (bf)->bf_list.sqe_next = ((void *)0); *(&sc->txbufs
)->sqh_last = (bf); (&sc->txbufs)->sqh_last = &
(bf)->bf_list.sqe_next; } while (0);
}
1885}

1887int
1888athn_tx_pending(struct athn_softc *sc, int qid)
1889{
return (MS(AR_READ(sc, AR_QSTS(qid)), AR_Q_STS_PEND_FR_CNT)(((uint32_t)((sc)->ops.read((sc), ((0x0a00 + (qid) * 4))))
 & 0x00000003) >> 0) != 0 ||
   (AR_READ(sc, AR_Q_TXE)(sc)->ops.read((sc), (0x0840)) & (1 << qid)) != 0);
1892}

1894void
1895athn_stop_tx_dma(struct athn_softc *sc, int qid)
1896{
uint32_t tsflo;
int ntries, i;

AR_WRITE(sc, AR_Q_TXD, 1 << qid)(sc)->ops.write((sc), (0x0880), (1 << qid));
for (ntries = 0; ntries < 40; ntries++) {
if (!athn_tx_pending(sc, qid))
	break;
DELAY(100)(*delay_func)(100);
}
if (ntries == 40) {
for (i = 0; i < 2; i++) {
	tsflo = AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c)) / 1024;
	AR_WRITE(sc, AR_QUIET2,(sc)->ops.write((sc), (0x8100), ((((uint32_t)(10) <<
 16) & 0xffff0000)))
	    SM(AR_QUIET2_QUIET_DUR, 10))(sc)->ops.write((sc), (0x8100), ((((uint32_t)(10) <<
 16) & 0xffff0000)));
	AR_WRITE(sc, AR_QUIET_PERIOD, 100)(sc)->ops.write((sc), ((0x8200 + (14) * 4)), (100));
	AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo)(sc)->ops.write((sc), ((0x8200 + (6) * 4)), (tsflo));
	AR_SETBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN)(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), (
0x8240)) | (0x00000040)));
	if (AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c)) / 1024 == tsflo)
		break;
}
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) | (0x00400000)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
DELAY(200)(*delay_func)(200);
AR_CLRBITS(sc, AR_TIMER_MODE, AR_QUIET_TIMER_EN)(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), (
0x8240)) & ~(0x00000040)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

for (ntries = 0; ntries < 40; ntries++) {
	if (!athn_tx_pending(sc, qid))
		break;
	DELAY(100)(*delay_func)(100);
}

AR_CLRBITS(sc, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) & ~(0x00400000)));
}
AR_WRITE(sc, AR_Q_TXD, 0)(sc)->ops.write((sc), (0x0880), (0));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
1933}

1935int
1936athn_txtime(struct athn_softc *sc, int len, int ridx, u_int flags)
1937{
struct ieee80211com *ic = &sc->sc_ic;
1939#define divround(a, b)	(((a) + (b) - 1) / (b))
int txtime;

if (athn_rates[ridx].hwrate & 0x80) { /* MCS */
	/* Assumes a 20MHz channel, HT-mixed frame format, no STBC. */
txtime = 8 + 8 + 4 + 4 + 4 * 4 + 8 /* HT PLCP */
    + 4 * ((8 * len + 16 + 6) / (athn_rates[ridx].rate * 2));
if (IEEE80211_IS_CHAN_2GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0080) != 0
))
	txtime += 6; /* aSignalExtension */
} else if (athn_rates[ridx].phy == IEEE80211_T_OFDM) {
txtime = divround(8 + 4 * len + 3, athn_rates[ridx].rate);
/* SIFS is 10us for 11g but Signal Extension adds 6us. */
txtime = 16 + 4 + 4 * txtime + 16;
} else {
txtime = divround(16 * len, athn_rates[ridx].rate);
if (ridx != ATHN_RIDX_CCK10 && (flags & IEEE80211_F_SHPREAMBLE0x00040000))
	txtime +=  72 + 24;
else
	txtime += 144 + 48;
txtime += 10;	/* 10us SIFS. */
}
return (txtime);
1961#undef divround
1962}

1964void
1965athn_init_tx_queues(struct athn_softc *sc)
1966{
int qid;

for (qid = 0; qid < ATHN_QID_COUNT8; qid++) {
SIMPLEQ_INIT(&sc->txq[qid].head)do { (&sc->txq[qid].head)->sqh_first = ((void *)0);
 (&sc->txq[qid].head)->sqh_last = &(&sc->
txq[qid].head)->sqh_first; } while (0);
sc->txq[qid].lastds = NULL((void *)0);
sc->txq[qid].wait = NULL((void *)0);
sc->txq[qid].queued = 0;

AR_WRITE(sc, AR_DRETRY_LIMIT(qid),(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t
)(32) << 8) & 0x00003f00) | (((uint32_t)(32) <<
 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f
)))
    SM(AR_D_RETRY_LIMIT_STA_SH, 32) |(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t
)(32) << 8) & 0x00003f00) | (((uint32_t)(32) <<
 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f
)))
    SM(AR_D_RETRY_LIMIT_STA_LG, 32) |(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t
)(32) << 8) & 0x00003f00) | (((uint32_t)(32) <<
 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f
)))
    SM(AR_D_RETRY_LIMIT_FR_SH, 10))(sc)->ops.write((sc), ((0x1080 + (qid) * 4)), ((((uint32_t
)(32) << 8) & 0x00003f00) | (((uint32_t)(32) <<
 14) & 0x000fc000) | (((uint32_t)(10) << 0) & 0x0000000f
)));
AR_WRITE(sc, AR_QMISC(qid),(sc)->ops.write((sc), ((0x09c0 + (qid) * 4)), (0x00000800)
)
    AR_Q_MISC_DCU_EARLY_TERM_REQ)(sc)->ops.write((sc), ((0x09c0 + (qid) * 4)), (0x00000800)
);
AR_WRITE(sc, AR_DMISC(qid),(sc)->ops.write((sc), ((0x1100 + (qid) * 4)), ((((uint32_t
)(2) << 0) & 0x0000003f) | 0x00001000 | 0x00000100)
)
    SM(AR_D_MISC_BKOFF_THRESH, 2) |(sc)->ops.write((sc), ((0x1100 + (qid) * 4)), ((((uint32_t
)(2) << 0) & 0x0000003f) | 0x00001000 | 0x00000100)
)
    AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN)(sc)->ops.write((sc), ((0x1100 + (qid) * 4)), ((((uint32_t
)(2) << 0) & 0x0000003f) | 0x00001000 | 0x00000100)
);
}

/* Init beacon queue. */
AR_SETBITS(sc, AR_QMISC(ATHN_QID_BEACON),(sc)->ops.write((sc), ((0x09c0 + (7) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (7) * 4))) | (2 | 0x00000080 | 0x00000020
)))
   AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_BEACON_USE |(sc)->ops.write((sc), ((0x09c0 + (7) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (7) * 4))) | (2 | 0x00000080 | 0x00000020
)))
   AR_Q_MISC_CBR_INCR_DIS1)(sc)->ops.write((sc), ((0x09c0 + (7) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (7) * 4))) | (2 | 0x00000080 | 0x00000020
)));
AR_SETBITS(sc, AR_DMISC(ATHN_QID_BEACON),(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000) | 0x00010000 | 0x00200000)))
   SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000) | 0x00010000 | 0x00200000)))
      AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL) |(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000) | 0x00010000 | 0x00200000)))
   AR_D_MISC_BEACON_USE |(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000) | 0x00010000 | 0x00200000)))
   AR_D_MISC_POST_FR_BKOFF_DIS)(sc)->ops.write((sc), ((0x1100 + (7) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (7) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000) | 0x00010000 | 0x00200000)));
AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)(
0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10
) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000
)))
   SM(AR_D_LCL_IFS_CWMIN, 0) |(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)(
0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10
) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000
)))
   SM(AR_D_LCL_IFS_CWMAX, 0) |(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)(
0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10
) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000
)))
   SM(AR_D_LCL_IFS_AIFS,  1))(sc)->ops.write((sc), ((0x1040 + (7) * 4)), ((((uint32_t)(
0) << 0) & 0x000003ff) | (((uint32_t)(0) << 10
) & 0x000ffc00) | (((uint32_t)(1) << 20) & 0x0ff00000
)));

/* Init CAB (Content After Beacon) queue. */
AR_SETBITS(sc, AR_QMISC(ATHN_QID_CAB),(sc)->ops.write((sc), ((0x09c0 + (6) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (6) * 4))) | (2 | 0x00000020 | 0x00000040
)))
   AR_Q_MISC_FSP_DBA_GATED | AR_Q_MISC_CBR_INCR_DIS1 |(sc)->ops.write((sc), ((0x09c0 + (6) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (6) * 4))) | (2 | 0x00000020 | 0x00000040
)))
   AR_Q_MISC_CBR_INCR_DIS0)(sc)->ops.write((sc), ((0x09c0 + (6) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (6) * 4))) | (2 | 0x00000020 | 0x00000040
)));
AR_SETBITS(sc, AR_DMISC(ATHN_QID_CAB),(sc)->ops.write((sc), ((0x1100 + (6) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (6) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000))))
   SM(AR_D_MISC_ARB_LOCKOUT_CNTRL,(sc)->ops.write((sc), ((0x1100 + (6) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (6) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000))))
      AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL))(sc)->ops.write((sc), ((0x1100 + (6) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (6) * 4))) | ((((uint32_t)(2) << 17
) & 0x00060000))));

/* Init PS-Poll queue. */
AR_SETBITS(sc, AR_QMISC(ATHN_QID_PSPOLL),(sc)->ops.write((sc), ((0x09c0 + (1) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (1) * 4))) | (0x00000020)))
   AR_Q_MISC_CBR_INCR_DIS1)(sc)->ops.write((sc), ((0x09c0 + (1) * 4)), ((sc)->ops.
read((sc), ((0x09c0 + (1) * 4))) | (0x00000020)));

/* Init UAPSD queue. */
AR_SETBITS(sc, AR_DMISC(ATHN_QID_UAPSD),(sc)->ops.write((sc), ((0x1100 + (5) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (5) * 4))) | (0x00200000)))
   AR_D_MISC_POST_FR_BKOFF_DIS)(sc)->ops.write((sc), ((0x1100 + (5) * 4)), ((sc)->ops.
read((sc), ((0x1100 + (5) * 4))) | (0x00200000)));

if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
/* Enable MAC descriptor CRC check. */
AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN)(sc)->ops.write((sc), (0x0a44), (0x00000001));
}
/* Enable DESC interrupts for all Tx queues. */
AR_WRITE(sc, AR_IMR_S0, 0x00ff0000)(sc)->ops.write((sc), (0x00a4), (0x00ff0000));
/* Enable EOL interrupts for all Tx queues except UAPSD. */
AR_WRITE(sc, AR_IMR_S1, 0x00df0000)(sc)->ops.write((sc), (0x00a8), (0x00df0000));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2025}

2027void
2028athn_set_sta_timers(struct athn_softc *sc)
2029{
struct ieee80211com *ic = &sc->sc_ic;
uint32_t tsfhi, tsflo, tsftu, reg;
uint32_t intval, next_tbtt, next_dtim;
int dtim_period, dtim_count, rem_dtim_count;

tsfhi = AR_READ(sc, AR_TSF_U32)(sc)->ops.read((sc), (0x8050));
tsflo = AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c));
tsftu = AR_TSF_TO_TU(tsfhi, tsflo)((tsfhi) << 22 | (tsflo) >> 10) + AR_FUDGE2;

/* Beacon interval in TU. */
intval = ic->ic_bss->ni_intval;

next_tbtt = roundup(tsftu, intval)((((tsftu)+((intval)-1))/(intval))*(intval));
2043#ifdef notyet
dtim_period = ic->ic_dtim_period;
if (dtim_period <= 0)
2046#endif
dtim_period = 1;	/* Assume all TIMs are DTIMs. */

2049#ifdef notyet
dtim_count = ic->ic_dtim_count;
if (dtim_count >= dtim_period)	/* Should not happen. */
2052#endif
dtim_count = 0;	/* Assume last TIM was a DTIM. */

/* Compute number of remaining TIMs until next DTIM. */
rem_dtim_count = 0;	/* XXX */
next_dtim = next_tbtt + rem_dtim_count * intval;

AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (0) * 4)), (next_tbtt * 1024
));
AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (8) * 4)), (intval * 1024
));
AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (9) * 4)), (intval * 1024
));

/*
* Set the number of consecutive beacons to miss before raising
* a BMISS interrupt to 10.
*/
reg = AR_READ(sc, AR_RSSI_THR)(sc)->ops.read((sc), (0x8018));
reg = RW(reg, AR_RSSI_THR_BM_THR, 10)(((reg) & ~0x0000ff00) | (((uint32_t)(10) << 8) &
 0x0000ff00));
AR_WRITE(sc, AR_RSSI_THR, reg)(sc)->ops.write((sc), (0x8018), (reg));

AR_WRITE(sc, AR_NEXT_DTIM,(sc)->ops.write((sc), ((0x8200 + (5) * 4)), ((next_dtim - 3
) * 1024))
   (next_dtim - AR_SLEEP_SLOP) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (5) * 4)), ((next_dtim - 3
) * 1024));
AR_WRITE(sc, AR_NEXT_TIM,(sc)->ops.write((sc), ((0x8200 + (4) * 4)), ((next_tbtt - 3
) * 1024))
   (next_tbtt - AR_SLEEP_SLOP) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (4) * 4)), ((next_tbtt - 3
) * 1024));

/* CAB timeout is in 1/8 TU. */
AR_WRITE(sc, AR_SLEEP1,(sc)->ops.write((sc), (0x80d4), ((((uint32_t)(10 * 8) <<
 21) & 0xffe00000) | 0x00080000))
   SM(AR_SLEEP1_CAB_TIMEOUT, AR_CAB_TIMEOUT_VAL * 8) |(sc)->ops.write((sc), (0x80d4), ((((uint32_t)(10 * 8) <<
 21) & 0xffe00000) | 0x00080000))
   AR_SLEEP1_ASSUME_DTIM)(sc)->ops.write((sc), (0x80d4), ((((uint32_t)(10 * 8) <<
 21) & 0xffe00000) | 0x00080000));
AR_WRITE(sc, AR_SLEEP2,(sc)->ops.write((sc), (0x80d8), ((((uint32_t)(1) << 21
) & 0xffe00000)))
   SM(AR_SLEEP2_BEACON_TIMEOUT, AR_MIN_BEACON_TIMEOUT_VAL))(sc)->ops.write((sc), (0x80d8), ((((uint32_t)(1) << 21
) & 0xffe00000)));

AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (12) * 4)), (intval * 1024
));
AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (13) * 4)), (dtim_period *
 intval * 1024));

AR_SETBITS(sc, AR_TIMER_MODE,(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), (
0x8240)) | (0x00000001 | 0x00000010 | 0x00000020)))
   AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | AR_DTIM_TIMER_EN)(sc)->ops.write((sc), (0x8240), ((sc)->ops.read((sc), (
0x8240)) | (0x00000001 | 0x00000010 | 0x00000020)));

/* Set TSF out-of-range threshold (fixed at 16k us). */
AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240)(sc)->ops.write((sc), (0x813c), (0x4240));

AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2093}

2095#ifndef IEEE80211_STA_ONLY
2096void
2097athn_set_hostap_timers(struct athn_softc *sc)
2098{
struct ieee80211com *ic = &sc->sc_ic;
uint32_t intval, next_tbtt;

/* Beacon interval in TU. */
intval = ic->ic_bss->ni_intval;
next_tbtt = intval;

AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (0) * 4)), (next_tbtt * 1024
));
AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,(sc)->ops.write((sc), ((0x8200 + (1) * 4)), ((next_tbtt - 2
) * 1024))
   (next_tbtt - AR_BEACON_DMA_DELAY) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (1) * 4)), ((next_tbtt - 2
) * 1024));
AR_WRITE(sc, AR_NEXT_CFP,(sc)->ops.write((sc), ((0x8200 + (2) * 4)), ((next_tbtt - 10
) * 1024))
   (next_tbtt - AR_SWBA_DELAY) * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (2) * 4)), ((next_tbtt - 10
) * 1024));

AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (8) * 4)), (intval * 1024
));
AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (9) * 4)), (intval * 1024
));
AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (10) * 4)), (intval * 1024
));
AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU)(sc)->ops.write((sc), ((0x8200 + (15) * 4)), (intval * 1024
));

AR_WRITE(sc, AR_TIMER_MODE,(sc)->ops.write((sc), (0x8240), (0x00000001 | 0x00000002 |
 0x00000004))
   AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN)(sc)->ops.write((sc), (0x8240), (0x00000001 | 0x00000002 |
 0x00000004));

AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2121}
2122#endif

2124void
2125athn_set_opmode(struct athn_softc *sc)
2126{
uint32_t reg;

switch (sc->sc_ic.ic_opmode) {
2130#ifndef IEEE80211_STA_ONLY
case IEEE80211_M_HOSTAP:
reg = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004));
reg &= ~AR_STA_ID1_ADHOC0x00020000;
reg |= AR_STA_ID1_STA_AP0x00010000 | AR_STA_ID1_KSRCH_MODE0x10000000;
AR_WRITE(sc, AR_STA_ID1, reg)(sc)->ops.write((sc), (0x8004), (reg));

AR_CLRBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION)(sc)->ops.write((sc), (0x0014), ((sc)->ops.read((sc), (
0x0014)) & ~(0x00000020)));
break;
case IEEE80211_M_IBSS:
case IEEE80211_M_AHDEMO:
reg = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004));
reg &= ~AR_STA_ID1_STA_AP0x00010000;
reg |= AR_STA_ID1_ADHOC0x00020000 | AR_STA_ID1_KSRCH_MODE0x10000000;
AR_WRITE(sc, AR_STA_ID1, reg)(sc)->ops.write((sc), (0x8004), (reg));

AR_SETBITS(sc, AR_CFG, AR_CFG_AP_ADHOC_INDICATION)(sc)->ops.write((sc), (0x0014), ((sc)->ops.read((sc), (
0x0014)) | (0x00000020)));
break;
2148#endif
default:
reg = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004));
reg &= ~(AR_STA_ID1_ADHOC0x00020000 | AR_STA_ID1_STA_AP0x00010000);
reg |= AR_STA_ID1_KSRCH_MODE0x10000000;
AR_WRITE(sc, AR_STA_ID1, reg)(sc)->ops.write((sc), (0x8004), (reg));
break;
}
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2157}

2159void
2160athn_set_bss(struct athn_softc *sc, struct ieee80211_node *ni)
2161{
const uint8_t *bssid = ni->ni_bssid;

AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]))(sc)->ops.write((sc), (0x8008), (((&bssid[0])[0] | (&
bssid[0])[1] << 8 | (&bssid[0])[2] << 16 | (&
bssid[0])[3] << 24)));
AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |(sc)->ops.write((sc), (0x800c), (((&bssid[4])[0] | (&
bssid[4])[1] << 8) | (((uint32_t)(((ni->ni_associd) &
~ 0xc000)) << 16) & 0x07ff0000)))
   SM(AR_BSS_ID1_AID, IEEE80211_AID(ni->ni_associd)))(sc)->ops.write((sc), (0x800c), (((&bssid[4])[0] | (&
bssid[4])[1] << 8) | (((uint32_t)(((ni->ni_associd) &
~ 0xc000)) << 16) & 0x07ff0000)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2168}

2170void
2171athn_enable_interrupts(struct athn_softc *sc)
2172{
uint32_t mask2;

athn_disable_interrupts(sc);	/* XXX */

AR_WRITE(sc, AR_IMR, sc->imask)(sc)->ops.write((sc), (0x00a0), (sc->imask));

mask2 = AR_READ(sc, AR_IMR_S2)(sc)->ops.read((sc), (0x00ac));
mask2 &= ~(AR_IMR_S2_TIM0x01000000 | AR_IMR_S2_DTIM0x20000000 | AR_IMR_S2_DTIMSYNC0x04000000 |
   AR_IMR_S2_CABEND0x02000000 | AR_IMR_S2_CABTO0x10000000 | AR_IMR_S2_TSFOOR0x40000000);
mask2 |= AR_IMR_S2_GTT0x00800000 | AR_IMR_S2_CST0x00400000;
AR_WRITE(sc, AR_IMR_S2, mask2)(sc)->ops.write((sc), (0x00ac), (mask2));

AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER)(sc)->ops.write((sc), (0x00b8), ((sc)->ops.read((sc), (
0x00b8)) & ~(0x00000010)));

AR_WRITE(sc, AR_IER, AR_IER_ENABLE)(sc)->ops.write((sc), (0x0024), (0x00000001));

AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ)(sc)->ops.write((sc), (0x403c), (0x00000002));
AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ)(sc)->ops.write((sc), (0x4030), (0x00000002));

AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync)(sc)->ops.write((sc), (0x402c), (sc->isync));
AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->isync)(sc)->ops.write((sc), (0x4034), (sc->isync));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2195}

2197void
2198athn_disable_interrupts(struct athn_softc *sc)
2199{
AR_WRITE(sc, AR_IER, 0)(sc)->ops.write((sc), (0x0024), (0));
(void)AR_READ(sc, AR_IER)(sc)->ops.read((sc), (0x0024));

AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0)(sc)->ops.write((sc), (0x403c), (0));
(void)AR_READ(sc, AR_INTR_ASYNC_ENABLE)(sc)->ops.read((sc), (0x403c));

AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0)(sc)->ops.write((sc), (0x402c), (0));
(void)AR_READ(sc, AR_INTR_SYNC_ENABLE)(sc)->ops.read((sc), (0x402c));

AR_WRITE(sc, AR_IMR, 0)(sc)->ops.write((sc), (0x00a0), (0));

AR_CLRBITS(sc, AR_IMR_S2, AR_IMR_S2_TIM | AR_IMR_S2_DTIM |(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), (
0x00ac)) & ~(0x01000000 | 0x20000000 | 0x04000000 | 0x02000000
 | 0x10000000 | 0x40000000 | 0x00800000 | 0x00400000)))
   AR_IMR_S2_DTIMSYNC | AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), (
0x00ac)) & ~(0x01000000 | 0x20000000 | 0x04000000 | 0x02000000
 | 0x10000000 | 0x40000000 | 0x00800000 | 0x00400000)))
   AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST)(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), (
0x00ac)) & ~(0x01000000 | 0x20000000 | 0x04000000 | 0x02000000
 | 0x10000000 | 0x40000000 | 0x00800000 | 0x00400000)));

AR_CLRBITS(sc, AR_IMR_S5, AR_IMR_S5_TIM_TIMER)(sc)->ops.write((sc), (0x00b8), ((sc)->ops.read((sc), (
0x00b8)) & ~(0x00000010)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2217}

2219void
2220athn_init_qos(struct athn_softc *sc)
2221{
/* Initialize QoS settings. */
AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa)(sc)->ops.write((sc), (0x8118), (0x100aa));
AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210)(sc)->ops.write((sc), (0x811c), (0x3210));
AR_WRITE(sc, AR_QOS_NO_ACK,(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0
) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f
) | (((uint32_t)(0) << 7) & 0x00000180)))
   SM(AR_QOS_NO_ACK_TWO_BIT, 2) |(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0
) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f
) | (((uint32_t)(0) << 7) & 0x00000180)))
   SM(AR_QOS_NO_ACK_BIT_OFF, 5) |(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0
) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f
) | (((uint32_t)(0) << 7) & 0x00000180)))
   SM(AR_QOS_NO_ACK_BYTE_OFF, 0))(sc)->ops.write((sc), (0x8108), ((((uint32_t)(2) << 0
) & 0x0000000f) | (((uint32_t)(5) << 4) & 0x0000007f
) | (((uint32_t)(0) << 7) & 0x00000180)));
AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL)(sc)->ops.write((sc), (0x81ec), (0x000000ff));
/* Initialize TXOP for all TIDs. */
AR_WRITE(sc, AR_TXOP_0_3,   0xffffffff)(sc)->ops.write((sc), (0x81f0), (0xffffffff));
AR_WRITE(sc, AR_TXOP_4_7,   0xffffffff)(sc)->ops.write((sc), (0x81f4), (0xffffffff));
AR_WRITE(sc, AR_TXOP_8_11,  0xffffffff)(sc)->ops.write((sc), (0x81f8), (0xffffffff));
AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff)(sc)->ops.write((sc), (0x81fc), (0xffffffff));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2236}

2238int
2239athn_hw_reset(struct athn_softc *sc, struct ieee80211_channel *c,
  struct ieee80211_channel *extc, int init)
2241{
struct ieee80211com *ic = &sc->sc_ic;
struct athn_ops *ops = &sc->ops;
uint32_t reg, def_ant, sta_id1, cfg_led, tsflo, tsfhi;
int i, error;

/* XXX not if already awake */
if ((error = athn_set_power_awake(sc)) != 0) {
printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname);
return (error);
}

/* Preserve the antenna on a channel switch. */
if ((def_ant = AR_READ(sc, AR_DEF_ANTENNA)(sc)->ops.read((sc), (0x8058))) == 0)
def_ant = 1;
/* Preserve other registers. */
sta_id1 = AR_READ(sc, AR_STA_ID1)(sc)->ops.read((sc), (0x8004)) & AR_STA_ID1_BASE_RATE_11B0x02000000;
cfg_led = AR_READ(sc, AR_CFG_LED)(sc)->ops.read((sc), (0x1f04)) & (AR_CFG_LED_ASSOC_CTL_M0x00000c00 |
   AR_CFG_LED_MODE_SEL_M0x00000380 | AR_CFG_LED_BLINK_THRESH_SEL_M0x00000070 |
   AR_CFG_LED_BLINK_SLOW0x00000008);

/* Mark PHY as inactive. */
ops->disable_phy(sc);

if (init && AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) {
AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,(sc)->ops.write((sc), (0x050044), (0x00000020))
    AR9271_RADIO_RF_RST)(sc)->ops.write((sc), (0x050044), (0x00000020));
DELAY(50)(*delay_func)(50);
}
if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080) && (sc->flags & ATHN_FLAG_OLPC(1 << 2))) {
/* Save TSF before it gets cleared. */
tsfhi = AR_READ(sc, AR_TSF_U32)(sc)->ops.read((sc), (0x8050));
tsflo = AR_READ(sc, AR_TSF_L32)(sc)->ops.read((sc), (0x804c));

/* NB: RTC reset clears TSF. */
error = athn_reset_power_on(sc);
} else
error = athn_reset(sc, 0);
if (error != 0) {
printf("%s: could not reset chip (error=%d)\n",
    sc->sc_dev.dv_xname, error);
return (error);
}

/* XXX not if already awake */
if ((error = athn_set_power_awake(sc)) != 0) {
printf("%s: could not wakeup chip\n", sc->sc_dev.dv_xname);
return (error);
}

athn_init_pll(sc, c);
ops->set_rf_mode(sc, c);

if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5)) {
/* Check that the radio is not disabled by hardware switch. */
reg = ops->gpio_read(sc, sc->rfsilent_pin);
if (sc->flags & ATHN_FLAG_RFSILENT_REVERSED(1 << 6))
	reg = !reg;
if (!reg) {
	printf("%s: radio is disabled by hardware switch\n",
	    sc->sc_dev.dv_xname);
	return (EPERM1);
}
}
if (init && AR_SREV_9271(sc)((sc)->mac_ver == 0x140)) {
AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,(sc)->ops.write((sc), (0x050044), (0x00004000))
    AR9271_GATE_MAC_CTL)(sc)->ops.write((sc), (0x050044), (0x00004000));
DELAY(50)(*delay_func)(50);
}
if (AR_SREV_9280(sc)((sc)->mac_ver == 0x080) && (sc->flags & ATHN_FLAG_OLPC(1 << 2))) {
/* Restore TSF if it got cleared. */
AR_WRITE(sc, AR_TSF_L32, tsflo)(sc)->ops.write((sc), (0x804c), (tsflo));
AR_WRITE(sc, AR_TSF_U32, tsfhi)(sc)->ops.write((sc), (0x8050), (tsfhi));
}

if (AR_SREV_9280_10_OR_LATER(sc)((sc)->mac_ver >= 0x080))
AR_SETBITS(sc, sc->gpio_input_en_off, AR_GPIO_JTAG_DISABLE)(sc)->ops.write((sc), (sc->gpio_input_en_off), ((sc)->
ops.read((sc), (sc->gpio_input_en_off)) | (0x00020000)));

if (AR_SREV_9287_13_OR_LATER(sc)((sc)->mac_ver > 0x180 || (((sc)->mac_ver == 0x180) &&
 (sc)->mac_rev >= 3)) && !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
ar9287_1_3_enable_async_fifo(sc);

/* Write init values to hardware. */
ops->hw_init(sc, c, extc);

/*
* Only >=AR9280 2.0 parts are capable of encrypting unicast
* management frames using CCMP.
*/
if (AR_SREV_9280_20_OR_LATER(sc)((sc)->mac_ver > 0x080 || (((sc)->mac_ver == 0x080) &&
 (sc)->mac_rev >= 1))) {
reg = AR_READ(sc, AR_AES_MUTE_MASK1)(sc)->ops.read((sc), (0x8060));
/* Do not mask the subtype field in management frames. */
reg = RW(reg, AR_AES_MUTE_MASK1_FC0_MGMT, 0xff)(((reg) & ~0x00ff0000) | (((uint32_t)(0xff) << 16) &
 0x00ff0000));
reg = RW(reg, AR_AES_MUTE_MASK1_FC1_MGMT,(((reg) & ~0xff000000) | (((uint32_t)(~(0x08 | 0x10 | 0x20
)) << 24) & 0xff000000))
    ~(IEEE80211_FC1_RETRY | IEEE80211_FC1_PWR_MGT |(((reg) & ~0xff000000) | (((uint32_t)(~(0x08 | 0x10 | 0x20
)) << 24) & 0xff000000))
      IEEE80211_FC1_MORE_DATA))(((reg) & ~0xff000000) | (((uint32_t)(~(0x08 | 0x10 | 0x20
)) << 24) & 0xff000000));
AR_WRITE(sc, AR_AES_MUTE_MASK1, reg)(sc)->ops.write((sc), (0x8060), (reg));
} else if (AR_SREV_9160_10_OR_LATER(sc)((sc)->mac_ver >= 0x040)) {
/* Disable hardware crypto for management frames. */
AR_CLRBITS(sc, AR_PCU_MISC_MODE2,(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), (
0x8344)) & ~(0x00000002)))
    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE)(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), (
0x8344)) & ~(0x00000002)));
AR_SETBITS(sc, AR_PCU_MISC_MODE2,(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), (
0x8344)) | (0x00000004)))
    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT)(sc)->ops.write((sc), (0x8344), ((sc)->ops.read((sc), (
0x8344)) | (0x00000004)));
}

if (ic->ic_curmode != IEEE80211_MODE_11B)
ops->set_delta_slope(sc, c, extc);

ops->spur_mitigate(sc, c, extc);
ops->init_from_rom(sc, c, extc);

/* XXX */
AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]))(sc)->ops.write((sc), (0x8000), (((&ic->ic_myaddr[0
])[0] | (&ic->ic_myaddr[0])[1] << 8 | (&ic->
ic_myaddr[0])[2] << 16 | (&ic->ic_myaddr[0])[3] <<
 24)));
AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |(sc)->ops.write((sc), (0x8004), (((&ic->ic_myaddr[4
])[0] | (&ic->ic_myaddr[4])[1] << 8) | sta_id1 |
 0x00800000 | 0x08000000))
   sta_id1 | AR_STA_ID1_RTS_USE_DEF | AR_STA_ID1_CRPT_MIC_ENABLE)(sc)->ops.write((sc), (0x8004), (((&ic->ic_myaddr[4
])[0] | (&ic->ic_myaddr[4])[1] << 8) | sta_id1 |
 0x00800000 | 0x08000000));

athn_set_opmode(sc);

AR_WRITE(sc, AR_BSSMSKL, 0xffffffff)(sc)->ops.write((sc), (0x80e0), (0xffffffff));
AR_WRITE(sc, AR_BSSMSKU, 0xffff)(sc)->ops.write((sc), (0x80e4), (0xffff));

/* Restore previous antenna. */
AR_WRITE(sc, AR_DEF_ANTENNA, def_ant)(sc)->ops.write((sc), (0x8058), (def_ant));

AR_WRITE(sc, AR_BSS_ID0, 0)(sc)->ops.write((sc), (0x8008), (0));
AR_WRITE(sc, AR_BSS_ID1, 0)(sc)->ops.write((sc), (0x800c), (0));

AR_WRITE(sc, AR_ISR, 0xffffffff)(sc)->ops.write((sc), (0x0080), (0xffffffff));

AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7))(sc)->ops.write((sc), (0x8018), ((((uint32_t)(7) << 8
) & 0x0000ff00)));

if ((error = ops->set_synth(sc, c, extc)) != 0) {
printf("%s: could not set channel\n", sc->sc_dev.dv_xname);
return (error);
}
sc->curchan = c;
sc->curchanext = extc;

for (i = 0; i < AR_NUM_DCU10; i++)
AR_WRITE(sc, AR_DQCUMASK(i), 1 << i)(sc)->ops.write((sc), ((0x1000 + (i) * 4)), (1 << i)
);

athn_init_tx_queues(sc);

/* Initialize interrupt mask. */
sc->imask =
   AR_IMR_TXDESC0x00000080 | AR_IMR_TXEOL0x00000400 |
   AR_IMR_RXERR0x00000004 | AR_IMR_RXEOL0x00000010 | AR_IMR_RXORN0x00000020 |
   AR_IMR_RXMINTR0x01000000 | AR_IMR_RXINTM0x80000000 |
   AR_IMR_GENTMR0x10000000 | AR_IMR_BCNMISC0x00800000;
if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
sc->imask |= AR_IMR_RXERR0x00000004 | AR_IMR_HP_RXOK0x00000001;
2391#ifndef IEEE80211_STA_ONLY
if (0 && ic->ic_opmode == IEEE80211_M_HOSTAP)
sc->imask |= AR_IMR_MIB0x00001000;
2394#endif
AR_WRITE(sc, AR_IMR, sc->imask)(sc)->ops.write((sc), (0x00a0), (sc->imask));
AR_SETBITS(sc, AR_IMR_S2, AR_IMR_S2_GTT)(sc)->ops.write((sc), (0x00ac), ((sc)->ops.read((sc), (
0x00ac)) | (0x00800000)));
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff)(sc)->ops.write((sc), (0x4028), (0xffffffff));
sc->isync = AR_INTR_SYNC_DEFAULT(0x00000020 | 0x00000040 | 0x00000100 | 0x00000200 | 0x00000400
 | 0x00000800 | 0x00001000 | 0x00002000 | 0x00020000);
if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5))
sc->isync |= AR_INTR_SYNC_GPIO_PIN(sc->rfsilent_pin)(1 << (18 + (sc->rfsilent_pin)));
AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->isync)(sc)->ops.write((sc), (0x402c), (sc->isync));
AR_WRITE(sc, AR_INTR_SYNC_MASK, 0)(sc)->ops.write((sc), (0x4034), (0));
if (AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0)) {
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0)(sc)->ops.write((sc), (0x40d4), (0));
AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0)(sc)->ops.write((sc), (0x40c8), (0));
AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0)(sc)->ops.write((sc), (0x40c4), (0));
AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0)(sc)->ops.write((sc), (0x40cc), (0));
}

athn_init_qos(sc);

AR_SETBITS(sc, AR_PCU_MISC, AR_PCU_MIC_NEW_LOC_ENA)(sc)->ops.write((sc), (0x8120), ((sc)->ops.read((sc), (
0x8120)) | (0x00000004)));

athn_setsifs(sc);
athn_updateslot(ic);
athn_setclockrate(sc);
if (AR_SREV_9287_13_OR_LATER(sc)((sc)->mac_ver > 0x180 || (((sc)->mac_ver == 0x180) &&
 (sc)->mac_rev >= 3)) && !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
ar9287_1_3_setup_async_fifo(sc);

/* Disable sequence number generation in hardware. */
AR_SETBITS(sc, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM)(sc)->ops.write((sc), (0x8004), ((sc)->ops.read((sc), (
0x8004)) | (0x20000000)));

athn_init_dma(sc);

/* Program observation bus to see MAC interrupts. */
AR_WRITE(sc, sc->obs_off, 8)(sc)->ops.write((sc), (sc->obs_off), (8));

/* Setup Rx interrupt mitigation. */
AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500))(sc)->ops.write((sc), (0x002c), ((((uint32_t)(2000) <<
 16) & 0xffff0000) | (((uint32_t)(500) << 0) & 0x0000ffff
)));

/* Setup Tx interrupt mitigation. */
AR_WRITE(sc, AR_TIMT, SM(AR_TIMT_FIRST, 2000) | SM(AR_TIMT_LAST, 500))(sc)->ops.write((sc), (0x0028), ((((uint32_t)(2000) <<
 16) & 0xffff0000) | (((uint32_t)(500) << 0) & 0x0000ffff
)));

/* Set maximum interrupt rate threshold (in micro seconds). */
AR_WRITE(sc, AR_MIRT, SM(AR_MIRT_RATE_THRES, 2000))(sc)->ops.write((sc), (0x0020), ((((uint32_t)(2000) <<
 0) & 0x0000ffff)));

ops->init_baseband(sc);

if ((error = athn_init_calib(sc, c, extc)) != 0) {
printf("%s: could not initialize calibration\n",
    sc->sc_dev.dv_xname);
return (error);
}

ops->set_rxchains(sc);

AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ)(sc)->ops.write((sc), (0x1f04), (cfg_led | 3));

if (sc->flags & ATHN_FLAG_USB(1 << 1)) {
if (AR_SREV_9271(sc)((sc)->mac_ver == 0x140))
	AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB)(sc)->ops.write((sc), (0x0014), (0x00000008 | 0x00000002));
else
	AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD)(sc)->ops.write((sc), (0x0014), (0x00000001 | 0x00000004));
}
2455#if BYTE_ORDER1234 == BIG_ENDIAN4321
else {
/* Default is LE, turn on swapping for BE. */
AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD)(sc)->ops.write((sc), (0x0014), (0x00000001 | 0x00000004));
}
2460#endif
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

return (0);
2464}

2466struct ieee80211_node *
2467athn_node_alloc(struct ieee80211com *ic)
2468{
struct athn_node *an;

an = malloc(sizeof(struct athn_node), M_DEVBUF2, M_NOWAIT0x0002 | M_ZERO0x0008);
if (an && (ic->ic_flags & IEEE80211_F_HTON0x02000000))
ieee80211_ra_node_init(&an->rn);
return (struct ieee80211_node *)an;
2475}

2477void
2478athn_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew)
2479{
struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
struct athn_node *an = (void *)ni;
struct ieee80211_rateset *rs = &ni->ni_rates;
uint8_t rate;
int ridx, i, j;

if ((ni->ni_flags & IEEE80211_NODE_HT0x0400) == 0)
ieee80211_amrr_node_init(&sc->amrr, &an->amn);
else if (ic->ic_opmode == IEEE80211_M_STA)
ieee80211_ra_node_init(&an->rn);

/* Start at lowest available bit-rate, AMRR will raise. */
ni->ni_txrate = 0;

for (i = 0; i < rs->rs_nrates; i++) {
rate = rs->rs_rates[i] & IEEE80211_RATE_VAL0x7f;

/* Map 802.11 rate to HW rate index. */
for (ridx = 0; ridx <= ATHN_RIDX_MAX27; ridx++)
	if (athn_rates[ridx].rate == rate)
		break;
an->ridx[i] = ridx;
DPRINTFN(2, ("rate %d index %d\n", rate, ridx));

/* Compute fallback rate for retries. */
an->fallback[i] = i;
for (j = i - 1; j >= 0; j--) {
	if (athn_rates[an->ridx[j]].phy ==
	    athn_rates[an->ridx[i]].phy) {
		an->fallback[i] = j;
		break;
	}
}
DPRINTFN(2, ("%d fallbacks to %d\n", i, an->fallback[i]));
}

/* In 11n mode, start at lowest available bit-rate, MiRA will raise. */
ni->ni_txmcs = 0;

for (i = 0; i <= ATHN_MCS_MAX15; i++) {
/* Map MCS index to HW rate index. */
ridx = ATHN_NUM_LEGACY_RATES15 + i;
an->ridx[ridx] = ATHN_RIDX_MCS012 + i;

DPRINTFN(2, ("mcs %d index %d ", i, ridx));
/* Compute fallback rate for retries. */
if (i == 0 || i == 8) {
 	/* MCS 0 and 8 fall back to the lowest legacy rate. */
	if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan)(((ni->ni_chan)->ic_flags & 0x0100) != 0))
		an->fallback[ridx] = ATHN_RIDX_OFDM64;
	else
		an->fallback[ridx] = ATHN_RIDX_CCK10;
} else {
	/* Other MCS fall back to next supported lower MCS. */
	an->fallback[ridx] = ATHN_NUM_LEGACY_RATES15 + i;
	for (j = i - 1; j >= 0; j--) {
		if (!isset(ni->ni_rxmcs, j)((ni->ni_rxmcs)[(j)>>3] & (1<<((j)&(8 -
1)))))
			continue;
		an->fallback[ridx] = ATHN_NUM_LEGACY_RATES15 + j;
		break;
	}
}
DPRINTFN(2, (" fallback to %d\n", an->fallback[ridx]));
}
2544}

2546int
2547athn_media_change(struct ifnet *ifp)
2548{
struct athn_softc *sc = ifp->if_softc;
struct ieee80211com *ic = &sc->sc_ic;
uint8_t rate, ridx;
int error;

error = ieee80211_media_change(ifp);
if (error != ENETRESET52)
return (error);

if (ic->ic_fixed_rate != -1) {
rate = ic->ic_sup_rates[ic->ic_curmode].
    rs_rates[ic->ic_fixed_rate] & IEEE80211_RATE_VAL0x7f;
/* Map 802.11 rate to HW rate index. */
for (ridx = 0; ridx <= ATHN_RIDX_MAX27; ridx++)
	if (athn_rates[ridx].rate == rate)
		break;
sc->fixed_ridx = ridx;
}
if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
   (IFF_UP0x1 | IFF_RUNNING0x40)) {
athn_stop(ifp, 0);
error = athn_init(ifp);
}
return (error);
2573}

2575void
2576athn_next_scan(void *arg)
2577{
struct athn_softc *sc = arg;
struct ieee80211com *ic = &sc->sc_ic;
int s;

s = splnet()splraise(0x4);
if (ic->ic_state == IEEE80211_S_SCAN)
ieee80211_next_scan(&ic->ic_ific_ac.ac_if);
splx(s)spllower(s);
2586}

2588int
2589athn_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2590{
struct ifnet *ifp = &ic->ic_ific_ac.ac_if;
struct athn_softc *sc = ifp->if_softc;
uint32_t reg;
int error;

timeout_del(&sc->calib_to);

switch (nstate) {
case IEEE80211_S_INIT:
athn_set_led(sc, 0);
break;
case IEEE80211_S_SCAN:
/* Make the LED blink while scanning. */
athn_set_led(sc, !sc->led_state);
error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL((void *)0));
if (error != 0)
	return (error);
timeout_add_msec(&sc->scan_to, 200);
break;
case IEEE80211_S_AUTH:
athn_set_led(sc, 0);
error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL((void *)0));
if (error != 0)
	return (error);
break;
case IEEE80211_S_ASSOC:
break;
case IEEE80211_S_RUN:
athn_set_led(sc, 1);
2620#ifndef IEEE80211_STA_ONLY
if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
	error = athn_switch_chan(sc, ic->ic_bss->ni_chan, NULL((void *)0));
	if (error != 0)
		return (error);
} else
2626#endif
if (ic->ic_opmode == IEEE80211_M_MONITOR) {
	error = athn_switch_chan(sc, ic->ic_ibss_chan, NULL((void *)0));
	if (error != 0)
		return (error);
	break;
}

/* Fake a join to initialize the Tx rate. */
athn_newassoc(ic, ic->ic_bss, 1);

athn_set_bss(sc, ic->ic_bss);
athn_disable_interrupts(sc);
2639#ifndef IEEE80211_STA_ONLY
if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
	athn_set_hostap_timers(sc);
	/* Enable software beacon alert interrupts. */
	sc->imask |= AR_IMR_SWBA0x00010000;
} else
2645#endif
{
	athn_set_sta_timers(sc);
	/* Enable beacon miss interrupts. */
	sc->imask |= AR_IMR_BMISS0x00040000;

	/* Stop receiving beacons from other BSS. */
	reg = AR_READ(sc, AR_RX_FILTER)(sc)->ops.read((sc), (0x803c));
	reg = (reg & ~AR_RX_FILTER_BEACON0x00000010) |
	    AR_RX_FILTER_MYBEACON0x00000200;
	AR_WRITE(sc, AR_RX_FILTER, reg)(sc)->ops.write((sc), (0x803c), (reg));
	AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
}
athn_enable_interrupts(sc);

if (sc->sup_calib_mask != 0) {
	memset(&sc->calib, 0, sizeof(sc->calib))__builtin_memset((&sc->calib), (0), (sizeof(sc->calib
)));
	sc->cur_calib_mask = sc->sup_calib_mask;
	sc->ops.do_calib(sc);
}
/* XXX Start ANI. */

athn_start_noisefloor_calib(sc, 1);
timeout_add_msec(&sc->calib_to, 500);
break;
}

return (sc->sc_newstate(ic, nstate, arg));
2673}

2675void
2676athn_updateedca(struct ieee80211com *ic)
2677{
2678#define ATHN_EXP2(x)	((1 << (x)) - 1)	/* CWmin = 2^ECWmin - 1 */
struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
const struct ieee80211_edca_ac_params *ac;
int aci, qid;

for (aci = 0; aci < EDCA_NUM_AC4; aci++) {
ac = &ic->ic_edca_ac[aci];
qid = athn_ac2qid[aci];

AR_WRITE(sc, AR_DLCL_IFS(qid),(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t
)(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) |
 (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) &
 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) &
 0x0ff00000)))
    SM(AR_D_LCL_IFS_CWMIN, ATHN_EXP2(ac->ac_ecwmin)) |(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t
)(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) |
 (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) &
 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) &
 0x0ff00000)))
    SM(AR_D_LCL_IFS_CWMAX, ATHN_EXP2(ac->ac_ecwmax)) |(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t
)(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) |
 (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) &
 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) &
 0x0ff00000)))
    SM(AR_D_LCL_IFS_AIFS, ac->ac_aifsn))(sc)->ops.write((sc), ((0x1040 + (qid) * 4)), ((((uint32_t
)(ATHN_EXP2(ac->ac_ecwmin)) << 0) & 0x000003ff) |
 (((uint32_t)(ATHN_EXP2(ac->ac_ecwmax)) << 10) &
 0x000ffc00) | (((uint32_t)(ac->ac_aifsn) << 20) &
 0x0ff00000)));
if (ac->ac_txoplimit != 0) {
	AR_WRITE(sc, AR_DCHNTIME(qid),(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t
)(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff)
 | 0x00100000))
	    SM(AR_D_CHNTIME_DUR,(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t
)(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff)
 | 0x00100000))
	       IEEE80211_TXOP_TO_US(ac->ac_txoplimit)) |(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t
)(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff)
 | 0x00100000))
	    AR_D_CHNTIME_EN)(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), ((((uint32_t
)(((ac->ac_txoplimit) * 32)) << 0) & 0x000fffff)
 | 0x00100000));
} else
	AR_WRITE(sc, AR_DCHNTIME(qid), 0)(sc)->ops.write((sc), ((0x10c0 + (qid) * 4)), (0));
}
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2700#undef ATHN_EXP2
2701}

2703int
2704athn_clock_rate(struct athn_softc *sc)
2705{
struct ieee80211com *ic = &sc->sc_ic;
int clockrate;	/* MHz. */

/*
* AR9287 v1.3+ MAC runs at 117MHz (instead of 88/44MHz) when
* ASYNC FIFO is enabled.
*/
if (AR_SREV_9287_13_OR_LATER(sc)((sc)->mac_ver > 0x180 || (((sc)->mac_ver == 0x180) &&
 (sc)->mac_rev >= 3)) && !AR_SREV_9380_10_OR_LATER(sc)((sc)->mac_ver >= 0x1c0))
clockrate = 117;
else if (ic->ic_bss->ni_chan != IEEE80211_CHAN_ANYC((struct ieee80211_channel *) ((void *)0)) &&
   IEEE80211_IS_CHAN_5GHZ(ic->ic_bss->ni_chan)(((ic->ic_bss->ni_chan)->ic_flags & 0x0100) != 0
)) {
if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK(1 << 4))
	clockrate = AR_CLOCK_RATE_FAST_5GHZ_OFDM44;
else
	clockrate = AR_CLOCK_RATE_5GHZ_OFDM40;
} else if (ic->ic_curmode == IEEE80211_MODE_11B) {
clockrate = AR_CLOCK_RATE_CCK22;
} else
clockrate = AR_CLOCK_RATE_2GHZ_OFDM44;
if (sc->curchanext != NULL((void *)0))
clockrate *= 2;

return (clockrate);
2729}

2731int
2732athn_chan_sifs(struct ieee80211_channel *c)
2733{
return IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0) ? IEEE80211_DUR_DS_SIFS10 : 16;
2735}

2737void
2738athn_setsifs(struct athn_softc *sc)
2739{
int sifs = athn_chan_sifs(sc->sc_ic.ic_bss->ni_chan);
AR_WRITE(sc, AR_D_GBL_IFS_SIFS, (sifs - 2) * athn_clock_rate(sc))(sc)->ops.write((sc), (0x1030), ((sifs - 2) * athn_clock_rate
(sc)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2743}

2745int
2746athn_acktimeout(struct ieee80211_channel *c, int slot)
2747{
int sifs = athn_chan_sifs(c);
int ackto = sifs + slot;

/* Workaround for early ACK timeouts. */
if (IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0))
ackto += 64 - sifs - slot;

return ackto;
2756}

2758void
2759athn_setacktimeout(struct athn_softc *sc, struct ieee80211_channel *c, int slot)
2760{
int ackto = athn_acktimeout(c, slot);
uint32_t reg = AR_READ(sc, AR_TIME_OUT)(sc)->ops.read((sc), (0x8014));
reg = RW(reg, AR_TIME_OUT_ACK, ackto * athn_clock_rate(sc))(((reg) & ~0x00003fff) | (((uint32_t)(ackto * athn_clock_rate
(sc)) << 0) & 0x00003fff));
AR_WRITE(sc, AR_TIME_OUT, reg)(sc)->ops.write((sc), (0x8014), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2766}

2768void
2769athn_setctstimeout(struct athn_softc *sc, struct ieee80211_channel *c, int slot)
2770{
int ctsto = athn_acktimeout(c, slot);
int sifs = athn_chan_sifs(c);
uint32_t reg = AR_READ(sc, AR_TIME_OUT)(sc)->ops.read((sc), (0x8014));

/* Workaround for early CTS timeouts. */
if (IEEE80211_IS_CHAN_2GHZ(c)(((c)->ic_flags & 0x0080) != 0))
ctsto += 48 - sifs - slot;

reg = RW(reg, AR_TIME_OUT_CTS, ctsto * athn_clock_rate(sc))(((reg) & ~0x3fff0000) | (((uint32_t)(ctsto * athn_clock_rate
(sc)) << 16) & 0x3fff0000));
AR_WRITE(sc, AR_TIME_OUT, reg)(sc)->ops.write((sc), (0x8014), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2782}

2784void
2785athn_setclockrate(struct athn_softc *sc)
2786{
int clockrate = athn_clock_rate(sc);
uint32_t reg = AR_READ(sc, AR_USEC)(sc)->ops.read((sc), (0x801c));
reg = RW(reg, AR_USEC_USEC, clockrate - 1)(((reg) & ~0x0000007f) | (((uint32_t)(clockrate - 1) <<
 0) & 0x0000007f));
AR_WRITE(sc, AR_USEC, reg)(sc)->ops.write((sc), (0x801c), (reg));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2792}

2794void
2795athn_updateslot(struct ieee80211com *ic)
2796{
struct athn_softc *sc = ic->ic_softcic_ac.ac_if.if_softc;
int slot;

slot = (ic->ic_flags & IEEE80211_F_SHSLOT0x00020000) ?
   IEEE80211_DUR_DS_SHSLOT9 : IEEE80211_DUR_DS_SLOT20;
AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc))(sc)->ops.write((sc), (0x1070), (slot * athn_clock_rate(sc
)));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));

athn_setacktimeout(sc, ic->ic_bss->ni_chan, slot);
athn_setctstimeout(sc, ic->ic_bss->ni_chan, slot);
2807}

2809void
2810athn_start(struct ifnet *ifp)
2811{
struct athn_softc *sc = ifp->if_softc;
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_node *ni;
struct mbuf *m;

if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd))
return;

for (;;) {
if (SIMPLEQ_EMPTY(&sc->txbufs)(((&sc->txbufs)->sqh_first) == ((void *)0))) {
	ifq_set_oactive(&ifp->if_snd);
	break;
}
/* Send pending management frames first. */
m = mq_dequeue(&ic->ic_mgtq);
if (m != NULL((void *)0)) {
	ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie;
	goto sendit;
}
if (ic->ic_state != IEEE80211_S_RUN)
	break;

m = mq_dequeue(&ic->ic_pwrsaveq);
if (m != NULL((void *)0)) {
	ni = m->m_pkthdrM_dat.MH.MH_pkthdr.ph_cookie;
	goto sendit;
}
if (ic->ic_state != IEEE80211_S_RUN)
	break;

/* Encapsulate and send data frames. */
m = ifq_dequeue(&ifp->if_snd);
if (m == NULL((void *)0))
	break;
2846#if NBPFILTER1 > 0
if (ifp->if_bpf != NULL((void *)0))
	bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
2849#endif
if ((m = ieee80211_encap(ifp, m, &ni)) == NULL((void *)0))
	continue;
sendit:
2853#if NBPFILTER1 > 0
if (ic->ic_rawbpf != NULL((void *)0))
	bpf_mtap(ic->ic_rawbpf, m, BPF_DIRECTION_OUT(1 << 1));
2856#endif
if (sc->ops.tx(sc, m, ni, 0) != 0) {
	ieee80211_release_node(ic, ni);
	ifp->if_oerrorsif_data.ifi_oerrors++;
	continue;
}

sc->sc_tx_timer = 5;
ifp->if_timer = 1;
}
2866}

2868void
2869athn_watchdog(struct ifnet *ifp)
2870{
struct athn_softc *sc = ifp->if_softc;

ifp->if_timer = 0;

if (sc->sc_tx_timer > 0) {
if (--sc->sc_tx_timer == 0) {
	printf("%s: device timeout\n", sc->sc_dev.dv_xname);
	athn_stop(ifp, 1);
	(void)athn_init(ifp);
	ifp->if_oerrorsif_data.ifi_oerrors++;
	return;
}
ifp->if_timer = 1;
}

ieee80211_watchdog(ifp);
2887}

2889void
2890athn_set_multi(struct athn_softc *sc)
2891{
struct arpcom *ac = &sc->sc_ic.ic_ac;
struct ifnet *ifp = &ac->ac_if;
struct ether_multi *enm;
struct ether_multistep step;
const uint8_t *addr;
uint32_t val, lo, hi;
uint8_t bit;

if (ac->ac_multirangecnt > 0)
ifp->if_flags |= IFF_ALLMULTI0x200;

if ((ifp->if_flags & (IFF_ALLMULTI0x200 | IFF_PROMISC0x100)) != 0) {
lo = hi = 0xffffffff;
goto done;
}
lo = hi = 0;
ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
 ( 0);
while (enm != NULL((void *)0)) {
addr = enm->enm_addrlo;
/* Calculate the XOR value of all eight 6-bit words. */
val = addr[0] | addr[1] << 8 | addr[2] << 16;
bit  = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
val = addr[3] | addr[4] << 8 | addr[5] << 16;
bit ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
bit &= 0x3f;
if (bit < 32)
	lo |= 1 << bit;
else
	hi |= 1 << (bit - 32);
ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}
done:
AR_WRITE(sc, AR_MCAST_FIL0, lo)(sc)->ops.write((sc), (0x8040), (lo));
AR_WRITE(sc, AR_MCAST_FIL1, hi)(sc)->ops.write((sc), (0x8044), (hi));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
2927}

2929int
2930athn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2931{
struct athn_softc *sc = ifp->if_softc;
struct ieee80211com *ic = &sc->sc_ic;
struct ifreq *ifr;
int s, error = 0;

s = splnet()splraise(0x4);

switch (cmd) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
/* FALLTHROUGH */
case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if ((ifp->if_flags & IFF_RUNNING0x40) &&
	    ((ifp->if_flags ^ sc->sc_if_flags) &
	     (IFF_ALLMULTI0x200 | IFF_PROMISC0x100)) != 0) {
		athn_set_multi(sc);
	} else if (!(ifp->if_flags & IFF_RUNNING0x40))
		error = athn_init(ifp);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		athn_stop(ifp, 1);
}
sc->sc_if_flags = ifp->if_flags;
break;

case SIOCADDMULTI((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((49))):
case SIOCDELMULTI((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((50))):
ifr = (struct ifreq *)data;
error = (cmd == SIOCADDMULTI((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((49)))) ?
    ether_addmulti(ifr, &ic->ic_ac) :
    ether_delmulti(ifr, &ic->ic_ac);
if (error == ENETRESET52) {
	athn_set_multi(sc);
	error = 0;
}
break;

case SIOCS80211CHANNEL((unsigned long)0x80000000 | ((sizeof(struct ieee80211chanreq
) & 0x1fff) << 16) | ((('i')) << 8) | ((238))
):
error = ieee80211_ioctl(ifp, cmd, data);
if (error == ENETRESET52 &&
    ic->ic_opmode == IEEE80211_M_MONITOR) {
	if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
	    (IFF_UP0x1 | IFF_RUNNING0x40))
		athn_switch_chan(sc, ic->ic_ibss_chan, NULL((void *)0));
	error = 0;
}
break;

default:
error = ieee80211_ioctl(ifp, cmd, data);
}

if (error == ENETRESET52) {
error = 0;
if ((ifp->if_flags & (IFF_UP0x1 | IFF_RUNNING0x40)) ==
    (IFF_UP0x1 | IFF_RUNNING0x40)) {
	athn_stop(ifp, 0);
	error = athn_init(ifp);
}
}

splx(s)spllower(s);
return (error);
2996}

2998int
2999athn_init(struct ifnet *ifp)
3000{
struct athn_softc *sc = ifp->if_softc;
struct athn_ops *ops = &sc->ops;
struct ieee80211com *ic = &sc->sc_ic;
struct ieee80211_channel *c, *extc;
int i, error;

c = ic->ic_bss->ni_chan = ic->ic_ibss_chan;
extc = NULL((void *)0);

/* In case a new MAC address has been configured. */
IEEE80211_ADDR_COPY(ic->ic_myaddr, LLADDR(ifp->if_sadl))__builtin_memcpy((ic->ic_myaddr), (((caddr_t)((ifp->if_sadl
)->sdl_data + (ifp->if_sadl)->sdl_nlen))), (6));

/* For CardBus, power on the socket. */
if (sc->sc_enable != NULL((void *)0)) {
4
←
Assuming field 'sc_enable' is equal to NULL→
5
←
Taking false branch→
if ((error = sc->sc_enable(sc)) != 0) {
	printf("%s: could not enable device\n",
	    sc->sc_dev.dv_xname);
	goto fail;
}
if ((error = athn_reset_power_on(sc)) != 0) {
	printf("%s: could not power on device\n",
	    sc->sc_dev.dv_xname);
	goto fail;
}
}
if (!(sc->flags & ATHN_FLAG_PCIE(1 << 0)))
6
←
Assuming the condition is true→
7
←
Taking true branch→
athn_config_nonpcie(sc);
else
athn_config_pcie(sc);

ops->enable_antenna_diversity(sc);

3033#ifdef ATHN_BT_COEXISTENCE
/* Configure bluetooth coexistence for combo chips. */
if (sc->flags & ATHN_FLAG_BTCOEX((1 << 7) | (1 << 8)))
athn_btcoex_init(sc);
3037#endif

/* Configure LED. */
athn_led_init(sc);

/* Configure hardware radio switch. */
if (sc->flags & ATHN_FLAG_RFSILENT(1 << 5))
8
←
Assuming the condition is false→
9
←
Taking false branch→
ops->rfsilent_init(sc);

if ((error = athn_hw_reset(sc, c, extc, 1)) != 0) {
10
←
Assuming the condition is false→
11
←
Taking false branch→
printf("%s: unable to reset hardware; reset status %d\n",
    sc->sc_dev.dv_xname, error);
goto fail;
}

athn_config_ht(sc);
12
←
Calling 'athn_config_ht'→

/* Enable Rx. */
athn_rx_start(sc);

/* Reset HW key cache entries. */
for (i = 0; i < sc->kc_entries; i++)
athn_reset_key(sc, i);

/* Enable interrupts. */
athn_enable_interrupts(sc);

3064#ifdef ATHN_BT_COEXISTENCE
/* Enable bluetooth coexistence for combo chips. */
if (sc->flags & ATHN_FLAG_BTCOEX((1 << 7) | (1 << 8)))
athn_btcoex_enable(sc);
3068#endif

ifq_clr_oactive(&ifp->if_snd);
ifp->if_flags |= IFF_RUNNING0x40;

3073#ifdef notyet
if (ic->ic_flags & IEEE80211_F_WEPON0x00000100) {
/* Configure WEP keys. */
for (i = 0; i < IEEE80211_WEP_NKID4; i++)
	athn_set_key(ic, NULL((void *)0), &ic->ic_nw_keys[i]);
}
3079#endif
if (ic->ic_opmode == IEEE80211_M_MONITOR)
ieee80211_new_state(ic, IEEE80211_S_RUN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_RUN), (-1)));
else
ieee80211_new_state(ic, IEEE80211_S_SCAN, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_SCAN), (-1)));

return (0);
fail:
athn_stop(ifp, 1);
return (error);
3089}

3091void
3092athn_stop(struct ifnet *ifp, int disable)
3093{
struct athn_softc *sc = ifp->if_softc;
struct ieee80211com *ic = &sc->sc_ic;
int qid, i;

ifp->if_timer = sc->sc_tx_timer = 0;
ifp->if_flags &= ~IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

timeout_del(&sc->scan_to);

ieee80211_new_state(ic, IEEE80211_S_INIT, -1)(((ic)->ic_newstate)((ic), (IEEE80211_S_INIT), (-1)));

3106#ifdef ATHN_BT_COEXISTENCE
/* Disable bluetooth coexistence for combo chips. */
if (sc->flags & ATHN_FLAG_BTCOEX((1 << 7) | (1 << 8)))
athn_btcoex_disable(sc);
3110#endif

/* Disable interrupts. */
athn_disable_interrupts(sc);
/* Acknowledge interrupts (avoids interrupt storms). */
AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff)(sc)->ops.write((sc), (0x4028), (0xffffffff));
AR_WRITE(sc, AR_INTR_SYNC_MASK, 0)(sc)->ops.write((sc), (0x4034), (0));

for (qid = 0; qid < ATHN_QID_COUNT8; qid++)
athn_stop_tx_dma(sc, qid);
/* XXX call athn_hw_reset if Tx still pending? */
for (qid = 0; qid < ATHN_QID_COUNT8; qid++)
athn_tx_reclaim(sc, qid);

/* Stop Rx. */
AR_SETBITS(sc, AR_DIAG_SW, AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)(sc)->ops.write((sc), (0x8048), ((sc)->ops.read((sc), (
0x8048)) | (0x00000020 | 0x02000000)));
AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC)(sc)->ops.write((sc), (0x0040), (0x00000002));
AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC)(sc)->ops.write((sc), (0x0040), (0x00000004));
AR_WRITE(sc, AR_FILT_OFDM, 0)(sc)->ops.write((sc), (0x8124), (0));
AR_WRITE(sc, AR_FILT_CCK, 0)(sc)->ops.write((sc), (0x8128), (0));
AR_WRITE_BARRIER(sc)(sc)->ops.write_barrier((sc));
athn_set_rxfilter(sc, 0);
athn_stop_rx_dma(sc);

/* Reset HW key cache entries. */
for (i = 0; i < sc->kc_entries; i++)
athn_reset_key(sc, i);

athn_reset(sc, 0);
athn_init_pll(sc, NULL((void *)0));
athn_set_power_awake(sc);
athn_reset(sc, 1);
athn_init_pll(sc, NULL((void *)0));

athn_set_power_sleep(sc);

/* For CardBus, power down the socket. */
if (disable && sc->sc_disable != NULL((void *)0))
sc->sc_disable(sc);
3149}

3151void
3152athn_suspend(struct athn_softc *sc)
3153{
struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;

if (ifp->if_flags & IFF_RUNNING0x40)
athn_stop(ifp, 1);
3158}

3160void
3161athn_wakeup(struct athn_softc *sc)
3162{
struct ifnet *ifp = &sc->sc_ic.ic_ific_ac.ac_if;

if (ifp->if_flags & IFF_UP0x1)
1
Assuming the condition is true→
2
←
Taking true branch→
athn_init(ifp);
3
←
Calling 'athn_init'→
3167}