Bug Summary

File:dev/pci/drm/amd/amdgpu/gfx_v10_0.c
Warning:line 5966, column 2
Value stored to 'tmp' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name gfx_v10_0.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "amdgpu.h"
30#include "amdgpu_gfx.h"
31#include "amdgpu_psp.h"
32#include "nv.h"
33#include "nvd.h"
34
35#include "gc/gc_10_1_0_offset.h"
36#include "gc/gc_10_1_0_sh_mask.h"
37#include "smuio/smuio_11_0_0_offset.h"
38#include "smuio/smuio_11_0_0_sh_mask.h"
39#include "navi10_enum.h"
40#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42#include "soc15.h"
43#include "soc15d.h"
44#include "soc15_common.h"
45#include "clearstate_gfx10.h"
46#include "v10_structs.h"
47#include "gfx_v10_0.h"
48#include "nbio_v2_3.h"
49
50/*
51 * Navi10 has two graphic rings to share each graphic pipe.
52 * 1. Primary ring
53 * 2. Async ring
54 */
55#define GFX10_NUM_GFX_RINGS_NV1X1 1
56#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid2 2
57#define GFX10_MEC_HPD_SIZE2048 2048
58
59#define F32_CE_PROGRAM_RAM_SIZE65536 65536
60#define RLCG_UCODE_LOADING_START_ADDRESS0x00002000L 0x00002000L
61
62#define mmCGTT_GS_NGG_CLK_CTRL0x5087 0x5087
63#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX1 1
64#define mmCGTT_SPI_RA0_CLK_CTRL0x507a 0x507a
65#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX1 1
66#define mmCGTT_SPI_RA1_CLK_CTRL0x507b 0x507b
67#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX1 1
68
69#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT0x8 0x8
70#define GB_ADDR_CONFIG__NUM_PKRS_MASK0x00000700L 0x00000700L
71
72#define mmCGTS_TCC_DISABLE_gc_10_30x5006 0x5006
73#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX1 1
74#define mmCGTS_USER_TCC_DISABLE_gc_10_30x5007 0x5007
75#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX1 1
76
77#define mmCP_MEC_CNTL_Sienna_Cichlid0x0f55 0x0f55
78#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX0 0
79#define mmRLC_SAFE_MODE_Sienna_Cichlid0x4ca0 0x4ca0
80#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX1 1
81#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid0x4ca1 0x4ca1
82#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX1 1
83#define mmSPI_CONFIG_CNTL_Sienna_Cichlid0x11ec 0x11ec
84#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX0 0
85#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid0x0fc1 0x0fc1
86#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX0 0
87#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid0x0fc2 0x0fc2
88#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX0 0
89#define mmVGT_TF_RING_SIZE_Sienna_Cichlid0x0fc3 0x0fc3
90#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX0 0
91#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid0x0fc4 0x0fc4
92#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX0 0
93#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid0x0fc5 0x0fc5
94#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX0 0
95#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid0x0fc6 0x0fc6
96#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX0 0
97#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT0x1a 0x1a
98#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK0x04000000L 0x04000000L
99#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK0x00000FFCL 0x00000FFCL
100#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT0x2 0x2
101#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK0x00000FFCL 0x00000FFCL
102#define mmGCR_GENERAL_CNTL_Sienna_Cichlid0x1580 0x1580
103#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX0 0
104
105#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh0x0025 0x0025
106#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX1 1
107#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh0x0026 0x0026
108#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX1 1
109
110#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_60x002d 0x002d
111#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX1 1
112#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_60x002e 0x002e
113#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX1 1
114
115#define mmSPI_CONFIG_CNTL_1_Vangogh0x2441 0x2441
116#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX1 1
117#define mmVGT_TF_MEMORY_BASE_HI_Vangogh0x2261 0x2261
118#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX1 1
119#define mmVGT_HS_OFFCHIP_PARAM_Vangogh0x224f 0x224f
120#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX1 1
121#define mmVGT_TF_RING_SIZE_Vangogh0x224e 0x224e
122#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX1 1
123#define mmVGT_GSVS_RING_SIZE_Vangogh0x2241 0x2241
124#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX1 1
125#define mmVGT_TF_MEMORY_BASE_Vangogh0x2250 0x2250
126#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX1 1
127#define mmVGT_ESGS_RING_SIZE_Vangogh0x2240 0x2240
128#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX1 1
129#define mmSPI_CONFIG_CNTL_Vangogh0x2440 0x2440
130#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX1 1
131#define mmGCR_GENERAL_CNTL_Vangogh0x1580 0x1580
132#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX0 0
133#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh0x0000FFFFL 0x0000FFFFL
134
135#define mmCP_HYP_PFP_UCODE_ADDR0x5814 0x5814
136#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX1 1
137#define mmCP_HYP_PFP_UCODE_DATA0x5815 0x5815
138#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX1 1
139#define mmCP_HYP_CE_UCODE_ADDR0x5818 0x5818
140#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX1 1
141#define mmCP_HYP_CE_UCODE_DATA0x5819 0x5819
142#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX1 1
143#define mmCP_HYP_ME_UCODE_ADDR0x5816 0x5816
144#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX1 1
145#define mmCP_HYP_ME_UCODE_DATA0x5817 0x5817
146#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX1 1
147
148#define mmCPG_PSP_DEBUG0x5c10 0x5c10
149#define mmCPG_PSP_DEBUG_BASE_IDX1 1
150#define mmCPC_PSP_DEBUG0x5c11 0x5c11
151#define mmCPC_PSP_DEBUG_BASE_IDX1 1
152#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK0x00000008L 0x00000008L
153#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK0x00000008L 0x00000008L
154
155//CC_GC_SA_UNIT_DISABLE
156#define mmCC_GC_SA_UNIT_DISABLE0x0fe9 0x0fe9
157#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX0 0
158#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8 0x8
159#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L 0x0000FF00L
160//GC_USER_SA_UNIT_DISABLE
161#define mmGC_USER_SA_UNIT_DISABLE0x0fea 0x0fea
162#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX0 0
163#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8 0x8
164#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L 0x0000FF00L
165//PA_SC_ENHANCE_3
166#define mmPA_SC_ENHANCE_30x1085 0x1085
167#define mmPA_SC_ENHANCE_3_BASE_IDX0 0
168#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT0x3 0x3
169#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK0x00000008L 0x00000008L
170
171#define mmCGTT_SPI_CS_CLK_CTRL0x507c 0x507c
172#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX1 1
173
174#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid0x16f3 0x16f3
175#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX0 0
176#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid0x15db 0x15db
177#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX0 0
178
179#define mmGC_THROTTLE_CTRL_Sienna_Cichlid0x2030 0x2030
180#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX0 0
181
182#define mmRLC_SPARE_INT_0_Sienna_Cichlid0x4ca5 0x4ca5
183#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX1 1
184
185MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
186MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
187MODULE_FIRMWARE("amdgpu/navi10_me.bin");
188MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
189MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
190MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
191
192MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
193MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
194MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
195MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
196MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
197MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
198MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
199MODULE_FIRMWARE("amdgpu/navi14_me.bin");
200MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
201MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
202MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
203
204MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
205MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
206MODULE_FIRMWARE("amdgpu/navi12_me.bin");
207MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
208MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
209MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
210
211MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
212MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
213MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
214MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
215MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
216MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
217
218MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
219MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
220MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
221MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
222MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
223MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
224
225MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
226MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
227MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
228MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
229MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
230MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
231
232MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
233MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
234MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
235MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
236MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
237MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
238
239MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
240MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
241MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
242MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
243MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
244MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
245
246MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
247MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
248MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
249MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
250MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
251MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
252
253MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
254MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
255MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
256MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
257MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
258MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
259
260MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
261MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
262MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
263MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
264MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
265MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
266
267MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
268MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
269MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
270MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
271MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
272MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
273
274static const struct soc15_reg_golden golden_settings_gc_10_1[] =
275{
276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014){ GC_HWIP, 0, 0, 0x1422, 0xffffffff, 0x00400014 },
277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100){ GC_HWIP, 0, 1, 0x50b1, 0xfcff8fff, 0xf8000100 },
278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100){ GC_HWIP, 0, 1, 0x5080, 0xcd000000, 0x0d000100 },
279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100){ GC_HWIP, 0, 1, 0x508c, 0x60000ff0, 0x60000100 },
280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100){ GC_HWIP, 0, 1, 0x508d, 0x40000000, 0x40000100 },
281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5084, 0xffff8fff, 0xffff8100 },
282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100){ GC_HWIP, 0, 1, 0x5086, 0xfeff8fff, 0xfeff8100 },
283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xe4e4e4e4 },
284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000){ GC_HWIP, 0, 1, 0x2d94, 0x00000002, 0x00000000 },
285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x000007ff, 0x000005ff },
286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0x20000000, 0x20000000 },
287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420){ GC_HWIP, 0, 0, 0x13ad, 0xffffffff, 0x00000420 },
288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0x00000200, 0x00000200 },
289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000){ GC_HWIP, 0, 0, 0x13af, 0x07900000, 0x04900000 },
290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f){ GC_HWIP, 0, 0, 0x13d2, 0x0000ffff, 0x0000003f },
291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860204 },
292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1583, 0x1ff0ffff, 0x00000500 },
293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe){ GC_HWIP, 0, 0, 0x1004, 0x000007ff, 0x000001fe },
294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d10, 0xffffffff, 0xe4e4e4e4 },
295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x10321032 },
296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x02310231 },
297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0x10000000, 0x10000100 },
300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f){ GC_HWIP, 0, 1, 0x2e01, 0xffffffff, 0x1402002f },
301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188){ GC_HWIP, 0, 1, 0x2e0c, 0xffff9fff, 0x00001188 },
302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x3fffffff, 0x08000009 },
304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000){ GC_HWIP, 0, 0, 0x109d, 0x00400000, 0x04440000 },
305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000800, 0x00000820 },
306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffffffff, 0xffff3101 },
308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0x001f0000, 0x00070104 },
309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x508e, 0xffffffff, 0xffffffff },
310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000100, 0x00000130 },
311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010){ GC_HWIP, 0, 0, 0x18a2, 0x60000010, 0x479c0010 },
314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100){ GC_HWIP, 0, 1, 0x50c3, 0xfeff0fff, 0x40000100 },
315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000){ GC_HWIP, 0, 0, 0x1588, 0x00c00000, 0x00c00000 }
316};
317
318static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
319{
320 /* Pending on emulation bring up */
321};
322
323static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
324{
325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xe0000000, 0x0 },
326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x28 },
328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x20 },
340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc8 },
344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xcc },
348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd0 },
352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd4 },
356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4 },
368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8 },
372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x0 },
376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x88 },
388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8c },
392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb0 },
396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb4 },
400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb8 },
404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xbc },
408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc0 },
412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc4 },
416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x90 },
420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x94 },
424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x98 },
428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x9c },
432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa0 },
436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa4 },
440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa8 },
444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xac },
448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x10 },
452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc },
456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x18 },
460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x38 },
464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x3c },
468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x40 },
472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x44 },
476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x48 },
480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4c },
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x70 },
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x74 },
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x78 },
496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x7c },
500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x80 },
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x84 },
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x50 },
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x54 },
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x58 },
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x5c },
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x60 },
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x64 },
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x68 },
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x6c },
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x1c },
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x14 },
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x12 },
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1 },
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1 },
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x2 },
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x3 },
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x30 },
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x34 },
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x2c },
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19){ GC_HWIP, 0, 1, 0x3c8c, 0x000000FF, 0x19 },
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20){ GC_HWIP, 0, 1, 0x3c8d, 0x000000FF, 0x20 },
1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x5 },
1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0xa },
1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x14 },
1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x19 },
1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33){ GC_HWIP, 0, 1, 0x3c8b, 0x000000FF, 0x33 },
1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xFFFFFFFF, 0xe0000000 }
1377};
1378
1379static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380{
1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014){ GC_HWIP, 0, 0, 0x1422, 0xffffffff, 0x003c0014 },
1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5087, 0xffff8fff, 0xffff8100 },
1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100){ GC_HWIP, 0, 1, 0x5085, 0xffff0fff, 0xffff0100 },
1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100){ GC_HWIP, 0, 1, 0x5080, 0xcd000000, 0x0d000100 },
1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100){ GC_HWIP, 0, 1, 0x508c, 0xf8ff0fff, 0x60000100 },
1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100){ GC_HWIP, 0, 1, 0x508d, 0x40000ff0, 0x40000100 },
1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5084, 0xffff8fff, 0xffff8100 },
1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5086, 0xffff8fff, 0xffff8100 },
1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xe4e4e4e4 },
1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000){ GC_HWIP, 0, 1, 0x2d94, 0x00000002, 0x00000000 },
1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x800007ff, 0x000005ff },
1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0xffffffff, 0x20000000 },
1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420){ GC_HWIP, 0, 0, 0x13ad, 0xffffffff, 0x00000420 },
1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0x00000200, 0x00000200 },
1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x04900000 },
1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f){ GC_HWIP, 0, 0, 0x13d2, 0x0000ffff, 0x0000003f },
1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860204 },
1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1583, 0x1ff0ffff, 0x00000500 },
1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe){ GC_HWIP, 0, 0, 0x1004, 0x000007ff, 0x000001fe },
1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d10, 0xffffffff, 0xe4e4e4e4 },
1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffe7 },
1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffe7 },
1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0xffff0fff, 0x10000100 },
1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f){ GC_HWIP, 0, 1, 0x2e01, 0xffffffff, 0x1402002f },
1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188){ GC_HWIP, 0, 1, 0x2e0c, 0xffffbfff, 0x00000188 },
1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x3fffffff, 0x08000009 },
1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000){ GC_HWIP, 0, 0, 0x109d, 0x00400000, 0x04440000 },
1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000800, 0x00000820 },
1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffffffff, 0xffff3101 },
1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105){ GC_HWIP, 0, 0, 0x11ef, 0x001f0000, 0x00070105 },
1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x508e, 0xffffffff, 0xffffffff },
1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000133, 0x00000130 },
1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010){ GC_HWIP, 0, 0, 0x18a2, 0x60000010, 0x479c0010 },
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000){ GC_HWIP, 0, 0, 0x1588, 0x00c00000, 0x00c00000 },
1419};
1420
1421static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422{
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014){ GC_HWIP, 0, 0, 0x1422, 0x003e001f, 0x003c0014 },
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5087, 0xffff8fff, 0xffff8100 },
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100){ GC_HWIP, 0, 1, 0x5085, 0xffff0fff, 0xffff0100 },
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100){ GC_HWIP, 0, 1, 0x5080, 0xff7f0fff, 0x0d000100 },
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100){ GC_HWIP, 0, 1, 0x508c, 0xffffcfff, 0x60000100 },
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100){ GC_HWIP, 0, 1, 0x508d, 0xffff0fff, 0x40000100 },
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5084, 0xffff8fff, 0xffff8100 },
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100){ GC_HWIP, 0, 1, 0x5086, 0xffff8fff, 0xffff8100 },
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xe4e4e4e4 },
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000){ GC_HWIP, 0, 1, 0x2d94, 0x00000003, 0x00000000 },
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x800007ff, 0x000005ff },
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0xffffffff, 0x20000000 },
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420){ GC_HWIP, 0, 0, 0x13ad, 0xffffffff, 0x00000420 },
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000200 },
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x04900000 },
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f){ GC_HWIP, 0, 0, 0x13d2, 0x0000ffff, 0x0000003f },
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860204 },
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044){ GC_HWIP, 0, 0, 0x13de, 0x0c1800ff, 0x00000044 },
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1583, 0x1ff0ffff, 0x00000500 },
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe){ GC_HWIP, 0, 0, 0x1004, 0x00007fff, 0x000001fe },
1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4){ GC_HWIP, 0, 1, 0x2d10, 0xffffffff, 0xe4e4e4e4 },
1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x10321032 },
1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x02310231 },
1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0xffff0fff, 0x10000100 },
1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f){ GC_HWIP, 0, 1, 0x2e01, 0xffffffff, 0x1402002f },
1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188){ GC_HWIP, 0, 1, 0x2e0c, 0xffffbfff, 0x00000188 },
1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02){ GC_HWIP, 0, 0, 0x106c, 0xffffffff, 0x842a4c02 },
1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x3fffffff, 0x08000009 },
1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000){ GC_HWIP, 0, 0, 0x109d, 0xffffffff, 0x04440000 },
1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000820, 0x00000820 },
1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000ff0f, 0x00000000 },
1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffffffff, 0xffff3101 },
1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0x001f0000, 0x00070104 },
1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x508e, 0xffffffff, 0xffffffff },
1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000133, 0x00000130 },
1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010){ GC_HWIP, 0, 0, 0x18a2, 0xffdf80ff, 0x479c0010 },
1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000){ GC_HWIP, 0, 0, 0x1588, 0xffffffff, 0x00c00000 }
1465};
1466
1467static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468{
1469 /* Pending on emulation bring up */
1470};
1471
1472static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473{
1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xE0000000L, 0x0 },
1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x28 },
1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x20 },
1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xf },
1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x80 },
1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x84 },
1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x88 },
1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8c },
1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4 },
1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8 },
1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x0 },
1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x60 },
1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x64 },
1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x68 },
1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x6c },
1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x70 },
1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x74 },
1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x78 },
1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x7c },
1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x10 },
1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc },
1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x18 },
1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x38 },
1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x3c },
1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x40 },
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x44 },
1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x48 },
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4c },
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x50 },
1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x54 },
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x58 },
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x5c },
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x1c },
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x14 },
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xe },
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1e },
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe4 },
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x8 },
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1a0 },
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1a4 },
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1b0 },
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1b4 },
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1a8 },
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1ac },
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1b8 },
2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1bc },
2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1c8 },
2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1cc },
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1c0 },
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x1c4 },
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x30 },
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x34 },
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x20 },
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x2c },
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26){ GC_HWIP, 0, 1, 0x3c8c, 0x000000FF, 0x26 },
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28){ GC_HWIP, 0, 1, 0x3c8d, 0x000000FF, 0x28 },
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0xf },
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x15 },
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x1f },
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x25 },
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b){ GC_HWIP, 0, 1, 0x3c8b, 0x000000FF, 0x3b },
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xFFFFFFFF, 0xe0000000 }
2094};
2095
2096static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097{
2098 /* Pending on emulation bring up */
2099};
2100
2101static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102{
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xe0000000L, 0x0 },
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x28 },
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8 },
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x20 },
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc8 },
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xcc },
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd0 },
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xd4 },
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x24 },
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4 },
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8 },
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x0 },
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x10 },
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc },
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x88 },
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x0 },
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x8c },
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb0 },
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb4 },
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xb8 },
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xbc },
2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc0 },
2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc4 },
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x90 },
2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x2 },
2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x94 },
2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x1 },
2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x98 },
2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x9c },
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa0 },
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x1 },
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa4 },
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xa8 },
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xac },
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x10 },
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x5 },
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0xc },
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x18 },
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x9 },
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x38 },
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x3c },
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x40 },
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x44 },
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x48 },
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x4c },
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x70 },
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xc },
2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x74 },
2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x78 },
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x8 },
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x7c },
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x80 },
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x84 },
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x50 },
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x54 },
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x58 },
2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x5c },
2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x60 },
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x6 },
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x64 },
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x4 },
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x68 },
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x7 },
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x6c },
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xa },
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x1c },
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x3 },
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x14 },
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x20 },
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1c },
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x24 },
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x28 },
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x2c },
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x30 },
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x34 },
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x38 },
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x3c },
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18 },
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x18 },
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x50 },
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x54 },
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x58 },
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x5c },
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14 },
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x48 },
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4c },
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x40 },
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x44 },
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1a },
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10 },
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x60 },
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x64 },
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x70 },
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x74 },
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x68 },
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x6c },
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x78 },
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x7c },
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x88 },
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x8c },
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x80 },
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x84 },
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x90 },
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x94 },
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa0 },
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa4 },
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x98 },
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x9c },
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x4 },
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xa8 },
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xac },
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb8 },
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xbc },
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb0 },
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xb4 },
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc0 },
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc4 },
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd0 },
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd4 },
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xc8 },
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xcc },
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe8 },
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xec },
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x16 },
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf0 },
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf4 },
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xf8 },
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xfc },
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x17 },
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x100 },
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x13 },
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x104 },
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x11 },
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xe0 },
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x118 },
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x11c },
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x120 },
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x124 },
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xdc },
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x110 },
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x15 },
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x114 },
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x14 },
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x108 },
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x10c },
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x19 },
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0xd8 },
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1b },
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x128 },
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x12c },
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x138 },
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x13c },
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x130 },
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x12 },
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x134 },
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xf },
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x140 },
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x144 },
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x150 },
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x154 },
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xd },
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x148 },
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x14c },
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x7 },
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x158 },
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x15c },
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x168 },
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xa },
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x16c },
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x9 },
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x160 },
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x164 },
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x0 },
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x170 },
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x174 },
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x180 },
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x184 },
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x178 },
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x10 },
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x17c },
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x188 },
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x18c },
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x5 },
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x198 },
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xc },
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x19c },
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xb },
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x190 },
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0xe },
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x194 },
3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x6 },
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x30 },
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xd },
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x34 },
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0x11 },
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x0 },
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1d },
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4){ GC_HWIP, 0, 1, 0x3c92, 0xFFFFFFFF, 0x4 },
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f){ GC_HWIP, 0, 1, 0x3c93, 0xFFFFFFFF, 0x1f },
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c){ GC_HWIP, 0, 1, 0x3c90, 0xFFFFFFFF, 0x2c },
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb){ GC_HWIP, 0, 1, 0x3c91, 0xFFFFFFFF, 0xb },
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f){ GC_HWIP, 0, 1, 0x3c8c, 0x000000FF, 0x1f },
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22){ GC_HWIP, 0, 1, 0x3c8d, 0x000000FF, 0x22 },
3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x1 },
3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6){ GC_HWIP, 0, 1, 0x3c8e, 0x000000FF, 0x6 },
3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x10 },
3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x10000 },
3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15){ GC_HWIP, 0, 1, 0x3c8f, 0x000000FF, 0x15 },
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0){ GC_HWIP, 0, 1, 0x2200, 0xffffff, 0x0 },
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35){ GC_HWIP, 0, 1, 0x3c8b, 0x000000FF, 0x35 },
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xFFFFFFFF, 0xe0000000 }
3155};
3156
3157static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158{
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0x78000000, 0x78000100 },
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507d, 0xff7f0fff, 0x78000100 },
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0xff7f0fff, 0x30000100 },
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0xff7f0fff, 0x7e000100 },
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c000 },
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000){ GC_HWIP, 0, 0, 0x13bf, 0x7fff0f1f, 0x00b80000 },
3167 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100){ GC_HWIP, 0, 0, 0x189b, 0xffffffff, 0x10100100 },
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088){ GC_HWIP, 0, 0, 0x189c, 0xffffffff, 0x17000088 },
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080){ GC_HWIP, 0, 0, 0x16f3, 0xff000000, 0xff008080 },
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080){ GC_HWIP, 0, 0, 0x15db, 0xff000000, 0xff008080 },
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400){ GC_HWIP, 0, 0, 0x0fe5, 0x003fffff, 0x00280400 },
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x10f80988 },
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x00000020, 0x00000020 },
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0xffffffff, 0x00070104 },
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070){ GC_HWIP, 0, 0, 0x10a0, 0xe07df47f, 0x00180070 },
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c0, 0xf0f001ff, 0x00000000 },
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c1, 0xf0f001ff, 0x00000000 },
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ca, 0xf0f001ff, 0x00000000 },
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cb, 0xf0f001ff, 0x00000000 },
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cc, 0xf0f001ff, 0x00000000 },
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cd, 0xf0f001ff, 0x00000000 },
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ce, 0xf0f001ff, 0x00000000 },
3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cf, 0xf0f001ff, 0x00000000 },
3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c2, 0xf0f001ff, 0x00000000 },
3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c3, 0xf0f001ff, 0x00000000 },
3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c4, 0xf0f001ff, 0x00000000 },
3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c5, 0xf0f001ff, 0x00000000 },
3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c6, 0xf0f001ff, 0x00000000 },
3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c7, 0xf0f001ff, 0x00000000 },
3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c8, 0xf0f001ff, 0x00000000 },
3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c9, 0xf0f001ff, 0x00000000 },
3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020){ GC_HWIP, 0, 0, 0x11b8, 0x00010000, 0x00010020 },
3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000){ GC_HWIP, 0, 0, 0x1588, 0xffbfffff, 0x00a00000 }
3202};
3203
3204static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205{
3206 /* Pending on emulation bring up */
3207};
3208
3209static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210{
3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0xff7f0fff, 0x78000100 },
3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507d, 0xff7f0fff, 0x78000100 },
3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0xff7f0fff, 0x30000100 },
3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0xff7f0fff, 0x7e000100 },
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c000 },
3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000){ GC_HWIP, 0, 0, 0x13bf, 0x7fff0f1f, 0x00b80000 },
3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080){ GC_HWIP, 0, 0, 0x16f3, 0xffffffff, 0xff008080 },
3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080){ GC_HWIP, 0, 0, 0x15db, 0xffff8fff, 0xff008080 },
3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400){ GC_HWIP, 0, 0, 0x0fe5, 0x003fffff, 0x00280400 },
3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104){ GC_HWIP, 0, 0, 0x11ef, 0xffffffff, 0x00070104 },
3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004){ GC_HWIP, 0, 0, 0x11db, 0x000000ff, 0x00000004 },
3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070){ GC_HWIP, 0, 0, 0x10a0, 0xe07df47f, 0x00180070 },
3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c0, 0xf0f001ff, 0x00000000 },
3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c1, 0xf0f001ff, 0x00000000 },
3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ca, 0xf0f001ff, 0x00000000 },
3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cb, 0xf0f001ff, 0x00000000 },
3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cc, 0xf0f001ff, 0x00000000 },
3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cd, 0xf0f001ff, 0x00000000 },
3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ce, 0xf0f001ff, 0x00000000 },
3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cf, 0xf0f001ff, 0x00000000 },
3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c2, 0xf0f001ff, 0x00000000 },
3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c3, 0xf0f001ff, 0x00000000 },
3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c4, 0xf0f001ff, 0x00000000 },
3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c5, 0xf0f001ff, 0x00000000 },
3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c6, 0xf0f001ff, 0x00000000 },
3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c7, 0xf0f001ff, 0x00000000 },
3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c8, 0xf0f001ff, 0x00000000 },
3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c9, 0xf0f001ff, 0x00000000 },
3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000){ GC_HWIP, 0, 0, 0x1588, 0xffbfffff, 0x00a00000 },
3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff){ GC_HWIP, 0, 0, 0x1009, 0x00000fff, 0x000003ff },
3252
3253 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x00000020, 0x00000020 },
3255};
3256
3257static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258{
3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0xff7f0fff, 0x30000100 },
3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0xff7f0fff, 0x7e000100 },
3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4){ GC_HWIP, 0, 1, 0x2d90, 0x000000ff, 0x000000e4 },
3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000200 },
3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000){ GC_HWIP, 0, 0, 0x13bf, 0x7fff0f1f, 0x00b80000 },
3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142){ GC_HWIP, 0, 0, 0x13de, 0x0c1807ff, 0x00000142 },
3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4){ GC_HWIP, 0, 1, 0x2d10, 0x000000ff, 0x000000e4 },
3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x32103210 },
3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x32103210 },
3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xfffffff3 },
3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xfffffff3 },
3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000020 },
3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103){ GC_HWIP, 0, 1, 0x2441, 0xffffffff, 0x00070103 },
3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000){ GC_HWIP, 0, 0, 0x10ba, 0x000017ff, 0x00001000 },
3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020){ GC_HWIP, 0, 0, 0x11b8, 0x00010000, 0x00010020 },
3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000){ GC_HWIP, 0, 0, 0x1588, 0xffffffff, 0x00400000 },
3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff){ GC_HWIP, 0, 0, 0x1009, 0x00000fff, 0x000000ff },
3283
3284 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x00000020, 0x00000020 },
3286};
3287
3288static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289{
3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0xff7f0fff, 0x78000100 },
3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4){ GC_HWIP, 0, 1, 0x2d90, 0x000000ff, 0x000000e4 },
3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c200 },
3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242){ GC_HWIP, 0, 0, 0x13de, 0x0c1807ff, 0x00000242 },
3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4){ GC_HWIP, 0, 1, 0x2d10, 0x000000ff, 0x000000e4 },
3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x32103210 },
3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x32103210 },
3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xfffffff3 },
3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xfffffff3 },
3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x000001ff, 0x00000020 },
3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000){ GC_HWIP, 0, 0, 0x1588, 0xffffffff, 0x00100000 }
3310};
3311
3312static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313{
3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0x78000000, 0x78000100 },
3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0x30000000, 0x30000100 },
3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0x7e000000, 0x7e000100 },
3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c000 },
3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0x00000280, 0x00000280 },
3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0x07800000, 0x00800000 },
3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x00001d00, 0x00000500 },
3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400){ GC_HWIP, 0, 0, 0x0fe5, 0x003c0000, 0x00280400 },
3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0x40000000, 0x580f1008 },
3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0x00040000, 0x00f80988 },
3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0x01000000, 0x01200007 },
3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0x00000800, 0x00000820 },
3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070){ GC_HWIP, 0, 0, 0x10a0, 0x0000001f, 0x00180070 },
3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c0, 0xf0f001ff, 0x00000000 },
3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c1, 0xf0f001ff, 0x00000000 },
3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ca, 0xf0f001ff, 0x00000000 },
3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cb, 0xf0f001ff, 0x00000000 },
3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cc, 0xf0f001ff, 0x00000000 },
3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cd, 0xf0f001ff, 0x00000000 },
3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ce, 0xf0f001ff, 0x00000000 },
3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cf, 0xf0f001ff, 0x00000000 },
3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c2, 0xf0f001ff, 0x00000000 },
3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c3, 0xf0f001ff, 0x00000000 },
3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c4, 0xf0f001ff, 0x00000000 },
3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c5, 0xf0f001ff, 0x00000000 },
3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c6, 0xf0f001ff, 0x00000000 },
3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c7, 0xf0f001ff, 0x00000000 },
3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c8, 0xf0f001ff, 0x00000000 },
3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c9, 0xf0f001ff, 0x00000000 },
3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020){ GC_HWIP, 0, 0, 0x11b8, 0x00010000, 0x00010020 },
3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0x01030000, 0x01030000 },
3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000){ GC_HWIP, 0, 0, 0x1588, 0x03a00000, 0x00a00000 },
3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x00000020, 0x00000020 }
3350};
3351
3352static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0x78000000, 0x78000100 },
3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100){ GC_HWIP, 0, 1, 0x507a, 0xb0000ff0, 0x30000100 },
3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100){ GC_HWIP, 0, 1, 0x507b, 0xff000000, 0x7e000100 },
3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c000 },
3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x000001ff, 0x00000020 },
3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070){ GC_HWIP, 0, 0, 0x10a0, 0xe07df47f, 0x00180070 },
3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c0, 0xf0f001ff, 0x00000000 },
3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c1, 0xf0f001ff, 0x00000000 },
3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ca, 0xf0f001ff, 0x00000000 },
3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cb, 0xf0f001ff, 0x00000000 },
3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cc, 0xf0f001ff, 0x00000000 },
3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cd, 0xf0f001ff, 0x00000000 },
3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39ce, 0xf0f001ff, 0x00000000 },
3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39cf, 0xf0f001ff, 0x00000000 },
3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c2, 0xf0f001ff, 0x00000000 },
3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c3, 0xf0f001ff, 0x00000000 },
3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c4, 0xf0f001ff, 0x00000000 },
3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c5, 0xf0f001ff, 0x00000000 },
3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c6, 0xf0f001ff, 0x00000000 },
3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c7, 0xf0f001ff, 0x00000000 },
3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c8, 0xf0f001ff, 0x00000000 },
3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000){ GC_HWIP, 0, 1, 0x39c9, 0xf0f001ff, 0x00000000 },
3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000){ GC_HWIP, 0, 0, 0x1588, 0xffbfffff, 0x00a00000 }
3385};
3386
3387static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000){ GC_HWIP, 0, 1, 0x2200, 0xffffffff, 0xe0000000 },
3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e){ GC_HWIP, 0, 0, 0x0fe8, 0x3fffffff, 0x0000493e },
3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100){ GC_HWIP, 0, 1, 0x50b1, 0xfcff8fff, 0xf8000100 },
3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100){ GC_HWIP, 0, 1, 0x5080, 0xff7f0fff, 0x3c000100 },
3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000){ GC_HWIP, 0, 0, 0x1423, 0xa0000000, 0xa0000000 },
3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014){ GC_HWIP, 0, 0, 0x1422, 0x00008000, 0x003c8014 },
3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017){ GC_HWIP, 0, 1, 0x2d84, 0x00000010, 0x00000017 },
3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8){ GC_HWIP, 0, 1, 0x2d90, 0xffffffff, 0xd8d8d8d8 },
3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003){ GC_HWIP, 0, 1, 0x2d94, 0x00000003, 0x00000003 },
3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff){ GC_HWIP, 0, 0, 0x1f57, 0x800007ff, 0x000005ff },
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000){ GC_HWIP, 0, 0, 0x13ac, 0xffffffff, 0x20000000 },
3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000200 },
3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x04800000 },
3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210){ GC_HWIP, 0, 0, 0x13ba, 0xffffffff, 0x03860210 },
3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044){ GC_HWIP, 0, 0, 0x13de, 0x0c1800ff, 0x00000044 },
3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500){ GC_HWIP, 0, 0, 0x1583, 0x00009d00, 0x00008500 },
3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff){ GC_HWIP, 0, 0, 0x1712, 0xffffffff, 0x000fffff },
3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017){ GC_HWIP, 0, 1, 0x2d04, 0x00000010, 0x00000017 },
3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8){ GC_HWIP, 0, 1, 0x2d10, 0xfcfcfcfc, 0xd8d8d8d8 },
3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130){ GC_HWIP, 0, 1, 0x2e25, 0x77707770, 0x21302130 },
3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130){ GC_HWIP, 0, 1, 0x2e26, 0x77707770, 0x21302130 },
3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffcf },
3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffcf },
3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100){ GC_HWIP, 0, 1, 0x50ac, 0x10000000, 0x10000100 },
3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f){ GC_HWIP, 0, 1, 0x2e01, 0xfc02002f, 0x9402002f },
3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188){ GC_HWIP, 0, 1, 0x2e0c, 0x00002188, 0x00000188 },
3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009){ GC_HWIP, 0, 0, 0x109c, 0x08000009, 0x08000009 },
3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02){ GC_HWIP, 0, 0, 0x106c, 0xcc3fcc03, 0x842a4c02 },
3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000){ GC_HWIP, 0, 1, 0x2281, 0x0000000f, 0x00000000 },
3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101){ GC_HWIP, 0, 0, 0x153f, 0xffff3109, 0xffff3101 },
3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130){ GC_HWIP, 0, 0, 0x10ac, 0x00000100, 0x00000130 },
3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x5090, 0xffffffff, 0xffffffff },
3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0x00030008, 0x01030000 },
3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000){ GC_HWIP, 0, 0, 0x1588, 0x00800000, 0x00800000 }
3422};
3423
3424static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425{
3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0xff7f0fff, 0x78000100 },
3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044){ GC_HWIP, 0, 1, 0x2d90, 0x000000ff, 0x00000044 },
3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c200 },
3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042){ GC_HWIP, 0, 0, 0x13de, 0x0c1807ff, 0x00000042 },
3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044){ GC_HWIP, 0, 1, 0x2d10, 0x000000ff, 0x00000044 },
3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x32103210 },
3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x32103210 },
3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xfffffff3 },
3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xfffffff3 },
3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x000001ff, 0x00000020 },
3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf17fffff, 0x01200007 },
3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000){ GC_HWIP, 0, 0, 0x10ba, 0x000017ff, 0x00001000 },
3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020){ GC_HWIP, 0, 0, 0x11b8, 0xffffff7f, 0x00010020 },
3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000){ GC_HWIP, 0, 0, 0x1588, 0xffffffff, 0x00100000 }
3448};
3449
3450static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100){ GC_HWIP, 0, 1, 0x507c, 0xff7f0fff, 0x78000100 },
3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4){ GC_HWIP, 0, 1, 0x2d90, 0x000000ff, 0x000000e4 },
3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200){ GC_HWIP, 0, 0, 0x1f53, 0x0007ffff, 0x0000c200 },
3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280){ GC_HWIP, 0, 0, 0x13ae, 0xffffffff, 0x00000280 },
3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000){ GC_HWIP, 0, 0, 0x13af, 0xffffffff, 0x00800000 },
3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041){ GC_HWIP, 0, 0, 0x13de, 0x0c1807ff, 0x00000041 },
3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500){ GC_HWIP, 0, 0, 0x1580, 0x1ff1ffff, 0x00000500 },
3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4){ GC_HWIP, 0, 1, 0x2d10, 0x000000ff, 0x000000e4 },
3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e25, 0x77777777, 0x32103210 },
3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210){ GC_HWIP, 0, 1, 0x2e26, 0x77777777, 0x32103210 },
3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x2e21, 0xffffffff, 0xffffffff },
3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff){ GC_HWIP, 0, 1, 0x2e03, 0xffffffff, 0xffffffff },
3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008){ GC_HWIP, 0, 1, 0x2e08, 0xff8fff0f, 0x580f1008 },
3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988){ GC_HWIP, 0, 1, 0x2e0c, 0xf7ffffff, 0x00f80988 },
3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020){ GC_HWIP, 0, 0, 0x10a2, 0x000001ff, 0x00000020 },
3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007){ GC_HWIP, 0, 0, 0x1025, 0xf000003f, 0x01200007 },
3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800){ GC_HWIP, 0, 0, 0x1070, 0xffffffff, 0x00000800 },
3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820){ GC_HWIP, 0, 0, 0x107c, 0xffffffbf, 0x00000820 },
3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000){ GC_HWIP, 0, 0, 0x10ba, 0x000017ff, 0x00001000 },
3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020){ GC_HWIP, 0, 0, 0x11b8, 0xffffff7f, 0x00010020 },
3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000){ GC_HWIP, 0, 0, 0x12e2, 0xfff7ffff, 0x01030000 },
3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000){ GC_HWIP, 0, 0, 0x1588, 0xffffffff, 0x00100000 }
3473};
3474
3475#define DEFAULT_SH_MEM_CONFIG((SH_MEM_ADDRESS_MODE_64 << 0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED
<< 0x2) | (SH_MEM_RETRY_MODE_ALL << 0xc) | (3 <<
0xe)) \
3476 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT0x0) | \
3477 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT0x2) | \
3478 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT0xc) | \
3479 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT0xe))
3480
3481/* TODO: pending on golden setting value of gb address config */
3482#define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN0x00100044 0x00100044
3483
3484static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490 struct amdgpu_cu_info *cu_info);
3491static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493 u32 sh_num, u32 instance);
3494static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495
3496static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool_Bool resume);
3501static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool_Bool resume);
3502static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool_Bool start, bool_Bool secure);
3503static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507 uint16_t pasid, uint32_t flush_type,
3508 bool_Bool all_hub, uint8_t dst_sel);
3509
3510static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511{
3512 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)((3 << 30) | (((0xA0) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
3513 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0)((0) << 0) |
3514 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)((0) << 29)); /* vmid_mask:0 queue_type:0 (KIQ) */
3515 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)((u32)(queue_mask))); /* queue mask lo */
3516 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)((u32)(((queue_mask) >> 16) >> 16))); /* queue mask hi */
3517 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3518 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3519 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3520 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3521}
3522
3523static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524 struct amdgpu_ring *ring)
3525{
3526 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527 uint64_t wptr_addr = ring->wptr_gpu_addr;
3528 uint32_t eng_sel = 0;
3529
3530 switch (ring->funcs->type) {
3531 case AMDGPU_RING_TYPE_COMPUTE:
3532 eng_sel = 0;
3533 break;
3534 case AMDGPU_RING_TYPE_GFX:
3535 eng_sel = 4;
3536 break;
3537 case AMDGPU_RING_TYPE_MES:
3538 eng_sel = 5;
3539 break;
3540 default:
3541 WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "1", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 3541
); __builtin_expect(!!(__ret), 0); });
3542 }
3543
3544 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)((3 << 30) | (((0xA2) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
3545 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547 PACKET3_MAP_QUEUES_QUEUE_SEL(0)((0) << 4) | /* Queue_Sel */
3548 PACKET3_MAP_QUEUES_VMID(0)((0) << 8) | /* VMID */
3549 PACKET3_MAP_QUEUES_QUEUE(ring->queue)((ring->queue) << 13) |
3550 PACKET3_MAP_QUEUES_PIPE(ring->pipe)((ring->pipe) << 16) |
3551 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1))(((ring->me == 1 ? 0 : 1)) << 18) |
3552 PACKET3_MAP_QUEUES_QUEUE_TYPE(0)((0) << 21) | /*queue_type: normal compute queue */
3553 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0)((0) << 24) | /* alloc format: all_on_one_pipe */
3554 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) |
3555 PACKET3_MAP_QUEUES_NUM_QUEUES(1)((1) << 29)); /* num_queues: must be 1 */
3556 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2));
3557 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)((u32)(mqd_addr)));
3558 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)((u32)(((mqd_addr) >> 16) >> 16)));
3559 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)((u32)(wptr_addr)));
3560 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)((u32)(((wptr_addr) >> 16) >> 16)));
3561}
3562
3563static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564 struct amdgpu_ring *ring,
3565 enum amdgpu_unmap_queues_action action,
3566 u64 gpu_addr, u64 seq)
3567{
3568 struct amdgpu_device *adev = kiq_ring->adev;
3569 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570
3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573 return;
3574 }
3575
3576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)((3 << 30) | (((0xA3) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
3577 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578 PACKET3_UNMAP_QUEUES_ACTION(action)((action) << 0) |
3579 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0)((0) << 4) |
3580 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel)((eng_sel) << 26) |
3581 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)((1) << 29));
3582 amdgpu_ring_write(kiq_ring,
3583 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)((ring->doorbell_index) << 2));
3584
3585 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)((u32)(gpu_addr)));
3587 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)));
3588 amdgpu_ring_write(kiq_ring, seq);
3589 } else {
3590 amdgpu_ring_write(kiq_ring, 0);
3591 amdgpu_ring_write(kiq_ring, 0);
3592 amdgpu_ring_write(kiq_ring, 0);
3593 }
3594}
3595
3596static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597 struct amdgpu_ring *ring,
3598 u64 addr,
3599 u64 seq)
3600{
3601 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602
3603 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)((3 << 30) | (((0xA4) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
3604 amdgpu_ring_write(kiq_ring,
3605 PACKET3_QUERY_STATUS_CONTEXT_ID(0)((0) << 0) |
3606 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0)((0) << 28) |
3607 PACKET3_QUERY_STATUS_COMMAND(2)((2) << 30));
3608 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index)((ring->doorbell_index) << 2) |
3610 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)((eng_sel) << 25));
3611 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)((u32)(addr)));
3612 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
3613 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)((u32)(seq)));
3614 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
3615}
3616
3617static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618 uint16_t pasid, uint32_t flush_type,
3619 bool_Bool all_hub)
3620{
3621 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622}
3623
3624static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625 .kiq_set_resources = gfx10_kiq_set_resources,
3626 .kiq_map_queues = gfx10_kiq_map_queues,
3627 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628 .kiq_query_status = gfx10_kiq_query_status,
3629 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630 .set_resources_size = 8,
3631 .map_queues_size = 7,
3632 .unmap_queues_size = 6,
3633 .query_status_size = 7,
3634 .invalidate_tlbs_size = 2,
3635};
3636
3637static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638{
3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640}
3641
3642static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643{
3644 switch (adev->ip_versions[GC_HWIP][0]) {
3645 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
3646 soc15_program_register_sequence(adev,
3647 golden_settings_gc_rlc_spm_10_0_nv10,
3648 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)(sizeof((golden_settings_gc_rlc_spm_10_0_nv10)) / sizeof((golden_settings_gc_rlc_spm_10_0_nv10
)[0])));
3649 break;
3650 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
3651 soc15_program_register_sequence(adev,
3652 golden_settings_gc_rlc_spm_10_1_nv14,
3653 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)(sizeof((golden_settings_gc_rlc_spm_10_1_nv14)) / sizeof((golden_settings_gc_rlc_spm_10_1_nv14
)[0])));
3654 break;
3655 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
3656 soc15_program_register_sequence(adev,
3657 golden_settings_gc_rlc_spm_10_1_2_nv12,
3658 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)(sizeof((golden_settings_gc_rlc_spm_10_1_2_nv12)) / sizeof((golden_settings_gc_rlc_spm_10_1_2_nv12
)[0])));
3659 break;
3660 default:
3661 break;
3662 }
3663}
3664
3665static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666{
3667 switch (adev->ip_versions[GC_HWIP][0]) {
3668 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
3669 soc15_program_register_sequence(adev,
3670 golden_settings_gc_10_1,
3671 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)(sizeof((golden_settings_gc_10_1)) / sizeof((golden_settings_gc_10_1
)[0])));
3672 soc15_program_register_sequence(adev,
3673 golden_settings_gc_10_0_nv10,
3674 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)(sizeof((golden_settings_gc_10_0_nv10)) / sizeof((golden_settings_gc_10_0_nv10
)[0])));
3675 break;
3676 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
3677 soc15_program_register_sequence(adev,
3678 golden_settings_gc_10_1_1,
3679 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)(sizeof((golden_settings_gc_10_1_1)) / sizeof((golden_settings_gc_10_1_1
)[0])));
3680 soc15_program_register_sequence(adev,
3681 golden_settings_gc_10_1_nv14,
3682 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)(sizeof((golden_settings_gc_10_1_nv14)) / sizeof((golden_settings_gc_10_1_nv14
)[0])));
3683 break;
3684 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
3685 soc15_program_register_sequence(adev,
3686 golden_settings_gc_10_1_2,
3687 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)(sizeof((golden_settings_gc_10_1_2)) / sizeof((golden_settings_gc_10_1_2
)[0])));
3688 soc15_program_register_sequence(adev,
3689 golden_settings_gc_10_1_2_nv12,
3690 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)(sizeof((golden_settings_gc_10_1_2_nv12)) / sizeof((golden_settings_gc_10_1_2_nv12
)[0])));
3691 break;
3692 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
3693 soc15_program_register_sequence(adev,
3694 golden_settings_gc_10_3,
3695 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)(sizeof((golden_settings_gc_10_3)) / sizeof((golden_settings_gc_10_3
)[0])));
3696 soc15_program_register_sequence(adev,
3697 golden_settings_gc_10_3_sienna_cichlid,
3698 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)(sizeof((golden_settings_gc_10_3_sienna_cichlid)) / sizeof((golden_settings_gc_10_3_sienna_cichlid
)[0])));
3699 break;
3700 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
3701 soc15_program_register_sequence(adev,
3702 golden_settings_gc_10_3_2,
3703 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)(sizeof((golden_settings_gc_10_3_2)) / sizeof((golden_settings_gc_10_3_2
)[0])));
3704 break;
3705 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
3706 soc15_program_register_sequence(adev,
3707 golden_settings_gc_10_3_vangogh,
3708 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)(sizeof((golden_settings_gc_10_3_vangogh)) / sizeof((golden_settings_gc_10_3_vangogh
)[0])));
3709 break;
3710 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
3711 soc15_program_register_sequence(adev,
3712 golden_settings_gc_10_3_3,
3713 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)(sizeof((golden_settings_gc_10_3_3)) / sizeof((golden_settings_gc_10_3_3
)[0])));
3714 break;
3715 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
3716 soc15_program_register_sequence(adev,
3717 golden_settings_gc_10_3_4,
3718 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)(sizeof((golden_settings_gc_10_3_4)) / sizeof((golden_settings_gc_10_3_4
)[0])));
3719 break;
3720 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
3721 soc15_program_register_sequence(adev,
3722 golden_settings_gc_10_3_5,
3723 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)(sizeof((golden_settings_gc_10_3_5)) / sizeof((golden_settings_gc_10_3_5
)[0])));
3724 break;
3725 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
3726 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
3727 soc15_program_register_sequence(adev,
3728 golden_settings_gc_10_0_cyan_skillfish,
3729 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)(sizeof((golden_settings_gc_10_0_cyan_skillfish)) / sizeof((golden_settings_gc_10_0_cyan_skillfish
)[0])));
3730 break;
3731 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
3732 soc15_program_register_sequence(adev,
3733 golden_settings_gc_10_3_6,
3734 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)(sizeof((golden_settings_gc_10_3_6)) / sizeof((golden_settings_gc_10_3_6
)[0])));
3735 break;
3736 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
3737 soc15_program_register_sequence(adev,
3738 golden_settings_gc_10_3_7,
3739 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)(sizeof((golden_settings_gc_10_3_7)) / sizeof((golden_settings_gc_10_3_7
)[0])));
3740 break;
3741 default:
3742 break;
3743 }
3744 gfx_v10_0_init_spm_golden_registers(adev);
3745}
3746
3747static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748 bool_Bool wc, uint32_t reg, uint32_t val)
3749{
3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
3751 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel)((eng_sel) << 30) |
3752 WRITE_DATA_DST_SEL(0)((0) << 8) | (wc ? WR_CONFIRM(1 << 20) : 0));
3753 amdgpu_ring_write(ring, reg);
3754 amdgpu_ring_write(ring, 0);
3755 amdgpu_ring_write(ring, val);
3756}
3757
3758static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759 int mem_space, int opt, uint32_t addr0,
3760 uint32_t addr1, uint32_t ref, uint32_t mask,
3761 uint32_t inv)
3762{
3763 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)((3 << 30) | (((0x3C) & 0xFF) << 8) | ((5) &
0x3FFF) << 16));
3764 amdgpu_ring_write(ring,
3765 /* memory (1) or register (0) */
3766 (WAIT_REG_MEM_MEM_SPACE(mem_space)((mem_space) << 4) |
3767 WAIT_REG_MEM_OPERATION(opt)((opt) << 6) | /* wait */
3768 WAIT_REG_MEM_FUNCTION(3)((3) << 0) | /* equal */
3769 WAIT_REG_MEM_ENGINE(eng_sel)((eng_sel) << 8)));
3770
3771 if (mem_space)
3772 BUG_ON(addr0 & 0x3)((!(addr0 & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 3772, "!(addr0 & 0x3)")); /* Dword align */
3773 amdgpu_ring_write(ring, addr0);
3774 amdgpu_ring_write(ring, addr1);
3775 amdgpu_ring_write(ring, ref);
3776 amdgpu_ring_write(ring, mask);
3777 amdgpu_ring_write(ring, inv); /* poll interval */
3778}
3779
3780static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781{
3782 struct amdgpu_device *adev = ring->adev;
3783 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0)(adev->reg_offset[GC_HWIP][0][1] + 0x2040);
3784 uint32_t tmp = 0;
3785 unsigned i;
3786 int r;
3787
3788 WREG32(scratch, 0xCAFEDEAD)amdgpu_device_wreg(adev, (scratch), (0xCAFEDEAD), 0);
3789 r = amdgpu_ring_alloc(ring, 3);
3790 if (r) {
3791 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",__drm_err("amdgpu: cp failed to lock ring %d (%d).\n", ring->
idx, r)
3792 ring->idx, r)__drm_err("amdgpu: cp failed to lock ring %d (%d).\n", ring->
idx, r);
3793 return r;
3794 }
3795
3796 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)((3 << 30) | (((0x79) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
3797 amdgpu_ring_write(ring, scratch -
3798 PACKET3_SET_UCONFIG_REG_START0x0000c000);
3799 amdgpu_ring_write(ring, 0xDEADBEEF);
3800 amdgpu_ring_commit(ring);
3801
3802 for (i = 0; i < adev->usec_timeout; i++) {
3803 tmp = RREG32(scratch)amdgpu_device_rreg(adev, (scratch), 0);
3804 if (tmp == 0xDEADBEEF)
3805 break;
3806 if (amdgpu_emu_mode == 1)
3807 drm_msleep(1)mdelay(1);
3808 else
3809 udelay(1);
3810 }
3811
3812 if (i >= adev->usec_timeout)
3813 r = -ETIMEDOUT60;
3814
3815 return r;
3816}
3817
3818static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3819{
3820 struct amdgpu_device *adev = ring->adev;
3821 struct amdgpu_ib ib;
3822 struct dma_fence *f = NULL((void *)0);
3823 unsigned index;
3824 uint64_t gpu_addr;
3825 volatile uint32_t *cpu_ptr;
3826 long r;
3827
3828 memset(&ib, 0, sizeof(ib))__builtin_memset((&ib), (0), (sizeof(ib)));
3829
3830 if (ring->is_mes_queue) {
3831 uint32_t padding, offset;
3832
3833 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3834 padding = amdgpu_mes_ctx_get_offs(ring,
3835 AMDGPU_MES_CTX_PADDING_OFFS);
3836
3837 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
3838 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : (
(void *)0));
3839
3840 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + padding) : 0);
3841 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + padding) :
((void *)0));
3842 *cpu_ptr = cpu_to_le32(0xCAFEDEAD)((__uint32_t)(0xCAFEDEAD));
3843 } else {
3844 r = amdgpu_device_wb_get(adev, &index);
3845 if (r)
3846 return r;
3847
3848 gpu_addr = adev->wb.gpu_addr + (index * 4);
3849 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD)((__uint32_t)(0xCAFEDEAD));
3850 cpu_ptr = &adev->wb.wb[index];
3851
3852 r = amdgpu_ib_get(adev, NULL((void *)0), 20, AMDGPU_IB_POOL_DIRECT, &ib);
3853 if (r) {
3854 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r)__drm_err("amdgpu: failed to get ib (%ld).\n", r);
3855 goto err1;
3856 }
3857 }
3858
3859 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16);
3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20);
3861 ib.ptr[2] = lower_32_bits(gpu_addr)((u32)(gpu_addr));
3862 ib.ptr[3] = upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16));
3863 ib.ptr[4] = 0xDEADBEEF;
3864 ib.length_dw = 5;
3865
3866 r = amdgpu_ib_schedule(ring, 1, &ib, NULL((void *)0), &f);
3867 if (r)
3868 goto err2;
3869
3870 r = dma_fence_wait_timeout(f, false0, timeout);
3871 if (r == 0) {
3872 r = -ETIMEDOUT60;
3873 goto err2;
3874 } else if (r < 0) {
3875 goto err2;
3876 }
3877
3878 if (le32_to_cpu(*cpu_ptr)((__uint32_t)(*cpu_ptr)) == 0xDEADBEEF)
3879 r = 0;
3880 else
3881 r = -EINVAL22;
3882err2:
3883 if (!ring->is_mes_queue)
3884 amdgpu_ib_free(adev, &ib, NULL((void *)0));
3885 dma_fence_put(f);
3886err1:
3887 if (!ring->is_mes_queue)
3888 amdgpu_device_wb_free(adev, index);
3889 return r;
3890}
3891
3892static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3893{
3894 release_firmware(adev->gfx.pfp_fw);
3895 adev->gfx.pfp_fw = NULL((void *)0);
3896 release_firmware(adev->gfx.me_fw);
3897 adev->gfx.me_fw = NULL((void *)0);
3898 release_firmware(adev->gfx.ce_fw);
3899 adev->gfx.ce_fw = NULL((void *)0);
3900 release_firmware(adev->gfx.rlc_fw);
3901 adev->gfx.rlc_fw = NULL((void *)0);
3902 release_firmware(adev->gfx.mec_fw);
3903 adev->gfx.mec_fw = NULL((void *)0);
3904 release_firmware(adev->gfx.mec2_fw);
3905 adev->gfx.mec2_fw = NULL((void *)0);
3906
3907 kfree(adev->gfx.rlc.register_list_format);
3908}
3909
3910static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3911{
3912 adev->gfx.cp_fw_write_wait = false0;
3913
3914 switch (adev->ip_versions[GC_HWIP][0]) {
3915 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
3916 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
3917 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
3918 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
3919 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
3920 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3921 (adev->gfx.me_feature_version >= 27) &&
3922 (adev->gfx.pfp_fw_version >= 0x00000068) &&
3923 (adev->gfx.pfp_feature_version >= 27) &&
3924 (adev->gfx.mec_fw_version >= 0x0000005b) &&
3925 (adev->gfx.mec_feature_version >= 27))
3926 adev->gfx.cp_fw_write_wait = true1;
3927 break;
3928 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
3929 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
3930 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
3931 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
3932 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
3933 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
3934 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
3935 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
3936 adev->gfx.cp_fw_write_wait = true1;
3937 break;
3938 default:
3939 break;
3940 }
3941
3942 if (!adev->gfx.cp_fw_write_wait)
3943 DRM_WARN_ONCE("CP firmware version too old, please update!")({ static int __warned; if (!__warned) { printk("\0014" "[" "drm"
"] " "CP firmware version too old, please update!"); __warned
= 1; } });
3944}
3945
3946static bool_Bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3947{
3948 bool_Bool ret = false0;
3949
3950 switch (adev->pdev->revision) {
3951 case 0xc2:
3952 case 0xc3:
3953 ret = true1;
3954 break;
3955 default:
3956 ret = false0;
3957 break;
3958 }
3959
3960 return ret ;
3961}
3962
3963static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3964{
3965 switch (adev->ip_versions[GC_HWIP][0]) {
3966 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
3967 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3968 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3969 break;
3970 default:
3971 break;
3972 }
3973}
3974
3975static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3976{
3977 const char *chip_name;
3978 char fw_name[40];
3979 char *wks = "";
3980 int err;
3981 const struct rlc_firmware_header_v2_0 *rlc_hdr;
3982 uint16_t version_major;
3983 uint16_t version_minor;
3984
3985 DRM_DEBUG("\n")___drm_dbg(((void *)0), DRM_UT_CORE, "\n");
3986
3987 switch (adev->ip_versions[GC_HWIP][0]) {
3988 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
3989 chip_name = "navi10";
3990 break;
3991 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
3992 chip_name = "navi14";
3993 if (!(adev->pdev->device == 0x7340 &&
3994 adev->pdev->revision != 0x00))
3995 wks = "_wks";
3996 break;
3997 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
3998 chip_name = "navi12";
3999 break;
4000 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
4001 chip_name = "sienna_cichlid";
4002 break;
4003 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
4004 chip_name = "navy_flounder";
4005 break;
4006 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
4007 chip_name = "vangogh";
4008 break;
4009 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
4010 chip_name = "dimgrey_cavefish";
4011 break;
4012 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
4013 chip_name = "beige_goby";
4014 break;
4015 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
4016 chip_name = "yellow_carp";
4017 break;
4018 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
4019 chip_name = "gc_10_3_6";
4020 break;
4021 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
4022 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
4023 chip_name = "cyan_skillfish2";
4024 break;
4025 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
4026 chip_name = "gc_10_3_7";
4027 break;
4028 default:
4029 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4029); } while (0);
4030 }
4031
4032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4033 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4034 if (err)
4035 goto out;
4036 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4037 if (err)
4038 goto out;
4039 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4040
4041 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4042 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4043 if (err)
4044 goto out;
4045 err = amdgpu_ucode_validate(adev->gfx.me_fw);
4046 if (err)
4047 goto out;
4048 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4049
4050 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4051 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4052 if (err)
4053 goto out;
4054 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4055 if (err)
4056 goto out;
4057 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4058
4059 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
4060 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4061 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4062 if (err)
4063 goto out;
4064 /* don't check this. There are apparently firmwares in the wild with
4065 * incorrect size in the header
4066 */
4067 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4068 if (err)
4069 dev_dbg(adev->dev,do { } while(0)
4070 "gfx10: amdgpu_ucode_validate() failed \"%s\"\n",do { } while(0)
4071 fw_name)do { } while(0);
4072 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4073 version_major = le16_to_cpu(rlc_hdr->header.header_version_major)((__uint16_t)(rlc_hdr->header.header_version_major));
4074 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor)((__uint16_t)(rlc_hdr->header.header_version_minor));
4075 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4076 if (err)
4077 goto out;
4078 }
4079
4080 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4081 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4082 if (err)
4083 goto out;
4084 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4085 if (err)
4086 goto out;
4087 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4088 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4089
4090 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4091 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4092 if (!err) {
4093 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4094 if (err)
4095 goto out;
4096 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4097 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4098 } else {
4099 err = 0;
4100 adev->gfx.mec2_fw = NULL((void *)0);
4101 }
4102
4103 gfx_v10_0_check_fw_write_wait(adev);
4104out:
4105 if (err) {
4106 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "gfx10: Failed to init firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
4107 "gfx10: Failed to init firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "gfx10: Failed to init firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
)
4108 fw_name)printf("drm:pid%d:%s *ERROR* " "gfx10: Failed to init firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name
);
4109 release_firmware(adev->gfx.pfp_fw);
4110 adev->gfx.pfp_fw = NULL((void *)0);
4111 release_firmware(adev->gfx.me_fw);
4112 adev->gfx.me_fw = NULL((void *)0);
4113 release_firmware(adev->gfx.ce_fw);
4114 adev->gfx.ce_fw = NULL((void *)0);
4115 release_firmware(adev->gfx.rlc_fw);
4116 adev->gfx.rlc_fw = NULL((void *)0);
4117 release_firmware(adev->gfx.mec_fw);
4118 adev->gfx.mec_fw = NULL((void *)0);
4119 release_firmware(adev->gfx.mec2_fw);
4120 adev->gfx.mec2_fw = NULL((void *)0);
4121 }
4122
4123 gfx_v10_0_check_gfxoff_flag(adev);
4124
4125 return err;
4126}
4127
4128static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4129{
4130 u32 count = 0;
4131 const struct cs_section_def *sect = NULL((void *)0);
4132 const struct cs_extent_def *ext = NULL((void *)0);
4133
4134 /* begin clear state */
4135 count += 2;
4136 /* context control state */
4137 count += 3;
4138
4139 for (sect = gfx10_cs_data; sect->section != NULL((void *)0); ++sect) {
4140 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
4141 if (sect->id == SECT_CONTEXT)
4142 count += 2 + ext->reg_count;
4143 else
4144 return 0;
4145 }
4146 }
4147
4148 /* set PA_SC_TILE_STEERING_OVERRIDE */
4149 count += 3;
4150 /* end clear state */
4151 count += 2;
4152 /* clear state */
4153 count += 2;
4154
4155 return count;
4156}
4157
4158static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4159 volatile u32 *buffer)
4160{
4161 u32 count = 0, i;
4162 const struct cs_section_def *sect = NULL((void *)0);
4163 const struct cs_extent_def *ext = NULL((void *)0);
4164 int ctx_reg_offset;
4165
4166 if (adev->gfx.rlc.cs_data == NULL((void *)0))
4167 return;
4168 if (buffer == NULL((void *)0))
4169 return;
4170
4171 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
4172 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE)((__uint32_t)((2 << 28)));
4173
4174 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1))((__uint32_t)(((3 << 30) | (((0x28) & 0xFF) <<
8) | ((1) & 0x3FFF) << 16)));
4175 buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000));
4176 buffer[count++] = cpu_to_le32(0x80000000)((__uint32_t)(0x80000000));
4177
4178 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL((void *)0); ++sect) {
4179 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
4180 if (sect->id == SECT_CONTEXT) {
4181 buffer[count++] =
4182 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) <<
8) | ((ext->reg_count) & 0x3FFF) << 16)));
4183 buffer[count++] = cpu_to_le32(ext->reg_index -((__uint32_t)(ext->reg_index - 0x0000a000))
4184 PACKET3_SET_CONTEXT_REG_START)((__uint32_t)(ext->reg_index - 0x0000a000));
4185 for (i = 0; i < ext->reg_count; i++)
4186 buffer[count++] = cpu_to_le32(ext->extent[i])((__uint32_t)(ext->extent[i]));
4187 } else {
4188 return;
4189 }
4190 }
4191 }
4192
4193 ctx_reg_offset =
4194 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE)(adev->reg_offset[GC_HWIP][0][1] + 0x00d7) - PACKET3_SET_CONTEXT_REG_START0x0000a000;
4195 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1))((__uint32_t)(((3 << 30) | (((0x69) & 0xFF) <<
8) | ((1) & 0x3FFF) << 16)));
4196 buffer[count++] = cpu_to_le32(ctx_reg_offset)((__uint32_t)(ctx_reg_offset));
4197 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override)((__uint32_t)(adev->gfx.config.pa_sc_tile_steering_override
));
4198
4199 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))((__uint32_t)(((3 << 30) | (((0x4A) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
4200 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE)((__uint32_t)((3 << 28)));
4201
4202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0))((__uint32_t)(((3 << 30) | (((0x12) & 0xFF) <<
8) | ((0) & 0x3FFF) << 16)));
4203 buffer[count++] = cpu_to_le32(0)((__uint32_t)(0));
4204}
4205
4206static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4207{
4208 /* clear state block */
4209 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4210 &adev->gfx.rlc.clear_state_gpu_addr,
4211 (void **)&adev->gfx.rlc.cs_ptr);
4212
4213 /* jump table block */
4214 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4215 &adev->gfx.rlc.cp_table_gpu_addr,
4216 (void **)&adev->gfx.rlc.cp_table_ptr);
4217}
4218
4219static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4220{
4221 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4222
4223 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4224 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0)(adev->reg_offset[GC_HWIP][0][1] + 0x2040);
4225 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1)(adev->reg_offset[GC_HWIP][0][1] + 0x2041);
4226 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2)(adev->reg_offset[GC_HWIP][0][1] + 0x2042);
4227 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3)(adev->reg_offset[GC_HWIP][0][1] + 0x2043);
4228 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x0dc2);
4229 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX)(adev->reg_offset[GC_HWIP][0][1] + 0x2200);
4230 switch (adev->ip_versions[GC_HWIP][0]) {
4231 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
4232 reg_access_ctrl->spare_int =
4233 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][1] + 0x4ca5);
4234 break;
4235 default:
4236 reg_access_ctrl->spare_int =
4237 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT)(adev->reg_offset[GC_HWIP][0][1] + 0x4ccc);
4238 break;
4239 }
4240 adev->gfx.rlc.rlcg_reg_access_supported = true1;
4241}
4242
4243static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4244{
4245 const struct cs_section_def *cs_data;
4246 int r;
4247
4248 adev->gfx.rlc.cs_data = gfx10_cs_data;
4249
4250 cs_data = adev->gfx.rlc.cs_data;
4251
4252 if (cs_data) {
4253 /* init clear state block */
4254 r = amdgpu_gfx_rlc_init_csb(adev);
4255 if (r)
4256 return r;
4257 }
4258
4259 /* init spm vmid with 0xf */
4260 if (adev->gfx.rlc.funcs->update_spm_vmid)
4261 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4262
4263
4264 return 0;
4265}
4266
4267static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4268{
4269 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL((void *)0), NULL((void *)0));
4270 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL((void *)0), NULL((void *)0));
4271}
4272
4273static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4274{
4275 int r;
4276
4277 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES128);
4278
4279 amdgpu_gfx_graphics_queue_acquire(adev);
4280
4281 r = gfx_v10_0_init_microcode(adev);
4282 if (r)
4283 DRM_ERROR("Failed to load gfx firmware!\n")__drm_err("Failed to load gfx firmware!\n");
4284
4285 return r;
4286}
4287
4288static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4289{
4290 int r;
4291 u32 *hpd;
4292 const __le32 *fw_data = NULL((void *)0);
4293 unsigned fw_size;
4294 u32 *fw = NULL((void *)0);
4295 size_t mec_hpd_size;
4296
4297 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL((void *)0);
4298
4299 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES128);
4300
4301 /* take ownership of the relevant compute queues */
4302 amdgpu_gfx_compute_queue_acquire(adev);
4303 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE2048;
4304
4305 if (mec_hpd_size) {
4306 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE(1 << 12),
4307 AMDGPU_GEM_DOMAIN_GTT0x2,
4308 &adev->gfx.mec.hpd_eop_obj,
4309 &adev->gfx.mec.hpd_eop_gpu_addr,
4310 (void **)&hpd);
4311 if (r) {
4312 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r)printf("drm:pid%d:%s *WARNING* " "(%d) create HDP EOP bo failed\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
4313 gfx_v10_0_mec_fini(adev);
4314 return r;
4315 }
4316
4317 memset(hpd, 0, mec_hpd_size)__builtin_memset((hpd), (0), (mec_hpd_size));
4318
4319 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4320 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4321 }
4322
4323 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4324 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4325
4326 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4327 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes)));
4328 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes)((__uint32_t)(mec_hdr->header.ucode_size_bytes));
4329
4330 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4331 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
4332 &adev->gfx.mec.mec_fw_obj,
4333 &adev->gfx.mec.mec_fw_gpu_addr,
4334 (void **)&fw);
4335 if (r) {
4336 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create mec fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
4337 gfx_v10_0_mec_fini(adev);
4338 return r;
4339 }
4340
4341 memcpy(fw, fw_data, fw_size)__builtin_memcpy((fw), (fw_data), (fw_size));
4342
4343 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4344 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4345 }
4346
4347 return 0;
4348}
4349
4350static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4351{
4352 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (address << 0x10), 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1118)), ((wave << 0x0) | (address << 0x10
)), 0))
4353 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (address << 0x10), 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1118)), ((wave << 0x0) | (address << 0x10
)), 0))
4354 (address << SQ_IND_INDEX__INDEX__SHIFT))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (address << 0x10), 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1118)), ((wave << 0x0) | (address << 0x10
)), 0));
4355 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1119, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1119), 0));
4356}
4357
4358static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4359 uint32_t thread, uint32_t regno,
4360 uint32_t num, uint32_t *out)
4361{
4362 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1118)), ((wave
<< 0x0) | (regno << 0x10) | (thread << 0x5
) | (0x00000800L)), 0))
4363 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1118)), ((wave
<< 0x0) | (regno << 0x10) | (thread << 0x5
) | (0x00000800L)), 0))
4364 (regno << SQ_IND_INDEX__INDEX__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1118)), ((wave
<< 0x0) | (regno << 0x10) | (thread << 0x5
) | (0x00000800L)), 0))
4365 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1118)), ((wave
<< 0x0) | (regno << 0x10) | (thread << 0x5
) | (0x00000800L)), 0))
4366 (SQ_IND_INDEX__AUTO_INCR_MASK))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1118), (wave << 0x0) | (regno << 0x10) | (
thread << 0x5) | (0x00000800L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1118)), ((wave
<< 0x0) | (regno << 0x10) | (thread << 0x5
) | (0x00000800L)), 0));
4367 while (num--)
4368 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1119, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1119), 0));
4369}
4370
4371static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4372{
4373 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4374 * field when performing a select_se_sh so it should be
4375 * zero here */
4376 WARN_ON(simd != 0)({ int __ret = !!(simd != 0); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "simd != 0", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4376); __builtin_expect(!!(__ret), 0); });
4377
4378 /* type 2 wave data */
4379 dst[(*no_fields)++] = 2;
4380 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS0x0102);
4381 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO0x0108);
4382 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI0x0109);
4383 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO0x027e);
4384 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI0x027f);
4385 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID10x0117);
4386 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID20x0118);
4387 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW00x010a);
4388 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC0x0105);
4389 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC0x0106);
4390 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS0x0103);
4391 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS0x0107);
4392 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS20x011c);
4393 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG10x010d);
4394 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M00x027c);
4395 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE0x0101);
4396}
4397
4398static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4399 uint32_t wave, uint32_t start,
4400 uint32_t size, uint32_t *dst)
4401{
4402 WARN_ON(simd != 0)({ int __ret = !!(simd != 0); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "simd != 0", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4402); __builtin_expect(!!(__ret), 0); });
4403
4404 wave_read_regs(
4405 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET0x00000200, size,
4406 dst);
4407}
4408
4409static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4410 uint32_t wave, uint32_t thread,
4411 uint32_t start, uint32_t size,
4412 uint32_t *dst)
4413{
4414 wave_read_regs(
4415 adev, wave, thread,
4416 start + SQIND_WAVE_VGPRS_OFFSET0x00000400, size, dst);
4417}
4418
4419static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4420 u32 me, u32 pipe, u32 q, u32 vm)
4421{
4422 nv_grbm_select(adev, me, pipe, q, vm);
4423}
4424
4425static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4426 bool_Bool enable)
4427{
4428 uint32_t data, def;
4429
4430 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x3ce4, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x3ce4), 0));
4431
4432 if (enable)
4433 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK0x00000001L;
4434 else
4435 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK0x00000001L;
4436
4437 if (data != def)
4438 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x3ce4), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x3ce4)), (data), 0));
4439}
4440
4441static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4442 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4443 .select_se_sh = &gfx_v10_0_select_se_sh,
4444 .read_wave_data = &gfx_v10_0_read_wave_data,
4445 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4446 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4447 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4448 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4449 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4450};
4451
4452static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4453{
4454 u32 gb_addr_config;
4455
4456 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4457
4458 switch (adev->ip_versions[GC_HWIP][0]) {
4459 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
4460 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
4461 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
4462 adev->gfx.config.max_hw_contexts = 8;
4463 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4464 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4465 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4466 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4467 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x13de, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x13de), 0));
4468 break;
4469 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
4470 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
4471 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
4472 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
4473 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
4474 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
4475 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
4476 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
4477 adev->gfx.config.max_hw_contexts = 8;
4478 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4479 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4480 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4481 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4482 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x13de, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x13de), 0));
4483 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4484 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS)(((gb_addr_config) & 0x00000700L) >> 0x8);
4485 break;
4486 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
4487 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
4488 adev->gfx.config.max_hw_contexts = 8;
4489 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4490 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4491 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4492 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4493 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN0x00100044;
4494 break;
4495 default:
4496 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 4496); } while (0);
4497 break;
4498 }
4499
4500 adev->gfx.config.gb_addr_config = gb_addr_config;
4501
4502 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4503 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0)
4504 GB_ADDR_CONFIG, NUM_PIPES)(((adev->gfx.config.gb_addr_config) & 0x00000007L) >>
0x0);
4505
4506 adev->gfx.config.max_tile_pipes =
4507 adev->gfx.config.gb_addr_config_fields.num_pipes;
4508
4509 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4510 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6)
4511 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS)(((adev->gfx.config.gb_addr_config) & 0x000000C0L) >>
0x6);
4512 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4513 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a)
4514 GB_ADDR_CONFIG, NUM_RB_PER_SE)(((adev->gfx.config.gb_addr_config) & 0x0C000000L) >>
0x1a);
4515 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4516 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13)
4517 GB_ADDR_CONFIG, NUM_SHADER_ENGINES)(((adev->gfx.config.gb_addr_config) & 0x00180000L) >>
0x13);
4518 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4519 REG_GET_FIELD(adev->gfx.config.gb_addr_config,(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3)
4520 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)(((adev->gfx.config.gb_addr_config) & 0x00000038L) >>
0x3));
4521}
4522
4523static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4524 int me, int pipe, int queue)
4525{
4526 struct amdgpu_ring *ring;
4527 unsigned int irq_type;
4528 unsigned int hw_prio;
4529
4530 ring = &adev->gfx.gfx_ring[ring_id];
4531
4532 ring->me = me;
4533 ring->pipe = pipe;
4534 ring->queue = queue;
4535
4536 ring->ring_obj = NULL((void *)0);
4537 ring->use_doorbell = true1;
4538
4539 if (!ring_id)
4540 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4541 else
4542 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4543 snprintf(ring->name, sizeof(ring->name), "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4544
4545 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4546 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4547 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4548 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4549 hw_prio, NULL((void *)0));
4550}
4551
4552static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4553 int mec, int pipe, int queue)
4554{
4555 unsigned irq_type;
4556 struct amdgpu_ring *ring;
4557 unsigned int hw_prio;
4558
4559 ring = &adev->gfx.compute_ring[ring_id];
4560
4561 /* mec0 is me1 */
4562 ring->me = mec + 1;
4563 ring->pipe = pipe;
4564 ring->queue = queue;
4565
4566 ring->ring_obj = NULL((void *)0);
4567 ring->use_doorbell = true1;
4568 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4569 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4570 + (ring_id * GFX10_MEC_HPD_SIZE2048);
4571 snprintf(ring->name, sizeof(ring->name), "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4572
4573 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4574 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4575 + ring->pipe;
4576 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4577 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4578 /* type-2 packets are deprecated on MEC, use type-3 instead */
4579 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4580 hw_prio, NULL((void *)0));
4581}
4582
4583static int gfx_v10_0_sw_init(void *handle)
4584{
4585 int i, j, k, r, ring_id = 0;
4586 struct amdgpu_kiq *kiq;
4587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4588
4589 switch (adev->ip_versions[GC_HWIP][0]) {
4590 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
4591 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
4592 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
4593 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
4594 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
4595 adev->gfx.me.num_me = 1;
4596 adev->gfx.me.num_pipe_per_me = 1;
4597 adev->gfx.me.num_queue_per_pipe = 1;
4598 adev->gfx.mec.num_mec = 2;
4599 adev->gfx.mec.num_pipe_per_mec = 4;
4600 adev->gfx.mec.num_queue_per_pipe = 8;
4601 break;
4602 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
4603 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
4604 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
4605 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
4606 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
4607 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
4608 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
4609 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
4610 adev->gfx.me.num_me = 1;
4611 adev->gfx.me.num_pipe_per_me = 1;
4612 adev->gfx.me.num_queue_per_pipe = 1;
4613 adev->gfx.mec.num_mec = 2;
4614 adev->gfx.mec.num_pipe_per_mec = 4;
4615 adev->gfx.mec.num_queue_per_pipe = 4;
4616 break;
4617 default:
4618 adev->gfx.me.num_me = 1;
4619 adev->gfx.me.num_pipe_per_me = 1;
4620 adev->gfx.me.num_queue_per_pipe = 1;
4621 adev->gfx.mec.num_mec = 1;
4622 adev->gfx.mec.num_pipe_per_mec = 4;
4623 adev->gfx.mec.num_queue_per_pipe = 8;
4624 break;
4625 }
4626
4627 /* KIQ event */
4628 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4629 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT178,
4630 &adev->gfx.kiq.irq);
4631 if (r)
4632 return r;
4633
4634 /* EOP Event */
4635 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4636 GFX_10_1__SRCID__CP_EOP_INTERRUPT181,
4637 &adev->gfx.eop_irq);
4638 if (r)
4639 return r;
4640
4641 /* Privileged reg */
4642 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT184,
4643 &adev->gfx.priv_reg_irq);
4644 if (r)
4645 return r;
4646
4647 /* Privileged inst */
4648 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT185,
4649 &adev->gfx.priv_inst_irq);
4650 if (r)
4651 return r;
4652
4653 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE0x00000000L;
4654
4655 r = gfx_v10_0_me_init(adev);
4656 if (r)
4657 return r;
4658
4659 if (adev->gfx.rlc.funcs) {
4660 if (adev->gfx.rlc.funcs->init) {
4661 r = adev->gfx.rlc.funcs->init(adev);
4662 if (r) {
4663 dev_err(adev->dev, "Failed to init rlc BOs!\n")printf("drm:pid%d:%s *ERROR* " "Failed to init rlc BOs!\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
4664 return r;
4665 }
4666 }
4667 }
4668
4669 r = gfx_v10_0_mec_init(adev);
4670 if (r) {
4671 DRM_ERROR("Failed to init MEC BOs!\n")__drm_err("Failed to init MEC BOs!\n");
4672 return r;
4673 }
4674
4675 /* set up the gfx ring */
4676 for (i = 0; i < adev->gfx.me.num_me; i++) {
4677 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4678 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4679 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4680 continue;
4681
4682 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4683 i, k, j);
4684 if (r)
4685 return r;
4686 ring_id++;
4687 }
4688 }
4689 }
4690
4691 ring_id = 0;
4692 /* set up the compute queues - allocate horizontally across pipes */
4693 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4694 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4695 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4696 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4697 j))
4698 continue;
4699
4700 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4701 i, k, j);
4702 if (r)
4703 return r;
4704
4705 ring_id++;
4706 }
4707 }
4708 }
4709
4710 if (!adev->enable_mes_kiq) {
4711 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE2048);
4712 if (r) {
4713 DRM_ERROR("Failed to init KIQ BOs!\n")__drm_err("Failed to init KIQ BOs!\n");
4714 return r;
4715 }
4716
4717 kiq = &adev->gfx.kiq;
4718 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4719 if (r)
4720 return r;
4721 }
4722
4723 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4724 if (r)
4725 return r;
4726
4727 /* allocate visible FB for rlc auto-loading fw */
4728 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4729 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4730 if (r)
4731 return r;
4732 }
4733
4734 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE65536;
4735
4736 gfx_v10_0_gpu_early_init(adev);
4737
4738 return 0;
4739}
4740
4741static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4742{
4743 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4744 &adev->gfx.pfp.pfp_fw_gpu_addr,
4745 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4746}
4747
4748static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4749{
4750 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4751 &adev->gfx.ce.ce_fw_gpu_addr,
4752 (void **)&adev->gfx.ce.ce_fw_ptr);
4753}
4754
4755static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4756{
4757 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4758 &adev->gfx.me.me_fw_gpu_addr,
4759 (void **)&adev->gfx.me.me_fw_ptr);
4760}
4761
4762static int gfx_v10_0_sw_fini(void *handle)
4763{
4764 int i;
4765 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4766
4767 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4768 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4769 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4770 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4771
4772 amdgpu_gfx_mqd_sw_fini(adev);
4773
4774 if (!adev->enable_mes_kiq) {
4775 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4776 amdgpu_gfx_kiq_fini(adev);
4777 }
4778
4779 gfx_v10_0_pfp_fini(adev);
4780 gfx_v10_0_ce_fini(adev);
4781 gfx_v10_0_me_fini(adev);
4782 gfx_v10_0_rlc_fini(adev);
4783 gfx_v10_0_mec_fini(adev);
4784
4785 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4786 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4787
4788 gfx_v10_0_free_microcode(adev);
4789
4790 return 0;
4791}
4792
4793static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4794 u32 sh_num, u32 instance)
4795{
4796 u32 data;
4797
4798 if (instance == 0xffffffff)
4799 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,(((0) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e
)))
4800 INSTANCE_BROADCAST_WRITES, 1)(((0) & ~0x40000000L) | (0x40000000L & ((1) << 0x1e
)));
4801 else
4802 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,(((0) & ~0x000000FFL) | (0x000000FFL & ((instance) <<
0x0)))
4803 instance)(((0) & ~0x000000FFL) | (0x000000FFL & ((instance) <<
0x0)));
4804
4805 if (se_num == 0xffffffff)
4806 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,(((data) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)))
4807 1)(((data) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)));
4808 else
4809 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num)(((data) & ~0x00FF0000L) | (0x00FF0000L & ((se_num) <<
0x10)));
4810
4811 if (sh_num == 0xffffffff)
4812 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,(((data) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)))
4813 1)(((data) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
4814 else
4815 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num)(((data) & ~0x0000FF00L) | (0x0000FF00L & ((sh_num) <<
0x8)));
4816
4817 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2200), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x2200)), (data), 0));
4818}
4819
4820static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4821{
4822 u32 data, mask;
4823
4824 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x13dd, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x13dd), 0));
4825 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x147f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x147f), 0));
4826
4827 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK0x00FF0000L;
4828 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT0x10;
4829
4830 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4831 adev->gfx.config.max_sh_per_se);
4832
4833 return (~data) & mask;
4834}
4835
4836static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4837{
4838 int i, j;
4839 u32 data;
4840 u32 active_rbs = 0;
4841 u32 bitmap;
4842 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4843 adev->gfx.config.max_sh_per_se;
4844
4845 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
4846 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4847 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4848 bitmap = i * adev->gfx.config.max_sh_per_se + j;
4849 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0))) ||
4850 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3))) ||
4851 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)))) &&
4852 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4853 continue;
4854 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4855 data = gfx_v10_0_get_rb_active_bitmap(adev);
4856 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4857 rb_bitmap_width_per_sh);
4858 }
4859 }
4860 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4861 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
4862
4863 adev->gfx.config.backend_enable_mask = active_rbs;
4864 adev->gfx.config.num_rbs = hweight32(active_rbs);
4865}
4866
4867static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4868{
4869 uint32_t num_sc;
4870 uint32_t enabled_rb_per_sh;
4871 uint32_t active_rb_bitmap;
4872 uint32_t num_rb_per_sc;
4873 uint32_t num_packer_per_sc;
4874 uint32_t pa_sc_tile_steering_override;
4875
4876 /* for ASICs that integrates GFX v10.3
4877 * pa_sc_tile_steering_override should be set to 0 */
4878 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)))
4879 return 0;
4880
4881 /* init num_sc */
4882 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4883 adev->gfx.config.num_sc_per_sh;
4884 /* init num_rb_per_sc */
4885 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4886 enabled_rb_per_sh = hweight32(active_rb_bitmap);
4887 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4888 /* init num_packer_per_sc */
4889 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4890
4891 pa_sc_tile_steering_override = 0;
4892 pa_sc_tile_steering_override |=
4893 (order_base_2(num_sc)drm_order(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT0xc) &
4894 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK0x00003000L;
4895 pa_sc_tile_steering_override |=
4896 (order_base_2(num_rb_per_sc)drm_order(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT0x10) &
4897 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK0x00030000L;
4898 pa_sc_tile_steering_override |=
4899 (order_base_2(num_packer_per_sc)drm_order(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT0x14) &
4900 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK0x00100000L;
4901
4902 return pa_sc_tile_steering_override;
4903}
4904
4905#define DEFAULT_SH_MEM_BASES(0x6000) (0x6000)
4906
4907static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4908{
4909 int i;
4910 uint32_t sh_mem_bases;
4911
4912 /*
4913 * Configure apertures:
4914 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
4915 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
4916 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
4917 */
4918 sh_mem_bases = DEFAULT_SH_MEM_BASES(0x6000) | (DEFAULT_SH_MEM_BASES(0x6000) << 16);
4919
4920 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
4921 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) {
4922 nv_grbm_select(adev, 0, 0, 0, i);
4923 /* CP and shaders */
4924 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x10ad), ((SH_MEM_ADDRESS_MODE_64 << 0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED
<< 0x2) | (SH_MEM_RETRY_MODE_ALL << 0xc) | (3 <<
0xe)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x10ad)), (((SH_MEM_ADDRESS_MODE_64 <<
0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 0x2) | (SH_MEM_RETRY_MODE_ALL
<< 0xc) | (3 << 0xe))), 0));
4925 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x10aa), sh_mem_bases, 0, GC_HWIP) : amdgpu_device_wreg(
adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x10aa)), (sh_mem_bases
), 0));
4926 }
4927 nv_grbm_select(adev, 0, 0, 0, 0);
4928 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
4929
4930 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4931 access. These should be enabled by FW for target VMIDs. */
4932 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID16; i++) {
4933 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20a0) + 2 * i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x20a0) + 2 * i), (0
), 0));
4934 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20a1) + 2 * i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x20a1) + 2 * i), (0
), 0));
4935 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20c0) + i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[GC_HWIP][0][0] + 0x20c0) + i), (0), 0));
4936 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20d0) + i, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[GC_HWIP][0][0] + 0x20d0) + i), (0), 0));
4937 }
4938}
4939
4940static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4941{
4942 int vmid;
4943
4944 /*
4945 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4946 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4947 * the driver can enable them for graphics. VMID0 should maintain
4948 * access so that HWS firmware can save/restore entries.
4949 */
4950 for (vmid = 1; vmid < AMDGPU_NUM_VMID16; vmid++) {
4951 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20a0) + 2 * vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg(
adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x20a0) + 2 * vmid
), (0), 0));
4952 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20a1) + 2 * vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg(
adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x20a1) + 2 * vmid
), (0), 0));
4953 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20c0) + vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x20c0) + vmid), (0)
, 0));
4954 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x20d0) + vmid, 0, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x20d0) + vmid), (0)
, 0));
4955 }
4956}
4957
4958
4959static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4960{
4961 int i, j, k;
4962 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4963 u32 tmp, wgp_active_bitmap = 0;
4964 u32 gcrd_targets_disable_tcp = 0;
4965 u32 utcl_invreq_disable = 0;
4966 /*
4967 * GCRD_TARGETS_DISABLE field contains
4968 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4969 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4970 */
4971 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4972 2 * max_wgp_per_sh + /* TCP */
4973 max_wgp_per_sh + /* SQC */
4974 4); /* GL1C */
4975 /*
4976 * UTCL1_UTCL0_INVREQ_DISABLE field contains
4977 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4978 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4979 */
4980 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4981 2 * max_wgp_per_sh + /* TCP */
4982 2 * max_wgp_per_sh + /* SQC */
4983 4 + /* RMI */
4984 1); /* SQG */
4985
4986 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
4987 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4988 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4989 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4990 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4991 /*
4992 * Set corresponding TCP bits for the inactive WGPs in
4993 * GCRD_SA_TARGETS_DISABLE
4994 */
4995 gcrd_targets_disable_tcp = 0;
4996 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4997 utcl_invreq_disable = 0;
4998
4999 for (k = 0; k < max_wgp_per_sh; k++) {
5000 if (!(wgp_active_bitmap & (1 << k))) {
5001 gcrd_targets_disable_tcp |= 3 << (2 * k);
5002 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5003 utcl_invreq_disable |= (3 << (2 * k)) |
5004 (3 << (2 * (max_wgp_per_sh + k)));
5005 }
5006 }
5007
5008 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x158a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x158a), 0));
5009 /* only override TCP & SQC bits */
5010 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5011 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5012 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x158a), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x158a)), (tmp), 0));
5013
5014 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x158b, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x158b), 0));
5015 /* only override TCP & SQC bits */
5016 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5017 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5018 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x158b), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x158b)), (tmp), 0));
5019 }
5020 }
5021
5022 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5023 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
5024}
5025
5026static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5027{
5028 /* TCCs are global (not instanced). */
5029 uint32_t tcc_disable;
5030
5031 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0))) {
5032 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5006, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5006), 0)) |
5033 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5007, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5007), 0));
5034 } else {
5035 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x500a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x500a), 0)) |
5036 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x500b, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x500b), 0));
5037 }
5038
5039 adev->gfx.config.tcc_disabled_mask =
5040 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE)(((tcc_disable) & 0xFFFF0000L) >> 0x10) |
5041 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE)(((tcc_disable) & 0x0000FF00L) >> 0x8) << 16);
5042}
5043
5044static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5045{
5046 u32 tmp;
5047 int i;
5048
5049 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da0, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da0, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da0), 0)) & ~0x000000FFL) |
(0xff) << 0x0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (
adev->reg_offset[GC_HWIP][0][0] + 0x0da0), ((((((adev)->
virt.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][0] + 0x0da0, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[0] + 0x0da0), 0)) & ~0x000000FFL) | (0xff) << 0x0)
, 0));
5050
5051 gfx_v10_0_setup_rb(adev);
5052 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5053 gfx_v10_0_get_tcc_info(adev);
5054 adev->gfx.config.pa_sc_tile_steering_override =
5055 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5056
5057 /* XXX SH_MEM regs */
5058 /* where to put LDS, scratch, GPUVM in FSA64 space */
5059 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
5060 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_00].num_ids; i++) {
5061 nv_grbm_select(adev, 0, 0, 0, i);
5062 /* CP and shaders */
5063 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x10ad), ((SH_MEM_ADDRESS_MODE_64 << 0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED
<< 0x2) | (SH_MEM_RETRY_MODE_ALL << 0xc) | (3 <<
0xe)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x10ad)), (((SH_MEM_ADDRESS_MODE_64 <<
0x0) | (SH_MEM_ALIGNMENT_MODE_UNALIGNED << 0x2) | (SH_MEM_RETRY_MODE_ALL
<< 0xc) | (3 << 0xe))), 0));
5064 if (i != 0) {
5065 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc
.private_aperture_start >> 48)) << 0x0)))
5066 (adev->gmc.private_aperture_start >> 48))(((0) & ~0x0000FFFFL) | (0x0000FFFFL & (((adev->gmc
.private_aperture_start >> 48)) << 0x0)));
5067 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev->
gmc.shared_aperture_start >> 48)) << 0x10)))
5068 (adev->gmc.shared_aperture_start >> 48))(((tmp) & ~0xFFFF0000L) | (0xFFFF0000L & (((adev->
gmc.shared_aperture_start >> 48)) << 0x10)));
5069 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x10aa), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x10aa)), (tmp), 0));
5070 }
5071 }
5072 nv_grbm_select(adev, 0, 0, 0, 0);
5073
5074 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
5075
5076 gfx_v10_0_init_compute_vmid(adev);
5077 gfx_v10_0_init_gds_vmid(adev);
5078
5079}
5080
5081static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5082 bool_Bool enable)
5083{
5084 u32 tmp;
5085
5086 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
5087 return;
5088
5089 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0));
5090
5091 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,(((tmp) & ~0x00080000L) | (0x00080000L & ((enable ? 1
: 0) << 0x13)))
5092 enable ? 1 : 0)(((tmp) & ~0x00080000L) | (0x00080000L & ((enable ? 1
: 0) << 0x13)));
5093 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,(((tmp) & ~0x00100000L) | (0x00100000L & ((enable ? 1
: 0) << 0x14)))
5094 enable ? 1 : 0)(((tmp) & ~0x00100000L) | (0x00100000L & ((enable ? 1
: 0) << 0x14)));
5095 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,(((tmp) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)))
5096 enable ? 1 : 0)(((tmp) & ~0x00040000L) | (0x00040000L & ((enable ? 1
: 0) << 0x12)));
5097 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,(((tmp) & ~0x00200000L) | (0x00200000L & ((enable ? 1
: 0) << 0x15)))
5098 enable ? 1 : 0)(((tmp) & ~0x00200000L) | (0x00200000L & ((enable ? 1
: 0) << 0x15)));
5099
5100 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e0a), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a)), (tmp), 0));
5101}
5102
5103static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5104{
5105 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5106
5107 /* csib */
5108 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2))) {
5109 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca3; ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target_reg, adev->gfx.rlc.clear_state_gpu_addr
>> 32, (1<<2), GC_HWIP) : amdgpu_device_wreg(adev
, (target_reg), (adev->gfx.rlc.clear_state_gpu_addr >>
32), 0)); } while (0)
5110 adev->gfx.rlc.clear_state_gpu_addr >> 32)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca3; ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target_reg, adev->gfx.rlc.clear_state_gpu_addr
>> 32, (1<<2), GC_HWIP) : amdgpu_device_wreg(adev
, (target_reg), (adev->gfx.rlc.clear_state_gpu_addr >>
32), 0)); } while (0);
5111 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca2; ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target_reg, adev->gfx.rlc.clear_state_gpu_addr
& 0xfffffffc, (1<<2), GC_HWIP) : amdgpu_device_wreg
(adev, (target_reg), (adev->gfx.rlc.clear_state_gpu_addr &
0xfffffffc), 0)); } while (0)
5112 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca2; ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target_reg, adev->gfx.rlc.clear_state_gpu_addr
& 0xfffffffc, (1<<2), GC_HWIP) : amdgpu_device_wreg
(adev, (target_reg), (adev->gfx.rlc.clear_state_gpu_addr &
0xfffffffc), 0)); } while (0);
5113 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][1]
+ 0x4ca4; ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target_reg, adev->gfx.rlc.clear_state_size
, (1<<2), GC_HWIP) : amdgpu_device_wreg(adev, (target_reg
), (adev->gfx.rlc.clear_state_size), 0)); } while (0);
5114 } else {
5115 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca3), adev->gfx.rlc.clear_state_gpu_addr >> 32
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x4ca3)), (adev->gfx.rlc.clear_state_gpu_addr
>> 32), 0))
5116 adev->gfx.rlc.clear_state_gpu_addr >> 32)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca3), adev->gfx.rlc.clear_state_gpu_addr >> 32
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x4ca3)), (adev->gfx.rlc.clear_state_gpu_addr
>> 32), 0));
5117 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca2), adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x4ca2)), (adev->gfx.rlc.clear_state_gpu_addr
& 0xfffffffc), 0))
5118 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca2), adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x4ca2)), (adev->gfx.rlc.clear_state_gpu_addr
& 0xfffffffc), 0));
5119 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca4), adev->gfx.rlc.clear_state_size, 0, GC_HWIP) :
amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][1
] + 0x4ca4)), (adev->gfx.rlc.clear_state_size), 0));
5120 }
5121 return 0;
5122}
5123
5124static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5125{
5126 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c00), 0));
5127
5128 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0)(((tmp) & ~0x00000001L) | (0x00000001L & ((0) <<
0x0)));
5129 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c00), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4c00)), (tmp), 0));
5130}
5131
5132static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5133{
5134 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da8), 0)) & ~0x00000004L) |
(1) << 0x2, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev
->reg_offset[GC_HWIP][0][0] + 0x0da8), ((((((adev)->virt
.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][0] + 0x0da8, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[0] + 0x0da8), 0)) & ~0x00000004L) | (1) << 0x2), 0
));
5135 udelay(50);
5136 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da8), 0)) & ~0x00000004L) |
(0) << 0x2, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev
->reg_offset[GC_HWIP][0][0] + 0x0da8), ((((((adev)->virt
.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][0] + 0x0da8, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[0] + 0x0da8), 0)) & ~0x00000004L) | (0) << 0x2), 0
));
5137 udelay(50);
5138}
5139
5140static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5141 bool_Bool enable)
5142{
5143 uint32_t rlc_pg_cntl;
5144
5145 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c43, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c43), 0));
5146
5147 if (!enable) {
5148 /* RLC_PG_CNTL[23] = 0 (default)
5149 * RLC will wait for handshake acks with SMU
5150 * GFXOFF will be enabled
5151 * RLC_PG_CNTL[23] = 1
5152 * RLC will not issue any message to SMU
5153 * hence no handshake between SMU & RLC
5154 * GFXOFF will be disabled
5155 */
5156 rlc_pg_cntl |= 0x800000;
5157 } else
5158 rlc_pg_cntl &= ~0x800000;
5159 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c43), rlc_pg_cntl, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (rlc_pg_cntl
), 0));
5160}
5161
5162static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5163{
5164 /* TODO: enable rlc & smu handshake until smu
5165 * and gfxoff feature works as expected */
5166 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5167 gfx_v10_0_rlc_smu_handshake_cntl(adev, false0);
5168
5169 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c00, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c00), 0)) & ~0x00000001L) |
(1) << 0x0, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev
->reg_offset[GC_HWIP][0][1] + 0x4c00), ((((((adev)->virt
.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][1] + 0x4c00, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[1] + 0x4c00), 0)) & ~0x00000001L) | (1) << 0x0), 0
));
5170 udelay(50);
5171}
5172
5173static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5174{
5175 uint32_t tmp;
5176
5177 /* enable Save Restore Machine */
5178 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c80, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c80), 0));
5179 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK0x00000002L;
5180 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK0x00000001L;
5181 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c80), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4c80)), (tmp), 0));
5182}
5183
5184static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5185{
5186 const struct rlc_firmware_header_v2_0 *hdr;
5187 const __le32 *fw_data;
5188 unsigned i, fw_size;
5189
5190 if (!adev->gfx.rlc_fw)
5191 return -EINVAL22;
5192
5193 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5194 amdgpu_ucode_print_rlc_hdr(&hdr->header);
5195
5196 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5197 le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)));
5198 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes)((__uint32_t)(hdr->header.ucode_size_bytes)) / 4;
5199
5200 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b61), 0x00002000L, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x5b61)), (0x00002000L
), 0))
5201 RLCG_UCODE_LOADING_START_ADDRESS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b61), 0x00002000L, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x5b61)), (0x00002000L
), 0));
5202
5203 for (i = 0; i < fw_size; i++)
5204 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b62), ((__uint32_t)(*(__uint32_t *)(fw_data++))), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5b62)), (((__uint32_t)(*(__uint32_t *)(fw_data++))))
, 0))
5205 le32_to_cpup(fw_data++))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b62), ((__uint32_t)(*(__uint32_t *)(fw_data++))), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5b62)), (((__uint32_t)(*(__uint32_t *)(fw_data++))))
, 0));
5206
5207 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b61), adev->gfx.rlc_fw_version, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5b61)), (adev
->gfx.rlc_fw_version), 0));
5208
5209 return 0;
5210}
5211
5212static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5213{
5214 int r;
5215
5216 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5217 adev->psp.autoload_supported) {
5218
5219 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5220 if (r)
5221 return r;
5222
5223 gfx_v10_0_init_csb(adev);
5224
5225 if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) /* enable RLC SRM */
5226 gfx_v10_0_rlc_enable_srm(adev);
5227 } else {
5228 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
5229 gfx_v10_0_init_csb(adev);
5230 return 0;
5231 }
5232
5233 adev->gfx.rlc.funcs->stop(adev);
5234
5235 /* disable CG */
5236 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c49), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4c49)), (0), 0));
5237
5238 /* disable PG */
5239 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c43), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4c43)), (0), 0));
5240
5241 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5242 /* legacy rlc firmware loading */
5243 r = gfx_v10_0_rlc_load_microcode(adev);
5244 if (r)
5245 return r;
5246 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5247 /* rlc backdoor autoload firmware */
5248 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5249 if (r)
5250 return r;
5251 }
5252
5253 gfx_v10_0_init_csb(adev);
5254
5255 adev->gfx.rlc.funcs->start(adev);
5256
5257 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5258 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5259 if (r)
5260 return r;
5261 }
5262 }
5263 return 0;
5264}
5265
5266static struct {
5267 FIRMWARE_ID id;
5268 unsigned int offset;
5269 unsigned int size;
5270} rlc_autoload_info[FIRMWARE_ID_MAX];
5271
5272static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5273{
5274 int ret;
5275 RLC_TABLE_OF_CONTENT *rlc_toc;
5276
5277 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE(1 << 12),
5278 AMDGPU_GEM_DOMAIN_GTT0x2,
5279 &adev->gfx.rlc.rlc_toc_bo,
5280 &adev->gfx.rlc.rlc_toc_gpu_addr,
5281 (void **)&adev->gfx.rlc.rlc_toc_buf);
5282 if (ret) {
5283 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create rlc toc bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , ret);
5284 return ret;
5285 }
5286
5287 /* Copy toc from psp sos fw to rlc toc buffer */
5288 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes)__builtin_memcpy((adev->gfx.rlc.rlc_toc_buf), (adev->psp
.toc.start_addr), (adev->psp.toc.size_bytes));
5289
5290 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5291 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5292 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5293 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5294 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5295 /* Offset needs 4KB alignment */
5296 rlc_toc->offset = roundup2(rlc_toc->offset * 4, PAGE_SIZE)(((rlc_toc->offset * 4) + (((1 << 12)) - 1)) & (
~((__typeof(rlc_toc->offset * 4))((1 << 12)) - 1)));
5297 }
5298
5299 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5300 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5301 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5302
5303 rlc_toc++;
5304 }
5305
5306 return 0;
5307}
5308
5309static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5310{
5311 uint32_t total_size = 0;
5312 FIRMWARE_ID id;
5313 int ret;
5314
5315 ret = gfx_v10_0_parse_rlc_toc(adev);
5316 if (ret) {
5317 dev_err(adev->dev, "failed to parse rlc toc\n")printf("drm:pid%d:%s *ERROR* " "failed to parse rlc toc\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5318 return 0;
5319 }
5320
5321 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5322 total_size += rlc_autoload_info[id].size;
5323
5324 /* In case the offset in rlc toc ucode is aligned */
5325 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5326 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5327 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5328
5329 return total_size;
5330}
5331
5332static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5333{
5334 int r;
5335 uint32_t total_size;
5336
5337 total_size = gfx_v10_0_calc_toc_total_size(adev);
5338
5339 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE(1 << 12),
5340 AMDGPU_GEM_DOMAIN_GTT0x2,
5341 &adev->gfx.rlc.rlc_autoload_bo,
5342 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5343 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5344 if (r) {
5345 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create fw autoload bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5346 return r;
5347 }
5348
5349 return 0;
5350}
5351
5352static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5353{
5354 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5355 &adev->gfx.rlc.rlc_toc_gpu_addr,
5356 (void **)&adev->gfx.rlc.rlc_toc_buf);
5357 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5358 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5359 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5360}
5361
5362static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5363 FIRMWARE_ID id,
5364 const void *fw_data,
5365 uint32_t fw_size)
5366{
5367 uint32_t toc_offset;
5368 uint32_t toc_fw_size;
5369 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5370
5371 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5372 return;
5373
5374 toc_offset = rlc_autoload_info[id].offset;
5375 toc_fw_size = rlc_autoload_info[id].size;
5376
5377 if (fw_size == 0)
5378 fw_size = toc_fw_size;
5379
5380 if (fw_size > toc_fw_size)
5381 fw_size = toc_fw_size;
5382
5383 memcpy(ptr + toc_offset, fw_data, fw_size)__builtin_memcpy((ptr + toc_offset), (fw_data), (fw_size));
5384
5385 if (fw_size < toc_fw_size)
5386 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size)__builtin_memset((ptr + toc_offset + fw_size), (0), (toc_fw_size
- fw_size));
5387}
5388
5389static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5390{
5391 void *data;
5392 uint32_t size;
5393
5394 data = adev->gfx.rlc.rlc_toc_buf;
5395 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5396
5397 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5398 FIRMWARE_ID_RLC_TOC,
5399 data, size);
5400}
5401
5402static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5403{
5404 const __le32 *fw_data;
5405 uint32_t fw_size;
5406 const struct gfx_firmware_header_v1_0 *cp_hdr;
5407 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5408
5409 /* pfp ucode */
5410 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5411 adev->gfx.pfp_fw->data;
5412 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5413 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5414 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes));
5415 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5416 FIRMWARE_ID_CP_PFP,
5417 fw_data, fw_size);
5418
5419 /* ce ucode */
5420 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5421 adev->gfx.ce_fw->data;
5422 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5423 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5424 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes));
5425 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5426 FIRMWARE_ID_CP_CE,
5427 fw_data, fw_size);
5428
5429 /* me ucode */
5430 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5431 adev->gfx.me_fw->data;
5432 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5433 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5434 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes));
5435 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5436 FIRMWARE_ID_CP_ME,
5437 fw_data, fw_size);
5438
5439 /* rlc ucode */
5440 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5441 adev->gfx.rlc_fw->data;
5442 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5443 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)((__uint32_t)(rlc_hdr->header.ucode_array_offset_bytes)));
5444 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes)((__uint32_t)(rlc_hdr->header.ucode_size_bytes));
5445 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5446 FIRMWARE_ID_RLC_G_UCODE,
5447 fw_data, fw_size);
5448
5449 /* mec1 ucode */
5450 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5451 adev->gfx.mec_fw->data;
5452 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5453 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(cp_hdr->header.ucode_array_offset_bytes)));
5454 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes)((__uint32_t)(cp_hdr->header.ucode_size_bytes)) -
5455 cp_hdr->jt_size * 4;
5456 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5457 FIRMWARE_ID_CP_MEC,
5458 fw_data, fw_size);
5459 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5460}
5461
5462/* Temporarily put sdma part here */
5463static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5464{
5465 const __le32 *fw_data;
5466 uint32_t fw_size;
5467 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5468 int i;
5469
5470 for (i = 0; i < adev->sdma.num_instances; i++) {
5471 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5472 adev->sdma.instance[i].fw->data;
5473 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5474 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)((__uint32_t)(sdma_hdr->header.ucode_array_offset_bytes)));
5475 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes)((__uint32_t)(sdma_hdr->header.ucode_size_bytes));
5476
5477 if (i == 0) {
5478 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5479 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5480 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5481 FIRMWARE_ID_SDMA0_JT,
5482 (uint32_t *)fw_data +
5483 sdma_hdr->jt_offset,
5484 sdma_hdr->jt_size * 4);
5485 } else if (i == 1) {
5486 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5487 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5488 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5489 FIRMWARE_ID_SDMA1_JT,
5490 (uint32_t *)fw_data +
5491 sdma_hdr->jt_offset,
5492 sdma_hdr->jt_size * 4);
5493 }
5494 }
5495}
5496
5497static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5498{
5499 uint32_t rlc_g_offset, rlc_g_size, tmp;
5500 uint64_t gpu_addr;
5501
5502 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5503 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5504 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5505
5506 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5507 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5508 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5509
5510 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b5e), ((u32)(((gpu_addr) >> 16) >> 16)), 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][1] + 0x5b5e)), (((u32)(((gpu_addr) >> 16) >>
16))), 0));
5511 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b5d), ((u32)(gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5b5d)), (((u32
)(gpu_addr))), 0));
5512 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b5c), rlc_g_size, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x5b5c)), (rlc_g_size
), 0));
5513
5514 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5b54, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5b54), 0));
5515 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK0x00000001L |
5516 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK0x00000002L))) {
5517 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n")__drm_err("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5518 return -EINVAL22;
5519 }
5520
5521 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c00), 0));
5522 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK0x00000001L) {
5523 DRM_ERROR("RLC ROM should halt itself\n")__drm_err("RLC ROM should halt itself\n");
5524 return -EINVAL22;
5525 }
5526
5527 return 0;
5528}
5529
5530static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5531{
5532 uint32_t usec_timeout = 50000; /* wait for 50ms */
5533 uint32_t tmp;
5534 int i;
5535 uint64_t addr;
5536
5537 /* Trigger an invalidation of the L1 instruction caches */
5538 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5847, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5847), 0));
5539 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5540 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5847), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5847)), (tmp), 0));
5541
5542 /* Wait for invalidation complete */
5543 for (i = 0; i < usec_timeout; i++) {
5544 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5847, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5847), 0));
5545 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5546 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5547 break;
5548 udelay(1);
5549 }
5550
5551 if (i >= usec_timeout) {
5552 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5553 return -EINVAL22;
5554 }
5555
5556 /* Program me ucode address into intruction cache address register */
5557 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5558 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5559 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5844), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5844)), (((u32
)(addr)) & 0xFFFFF000), 0))
5560 lower_32_bits(addr) & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5844), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5844)), (((u32
)(addr)) & 0xFFFFF000), 0));
5561 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5845), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5845)), (((u32)(((addr) >> 16) >> 16))),
0))
5562 upper_32_bits(addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5845), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5845)), (((u32)(((addr) >> 16) >> 16))),
0));
5563
5564 return 0;
5565}
5566
5567static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5568{
5569 uint32_t usec_timeout = 50000; /* wait for 50ms */
5570 uint32_t tmp;
5571 int i;
5572 uint64_t addr;
5573
5574 /* Trigger an invalidation of the L1 instruction caches */
5575 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584b, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584b), 0));
5576 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5577 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584b), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x584b)), (tmp), 0));
5578
5579 /* Wait for invalidation complete */
5580 for (i = 0; i < usec_timeout; i++) {
5581 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584b, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584b), 0));
5582 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5583 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5584 break;
5585 udelay(1);
5586 }
5587
5588 if (i >= usec_timeout) {
5589 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5590 return -EINVAL22;
5591 }
5592
5593 /* Program ce ucode address into intruction cache address register */
5594 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5595 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5596 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5848), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5848)), (((u32
)(addr)) & 0xFFFFF000), 0))
5597 lower_32_bits(addr) & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5848), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5848)), (((u32
)(addr)) & 0xFFFFF000), 0));
5598 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5849), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5849)), (((u32)(((addr) >> 16) >> 16))),
0))
5599 upper_32_bits(addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5849), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5849)), (((u32)(((addr) >> 16) >> 16))),
0));
5600
5601 return 0;
5602}
5603
5604static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5605{
5606 uint32_t usec_timeout = 50000; /* wait for 50ms */
5607 uint32_t tmp;
5608 int i;
5609 uint64_t addr;
5610
5611 /* Trigger an invalidation of the L1 instruction caches */
5612 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5843, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5843), 0));
5613 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5614 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5843), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5843)), (tmp), 0));
5615
5616 /* Wait for invalidation complete */
5617 for (i = 0; i < usec_timeout; i++) {
5618 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5843, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5843), 0));
5619 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5620 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5621 break;
5622 udelay(1);
5623 }
5624
5625 if (i >= usec_timeout) {
5626 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5627 return -EINVAL22;
5628 }
5629
5630 /* Program pfp ucode address into intruction cache address register */
5631 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5632 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5633 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5840), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5840)), (((u32
)(addr)) & 0xFFFFF000), 0))
5634 lower_32_bits(addr) & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5840), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5840)), (((u32
)(addr)) & 0xFFFFF000), 0));
5635 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5841), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5841)), (((u32)(((addr) >> 16) >> 16))),
0))
5636 upper_32_bits(addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5841), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x5841)), (((u32)(((addr) >> 16) >> 16))),
0));
5637
5638 return 0;
5639}
5640
5641static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5642{
5643 uint32_t usec_timeout = 50000; /* wait for 50ms */
5644 uint32_t tmp;
5645 int i;
5646 uint64_t addr;
5647
5648 /* Trigger an invalidation of the L1 instruction caches */
5649 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584f), 0));
5650 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5651 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584f), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x584f)), (tmp), 0));
5652
5653 /* Wait for invalidation complete */
5654 for (i = 0; i < usec_timeout; i++) {
5655 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584f), 0));
5656 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5657 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5658 break;
5659 udelay(1);
5660 }
5661
5662 if (i >= usec_timeout) {
5663 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5664 return -EINVAL22;
5665 }
5666
5667 /* Program mec1 ucode address into intruction cache address register */
5668 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5669 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5670 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584c), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x584c)), (((u32
)(addr)) & 0xFFFFF000), 0))
5671 lower_32_bits(addr) & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584c), ((u32)(addr)) & 0xFFFFF000, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x584c)), (((u32
)(addr)) & 0xFFFFF000), 0));
5672 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584d), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x584d)), (((u32)(((addr) >> 16) >> 16))),
0))
5673 upper_32_bits(addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584d), ((u32)(((addr) >> 16) >> 16)), 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][1] + 0x584d)), (((u32)(((addr) >> 16) >> 16))),
0));
5674
5675 return 0;
5676}
5677
5678static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5679{
5680 uint32_t cp_status;
5681 uint32_t bootload_status;
5682 int i, r;
5683
5684 for (i = 0; i < adev->usec_timeout; i++) {
5685 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0f40, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0f40), 0));
5686 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4e8d, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4e8d), 0));
5687 if ((cp_status == 0) &&
5688 (REG_GET_FIELD(bootload_status,(((bootload_status) & 0x80000000L) >> 0x1f)
5689 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE)(((bootload_status) & 0x80000000L) >> 0x1f) == 1)) {
5690 break;
5691 }
5692 udelay(1);
5693 }
5694
5695 if (i >= adev->usec_timeout) {
5696 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n")printf("drm:pid%d:%s *ERROR* " "rlc autoload: gc ucode autoload timeout\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5697 return -ETIMEDOUT60;
5698 }
5699
5700 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5701 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5702 if (r)
5703 return r;
5704
5705 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5706 if (r)
5707 return r;
5708
5709 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5710 if (r)
5711 return r;
5712
5713 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5714 if (r)
5715 return r;
5716 }
5717
5718 return 0;
5719}
5720
5721static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool_Bool enable)
5722{
5723 int i;
5724 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0f56, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0f56), 0));
5725
5726 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((enable ? 0
: 1) << 0x1c)));
5727 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1)(((tmp) & ~0x04000000L) | (0x04000000L & ((enable ? 0
: 1) << 0x1a)));
5728 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((enable ? 0
: 1) << 0x18)));
5729
5730 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2))) {
5731 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp)do { uint32_t target_reg = adev->reg_offset[GC_HWIP][0][0]
+ 0x0f56; ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target_reg, tmp, (1<<2), GC_HWIP
) : amdgpu_device_wreg(adev, (target_reg), (tmp), 0)); } while
(0);
5732 } else {
5733 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f56), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0f56)), (tmp), 0));
5734 }
5735
5736 if (adev->job_hang && !enable)
5737 return 0;
5738
5739 for (i = 0; i < adev->usec_timeout; i++) {
5740 if (RREG32_SOC15(GC, 0, mmCP_STAT)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0f40, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0f40), 0)) == 0)
5741 break;
5742 udelay(1);
5743 }
5744
5745 if (i >= adev->usec_timeout)
5746 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt")__drm_err("failed to %s cp gfx\n", enable ? "unhalt" : "halt"
);
5747
5748 return 0;
5749}
5750
5751static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5752{
5753 int r;
5754 const struct gfx_firmware_header_v1_0 *pfp_hdr;
5755 const __le32 *fw_data;
5756 unsigned i, fw_size;
5757 uint32_t tmp;
5758 uint32_t usec_timeout = 50000; /* wait for 50ms */
5759
5760 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5761 adev->gfx.pfp_fw->data;
5762
5763 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5764
5765 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5766 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)((__uint32_t)(pfp_hdr->header.ucode_array_offset_bytes)));
5767 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes)((__uint32_t)(pfp_hdr->header.ucode_size_bytes));
5768
5769 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5770 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
5771 &adev->gfx.pfp.pfp_fw_obj,
5772 &adev->gfx.pfp.pfp_fw_gpu_addr,
5773 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5774 if (r) {
5775 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create pfp fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5776 gfx_v10_0_pfp_fini(adev);
5777 return r;
5778 }
5779
5780 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size)__builtin_memcpy((adev->gfx.pfp.pfp_fw_ptr), (fw_data), (fw_size
));
5781
5782 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5783 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5784
5785 /* Trigger an invalidation of the L1 instruction caches */
5786 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5843, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5843), 0));
5787 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5788 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5843), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5843)), (tmp), 0));
5789
5790 /* Wait for invalidation complete */
5791 for (i = 0; i < usec_timeout; i++) {
5792 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5843, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5843), 0));
5793 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5794 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5795 break;
5796 udelay(1);
5797 }
5798
5799 if (i >= usec_timeout) {
5800 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5801 return -EINVAL22;
5802 }
5803
5804 if (amdgpu_emu_mode == 1)
5805 adev->hdp.funcs->flush_hdp(adev, NULL((void *)0));
5806
5807 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5842, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5842), 0));
5808 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
5809 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
5810 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
5811 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
5812 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5842), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5842)), (tmp), 0));
5813 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5840), adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x5840)), (adev->gfx.pfp.pfp_fw_gpu_addr
& 0xFFFFF000), 0))
5814 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5840), adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x5840)), (adev->gfx.pfp.pfp_fw_gpu_addr
& 0xFFFFF000), 0));
5815 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5841), ((u32)(((adev->gfx.pfp.pfp_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5841)), (((u32)(((adev
->gfx.pfp.pfp_fw_gpu_addr) >> 16) >> 16))), 0)
)
5816 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5841), ((u32)(((adev->gfx.pfp.pfp_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5841)), (((u32)(((adev
->gfx.pfp.pfp_fw_gpu_addr) >> 16) >> 16))), 0)
);
5817
5818 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5814), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5814)), (0), 0));
5819
5820 for (i = 0; i < pfp_hdr->jt_size; i++)
5821 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5815), ((__uint32_t)(*(__uint32_t *)(fw_data + pfp_hdr
->jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][1] + 0x5815)), (((__uint32_t
)(*(__uint32_t *)(fw_data + pfp_hdr->jt_offset + i)))), 0)
)
5822 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5815), ((__uint32_t)(*(__uint32_t *)(fw_data + pfp_hdr
->jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][1] + 0x5815)), (((__uint32_t
)(*(__uint32_t *)(fw_data + pfp_hdr->jt_offset + i)))), 0)
);
5823
5824 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5814), adev->gfx.pfp_fw_version, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5814)), (adev
->gfx.pfp_fw_version), 0));
5825
5826 return 0;
5827}
5828
5829static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5830{
5831 int r;
5832 const struct gfx_firmware_header_v1_0 *ce_hdr;
5833 const __le32 *fw_data;
5834 unsigned i, fw_size;
5835 uint32_t tmp;
5836 uint32_t usec_timeout = 50000; /* wait for 50ms */
5837
5838 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5839 adev->gfx.ce_fw->data;
5840
5841 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5842
5843 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5844 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)((__uint32_t)(ce_hdr->header.ucode_array_offset_bytes)));
5845 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes)((__uint32_t)(ce_hdr->header.ucode_size_bytes));
5846
5847 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5848 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
5849 &adev->gfx.ce.ce_fw_obj,
5850 &adev->gfx.ce.ce_fw_gpu_addr,
5851 (void **)&adev->gfx.ce.ce_fw_ptr);
5852 if (r) {
5853 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create ce fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5854 gfx_v10_0_ce_fini(adev);
5855 return r;
5856 }
5857
5858 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size)__builtin_memcpy((adev->gfx.ce.ce_fw_ptr), (fw_data), (fw_size
));
5859
5860 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5861 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5862
5863 /* Trigger an invalidation of the L1 instruction caches */
5864 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584b, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584b), 0));
5865 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5866 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584b), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x584b)), (tmp), 0));
5867
5868 /* Wait for invalidation complete */
5869 for (i = 0; i < usec_timeout; i++) {
5870 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584b, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584b), 0));
5871 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5872 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5873 break;
5874 udelay(1);
5875 }
5876
5877 if (i >= usec_timeout) {
5878 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5879 return -EINVAL22;
5880 }
5881
5882 if (amdgpu_emu_mode == 1)
5883 adev->hdp.funcs->flush_hdp(adev, NULL((void *)0));
5884
5885 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584a), 0));
5886 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
5887 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
5888 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
5889 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
5890 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5848), adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x5848)), (adev->gfx.ce.ce_fw_gpu_addr &
0xFFFFF000), 0))
5891 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5848), adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x5848)), (adev->gfx.ce.ce_fw_gpu_addr &
0xFFFFF000), 0));
5892 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5849), ((u32)(((adev->gfx.ce.ce_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5849)), (((u32)(((adev
->gfx.ce.ce_fw_gpu_addr) >> 16) >> 16))), 0))
5893 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5849), ((u32)(((adev->gfx.ce.ce_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5849)), (((u32)(((adev
->gfx.ce.ce_fw_gpu_addr) >> 16) >> 16))), 0));
5894
5895 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5818), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5818)), (0), 0));
5896
5897 for (i = 0; i < ce_hdr->jt_size; i++)
5898 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5819), ((__uint32_t)(*(__uint32_t *)(fw_data + ce_hdr->
jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5819)), (((__uint32_t)(*(__uint32_t
*)(fw_data + ce_hdr->jt_offset + i)))), 0))
5899 le32_to_cpup(fw_data + ce_hdr->jt_offset + i))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5819), ((__uint32_t)(*(__uint32_t *)(fw_data + ce_hdr->
jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5819)), (((__uint32_t)(*(__uint32_t
*)(fw_data + ce_hdr->jt_offset + i)))), 0));
5900
5901 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5818), adev->gfx.ce_fw_version, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5818)), (adev
->gfx.ce_fw_version), 0));
5902
5903 return 0;
5904}
5905
5906static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5907{
5908 int r;
5909 const struct gfx_firmware_header_v1_0 *me_hdr;
5910 const __le32 *fw_data;
5911 unsigned i, fw_size;
5912 uint32_t tmp;
5913 uint32_t usec_timeout = 50000; /* wait for 50ms */
5914
5915 me_hdr = (const struct gfx_firmware_header_v1_0 *)
5916 adev->gfx.me_fw->data;
5917
5918 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5919
5920 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5921 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)((__uint32_t)(me_hdr->header.ucode_array_offset_bytes)));
5922 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes)((__uint32_t)(me_hdr->header.ucode_size_bytes));
5923
5924 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5925 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
5926 &adev->gfx.me.me_fw_obj,
5927 &adev->gfx.me.me_fw_gpu_addr,
5928 (void **)&adev->gfx.me.me_fw_ptr);
5929 if (r) {
5930 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to create me fw bo\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5931 gfx_v10_0_me_fini(adev);
5932 return r;
5933 }
5934
5935 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size)__builtin_memcpy((adev->gfx.me.me_fw_ptr), (fw_data), (fw_size
));
5936
5937 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5938 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5939
5940 /* Trigger an invalidation of the L1 instruction caches */
5941 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5847, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5847), 0));
5942 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
5943 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5847), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5847)), (tmp), 0));
5944
5945 /* Wait for invalidation complete */
5946 for (i = 0; i < usec_timeout; i++) {
5947 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5847, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5847), 0));
5948 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
5949 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
5950 break;
5951 udelay(1);
5952 }
5953
5954 if (i >= usec_timeout) {
5955 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
5956 return -EINVAL22;
5957 }
5958
5959 if (amdgpu_emu_mode == 1)
5960 adev->hdp.funcs->flush_hdp(adev, NULL((void *)0));
5961
5962 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5846, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5846), 0));
5963 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
5964 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
5965 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
5966 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
Value stored to 'tmp' is never read
5967 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5844), adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x5844)), (adev->gfx.me.me_fw_gpu_addr &
0xFFFFF000), 0))
5968 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5844), adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x5844)), (adev->gfx.me.me_fw_gpu_addr &
0xFFFFF000), 0));
5969 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5845), ((u32)(((adev->gfx.me.me_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5845)), (((u32)(((adev
->gfx.me.me_fw_gpu_addr) >> 16) >> 16))), 0))
5970 upper_32_bits(adev->gfx.me.me_fw_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5845), ((u32)(((adev->gfx.me.me_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5845)), (((u32)(((adev
->gfx.me.me_fw_gpu_addr) >> 16) >> 16))), 0));
5971
5972 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5816), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5816)), (0), 0));
5973
5974 for (i = 0; i < me_hdr->jt_size; i++)
5975 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5817), ((__uint32_t)(*(__uint32_t *)(fw_data + me_hdr->
jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5817)), (((__uint32_t)(*(__uint32_t
*)(fw_data + me_hdr->jt_offset + i)))), 0))
5976 le32_to_cpup(fw_data + me_hdr->jt_offset + i))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5817), ((__uint32_t)(*(__uint32_t *)(fw_data + me_hdr->
jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5817)), (((__uint32_t)(*(__uint32_t
*)(fw_data + me_hdr->jt_offset + i)))), 0));
5977
5978 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5816), adev->gfx.me_fw_version, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x5816)), (adev
->gfx.me_fw_version), 0));
5979
5980 return 0;
5981}
5982
5983static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5984{
5985 int r;
5986
5987 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5988 return -EINVAL22;
5989
5990 gfx_v10_0_cp_gfx_enable(adev, false0);
5991
5992 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5993 if (r) {
5994 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to load pfp fw\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
5995 return r;
5996 }
5997
5998 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5999 if (r) {
6000 dev_err(adev->dev, "(%d) failed to load ce fw\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to load ce fw\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
6001 return r;
6002 }
6003
6004 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6005 if (r) {
6006 dev_err(adev->dev, "(%d) failed to load me fw\n", r)printf("drm:pid%d:%s *ERROR* " "(%d) failed to load me fw\n",
({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
6007 return r;
6008 }
6009
6010 return 0;
6011}
6012
6013static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6014{
6015 struct amdgpu_ring *ring;
6016 const struct cs_section_def *sect = NULL((void *)0);
6017 const struct cs_extent_def *ext = NULL((void *)0);
6018 int r, i;
6019 int ctx_reg_offset;
6020
6021 /* init the CP */
6022 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e4e), adev->gfx.config.max_hw_contexts - 1, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1e4e)), (adev->gfx.config.max_hw_contexts - 1), 0
))
6023 adev->gfx.config.max_hw_contexts - 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e4e), adev->gfx.config.max_hw_contexts - 1, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1e4e)), (adev->gfx.config.max_hw_contexts - 1), 0
));
6024 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1deb), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1deb)), (1), 0));
6025
6026 gfx_v10_0_cp_gfx_enable(adev, true1);
6027
6028 ring = &adev->gfx.gfx_ring[0];
6029 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6030 if (r) {
6031 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r);
6032 return r;
6033 }
6034
6035 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
6036 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE(2 << 28));
6037
6038 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
6039 amdgpu_ring_write(ring, 0x80000000);
6040 amdgpu_ring_write(ring, 0x80000000);
6041
6042 for (sect = gfx10_cs_data; sect->section != NULL((void *)0); ++sect) {
6043 for (ext = sect->section; ext->extent != NULL((void *)0); ++ext) {
6044 if (sect->id == SECT_CONTEXT) {
6045 amdgpu_ring_write(ring,
6046 PACKET3(PACKET3_SET_CONTEXT_REG,((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->
reg_count) & 0x3FFF) << 16)
6047 ext->reg_count)((3 << 30) | (((0x69) & 0xFF) << 8) | ((ext->
reg_count) & 0x3FFF) << 16));
6048 amdgpu_ring_write(ring, ext->reg_index -
6049 PACKET3_SET_CONTEXT_REG_START0x0000a000);
6050 for (i = 0; i < ext->reg_count; i++)
6051 amdgpu_ring_write(ring, ext->extent[i]);
6052 }
6053 }
6054 }
6055
6056 ctx_reg_offset =
6057 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE)(adev->reg_offset[GC_HWIP][0][1] + 0x00d7) - PACKET3_SET_CONTEXT_REG_START0x0000a000;
6058 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)((3 << 30) | (((0x69) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
6059 amdgpu_ring_write(ring, ctx_reg_offset);
6060 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6061
6062 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)((3 << 30) | (((0x4A) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
6063 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE(3 << 28));
6064
6065 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
6066 amdgpu_ring_write(ring, 0);
6067
6068 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)((3 << 30) | (((0x11) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
6069 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)((3) << 0));
6070 amdgpu_ring_write(ring, 0x8000);
6071 amdgpu_ring_write(ring, 0x8000);
6072
6073 amdgpu_ring_commit(ring);
6074
6075 /* submit cs packet to copy state 0 to next available state */
6076 if (adev->gfx.num_gfx_rings > 1) {
6077 /* maximum supported gfx ring is 2 */
6078 ring = &adev->gfx.gfx_ring[1];
6079 r = amdgpu_ring_alloc(ring, 2);
6080 if (r) {
6081 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r)__drm_err("amdgpu: cp failed to lock ring (%d).\n", r);
6082 return r;
6083 }
6084
6085 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)((3 << 30) | (((0x12) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
6086 amdgpu_ring_write(ring, 0);
6087
6088 amdgpu_ring_commit(ring);
6089 }
6090 return 0;
6091}
6092
6093static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6094 CP_PIPE_ID pipe)
6095{
6096 u32 tmp;
6097
6098 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0dc2, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0dc2), 0));
6099 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe)(((tmp) & ~0x00000003L) | (0x00000003L & ((pipe) <<
0x0)));
6100
6101 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0dc2), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0dc2)), (tmp), 0));
6102}
6103
6104static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6105 struct amdgpu_ring *ring)
6106{
6107 u32 tmp;
6108
6109 if (!amdgpu_async_gfx_ring) {
6110 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e8d, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e8d), 0));
6111 if (ring->use_doorbell) {
6112 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
6113 DOORBELL_OFFSET, ring->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
6114 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
6115 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6116 } else {
6117 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
6118 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
6119 }
6120 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8d), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1e8d)), (tmp), 0));
6121 }
6122 switch (adev->ip_versions[GC_HWIP][0]) {
6123 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
6124 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
6125 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
6126 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
6127 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
6128 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
6129 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
6130 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
6131 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x00000FFCL) | (0x00000FFCL & ((ring->doorbell_index
) << 0x2)))
6132 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index)(((0) & ~0x00000FFCL) | (0x00000FFCL & ((ring->doorbell_index
) << 0x2)));
6133 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfa), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1dfa)), (tmp), 0));
6134
6135 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfb), 0x00000FFCL, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x1dfb)), (0x00000FFCL
), 0))
6136 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfb), 0x00000FFCL, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x1dfb)), (0x00000FFCL
), 0));
6137 break;
6138 default:
6139 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)))
6140 DOORBELL_RANGE_LOWER, ring->doorbell_index)(((0) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((ring->doorbell_index
) << 0x2)));
6141 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfa), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1dfa)), (tmp), 0));
6142
6143 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfb), 0x0FFFFFFCL, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x1dfb)), (0x0FFFFFFCL
), 0))
6144 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfb), 0x0FFFFFFCL, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][0] + 0x1dfb)), (0x0FFFFFFCL
), 0));
6145 break;
6146 }
6147}
6148
6149static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6150{
6151 struct amdgpu_ring *ring;
6152 u32 tmp;
6153 u32 rb_bufsz;
6154 u64 rb_addr, rptr_addr, wptr_gpu_addr;
6155 u32 i;
6156
6157 /* Set the write pointer delay */
6158 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f61), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0f61)), (0), 0));
6159
6160 /* set the RB to use vmid 0 */
6161 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df1), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1df1)), (0), 0));
6162
6163 /* Init gfx ring 0 for pipe 0 */
6164 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6165 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6166
6167 /* Set ring buffer size */
6168 ring = &adev->gfx.gfx_ring[0];
6169 rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
6170 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
6171 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
6172#ifdef __BIG_ENDIAN
6173 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1)(((tmp) & ~0x00030000L) | (0x00030000L & ((1) <<
0x10)));
6174#endif
6175 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1de1), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1de1)), (tmp), 0));
6176
6177 /* Initialize the ring buffer's write pointers */
6178 ring->wptr = 0;
6179 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df4), ((u32)(ring->wptr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1df4)), (((u32
)(ring->wptr))), 0));
6180 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df5), ((u32)(((ring->wptr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1df5)), (((u32)(((ring->wptr) >>
16) >> 16))), 0));
6181
6182 /* set the wb address wether it's enabled or not */
6183 rptr_addr = ring->rptr_gpu_addr;
6184 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1de3), ((u32)(rptr_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1de3)), (((u32
)(rptr_addr))), 0));
6185 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1de4), ((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->
reg_offset[GC_HWIP][0][0] + 0x1de4)), (((u32)(((rptr_addr) >>
16) >> 16)) & 0x0000FFFFL), 0))
6186 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1de4), ((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->
reg_offset[GC_HWIP][0][0] + 0x1de4)), (((u32)(((rptr_addr) >>
16) >> 16)) & 0x0000FFFFL), 0));
6187
6188 wptr_gpu_addr = ring->wptr_gpu_addr;
6189 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8b), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8b)), (((u32
)(wptr_gpu_addr))), 0))
6190 lower_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8b), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8b)), (((u32
)(wptr_gpu_addr))), 0));
6191 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8c), ((u32)(((wptr_gpu_addr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1e8c)), (((u32)(((wptr_gpu_addr) >>
16) >> 16))), 0))
6192 upper_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8c), ((u32)(((wptr_gpu_addr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1e8c)), (((u32)(((wptr_gpu_addr) >>
16) >> 16))), 0));
6193
6194 mdelay(1);
6195 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1de1), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1de1)), (tmp), 0));
6196
6197 rb_addr = ring->gpu_addr >> 8;
6198 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1de0), rb_addr, 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][0] + 0x1de0)), (rb_addr), 0
));
6199 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e51), ((u32)(((rb_addr) >> 16) >> 16)), 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1e51)), (((u32)(((rb_addr) >> 16) >> 16
))), 0));
6200
6201 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1f40), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1f40)), (1), 0));
6202
6203 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6204 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6205
6206 /* Init gfx ring 1 for pipe 1 */
6207 if (adev->gfx.num_gfx_rings > 1) {
6208 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6209 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6210 /* maximum supported gfx ring is 2 */
6211 ring = &adev->gfx.gfx_ring[1];
6212 rb_bufsz = order_base_2(ring->ring_size / 8)drm_order(ring->ring_size / 8);
6213 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
6214 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
6215 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e01), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1e01)), (tmp), 0));
6216 /* Initialize the ring buffer's write pointers */
6217 ring->wptr = 0;
6218 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df6), ((u32)(ring->wptr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1df6)), (((u32
)(ring->wptr))), 0));
6219 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df7), ((u32)(((ring->wptr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1df7)), (((u32)(((ring->wptr) >>
16) >> 16))), 0));
6220 /* Set the wb address wether it's enabled or not */
6221 rptr_addr = ring->rptr_gpu_addr;
6222 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e02), ((u32)(rptr_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e02)), (((u32
)(rptr_addr))), 0));
6223 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e03), ((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->
reg_offset[GC_HWIP][0][0] + 0x1e03)), (((u32)(((rptr_addr) >>
16) >> 16)) & 0x0000FFFFL), 0))
6224 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e03), ((u32)(((rptr_addr) >> 16) >> 16)) &
0x0000FFFFL, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->
reg_offset[GC_HWIP][0][0] + 0x1e03)), (((u32)(((rptr_addr) >>
16) >> 16)) & 0x0000FFFFL), 0));
6225 wptr_gpu_addr = ring->wptr_gpu_addr;
6226 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8b), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8b)), (((u32
)(wptr_gpu_addr))), 0))
6227 lower_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8b), ((u32)(wptr_gpu_addr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8b)), (((u32
)(wptr_gpu_addr))), 0));
6228 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8c), ((u32)(((wptr_gpu_addr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1e8c)), (((u32)(((wptr_gpu_addr) >>
16) >> 16))), 0))
6229 upper_32_bits(wptr_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8c), ((u32)(((wptr_gpu_addr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1e8c)), (((u32)(((wptr_gpu_addr) >>
16) >> 16))), 0));
6230
6231 mdelay(1);
6232 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e01), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1e01)), (tmp), 0));
6233
6234 rb_addr = ring->gpu_addr >> 8;
6235 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e00), rb_addr, 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][0] + 0x1e00)), (rb_addr), 0
));
6236 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e52), ((u32)(((rb_addr) >> 16) >> 16)), 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1e52)), (((u32)(((rb_addr) >> 16) >> 16
))), 0));
6237 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1f41), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1f41)), (1), 0));
6238
6239 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6240 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6241 }
6242 /* Switch to pipe 0 */
6243 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6244 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6245 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6246
6247 /* start the ring */
6248 gfx_v10_0_cp_gfx_start(adev);
6249
6250 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6251 ring = &adev->gfx.gfx_ring[i];
6252 ring->sched.ready = true1;
6253 }
6254
6255 return 0;
6256}
6257
6258static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool_Bool enable)
6259{
6260 if (enable) {
6261 switch (adev->ip_versions[GC_HWIP][0]) {
6262 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
6263 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
6264 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
6265 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
6266 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
6267 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
6268 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
6269 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
6270 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f55), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0f55)), (0), 0));
6271 break;
6272 default:
6273 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0e2d), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0e2d)), (0), 0));
6274 break;
6275 }
6276 } else {
6277 switch (adev->ip_versions[GC_HWIP][0]) {
6278 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
6279 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
6280 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
6281 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
6282 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
6283 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
6284 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
6285 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
6286 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f55), (0x40000000L | 0x10000000L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0f55)), ((0x40000000L
| 0x10000000L)), 0))
6287 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f55), (0x40000000L | 0x10000000L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0f55)), ((0x40000000L
| 0x10000000L)), 0))
6288 CP_MEC_CNTL__MEC_ME2_HALT_MASK))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f55), (0x40000000L | 0x10000000L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0f55)), ((0x40000000L
| 0x10000000L)), 0));
6289 break;
6290 default:
6291 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0e2d), (0x40000000L | 0x10000000L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0e2d)), ((0x40000000L
| 0x10000000L)), 0))
6292 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0e2d), (0x40000000L | 0x10000000L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0e2d)), ((0x40000000L
| 0x10000000L)), 0))
6293 CP_MEC_CNTL__MEC_ME2_HALT_MASK))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0e2d), (0x40000000L | 0x10000000L), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x0e2d)), ((0x40000000L
| 0x10000000L)), 0));
6294 break;
6295 }
6296 adev->gfx.kiq.ring.sched.ready = false0;
6297 }
6298 udelay(50);
6299}
6300
6301static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6302{
6303 const struct gfx_firmware_header_v1_0 *mec_hdr;
6304 const __le32 *fw_data;
6305 unsigned i;
6306 u32 tmp;
6307 u32 usec_timeout = 50000; /* Wait for 50 ms */
6308
6309 if (!adev->gfx.mec_fw)
6310 return -EINVAL22;
6311
6312 gfx_v10_0_cp_compute_enable(adev, false0);
6313
6314 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6315 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6316
6317 fw_data = (const __le32 *)
6318 (adev->gfx.mec_fw->data +
6319 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)((__uint32_t)(mec_hdr->header.ucode_array_offset_bytes)));
6320
6321 /* Trigger an invalidation of the L1 instruction caches */
6322 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584f), 0));
6323 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
6324 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584f), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x584f)), (tmp), 0));
6325
6326 /* Wait for invalidation complete */
6327 for (i = 0; i < usec_timeout; i++) {
6328 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584f), 0));
6329 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,(((tmp) & 0x00000002L) >> 0x1)
6330 INVALIDATE_CACHE_COMPLETE)(((tmp) & 0x00000002L) >> 0x1))
6331 break;
6332 udelay(1);
6333 }
6334
6335 if (i >= usec_timeout) {
6336 dev_err(adev->dev, "failed to invalidate instruction cache\n")printf("drm:pid%d:%s *ERROR* " "failed to invalidate instruction cache\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
6337 return -EINVAL22;
6338 }
6339
6340 if (amdgpu_emu_mode == 1)
6341 adev->hdp.funcs->flush_hdp(adev, NULL((void *)0));
6342
6343 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x584e, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x584e), 0));
6344 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
6345 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0)(((tmp) & ~0x00800000L) | (0x00800000L & ((0) <<
0x17)));
6346 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1)(((tmp) & ~0x00000010L) | (0x00000010L & ((1) <<
0x4)));
6347 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584e), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x584e)), (tmp), 0));
6348
6349 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584c), adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x584c)), (adev->gfx.mec.mec_fw_gpu_addr
& 0xFFFFF000), 0))
6350 0xFFFFF000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584c), adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000
, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][1] + 0x584c)), (adev->gfx.mec.mec_fw_gpu_addr
& 0xFFFFF000), 0));
6351 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584d), ((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x584d)), (((u32)(((adev
->gfx.mec.mec_fw_gpu_addr) >> 16) >> 16))), 0)
)
6352 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x584d), ((u32)(((adev->gfx.mec.mec_fw_gpu_addr) >>
16) >> 16)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x584d)), (((u32)(((adev
->gfx.mec.mec_fw_gpu_addr) >> 16) >> 16))), 0)
);
6353
6354 /* MEC1 */
6355 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x581a), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x581a)), (0), 0));
6356
6357 for (i = 0; i < mec_hdr->jt_size; i++)
6358 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x581b), ((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr
->jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][1] + 0x581b)), (((__uint32_t
)(*(__uint32_t *)(fw_data + mec_hdr->jt_offset + i)))), 0)
)
6359 le32_to_cpup(fw_data + mec_hdr->jt_offset + i))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x581b), ((__uint32_t)(*(__uint32_t *)(fw_data + mec_hdr
->jt_offset + i))), 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][1] + 0x581b)), (((__uint32_t
)(*(__uint32_t *)(fw_data + mec_hdr->jt_offset + i)))), 0)
);
6360
6361 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x581a), adev->gfx.mec_fw_version, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x581a)), (adev
->gfx.mec_fw_version), 0));
6362
6363 /*
6364 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6365 * different microcode than MEC1.
6366 */
6367
6368 return 0;
6369}
6370
6371static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6372{
6373 uint32_t tmp;
6374 struct amdgpu_device *adev = ring->adev;
6375
6376 /* tell RLC which is KIQ queue */
6377 switch (adev->ip_versions[GC_HWIP][0]) {
6378 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
6379 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
6380 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
6381 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
6382 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
6383 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
6384 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
6385 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
6386 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4ca1, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4ca1), 0));
6387 tmp &= 0xffffff00;
6388 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6389 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca1), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4ca1)), (tmp), 0));
6390 tmp |= 0x80;
6391 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca1), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4ca1)), (tmp), 0));
6392 break;
6393 default:
6394 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4caa, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4caa), 0));
6395 tmp &= 0xffffff00;
6396 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6397 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4caa), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4caa)), (tmp), 0));
6398 tmp |= 0x80;
6399 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4caa), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4caa)), (tmp), 0));
6400 break;
6401 }
6402}
6403
6404static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6405 struct v10_gfx_mqd *mqd,
6406 struct amdgpu_mqd_prop *prop)
6407{
6408 bool_Bool priority = 0;
6409 u32 tmp;
6410
6411 /* set up default queue priority level
6412 * 0x0 = low priority, 0x1 = high priority
6413 */
6414 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6415 priority = 1;
6416
6417 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e84, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e84), 0));
6418 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((priority) <<
0x0)));
6419 mqd->cp_gfx_hqd_queue_priority = tmp;
6420}
6421
6422static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6423 struct amdgpu_mqd_prop *prop)
6424{
6425 struct v10_gfx_mqd *mqd = m;
6426 uint64_t hqd_gpu_addr, wb_gpu_addr;
6427 uint32_t tmp;
6428 uint32_t rb_bufsz;
6429
6430 /* set up gfx hqd wptr */
6431 mqd->cp_gfx_hqd_wptr = 0;
6432 mqd->cp_gfx_hqd_wptr_hi = 0;
6433
6434 /* set the pointer to the MQD */
6435 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6436 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr)((u32)(((prop->mqd_gpu_addr) >> 16) >> 16));
6437
6438 /* set up mqd control */
6439 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e9a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e9a), 0));
6440 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6441 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x00000100L) | (0x00000100L & ((1) <<
0x8)));
6442 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0)(((tmp) & ~0x03000000L) | (0x03000000L & ((0) <<
0x18)));
6443 mqd->cp_gfx_mqd_control = tmp;
6444
6445 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6446 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e81, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e81), 0));
6447 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6448 mqd->cp_gfx_hqd_vmid = 0;
6449
6450 /* set up gfx queue priority */
6451 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6452
6453 /* set up time quantum */
6454 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e85, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e85), 0));
6455 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1)(((tmp) & ~0x00000001L) | (0x00000001L & ((1) <<
0x0)));
6456 mqd->cp_gfx_hqd_quantum = tmp;
6457
6458 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6459 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6460 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6461 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16));
6462
6463 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6464 wb_gpu_addr = prop->rptr_gpu_addr;
6465 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6466 mqd->cp_gfx_hqd_rptr_addr_hi =
6467 upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6468
6469 /* set up rb_wptr_poll addr */
6470 wb_gpu_addr = prop->wptr_gpu_addr;
6471 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6472 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6473
6474 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6475 rb_bufsz = order_base_2(prop->queue_size / 4)drm_order(prop->queue_size / 4) - 1;
6476 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e8f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e8f), 0));
6477 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz)(((tmp) & ~0x0000003FL) | (0x0000003FL & ((rb_bufsz) <<
0x0)));
6478 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2)(((tmp) & ~0x00003F00L) | (0x00003F00L & ((rb_bufsz -
2) << 0x8)));
6479#ifdef __BIG_ENDIAN
6480 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1)(((tmp) & ~0x00030000L) | (0x00030000L & ((1) <<
0x10)));
6481#endif
6482 mqd->cp_gfx_hqd_cntl = tmp;
6483
6484 /* set up cp_doorbell_control */
6485 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e8d, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e8d), 0));
6486 if (prop->use_doorbell) {
6487 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((prop->doorbell_index
) << 0x2)))
6488 DOORBELL_OFFSET, prop->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((prop->doorbell_index
) << 0x2)));
6489 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
6490 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6491 } else
6492 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
6493 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
6494 mqd->cp_rb_doorbell_control = tmp;
6495
6496 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6497 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e88, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e88), 0));
6498
6499 /* active the queue */
6500 mqd->cp_gfx_hqd_active = 1;
6501
6502 return 0;
6503}
6504
6505#ifdef BRING_UP_DEBUG
6506static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6507{
6508 struct amdgpu_device *adev = ring->adev;
6509 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6510
6511 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6512 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e91), mqd->cp_gfx_hqd_wptr, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e91)), (mqd->
cp_gfx_hqd_wptr), 0));
6513 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e92), mqd->cp_gfx_hqd_wptr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e92)), (mqd->
cp_gfx_hqd_wptr_hi), 0));
6514
6515 /* set GFX_MQD_BASE */
6516 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fa9), mqd->cp_mqd_base_addr, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fa9)), (mqd->
cp_mqd_base_addr), 0));
6517 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1faa), mqd->cp_mqd_base_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1faa)), (mqd->
cp_mqd_base_addr_hi), 0));
6518
6519 /* set GFX_MQD_CONTROL */
6520 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e9a), mqd->cp_gfx_mqd_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e9a)), (mqd->
cp_gfx_mqd_control), 0));
6521
6522 /* set GFX_HQD_VMID to 0 */
6523 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e81), mqd->cp_gfx_hqd_vmid, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e81)), (mqd->
cp_gfx_hqd_vmid), 0));
6524
6525 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e84), mqd->cp_gfx_hqd_queue_priority, 0, GC_HWIP) :
amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0
] + 0x1e84)), (mqd->cp_gfx_hqd_queue_priority), 0))
6526 mqd->cp_gfx_hqd_queue_priority)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e84), mqd->cp_gfx_hqd_queue_priority, 0, GC_HWIP) :
amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0][0
] + 0x1e84)), (mqd->cp_gfx_hqd_queue_priority), 0));
6527 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e85), mqd->cp_gfx_hqd_quantum, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e85)), (mqd->
cp_gfx_hqd_quantum), 0));
6528
6529 /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6530 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e86), mqd->cp_gfx_hqd_base, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e86)), (mqd->
cp_gfx_hqd_base), 0));
6531 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e87), mqd->cp_gfx_hqd_base_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e87)), (mqd->
cp_gfx_hqd_base_hi), 0));
6532
6533 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6534 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e89), mqd->cp_gfx_hqd_rptr_addr, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e89)), (mqd->
cp_gfx_hqd_rptr_addr), 0));
6535 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8a), mqd->cp_gfx_hqd_rptr_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8a)), (mqd->
cp_gfx_hqd_rptr_addr_hi), 0));
6536
6537 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6538 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8f), mqd->cp_gfx_hqd_cntl, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8f)), (mqd->
cp_gfx_hqd_cntl), 0));
6539
6540 /* set RB_WPTR_POLL_ADDR */
6541 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8b), mqd->cp_rb_wptr_poll_addr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8b)), (mqd->
cp_rb_wptr_poll_addr_lo), 0));
6542 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8c), mqd->cp_rb_wptr_poll_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8c)), (mqd->
cp_rb_wptr_poll_addr_hi), 0));
6543
6544 /* set RB_DOORBELL_CONTROL */
6545 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e8d), mqd->cp_rb_doorbell_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e8d)), (mqd->
cp_rb_doorbell_control), 0));
6546
6547 /* active the queue */
6548 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e80), mqd->cp_gfx_hqd_active, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e80)), (mqd->
cp_gfx_hqd_active), 0));
6549
6550 return 0;
6551}
6552#endif
6553
6554static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6555{
6556 struct amdgpu_device *adev = ring->adev;
6557 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6558 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6559
6560 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6561 memset((void *)mqd, 0, sizeof(*mqd))__builtin_memset(((void *)mqd), (0), (sizeof(*mqd)));
6562 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6563 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6564 amdgpu_ring_init_mqd(ring);
6565
6566 /*
6567 * if there are 2 gfx rings, set the lower doorbell
6568 * range of the first ring, otherwise the range of
6569 * the second ring will override the first ring
6570 */
6571 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6572 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6573
6574#ifdef BRING_UP_DEBUG
6575 gfx_v10_0_gfx_queue_init_register(ring);
6576#endif
6577 nv_grbm_select(adev, 0, 0, 0, 0);
6578 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6579 if (adev->gfx.me.mqd_backup[mqd_idx])
6580 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd))__builtin_memcpy((adev->gfx.me.mqd_backup[mqd_idx]), (mqd)
, (sizeof(*mqd)));
6581 } else if (amdgpu_in_reset(adev)) {
6582 /* reset mqd with the backup copy */
6583 if (adev->gfx.me.mqd_backup[mqd_idx])
6584 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd))__builtin_memcpy((mqd), (adev->gfx.me.mqd_backup[mqd_idx])
, (sizeof(*mqd)));
6585 /* reset the ring */
6586 ring->wptr = 0;
6587 *ring->wptr_cpu_addr = 0;
6588 amdgpu_ring_clear_ring(ring);
6589#ifdef BRING_UP_DEBUG
6590 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6591 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6592 gfx_v10_0_gfx_queue_init_register(ring);
6593 nv_grbm_select(adev, 0, 0, 0, 0);
6594 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6595#endif
6596 } else {
6597 amdgpu_ring_clear_ring(ring);
6598 }
6599
6600 return 0;
6601}
6602
6603#ifndef BRING_UP_DEBUG
6604static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6605{
6606 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6607 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6608 int r, i;
6609
6610 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6611 return -EINVAL22;
6612
6613 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6614 adev->gfx.num_gfx_rings);
6615 if (r) {
6616 DRM_ERROR("Failed to lock KIQ (%d).\n", r)__drm_err("Failed to lock KIQ (%d).\n", r);
6617 return r;
6618 }
6619
6620 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6621 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6622
6623 return amdgpu_ring_test_helper(kiq_ring);
6624}
6625#endif
6626
6627static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6628{
6629 int r, i;
6630 struct amdgpu_ring *ring;
6631
6632 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6633 ring = &adev->gfx.gfx_ring[i];
6634
6635 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
6636 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6637 goto done;
6638
6639 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6640 if (!r) {
6641 r = gfx_v10_0_gfx_init_queue(ring);
6642 amdgpu_bo_kunmap(ring->mqd_obj);
6643 ring->mqd_ptr = NULL((void *)0);
6644 }
6645 amdgpu_bo_unreserve(ring->mqd_obj);
6646 if (r)
6647 goto done;
6648 }
6649#ifndef BRING_UP_DEBUG
6650 r = gfx_v10_0_kiq_enable_kgq(adev);
6651 if (r)
6652 goto done;
6653#endif
6654 r = gfx_v10_0_cp_gfx_start(adev);
6655 if (r)
6656 goto done;
6657
6658 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6659 ring = &adev->gfx.gfx_ring[i];
6660 ring->sched.ready = true1;
6661 }
6662done:
6663 return r;
6664}
6665
6666static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6667 struct amdgpu_mqd_prop *prop)
6668{
6669 struct v10_compute_mqd *mqd = m;
6670 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6671 uint32_t tmp;
6672
6673 mqd->header = 0xC0310800;
6674 mqd->compute_pipelinestat_enable = 0x00000001;
6675 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6676 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6677 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6678 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6679 mqd->compute_misc_reserved = 0x00000003;
6680
6681 eop_base_addr = prop->eop_gpu_addr >> 8;
6682 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6683 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr)((u32)(((eop_base_addr) >> 16) >> 16));
6684
6685 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6686 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fd0, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fd0), 0));
6687 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(2048 / 4) - 1)) << 0x0)))
6688 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(2048 / 4) - 1)) << 0x0)));
6689
6690 mqd->cp_hqd_eop_control = tmp;
6691
6692 /* enable doorbell? */
6693 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fb8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fb8), 0));
6694
6695 if (prop->use_doorbell) {
6696 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((prop->doorbell_index
) << 0x2)))
6697 DOORBELL_OFFSET, prop->doorbell_index)(((tmp) & ~0x0FFFFFFCL) | (0x0FFFFFFCL & ((prop->doorbell_index
) << 0x2)));
6698 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)))
6699 DOORBELL_EN, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6700 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)))
6701 DOORBELL_SOURCE, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
6702 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)))
6703 DOORBELL_HIT, 0)(((tmp) & ~0x80000000L) | (0x80000000L & ((0) <<
0x1f)));
6704 } else {
6705 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)))
6706 DOORBELL_EN, 0)(((tmp) & ~0x40000000L) | (0x40000000L & ((0) <<
0x1e)));
6707 }
6708
6709 mqd->cp_hqd_pq_doorbell_control = tmp;
6710
6711 /* disable the queue if it's active */
6712 mqd->cp_hqd_dequeue_request = 0;
6713 mqd->cp_hqd_pq_rptr = 0;
6714 mqd->cp_hqd_pq_wptr_lo = 0;
6715 mqd->cp_hqd_pq_wptr_hi = 0;
6716
6717 /* set the pointer to the MQD */
6718 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6719 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr)((u32)(((prop->mqd_gpu_addr) >> 16) >> 16));
6720
6721 /* set MQD vmid to 0 */
6722 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fcb, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fcb), 0));
6723 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0)(((tmp) & ~0x0000000FL) | (0x0000000FL & ((0) <<
0x0)));
6724 mqd->cp_mqd_control = tmp;
6725
6726 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6727 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6728 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6729 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr)((u32)(((hqd_gpu_addr) >> 16) >> 16));
6730
6731 /* set up the HQD, this is similar to CP_RB0_CNTL */
6732 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fba, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fba), 0));
6733 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(prop->queue_size / 4) - 1)) << 0x0)))
6734 (order_base_2(prop->queue_size / 4) - 1))(((tmp) & ~0x0000003FL) | (0x0000003FL & (((drm_order
(prop->queue_size / 4) - 1)) << 0x0)));
6735 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,(((tmp) & ~0x00003F00L) | (0x00003F00L & (((drm_order
(4096 / 4) - 1)) << 0x8)))
6736 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1))(((tmp) & ~0x00003F00L) | (0x00003F00L & (((drm_order
(4096 / 4) - 1)) << 0x8)));
6737#ifdef __BIG_ENDIAN
6738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1)(((tmp) & ~0x00030000L) | (0x00030000L & ((1) <<
0x10)));
6739#endif
6740 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0)(((tmp) & ~0x10000000L) | (0x10000000L & ((0) <<
0x1c)));
6741 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
6742 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1)(((tmp) & ~0x40000000L) | (0x40000000L & ((1) <<
0x1e)));
6743 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1)(((tmp) & ~0x80000000L) | (0x80000000L & ((1) <<
0x1f)));
6744 mqd->cp_hqd_pq_control = tmp;
6745
6746 /* set the wb address whether it's enabled or not */
6747 wb_gpu_addr = prop->rptr_gpu_addr;
6748 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6749 mqd->cp_hqd_pq_rptr_report_addr_hi =
6750 upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6751
6752 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6753 wb_gpu_addr = prop->wptr_gpu_addr;
6754 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6755 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr)((u32)(((wb_gpu_addr) >> 16) >> 16)) & 0xffff;
6756
6757 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6758 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fb3, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fb3), 0));
6759
6760 /* set the vmid for the queue */
6761 mqd->cp_hqd_vmid = 0;
6762
6763 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fad, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fad), 0));
6764 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53)(((tmp) & ~0x0003FF00L) | (0x0003FF00L & ((0x53) <<
0x8)));
6765 mqd->cp_hqd_persistent_state = tmp;
6766
6767 /* set MIN_IB_AVAIL_SIZE */
6768 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fbe, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fbe), 0));
6769 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3)(((tmp) & ~0x00300000L) | (0x00300000L & ((3) <<
0x14)));
6770 mqd->cp_hqd_ib_control = tmp;
6771
6772 /* set static priority for a compute queue/ring */
6773 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6774 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6775
6776 mqd->cp_hqd_active = prop->hqd_active;
6777
6778 return 0;
6779}
6780
6781static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6782{
6783 struct amdgpu_device *adev = ring->adev;
6784 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6785 int j;
6786
6787 /* inactivate the queue */
6788 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
6789 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fab), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1fab)), (0), 0));
6790
6791 /* disable wptr polling */
6792 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e23, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e23, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e23), 0)) & ~0x80000000L) |
(0) << 0x1f, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev
->reg_offset[GC_HWIP][0][0] + 0x1e23), ((((((adev)->virt
.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][0] + 0x1e23, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[0] + 0x1e23), 0)) & ~0x80000000L) | (0) << 0x1f), 0
));
6793
6794 /* disable the queue if it's active */
6795 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fab, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fab), 0)) & 1) {
6796 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fc1), 1, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1fc1)), (1), 0));
6797 for (j = 0; j < adev->usec_timeout; j++) {
6798 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1fab, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1fab), 0)) & 1))
6799 break;
6800 udelay(1);
6801 }
6802 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fc1), mqd->cp_hqd_dequeue_request, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fc1)), (mqd->
cp_hqd_dequeue_request), 0))
6803 mqd->cp_hqd_dequeue_request)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fc1), mqd->cp_hqd_dequeue_request, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fc1)), (mqd->
cp_hqd_dequeue_request), 0));
6804 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb3), mqd->cp_hqd_pq_rptr, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fb3)), (mqd->
cp_hqd_pq_rptr), 0))
6805 mqd->cp_hqd_pq_rptr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb3), mqd->cp_hqd_pq_rptr, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fb3)), (mqd->
cp_hqd_pq_rptr), 0));
6806 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fdf), mqd->cp_hqd_pq_wptr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fdf)), (mqd->
cp_hqd_pq_wptr_lo), 0))
6807 mqd->cp_hqd_pq_wptr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fdf), mqd->cp_hqd_pq_wptr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fdf)), (mqd->
cp_hqd_pq_wptr_lo), 0));
6808 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fe0), mqd->cp_hqd_pq_wptr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fe0)), (mqd->
cp_hqd_pq_wptr_hi), 0))
6809 mqd->cp_hqd_pq_wptr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fe0), mqd->cp_hqd_pq_wptr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fe0)), (mqd->
cp_hqd_pq_wptr_hi), 0));
6810 }
6811
6812 /* disable doorbells */
6813 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb8), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1fb8)), (0), 0));
6814
6815 /* write the EOP addr */
6816 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fce), mqd->cp_hqd_eop_base_addr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fce)), (mqd->
cp_hqd_eop_base_addr_lo), 0))
6817 mqd->cp_hqd_eop_base_addr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fce), mqd->cp_hqd_eop_base_addr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fce)), (mqd->
cp_hqd_eop_base_addr_lo), 0));
6818 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fcf), mqd->cp_hqd_eop_base_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fcf)), (mqd->
cp_hqd_eop_base_addr_hi), 0))
6819 mqd->cp_hqd_eop_base_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fcf), mqd->cp_hqd_eop_base_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fcf)), (mqd->
cp_hqd_eop_base_addr_hi), 0));
6820
6821 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6822 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fd0), mqd->cp_hqd_eop_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fd0)), (mqd->
cp_hqd_eop_control), 0))
6823 mqd->cp_hqd_eop_control)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fd0), mqd->cp_hqd_eop_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fd0)), (mqd->
cp_hqd_eop_control), 0));
6824
6825 /* set the pointer to the MQD */
6826 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fa9), mqd->cp_mqd_base_addr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fa9)), (mqd->
cp_mqd_base_addr_lo), 0))
6827 mqd->cp_mqd_base_addr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fa9), mqd->cp_mqd_base_addr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fa9)), (mqd->
cp_mqd_base_addr_lo), 0));
6828 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1faa), mqd->cp_mqd_base_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1faa)), (mqd->
cp_mqd_base_addr_hi), 0))
6829 mqd->cp_mqd_base_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1faa), mqd->cp_mqd_base_addr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1faa)), (mqd->
cp_mqd_base_addr_hi), 0));
6830
6831 /* set MQD vmid to 0 */
6832 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fcb), mqd->cp_mqd_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fcb)), (mqd->
cp_mqd_control), 0))
6833 mqd->cp_mqd_control)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fcb), mqd->cp_mqd_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fcb)), (mqd->
cp_mqd_control), 0));
6834
6835 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6836 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb1), mqd->cp_hqd_pq_base_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fb1)), (mqd->
cp_hqd_pq_base_lo), 0))
6837 mqd->cp_hqd_pq_base_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb1), mqd->cp_hqd_pq_base_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fb1)), (mqd->
cp_hqd_pq_base_lo), 0));
6838 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb2), mqd->cp_hqd_pq_base_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fb2)), (mqd->
cp_hqd_pq_base_hi), 0))
6839 mqd->cp_hqd_pq_base_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb2), mqd->cp_hqd_pq_base_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fb2)), (mqd->
cp_hqd_pq_base_hi), 0));
6840
6841 /* set up the HQD, this is similar to CP_RB0_CNTL */
6842 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fba), mqd->cp_hqd_pq_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fba)), (mqd->
cp_hqd_pq_control), 0))
6843 mqd->cp_hqd_pq_control)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fba), mqd->cp_hqd_pq_control, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fba)), (mqd->
cp_hqd_pq_control), 0));
6844
6845 /* set the wb address whether it's enabled or not */
6846 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb4), mqd->cp_hqd_pq_rptr_report_addr_lo, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb4)), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0))
6847 mqd->cp_hqd_pq_rptr_report_addr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb4), mqd->cp_hqd_pq_rptr_report_addr_lo, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb4)), (mqd->cp_hqd_pq_rptr_report_addr_lo), 0));
6848 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb5), mqd->cp_hqd_pq_rptr_report_addr_hi, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb5)), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0))
6849 mqd->cp_hqd_pq_rptr_report_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb5), mqd->cp_hqd_pq_rptr_report_addr_hi, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb5)), (mqd->cp_hqd_pq_rptr_report_addr_hi), 0));
6850
6851 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6852 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb6), mqd->cp_hqd_pq_wptr_poll_addr_lo, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb6)), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0))
6853 mqd->cp_hqd_pq_wptr_poll_addr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb6), mqd->cp_hqd_pq_wptr_poll_addr_lo, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb6)), (mqd->cp_hqd_pq_wptr_poll_addr_lo), 0));
6854 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb7), mqd->cp_hqd_pq_wptr_poll_addr_hi, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb7)), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0))
6855 mqd->cp_hqd_pq_wptr_poll_addr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb7), mqd->cp_hqd_pq_wptr_poll_addr_hi, 0, GC_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0
][0] + 0x1fb7)), (mqd->cp_hqd_pq_wptr_poll_addr_hi), 0));
6856
6857 /* enable the doorbell if requested */
6858 if (ring->use_doorbell) {
6859 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfc), (adev->doorbell_index.kiq * 2) << 2, 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1dfc)), ((adev->doorbell_index.kiq * 2) <<
2), 0))
6860 (adev->doorbell_index.kiq * 2) << 2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfc), (adev->doorbell_index.kiq * 2) << 2, 0
, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP
][0][0] + 0x1dfc)), ((adev->doorbell_index.kiq * 2) <<
2), 0));
6861 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfd), (adev->doorbell_index.userqueue_end * 2) <<
2, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1dfd)), ((adev->doorbell_index.userqueue_end
* 2) << 2), 0))
6862 (adev->doorbell_index.userqueue_end * 2) << 2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1dfd), (adev->doorbell_index.userqueue_end * 2) <<
2, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1dfd)), ((adev->doorbell_index.userqueue_end
* 2) << 2), 0));
6863 }
6864
6865 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb8), mqd->cp_hqd_pq_doorbell_control, 0, GC_HWIP)
: amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0]
[0] + 0x1fb8)), (mqd->cp_hqd_pq_doorbell_control), 0))
6866 mqd->cp_hqd_pq_doorbell_control)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fb8), mqd->cp_hqd_pq_doorbell_control, 0, GC_HWIP)
: amdgpu_device_wreg(adev, ((adev->reg_offset[GC_HWIP][0]
[0] + 0x1fb8)), (mqd->cp_hqd_pq_doorbell_control), 0));
6867
6868 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6869 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fdf), mqd->cp_hqd_pq_wptr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fdf)), (mqd->
cp_hqd_pq_wptr_lo), 0))
6870 mqd->cp_hqd_pq_wptr_lo)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fdf), mqd->cp_hqd_pq_wptr_lo, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fdf)), (mqd->
cp_hqd_pq_wptr_lo), 0));
6871 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fe0), mqd->cp_hqd_pq_wptr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fe0)), (mqd->
cp_hqd_pq_wptr_hi), 0))
6872 mqd->cp_hqd_pq_wptr_hi)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fe0), mqd->cp_hqd_pq_wptr_hi, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fe0)), (mqd->
cp_hqd_pq_wptr_hi), 0));
6873
6874 /* set the vmid for the queue */
6875 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fac), mqd->cp_hqd_vmid, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fac)), (mqd->
cp_hqd_vmid), 0));
6876
6877 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fad), mqd->cp_hqd_persistent_state, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fad)), (mqd->
cp_hqd_persistent_state), 0))
6878 mqd->cp_hqd_persistent_state)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fad), mqd->cp_hqd_persistent_state, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fad)), (mqd->
cp_hqd_persistent_state), 0));
6879
6880 /* activate the queue */
6881 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fab), mqd->cp_hqd_active, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fab)), (mqd->
cp_hqd_active), 0))
6882 mqd->cp_hqd_active)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1fab), mqd->cp_hqd_active, 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1fab)), (mqd->
cp_hqd_active), 0));
6883
6884 if (ring->use_doorbell)
6885 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e58, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e58, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e58), 0)) & ~0x00000002L) |
(1) << 0x1, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev
->reg_offset[GC_HWIP][0][0] + 0x1e58), ((((((adev)->virt
.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][0] + 0x1e58, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[0] + 0x1e58), 0)) & ~0x00000002L) | (1) << 0x1), 0
));
6886
6887 return 0;
6888}
6889
6890static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6891{
6892 struct amdgpu_device *adev = ring->adev;
6893 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6894 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS8;
6895
6896 gfx_v10_0_kiq_setting(ring);
6897
6898 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6899 /* reset MQD to a clean status */
6900 if (adev->gfx.mec.mqd_backup[mqd_idx])
6901 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx]
), (sizeof(*mqd)));
6902
6903 /* reset ring buffer */
6904 ring->wptr = 0;
6905 amdgpu_ring_clear_ring(ring);
6906
6907 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6908 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6909 gfx_v10_0_kiq_init_register(ring);
6910 nv_grbm_select(adev, 0, 0, 0, 0);
6911 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6912 } else {
6913 memset((void *)mqd, 0, sizeof(*mqd))__builtin_memset(((void *)mqd), (0), (sizeof(*mqd)));
6914 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6915 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6916 amdgpu_ring_init_mqd(ring);
6917 gfx_v10_0_kiq_init_register(ring);
6918 nv_grbm_select(adev, 0, 0, 0, 0);
6919 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6920
6921 if (adev->gfx.mec.mqd_backup[mqd_idx])
6922 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd
), (sizeof(*mqd)));
6923 }
6924
6925 return 0;
6926}
6927
6928static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6929{
6930 struct amdgpu_device *adev = ring->adev;
6931 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6932 int mqd_idx = ring - &adev->gfx.compute_ring[0];
6933
6934 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6935 memset((void *)mqd, 0, sizeof(*mqd))__builtin_memset(((void *)mqd), (0), (sizeof(*mqd)));
6936 mutex_lock(&adev->srbm_mutex)rw_enter_write(&adev->srbm_mutex);
6937 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6938 amdgpu_ring_init_mqd(ring);
6939 nv_grbm_select(adev, 0, 0, 0, 0);
6940 mutex_unlock(&adev->srbm_mutex)rw_exit_write(&adev->srbm_mutex);
6941
6942 if (adev->gfx.mec.mqd_backup[mqd_idx])
6943 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd))__builtin_memcpy((adev->gfx.mec.mqd_backup[mqd_idx]), (mqd
), (sizeof(*mqd)));
6944 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6945 /* reset MQD to a clean status */
6946 if (adev->gfx.mec.mqd_backup[mqd_idx])
6947 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd))__builtin_memcpy((mqd), (adev->gfx.mec.mqd_backup[mqd_idx]
), (sizeof(*mqd)));
6948
6949 /* reset ring buffer */
6950 ring->wptr = 0;
6951 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
0)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; });
6952 amdgpu_ring_clear_ring(ring);
6953 } else {
6954 amdgpu_ring_clear_ring(ring);
6955 }
6956
6957 return 0;
6958}
6959
6960static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6961{
6962 struct amdgpu_ring *ring;
6963 int r;
6964
6965 ring = &adev->gfx.kiq.ring;
6966
6967 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
6968 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6969 return r;
6970
6971 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6972 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0)) {
6973 amdgpu_bo_unreserve(ring->mqd_obj);
6974 return r;
6975 }
6976
6977 gfx_v10_0_kiq_init_queue(ring);
6978 amdgpu_bo_kunmap(ring->mqd_obj);
6979 ring->mqd_ptr = NULL((void *)0);
6980 amdgpu_bo_unreserve(ring->mqd_obj);
6981 ring->sched.ready = true1;
6982 return 0;
6983}
6984
6985static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6986{
6987 struct amdgpu_ring *ring = NULL((void *)0);
6988 int r = 0, i;
6989
6990 gfx_v10_0_cp_compute_enable(adev, true1);
6991
6992 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6993 ring = &adev->gfx.compute_ring[i];
6994
6995 r = amdgpu_bo_reserve(ring->mqd_obj, false0);
6996 if (unlikely(r != 0)__builtin_expect(!!(r != 0), 0))
6997 goto done;
6998 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6999 if (!r) {
7000 r = gfx_v10_0_kcq_init_queue(ring);
7001 amdgpu_bo_kunmap(ring->mqd_obj);
7002 ring->mqd_ptr = NULL((void *)0);
7003 }
7004 amdgpu_bo_unreserve(ring->mqd_obj);
7005 if (r)
7006 goto done;
7007 }
7008
7009 r = amdgpu_gfx_enable_kcq(adev);
7010done:
7011 return r;
7012}
7013
7014static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7015{
7016 int r, i;
7017 struct amdgpu_ring *ring;
7018
7019 if (!(adev->flags & AMD_IS_APU))
7020 gfx_v10_0_enable_gui_idle_interrupt(adev, false0);
7021
7022 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7023 /* legacy firmware loading */
7024 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7025 if (r)
7026 return r;
7027
7028 r = gfx_v10_0_cp_compute_load_microcode(adev);
7029 if (r)
7030 return r;
7031 }
7032
7033 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7034 r = amdgpu_mes_kiq_hw_init(adev)(adev)->mes.kiq_hw_init((adev));
7035 else
7036 r = gfx_v10_0_kiq_resume(adev);
7037 if (r)
7038 return r;
7039
7040 r = gfx_v10_0_kcq_resume(adev);
7041 if (r)
7042 return r;
7043
7044 if (!amdgpu_async_gfx_ring) {
7045 r = gfx_v10_0_cp_gfx_resume(adev);
7046 if (r)
7047 return r;
7048 } else {
7049 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7050 if (r)
7051 return r;
7052 }
7053
7054 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7055 ring = &adev->gfx.gfx_ring[i];
7056 r = amdgpu_ring_test_helper(ring);
7057 if (r)
7058 return r;
7059 }
7060
7061 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7062 ring = &adev->gfx.compute_ring[i];
7063 r = amdgpu_ring_test_helper(ring);
7064 if (r)
7065 return r;
7066 }
7067
7068 return 0;
7069}
7070
7071static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool_Bool enable)
7072{
7073 gfx_v10_0_cp_gfx_enable(adev, enable);
7074 gfx_v10_0_cp_compute_enable(adev, enable);
7075}
7076
7077static bool_Bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7078{
7079 uint32_t data, pattern = 0xDEADBEEF;
7080
7081 /* check if mmVGT_ESGS_RING_SIZE_UMD
7082 * has been remapped to mmVGT_ESGS_RING_SIZE */
7083 switch (adev->ip_versions[GC_HWIP][0]) {
7084 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
7085 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
7086 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
7087 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
7088 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0fc1, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0fc1), 0));
7089 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0fc1), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0fc1)), (0), 0));
7090 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2240), pattern, 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][1] + 0x2240)), (pattern), 0
));
7091
7092 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0fc1, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0fc1), 0)) == pattern) {
7093 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2240), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x2240)), (data), 0));
7094 return true1;
7095 } else {
7096 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0fc1), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x0fc1)), (data), 0));
7097 return false0;
7098 }
7099 break;
7100 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7101 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7102 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7103 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
7104 return true1;
7105 default:
7106 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0fd2, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0fd2), 0));
7107 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0fd2), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0fd2)), (0), 0));
7108 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2240), pattern, 0, GC_HWIP) : amdgpu_device_wreg(adev,
((adev->reg_offset[GC_HWIP][0][1] + 0x2240)), (pattern), 0
));
7109
7110 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0fd2, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0fd2), 0)) == pattern) {
7111 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2240), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x2240)), (data), 0));
7112 return true1;
7113 } else {
7114 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0fd2), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x0fd2)), (data), 0));
7115 return false0;
7116 }
7117 break;
7118 }
7119}
7120
7121static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7122{
7123 uint32_t data;
7124
7125 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
7126 return;
7127
7128 /* initialize cam_index to 0
7129 * index will auto-inc after each data writting */
7130 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a04), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a04)), (0), 0));
7131
7132 switch (adev->ip_versions[GC_HWIP][0]) {
7133 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
7134 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
7135 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7136 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
7137 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
7138 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7139 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7140 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
7141 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7142 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224e) <<
7143 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7144 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc3) <<
7145 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7146 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7147 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7148
7149 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7150 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2250) <<
7151 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7152 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc5) <<
7153 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7154 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7155 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7156
7157 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7158 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2261) <<
7159 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7160 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc6) <<
7161 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7162 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7163 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7164
7165 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7166 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224f) <<
7167 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7168 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc4) <<
7169 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7170 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7171 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7172
7173 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7174 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2240) <<
7175 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7176 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc1) <<
7177 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7178 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7179 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7180
7181 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7182 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2241) <<
7183 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7184 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x0fc2) <<
7185 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7186 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7187 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7188
7189 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7190 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP)(adev->reg_offset[GC_HWIP][0][1] + 0x2440) <<
7191 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7192 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid)(adev->reg_offset[GC_HWIP][0][0] + 0x11ec) <<
7193 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7194 break;
7195 default:
7196 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7197 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224e) <<
7198 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7199 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x1002) <<
7200 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7201 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7202 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7203
7204 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7205 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2250) <<
7206 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7207 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE)(adev->reg_offset[GC_HWIP][0][0] + 0x100e) <<
7208 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7209 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7210 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7211
7212 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7213 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2261) <<
7214 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7215 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI)(adev->reg_offset[GC_HWIP][0][0] + 0x1018) <<
7216 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7217 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7218 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7219
7220 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7221 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x224f) <<
7222 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7223 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM)(adev->reg_offset[GC_HWIP][0][0] + 0x100c) <<
7224 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7225 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7226 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7227
7228 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7229 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2240) <<
7230 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7231 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x0fd2) <<
7232 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7233 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7234 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7235
7236 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7237 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD)(adev->reg_offset[GC_HWIP][0][1] + 0x2241) <<
7238 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7239 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x0fd3) <<
7240 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7241 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7242 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7243
7244 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7245 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP)(adev->reg_offset[GC_HWIP][0][1] + 0x2440) <<
7246 GRBM_CAM_DATA__CAM_ADDR__SHIFT0x0) |
7247 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x11e0) <<
7248 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT0x10);
7249 break;
7250 }
7251
7252 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a06), 0, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x5a06)), (0), 0));
7253 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5a05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5a05)), (data), 0));
7254}
7255
7256static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7257{
7258 uint32_t data;
7259 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5c11, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5c11), 0));
7260 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK0x00000008L;
7261 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5c11), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5c11)), (data), 0));
7262
7263 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5c10, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5c10), 0));
7264 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK0x00000008L;
7265 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5c10), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5c10)), (data), 0));
7266}
7267
7268static int gfx_v10_0_hw_init(void *handle)
7269{
7270 int r;
7271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7272
7273 if (!amdgpu_emu_mode)
7274 gfx_v10_0_init_golden_registers(adev);
7275
7276 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7277 /**
7278 * For gfx 10, rlc firmware loading relies on smu firmware is
7279 * loaded firstly, so in direct type, it has to load smc ucode
7280 * here before rlc.
7281 */
7282 if (!(adev->flags & AMD_IS_APU)) {
7283 r = amdgpu_pm_load_smu_firmware(adev, NULL((void *)0));
7284 if (r)
7285 return r;
7286 }
7287 gfx_v10_0_disable_gpa_mode(adev);
7288 }
7289
7290 /* if GRBM CAM not remapped, set up the remapping */
7291 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7292 gfx_v10_0_setup_grbm_cam_remapping(adev);
7293
7294 gfx_v10_0_constants_init(adev);
7295
7296 r = gfx_v10_0_rlc_resume(adev);
7297 if (r)
7298 return r;
7299
7300 /*
7301 * init golden registers and rlc resume may override some registers,
7302 * reconfig them here
7303 */
7304 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)) ||
7305 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)) ||
7306 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)))
7307 gfx_v10_0_tcp_harvest(adev);
7308
7309 r = gfx_v10_0_cp_resume(adev);
7310 if (r)
7311 return r;
7312
7313 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)))
7314 gfx_v10_3_program_pbb_mode(adev);
7315
7316 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)))
7317 gfx_v10_3_set_power_brake_sequence(adev);
7318
7319 return r;
7320}
7321
7322#ifndef BRING_UP_DEBUG
7323static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7324{
7325 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7326 struct amdgpu_ring *kiq_ring = &kiq->ring;
7327 int i;
7328
7329 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7330 return -EINVAL22;
7331
7332 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7333 adev->gfx.num_gfx_rings))
7334 return -ENOMEM12;
7335
7336 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7337 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7338 PREEMPT_QUEUES, 0, 0);
7339 if (!adev->job_hang)
7340 return amdgpu_ring_test_helper(kiq_ring);
7341 else
7342 return 0;
7343}
7344#endif
7345
7346static int gfx_v10_0_hw_fini(void *handle)
7347{
7348 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7349 int r;
7350 uint32_t tmp;
7351
7352 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7353 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7354
7355 if (!adev->no_hw_access) {
7356#ifndef BRING_UP_DEBUG
7357 if (amdgpu_async_gfx_ring) {
7358 r = gfx_v10_0_kiq_disable_kgq(adev);
7359 if (r)
7360 DRM_ERROR("KGQ disable failed\n")__drm_err("KGQ disable failed\n");
7361 }
7362#endif
7363 if (amdgpu_gfx_disable_kcq(adev))
7364 DRM_ERROR("KCQ disable failed\n")__drm_err("KCQ disable failed\n");
7365 }
7366
7367 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
7368 gfx_v10_0_cp_gfx_enable(adev, false0);
7369 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7370 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0))) {
7371 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4ca1, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4ca1), 0));
7372 tmp &= 0xffffff00;
7373 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca1), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4ca1)), (tmp), 0));
7374 } else {
7375 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4caa, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4caa), 0));
7376 tmp &= 0xffffff00;
7377 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4caa), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x4caa)), (tmp), 0));
7378 }
7379
7380 return 0;
7381 }
7382 gfx_v10_0_cp_enable(adev, false0);
7383 gfx_v10_0_enable_gui_idle_interrupt(adev, false0);
7384
7385 return 0;
7386}
7387
7388static int gfx_v10_0_suspend(void *handle)
7389{
7390 return gfx_v10_0_hw_fini(handle);
7391}
7392
7393static int gfx_v10_0_resume(void *handle)
7394{
7395 return gfx_v10_0_hw_init(handle);
7396}
7397
7398static bool_Bool gfx_v10_0_is_idle(void *handle)
7399{
7400 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7401
7402 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),(((((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da4, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da4), 0))) & 0x80000000L) >>
0x1f)
7403 GRBM_STATUS, GUI_ACTIVE)(((((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da4, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da4), 0))) & 0x80000000L) >>
0x1f))
7404 return false0;
7405 else
7406 return true1;
7407}
7408
7409static int gfx_v10_0_wait_for_idle(void *handle)
7410{
7411 unsigned i;
7412 u32 tmp;
7413 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7414
7415 for (i = 0; i < adev->usec_timeout; i++) {
7416 /* read MC_STATUS */
7417 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da4, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da4), 0)) &
7418 GRBM_STATUS__GUI_ACTIVE_MASK0x80000000L;
7419
7420 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)(((tmp) & 0x80000000L) >> 0x1f))
7421 return 0;
7422 udelay(1);
7423 }
7424 return -ETIMEDOUT60;
7425}
7426
7427static int gfx_v10_0_soft_reset(void *handle)
7428{
7429 u32 grbm_soft_reset = 0;
7430 u32 tmp;
7431 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7432
7433 /* GRBM_STATUS */
7434 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da4, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da4), 0));
7435 if (tmp & (GRBM_STATUS__PA_BUSY_MASK0x02000000L | GRBM_STATUS__SC_BUSY_MASK0x01000000L |
7436 GRBM_STATUS__BCI_BUSY_MASK0x00800000L | GRBM_STATUS__SX_BUSY_MASK0x00100000L |
7437 GRBM_STATUS__TA_BUSY_MASK0x00004000L | GRBM_STATUS__DB_BUSY_MASK0x04000000L |
7438 GRBM_STATUS__CB_BUSY_MASK0x40000000L | GRBM_STATUS__GDS_BUSY_MASK0x00008000L |
7439 GRBM_STATUS__SPI_BUSY_MASK0x00400000L | GRBM_STATUS__GE_BUSY_NO_DMA_MASK0x00010000L)) {
7440 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7441 GRBM_SOFT_RESET, SOFT_RESET_CP,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7442 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)));
7443 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)))
7444 GRBM_SOFT_RESET, SOFT_RESET_GFX,(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)))
7445 1)(((grbm_soft_reset) & ~0x00010000L) | (0x00010000L & (
(1) << 0x10)));
7446 }
7447
7448 if (tmp & (GRBM_STATUS__CP_BUSY_MASK0x20000000L | GRBM_STATUS__CP_COHERENCY_BUSY_MASK0x10000000L)) {
7449 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7450 GRBM_SOFT_RESET, SOFT_RESET_CP,(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)))
7451 1)(((grbm_soft_reset) & ~0x00000001L) | (0x00000001L & (
(1) << 0x0)));
7452 }
7453
7454 /* GRBM_STATUS2 */
7455 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da2, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da2), 0));
7456 switch (adev->ip_versions[GC_HWIP][0]) {
7457 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
7458 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
7459 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7460 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
7461 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
7462 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7463 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7464 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)(((tmp) & 0x04000000L) >> 0x1a))
7465 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7466 GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7467 SOFT_RESET_RLC,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7468 1)(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
7469 break;
7470 default:
7471 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)(((tmp) & 0x01000000L) >> 0x18))
7472 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7473 GRBM_SOFT_RESET,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7474 SOFT_RESET_RLC,(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)))
7475 1)(((grbm_soft_reset) & ~0x00000004L) | (0x00000004L & (
(1) << 0x2)));
7476 break;
7477 }
7478
7479 if (grbm_soft_reset) {
7480 /* stop the rlc */
7481 gfx_v10_0_rlc_stop(adev);
7482
7483 /* Disable GFX parsing/prefetching */
7484 gfx_v10_0_cp_gfx_enable(adev, false0);
7485
7486 /* Disable MEC parsing/prefetching */
7487 gfx_v10_0_cp_compute_enable(adev, false0);
7488
7489 if (grbm_soft_reset) {
7490 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da8), 0));
7491 tmp |= grbm_soft_reset;
7492 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp)do { } while(0);
7493 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0da8), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0da8)), (tmp), 0));
7494 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da8), 0));
7495
7496 udelay(50);
7497
7498 tmp &= ~grbm_soft_reset;
7499 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0da8), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x0da8)), (tmp), 0));
7500 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0da8, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0da8), 0));
7501 }
7502
7503 /* Wait a little for things to settle down */
7504 udelay(50);
7505 }
7506 return 0;
7507}
7508
7509static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7510{
7511 uint64_t clock, clock_lo, clock_hi, hi_check;
7512
7513 switch (adev->ip_versions[GC_HWIP][0]) {
7514 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7515 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7516 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
7517 preempt_disable();
7518 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0025, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0025), 0));
7519 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0026, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0026), 0));
7520 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0025, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0025), 0));
7521 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7522 * roughly every 42 seconds.
7523 */
7524 if (hi_check != clock_hi) {
7525 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0026, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0026), 0));
7526 clock_hi = hi_check;
7527 }
7528 preempt_enable();
7529 clock = clock_lo | (clock_hi << 32ULL);
7530 break;
7531 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7532 preempt_disable();
7533 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x002d, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x002d), 0));
7534 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x002e, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x002e), 0));
7535 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x002d, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x002d), 0));
7536 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7537 * roughly every 42 seconds.
7538 */
7539 if (hi_check != clock_hi) {
7540 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x002e, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x002e), 0));
7541 clock_hi = hi_check;
7542 }
7543 preempt_enable();
7544 clock = clock_lo | (clock_hi << 32ULL);
7545 break;
7546 default:
7547 preempt_disable();
7548 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0102, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0102), 0));
7549 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0103, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0103), 0));
7550 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0102, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0102), 0));
7551 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7552 * roughly every 42 seconds.
7553 */
7554 if (hi_check != clock_hi) {
7555 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[SMUIO_HWIP][0
][1] + 0x0103, (1<<1), SMUIO_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[SMUIO_HWIP][0][1] + 0x0103), 0));
7556 clock_hi = hi_check;
7557 }
7558 preempt_enable();
7559 clock = clock_lo | (clock_hi << 32ULL);
7560 break;
7561 }
7562 return clock;
7563}
7564
7565static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7566 uint32_t vmid,
7567 uint32_t gds_base, uint32_t gds_size,
7568 uint32_t gws_base, uint32_t gws_size,
7569 uint32_t oa_base, uint32_t oa_size)
7570{
7571 struct amdgpu_device *adev = ring->adev;
7572
7573 /* GDS Base */
7574 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7575 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE)(adev->reg_offset[GC_HWIP][0][0] + 0x20a0) + 2 * vmid,
7576 gds_base);
7577
7578 /* GDS Size */
7579 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7580 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE)(adev->reg_offset[GC_HWIP][0][0] + 0x20a1) + 2 * vmid,
7581 gds_size);
7582
7583 /* GWS */
7584 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7585 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x20c0) + vmid,
7586 gws_size << GDS_GWS_VMID0__SIZE__SHIFT0x10 | gws_base);
7587
7588 /* OA */
7589 gfx_v10_0_write_data_to_reg(ring, 0, false0,
7590 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)(adev->reg_offset[GC_HWIP][0][0] + 0x20d0) + vmid,
7591 (1 << (oa_size + oa_base)) - (1 << oa_base));
7592}
7593
7594static int gfx_v10_0_early_init(void *handle)
7595{
7596 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7597
7598 switch (adev->ip_versions[GC_HWIP][0]) {
7599 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
7600 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
7601 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
7602 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
7603 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
7604 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X1;
7605 break;
7606 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
7607 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
7608 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7609 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
7610 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
7611 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7612 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7613 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
7614 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid2;
7615 break;
7616 default:
7617 break;
7618 }
7619
7620 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),(((amdgpu_gfx_get_num_kcq(adev))<(8))?(amdgpu_gfx_get_num_kcq
(adev)):(8))
7621 AMDGPU_MAX_COMPUTE_RINGS)(((amdgpu_gfx_get_num_kcq(adev))<(8))?(amdgpu_gfx_get_num_kcq
(adev)):(8));
7622
7623 gfx_v10_0_set_kiq_pm4_funcs(adev);
7624 gfx_v10_0_set_ring_funcs(adev);
7625 gfx_v10_0_set_irq_funcs(adev);
7626 gfx_v10_0_set_gds_init(adev);
7627 gfx_v10_0_set_rlc_funcs(adev);
7628 gfx_v10_0_set_mqd_funcs(adev);
7629
7630 /* init rlcg reg access ctrl */
7631 gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7632
7633 return 0;
7634}
7635
7636static int gfx_v10_0_late_init(void *handle)
7637{
7638 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7639 int r;
7640
7641 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7642 if (r)
7643 return r;
7644
7645 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7646 if (r)
7647 return r;
7648
7649 return 0;
7650}
7651
7652static bool_Bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7653{
7654 uint32_t rlc_cntl;
7655
7656 /* if RLC is not enabled, do nothing */
7657 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c00, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c00), 0));
7658 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)(((rlc_cntl) & 0x00000001L) >> 0x0)) ? true1 : false0;
7659}
7660
7661static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7662{
7663 uint32_t data;
7664 unsigned i;
7665
7666 data = RLC_SAFE_MODE__CMD_MASK0x00000001L;
7667 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT0x1);
7668
7669 switch (adev->ip_versions[GC_HWIP][0]) {
7670 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
7671 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
7672 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7673 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
7674 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
7675 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7676 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7677 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
7678 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca0), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4ca0)), (data), 0));
7679
7680 /* wait for RLC_SAFE_MODE */
7681 for (i = 0; i < adev->usec_timeout; i++) {
7682 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),(((((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4ca0, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4ca0), 0))) & 0x00000001L) >>
0x0)
7683 RLC_SAFE_MODE, CMD)(((((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4ca0, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4ca0), 0))) & 0x00000001L) >>
0x0))
7684 break;
7685 udelay(1);
7686 }
7687 break;
7688 default:
7689 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c05)), (data), 0));
7690
7691 /* wait for RLC_SAFE_MODE */
7692 for (i = 0; i < adev->usec_timeout; i++) {
7693 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),(((((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c05, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c05), 0))) & 0x00000001L) >>
0x0)
7694 RLC_SAFE_MODE, CMD)(((((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c05, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c05), 0))) & 0x00000001L) >>
0x0))
7695 break;
7696 udelay(1);
7697 }
7698 break;
7699 }
7700}
7701
7702static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7703{
7704 uint32_t data;
7705
7706 data = RLC_SAFE_MODE__CMD_MASK0x00000001L;
7707 switch (adev->ip_versions[GC_HWIP][0]) {
7708 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
7709 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
7710 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
7711 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
7712 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
7713 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
7714 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
7715 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
7716 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4ca0), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4ca0)), (data), 0));
7717 break;
7718 default:
7719 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c05), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c05)), (data), 0));
7720 break;
7721 }
7722}
7723
7724static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7725 bool_Bool enable)
7726{
7727 uint32_t data, def;
7728
7729 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG(1ULL << 0) | AMD_CG_SUPPORT_GFX_MGLS(1ULL << 1))))
7730 return;
7731
7732 /* It is disabled by HW by default */
7733 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG(1ULL << 0))) {
7734 /* 0 - Disable some blocks' MGCG */
7735 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2200), 0xe0000000, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x2200)), (0xe0000000
), 0));
7736 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5086), 0xff000000, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x5086)), (0xff000000
), 0));
7737 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5084), 0xff000000, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x5084)), (0xff000000
), 0));
7738 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5085), 0xff000000, 0, GC_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[GC_HWIP][0][1] + 0x5085)), (0xff000000
), 0));
7739
7740 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7741 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c48), 0));
7742 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L |
7743 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L |
7744 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L |
7745 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L |
7746 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK0x00000100L |
7747 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK0x00010000L);
7748
7749 if (def != data)
7750 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0));
7751
7752 /* MGLS is a global flag to control all MGLS in GFX */
7753 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS(1ULL << 1)) {
7754 /* 2 - RLC memory Light sleep */
7755 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS(1ULL << 7)) {
7756 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c06, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c06), 0));
7757 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L;
7758 if (def != data)
7759 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c06), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c06)), (data), 0));
7760 }
7761 /* 3 - CP memory Light sleep */
7762 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS(1ULL << 6)) {
7763 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e19, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e19), 0));
7764 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L;
7765 if (def != data)
7766 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e19), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x1e19)), (data), 0));
7767 }
7768 }
7769 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG(1ULL << 0))) {
7770 /* 1 - MGCG_OVERRIDE */
7771 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c48), 0));
7772 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK0x00000002L |
7773 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK0x00000020L |
7774 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L |
7775 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK0x00000040L |
7776 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK0x00000100L |
7777 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK0x00010000L);
7778 if (def != data)
7779 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0));
7780
7781 /* 2 - disable MGLS in CP */
7782 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e19, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e19), 0));
7783 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L) {
7784 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L;
7785 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e19), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x1e19)), (data), 0));
7786 }
7787
7788 /* 3 - disable MGLS in RLC */
7789 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c06, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c06), 0));
7790 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L) {
7791 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L;
7792 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c06), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c06)), (data), 0));
7793 }
7794
7795 }
7796}
7797
7798static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7799 bool_Bool enable)
7800{
7801 uint32_t data, def;
7802
7803 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20) | AMD_CG_SUPPORT_GFX_3D_CGLS(1ULL << 21))))
7804 return;
7805
7806 /* Enable 3D CGCG/CGLS */
7807 if (enable) {
7808 /* write cmd to clear cgcg/cgls ov */
7809 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c48), 0));
7810
7811 /* unset CGCG override */
7812 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20))
7813 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK0x00000080L;
7814
7815 /* update CGCG and CGLS override bits */
7816 if (def != data)
7817 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0));
7818
7819 /* enable 3Dcgcg FSM(0x0000363f) */
7820 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4cc5, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4cc5), 0));
7821 data = 0;
7822
7823 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20))
7824 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
7825 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L;
7826
7827 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS(1ULL << 21))
7828 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT0x2) |
7829 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L;
7830
7831 if (def != data)
7832 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4cc5), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4cc5)), (data), 0));
7833
7834 /* set IDLE_POLL_COUNT(0x00900100) */
7835 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0f62, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0f62), 0));
7836 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT0x0) |
7837 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
7838 if (def != data)
7839 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f62), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x0f62)), (data), 0));
7840 } else {
7841 /* Disable CGCG/CGLS */
7842 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4cc5, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4cc5), 0));
7843
7844 /* disable cgcg, cgls should be disabled */
7845 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20))
7846 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L;
7847
7848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS(1ULL << 21))
7849 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L;
7850
7851 /* disable cgcg and cgls in FSM */
7852 if (def != data)
7853 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4cc5), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4cc5)), (data), 0));
7854 }
7855}
7856
7857static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7858 bool_Bool enable)
7859{
7860 uint32_t def, data;
7861
7862 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG(1ULL << 2) | AMD_CG_SUPPORT_GFX_CGLS(1ULL << 3))))
7863 return;
7864
7865 if (enable) {
7866 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c48), 0));
7867
7868 /* unset CGCG override */
7869 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG(1ULL << 2))
7870 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK0x00000008L;
7871
7872 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1ULL << 3))
7873 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK0x00000010L;
7874
7875 /* update CGCG and CGLS override bits */
7876 if (def != data)
7877 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0));
7878
7879 /* enable cgcg FSM(0x0000363F) */
7880 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c49, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c49), 0));
7881 data = 0;
7882
7883 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG(1ULL << 2))
7884 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT0x8) |
7885 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L;
7886
7887 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1ULL << 3))
7888 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT0x2) |
7889 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L;
7890
7891 if (def != data)
7892 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c49), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c49)), (data), 0));
7893
7894 /* set IDLE_POLL_COUNT(0x00900100) */
7895 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0f62, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0f62), 0));
7896 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT0x0) |
7897 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT0x10);
7898 if (def != data)
7899 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x0f62), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x0f62)), (data), 0));
7900 } else {
7901 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c49, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c49), 0));
7902
7903 /* reset CGCG/CGLS bits */
7904 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG(1ULL << 2))
7905 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L;
7906
7907 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS(1ULL << 3))
7908 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L;
7909
7910 /* disable cgcg and cgls in FSM */
7911 if (def != data)
7912 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c49), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c49)), (data), 0));
7913 }
7914}
7915
7916static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7917 bool_Bool enable)
7918{
7919 uint32_t def, data;
7920
7921 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG(1ULL << 31)))
7922 return;
7923
7924 if (enable) {
7925 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c48), 0));
7926 /* unset FGCG override */
7927 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK0x00000100L;
7928 /* update FGCG override bits */
7929 if (def != data)
7930 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0));
7931
7932 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5b31, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5b31), 0));
7933 /* unset RLC SRAM CLK GATER override */
7934 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK0x00000100L;
7935 /* update RLC SRAM CLK GATER override bits */
7936 if (def != data)
7937 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b31), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5b31)), (data), 0));
7938 } else {
7939 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c48, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c48), 0));
7940 /* reset FGCG bits */
7941 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK0x00000100L;
7942 /* disable FGCG*/
7943 if (def != data)
7944 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c48), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c48)), (data), 0));
7945
7946 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x5b31, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x5b31), 0));
7947 /* reset RLC SRAM CLK GATER bits */
7948 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK0x00000100L;
7949 /* disable RLC SRAM CLK*/
7950 if (def != data)
7951 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x5b31), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x5b31)), (data), 0));
7952 }
7953}
7954
7955static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7956{
7957 uint32_t reg_data = 0;
7958 uint32_t reg_idx = 0;
7959 uint32_t i;
7960
7961 const uint32_t tcp_ctrl_regs[] = {
7962 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG0x5013,
7963 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG0x5017,
7964 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG0x501b,
7965 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG0x501f,
7966 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG0x5023,
7967 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG0x5027,
7968 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG0x502b,
7969 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG0x502f,
7970 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG0x5033,
7971 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG0x5037,
7972 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG0x5063,
7973 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG0x5067,
7974 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG0x503b,
7975 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG0x503f,
7976 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG0x5043,
7977 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG0x5047,
7978 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG0x504b,
7979 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG0x504f,
7980 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG0x5053,
7981 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG0x5057,
7982 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG0x505b,
7983 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG0x505f,
7984 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG0x506b,
7985 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG0x506f
7986 };
7987
7988 const uint32_t tcp_ctrl_regs_nv12[] = {
7989 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG0x5013,
7990 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG0x5017,
7991 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG0x501b,
7992 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG0x501f,
7993 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG0x5023,
7994 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG0x5027,
7995 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG0x502b,
7996 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG0x502f,
7997 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG0x5033,
7998 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG0x5037,
7999 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG0x503b,
8000 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG0x503f,
8001 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG0x5043,
8002 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG0x5047,
8003 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG0x504b,
8004 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG0x504f,
8005 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG0x5053,
8006 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG0x5057,
8007 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG0x505b,
8008 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG0x505f,
8009 };
8010
8011 const uint32_t sm_ctlr_regs[] = {
8012 mmCGTS_SA0_QUAD0_SM_CTRL_REG0x5000,
8013 mmCGTS_SA0_QUAD1_SM_CTRL_REG0x5002,
8014 mmCGTS_SA1_QUAD0_SM_CTRL_REG0x5004,
8015 mmCGTS_SA1_QUAD1_SM_CTRL_REG0x5006
8016 };
8017
8018 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2))) {
8019 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12)(sizeof((tcp_ctrl_regs_nv12)) / sizeof((tcp_ctrl_regs_nv12)[0
])); i++) {
8020 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX1] +
8021 tcp_ctrl_regs_nv12[i];
8022 reg_data = RREG32(reg_idx)amdgpu_device_rreg(adev, (reg_idx), 0);
8023 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK0x00020000L;
8024 WREG32(reg_idx, reg_data)amdgpu_device_wreg(adev, (reg_idx), (reg_data), 0);
8025 }
8026 } else {
8027 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs)(sizeof((tcp_ctrl_regs)) / sizeof((tcp_ctrl_regs)[0])); i++) {
8028 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX1] +
8029 tcp_ctrl_regs[i];
8030 reg_data = RREG32(reg_idx)amdgpu_device_rreg(adev, (reg_idx), 0);
8031 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK0x00020000L;
8032 WREG32(reg_idx, reg_data)amdgpu_device_wreg(adev, (reg_idx), (reg_data), 0);
8033 }
8034 }
8035
8036 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs)(sizeof((sm_ctlr_regs)) / sizeof((sm_ctlr_regs)[0])); i++) {
8037 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX1] +
8038 sm_ctlr_regs[i];
8039 reg_data = RREG32(reg_idx)amdgpu_device_rreg(adev, (reg_idx), 0);
8040 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK0x000E0000L;
8041 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT0x11;
8042 WREG32(reg_idx, reg_data)amdgpu_device_wreg(adev, (reg_idx), (reg_data), 0);
8043 }
8044}
8045
8046static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8047 bool_Bool enable)
8048{
8049 amdgpu_gfx_rlc_enter_safe_mode(adev);
8050
8051 if (enable) {
8052 /* enable FGCG firstly*/
8053 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8054 /* CGCG/CGLS should be enabled after MGCG/MGLS
8055 * === MGCG + MGLS ===
8056 */
8057 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8058 /* === CGCG /CGLS for GFX 3D Only === */
8059 gfx_v10_0_update_3d_clock_gating(adev, enable);
8060 /* === CGCG + CGLS === */
8061 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8062
8063 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10))) ||
8064 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1))) ||
8065 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2))))
8066 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8067 } else {
8068 /* CGCG/CGLS should be disabled before MGCG/MGLS
8069 * === CGCG + CGLS ===
8070 */
8071 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8072 /* === CGCG /CGLS for GFX 3D Only === */
8073 gfx_v10_0_update_3d_clock_gating(adev, enable);
8074 /* === MGCG + MGLS === */
8075 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8076 /* disable fgcg at last*/
8077 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8078 }
8079
8080 if (adev->cg_flags &
8081 (AMD_CG_SUPPORT_GFX_MGCG(1ULL << 0) |
8082 AMD_CG_SUPPORT_GFX_CGLS(1ULL << 3) |
8083 AMD_CG_SUPPORT_GFX_CGCG(1ULL << 2) |
8084 AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20) |
8085 AMD_CG_SUPPORT_GFX_3D_CGLS(1ULL << 21)))
8086 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8087
8088 amdgpu_gfx_rlc_exit_safe_mode(adev);
8089
8090 return 0;
8091}
8092
8093static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8094{
8095 u32 reg, data;
8096
8097 amdgpu_gfx_off_ctrl(adev, false0);
8098
8099 /* not for *_SOC15 */
8100 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL)(adev->reg_offset[GC_HWIP][0][1] + 0x4c71);
8101 if (amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF))
8102 data = RREG32_NO_KIQ(reg)amdgpu_device_rreg(adev, (reg), (1<<1));
8103 else
8104 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c71, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c71), 0));
8105
8106 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK0x0000000FL;
8107 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK0x0000000FL) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT0x0;
8108
8109 if (amdgpu_sriov_is_pp_one_vf(adev)((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF))
8110 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c71, data, (1<<1), GC_HWIP) : amdgpu_device_wreg
(adev, (adev->reg_offset[GC_HWIP][0][1] + 0x4c71), (data),
0));
8111 else
8112 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c71), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c71)), (data), 0));
8113
8114 amdgpu_gfx_off_ctrl(adev, true1);
8115}
8116
8117static bool_Bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8118 uint32_t offset,
8119 struct soc15_reg_rlcg *entries, int arr_size)
8120{
8121 int i;
8122 uint32_t reg;
8123
8124 if (!entries)
8125 return false0;
8126
8127 for (i = 0; i < arr_size; i++) {
8128 const struct soc15_reg_rlcg *entry;
8129
8130 entry = &entries[i];
8131 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8132 if (offset == reg)
8133 return true1;
8134 }
8135
8136 return false0;
8137}
8138
8139static bool_Bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8140{
8141 return gfx_v10_0_check_rlcg_range(adev, offset, NULL((void *)0), 0);
8142}
8143
8144static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool_Bool enable)
8145{
8146 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][1
] + 0x4c43, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][1] + 0x4c43), 0));
8147
8148 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG(1 << 0)))
8149 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK0x00000001L;
8150 else
8151 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK0x00000001L;
8152
8153 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c43), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c43)), (data), 0));
8154
8155 /*
8156 * CGPG enablement required and the register to program the hysteresis value
8157 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8158 * in refclk count. Note that RLC FW is modified to take 16 bits from
8159 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8160 *
8161 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8162 * of CGPG enablement starting point.
8163 * Power/performance team will optimize it and might give a new value later.
8164 */
8165 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG(1 << 0))) {
8166 switch (adev->ip_versions[GC_HWIP][0]) {
8167 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
8168 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
8169 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
8170 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
8171 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh0x0000FFFFL;
8172 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x4c78), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][1] + 0x4c78)), (data), 0));
8173 break;
8174 default:
8175 break;
8176 }
8177 }
8178}
8179
8180static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool_Bool enable)
8181{
8182 amdgpu_gfx_rlc_enter_safe_mode(adev);
8183
8184 gfx_v10_cntl_power_gating(adev, enable);
8185
8186 amdgpu_gfx_rlc_exit_safe_mode(adev);
8187}
8188
8189static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8190 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8191 .set_safe_mode = gfx_v10_0_set_safe_mode,
8192 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8193 .init = gfx_v10_0_rlc_init,
8194 .get_csb_size = gfx_v10_0_get_csb_size,
8195 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8196 .resume = gfx_v10_0_rlc_resume,
8197 .stop = gfx_v10_0_rlc_stop,
8198 .reset = gfx_v10_0_rlc_reset,
8199 .start = gfx_v10_0_rlc_start,
8200 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8201};
8202
8203static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8204 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8205 .set_safe_mode = gfx_v10_0_set_safe_mode,
8206 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8207 .init = gfx_v10_0_rlc_init,
8208 .get_csb_size = gfx_v10_0_get_csb_size,
8209 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8210 .resume = gfx_v10_0_rlc_resume,
8211 .stop = gfx_v10_0_rlc_stop,
8212 .reset = gfx_v10_0_rlc_reset,
8213 .start = gfx_v10_0_rlc_start,
8214 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8215 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8216};
8217
8218static int gfx_v10_0_set_powergating_state(void *handle,
8219 enum amd_powergating_state state)
8220{
8221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8222 bool_Bool enable = (state == AMD_PG_STATE_GATE);
8223
8224 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
8225 return 0;
8226
8227 switch (adev->ip_versions[GC_HWIP][0]) {
8228 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
8229 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
8230 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
8231 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
8232 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
8233 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
8234 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
8235 amdgpu_gfx_off_ctrl(adev, enable);
8236 break;
8237 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
8238 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
8239 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
8240 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
8241 if (!enable)
8242 amdgpu_gfx_off_ctrl(adev, false0);
8243
8244 gfx_v10_cntl_pg(adev, enable);
8245
8246 if (enable)
8247 amdgpu_gfx_off_ctrl(adev, true1);
8248
8249 break;
8250 default:
8251 break;
8252 }
8253 return 0;
8254}
8255
8256static int gfx_v10_0_set_clockgating_state(void *handle,
8257 enum amd_clockgating_state state)
8258{
8259 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8260
8261 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
8262 return 0;
8263
8264 switch (adev->ip_versions[GC_HWIP][0]) {
8265 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
8266 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
8267 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
8268 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
8269 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
8270 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
8271 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
8272 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
8273 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
8274 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
8275 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
8276 gfx_v10_0_update_gfx_clock_gating(adev,
8277 state == AMD_CG_STATE_GATE);
8278 break;
8279 default:
8280 break;
8281 }
8282 return 0;
8283}
8284
8285static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8286{
8287 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8288 int data;
8289
8290 /* AMD_CG_SUPPORT_GFX_FGCG */
8291 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c48
)));
8292 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK0x00000100L))
8293 *flags |= AMD_CG_SUPPORT_GFX_FGCG(1ULL << 31);
8294
8295 /* AMD_CG_SUPPORT_GFX_MGCG */
8296 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c48
)));
8297 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK0x00000004L))
8298 *flags |= AMD_CG_SUPPORT_GFX_MGCG(1ULL << 0);
8299
8300 /* AMD_CG_SUPPORT_GFX_CGCG */
8301 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c49
)));
8302 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK0x00000001L)
8303 *flags |= AMD_CG_SUPPORT_GFX_CGCG(1ULL << 2);
8304
8305 /* AMD_CG_SUPPORT_GFX_CGLS */
8306 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK0x00000002L)
8307 *flags |= AMD_CG_SUPPORT_GFX_CGLS(1ULL << 3);
8308
8309 /* AMD_CG_SUPPORT_GFX_RLC_LS */
8310 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4c06
)));
8311 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK0x00000001L)
8312 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS(1ULL << 7) | AMD_CG_SUPPORT_GFX_MGLS(1ULL << 1);
8313
8314 /* AMD_CG_SUPPORT_GFX_CP_LS */
8315 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1e19
)));
8316 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK0x00000001L)
8317 *flags |= AMD_CG_SUPPORT_GFX_CP_LS(1ULL << 6) | AMD_CG_SUPPORT_GFX_MGLS(1ULL << 1);
8318
8319 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8320 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D))amdgpu_kiq_rreg(adev, ((adev->reg_offset[GC_HWIP][0][1] + 0x4cc5
)));
8321 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK0x00000001L)
8322 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG(1ULL << 20);
8323
8324 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8325 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK0x00000002L)
8326 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS(1ULL << 21);
8327}
8328
8329static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8330{
8331 /* gfx10 is 32bit rptr*/
8332 return *(uint32_t *)ring->rptr_cpu_addr;
8333}
8334
8335static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8336{
8337 struct amdgpu_device *adev = ring->adev;
8338 u64 wptr;
8339
8340 /* XXX check if swapping is necessary on BE */
8341 if (ring->use_doorbell) {
8342 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = *(
volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr)) *)&
(*((atomic64_t *)ring->wptr_cpu_addr)); membar_datadep_consumer
(); __tmp; });
8343 } else {
8344 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1df4, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1df4), 0));
8345 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1df5, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1df5), 0)) << 32;
8346 }
8347
8348 return wptr;
8349}
8350
8351static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8352{
8353 struct amdgpu_device *adev = ring->adev;
8354 uint32_t *wptr_saved;
8355 uint32_t *is_queue_unmap;
8356 uint64_t aggregated_db_index;
8357 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX0].mqd_size;
8358 uint64_t wptr_tmp;
8359
8360 if (ring->is_mes_queue) {
8361 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8362 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8363 sizeof(uint32_t));
8364 aggregated_db_index =
8365 amdgpu_mes_get_aggregated_doorbell_index(adev,
8366 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8367
8368 wptr_tmp = ring->wptr & ring->buf_mask;
8369 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
wptr_tmp)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; });
8370 *wptr_saved = wptr_tmp;
8371 /* assume doorbell always being used by mes mapped queue */
8372 if (*is_queue_unmap) {
8373 WDOORBELL64(aggregated_db_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (wptr_tmp)
);
8374 WDOORBELL64(ring->doorbell_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (wptr_tmp
));
8375 } else {
8376 WDOORBELL64(ring->doorbell_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (wptr_tmp
));
8377
8378 if (*is_queue_unmap)
8379 WDOORBELL64(aggregated_db_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (wptr_tmp)
);
8380 }
8381 } else {
8382 if (ring->use_doorbell) {
8383 /* XXX check if swapping is necessary on BE */
8384 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; })
8385 ring->wptr)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; });
8386 WDOORBELL64(ring->doorbell_index, ring->wptr)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr));
8387 } else {
8388 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df4), ((u32)(ring->wptr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1df4)), (((u32
)(ring->wptr))), 0))
8389 lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df4), ((u32)(ring->wptr)), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x1df4)), (((u32
)(ring->wptr))), 0));
8390 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df5), ((u32)(((ring->wptr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1df5)), (((u32)(((ring->wptr) >>
16) >> 16))), 0))
8391 upper_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1df5), ((u32)(((ring->wptr) >> 16) >> 16
)), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x1df5)), (((u32)(((ring->wptr) >>
16) >> 16))), 0));
8392 }
8393 }
8394}
8395
8396static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8397{
8398 /* gfx10 hardware is 32bit rptr */
8399 return *(uint32_t *)ring->rptr_cpu_addr;
8400}
8401
8402static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8403{
8404 u64 wptr;
8405
8406 /* XXX check if swapping is necessary on BE */
8407 if (ring->use_doorbell)
8408 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = *(
volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr)) *)&
(*((atomic64_t *)ring->wptr_cpu_addr)); membar_datadep_consumer
(); __tmp; });
8409 else
8410 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8410); } while (0);
8411 return wptr;
8412}
8413
8414static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8415{
8416 struct amdgpu_device *adev = ring->adev;
8417 uint32_t *wptr_saved;
8418 uint32_t *is_queue_unmap;
8419 uint64_t aggregated_db_index;
8420 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE1].mqd_size;
8421 uint64_t wptr_tmp;
8422
8423 if (ring->is_mes_queue) {
8424 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8425 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8426 sizeof(uint32_t));
8427 aggregated_db_index =
8428 amdgpu_mes_get_aggregated_doorbell_index(adev,
8429 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8430
8431 wptr_tmp = ring->wptr & ring->buf_mask;
8432 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
wptr_tmp)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; });
8433 *wptr_saved = wptr_tmp;
8434 /* assume doorbell always used by mes mapped queue */
8435 if (*is_queue_unmap) {
8436 WDOORBELL64(aggregated_db_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (wptr_tmp)
);
8437 WDOORBELL64(ring->doorbell_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (wptr_tmp
));
8438 } else {
8439 WDOORBELL64(ring->doorbell_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (wptr_tmp
));
8440
8441 if (*is_queue_unmap)
8442 WDOORBELL64(aggregated_db_index, wptr_tmp)amdgpu_mm_wdoorbell64(adev, (aggregated_db_index), (wptr_tmp)
);
8443 }
8444 } else {
8445 /* XXX check if swapping is necessary on BE */
8446 if (ring->use_doorbell) {
8447 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; })
8448 ring->wptr)({ typeof(*((atomic64_t *)ring->wptr_cpu_addr)) __tmp = ((
ring->wptr)); *(volatile typeof(*((atomic64_t *)ring->wptr_cpu_addr
)) *)&(*((atomic64_t *)ring->wptr_cpu_addr)) = __tmp; __tmp
; });
8449 WDOORBELL64(ring->doorbell_index, ring->wptr)amdgpu_mm_wdoorbell64(adev, (ring->doorbell_index), (ring->
wptr));
8450 } else {
8451 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8451); } while (0); /* only DOORBELL method supported on gfx10 now */
8452 }
8453 }
8454}
8455
8456static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8457{
8458 struct amdgpu_device *adev = ring->adev;
8459 u32 ref_and_mask, reg_mem_engine;
8460 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8461
8462 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8463 switch (ring->me) {
8464 case 1:
8465 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8466 break;
8467 case 2:
8468 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8469 break;
8470 default:
8471 return;
8472 }
8473 reg_mem_engine = 0;
8474 } else {
8475 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8476 reg_mem_engine = 1; /* pfp */
8477 }
8478
8479 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8480 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8481 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8482 ref_and_mask, ref_and_mask, 0x20);
8483}
8484
8485static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8486 struct amdgpu_job *job,
8487 struct amdgpu_ib *ib,
8488 uint32_t flags)
8489{
8490 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
8491 u32 header, control = 0;
8492
8493 if (ib->flags & AMDGPU_IB_FLAG_CE(1<<0))
8494 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2)((3 << 30) | (((0x33) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
8495 else
8496 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x3F) & 0xFF) << 8) | ((2) &
0x3FFF) << 16);
8497
8498 control |= ib->length_dw | (vmid << 24);
8499
8500 if ((amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT(1<<2))) {
8501 control |= INDIRECT_BUFFER_PRE_ENB(1)((1) << 21);
8502
8503 if (flags & AMDGPU_IB_PREEMPTED(1 << 3))
8504 control |= INDIRECT_BUFFER_PRE_RESUME(1)((1) << 30);
8505
8506 if (!(ib->flags & AMDGPU_IB_FLAG_CE(1<<0)) && vmid)
8507 gfx_v10_0_ring_emit_de_meta(ring,
8508 (!amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) && flags & AMDGPU_IB_PREEMPTED(1 << 3)) ? true1 : false0);
8509 }
8510
8511 if (ring->is_mes_queue)
8512 /* inherit vmid from mqd */
8513 control |= 0x400000;
8514
8515 amdgpu_ring_write(ring, header);
8516 BUG_ON(ib->gpu_addr & 0x3)((!(ib->gpu_addr & 0x3)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 8516, "!(ib->gpu_addr & 0x3)"
)); /* Dword align */
8517 amdgpu_ring_write(ring,
8518#ifdef __BIG_ENDIAN
8519 (2 << 0) |
8520#endif
8521 lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
8522 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
8523 amdgpu_ring_write(ring, control);
8524}
8525
8526static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8527 struct amdgpu_job *job,
8528 struct amdgpu_ib *ib,
8529 uint32_t flags)
8530{
8531 unsigned vmid = AMDGPU_JOB_GET_VMID(job)((job) ? (job)->vmid : 0);
8532 u32 control = INDIRECT_BUFFER_VALID(1 << 23) | ib->length_dw | (vmid << 24);
8533
8534 if (ring->is_mes_queue)
8535 /* inherit vmid from mqd */
8536 control |= 0x40000000;
8537
8538 /* Currently, there is a high possibility to get wave ID mismatch
8539 * between ME and GDS, leading to a hw deadlock, because ME generates
8540 * different wave IDs than the GDS expects. This situation happens
8541 * randomly when at least 5 compute pipes use GDS ordered append.
8542 * The wave IDs generated by ME are also wrong after suspend/resume.
8543 * Those are probably bugs somewhere else in the kernel driver.
8544 *
8545 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8546 * GDS to 0 for this ring (me/pipe).
8547 */
8548 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID(1 << 4)) {
8549 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)((3 << 30) | (((0x68) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
8550 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID0x20e8);
8551 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8552 }
8553
8554 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)((3 << 30) | (((0x3F) & 0xFF) << 8) | ((2) &
0x3FFF) << 16));
8555 BUG_ON(ib->gpu_addr & 0x3)((!(ib->gpu_addr & 0x3)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 8555, "!(ib->gpu_addr & 0x3)"
)); /* Dword align */
8556 amdgpu_ring_write(ring,
8557#ifdef __BIG_ENDIAN
8558 (2 << 0) |
8559#endif
8560 lower_32_bits(ib->gpu_addr)((u32)(ib->gpu_addr)));
8561 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)((u32)(((ib->gpu_addr) >> 16) >> 16)));
8562 amdgpu_ring_write(ring, control);
8563}
8564
8565static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8566 u64 seq, unsigned flags)
8567{
8568 bool_Bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT(1 << 0);
8569 bool_Bool int_sel = flags & AMDGPU_FENCE_FLAG_INT(1 << 1);
8570
8571 /* RELEASE_MEM - flush caches, send int */
8572 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)((3 << 30) | (((0x49) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
8573 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ(1 << 22) |
8574 PACKET3_RELEASE_MEM_GCR_GL2_WB(1 << 21) |
8575 PACKET3_RELEASE_MEM_GCR_GLM_INV(1 << 13) | /* must be set with GLM_WB */
8576 PACKET3_RELEASE_MEM_GCR_GLM_WB(1 << 12) |
8577 PACKET3_RELEASE_MEM_CACHE_POLICY(3)((3) << 25) |
8578 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT)((CACHE_FLUSH_AND_INV_TS_EVENT) << 0) |
8579 PACKET3_RELEASE_MEM_EVENT_INDEX(5)((5) << 8)));
8580 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1)((write64bit ? 2 : 1) << 29) |
8581 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)((int_sel ? 2 : 0) << 24)));
8582
8583 /*
8584 * the address should be Qword aligned if 64bit write, Dword
8585 * aligned if only send 32bit data low (discard data high)
8586 */
8587 if (write64bit)
8588 BUG_ON(addr & 0x7)((!(addr & 0x7)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8588, "!(addr & 0x7)"));
8589 else
8590 BUG_ON(addr & 0x3)((!(addr & 0x3)) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8590, "!(addr & 0x3)"));
8591 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
8592 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
8593 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
8594 amdgpu_ring_write(ring, upper_32_bits(seq)((u32)(((seq) >> 16) >> 16)));
8595 amdgpu_ring_write(ring, ring->is_mes_queue ?
8596 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG0x1000000u) : 0);
8597}
8598
8599static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8600{
8601 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8602 uint32_t seq = ring->fence_drv.sync_seq;
8603 uint64_t addr = ring->fence_drv.gpu_addr;
8604
8605 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr)((u32)(addr)),
8606 upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)), seq, 0xffffffff, 4);
8607}
8608
8609static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8610 uint16_t pasid, uint32_t flush_type,
8611 bool_Bool all_hub, uint8_t dst_sel)
8612{
8613 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)((3 << 30) | (((0x98) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
8614 amdgpu_ring_write(ring,
8615 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel)((dst_sel) << 0) |
8616 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub)((all_hub) << 4) |
8617 PACKET3_INVALIDATE_TLBS_PASID(pasid)((pasid) << 5) |
8618 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)((flush_type) << 29));
8619}
8620
8621static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8622 unsigned vmid, uint64_t pd_addr)
8623{
8624 if (ring->is_mes_queue)
8625 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false0, 0);
8626 else
8627 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr)(ring)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((ring
), (vmid), (pd_addr));
8628
8629 /* compute doesn't have PFP */
8630 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8631 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8632 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)((3 << 30) | (((0x42) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
8633 amdgpu_ring_write(ring, 0x0);
8634 }
8635}
8636
8637static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8638 u64 seq, unsigned int flags)
8639{
8640 struct amdgpu_device *adev = ring->adev;
8641
8642 /* we only allocate 32bit for each seq wb address */
8643 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT)((!(flags & (1 << 0))) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 8643, "!(flags & (1 << 0))"
));
8644
8645 /* write fence seq to the "addr" */
8646 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
8647 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0)((0) << 30) |
8648 WRITE_DATA_DST_SEL(5)((5) << 8) | WR_CONFIRM(1 << 20)));
8649 amdgpu_ring_write(ring, lower_32_bits(addr)((u32)(addr)));
8650 amdgpu_ring_write(ring, upper_32_bits(addr)((u32)(((addr) >> 16) >> 16)));
8651 amdgpu_ring_write(ring, lower_32_bits(seq)((u32)(seq)));
8652
8653 if (flags & AMDGPU_FENCE_FLAG_INT(1 << 1)) {
8654 /* set register to trigger INT */
8655 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
8656 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0)((0) << 30) |
8657 WRITE_DATA_DST_SEL(0)((0) << 8) | WR_CONFIRM(1 << 20)));
8658 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)(adev->reg_offset[GC_HWIP][0][0] + 0x1e55));
8659 amdgpu_ring_write(ring, 0);
8660 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8661 }
8662}
8663
8664static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8665{
8666 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)((3 << 30) | (((0x8B) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
8667 amdgpu_ring_write(ring, 0);
8668}
8669
8670static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8671 uint32_t flags)
8672{
8673 uint32_t dw2 = 0;
8674
8675 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)))
8676 gfx_v10_0_ring_emit_ce_meta(ring,
8677 (!amdgpu_sriov_vf(ring->adev)((ring->adev)->virt.caps & (1 << 2)) && flags & AMDGPU_IB_PREEMPTED(1 << 3)) ? true1 : false0);
8678
8679 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8680 if (flags & AMDGPU_HAVE_CTX_SWITCH(1 << 2)) {
8681 /* set load_global_config & load_global_uconfig */
8682 dw2 |= 0x8001;
8683 /* set load_cs_sh_regs */
8684 dw2 |= 0x01000000;
8685 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8686 dw2 |= 0x10002;
8687
8688 /* set load_ce_ram if preamble presented */
8689 if (AMDGPU_PREAMBLE_IB_PRESENT(1 << 0) & flags)
8690 dw2 |= 0x10000000;
8691 } else {
8692 /* still load_ce_ram if this is the first time preamble presented
8693 * although there is no context switch happens.
8694 */
8695 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST(1 << 1) & flags)
8696 dw2 |= 0x10000000;
8697 }
8698
8699 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)((3 << 30) | (((0x28) & 0xFF) << 8) | ((1) &
0x3FFF) << 16));
8700 amdgpu_ring_write(ring, dw2);
8701 amdgpu_ring_write(ring, 0);
8702}
8703
8704static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8705{
8706 unsigned ret;
8707
8708 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)((3 << 30) | (((0x22) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
8709 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)((u32)(ring->cond_exe_gpu_addr)));
8710 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)((u32)(((ring->cond_exe_gpu_addr) >> 16) >> 16
)));
8711 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8712 ret = ring->wptr & ring->buf_mask;
8713 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8714
8715 return ret;
8716}
8717
8718static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8719{
8720 unsigned cur;
8721 BUG_ON(offset > ring->buf_mask)((!(offset > ring->buf_mask)) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c", 8721, "!(offset > ring->buf_mask)"
));
8722 BUG_ON(ring->ring[offset] != 0x55aa55aa)((!(ring->ring[offset] != 0x55aa55aa)) ? (void)0 : __assert
("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 8722, "!(ring->ring[offset] != 0x55aa55aa)"));
8723
8724 cur = (ring->wptr - 1) & ring->buf_mask;
8725 if (likely(cur > offset)__builtin_expect(!!(cur > offset), 1))
8726 ring->ring[offset] = cur - offset;
8727 else
8728 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8729}
8730
8731static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8732{
8733 int i, r = 0;
8734 struct amdgpu_device *adev = ring->adev;
8735 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8736 struct amdgpu_ring *kiq_ring = &kiq->ring;
8737 unsigned long flags;
8738
8739 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8740 return -EINVAL22;
8741
8742 spin_lock_irqsave(&kiq->ring_lock, flags)do { flags = 0; mtx_enter(&kiq->ring_lock); } while (0
);
8743
8744 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8745 spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while
(0);
8746 return -ENOMEM12;
8747 }
8748
8749 /* assert preemption condition */
8750 amdgpu_ring_set_preempt_cond_exec(ring, false0);
8751
8752 /* assert IB preemption, emit the trailing fence */
8753 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8754 ring->trail_fence_gpu_addr,
8755 ++ring->trail_seq);
8756 amdgpu_ring_commit(kiq_ring);
8757
8758 spin_unlock_irqrestore(&kiq->ring_lock, flags)do { (void)(flags); mtx_leave(&kiq->ring_lock); } while
(0);
8759
8760 /* poll the trailing fence */
8761 for (i = 0; i < adev->usec_timeout; i++) {
8762 if (ring->trail_seq ==
8763 le32_to_cpu(*(ring->trail_fence_cpu_addr))((__uint32_t)(*(ring->trail_fence_cpu_addr))))
8764 break;
8765 udelay(1);
8766 }
8767
8768 if (i >= adev->usec_timeout) {
8769 r = -EINVAL22;
8770 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx)__drm_err("ring %d failed to preempt ib\n", ring->idx);
8771 }
8772
8773 /* deassert preemption condition */
8774 amdgpu_ring_set_preempt_cond_exec(ring, true1);
8775 return r;
8776}
8777
8778static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool_Bool resume)
8779{
8780 struct amdgpu_device *adev = ring->adev;
8781 struct v10_ce_ib_state ce_payload = {0};
8782 uint64_t offset, ce_payload_gpu_addr;
8783 void *ce_payload_cpu_addr;
8784 int cnt;
8785
8786 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8787
8788 if (ring->is_mes_queue) {
8789 offset = offsetof(struct amdgpu_mes_ctx_meta_data,__builtin_offsetof(struct amdgpu_mes_ctx_meta_data, gfx[0].gfx_meta_data
)
8790 gfx[0].gfx_meta_data)__builtin_offsetof(struct amdgpu_mes_ctx_meta_data, gfx[0].gfx_meta_data
) +
8791 offsetof(struct v10_gfx_meta_data, ce_payload)__builtin_offsetof(struct v10_gfx_meta_data, ce_payload);
8792 ce_payload_gpu_addr =
8793 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
8794 ce_payload_cpu_addr =
8795 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : (
(void *)0));
8796 } else {
8797 offset = offsetof(struct v10_gfx_meta_data, ce_payload)__builtin_offsetof(struct v10_gfx_meta_data, ce_payload);
8798 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8799 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8800 }
8801
8802 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)((3 << 30) | (((0x37) & 0xFF) << 8) | ((cnt) &
0x3FFF) << 16));
8803 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2)((2) << 30) |
8804 WRITE_DATA_DST_SEL(8)((8) << 8) |
8805 WR_CONFIRM(1 << 20)) |
8806 WRITE_DATA_CACHE_POLICY(0)((0) << 25));
8807 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)((u32)(ce_payload_gpu_addr)));
8808 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)((u32)(((ce_payload_gpu_addr) >> 16) >> 16)));
8809
8810 if (resume)
8811 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8812 sizeof(ce_payload) >> 2);
8813 else
8814 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8815 sizeof(ce_payload) >> 2);
8816}
8817
8818static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool_Bool resume)
8819{
8820 struct amdgpu_device *adev = ring->adev;
8821 struct v10_de_ib_state de_payload = {0};
8822 uint64_t offset, gds_addr, de_payload_gpu_addr;
8823 void *de_payload_cpu_addr;
8824 int cnt;
8825
8826 if (ring->is_mes_queue) {
8827 offset = offsetof(struct amdgpu_mes_ctx_meta_data,__builtin_offsetof(struct amdgpu_mes_ctx_meta_data, gfx[0].gfx_meta_data
)
8828 gfx[0].gfx_meta_data)__builtin_offsetof(struct amdgpu_mes_ctx_meta_data, gfx[0].gfx_meta_data
) +
8829 offsetof(struct v10_gfx_meta_data, de_payload)__builtin_offsetof(struct v10_gfx_meta_data, de_payload);
8830 de_payload_gpu_addr =
8831 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
8832 de_payload_cpu_addr =
8833 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (void *)
((uint8_t *)(ring->mes_ctx->meta_data_ptr) + offset) : (
(void *)0));
8834
8835 offset = offsetof(struct amdgpu_mes_ctx_meta_data,__builtin_offsetof(struct amdgpu_mes_ctx_meta_data, gfx[0].gds_backup
)
8836 gfx[0].gds_backup)__builtin_offsetof(struct amdgpu_mes_ctx_meta_data, gfx[0].gds_backup
) +
8837 offsetof(struct v10_gfx_meta_data, de_payload)__builtin_offsetof(struct v10_gfx_meta_data, de_payload);
8838 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset)(ring->is_mes_queue && ring->mes_ctx ? (ring->
mes_ctx->meta_data_gpu_addr + offset) : 0);
8839 } else {
8840 offset = offsetof(struct v10_gfx_meta_data, de_payload)__builtin_offsetof(struct v10_gfx_meta_data, de_payload);
8841 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8842 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8843
8844 gds_addr = roundup2(amdgpu_csa_vaddr(ring->adev) +(((amdgpu_csa_vaddr(ring->adev) + (128 * 1024) - adev->
gds.gds_size) + (((1 << 12)) - 1)) & (~((__typeof(amdgpu_csa_vaddr
(ring->adev) + (128 * 1024) - adev->gds.gds_size))((1 <<
12)) - 1)))
8845 AMDGPU_CSA_SIZE - adev->gds.gds_size,(((amdgpu_csa_vaddr(ring->adev) + (128 * 1024) - adev->
gds.gds_size) + (((1 << 12)) - 1)) & (~((__typeof(amdgpu_csa_vaddr
(ring->adev) + (128 * 1024) - adev->gds.gds_size))((1 <<
12)) - 1)))
8846 PAGE_SIZE)(((amdgpu_csa_vaddr(ring->adev) + (128 * 1024) - adev->
gds.gds_size) + (((1 << 12)) - 1)) & (~((__typeof(amdgpu_csa_vaddr
(ring->adev) + (128 * 1024) - adev->gds.gds_size))((1 <<
12)) - 1)));
8847 }
8848
8849 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr)((u32)(gds_addr));
8850 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr)((u32)(((gds_addr) >> 16) >> 16));
8851
8852 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8853 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)((3 << 30) | (((0x37) & 0xFF) << 8) | ((cnt) &
0x3FFF) << 16));
8854 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1)((1) << 30) |
8855 WRITE_DATA_DST_SEL(8)((8) << 8) |
8856 WR_CONFIRM(1 << 20)) |
8857 WRITE_DATA_CACHE_POLICY(0)((0) << 25));
8858 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)((u32)(de_payload_gpu_addr)));
8859 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)((u32)(((de_payload_gpu_addr) >> 16) >> 16)));
8860
8861 if (resume)
8862 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8863 sizeof(de_payload) >> 2);
8864 else
8865 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8866 sizeof(de_payload) >> 2);
8867}
8868
8869static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool_Bool start,
8870 bool_Bool secure)
8871{
8872 uint32_t v = secure ? FRAME_TMZ(1 << 0) : 0;
8873
8874 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)((3 << 30) | (((0x90) & 0xFF) << 8) | ((0) &
0x3FFF) << 16));
8875 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)((start ? 0 : 1) << 28));
8876}
8877
8878static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8879 uint32_t reg_val_offs)
8880{
8881 struct amdgpu_device *adev = ring->adev;
8882
8883 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)((3 << 30) | (((0x40) & 0xFF) << 8) | ((4) &
0x3FFF) << 16));
8884 amdgpu_ring_write(ring, 0 | /* src: register*/
8885 (5 << 8) | /* dst: memory */
8886 (1 << 20)); /* write confirm */
8887 amdgpu_ring_write(ring, reg);
8888 amdgpu_ring_write(ring, 0);
8889 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +((u32)(adev->wb.gpu_addr + reg_val_offs * 4))
8890 reg_val_offs * 4)((u32)(adev->wb.gpu_addr + reg_val_offs * 4)));
8891 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16))
8892 reg_val_offs * 4)((u32)(((adev->wb.gpu_addr + reg_val_offs * 4) >> 16
) >> 16)));
8893}
8894
8895static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8896 uint32_t val)
8897{
8898 uint32_t cmd = 0;
8899
8900 switch (ring->funcs->type) {
8901 case AMDGPU_RING_TYPE_GFX:
8902 cmd = WRITE_DATA_ENGINE_SEL(1)((1) << 30) | WR_CONFIRM(1 << 20);
8903 break;
8904 case AMDGPU_RING_TYPE_KIQ:
8905 cmd = (1 << 16); /* no inc addr */
8906 break;
8907 default:
8908 cmd = WR_CONFIRM(1 << 20);
8909 break;
8910 }
8911 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)((3 << 30) | (((0x37) & 0xFF) << 8) | ((3) &
0x3FFF) << 16));
8912 amdgpu_ring_write(ring, cmd);
8913 amdgpu_ring_write(ring, reg);
8914 amdgpu_ring_write(ring, 0);
8915 amdgpu_ring_write(ring, val);
8916}
8917
8918static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8919 uint32_t val, uint32_t mask)
8920{
8921 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8922}
8923
8924static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8925 uint32_t reg0, uint32_t reg1,
8926 uint32_t ref, uint32_t mask)
8927{
8928 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8929 struct amdgpu_device *adev = ring->adev;
8930 bool_Bool fw_version_ok = false0;
8931
8932 fw_version_ok = adev->gfx.cp_fw_write_wait;
8933
8934 if (fw_version_ok)
8935 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8936 ref, mask, 0x20);
8937 else
8938 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8939 ref, mask);
8940}
8941
8942static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8943 unsigned vmid)
8944{
8945 struct amdgpu_device *adev = ring->adev;
8946 uint32_t value = 0;
8947
8948 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03)(((value) & ~0x0000000FL) | (0x0000000FL & ((0x03) <<
0x0)));
8949 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01)(((value) & ~0x00000070L) | (0x00000070L & ((0x01) <<
0x4)));
8950 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1)(((value) & ~0x00000080L) | (0x00000080L & ((1) <<
0x7)));
8951 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid)(((value) & ~0xF0000000L) | (0xF0000000L & ((vmid) <<
0x1c)));
8952 WREG32_SOC15(GC, 0, mmSQ_CMD, value)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x111b), value, 0, GC_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[GC_HWIP][0][0] + 0x111b)), (value), 0));
8953}
8954
8955static void
8956gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8957 uint32_t me, uint32_t pipe,
8958 enum amdgpu_interrupt_state state)
8959{
8960 uint32_t cp_int_cntl, cp_int_cntl_reg;
8961
8962 if (!me) {
8963 switch (pipe) {
8964 case 0:
8965 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0)(adev->reg_offset[GC_HWIP][0][0] + 0x1e0a);
8966 break;
8967 case 1:
8968 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1)(adev->reg_offset[GC_HWIP][0][0] + 0x1e0b);
8969 break;
8970 default:
8971 DRM_DEBUG("invalid pipe %d\n", pipe)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid pipe %d\n", pipe
);
8972 return;
8973 }
8974 } else {
8975 DRM_DEBUG("invalid me %d\n", me)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid me %d\n", me);
8976 return;
8977 }
8978
8979 switch (state) {
8980 case AMDGPU_IRQ_STATE_DISABLE:
8981 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, cp_int_cntl_reg, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (cp_int_cntl_reg), 0));
8982 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((0)
<< 0x1a)))
8983 TIME_STAMP_INT_ENABLE, 0)(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((0)
<< 0x1a)));
8984 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, cp_int_cntl_reg, cp_int_cntl, 0, GC_HWIP
) : amdgpu_device_wreg(adev, (cp_int_cntl_reg), (cp_int_cntl)
, 0));
8985 break;
8986 case AMDGPU_IRQ_STATE_ENABLE:
8987 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, cp_int_cntl_reg, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (cp_int_cntl_reg), 0));
8988 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((1)
<< 0x1a)))
8989 TIME_STAMP_INT_ENABLE, 1)(((cp_int_cntl) & ~0x04000000L) | (0x04000000L & ((1)
<< 0x1a)));
8990 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, cp_int_cntl_reg, cp_int_cntl, 0, GC_HWIP
) : amdgpu_device_wreg(adev, (cp_int_cntl_reg), (cp_int_cntl)
, 0));
8991 break;
8992 default:
8993 break;
8994 }
8995}
8996
8997static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8998 int me, int pipe,
8999 enum amdgpu_interrupt_state state)
9000{
9001 u32 mec_int_cntl, mec_int_cntl_reg;
9002
9003 /*
9004 * amdgpu controls only the first MEC. That's why this function only
9005 * handles the setting of interrupts for this specific MEC. All other
9006 * pipes' interrupts are set by amdkfd.
9007 */
9008
9009 if (me == 1) {
9010 switch (pipe) {
9011 case 0:
9012 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e25);
9013 break;
9014 case 1:
9015 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e26);
9016 break;
9017 case 2:
9018 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e27);
9019 break;
9020 case 3:
9021 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e28);
9022 break;
9023 default:
9024 DRM_DEBUG("invalid pipe %d\n", pipe)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid pipe %d\n", pipe
);
9025 return;
9026 }
9027 } else {
9028 DRM_DEBUG("invalid me %d\n", me)___drm_dbg(((void *)0), DRM_UT_CORE, "invalid me %d\n", me);
9029 return;
9030 }
9031
9032 switch (state) {
9033 case AMDGPU_IRQ_STATE_DISABLE:
9034 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, mec_int_cntl_reg, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (mec_int_cntl_reg), 0));
9035 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)))
9036 TIME_STAMP_INT_ENABLE, 0)(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((0
) << 0x1a)));
9037 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, mec_int_cntl_reg, mec_int_cntl, 0
, GC_HWIP) : amdgpu_device_wreg(adev, (mec_int_cntl_reg), (mec_int_cntl
), 0));
9038 break;
9039 case AMDGPU_IRQ_STATE_ENABLE:
9040 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, mec_int_cntl_reg, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (mec_int_cntl_reg), 0));
9041 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)))
9042 TIME_STAMP_INT_ENABLE, 1)(((mec_int_cntl) & ~0x04000000L) | (0x04000000L & ((1
) << 0x1a)));
9043 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, mec_int_cntl_reg, mec_int_cntl, 0
, GC_HWIP) : amdgpu_device_wreg(adev, (mec_int_cntl_reg), (mec_int_cntl
), 0));
9044 break;
9045 default:
9046 break;
9047 }
9048}
9049
9050static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9051 struct amdgpu_irq_src *src,
9052 unsigned type,
9053 enum amdgpu_interrupt_state state)
9054{
9055 switch (type) {
9056 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9057 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9058 break;
9059 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9060 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9061 break;
9062 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9063 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9064 break;
9065 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9066 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9067 break;
9068 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9069 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9070 break;
9071 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9072 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9073 break;
9074 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9075 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9076 break;
9077 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9078 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9079 break;
9080 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9081 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9082 break;
9083 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9084 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9085 break;
9086 default:
9087 break;
9088 }
9089 return 0;
9090}
9091
9092static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9093 struct amdgpu_irq_src *source,
9094 struct amdgpu_iv_entry *entry)
9095{
9096 int i;
9097 u8 me_id, pipe_id, queue_id;
9098 struct amdgpu_ring *ring;
9099 uint32_t mes_queue_id = entry->src_data[0];
9100
9101 DRM_DEBUG("IH: CP EOP\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: CP EOP\n");
9102
9103 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG0x1000000u)) {
9104 struct amdgpu_mes_queue *queue;
9105
9106 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK(0x1000000u - 1);
9107
9108 spin_lock(&adev->mes.queue_id_lock)mtx_enter(&adev->mes.queue_id_lock);
9109 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9110 if (queue) {
9111 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id)___drm_dbg(((void *)0), DRM_UT_CORE, "process mes queue id = %d\n"
, mes_queue_id);
9112 amdgpu_fence_process(queue->ring);
9113 }
9114 spin_unlock(&adev->mes.queue_id_lock)mtx_leave(&adev->mes.queue_id_lock);
9115 } else {
9116 me_id = (entry->ring_id & 0x0c) >> 2;
9117 pipe_id = (entry->ring_id & 0x03) >> 0;
9118 queue_id = (entry->ring_id & 0x70) >> 4;
9119
9120 switch (me_id) {
9121 case 0:
9122 if (pipe_id == 0)
9123 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9124 else
9125 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9126 break;
9127 case 1:
9128 case 2:
9129 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9130 ring = &adev->gfx.compute_ring[i];
9131 /* Per-queue interrupt is supported for MEC starting from VI.
9132 * The interrupt can only be enabled/disabled per pipe instead
9133 * of per queue.
9134 */
9135 if ((ring->me == me_id) &&
9136 (ring->pipe == pipe_id) &&
9137 (ring->queue == queue_id))
9138 amdgpu_fence_process(ring);
9139 }
9140 break;
9141 }
9142 }
9143
9144 return 0;
9145}
9146
9147static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9148 struct amdgpu_irq_src *source,
9149 unsigned type,
9150 enum amdgpu_interrupt_state state)
9151{
9152 switch (state) {
9153 case AMDGPU_IRQ_STATE_DISABLE:
9154 case AMDGPU_IRQ_STATE_ENABLE:
9155 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) & ~0x00800000L) |
(state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x17, 0,
GC_HWIP) : amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), ((((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) &
~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) <<
0x17), 0))
9156 PRIV_REG_INT_ENABLE,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) & ~0x00800000L) |
(state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x17, 0,
GC_HWIP) : amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), ((((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) &
~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) <<
0x17), 0))
9157 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) & ~0x00800000L) |
(state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x17, 0,
GC_HWIP) : amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), ((((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) &
~0x00800000L) | (state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) <<
0x17), 0));
9158 break;
9159 default:
9160 break;
9161 }
9162
9163 return 0;
9164}
9165
9166static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9167 struct amdgpu_irq_src *source,
9168 unsigned type,
9169 enum amdgpu_interrupt_state state)
9170{
9171 switch (state) {
9172 case AMDGPU_IRQ_STATE_DISABLE:
9173 case AMDGPU_IRQ_STATE_ENABLE:
9174 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) & ~0x00400000L) |
(state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x16, 0,
GC_HWIP) : amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), ((((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) &
~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) <<
0x16), 0))
9175 PRIV_INSTR_INT_ENABLE,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) & ~0x00400000L) |
(state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x16, 0,
GC_HWIP) : amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), ((((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) &
~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) <<
0x16), 0))
9176 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) & ~0x00400000L) |
(state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) << 0x16, 0,
GC_HWIP) : amdgpu_device_wreg(adev, (adev->reg_offset[GC_HWIP
][0][0] + 0x1e0a), ((((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg(adev, adev
->reg_offset[GC_HWIP][0][0] + 0x1e0a, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (adev->reg_offset[GC_HWIP][0][0] + 0x1e0a), 0)) &
~0x00400000L) | (state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0) <<
0x16), 0));
9177 break;
9178 default:
9179 break;
9180 }
9181
9182 return 0;
9183}
9184
9185static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9186 struct amdgpu_iv_entry *entry)
9187{
9188 u8 me_id, pipe_id, queue_id;
9189 struct amdgpu_ring *ring;
9190 int i;
9191
9192 me_id = (entry->ring_id & 0x0c) >> 2;
9193 pipe_id = (entry->ring_id & 0x03) >> 0;
9194 queue_id = (entry->ring_id & 0x70) >> 4;
9195
9196 switch (me_id) {
9197 case 0:
9198 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9199 ring = &adev->gfx.gfx_ring[i];
9200 /* we only enabled 1 gfx queue per pipe for now */
9201 if (ring->me == me_id && ring->pipe == pipe_id)
9202 drm_sched_fault(&ring->sched);
9203 }
9204 break;
9205 case 1:
9206 case 2:
9207 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9208 ring = &adev->gfx.compute_ring[i];
9209 if (ring->me == me_id && ring->pipe == pipe_id &&
9210 ring->queue == queue_id)
9211 drm_sched_fault(&ring->sched);
9212 }
9213 break;
9214 default:
9215 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 9215); } while (0);
9216 }
9217}
9218
9219static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9220 struct amdgpu_irq_src *source,
9221 struct amdgpu_iv_entry *entry)
9222{
9223 DRM_ERROR("Illegal register access in command stream\n")__drm_err("Illegal register access in command stream\n");
9224 gfx_v10_0_handle_priv_fault(adev, entry);
9225 return 0;
9226}
9227
9228static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9229 struct amdgpu_irq_src *source,
9230 struct amdgpu_iv_entry *entry)
9231{
9232 DRM_ERROR("Illegal instruction in command stream\n")__drm_err("Illegal instruction in command stream\n");
9233 gfx_v10_0_handle_priv_fault(adev, entry);
9234 return 0;
9235}
9236
9237static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9238 struct amdgpu_irq_src *src,
9239 unsigned int type,
9240 enum amdgpu_interrupt_state state)
9241{
9242 uint32_t tmp, target;
9243 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9244
9245 if (ring->me == 1)
9246 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e25);
9247 else
9248 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL)(adev->reg_offset[GC_HWIP][0][0] + 0x1e29);
9249 target += ring->pipe;
9250
9251 switch (type) {
9252 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9253 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9254 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e54, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e54), 0));
9255 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)))
9256 GENERIC2_INT_ENABLE, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
9257 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e54), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1e54)), (tmp), 0));
9258
9259 tmp = RREG32_SOC15_IP(GC, target)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, target, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (target), 0));
9260 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)))
9261 GENERIC2_INT_ENABLE, 0)(((tmp) & ~0x20000000L) | (0x20000000L & ((0) <<
0x1d)));
9262 WREG32_SOC15_IP(GC, target, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target, tmp, 0, GC_HWIP) : amdgpu_device_wreg
(adev, (target), (tmp), 0));
9263 } else {
9264 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1e54, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1e54), 0));
9265 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)))
9266 GENERIC2_INT_ENABLE, 1)(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
9267 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1e54), tmp, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][0] + 0x1e54)), (tmp), 0));
9268
9269 tmp = RREG32_SOC15_IP(GC, target)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, target, 0, GC_HWIP) : amdgpu_device_rreg
(adev, (target), 0));
9270 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)))
9271 GENERIC2_INT_ENABLE, 1)(((tmp) & ~0x20000000L) | (0x20000000L & ((1) <<
0x1d)));
9272 WREG32_SOC15_IP(GC, target, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, target, tmp, 0, GC_HWIP) : amdgpu_device_wreg
(adev, (target), (tmp), 0));
9273 }
9274 break;
9275 default:
9276 BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/amd/amdgpu/gfx_v10_0.c"
, 9276); } while (0); /* kiq only support GENERIC2_INT now */
9277 break;
9278 }
9279 return 0;
9280}
9281
9282static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9283 struct amdgpu_irq_src *source,
9284 struct amdgpu_iv_entry *entry)
9285{
9286 u8 me_id, pipe_id, queue_id;
9287 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9288
9289 me_id = (entry->ring_id & 0x0c) >> 2;
9290 pipe_id = (entry->ring_id & 0x03) >> 0;
9291 queue_id = (entry->ring_id & 0x70) >> 4;
9292 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",___drm_dbg(((void *)0), DRM_UT_CORE, "IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n"
, me_id, pipe_id, queue_id)
9293 me_id, pipe_id, queue_id)___drm_dbg(((void *)0), DRM_UT_CORE, "IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n"
, me_id, pipe_id, queue_id);
9294
9295 amdgpu_fence_process(ring);
9296 return 0;
9297}
9298
9299static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9300{
9301 const unsigned int gcr_cntl =
9302 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1)((1) << 14) |
9303 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1)((1) << 15) |
9304 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1)((1) << 5) |
9305 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1)((1) << 4) |
9306 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1)((1) << 9) |
9307 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1)((1) << 8) |
9308 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1)((1) << 7) |
9309 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1)((1) << 0);
9310
9311 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9312 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)((3 << 30) | (((0x58) & 0xFF) << 8) | ((6) &
0x3FFF) << 16));
9313 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9314 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9315 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9316 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9317 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9318 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9319 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9320}
9321
9322static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9323 .name = "gfx_v10_0",
9324 .early_init = gfx_v10_0_early_init,
9325 .late_init = gfx_v10_0_late_init,
9326 .sw_init = gfx_v10_0_sw_init,
9327 .sw_fini = gfx_v10_0_sw_fini,
9328 .hw_init = gfx_v10_0_hw_init,
9329 .hw_fini = gfx_v10_0_hw_fini,
9330 .suspend = gfx_v10_0_suspend,
9331 .resume = gfx_v10_0_resume,
9332 .is_idle = gfx_v10_0_is_idle,
9333 .wait_for_idle = gfx_v10_0_wait_for_idle,
9334 .soft_reset = gfx_v10_0_soft_reset,
9335 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9336 .set_powergating_state = gfx_v10_0_set_powergating_state,
9337 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9338};
9339
9340static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9341 .type = AMDGPU_RING_TYPE_GFX,
9342 .align_mask = 0xff,
9343 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
9344 .support_64bit_ptrs = true1,
9345 .secure_submission_supported = true1,
9346 .vmhub = AMDGPU_GFXHUB_00,
9347 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9348 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9349 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9350 .emit_frame_size = /* totally 242 maximum if 16 IBs */
9351 5 + /* COND_EXEC */
9352 7 + /* PIPELINE_SYNC */
9353 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
9354 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
9355 2 + /* VM_FLUSH */
9356 8 + /* FENCE for VM_FLUSH */
9357 20 + /* GDS switch */
9358 4 + /* double SWITCH_BUFFER,
9359 * the first COND_EXEC jump to the place
9360 * just prior to this double SWITCH_BUFFER
9361 */
9362 5 + /* COND_EXEC */
9363 7 + /* HDP_flush */
9364 4 + /* VGT_flush */
9365 14 + /* CE_META */
9366 31 + /* DE_META */
9367 3 + /* CNTX_CTRL */
9368 5 + /* HDP_INVL */
9369 8 + 8 + /* FENCE x2 */
9370 2 + /* SWITCH_BUFFER */
9371 8, /* gfx_v10_0_emit_mem_sync */
9372 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9373 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9374 .emit_fence = gfx_v10_0_ring_emit_fence,
9375 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9376 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9377 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9378 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9379 .test_ring = gfx_v10_0_ring_test_ring,
9380 .test_ib = gfx_v10_0_ring_test_ib,
9381 .insert_nop = amdgpu_ring_insert_nop,
9382 .pad_ib = amdgpu_ring_generic_pad_ib,
9383 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9384 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9385 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9386 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9387 .preempt_ib = gfx_v10_0_ring_preempt_ib,
9388 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9389 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9390 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9391 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9392 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9393 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9394};
9395
9396static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9397 .type = AMDGPU_RING_TYPE_COMPUTE,
9398 .align_mask = 0xff,
9399 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
9400 .support_64bit_ptrs = true1,
9401 .vmhub = AMDGPU_GFXHUB_00,
9402 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9403 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9404 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9405 .emit_frame_size =
9406 20 + /* gfx_v10_0_ring_emit_gds_switch */
9407 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9408 5 + /* hdp invalidate */
9409 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9410 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
9411 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
9412 2 + /* gfx_v10_0_ring_emit_vm_flush */
9413 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9414 8, /* gfx_v10_0_emit_mem_sync */
9415 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9416 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9417 .emit_fence = gfx_v10_0_ring_emit_fence,
9418 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9419 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9420 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9421 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9422 .test_ring = gfx_v10_0_ring_test_ring,
9423 .test_ib = gfx_v10_0_ring_test_ib,
9424 .insert_nop = amdgpu_ring_insert_nop,
9425 .pad_ib = amdgpu_ring_generic_pad_ib,
9426 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9427 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9428 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9429 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9430};
9431
9432static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9433 .type = AMDGPU_RING_TYPE_KIQ,
9434 .align_mask = 0xff,
9435 .nop = PACKET3(PACKET3_NOP, 0x3FFF)((3 << 30) | (((0x10) & 0xFF) << 8) | ((0x3FFF
) & 0x3FFF) << 16),
9436 .support_64bit_ptrs = true1,
9437 .vmhub = AMDGPU_GFXHUB_00,
9438 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9439 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9440 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9441 .emit_frame_size =
9442 20 + /* gfx_v10_0_ring_emit_gds_switch */
9443 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9444 5 + /*hdp invalidate */
9445 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9446 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 5 +
9447 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 7 +
9448 2 + /* gfx_v10_0_ring_emit_vm_flush */
9449 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9450 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9451 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9452 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9453 .test_ring = gfx_v10_0_ring_test_ring,
9454 .test_ib = gfx_v10_0_ring_test_ib,
9455 .insert_nop = amdgpu_ring_insert_nop,
9456 .pad_ib = amdgpu_ring_generic_pad_ib,
9457 .emit_rreg = gfx_v10_0_ring_emit_rreg,
9458 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9459 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9460 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9461};
9462
9463static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9464{
9465 int i;
9466
9467 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9468
9469 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9470 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9471
9472 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9473 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9474}
9475
9476static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9477 .set = gfx_v10_0_set_eop_interrupt_state,
9478 .process = gfx_v10_0_eop_irq,
9479};
9480
9481static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9482 .set = gfx_v10_0_set_priv_reg_fault_state,
9483 .process = gfx_v10_0_priv_reg_irq,
9484};
9485
9486static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9487 .set = gfx_v10_0_set_priv_inst_fault_state,
9488 .process = gfx_v10_0_priv_inst_irq,
9489};
9490
9491static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9492 .set = gfx_v10_0_kiq_set_interrupt_state,
9493 .process = gfx_v10_0_kiq_irq,
9494};
9495
9496static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9497{
9498 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9499 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9500
9501 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9502 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9503
9504 adev->gfx.priv_reg_irq.num_types = 1;
9505 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9506
9507 adev->gfx.priv_inst_irq.num_types = 1;
9508 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9509}
9510
9511static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9512{
9513 switch (adev->ip_versions[GC_HWIP][0]) {
9514 case IP_VERSION(10, 1, 10)(((10) << 16) | ((1) << 8) | (10)):
9515 case IP_VERSION(10, 1, 1)(((10) << 16) | ((1) << 8) | (1)):
9516 case IP_VERSION(10, 1, 3)(((10) << 16) | ((1) << 8) | (3)):
9517 case IP_VERSION(10, 1, 4)(((10) << 16) | ((1) << 8) | (4)):
9518 case IP_VERSION(10, 3, 2)(((10) << 16) | ((3) << 8) | (2)):
9519 case IP_VERSION(10, 3, 1)(((10) << 16) | ((3) << 8) | (1)):
9520 case IP_VERSION(10, 3, 4)(((10) << 16) | ((3) << 8) | (4)):
9521 case IP_VERSION(10, 3, 5)(((10) << 16) | ((3) << 8) | (5)):
9522 case IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6)):
9523 case IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3)):
9524 case IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)):
9525 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9526 break;
9527 case IP_VERSION(10, 1, 2)(((10) << 16) | ((1) << 8) | (2)):
9528 case IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0)):
9529 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9530 break;
9531 default:
9532 break;
9533 }
9534}
9535
9536static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9537{
9538 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9539 adev->gfx.config.max_sh_per_se *
9540 adev->gfx.config.max_shader_engines;
9541
9542 adev->gds.gds_size = 0x10000;
9543 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9544 adev->gds.gws_size = 64;
9545 adev->gds.oa_size = 16;
9546}
9547
9548static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9549{
9550 /* set gfx eng mqd */
9551 adev->mqds[AMDGPU_HW_IP_GFX0].mqd_size =
9552 sizeof(struct v10_gfx_mqd);
9553 adev->mqds[AMDGPU_HW_IP_GFX0].init_mqd =
9554 gfx_v10_0_gfx_mqd_init;
9555 /* set compute eng mqd */
9556 adev->mqds[AMDGPU_HW_IP_COMPUTE1].mqd_size =
9557 sizeof(struct v10_compute_mqd);
9558 adev->mqds[AMDGPU_HW_IP_COMPUTE1].init_mqd =
9559 gfx_v10_0_compute_mqd_init;
9560}
9561
9562static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9563 u32 bitmap)
9564{
9565 u32 data;
9566
9567 if (!bitmap)
9568 return;
9569
9570 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT0x10;
9571 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK0xFFFF0000L;
9572
9573 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x1010), data, 0, GC_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[GC_HWIP][0][0] + 0x1010)), (data), 0));
9574}
9575
9576static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9577{
9578 u32 disabled_mask =
9579 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9580 u32 efuse_setting = 0;
9581 u32 vbios_setting = 0;
9582
9583 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x100f, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x100f), 0));
9584 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK0xFFFF0000L;
9585 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT0x10;
9586
9587 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1010, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1010), 0));
9588 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK0xFFFF0000L;
9589 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT0x10;
9590
9591 disabled_mask |= efuse_setting | vbios_setting;
9592
9593 return (~disabled_mask);
9594}
9595
9596static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9597{
9598 u32 wgp_idx, wgp_active_bitmap;
9599 u32 cu_bitmap_per_wgp, cu_active_bitmap;
9600
9601 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9602 cu_active_bitmap = 0;
9603
9604 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9605 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9606 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9607 if (wgp_active_bitmap & (1 << wgp_idx))
9608 cu_active_bitmap |= cu_bitmap_per_wgp;
9609 }
9610
9611 return cu_active_bitmap;
9612}
9613
9614static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9615 struct amdgpu_cu_info *cu_info)
9616{
9617 int i, j, k, counter, active_cu_number = 0;
9618 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9619 unsigned disable_masks[4 * 2];
9620
9621 if (!adev || !cu_info)
9622 return -EINVAL22;
9623
9624 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9625
9626 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
9627 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9628 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9629 bitmap = i * adev->gfx.config.max_sh_per_se + j;
9630 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0))) ||
9631 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)(((10) << 16) | ((3) << 8) | (3))) ||
9632 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)(((10) << 16) | ((3) << 8) | (6))) ||
9633 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7)(((10) << 16) | ((3) << 8) | (7)))) &&
9634 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9635 continue;
9636 mask = 1;
9637 ao_bitmap = 0;
9638 counter = 0;
9639 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9640 if (i < 4 && j < 2)
9641 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9642 adev, disable_masks[i * 2 + j]);
9643 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9644 cu_info->bitmap[i][j] = bitmap;
9645
9646 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9647 if (bitmap & mask) {
9648 if (counter < adev->gfx.config.max_cu_per_sh)
9649 ao_bitmap |= mask;
9650 counter++;
9651 }
9652 mask <<= 1;
9653 }
9654 active_cu_number += counter;
9655 if (i < 2 && j < 2)
9656 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9657 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9658 }
9659 }
9660 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9661 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
9662
9663 cu_info->number = active_cu_number;
9664 cu_info->ao_cu_mask = ao_cu_mask;
9665 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9666
9667 return 0;
9668}
9669
9670static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9671{
9672 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9673
9674 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0fe9, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0fe9), 0));
9675 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L;
9676 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8;
9677
9678 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x0fea, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x0fea), 0));
9679 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK0x0000FF00L;
9680 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT0x8;
9681
9682 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9683 adev->gfx.config.max_shader_engines);
9684 disabled_sa = efuse_setting | vbios_setting;
9685 disabled_sa &= max_sa_mask;
9686
9687 return disabled_sa;
9688}
9689
9690static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9691{
9692 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9693 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9694
9695 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9696
9697 max_sa_per_se = adev->gfx.config.max_sh_per_se;
9698 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9699 max_shader_engines = adev->gfx.config.max_shader_engines;
9700
9701 for (se_index = 0; max_shader_engines > se_index; se_index++) {
9702 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9703 disabled_sa_per_se &= max_sa_per_se_mask;
9704 if (disabled_sa_per_se == max_sa_per_se_mask) {
9705 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1085, (((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[GC_HWIP][0][0
] + 0x1085, 0, GC_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[GC_HWIP][0][0] + 0x1085), 0)) & ~0x00000008L) |
(1) << 0x3, 0, GC_HWIP) : amdgpu_device_wreg(adev, (adev
->reg_offset[GC_HWIP][0][0] + 0x1085), ((((((adev)->virt
.caps & (1 << 2)) && adev->gfx.rlc.funcs
&& adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_rreg
(adev, adev->reg_offset[GC_HWIP][0][0] + 0x1085, 0, GC_HWIP
) : amdgpu_device_rreg(adev, (adev->reg_offset[GC_HWIP][0]
[0] + 0x1085), 0)) & ~0x00000008L) | (1) << 0x3), 0
));
9706 break;
9707 }
9708 }
9709}
9710
9711static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9712{
9713 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2200), (0x1 << 0x1d) | (0x1 << 0x1e) | (0x1
<< 0x1f), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x2200)), ((0x1 << 0x1d
) | (0x1 << 0x1e) | (0x1 << 0x1f)), 0))
9714 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2200), (0x1 << 0x1d) | (0x1 << 0x1e) | (0x1
<< 0x1f), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x2200)), ((0x1 << 0x1d
) | (0x1 << 0x1e) | (0x1 << 0x1f)), 0))
9715 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2200), (0x1 << 0x1d) | (0x1 << 0x1e) | (0x1
<< 0x1f), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x2200)), ((0x1 << 0x1d
) | (0x1 << 0x1e) | (0x1 << 0x1f)), 0))
9716 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
1] + 0x2200), (0x1 << 0x1d) | (0x1 << 0x1e) | (0x1
<< 0x1f), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[GC_HWIP][0][1] + 0x2200)), ((0x1 << 0x1d
) | (0x1 << 0x1e) | (0x1 << 0x1f)), 0));
9717
9718 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x203c), 0x0001, 0, GC_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[GC_HWIP][0][0] + 0x203c)), (0x0001), 0));
9719 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x203d), (0x1 << 0x0) | (0x12 << 0xa) | (0x13
<< 0xf) | (0xf << 0x14), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x203d)), ((0x1
<< 0x0) | (0x12 << 0xa) | (0x13 << 0xf) | (
0xf << 0x14)), 0))
9720 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x203d), (0x1 << 0x0) | (0x12 << 0xa) | (0x13
<< 0xf) | (0xf << 0x14), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x203d)), ((0x1
<< 0x0) | (0x12 << 0xa) | (0x13 << 0xf) | (
0xf << 0x14)), 0))
9721 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x203d), (0x1 << 0x0) | (0x12 << 0xa) | (0x13
<< 0xf) | (0xf << 0x14), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x203d)), ((0x1
<< 0x0) | (0x12 << 0xa) | (0x13 << 0xf) | (
0xf << 0x14)), 0))
9722 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x203d), (0x1 << 0x0) | (0x12 << 0xa) | (0x13
<< 0xf) | (0xf << 0x14), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x203d)), ((0x1
<< 0x0) | (0x12 << 0xa) | (0x13 << 0xf) | (
0xf << 0x14)), 0))
9723 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x203d), (0x1 << 0x0) | (0x12 << 0xa) | (0x13
<< 0xf) | (0xf << 0x14), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x203d)), ((0x1
<< 0x0) | (0x12 << 0xa) | (0x13 << 0xf) | (
0xf << 0x14)), 0));
9724
9725 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2030), (0x1 << 0x2) | (0x1 << 0x5) | (0x5 <<
0xd), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x2030)), ((0x1 << 0x2) | (0x1 <<
0x5) | (0x5 << 0xd)), 0))
9726 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2030), (0x1 << 0x2) | (0x1 << 0x5) | (0x5 <<
0xd), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x2030)), ((0x1 << 0x2) | (0x1 <<
0x5) | (0x5 << 0xd)), 0))
9727 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2030), (0x1 << 0x2) | (0x1 << 0x5) | (0x5 <<
0xd), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x2030)), ((0x1 << 0x2) | (0x1 <<
0x5) | (0x5 << 0xd)), 0))
9728 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2030), (0x1 << 0x2) | (0x1 << 0x5) | (0x5 <<
0xd), 0, GC_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[GC_HWIP][0][0] + 0x2030)), ((0x1 << 0x2) | (0x1 <<
0x5) | (0x5 << 0xd)), 0));
9729
9730 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2020), 0x001a, 0, GC_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[GC_HWIP][0][0] + 0x2020)), (0x001a), 0));
9731
9732 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2021), (0x1 << 0x2), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x2021)), ((0x1
<< 0x2)), 0))
9733 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[GC_HWIP][0][
0] + 0x2021), (0x1 << 0x2), 0, GC_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[GC_HWIP][0][0] + 0x2021)), ((0x1
<< 0x2)), 0));
9734}
9735
9736const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9737{
9738 .type = AMD_IP_BLOCK_TYPE_GFX,
9739 .major = 10,
9740 .minor = 0,
9741 .rev = 0,
9742 .funcs = &gfx_v10_0_ip_funcs,
9743};