Bug Summary

File:dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
Warning:line 206, column 6
Access to field 'hwmgr_func' results in a dereference of a null pointer (loaded from variable 'hwmgr')

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name amd_powerplay.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/powerplay/amd_powerplay.c
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "pp_debug.h"
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/gfp.h>
27#include <linux/slab.h>
28#include <linux/firmware.h>
29#include <linux/reboot.h>
30#include "amd_shared.h"
31#include "amd_powerplay.h"
32#include "power_state.h"
33#include "amdgpu.h"
34#include "hwmgr.h"
35#include "amdgpu_dpm_internal.h"
36#include "amdgpu_display.h"
37
38static const struct amd_pm_funcs pp_dpm_funcs;
39
40static int amd_powerplay_create(struct amdgpu_device *adev)
41{
42 struct pp_hwmgr *hwmgr;
43
44 if (adev == NULL((void *)0))
45 return -EINVAL22;
46
47 hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL(0x0001 | 0x0004));
48 if (hwmgr == NULL((void *)0))
49 return -ENOMEM12;
50
51 hwmgr->adev = adev;
52 hwmgr->not_vf = !amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2));
53 hwmgr->device = amdgpu_cgs_create_device(adev);
54 rw_init(&hwmgr->msg_lock, "ppmsg")_rw_init_flags(&hwmgr->msg_lock, "ppmsg", 0, ((void *)
0));
55 hwmgr->chip_family = adev->family;
56 hwmgr->chip_id = adev->asic_type;
57 hwmgr->feature_mask = adev->pm.pp_feature;
58 hwmgr->display_config = &adev->pm.pm_display_cfg;
59 adev->powerplay.pp_handle = hwmgr;
60 adev->powerplay.pp_funcs = &pp_dpm_funcs;
61 return 0;
62}
63
64
65static void amd_powerplay_destroy(struct amdgpu_device *adev)
66{
67 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
68
69 mutex_destroy(&hwmgr->msg_lock);
70
71 kfree(hwmgr->hardcode_pp_table);
72 hwmgr->hardcode_pp_table = NULL((void *)0);
73
74 kfree(hwmgr);
75 hwmgr = NULL((void *)0);
76}
77
78static int pp_early_init(void *handle)
79{
80 int ret;
81 struct amdgpu_device *adev = handle;
82
83 ret = amd_powerplay_create(adev);
84
85 if (ret != 0)
86 return ret;
87
88 ret = hwmgr_early_init(adev->powerplay.pp_handle);
89 if (ret)
90 return -EINVAL22;
91
92 return 0;
93}
94
95static void pp_swctf_delayed_work_handler(struct work_struct *work)
96{
97 struct pp_hwmgr *hwmgr =
98 container_of(work, struct pp_hwmgr, swctf_delayed_work.work)({ const __typeof( ((struct pp_hwmgr *)0)->swctf_delayed_work
.work ) *__mptr = (work); (struct pp_hwmgr *)( (char *)__mptr
- __builtin_offsetof(struct pp_hwmgr, swctf_delayed_work.work
) );});
99 struct amdgpu_device *adev = hwmgr->adev;
100 struct amdgpu_dpm_thermal *range =
101 &adev->pm.dpm.thermal;
102 uint32_t gpu_temperature, size;
103 int ret;
104
105 /*
106 * If the hotspot/edge temperature is confirmed as below SW CTF setting point
107 * after the delay enforced, nothing will be done.
108 * Otherwise, a graceful shutdown will be performed to prevent further damage.
109 */
110 if (range->sw_ctf_threshold &&
111 hwmgr->hwmgr_func->read_sensor) {
112 ret = hwmgr->hwmgr_func->read_sensor(hwmgr,
113 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
114 &gpu_temperature,
115 &size);
116 /*
117 * For some legacy ASICs, hotspot temperature retrieving might be not
118 * supported. Check the edge temperature instead then.
119 */
120 if (ret == -EOPNOTSUPP45)
121 ret = hwmgr->hwmgr_func->read_sensor(hwmgr,
122 AMDGPU_PP_SENSOR_EDGE_TEMP,
123 &gpu_temperature,
124 &size);
125 if (!ret && gpu_temperature / 1000 < range->sw_ctf_threshold)
126 return;
127 }
128
129 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: GPU over temperature range(SW CTF) detected!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
130 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n")printf("drm:pid%d:%s *EMERGENCY* " "ERROR: System is going to shutdown due to GPU SW CTF!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
131 orderly_poweroff(true1);
132}
133
134static int pp_sw_init(void *handle)
135{
136 struct amdgpu_device *adev = handle;
137 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
138 int ret = 0;
139
140 ret = hwmgr_sw_init(hwmgr);
141
142 pr_debug("powerplay sw init %s\n", ret ? "failed" : "successfully")do { } while(0);
143
144 if (!ret)
145 INIT_DELAYED_WORK(&hwmgr->swctf_delayed_work,
146 pp_swctf_delayed_work_handler);
147
148 return ret;
149}
150
151static int pp_sw_fini(void *handle)
152{
153 struct amdgpu_device *adev = handle;
154 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
155
156 hwmgr_sw_fini(hwmgr);
157
158 release_firmware(adev->pm.fw);
159 adev->pm.fw = NULL((void *)0);
160
161 return 0;
162}
163
164static int pp_hw_init(void *handle)
165{
166 int ret = 0;
167 struct amdgpu_device *adev = handle;
168 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
169
170 ret = hwmgr_hw_init(hwmgr);
171
172 if (ret)
173 pr_err("powerplay hw init failed\n")printk("\0013" "amdgpu: " "powerplay hw init failed\n");
174
175 return ret;
176}
177
178static int pp_hw_fini(void *handle)
179{
180 struct amdgpu_device *adev = handle;
181 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
182
183 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work);
184
185 hwmgr_hw_fini(hwmgr);
186
187 return 0;
188}
189
190static void pp_reserve_vram_for_smu(struct amdgpu_device *adev)
191{
192 int r = -EINVAL22;
193 void *cpu_ptr = NULL((void *)0);
194 uint64_t gpu_addr;
195 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
5
←
'hwmgr' initialized to a null pointer value
→
196
197 if (amdgpu_bo_create_kernel(adev, adev->pm.smu_prv_buffer_size,
6
←
Assuming the condition is false
→
7
←
Taking false branch
→
198 PAGE_SIZE(1 << 12), AMDGPU_GEM_DOMAIN_GTT0x2,
199 &adev->pm.smu_prv_buffer,
200 &gpu_addr,
201 &cpu_ptr)) {
202 DRM_ERROR("amdgpu: failed to create smu prv buffer\n")__drm_err("amdgpu: failed to create smu prv buffer\n");
203 return;
204 }
205
206 if (hwmgr->hwmgr_func->notify_cac_buffer_info)
8
←
Access to field 'hwmgr_func' results in a dereference of a null pointer (loaded from variable 'hwmgr')
207 r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
208 lower_32_bits((unsigned long)cpu_ptr)((u32)((unsigned long)cpu_ptr)),
209 upper_32_bits((unsigned long)cpu_ptr)((u32)((((unsigned long)cpu_ptr) >> 16) >> 16)),
210 lower_32_bits(gpu_addr)((u32)(gpu_addr)),
211 upper_32_bits(gpu_addr)((u32)(((gpu_addr) >> 16) >> 16)),
212 adev->pm.smu_prv_buffer_size);
213
214 if (r) {
215 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL((void *)0), NULL((void *)0));
216 adev->pm.smu_prv_buffer = NULL((void *)0);
217 DRM_ERROR("amdgpu: failed to notify SMU buffer address\n")__drm_err("amdgpu: failed to notify SMU buffer address\n");
218 }
219}
220
221static int pp_late_init(void *handle)
222{
223 struct amdgpu_device *adev = handle;
224 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
225
226 if (hwmgr && hwmgr->pm_en)
1
Assuming 'hwmgr' is null
→
227 hwmgr_handle_task(hwmgr,
228 AMD_PP_TASK_COMPLETE_INIT, NULL((void *)0));
229 if (adev->pm.smu_prv_buffer_size != 0)
2
←
Assuming field 'smu_prv_buffer_size' is not equal to 0
→
3
←
Taking true branch
→
230 pp_reserve_vram_for_smu(adev);
4
←
Calling 'pp_reserve_vram_for_smu'
→
231
232 return 0;
233}
234
235static void pp_late_fini(void *handle)
236{
237 struct amdgpu_device *adev = handle;
238
239 if (adev->pm.smu_prv_buffer)
240 amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL((void *)0), NULL((void *)0));
241 amd_powerplay_destroy(adev);
242}
243
244
245static bool_Bool pp_is_idle(void *handle)
246{
247 return false0;
248}
249
250static int pp_wait_for_idle(void *handle)
251{
252 return 0;
253}
254
255static int pp_sw_reset(void *handle)
256{
257 return 0;
258}
259
260static int pp_set_powergating_state(void *handle,
261 enum amd_powergating_state state)
262{
263 return 0;
264}
265
266static int pp_suspend(void *handle)
267{
268 struct amdgpu_device *adev = handle;
269 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
270
271 cancel_delayed_work_sync(&hwmgr->swctf_delayed_work);
272
273 return hwmgr_suspend(hwmgr);
274}
275
276static int pp_resume(void *handle)
277{
278 struct amdgpu_device *adev = handle;
279 struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
280
281 return hwmgr_resume(hwmgr);
282}
283
284static int pp_set_clockgating_state(void *handle,
285 enum amd_clockgating_state state)
286{
287 return 0;
288}
289
290static const struct amd_ip_funcs pp_ip_funcs = {
291 .name = "powerplay",
292 .early_init = pp_early_init,
293 .late_init = pp_late_init,
294 .sw_init = pp_sw_init,
295 .sw_fini = pp_sw_fini,
296 .hw_init = pp_hw_init,
297 .hw_fini = pp_hw_fini,
298 .late_fini = pp_late_fini,
299 .suspend = pp_suspend,
300 .resume = pp_resume,
301 .is_idle = pp_is_idle,
302 .wait_for_idle = pp_wait_for_idle,
303 .soft_reset = pp_sw_reset,
304 .set_clockgating_state = pp_set_clockgating_state,
305 .set_powergating_state = pp_set_powergating_state,
306};
307
308const struct amdgpu_ip_block_version pp_smu_ip_block =
309{
310 .type = AMD_IP_BLOCK_TYPE_SMC,
311 .major = 1,
312 .minor = 0,
313 .rev = 0,
314 .funcs = &pp_ip_funcs,
315};
316
317/* This interface only be supported On Vi,
318 * because only smu7/8 can help to load gfx/sdma fw,
319 * smu need to be enabled before load other ip's fw.
320 * so call start smu to load smu7 fw and other ip's fw
321 */
322static int pp_dpm_load_fw(void *handle)
323{
324 struct pp_hwmgr *hwmgr = handle;
325
326 if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
327 return -EINVAL22;
328
329 if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
330 pr_err("fw load failed\n")printk("\0013" "amdgpu: " "fw load failed\n");
331 return -EINVAL22;
332 }
333
334 return 0;
335}
336
337static int pp_dpm_fw_loading_complete(void *handle)
338{
339 return 0;
340}
341
342static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id)
343{
344 struct pp_hwmgr *hwmgr = handle;
345
346 if (!hwmgr || !hwmgr->pm_en)
347 return -EINVAL22;
348
349 if (hwmgr->hwmgr_func->update_clock_gatings == NULL((void *)0)) {
350 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
351 return 0;
352 }
353
354 return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
355}
356
357static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr,
358 enum amd_dpm_forced_level *level)
359{
360 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
361 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
362 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
363 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
364
365 if (!(hwmgr->dpm_level & profile_mode_mask)) {
366 /* enter umd pstate, save current level, disable gfx cg*/
367 if (*level & profile_mode_mask) {
368 hwmgr->saved_dpm_level = hwmgr->dpm_level;
369 hwmgr->en_umd_pstate = true1;
370 }
371 } else {
372 /* exit umd pstate, restore level, enable gfx cg*/
373 if (!(*level & profile_mode_mask)) {
374 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
375 *level = hwmgr->saved_dpm_level;
376 hwmgr->en_umd_pstate = false0;
377 }
378 }
379}
380
381static int pp_dpm_force_performance_level(void *handle,
382 enum amd_dpm_forced_level level)
383{
384 struct pp_hwmgr *hwmgr = handle;
385
386 if (!hwmgr || !hwmgr->pm_en)
387 return -EINVAL22;
388
389 if (level == hwmgr->dpm_level)
390 return 0;
391
392 pp_dpm_en_umd_pstate(hwmgr, &level);
393 hwmgr->request_dpm_level = level;
394 hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL((void *)0));
395
396 return 0;
397}
398
399static enum amd_dpm_forced_level pp_dpm_get_performance_level(
400 void *handle)
401{
402 struct pp_hwmgr *hwmgr = handle;
403
404 if (!hwmgr || !hwmgr->pm_en)
405 return -EINVAL22;
406
407 return hwmgr->dpm_level;
408}
409
410static uint32_t pp_dpm_get_sclk(void *handle, bool_Bool low)
411{
412 struct pp_hwmgr *hwmgr = handle;
413
414 if (!hwmgr || !hwmgr->pm_en)
415 return 0;
416
417 if (hwmgr->hwmgr_func->get_sclk == NULL((void *)0)) {
418 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
419 return 0;
420 }
421 return hwmgr->hwmgr_func->get_sclk(hwmgr, low);
422}
423
424static uint32_t pp_dpm_get_mclk(void *handle, bool_Bool low)
425{
426 struct pp_hwmgr *hwmgr = handle;
427
428 if (!hwmgr || !hwmgr->pm_en)
429 return 0;
430
431 if (hwmgr->hwmgr_func->get_mclk == NULL((void *)0)) {
432 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
433 return 0;
434 }
435 return hwmgr->hwmgr_func->get_mclk(hwmgr, low);
436}
437
438static void pp_dpm_powergate_vce(void *handle, bool_Bool gate)
439{
440 struct pp_hwmgr *hwmgr = handle;
441
442 if (!hwmgr || !hwmgr->pm_en)
443 return;
444
445 if (hwmgr->hwmgr_func->powergate_vce == NULL((void *)0)) {
446 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
447 return;
448 }
449 hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
450}
451
452static void pp_dpm_powergate_uvd(void *handle, bool_Bool gate)
453{
454 struct pp_hwmgr *hwmgr = handle;
455
456 if (!hwmgr || !hwmgr->pm_en)
457 return;
458
459 if (hwmgr->hwmgr_func->powergate_uvd == NULL((void *)0)) {
460 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
461 return;
462 }
463 hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
464}
465
466static int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_task task_id,
467 enum amd_pm_state_type *user_state)
468{
469 struct pp_hwmgr *hwmgr = handle;
470
471 if (!hwmgr || !hwmgr->pm_en)
472 return -EINVAL22;
473
474 return hwmgr_handle_task(hwmgr, task_id, user_state);
475}
476
477static enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle)
478{
479 struct pp_hwmgr *hwmgr = handle;
480 struct pp_power_state *state;
481 enum amd_pm_state_type pm_type;
482
483 if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
484 return -EINVAL22;
485
486 state = hwmgr->current_ps;
487
488 switch (state->classification.ui_label) {
489 case PP_StateUILabel_Battery:
490 pm_type = POWER_STATE_TYPE_BATTERY;
491 break;
492 case PP_StateUILabel_Balanced:
493 pm_type = POWER_STATE_TYPE_BALANCED;
494 break;
495 case PP_StateUILabel_Performance:
496 pm_type = POWER_STATE_TYPE_PERFORMANCE;
497 break;
498 default:
499 if (state->classification.flags & PP_StateClassificationFlag_Boot)
500 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
501 else
502 pm_type = POWER_STATE_TYPE_DEFAULT;
503 break;
504 }
505
506 return pm_type;
507}
508
509static int pp_dpm_set_fan_control_mode(void *handle, uint32_t mode)
510{
511 struct pp_hwmgr *hwmgr = handle;
512
513 if (!hwmgr || !hwmgr->pm_en)
514 return -EOPNOTSUPP45;
515
516 if (hwmgr->hwmgr_func->set_fan_control_mode == NULL((void *)0))
517 return -EOPNOTSUPP45;
518
519 if (mode == U32_MAX0xffffffffU)
520 return -EINVAL22;
521
522 hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
523
524 return 0;
525}
526
527static int pp_dpm_get_fan_control_mode(void *handle, uint32_t *fan_mode)
528{
529 struct pp_hwmgr *hwmgr = handle;
530
531 if (!hwmgr || !hwmgr->pm_en)
532 return -EOPNOTSUPP45;
533
534 if (hwmgr->hwmgr_func->get_fan_control_mode == NULL((void *)0))
535 return -EOPNOTSUPP45;
536
537 if (!fan_mode)
538 return -EINVAL22;
539
540 *fan_mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
541 return 0;
542}
543
544static int pp_dpm_set_fan_speed_pwm(void *handle, uint32_t speed)
545{
546 struct pp_hwmgr *hwmgr = handle;
547
548 if (!hwmgr || !hwmgr->pm_en)
549 return -EOPNOTSUPP45;
550
551 if (hwmgr->hwmgr_func->set_fan_speed_pwm == NULL((void *)0))
552 return -EOPNOTSUPP45;
553
554 if (speed == U32_MAX0xffffffffU)
555 return -EINVAL22;
556
557 return hwmgr->hwmgr_func->set_fan_speed_pwm(hwmgr, speed);
558}
559
560static int pp_dpm_get_fan_speed_pwm(void *handle, uint32_t *speed)
561{
562 struct pp_hwmgr *hwmgr = handle;
563
564 if (!hwmgr || !hwmgr->pm_en)
565 return -EOPNOTSUPP45;
566
567 if (hwmgr->hwmgr_func->get_fan_speed_pwm == NULL((void *)0))
568 return -EOPNOTSUPP45;
569
570 if (!speed)
571 return -EINVAL22;
572
573 return hwmgr->hwmgr_func->get_fan_speed_pwm(hwmgr, speed);
574}
575
576static int pp_dpm_get_fan_speed_rpm(void *handle, uint32_t *rpm)
577{
578 struct pp_hwmgr *hwmgr = handle;
579
580 if (!hwmgr || !hwmgr->pm_en)
581 return -EOPNOTSUPP45;
582
583 if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL((void *)0))
584 return -EOPNOTSUPP45;
585
586 if (!rpm)
587 return -EINVAL22;
588
589 return hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
590}
591
592static int pp_dpm_set_fan_speed_rpm(void *handle, uint32_t rpm)
593{
594 struct pp_hwmgr *hwmgr = handle;
595
596 if (!hwmgr || !hwmgr->pm_en)
597 return -EOPNOTSUPP45;
598
599 if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL((void *)0))
600 return -EOPNOTSUPP45;
601
602 if (rpm == U32_MAX0xffffffffU)
603 return -EINVAL22;
604
605 return hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
606}
607
608static int pp_dpm_get_pp_num_states(void *handle,
609 struct pp_states_info *data)
610{
611 struct pp_hwmgr *hwmgr = handle;
612 int i;
613
614 memset(data, 0, sizeof(*data))__builtin_memset((data), (0), (sizeof(*data)));
615
616 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
617 return -EINVAL22;
618
619 data->nums = hwmgr->num_ps;
620
621 for (i = 0; i < hwmgr->num_ps; i++) {
622 struct pp_power_state *state = (struct pp_power_state *)
623 ((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
624 switch (state->classification.ui_label) {
625 case PP_StateUILabel_Battery:
626 data->states[i] = POWER_STATE_TYPE_BATTERY;
627 break;
628 case PP_StateUILabel_Balanced:
629 data->states[i] = POWER_STATE_TYPE_BALANCED;
630 break;
631 case PP_StateUILabel_Performance:
632 data->states[i] = POWER_STATE_TYPE_PERFORMANCE;
633 break;
634 default:
635 if (state->classification.flags & PP_StateClassificationFlag_Boot)
636 data->states[i] = POWER_STATE_TYPE_INTERNAL_BOOT;
637 else
638 data->states[i] = POWER_STATE_TYPE_DEFAULT;
639 }
640 }
641 return 0;
642}
643
644static int pp_dpm_get_pp_table(void *handle, char **table)
645{
646 struct pp_hwmgr *hwmgr = handle;
647
648 if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
649 return -EINVAL22;
650
651 *table = (char *)hwmgr->soft_pp_table;
652 return hwmgr->soft_pp_table_size;
653}
654
655static int amd_powerplay_reset(void *handle)
656{
657 struct pp_hwmgr *hwmgr = handle;
658 int ret;
659
660 ret = hwmgr_hw_fini(hwmgr);
661 if (ret)
662 return ret;
663
664 ret = hwmgr_hw_init(hwmgr);
665 if (ret)
666 return ret;
667
668 return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL((void *)0));
669}
670
671static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
672{
673 struct pp_hwmgr *hwmgr = handle;
674 int ret = -ENOMEM12;
675
676 if (!hwmgr || !hwmgr->pm_en)
677 return -EINVAL22;
678
679 if (!hwmgr->hardcode_pp_table) {
680 hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
681 hwmgr->soft_pp_table_size,
682 GFP_KERNEL(0x0001 | 0x0004));
683 if (!hwmgr->hardcode_pp_table)
684 return ret;
685 }
686
687 memcpy(hwmgr->hardcode_pp_table, buf, size)__builtin_memcpy((hwmgr->hardcode_pp_table), (buf), (size)
);
688
689 hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
690
691 ret = amd_powerplay_reset(handle);
692 if (ret)
693 return ret;
694
695 if (hwmgr->hwmgr_func->avfs_control)
696 ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false0);
697
698 return ret;
699}
700
701static int pp_dpm_force_clock_level(void *handle,
702 enum pp_clock_type type, uint32_t mask)
703{
704 struct pp_hwmgr *hwmgr = handle;
705
706 if (!hwmgr || !hwmgr->pm_en)
707 return -EINVAL22;
708
709 if (hwmgr->hwmgr_func->force_clock_level == NULL((void *)0)) {
710 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
711 return 0;
712 }
713
714 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
715 pr_debug("force clock level is for dpm manual mode only.\n")do { } while(0);
716 return -EINVAL22;
717 }
718
719 return hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
720}
721
722static int pp_dpm_emit_clock_levels(void *handle,
723 enum pp_clock_type type,
724 char *buf,
725 int *offset)
726{
727 struct pp_hwmgr *hwmgr = handle;
728
729 if (!hwmgr || !hwmgr->pm_en)
730 return -EOPNOTSUPP45;
731
732 if (!hwmgr->hwmgr_func->emit_clock_levels)
733 return -ENOENT2;
734
735 return hwmgr->hwmgr_func->emit_clock_levels(hwmgr, type, buf, offset);
736}
737
738static int pp_dpm_print_clock_levels(void *handle,
739 enum pp_clock_type type, char *buf)
740{
741 struct pp_hwmgr *hwmgr = handle;
742
743 if (!hwmgr || !hwmgr->pm_en)
744 return -EINVAL22;
745
746 if (hwmgr->hwmgr_func->print_clock_levels == NULL((void *)0)) {
747 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
748 return 0;
749 }
750 return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
751}
752
753static int pp_dpm_get_sclk_od(void *handle)
754{
755 struct pp_hwmgr *hwmgr = handle;
756
757 if (!hwmgr || !hwmgr->pm_en)
758 return -EINVAL22;
759
760 if (hwmgr->hwmgr_func->get_sclk_od == NULL((void *)0)) {
761 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
762 return 0;
763 }
764 return hwmgr->hwmgr_func->get_sclk_od(hwmgr);
765}
766
767static int pp_dpm_set_sclk_od(void *handle, uint32_t value)
768{
769 struct pp_hwmgr *hwmgr = handle;
770
771 if (!hwmgr || !hwmgr->pm_en)
772 return -EINVAL22;
773
774 if (hwmgr->hwmgr_func->set_sclk_od == NULL((void *)0)) {
775 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
776 return 0;
777 }
778
779 return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
780}
781
782static int pp_dpm_get_mclk_od(void *handle)
783{
784 struct pp_hwmgr *hwmgr = handle;
785
786 if (!hwmgr || !hwmgr->pm_en)
787 return -EINVAL22;
788
789 if (hwmgr->hwmgr_func->get_mclk_od == NULL((void *)0)) {
790 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
791 return 0;
792 }
793 return hwmgr->hwmgr_func->get_mclk_od(hwmgr);
794}
795
796static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
797{
798 struct pp_hwmgr *hwmgr = handle;
799
800 if (!hwmgr || !hwmgr->pm_en)
801 return -EINVAL22;
802
803 if (hwmgr->hwmgr_func->set_mclk_od == NULL((void *)0)) {
804 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
805 return 0;
806 }
807 return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
808}
809
810static int pp_dpm_read_sensor(void *handle, int idx,
811 void *value, int *size)
812{
813 struct pp_hwmgr *hwmgr = handle;
814
815 if (!hwmgr || !hwmgr->pm_en || !value)
816 return -EINVAL22;
817
818 switch (idx) {
819 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
820 *((uint32_t *)value) = hwmgr->pstate_sclk * 100;
821 return 0;
822 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
823 *((uint32_t *)value) = hwmgr->pstate_mclk * 100;
824 return 0;
825 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
826 *((uint32_t *)value) = hwmgr->pstate_sclk_peak * 100;
827 return 0;
828 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
829 *((uint32_t *)value) = hwmgr->pstate_mclk_peak * 100;
830 return 0;
831 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
832 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
833 return 0;
834 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
835 *((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
836 return 0;
837 default:
838 return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
839 }
840}
841
842static struct amd_vce_state*
843pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
844{
845 struct pp_hwmgr *hwmgr = handle;
846
847 if (!hwmgr || !hwmgr->pm_en)
848 return NULL((void *)0);
849
850 if (idx < hwmgr->num_vce_state_tables)
851 return &hwmgr->vce_states[idx];
852 return NULL((void *)0);
853}
854
855static int pp_get_power_profile_mode(void *handle, char *buf)
856{
857 struct pp_hwmgr *hwmgr = handle;
858
859 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->get_power_profile_mode)
860 return -EOPNOTSUPP45;
861 if (!buf)
862 return -EINVAL22;
863
864 return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
865}
866
867static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
868{
869 struct pp_hwmgr *hwmgr = handle;
870
871 if (!hwmgr || !hwmgr->pm_en || !hwmgr->hwmgr_func->set_power_profile_mode)
872 return -EOPNOTSUPP45;
873
874 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
875 pr_debug("power profile setting is for manual dpm mode only.\n")do { } while(0);
876 return -EINVAL22;
877 }
878
879 return hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
880}
881
882static int pp_set_fine_grain_clk_vol(void *handle, uint32_t type, long *input, uint32_t size)
883{
884 struct pp_hwmgr *hwmgr = handle;
885
886 if (!hwmgr || !hwmgr->pm_en)
887 return -EINVAL22;
888
889 if (hwmgr->hwmgr_func->set_fine_grain_clk_vol == NULL((void *)0))
890 return 0;
891
892 return hwmgr->hwmgr_func->set_fine_grain_clk_vol(hwmgr, type, input, size);
893}
894
895static int pp_odn_edit_dpm_table(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
896 long *input, uint32_t size)
897{
898 struct pp_hwmgr *hwmgr = handle;
899
900 if (!hwmgr || !hwmgr->pm_en)
901 return -EINVAL22;
902
903 if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL((void *)0)) {
904 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
905 return 0;
906 }
907
908 return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
909}
910
911static int pp_dpm_set_mp1_state(void *handle, enum pp_mp1_state mp1_state)
912{
913 struct pp_hwmgr *hwmgr = handle;
914
915 if (!hwmgr)
916 return -EINVAL22;
917
918 if (!hwmgr->pm_en)
919 return 0;
920
921 if (hwmgr->hwmgr_func->set_mp1_state)
922 return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
923
924 return 0;
925}
926
927static int pp_dpm_switch_power_profile(void *handle,
928 enum PP_SMC_POWER_PROFILE type, bool_Bool en)
929{
930 struct pp_hwmgr *hwmgr = handle;
931 long workload;
932 uint32_t index;
933
934 if (!hwmgr || !hwmgr->pm_en)
935 return -EINVAL22;
936
937 if (hwmgr->hwmgr_func->set_power_profile_mode == NULL((void *)0)) {
938 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
939 return -EINVAL22;
940 }
941
942 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
943 return -EINVAL22;
944
945 if (!en) {
946 hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
947 index = fls(hwmgr->workload_mask);
948 index = index > 0 && index <= Workload_Policy_Max6 ? index - 1 : 0;
949 workload = hwmgr->workload_setting[index];
950 } else {
951 hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
952 index = fls(hwmgr->workload_mask);
953 index = index <= Workload_Policy_Max6 ? index - 1 : 0;
954 workload = hwmgr->workload_setting[index];
955 }
956
957 if (type == PP_SMC_POWER_PROFILE_COMPUTE &&
958 hwmgr->hwmgr_func->disable_power_features_for_compute_performance) {
959 if (hwmgr->hwmgr_func->disable_power_features_for_compute_performance(hwmgr, en))
960 return -EINVAL22;
961 }
962
963 if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
964 hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
965
966 return 0;
967}
968
969static int pp_set_power_limit(void *handle, uint32_t limit)
970{
971 struct pp_hwmgr *hwmgr = handle;
972 uint32_t max_power_limit;
973
974 if (!hwmgr || !hwmgr->pm_en)
975 return -EINVAL22;
976
977 if (hwmgr->hwmgr_func->set_power_limit == NULL((void *)0)) {
978 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
979 return -EINVAL22;
980 }
981
982 if (limit == 0)
983 limit = hwmgr->default_power_limit;
984
985 max_power_limit = hwmgr->default_power_limit;
986 if (hwmgr->od_enabled) {
987 max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
988 max_power_limit /= 100;
989 }
990
991 if (limit > max_power_limit)
992 return -EINVAL22;
993
994 hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
995 hwmgr->power_limit = limit;
996 return 0;
997}
998
999static int pp_get_power_limit(void *handle, uint32_t *limit,
1000 enum pp_power_limit_level pp_limit_level,
1001 enum pp_power_type power_type)
1002{
1003 struct pp_hwmgr *hwmgr = handle;
1004 int ret = 0;
1005
1006 if (!hwmgr || !hwmgr->pm_en ||!limit)
1007 return -EINVAL22;
1008
1009 if (power_type != PP_PWR_TYPE_SUSTAINED)
1010 return -EOPNOTSUPP45;
1011
1012 switch (pp_limit_level) {
1013 case PP_PWR_LIMIT_CURRENT:
1014 *limit = hwmgr->power_limit;
1015 break;
1016 case PP_PWR_LIMIT_DEFAULT:
1017 *limit = hwmgr->default_power_limit;
1018 break;
1019 case PP_PWR_LIMIT_MAX:
1020 *limit = hwmgr->default_power_limit;
1021 if (hwmgr->od_enabled) {
1022 *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
1023 *limit /= 100;
1024 }
1025 break;
1026 default:
1027 ret = -EOPNOTSUPP45;
1028 break;
1029 }
1030
1031 return ret;
1032}
1033
1034static int pp_display_configuration_change(void *handle,
1035 const struct amd_pp_display_configuration *display_config)
1036{
1037 struct pp_hwmgr *hwmgr = handle;
1038
1039 if (!hwmgr || !hwmgr->pm_en)
1040 return -EINVAL22;
1041
1042 phm_store_dal_configuration_data(hwmgr, display_config);
1043 return 0;
1044}
1045
1046static int pp_get_display_power_level(void *handle,
1047 struct amd_pp_simple_clock_info *output)
1048{
1049 struct pp_hwmgr *hwmgr = handle;
1050
1051 if (!hwmgr || !hwmgr->pm_en ||!output)
1052 return -EINVAL22;
1053
1054 return phm_get_dal_power_level(hwmgr, output);
1055}
1056
1057static int pp_get_current_clocks(void *handle,
1058 struct amd_pp_clock_info *clocks)
1059{
1060 struct amd_pp_simple_clock_info simple_clocks = { 0 };
1061 struct pp_clock_info hw_clocks;
1062 struct pp_hwmgr *hwmgr = handle;
1063 int ret = 0;
1064
1065 if (!hwmgr || !hwmgr->pm_en)
1066 return -EINVAL22;
1067
1068 phm_get_dal_power_level(hwmgr, &simple_clocks);
1069
1070 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1071 PHM_PlatformCaps_PowerContainment))
1072 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1073 &hw_clocks, PHM_PerformanceLevelDesignation_PowerContainment);
1074 else
1075 ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
1076 &hw_clocks, PHM_PerformanceLevelDesignation_Activity);
1077
1078 if (ret) {
1079 pr_debug("Error in phm_get_clock_info \n")do { } while(0);
1080 return -EINVAL22;
1081 }
1082
1083 clocks->min_engine_clock = hw_clocks.min_eng_clk;
1084 clocks->max_engine_clock = hw_clocks.max_eng_clk;
1085 clocks->min_memory_clock = hw_clocks.min_mem_clk;
1086 clocks->max_memory_clock = hw_clocks.max_mem_clk;
1087 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1088 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1089
1090 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1091 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1092
1093 if (simple_clocks.level == 0)
1094 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1095 else
1096 clocks->max_clocks_state = simple_clocks.level;
1097
1098 if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
1099 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1100 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1101 }
1102 return 0;
1103}
1104
1105static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
1106{
1107 struct pp_hwmgr *hwmgr = handle;
1108
1109 if (!hwmgr || !hwmgr->pm_en)
1110 return -EINVAL22;
1111
1112 if (clocks == NULL((void *)0))
1113 return -EINVAL22;
1114
1115 return phm_get_clock_by_type(hwmgr, type, clocks);
1116}
1117
1118static int pp_get_clock_by_type_with_latency(void *handle,
1119 enum amd_pp_clock_type type,
1120 struct pp_clock_levels_with_latency *clocks)
1121{
1122 struct pp_hwmgr *hwmgr = handle;
1123
1124 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1125 return -EINVAL22;
1126
1127 return phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
1128}
1129
1130static int pp_get_clock_by_type_with_voltage(void *handle,
1131 enum amd_pp_clock_type type,
1132 struct pp_clock_levels_with_voltage *clocks)
1133{
1134 struct pp_hwmgr *hwmgr = handle;
1135
1136 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1137 return -EINVAL22;
1138
1139 return phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
1140}
1141
1142static int pp_set_watermarks_for_clocks_ranges(void *handle,
1143 void *clock_ranges)
1144{
1145 struct pp_hwmgr *hwmgr = handle;
1146
1147 if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
1148 return -EINVAL22;
1149
1150 return phm_set_watermarks_for_clocks_ranges(hwmgr,
1151 clock_ranges);
1152}
1153
1154static int pp_display_clock_voltage_request(void *handle,
1155 struct pp_display_clock_request *clock)
1156{
1157 struct pp_hwmgr *hwmgr = handle;
1158
1159 if (!hwmgr || !hwmgr->pm_en ||!clock)
1160 return -EINVAL22;
1161
1162 return phm_display_clock_voltage_request(hwmgr, clock);
1163}
1164
1165static int pp_get_display_mode_validation_clocks(void *handle,
1166 struct amd_pp_simple_clock_info *clocks)
1167{
1168 struct pp_hwmgr *hwmgr = handle;
1169 int ret = 0;
1170
1171 if (!hwmgr || !hwmgr->pm_en ||!clocks)
1172 return -EINVAL22;
1173
1174 clocks->level = PP_DAL_POWERLEVEL_7;
1175
1176 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
1177 ret = phm_get_max_high_clocks(hwmgr, clocks);
1178
1179 return ret;
1180}
1181
1182static int pp_dpm_powergate_mmhub(void *handle)
1183{
1184 struct pp_hwmgr *hwmgr = handle;
1185
1186 if (!hwmgr || !hwmgr->pm_en)
1187 return -EINVAL22;
1188
1189 if (hwmgr->hwmgr_func->powergate_mmhub == NULL((void *)0)) {
1190 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1191 return 0;
1192 }
1193
1194 return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
1195}
1196
1197static int pp_dpm_powergate_gfx(void *handle, bool_Bool gate)
1198{
1199 struct pp_hwmgr *hwmgr = handle;
1200
1201 if (!hwmgr || !hwmgr->pm_en)
1202 return 0;
1203
1204 if (hwmgr->hwmgr_func->powergate_gfx == NULL((void *)0)) {
1205 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1206 return 0;
1207 }
1208
1209 return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
1210}
1211
1212static void pp_dpm_powergate_acp(void *handle, bool_Bool gate)
1213{
1214 struct pp_hwmgr *hwmgr = handle;
1215
1216 if (!hwmgr || !hwmgr->pm_en)
1217 return;
1218
1219 if (hwmgr->hwmgr_func->powergate_acp == NULL((void *)0)) {
1220 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1221 return;
1222 }
1223
1224 hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
1225}
1226
1227static void pp_dpm_powergate_sdma(void *handle, bool_Bool gate)
1228{
1229 struct pp_hwmgr *hwmgr = handle;
1230
1231 if (!hwmgr)
1232 return;
1233
1234 if (hwmgr->hwmgr_func->powergate_sdma == NULL((void *)0)) {
1235 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1236 return;
1237 }
1238
1239 hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
1240}
1241
1242static int pp_set_powergating_by_smu(void *handle,
1243 uint32_t block_type, bool_Bool gate)
1244{
1245 int ret = 0;
1246
1247 switch (block_type) {
1248 case AMD_IP_BLOCK_TYPE_UVD:
1249 case AMD_IP_BLOCK_TYPE_VCN:
1250 pp_dpm_powergate_uvd(handle, gate);
1251 break;
1252 case AMD_IP_BLOCK_TYPE_VCE:
1253 pp_dpm_powergate_vce(handle, gate);
1254 break;
1255 case AMD_IP_BLOCK_TYPE_GMC:
1256 /*
1257 * For now, this is only used on PICASSO.
1258 * And only "gate" operation is supported.
1259 */
1260 if (gate)
1261 pp_dpm_powergate_mmhub(handle);
1262 break;
1263 case AMD_IP_BLOCK_TYPE_GFX:
1264 ret = pp_dpm_powergate_gfx(handle, gate);
1265 break;
1266 case AMD_IP_BLOCK_TYPE_ACP:
1267 pp_dpm_powergate_acp(handle, gate);
1268 break;
1269 case AMD_IP_BLOCK_TYPE_SDMA:
1270 pp_dpm_powergate_sdma(handle, gate);
1271 break;
1272 default:
1273 break;
1274 }
1275 return ret;
1276}
1277
1278static int pp_notify_smu_enable_pwe(void *handle)
1279{
1280 struct pp_hwmgr *hwmgr = handle;
1281
1282 if (!hwmgr || !hwmgr->pm_en)
1283 return -EINVAL22;
1284
1285 if (hwmgr->hwmgr_func->smus_notify_pwe == NULL((void *)0)) {
1286 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1287 return -EINVAL22;
1288 }
1289
1290 hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
1291
1292 return 0;
1293}
1294
1295static int pp_enable_mgpu_fan_boost(void *handle)
1296{
1297 struct pp_hwmgr *hwmgr = handle;
1298
1299 if (!hwmgr)
1300 return -EINVAL22;
1301
1302 if (!hwmgr->pm_en ||
1303 hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL((void *)0))
1304 return 0;
1305
1306 hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
1307
1308 return 0;
1309}
1310
1311static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
1312{
1313 struct pp_hwmgr *hwmgr = handle;
1314
1315 if (!hwmgr || !hwmgr->pm_en)
1316 return -EINVAL22;
1317
1318 if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL((void *)0)) {
1319 pr_debug("%s was not implemented.\n", __func__)do { } while(0);
1320 return -EINVAL22;
1321 }
1322
1323 hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
1324
1325 return 0;
1326}
1327
1328static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)
1329{
1330 struct pp_hwmgr *hwmgr = handle;
1331
1332 if (!hwmgr || !hwmgr->pm_en)
1333 return -EINVAL22;
1334
1335 if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL((void *)0)) {
1336 pr_debug("%s was not implemented.\n", __func__)do { } while(0);
1337 return -EINVAL22;
1338 }
1339
1340 hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
1341
1342 return 0;
1343}
1344
1345static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)
1346{
1347 struct pp_hwmgr *hwmgr = handle;
1348
1349 if (!hwmgr || !hwmgr->pm_en)
1350 return -EINVAL22;
1351
1352 if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL((void *)0)) {
1353 pr_debug("%s was not implemented.\n", __func__)do { } while(0);
1354 return -EINVAL22;
1355 }
1356
1357 hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
1358
1359 return 0;
1360}
1361
1362static int pp_set_active_display_count(void *handle, uint32_t count)
1363{
1364 struct pp_hwmgr *hwmgr = handle;
1365
1366 if (!hwmgr || !hwmgr->pm_en)
1367 return -EINVAL22;
1368
1369 return phm_set_active_display_count(hwmgr, count);
1370}
1371
1372static int pp_get_asic_baco_capability(void *handle, bool_Bool *cap)
1373{
1374 struct pp_hwmgr *hwmgr = handle;
1375
1376 *cap = false0;
1377 if (!hwmgr)
1378 return -EINVAL22;
1379
1380 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1381 !hwmgr->hwmgr_func->get_asic_baco_capability)
1382 return 0;
1383
1384 hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
1385
1386 return 0;
1387}
1388
1389static int pp_get_asic_baco_state(void *handle, int *state)
1390{
1391 struct pp_hwmgr *hwmgr = handle;
1392
1393 if (!hwmgr)
1394 return -EINVAL22;
1395
1396 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
1397 return 0;
1398
1399 hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
1400
1401 return 0;
1402}
1403
1404static int pp_set_asic_baco_state(void *handle, int state)
1405{
1406 struct pp_hwmgr *hwmgr = handle;
1407
1408 if (!hwmgr)
1409 return -EINVAL22;
1410
1411 if (!(hwmgr->not_vf && amdgpu_dpm) ||
1412 !hwmgr->hwmgr_func->set_asic_baco_state)
1413 return 0;
1414
1415 hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
1416
1417 return 0;
1418}
1419
1420static int pp_get_ppfeature_status(void *handle, char *buf)
1421{
1422 struct pp_hwmgr *hwmgr = handle;
1423
1424 if (!hwmgr || !hwmgr->pm_en || !buf)
1425 return -EINVAL22;
1426
1427 if (hwmgr->hwmgr_func->get_ppfeature_status == NULL((void *)0)) {
1428 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1429 return -EINVAL22;
1430 }
1431
1432 return hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
1433}
1434
1435static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
1436{
1437 struct pp_hwmgr *hwmgr = handle;
1438
1439 if (!hwmgr || !hwmgr->pm_en)
1440 return -EINVAL22;
1441
1442 if (hwmgr->hwmgr_func->set_ppfeature_status == NULL((void *)0)) {
1443 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1444 return -EINVAL22;
1445 }
1446
1447 return hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
1448}
1449
1450static int pp_asic_reset_mode_2(void *handle)
1451{
1452 struct pp_hwmgr *hwmgr = handle;
1453
1454 if (!hwmgr || !hwmgr->pm_en)
1455 return -EINVAL22;
1456
1457 if (hwmgr->hwmgr_func->asic_reset == NULL((void *)0)) {
1458 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1459 return -EINVAL22;
1460 }
1461
1462 return hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
1463}
1464
1465static int pp_smu_i2c_bus_access(void *handle, bool_Bool acquire)
1466{
1467 struct pp_hwmgr *hwmgr = handle;
1468
1469 if (!hwmgr || !hwmgr->pm_en)
1470 return -EINVAL22;
1471
1472 if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL((void *)0)) {
1473 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1474 return -EINVAL22;
1475 }
1476
1477 return hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
1478}
1479
1480static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
1481{
1482 struct pp_hwmgr *hwmgr = handle;
1483
1484 if (!hwmgr)
1485 return -EINVAL22;
1486
1487 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_df_cstate)
1488 return 0;
1489
1490 hwmgr->hwmgr_func->set_df_cstate(hwmgr, state);
1491
1492 return 0;
1493}
1494
1495static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
1496{
1497 struct pp_hwmgr *hwmgr = handle;
1498
1499 if (!hwmgr)
1500 return -EINVAL22;
1501
1502 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
1503 return 0;
1504
1505 hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
1506
1507 return 0;
1508}
1509
1510static ssize_t pp_get_gpu_metrics(void *handle, void **table)
1511{
1512 struct pp_hwmgr *hwmgr = handle;
1513
1514 if (!hwmgr)
1515 return -EINVAL22;
1516
1517 if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_gpu_metrics)
1518 return -EOPNOTSUPP45;
1519
1520 return hwmgr->hwmgr_func->get_gpu_metrics(hwmgr, table);
1521}
1522
1523static int pp_gfx_state_change_set(void *handle, uint32_t state)
1524{
1525 struct pp_hwmgr *hwmgr = handle;
1526
1527 if (!hwmgr || !hwmgr->pm_en)
1528 return -EINVAL22;
1529
1530 if (hwmgr->hwmgr_func->gfx_state_change == NULL((void *)0)) {
1531 pr_info_ratelimited("%s was not implemented.\n", __func__)do { } while(0);
1532 return -EINVAL22;
1533 }
1534
1535 hwmgr->hwmgr_func->gfx_state_change(hwmgr, state);
1536 return 0;
1537}
1538
1539static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size)
1540{
1541 struct pp_hwmgr *hwmgr = handle;
1542 struct amdgpu_device *adev = hwmgr->adev;
1543 int err;
1544
1545 if (!addr || !size)
1546 return -EINVAL22;
1547
1548 *addr = NULL((void *)0);
1549 *size = 0;
1550 if (adev->pm.smu_prv_buffer) {
1551 err = amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
1552 if (err)
1553 return err;
1554 *size = adev->pm.smu_prv_buffer_size;
1555 }
1556
1557 return 0;
1558}
1559
1560static void pp_pm_compute_clocks(void *handle)
1561{
1562 struct pp_hwmgr *hwmgr = handle;
1563 struct amdgpu_device *adev = hwmgr->adev;
1564
1565 if (!amdgpu_device_has_dc_support(adev)) {
1566 amdgpu_dpm_get_active_displays(adev);
1567 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count;
1568 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev);
1569 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev);
1570 /* we have issues with mclk switching with
1571 * refresh rates over 120 hz on the non-DC code.
1572 */
1573 if (adev->pm.pm_display_cfg.vrefresh > 120)
1574 adev->pm.pm_display_cfg.min_vblank_time = 0;
1575
1576 pp_display_configuration_change(handle,
1577 &adev->pm.pm_display_cfg);
1578 }
1579
1580 pp_dpm_dispatch_tasks(handle,
1581 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
1582 NULL((void *)0));
1583}
1584
1585static const struct amd_pm_funcs pp_dpm_funcs = {
1586 .load_firmware = pp_dpm_load_fw,
1587 .wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
1588 .force_performance_level = pp_dpm_force_performance_level,
1589 .get_performance_level = pp_dpm_get_performance_level,
1590 .get_current_power_state = pp_dpm_get_current_power_state,
1591 .dispatch_tasks = pp_dpm_dispatch_tasks,
1592 .set_fan_control_mode = pp_dpm_set_fan_control_mode,
1593 .get_fan_control_mode = pp_dpm_get_fan_control_mode,
1594 .set_fan_speed_pwm = pp_dpm_set_fan_speed_pwm,
1595 .get_fan_speed_pwm = pp_dpm_get_fan_speed_pwm,
1596 .get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
1597 .set_fan_speed_rpm = pp_dpm_set_fan_speed_rpm,
1598 .get_pp_num_states = pp_dpm_get_pp_num_states,
1599 .get_pp_table = pp_dpm_get_pp_table,
1600 .set_pp_table = pp_dpm_set_pp_table,
1601 .force_clock_level = pp_dpm_force_clock_level,
1602 .emit_clock_levels = pp_dpm_emit_clock_levels,
1603 .print_clock_levels = pp_dpm_print_clock_levels,
1604 .get_sclk_od = pp_dpm_get_sclk_od,
1605 .set_sclk_od = pp_dpm_set_sclk_od,
1606 .get_mclk_od = pp_dpm_get_mclk_od,
1607 .set_mclk_od = pp_dpm_set_mclk_od,
1608 .read_sensor = pp_dpm_read_sensor,
1609 .get_vce_clock_state = pp_dpm_get_vce_clock_state,
1610 .switch_power_profile = pp_dpm_switch_power_profile,
1611 .set_clockgating_by_smu = pp_set_clockgating_by_smu,
1612 .set_powergating_by_smu = pp_set_powergating_by_smu,
1613 .get_power_profile_mode = pp_get_power_profile_mode,
1614 .set_power_profile_mode = pp_set_power_profile_mode,
1615 .set_fine_grain_clk_vol = pp_set_fine_grain_clk_vol,
1616 .odn_edit_dpm_table = pp_odn_edit_dpm_table,
1617 .set_mp1_state = pp_dpm_set_mp1_state,
1618 .set_power_limit = pp_set_power_limit,
1619 .get_power_limit = pp_get_power_limit,
1620/* export to DC */
1621 .get_sclk = pp_dpm_get_sclk,
1622 .get_mclk = pp_dpm_get_mclk,
1623 .display_configuration_change = pp_display_configuration_change,
1624 .get_display_power_level = pp_get_display_power_level,
1625 .get_current_clocks = pp_get_current_clocks,
1626 .get_clock_by_type = pp_get_clock_by_type,
1627 .get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
1628 .get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
1629 .set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
1630 .display_clock_voltage_request = pp_display_clock_voltage_request,
1631 .get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
1632 .notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
1633 .enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
1634 .set_active_display_count = pp_set_active_display_count,
1635 .set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
1636 .set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
1637 .set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
1638 .get_asic_baco_capability = pp_get_asic_baco_capability,
1639 .get_asic_baco_state = pp_get_asic_baco_state,
1640 .set_asic_baco_state = pp_set_asic_baco_state,
1641 .get_ppfeature_status = pp_get_ppfeature_status,
1642 .set_ppfeature_status = pp_set_ppfeature_status,
1643 .asic_reset_mode_2 = pp_asic_reset_mode_2,
1644 .smu_i2c_bus_access = pp_smu_i2c_bus_access,
1645 .set_df_cstate = pp_set_df_cstate,
1646 .set_xgmi_pstate = pp_set_xgmi_pstate,
1647 .get_gpu_metrics = pp_get_gpu_metrics,
1648 .gfx_state_change_set = pp_gfx_state_change_set,
1649 .get_smu_prv_buf_details = pp_get_prv_buffer_details,
1650 .pm_compute_clocks = pp_pm_compute_clocks,
1651};