File: | dev/pci/drm/i915/display/intel_pps.c |
Warning: | line 1155, column 27 Value stored to 'i915' during its initialization is never read |
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1 | // SPDX-License-Identifier: MIT |
2 | /* |
3 | * Copyright © 2020 Intel Corporation |
4 | */ |
5 | |
6 | #include "g4x_dp.h" |
7 | #include "i915_drv.h" |
8 | #include "intel_de.h" |
9 | #include "intel_display_power_well.h" |
10 | #include "intel_display_types.h" |
11 | #include "intel_dp.h" |
12 | #include "intel_dpll.h" |
13 | #include "intel_lvds.h" |
14 | #include "intel_pps.h" |
15 | #include "intel_quirks.h" |
16 | |
17 | static void vlv_steal_power_sequencer(struct drm_i915_privateinteldrm_softc *dev_priv, |
18 | enum pipe pipe); |
19 | |
20 | static void pps_init_delays(struct intel_dp *intel_dp); |
21 | static void pps_init_registers(struct intel_dp *intel_dp, bool_Bool force_disable_vdd); |
22 | |
23 | intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp) |
24 | { |
25 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
26 | intel_wakeref_t wakeref; |
27 | |
28 | /* |
29 | * See intel_pps_reset_all() why we need a power domain reference here. |
30 | */ |
31 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); |
32 | mutex_lock(&dev_priv->display.pps.mutex)rw_enter_write(&dev_priv->display.pps.mutex); |
33 | |
34 | return wakeref; |
35 | } |
36 | |
37 | intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp, |
38 | intel_wakeref_t wakeref) |
39 | { |
40 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
41 | |
42 | mutex_unlock(&dev_priv->display.pps.mutex)rw_exit_write(&dev_priv->display.pps.mutex); |
43 | intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); |
44 | |
45 | return 0; |
46 | } |
47 | |
48 | static void |
49 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) |
50 | { |
51 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
52 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
53 | enum pipe pipe = intel_dp->pps.pps_pipe; |
54 | bool_Bool pll_enabled, release_cl_override = false0; |
55 | enum dpio_phy phy = DPIO_PHY(pipe)((pipe) >> 1); |
56 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); |
57 | u32 DP; |
58 | |
59 | if (drm_WARN(&dev_priv->drm,({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
60 | intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
61 | "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
62 | pipe_name(pipe), dig_port->base.base.base.id,({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); }) |
63 | dig_port->base.base.name)({ int __ret = !!(intel_de_read(dev_priv, intel_dp->output_reg ) & (1 << 31)); if (__ret) printf("%s %s: " "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), dig_port->base.base.base.id, dig_port->base.base .name); __builtin_expect(!!(__ret), 0); })) |
64 | return; |
65 | |
66 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
67 | "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
68 | pipe_name(pipe), dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
69 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name); |
70 | |
71 | /* Preserve the BIOS-computed detected bit. This is |
72 | * supposed to be read-only. |
73 | */ |
74 | DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED(1 << 2); |
75 | DP |= DP_VOLTAGE_0_4(0 << 25) | DP_PRE_EMPHASIS_0(0 << 22); |
76 | DP |= DP_PORT_WIDTH(1)(((1) - 1) << 19); |
77 | DP |= DP_LINK_TRAIN_PAT_1(0 << 28); |
78 | |
79 | if (IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
80 | DP |= DP_PIPE_SEL_CHV(pipe)((pipe) << 16); |
81 | else |
82 | DP |= DP_PIPE_SEL(pipe)((pipe) << 30); |
83 | |
84 | pll_enabled = intel_de_read(dev_priv, DPLL(pipe)((const i915_reg_t){ .reg = ((((const u32 []){ (((&(dev_priv )->__info)->display.mmio_offset) + 0x6014), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6018), (((&(dev_priv )->__info)->display.mmio_offset) + 0x6030) })[(pipe)])) })) & DPLL_VCO_ENABLE(1 << 31); |
85 | |
86 | /* |
87 | * The DPLL for the pipe must be enabled for this to work. |
88 | * So enable temporarily it if it's not already enabled. |
89 | */ |
90 | if (!pll_enabled) { |
91 | release_cl_override = IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) && |
92 | !chv_phy_powergate_ch(dev_priv, phy, ch, true1); |
93 | |
94 | if (vlv_force_pll_on(dev_priv, pipe, vlv_get_dpll(dev_priv))) { |
95 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to force on pll for pipe %c!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
96 | "Failed to force on pll for pipe %c!\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to force on pll for pipe %c!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')) |
97 | pipe_name(pipe))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to force on pll for pipe %c!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((pipe ) + 'A')); |
98 | return; |
99 | } |
100 | } |
101 | |
102 | /* |
103 | * Similar magic as in intel_dp_enable_port(). |
104 | * We _must_ do this port enable + disable trick |
105 | * to make this power sequencer lock onto the port. |
106 | * Otherwise even VDD force bit won't work. |
107 | */ |
108 | intel_de_write(dev_priv, intel_dp->output_reg, DP); |
109 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
110 | |
111 | intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN(1 << 31)); |
112 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
113 | |
114 | intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN(1 << 31)); |
115 | intel_de_posting_read(dev_priv, intel_dp->output_reg); |
116 | |
117 | if (!pll_enabled) { |
118 | vlv_force_pll_off(dev_priv, pipe); |
119 | |
120 | if (release_cl_override) |
121 | chv_phy_powergate_ch(dev_priv, phy, ch, false0); |
122 | } |
123 | } |
124 | |
125 | static enum pipe vlv_find_free_pps(struct drm_i915_privateinteldrm_softc *dev_priv) |
126 | { |
127 | struct intel_encoder *encoder; |
128 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); |
129 | |
130 | /* |
131 | * We don't have power sequencer currently. |
132 | * Pick one that's not used by other ports. |
133 | */ |
134 | for_each_intel_dp(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) if (!(intel_encoder_is_dp (encoder))) {} else { |
135 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
136 | |
137 | if (encoder->type == INTEL_OUTPUT_EDP) { |
138 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps. pps_pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
139 | intel_dp->pps.active_pipe != INVALID_PIPE &&({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps. pps_pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
140 | intel_dp->pps.active_pipe !=({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps. pps_pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
141 | intel_dp->pps.pps_pipe)({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps. pps_pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }); |
142 | |
143 | if (intel_dp->pps.pps_pipe != INVALID_PIPE) |
144 | pipes &= ~(1 << intel_dp->pps.pps_pipe); |
145 | } else { |
146 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->pps.pps_pipe != INVALID_PIPE) ); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.pps_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }) |
147 | intel_dp->pps.pps_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->pps.pps_pipe != INVALID_PIPE) ); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.pps_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
148 | |
149 | if (intel_dp->pps.active_pipe != INVALID_PIPE) |
150 | pipes &= ~(1 << intel_dp->pps.active_pipe); |
151 | } |
152 | } |
153 | |
154 | if (pipes == 0) |
155 | return INVALID_PIPE; |
156 | |
157 | return ffs(pipes) - 1; |
158 | } |
159 | |
160 | static enum pipe |
161 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
162 | { |
163 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
164 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
165 | enum pipe pipe; |
166 | |
167 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
168 | |
169 | /* We should never land here with regular DP ports */ |
170 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp))({ int __ret = !!((!intel_dp_is_edp(intel_dp))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!intel_dp_is_edp(intel_dp)" ")"); __builtin_expect (!!(__ret), 0); }); |
171 | |
172 | drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE &&({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps. pps_pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }) |
173 | intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe)({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps. pps_pipe)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE && intel_dp->pps.active_pipe != intel_dp->pps.pps_pipe" ")"); __builtin_expect(!!(__ret), 0); }); |
174 | |
175 | if (intel_dp->pps.pps_pipe != INVALID_PIPE) |
176 | return intel_dp->pps.pps_pipe; |
177 | |
178 | pipe = vlv_find_free_pps(dev_priv); |
179 | |
180 | /* |
181 | * Didn't find one. This should not happen since there |
182 | * are two power sequencers and up to two eDP ports. |
183 | */ |
184 | if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE)({ int __ret = !!((pipe == INVALID_PIPE)); if (__ret) printf( "%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "pipe == INVALID_PIPE" ")"); __builtin_expect (!!(__ret), 0); })) |
185 | pipe = PIPE_A; |
186 | |
187 | vlv_steal_power_sequencer(dev_priv, pipe); |
188 | intel_dp->pps.pps_pipe = pipe; |
189 | |
190 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), dig_port->base.base .base.id, dig_port->base.base.name) |
191 | "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), dig_port->base.base .base.id, dig_port->base.base.name) |
192 | pipe_name(intel_dp->pps.pps_pipe),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), dig_port->base.base .base.id, dig_port->base.base.name) |
193 | dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), dig_port->base.base .base.id, dig_port->base.base.name) |
194 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "picked pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), dig_port->base.base .base.id, dig_port->base.base.name); |
195 | |
196 | /* init power sequencer on this pipe and port */ |
197 | pps_init_delays(intel_dp); |
198 | pps_init_registers(intel_dp, true1); |
199 | |
200 | /* |
201 | * Even vdd force doesn't work until we've made |
202 | * the power sequencer lock in on the port. |
203 | */ |
204 | vlv_power_sequencer_kick(intel_dp); |
205 | |
206 | return intel_dp->pps.pps_pipe; |
207 | } |
208 | |
209 | static int |
210 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) |
211 | { |
212 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
213 | struct intel_connector *connector = intel_dp->attached_connector; |
214 | int backlight_controller = connector->panel.vbt.backlight.controller; |
215 | |
216 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
217 | |
218 | /* We should never land here with regular DP ports */ |
219 | drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp))({ int __ret = !!((!intel_dp_is_edp(intel_dp))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "!intel_dp_is_edp(intel_dp)" ")"); __builtin_expect (!!(__ret), 0); }); |
220 | |
221 | if (!intel_dp->pps.pps_reset) |
222 | return backlight_controller; |
223 | |
224 | intel_dp->pps.pps_reset = false0; |
225 | |
226 | /* |
227 | * Only the HW needs to be reprogrammed, the SW state is fixed and |
228 | * has been setup during connector init. |
229 | */ |
230 | pps_init_registers(intel_dp, false0); |
231 | |
232 | return backlight_controller; |
233 | } |
234 | |
235 | typedef bool_Bool (*vlv_pipe_check)(struct drm_i915_privateinteldrm_softc *dev_priv, |
236 | enum pipe pipe); |
237 | |
238 | static bool_Bool vlv_pipe_has_pp_on(struct drm_i915_privateinteldrm_softc *dev_priv, |
239 | enum pipe pipe) |
240 | { |
241 | return intel_de_read(dev_priv, PP_STATUS(pipe)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61200) + (pipe) * 0x100) })) & PP_ON((u32)((1UL << (31)) + 0)); |
242 | } |
243 | |
244 | static bool_Bool vlv_pipe_has_vdd_on(struct drm_i915_privateinteldrm_softc *dev_priv, |
245 | enum pipe pipe) |
246 | { |
247 | return intel_de_read(dev_priv, PP_CONTROL(pipe)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (pipe) * 0x100) })) & EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
248 | } |
249 | |
250 | static bool_Bool vlv_pipe_any(struct drm_i915_privateinteldrm_softc *dev_priv, |
251 | enum pipe pipe) |
252 | { |
253 | return true1; |
254 | } |
255 | |
256 | static enum pipe |
257 | vlv_initial_pps_pipe(struct drm_i915_privateinteldrm_softc *dev_priv, |
258 | enum port port, |
259 | vlv_pipe_check pipe_check) |
260 | { |
261 | enum pipe pipe; |
262 | |
263 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
264 | u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61208) + (pipe) * 0x100) })) & |
265 | PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)); |
266 | |
267 | if (port_sel != PANEL_PORT_SELECT_VLV(port)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(port) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 ))) |
268 | continue; |
269 | |
270 | if (!pipe_check(dev_priv, pipe)) |
271 | continue; |
272 | |
273 | return pipe; |
274 | } |
275 | |
276 | return INVALID_PIPE; |
277 | } |
278 | |
279 | static void |
280 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) |
281 | { |
282 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
283 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
284 | enum port port = dig_port->base.port; |
285 | |
286 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
287 | |
288 | /* try to find a pipe with this port selected */ |
289 | /* first pick one where the panel is on */ |
290 | intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
291 | vlv_pipe_has_pp_on); |
292 | /* didn't find one? pick one where vdd is on */ |
293 | if (intel_dp->pps.pps_pipe == INVALID_PIPE) |
294 | intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
295 | vlv_pipe_has_vdd_on); |
296 | /* didn't find one? pick one with just the correct port */ |
297 | if (intel_dp->pps.pps_pipe == INVALID_PIPE) |
298 | intel_dp->pps.pps_pipe = vlv_initial_pps_pipe(dev_priv, port, |
299 | vlv_pipe_any); |
300 | |
301 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ |
302 | if (intel_dp->pps.pps_pipe == INVALID_PIPE) { |
303 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
304 | "no initial power sequencer for [ENCODER:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
305 | dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
306 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "no initial power sequencer for [ENCODER:%d:%s]\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
307 | return; |
308 | } |
309 | |
310 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps.pps_pipe) + 'A')) |
311 | "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps.pps_pipe) + 'A')) |
312 | dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps.pps_pipe) + 'A')) |
313 | dig_port->base.base.name,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps.pps_pipe) + 'A')) |
314 | pipe_name(intel_dp->pps.pps_pipe))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n" , dig_port->base.base.base.id, dig_port->base.base.name , ((intel_dp->pps.pps_pipe) + 'A')); |
315 | } |
316 | |
317 | void intel_pps_reset_all(struct drm_i915_privateinteldrm_softc *dev_priv) |
318 | { |
319 | struct intel_encoder *encoder; |
320 | |
321 | if (drm_WARN_ON(&dev_priv->drm, !IS_LP(dev_priv))({ int __ret = !!((!((&(dev_priv)->__info)->is_lp)) ); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__info)->is_lp)" ")"); __builtin_expect(!!(__ret), 0); })) |
322 | return; |
323 | |
324 | if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0)) |
325 | return; |
326 | |
327 | /* |
328 | * We can't grab pps_mutex here due to deadlock with power_domain |
329 | * mutex when power_domain functions are called while holding pps_mutex. |
330 | * That also means that in order to use pps_pipe the code needs to |
331 | * hold both a power domain reference and pps_mutex, and the power domain |
332 | * reference get/put must be done while _not_ holding pps_mutex. |
333 | * pps_{lock,unlock}() do these steps in the correct order, so one |
334 | * should use them always. |
335 | */ |
336 | |
337 | for_each_intel_dp(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) if (!(intel_encoder_is_dp (encoder))) {} else { |
338 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
339 | |
340 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }) |
341 | intel_dp->pps.active_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
342 | |
343 | if (encoder->type != INTEL_OUTPUT_EDP) |
344 | continue; |
345 | |
346 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 9) |
347 | intel_dp->pps.pps_reset = true1; |
348 | else |
349 | intel_dp->pps.pps_pipe = INVALID_PIPE; |
350 | } |
351 | } |
352 | |
353 | struct pps_registers { |
354 | i915_reg_t pp_ctrl; |
355 | i915_reg_t pp_stat; |
356 | i915_reg_t pp_on; |
357 | i915_reg_t pp_off; |
358 | i915_reg_t pp_div; |
359 | }; |
360 | |
361 | static void intel_pps_get_registers(struct intel_dp *intel_dp, |
362 | struct pps_registers *regs) |
363 | { |
364 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
365 | int pps_idx = 0; |
366 | |
367 | memset(regs, 0, sizeof(*regs))__builtin_memset((regs), (0), (sizeof(*regs))); |
368 | |
369 | if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
370 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
371 | else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
372 | pps_idx = vlv_power_sequencer_pipe(intel_dp); |
373 | |
374 | regs->pp_ctrl = PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (pps_idx) * 0x100) }); |
375 | regs->pp_stat = PP_STATUS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61200) + (pps_idx) * 0x100) }); |
376 | regs->pp_on = PP_ON_DELAYS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61208) + (pps_idx) * 0x100) }); |
377 | regs->pp_off = PP_OFF_DELAYS(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x6120C) + (pps_idx) * 0x100) }); |
378 | |
379 | /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ |
380 | if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) || |
381 | INTEL_PCH_TYPE(dev_priv)((dev_priv)->pch_type) >= PCH_CNP) |
382 | regs->pp_div = INVALID_MMIO_REG((const i915_reg_t){ .reg = (0) }); |
383 | else |
384 | regs->pp_div = PP_DIVISOR(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61210) + (pps_idx) * 0x100) }); |
385 | } |
386 | |
387 | static i915_reg_t |
388 | _pp_ctrl_reg(struct intel_dp *intel_dp) |
389 | { |
390 | struct pps_registers regs; |
391 | |
392 | intel_pps_get_registers(intel_dp, ®s); |
393 | |
394 | return regs.pp_ctrl; |
395 | } |
396 | |
397 | static i915_reg_t |
398 | _pp_stat_reg(struct intel_dp *intel_dp) |
399 | { |
400 | struct pps_registers regs; |
401 | |
402 | intel_pps_get_registers(intel_dp, ®s); |
403 | |
404 | return regs.pp_stat; |
405 | } |
406 | |
407 | static bool_Bool edp_have_panel_power(struct intel_dp *intel_dp) |
408 | { |
409 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
410 | |
411 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
412 | |
413 | if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) && |
414 | intel_dp->pps.pps_pipe == INVALID_PIPE) |
415 | return false0; |
416 | |
417 | return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON((u32)((1UL << (31)) + 0))) != 0; |
418 | } |
419 | |
420 | static bool_Bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
421 | { |
422 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
423 | |
424 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
425 | |
426 | if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) && |
427 | intel_dp->pps.pps_pipe == INVALID_PIPE) |
428 | return false0; |
429 | |
430 | return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
431 | } |
432 | |
433 | void intel_pps_check_power_unlocked(struct intel_dp *intel_dp) |
434 | { |
435 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
436 | |
437 | if (!intel_dp_is_edp(intel_dp)) |
438 | return; |
439 | |
440 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
441 | drm_WARN(&dev_priv->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "eDP powered off while attempting aux channel communication.\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }) |
442 | "eDP powered off while attempting aux channel communication.\n")({ int __ret = !!(1); if (__ret) printf("%s %s: " "eDP powered off while attempting aux channel communication.\n" , dev_driver_string((&dev_priv->drm)->dev), ""); __builtin_expect (!!(__ret), 0); }); |
443 | drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Status 0x%08x Control 0x%08x\n" , intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read (dev_priv, _pp_ctrl_reg(intel_dp))) |
444 | intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Status 0x%08x Control 0x%08x\n" , intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read (dev_priv, _pp_ctrl_reg(intel_dp))) |
445 | intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Status 0x%08x Control 0x%08x\n" , intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), intel_de_read (dev_priv, _pp_ctrl_reg(intel_dp))); |
446 | } |
447 | } |
448 | |
449 | #define IDLE_ON_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | ((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | PP_SEQUENCE_STATE_MASK((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) |
450 | #define IDLE_ON_VALUE(((u32)((1UL << (31)) + 0)) | ((u32)((((typeof(((u32)(( ((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28) )) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0)) | 0 | ((u32)((((typeof(((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))))(0x8) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | PP_SEQUENCE_STATE_ON_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))) |
451 | |
452 | #define IDLE_OFF_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | 0) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | 0) |
453 | #define IDLE_OFF_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | 0) (0 | PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | 0) |
454 | |
455 | #define IDLE_CYCLE_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | ((u32)( (1UL << (27)) + 0)) | ((u32)((((~0UL) >> (64 - (3 ) - 1)) & ((~0UL) << (0))) + 0))) (PP_ON((u32)((1UL << (31)) + 0)) | PP_SEQUENCE_MASK((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | PP_CYCLE_DELAY_ACTIVE((u32)((1UL << (27)) + 0)) | PP_SEQUENCE_STATE_MASK((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) |
456 | #define IDLE_CYCLE_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) ) (0 | PP_SEQUENCE_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | PP_SEQUENCE_STATE_OFF_IDLE((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))) |
457 | |
458 | static void intel_pps_verify_state(struct intel_dp *intel_dp); |
459 | |
460 | static void wait_panel_status(struct intel_dp *intel_dp, |
461 | u32 mask, |
462 | u32 value) |
463 | { |
464 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
465 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
466 | |
467 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
468 | |
469 | intel_pps_verify_state(intel_dp); |
470 | |
471 | pp_stat_reg = _pp_stat_reg(intel_dp); |
472 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
473 | |
474 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
475 | "mask %08x value %08x status %08x control %08x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
476 | mask, value,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
477 | intel_de_read(dev_priv, pp_stat_reg),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)) |
478 | intel_de_read(dev_priv, pp_ctrl_reg))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "mask %08x value %08x status %08x control %08x\n" , mask, value, intel_de_read(dev_priv, pp_stat_reg), intel_de_read (dev_priv, pp_ctrl_reg)); |
479 | |
480 | if (intel_de_wait_for_register(dev_priv, pp_stat_reg, |
481 | mask, value, 5000)) |
482 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ) |
483 | "Panel status timeout: status %08x control %08x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ) |
484 | intel_de_read(dev_priv, pp_stat_reg),printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ) |
485 | intel_de_read(dev_priv, pp_ctrl_reg))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Panel status timeout: status %08x control %08x\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , intel_de_read (dev_priv, pp_stat_reg), intel_de_read(dev_priv, pp_ctrl_reg) ); |
486 | |
487 | drm_dbg_kms(&dev_priv->drm, "Wait complete\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Wait complete\n" ); |
488 | } |
489 | |
490 | static void wait_panel_on(struct intel_dp *intel_dp) |
491 | { |
492 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
493 | |
494 | drm_dbg_kms(&i915->drm, "Wait for panel power on\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Wait for panel power on\n" ); |
495 | wait_panel_status(intel_dp, IDLE_ON_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | ((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))), IDLE_ON_VALUE(((u32)((1UL << (31)) + 0)) | ((u32)((((typeof(((u32)(( ((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28) )) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0)) | 0 | ((u32)((((typeof(((u32 )((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0 ))) + 0))))(0x8) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)))); |
496 | } |
497 | |
498 | static void wait_panel_off(struct intel_dp *intel_dp) |
499 | { |
500 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
501 | |
502 | drm_dbg_kms(&i915->drm, "Wait for panel power off time\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Wait for panel power off time\n" ); |
503 | wait_panel_status(intel_dp, IDLE_OFF_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | 0 | 0), IDLE_OFF_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | 0)); |
504 | } |
505 | |
506 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
507 | { |
508 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
509 | ktime_t panel_power_on_time; |
510 | s64 panel_power_off_duration; |
511 | |
512 | drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Wait for panel power cycle\n" ); |
513 | |
514 | /* take the difference of current time and panel power off time |
515 | * and then make panel wait for t11_t12 if needed. */ |
516 | panel_power_on_time = ktime_get_boottime(); |
517 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->pps.panel_power_off_time); |
518 | |
519 | /* When we disable the VDD override bit last we have to do the manual |
520 | * wait. */ |
521 | if (panel_power_off_duration < (s64)intel_dp->pps.panel_power_cycle_delay) |
522 | wait_remaining_ms_from_jiffies(jiffies, |
523 | intel_dp->pps.panel_power_cycle_delay - panel_power_off_duration); |
524 | |
525 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK(((u32)((1UL << (31)) + 0)) | ((u32)((((~0UL) >> ( 64 - (29) - 1)) & ((~0UL) << (28))) + 0)) | ((u32)( (1UL << (27)) + 0)) | ((u32)((((~0UL) >> (64 - (3 ) - 1)) & ((~0UL) << (0))) + 0))), IDLE_CYCLE_VALUE(0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (29) - 1 )) & ((~0UL) << (28))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (29) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (29 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )) | 0 | ((u32)((((typeof(((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)) )); |
526 | } |
527 | |
528 | void intel_pps_wait_power_cycle(struct intel_dp *intel_dp) |
529 | { |
530 | intel_wakeref_t wakeref; |
531 | |
532 | if (!intel_dp_is_edp(intel_dp)) |
533 | return; |
534 | |
535 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) |
536 | wait_panel_power_cycle(intel_dp); |
537 | } |
538 | |
539 | static void wait_backlight_on(struct intel_dp *intel_dp) |
540 | { |
541 | wait_remaining_ms_from_jiffies(intel_dp->pps.last_power_on, |
542 | intel_dp->pps.backlight_on_delay); |
543 | } |
544 | |
545 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
546 | { |
547 | wait_remaining_ms_from_jiffies(intel_dp->pps.last_backlight_off, |
548 | intel_dp->pps.backlight_off_delay); |
549 | } |
550 | |
551 | /* Read the current pp_control value, unlocking the register if it |
552 | * is locked |
553 | */ |
554 | |
555 | static u32 ilk_get_pp_control(struct intel_dp *intel_dp) |
556 | { |
557 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
558 | u32 control; |
559 | |
560 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
561 | |
562 | control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)); |
563 | if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&({ int __ret = !!((!((&(dev_priv)->__info)->display .has_ddi) && (control & ((u32)((((~0UL) >> ( 64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32 )((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ( (~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__info)->display.has_ddi) && (control & ((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); }) |
564 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)({ int __ret = !!((!((&(dev_priv)->__info)->display .has_ddi) && (control & ((u32)((((~0UL) >> ( 64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32 )((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ( (~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!((&(dev_priv)->__info)->display.has_ddi) && (control & ((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); })) { |
565 | control &= ~PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0)); |
566 | control |= PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )); |
567 | } |
568 | return control; |
569 | } |
570 | |
571 | /* |
572 | * Must be paired with intel_pps_vdd_off_unlocked(). |
573 | * Must hold pps_mutex around the whole on/off sequence. |
574 | * Can be nested with intel_pps_vdd_{on,off}() calls. |
575 | */ |
576 | bool_Bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp) |
577 | { |
578 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
579 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
580 | u32 pp; |
581 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
582 | bool_Bool need_to_disable = !intel_dp->pps.want_panel_vdd; |
583 | |
584 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
585 | |
586 | if (!intel_dp_is_edp(intel_dp)) |
587 | return false0; |
588 | |
589 | cancel_delayed_work(&intel_dp->pps.panel_vdd_work); |
590 | intel_dp->pps.want_panel_vdd = true1; |
591 | |
592 | if (edp_have_panel_vdd(intel_dp)) |
593 | return need_to_disable; |
594 | |
595 | drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref)({ int __ret = !!((intel_dp->pps.vdd_wakeref)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.vdd_wakeref" ")"); __builtin_expect(!!(__ret), 0); }); |
596 | intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, |
597 | intel_aux_power_domain(dig_port)); |
598 | |
599 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD on\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
600 | dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD on\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
601 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD on\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
602 | |
603 | if (!edp_have_panel_power(intel_dp)) |
604 | wait_panel_power_cycle(intel_dp); |
605 | |
606 | pp = ilk_get_pp_control(intel_dp); |
607 | pp |= EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
608 | |
609 | pp_stat_reg = _pp_stat_reg(intel_dp); |
610 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
611 | |
612 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
613 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
614 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
615 | intel_de_read(dev_priv, pp_stat_reg),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
616 | intel_de_read(dev_priv, pp_ctrl_reg))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)); |
617 | /* |
618 | * If the panel wasn't on, delay before accessing aux channel |
619 | */ |
620 | if (!edp_have_panel_power(intel_dp)) { |
621 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
622 | "[ENCODER:%d:%s] panel power wasn't enabled\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
623 | dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
624 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] panel power wasn't enabled\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
625 | drm_msleep(intel_dp->pps.panel_power_up_delay)mdelay(intel_dp->pps.panel_power_up_delay); |
626 | } |
627 | |
628 | return need_to_disable; |
629 | } |
630 | |
631 | /* |
632 | * Must be paired with intel_pps_off(). |
633 | * Nested calls to these functions are not allowed since |
634 | * we drop the lock. Caller must use some higher level |
635 | * locking to prevent nested calls from other threads. |
636 | */ |
637 | void intel_pps_vdd_on(struct intel_dp *intel_dp) |
638 | { |
639 | intel_wakeref_t wakeref; |
640 | bool_Bool vdd; |
641 | |
642 | if (!intel_dp_is_edp(intel_dp)) |
643 | return; |
644 | |
645 | vdd = false0; |
646 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) |
647 | vdd = intel_pps_vdd_on_unlocked(intel_dp); |
648 | I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",({ int __ret_warn_on = !!(!vdd); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret_warn_on ), 0); }) |
649 | dp_to_dig_port(intel_dp)->base.base.base.id,({ int __ret_warn_on = !!(!vdd); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret_warn_on ), 0); }) |
650 | dp_to_dig_port(intel_dp)->base.base.name)({ int __ret_warn_on = !!(!vdd); if (__builtin_expect(!!(__ret_warn_on ), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks ); if (__ret) printf("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD already requested on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret_warn_on ), 0); }); |
651 | } |
652 | |
653 | static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp) |
654 | { |
655 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
656 | struct intel_digital_port *dig_port = |
657 | dp_to_dig_port(intel_dp); |
658 | u32 pp; |
659 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
660 | |
661 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
662 | |
663 | drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd)({ int __ret = !!((intel_dp->pps.want_panel_vdd)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.want_panel_vdd" ")"); __builtin_expect(!!(__ret), 0); }); |
664 | |
665 | if (!edp_have_panel_vdd(intel_dp)) |
666 | return; |
667 | |
668 | drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD off\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
669 | dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD off\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
670 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turning [ENCODER:%d:%s] VDD off\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
671 | |
672 | pp = ilk_get_pp_control(intel_dp); |
673 | pp &= ~EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
674 | |
675 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
676 | pp_stat_reg = _pp_stat_reg(intel_dp); |
677 | |
678 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
679 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
680 | |
681 | /* Make sure sequencer is idle before allowing subsequent activity */ |
682 | drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
683 | intel_de_read(dev_priv, pp_stat_reg),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)) |
684 | intel_de_read(dev_priv, pp_ctrl_reg))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n" , intel_de_read(dev_priv, pp_stat_reg), intel_de_read(dev_priv , pp_ctrl_reg)); |
685 | |
686 | if ((pp & PANEL_POWER_ON((u32)((1UL << (0)) + 0))) == 0) |
687 | intel_dp->pps.panel_power_off_time = ktime_get_boottime(); |
688 | |
689 | intel_display_power_put(dev_priv, |
690 | intel_aux_power_domain(dig_port), |
691 | fetch_and_zero(&intel_dp->pps.vdd_wakeref)({ typeof(*&intel_dp->pps.vdd_wakeref) __T = *(&intel_dp ->pps.vdd_wakeref); *(&intel_dp->pps.vdd_wakeref) = (typeof(*&intel_dp->pps.vdd_wakeref))0; __T; })); |
692 | } |
693 | |
694 | void intel_pps_vdd_off_sync(struct intel_dp *intel_dp) |
695 | { |
696 | intel_wakeref_t wakeref; |
697 | |
698 | if (!intel_dp_is_edp(intel_dp)) |
699 | return; |
700 | |
701 | cancel_delayed_work_sync(&intel_dp->pps.panel_vdd_work); |
702 | /* |
703 | * vdd might still be enabled due to the delayed vdd off. |
704 | * Make sure vdd is actually turned off here. |
705 | */ |
706 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) |
707 | intel_pps_vdd_off_sync_unlocked(intel_dp); |
708 | } |
709 | |
710 | static void edp_panel_vdd_work(struct work_struct *__work) |
711 | { |
712 | struct intel_pps *pps = container_of(to_delayed_work(__work),({ const __typeof( ((struct intel_pps *)0)->panel_vdd_work ) *__mptr = (to_delayed_work(__work)); (struct intel_pps *)( (char *)__mptr - __builtin_offsetof(struct intel_pps, panel_vdd_work ) );}) |
713 | struct intel_pps, panel_vdd_work)({ const __typeof( ((struct intel_pps *)0)->panel_vdd_work ) *__mptr = (to_delayed_work(__work)); (struct intel_pps *)( (char *)__mptr - __builtin_offsetof(struct intel_pps, panel_vdd_work ) );}); |
714 | struct intel_dp *intel_dp = container_of(pps, struct intel_dp, pps)({ const __typeof( ((struct intel_dp *)0)->pps ) *__mptr = (pps); (struct intel_dp *)( (char *)__mptr - __builtin_offsetof (struct intel_dp, pps) );}); |
715 | intel_wakeref_t wakeref; |
716 | |
717 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
718 | if (!intel_dp->pps.want_panel_vdd) |
719 | intel_pps_vdd_off_sync_unlocked(intel_dp); |
720 | } |
721 | } |
722 | |
723 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
724 | { |
725 | unsigned long delay; |
726 | |
727 | /* |
728 | * We may not yet know the real power sequencing delays, |
729 | * so keep VDD enabled until we're done with init. |
730 | */ |
731 | if (intel_dp->pps.initializing) |
732 | return; |
733 | |
734 | /* |
735 | * Queue the timer to fire a long time from now (relative to the power |
736 | * down delay) to keep the panel power up across a sequence of |
737 | * operations. |
738 | */ |
739 | delay = msecs_to_jiffies(intel_dp->pps.panel_power_cycle_delay * 5)(((uint64_t)(intel_dp->pps.panel_power_cycle_delay * 5)) * hz / 1000); |
740 | schedule_delayed_work(&intel_dp->pps.panel_vdd_work, delay); |
741 | } |
742 | |
743 | /* |
744 | * Must be paired with edp_panel_vdd_on(). |
745 | * Must hold pps_mutex around the whole on/off sequence. |
746 | * Can be nested with intel_pps_vdd_{on,off}() calls. |
747 | */ |
748 | void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool_Bool sync) |
749 | { |
750 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
751 | |
752 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
753 | |
754 | if (!intel_dp_is_edp(intel_dp)) |
755 | return; |
756 | |
757 | I915_STATE_WARN(!intel_dp->pps.want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",({ int __ret_warn_on = !!(!intel_dp->pps.want_panel_vdd); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] VDD not forced on" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD not forced on", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret_warn_on), 0); }) |
758 | dp_to_dig_port(intel_dp)->base.base.base.id,({ int __ret_warn_on = !!(!intel_dp->pps.want_panel_vdd); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] VDD not forced on" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD not forced on", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret_warn_on), 0); }) |
759 | dp_to_dig_port(intel_dp)->base.base.name)({ int __ret_warn_on = !!(!intel_dp->pps.want_panel_vdd); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf("[ENCODER:%d:%s] VDD not forced on" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); __builtin_expect(!!(__ret), 0 ); })) __drm_err("[ENCODER:%d:%s] VDD not forced on", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret_warn_on), 0); }); |
760 | |
761 | intel_dp->pps.want_panel_vdd = false0; |
762 | |
763 | if (sync) |
764 | intel_pps_vdd_off_sync_unlocked(intel_dp); |
765 | else |
766 | edp_panel_vdd_schedule_off(intel_dp); |
767 | } |
768 | |
769 | void intel_pps_on_unlocked(struct intel_dp *intel_dp) |
770 | { |
771 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
772 | u32 pp; |
773 | i915_reg_t pp_ctrl_reg; |
774 | |
775 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
776 | |
777 | if (!intel_dp_is_edp(intel_dp)) |
778 | return; |
779 | |
780 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name) |
781 | dp_to_dig_port(intel_dp)->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name) |
782 | dp_to_dig_port(intel_dp)->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power on\n" , dp_to_dig_port(intel_dp)->base.base.base.id, dp_to_dig_port (intel_dp)->base.base.name); |
783 | |
784 | if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); }) |
785 | "[ENCODER:%d:%s] panel power already on\n",({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); }) |
786 | dp_to_dig_port(intel_dp)->base.base.base.id,({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); }) |
787 | dp_to_dig_port(intel_dp)->base.base.name)({ int __ret = !!(edp_have_panel_power(intel_dp)); if (__ret) printf("%s %s: " "[ENCODER:%d:%s] panel power already on\n", dev_driver_string((&dev_priv->drm)->dev), "", dp_to_dig_port (intel_dp)->base.base.base.id, dp_to_dig_port(intel_dp)-> base.base.name); __builtin_expect(!!(__ret), 0); })) |
788 | return; |
789 | |
790 | wait_panel_power_cycle(intel_dp); |
791 | |
792 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
793 | pp = ilk_get_pp_control(intel_dp); |
794 | if (IS_IRONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IRONLAKE)) { |
795 | /* ILK workaround: disable reset around power sequence */ |
796 | pp &= ~PANEL_POWER_RESET((u32)((1UL << (1)) + 0)); |
797 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
798 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
799 | } |
800 | |
801 | pp |= PANEL_POWER_ON((u32)((1UL << (0)) + 0)); |
802 | if (!IS_IRONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IRONLAKE)) |
803 | pp |= PANEL_POWER_RESET((u32)((1UL << (1)) + 0)); |
804 | |
805 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
806 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
807 | |
808 | wait_panel_on(intel_dp); |
809 | intel_dp->pps.last_power_on = jiffies; |
810 | |
811 | if (IS_IRONLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_IRONLAKE)) { |
812 | pp |= PANEL_POWER_RESET((u32)((1UL << (1)) + 0)); /* restore panel reset bit */ |
813 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
814 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
815 | } |
816 | } |
817 | |
818 | void intel_pps_on(struct intel_dp *intel_dp) |
819 | { |
820 | intel_wakeref_t wakeref; |
821 | |
822 | if (!intel_dp_is_edp(intel_dp)) |
823 | return; |
824 | |
825 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) |
826 | intel_pps_on_unlocked(intel_dp); |
827 | } |
828 | |
829 | void intel_pps_off_unlocked(struct intel_dp *intel_dp) |
830 | { |
831 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
832 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
833 | u32 pp; |
834 | i915_reg_t pp_ctrl_reg; |
835 | |
836 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
837 | |
838 | if (!intel_dp_is_edp(intel_dp)) |
839 | return; |
840 | |
841 | drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power off\n" , dig_port->base.base.base.id, dig_port->base.base.name ) |
842 | dig_port->base.base.base.id, dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Turn [ENCODER:%d:%s] panel power off\n" , dig_port->base.base.base.id, dig_port->base.base.name ); |
843 | |
844 | drm_WARN(&dev_priv->drm, !intel_dp->pps.want_panel_vdd,({ int __ret = !!(!intel_dp->pps.want_panel_vdd); if (__ret ) printf("%s %s: " "Need [ENCODER:%d:%s] VDD to turn off panel\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name); __builtin_expect (!!(__ret), 0); }) |
845 | "Need [ENCODER:%d:%s] VDD to turn off panel\n",({ int __ret = !!(!intel_dp->pps.want_panel_vdd); if (__ret ) printf("%s %s: " "Need [ENCODER:%d:%s] VDD to turn off panel\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name); __builtin_expect (!!(__ret), 0); }) |
846 | dig_port->base.base.base.id, dig_port->base.base.name)({ int __ret = !!(!intel_dp->pps.want_panel_vdd); if (__ret ) printf("%s %s: " "Need [ENCODER:%d:%s] VDD to turn off panel\n" , dev_driver_string((&dev_priv->drm)->dev), "", dig_port ->base.base.base.id, dig_port->base.base.name); __builtin_expect (!!(__ret), 0); }); |
847 | |
848 | pp = ilk_get_pp_control(intel_dp); |
849 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
850 | * panels get very unhappy and cease to work. */ |
851 | pp &= ~(PANEL_POWER_ON((u32)((1UL << (0)) + 0)) | PANEL_POWER_RESET((u32)((1UL << (1)) + 0)) | EDP_FORCE_VDD((u32)((1UL << (3)) + 0)) | |
852 | EDP_BLC_ENABLE((u32)((1UL << (2)) + 0))); |
853 | |
854 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
855 | |
856 | intel_dp->pps.want_panel_vdd = false0; |
857 | |
858 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
859 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
860 | |
861 | wait_panel_off(intel_dp); |
862 | intel_dp->pps.panel_power_off_time = ktime_get_boottime(); |
863 | |
864 | /* We got a reference when we enabled the VDD. */ |
865 | intel_display_power_put(dev_priv, |
866 | intel_aux_power_domain(dig_port), |
867 | fetch_and_zero(&intel_dp->pps.vdd_wakeref)({ typeof(*&intel_dp->pps.vdd_wakeref) __T = *(&intel_dp ->pps.vdd_wakeref); *(&intel_dp->pps.vdd_wakeref) = (typeof(*&intel_dp->pps.vdd_wakeref))0; __T; })); |
868 | } |
869 | |
870 | void intel_pps_off(struct intel_dp *intel_dp) |
871 | { |
872 | intel_wakeref_t wakeref; |
873 | |
874 | if (!intel_dp_is_edp(intel_dp)) |
875 | return; |
876 | |
877 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) |
878 | intel_pps_off_unlocked(intel_dp); |
879 | } |
880 | |
881 | /* Enable backlight in the panel power control. */ |
882 | void intel_pps_backlight_on(struct intel_dp *intel_dp) |
883 | { |
884 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
885 | intel_wakeref_t wakeref; |
886 | |
887 | /* |
888 | * If we enable the backlight right away following a panel power |
889 | * on, we may see slight flicker as the panel syncs with the eDP |
890 | * link. So delay a bit to make sure the image is solid before |
891 | * allowing it to appear. |
892 | */ |
893 | wait_backlight_on(intel_dp); |
894 | |
895 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
896 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
897 | u32 pp; |
898 | |
899 | pp = ilk_get_pp_control(intel_dp); |
900 | pp |= EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)); |
901 | |
902 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
903 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
904 | } |
905 | } |
906 | |
907 | /* Disable backlight in the panel power control. */ |
908 | void intel_pps_backlight_off(struct intel_dp *intel_dp) |
909 | { |
910 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
911 | intel_wakeref_t wakeref; |
912 | |
913 | if (!intel_dp_is_edp(intel_dp)) |
914 | return; |
915 | |
916 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
917 | i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
918 | u32 pp; |
919 | |
920 | pp = ilk_get_pp_control(intel_dp); |
921 | pp &= ~EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)); |
922 | |
923 | intel_de_write(dev_priv, pp_ctrl_reg, pp); |
924 | intel_de_posting_read(dev_priv, pp_ctrl_reg); |
925 | } |
926 | |
927 | intel_dp->pps.last_backlight_off = jiffies; |
928 | edp_wait_backlight_off(intel_dp); |
929 | } |
930 | |
931 | /* |
932 | * Hook for controlling the panel power control backlight through the bl_power |
933 | * sysfs attribute. Take care to handle multiple calls. |
934 | */ |
935 | void intel_pps_backlight_power(struct intel_connector *connector, bool_Bool enable) |
936 | { |
937 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->base.dev); |
938 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
939 | intel_wakeref_t wakeref; |
940 | bool_Bool is_enabled; |
941 | |
942 | is_enabled = false0; |
943 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) |
944 | is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE((u32)((1UL << (2)) + 0)); |
945 | if (is_enabled == enable) |
946 | return; |
947 | |
948 | drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "panel power control backlight %s\n" , enable ? "enable" : "disable") |
949 | enable ? "enable" : "disable")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "panel power control backlight %s\n" , enable ? "enable" : "disable"); |
950 | |
951 | if (enable) |
952 | intel_pps_backlight_on(intel_dp); |
953 | else |
954 | intel_pps_backlight_off(intel_dp); |
955 | } |
956 | |
957 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
958 | { |
959 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
960 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
961 | enum pipe pipe = intel_dp->pps.pps_pipe; |
962 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61208) + (pipe) * 0x100) }); |
963 | |
964 | drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
965 | |
966 | if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B)({ int __ret = !!((pipe != PIPE_A && pipe != PIPE_B)) ; if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "pipe != PIPE_A && pipe != PIPE_B" ")"); __builtin_expect(!!(__ret), 0); })) |
967 | return; |
968 | |
969 | intel_pps_vdd_off_sync_unlocked(intel_dp); |
970 | |
971 | /* |
972 | * VLV seems to get confused when multiple power sequencers |
973 | * have the same port selected (even if only one has power/vdd |
974 | * enabled). The failure manifests as vlv_wait_port_ready() failing |
975 | * CHV on the other hand doesn't seem to mind having the same port |
976 | * selected in multiple power sequencers, but let's clear the |
977 | * port select always when logically disconnecting a power sequencer |
978 | * from a port. |
979 | */ |
980 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
981 | "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
982 | pipe_name(pipe), dig_port->base.base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name) |
983 | dig_port->base.base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), dig_port->base.base.base.id, dig_port-> base.base.name); |
984 | intel_de_write(dev_priv, pp_on_reg, 0); |
985 | intel_de_posting_read(dev_priv, pp_on_reg); |
986 | |
987 | intel_dp->pps.pps_pipe = INVALID_PIPE; |
988 | } |
989 | |
990 | static void vlv_steal_power_sequencer(struct drm_i915_privateinteldrm_softc *dev_priv, |
991 | enum pipe pipe) |
992 | { |
993 | struct intel_encoder *encoder; |
994 | |
995 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
996 | |
997 | for_each_intel_dp(&dev_priv->drm, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(&dev_priv->drm)->mode_config .encoder_list)->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof(*encoder), base.head) );}); & encoder->base.head != (&(&dev_priv->drm)->mode_config .encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder ) *)0)->base.head ) *__mptr = (encoder->base.head.next) ; (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );})) if (!(intel_encoder_is_dp (encoder))) {} else { |
998 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
999 | |
1000 | drm_WARN(&dev_priv->drm, intel_dp->pps.active_pipe == pipe,({ int __ret = !!(intel_dp->pps.active_pipe == pipe); if ( __ret) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }) |
1001 | "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",({ int __ret = !!(intel_dp->pps.active_pipe == pipe); if ( __ret) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }) |
1002 | pipe_name(pipe), encoder->base.base.id,({ int __ret = !!(intel_dp->pps.active_pipe == pipe); if ( __ret) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }) |
1003 | encoder->base.name)({ int __ret = !!(intel_dp->pps.active_pipe == pipe); if ( __ret) printf("%s %s: " "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n" , dev_driver_string((&dev_priv->drm)->dev), "", ((pipe ) + 'A'), encoder->base.base.id, encoder->base.name); __builtin_expect (!!(__ret), 0); }); |
1004 | |
1005 | if (intel_dp->pps.pps_pipe != pipe) |
1006 | continue; |
1007 | |
1008 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name) |
1009 | "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name) |
1010 | pipe_name(pipe), encoder->base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name) |
1011 | encoder->base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n" , ((pipe) + 'A'), encoder->base.base.id, encoder->base. name); |
1012 | |
1013 | /* make sure vdd is off before we steal it */ |
1014 | vlv_detach_power_sequencer(intel_dp); |
1015 | } |
1016 | } |
1017 | |
1018 | void vlv_pps_init(struct intel_encoder *encoder, |
1019 | const struct intel_crtc_state *crtc_state) |
1020 | { |
1021 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
1022 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1023 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
1024 | |
1025 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
1026 | |
1027 | drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE)({ int __ret = !!((intel_dp->pps.active_pipe != INVALID_PIPE )); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.active_pipe != INVALID_PIPE" ")"); __builtin_expect(!!(__ret), 0); }); |
1028 | |
1029 | if (intel_dp->pps.pps_pipe != INVALID_PIPE && |
1030 | intel_dp->pps.pps_pipe != crtc->pipe) { |
1031 | /* |
1032 | * If another power sequencer was being used on this |
1033 | * port previously make sure to turn off vdd there while |
1034 | * we still have control of it. |
1035 | */ |
1036 | vlv_detach_power_sequencer(intel_dp); |
1037 | } |
1038 | |
1039 | /* |
1040 | * We may be stealing the power |
1041 | * sequencer from another port. |
1042 | */ |
1043 | vlv_steal_power_sequencer(dev_priv, crtc->pipe); |
1044 | |
1045 | intel_dp->pps.active_pipe = crtc->pipe; |
1046 | |
1047 | if (!intel_dp_is_edp(intel_dp)) |
1048 | return; |
1049 | |
1050 | /* now it's all ours */ |
1051 | intel_dp->pps.pps_pipe = crtc->pipe; |
1052 | |
1053 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), encoder->base.base. id, encoder->base.name) |
1054 | "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), encoder->base.base. id, encoder->base.name) |
1055 | pipe_name(intel_dp->pps.pps_pipe), encoder->base.base.id,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), encoder->base.base. id, encoder->base.name) |
1056 | encoder->base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n" , ((intel_dp->pps.pps_pipe) + 'A'), encoder->base.base. id, encoder->base.name); |
1057 | |
1058 | /* init power sequencer on this pipe and port */ |
1059 | pps_init_delays(intel_dp); |
1060 | pps_init_registers(intel_dp, true1); |
1061 | } |
1062 | |
1063 | static void pps_vdd_init(struct intel_dp *intel_dp) |
1064 | { |
1065 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1066 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1067 | |
1068 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
1069 | |
1070 | if (!edp_have_panel_vdd(intel_dp)) |
1071 | return; |
1072 | |
1073 | /* |
1074 | * The VDD bit needs a power domain reference, so if the bit is |
1075 | * already enabled when we boot or resume, grab this reference and |
1076 | * schedule a vdd off, so we don't hold on to the reference |
1077 | * indefinitely. |
1078 | */ |
1079 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VDD left on by BIOS, adjusting state tracking\n" ) |
1080 | "VDD left on by BIOS, adjusting state tracking\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VDD left on by BIOS, adjusting state tracking\n" ); |
1081 | drm_WARN_ON(&dev_priv->drm, intel_dp->pps.vdd_wakeref)({ int __ret = !!((intel_dp->pps.vdd_wakeref)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "intel_dp->pps.vdd_wakeref" ")"); __builtin_expect(!!(__ret), 0); }); |
1082 | intel_dp->pps.vdd_wakeref = intel_display_power_get(dev_priv, |
1083 | intel_aux_power_domain(dig_port)); |
1084 | } |
1085 | |
1086 | bool_Bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp) |
1087 | { |
1088 | intel_wakeref_t wakeref; |
1089 | bool_Bool have_power = false0; |
1090 | |
1091 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
1092 | have_power = edp_have_panel_power(intel_dp) || |
1093 | edp_have_panel_vdd(intel_dp); |
1094 | } |
1095 | |
1096 | return have_power; |
1097 | } |
1098 | |
1099 | static void pps_init_timestamps(struct intel_dp *intel_dp) |
1100 | { |
1101 | intel_dp->pps.panel_power_off_time = ktime_get_boottime(); |
1102 | intel_dp->pps.last_power_on = jiffies; |
1103 | intel_dp->pps.last_backlight_off = jiffies; |
1104 | } |
1105 | |
1106 | static void |
1107 | intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) |
1108 | { |
1109 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1110 | u32 pp_on, pp_off, pp_ctl; |
1111 | struct pps_registers regs; |
1112 | |
1113 | intel_pps_get_registers(intel_dp, ®s); |
1114 | |
1115 | pp_ctl = ilk_get_pp_control(intel_dp); |
1116 | |
1117 | /* Ensure PPS is unlocked */ |
1118 | if (!HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
1119 | intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); |
1120 | |
1121 | pp_on = intel_de_read(dev_priv, regs.pp_on); |
1122 | pp_off = intel_de_read(dev_priv, regs.pp_off); |
1123 | |
1124 | /* Pull timing values out of registers */ |
1125 | seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on)((u32)((typeof(((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))))(((pp_on) & (((u32)((((~0UL ) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0 )))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))) - 1)))); |
1126 | seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on)((u32)((typeof(((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0))))(((pp_on) & (((u32)((((~0UL ) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0) ))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 12) - 1)) & ((~0UL) << (0))) + 0))) - 1)))); |
1127 | seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off)((u32)((typeof(((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0))))(((pp_off) & (((u32)((((~0UL ) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0) ))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 12) - 1)) & ((~0UL) << (0))) + 0))) - 1)))); |
1128 | seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off)((u32)((typeof(((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))))(((pp_off) & (((u32)((((~ 0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0)))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))) - 1)))); |
1129 | |
1130 | if (i915_mmio_reg_valid(regs.pp_div)) { |
1131 | u32 pp_div; |
1132 | |
1133 | pp_div = intel_de_read(dev_priv, regs.pp_div); |
1134 | |
1135 | seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div)((u32)((typeof(((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (0))) + 0))))(((pp_div) & (((u32)((((~0UL ) >> (64 - (4) - 1)) & ((~0UL) << (0))) + 0)) )) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 4) - 1)) & ((~0UL) << (0))) + 0))) - 1)))) * 1000; |
1136 | } else { |
1137 | seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl)((u32)((typeof(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (4))) + 0))))(((pp_ctl) & (((u32)((((~0UL ) >> (64 - (8) - 1)) & ((~0UL) << (4))) + 0)) )) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 8) - 1)) & ((~0UL) << (4))) + 0))) - 1)))) * 1000; |
1138 | } |
1139 | } |
1140 | |
1141 | static void |
1142 | intel_pps_dump_state(struct intel_dp *intel_dp, const char *state_name, |
1143 | const struct edp_power_seq *seq) |
1144 | { |
1145 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1146 | |
1147 | drm_dbg_kms(&i915->drm, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n" , state_name, seq->t1_t3, seq->t8, seq->t9, seq-> t10, seq->t11_t12) |
1148 | state_name,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n" , state_name, seq->t1_t3, seq->t8, seq->t9, seq-> t10, seq->t11_t12) |
1149 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n" , state_name, seq->t1_t3, seq->t8, seq->t9, seq-> t10, seq->t11_t12); |
1150 | } |
1151 | |
1152 | static void |
1153 | intel_pps_verify_state(struct intel_dp *intel_dp) |
1154 | { |
1155 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
Value stored to 'i915' during its initialization is never read | |
1156 | struct edp_power_seq hw; |
1157 | struct edp_power_seq *sw = &intel_dp->pps.pps_delays; |
1158 | |
1159 | intel_pps_readout_hw_state(intel_dp, &hw); |
1160 | |
1161 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || |
1162 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { |
1163 | drm_err(&i915->drm, "PPS state mismatch\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PPS state mismatch\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1164 | intel_pps_dump_state(intel_dp, "sw", sw); |
1165 | intel_pps_dump_state(intel_dp, "hw", &hw); |
1166 | } |
1167 | } |
1168 | |
1169 | static bool_Bool pps_delays_valid(struct edp_power_seq *delays) |
1170 | { |
1171 | return delays->t1_t3 || delays->t8 || delays->t9 || |
1172 | delays->t10 || delays->t11_t12; |
1173 | } |
1174 | |
1175 | static void pps_init_delays_bios(struct intel_dp *intel_dp, |
1176 | struct edp_power_seq *bios) |
1177 | { |
1178 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1179 | |
1180 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
1181 | |
1182 | if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays)) |
1183 | intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays); |
1184 | |
1185 | *bios = intel_dp->pps.bios_pps_delays; |
1186 | |
1187 | intel_pps_dump_state(intel_dp, "bios", bios); |
1188 | } |
1189 | |
1190 | static void pps_init_delays_vbt(struct intel_dp *intel_dp, |
1191 | struct edp_power_seq *vbt) |
1192 | { |
1193 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1194 | struct intel_connector *connector = intel_dp->attached_connector; |
1195 | |
1196 | *vbt = connector->panel.vbt.edp.pps; |
1197 | |
1198 | if (!pps_delays_valid(vbt)) |
1199 | return; |
1200 | |
1201 | /* On Toshiba Satellite P50-C-18C system the VBT T12 delay |
1202 | * of 500ms appears to be too short. Ocassionally the panel |
1203 | * just fails to power back on. Increasing the delay to 800ms |
1204 | * seems sufficient to avoid this problem. |
1205 | */ |
1206 | if (intel_has_quirk(dev_priv, QUIRK_INCREASE_T12_DELAY)) { |
1207 | vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10)({ u16 __max_a = (vbt->t11_t12); u16 __max_b = (1300 * 10) ; __max_a > __max_b ? __max_a : __max_b; }); |
1208 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Increasing T12 panel delay as per the quirk to %d\n" , vbt->t11_t12) |
1209 | "Increasing T12 panel delay as per the quirk to %d\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Increasing T12 panel delay as per the quirk to %d\n" , vbt->t11_t12) |
1210 | vbt->t11_t12)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Increasing T12 panel delay as per the quirk to %d\n" , vbt->t11_t12); |
1211 | } |
1212 | |
1213 | /* T11_T12 delay is special and actually in units of 100ms, but zero |
1214 | * based in the hw (so we need to add 100 ms). But the sw vbt |
1215 | * table multiplies it with 1000 to make it in units of 100usec, |
1216 | * too. */ |
1217 | vbt->t11_t12 += 100 * 10; |
1218 | |
1219 | intel_pps_dump_state(intel_dp, "vbt", vbt); |
1220 | } |
1221 | |
1222 | static void pps_init_delays_spec(struct intel_dp *intel_dp, |
1223 | struct edp_power_seq *spec) |
1224 | { |
1225 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1226 | |
1227 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
1228 | |
1229 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
1230 | * our hw here, which are all in 100usec. */ |
1231 | spec->t1_t3 = 210 * 10; |
1232 | spec->t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
1233 | spec->t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
1234 | spec->t10 = 500 * 10; |
1235 | /* This one is special and actually in units of 100ms, but zero |
1236 | * based in the hw (so we need to add 100 ms). But the sw vbt |
1237 | * table multiplies it with 1000 to make it in units of 100usec, |
1238 | * too. */ |
1239 | spec->t11_t12 = (510 + 100) * 10; |
1240 | |
1241 | intel_pps_dump_state(intel_dp, "spec", spec); |
1242 | } |
1243 | |
1244 | static void pps_init_delays(struct intel_dp *intel_dp) |
1245 | { |
1246 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1247 | struct edp_power_seq cur, vbt, spec, |
1248 | *final = &intel_dp->pps.pps_delays; |
1249 | |
1250 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
1251 | |
1252 | /* already initialized? */ |
1253 | if (pps_delays_valid(final)) |
1254 | return; |
1255 | |
1256 | pps_init_delays_bios(intel_dp, &cur); |
1257 | pps_init_delays_vbt(intel_dp, &vbt); |
1258 | pps_init_delays_spec(intel_dp, &spec); |
1259 | |
1260 | /* Use the max of the register settings and vbt. If both are |
1261 | * unset, fall back to the spec limits. */ |
1262 | #define assign_final(field) final->field = (max(cur.field, vbt.field)(((cur.field)>(vbt.field))?(cur.field):(vbt.field)) == 0 ? \ |
1263 | spec.field : \ |
1264 | max(cur.field, vbt.field)(((cur.field)>(vbt.field))?(cur.field):(vbt.field))) |
1265 | assign_final(t1_t3); |
1266 | assign_final(t8); |
1267 | assign_final(t9); |
1268 | assign_final(t10); |
1269 | assign_final(t11_t12); |
1270 | #undef assign_final |
1271 | |
1272 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)(((final->field) + ((10) - 1)) / (10))) |
1273 | intel_dp->pps.panel_power_up_delay = get_delay(t1_t3); |
1274 | intel_dp->pps.backlight_on_delay = get_delay(t8); |
1275 | intel_dp->pps.backlight_off_delay = get_delay(t9); |
1276 | intel_dp->pps.panel_power_down_delay = get_delay(t10); |
1277 | intel_dp->pps.panel_power_cycle_delay = get_delay(t11_t12); |
1278 | #undef get_delay |
1279 | |
1280 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power up delay %d, power down delay %d, power cycle delay %d\n" , intel_dp->pps.panel_power_up_delay, intel_dp->pps.panel_power_down_delay , intel_dp->pps.panel_power_cycle_delay) |
1281 | "panel power up delay %d, power down delay %d, power cycle delay %d\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power up delay %d, power down delay %d, power cycle delay %d\n" , intel_dp->pps.panel_power_up_delay, intel_dp->pps.panel_power_down_delay , intel_dp->pps.panel_power_cycle_delay) |
1282 | intel_dp->pps.panel_power_up_delay,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power up delay %d, power down delay %d, power cycle delay %d\n" , intel_dp->pps.panel_power_up_delay, intel_dp->pps.panel_power_down_delay , intel_dp->pps.panel_power_cycle_delay) |
1283 | intel_dp->pps.panel_power_down_delay,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power up delay %d, power down delay %d, power cycle delay %d\n" , intel_dp->pps.panel_power_up_delay, intel_dp->pps.panel_power_down_delay , intel_dp->pps.panel_power_cycle_delay) |
1284 | intel_dp->pps.panel_power_cycle_delay)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power up delay %d, power down delay %d, power cycle delay %d\n" , intel_dp->pps.panel_power_up_delay, intel_dp->pps.panel_power_down_delay , intel_dp->pps.panel_power_cycle_delay); |
1285 | |
1286 | drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "backlight on delay %d, off delay %d\n" , intel_dp->pps.backlight_on_delay, intel_dp->pps.backlight_off_delay ) |
1287 | intel_dp->pps.backlight_on_delay,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "backlight on delay %d, off delay %d\n" , intel_dp->pps.backlight_on_delay, intel_dp->pps.backlight_off_delay ) |
1288 | intel_dp->pps.backlight_off_delay)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "backlight on delay %d, off delay %d\n" , intel_dp->pps.backlight_on_delay, intel_dp->pps.backlight_off_delay ); |
1289 | |
1290 | /* |
1291 | * We override the HW backlight delays to 1 because we do manual waits |
1292 | * on them. For T8, even BSpec recommends doing it. For T9, if we |
1293 | * don't do this, we'll end up waiting for the backlight off delay |
1294 | * twice: once when we do the manual sleep, and once when we disable |
1295 | * the panel and wait for the PP_STATUS bit to become zero. |
1296 | */ |
1297 | final->t8 = 1; |
1298 | final->t9 = 1; |
1299 | |
1300 | /* |
1301 | * HW has only a 100msec granularity for t11_t12 so round it up |
1302 | * accordingly. |
1303 | */ |
1304 | final->t11_t12 = roundup(final->t11_t12, 100 * 10)((((final->t11_t12)+((100 * 10)-1))/(100 * 10))*(100 * 10) ); |
1305 | } |
1306 | |
1307 | static void pps_init_registers(struct intel_dp *intel_dp, bool_Bool force_disable_vdd) |
1308 | { |
1309 | struct drm_i915_privateinteldrm_softc *dev_priv = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1310 | u32 pp_on, pp_off, port_sel = 0; |
1311 | int div = RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime)->rawclk_freq / 1000; |
1312 | struct pps_registers regs; |
1313 | enum port port = dp_to_dig_port(intel_dp)->base.port; |
1314 | const struct edp_power_seq *seq = &intel_dp->pps.pps_delays; |
1315 | |
1316 | lockdep_assert_held(&dev_priv->display.pps.mutex)do { (void)(&dev_priv->display.pps.mutex); } while(0); |
1317 | |
1318 | intel_pps_get_registers(intel_dp, ®s); |
1319 | |
1320 | /* |
1321 | * On some VLV machines the BIOS can leave the VDD |
1322 | * enabled even on power sequencers which aren't |
1323 | * hooked up to any port. This would mess up the |
1324 | * power domain tracking the first time we pick |
1325 | * one of these power sequencers for use since |
1326 | * intel_pps_vdd_on_unlocked() would notice that the VDD was |
1327 | * already on and therefore wouldn't grab the power |
1328 | * domain reference. Disable VDD first to avoid this. |
1329 | * This also avoids spuriously turning the VDD on as |
1330 | * soon as the new power sequencer gets initialized. |
1331 | */ |
1332 | if (force_disable_vdd) { |
1333 | u32 pp = ilk_get_pp_control(intel_dp); |
1334 | |
1335 | drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,({ int __ret = !!(pp & ((u32)((1UL << (0)) + 0))); if (__ret) printf("%s %s: " "Panel power already on\n", dev_driver_string ((&dev_priv->drm)->dev), ""); __builtin_expect(!!(__ret ), 0); }) |
1336 | "Panel power already on\n")({ int __ret = !!(pp & ((u32)((1UL << (0)) + 0))); if (__ret) printf("%s %s: " "Panel power already on\n", dev_driver_string ((&dev_priv->drm)->dev), ""); __builtin_expect(!!(__ret ), 0); }); |
1337 | |
1338 | if (pp & EDP_FORCE_VDD((u32)((1UL << (3)) + 0))) |
1339 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VDD already on, disabling first\n" ) |
1340 | "VDD already on, disabling first\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VDD already on, disabling first\n" ); |
1341 | |
1342 | pp &= ~EDP_FORCE_VDD((u32)((1UL << (3)) + 0)); |
1343 | |
1344 | intel_de_write(dev_priv, regs.pp_ctrl, pp); |
1345 | } |
1346 | |
1347 | pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3)((u32)((((typeof(((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))))(seq->t1_t3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (28 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )) | |
1348 | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8)((u32)((((typeof(((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0))))(seq->t8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (12 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) ); |
1349 | pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9)((u32)((((typeof(((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0))))(seq->t9) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (12) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (12 ) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0) ) | |
1350 | REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10)((u32)((((typeof(((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))))(seq->t10) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (28) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (28 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )); |
1351 | |
1352 | /* Haswell doesn't have any port selection bits for the panel |
1353 | * power sequencer any more. */ |
1354 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
1355 | port_sel = PANEL_PORT_SELECT_VLV(port)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(port) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )); |
1356 | } else if (HAS_PCH_IBX(dev_priv)(((dev_priv)->pch_type) == PCH_IBX) || HAS_PCH_CPT(dev_priv)(((dev_priv)->pch_type) == PCH_CPT)) { |
1357 | switch (port) { |
1358 | case PORT_A: |
1359 | port_sel = PANEL_PORT_SELECT_DPA((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )); |
1360 | break; |
1361 | case PORT_C: |
1362 | port_sel = PANEL_PORT_SELECT_DPC((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )); |
1363 | break; |
1364 | case PORT_D: |
1365 | port_sel = PANEL_PORT_SELECT_DPD((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )); |
1366 | break; |
1367 | default: |
1368 | MISSING_CASE(port)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "port", (long)(port)); __builtin_expect(!!(__ret), 0); }); |
1369 | break; |
1370 | } |
1371 | } |
1372 | |
1373 | pp_on |= port_sel; |
1374 | |
1375 | intel_de_write(dev_priv, regs.pp_on, pp_on); |
1376 | intel_de_write(dev_priv, regs.pp_off, pp_off); |
1377 | |
1378 | /* |
1379 | * Compute the divisor for the pp clock, simply match the Bspec formula. |
1380 | */ |
1381 | if (i915_mmio_reg_valid(regs.pp_div)) { |
1382 | intel_de_write(dev_priv, regs.pp_div, |
1383 | REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1)((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (8))) + 0))))((100 * div) / 2 - 1) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (8))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (8))) + 0)))) + 0 + 0 + 0 + 0)) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))((u32)((((typeof(((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (0))) + 0))))((((seq->t11_t12) + ((1000) - 1)) / (1000))) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0))); |
1384 | } else { |
1385 | u32 pp_ctl; |
1386 | |
1387 | pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl); |
1388 | pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (4))) + 0)); |
1389 | pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))((u32)((((typeof(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (4))) + 0))))((((seq->t11_t12) + ((1000) - 1)) / (1000))) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (4))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL) << (4))) + 0)))) + 0 + 0 + 0 + 0)); |
1390 | intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl); |
1391 | } |
1392 | |
1393 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))) |
1394 | "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))) |
1395 | intel_de_read(dev_priv, regs.pp_on),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))) |
1396 | intel_de_read(dev_priv, regs.pp_off),__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))) |
1397 | i915_mmio_reg_valid(regs.pp_div) ?__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))) |
1398 | intel_de_read(dev_priv, regs.pp_div) :__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))) |
1399 | (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n" , intel_de_read(dev_priv, regs.pp_on), intel_de_read(dev_priv , regs.pp_off), i915_mmio_reg_valid(regs.pp_div) ? intel_de_read (dev_priv, regs.pp_div) : (intel_de_read(dev_priv, regs.pp_ctrl ) & ((u32)((((~0UL) >> (64 - (8) - 1)) & ((~0UL ) << (4))) + 0)))); |
1400 | } |
1401 | |
1402 | void intel_pps_encoder_reset(struct intel_dp *intel_dp) |
1403 | { |
1404 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1405 | intel_wakeref_t wakeref; |
1406 | |
1407 | if (!intel_dp_is_edp(intel_dp)) |
1408 | return; |
1409 | |
1410 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
1411 | /* |
1412 | * Reinit the power sequencer also on the resume path, in case |
1413 | * BIOS did something nasty with it. |
1414 | */ |
1415 | if (IS_VALLEYVIEW(i915)IS_PLATFORM(i915, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(i915)IS_PLATFORM(i915, INTEL_CHERRYVIEW)) |
1416 | vlv_initial_power_sequencer_setup(intel_dp); |
1417 | |
1418 | pps_init_delays(intel_dp); |
1419 | pps_init_registers(intel_dp, false0); |
1420 | pps_vdd_init(intel_dp); |
1421 | |
1422 | if (edp_have_panel_vdd(intel_dp)) |
1423 | edp_panel_vdd_schedule_off(intel_dp); |
1424 | } |
1425 | } |
1426 | |
1427 | void intel_pps_init(struct intel_dp *intel_dp) |
1428 | { |
1429 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1430 | intel_wakeref_t wakeref; |
1431 | |
1432 | intel_dp->pps.initializing = true1; |
1433 | INIT_DELAYED_WORK(&intel_dp->pps.panel_vdd_work, edp_panel_vdd_work); |
1434 | |
1435 | pps_init_timestamps(intel_dp); |
1436 | |
1437 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
1438 | if (IS_VALLEYVIEW(i915)IS_PLATFORM(i915, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(i915)IS_PLATFORM(i915, INTEL_CHERRYVIEW)) |
1439 | vlv_initial_power_sequencer_setup(intel_dp); |
1440 | |
1441 | pps_init_delays(intel_dp); |
1442 | pps_init_registers(intel_dp, false0); |
1443 | pps_vdd_init(intel_dp); |
1444 | } |
1445 | } |
1446 | |
1447 | void intel_pps_init_late(struct intel_dp *intel_dp) |
1448 | { |
1449 | intel_wakeref_t wakeref; |
1450 | |
1451 | with_intel_pps_lock(intel_dp, wakeref)for ((wakeref) = intel_pps_lock(intel_dp); (wakeref); (wakeref ) = intel_pps_unlock((intel_dp), (wakeref))) { |
1452 | /* Reinit delays after per-panel info has been parsed from VBT */ |
1453 | memset(&intel_dp->pps.pps_delays, 0, sizeof(intel_dp->pps.pps_delays))__builtin_memset((&intel_dp->pps.pps_delays), (0), (sizeof (intel_dp->pps.pps_delays))); |
1454 | pps_init_delays(intel_dp); |
1455 | pps_init_registers(intel_dp, false0); |
1456 | |
1457 | intel_dp->pps.initializing = false0; |
1458 | |
1459 | if (edp_have_panel_vdd(intel_dp)) |
1460 | edp_panel_vdd_schedule_off(intel_dp); |
1461 | } |
1462 | } |
1463 | |
1464 | void intel_pps_unlock_regs_wa(struct drm_i915_privateinteldrm_softc *dev_priv) |
1465 | { |
1466 | int pps_num; |
1467 | int pps_idx; |
1468 | |
1469 | if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0) || HAS_DDI(dev_priv)((&(dev_priv)->__info)->display.has_ddi)) |
1470 | return; |
1471 | /* |
1472 | * This w/a is needed at least on CPT/PPT, but to be sure apply it |
1473 | * everywhere where registers can be write protected. |
1474 | */ |
1475 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
1476 | pps_num = 2; |
1477 | else |
1478 | pps_num = 1; |
1479 | |
1480 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { |
1481 | u32 val = intel_de_read(dev_priv, PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (pps_idx) * 0x100) })); |
1482 | |
1483 | val = (val & ~PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) | PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )); |
1484 | intel_de_write(dev_priv, PP_CONTROL(pps_idx)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (pps_idx) * 0x100) }), val); |
1485 | } |
1486 | } |
1487 | |
1488 | void intel_pps_setup(struct drm_i915_privateinteldrm_softc *i915) |
1489 | { |
1490 | if (HAS_PCH_SPLIT(i915)(((i915)->pch_type) != PCH_NONE) || IS_GEMINILAKE(i915)IS_PLATFORM(i915, INTEL_GEMINILAKE) || IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON)) |
1491 | i915->display.pps.mmio_base = PCH_PPS_BASE0xC7200; |
1492 | else if (IS_VALLEYVIEW(i915)IS_PLATFORM(i915, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(i915)IS_PLATFORM(i915, INTEL_CHERRYVIEW)) |
1493 | i915->display.pps.mmio_base = VLV_PPS_BASE(0x180000 + 0x61200); |
1494 | else |
1495 | i915->display.pps.mmio_base = PPS_BASE0x61200; |
1496 | } |
1497 | |
1498 | void assert_pps_unlocked(struct drm_i915_privateinteldrm_softc *dev_priv, enum pipe pipe) |
1499 | { |
1500 | i915_reg_t pp_reg; |
1501 | u32 val; |
1502 | enum pipe panel_pipe = INVALID_PIPE; |
1503 | bool_Bool locked = true1; |
1504 | |
1505 | if (drm_WARN_ON(&dev_priv->drm, HAS_DDI(dev_priv))({ int __ret = !!((((&(dev_priv)->__info)->display. has_ddi))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__info)->display.has_ddi)" ")"); __builtin_expect(!!(__ret), 0); })) |
1506 | return; |
1507 | |
1508 | if (HAS_PCH_SPLIT(dev_priv)(((dev_priv)->pch_type) != PCH_NONE)) { |
1509 | u32 port_sel; |
1510 | |
1511 | pp_reg = PP_CONTROL(0)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (0) * 0x100) }); |
1512 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61208) + (0) * 0x100) })) & PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)); |
1513 | |
1514 | switch (port_sel) { |
1515 | case PANEL_PORT_SELECT_LVDS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
1516 | intel_lvds_port_enabled(dev_priv, PCH_LVDS((const i915_reg_t){ .reg = (0xe1180) }), &panel_pipe); |
1517 | break; |
1518 | case PANEL_PORT_SELECT_DPA((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
1519 | g4x_dp_port_enabled(dev_priv, DP_A((const i915_reg_t){ .reg = (0x64000) }), PORT_A, &panel_pipe); |
1520 | break; |
1521 | case PANEL_PORT_SELECT_DPC((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
1522 | g4x_dp_port_enabled(dev_priv, PCH_DP_C((const i915_reg_t){ .reg = (0xe4200) }), PORT_C, &panel_pipe); |
1523 | break; |
1524 | case PANEL_PORT_SELECT_DPD((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0 )): |
1525 | g4x_dp_port_enabled(dev_priv, PCH_DP_D((const i915_reg_t){ .reg = (0xe4300) }), PORT_D, &panel_pipe); |
1526 | break; |
1527 | default: |
1528 | MISSING_CASE(port_sel)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "port_sel", (long)(port_sel)); __builtin_expect(!!(__ret), 0 ); }); |
1529 | break; |
1530 | } |
1531 | } else if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
1532 | /* presumably write lock depends on pipe, not port select */ |
1533 | pp_reg = PP_CONTROL(pipe)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (pipe) * 0x100) }); |
1534 | panel_pipe = pipe; |
1535 | } else { |
1536 | u32 port_sel; |
1537 | |
1538 | pp_reg = PP_CONTROL(0)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61204) + (0) * 0x100) }); |
1539 | port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)((const i915_reg_t){ .reg = (dev_priv->display.pps.mmio_base - 0x61200 + (0x61208) + (0) * 0x100) })) & PANEL_PORT_SELECT_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)); |
1540 | |
1541 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((port_sel != ((u32)((((typeof(((u32)((((~0UL ) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0 ))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0)))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "port_sel != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); }) |
1542 | port_sel != PANEL_PORT_SELECT_LVDS)({ int __ret = !!((port_sel != ((u32)((((typeof(((u32)((((~0UL ) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0 ))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0)))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "port_sel != ((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))))(0) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (30))) + 0)))) + 0 + 0 + 0 + 0))" ")"); __builtin_expect(!!(__ret), 0); }); |
1543 | intel_lvds_port_enabled(dev_priv, LVDS((const i915_reg_t){ .reg = (0x61180) }), &panel_pipe); |
1544 | } |
1545 | |
1546 | val = intel_de_read(dev_priv, pp_reg); |
1547 | if (!(val & PANEL_POWER_ON((u32)((1UL << (0)) + 0))) || |
1548 | ((val & PANEL_UNLOCK_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) == PANEL_UNLOCK_REGS((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))))(0xabcd) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (16))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (16))) + 0)))) + 0 + 0 + 0 + 0 )))) |
1549 | locked = false0; |
1550 | |
1551 | I915_STATE_WARN(panel_pipe == pipe && locked,({ int __ret_warn_on = !!(panel_pipe == pipe && locked ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A' )); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
1552 | "panel assertion failure, pipe %c regs locked\n",({ int __ret_warn_on = !!(panel_pipe == pipe && locked ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A' )); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }) |
1553 | pipe_name(pipe))({ int __ret_warn_on = !!(panel_pipe == pipe && locked ); if (__builtin_expect(!!(__ret_warn_on), 0)) if (!({ int __ret = !!(i915_modparams.verbose_state_checks); if (__ret) printf ("panel assertion failure, pipe %c regs locked\n", ((pipe) + 'A' )); __builtin_expect(!!(__ret), 0); })) __drm_err("panel assertion failure, pipe %c regs locked\n" , ((pipe) + 'A')); __builtin_expect(!!(__ret_warn_on), 0); }); |
1554 | } |