Bug Summary

File:dev/pci/drm/i915/display/vlv_dsi.c
Warning:line 147, column 2
Value stored to 'data' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name vlv_dsi.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/i915/display/vlv_dsi.c
1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <linux/slab.h>
27
28#include <drm/drm_atomic_helper.h>
29#include <drm/drm_crtc.h>
30#include <drm/drm_edid.h>
31#include <drm/drm_mipi_dsi.h>
32
33#include "i915_drv.h"
34#include "intel_atomic.h"
35#include "intel_backlight.h"
36#include "intel_connector.h"
37#include "intel_crtc.h"
38#include "intel_de.h"
39#include "intel_display_types.h"
40#include "intel_dsi.h"
41#include "intel_dsi_vbt.h"
42#include "intel_fifo_underrun.h"
43#include "intel_panel.h"
44#include "skl_scaler.h"
45#include "vlv_dsi.h"
46#include "vlv_dsi_pll.h"
47#include "vlv_dsi_regs.h"
48#include "vlv_sideband.h"
49
50/* return pixels in terms of txbyteclkhs */
51static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
52 u16 burst_mode_ratio)
53{
54 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,((((((pixels * bpp * burst_mode_ratio) + ((8 * 100) - 1)) / (
8 * 100))) + ((lane_count) - 1)) / (lane_count))
55 8 * 100), lane_count)((((((pixels * bpp * burst_mode_ratio) + ((8 * 100) - 1)) / (
8 * 100))) + ((lane_count) - 1)) / (lane_count));
56}
57
58/* return pixels equvalent to txbyteclkhs */
59static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
60 u16 burst_mode_ratio)
61{
62 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),((((clk_hs * lane_count * 8 * 100)) + (((bpp * burst_mode_ratio
)) - 1)) / ((bpp * burst_mode_ratio)))
63 (bpp * burst_mode_ratio))((((clk_hs * lane_count * 8 * 100)) + (((bpp * burst_mode_ratio
)) - 1)) / ((bpp * burst_mode_ratio)));
64}
65
66enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
67{
68 /* It just so happens the VBT matches register contents. */
69 switch (fmt) {
70 case VID_MODE_FORMAT_RGB888(4 << 7):
71 return MIPI_DSI_FMT_RGB888;
72 case VID_MODE_FORMAT_RGB666(3 << 7):
73 return MIPI_DSI_FMT_RGB666;
74 case VID_MODE_FORMAT_RGB666_PACKED(2 << 7):
75 return MIPI_DSI_FMT_RGB666_PACKED;
76 case VID_MODE_FORMAT_RGB565(1 << 7):
77 return MIPI_DSI_FMT_RGB565;
78 default:
79 MISSING_CASE(fmt)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fmt", (long)(fmt)); __builtin_expect(!!(__ret), 0); });
80 return MIPI_DSI_FMT_RGB666;
81 }
82}
83
84void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
85{
86 struct drm_encoder *encoder = &intel_dsi->base.base;
87 struct drm_device *dev = encoder->dev;
88 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
89 u32 mask;
90
91 mask = LP_CTRL_FIFO_EMPTY(1 << 26) | HS_CTRL_FIFO_EMPTY(1 << 18) |
92 LP_DATA_FIFO_EMPTY(1 << 10) | HS_DATA_FIFO_EMPTY(1 << 2);
93
94 if (intel_de_wait_for_set(dev_priv, MIPI_GEN_FIFO_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb074) : (((dev_priv)->display
.dsi.mmio_base) + 0xb874))) }),
95 mask, 100))
96 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DPI FIFOs are not empty\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
97}
98
99static void write_data(struct drm_i915_privateinteldrm_softc *dev_priv,
100 i915_reg_t reg,
101 const u8 *data, u32 len)
102{
103 u32 i, j;
104
105 for (i = 0; i < len; i += 4) {
106 u32 val = 0;
107
108 for (j = 0; j < min_t(u32, len - i, 4)({ u32 __min_a = (len - i); u32 __min_b = (4); __min_a < __min_b
? __min_a : __min_b; }); j++)
109 val |= *data++ << 8 * j;
110
111 intel_de_write(dev_priv, reg, val);
112 }
113}
114
115static void read_data(struct drm_i915_privateinteldrm_softc *dev_priv,
116 i915_reg_t reg,
117 u8 *data, u32 len)
118{
119 u32 i, j;
120
121 for (i = 0; i < len; i += 4) {
122 u32 val = intel_de_read(dev_priv, reg);
123
124 for (j = 0; j < min_t(u32, len - i, 4)({ u32 __min_a = (len - i); u32 __min_b = (4); __min_a < __min_b
? __min_a : __min_b; }); j++)
125 *data++ = val >> 8 * j;
126 }
127}
128
129static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
130 const struct mipi_dsi_msg *msg)
131{
132 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
133 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
134 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
135 enum port port = intel_dsi_host->port;
136 struct mipi_dsi_packet packet;
137 ssize_t ret;
138 const u8 *header, *data;
139 i915_reg_t data_reg, ctrl_reg;
140 u32 data_mask, ctrl_mask;
141
142 ret = mipi_dsi_create_packet(&packet, msg);
143 if (ret < 0)
144 return ret;
145
146 header = packet.header;
147 data = packet.payload;
Value stored to 'data' is never read
148
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM(1 << 0)) {
150 data_reg = MIPI_LP_GEN_DATA(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb064) : (((dev_priv)->display
.dsi.mmio_base) + 0xb864))) });
151 data_mask = LP_DATA_FIFO_FULL(1 << 8);
152 ctrl_reg = MIPI_LP_GEN_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb06c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb86c))) });
153 ctrl_mask = LP_CTRL_FIFO_FULL(1 << 24);
154 } else {
155 data_reg = MIPI_HS_GEN_DATA(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb068) : (((dev_priv)->display
.dsi.mmio_base) + 0xb868))) });
156 data_mask = HS_DATA_FIFO_FULL(1 << 0);
157 ctrl_reg = MIPI_HS_GEN_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb070) : (((dev_priv)->display
.dsi.mmio_base) + 0xb870))) });
158 ctrl_mask = HS_CTRL_FIFO_FULL(1 << 16);
159 }
160
161 /* note: this is never true for reads */
162 if (packet.payload_length) {
163 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb074) : (((dev_priv)->display
.dsi.mmio_base) + 0xb874))) }),
164 data_mask, 50))
165 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for HS/LP DATA FIFO !full\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
166 "Timeout waiting for HS/LP DATA FIFO !full\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for HS/LP DATA FIFO !full\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
167
168 write_data(dev_priv, data_reg, packet.payload,
169 packet.payload_length);
170 }
171
172 if (msg->rx_len) {
173 intel_de_write(dev_priv, MIPI_INTR_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb004) : (((dev_priv)->display
.dsi.mmio_base) + 0xb804))) }),
174 GEN_READ_DATA_AVAIL(1 << 29));
175 }
176
177 if (intel_de_wait_for_clear(dev_priv, MIPI_GEN_FIFO_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb074) : (((dev_priv)->display
.dsi.mmio_base) + 0xb874))) }),
178 ctrl_mask, 50)) {
179 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for HS/LP CTRL FIFO !full\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
180 "Timeout waiting for HS/LP CTRL FIFO !full\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for HS/LP CTRL FIFO !full\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
181 }
182
183 intel_de_write(dev_priv, ctrl_reg,
184 header[2] << 16 | header[1] << 8 | header[0]);
185
186 /* ->rx_len is set only for reads */
187 if (msg->rx_len) {
188 data_mask = GEN_READ_DATA_AVAIL(1 << 29);
189 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb004) : (((dev_priv)->display
.dsi.mmio_base) + 0xb804))) }),
190 data_mask, 50))
191 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for read data.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
192 "Timeout waiting for read data.\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for read data.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
193
194 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
195 }
196
197 /* XXX: fix for reads and writes */
198 return 4 + packet.payload_length;
199}
200
201static int intel_dsi_host_attach(struct mipi_dsi_host *host,
202 struct mipi_dsi_device *dsi)
203{
204 return 0;
205}
206
207static int intel_dsi_host_detach(struct mipi_dsi_host *host,
208 struct mipi_dsi_device *dsi)
209{
210 return 0;
211}
212
213static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
214 .attach = intel_dsi_host_attach,
215 .detach = intel_dsi_host_detach,
216 .transfer = intel_dsi_host_transfer,
217};
218
219/*
220 * send a video mode command
221 *
222 * XXX: commands with data in MIPI_DPI_DATA?
223 */
224static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool_Bool hs,
225 enum port port)
226{
227 struct drm_encoder *encoder = &intel_dsi->base.base;
228 struct drm_device *dev = encoder->dev;
229 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
230 u32 mask;
231
232 /* XXX: pipe, hs */
233 if (hs)
234 cmd &= ~DPI_LP_MODE(1 << 6);
235 else
236 cmd |= DPI_LP_MODE(1 << 6);
237
238 /* clear bit */
239 intel_de_write(dev_priv, MIPI_INTR_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb004) : (((dev_priv)->display
.dsi.mmio_base) + 0xb804))) }), SPL_PKT_SENT_INTERRUPT(1 << 30));
240
241 /* XXX: old code skips write if control unchanged */
242 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb048) : (((dev_priv)->display
.dsi.mmio_base) + 0xb848))) })))
243 drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Same special packet %02x twice in a row.\n"
, cmd)
244 "Same special packet %02x twice in a row.\n", cmd)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Same special packet %02x twice in a row.\n"
, cmd);
245
246 intel_de_write(dev_priv, MIPI_DPI_CONTROL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb048) : (((dev_priv)->display
.dsi.mmio_base) + 0xb848))) }), cmd);
247
248 mask = SPL_PKT_SENT_INTERRUPT(1 << 30);
249 if (intel_de_wait_for_set(dev_priv, MIPI_INTR_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb004) : (((dev_priv)->display
.dsi.mmio_base) + 0xb804))) }), mask, 100))
250 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Video mode command 0x%08x send failed.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , cmd)
251 "Video mode command 0x%08x send failed.\n", cmd)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Video mode command 0x%08x send failed.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , cmd);
252
253 return 0;
254}
255
256static void band_gap_reset(struct drm_i915_privateinteldrm_softc *dev_priv)
257{
258 vlv_flisdsi_get(dev_priv);
259
260 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
261 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
262 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
263 udelay(150);
264 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
265 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
266
267 vlv_flisdsi_put(dev_priv);
268}
269
270static int intel_dsi_compute_config(struct intel_encoder *encoder,
271 struct intel_crtc_state *pipe_config,
272 struct drm_connector_state *conn_state)
273{
274 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
275 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,({ const __typeof( ((struct intel_dsi *)0)->base ) *__mptr
= (encoder); (struct intel_dsi *)( (char *)__mptr - __builtin_offsetof
(struct intel_dsi, base) );})
276 base)({ const __typeof( ((struct intel_dsi *)0)->base ) *__mptr
= (encoder); (struct intel_dsi *)( (char *)__mptr - __builtin_offsetof
(struct intel_dsi, base) );});
277 struct intel_connector *intel_connector = intel_dsi->attached_connector;
278 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
279 int ret;
280
281 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
282 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
283
284 ret = intel_panel_compute_config(intel_connector, adjusted_mode);
285 if (ret)
286 return ret;
287
288 ret = intel_panel_fitting(pipe_config, conn_state);
289 if (ret)
290 return ret;
291
292 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5))
293 return -EINVAL22;
294
295 /* DSI uses short packets for sync events, so clear mode flags for DSI */
296 adjusted_mode->flags = 0;
297
298 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
299 pipe_config->pipe_bpp = 24;
300 else
301 pipe_config->pipe_bpp = 18;
302
303 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
304 /* Enable Frame time stamp based scanline reporting */
305 pipe_config->mode_flags |=
306 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP(1<<1);
307
308 /* Dual link goes to DSI transcoder A. */
309 if (intel_dsi->ports == BIT(PORT_C)(1UL << (PORT_C)))
310 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
311 else
312 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
313
314 ret = bxt_dsi_pll_compute(encoder, pipe_config);
315 if (ret)
316 return -EINVAL22;
317 } else {
318 ret = vlv_dsi_pll_compute(encoder, pipe_config);
319 if (ret)
320 return -EINVAL22;
321 }
322
323 pipe_config->clock_set = true1;
324
325 return 0;
326}
327
328static bool_Bool glk_dsi_enable_io(struct intel_encoder *encoder)
329{
330 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
332 enum port port;
333 u32 tmp;
334 bool_Bool cold_boot = false0;
335
336 /* Set the MIPI mode
337 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
338 * Power ON MIPI IO first and then write into IO reset and LP wake bits
339 */
340 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
341 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
342 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
343 tmp | GLK_MIPIIO_ENABLE(1 << 0));
344 }
345
346 /* Put the IO into reset */
347 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
348 tmp &= ~GLK_MIPIIO_RESET_RELEASED(1 << 28);
349 intel_de_write(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }), tmp);
350
351 /* Program LP Wake */
352 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
353 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
354 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) })) & DEVICE_READY(1 << 0)))
355 tmp &= ~GLK_LP_WAKE(1 << 22);
356 else
357 tmp |= GLK_LP_WAKE(1 << 22);
358 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }), tmp);
359 }
360
361 /* Wait for Pwr ACK */
362 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
363 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
364 GLK_MIPIIO_PORT_POWERED(1 << 1), 20))
365 drm_err(&dev_priv->drm, "MIPIO port is powergated\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "MIPIO port is powergated\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
366 }
367
368 /* Check for cold boot scenario */
369 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
370 cold_boot |=
371 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) })) & DEVICE_READY(1 << 0));
372 }
373
374 return cold_boot;
375}
376
377static void glk_dsi_device_ready(struct intel_encoder *encoder)
378{
379 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
380 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
381 enum port port;
382 u32 val;
383
384 /* Wait for MIPI PHY status bit to set */
385 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
386 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
387 GLK_PHY_STATUS_PORT_READY(1 << 31), 20))
388 drm_err(&dev_priv->drm, "PHY is not ON\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PHY is not ON\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
389 }
390
391 /* Get IO out of reset */
392 val = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
393 intel_de_write(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
394 val | GLK_MIPIIO_RESET_RELEASED(1 << 28));
395
396 /* Get IO out of Low power state*/
397 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
398 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) })) & DEVICE_READY(1 << 0))) {
399 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }));
400 val &= ~ULPS_STATE_MASK(3 << 1);
401 val |= DEVICE_READY(1 << 0);
402 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
403 usleep_range(10, 15);
404 } else {
405 /* Enter ULPS */
406 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }));
407 val &= ~ULPS_STATE_MASK(3 << 1);
408 val |= (ULPS_STATE_ENTER(2 << 1) | DEVICE_READY(1 << 0));
409 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
410
411 /* Wait for ULPS active */
412 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
413 GLK_ULPS_NOT_ACTIVE(1 << 30), 20))
414 drm_err(&dev_priv->drm, "ULPS not active\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "ULPS not active\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
415
416 /* Exit ULPS */
417 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }));
418 val &= ~ULPS_STATE_MASK(3 << 1);
419 val |= (ULPS_STATE_EXIT(1 << 1) | DEVICE_READY(1 << 0));
420 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
421
422 /* Enter Normal Mode */
423 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }));
424 val &= ~ULPS_STATE_MASK(3 << 1);
425 val |= (ULPS_STATE_NORMAL_OPERATION(0 << 1) | DEVICE_READY(1 << 0));
426 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
427
428 val = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
429 val &= ~GLK_LP_WAKE(1 << 22);
430 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }), val);
431 }
432 }
433
434 /* Wait for Stop state */
435 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
436 if (intel_de_wait_for_set(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
437 GLK_DATA_LANE_STOP_STATE(1 << 26), 20))
438 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Date lane not in STOP state\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
439 "Date lane not in STOP state\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Date lane not in STOP state\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
440 }
441
442 /* Wait for AFE LATCH */
443 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
444 if (intel_de_wait_for_set(dev_priv, BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }),
445 AFE_LATCHOUT(1 << 17), 20))
446 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "D-PHY not entering LP-11 state\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
447 "D-PHY not entering LP-11 state\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "D-PHY not entering LP-11 state\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
448 }
449}
450
451static void bxt_dsi_device_ready(struct intel_encoder *encoder)
452{
453 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
454 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
455 enum port port;
456 u32 val;
457
458 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
459
460 /* Enable MIPI PHY transparent latch */
461 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
462 val = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }));
463 intel_de_write(dev_priv, BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }),
464 val | LP_OUTPUT_HOLD(1 << 16));
465 usleep_range(2000, 2500);
466 }
467
468 /* Clear ULPS and set device ready */
469 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
470 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }));
471 val &= ~ULPS_STATE_MASK(3 << 1);
472 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
473 usleep_range(2000, 2500);
474 val |= DEVICE_READY(1 << 0);
475 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
476 }
477}
478
479static void vlv_dsi_device_ready(struct intel_encoder *encoder)
480{
481 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
482 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
483 enum port port;
484 u32 val;
485
486 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
487
488 vlv_flisdsi_get(dev_priv);
489 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
490 * needed everytime after power gate */
491 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
492 vlv_flisdsi_put(dev_priv);
493
494 /* bandgap reset is needed after everytime we do power gate */
495 band_gap_reset(dev_priv);
496
497 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
498
499 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }),
500 ULPS_STATE_ENTER(2 << 1));
501 usleep_range(2500, 3000);
502
503 /* Enable MIPI PHY transparent latch
504 * Common bit for both MIPI Port A & MIPI Port C
505 * No similar bit in MIPI Port C reg
506 */
507 val = intel_de_read(dev_priv, MIPI_PORT_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (0x180000
+ 0x61190) : (0x180000 + 0x61700))) }));
508 intel_de_write(dev_priv, MIPI_PORT_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (0x180000
+ 0x61190) : (0x180000 + 0x61700))) }),
509 val | LP_OUTPUT_HOLD(1 << 16));
510 usleep_range(1000, 1500);
511
512 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }),
513 ULPS_STATE_EXIT(1 << 1));
514 usleep_range(2500, 3000);
515
516 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }),
517 DEVICE_READY(1 << 0));
518 usleep_range(2500, 3000);
519 }
520}
521
522static void intel_dsi_device_ready(struct intel_encoder *encoder)
523{
524 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
525
526 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))
527 glk_dsi_device_ready(encoder);
528 else if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
529 bxt_dsi_device_ready(encoder);
530 else
531 vlv_dsi_device_ready(encoder);
532}
533
534static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
535{
536 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
537 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
538 enum port port;
539 u32 val;
540
541 /* Enter ULPS */
542 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
543 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }));
544 val &= ~ULPS_STATE_MASK(3 << 1);
545 val |= (ULPS_STATE_ENTER(2 << 1) | DEVICE_READY(1 << 0));
546 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), val);
547 }
548
549 /* Wait for MIPI PHY status bit to unset */
550 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
551 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
552 GLK_PHY_STATUS_PORT_READY(1 << 31), 20))
553 drm_err(&dev_priv->drm, "PHY is not turning OFF\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PHY is not turning OFF\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
554 }
555
556 /* Wait for Pwr ACK bit to unset */
557 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
558 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
559 GLK_MIPIIO_PORT_POWERED(1 << 1), 20))
560 drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "MIPI IO Port is not powergated\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__)
561 "MIPI IO Port is not powergated\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "MIPI IO Port is not powergated\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
562 }
563}
564
565static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
566{
567 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
568 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
569 enum port port;
570 u32 tmp;
571
572 /* Put the IO into reset */
573 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
574 tmp &= ~GLK_MIPIIO_RESET_RELEASED(1 << 28);
575 intel_de_write(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }), tmp);
576
577 /* Wait for MIPI PHY status bit to unset */
578 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
579 if (intel_de_wait_for_clear(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
580 GLK_PHY_STATUS_PORT_READY(1 << 31), 20))
581 drm_err(&dev_priv->drm, "PHY is not turning OFF\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "PHY is not turning OFF\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
582 }
583
584 /* Clear MIPI mode */
585 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
586 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
587 tmp &= ~GLK_MIPIIO_ENABLE(1 << 0);
588 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }), tmp);
589 }
590}
591
592static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
593{
594 glk_dsi_enter_low_power_mode(encoder);
595 glk_dsi_disable_mipi_io(encoder);
596}
597
598static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
599{
600 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
601 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
602 enum port port;
603
604 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
605 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
606 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
607 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) ?
608 BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }) : MIPI_PORT_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (0x180000
+ 0x61190) : (0x180000 + 0x61700))) });
609 u32 val;
610
611 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }),
612 DEVICE_READY(1 << 0) | ULPS_STATE_ENTER(2 << 1));
613 usleep_range(2000, 2500);
614
615 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }),
616 DEVICE_READY(1 << 0) | ULPS_STATE_EXIT(1 << 1));
617 usleep_range(2000, 2500);
618
619 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }),
620 DEVICE_READY(1 << 0) | ULPS_STATE_ENTER(2 << 1));
621 usleep_range(2000, 2500);
622
623 /*
624 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
625 * Port A only. MIPI Port C has no similar bit for checking.
626 */
627 if ((IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) || port == PORT_A) &&
628 intel_de_wait_for_clear(dev_priv, port_ctrl,
629 AFE_LATCHOUT(1 << 17), 30))
630 drm_err(&dev_priv->drm, "DSI LP not going Low\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "DSI LP not going Low\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__);
631
632 /* Disable MIPI PHY transparent latch */
633 val = intel_de_read(dev_priv, port_ctrl);
634 intel_de_write(dev_priv, port_ctrl, val & ~LP_OUTPUT_HOLD(1 << 16));
635 usleep_range(1000, 1500);
636
637 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), 0x00);
638 usleep_range(2000, 2500);
639 }
640}
641
642static void intel_dsi_port_enable(struct intel_encoder *encoder,
643 const struct intel_crtc_state *crtc_state)
644{
645 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
646 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
647 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
648 enum port port;
649
650 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1) {
651 u32 temp;
652 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
653 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
654 temp = intel_de_read(dev_priv,
655 MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
656 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK(0xf << 10) |
657 intel_dsi->pixel_overlap <<
658 BXT_PIXEL_OVERLAP_CNT_SHIFT10;
659 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
660 temp);
661 }
662 } else {
663 temp = intel_de_read(dev_priv, VLV_CHICKEN_3((const i915_reg_t){ .reg = (0x180000 + 0x7040C) }));
664 temp &= ~PIXEL_OVERLAP_CNT_MASK(3 << 30) |
665 intel_dsi->pixel_overlap <<
666 PIXEL_OVERLAP_CNT_SHIFT30;
667 intel_de_write(dev_priv, VLV_CHICKEN_3((const i915_reg_t){ .reg = (0x180000 + 0x7040C) }), temp);
668 }
669 }
670
671 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
672 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) ?
673 BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }) : MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61190) : (0x180000 + 0x61700))) });
674 u32 temp;
675
676 temp = intel_de_read(dev_priv, port_ctrl);
677
678 temp &= ~LANE_CONFIGURATION_MASK(3 << 0);
679 temp &= ~DUAL_LINK_MODE_MASK(1 << 26);
680
681 if (intel_dsi->ports == (BIT(PORT_A)(1UL << (PORT_A)) | BIT(PORT_C)(1UL << (PORT_C)))) {
682 temp |= (intel_dsi->dual_link - 1)
683 << DUAL_LINK_MODE_SHIFT26;
684 if (IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
685 temp |= LANE_CONFIGURATION_DUAL_LINK_A(1 << 0);
686 else
687 temp |= crtc->pipe ?
688 LANE_CONFIGURATION_DUAL_LINK_B(2 << 0) :
689 LANE_CONFIGURATION_DUAL_LINK_A(1 << 0);
690 }
691
692 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888)
693 temp |= DITHERING_ENABLE(1 << 25);
694
695 /* assert ip_tg_enable signal */
696 intel_de_write(dev_priv, port_ctrl, temp | DPI_ENABLE(1 << 31));
697 intel_de_posting_read(dev_priv, port_ctrl);
698 }
699}
700
701static void intel_dsi_port_disable(struct intel_encoder *encoder)
702{
703 struct drm_device *dev = encoder->base.dev;
704 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
705 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
706 enum port port;
707
708 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
709 i915_reg_t port_ctrl = IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) ?
710 BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }) : MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61190) : (0x180000 + 0x61700))) });
711 u32 temp;
712
713 /* de-assert ip_tg_enable signal */
714 temp = intel_de_read(dev_priv, port_ctrl);
715 intel_de_write(dev_priv, port_ctrl, temp & ~DPI_ENABLE(1 << 31));
716 intel_de_posting_read(dev_priv, port_ctrl);
717 }
718}
719
720static void intel_dsi_wait_panel_power_cycle(struct intel_dsi *intel_dsi)
721{
722 ktime_t panel_power_on_time;
723 s64 panel_power_off_duration;
724
725 panel_power_on_time = ktime_get_boottime();
726 panel_power_off_duration = ktime_ms_delta(panel_power_on_time,
727 intel_dsi->panel_power_off_time);
728
729 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay)
730 drm_msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration)mdelay(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration
);
731}
732
733static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
734 const struct intel_crtc_state *pipe_config);
735static void intel_dsi_unprepare(struct intel_encoder *encoder);
736
737/*
738 * Panel enable/disable sequences from the VBT spec.
739 *
740 * Note the spec has AssertReset / DeassertReset swapped from their
741 * usual naming. We use the normal names to avoid confusion (so below
742 * they are swapped compared to the spec).
743 *
744 * Steps starting with MIPI refer to VBT sequences, note that for v2
745 * VBTs several steps which have a VBT in v2 are expected to be handled
746 * directly by the driver, by directly driving gpios for example.
747 *
748 * v2 video mode seq v3 video mode seq command mode seq
749 * - power on - MIPIPanelPowerOn - power on
750 * - wait t1+t2 - wait t1+t2
751 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
752 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
753 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
754 * - MIPITearOn
755 * - MIPIDisplayOn
756 * - turn on DPI - turn on DPI - set pipe to dsr mode
757 * - MIPIDisplayOn - MIPIDisplayOn
758 * - wait t5 - wait t5
759 * - backlight on - MIPIBacklightOn - backlight on
760 * ... ... ... issue mem cmds ...
761 * - backlight off - MIPIBacklightOff - backlight off
762 * - wait t6 - wait t6
763 * - MIPIDisplayOff
764 * - turn off DPI - turn off DPI - disable pipe dsr mode
765 * - MIPITearOff
766 * - MIPIDisplayOff - MIPIDisplayOff
767 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
768 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
769 * - wait t3 - wait t3
770 * - power off - MIPIPanelPowerOff - power off
771 * - wait t4 - wait t4
772 */
773
774/*
775 * DSI port enable has to be done before pipe and plane enable, so we do it in
776 * the pre_enable hook instead of the enable hook.
777 */
778static void intel_dsi_pre_enable(struct intel_atomic_state *state,
779 struct intel_encoder *encoder,
780 const struct intel_crtc_state *pipe_config,
781 const struct drm_connector_state *conn_state)
782{
783 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
784 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (pipe_config->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
785 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
786 enum pipe pipe = crtc->pipe;
787 enum port port;
788 u32 val;
789 bool_Bool glk_cold_boot = false0;
790
791 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
792
793 intel_dsi_wait_panel_power_cycle(intel_dsi);
794
795 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true1);
796
797 /*
798 * The BIOS may leave the PLL in a wonky state where it doesn't
799 * lock. It needs to be fully powered down to fix it.
800 */
801 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
802 bxt_dsi_pll_disable(encoder);
803 bxt_dsi_pll_enable(encoder, pipe_config);
804 } else {
805 vlv_dsi_pll_disable(encoder);
806 vlv_dsi_pll_enable(encoder, pipe_config);
807 }
808
809 if (IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
810 /* Add MIPI IO reset programming for modeset */
811 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }));
812 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }),
813 val | MIPIO_RST_CTRL(1 << 2));
814
815 /* Power up DSI regulator */
816 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG((const i915_reg_t){ .reg = (0x160020) }), STAP_SELECT(1 << 0));
817 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL((const i915_reg_t){ .reg = (0x160054) }), 0);
818 }
819
820 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) {
821 u32 val;
822
823 /* Disable DPOunit clock gating, can stall pipe */
824 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display.mmio_offset) + 0x6200) }));
825 val |= DPOUNIT_CLOCK_GATE_DISABLE(1 << 11);
826 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display.mmio_offset) + 0x6200) }), val);
827 }
828
829 if (!IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))
830 intel_dsi_prepare(encoder, pipe_config);
831
832 /* Give the panel time to power-on and then deassert its reset */
833 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
834 drm_msleep(intel_dsi->panel_on_delay)mdelay(intel_dsi->panel_on_delay);
835 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
836
837 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
838 glk_cold_boot = glk_dsi_enable_io(encoder);
839
840 /* Prepare port in cold boot(s3/s4) scenario */
841 if (glk_cold_boot)
842 intel_dsi_prepare(encoder, pipe_config);
843 }
844
845 /* Put device in ready state (LP-11) */
846 intel_dsi_device_ready(encoder);
847
848 /* Prepare port in normal boot scenario */
849 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) && !glk_cold_boot)
850 intel_dsi_prepare(encoder, pipe_config);
851
852 /* Send initialization commands in LP mode */
853 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
854
855 /*
856 * Enable port in pre-enable phase itself because as per hw team
857 * recommendation, port should be enabled before plane & pipe
858 */
859 if (is_cmd_mode(intel_dsi)) {
860 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else
861 intel_de_write(dev_priv,
862 MIPI_MAX_RETURN_PKT_SIZE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb054) : (((dev_priv)->display
.dsi.mmio_base) + 0xb854))) }), 8 * 4);
863 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
864 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
865 } else {
866 drm_msleep(20)mdelay(20); /* XXX */
867 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else
868 dpi_send_cmd(intel_dsi, TURN_ON(1 << 1), false0, port);
869 drm_msleep(100)mdelay(100);
870
871 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
872
873 intel_dsi_port_enable(encoder, pipe_config);
874 }
875
876 intel_backlight_enable(pipe_config, conn_state);
877 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
878}
879
880static void bxt_dsi_enable(struct intel_atomic_state *state,
881 struct intel_encoder *encoder,
882 const struct intel_crtc_state *crtc_state,
883 const struct drm_connector_state *conn_state)
884{
885 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder)({ int __ret = !!((crtc_state->has_pch_encoder)); if (__ret
) printf("%s %s: " "%s", dev_driver_string(((state->base.dev
))->dev), "", "drm_WARN_ON(" "crtc_state->has_pch_encoder"
")"); __builtin_expect(!!(__ret), 0); });
886
887 intel_crtc_vblank_on(crtc_state);
888}
889
890/*
891 * DSI port disable has to be done after pipe and plane disable, so we do it in
892 * the post_disable hook.
893 */
894static void intel_dsi_disable(struct intel_atomic_state *state,
895 struct intel_encoder *encoder,
896 const struct intel_crtc_state *old_crtc_state,
897 const struct drm_connector_state *old_conn_state)
898{
899 struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev);
900 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
901 enum port port;
902
903 drm_dbg_kms(&i915->drm, "\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915->
drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
904
905 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
906 intel_backlight_disable(old_conn_state);
907
908 /*
909 * According to the spec we should send SHUTDOWN before
910 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
911 * has shown that the v3 sequence works for v2 VBTs too
912 */
913 if (is_vid_mode(intel_dsi)) {
914 /* Send Shutdown command to the panel in LP mode */
915 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else
916 dpi_send_cmd(intel_dsi, SHUTDOWN(1 << 0), false0, port);
917 drm_msleep(10)mdelay(10);
918 }
919}
920
921static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
922{
923 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
924
925 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))
926 glk_dsi_clear_device_ready(encoder);
927 else
928 vlv_dsi_clear_device_ready(encoder);
929}
930
931static void intel_dsi_post_disable(struct intel_atomic_state *state,
932 struct intel_encoder *encoder,
933 const struct intel_crtc_state *old_crtc_state,
934 const struct drm_connector_state *old_conn_state)
935{
936 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
937 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
938 enum port port;
939 u32 val;
940
941 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
942
943 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
944 intel_crtc_vblank_off(old_crtc_state);
945
946 skl_scaler_disable(old_crtc_state);
947 }
948
949 if (is_vid_mode(intel_dsi)) {
950 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else
951 vlv_dsi_wait_for_fifo_empty(intel_dsi, port);
952
953 intel_dsi_port_disable(encoder);
954 usleep_range(2000, 5000);
955 }
956
957 intel_dsi_unprepare(encoder);
958
959 /*
960 * if disable packets are sent before sending shutdown packet then in
961 * some next enable sequence send turn on packet error is observed
962 */
963 if (is_cmd_mode(intel_dsi))
964 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
965 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
966
967 /* Transition to LP-00 */
968 intel_dsi_clear_device_ready(encoder);
969
970 if (IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
971 /* Power down DSI regulator to save power */
972 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_CFG((const i915_reg_t){ .reg = (0x160020) }), STAP_SELECT(1 << 0));
973 intel_de_write(dev_priv, BXT_P_DSI_REGULATOR_TX_CTRL((const i915_reg_t){ .reg = (0x160054) }),
974 HS_IO_CTRL_SELECT(1 << 0));
975
976 /* Add MIPI IO reset programming for modeset */
977 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }));
978 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON((const i915_reg_t){ .reg = (0x138090) }),
979 val & ~MIPIO_RST_CTRL(1 << 2));
980 }
981
982 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
983 bxt_dsi_pll_disable(encoder);
984 } else {
985 u32 val;
986
987 vlv_dsi_pll_disable(encoder);
988
989 val = intel_de_read(dev_priv, DSPCLK_GATE_D(dev_priv)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display.mmio_offset) + 0x6200) }));
990 val &= ~DPOUNIT_CLOCK_GATE_DISABLE(1 << 11);
991 intel_de_write(dev_priv, DSPCLK_GATE_D(dev_priv)((const i915_reg_t){ .reg = (((&(dev_priv)->__info)->
display.mmio_offset) + 0x6200) }), val);
992 }
993
994 /* Assert reset */
995 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
996
997 drm_msleep(intel_dsi->panel_off_delay)mdelay(intel_dsi->panel_off_delay);
998 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
999
1000 intel_dsi->panel_power_off_time = ktime_get_boottime();
1001}
1002
1003static void intel_dsi_shutdown(struct intel_encoder *encoder)
1004{
1005 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1006
1007 intel_dsi_wait_panel_power_cycle(intel_dsi);
1008}
1009
1010static bool_Bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1011 enum pipe *pipe)
1012{
1013 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1014 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1015 intel_wakeref_t wakeref;
1016 enum port port;
1017 bool_Bool active = false0;
1018
1019 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
1020
1021 wakeref = intel_display_power_get_if_enabled(dev_priv,
1022 encoder->power_domain);
1023 if (!wakeref)
1024 return false0;
1025
1026 /*
1027 * On Broxton the PLL needs to be enabled with a valid divider
1028 * configuration, otherwise accessing DSI registers will hang the
1029 * machine. See BSpec North Display Engine registers/MIPI[BXT].
1030 */
1031 if ((IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) &&
1032 !bxt_dsi_pll_is_enabled(dev_priv))
1033 goto out_put_power;
1034
1035 /* XXX: this only works for one DSI output */
1036 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1037 i915_reg_t ctrl_reg = IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) ?
1038 BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) }) : MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (0x180000 +
0x61190) : (0x180000 + 0x61700))) });
1039 bool_Bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE(1 << 31);
1040
1041 /*
1042 * Due to some hardware limitations on VLV/CHV, the DPI enable
1043 * bit in port C control register does not get set. As a
1044 * workaround, check pipe B conf instead.
1045 */
1046 if ((IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) &&
1047 port == PORT_C)
1048 enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.pipe_offsets[(PIPE_B)] - (&(dev_priv)->__info)
->display.pipe_offsets[PIPE_A] + ((&(dev_priv)->__info
)->display.mmio_offset) + (0x70008)) })) & PIPECONF_ENABLE((u32)((1UL << (31)) + 0));
1049
1050 /* Try command mode if video mode not enabled */
1051 if (!enabled) {
1052 u32 tmp = intel_de_read(dev_priv,
1053 MIPI_DSI_FUNC_PRG(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb00c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb80c))) }));
1054 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK(7 << 13);
1055 }
1056
1057 if (!enabled)
1058 continue;
1059
1060 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) })) & DEVICE_READY(1 << 0)))
1061 continue;
1062
1063 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
1064 u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
1065 tmp &= BXT_PIPE_SELECT_MASK(7 << 7);
1066 tmp >>= BXT_PIPE_SELECT_SHIFT7;
1067
1068 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)({ int __ret = !!((tmp > PIPE_C)); if (__ret) printf("%s %s: "
"%s", dev_driver_string(((&dev_priv->drm))->dev), ""
, "drm_WARN_ON(" "tmp > PIPE_C" ")"); __builtin_expect(!!(
__ret), 0); }))
1069 continue;
1070
1071 *pipe = tmp;
1072 } else {
1073 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1074 }
1075
1076 active = true1;
1077 break;
1078 }
1079
1080out_put_power:
1081 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1082
1083 return active;
1084}
1085
1086static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1087 struct intel_crtc_state *pipe_config)
1088{
1089 struct drm_device *dev = encoder->base.dev;
1090 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1091 struct drm_display_mode *adjusted_mode =
1092 &pipe_config->hw.adjusted_mode;
1093 struct drm_display_mode *adjusted_mode_sw;
1094 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (pipe_config->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
1095 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1096 unsigned int lane_count = intel_dsi->lane_count;
1097 unsigned int bpp, fmt;
1098 enum port port;
1099 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1100 u16 hfp_sw, hsync_sw, hbp_sw;
1101 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1102 crtc_hblank_start_sw, crtc_hblank_end_sw;
1103
1104 /* FIXME: hw readout should not depend on SW state */
1105 adjusted_mode_sw = &crtc->config->hw.adjusted_mode;
1106
1107 /*
1108 * Atleast one port is active as encoder->get_config called only if
1109 * encoder->get_hw_state() returns true.
1110 */
1111 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1112 if (intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0C0 : 0x6B8C0
)) })) & DPI_ENABLE(1 << 31))
1113 break;
1114 }
1115
1116 fmt = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb00c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb80c))) })) & VID_MODE_FORMAT_MASK(0xf << 7);
1117 bpp = mipi_dsi_pixel_format_to_bpp(
1118 pixel_format_from_register_bits(fmt));
1119
1120 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
1121
1122 /* Enable Frame time stamo based scanline reporting */
1123 pipe_config->mode_flags |=
1124 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP(1<<1);
1125
1126 /* In terms of pixels */
1127 adjusted_mode->crtc_hdisplay =
1128 intel_de_read(dev_priv,
1129 BXT_MIPI_TRANS_HACTIVE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0F8 : 0x6B8F8
)) }));
1130 adjusted_mode->crtc_vdisplay =
1131 intel_de_read(dev_priv,
1132 BXT_MIPI_TRANS_VACTIVE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0FC : 0x6B8FC
)) }));
1133 adjusted_mode->crtc_vtotal =
1134 intel_de_read(dev_priv,
1135 BXT_MIPI_TRANS_VTOTAL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B100 : 0x6B900
)) }));
1136
1137 hactive = adjusted_mode->crtc_hdisplay;
1138 hfp = intel_de_read(dev_priv, MIPI_HFP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb030) : (((dev_priv)->display
.dsi.mmio_base) + 0xb830))) }));
1139
1140 /*
1141 * Meaningful for video mode non-burst sync pulse mode only,
1142 * can be zero for non-burst sync events and burst modes
1143 */
1144 hsync = intel_de_read(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb028) : (((dev_priv)->display
.dsi.mmio_base) + 0xb828))) }));
1145 hbp = intel_de_read(dev_priv, MIPI_HBP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb02c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb82c))) }));
1146
1147 /* harizontal values are in terms of high speed byte clock */
1148 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1149 intel_dsi->burst_mode_ratio);
1150 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1151 intel_dsi->burst_mode_ratio);
1152 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1153 intel_dsi->burst_mode_ratio);
1154
1155 if (intel_dsi->dual_link) {
1156 hfp *= 2;
1157 hsync *= 2;
1158 hbp *= 2;
1159 }
1160
1161 /* vertical values are in terms of lines */
1162 vfp = intel_de_read(dev_priv, MIPI_VFP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb040) : (((dev_priv)->display
.dsi.mmio_base) + 0xb840))) }));
1163 vsync = intel_de_read(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb038) : (((dev_priv)->display
.dsi.mmio_base) + 0xb838))) }));
1164 vbp = intel_de_read(dev_priv, MIPI_VBP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb03c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb83c))) }));
1165
1166 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1167 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1168 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1169 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1170 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1171
1172 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1173 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1174 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1175 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1176
1177 /*
1178 * In BXT DSI there is no regs programmed with few horizontal timings
1179 * in Pixels but txbyteclkhs.. So retrieval process adds some
1180 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1181 * Actually here for the given adjusted_mode, we are calculating the
1182 * value programmed to the port and then back to the horizontal timing
1183 * param in pixels. This is the expected value, including roundup errors
1184 * And if that is same as retrieved value from port, then
1185 * (HW state) adjusted_mode's horizontal timings are corrected to
1186 * match with SW state to nullify the errors.
1187 */
1188 /* Calculating the value programmed to the Port register */
1189 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1190 adjusted_mode_sw->crtc_hdisplay;
1191 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1192 adjusted_mode_sw->crtc_hsync_start;
1193 hbp_sw = adjusted_mode_sw->crtc_htotal -
1194 adjusted_mode_sw->crtc_hsync_end;
1195
1196 if (intel_dsi->dual_link) {
1197 hfp_sw /= 2;
1198 hsync_sw /= 2;
1199 hbp_sw /= 2;
1200 }
1201
1202 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1203 intel_dsi->burst_mode_ratio);
1204 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1205 intel_dsi->burst_mode_ratio);
1206 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1207 intel_dsi->burst_mode_ratio);
1208
1209 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1210 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1211 intel_dsi->burst_mode_ratio);
1212 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1213 intel_dsi->burst_mode_ratio);
1214 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1215 intel_dsi->burst_mode_ratio);
1216
1217 if (intel_dsi->dual_link) {
1218 hfp_sw *= 2;
1219 hsync_sw *= 2;
1220 hbp_sw *= 2;
1221 }
1222
1223 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1224 hsync_sw + hbp_sw;
1225 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1226 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1227 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1228 crtc_hblank_end_sw = crtc_htotal_sw;
1229
1230 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1231 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1232
1233 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1234 adjusted_mode->crtc_hsync_start =
1235 adjusted_mode_sw->crtc_hsync_start;
1236
1237 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1238 adjusted_mode->crtc_hsync_end =
1239 adjusted_mode_sw->crtc_hsync_end;
1240
1241 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1242 adjusted_mode->crtc_hblank_start =
1243 adjusted_mode_sw->crtc_hblank_start;
1244
1245 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1246 adjusted_mode->crtc_hblank_end =
1247 adjusted_mode_sw->crtc_hblank_end;
1248}
1249
1250static void intel_dsi_get_config(struct intel_encoder *encoder,
1251 struct intel_crtc_state *pipe_config)
1252{
1253 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1254 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1255 u32 pclk;
1256
1257 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
1258
1259 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI)(1UL << (INTEL_OUTPUT_DSI));
1260
1261 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
1262 bxt_dsi_get_pipe_config(encoder, pipe_config);
1263 pclk = bxt_dsi_get_pclk(encoder, pipe_config);
1264 } else {
1265 pclk = vlv_dsi_get_pclk(encoder, pipe_config);
1266 }
1267
1268 pipe_config->port_clock = pclk;
1269
1270 /* FIXME definitely not right for burst/cmd mode/pixel overlap */
1271 pipe_config->hw.adjusted_mode.crtc_clock = pclk;
1272 if (intel_dsi->dual_link)
1273 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1274}
1275
1276/* return txclkesc cycles in terms of divider and duration in us */
1277static u16 txclkesc(u32 divider, unsigned int us)
1278{
1279 switch (divider) {
1280 case ESCAPE_CLOCK_DIVIDER_1(0 << 5):
1281 default:
1282 return 20 * us;
1283 case ESCAPE_CLOCK_DIVIDER_2(1 << 5):
1284 return 10 * us;
1285 case ESCAPE_CLOCK_DIVIDER_4(2 << 5):
1286 return 5 * us;
1287 }
1288}
1289
1290static void set_dsi_timings(struct drm_encoder *encoder,
1291 const struct drm_display_mode *adjusted_mode)
1292{
1293 struct drm_device *dev = encoder->dev;
1294 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1295 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr
= (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof
(struct intel_encoder, base) );}));
1296 enum port port;
1297 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1298 unsigned int lane_count = intel_dsi->lane_count;
1299
1300 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1301
1302 hactive = adjusted_mode->crtc_hdisplay;
1303 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1304 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1305 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1306
1307 if (intel_dsi->dual_link) {
1308 hactive /= 2;
1309 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1)
1310 hactive += intel_dsi->pixel_overlap;
1311 hfp /= 2;
1312 hsync /= 2;
1313 hbp /= 2;
1314 }
1315
1316 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1317 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1318 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1319
1320 /* horizontal values are in terms of high speed byte clock */
1321 hactive = txbyteclkhs(hactive, bpp, lane_count,
1322 intel_dsi->burst_mode_ratio);
1323 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1324 hsync = txbyteclkhs(hsync, bpp, lane_count,
1325 intel_dsi->burst_mode_ratio);
1326 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1327
1328 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1329 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
1330 /*
1331 * Program hdisplay and vdisplay on MIPI transcoder.
1332 * This is different from calculated hactive and
1333 * vactive, as they are calculated per channel basis,
1334 * whereas these values should be based on resolution.
1335 */
1336 intel_de_write(dev_priv, BXT_MIPI_TRANS_HACTIVE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0F8 : 0x6B8F8
)) }),
1337 adjusted_mode->crtc_hdisplay);
1338 intel_de_write(dev_priv, BXT_MIPI_TRANS_VACTIVE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B0FC : 0x6B8FC
)) }),
1339 adjusted_mode->crtc_vdisplay);
1340 intel_de_write(dev_priv, BXT_MIPI_TRANS_VTOTAL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? 0x6B100 : 0x6B900
)) }),
1341 adjusted_mode->crtc_vtotal);
1342 }
1343
1344 intel_de_write(dev_priv, MIPI_HACTIVE_AREA_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb034) : (((dev_priv)->display
.dsi.mmio_base) + 0xb834))) }),
1345 hactive);
1346 intel_de_write(dev_priv, MIPI_HFP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb030) : (((dev_priv)->display
.dsi.mmio_base) + 0xb830))) }), hfp);
1347
1348 /* meaningful for video mode non-burst sync pulse mode only,
1349 * can be zero for non-burst sync events and burst modes */
1350 intel_de_write(dev_priv, MIPI_HSYNC_PADDING_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb028) : (((dev_priv)->display
.dsi.mmio_base) + 0xb828))) }),
1351 hsync);
1352 intel_de_write(dev_priv, MIPI_HBP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb02c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb82c))) }), hbp);
1353
1354 /* vertical values are in terms of lines */
1355 intel_de_write(dev_priv, MIPI_VFP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb040) : (((dev_priv)->display
.dsi.mmio_base) + 0xb840))) }), vfp);
1356 intel_de_write(dev_priv, MIPI_VSYNC_PADDING_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb038) : (((dev_priv)->display
.dsi.mmio_base) + 0xb838))) }),
1357 vsync);
1358 intel_de_write(dev_priv, MIPI_VBP_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb03c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb83c))) }), vbp);
1359 }
1360}
1361
1362static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1363{
1364 switch (fmt) {
1365 case MIPI_DSI_FMT_RGB888:
1366 return VID_MODE_FORMAT_RGB888(4 << 7);
1367 case MIPI_DSI_FMT_RGB666:
1368 return VID_MODE_FORMAT_RGB666(3 << 7);
1369 case MIPI_DSI_FMT_RGB666_PACKED:
1370 return VID_MODE_FORMAT_RGB666_PACKED(2 << 7);
1371 case MIPI_DSI_FMT_RGB565:
1372 return VID_MODE_FORMAT_RGB565(1 << 7);
1373 default:
1374 MISSING_CASE(fmt)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "fmt", (long)(fmt)); __builtin_expect(!!(__ret), 0); });
1375 return VID_MODE_FORMAT_RGB666(3 << 7);
1376 }
1377}
1378
1379static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1380 const struct intel_crtc_state *pipe_config)
1381{
1382 struct drm_encoder *encoder = &intel_encoder->base;
1383 struct drm_device *dev = encoder->dev;
1384 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1385 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (pipe_config->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
1386 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr
= (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof
(struct intel_encoder, base) );}));
1387 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1388 enum port port;
1389 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1390 u32 val, tmp;
1391 u16 mode_hdisplay;
1392
1393 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "pipe %c\n", ((crtc
->pipe) + 'A'));
1394
1395 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1396
1397 if (intel_dsi->dual_link) {
1398 mode_hdisplay /= 2;
1399 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK1)
1400 mode_hdisplay += intel_dsi->pixel_overlap;
1401 }
1402
1403 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1404 if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) {
1405 /*
1406 * escape clock divider, 20MHz, shared for A and C.
1407 * device ready must be off when doing this! txclkesc?
1408 */
1409 tmp = intel_de_read(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
1410 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK(3 << 5);
1411 intel_de_write(dev_priv, MIPI_CTRL(PORT_A)((const i915_reg_t){ .reg = ((((PORT_A) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
1412 tmp | ESCAPE_CLOCK_DIVIDER_1(0 << 5));
1413
1414 /* read request priority is per pipe */
1415 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
1416 tmp &= ~READ_REQUEST_PRIORITY_MASK(3 << 3);
1417 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }),
1418 tmp | READ_REQUEST_PRIORITY_HIGH(3 << 3));
1419 } else if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
1420 enum pipe pipe = crtc->pipe;
1421
1422 tmp = intel_de_read(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }));
1423 tmp &= ~BXT_PIPE_SELECT_MASK(7 << 7);
1424
1425 tmp |= BXT_PIPE_SELECT(pipe)((pipe) << 7);
1426 intel_de_write(dev_priv, MIPI_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb104) : (((dev_priv)->display
.dsi.mmio_base) + 0xb904))) }), tmp);
1427 }
1428
1429 /* XXX: why here, why like this? handling in irq handler?! */
1430 intel_de_write(dev_priv, MIPI_INTR_STAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb004) : (((dev_priv)->display
.dsi.mmio_base) + 0xb804))) }), 0xffffffff);
1431 intel_de_write(dev_priv, MIPI_INTR_EN(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb008) : (((dev_priv)->display
.dsi.mmio_base) + 0xb808))) }), 0xffffffff);
1432
1433 intel_de_write(dev_priv, MIPI_DPHY_PARAM(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb080) : (((dev_priv)->display
.dsi.mmio_base) + 0xb880))) }),
1434 intel_dsi->dphy_reg);
1435
1436 intel_de_write(dev_priv, MIPI_DPI_RESOLUTION(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb020) : (((dev_priv)->display
.dsi.mmio_base) + 0xb820))) }),
1437 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT16 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT0);
1438 }
1439
1440 set_dsi_timings(encoder, adjusted_mode);
1441
1442 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT0;
1443 if (is_cmd_mode(intel_dsi)) {
1444 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT5;
1445 val |= CMD_MODE_DATA_WIDTH_8_BIT(3 << 13); /* XXX */
1446 } else {
1447 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT3;
1448 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1449 }
1450
1451 tmp = 0;
1452 if (intel_dsi->eotp_pkt == 0)
1453 tmp |= EOT_DISABLE(1 << 0);
1454 if (intel_dsi->clock_stop)
1455 tmp |= CLOCKSTOP(1 << 1);
1456
1457 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) {
1458 tmp |= BXT_DPHY_DEFEATURE_EN(1 << 8);
1459 if (!is_cmd_mode(intel_dsi))
1460 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR(1 << 9);
1461 }
1462
1463 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1464 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb00c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb80c))) }), val);
1465
1466 /* timeouts for recovery. one frame IIUC. if counter expires,
1467 * EOT and stop state. */
1468
1469 /*
1470 * In burst mode, value greater than one DPI line Time in byte
1471 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1472 * said value is recommended.
1473 *
1474 * In non-burst mode, Value greater than one DPI frame time in
1475 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1476 * said value is recommended.
1477 *
1478 * In DBI only mode, value greater than one DBI frame time in
1479 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1480 * said value is recommended.
1481 */
1482
1483 if (is_vid_mode(intel_dsi) &&
1484 intel_dsi->video_mode == BURST_MODE0x3) {
1485 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb010) : (((dev_priv)->display
.dsi.mmio_base) + 0xb810))) }),
1486 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1487 } else {
1488 intel_de_write(dev_priv, MIPI_HS_TX_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb010) : (((dev_priv)->display
.dsi.mmio_base) + 0xb810))) }),
1489 txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
1490 }
1491 intel_de_write(dev_priv, MIPI_LP_RX_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb014) : (((dev_priv)->display
.dsi.mmio_base) + 0xb814))) }),
1492 intel_dsi->lp_rx_timeout);
1493 intel_de_write(dev_priv, MIPI_TURN_AROUND_TIMEOUT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb018) : (((dev_priv)->display
.dsi.mmio_base) + 0xb818))) }),
1494 intel_dsi->turn_arnd_val);
1495 intel_de_write(dev_priv, MIPI_DEVICE_RESET_TIMER(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb01c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb81c))) }),
1496 intel_dsi->rst_timer_val);
1497
1498 /* dphy stuff */
1499
1500 /* in terms of low power clock */
1501 intel_de_write(dev_priv, MIPI_INIT_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb050) : (((dev_priv)->display
.dsi.mmio_base) + 0xb850))) }),
1502 txclkesc(intel_dsi->escape_clk_div, 100));
1503
1504 if ((IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) &&
1505 !intel_dsi->dual_link) {
1506 /*
1507 * BXT spec says write MIPI_INIT_COUNT for
1508 * both the ports, even if only one is
1509 * getting used. So write the other port
1510 * if not in dual link mode.
1511 */
1512 intel_de_write(dev_priv,
1513 MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A)((const i915_reg_t){ .reg = ((((port == PORT_A ? PORT_C : PORT_A
) == PORT_A) ? (((dev_priv)->display.dsi.mmio_base) + 0xb050
) : (((dev_priv)->display.dsi.mmio_base) + 0xb850))) }),
1514 intel_dsi->init_count);
1515 }
1516
1517 /* recovery disables */
1518 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb05c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb85c))) }), tmp);
1519
1520 /* in terms of low power clock */
1521 intel_de_write(dev_priv, MIPI_INIT_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb050) : (((dev_priv)->display
.dsi.mmio_base) + 0xb850))) }),
1522 intel_dsi->init_count);
1523
1524 /* in terms of txbyteclkhs. actual high to low switch +
1525 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1526 *
1527 * XXX: write MIPI_STOP_STATE_STALL?
1528 */
1529 intel_de_write(dev_priv, MIPI_HIGH_LOW_SWITCH_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb044) : (((dev_priv)->display
.dsi.mmio_base) + 0xb844))) }),
1530 intel_dsi->hs_to_lp_count);
1531
1532 /* XXX: low power clock equivalence in terms of byte clock.
1533 * the number of byte clocks occupied in one low power clock.
1534 * based on txbyteclkhs and txclkesc.
1535 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1536 * ) / 105.???
1537 */
1538 intel_de_write(dev_priv, MIPI_LP_BYTECLK(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb060) : (((dev_priv)->display
.dsi.mmio_base) + 0xb860))) }),
1539 intel_dsi->lp_byte_clk);
1540
1541 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)) {
1542 intel_de_write(dev_priv, MIPI_TLPX_TIME_COUNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb0a4) : (((dev_priv)->display
.dsi.mmio_base) + 0xb8a4))) }),
1543 intel_dsi->lp_byte_clk);
1544 /* Shadow of DPHY reg */
1545 intel_de_write(dev_priv, MIPI_CLK_LANE_TIMING(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb098) : (((dev_priv)->display
.dsi.mmio_base) + 0xb898))) }),
1546 intel_dsi->dphy_reg);
1547 }
1548
1549 /* the bw essential for transmitting 16 long packets containing
1550 * 252 bytes meant for dcs write memory command is programmed in
1551 * this register in terms of byte clocks. based on dsi transfer
1552 * rate and the number of lanes configured the time taken to
1553 * transmit 16 long packets in a dsi stream varies. */
1554 intel_de_write(dev_priv, MIPI_DBI_BW_CTRL(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb084) : (((dev_priv)->display
.dsi.mmio_base) + 0xb884))) }),
1555 intel_dsi->bw_timer);
1556
1557 intel_de_write(dev_priv, MIPI_CLK_LANE_SWITCH_TIME_CNT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb088) : (((dev_priv)->display
.dsi.mmio_base) + 0xb888))) }),
1558 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT16 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT0);
1559
1560 if (is_vid_mode(intel_dsi)) {
1561 u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG(1 << 2);
1562
1563 /*
1564 * Some panels might have resolution which is not a
1565 * multiple of 64 like 1366 x 768. Enable RANDOM
1566 * resolution support for such panels by default.
1567 */
1568 fmt |= RANDOM_DPI_DISPLAY_RESOLUTION(1 << 4);
1569
1570 switch (intel_dsi->video_mode) {
1571 default:
1572 MISSING_CASE(intel_dsi->video_mode)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n"
, "intel_dsi->video_mode", (long)(intel_dsi->video_mode
)); __builtin_expect(!!(__ret), 0); });
1573 fallthroughdo {} while (0);
1574 case NON_BURST_SYNC_EVENTS0x2:
1575 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS(2 << 0);
1576 break;
1577 case NON_BURST_SYNC_PULSE0x1:
1578 fmt |= VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE(1 << 0);
1579 break;
1580 case BURST_MODE0x3:
1581 fmt |= VIDEO_MODE_BURST(3 << 0);
1582 break;
1583 }
1584
1585 intel_de_write(dev_priv, MIPI_VIDEO_MODE_FORMAT(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb058) : (((dev_priv)->display
.dsi.mmio_base) + 0xb858))) }), fmt);
1586 }
1587 }
1588}
1589
1590static void intel_dsi_unprepare(struct intel_encoder *encoder)
1591{
1592 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
1593 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1594 enum port port;
1595 u32 val;
1596
1597 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE))
1598 return;
1599
1600 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1601 /* Panel commands can be sent when clock is in LP11 */
1602 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), 0x0);
1603
1604 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
1605 bxt_dsi_reset_clocks(encoder, port);
1606 else
1607 vlv_dsi_reset_clocks(encoder, port);
1608 intel_de_write(dev_priv, MIPI_EOT_DISABLE(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb05c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb85c))) }), CLOCKSTOP(1 << 1));
1609
1610 val = intel_de_read(dev_priv, MIPI_DSI_FUNC_PRG(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb00c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb80c))) }));
1611 val &= ~VID_MODE_FORMAT_MASK(0xf << 7);
1612 intel_de_write(dev_priv, MIPI_DSI_FUNC_PRG(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb00c) : (((dev_priv)->display
.dsi.mmio_base) + 0xb80c))) }), val);
1613
1614 intel_de_write(dev_priv, MIPI_DEVICE_READY(port)((const i915_reg_t){ .reg = ((((port) == PORT_A) ? (((dev_priv
)->display.dsi.mmio_base) + 0xb000) : (((dev_priv)->display
.dsi.mmio_base) + 0xb800))) }), 0x1);
1615 }
1616}
1617
1618static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1619{
1620 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr
= (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof
(struct intel_encoder, base) );}));
1621
1622 intel_dsi_vbt_gpio_cleanup(intel_dsi);
1623 intel_encoder_destroy(encoder);
1624}
1625
1626static const struct drm_encoder_funcs intel_dsi_funcs = {
1627 .destroy = intel_dsi_encoder_destroy,
1628};
1629
1630static enum drm_mode_status vlv_dsi_mode_valid(struct drm_connector *connector,
1631 struct drm_display_mode *mode)
1632{
1633 struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->dev);
1634
1635 if (IS_VALLEYVIEW(i915)IS_PLATFORM(i915, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(i915)IS_PLATFORM(i915, INTEL_CHERRYVIEW)) {
1636 enum drm_mode_status status;
1637
1638 status = intel_cpu_transcoder_mode_valid(i915, mode);
1639 if (status != MODE_OK)
1640 return status;
1641 }
1642
1643 return intel_dsi_mode_valid(connector, mode);
1644}
1645
1646static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1647 .get_modes = intel_dsi_get_modes,
1648 .mode_valid = vlv_dsi_mode_valid,
1649 .atomic_check = intel_digital_connector_atomic_check,
1650};
1651
1652static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1653 .detect = intel_panel_detect,
1654 .late_register = intel_connector_register,
1655 .early_unregister = intel_connector_unregister,
1656 .destroy = intel_connector_destroy,
1657 .fill_modes = drm_helper_probe_single_connector_modes,
1658 .atomic_get_property = intel_digital_connector_atomic_get_property,
1659 .atomic_set_property = intel_digital_connector_atomic_set_property,
1660 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1661 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1662};
1663
1664static void vlv_dsi_add_properties(struct intel_connector *connector)
1665{
1666 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(connector->base.dev);
1667 const struct drm_display_mode *fixed_mode =
1668 intel_panel_preferred_fixed_mode(connector);
1669 u32 allowed_scalers;
1670
1671 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT)(1UL << (3)) | BIT(DRM_MODE_SCALE_FULLSCREEN)(1UL << (1));
1672 if (!HAS_GMCH(dev_priv)((&(dev_priv)->__info)->display.has_gmch))
1673 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER)(1UL << (2));
1674
1675 drm_connector_attach_scaling_mode_property(&connector->base,
1676 allowed_scalers);
1677
1678 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT3;
1679
1680 drm_connector_set_panel_orientation_with_quirk(&connector->base,
1681 intel_dsi_get_panel_orientation(connector),
1682 fixed_mode->hdisplay,
1683 fixed_mode->vdisplay);
1684}
1685
1686#define NS_KHZ_RATIO1000000 1000000
1687
1688#define PREPARE_CNT_MAX0x3F 0x3F
1689#define EXIT_ZERO_CNT_MAX0x3F 0x3F
1690#define CLK_ZERO_CNT_MAX0xFF 0xFF
1691#define TRAIL_CNT_MAX0x1F 0x1F
1692
1693static void vlv_dphy_param_init(struct intel_dsi *intel_dsi)
1694{
1695 struct drm_device *dev = intel_dsi->base.base.dev;
1696 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev);
1697 struct intel_connector *connector = intel_dsi->attached_connector;
1698 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1699 u32 tlpx_ns, extra_byte_count, tlpx_ui;
1700 u32 ui_num, ui_den;
1701 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1702 u32 ths_prepare_ns, tclk_trail_ns;
1703 u32 tclk_prepare_clkzero, ths_prepare_hszero;
1704 u32 lp_to_hs_switch, hs_to_lp_switch;
1705 u32 mul;
1706
1707 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1708
1709 switch (intel_dsi->lane_count) {
1710 case 1:
1711 case 2:
1712 extra_byte_count = 2;
1713 break;
1714 case 3:
1715 extra_byte_count = 4;
1716 break;
1717 case 4:
1718 default:
1719 extra_byte_count = 3;
1720 break;
1721 }
1722
1723 /* in Kbps */
1724 ui_num = NS_KHZ_RATIO1000000;
1725 ui_den = intel_dsi_bitrate(intel_dsi);
1726
1727 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero;
1728 ths_prepare_hszero = mipi_config->ths_prepare_hszero;
1729
1730 /*
1731 * B060
1732 * LP byte clock = TLPX/ (8UI)
1733 */
1734 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num)(((tlpx_ns * ui_den) + ((8 * ui_num) - 1)) / (8 * ui_num));
1735
1736 /* DDR clock period = 2 * UI
1737 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
1738 * UI(nsec) = 10^6 / bitrate
1739 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
1740 * DDR clock count = ns_value / DDR clock period
1741 *
1742 * For GEMINILAKE dphy_param_reg will be programmed in terms of
1743 * HS byte clock count for other platform in HS ddr clock count
1744 */
1745 mul = IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) ? 8 : 2;
1746 ths_prepare_ns = max(mipi_config->ths_prepare,(((mipi_config->ths_prepare)>(mipi_config->tclk_prepare
))?(mipi_config->ths_prepare):(mipi_config->tclk_prepare
))
1747 mipi_config->tclk_prepare)(((mipi_config->ths_prepare)>(mipi_config->tclk_prepare
))?(mipi_config->ths_prepare):(mipi_config->tclk_prepare
));
1748
1749 /* prepare count */
1750 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * mul)(((ths_prepare_ns * ui_den) + ((ui_num * mul) - 1)) / (ui_num
* mul));
1751
1752 if (prepare_cnt > PREPARE_CNT_MAX0x3F) {
1753 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "prepare count too high %u\n"
, prepare_cnt)
1754 prepare_cnt)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "prepare count too high %u\n"
, prepare_cnt);
1755 prepare_cnt = PREPARE_CNT_MAX0x3F;
1756 }
1757
1758 /* exit zero count */
1759 exit_zero_cnt = DIV_ROUND_UP(((((ths_prepare_hszero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul))
1760 (ths_prepare_hszero - ths_prepare_ns) * ui_den,((((ths_prepare_hszero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul))
1761 ui_num * mul((((ths_prepare_hszero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul))
1762 )((((ths_prepare_hszero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul));
1763
1764 /*
1765 * Exit zero is unified val ths_zero and ths_exit
1766 * minimum value for ths_exit = 110ns
1767 * min (exit_zero_cnt * 2) = 110/UI
1768 * exit_zero_cnt = 55/UI
1769 */
1770 if (exit_zero_cnt < (55 * ui_den / ui_num) && (55 * ui_den) % ui_num)
1771 exit_zero_cnt += 1;
1772
1773 if (exit_zero_cnt > EXIT_ZERO_CNT_MAX0x3F) {
1774 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "exit zero count too high %u\n"
, exit_zero_cnt)
1775 exit_zero_cnt)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "exit zero count too high %u\n"
, exit_zero_cnt);
1776 exit_zero_cnt = EXIT_ZERO_CNT_MAX0x3F;
1777 }
1778
1779 /* clk zero count */
1780 clk_zero_cnt = DIV_ROUND_UP(((((tclk_prepare_clkzero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul))
1781 (tclk_prepare_clkzero - ths_prepare_ns)((((tclk_prepare_clkzero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul))
1782 * ui_den, ui_num * mul)((((tclk_prepare_clkzero - ths_prepare_ns) * ui_den) + ((ui_num
* mul) - 1)) / (ui_num * mul));
1783
1784 if (clk_zero_cnt > CLK_ZERO_CNT_MAX0xFF) {
1785 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "clock zero count too high %u\n"
, clk_zero_cnt)
1786 clk_zero_cnt)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "clock zero count too high %u\n"
, clk_zero_cnt);
1787 clk_zero_cnt = CLK_ZERO_CNT_MAX0xFF;
1788 }
1789
1790 /* trail count */
1791 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail)(((mipi_config->tclk_trail)>(mipi_config->ths_trail)
)?(mipi_config->tclk_trail):(mipi_config->ths_trail));
1792 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, ui_num * mul)(((tclk_trail_ns * ui_den) + ((ui_num * mul) - 1)) / (ui_num *
mul));
1793
1794 if (trail_cnt > TRAIL_CNT_MAX0x1F) {
1795 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "trail count too high %u\n"
, trail_cnt)
1796 trail_cnt)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "trail count too high %u\n"
, trail_cnt);
1797 trail_cnt = TRAIL_CNT_MAX0x1F;
1798 }
1799
1800 /* B080 */
1801 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 |
1802 clk_zero_cnt << 8 | prepare_cnt;
1803
1804 /*
1805 * LP to HS switch count = 4TLPX + PREP_COUNT * mul + EXIT_ZERO_COUNT *
1806 * mul + 10UI + Extra Byte Count
1807 *
1808 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count
1809 * Extra Byte Count is calculated according to number of lanes.
1810 * High Low Switch Count is the Max of LP to HS and
1811 * HS to LP switch count
1812 *
1813 */
1814 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num)(((tlpx_ns * ui_den) + ((ui_num) - 1)) / (ui_num));
1815
1816 /* B044 */
1817 /* FIXME:
1818 * The comment above does not match with the code */
1819 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * mul +(((4 * tlpx_ui + prepare_cnt * mul + exit_zero_cnt * mul + 10
) + ((8) - 1)) / (8))
1820 exit_zero_cnt * mul + 10, 8)(((4 * tlpx_ui + prepare_cnt * mul + exit_zero_cnt * mul + 10
) + ((8) - 1)) / (8));
1821
1822 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8)(((mipi_config->ths_trail + 2 * tlpx_ui) + ((8) - 1)) / (8
));
1823
1824 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch)(((lp_to_hs_switch)>(hs_to_lp_switch))?(lp_to_hs_switch):(
hs_to_lp_switch));
1825 intel_dsi->hs_to_lp_count += extra_byte_count;
1826
1827 /* B088 */
1828 /* LP -> HS for clock lanes
1829 * LP clk sync + LP11 + LP01 + tclk_prepare + tclk_zero +
1830 * extra byte count
1831 * 2TPLX + 1TLPX + 1 TPLX(in ns) + prepare_cnt * 2 + clk_zero_cnt *
1832 * 2(in UI) + extra byte count
1833 * In byteclks = (4TLPX + prepare_cnt * 2 + clk_zero_cnt *2 (in UI)) /
1834 * 8 + extra byte count
1835 */
1836 intel_dsi->clk_lp_to_hs_count =
1837 DIV_ROUND_UP((((4 * tlpx_ui + prepare_cnt * 2 + clk_zero_cnt * 2) + ((8) -
1)) / (8))
1838 4 * tlpx_ui + prepare_cnt * 2 +(((4 * tlpx_ui + prepare_cnt * 2 + clk_zero_cnt * 2) + ((8) -
1)) / (8))
1839 clk_zero_cnt * 2,(((4 * tlpx_ui + prepare_cnt * 2 + clk_zero_cnt * 2) + ((8) -
1)) / (8))
1840 8)(((4 * tlpx_ui + prepare_cnt * 2 + clk_zero_cnt * 2) + ((8) -
1)) / (8));
1841
1842 intel_dsi->clk_lp_to_hs_count += extra_byte_count;
1843
1844 /* HS->LP for Clock Lanes
1845 * Low Power clock synchronisations + 1Tx byteclk + tclk_trail +
1846 * Extra byte count
1847 * 2TLPX + 8UI + (trail_count*2)(in UI) + Extra byte count
1848 * In byteclks = (2*TLpx(in UI) + trail_count*2 +8)(in UI)/8 +
1849 * Extra byte count
1850 */
1851 intel_dsi->clk_hs_to_lp_count =
1852 DIV_ROUND_UP(2 * tlpx_ui + trail_cnt * 2 + 8,(((2 * tlpx_ui + trail_cnt * 2 + 8) + ((8) - 1)) / (8))
1853 8)(((2 * tlpx_ui + trail_cnt * 2 + 8) + ((8) - 1)) / (8));
1854 intel_dsi->clk_hs_to_lp_count += extra_byte_count;
1855
1856 intel_dsi_log_params(intel_dsi);
1857}
1858
1859void vlv_dsi_init(struct drm_i915_privateinteldrm_softc *dev_priv)
1860{
1861 struct drm_device *dev = &dev_priv->drm;
1862 struct intel_dsi *intel_dsi;
1863 struct intel_encoder *intel_encoder;
1864 struct drm_encoder *encoder;
1865 struct intel_connector *intel_connector;
1866 struct drm_connector *connector;
1867 struct drm_display_mode *current_mode;
1868 enum port port;
1869 enum pipe pipe;
1870
1871 drm_dbg_kms(&dev_priv->drm, "\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "\n");
1872
1873 /* There is no detection method for MIPI so rely on VBT */
1874 if (!intel_bios_is_dsi_present(dev_priv, &port))
1875 return;
1876
1877 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
1878 dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE0x60000;
1879 else
1880 dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE0x180000;
1881
1882 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL(0x0001 | 0x0004));
1883 if (!intel_dsi)
1884 return;
1885
1886 intel_connector = intel_connector_alloc();
1887 if (!intel_connector) {
1888 kfree(intel_dsi);
1889 return;
1890 }
1891
1892 intel_encoder = &intel_dsi->base;
1893 encoder = &intel_encoder->base;
1894 intel_dsi->attached_connector = intel_connector;
1895
1896 connector = &intel_connector->base;
1897
1898 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI6,
1899 "DSI %c", port_name(port)((port) + 'A'));
1900
1901 intel_encoder->compute_config = intel_dsi_compute_config;
1902 intel_encoder->pre_enable = intel_dsi_pre_enable;
1903 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
1904 intel_encoder->enable = bxt_dsi_enable;
1905 intel_encoder->disable = intel_dsi_disable;
1906 intel_encoder->post_disable = intel_dsi_post_disable;
1907 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1908 intel_encoder->get_config = intel_dsi_get_config;
1909 intel_encoder->update_pipe = intel_backlight_update;
1910 intel_encoder->shutdown = intel_dsi_shutdown;
1911
1912 intel_connector->get_hw_state = intel_connector_get_hw_state;
1913
1914 intel_encoder->port = port;
1915 intel_encoder->type = INTEL_OUTPUT_DSI;
1916 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1917 intel_encoder->cloneable = 0;
1918
1919 /*
1920 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1921 * port C. BXT isn't limited like this.
1922 */
1923 if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))
1924 intel_encoder->pipe_mask = ~0;
1925 else if (port == PORT_A)
1926 intel_encoder->pipe_mask = BIT(PIPE_A)(1UL << (PIPE_A));
1927 else
1928 intel_encoder->pipe_mask = BIT(PIPE_B)(1UL << (PIPE_B));
1929
1930 intel_dsi->panel_power_off_time = ktime_get_boottime();
1931
1932 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, NULL((void *)0), NULL((void *)0));
1933
1934 if (intel_connector->panel.vbt.dsi.config->dual_link)
1935 intel_dsi->ports = BIT(PORT_A)(1UL << (PORT_A)) | BIT(PORT_C)(1UL << (PORT_C));
1936 else
1937 intel_dsi->ports = BIT(port)(1UL << (port));
1938
1939 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)({ int __ret = !!((intel_connector->panel.vbt.dsi.bl_ports
& ~intel_dsi->ports)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
"intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports"
")"); __builtin_expect(!!(__ret), 0); }))
1940 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1941
1942 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)({ int __ret = !!((intel_connector->panel.vbt.dsi.cabc_ports
& ~intel_dsi->ports)); if (__ret) printf("%s %s: " "%s"
, dev_driver_string(((&dev_priv->drm))->dev), "", "drm_WARN_ON("
"intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports"
")"); __builtin_expect(!!(__ret), 0); }))
1943 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1944
1945 /* Create a DSI host (and a device) for each port. */
1946 for_each_dsi_port(port, intel_dsi->ports)for ((port) = PORT_A; (port) < I915_MAX_PORTS; (port)++) if
(!((intel_dsi->ports) & (1UL << (port)))) {} else {
1947 struct intel_dsi_host *host;
1948
1949 host = intel_dsi_host_init(intel_dsi, &intel_dsi_host_ops,
1950 port);
1951 if (!host)
1952 goto err;
1953
1954 intel_dsi->dsi_hosts[port] = host;
1955 }
1956
1957 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID1)) {
1958 drm_dbg_kms(&dev_priv->drm, "no device found\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "no device found\n"
);
1959 goto err;
1960 }
1961
1962 /* Use clock read-back from current hw-state for fastboot */
1963 current_mode = intel_encoder_current_mode(intel_encoder);
1964 if (current_mode) {
1965 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Calculated pclk %d GOP %d\n"
, intel_dsi->pclk, current_mode->clock)
1966 intel_dsi->pclk, current_mode->clock)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Calculated pclk %d GOP %d\n"
, intel_dsi->pclk, current_mode->clock);
1967 if (intel_fuzzy_clock_check(intel_dsi->pclk,
1968 current_mode->clock)) {
1969 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "Using GOP pclk\n"
);
1970 intel_dsi->pclk = current_mode->clock;
1971 }
1972
1973 kfree(current_mode);
1974 }
1975
1976 vlv_dphy_param_init(intel_dsi);
1977
1978 intel_dsi_vbt_gpio_init(intel_dsi,
1979 intel_dsi_get_hw_state(intel_encoder, &pipe));
1980
1981 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1982 DRM_MODE_CONNECTOR_DSI16);
1983
1984 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1985
1986 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1987 connector->interlace_allowed = false0;
1988 connector->doublescan_allowed = false0;
1989
1990 intel_connector_attach_encoder(intel_connector, intel_encoder);
1991
1992 mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex);
1993 intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1994 mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex);
1995
1996 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1997 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv
->drm)->dev : ((void *)0), DRM_UT_KMS, "no fixed mode\n"
);
1998 goto err_cleanup_connector;
1999 }
2000
2001 intel_panel_init(intel_connector);
2002
2003 intel_backlight_setup(intel_connector, INVALID_PIPE);
2004
2005 vlv_dsi_add_properties(intel_connector);
2006
2007 return;
2008
2009err_cleanup_connector:
2010 drm_connector_cleanup(&intel_connector->base);
2011err:
2012 drm_encoder_cleanup(&intel_encoder->base);
2013 kfree(intel_dsi);
2014 kfree(intel_connector);
2015}