| File: | dev/mii/atphy.c |
| Warning: | line 178, column 3 Value stored to 'bmcr' is never read |
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| 1 | /* $OpenBSD: atphy.c,v 1.13 2022/04/06 18:59:29 naddy Exp $ */ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice unmodified, this list of conditions, and the following |
| 12 | * disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 18 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 21 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 22 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 23 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 24 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 25 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 26 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 27 | * SUCH DAMAGE. |
| 28 | */ |
| 29 | |
| 30 | /* |
| 31 | * Driver for the Attansic F1 10/100/1000 PHY. |
| 32 | */ |
| 33 | |
| 34 | #include <sys/param.h> |
| 35 | #include <sys/systm.h> |
| 36 | #include <sys/device.h> |
| 37 | #include <sys/socket.h> |
| 38 | |
| 39 | #include <net/if.h> |
| 40 | #include <net/if_var.h> |
| 41 | #include <net/if_media.h> |
| 42 | |
| 43 | #include <dev/mii/mii.h> |
| 44 | #include <dev/mii/miivar.h> |
| 45 | #include <dev/mii/miidevs.h> |
| 46 | |
| 47 | /* Special Control Register */ |
| 48 | #define ATPHY_SCR0x10 0x10 |
| 49 | #define ATPHY_SCR_JABBER_DISABLE0x0001 0x0001 |
| 50 | #define ATPHY_SCR_POLARITY_REVERSAL0x0002 0x0002 |
| 51 | #define ATPHY_SCR_SQE_TEST0x0004 0x0004 |
| 52 | #define ATPHY_SCR_MAC_PDOWN0x0008 0x0008 |
| 53 | #define ATPHY_SCR_CLK125_DISABLE0x0010 0x0010 |
| 54 | #define ATPHY_SCR_MDI_MANUAL_MODE0x0000 0x0000 |
| 55 | #define ATPHY_SCR_MDIX_MANUAL_MODE0x0020 0x0020 |
| 56 | #define ATPHY_SCR_AUTO_X_1000T0x0040 0x0040 |
| 57 | #define ATPHY_SCR_AUTO_X_MODE0x0060 0x0060 |
| 58 | #define ATPHY_SCR_10BT_EXT_ENABLE0x0080 0x0080 |
| 59 | #define ATPHY_SCR_MII_5BIT_ENABLE0x0100 0x0100 |
| 60 | #define ATPHY_SCR_SCRAMBLER_DISABLE0x0200 0x0200 |
| 61 | #define ATPHY_SCR_FORCE_LINK_GOOD0x0400 0x0400 |
| 62 | #define ATPHY_SCR_ASSERT_CRS_ON_TX0x0800 0x0800 |
| 63 | |
| 64 | /* Special Status Register. */ |
| 65 | #define ATPHY_SSR0x11 0x11 |
| 66 | #define ATPHY_SSR_SPD_DPLX_RESOLVED0x0800 0x0800 |
| 67 | #define ATPHY_SSR_DUPLEX0x2000 0x2000 |
| 68 | #define ATPHY_SSR_SPEED_MASK0xC000 0xC000 |
| 69 | #define ATPHY_SSR_10MBS0x0000 0x0000 |
| 70 | #define ATPHY_SSR_100MBS0x4000 0x4000 |
| 71 | #define ATPHY_SSR_1000MBS0x8000 0x8000 |
| 72 | |
| 73 | int atphy_service(struct mii_softc *, struct mii_data *, int); |
| 74 | void atphy_attach(struct device *, struct device *, void *); |
| 75 | int atphy_match(struct device *, void *, void *); |
| 76 | void atphy_reset(struct mii_softc *); |
| 77 | void atphy_status(struct mii_softc *); |
| 78 | int atphy_mii_phy_auto(struct mii_softc *); |
| 79 | |
| 80 | const struct mii_phy_funcs atphy_funcs = { |
| 81 | atphy_service, atphy_status, atphy_reset, |
| 82 | }; |
| 83 | |
| 84 | static const struct mii_phydesc atphys[] = { |
| 85 | { MII_OUI_ATHEROS0x001374, MII_MODEL_ATHEROS_F10x0001, |
| 86 | MII_STR_ATHEROS_F1"F1 10/100/1000 PHY" }, |
| 87 | { MII_OUI_ATHEROS0x001374, MII_MODEL_ATHEROS_F20x0002, |
| 88 | MII_STR_ATHEROS_F2"F2 10/100 PHY" }, |
| 89 | { MII_OUI_ATHEROS0x001374, MII_MODEL_ATHEROS_AR80350x0007, |
| 90 | MII_STR_ATHEROS_AR8035"AR8035 10/100/1000 PHY" }, |
| 91 | { 0, 0, |
| 92 | NULL((void *)0) }, |
| 93 | }; |
| 94 | |
| 95 | const struct cfattach atphy_ca = { |
| 96 | sizeof (struct mii_softc), atphy_match, atphy_attach, |
| 97 | mii_phy_detach |
| 98 | }; |
| 99 | |
| 100 | struct cfdriver atphy_cd = { |
| 101 | NULL((void *)0), "atphy", DV_DULL |
| 102 | }; |
| 103 | |
| 104 | int |
| 105 | atphy_match(struct device *parent, void *match, void *aux) |
| 106 | { |
| 107 | struct mii_attach_args *ma = aux; |
| 108 | |
| 109 | if (mii_phy_match(ma, atphys) != NULL((void *)0)) |
| 110 | return (10); |
| 111 | |
| 112 | return (0); |
| 113 | } |
| 114 | |
| 115 | void |
| 116 | atphy_attach(struct device *parent, struct device *self, void *aux) |
| 117 | { |
| 118 | struct mii_softc *sc = (struct mii_softc *)self; |
| 119 | struct mii_attach_args *ma = aux; |
| 120 | struct mii_data *mii = ma->mii_data; |
| 121 | const struct mii_phydesc *mpd; |
| 122 | |
| 123 | mpd = mii_phy_match(ma, atphys); |
| 124 | printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2)((ma->mii_id2) & 0x000f)); |
| 125 | |
| 126 | sc->mii_inst = mii->mii_instance; |
| 127 | sc->mii_phy = ma->mii_phyno; |
| 128 | sc->mii_funcs = &atphy_funcs; |
| 129 | sc->mii_oui = MII_OUI(ma->mii_id1, ma->mii_id2)(((ma->mii_id1) << 6) | ((ma->mii_id2) >> 10 )); |
| 130 | sc->mii_model = MII_MODEL(ma->mii_id2)(((ma->mii_id2) & 0x03f0) >> 4); |
| 131 | sc->mii_pdata = mii; |
| 132 | sc->mii_flags = ma->mii_flags; |
| 133 | sc->mii_anegticks = MII_ANEGTICKS_GIGE10; |
| 134 | |
| 135 | sc->mii_flags |= MIIF_NOLOOP0x0004; |
| 136 | |
| 137 | PHY_RESET(sc)(*(sc)->mii_funcs->pf_reset)((sc)); |
| 138 | |
| 139 | sc->mii_capabilities = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) & ma->mii_capmask; |
| 140 | if (sc->mii_capabilities & BMSR_EXTSTAT0x0100) |
| 141 | sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0f)); |
| 142 | |
| 143 | mii_phy_add_media(sc); |
| 144 | } |
| 145 | |
| 146 | int |
| 147 | atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) |
| 148 | { |
| 149 | struct ifmedia_entry *ife = mii->mii_media.ifm_cur; |
| 150 | uint16_t anar, bmcr, bmsr; |
| 151 | |
| 152 | switch (cmd) { |
| 153 | case MII_POLLSTAT3: |
| 154 | /* |
| 155 | * If we're not polling our PHY instance, just return. |
| 156 | */ |
| 157 | if (IFM_INST(ife->ifm_media)(((ife->ifm_media) & 0xff00000000000000ULL) >> 56 ) != sc->mii_inst) |
| 158 | return (0); |
| 159 | break; |
| 160 | |
| 161 | case MII_MEDIACHG2: |
| 162 | /* |
| 163 | * If the media indicates a different PHY instance, |
| 164 | * isolate ourselves. |
| 165 | */ |
| 166 | if (IFM_INST(ife->ifm_media)(((ife->ifm_media) & 0xff00000000000000ULL) >> 56 ) != sc->mii_inst) { |
| 167 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); |
| 168 | PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (bmcr | 0x0400)); |
| 169 | return (0); |
| 170 | } |
| 171 | |
| 172 | /* |
| 173 | * If the interface is not up, don't do anything. |
| 174 | */ |
| 175 | if ((mii->mii_ifp->if_flags & IFF_UP0x1) == 0) |
| 176 | break; |
| 177 | |
| 178 | bmcr = 0; |
Value stored to 'bmcr' is never read | |
| 179 | switch (IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL)) { |
| 180 | case IFM_AUTO0ULL: |
| 181 | case IFM_1000_T16: |
| 182 | atphy_mii_phy_auto(sc); |
| 183 | goto done; |
| 184 | case IFM_100_TX6: |
| 185 | bmcr = BMCR_S1000x2000; |
| 186 | break; |
| 187 | case IFM_10_T3: |
| 188 | bmcr = BMCR_S100x0000; |
| 189 | break; |
| 190 | case IFM_NONE2ULL: |
| 191 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); |
| 192 | /* |
| 193 | * XXX |
| 194 | * Due to an unknown reason powering down PHY resulted |
| 195 | * in unexpected results such as inaccessibility of |
| 196 | * hardware of freshly rebooted system. Disable |
| 197 | * powering down PHY until I get more information for |
| 198 | * Attansic/Atheros PHY hardware. |
| 199 | */ |
| 200 | PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (bmcr | 0x0400)); |
| 201 | goto done; |
| 202 | default: |
| 203 | return (EINVAL22); |
| 204 | } |
| 205 | |
| 206 | anar = mii_anar(ife->ifm_media); |
| 207 | if (((ife->ifm_media & IFM_GMASK0x00ffff0000000000ULL) & IFM_FDX0x0000010000000000ULL) != 0) { |
| 208 | bmcr |= BMCR_FDX0x0100; |
| 209 | /* Enable pause. */ |
| 210 | if (sc->mii_flags & MIIF_DOPAUSE0x0100) |
| 211 | anar |= ANAR_PAUSE_TOWARDS(3 << 10); |
| 212 | } |
| 213 | |
| 214 | if ((sc->mii_extcapabilities & (EXTSR_1000TFDX0x2000 | |
| 215 | EXTSR_1000THDX0x1000)) != 0) |
| 216 | PHY_WRITE(sc, MII_100T2CR, 0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (0)); |
| 217 | PHY_WRITE(sc, MII_ANAR, anar)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x04), (anar)); |
| 218 | |
| 219 | /* |
| 220 | * Reset the PHY so all changes take effect. |
| 221 | */ |
| 222 | PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (bmcr | 0x8000 | 0x1000 | 0x0200) ) |
| 223 | BMCR_STARTNEG)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (bmcr | 0x8000 | 0x1000 | 0x0200) ); |
| 224 | done: |
| 225 | break; |
| 226 | |
| 227 | case MII_TICK1: |
| 228 | /* |
| 229 | * If we're not currently selected, just return. |
| 230 | */ |
| 231 | if (IFM_INST(ife->ifm_media)(((ife->ifm_media) & 0xff00000000000000ULL) >> 56 ) != sc->mii_inst) |
| 232 | return (0); |
| 233 | |
| 234 | /* |
| 235 | * Is the interface even up? |
| 236 | */ |
| 237 | if ((mii->mii_ifp->if_flags & IFF_UP0x1) == 0) |
| 238 | return (0); |
| 239 | |
| 240 | /* |
| 241 | * Only used for autonegotiation. |
| 242 | */ |
| 243 | if (IFM_SUBTYPE(ife->ifm_media)((ife->ifm_media) & 0x00000000000000ffULL) != IFM_AUTO0ULL) { |
| 244 | sc->mii_ticks = 0; |
| 245 | break; |
| 246 | } |
| 247 | |
| 248 | /* |
| 249 | * Check for link. |
| 250 | * Read the status register twice; BMSR_LINK is latch-low. |
| 251 | */ |
| 252 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); |
| 253 | if (bmsr & BMSR_LINK0x0004) { |
| 254 | sc->mii_ticks = 0; |
| 255 | break; |
| 256 | } |
| 257 | |
| 258 | /* Announce link loss right after it happens. */ |
| 259 | if (sc->mii_ticks++ == 0) |
| 260 | break; |
| 261 | |
| 262 | /* |
| 263 | * Only retry autonegotiation every mii_anegticks seconds. |
| 264 | */ |
| 265 | if (sc->mii_ticks <= sc->mii_anegticks) |
| 266 | return (0); |
| 267 | |
| 268 | sc->mii_ticks = 0; |
| 269 | atphy_mii_phy_auto(sc); |
| 270 | break; |
| 271 | } |
| 272 | |
| 273 | /* Update the media status. */ |
| 274 | mii_phy_status(sc); |
| 275 | |
| 276 | /* Callback if something changed. */ |
| 277 | mii_phy_update(sc, cmd); |
| 278 | return (0); |
| 279 | } |
| 280 | |
| 281 | void |
| 282 | atphy_status(struct mii_softc *sc) |
| 283 | { |
| 284 | struct mii_data *mii = sc->mii_pdata; |
| 285 | uint32_t bmsr, bmcr, gsr, ssr; |
| 286 | |
| 287 | mii->mii_media_status = IFM_AVALID0x0000000000000001ULL; |
| 288 | mii->mii_media_active = IFM_ETHER0x0000000000000100ULL; |
| 289 | |
| 290 | bmsr = PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)) | PHY_READ(sc, MII_BMSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x01)); |
| 291 | if (bmsr & BMSR_LINK0x0004) |
| 292 | mii->mii_media_status |= IFM_ACTIVE0x0000000000000002ULL; |
| 293 | |
| 294 | bmcr = PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)); |
| 295 | if (bmcr & BMCR_ISO0x0400) { |
| 296 | mii->mii_media_active |= IFM_NONE2ULL; |
| 297 | mii->mii_media_status = 0; |
| 298 | return; |
| 299 | } |
| 300 | |
| 301 | if (bmcr & BMCR_LOOP0x4000) |
| 302 | mii->mii_media_active |= IFM_LOOP0x0000800000000000ULL; |
| 303 | |
| 304 | ssr = PHY_READ(sc, ATPHY_SSR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x11)); |
| 305 | if (!(ssr & ATPHY_SSR_SPD_DPLX_RESOLVED0x0800)) { |
| 306 | /* Erg, still trying, I guess... */ |
| 307 | mii->mii_media_active |= IFM_NONE2ULL; |
| 308 | return; |
| 309 | } |
| 310 | |
| 311 | switch (ssr & ATPHY_SSR_SPEED_MASK0xC000) { |
| 312 | case ATPHY_SSR_1000MBS0x8000: |
| 313 | mii->mii_media_active |= IFM_1000_T16; |
| 314 | /* |
| 315 | * atphy(4) has a valid link so reset mii_ticks. |
| 316 | * Resetting mii_ticks is needed in order to |
| 317 | * detect link loss after auto-negotiation. |
| 318 | */ |
| 319 | sc->mii_ticks = 0; |
| 320 | break; |
| 321 | case ATPHY_SSR_100MBS0x4000: |
| 322 | mii->mii_media_active |= IFM_100_TX6; |
| 323 | sc->mii_ticks = 0; |
| 324 | break; |
| 325 | case ATPHY_SSR_10MBS0x0000: |
| 326 | mii->mii_media_active |= IFM_10_T3; |
| 327 | sc->mii_ticks = 0; |
| 328 | break; |
| 329 | default: |
| 330 | mii->mii_media_active |= IFM_NONE2ULL; |
| 331 | return; |
| 332 | } |
| 333 | |
| 334 | if (ssr & ATPHY_SSR_DUPLEX0x2000) |
| 335 | mii->mii_media_active |= IFM_FDX0x0000010000000000ULL | mii_phy_flowstatus(sc); |
| 336 | else |
| 337 | mii->mii_media_active |= IFM_HDX0x0000020000000000ULL; |
| 338 | |
| 339 | gsr = PHY_READ(sc, MII_100T2SR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x0a)); |
| 340 | if ((IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL) == IFM_1000_T16) && |
| 341 | gsr & GTSR_MS_RES0x4000) |
| 342 | mii->mii_media_active |= IFM_ETH_MASTER0x0000000000010000ULL; |
| 343 | } |
| 344 | |
| 345 | void |
| 346 | atphy_reset(struct mii_softc *sc) |
| 347 | { |
| 348 | uint32_t reg; |
| 349 | int i; |
| 350 | |
| 351 | /* Take PHY out of power down mode. */ |
| 352 | PHY_WRITE(sc, 29, 0x29)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (29), (0x29)); |
| 353 | PHY_WRITE(sc, 30, 0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (30), (0)); |
| 354 | |
| 355 | reg = PHY_READ(sc, ATPHY_SCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10)); |
| 356 | /* Enable automatic crossover. */ |
| 357 | reg |= ATPHY_SCR_AUTO_X_MODE0x0060; |
| 358 | /* Disable power down. */ |
| 359 | reg &= ~ATPHY_SCR_MAC_PDOWN0x0008; |
| 360 | /* Enable CRS on Tx. */ |
| 361 | reg |= ATPHY_SCR_ASSERT_CRS_ON_TX0x0800; |
| 362 | /* Auto correction for reversed cable polarity. */ |
| 363 | reg |= ATPHY_SCR_POLARITY_REVERSAL0x0002; |
| 364 | PHY_WRITE(sc, ATPHY_SCR, reg)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x10), (reg)); |
| 365 | |
| 366 | /* Workaround F1 bug to reset phy. */ |
| 367 | atphy_mii_phy_auto(sc); |
| 368 | |
| 369 | for (i = 0; i < 1000; i++) { |
| 370 | DELAY(1)(*delay_func)(1); |
| 371 | if ((PHY_READ(sc, MII_BMCR)(*(sc)->mii_pdata->mii_readreg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00)) & BMCR_RESET0x8000) == 0) |
| 372 | break; |
| 373 | } |
| 374 | } |
| 375 | |
| 376 | int |
| 377 | atphy_mii_phy_auto(struct mii_softc *sc) |
| 378 | { |
| 379 | uint16_t anar; |
| 380 | |
| 381 | anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities)(((sc->mii_capabilities) & (0x8000|0x4000|0x2000| 0x1000 |0x0800|0x0400|0x0200)) >> 6) | ANAR_CSMA0x0001; |
| 382 | if (sc->mii_flags & MIIF_DOPAUSE0x0100) |
| 383 | anar |= ANAR_PAUSE_TOWARDS(3 << 10); |
| 384 | PHY_WRITE(sc, MII_ANAR, anar)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x04), (anar)); |
| 385 | if (sc->mii_extcapabilities & (EXTSR_1000TFDX0x2000 | EXTSR_1000THDX0x1000)) |
| 386 | PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (0x0200 | 0x0100)) |
| 387 | GTCR_ADV_1000THDX)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (0x0200 | 0x0100)); |
| 388 | else if (sc->mii_model == MII_MODEL_ATHEROS_F10x0001) { |
| 389 | /* |
| 390 | * AR8132 has 10/100 PHY and the PHY uses the same |
| 391 | * model number of F1 gigabit PHY. The PHY has no |
| 392 | * ability to establish gigabit link so explicitly |
| 393 | * disable 1000baseT configuration for the PHY. |
| 394 | * Otherwise, there is a case that atphy(4) could |
| 395 | * not establish a link against gigabit link partner |
| 396 | * unless the link partner supports down-shifting. |
| 397 | */ |
| 398 | PHY_WRITE(sc, MII_100T2CR, 0)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x09), (0)); |
| 399 | } |
| 400 | PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG)(*(sc)->mii_pdata->mii_writereg)((sc)->mii_dev.dv_parent , (sc)->mii_phy, (0x00), (0x8000 | 0x1000 | 0x0200)); |
| 401 | |
| 402 | return (EJUSTRETURN-2); |
| 403 | } |