| File: | dev/pci/drm/amd/amdgpu/amdgpu_drv.c |
| Warning: | line 2354, column 4 Value stored to 'r' is never read |
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| 1 | /* |
| 2 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. |
| 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | */ |
| 24 | |
| 25 | #include <drm/amdgpu_drm.h> |
| 26 | #include <drm/drm_drv.h> |
| 27 | #include <drm/drm_gem.h> |
| 28 | #include <drm/drm_vblank.h> |
| 29 | #include <drm/drm_managed.h> |
| 30 | #include "amdgpu_drv.h" |
| 31 | |
| 32 | #include <drm/drm_pciids.h> |
| 33 | #include <linux/module.h> |
| 34 | #include <linux/pm_runtime.h> |
| 35 | #include <linux/vga_switcheroo.h> |
| 36 | #include <drm/drm_probe_helper.h> |
| 37 | #include <linux/mmu_notifier.h> |
| 38 | #include <linux/suspend.h> |
| 39 | #include <linux/cc_platform.h> |
| 40 | #include <linux/fb.h> |
| 41 | #include <linux/dynamic_debug.h> |
| 42 | |
| 43 | #include "amdgpu.h" |
| 44 | #include "amdgpu_irq.h" |
| 45 | #include "amdgpu_dma_buf.h" |
| 46 | #include "amdgpu_sched.h" |
| 47 | #include "amdgpu_fdinfo.h" |
| 48 | #include "amdgpu_amdkfd.h" |
| 49 | |
| 50 | #include "amdgpu_ras.h" |
| 51 | #include "amdgpu_xgmi.h" |
| 52 | #include "amdgpu_reset.h" |
| 53 | |
| 54 | /* |
| 55 | * KMS wrapper. |
| 56 | * - 3.0.0 - initial driver |
| 57 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
| 58 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
| 59 | * at the end of IBs. |
| 60 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
| 61 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
| 62 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
| 63 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
| 64 | * - 3.7.0 - Add support for VCE clock list packet |
| 65 | * - 3.8.0 - Add support raster config init in the kernel |
| 66 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
| 67 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
| 68 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). |
| 69 | * - 3.12.0 - Add query for double offchip LDS buffers |
| 70 | * - 3.13.0 - Add PRT support |
| 71 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality |
| 72 | * - 3.15.0 - Export more gpu info for gfx9 |
| 73 | * - 3.16.0 - Add reserved vmid support |
| 74 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. |
| 75 | * - 3.18.0 - Export gpu always on cu bitmap |
| 76 | * - 3.19.0 - Add support for UVD MJPEG decode |
| 77 | * - 3.20.0 - Add support for local BOs |
| 78 | * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl |
| 79 | * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl |
| 80 | * - 3.23.0 - Add query for VRAM lost counter |
| 81 | * - 3.24.0 - Add high priority compute support for gfx9 |
| 82 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). |
| 83 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. |
| 84 | * - 3.27.0 - Add new chunk to AMDGPU_CS to enable BO_LIST creation. |
| 85 | * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES |
| 86 | * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID |
| 87 | * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. |
| 88 | * - 3.31.0 - Add support for per-flip tiling attribute changes with DC |
| 89 | * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. |
| 90 | * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. |
| 91 | * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches |
| 92 | * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask |
| 93 | * - 3.36.0 - Allow reading more status registers on si/cik |
| 94 | * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness |
| 95 | * - 3.38.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC |
| 96 | * - 3.39.0 - DMABUF implicit sync does a full pipeline sync |
| 97 | * - 3.40.0 - Add AMDGPU_IDS_FLAGS_TMZ |
| 98 | * - 3.41.0 - Add video codec query |
| 99 | * - 3.42.0 - Add 16bpc fixed point display support |
| 100 | * - 3.43.0 - Add device hot plug/unplug support |
| 101 | * - 3.44.0 - DCN3 supports DCC independent block settings: !64B && 128B, 64B && 128B |
| 102 | * - 3.45.0 - Add context ioctl stable pstate interface |
| 103 | * - 3.46.0 - To enable hot plug amdgpu tests in libdrm |
| 104 | * - 3.47.0 - Add AMDGPU_GEM_CREATE_DISCARDABLE and AMDGPU_VM_NOALLOC flags |
| 105 | * - 3.48.0 - Add IP discovery version info to HW INFO |
| 106 | * 3.49.0 - Add gang submit into CS IOCTL |
| 107 | */ |
| 108 | #define KMS_DRIVER_MAJOR3 3 |
| 109 | #define KMS_DRIVER_MINOR49 49 |
| 110 | #define KMS_DRIVER_PATCHLEVEL0 0 |
| 111 | |
| 112 | int amdgpu_vram_limit; |
| 113 | int amdgpu_vis_vram_limit; |
| 114 | int amdgpu_gart_size = -1; /* auto */ |
| 115 | int amdgpu_gtt_size = -1; /* auto */ |
| 116 | int amdgpu_moverate = -1; /* auto */ |
| 117 | int amdgpu_audio = -1; |
| 118 | int amdgpu_disp_priority; |
| 119 | int amdgpu_hw_i2c; |
| 120 | int amdgpu_pcie_gen2 = -1; |
| 121 | int amdgpu_msi = -1; |
| 122 | char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH256]; |
| 123 | int amdgpu_dpm = -1; |
| 124 | int amdgpu_fw_load_type = -1; |
| 125 | int amdgpu_aspm = -1; |
| 126 | int amdgpu_runtime_pm = -1; |
| 127 | uint amdgpu_ip_block_mask = 0xffffffff; |
| 128 | int amdgpu_bapm = -1; |
| 129 | int amdgpu_deep_color; |
| 130 | int amdgpu_vm_size = -1; |
| 131 | int amdgpu_vm_fragment_size = -1; |
| 132 | int amdgpu_vm_block_size = -1; |
| 133 | int amdgpu_vm_fault_stop; |
| 134 | int amdgpu_vm_debug; |
| 135 | int amdgpu_vm_update_mode = -1; |
| 136 | int amdgpu_exp_hw_support; |
| 137 | int amdgpu_dc = -1; |
| 138 | int amdgpu_sched_jobs = 32; |
| 139 | int amdgpu_sched_hw_submission = 2; |
| 140 | uint amdgpu_pcie_gen_cap; |
| 141 | uint amdgpu_pcie_lane_cap; |
| 142 | u64 amdgpu_cg_mask = 0xffffffffffffffff; |
| 143 | uint amdgpu_pg_mask = 0xffffffff; |
| 144 | uint amdgpu_sdma_phase_quantum = 32; |
| 145 | char *amdgpu_disable_cu = NULL((void *)0); |
| 146 | char *amdgpu_virtual_display = NULL((void *)0); |
| 147 | |
| 148 | /* |
| 149 | * OverDrive(bit 14) disabled by default |
| 150 | * GFX DCS(bit 19) disabled by default |
| 151 | */ |
| 152 | uint amdgpu_pp_feature_mask = 0xfff7bfff; |
| 153 | uint amdgpu_force_long_training; |
| 154 | int amdgpu_job_hang_limit; |
| 155 | int amdgpu_lbpw = -1; |
| 156 | int amdgpu_compute_multipipe = -1; |
| 157 | int amdgpu_gpu_recovery = -1; /* auto */ |
| 158 | int amdgpu_emu_mode; |
| 159 | uint amdgpu_smu_memory_pool_size; |
| 160 | int amdgpu_smu_pptable_id = -1; |
| 161 | /* |
| 162 | * FBC (bit 0) disabled by default |
| 163 | * MULTI_MON_PP_MCLK_SWITCH (bit 1) enabled by default |
| 164 | * - With this, for multiple monitors in sync(e.g. with the same model), |
| 165 | * mclk switching will be allowed. And the mclk will be not foced to the |
| 166 | * highest. That helps saving some idle power. |
| 167 | * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default |
| 168 | * PSR (bit 3) disabled by default |
| 169 | * EDP NO POWER SEQUENCING (bit 4) disabled by default |
| 170 | */ |
| 171 | uint amdgpu_dc_feature_mask = 2; |
| 172 | uint amdgpu_dc_debug_mask; |
| 173 | uint amdgpu_dc_visual_confirm; |
| 174 | int amdgpu_async_gfx_ring = 1; |
| 175 | int amdgpu_mcbp; |
| 176 | int amdgpu_discovery = -1; |
| 177 | int amdgpu_mes; |
| 178 | int amdgpu_mes_kiq; |
| 179 | int amdgpu_noretry = -1; |
| 180 | int amdgpu_force_asic_type = -1; |
| 181 | int amdgpu_tmz = -1; /* auto */ |
| 182 | uint amdgpu_freesync_vid_mode; |
| 183 | int amdgpu_reset_method = -1; /* auto */ |
| 184 | int amdgpu_num_kcq = -1; |
| 185 | int amdgpu_smartshift_bias; |
| 186 | int amdgpu_use_xgmi_p2p = 1; |
| 187 | int amdgpu_vcnfw_log; |
| 188 | int amdgpu_sg_display = -1; /* auto */ |
| 189 | |
| 190 | static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); |
| 191 | |
| 192 | DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, |
| 193 | "DRM_UT_CORE", |
| 194 | "DRM_UT_DRIVER", |
| 195 | "DRM_UT_KMS", |
| 196 | "DRM_UT_PRIME", |
| 197 | "DRM_UT_ATOMIC", |
| 198 | "DRM_UT_VBL", |
| 199 | "DRM_UT_STATE", |
| 200 | "DRM_UT_LEASE", |
| 201 | "DRM_UT_DP", |
| 202 | "DRM_UT_DRMRES"); |
| 203 | |
| 204 | struct amdgpu_mgpu_info mgpu_info = { |
| 205 | .mutex = RWLOCK_INITIALIZER("mgpu_info"){ 0, "mgpu_info" }, |
| 206 | .delayed_reset_work = __DELAYED_WORK_INITIALIZER({ .to = { .to_list = { ((void *)0), ((void *)0) }, .to_abstime = { .tv_sec = 0, .tv_nsec = 0 }, .to_func = ((__delayed_work_tick )), .to_arg = ((&(mgpu_info.delayed_reset_work))), .to_time = 0, .to_flags = (0) | 0x04, .to_kclock = ((-1)) }, .tq = (( void *)0), .work.tq = ((void *)0), .work.task = {{ ((void *)0 ), ((void *)0) }, ((void (*)(void *))(amdgpu_drv_delayed_reset_work_handler )), (&(mgpu_info.delayed_reset_work).work), 0 } } |
| 207 | mgpu_info.delayed_reset_work,{ .to = { .to_list = { ((void *)0), ((void *)0) }, .to_abstime = { .tv_sec = 0, .tv_nsec = 0 }, .to_func = ((__delayed_work_tick )), .to_arg = ((&(mgpu_info.delayed_reset_work))), .to_time = 0, .to_flags = (0) | 0x04, .to_kclock = ((-1)) }, .tq = (( void *)0), .work.tq = ((void *)0), .work.task = {{ ((void *)0 ), ((void *)0) }, ((void (*)(void *))(amdgpu_drv_delayed_reset_work_handler )), (&(mgpu_info.delayed_reset_work).work), 0 } } |
| 208 | amdgpu_drv_delayed_reset_work_handler, 0){ .to = { .to_list = { ((void *)0), ((void *)0) }, .to_abstime = { .tv_sec = 0, .tv_nsec = 0 }, .to_func = ((__delayed_work_tick )), .to_arg = ((&(mgpu_info.delayed_reset_work))), .to_time = 0, .to_flags = (0) | 0x04, .to_kclock = ((-1)) }, .tq = (( void *)0), .work.tq = ((void *)0), .work.task = {{ ((void *)0 ), ((void *)0) }, ((void (*)(void *))(amdgpu_drv_delayed_reset_work_handler )), (&(mgpu_info.delayed_reset_work).work), 0 } }, |
| 209 | }; |
| 210 | int amdgpu_ras_enable = -1; |
| 211 | uint amdgpu_ras_mask = 0xffffffff; |
| 212 | int amdgpu_bad_page_threshold = -1; |
| 213 | struct amdgpu_watchdog_timer amdgpu_watchdog_timer = { |
| 214 | .timeout_fatal_disable = false0, |
| 215 | .period = 0x0, /* default to 0x0 (timeout disable) */ |
| 216 | }; |
| 217 | |
| 218 | /** |
| 219 | * DOC: vramlimit (int) |
| 220 | * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). |
| 221 | */ |
| 222 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
| 223 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); |
| 224 | |
| 225 | /** |
| 226 | * DOC: vis_vramlimit (int) |
| 227 | * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). |
| 228 | */ |
| 229 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); |
| 230 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); |
| 231 | |
| 232 | /** |
| 233 | * DOC: gartsize (uint) |
| 234 | * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). |
| 235 | */ |
| 236 | MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); |
| 237 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600); |
| 238 | |
| 239 | /** |
| 240 | * DOC: gttsize (int) |
| 241 | * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, |
| 242 | * otherwise 3/4 RAM size). |
| 243 | */ |
| 244 | MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); |
| 245 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600); |
| 246 | |
| 247 | /** |
| 248 | * DOC: moverate (int) |
| 249 | * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). |
| 250 | */ |
| 251 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
| 252 | module_param_named(moverate, amdgpu_moverate, int, 0600); |
| 253 | |
| 254 | /** |
| 255 | * DOC: audio (int) |
| 256 | * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. |
| 257 | */ |
| 258 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); |
| 259 | module_param_named(audio, amdgpu_audio, int, 0444); |
| 260 | |
| 261 | /** |
| 262 | * DOC: disp_priority (int) |
| 263 | * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). |
| 264 | */ |
| 265 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
| 266 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); |
| 267 | |
| 268 | /** |
| 269 | * DOC: hw_i2c (int) |
| 270 | * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). |
| 271 | */ |
| 272 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
| 273 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); |
| 274 | |
| 275 | /** |
| 276 | * DOC: pcie_gen2 (int) |
| 277 | * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). |
| 278 | */ |
| 279 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
| 280 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); |
| 281 | |
| 282 | /** |
| 283 | * DOC: msi (int) |
| 284 | * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). |
| 285 | */ |
| 286 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
| 287 | module_param_named(msi, amdgpu_msi, int, 0444); |
| 288 | |
| 289 | /** |
| 290 | * DOC: lockup_timeout (string) |
| 291 | * Set GPU scheduler timeout value in ms. |
| 292 | * |
| 293 | * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or |
| 294 | * multiple values specified. 0 and negative values are invalidated. They will be adjusted |
| 295 | * to the default timeout. |
| 296 | * |
| 297 | * - With one value specified, the setting will apply to all non-compute jobs. |
| 298 | * - With multiple values specified, the first one will be for GFX. |
| 299 | * The second one is for Compute. The third and fourth ones are |
| 300 | * for SDMA and Video. |
| 301 | * |
| 302 | * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) |
| 303 | * jobs is 10000. The timeout for compute is 60000. |
| 304 | */ |
| 305 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; " |
| 306 | "for passthrough or sriov, 10000 for all jobs." |
| 307 | " 0: keep default value. negative: infinity timeout), " |
| 308 | "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " |
| 309 | "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); |
| 310 | module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); |
| 311 | |
| 312 | /** |
| 313 | * DOC: dpm (int) |
| 314 | * Override for dynamic power management setting |
| 315 | * (0 = disable, 1 = enable) |
| 316 | * The default is -1 (auto). |
| 317 | */ |
| 318 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); |
| 319 | module_param_named(dpm, amdgpu_dpm, int, 0444); |
| 320 | |
| 321 | /** |
| 322 | * DOC: fw_load_type (int) |
| 323 | * Set different firmware loading type for debugging, if supported. |
| 324 | * Set to 0 to force direct loading if supported by the ASIC. Set |
| 325 | * to -1 to select the default loading mode for the ASIC, as defined |
| 326 | * by the driver. The default is -1 (auto). |
| 327 | */ |
| 328 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (3 = rlc backdoor autoload if supported, 2 = smu load if supported, 1 = psp load, 0 = force direct if supported, -1 = auto)"); |
| 329 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); |
| 330 | |
| 331 | /** |
| 332 | * DOC: aspm (int) |
| 333 | * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). |
| 334 | */ |
| 335 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); |
| 336 | module_param_named(aspm, amdgpu_aspm, int, 0444); |
| 337 | |
| 338 | /** |
| 339 | * DOC: runpm (int) |
| 340 | * Override for runtime power management control for dGPUs. The amdgpu driver can dynamically power down |
| 341 | * the dGPUs when they are idle if supported. The default is -1 (auto enable). |
| 342 | * Setting the value to 0 disables this functionality. |
| 343 | */ |
| 344 | MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = auto)"); |
| 345 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); |
| 346 | |
| 347 | /** |
| 348 | * DOC: ip_block_mask (uint) |
| 349 | * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). |
| 350 | * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have |
| 351 | * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in |
| 352 | * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). |
| 353 | */ |
| 354 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
| 355 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); |
| 356 | |
| 357 | /** |
| 358 | * DOC: bapm (int) |
| 359 | * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. |
| 360 | * The default -1 (auto, enabled) |
| 361 | */ |
| 362 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); |
| 363 | module_param_named(bapm, amdgpu_bapm, int, 0444); |
| 364 | |
| 365 | /** |
| 366 | * DOC: deep_color (int) |
| 367 | * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). |
| 368 | */ |
| 369 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); |
| 370 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); |
| 371 | |
| 372 | /** |
| 373 | * DOC: vm_size (int) |
| 374 | * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). |
| 375 | */ |
| 376 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
| 377 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
| 378 | |
| 379 | /** |
| 380 | * DOC: vm_fragment_size (int) |
| 381 | * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). |
| 382 | */ |
| 383 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); |
| 384 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); |
| 385 | |
| 386 | /** |
| 387 | * DOC: vm_block_size (int) |
| 388 | * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). |
| 389 | */ |
| 390 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); |
| 391 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); |
| 392 | |
| 393 | /** |
| 394 | * DOC: vm_fault_stop (int) |
| 395 | * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). |
| 396 | */ |
| 397 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
| 398 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); |
| 399 | |
| 400 | /** |
| 401 | * DOC: vm_debug (int) |
| 402 | * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). |
| 403 | */ |
| 404 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
| 405 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); |
| 406 | |
| 407 | /** |
| 408 | * DOC: vm_update_mode (int) |
| 409 | * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default |
| 410 | * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). |
| 411 | */ |
| 412 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); |
| 413 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); |
| 414 | |
| 415 | /** |
| 416 | * DOC: exp_hw_support (int) |
| 417 | * Enable experimental hw support (1 = enable). The default is 0 (disabled). |
| 418 | */ |
| 419 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
| 420 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); |
| 421 | |
| 422 | /** |
| 423 | * DOC: dc (int) |
| 424 | * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). |
| 425 | */ |
| 426 | MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); |
| 427 | module_param_named(dc, amdgpu_dc, int, 0444); |
| 428 | |
| 429 | /** |
| 430 | * DOC: sched_jobs (int) |
| 431 | * Override the max number of jobs supported in the sw queue. The default is 32. |
| 432 | */ |
| 433 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
| 434 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
| 435 | |
| 436 | /** |
| 437 | * DOC: sched_hw_submission (int) |
| 438 | * Override the max number of HW submissions. The default is 2. |
| 439 | */ |
| 440 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
| 441 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); |
| 442 | |
| 443 | /** |
| 444 | * DOC: ppfeaturemask (hexint) |
| 445 | * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
| 446 | * The default is the current set of stable power features. |
| 447 | */ |
| 448 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
| 449 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); |
| 450 | |
| 451 | /** |
| 452 | * DOC: forcelongtraining (uint) |
| 453 | * Force long memory training in resume. |
| 454 | * The default is zero, indicates short training in resume. |
| 455 | */ |
| 456 | MODULE_PARM_DESC(forcelongtraining, "force memory long training"); |
| 457 | module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); |
| 458 | |
| 459 | /** |
| 460 | * DOC: pcie_gen_cap (uint) |
| 461 | * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. |
| 462 | * The default is 0 (automatic for each asic). |
| 463 | */ |
| 464 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
| 465 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); |
| 466 | |
| 467 | /** |
| 468 | * DOC: pcie_lane_cap (uint) |
| 469 | * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. |
| 470 | * The default is 0 (automatic for each asic). |
| 471 | */ |
| 472 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); |
| 473 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); |
| 474 | |
| 475 | /** |
| 476 | * DOC: cg_mask (ullong) |
| 477 | * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in |
| 478 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffffffffffff (all enabled). |
| 479 | */ |
| 480 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
| 481 | module_param_named(cg_mask, amdgpu_cg_mask, ullong, 0444); |
| 482 | |
| 483 | /** |
| 484 | * DOC: pg_mask (uint) |
| 485 | * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in |
| 486 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). |
| 487 | */ |
| 488 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); |
| 489 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); |
| 490 | |
| 491 | /** |
| 492 | * DOC: sdma_phase_quantum (uint) |
| 493 | * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. |
| 494 | */ |
| 495 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); |
| 496 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); |
| 497 | |
| 498 | /** |
| 499 | * DOC: disable_cu (charp) |
| 500 | * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. |
| 501 | */ |
| 502 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
| 503 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); |
| 504 | |
| 505 | /** |
| 506 | * DOC: virtual_display (charp) |
| 507 | * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards |
| 508 | * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of |
| 509 | * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci |
| 510 | * device at 26:00.0. The default is NULL. |
| 511 | */ |
| 512 | MODULE_PARM_DESC(virtual_display, |
| 513 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); |
| 514 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
| 515 | |
| 516 | /** |
| 517 | * DOC: job_hang_limit (int) |
| 518 | * Set how much time allow a job hang and not drop it. The default is 0. |
| 519 | */ |
| 520 | MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); |
| 521 | module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); |
| 522 | |
| 523 | /** |
| 524 | * DOC: lbpw (int) |
| 525 | * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). |
| 526 | */ |
| 527 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); |
| 528 | module_param_named(lbpw, amdgpu_lbpw, int, 0444); |
| 529 | |
| 530 | MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); |
| 531 | module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); |
| 532 | |
| 533 | /** |
| 534 | * DOC: gpu_recovery (int) |
| 535 | * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). |
| 536 | */ |
| 537 | MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)"); |
| 538 | module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); |
| 539 | |
| 540 | /** |
| 541 | * DOC: emu_mode (int) |
| 542 | * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). |
| 543 | */ |
| 544 | MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); |
| 545 | module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); |
| 546 | |
| 547 | /** |
| 548 | * DOC: ras_enable (int) |
| 549 | * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) |
| 550 | */ |
| 551 | MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); |
| 552 | module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); |
| 553 | |
| 554 | /** |
| 555 | * DOC: ras_mask (uint) |
| 556 | * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 |
| 557 | * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h |
| 558 | */ |
| 559 | MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); |
| 560 | module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); |
| 561 | |
| 562 | /** |
| 563 | * DOC: timeout_fatal_disable (bool) |
| 564 | * Disable Watchdog timeout fatal error event |
| 565 | */ |
| 566 | MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)"); |
| 567 | module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644); |
| 568 | |
| 569 | /** |
| 570 | * DOC: timeout_period (uint) |
| 571 | * Modify the watchdog timeout max_cycles as (1 << period) |
| 572 | */ |
| 573 | MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)"); |
| 574 | module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); |
| 575 | |
| 576 | /** |
| 577 | * DOC: si_support (int) |
| 578 | * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, |
| 579 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, |
| 580 | * otherwise using amdgpu driver. |
| 581 | */ |
| 582 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 583 | |
| 584 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) |
| 585 | int amdgpu_si_support = 0; |
| 586 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); |
| 587 | #else |
| 588 | int amdgpu_si_support = 1; |
| 589 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); |
| 590 | #endif |
| 591 | |
| 592 | module_param_named(si_support, amdgpu_si_support, int, 0444); |
| 593 | #endif |
| 594 | |
| 595 | /** |
| 596 | * DOC: cik_support (int) |
| 597 | * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, |
| 598 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, |
| 599 | * otherwise using amdgpu driver. |
| 600 | */ |
| 601 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 602 | |
| 603 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) |
| 604 | int amdgpu_cik_support = 0; |
| 605 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); |
| 606 | #else |
| 607 | int amdgpu_cik_support = 1; |
| 608 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); |
| 609 | #endif |
| 610 | |
| 611 | module_param_named(cik_support, amdgpu_cik_support, int, 0444); |
| 612 | #endif |
| 613 | |
| 614 | /** |
| 615 | * DOC: smu_memory_pool_size (uint) |
| 616 | * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. |
| 617 | * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). |
| 618 | */ |
| 619 | MODULE_PARM_DESC(smu_memory_pool_size, |
| 620 | "reserve gtt for smu debug usage, 0 = disable," |
| 621 | "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); |
| 622 | module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); |
| 623 | |
| 624 | /** |
| 625 | * DOC: async_gfx_ring (int) |
| 626 | * It is used to enable gfx rings that could be configured with different prioritites or equal priorities |
| 627 | */ |
| 628 | MODULE_PARM_DESC(async_gfx_ring, |
| 629 | "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); |
| 630 | module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); |
| 631 | |
| 632 | /** |
| 633 | * DOC: mcbp (int) |
| 634 | * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) |
| 635 | */ |
| 636 | MODULE_PARM_DESC(mcbp, |
| 637 | "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); |
| 638 | module_param_named(mcbp, amdgpu_mcbp, int, 0444); |
| 639 | |
| 640 | /** |
| 641 | * DOC: discovery (int) |
| 642 | * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. |
| 643 | * (-1 = auto (default), 0 = disabled, 1 = enabled, 2 = use ip_discovery table from file) |
| 644 | */ |
| 645 | MODULE_PARM_DESC(discovery, |
| 646 | "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); |
| 647 | module_param_named(discovery, amdgpu_discovery, int, 0444); |
| 648 | |
| 649 | /** |
| 650 | * DOC: mes (int) |
| 651 | * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. |
| 652 | * (0 = disabled (default), 1 = enabled) |
| 653 | */ |
| 654 | MODULE_PARM_DESC(mes, |
| 655 | "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); |
| 656 | module_param_named(mes, amdgpu_mes, int, 0444); |
| 657 | |
| 658 | /** |
| 659 | * DOC: mes_kiq (int) |
| 660 | * Enable Micro Engine Scheduler KIQ. This is a new engine pipe for kiq. |
| 661 | * (0 = disabled (default), 1 = enabled) |
| 662 | */ |
| 663 | MODULE_PARM_DESC(mes_kiq, |
| 664 | "Enable Micro Engine Scheduler KIQ (0 = disabled (default), 1 = enabled)"); |
| 665 | module_param_named(mes_kiq, amdgpu_mes_kiq, int, 0444); |
| 666 | |
| 667 | /** |
| 668 | * DOC: noretry (int) |
| 669 | * Disable XNACK retry in the SQ by default on GFXv9 hardware. On ASICs that |
| 670 | * do not support per-process XNACK this also disables retry page faults. |
| 671 | * (0 = retry enabled, 1 = retry disabled, -1 auto (default)) |
| 672 | */ |
| 673 | MODULE_PARM_DESC(noretry, |
| 674 | "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))"); |
| 675 | module_param_named(noretry, amdgpu_noretry, int, 0644); |
| 676 | |
| 677 | /** |
| 678 | * DOC: force_asic_type (int) |
| 679 | * A non negative value used to specify the asic type for all supported GPUs. |
| 680 | */ |
| 681 | MODULE_PARM_DESC(force_asic_type, |
| 682 | "A non negative value used to specify the asic type for all supported GPUs"); |
| 683 | module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); |
| 684 | |
| 685 | /** |
| 686 | * DOC: use_xgmi_p2p (int) |
| 687 | * Enables/disables XGMI P2P interface (0 = disable, 1 = enable). |
| 688 | */ |
| 689 | MODULE_PARM_DESC(use_xgmi_p2p, |
| 690 | "Enable XGMI P2P interface (0 = disable; 1 = enable (default))"); |
| 691 | module_param_named(use_xgmi_p2p, amdgpu_use_xgmi_p2p, int, 0444); |
| 692 | |
| 693 | |
| 694 | #ifdef CONFIG_HSA_AMD |
| 695 | /** |
| 696 | * DOC: sched_policy (int) |
| 697 | * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. |
| 698 | * Setting 1 disables over-subscription. Setting 2 disables HWS and statically |
| 699 | * assigns queues to HQDs. |
| 700 | */ |
| 701 | int sched_policy = KFD_SCHED_POLICY_HWS; |
| 702 | module_param(sched_policy, int, 0444); |
| 703 | MODULE_PARM_DESC(sched_policy, |
| 704 | "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); |
| 705 | |
| 706 | /** |
| 707 | * DOC: hws_max_conc_proc (int) |
| 708 | * Maximum number of processes that HWS can schedule concurrently. The maximum is the |
| 709 | * number of VMIDs assigned to the HWS, which is also the default. |
| 710 | */ |
| 711 | int hws_max_conc_proc = -1; |
| 712 | module_param(hws_max_conc_proc, int, 0444); |
| 713 | MODULE_PARM_DESC(hws_max_conc_proc, |
| 714 | "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); |
| 715 | |
| 716 | /** |
| 717 | * DOC: cwsr_enable (int) |
| 718 | * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in |
| 719 | * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 |
| 720 | * disables it. |
| 721 | */ |
| 722 | int cwsr_enable = 1; |
| 723 | module_param(cwsr_enable, int, 0444); |
| 724 | MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); |
| 725 | |
| 726 | /** |
| 727 | * DOC: max_num_of_queues_per_device (int) |
| 728 | * Maximum number of queues per device. Valid setting is between 1 and 4096. Default |
| 729 | * is 4096. |
| 730 | */ |
| 731 | int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT4096; |
| 732 | module_param(max_num_of_queues_per_device, int, 0444); |
| 733 | MODULE_PARM_DESC(max_num_of_queues_per_device, |
| 734 | "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); |
| 735 | |
| 736 | /** |
| 737 | * DOC: send_sigterm (int) |
| 738 | * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm |
| 739 | * but just print errors on dmesg. Setting 1 enables sending sigterm. |
| 740 | */ |
| 741 | int send_sigterm; |
| 742 | module_param(send_sigterm, int, 0444); |
| 743 | MODULE_PARM_DESC(send_sigterm, |
| 744 | "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); |
| 745 | |
| 746 | /** |
| 747 | * DOC: debug_largebar (int) |
| 748 | * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar |
| 749 | * system. This limits the VRAM size reported to ROCm applications to the visible |
| 750 | * size, usually 256MB. |
| 751 | * Default value is 0, diabled. |
| 752 | */ |
| 753 | int debug_largebar; |
| 754 | module_param(debug_largebar, int, 0444); |
| 755 | MODULE_PARM_DESC(debug_largebar, |
| 756 | "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); |
| 757 | |
| 758 | /** |
| 759 | * DOC: ignore_crat (int) |
| 760 | * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT |
| 761 | * table to get information about AMD APUs. This option can serve as a workaround on |
| 762 | * systems with a broken CRAT table. |
| 763 | * |
| 764 | * Default is auto (according to asic type, iommu_v2, and crat table, to decide |
| 765 | * whether use CRAT) |
| 766 | */ |
| 767 | int ignore_crat; |
| 768 | module_param(ignore_crat, int, 0444); |
| 769 | MODULE_PARM_DESC(ignore_crat, |
| 770 | "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)"); |
| 771 | |
| 772 | /** |
| 773 | * DOC: halt_if_hws_hang (int) |
| 774 | * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. |
| 775 | * Setting 1 enables halt on hang. |
| 776 | */ |
| 777 | int halt_if_hws_hang; |
| 778 | module_param(halt_if_hws_hang, int, 0644); |
| 779 | MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); |
| 780 | |
| 781 | /** |
| 782 | * DOC: hws_gws_support(bool) |
| 783 | * Assume that HWS supports GWS barriers regardless of what firmware version |
| 784 | * check says. Default value: false (rely on MEC2 firmware version check). |
| 785 | */ |
| 786 | bool_Bool hws_gws_support; |
| 787 | module_param(hws_gws_support, bool, 0444); |
| 788 | MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)"); |
| 789 | |
| 790 | /** |
| 791 | * DOC: queue_preemption_timeout_ms (int) |
| 792 | * queue preemption timeout in ms (1 = Minimum, 9000 = default) |
| 793 | */ |
| 794 | int queue_preemption_timeout_ms = 9000; |
| 795 | module_param(queue_preemption_timeout_ms, int, 0644); |
| 796 | MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); |
| 797 | |
| 798 | /** |
| 799 | * DOC: debug_evictions(bool) |
| 800 | * Enable extra debug messages to help determine the cause of evictions |
| 801 | */ |
| 802 | bool_Bool debug_evictions; |
| 803 | module_param(debug_evictions, bool, 0644); |
| 804 | MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)"); |
| 805 | |
| 806 | /** |
| 807 | * DOC: no_system_mem_limit(bool) |
| 808 | * Disable system memory limit, to support multiple process shared memory |
| 809 | */ |
| 810 | bool_Bool no_system_mem_limit; |
| 811 | module_param(no_system_mem_limit, bool, 0644); |
| 812 | MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)"); |
| 813 | |
| 814 | /** |
| 815 | * DOC: no_queue_eviction_on_vm_fault (int) |
| 816 | * If set, process queues will not be evicted on gpuvm fault. This is to keep the wavefront context for debugging (0 = queue eviction, 1 = no queue eviction). The default is 0 (queue eviction). |
| 817 | */ |
| 818 | int amdgpu_no_queue_eviction_on_vm_fault = 0; |
| 819 | MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); |
| 820 | module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); |
| 821 | #endif |
| 822 | |
| 823 | /** |
| 824 | * DOC: pcie_p2p (bool) |
| 825 | * Enable PCIe P2P (requires large-BAR). Default value: true (on) |
| 826 | */ |
| 827 | #ifdef CONFIG_HSA_AMD_P2P |
| 828 | bool_Bool pcie_p2p = true1; |
| 829 | module_param(pcie_p2p, bool, 0444); |
| 830 | MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); |
| 831 | #endif |
| 832 | |
| 833 | /** |
| 834 | * DOC: dcfeaturemask (uint) |
| 835 | * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
| 836 | * The default is the current set of stable display features. |
| 837 | */ |
| 838 | MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); |
| 839 | module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); |
| 840 | |
| 841 | /** |
| 842 | * DOC: dcdebugmask (uint) |
| 843 | * Override display features enabled. See enum DC_DEBUG_MASK in drivers/gpu/drm/amd/include/amd_shared.h. |
| 844 | */ |
| 845 | MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))"); |
| 846 | module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444); |
| 847 | |
| 848 | MODULE_PARM_DESC(visualconfirm, "Visual confirm (0 = off (default), 1 = MPO, 5 = PSR)"); |
| 849 | module_param_named(visualconfirm, amdgpu_dc_visual_confirm, uint, 0444); |
| 850 | |
| 851 | /** |
| 852 | * DOC: abmlevel (uint) |
| 853 | * Override the default ABM (Adaptive Backlight Management) level used for DC |
| 854 | * enabled hardware. Requires DMCU to be supported and loaded. |
| 855 | * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by |
| 856 | * default. Values 1-4 control the maximum allowable brightness reduction via |
| 857 | * the ABM algorithm, with 1 being the least reduction and 4 being the most |
| 858 | * reduction. |
| 859 | * |
| 860 | * Defaults to 0, or disabled. Userspace can still override this level later |
| 861 | * after boot. |
| 862 | */ |
| 863 | uint amdgpu_dm_abm_level; |
| 864 | MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); |
| 865 | module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); |
| 866 | |
| 867 | int amdgpu_backlight = -1; |
| 868 | MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))"); |
| 869 | module_param_named(backlight, amdgpu_backlight, bint, 0444); |
| 870 | |
| 871 | /** |
| 872 | * DOC: tmz (int) |
| 873 | * Trusted Memory Zone (TMZ) is a method to protect data being written |
| 874 | * to or read from memory. |
| 875 | * |
| 876 | * The default value: 0 (off). TODO: change to auto till it is completed. |
| 877 | */ |
| 878 | MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)"); |
| 879 | module_param_named(tmz, amdgpu_tmz, int, 0444); |
| 880 | |
| 881 | /** |
| 882 | * DOC: freesync_video (uint) |
| 883 | * Enable the optimization to adjust front porch timing to achieve seamless |
| 884 | * mode change experience when setting a freesync supported mode for which full |
| 885 | * modeset is not needed. |
| 886 | * |
| 887 | * The Display Core will add a set of modes derived from the base FreeSync |
| 888 | * video mode into the corresponding connector's mode list based on commonly |
| 889 | * used refresh rates and VRR range of the connected display, when users enable |
| 890 | * this feature. From the userspace perspective, they can see a seamless mode |
| 891 | * change experience when the change between different refresh rates under the |
| 892 | * same resolution. Additionally, userspace applications such as Video playback |
| 893 | * can read this modeset list and change the refresh rate based on the video |
| 894 | * frame rate. Finally, the userspace can also derive an appropriate mode for a |
| 895 | * particular refresh rate based on the FreeSync Mode and add it to the |
| 896 | * connector's mode list. |
| 897 | * |
| 898 | * Note: This is an experimental feature. |
| 899 | * |
| 900 | * The default value: 0 (off). |
| 901 | */ |
| 902 | MODULE_PARM_DESC( |
| 903 | freesync_video, |
| 904 | "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)"); |
| 905 | module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444); |
| 906 | |
| 907 | /** |
| 908 | * DOC: reset_method (int) |
| 909 | * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco) |
| 910 | */ |
| 911 | MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)"); |
| 912 | module_param_named(reset_method, amdgpu_reset_method, int, 0444); |
| 913 | |
| 914 | /** |
| 915 | * DOC: bad_page_threshold (int) Bad page threshold is specifies the |
| 916 | * threshold value of faulty pages detected by RAS ECC, which may |
| 917 | * result in the GPU entering bad status when the number of total |
| 918 | * faulty pages by ECC exceeds the threshold value. |
| 919 | */ |
| 920 | MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement, -2 = ignore bad page threshold)"); |
| 921 | module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444); |
| 922 | |
| 923 | MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)"); |
| 924 | module_param_named(num_kcq, amdgpu_num_kcq, int, 0444); |
| 925 | |
| 926 | /** |
| 927 | * DOC: vcnfw_log (int) |
| 928 | * Enable vcnfw log output for debugging, the default is disabled. |
| 929 | */ |
| 930 | MODULE_PARM_DESC(vcnfw_log, "Enable vcnfw log(0 = disable (default value), 1 = enable)"); |
| 931 | module_param_named(vcnfw_log, amdgpu_vcnfw_log, int, 0444); |
| 932 | |
| 933 | /** |
| 934 | * DOC: sg_display (int) |
| 935 | * Disable S/G (scatter/gather) display (i.e., display from system memory). |
| 936 | * This option is only relevant on APUs. Set this option to 0 to disable |
| 937 | * S/G display if you experience flickering or other issues under memory |
| 938 | * pressure and report the issue. |
| 939 | */ |
| 940 | MODULE_PARM_DESC(sg_display, "S/G Display (-1 = auto (default), 0 = disable)"); |
| 941 | module_param_named(sg_display, amdgpu_sg_display, int, 0444); |
| 942 | |
| 943 | /** |
| 944 | * DOC: smu_pptable_id (int) |
| 945 | * Used to override pptable id. id = 0 use VBIOS pptable. |
| 946 | * id > 0 use the soft pptable with specicfied id. |
| 947 | */ |
| 948 | MODULE_PARM_DESC(smu_pptable_id, |
| 949 | "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)"); |
| 950 | module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444); |
| 951 | |
| 952 | /* These devices are not supported by amdgpu. |
| 953 | * They are supported by the mach64, r128, radeon drivers |
| 954 | */ |
| 955 | static const u16 amdgpu_unsupported_pciidlist[] = { |
| 956 | /* mach64 */ |
| 957 | 0x4354, |
| 958 | 0x4358, |
| 959 | 0x4554, |
| 960 | 0x4742, |
| 961 | 0x4744, |
| 962 | 0x4749, |
| 963 | 0x474C, |
| 964 | 0x474D, |
| 965 | 0x474E, |
| 966 | 0x474F, |
| 967 | 0x4750, |
| 968 | 0x4751, |
| 969 | 0x4752, |
| 970 | 0x4753, |
| 971 | 0x4754, |
| 972 | 0x4755, |
| 973 | 0x4756, |
| 974 | 0x4757, |
| 975 | 0x4758, |
| 976 | 0x4759, |
| 977 | 0x475A, |
| 978 | 0x4C42, |
| 979 | 0x4C44, |
| 980 | 0x4C47, |
| 981 | 0x4C49, |
| 982 | 0x4C4D, |
| 983 | 0x4C4E, |
| 984 | 0x4C50, |
| 985 | 0x4C51, |
| 986 | 0x4C52, |
| 987 | 0x4C53, |
| 988 | 0x5654, |
| 989 | 0x5655, |
| 990 | 0x5656, |
| 991 | /* r128 */ |
| 992 | 0x4c45, |
| 993 | 0x4c46, |
| 994 | 0x4d46, |
| 995 | 0x4d4c, |
| 996 | 0x5041, |
| 997 | 0x5042, |
| 998 | 0x5043, |
| 999 | 0x5044, |
| 1000 | 0x5045, |
| 1001 | 0x5046, |
| 1002 | 0x5047, |
| 1003 | 0x5048, |
| 1004 | 0x5049, |
| 1005 | 0x504A, |
| 1006 | 0x504B, |
| 1007 | 0x504C, |
| 1008 | 0x504D, |
| 1009 | 0x504E, |
| 1010 | 0x504F, |
| 1011 | 0x5050, |
| 1012 | 0x5051, |
| 1013 | 0x5052, |
| 1014 | 0x5053, |
| 1015 | 0x5054, |
| 1016 | 0x5055, |
| 1017 | 0x5056, |
| 1018 | 0x5057, |
| 1019 | 0x5058, |
| 1020 | 0x5245, |
| 1021 | 0x5246, |
| 1022 | 0x5247, |
| 1023 | 0x524b, |
| 1024 | 0x524c, |
| 1025 | 0x534d, |
| 1026 | 0x5446, |
| 1027 | 0x544C, |
| 1028 | 0x5452, |
| 1029 | /* radeon */ |
| 1030 | 0x3150, |
| 1031 | 0x3151, |
| 1032 | 0x3152, |
| 1033 | 0x3154, |
| 1034 | 0x3155, |
| 1035 | 0x3E50, |
| 1036 | 0x3E54, |
| 1037 | 0x4136, |
| 1038 | 0x4137, |
| 1039 | 0x4144, |
| 1040 | 0x4145, |
| 1041 | 0x4146, |
| 1042 | 0x4147, |
| 1043 | 0x4148, |
| 1044 | 0x4149, |
| 1045 | 0x414A, |
| 1046 | 0x414B, |
| 1047 | 0x4150, |
| 1048 | 0x4151, |
| 1049 | 0x4152, |
| 1050 | 0x4153, |
| 1051 | 0x4154, |
| 1052 | 0x4155, |
| 1053 | 0x4156, |
| 1054 | 0x4237, |
| 1055 | 0x4242, |
| 1056 | 0x4336, |
| 1057 | 0x4337, |
| 1058 | 0x4437, |
| 1059 | 0x4966, |
| 1060 | 0x4967, |
| 1061 | 0x4A48, |
| 1062 | 0x4A49, |
| 1063 | 0x4A4A, |
| 1064 | 0x4A4B, |
| 1065 | 0x4A4C, |
| 1066 | 0x4A4D, |
| 1067 | 0x4A4E, |
| 1068 | 0x4A4F, |
| 1069 | 0x4A50, |
| 1070 | 0x4A54, |
| 1071 | 0x4B48, |
| 1072 | 0x4B49, |
| 1073 | 0x4B4A, |
| 1074 | 0x4B4B, |
| 1075 | 0x4B4C, |
| 1076 | 0x4C57, |
| 1077 | 0x4C58, |
| 1078 | 0x4C59, |
| 1079 | 0x4C5A, |
| 1080 | 0x4C64, |
| 1081 | 0x4C66, |
| 1082 | 0x4C67, |
| 1083 | 0x4E44, |
| 1084 | 0x4E45, |
| 1085 | 0x4E46, |
| 1086 | 0x4E47, |
| 1087 | 0x4E48, |
| 1088 | 0x4E49, |
| 1089 | 0x4E4A, |
| 1090 | 0x4E4B, |
| 1091 | 0x4E50, |
| 1092 | 0x4E51, |
| 1093 | 0x4E52, |
| 1094 | 0x4E53, |
| 1095 | 0x4E54, |
| 1096 | 0x4E56, |
| 1097 | 0x5144, |
| 1098 | 0x5145, |
| 1099 | 0x5146, |
| 1100 | 0x5147, |
| 1101 | 0x5148, |
| 1102 | 0x514C, |
| 1103 | 0x514D, |
| 1104 | 0x5157, |
| 1105 | 0x5158, |
| 1106 | 0x5159, |
| 1107 | 0x515A, |
| 1108 | 0x515E, |
| 1109 | 0x5460, |
| 1110 | 0x5462, |
| 1111 | 0x5464, |
| 1112 | 0x5548, |
| 1113 | 0x5549, |
| 1114 | 0x554A, |
| 1115 | 0x554B, |
| 1116 | 0x554C, |
| 1117 | 0x554D, |
| 1118 | 0x554E, |
| 1119 | 0x554F, |
| 1120 | 0x5550, |
| 1121 | 0x5551, |
| 1122 | 0x5552, |
| 1123 | 0x5554, |
| 1124 | 0x564A, |
| 1125 | 0x564B, |
| 1126 | 0x564F, |
| 1127 | 0x5652, |
| 1128 | 0x5653, |
| 1129 | 0x5657, |
| 1130 | 0x5834, |
| 1131 | 0x5835, |
| 1132 | 0x5954, |
| 1133 | 0x5955, |
| 1134 | 0x5974, |
| 1135 | 0x5975, |
| 1136 | 0x5960, |
| 1137 | 0x5961, |
| 1138 | 0x5962, |
| 1139 | 0x5964, |
| 1140 | 0x5965, |
| 1141 | 0x5969, |
| 1142 | 0x5a41, |
| 1143 | 0x5a42, |
| 1144 | 0x5a61, |
| 1145 | 0x5a62, |
| 1146 | 0x5b60, |
| 1147 | 0x5b62, |
| 1148 | 0x5b63, |
| 1149 | 0x5b64, |
| 1150 | 0x5b65, |
| 1151 | 0x5c61, |
| 1152 | 0x5c63, |
| 1153 | 0x5d48, |
| 1154 | 0x5d49, |
| 1155 | 0x5d4a, |
| 1156 | 0x5d4c, |
| 1157 | 0x5d4d, |
| 1158 | 0x5d4e, |
| 1159 | 0x5d4f, |
| 1160 | 0x5d50, |
| 1161 | 0x5d52, |
| 1162 | 0x5d57, |
| 1163 | 0x5e48, |
| 1164 | 0x5e4a, |
| 1165 | 0x5e4b, |
| 1166 | 0x5e4c, |
| 1167 | 0x5e4d, |
| 1168 | 0x5e4f, |
| 1169 | 0x6700, |
| 1170 | 0x6701, |
| 1171 | 0x6702, |
| 1172 | 0x6703, |
| 1173 | 0x6704, |
| 1174 | 0x6705, |
| 1175 | 0x6706, |
| 1176 | 0x6707, |
| 1177 | 0x6708, |
| 1178 | 0x6709, |
| 1179 | 0x6718, |
| 1180 | 0x6719, |
| 1181 | 0x671c, |
| 1182 | 0x671d, |
| 1183 | 0x671f, |
| 1184 | 0x6720, |
| 1185 | 0x6721, |
| 1186 | 0x6722, |
| 1187 | 0x6723, |
| 1188 | 0x6724, |
| 1189 | 0x6725, |
| 1190 | 0x6726, |
| 1191 | 0x6727, |
| 1192 | 0x6728, |
| 1193 | 0x6729, |
| 1194 | 0x6738, |
| 1195 | 0x6739, |
| 1196 | 0x673e, |
| 1197 | 0x6740, |
| 1198 | 0x6741, |
| 1199 | 0x6742, |
| 1200 | 0x6743, |
| 1201 | 0x6744, |
| 1202 | 0x6745, |
| 1203 | 0x6746, |
| 1204 | 0x6747, |
| 1205 | 0x6748, |
| 1206 | 0x6749, |
| 1207 | 0x674A, |
| 1208 | 0x6750, |
| 1209 | 0x6751, |
| 1210 | 0x6758, |
| 1211 | 0x6759, |
| 1212 | 0x675B, |
| 1213 | 0x675D, |
| 1214 | 0x675F, |
| 1215 | 0x6760, |
| 1216 | 0x6761, |
| 1217 | 0x6762, |
| 1218 | 0x6763, |
| 1219 | 0x6764, |
| 1220 | 0x6765, |
| 1221 | 0x6766, |
| 1222 | 0x6767, |
| 1223 | 0x6768, |
| 1224 | 0x6770, |
| 1225 | 0x6771, |
| 1226 | 0x6772, |
| 1227 | 0x6778, |
| 1228 | 0x6779, |
| 1229 | 0x677B, |
| 1230 | 0x6840, |
| 1231 | 0x6841, |
| 1232 | 0x6842, |
| 1233 | 0x6843, |
| 1234 | 0x6849, |
| 1235 | 0x684C, |
| 1236 | 0x6850, |
| 1237 | 0x6858, |
| 1238 | 0x6859, |
| 1239 | 0x6880, |
| 1240 | 0x6888, |
| 1241 | 0x6889, |
| 1242 | 0x688A, |
| 1243 | 0x688C, |
| 1244 | 0x688D, |
| 1245 | 0x6898, |
| 1246 | 0x6899, |
| 1247 | 0x689b, |
| 1248 | 0x689c, |
| 1249 | 0x689d, |
| 1250 | 0x689e, |
| 1251 | 0x68a0, |
| 1252 | 0x68a1, |
| 1253 | 0x68a8, |
| 1254 | 0x68a9, |
| 1255 | 0x68b0, |
| 1256 | 0x68b8, |
| 1257 | 0x68b9, |
| 1258 | 0x68ba, |
| 1259 | 0x68be, |
| 1260 | 0x68bf, |
| 1261 | 0x68c0, |
| 1262 | 0x68c1, |
| 1263 | 0x68c7, |
| 1264 | 0x68c8, |
| 1265 | 0x68c9, |
| 1266 | 0x68d8, |
| 1267 | 0x68d9, |
| 1268 | 0x68da, |
| 1269 | 0x68de, |
| 1270 | 0x68e0, |
| 1271 | 0x68e1, |
| 1272 | 0x68e4, |
| 1273 | 0x68e5, |
| 1274 | 0x68e8, |
| 1275 | 0x68e9, |
| 1276 | 0x68f1, |
| 1277 | 0x68f2, |
| 1278 | 0x68f8, |
| 1279 | 0x68f9, |
| 1280 | 0x68fa, |
| 1281 | 0x68fe, |
| 1282 | 0x7100, |
| 1283 | 0x7101, |
| 1284 | 0x7102, |
| 1285 | 0x7103, |
| 1286 | 0x7104, |
| 1287 | 0x7105, |
| 1288 | 0x7106, |
| 1289 | 0x7108, |
| 1290 | 0x7109, |
| 1291 | 0x710A, |
| 1292 | 0x710B, |
| 1293 | 0x710C, |
| 1294 | 0x710E, |
| 1295 | 0x710F, |
| 1296 | 0x7140, |
| 1297 | 0x7141, |
| 1298 | 0x7142, |
| 1299 | 0x7143, |
| 1300 | 0x7144, |
| 1301 | 0x7145, |
| 1302 | 0x7146, |
| 1303 | 0x7147, |
| 1304 | 0x7149, |
| 1305 | 0x714A, |
| 1306 | 0x714B, |
| 1307 | 0x714C, |
| 1308 | 0x714D, |
| 1309 | 0x714E, |
| 1310 | 0x714F, |
| 1311 | 0x7151, |
| 1312 | 0x7152, |
| 1313 | 0x7153, |
| 1314 | 0x715E, |
| 1315 | 0x715F, |
| 1316 | 0x7180, |
| 1317 | 0x7181, |
| 1318 | 0x7183, |
| 1319 | 0x7186, |
| 1320 | 0x7187, |
| 1321 | 0x7188, |
| 1322 | 0x718A, |
| 1323 | 0x718B, |
| 1324 | 0x718C, |
| 1325 | 0x718D, |
| 1326 | 0x718F, |
| 1327 | 0x7193, |
| 1328 | 0x7196, |
| 1329 | 0x719B, |
| 1330 | 0x719F, |
| 1331 | 0x71C0, |
| 1332 | 0x71C1, |
| 1333 | 0x71C2, |
| 1334 | 0x71C3, |
| 1335 | 0x71C4, |
| 1336 | 0x71C5, |
| 1337 | 0x71C6, |
| 1338 | 0x71C7, |
| 1339 | 0x71CD, |
| 1340 | 0x71CE, |
| 1341 | 0x71D2, |
| 1342 | 0x71D4, |
| 1343 | 0x71D5, |
| 1344 | 0x71D6, |
| 1345 | 0x71DA, |
| 1346 | 0x71DE, |
| 1347 | 0x7200, |
| 1348 | 0x7210, |
| 1349 | 0x7211, |
| 1350 | 0x7240, |
| 1351 | 0x7243, |
| 1352 | 0x7244, |
| 1353 | 0x7245, |
| 1354 | 0x7246, |
| 1355 | 0x7247, |
| 1356 | 0x7248, |
| 1357 | 0x7249, |
| 1358 | 0x724A, |
| 1359 | 0x724B, |
| 1360 | 0x724C, |
| 1361 | 0x724D, |
| 1362 | 0x724E, |
| 1363 | 0x724F, |
| 1364 | 0x7280, |
| 1365 | 0x7281, |
| 1366 | 0x7283, |
| 1367 | 0x7284, |
| 1368 | 0x7287, |
| 1369 | 0x7288, |
| 1370 | 0x7289, |
| 1371 | 0x728B, |
| 1372 | 0x728C, |
| 1373 | 0x7290, |
| 1374 | 0x7291, |
| 1375 | 0x7293, |
| 1376 | 0x7297, |
| 1377 | 0x7834, |
| 1378 | 0x7835, |
| 1379 | 0x791e, |
| 1380 | 0x791f, |
| 1381 | 0x793f, |
| 1382 | 0x7941, |
| 1383 | 0x7942, |
| 1384 | 0x796c, |
| 1385 | 0x796d, |
| 1386 | 0x796e, |
| 1387 | 0x796f, |
| 1388 | 0x9400, |
| 1389 | 0x9401, |
| 1390 | 0x9402, |
| 1391 | 0x9403, |
| 1392 | 0x9405, |
| 1393 | 0x940A, |
| 1394 | 0x940B, |
| 1395 | 0x940F, |
| 1396 | 0x94A0, |
| 1397 | 0x94A1, |
| 1398 | 0x94A3, |
| 1399 | 0x94B1, |
| 1400 | 0x94B3, |
| 1401 | 0x94B4, |
| 1402 | 0x94B5, |
| 1403 | 0x94B9, |
| 1404 | 0x9440, |
| 1405 | 0x9441, |
| 1406 | 0x9442, |
| 1407 | 0x9443, |
| 1408 | 0x9444, |
| 1409 | 0x9446, |
| 1410 | 0x944A, |
| 1411 | 0x944B, |
| 1412 | 0x944C, |
| 1413 | 0x944E, |
| 1414 | 0x9450, |
| 1415 | 0x9452, |
| 1416 | 0x9456, |
| 1417 | 0x945A, |
| 1418 | 0x945B, |
| 1419 | 0x945E, |
| 1420 | 0x9460, |
| 1421 | 0x9462, |
| 1422 | 0x946A, |
| 1423 | 0x946B, |
| 1424 | 0x947A, |
| 1425 | 0x947B, |
| 1426 | 0x9480, |
| 1427 | 0x9487, |
| 1428 | 0x9488, |
| 1429 | 0x9489, |
| 1430 | 0x948A, |
| 1431 | 0x948F, |
| 1432 | 0x9490, |
| 1433 | 0x9491, |
| 1434 | 0x9495, |
| 1435 | 0x9498, |
| 1436 | 0x949C, |
| 1437 | 0x949E, |
| 1438 | 0x949F, |
| 1439 | 0x94C0, |
| 1440 | 0x94C1, |
| 1441 | 0x94C3, |
| 1442 | 0x94C4, |
| 1443 | 0x94C5, |
| 1444 | 0x94C6, |
| 1445 | 0x94C7, |
| 1446 | 0x94C8, |
| 1447 | 0x94C9, |
| 1448 | 0x94CB, |
| 1449 | 0x94CC, |
| 1450 | 0x94CD, |
| 1451 | 0x9500, |
| 1452 | 0x9501, |
| 1453 | 0x9504, |
| 1454 | 0x9505, |
| 1455 | 0x9506, |
| 1456 | 0x9507, |
| 1457 | 0x9508, |
| 1458 | 0x9509, |
| 1459 | 0x950F, |
| 1460 | 0x9511, |
| 1461 | 0x9515, |
| 1462 | 0x9517, |
| 1463 | 0x9519, |
| 1464 | 0x9540, |
| 1465 | 0x9541, |
| 1466 | 0x9542, |
| 1467 | 0x954E, |
| 1468 | 0x954F, |
| 1469 | 0x9552, |
| 1470 | 0x9553, |
| 1471 | 0x9555, |
| 1472 | 0x9557, |
| 1473 | 0x955f, |
| 1474 | 0x9580, |
| 1475 | 0x9581, |
| 1476 | 0x9583, |
| 1477 | 0x9586, |
| 1478 | 0x9587, |
| 1479 | 0x9588, |
| 1480 | 0x9589, |
| 1481 | 0x958A, |
| 1482 | 0x958B, |
| 1483 | 0x958C, |
| 1484 | 0x958D, |
| 1485 | 0x958E, |
| 1486 | 0x958F, |
| 1487 | 0x9590, |
| 1488 | 0x9591, |
| 1489 | 0x9593, |
| 1490 | 0x9595, |
| 1491 | 0x9596, |
| 1492 | 0x9597, |
| 1493 | 0x9598, |
| 1494 | 0x9599, |
| 1495 | 0x959B, |
| 1496 | 0x95C0, |
| 1497 | 0x95C2, |
| 1498 | 0x95C4, |
| 1499 | 0x95C5, |
| 1500 | 0x95C6, |
| 1501 | 0x95C7, |
| 1502 | 0x95C9, |
| 1503 | 0x95CC, |
| 1504 | 0x95CD, |
| 1505 | 0x95CE, |
| 1506 | 0x95CF, |
| 1507 | 0x9610, |
| 1508 | 0x9611, |
| 1509 | 0x9612, |
| 1510 | 0x9613, |
| 1511 | 0x9614, |
| 1512 | 0x9615, |
| 1513 | 0x9616, |
| 1514 | 0x9640, |
| 1515 | 0x9641, |
| 1516 | 0x9642, |
| 1517 | 0x9643, |
| 1518 | 0x9644, |
| 1519 | 0x9645, |
| 1520 | 0x9647, |
| 1521 | 0x9648, |
| 1522 | 0x9649, |
| 1523 | 0x964a, |
| 1524 | 0x964b, |
| 1525 | 0x964c, |
| 1526 | 0x964e, |
| 1527 | 0x964f, |
| 1528 | 0x9710, |
| 1529 | 0x9711, |
| 1530 | 0x9712, |
| 1531 | 0x9713, |
| 1532 | 0x9714, |
| 1533 | 0x9715, |
| 1534 | 0x9802, |
| 1535 | 0x9803, |
| 1536 | 0x9804, |
| 1537 | 0x9805, |
| 1538 | 0x9806, |
| 1539 | 0x9807, |
| 1540 | 0x9808, |
| 1541 | 0x9809, |
| 1542 | 0x980A, |
| 1543 | 0x9900, |
| 1544 | 0x9901, |
| 1545 | 0x9903, |
| 1546 | 0x9904, |
| 1547 | 0x9905, |
| 1548 | 0x9906, |
| 1549 | 0x9907, |
| 1550 | 0x9908, |
| 1551 | 0x9909, |
| 1552 | 0x990A, |
| 1553 | 0x990B, |
| 1554 | 0x990C, |
| 1555 | 0x990D, |
| 1556 | 0x990E, |
| 1557 | 0x990F, |
| 1558 | 0x9910, |
| 1559 | 0x9913, |
| 1560 | 0x9917, |
| 1561 | 0x9918, |
| 1562 | 0x9919, |
| 1563 | 0x9990, |
| 1564 | 0x9991, |
| 1565 | 0x9992, |
| 1566 | 0x9993, |
| 1567 | 0x9994, |
| 1568 | 0x9995, |
| 1569 | 0x9996, |
| 1570 | 0x9997, |
| 1571 | 0x9998, |
| 1572 | 0x9999, |
| 1573 | 0x999A, |
| 1574 | 0x999B, |
| 1575 | 0x999C, |
| 1576 | 0x999D, |
| 1577 | 0x99A0, |
| 1578 | 0x99A2, |
| 1579 | 0x99A4, |
| 1580 | /* radeon secondary ids */ |
| 1581 | 0x3171, |
| 1582 | 0x3e70, |
| 1583 | 0x4164, |
| 1584 | 0x4165, |
| 1585 | 0x4166, |
| 1586 | 0x4168, |
| 1587 | 0x4170, |
| 1588 | 0x4171, |
| 1589 | 0x4172, |
| 1590 | 0x4173, |
| 1591 | 0x496e, |
| 1592 | 0x4a69, |
| 1593 | 0x4a6a, |
| 1594 | 0x4a6b, |
| 1595 | 0x4a70, |
| 1596 | 0x4a74, |
| 1597 | 0x4b69, |
| 1598 | 0x4b6b, |
| 1599 | 0x4b6c, |
| 1600 | 0x4c6e, |
| 1601 | 0x4e64, |
| 1602 | 0x4e65, |
| 1603 | 0x4e66, |
| 1604 | 0x4e67, |
| 1605 | 0x4e68, |
| 1606 | 0x4e69, |
| 1607 | 0x4e6a, |
| 1608 | 0x4e71, |
| 1609 | 0x4f73, |
| 1610 | 0x5569, |
| 1611 | 0x556b, |
| 1612 | 0x556d, |
| 1613 | 0x556f, |
| 1614 | 0x5571, |
| 1615 | 0x5854, |
| 1616 | 0x5874, |
| 1617 | 0x5940, |
| 1618 | 0x5941, |
| 1619 | 0x5b70, |
| 1620 | 0x5b72, |
| 1621 | 0x5b73, |
| 1622 | 0x5b74, |
| 1623 | 0x5b75, |
| 1624 | 0x5d44, |
| 1625 | 0x5d45, |
| 1626 | 0x5d6d, |
| 1627 | 0x5d6f, |
| 1628 | 0x5d72, |
| 1629 | 0x5d77, |
| 1630 | 0x5e6b, |
| 1631 | 0x5e6d, |
| 1632 | 0x7120, |
| 1633 | 0x7124, |
| 1634 | 0x7129, |
| 1635 | 0x712e, |
| 1636 | 0x712f, |
| 1637 | 0x7162, |
| 1638 | 0x7163, |
| 1639 | 0x7166, |
| 1640 | 0x7167, |
| 1641 | 0x7172, |
| 1642 | 0x7173, |
| 1643 | 0x71a0, |
| 1644 | 0x71a1, |
| 1645 | 0x71a3, |
| 1646 | 0x71a7, |
| 1647 | 0x71bb, |
| 1648 | 0x71e0, |
| 1649 | 0x71e1, |
| 1650 | 0x71e2, |
| 1651 | 0x71e6, |
| 1652 | 0x71e7, |
| 1653 | 0x71f2, |
| 1654 | 0x7269, |
| 1655 | 0x726b, |
| 1656 | 0x726e, |
| 1657 | 0x72a0, |
| 1658 | 0x72a8, |
| 1659 | 0x72b1, |
| 1660 | 0x72b3, |
| 1661 | 0x793f, |
| 1662 | }; |
| 1663 | |
| 1664 | static const struct pci_device_id pciidlist[] = { |
| 1665 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 1666 | {0x1002, 0x6780, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1667 | {0x1002, 0x6784, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1668 | {0x1002, 0x6788, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1669 | {0x1002, 0x678A, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1670 | {0x1002, 0x6790, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1671 | {0x1002, 0x6791, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1672 | {0x1002, 0x6792, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1673 | {0x1002, 0x6798, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1674 | {0x1002, 0x6799, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1675 | {0x1002, 0x679A, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1676 | {0x1002, 0x679B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1677 | {0x1002, 0x679E, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1678 | {0x1002, 0x679F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TAHITI}, |
| 1679 | {0x1002, 0x6800, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, |
| 1680 | {0x1002, 0x6801, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, |
| 1681 | {0x1002, 0x6802, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, |
| 1682 | {0x1002, 0x6806, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1683 | {0x1002, 0x6808, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1684 | {0x1002, 0x6809, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1685 | {0x1002, 0x6810, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1686 | {0x1002, 0x6811, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1687 | {0x1002, 0x6816, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1688 | {0x1002, 0x6817, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1689 | {0x1002, 0x6818, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1690 | {0x1002, 0x6819, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_PITCAIRN}, |
| 1691 | {0x1002, 0x6600, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1692 | {0x1002, 0x6601, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1693 | {0x1002, 0x6602, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1694 | {0x1002, 0x6603, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1695 | {0x1002, 0x6604, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1696 | {0x1002, 0x6605, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1697 | {0x1002, 0x6606, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1698 | {0x1002, 0x6607, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1699 | {0x1002, 0x6608, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND}, |
| 1700 | {0x1002, 0x6610, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND}, |
| 1701 | {0x1002, 0x6611, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND}, |
| 1702 | {0x1002, 0x6613, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND}, |
| 1703 | {0x1002, 0x6617, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1704 | {0x1002, 0x6620, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1705 | {0x1002, 0x6621, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1706 | {0x1002, 0x6623, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, |
| 1707 | {0x1002, 0x6631, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_OLAND}, |
| 1708 | {0x1002, 0x6820, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1709 | {0x1002, 0x6821, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1710 | {0x1002, 0x6822, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1711 | {0x1002, 0x6823, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1712 | {0x1002, 0x6824, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1713 | {0x1002, 0x6825, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1714 | {0x1002, 0x6826, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1715 | {0x1002, 0x6827, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1716 | {0x1002, 0x6828, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1717 | {0x1002, 0x6829, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1718 | {0x1002, 0x682A, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1719 | {0x1002, 0x682B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1720 | {0x1002, 0x682C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1721 | {0x1002, 0x682D, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1722 | {0x1002, 0x682F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1723 | {0x1002, 0x6830, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1724 | {0x1002, 0x6831, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, |
| 1725 | {0x1002, 0x6835, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1726 | {0x1002, 0x6837, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1727 | {0x1002, 0x6838, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1728 | {0x1002, 0x6839, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1729 | {0x1002, 0x683B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1730 | {0x1002, 0x683D, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1731 | {0x1002, 0x683F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VERDE}, |
| 1732 | {0x1002, 0x6660, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 1733 | {0x1002, 0x6663, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 1734 | {0x1002, 0x6664, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 1735 | {0x1002, 0x6665, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 1736 | {0x1002, 0x6667, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 1737 | {0x1002, 0x666F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, |
| 1738 | #endif |
| 1739 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 1740 | /* Kaveri */ |
| 1741 | {0x1002, 0x1304, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1742 | {0x1002, 0x1305, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1743 | {0x1002, 0x1306, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1744 | {0x1002, 0x1307, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1745 | {0x1002, 0x1309, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1746 | {0x1002, 0x130A, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1747 | {0x1002, 0x130B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1748 | {0x1002, 0x130C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1749 | {0x1002, 0x130D, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1750 | {0x1002, 0x130E, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1751 | {0x1002, 0x130F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1752 | {0x1002, 0x1310, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1753 | {0x1002, 0x1311, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1754 | {0x1002, 0x1312, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1755 | {0x1002, 0x1313, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1756 | {0x1002, 0x1315, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1757 | {0x1002, 0x1316, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1758 | {0x1002, 0x1317, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1759 | {0x1002, 0x1318, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1760 | {0x1002, 0x131B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1761 | {0x1002, 0x131C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1762 | {0x1002, 0x131D, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KAVERI|AMD_IS_APU}, |
| 1763 | /* Bonaire */ |
| 1764 | {0x1002, 0x6640, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 1765 | {0x1002, 0x6641, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 1766 | {0x1002, 0x6646, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 1767 | {0x1002, 0x6647, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
| 1768 | {0x1002, 0x6649, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1769 | {0x1002, 0x6650, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1770 | {0x1002, 0x6651, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1771 | {0x1002, 0x6658, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1772 | {0x1002, 0x665c, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1773 | {0x1002, 0x665d, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1774 | {0x1002, 0x665f, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BONAIRE}, |
| 1775 | /* Hawaii */ |
| 1776 | {0x1002, 0x67A0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1777 | {0x1002, 0x67A1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1778 | {0x1002, 0x67A2, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1779 | {0x1002, 0x67A8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1780 | {0x1002, 0x67A9, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1781 | {0x1002, 0x67AA, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1782 | {0x1002, 0x67B0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1783 | {0x1002, 0x67B1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1784 | {0x1002, 0x67B8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1785 | {0x1002, 0x67B9, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1786 | {0x1002, 0x67BA, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1787 | {0x1002, 0x67BE, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_HAWAII}, |
| 1788 | /* Kabini */ |
| 1789 | {0x1002, 0x9830, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1790 | {0x1002, 0x9831, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1791 | {0x1002, 0x9832, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1792 | {0x1002, 0x9833, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1793 | {0x1002, 0x9834, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1794 | {0x1002, 0x9835, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1795 | {0x1002, 0x9836, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1796 | {0x1002, 0x9837, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1797 | {0x1002, 0x9838, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1798 | {0x1002, 0x9839, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1799 | {0x1002, 0x983a, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1800 | {0x1002, 0x983b, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1801 | {0x1002, 0x983c, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1802 | {0x1002, 0x983d, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1803 | {0x1002, 0x983e, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1804 | {0x1002, 0x983f, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_KABINI|AMD_IS_APU}, |
| 1805 | /* mullins */ |
| 1806 | {0x1002, 0x9850, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1807 | {0x1002, 0x9851, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1808 | {0x1002, 0x9852, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1809 | {0x1002, 0x9853, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1810 | {0x1002, 0x9854, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1811 | {0x1002, 0x9855, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1812 | {0x1002, 0x9856, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1813 | {0x1002, 0x9857, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1814 | {0x1002, 0x9858, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1815 | {0x1002, 0x9859, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1816 | {0x1002, 0x985A, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1817 | {0x1002, 0x985B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1818 | {0x1002, 0x985C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1819 | {0x1002, 0x985D, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1820 | {0x1002, 0x985E, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1821 | {0x1002, 0x985F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
| 1822 | #endif |
| 1823 | /* topaz */ |
| 1824 | {0x1002, 0x6900, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TOPAZ}, |
| 1825 | {0x1002, 0x6901, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TOPAZ}, |
| 1826 | {0x1002, 0x6902, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TOPAZ}, |
| 1827 | {0x1002, 0x6903, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TOPAZ}, |
| 1828 | {0x1002, 0x6907, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TOPAZ}, |
| 1829 | /* tonga */ |
| 1830 | {0x1002, 0x6920, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1831 | {0x1002, 0x6921, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1832 | {0x1002, 0x6928, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1833 | {0x1002, 0x6929, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1834 | {0x1002, 0x692B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1835 | {0x1002, 0x692F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1836 | {0x1002, 0x6930, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1837 | {0x1002, 0x6938, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1838 | {0x1002, 0x6939, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_TONGA}, |
| 1839 | /* fiji */ |
| 1840 | {0x1002, 0x7300, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_FIJI}, |
| 1841 | {0x1002, 0x730F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_FIJI}, |
| 1842 | /* carrizo */ |
| 1843 | {0x1002, 0x9870, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 1844 | {0x1002, 0x9874, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 1845 | {0x1002, 0x9875, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 1846 | {0x1002, 0x9876, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 1847 | {0x1002, 0x9877, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
| 1848 | /* stoney */ |
| 1849 | {0x1002, 0x98E4, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_STONEY|AMD_IS_APU}, |
| 1850 | /* Polaris11 */ |
| 1851 | {0x1002, 0x67E0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1852 | {0x1002, 0x67E3, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1853 | {0x1002, 0x67E8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1854 | {0x1002, 0x67EB, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1855 | {0x1002, 0x67EF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1856 | {0x1002, 0x67FF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1857 | {0x1002, 0x67E1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1858 | {0x1002, 0x67E7, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1859 | {0x1002, 0x67E9, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS11}, |
| 1860 | /* Polaris10 */ |
| 1861 | {0x1002, 0x67C0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1862 | {0x1002, 0x67C1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1863 | {0x1002, 0x67C2, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1864 | {0x1002, 0x67C4, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1865 | {0x1002, 0x67C7, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1866 | {0x1002, 0x67D0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1867 | {0x1002, 0x67DF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1868 | {0x1002, 0x67C8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1869 | {0x1002, 0x67C9, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1870 | {0x1002, 0x67CA, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1871 | {0x1002, 0x67CC, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1872 | {0x1002, 0x67CF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1873 | {0x1002, 0x6FDF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS10}, |
| 1874 | /* Polaris12 */ |
| 1875 | {0x1002, 0x6980, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1876 | {0x1002, 0x6981, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1877 | {0x1002, 0x6985, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1878 | {0x1002, 0x6986, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1879 | {0x1002, 0x6987, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1880 | {0x1002, 0x6995, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1881 | {0x1002, 0x6997, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1882 | {0x1002, 0x699F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_POLARIS12}, |
| 1883 | /* VEGAM */ |
| 1884 | {0x1002, 0x694C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGAM}, |
| 1885 | {0x1002, 0x694E, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGAM}, |
| 1886 | {0x1002, 0x694F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGAM}, |
| 1887 | /* Vega 10 */ |
| 1888 | {0x1002, 0x6860, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1889 | {0x1002, 0x6861, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1890 | {0x1002, 0x6862, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1891 | {0x1002, 0x6863, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1892 | {0x1002, 0x6864, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1893 | {0x1002, 0x6867, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1894 | {0x1002, 0x6868, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1895 | {0x1002, 0x6869, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1896 | {0x1002, 0x686a, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1897 | {0x1002, 0x686b, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1898 | {0x1002, 0x686c, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1899 | {0x1002, 0x686d, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1900 | {0x1002, 0x686e, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1901 | {0x1002, 0x686f, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1902 | {0x1002, 0x687f, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA10}, |
| 1903 | /* Vega 12 */ |
| 1904 | {0x1002, 0x69A0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA12}, |
| 1905 | {0x1002, 0x69A1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA12}, |
| 1906 | {0x1002, 0x69A2, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA12}, |
| 1907 | {0x1002, 0x69A3, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA12}, |
| 1908 | {0x1002, 0x69AF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA12}, |
| 1909 | /* Vega 20 */ |
| 1910 | {0x1002, 0x66A0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1911 | {0x1002, 0x66A1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1912 | {0x1002, 0x66A2, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1913 | {0x1002, 0x66A3, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1914 | {0x1002, 0x66A4, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1915 | {0x1002, 0x66A7, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1916 | {0x1002, 0x66AF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VEGA20}, |
| 1917 | /* Raven */ |
| 1918 | {0x1002, 0x15dd, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
| 1919 | {0x1002, 0x15d8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
| 1920 | /* Arcturus */ |
| 1921 | {0x1002, 0x738C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ARCTURUS}, |
| 1922 | {0x1002, 0x7388, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ARCTURUS}, |
| 1923 | {0x1002, 0x738E, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ARCTURUS}, |
| 1924 | {0x1002, 0x7390, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ARCTURUS}, |
| 1925 | /* Navi10 */ |
| 1926 | {0x1002, 0x7310, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1927 | {0x1002, 0x7312, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1928 | {0x1002, 0x7318, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1929 | {0x1002, 0x7319, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1930 | {0x1002, 0x731A, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1931 | {0x1002, 0x731B, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1932 | {0x1002, 0x731E, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1933 | {0x1002, 0x731F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI10}, |
| 1934 | /* Navi14 */ |
| 1935 | {0x1002, 0x7340, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI14}, |
| 1936 | {0x1002, 0x7341, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI14}, |
| 1937 | {0x1002, 0x7347, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI14}, |
| 1938 | {0x1002, 0x734F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI14}, |
| 1939 | |
| 1940 | /* Renoir */ |
| 1941 | {0x1002, 0x15E7, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1942 | {0x1002, 0x1636, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1943 | {0x1002, 0x1638, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1944 | {0x1002, 0x164C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
| 1945 | |
| 1946 | /* Navi12 */ |
| 1947 | {0x1002, 0x7360, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI12}, |
| 1948 | {0x1002, 0x7362, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVI12}, |
| 1949 | |
| 1950 | /* Sienna_Cichlid */ |
| 1951 | {0x1002, 0x73A0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1952 | {0x1002, 0x73A1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1953 | {0x1002, 0x73A2, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1954 | {0x1002, 0x73A3, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1955 | {0x1002, 0x73A5, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1956 | {0x1002, 0x73A8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1957 | {0x1002, 0x73A9, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1958 | {0x1002, 0x73AB, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1959 | {0x1002, 0x73AC, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1960 | {0x1002, 0x73AD, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1961 | {0x1002, 0x73AE, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1962 | {0x1002, 0x73AF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1963 | {0x1002, 0x73BF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_SIENNA_CICHLID}, |
| 1964 | |
| 1965 | /* Van Gogh */ |
| 1966 | {0x1002, 0x1435, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VANGOGH|AMD_IS_APU}, |
| 1967 | {0x1002, 0x163F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_VANGOGH|AMD_IS_APU}, |
| 1968 | |
| 1969 | /* Yellow Carp */ |
| 1970 | {0x1002, 0x164D, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, |
| 1971 | {0x1002, 0x1681, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU}, |
| 1972 | |
| 1973 | /* Navy_Flounder */ |
| 1974 | {0x1002, 0x73C0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1975 | {0x1002, 0x73C1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1976 | {0x1002, 0x73C3, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1977 | {0x1002, 0x73DA, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1978 | {0x1002, 0x73DB, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1979 | {0x1002, 0x73DC, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1980 | {0x1002, 0x73DD, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1981 | {0x1002, 0x73DE, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1982 | {0x1002, 0x73DF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_NAVY_FLOUNDER}, |
| 1983 | |
| 1984 | /* DIMGREY_CAVEFISH */ |
| 1985 | {0x1002, 0x73E0, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1986 | {0x1002, 0x73E1, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1987 | {0x1002, 0x73E2, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1988 | {0x1002, 0x73E3, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1989 | {0x1002, 0x73E8, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1990 | {0x1002, 0x73E9, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1991 | {0x1002, 0x73EA, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1992 | {0x1002, 0x73EB, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1993 | {0x1002, 0x73EC, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1994 | {0x1002, 0x73ED, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1995 | {0x1002, 0x73EF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1996 | {0x1002, 0x73FF, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_DIMGREY_CAVEFISH}, |
| 1997 | |
| 1998 | /* Aldebaran */ |
| 1999 | {0x1002, 0x7408, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ALDEBARAN}, |
| 2000 | {0x1002, 0x740C, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ALDEBARAN}, |
| 2001 | {0x1002, 0x740F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ALDEBARAN}, |
| 2002 | {0x1002, 0x7410, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_ALDEBARAN}, |
| 2003 | |
| 2004 | /* CYAN_SKILLFISH */ |
| 2005 | {0x1002, 0x13FE, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, |
| 2006 | {0x1002, 0x143F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU}, |
| 2007 | |
| 2008 | /* BEIGE_GOBY */ |
| 2009 | {0x1002, 0x7420, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BEIGE_GOBY}, |
| 2010 | {0x1002, 0x7421, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BEIGE_GOBY}, |
| 2011 | {0x1002, 0x7422, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BEIGE_GOBY}, |
| 2012 | {0x1002, 0x7423, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BEIGE_GOBY}, |
| 2013 | {0x1002, 0x7424, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BEIGE_GOBY}, |
| 2014 | {0x1002, 0x743F, PCI_ANY_ID(uint16_t) (~0U), PCI_ANY_ID(uint16_t) (~0U), 0, 0, CHIP_BEIGE_GOBY}, |
| 2015 | |
| 2016 | { PCI_DEVICE(0x1002, PCI_ANY_ID).vendor = (0x1002), .device = ((uint16_t) (~0U)), .subvendor = (uint16_t) (~0U), .subdevice = (uint16_t) (~0U), |
| 2017 | .class = PCI_CLASS_DISPLAY_VGA((0x03 << 8) | 0x00) << 8, |
| 2018 | .class_mask = 0xffffff, |
| 2019 | .driver_data = CHIP_IP_DISCOVERY }, |
| 2020 | |
| 2021 | { PCI_DEVICE(0x1002, PCI_ANY_ID).vendor = (0x1002), .device = ((uint16_t) (~0U)), .subvendor = (uint16_t) (~0U), .subdevice = (uint16_t) (~0U), |
| 2022 | .class = PCI_CLASS_DISPLAY_OTHER((0x03 << 8) | 0x80) << 8, |
| 2023 | .class_mask = 0xffffff, |
| 2024 | .driver_data = CHIP_IP_DISCOVERY }, |
| 2025 | |
| 2026 | {0, 0, 0} |
| 2027 | }; |
| 2028 | |
| 2029 | MODULE_DEVICE_TABLE(pci, pciidlist); |
| 2030 | |
| 2031 | static const struct drm_driver amdgpu_kms_driver; |
| 2032 | |
| 2033 | static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) |
| 2034 | { |
| 2035 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 2036 | #ifdef notyet |
| 2037 | struct pci_dev *p = NULL((void *)0); |
| 2038 | int i; |
| 2039 | |
| 2040 | /* 0 - GPU |
| 2041 | * 1 - audio |
| 2042 | * 2 - USB |
| 2043 | * 3 - UCSI |
| 2044 | */ |
| 2045 | for (i = 1; i < 4; i++) { |
| 2046 | p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus), |
| 2047 | adev->pdev->bus->number, i); |
| 2048 | if (p) { |
| 2049 | pm_runtime_get_sync(&p->dev); |
| 2050 | pm_runtime_mark_last_busy(&p->dev); |
| 2051 | pm_runtime_put_autosuspend(&p->dev); |
| 2052 | pci_dev_put(p); |
| 2053 | } |
| 2054 | } |
| 2055 | #endif |
| 2056 | } |
| 2057 | |
| 2058 | #ifdef notyet |
| 2059 | static int amdgpu_pci_probe(struct pci_dev *pdev, |
| 2060 | const struct pci_device_id *ent) |
| 2061 | { |
| 2062 | struct drm_device *ddev; |
| 2063 | struct amdgpu_device *adev; |
| 2064 | unsigned long flags = ent->driver_data; |
| 2065 | int ret, retry = 0, i; |
| 2066 | bool_Bool supports_atomic = false0; |
| 2067 | |
| 2068 | /* skip devices which are owned by radeon */ |
| 2069 | for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist)(sizeof((amdgpu_unsupported_pciidlist)) / sizeof((amdgpu_unsupported_pciidlist )[0])); i++) { |
| 2070 | if (amdgpu_unsupported_pciidlist[i] == pdev->device) |
| 2071 | return -ENODEV19; |
| 2072 | } |
| 2073 | |
| 2074 | if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) |
| 2075 | amdgpu_aspm = 0; |
| 2076 | |
| 2077 | if (amdgpu_virtual_display || |
| 2078 | amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) |
| 2079 | supports_atomic = true1; |
| 2080 | |
| 2081 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
| 2082 | DRM_INFO("This hardware requires experimental hardware support.\n"printk("\0016" "[" "drm" "] " "This hardware requires experimental hardware support.\n" "See modparam exp_hw_support\n") |
| 2083 | "See modparam exp_hw_support\n")printk("\0016" "[" "drm" "] " "This hardware requires experimental hardware support.\n" "See modparam exp_hw_support\n"); |
| 2084 | return -ENODEV19; |
| 2085 | } |
| 2086 | /* differentiate between P10 and P11 asics with the same DID */ |
| 2087 | if (pdev->device == 0x67FF && |
| 2088 | (pdev->revision == 0xE3 || |
| 2089 | pdev->revision == 0xE7 || |
| 2090 | pdev->revision == 0xF3 || |
| 2091 | pdev->revision == 0xF7)) { |
| 2092 | flags &= ~AMD_ASIC_MASK; |
| 2093 | flags |= CHIP_POLARIS10; |
| 2094 | } |
| 2095 | |
| 2096 | /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU mapping, |
| 2097 | * however, SME requires an indirect IOMMU mapping because the encryption |
| 2098 | * bit is beyond the DMA mask of the chip. |
| 2099 | */ |
| 2100 | if (cc_platform_has(CC_ATTR_MEM_ENCRYPT) && |
| 2101 | ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) { |
| 2102 | dev_info(&pdev->dev,do { } while(0) |
| 2103 | "SME is not compatible with RAVEN\n")do { } while(0); |
| 2104 | return -ENOTSUPP91; |
| 2105 | } |
| 2106 | |
| 2107 | #ifdef CONFIG_DRM_AMDGPU_SI |
| 2108 | if (!amdgpu_si_support) { |
| 2109 | switch (flags & AMD_ASIC_MASK) { |
| 2110 | case CHIP_TAHITI: |
| 2111 | case CHIP_PITCAIRN: |
| 2112 | case CHIP_VERDE: |
| 2113 | case CHIP_OLAND: |
| 2114 | case CHIP_HAINAN: |
| 2115 | dev_info(&pdev->dev,do { } while(0) |
| 2116 | "SI support provided by radeon.\n")do { } while(0); |
| 2117 | dev_info(&pdev->dev,do { } while(0) |
| 2118 | "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"do { } while(0) |
| 2119 | )do { } while(0); |
| 2120 | return -ENODEV19; |
| 2121 | } |
| 2122 | } |
| 2123 | #endif |
| 2124 | #ifdef CONFIG_DRM_AMDGPU_CIK |
| 2125 | if (!amdgpu_cik_support) { |
| 2126 | switch (flags & AMD_ASIC_MASK) { |
| 2127 | case CHIP_KAVERI: |
| 2128 | case CHIP_BONAIRE: |
| 2129 | case CHIP_HAWAII: |
| 2130 | case CHIP_KABINI: |
| 2131 | case CHIP_MULLINS: |
| 2132 | dev_info(&pdev->dev,do { } while(0) |
| 2133 | "CIK support provided by radeon.\n")do { } while(0); |
| 2134 | dev_info(&pdev->dev,do { } while(0) |
| 2135 | "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"do { } while(0) |
| 2136 | )do { } while(0); |
| 2137 | return -ENODEV19; |
| 2138 | } |
| 2139 | } |
| 2140 | #endif |
| 2141 | |
| 2142 | adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev)((typeof(*adev) *) __devm_drm_dev_alloc(&pdev->dev, & amdgpu_kms_driver, sizeof(typeof(*adev)), __builtin_offsetof( typeof(*adev), ddev))); |
| 2143 | if (IS_ERR(adev)) |
| 2144 | return PTR_ERR(adev); |
| 2145 | |
| 2146 | adev->dev = &pdev->dev; |
| 2147 | adev->pdev = pdev; |
| 2148 | ddev = adev_to_drm(adev); |
| 2149 | |
| 2150 | if (!supports_atomic) |
| 2151 | ddev->driver_features &= ~DRIVER_ATOMIC; |
| 2152 | |
| 2153 | ret = pci_enable_device(pdev); |
| 2154 | if (ret) |
| 2155 | return ret; |
| 2156 | |
| 2157 | pci_set_drvdata(pdev, ddev); |
| 2158 | |
| 2159 | ret = amdgpu_driver_load_kms(adev, flags); |
| 2160 | if (ret) |
| 2161 | goto err_pci; |
| 2162 | |
| 2163 | retry_init: |
| 2164 | ret = drm_dev_register(ddev, flags); |
| 2165 | if (ret == -EAGAIN35 && ++retry <= 3) { |
| 2166 | DRM_INFO("retry init %d\n", retry)printk("\0016" "[" "drm" "] " "retry init %d\n", retry); |
| 2167 | /* Don't request EX mode too frequently which is attacking */ |
| 2168 | drm_msleep(5000)mdelay(5000); |
| 2169 | goto retry_init; |
| 2170 | } else if (ret) { |
| 2171 | goto err_pci; |
| 2172 | } |
| 2173 | |
| 2174 | /* |
| 2175 | * 1. don't init fbdev on hw without DCE |
| 2176 | * 2. don't init fbdev if there are no connectors |
| 2177 | */ |
| 2178 | if (adev->mode_info.mode_config_initialized && |
| 2179 | !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { |
| 2180 | /* select 8 bpp console on low vram cards */ |
| 2181 | if (adev->gmc.real_vram_size <= (32*1024*1024)) |
| 2182 | drm_fbdev_generic_setup(adev_to_drm(adev), 8); |
| 2183 | else |
| 2184 | drm_fbdev_generic_setup(adev_to_drm(adev), 32); |
| 2185 | } |
| 2186 | |
| 2187 | ret = amdgpu_debugfs_init(adev); |
| 2188 | if (ret) |
| 2189 | DRM_ERROR("Creating debugfs files failed (%d).\n", ret)__drm_err("Creating debugfs files failed (%d).\n", ret); |
| 2190 | |
| 2191 | if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { |
| 2192 | /* only need to skip on ATPX */ |
| 2193 | if (amdgpu_device_supports_px(ddev)) |
| 2194 | dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); |
| 2195 | /* we want direct complete for BOCO */ |
| 2196 | if (amdgpu_device_supports_boco(ddev)) |
| 2197 | dev_pm_set_driver_flags(ddev->dev, DPM_FLAG_SMART_PREPARE | |
| 2198 | DPM_FLAG_SMART_SUSPEND | |
| 2199 | DPM_FLAG_MAY_SKIP_RESUME); |
| 2200 | pm_runtime_use_autosuspend(ddev->dev); |
| 2201 | pm_runtime_set_autosuspend_delay(ddev->dev, 5000); |
| 2202 | |
| 2203 | pm_runtime_allow(ddev->dev); |
| 2204 | |
| 2205 | pm_runtime_mark_last_busy(ddev->dev); |
| 2206 | pm_runtime_put_autosuspend(ddev->dev); |
| 2207 | |
| 2208 | pci_wake_from_d3(pdev, TRUE1); |
| 2209 | |
| 2210 | /* |
| 2211 | * For runpm implemented via BACO, PMFW will handle the |
| 2212 | * timing for BACO in and out: |
| 2213 | * - put ASIC into BACO state only when both video and |
| 2214 | * audio functions are in D3 state. |
| 2215 | * - pull ASIC out of BACO state when either video or |
| 2216 | * audio function is in D0 state. |
| 2217 | * Also, at startup, PMFW assumes both functions are in |
| 2218 | * D0 state. |
| 2219 | * |
| 2220 | * So if snd driver was loaded prior to amdgpu driver |
| 2221 | * and audio function was put into D3 state, there will |
| 2222 | * be no PMFW-aware D-state transition(D0->D3) on runpm |
| 2223 | * suspend. Thus the BACO will be not correctly kicked in. |
| 2224 | * |
| 2225 | * Via amdgpu_get_secondary_funcs(), the audio dev is put |
| 2226 | * into D0 state. Then there will be a PMFW-aware D-state |
| 2227 | * transition(D0->D3) on runpm suspend. |
| 2228 | */ |
| 2229 | if (amdgpu_device_supports_baco(ddev) && |
| 2230 | !(adev->flags & AMD_IS_APU) && |
| 2231 | (adev->asic_type >= CHIP_NAVI10)) |
| 2232 | amdgpu_get_secondary_funcs(adev); |
| 2233 | } |
| 2234 | |
| 2235 | return 0; |
| 2236 | |
| 2237 | err_pci: |
| 2238 | pci_disable_device(pdev); |
| 2239 | return ret; |
| 2240 | } |
| 2241 | |
| 2242 | static void |
| 2243 | amdgpu_pci_remove(struct pci_dev *pdev) |
| 2244 | { |
| 2245 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 2246 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2247 | |
| 2248 | drm_dev_unplug(dev); |
| 2249 | |
| 2250 | if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { |
| 2251 | pm_runtime_get_sync(dev->dev); |
| 2252 | pm_runtime_forbid(dev->dev); |
| 2253 | } |
| 2254 | |
| 2255 | if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)) && |
| 2256 | !amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) { |
| 2257 | bool_Bool need_to_reset_gpu = false0; |
| 2258 | |
| 2259 | if (adev->gmc.xgmi.num_physical_nodes > 1) { |
| 2260 | struct amdgpu_hive_info *hive; |
| 2261 | |
| 2262 | hive = amdgpu_get_xgmi_hive(adev); |
| 2263 | if (hive->device_remove_count == 0) |
| 2264 | need_to_reset_gpu = true1; |
| 2265 | hive->device_remove_count++; |
| 2266 | amdgpu_put_xgmi_hive(hive); |
| 2267 | } else { |
| 2268 | need_to_reset_gpu = true1; |
| 2269 | } |
| 2270 | |
| 2271 | /* Workaround for ASICs need to reset SMU. |
| 2272 | * Called only when the first device is removed. |
| 2273 | */ |
| 2274 | if (need_to_reset_gpu) { |
| 2275 | struct amdgpu_reset_context reset_context; |
| 2276 | |
| 2277 | adev->shutdown = true1; |
| 2278 | memset(&reset_context, 0, sizeof(reset_context))__builtin_memset((&reset_context), (0), (sizeof(reset_context ))); |
| 2279 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 2280 | reset_context.reset_req_dev = adev; |
| 2281 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 2282 | set_bit(AMDGPU_RESET_FOR_DEVICE_REMOVE, &reset_context.flags); |
| 2283 | amdgpu_device_gpu_recover(adev, NULL((void *)0), &reset_context); |
| 2284 | } |
| 2285 | } |
| 2286 | |
| 2287 | amdgpu_driver_unload_kms(dev); |
| 2288 | |
| 2289 | /* |
| 2290 | * Flush any in flight DMA operations from device. |
| 2291 | * Clear the Bus Master Enable bit and then wait on the PCIe Device |
| 2292 | * StatusTransactions Pending bit. |
| 2293 | */ |
| 2294 | pci_disable_device(pdev); |
| 2295 | pci_wait_for_pending_transaction(pdev); |
| 2296 | } |
| 2297 | |
| 2298 | static void |
| 2299 | amdgpu_pci_shutdown(struct pci_dev *pdev) |
| 2300 | { |
| 2301 | struct drm_device *dev = pci_get_drvdata(pdev); |
| 2302 | struct amdgpu_device *adev = drm_to_adev(dev); |
| 2303 | |
| 2304 | if (amdgpu_ras_intr_triggered()) |
| 2305 | return; |
| 2306 | |
| 2307 | /* if we are running in a VM, make sure the device |
| 2308 | * torn down properly on reboot/shutdown. |
| 2309 | * unfortunately we can't detect certain |
| 2310 | * hypervisors so just do this all the time. |
| 2311 | */ |
| 2312 | if (!amdgpu_passthrough(adev)((adev)->virt.caps & (1 << 3))) |
| 2313 | adev->mp1_state = PP_MP1_STATE_UNLOAD; |
| 2314 | amdgpu_device_ip_suspend(adev); |
| 2315 | adev->mp1_state = PP_MP1_STATE_NONE; |
| 2316 | } |
| 2317 | #endif |
| 2318 | |
| 2319 | /** |
| 2320 | * amdgpu_drv_delayed_reset_work_handler - work handler for reset |
| 2321 | * |
| 2322 | * @work: work_struct. |
| 2323 | */ |
| 2324 | static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) |
| 2325 | { |
| 2326 | struct list_head device_list; |
| 2327 | struct amdgpu_device *adev; |
| 2328 | int i, r; |
| 2329 | struct amdgpu_reset_context reset_context; |
| 2330 | |
| 2331 | memset(&reset_context, 0, sizeof(reset_context))__builtin_memset((&reset_context), (0), (sizeof(reset_context ))); |
| 2332 | |
| 2333 | mutex_lock(&mgpu_info.mutex)rw_enter_write(&mgpu_info.mutex); |
| 2334 | if (mgpu_info.pending_reset == true1) { |
| 2335 | mutex_unlock(&mgpu_info.mutex)rw_exit_write(&mgpu_info.mutex); |
| 2336 | return; |
| 2337 | } |
| 2338 | mgpu_info.pending_reset = true1; |
| 2339 | mutex_unlock(&mgpu_info.mutex)rw_exit_write(&mgpu_info.mutex); |
| 2340 | |
| 2341 | /* Use a common context, just need to make sure full reset is done */ |
| 2342 | reset_context.method = AMD_RESET_METHOD_NONE; |
| 2343 | set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); |
| 2344 | |
| 2345 | for (i = 0; i < mgpu_info.num_dgpu; i++) { |
| 2346 | adev = mgpu_info.gpu_ins[i].adev; |
| 2347 | reset_context.reset_req_dev = adev; |
| 2348 | r = amdgpu_device_pre_asic_reset(adev, &reset_context); |
| 2349 | if (r) { |
| 2350 | dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",printf("drm:pid%d:%s *ERROR* " "GPU pre asic reset failed with err, %d for drm dev, %s " , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r, adev_to_drm (adev)->unique) |
| 2351 | r, adev_to_drm(adev)->unique)printf("drm:pid%d:%s *ERROR* " "GPU pre asic reset failed with err, %d for drm dev, %s " , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , r, adev_to_drm (adev)->unique); |
| 2352 | } |
| 2353 | if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) |
| 2354 | r = -EALREADY37; |
Value stored to 'r' is never read | |
| 2355 | } |
| 2356 | for (i = 0; i < mgpu_info.num_dgpu; i++) { |
| 2357 | adev = mgpu_info.gpu_ins[i].adev; |
| 2358 | flush_work(&adev->xgmi_reset_work); |
| 2359 | adev->gmc.xgmi.pending_reset = false0; |
| 2360 | } |
| 2361 | |
| 2362 | /* reset function will rebuild the xgmi hive info , clear it now */ |
| 2363 | for (i = 0; i < mgpu_info.num_dgpu; i++) |
| 2364 | amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); |
| 2365 | |
| 2366 | INIT_LIST_HEAD(&device_list); |
| 2367 | |
| 2368 | for (i = 0; i < mgpu_info.num_dgpu; i++) |
| 2369 | list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); |
| 2370 | |
| 2371 | /* unregister the GPU first, reset function will add them back */ |
| 2372 | list_for_each_entry(adev, &device_list, reset_list)for (adev = ({ const __typeof( ((__typeof(*adev) *)0)->reset_list ) *__mptr = ((&device_list)->next); (__typeof(*adev) * )( (char *)__mptr - __builtin_offsetof(__typeof(*adev), reset_list ) );}); &adev->reset_list != (&device_list); adev = ({ const __typeof( ((__typeof(*adev) *)0)->reset_list ) * __mptr = (adev->reset_list.next); (__typeof(*adev) *)( (char *)__mptr - __builtin_offsetof(__typeof(*adev), reset_list) ) ;})) |
| 2373 | amdgpu_unregister_gpu_instance(adev); |
| 2374 | |
| 2375 | /* Use a common context, just need to make sure full reset is done */ |
| 2376 | set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); |
| 2377 | r = amdgpu_do_asic_reset(&device_list, &reset_context); |
| 2378 | |
| 2379 | if (r) { |
| 2380 | DRM_ERROR("reinit gpus failure")__drm_err("reinit gpus failure"); |
| 2381 | return; |
| 2382 | } |
| 2383 | for (i = 0; i < mgpu_info.num_dgpu; i++) { |
| 2384 | adev = mgpu_info.gpu_ins[i].adev; |
| 2385 | if (!adev->kfd.init_complete) |
| 2386 | amdgpu_amdkfd_device_init(adev); |
| 2387 | amdgpu_ttm_set_buffer_funcs_status(adev, true1); |
| 2388 | } |
| 2389 | return; |
| 2390 | } |
| 2391 | |
| 2392 | #ifdef notyet |
| 2393 | |
| 2394 | static int amdgpu_pmops_prepare(struct device *dev) |
| 2395 | { |
| 2396 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2397 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2398 | |
| 2399 | /* Return a positive number here so |
| 2400 | * DPM_FLAG_SMART_SUSPEND works properly |
| 2401 | */ |
| 2402 | if (amdgpu_device_supports_boco(drm_dev)) |
| 2403 | return pm_runtime_suspended(dev); |
| 2404 | |
| 2405 | /* if we will not support s3 or s2i for the device |
| 2406 | * then skip suspend |
| 2407 | */ |
| 2408 | if (!amdgpu_acpi_is_s0ix_active(adev) && |
| 2409 | !amdgpu_acpi_is_s3_active(adev)) |
| 2410 | return 1; |
| 2411 | |
| 2412 | return 0; |
| 2413 | } |
| 2414 | |
| 2415 | static void amdgpu_pmops_complete(struct device *dev) |
| 2416 | { |
| 2417 | /* nothing to do */ |
| 2418 | } |
| 2419 | |
| 2420 | static int amdgpu_pmops_suspend(struct device *dev) |
| 2421 | { |
| 2422 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2423 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2424 | |
| 2425 | if (amdgpu_acpi_is_s0ix_active(adev)) |
| 2426 | adev->in_s0ix = true1; |
| 2427 | else if (amdgpu_acpi_is_s3_active(adev)) |
| 2428 | adev->in_s3 = true1; |
| 2429 | if (!adev->in_s0ix && !adev->in_s3) |
| 2430 | return 0; |
| 2431 | return amdgpu_device_suspend(drm_dev, true1); |
| 2432 | } |
| 2433 | |
| 2434 | static int amdgpu_pmops_suspend_noirq(struct device *dev) |
| 2435 | { |
| 2436 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2437 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2438 | |
| 2439 | if (amdgpu_acpi_should_gpu_reset(adev)) |
| 2440 | return amdgpu_asic_reset(adev)(adev)->asic_funcs->reset((adev)); |
| 2441 | |
| 2442 | return 0; |
| 2443 | } |
| 2444 | |
| 2445 | static int amdgpu_pmops_resume(struct device *dev) |
| 2446 | { |
| 2447 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2448 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2449 | int r; |
| 2450 | |
| 2451 | if (!adev->in_s0ix && !adev->in_s3) |
| 2452 | return 0; |
| 2453 | |
| 2454 | /* Avoids registers access if device is physically gone */ |
| 2455 | if (!pci_device_is_present(adev->pdev)) |
| 2456 | adev->no_hw_access = true1; |
| 2457 | |
| 2458 | r = amdgpu_device_resume(drm_dev, true1); |
| 2459 | if (amdgpu_acpi_is_s0ix_active(adev)) |
| 2460 | adev->in_s0ix = false0; |
| 2461 | else |
| 2462 | adev->in_s3 = false0; |
| 2463 | return r; |
| 2464 | } |
| 2465 | |
| 2466 | static int amdgpu_pmops_freeze(struct device *dev) |
| 2467 | { |
| 2468 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2469 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2470 | int r; |
| 2471 | |
| 2472 | adev->in_s4 = true1; |
| 2473 | r = amdgpu_device_suspend(drm_dev, true1); |
| 2474 | adev->in_s4 = false0; |
| 2475 | if (r) |
| 2476 | return r; |
| 2477 | |
| 2478 | if (amdgpu_acpi_should_gpu_reset(adev)) |
| 2479 | return amdgpu_asic_reset(adev)(adev)->asic_funcs->reset((adev)); |
| 2480 | return 0; |
| 2481 | } |
| 2482 | |
| 2483 | static int amdgpu_pmops_thaw(struct device *dev) |
| 2484 | { |
| 2485 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2486 | |
| 2487 | return amdgpu_device_resume(drm_dev, true1); |
| 2488 | } |
| 2489 | |
| 2490 | static int amdgpu_pmops_poweroff(struct device *dev) |
| 2491 | { |
| 2492 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2493 | |
| 2494 | return amdgpu_device_suspend(drm_dev, true1); |
| 2495 | } |
| 2496 | |
| 2497 | static int amdgpu_pmops_restore(struct device *dev) |
| 2498 | { |
| 2499 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2500 | |
| 2501 | return amdgpu_device_resume(drm_dev, true1); |
| 2502 | } |
| 2503 | |
| 2504 | static int amdgpu_runtime_idle_check_display(struct device *dev) |
| 2505 | { |
| 2506 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2507 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 2508 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2509 | |
| 2510 | if (adev->mode_info.num_crtc) { |
| 2511 | struct drm_connector *list_connector; |
| 2512 | struct drm_connector_list_iter iter; |
| 2513 | int ret = 0; |
| 2514 | |
| 2515 | /* XXX: Return busy if any displays are connected to avoid |
| 2516 | * possible display wakeups after runtime resume due to |
| 2517 | * hotplug events in case any displays were connected while |
| 2518 | * the GPU was in suspend. Remove this once that is fixed. |
| 2519 | */ |
| 2520 | mutex_lock(&drm_dev->mode_config.mutex)rw_enter_write(&drm_dev->mode_config.mutex); |
| 2521 | drm_connector_list_iter_begin(drm_dev, &iter); |
| 2522 | drm_for_each_connector_iter(list_connector, &iter)while ((list_connector = drm_connector_list_iter_next(&iter ))) { |
| 2523 | if (list_connector->status == connector_status_connected) { |
| 2524 | ret = -EBUSY16; |
| 2525 | break; |
| 2526 | } |
| 2527 | } |
| 2528 | drm_connector_list_iter_end(&iter); |
| 2529 | mutex_unlock(&drm_dev->mode_config.mutex)rw_exit_write(&drm_dev->mode_config.mutex); |
| 2530 | |
| 2531 | if (ret) |
| 2532 | return ret; |
| 2533 | |
| 2534 | if (amdgpu_device_has_dc_support(adev)) { |
| 2535 | struct drm_crtc *crtc; |
| 2536 | |
| 2537 | drm_for_each_crtc(crtc, drm_dev)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head ) *__mptr = ((&(drm_dev)->mode_config.crtc_list)-> next); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof (__typeof(*crtc), head) );}); &crtc->head != (&(drm_dev )->mode_config.crtc_list); crtc = ({ const __typeof( ((__typeof (*crtc) *)0)->head ) *__mptr = (crtc->head.next); (__typeof (*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc ), head) );})) { |
| 2538 | drm_modeset_lock(&crtc->mutex, NULL((void *)0)); |
| 2539 | if (crtc->state->active) |
| 2540 | ret = -EBUSY16; |
| 2541 | drm_modeset_unlock(&crtc->mutex); |
| 2542 | if (ret < 0) |
| 2543 | break; |
| 2544 | } |
| 2545 | } else { |
| 2546 | mutex_lock(&drm_dev->mode_config.mutex)rw_enter_write(&drm_dev->mode_config.mutex); |
| 2547 | drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL((void *)0)); |
| 2548 | |
| 2549 | drm_connector_list_iter_begin(drm_dev, &iter); |
| 2550 | drm_for_each_connector_iter(list_connector, &iter)while ((list_connector = drm_connector_list_iter_next(&iter ))) { |
| 2551 | if (list_connector->dpms == DRM_MODE_DPMS_ON0) { |
| 2552 | ret = -EBUSY16; |
| 2553 | break; |
| 2554 | } |
| 2555 | } |
| 2556 | |
| 2557 | drm_connector_list_iter_end(&iter); |
| 2558 | |
| 2559 | drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); |
| 2560 | mutex_unlock(&drm_dev->mode_config.mutex)rw_exit_write(&drm_dev->mode_config.mutex); |
| 2561 | } |
| 2562 | if (ret) |
| 2563 | return ret; |
| 2564 | } |
| 2565 | |
| 2566 | return 0; |
| 2567 | } |
| 2568 | |
| 2569 | static int amdgpu_pmops_runtime_suspend(struct device *dev) |
| 2570 | { |
| 2571 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2572 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 2573 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2574 | int ret, i; |
| 2575 | |
| 2576 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { |
| 2577 | pm_runtime_forbid(dev); |
| 2578 | return -EBUSY16; |
| 2579 | } |
| 2580 | |
| 2581 | ret = amdgpu_runtime_idle_check_display(dev); |
| 2582 | if (ret) |
| 2583 | return ret; |
| 2584 | |
| 2585 | /* wait for all rings to drain before suspending */ |
| 2586 | for (i = 0; i < AMDGPU_MAX_RINGS28; i++) { |
| 2587 | struct amdgpu_ring *ring = adev->rings[i]; |
| 2588 | if (ring && ring->sched.ready) { |
| 2589 | ret = amdgpu_fence_wait_empty(ring); |
| 2590 | if (ret) |
| 2591 | return -EBUSY16; |
| 2592 | } |
| 2593 | } |
| 2594 | |
| 2595 | adev->in_runpm = true1; |
| 2596 | if (amdgpu_device_supports_px(drm_dev)) |
| 2597 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
| 2598 | |
| 2599 | /* |
| 2600 | * By setting mp1_state as PP_MP1_STATE_UNLOAD, MP1 will do some |
| 2601 | * proper cleanups and put itself into a state ready for PNP. That |
| 2602 | * can address some random resuming failure observed on BOCO capable |
| 2603 | * platforms. |
| 2604 | * TODO: this may be also needed for PX capable platform. |
| 2605 | */ |
| 2606 | if (amdgpu_device_supports_boco(drm_dev)) |
| 2607 | adev->mp1_state = PP_MP1_STATE_UNLOAD; |
| 2608 | |
| 2609 | ret = amdgpu_device_suspend(drm_dev, false0); |
| 2610 | if (ret) { |
| 2611 | adev->in_runpm = false0; |
| 2612 | if (amdgpu_device_supports_boco(drm_dev)) |
| 2613 | adev->mp1_state = PP_MP1_STATE_NONE; |
| 2614 | return ret; |
| 2615 | } |
| 2616 | |
| 2617 | if (amdgpu_device_supports_boco(drm_dev)) |
| 2618 | adev->mp1_state = PP_MP1_STATE_NONE; |
| 2619 | |
| 2620 | if (amdgpu_device_supports_px(drm_dev)) { |
| 2621 | /* Only need to handle PCI state in the driver for ATPX |
| 2622 | * PCI core handles it for _PR3. |
| 2623 | */ |
| 2624 | amdgpu_device_cache_pci_state(pdev); |
| 2625 | pci_disable_device(pdev); |
| 2626 | pci_ignore_hotplug(pdev); |
| 2627 | pci_set_power_state(pdev, PCI_D3cold); |
| 2628 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
| 2629 | } else if (amdgpu_device_supports_boco(drm_dev)) { |
| 2630 | /* nothing to do */ |
| 2631 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
| 2632 | amdgpu_device_baco_enter(drm_dev); |
| 2633 | } |
| 2634 | |
| 2635 | return 0; |
| 2636 | } |
| 2637 | |
| 2638 | static int amdgpu_pmops_runtime_resume(struct device *dev) |
| 2639 | { |
| 2640 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2641 | struct drm_device *drm_dev = pci_get_drvdata(pdev); |
| 2642 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2643 | int ret; |
| 2644 | |
| 2645 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) |
| 2646 | return -EINVAL22; |
| 2647 | |
| 2648 | /* Avoids registers access if device is physically gone */ |
| 2649 | if (!pci_device_is_present(adev->pdev)) |
| 2650 | adev->no_hw_access = true1; |
| 2651 | |
| 2652 | if (amdgpu_device_supports_px(drm_dev)) { |
| 2653 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
| 2654 | |
| 2655 | /* Only need to handle PCI state in the driver for ATPX |
| 2656 | * PCI core handles it for _PR3. |
| 2657 | */ |
| 2658 | pci_set_power_state(pdev, PCI_D0); |
| 2659 | amdgpu_device_load_pci_state(pdev); |
| 2660 | ret = pci_enable_device(pdev); |
| 2661 | if (ret) |
| 2662 | return ret; |
| 2663 | pci_set_master(pdev); |
| 2664 | } else if (amdgpu_device_supports_boco(drm_dev)) { |
| 2665 | /* Only need to handle PCI state in the driver for ATPX |
| 2666 | * PCI core handles it for _PR3. |
| 2667 | */ |
| 2668 | pci_set_master(pdev); |
| 2669 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
| 2670 | amdgpu_device_baco_exit(drm_dev); |
| 2671 | } |
| 2672 | ret = amdgpu_device_resume(drm_dev, false0); |
| 2673 | if (ret) { |
| 2674 | if (amdgpu_device_supports_px(drm_dev)) |
| 2675 | pci_disable_device(pdev); |
| 2676 | return ret; |
| 2677 | } |
| 2678 | |
| 2679 | if (amdgpu_device_supports_px(drm_dev)) |
| 2680 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; |
| 2681 | adev->in_runpm = false0; |
| 2682 | return 0; |
| 2683 | } |
| 2684 | |
| 2685 | static int amdgpu_pmops_runtime_idle(struct device *dev) |
| 2686 | { |
| 2687 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
| 2688 | struct amdgpu_device *adev = drm_to_adev(drm_dev); |
| 2689 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ |
| 2690 | int ret = 1; |
| 2691 | |
| 2692 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) { |
| 2693 | pm_runtime_forbid(dev); |
| 2694 | return -EBUSY16; |
| 2695 | } |
| 2696 | |
| 2697 | ret = amdgpu_runtime_idle_check_display(dev); |
| 2698 | |
| 2699 | pm_runtime_mark_last_busy(dev); |
| 2700 | pm_runtime_autosuspend(dev); |
| 2701 | return ret; |
| 2702 | } |
| 2703 | #endif /* notyet */ |
| 2704 | |
| 2705 | #ifdef __linux__ |
| 2706 | long amdgpu_drm_ioctl(struct file *filp, |
| 2707 | unsigned int cmd, unsigned long arg) |
| 2708 | { |
| 2709 | struct drm_file *file_priv = filp->private_data; |
| 2710 | struct drm_device *dev; |
| 2711 | long ret; |
| 2712 | dev = file_priv->minor->dev; |
| 2713 | ret = pm_runtime_get_sync(dev->dev); |
| 2714 | if (ret < 0) |
| 2715 | goto out; |
| 2716 | |
| 2717 | ret = drm_ioctl(filp, cmd, arg); |
| 2718 | |
| 2719 | pm_runtime_mark_last_busy(dev->dev); |
| 2720 | out: |
| 2721 | pm_runtime_put_autosuspend(dev->dev); |
| 2722 | return ret; |
| 2723 | } |
| 2724 | |
| 2725 | static const struct dev_pm_ops amdgpu_pm_ops = { |
| 2726 | .prepare = amdgpu_pmops_prepare, |
| 2727 | .complete = amdgpu_pmops_complete, |
| 2728 | .suspend = amdgpu_pmops_suspend, |
| 2729 | .suspend_noirq = amdgpu_pmops_suspend_noirq, |
| 2730 | .resume = amdgpu_pmops_resume, |
| 2731 | .freeze = amdgpu_pmops_freeze, |
| 2732 | .thaw = amdgpu_pmops_thaw, |
| 2733 | .poweroff = amdgpu_pmops_poweroff, |
| 2734 | .restore = amdgpu_pmops_restore, |
| 2735 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
| 2736 | .runtime_resume = amdgpu_pmops_runtime_resume, |
| 2737 | .runtime_idle = amdgpu_pmops_runtime_idle, |
| 2738 | }; |
| 2739 | |
| 2740 | static int amdgpu_flush(struct file *f, fl_owner_t id) |
| 2741 | { |
| 2742 | struct drm_file *file_priv = f->private_data; |
| 2743 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; |
| 2744 | long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY(((uint64_t)(1000)) * hz / 1000); |
| 2745 | |
| 2746 | timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); |
| 2747 | timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); |
| 2748 | |
| 2749 | return timeout >= 0 ? 0 : timeout; |
| 2750 | } |
| 2751 | |
| 2752 | static const struct file_operations amdgpu_driver_kms_fops = { |
| 2753 | .owner = THIS_MODULE((void *)0), |
| 2754 | .open = drm_open, |
| 2755 | .flush = amdgpu_flush, |
| 2756 | .release = drm_release, |
| 2757 | .unlocked_ioctl = amdgpu_drm_ioctl, |
| 2758 | .mmap = drm_gem_mmap, |
| 2759 | .poll = drm_poll, |
| 2760 | .read = drm_read, |
| 2761 | #ifdef CONFIG_COMPAT |
| 2762 | .compat_ioctl = amdgpu_kms_compat_ioctl, |
| 2763 | #endif |
| 2764 | #ifdef CONFIG_PROC_FS |
| 2765 | .show_fdinfo = amdgpu_show_fdinfo |
| 2766 | #endif |
| 2767 | }; |
| 2768 | |
| 2769 | #endif /* __linux__ */ |
| 2770 | |
| 2771 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) |
| 2772 | { |
| 2773 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 2774 | return -ENOSYS78; |
| 2775 | #ifdef notyet |
| 2776 | struct drm_file *file; |
| 2777 | |
| 2778 | if (!filp) |
| 2779 | return -EINVAL22; |
| 2780 | |
| 2781 | if (filp->f_op != &amdgpu_driver_kms_fops) { |
| 2782 | return -EINVAL22; |
| 2783 | } |
| 2784 | |
| 2785 | file = filp->private_data; |
| 2786 | *fpriv = file->driver_priv; |
| 2787 | return 0; |
| 2788 | #endif |
| 2789 | } |
| 2790 | |
| 2791 | const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { |
| 2792 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_gem_create) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x00)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_gem_create) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x00))), .func = amdgpu_gem_create_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_GEM_CREATE" }, |
| 2793 | DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_ctx) & 0x1fff) << 16) | (( ('d')) << 8) | ((0x40 + 0x02)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_ctx) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x02))), .func = amdgpu_ctx_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_CTX" }, |
| 2794 | DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_vm) & 0x1fff) << 16) | ((( 'd')) << 8) | ((0x40 + 0x13)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_vm) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x13))), .func = amdgpu_vm_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_VM" }, |
| 2795 | DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER)[((((unsigned long)0x80000000 | ((sizeof(union drm_amdgpu_sched ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x15)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(union drm_amdgpu_sched) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x15))), .func = amdgpu_sched_ioctl , .flags = DRM_MASTER, .name = "AMDGPU_SCHED" }, |
| 2796 | DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_bo_list) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x03)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_bo_list) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x03))), .func = amdgpu_bo_list_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_BO_LIST" }, |
| 2797 | DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_fence_to_handle) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x14)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(union drm_amdgpu_fence_to_handle) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x14) )), .func = amdgpu_cs_fence_to_handle_ioctl, .flags = DRM_AUTH |DRM_RENDER_ALLOW, .name = "AMDGPU_FENCE_TO_HANDLE" }, |
| 2798 | /* KMS */ |
| 2799 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_gem_mmap) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x01)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_gem_mmap) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x01))), .func = amdgpu_gem_mmap_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_GEM_MMAP" }, |
| 2800 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_gem_wait_idle) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x07)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(union drm_amdgpu_gem_wait_idle) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x07))), .func = amdgpu_gem_wait_idle_ioctl, .flags = DRM_AUTH|DRM_RENDER_ALLOW , .name = "AMDGPU_GEM_WAIT_IDLE" }, |
| 2801 | DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_cs) & 0x1fff) << 16) | ((( 'd')) << 8) | ((0x40 + 0x04)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_cs) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x04))), .func = amdgpu_cs_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_CS" }, |
| 2802 | DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_amdgpu_info ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x05)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_amdgpu_info) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x05))), .func = amdgpu_info_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_INFO" }, |
| 2803 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_wait_cs) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x09)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_wait_cs) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x09))), .func = amdgpu_cs_wait_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_WAIT_CS" }, |
| 2804 | DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(union drm_amdgpu_wait_fences) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x12)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(union drm_amdgpu_wait_fences) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x12))), .func = amdgpu_cs_wait_fences_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_WAIT_FENCES" }, |
| 2805 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_amdgpu_gem_metadata) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x06)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_amdgpu_gem_metadata) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x06))), .func = amdgpu_gem_metadata_ioctl, .flags = DRM_AUTH|DRM_RENDER_ALLOW , .name = "AMDGPU_GEM_METADATA" }, |
| 2806 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_amdgpu_gem_va ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x08)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_amdgpu_gem_va) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x08))), .func = amdgpu_gem_va_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_GEM_VA" }, |
| 2807 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_amdgpu_gem_op) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x10)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_amdgpu_gem_op) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x10))), .func = amdgpu_gem_op_ioctl , .flags = DRM_AUTH|DRM_RENDER_ALLOW, .name = "AMDGPU_GEM_OP" }, |
| 2808 | DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_amdgpu_gem_userptr) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x11)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_amdgpu_gem_userptr) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x11))), .func = amdgpu_gem_userptr_ioctl, .flags = DRM_AUTH|DRM_RENDER_ALLOW , .name = "AMDGPU_GEM_USERPTR" }, |
| 2809 | }; |
| 2810 | |
| 2811 | static const struct drm_driver amdgpu_kms_driver = { |
| 2812 | .driver_features = |
| 2813 | DRIVER_ATOMIC | |
| 2814 | DRIVER_GEM | |
| 2815 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | |
| 2816 | DRIVER_SYNCOBJ_TIMELINE, |
| 2817 | .open = amdgpu_driver_open_kms, |
| 2818 | #ifdef __OpenBSD__1 |
| 2819 | .mmap = drm_gem_mmap, |
| 2820 | #endif |
| 2821 | .postclose = amdgpu_driver_postclose_kms, |
| 2822 | .lastclose = amdgpu_driver_lastclose_kms, |
| 2823 | .ioctls = amdgpu_ioctls_kms, |
| 2824 | .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms)(sizeof((amdgpu_ioctls_kms)) / sizeof((amdgpu_ioctls_kms)[0]) ), |
| 2825 | .dumb_create = amdgpu_mode_dumb_create, |
| 2826 | .dumb_map_offset = amdgpu_mode_dumb_mmap, |
| 2827 | #ifdef __linux__ |
| 2828 | .fops = &amdgpu_driver_kms_fops, |
| 2829 | #endif |
| 2830 | .release = &amdgpu_driver_release_kms, |
| 2831 | |
| 2832 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 2833 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 2834 | .gem_prime_import = amdgpu_gem_prime_import, |
| 2835 | #ifdef notyet |
| 2836 | .gem_prime_mmap = drm_gem_prime_mmap, |
| 2837 | #endif |
| 2838 | |
| 2839 | .name = DRIVER_NAME"amdgpu", |
| 2840 | .desc = DRIVER_DESC"AMD GPU", |
| 2841 | .date = DRIVER_DATE"20150101", |
| 2842 | .major = KMS_DRIVER_MAJOR3, |
| 2843 | .minor = KMS_DRIVER_MINOR49, |
| 2844 | .patchlevel = KMS_DRIVER_PATCHLEVEL0, |
| 2845 | }; |
| 2846 | |
| 2847 | #ifdef __linux__ |
| 2848 | static struct pci_error_handlers amdgpu_pci_err_handler = { |
| 2849 | .error_detected = amdgpu_pci_error_detected, |
| 2850 | .mmio_enabled = amdgpu_pci_mmio_enabled, |
| 2851 | .slot_reset = amdgpu_pci_slot_reset, |
| 2852 | .resume = amdgpu_pci_resume, |
| 2853 | }; |
| 2854 | |
| 2855 | extern const struct attribute_group amdgpu_vram_mgr_attr_group; |
| 2856 | extern const struct attribute_group amdgpu_gtt_mgr_attr_group; |
| 2857 | extern const struct attribute_group amdgpu_vbios_version_attr_group; |
| 2858 | |
| 2859 | static const struct attribute_group *amdgpu_sysfs_groups[] = { |
| 2860 | &amdgpu_vram_mgr_attr_group, |
| 2861 | &amdgpu_gtt_mgr_attr_group, |
| 2862 | &amdgpu_vbios_version_attr_group, |
| 2863 | NULL((void *)0), |
| 2864 | }; |
| 2865 | |
| 2866 | |
| 2867 | static struct pci_driver amdgpu_kms_pci_driver = { |
| 2868 | .name = DRIVER_NAME"amdgpu", |
| 2869 | .id_table = pciidlist, |
| 2870 | .probe = amdgpu_pci_probe, |
| 2871 | .remove = amdgpu_pci_remove, |
| 2872 | .shutdown = amdgpu_pci_shutdown, |
| 2873 | .driver.pm = &amdgpu_pm_ops, |
| 2874 | .err_handler = &amdgpu_pci_err_handler, |
| 2875 | .dev_groups = amdgpu_sysfs_groups, |
| 2876 | }; |
| 2877 | |
| 2878 | static int __init amdgpu_init(void) |
| 2879 | { |
| 2880 | int r; |
| 2881 | |
| 2882 | if (drm_firmware_drivers_only()) |
| 2883 | return -EINVAL22; |
| 2884 | |
| 2885 | r = amdgpu_sync_init(); |
| 2886 | if (r) |
| 2887 | goto error_sync; |
| 2888 | |
| 2889 | r = amdgpu_fence_slab_init(); |
| 2890 | if (r) |
| 2891 | goto error_fence; |
| 2892 | |
| 2893 | DRM_INFO("amdgpu kernel modesetting enabled.\n")printk("\0016" "[" "drm" "] " "amdgpu kernel modesetting enabled.\n" ); |
| 2894 | amdgpu_register_atpx_handler(); |
| 2895 | amdgpu_acpi_detect(); |
| 2896 | |
| 2897 | /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ |
| 2898 | amdgpu_amdkfd_init(); |
| 2899 | |
| 2900 | /* let modprobe override vga console setting */ |
| 2901 | return pci_register_driver(&amdgpu_kms_pci_driver); |
| 2902 | |
| 2903 | error_fence: |
| 2904 | amdgpu_sync_fini(); |
| 2905 | |
| 2906 | error_sync: |
| 2907 | return r; |
| 2908 | } |
| 2909 | |
| 2910 | static void __exit amdgpu_exit(void) |
| 2911 | { |
| 2912 | amdgpu_amdkfd_fini(); |
| 2913 | pci_unregister_driver(&amdgpu_kms_pci_driver); |
| 2914 | amdgpu_unregister_atpx_handler(); |
| 2915 | amdgpu_sync_fini(); |
| 2916 | amdgpu_fence_slab_fini(); |
| 2917 | mmu_notifier_synchronize(); |
| 2918 | } |
| 2919 | |
| 2920 | module_init(amdgpu_init); |
| 2921 | module_exit(amdgpu_exit); |
| 2922 | |
| 2923 | MODULE_AUTHOR(DRIVER_AUTHOR); |
| 2924 | MODULE_DESCRIPTION(DRIVER_DESC); |
| 2925 | MODULE_LICENSE("GPL and additional rights"); |
| 2926 | #endif /* __linux__ */ |
| 2927 | |
| 2928 | #include <drm/drm_drv.h> |
| 2929 | #include <drm/drm_utils.h> |
| 2930 | |
| 2931 | #include "vga.h" |
| 2932 | |
| 2933 | #if NVGA1 > 0 |
| 2934 | #include <dev/ic/mc6845reg.h> |
| 2935 | #include <dev/ic/pcdisplayvar.h> |
| 2936 | #include <dev/ic/vgareg.h> |
| 2937 | #include <dev/ic/vgavar.h> |
| 2938 | |
| 2939 | extern int vga_console_attached; |
| 2940 | #endif |
| 2941 | |
| 2942 | #ifdef __amd64__1 |
| 2943 | #include "efifb.h" |
| 2944 | #include <machine/biosvar.h> |
| 2945 | #endif |
| 2946 | |
| 2947 | #if NEFIFB1 > 0 |
| 2948 | #include <machine/efifbvar.h> |
| 2949 | #endif |
| 2950 | |
| 2951 | int amdgpu_probe(struct device *, void *, void *); |
| 2952 | void amdgpu_attach(struct device *, struct device *, void *); |
| 2953 | int amdgpu_detach(struct device *, int); |
| 2954 | int amdgpu_activate(struct device *, int); |
| 2955 | void amdgpu_attachhook(struct device *); |
| 2956 | int amdgpu_forcedetach(struct amdgpu_device *); |
| 2957 | |
| 2958 | bool_Bool amdgpu_msi_ok(struct amdgpu_device *); |
| 2959 | |
| 2960 | /* |
| 2961 | * set if the mountroot hook has a fatal error |
| 2962 | * such as not being able to find the firmware |
| 2963 | */ |
| 2964 | int amdgpu_fatal_error; |
| 2965 | |
| 2966 | const struct cfattach amdgpu_ca = { |
| 2967 | sizeof (struct amdgpu_device), amdgpu_probe, amdgpu_attach, |
| 2968 | amdgpu_detach, amdgpu_activate |
| 2969 | }; |
| 2970 | |
| 2971 | struct cfdriver amdgpu_cd = { |
| 2972 | NULL((void *)0), "amdgpu", DV_DULL |
| 2973 | }; |
| 2974 | |
| 2975 | int |
| 2976 | amdgpu_probe(struct device *parent, void *match, void *aux) |
| 2977 | { |
| 2978 | struct pci_attach_args *pa = aux; |
| 2979 | const struct pci_device_id *id_entry; |
| 2980 | unsigned long flags = 0; |
| 2981 | int i; |
| 2982 | |
| 2983 | if (amdgpu_fatal_error) |
| 2984 | return 0; |
| 2985 | |
| 2986 | id_entry = drm_find_description(PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff), |
| 2987 | PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff), pciidlist); |
| 2988 | if (id_entry != NULL((void *)0)) { |
| 2989 | flags = id_entry->driver_data; |
| 2990 | |
| 2991 | if (id_entry->device == PCI_ANY_ID(uint16_t) (~0U)) { |
| 2992 | if (PCI_CLASS(pa->pa_class)(((pa->pa_class) >> 24) & 0xff) != PCI_CLASS_DISPLAY0x03) |
| 2993 | return 0; |
| 2994 | if (PCI_SUBCLASS(pa->pa_class)(((pa->pa_class) >> 16) & 0xff) != PCI_SUBCLASS_DISPLAY_VGA0x00 && |
| 2995 | PCI_SUBCLASS(pa->pa_class)(((pa->pa_class) >> 16) & 0xff) != PCI_SUBCLASS_DISPLAY_MISC0x80) |
| 2996 | return 0; |
| 2997 | } |
| 2998 | |
| 2999 | /* skip devices which are owned by radeon */ |
| 3000 | for (i = 0; i < ARRAY_SIZE(amdgpu_unsupported_pciidlist)(sizeof((amdgpu_unsupported_pciidlist)) / sizeof((amdgpu_unsupported_pciidlist )[0])); i++) { |
| 3001 | if (amdgpu_unsupported_pciidlist[i] == |
| 3002 | PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff)) |
| 3003 | return 0; |
| 3004 | } |
| 3005 | |
| 3006 | if (flags & AMD_EXP_HW_SUPPORT) |
| 3007 | return 0; |
| 3008 | else |
| 3009 | return 20; |
| 3010 | } |
| 3011 | |
| 3012 | return 0; |
| 3013 | } |
| 3014 | |
| 3015 | /* |
| 3016 | * some functions are only called once on init regardless of how many times |
| 3017 | * amdgpu attaches in linux this is handled via module_init()/module_exit() |
| 3018 | */ |
| 3019 | int amdgpu_refcnt; |
| 3020 | |
| 3021 | int __init drm_sched_fence_slab_init(void); |
| 3022 | void __exit drm_sched_fence_slab_fini(void); |
| 3023 | irqreturn_t amdgpu_irq_handler(void *); |
| 3024 | |
| 3025 | void |
| 3026 | amdgpu_attach(struct device *parent, struct device *self, void *aux) |
| 3027 | { |
| 3028 | struct amdgpu_device *adev = (struct amdgpu_device *)self; |
| 3029 | struct drm_device *dev; |
| 3030 | struct pci_attach_args *pa = aux; |
| 3031 | const struct pci_device_id *id_entry; |
| 3032 | pcireg_t type; |
| 3033 | int i; |
| 3034 | uint8_t rmmio_bar; |
| 3035 | paddr_t fb_aper; |
| 3036 | pcireg_t addr, mask; |
| 3037 | int s; |
| 3038 | bool_Bool supports_atomic = false0; |
| 3039 | |
| 3040 | id_entry = drm_find_description(PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff), |
| 3041 | PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff), pciidlist); |
| 3042 | adev->flags = id_entry->driver_data; |
| 3043 | adev->family = adev->flags & AMD_ASIC_MASK; |
| 3044 | adev->pc = pa->pa_pc; |
| 3045 | adev->pa_tag = pa->pa_tag; |
| 3046 | adev->iot = pa->pa_iot; |
| 3047 | adev->memt = pa->pa_memt; |
| 3048 | adev->dmat = pa->pa_dmat; |
| 3049 | |
| 3050 | if (PCI_CLASS(pa->pa_class)(((pa->pa_class) >> 24) & 0xff) == PCI_CLASS_DISPLAY0x03 && |
| 3051 | PCI_SUBCLASS(pa->pa_class)(((pa->pa_class) >> 16) & 0xff) == PCI_SUBCLASS_DISPLAY_VGA0x00 && |
| 3052 | (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04) |
| 3053 | & (PCI_COMMAND_IO_ENABLE0x00000001 | PCI_COMMAND_MEM_ENABLE0x00000002)) |
| 3054 | == (PCI_COMMAND_IO_ENABLE0x00000001 | PCI_COMMAND_MEM_ENABLE0x00000002)) { |
| 3055 | adev->primary = 1; |
| 3056 | #if NVGA1 > 0 |
| 3057 | adev->console = vga_is_console(pa->pa_iot, -1); |
| 3058 | vga_console_attached = 1; |
| 3059 | #endif |
| 3060 | } |
| 3061 | #if NEFIFB1 > 0 |
| 3062 | if (efifb_is_primary(pa)) { |
| 3063 | adev->primary = 1; |
| 3064 | adev->console = efifb_is_console(pa); |
| 3065 | efifb_detach(); |
| 3066 | } |
| 3067 | #endif |
| 3068 | |
| 3069 | #define AMDGPU_PCI_MEM0x10 0x10 |
| 3070 | |
| 3071 | type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM0x10); |
| 3072 | if (PCI_MAPREG_TYPE(type)((type) & 0x00000001) != PCI_MAPREG_TYPE_MEM0x00000000 || |
| 3073 | pci_mapreg_info(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM0x10, |
| 3074 | type, &adev->fb_aper_offset, &adev->fb_aper_size, NULL((void *)0))) { |
| 3075 | printf(": can't get frambuffer info\n"); |
| 3076 | return; |
| 3077 | } |
| 3078 | |
| 3079 | if (adev->fb_aper_offset == 0) { |
| 3080 | bus_size_t start, end, pci_mem_end; |
| 3081 | bus_addr_t base; |
| 3082 | |
| 3083 | KASSERT(pa->pa_memex != NULL)((pa->pa_memex != ((void *)0)) ? (void)0 : __assert("diagnostic " , "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_drv.c", 3083, "pa->pa_memex != NULL" )); |
| 3084 | |
| 3085 | start = max(PCI_MEM_START, pa->pa_memex->ex_start)(((0x100000)>(pa->pa_memex->ex_start))?(0x100000):(pa ->pa_memex->ex_start)); |
| 3086 | if (PCI_MAPREG_MEM_TYPE(type)((type) & 0x00000006) == PCI_MAPREG_MEM_TYPE_64BIT0x00000004) |
| 3087 | pci_mem_end = PCI_MEM64_END0xffffffffffffffff; |
| 3088 | else |
| 3089 | pci_mem_end = PCI_MEM_END0xffffffff; |
| 3090 | end = min(pci_mem_end, pa->pa_memex->ex_end)(((pci_mem_end)<(pa->pa_memex->ex_end))?(pci_mem_end ):(pa->pa_memex->ex_end)); |
| 3091 | if (extent_alloc_subregion(pa->pa_memex, start, end, |
| 3092 | adev->fb_aper_size, adev->fb_aper_size, 0, 0, 0, &base)) { |
| 3093 | printf(": can't reserve framebuffer space\n"); |
| 3094 | return; |
| 3095 | } |
| 3096 | pci_conf_write(pa->pa_pc, pa->pa_tag, AMDGPU_PCI_MEM0x10, base); |
| 3097 | if (PCI_MAPREG_MEM_TYPE(type)((type) & 0x00000006) == PCI_MAPREG_MEM_TYPE_64BIT0x00000004) |
| 3098 | pci_conf_write(pa->pa_pc, pa->pa_tag, |
| 3099 | AMDGPU_PCI_MEM0x10 + 4, (uint64_t)base >> 32); |
| 3100 | adev->fb_aper_offset = base; |
| 3101 | } |
| 3102 | |
| 3103 | if (adev->family >= CHIP_BONAIRE) { |
| 3104 | type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); |
| 3105 | if (PCI_MAPREG_TYPE(type)((type) & 0x00000001) != PCI_MAPREG_TYPE_MEM0x00000000 || |
| 3106 | pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR0x0002, |
| 3107 | &adev->doorbell.bst, &adev->doorbell.bsh, |
| 3108 | &adev->doorbell.base, &adev->doorbell.size, 0)) { |
| 3109 | printf(": can't map doorbell space\n"); |
| 3110 | return; |
| 3111 | } |
| 3112 | adev->doorbell.ptr = bus_space_vaddr(adev->doorbell.bst,((adev->doorbell.bst)->vaddr((adev->doorbell.bsh))) |
| 3113 | adev->doorbell.bsh)((adev->doorbell.bst)->vaddr((adev->doorbell.bsh))); |
| 3114 | } |
| 3115 | |
| 3116 | if (adev->family >= CHIP_BONAIRE) |
| 3117 | rmmio_bar = 0x24; |
| 3118 | else |
| 3119 | rmmio_bar = 0x18; |
| 3120 | |
| 3121 | type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); |
| 3122 | if (PCI_MAPREG_TYPE(type)((type) & 0x00000001) != PCI_MAPREG_TYPE_MEM0x00000000 || |
| 3123 | pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR0x0002, |
| 3124 | &adev->rmmio_bst, &adev->rmmio_bsh, &adev->rmmio_base, |
| 3125 | &adev->rmmio_size, 0)) { |
| 3126 | printf(": can't map rmmio space\n"); |
| 3127 | return; |
| 3128 | } |
| 3129 | adev->rmmio = bus_space_vaddr(adev->rmmio_bst, adev->rmmio_bsh)((adev->rmmio_bst)->vaddr((adev->rmmio_bsh))); |
| 3130 | |
| 3131 | /* |
| 3132 | * Make sure we have a base address for the ROM such that we |
| 3133 | * can map it later. |
| 3134 | */ |
| 3135 | s = splhigh()splraise(0xd); |
| 3136 | addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG0x30); |
| 3137 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG0x30, ~PCI_ROM_ENABLE0x00000001); |
| 3138 | mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG0x30); |
| 3139 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG0x30, addr); |
| 3140 | splx(s)spllower(s); |
| 3141 | |
| 3142 | if (addr == 0 && PCI_ROM_SIZE(mask)(((mask) & 0xfffff800) & -((mask) & 0xfffff800)) != 0 && pa->pa_memex) { |
| 3143 | bus_size_t size, start, end; |
| 3144 | bus_addr_t base; |
| 3145 | |
| 3146 | size = PCI_ROM_SIZE(mask)(((mask) & 0xfffff800) & -((mask) & 0xfffff800)); |
| 3147 | start = max(PCI_MEM_START, pa->pa_memex->ex_start)(((0x100000)>(pa->pa_memex->ex_start))?(0x100000):(pa ->pa_memex->ex_start)); |
| 3148 | end = min(PCI_MEM_END, pa->pa_memex->ex_end)(((0xffffffff)<(pa->pa_memex->ex_end))?(0xffffffff): (pa->pa_memex->ex_end)); |
| 3149 | if (extent_alloc_subregion(pa->pa_memex, start, end, size, |
| 3150 | size, 0, 0, 0, &base) == 0) |
| 3151 | pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG0x30, base); |
| 3152 | } |
| 3153 | |
| 3154 | printf("\n"); |
| 3155 | |
| 3156 | /* from amdgpu_pci_probe(), aspm test done later */ |
| 3157 | |
| 3158 | if (!amdgpu_virtual_display && |
| 3159 | amdgpu_device_asic_has_dc_support(adev->family)) |
| 3160 | supports_atomic = true1; |
| 3161 | |
| 3162 | if ((adev->flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
| 3163 | DRM_INFO("This hardware requires experimental hardware support.\n")printk("\0016" "[" "drm" "] " "This hardware requires experimental hardware support.\n" ); |
| 3164 | return; |
| 3165 | } |
| 3166 | |
| 3167 | /* |
| 3168 | * Initialize amdkfd before starting radeon. |
| 3169 | */ |
| 3170 | amdgpu_amdkfd_init(); |
| 3171 | |
| 3172 | dev = drm_attach_pci(&amdgpu_kms_driver, pa, 0, adev->primary, |
| 3173 | self, &adev->ddev); |
| 3174 | if (dev == NULL((void *)0)) { |
| 3175 | printf("%s: drm attach failed\n", adev->self.dv_xname); |
| 3176 | return; |
| 3177 | } |
| 3178 | adev->pdev = dev->pdev; |
| 3179 | |
| 3180 | /* from amdgpu_pci_probe() */ |
| 3181 | if (amdgpu_aspm == -1 && !pcie_aspm_enabled(adev->pdev)) |
| 3182 | amdgpu_aspm = 0; |
| 3183 | |
| 3184 | if (!supports_atomic) |
| 3185 | dev->driver_features &= ~DRIVER_ATOMIC; |
| 3186 | |
| 3187 | if (!amdgpu_msi_ok(adev)) |
| 3188 | pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED0x20; |
| 3189 | |
| 3190 | /* from amdgpu_init() */ |
| 3191 | if (amdgpu_refcnt == 0) { |
| 3192 | drm_sched_fence_slab_init(); |
| 3193 | |
| 3194 | if (amdgpu_sync_init()) { |
| 3195 | printf("%s: amdgpu_sync_init failed\n", |
| 3196 | adev->self.dv_xname); |
| 3197 | return; |
| 3198 | } |
| 3199 | |
| 3200 | if (amdgpu_fence_slab_init()) { |
| 3201 | amdgpu_sync_fini(); |
| 3202 | printf("%s: amdgpu_fence_slab_init failed\n", |
| 3203 | adev->self.dv_xname); |
| 3204 | return; |
| 3205 | } |
| 3206 | |
| 3207 | amdgpu_register_atpx_handler(); |
| 3208 | amdgpu_acpi_detect(); |
| 3209 | } |
| 3210 | amdgpu_refcnt++; |
| 3211 | |
| 3212 | adev->irq.msi_enabled = false0; |
| 3213 | if (pci_intr_map_msi(pa, &adev->intrh) == 0) |
| 3214 | adev->irq.msi_enabled = true1; |
| 3215 | else if (pci_intr_map(pa, &adev->intrh) != 0) { |
| 3216 | printf("%s: couldn't map interrupt\n", adev->self.dv_xname); |
| 3217 | return; |
| 3218 | } |
| 3219 | printf("%s: %s\n", adev->self.dv_xname, |
| 3220 | pci_intr_string(pa->pa_pc, adev->intrh)); |
| 3221 | |
| 3222 | adev->irqh = pci_intr_establish(pa->pa_pc, adev->intrh, IPL_TTY0x9, |
| 3223 | amdgpu_irq_handler, &adev->ddev, adev->self.dv_xname); |
| 3224 | if (adev->irqh == NULL((void *)0)) { |
| 3225 | printf("%s: couldn't establish interrupt\n", |
| 3226 | adev->self.dv_xname); |
| 3227 | return; |
| 3228 | } |
| 3229 | adev->pdev->irq = 0; |
| 3230 | |
| 3231 | fb_aper = bus_space_mmap(adev->memt, adev->fb_aper_offset, 0, 0, 0)((adev->memt)->mmap((adev->fb_aper_offset), (0), (0) , (0))); |
| 3232 | if (fb_aper != -1) |
| 3233 | rasops_claim_framebuffer(fb_aper, adev->fb_aper_size, self); |
| 3234 | |
| 3235 | |
| 3236 | adev->shutdown = true1; |
| 3237 | config_mountroot(self, amdgpu_attachhook); |
| 3238 | } |
| 3239 | |
| 3240 | int |
| 3241 | amdgpu_forcedetach(struct amdgpu_device *adev) |
| 3242 | { |
| 3243 | struct pci_softc *sc = (struct pci_softc *)adev->self.dv_parent; |
| 3244 | pcitag_t tag = adev->pa_tag; |
| 3245 | |
| 3246 | #if NVGA1 > 0 |
| 3247 | if (adev->primary) |
| 3248 | vga_console_attached = 0; |
| 3249 | #endif |
| 3250 | |
| 3251 | /* reprobe pci device for non efi systems */ |
| 3252 | #if NEFIFB1 > 0 |
| 3253 | if (bios_efiinfo == NULL((void *)0) && !efifb_cb_found()) { |
| 3254 | #endif |
| 3255 | config_detach(&adev->self, 0); |
| 3256 | return pci_probe_device(sc, tag, NULL((void *)0), NULL((void *)0)); |
| 3257 | #if NEFIFB1 > 0 |
| 3258 | } else if (adev->primary) { |
| 3259 | efifb_reattach(); |
| 3260 | } |
| 3261 | #endif |
| 3262 | |
| 3263 | return 0; |
| 3264 | } |
| 3265 | |
| 3266 | void amdgpu_burner(void *, u_int, u_int); |
| 3267 | void amdgpu_burner_cb(void *); |
| 3268 | int amdgpu_wsioctl(void *, u_long, caddr_t, int, struct proc *); |
| 3269 | paddr_t amdgpu_wsmmap(void *, off_t, int); |
| 3270 | int amdgpu_alloc_screen(void *, const struct wsscreen_descr *, |
| 3271 | void **, int *, int *, uint32_t *); |
| 3272 | void amdgpu_free_screen(void *, void *); |
| 3273 | int amdgpu_show_screen(void *, void *, int, |
| 3274 | void (*)(void *, int, int), void *); |
| 3275 | void amdgpu_doswitch(void *); |
| 3276 | void amdgpu_enter_ddb(void *, void *); |
| 3277 | |
| 3278 | struct wsscreen_descr amdgpu_stdscreen = { |
| 3279 | "std", |
| 3280 | 0, 0, |
| 3281 | 0, |
| 3282 | 0, 0, |
| 3283 | WSSCREEN_UNDERLINE16 | WSSCREEN_HILIT4 | |
| 3284 | WSSCREEN_REVERSE2 | WSSCREEN_WSCOLORS1 |
| 3285 | }; |
| 3286 | |
| 3287 | const struct wsscreen_descr *amdgpu_scrlist[] = { |
| 3288 | &amdgpu_stdscreen, |
| 3289 | }; |
| 3290 | |
| 3291 | struct wsscreen_list amdgpu_screenlist = { |
| 3292 | nitems(amdgpu_scrlist)(sizeof((amdgpu_scrlist)) / sizeof((amdgpu_scrlist)[0])), amdgpu_scrlist |
| 3293 | }; |
| 3294 | |
| 3295 | struct wsdisplay_accessops amdgpu_accessops = { |
| 3296 | .ioctl = amdgpu_wsioctl, |
| 3297 | .mmap = amdgpu_wsmmap, |
| 3298 | .alloc_screen = amdgpu_alloc_screen, |
| 3299 | .free_screen = amdgpu_free_screen, |
| 3300 | .show_screen = amdgpu_show_screen, |
| 3301 | .enter_ddb = amdgpu_enter_ddb, |
| 3302 | .getchar = rasops_getchar, |
| 3303 | .load_font = rasops_load_font, |
| 3304 | .list_font = rasops_list_font, |
| 3305 | .scrollback = rasops_scrollback, |
| 3306 | .burn_screen = amdgpu_burner |
| 3307 | }; |
| 3308 | |
| 3309 | int |
| 3310 | amdgpu_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) |
| 3311 | { |
| 3312 | struct rasops_info *ri = v; |
| 3313 | struct amdgpu_device *adev = ri->ri_hw; |
| 3314 | struct backlight_device *bd = adev->dm.backlight_dev[0]; |
| 3315 | struct wsdisplay_param *dp = (struct wsdisplay_param *)data; |
| 3316 | struct wsdisplay_fbinfo *wdf; |
| 3317 | |
| 3318 | switch (cmd) { |
| 3319 | case WSDISPLAYIO_GTYPE((unsigned long)0x40000000 | ((sizeof(u_int) & 0x1fff) << 16) | ((('W')) << 8) | ((64))): |
| 3320 | *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM70; |
| 3321 | return 0; |
| 3322 | case WSDISPLAYIO_GINFO((unsigned long)0x40000000 | ((sizeof(struct wsdisplay_fbinfo ) & 0x1fff) << 16) | ((('W')) << 8) | ((65))): |
| 3323 | wdf = (struct wsdisplay_fbinfo *)data; |
| 3324 | wdf->width = ri->ri_width; |
| 3325 | wdf->height = ri->ri_height; |
| 3326 | wdf->depth = ri->ri_depth; |
| 3327 | wdf->stride = ri->ri_stride; |
| 3328 | wdf->offset = 0; |
| 3329 | wdf->cmsize = 0; |
| 3330 | return 0; |
| 3331 | case WSDISPLAYIO_GETPARAM(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct wsdisplay_param) & 0x1fff) << 16) | ((('W') ) << 8) | ((89))): |
| 3332 | if (bd == NULL((void *)0)) |
| 3333 | return -1; |
| 3334 | |
| 3335 | switch (dp->param) { |
| 3336 | case WSDISPLAYIO_PARAM_BRIGHTNESS2: |
| 3337 | dp->min = 0; |
| 3338 | dp->max = bd->props.max_brightness; |
| 3339 | dp->curval = bd->props.brightness; |
| 3340 | return (dp->max > dp->min) ? 0 : -1; |
| 3341 | } |
| 3342 | break; |
| 3343 | case WSDISPLAYIO_SETPARAM(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct wsdisplay_param) & 0x1fff) << 16) | ((('W') ) << 8) | ((90))): |
| 3344 | if (bd == NULL((void *)0) || dp->curval > bd->props.max_brightness) |
| 3345 | return -1; |
| 3346 | |
| 3347 | switch (dp->param) { |
| 3348 | case WSDISPLAYIO_PARAM_BRIGHTNESS2: |
| 3349 | bd->props.brightness = dp->curval; |
| 3350 | backlight_update_status(bd); |
| 3351 | knote_locked(&adev->ddev.note, NOTE_CHANGE0x00000001); |
| 3352 | return 0; |
| 3353 | } |
| 3354 | break; |
| 3355 | case WSDISPLAYIO_SVIDEO((unsigned long)0x80000000 | ((sizeof(u_int) & 0x1fff) << 16) | ((('W')) << 8) | ((69))): |
| 3356 | case WSDISPLAYIO_GVIDEO((unsigned long)0x40000000 | ((sizeof(u_int) & 0x1fff) << 16) | ((('W')) << 8) | ((68))): |
| 3357 | return 0; |
| 3358 | } |
| 3359 | |
| 3360 | return (-1); |
| 3361 | } |
| 3362 | |
| 3363 | paddr_t |
| 3364 | amdgpu_wsmmap(void *v, off_t off, int prot) |
| 3365 | { |
| 3366 | return (-1); |
| 3367 | } |
| 3368 | |
| 3369 | int |
| 3370 | amdgpu_alloc_screen(void *v, const struct wsscreen_descr *type, |
| 3371 | void **cookiep, int *curxp, int *curyp, uint32_t *attrp) |
| 3372 | { |
| 3373 | return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); |
| 3374 | } |
| 3375 | |
| 3376 | void |
| 3377 | amdgpu_free_screen(void *v, void *cookie) |
| 3378 | { |
| 3379 | return rasops_free_screen(v, cookie); |
| 3380 | } |
| 3381 | |
| 3382 | int |
| 3383 | amdgpu_show_screen(void *v, void *cookie, int waitok, |
| 3384 | void (*cb)(void *, int, int), void *cbarg) |
| 3385 | { |
| 3386 | struct rasops_info *ri = v; |
| 3387 | struct amdgpu_device *adev = ri->ri_hw; |
| 3388 | |
| 3389 | if (cookie == ri->ri_active) |
| 3390 | return (0); |
| 3391 | |
| 3392 | adev->switchcb = cb; |
| 3393 | adev->switchcbarg = cbarg; |
| 3394 | adev->switchcookie = cookie; |
| 3395 | if (cb) { |
| 3396 | task_add(systq, &adev->switchtask); |
| 3397 | return (EAGAIN35); |
| 3398 | } |
| 3399 | |
| 3400 | amdgpu_doswitch(v); |
| 3401 | |
| 3402 | return (0); |
| 3403 | } |
| 3404 | |
| 3405 | void |
| 3406 | amdgpu_doswitch(void *v) |
| 3407 | { |
| 3408 | struct rasops_info *ri = v; |
| 3409 | struct amdgpu_device *adev = ri->ri_hw; |
| 3410 | struct amdgpu_crtc *amdgpu_crtc; |
| 3411 | int i, crtc; |
| 3412 | |
| 3413 | rasops_show_screen(ri, adev->switchcookie, 0, NULL((void *)0), NULL((void *)0)); |
| 3414 | drm_fb_helper_restore_fbdev_mode_unlocked(adev_to_drm(adev)->fb_helper); |
| 3415 | |
| 3416 | if (adev->switchcb) |
| 3417 | (adev->switchcb)(adev->switchcbarg, 0, 0); |
| 3418 | } |
| 3419 | |
| 3420 | void |
| 3421 | amdgpu_enter_ddb(void *v, void *cookie) |
| 3422 | { |
| 3423 | struct rasops_info *ri = v; |
| 3424 | struct amdgpu_device *adev = ri->ri_hw; |
| 3425 | struct drm_fb_helper *fb_helper = adev_to_drm(adev)->fb_helper; |
| 3426 | |
| 3427 | if (cookie == ri->ri_active) |
| 3428 | return; |
| 3429 | |
| 3430 | rasops_show_screen(ri, cookie, 0, NULL((void *)0), NULL((void *)0)); |
| 3431 | drm_fb_helper_debug_enter(fb_helper->fbdev); |
| 3432 | } |
| 3433 | |
| 3434 | void |
| 3435 | amdgpu_init_backlight(struct amdgpu_device *adev) |
| 3436 | { |
| 3437 | struct drm_device *dev = &adev->ddev; |
| 3438 | struct backlight_device *bd = adev->dm.backlight_dev[0]; |
| 3439 | struct drm_connector_list_iter conn_iter; |
| 3440 | struct drm_connector *connector; |
| 3441 | |
| 3442 | if (bd == NULL((void *)0)) |
| 3443 | return; |
| 3444 | |
| 3445 | drm_connector_list_iter_begin(dev, &conn_iter); |
| 3446 | drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter ))) { |
| 3447 | if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS7 && |
| 3448 | connector->connector_type != DRM_MODE_CONNECTOR_eDP14 && |
| 3449 | connector->connector_type != DRM_MODE_CONNECTOR_DSI16) |
| 3450 | continue; |
| 3451 | |
| 3452 | connector->backlight_device = bd; |
| 3453 | connector->backlight_property = drm_property_create_range(dev, |
| 3454 | 0, "Backlight", 0, bd->props.max_brightness); |
| 3455 | drm_object_attach_property(&connector->base, |
| 3456 | connector->backlight_property, bd->props.brightness); |
| 3457 | } |
| 3458 | drm_connector_list_iter_end(&conn_iter); |
| 3459 | } |
| 3460 | |
| 3461 | void |
| 3462 | amdgpu_attachhook(struct device *self) |
| 3463 | { |
| 3464 | struct amdgpu_device *adev = (struct amdgpu_device *)self; |
| 3465 | struct drm_device *dev = &adev->ddev; |
| 3466 | int r, acpi_status; |
| 3467 | struct rasops_info *ri = &adev->ro; |
| 3468 | struct drm_fb_helper *fb_helper; |
| 3469 | struct drm_framebuffer *fb; |
| 3470 | struct drm_gem_object *obj; |
| 3471 | struct amdgpu_bo *rbo; |
| 3472 | |
| 3473 | /* from amdgpu_driver_load_kms() */ |
| 3474 | |
| 3475 | /* amdgpu_device_init should report only fatal error |
| 3476 | * like memory allocation failure or iomapping failure, |
| 3477 | * or memory manager initialization failure, it must |
| 3478 | * properly initialize the GPU MC controller and permit |
| 3479 | * VRAM allocation |
| 3480 | */ |
| 3481 | r = amdgpu_device_init(adev, adev->flags); |
| 3482 | if (r) { |
| 3483 | dev_err(&dev->pdev->dev, "Fatal error during GPU init\n")printf("drm:pid%d:%s *ERROR* " "Fatal error during GPU init\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 3484 | goto out; |
| 3485 | } |
| 3486 | |
| 3487 | adev->pm.rpm_mode = AMDGPU_RUNPM_NONE; |
| 3488 | if (amdgpu_device_supports_px(dev) && |
| 3489 | (amdgpu_runtime_pm != 0)) { /* enable PX as runtime mode */ |
| 3490 | adev->pm.rpm_mode = AMDGPU_RUNPM_PX; |
| 3491 | dev_info(adev->dev, "Using ATPX for runtime pm\n")do { } while(0); |
| 3492 | } else if (amdgpu_device_supports_boco(dev) && |
| 3493 | (amdgpu_runtime_pm != 0)) { /* enable boco as runtime mode */ |
| 3494 | adev->pm.rpm_mode = AMDGPU_RUNPM_BOCO; |
| 3495 | dev_info(adev->dev, "Using BOCO for runtime pm\n")do { } while(0); |
| 3496 | } else if (amdgpu_device_supports_baco(dev) && |
| 3497 | (amdgpu_runtime_pm != 0)) { |
| 3498 | switch (adev->asic_type) { |
| 3499 | case CHIP_VEGA20: |
| 3500 | case CHIP_ARCTURUS: |
| 3501 | /* enable BACO as runpm mode if runpm=1 */ |
| 3502 | if (amdgpu_runtime_pm > 0) |
| 3503 | adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; |
| 3504 | break; |
| 3505 | case CHIP_VEGA10: |
| 3506 | /* enable BACO as runpm mode if noretry=0 */ |
| 3507 | if (!adev->gmc.noretry) |
| 3508 | adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; |
| 3509 | break; |
| 3510 | default: |
| 3511 | /* enable BACO as runpm mode on CI+ */ |
| 3512 | adev->pm.rpm_mode = AMDGPU_RUNPM_BACO; |
| 3513 | break; |
| 3514 | } |
| 3515 | |
| 3516 | if (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO) |
| 3517 | dev_info(adev->dev, "Using BACO for runtime pm\n")do { } while(0); |
| 3518 | } |
| 3519 | |
| 3520 | /* Call ACPI methods: require modeset init |
| 3521 | * but failure is not fatal |
| 3522 | */ |
| 3523 | |
| 3524 | acpi_status = amdgpu_acpi_init(adev); |
| 3525 | if (acpi_status) |
| 3526 | dev_dbg(dev->dev, "Error during ACPI methods call\n")do { } while(0); |
| 3527 | |
| 3528 | if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD)) |
| 3529 | DRM_WARN("smart shift update failed\n")printk("\0014" "[" "drm" "] " "smart shift update failed\n"); |
| 3530 | |
| 3531 | /* |
| 3532 | * 1. don't init fbdev on hw without DCE |
| 3533 | * 2. don't init fbdev if there are no connectors |
| 3534 | */ |
| 3535 | if (adev->mode_info.mode_config_initialized && |
| 3536 | !list_empty(&adev_to_drm(adev)->mode_config.connector_list)) { |
| 3537 | |
| 3538 | /* OpenBSD specific backlight property on connector */ |
| 3539 | amdgpu_init_backlight(adev); |
| 3540 | |
| 3541 | /* |
| 3542 | * in linux via amdgpu_pci_probe -> drm_dev_register |
| 3543 | * must be after (local) backlight property added not before |
| 3544 | * and before drm_fbdev_generic_setup() |
| 3545 | */ |
| 3546 | drm_dev_register(dev, adev->flags); |
| 3547 | |
| 3548 | /* select 8 bpp console on low vram cards */ |
| 3549 | if (adev->gmc.real_vram_size <= (32*1024*1024)) |
| 3550 | drm_fbdev_generic_setup(adev_to_drm(adev), 8); |
| 3551 | else |
| 3552 | drm_fbdev_generic_setup(adev_to_drm(adev), 32); |
| 3553 | |
| 3554 | fb_helper = adev_to_drm(adev)->fb_helper; |
| 3555 | if (fb_helper == NULL((void *)0)) { |
| 3556 | printf("fb_helper NULL\n"); |
| 3557 | return; |
| 3558 | } |
| 3559 | fb = fb_helper->fb; |
| 3560 | obj = fb->obj[0]; |
| 3561 | rbo = gem_to_amdgpu_bo(obj)({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr = ((obj)); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof (struct amdgpu_bo, tbo.base) );}); |
| 3562 | amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM0x4); |
| 3563 | amdgpu_bo_kmap(rbo, (void **)(&ri->ri_bits)); |
| 3564 | |
| 3565 | ri->ri_depth = fb->format->cpp[0] * 8; |
| 3566 | ri->ri_stride = fb->pitches[0]; |
| 3567 | ri->ri_width = fb_helper->fbdev->var.xres; |
| 3568 | ri->ri_height = fb_helper->fbdev->var.yres; |
| 3569 | |
| 3570 | switch (fb->format->format) { |
| 3571 | case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') << 16) | ((__u32)('4') << 24)): |
| 3572 | ri->ri_rnum = 8; |
| 3573 | ri->ri_rpos = 16; |
| 3574 | ri->ri_gnum = 8; |
| 3575 | ri->ri_gpos = 8; |
| 3576 | ri->ri_bnum = 8; |
| 3577 | ri->ri_bpos = 0; |
| 3578 | break; |
| 3579 | case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') << 16) | ((__u32)('6') << 24)): |
| 3580 | ri->ri_rnum = 5; |
| 3581 | ri->ri_rpos = 11; |
| 3582 | ri->ri_gnum = 6; |
| 3583 | ri->ri_gpos = 5; |
| 3584 | ri->ri_bnum = 5; |
| 3585 | ri->ri_bpos = 0; |
| 3586 | break; |
| 3587 | } |
| 3588 | } |
| 3589 | { |
| 3590 | struct wsemuldisplaydev_attach_args aa; |
| 3591 | int orientation_quirk; |
| 3592 | |
| 3593 | task_set(&adev->switchtask, amdgpu_doswitch, ri); |
| 3594 | task_set(&adev->burner_task, amdgpu_burner_cb, adev); |
| 3595 | |
| 3596 | if (ri->ri_bits == NULL((void *)0)) |
| 3597 | return; |
| 3598 | |
| 3599 | ri->ri_flg = RI_CENTER0x0040 | RI_VCONS0x0800 | RI_WRONLY0x1000; |
| 3600 | |
| 3601 | orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width, |
| 3602 | ri->ri_height); |
| 3603 | if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP) |
| 3604 | ri->ri_flg |= RI_ROTATE_CCW0x0200; |
| 3605 | else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP) |
| 3606 | ri->ri_flg |= RI_ROTATE_CW0x0100; |
| 3607 | |
| 3608 | rasops_init(ri, 160, 160); |
| 3609 | |
| 3610 | ri->ri_hw = adev; |
| 3611 | |
| 3612 | amdgpu_stdscreen.capabilities = ri->ri_caps; |
| 3613 | amdgpu_stdscreen.nrows = ri->ri_rows; |
| 3614 | amdgpu_stdscreen.ncols = ri->ri_cols; |
| 3615 | amdgpu_stdscreen.textops = &ri->ri_ops; |
| 3616 | amdgpu_stdscreen.fontwidth = ri->ri_font->fontwidth; |
| 3617 | amdgpu_stdscreen.fontheight = ri->ri_font->fontheight; |
| 3618 | |
| 3619 | aa.console = adev->console; |
| 3620 | aa.primary = adev->primary; |
| 3621 | aa.scrdata = &amdgpu_screenlist; |
| 3622 | aa.accessops = &amdgpu_accessops; |
| 3623 | aa.accesscookie = ri; |
| 3624 | aa.defaultscreens = 0; |
| 3625 | |
| 3626 | if (adev->console) { |
| 3627 | uint32_t defattr; |
| 3628 | |
| 3629 | ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); |
| 3630 | wsdisplay_cnattach(&amdgpu_stdscreen, ri->ri_active, |
| 3631 | ri->ri_ccol, ri->ri_crow, defattr); |
| 3632 | } |
| 3633 | |
| 3634 | /* |
| 3635 | * Now that we've taken over the console, disable decoding of |
| 3636 | * VGA legacy addresses, and opt out of arbitration. |
| 3637 | */ |
| 3638 | amdgpu_asic_set_vga_state(adev, false)(adev)->asic_funcs->set_vga_state((adev), (0)); |
| 3639 | pci_disable_legacy_vga(&adev->self); |
| 3640 | |
| 3641 | printf("%s: %dx%d, %dbpp\n", adev->self.dv_xname, |
| 3642 | ri->ri_width, ri->ri_height, ri->ri_depth); |
| 3643 | |
| 3644 | config_found_sm(&adev->self, &aa, wsemuldisplaydevprint, |
| 3645 | wsemuldisplaydevsubmatch); |
| 3646 | } |
| 3647 | |
| 3648 | out: |
| 3649 | if (r) { |
| 3650 | amdgpu_fatal_error = 1; |
| 3651 | amdgpu_forcedetach(adev); |
| 3652 | } |
| 3653 | } |
| 3654 | |
| 3655 | /* from amdgpu_exit amdgpu_driver_unload_kms */ |
| 3656 | int |
| 3657 | amdgpu_detach(struct device *self, int flags) |
| 3658 | { |
| 3659 | struct amdgpu_device *adev = (struct amdgpu_device *)self; |
| 3660 | struct drm_device *dev = &adev->ddev; |
| 3661 | |
| 3662 | if (adev == NULL((void *)0)) |
| 3663 | return 0; |
| 3664 | |
| 3665 | amdgpu_refcnt--; |
| 3666 | |
| 3667 | if (amdgpu_refcnt == 0) |
| 3668 | amdgpu_amdkfd_fini(); |
| 3669 | |
| 3670 | pci_intr_disestablish(adev->pc, adev->irqh); |
| 3671 | |
| 3672 | amdgpu_unregister_gpu_instance(adev); |
| 3673 | |
| 3674 | amdgpu_acpi_fini(adev); |
| 3675 | amdgpu_device_fini_hw(adev); |
| 3676 | |
| 3677 | if (amdgpu_refcnt == 0) { |
| 3678 | amdgpu_unregister_atpx_handler(); |
| 3679 | amdgpu_sync_fini(); |
| 3680 | amdgpu_fence_slab_fini(); |
| 3681 | |
| 3682 | drm_sched_fence_slab_fini(); |
| 3683 | } |
| 3684 | |
| 3685 | config_detach(adev->ddev.dev, flags); |
| 3686 | |
| 3687 | return 0; |
| 3688 | } |
| 3689 | |
| 3690 | int |
| 3691 | amdgpu_activate(struct device *self, int act) |
| 3692 | { |
| 3693 | struct amdgpu_device *adev = (struct amdgpu_device *)self; |
| 3694 | struct drm_device *dev = &adev->ddev; |
| 3695 | int rv = 0; |
| 3696 | |
| 3697 | if (dev->dev == NULL((void *)0) || amdgpu_fatal_error) |
| 3698 | return (0); |
| 3699 | |
| 3700 | switch (act) { |
| 3701 | case DVACT_QUIESCE2: |
| 3702 | rv = config_activate_children(self, act); |
| 3703 | amdgpu_device_suspend(dev, true1); |
| 3704 | break; |
| 3705 | case DVACT_SUSPEND3: |
| 3706 | break; |
| 3707 | case DVACT_RESUME4: |
| 3708 | break; |
| 3709 | case DVACT_WAKEUP5: |
| 3710 | amdgpu_device_resume(dev, true1); |
| 3711 | rv = config_activate_children(self, act); |
| 3712 | break; |
| 3713 | } |
| 3714 | |
| 3715 | return (rv); |
| 3716 | } |
| 3717 | |
| 3718 | void |
| 3719 | amdgpu_burner(void *v, u_int on, u_int flags) |
| 3720 | { |
| 3721 | struct rasops_info *ri = v; |
| 3722 | struct amdgpu_device *adev = ri->ri_hw; |
| 3723 | |
| 3724 | task_del(systq, &adev->burner_task); |
| 3725 | |
| 3726 | if (on) |
| 3727 | adev->burner_fblank = FB_BLANK_UNBLANK0; |
| 3728 | else { |
| 3729 | if (flags & WSDISPLAY_BURN_VBLANK0x0001) |
| 3730 | adev->burner_fblank = FB_BLANK_VSYNC_SUSPEND3; |
| 3731 | else |
| 3732 | adev->burner_fblank = FB_BLANK_NORMAL1; |
| 3733 | } |
| 3734 | |
| 3735 | /* |
| 3736 | * Setting the DPMS mode may sleep while waiting for vblank so |
| 3737 | * hand things off to a taskq. |
| 3738 | */ |
| 3739 | task_add(systq, &adev->burner_task); |
| 3740 | } |
| 3741 | |
| 3742 | void |
| 3743 | amdgpu_burner_cb(void *arg1) |
| 3744 | { |
| 3745 | struct amdgpu_device *adev = arg1; |
| 3746 | struct drm_fb_helper *helper = adev_to_drm(adev)->fb_helper; |
| 3747 | |
| 3748 | drm_fb_helper_blank(adev->burner_fblank, helper->fbdev); |
| 3749 | } |