/usr/src/sys/dev/usb/if

Bug Summary

File:	dev/usb/if_ure.c
Warning:	line 291, column 6 Assigned value is garbage or undefined
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name if_ure.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/usb/if_ure.c
1/*	$OpenBSD: if_ure.c,v 1.33 2023/09/09 14:23:37 kevlo Exp $	*/
2/*-
* Copyright (c) 2015, 2016, 2019 Kevin Lo <kevlo@openbsd.org>
* Copyright (c) 2020 Jonathon Fletcher <jonathon.fletcher@gmail.com>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
*    notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*    notice, this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/

29#include "bpfilter.h"
30#include "vlan.h"

32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/sockio.h>
35#include <sys/rwlock.h>
36#include <sys/mbuf.h>
37#include <sys/kernel.h>
38#include <sys/socket.h>
39#include <sys/device.h>

41#include <machine/bus.h>

43#include <net/if.h>
44#include <net/if_media.h>

46#if NBPFILTER1 > 0
47#include <net/bpf.h>
48#endif

50#include <netinet/in.h>
51#include <netinet/if_ether.h>

53#include <dev/mii/mii.h>
54#include <dev/mii/miivar.h>

56#include <dev/usb/usb.h>
57#include <dev/usb/usbdi.h>
58#include <dev/usb/usbdi_util.h>
59#include <dev/usb/usbdivar.h>
60#include <dev/usb/usbdevs.h>

62#include <dev/ic/rtl81x9reg.h>
63#include <dev/usb/if_urereg.h>

65#ifdef URE_DEBUG
66#define DPRINTF(x)	do { if (uredebug) printf x; } while (0)
67#define DPRINTFN(n,x)	do { if (uredebug >= (n)) printf x; } while (0)
68int	uredebug = 0;
69#else
70#define DPRINTF(x)
71#define DPRINTFN(n,x)
72#endif

74const struct usb_devno ure_devs[] = {
{ USB_VENDOR_ASUS0x0b05, USB_PRODUCT_ASUS_RTL81560x18d1 },
{ USB_VENDOR_BELKIN0x050d, USB_PRODUCT_BELKIN_RTL8152B0x047a },
{ USB_VENDOR_BELKIN0x050d, USB_PRODUCT_BELKIN_RTL81530x048a },
{ USB_VENDOR_CISCOLINKSYS0x13b1, USB_PRODUCT_CISCOLINKSYS_USB3GIGV10x0041 },
{ USB_VENDOR_CLEVO0x30da, USB_PRODUCT_CLEVO_RTL8153B0x5101 },
{ USB_VENDOR_CLUB3D0x2d1c, USB_PRODUCT_CLUB3D_RTL81530x8153 },
{ USB_VENDOR_DLINK0x2001, USB_PRODUCT_DLINK_RTL8153_10x7e34 },
{ USB_VENDOR_DLINK0x2001, USB_PRODUCT_DLINK_RTL8153_20xa710 },
{ USB_VENDOR_DYNABOOK0x30f3, USB_PRODUCT_DYNABOOK_RTL8153B_10x0419 },
{ USB_VENDOR_DYNABOOK0x30f3, USB_PRODUCT_DYNABOOK_RTL8153B_20x0425 },
{ USB_VENDOR_ELECOM0x056e, USB_PRODUCT_ELECOM_RTL8153B0x4013 },
{ USB_VENDOR_ELECOM0x056e, USB_PRODUCT_ELECOM_RTL8156B0x4017 },
{ USB_VENDOR_IOI0x0f21, USB_PRODUCT_IOI_RTL81530x8153 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_DOCK_ETHERNET0x3062 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINK0x720a },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINKPLUS0x3054 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_ONELINKPRO0x304f },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_10x3069 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_20x3098 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_30x309b },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_40x309c },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_50x309d },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_60x7214 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_70x721e },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_80x8153 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153B_90xa359 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_10x7205 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_20x720b },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_RTL8153_30x720c },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TABLETDOCK0x3052 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3DOCK0xa3c1 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3DOCKGEN20x3082 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_TB3GFXDOCK0x3065 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_USBCDOCKGEN20xa387 },
{ USB_VENDOR_LENOVO0x17ef, USB_PRODUCT_LENOVO_WIGIGDOCK0x3057 },
{ USB_VENDOR_LG0x043e, USB_PRODUCT_LG_RTL81530x9819 },
{ USB_VENDOR_LG0x043e, USB_PRODUCT_LG_RTL8153B0x9820 },
{ USB_VENDOR_LUXSHARE0x208e, USB_PRODUCT_LUXSHARE_RTL81530xd003 },
{ USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_DOCKETH0x07ab },
{ USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_DOCKETH20x07c6 },
{ USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_SURFETH0x0927 },
{ USB_VENDOR_MICROSOFT0x045e, USB_PRODUCT_MICROSOFT_WINDEVETH0x0c5e },
{ USB_VENDOR_NVIDIA0x0955, USB_PRODUCT_NVIDIA_TEGRAETH0x09ff },
{ USB_VENDOR_PIONEERDJ0x2b73, USB_PRODUCT_PIONEERDJ_RTL8152B0x0007 },
{ USB_VENDOR_PIONEERDJ0x2b73, USB_PRODUCT_PIONEERDJ_RTL8153B0x0031 },
{ USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81520x8152 },
{ USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL8152B0x8050 },
{ USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81530x8153 },
{ USB_VENDOR_REALTEK0x0bda, USB_PRODUCT_REALTEK_RTL81560x8156 },
{ USB_VENDOR_SAMSUNG20x04e8, USB_PRODUCT_SAMSUNG2_RTL81530xa101 },
{ USB_VENDOR_TOSHIBA0x0930, USB_PRODUCT_TOSHIBA_RTL8153B0x0416 },
{ USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_EU3000x0601 },
{ USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL8152B_10x0602 },
{ USB_VENDOR_TPLINK0x2357, USB_PRODUCT_TPLINK_RTL8152B_20x0603 },
{ USB_VENDOR_TRENDNET0x20f4, USB_PRODUCT_TRENDNET_RTL81560xe02b },
{ USB_VENDOR_TTL0x1025, USB_PRODUCT_TTL_RTL81530x104e },
{ USB_VENDOR_TWINHEAD0x14ff, USB_PRODUCT_TWINHEAD_RTL8153B0x1400 },
{ USB_VENDOR_XIAOMI0x2717, USB_PRODUCT_XIAOMI_RTL8152B0x0011 },
133};

135int	ure_match(struct device *, void *, void *);
136void	ure_attach(struct device *, struct device *, void *);
137int	ure_detach(struct device *, int);

139struct cfdriver ure_cd = {
NULL((void *)0), "ure", DV_IFNET
141};

143const struct cfattach ure_ca = {
sizeof(struct ure_softc), ure_match, ure_attach, ure_detach
145};

147int		ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
    void *, int);
149int		ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *,
    int);
151int		ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *,
    int);
153uint8_t		ure_read_1(struct ure_softc *, uint16_t, uint16_t);
154uint16_t	ure_read_2(struct ure_softc *, uint16_t, uint16_t);
155uint32_t	ure_read_4(struct ure_softc *, uint16_t, uint16_t);
156int		ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t);
157int		ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t);
158int		ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t);
159uint16_t	ure_ocp_reg_read(struct ure_softc *, uint16_t);
160void		ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t);

162void		ure_init(void *);
163void		ure_stop(struct ure_softc *);
164void		ure_start(struct ifnet *);
165void		ure_reset(struct ure_softc *);
166void		ure_watchdog(struct ifnet *);

168void		ure_miibus_statchg(struct device *);
169int		ure_miibus_readreg(struct device *, int, int);
170void		ure_miibus_writereg(struct device *, int, int, int);
171void		ure_lock_mii(struct ure_softc *);
172void		ure_unlock_mii(struct ure_softc *);

174int		ure_encap_txpkt(struct mbuf *, char *, uint32_t);
175int		ure_encap_xfer(struct ifnet *, struct ure_softc *,
    struct ure_chain *);
177void		ure_rxeof(struct usbd_xfer *, void *, usbd_status);
178void		ure_txeof(struct usbd_xfer *, void *, usbd_status);
179int		ure_xfer_list_init(struct ure_softc *, struct ure_chain *,
    uint32_t, int);
181void		ure_xfer_list_free(struct ure_softc *, struct ure_chain *, int);

183void		ure_tick_task(void *);
184void		ure_tick(void *);

186void		ure_ifmedia_init(struct ifnet *);
187int		ure_ifmedia_upd(struct ifnet *);
188void		ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
189void		ure_add_media_types(struct ure_softc *);
190void		ure_link_state(struct ure_softc *);
191int		ure_get_link_status(struct ure_softc *);
192void		ure_iff(struct ure_softc *);
193void		ure_rxvlan(struct ure_softc *);
194int		ure_ioctl(struct ifnet *, u_long, caddr_t);
195void		ure_rtl8152_init(struct ure_softc *);
196void		ure_rtl8153_init(struct ure_softc *);
197void		ure_rtl8153b_init(struct ure_softc *);
198void		ure_rtl8152_nic_reset(struct ure_softc *);
199void		ure_rtl8153_nic_reset(struct ure_softc *);
200uint16_t	ure_rtl8153_phy_status(struct ure_softc *, int);
201void		ure_wait_for_flash(struct ure_softc *);
202void		ure_reset_bmu(struct ure_softc *);
203void		ure_disable_teredo(struct ure_softc *);

205#define URE_SETBIT_1(sc, reg, index, x)ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) \
ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x))
207#define URE_SETBIT_2(sc, reg, index, x)ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) \
ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x))
209#define URE_SETBIT_4(sc, reg, index, x)ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) \
ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x))

212#define URE_CLRBIT_1(sc, reg, index, x)ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~
(x)) \
ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x))
214#define URE_CLRBIT_2(sc, reg, index, x)ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~
(x)) \
ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x))
216#define URE_CLRBIT_4(sc, reg, index, x)ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~
(x)) \
ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x))

219int
220ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index,
  void *buf, int len)
222{
usb_device_request_t	req;
usbd_status		err;

if (usbd_is_dying(sc->ure_udev))
6
←
Assuming the condition is true→
7
←
Taking true branch→
return 0;

if (rw == URE_CTL_WRITE0x02)
req.bmRequestType = UT_WRITE_VENDOR_DEVICE(0x00 | 0x40 | 0x00);
else
req.bmRequestType = UT_READ_VENDOR_DEVICE(0x80 | 0x40 | 0x00);
req.bRequest = UR_SET_ADDRESS0x05;
USETW(req.wValue, val)(*(u_int16_t *)(req.wValue) = (val));
USETW(req.wIndex, index)(*(u_int16_t *)(req.wIndex) = (index));
USETW(req.wLength, len)(*(u_int16_t *)(req.wLength) = (len));

DPRINTFN(5, ("ure_ctl: rw %d, val 0x%04hu, index 0x%04hu, len %d\n",
   rw, val, index, len));
err = usbd_do_request(sc->ure_udev, &req, buf);
if (err) {
DPRINTF(("ure_ctl: error %d\n", err));
return -1;
}

return 0;
247}

249int
250ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
  void *buf, int len)
252{
return (ure_ctl(sc, URE_CTL_READ0x01, addr, index, buf, len));
5
←
Calling 'ure_ctl'→
8
←
Returning from 'ure_ctl'→
254}

256int
257ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index,
  void *buf, int len)
259{
return (ure_ctl(sc, URE_CTL_WRITE0x02, addr, index, buf, len));
261}

263uint8_t
264ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index)
265{
uint32_t	val;
uint8_t		temp[4];
uint8_t		shift;

shift = (reg & 3) << 3;
reg &= ~3;

ure_read_mem(sc, reg, index, &temp, 4);
val = UGETDW(temp)(*(u_int32_t *)(temp));
val >>= shift;

return (val & 0xff);
278}

280uint16_t
281ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index)
282{
uint32_t	val;
uint8_t		temp[4];
uint8_t		shift;

shift = (reg & 2) << 3;
reg &= ~3;

ure_read_mem(sc, reg, index, &temp, 4);
4
←
Calling 'ure_read_mem'→
9
←
Returning from 'ure_read_mem'→
val = UGETDW(temp)(*(u_int32_t *)(temp));
10
←
Assigned value is garbage or undefined
val >>= shift;

return (val & 0xffff);
295}

297uint32_t
298ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index)
299{
uint8_t	temp[4];

ure_read_mem(sc, reg, index, &temp, 4);
return (UGETDW(temp)(*(u_int32_t *)(temp)));
304}

306int
307ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
308{
uint16_t	byen;
uint8_t		temp[4];
uint8_t		shift;

byen = URE_BYTE_EN_BYTE0x11;
shift = reg & 3;
val &= 0xff;

if (reg & 3) {
byen <<= shift;
val <<= (shift << 3);
reg &= ~3;
}

USETDW(temp, val)(*(u_int32_t *)(temp) = (val));
return (ure_write_mem(sc, reg, index | byen, &temp, 4));
325}

327int
328ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
329{
uint16_t	byen;
uint8_t		temp[4];
uint8_t		shift;

byen = URE_BYTE_EN_WORD0x33;
shift = reg & 2;
val &= 0xffff;

if (reg & 2) {
byen <<= shift;
val <<= (shift << 3);
reg &= ~3;
}

USETDW(temp, val)(*(u_int32_t *)(temp) = (val));
return (ure_write_mem(sc, reg, index | byen, &temp, 4));
346}

348int
349ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val)
350{
uint8_t	temp[4];

USETDW(temp, val)(*(u_int32_t *)(temp) = (val));
return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD0xff, &temp, 4));
355}

357uint16_t
358ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr)
359{
uint16_t	reg;

ure_write_2(sc, URE_PLA_OCP_GPHY_BASE0xe86c, URE_MCU_TYPE_PLA0x0100, addr & 0xf000);
reg = (addr & 0x0fff) | 0xb000;

return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA0x0100));
366}

368void
369ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data)
370{
uint16_t	reg;

ure_write_2(sc, URE_PLA_OCP_GPHY_BASE0xe86c, URE_MCU_TYPE_PLA0x0100, addr & 0xf000);
reg = (addr & 0x0fff) | 0xb000;

ure_write_2(sc, reg, URE_MCU_TYPE_PLA0x0100, data);
377}

379int
380ure_miibus_readreg(struct device *dev, int phy, int reg)
381{
struct ure_softc	*sc = (void *)dev;
uint16_t		val;

if (usbd_is_dying(sc->ure_udev))
return 0;

/* Let the rgephy driver read the URE_PLA_PHYSTATUS register. */
if (reg == RL_GMEDIASTAT0x006C)
return ure_read_1(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100);

ure_lock_mii(sc);
val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII0xa400 + reg * 2);
ure_unlock_mii(sc);

return val;	/* letoh16? */
397}

399void
400ure_miibus_writereg(struct device *dev, int phy, int reg, int val)
401{
struct ure_softc	*sc = (void *)dev;

ure_lock_mii(sc);
ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + reg * 2, val);	/* htole16? */
ure_unlock_mii(sc);
407}

409void
410ure_miibus_statchg(struct device *dev)
411{
struct ure_softc	*sc = (void *)dev;
struct mii_data		*mii = &sc->ure_mii;
struct ifnet		*ifp = &sc->ure_ac.ac_if;

if ((ifp->if_flags & IFF_RUNNING0x40) == 0)
return;

sc->ure_flags &= ~URE_FLAG_LINK0x0001;
if ((mii->mii_media_status & (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) ==
   (IFM_ACTIVE0x0000000000000002ULL | IFM_AVALID0x0000000000000001ULL)) {
switch (IFM_SUBTYPE(mii->mii_media_active)((mii->mii_media_active) & 0x00000000000000ffULL)) {
case IFM_10_T3:
case IFM_100_TX6:
	sc->ure_flags |= URE_FLAG_LINK0x0001;
	break;
case IFM_1000_T16:
	if ((sc->ure_flags & URE_FLAG_81520x1000) != 0)
		break;
	sc->ure_flags |= URE_FLAG_LINK0x0001;
	break;
default:
	break;
}
}

/* Lost link, do nothing. */
if ((sc->ure_flags & URE_FLAG_LINK0x0001) == 0)
return;

/*
* After a link change the media settings are getting reset on the
* hardware, and need to be re-initialized again for communication
* to continue work.
*/
ure_ifmedia_init(ifp);
447}

449void
450ure_ifmedia_init(struct ifnet *ifp)
451{
struct ure_softc *sc = ifp->if_softc;
uint32_t reg = 0;

/* Set MAC address. */
ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_CONFIG0xc0);
ure_write_mem(sc, URE_PLA_IDR0xc000, URE_MCU_TYPE_PLA0x0100 | URE_BYTE_EN_SIX_BYTES0x3f,
   sc->ure_ac.ac_enaddr, 8);
ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00);

if (!(sc->ure_flags & URE_FLAG_81520x1000)) {
if (sc->ure_flags & URE_FLAG_8156B0x8000)
	URE_CLRBIT_2(sc, URE_USB_RX_AGGR_NUM, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4ee, 0x0000, ure_read_2(sc, 0xd4ee, 0x0000
) & ~(0x1ff))
	    URE_RX_AGGR_NUM_MASK)ure_write_2(sc, 0xd4ee, 0x0000, ure_read_2(sc, 0xd4ee, 0x0000
) & ~(0x1ff));

reg = sc->ure_rxbufsz - URE_FRAMELEN(ifp->if_mtu)(ifp->if_data.ifi_mtu + ((6 * 2) + 2) + 4 + 4) -
    sizeof(struct ure_rxpkt) - URE_RX_BUF_ALIGN8;
if (sc->ure_flags &
    (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
	ure_write_2(sc, URE_USB_RX_EARLY_SIZE0xd42e, URE_MCU_TYPE_USB0x0000,
	    reg / 8);

	ure_write_2(sc, URE_USB_RX_EARLY_AGG0xd42c, URE_MCU_TYPE_USB0x0000,
	    (sc->ure_flags & URE_FLAG_8153B0x2000) ? 158 : 80);
	ure_write_2(sc, URE_USB_PM_CTRL_STATUS0xd432,
	    URE_MCU_TYPE_USB0x0000, 1875);
} else {
	ure_write_2(sc, URE_USB_RX_EARLY_SIZE0xd42e, URE_MCU_TYPE_USB0x0000,
	    reg / 4);
	switch (sc->ure_udev->speed) {
	case USB_SPEED_SUPER4:
		reg = URE_COALESCE_SUPER85000U / 8;
		break;
	case USB_SPEED_HIGH3:
		reg = URE_COALESCE_HIGH250000U / 8;
		break;
	default:
		reg = URE_COALESCE_SLOW524280U / 8;
		break;
	}
	ure_write_2(sc, URE_USB_RX_EARLY_AGG0xd42c, URE_MCU_TYPE_USB0x0000,
	    reg);
}

if (sc->ure_chip & URE_CHIP_VER_74200x80) {
	URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4,ure_write_2(sc, 0xe0ce, 0x0100, ure_read_2(sc, 0xe0ce, 0x0100
) | (0x0040))
	    URE_MCU_TYPE_PLA, URE_IDLE_SPDWN_EN)ure_write_2(sc, 0xe0ce, 0x0100, ure_read_2(sc, 0xe0ce, 0x0100
) | (0x0040));
}

if ((sc->ure_chip & URE_CHIP_VER_60100x40) ||
    (sc->ure_flags & URE_FLAG_8156B0x8000)) {
	URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) & ~(0x0002))
	    URE_FC_PATCH_TASK)ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) & ~(0x0002));
	usbd_delay_ms(sc->ure_udev, 1);
	URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002))
	    URE_FC_PATCH_TASK)ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002));
}
}

/* Reset the packet filter. */
URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN)ure_write_2(sc, 0xc0b4, 0x0100, ure_read_2(sc, 0xc0b4, 0x0100
) & ~(0x0001));
URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN)ure_write_2(sc, 0xc0b4, 0x0100, ure_read_2(sc, 0xc0b4, 0x0100
) | (0x0001));

/* Enable transmit and receive. */
URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100
) | (0x08 | 0x04));

if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
ure_write_1(sc, URE_USB_UPT_RXDMA_OWN0xd437, URE_MCU_TYPE_USB0x0000,
    URE_OWN_UPDATE0x01 | URE_OWN_CLEAR0x02);
}

URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100
) & ~(0x0008));
523}

525int
526ure_ifmedia_upd(struct ifnet *ifp)
527{
struct ure_softc	*sc = ifp->if_softc;
struct mii_data		*mii = &sc->ure_mii;
struct ifmedia		*ifm = &sc->ure_ifmedia;
int			anar, gig, err, reg;

if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
if (IFM_TYPE(ifm->ifm_media)((ifm->ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
	return (EINVAL22);

if (!(sc->ure_chip & URE_CHIP_VER_74200x80)) {
	reg = ure_ocp_reg_read(sc, URE_OCP_10GBT_CTRL0xa5d4);
	reg &= ~URE_ADV_2500TFDX0x0080;
}

anar = gig = 0;
switch (IFM_SUBTYPE(ifm->ifm_media)((ifm->ifm_media) & 0x00000000000000ffULL)) {
case IFM_AUTO0ULL:
	anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020;
	gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100;
	if (!(sc->ure_chip & URE_CHIP_VER_74200x80))
		reg |= URE_ADV_2500TFDX0x0080;
	break;
case IFM_2500_T34:
	anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020;
	gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100;
	reg |= URE_ADV_2500TFDX0x0080;
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(2500)((((2500) * 1000ULL) * 1000ULL));
	break;
case IFM_1000_T16:
	anar |= ANAR_TX_FD0x0100 | ANAR_TX0x0080 | ANAR_10_FD0x0040 | ANAR_100x0020;
	gig |= GTCR_ADV_1000TFDX0x0200 | GTCR_ADV_1000THDX0x0100;
	ifp->if_baudrateif_data.ifi_baudrate = IF_Gbps(1)((((((1) * 1000ULL) * 1000ULL) * 1000ULL)));
	break;
case IFM_100_TX6:
	anar |= ANAR_TX0x0080 | ANAR_TX_FD0x0100;
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(100)((((100) * 1000ULL) * 1000ULL));
	break;
case IFM_10_T3:
	anar |= ANAR_100x0020 | ANAR_10_FD0x0040;
	ifp->if_baudrateif_data.ifi_baudrate = IF_Mbps(10)((((10) * 1000ULL) * 1000ULL));
	break;
default:
	printf("%s: unsupported media type\n",
	    sc->ure_dev.dv_xname);
	return (EINVAL22);
}

ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_ANAR0x04 * 2,
    anar | ANAR_PAUSE_ASYM(2 << 10) | ANAR_FC0x0400);
ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_100T2CR0x09 * 2, gig);
if (!(sc->ure_chip & URE_CHIP_VER_74200x80))
	ure_ocp_reg_write(sc, URE_OCP_10GBT_CTRL0xa5d4, reg);
ure_ocp_reg_write(sc, URE_OCP_BASE_MII0xa400 + MII_BMCR0x00,
    BMCR_AUTOEN0x1000 | BMCR_STARTNEG0x0200);

return (0);
}

if (mii->mii_instance) {
struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)for((miisc) = ((&mii->mii_phys)->lh_first); (miisc)
!= ((void *)0); (miisc) = ((miisc)->mii_list.le_next))
	PHY_RESET(miisc)(*(miisc)->mii_funcs->pf_reset)((miisc));
}

err = mii_mediachg(mii);
if (err == ENXIO6)
return (0);
else
return (err);
597}

599void
600ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
601{
struct ure_softc	*sc = ifp->if_softc;
struct mii_data		*mii = &sc->ure_mii;
uint16_t		status = 0;

if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
if (ure_get_link_status(sc)) {
	ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;
	status = ure_read_2(sc, URE_PLA_PHYSTATUS0xe908,
	    URE_MCU_TYPE_PLA0x0100);
	if ((status & URE_PHYSTATUS_FDX0x0001) ||
	    (status & URE_PHYSTATUS_2500MBPS0x0400))
		ifmr->ifm_active |= IFM_FDX0x0000010000000000ULL;
	else
		ifmr->ifm_active |= IFM_HDX0x0000020000000000ULL;
	if (status & URE_PHYSTATUS_10MBPS0x0004)
		ifmr->ifm_active |= IFM_10_T3;
	else if (status & URE_PHYSTATUS_100MBPS0x0008)
		ifmr->ifm_active |= IFM_100_TX6;
	else if (status & URE_PHYSTATUS_1000MBPS0x0010)
		ifmr->ifm_active |= IFM_1000_T16;
	else if (status & URE_PHYSTATUS_2500MBPS0x0400)
		ifmr->ifm_active |= IFM_2500_T34;
}
return;
}

mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
632}

634void
635ure_add_media_types(struct ure_softc *sc)
636{
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_10_T3, 0, NULL((void *)0));
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_10_T3 | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, 0, NULL((void *)0));
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_100_TX6 | IFM_FDX0x0000010000000000ULL, 0,
   NULL((void *)0));
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16, 0, NULL((void *)0));
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_1000_T16 | IFM_FDX0x0000010000000000ULL, 0,
   NULL((void *)0));
if (!(sc->ure_chip & URE_CHIP_VER_74200x80)) {
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34, 0, NULL((void *)0));
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34 | IFM_FDX0x0000010000000000ULL,
    0, NULL((void *)0));
}
650}

652void
653ure_link_state(struct ure_softc *sc)
654{
struct ifnet	*ifp = &sc->ure_ac.ac_if;
int		link = LINK_STATE_DOWN2;

if (ure_get_link_status(sc))
link = LINK_STATE_UP4;

if (ifp->if_link_stateif_data.ifi_link_state != link) {
ifp->if_link_stateif_data.ifi_link_state = link;
if_link_state_change(ifp);
}
665}

667int
668ure_get_link_status(struct ure_softc *sc)
669{
if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) &
   URE_PHYSTATUS_LINK0x0002) {
sc->ure_flags |= URE_FLAG_LINK0x0001;
return (1);
} else {
sc->ure_flags &= ~URE_FLAG_LINK0x0001;
return (0);
}
678}

680void
681ure_iff(struct ure_softc *sc)
682{
struct ifnet		*ifp = &sc->ure_ac.ac_if;
struct ether_multi	*enm;
struct ether_multistep	step;
uint32_t		hashes[2] = { 0, 0 };
uint32_t		hash;
uint32_t		rxmode;

if (usbd_is_dying(sc->ure_udev))
return;

rxmode = ure_read_4(sc, URE_PLA_RCR0xc010, URE_MCU_TYPE_PLA0x0100);
rxmode &= ~URE_RCR_ACPT_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008);
ifp->if_flags &= ~IFF_ALLMULTI0x200;

/*
* Always accept frames destined to our station address.
* Always accept broadcast frames.
*/
rxmode |= URE_RCR_APM0x00000002 | URE_RCR_AB0x00000008;

if (ifp->if_flags & IFF_PROMISC0x100 || sc->ure_ac.ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI0x200;
rxmode |= URE_RCR_AM0x00000004;
if (ifp->if_flags & IFF_PROMISC0x100)
	rxmode |= URE_RCR_AAP0x00000001;
hashes[0] = hashes[1] = 0xffffffff;
} else {
rxmode |= URE_RCR_AM0x00000004;

ETHER_FIRST_MULTI(step, &sc->ure_ac, enm)do { (step).e_enm = ((&(&sc->ure_ac)->ac_multiaddrs
)->lh_first); do { if ((((enm)) = ((step)).e_enm) != ((void
 *)0)) ((step)).e_enm = ((((enm)))->enm_list.le_next); } while
 ( 0); } while ( 0);
while (enm != NULL((void *)0)) {
	hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN6)
	    >> 26;
	if (hash < 32)
		hashes[0] |= (1 << hash);
	else
		hashes[1] |= (1 << (hash - 32));

	ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
 (((enm))->enm_list.le_next); } while ( 0);
}

hash = swap32(hashes[0])(__uint32_t)(__builtin_constant_p(hashes[0]) ? (__uint32_t)((
(__uint32_t)(hashes[0]) & 0xff) << 24 | ((__uint32_t
)(hashes[0]) & 0xff00) << 8 | ((__uint32_t)(hashes[
0]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[0]) &
 0xff000000) >> 24) : __swap32md(hashes[0]));
hashes[0] = swap32(hashes[1])(__uint32_t)(__builtin_constant_p(hashes[1]) ? (__uint32_t)((
(__uint32_t)(hashes[1]) & 0xff) << 24 | ((__uint32_t
)(hashes[1]) & 0xff00) << 8 | ((__uint32_t)(hashes[
1]) & 0xff0000) >> 8 | ((__uint32_t)(hashes[1]) &
 0xff000000) >> 24) : __swap32md(hashes[1]));
hashes[1] = hash;
}

ure_write_mem(sc, URE_PLA_MAR0xcd00, URE_MCU_TYPE_PLA0x0100 | URE_BYTE_EN_DWORD0xff,
   hashes, sizeof(hashes));
ure_write_4(sc, URE_PLA_RCR0xc010, URE_MCU_TYPE_PLA0x0100, rxmode);
732}

734void
735ure_rxvlan(struct ure_softc *sc)
736{
struct ifnet	*ifp = &sc->ure_ac.ac_if;
uint16_t	reg;

if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
reg = ure_read_2(sc, URE_PLA_RCR10xc012, URE_MCU_TYPE_PLA0x0100);
reg &= ~(URE_INNER_VLAN0x0040 | URE_OUTER_VLAN0x0080);
if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)
	reg |= (URE_INNER_VLAN0x0040 | URE_OUTER_VLAN0x0080);
ure_write_2(sc, URE_PLA_RCR10xc012, URE_MCU_TYPE_PLA0x0100, reg);
} else {
reg = ure_read_2(sc, URE_PLA_CPCR0xe854, URE_MCU_TYPE_PLA0x0100);
reg &= ~URE_CPCR_RX_VLAN0x0040;
if (ifp->if_capabilitiesif_data.ifi_capabilities & IFCAP_VLAN_HWTAGGING0x00000020)
	reg |= URE_CPCR_RX_VLAN0x0040;
ure_write_2(sc, URE_PLA_CPCR0xe854, URE_MCU_TYPE_PLA0x0100, reg);
}
753}

755void
756ure_reset(struct ure_softc *sc)
757{
int	i;

if (sc->ure_flags & URE_FLAG_81560x4000) {
URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_TE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100
) & ~(0x04));
URE_CLRBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) & ~(0x01))
    BMU_RESET_EP_IN)ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) & ~(0x01));
URE_SETBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) | (0x0008))
    URE_CDC_ECM_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) | (0x0008));
URE_CLRBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE)ure_write_1(sc, 0xe813, 0x0100, ure_read_1(sc, 0xe813, 0x0100
) & ~(0x08));
URE_SETBIT_2(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) | (0x01))
    BMU_RESET_EP_IN)ure_write_2(sc, 0xd4b0, 0x0000, ure_read_2(sc, 0xd4b0, 0x0000
) | (0x01));
URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0008))
    URE_CDC_ECM_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0008));
} else {
ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, URE_CR_RST0x10);

for (i = 0; i < URE_TIMEOUT1000; i++) {
	if (!(ure_read_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100) &
	    URE_CR_RST0x10))
		break;
	DELAY(100)(*delay_func)(100);
}
if (i == URE_TIMEOUT1000)
	printf("%s: reset never completed\n",
	    sc->ure_dev.dv_xname);
}
784}

786void
787ure_watchdog(struct ifnet *ifp)
788{
struct ure_softc	*sc = ifp->if_softc;
struct ure_chain	*c;
usbd_status		err;
int			i, s;

ifp->if_timer = 0;

if (usbd_is_dying(sc->ure_udev))
return;

if ((ifp->if_flags & (IFF_RUNNING0x40|IFF_UP0x1)) != (IFF_RUNNING0x40|IFF_UP0x1))
return;

sc = ifp->if_softc;
s = splnet()splraise(0x4);

ifp->if_oerrorsif_data.ifi_oerrors++;
DPRINTF(("%s: watchdog timeout\n", sc->ure_dev.dv_xname));

for (i = 0; i < URE_TX_LIST_CNT1; i++) {
c = &sc->ure_cdata.ure_tx_chain[i];
if (c->uc_cnt > 0) {
	usbd_get_xfer_status(c->uc_xfer, NULL((void *)0), NULL((void *)0), NULL((void *)0),
	    &err);
	ure_txeof(c->uc_xfer, c, err);
}
}

if (ifq_is_oactive(&ifp->if_snd))
ifq_restart(&ifp->if_snd);
splx(s)spllower(s);
820}

822void
823ure_init(void *xsc)
824{
struct ure_softc	*sc = xsc;
struct ure_chain	*c;
struct ifnet		*ifp = &sc->ure_ac.ac_if;
usbd_status		err;
int			s, i;

s = splnet()splraise(0x4);

/* Cancel pending I/O. */
ure_stop(sc);

if (sc->ure_flags & URE_FLAG_81520x1000)
ure_rtl8152_nic_reset(sc);
else
ure_rtl8153_nic_reset(sc);

if (ure_xfer_list_init(sc, sc->ure_cdata.ure_rx_chain,
sc->ure_rxbufsz, URE_RX_LIST_CNT1) == ENOBUFS55) {
printf("%s: rx list init failed\n", sc->ure_dev.dv_xname);
splx(s)spllower(s);
return;
}

if (ure_xfer_list_init(sc, sc->ure_cdata.ure_tx_chain,
sc->ure_txbufsz, URE_TX_LIST_CNT1) == ENOBUFS55) {
printf("%s: tx list init failed\n", sc->ure_dev.dv_xname);
splx(s)spllower(s);
return;
}

/* Initialize the SLIST we are using for the multiple tx buffers */
SLIST_INIT(&sc->ure_cdata.ure_tx_free){ ((&sc->ure_cdata.ure_tx_free)->slh_first) = ((void
 *)0); };
for (i = 0; i < URE_TX_LIST_CNT1; i++)
SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free,do { (&sc->ure_cdata.ure_tx_chain[i])->uc_list.sle_next
 = (&sc->ure_cdata.ure_tx_free)->slh_first; (&sc
->ure_cdata.ure_tx_free)->slh_first = (&sc->ure_cdata
.ure_tx_chain[i]); } while (0)
    &sc->ure_cdata.ure_tx_chain[i], uc_list)do { (&sc->ure_cdata.ure_tx_chain[i])->uc_list.sle_next
 = (&sc->ure_cdata.ure_tx_free)->slh_first; (&sc
->ure_cdata.ure_tx_free)->slh_first = (&sc->ure_cdata
.ure_tx_chain[i]); } while (0);

/* Setup MAC address, and enable TX/RX. */
ure_ifmedia_init(ifp);

/* Load the multicast filter. */
ure_iff(sc);

/* Open RX and TX pipes. */
err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_RX0],
   USBD_EXCLUSIVE_USE0x01, &sc->ure_ep[URE_ENDPT_RX0]);
if (err) {
printf("%s: open rx pipe failed: %s\n",
    sc->ure_dev.dv_xname, usbd_errstr(err));
splx(s)spllower(s);
return;
}

err = usbd_open_pipe(sc->ure_iface, sc->ure_ed[URE_ENDPT_TX1],
   USBD_EXCLUSIVE_USE0x01, &sc->ure_ep[URE_ENDPT_TX1]);
if (err) {
printf("%s: open tx pipe failed: %s\n",
    sc->ure_dev.dv_xname, usbd_errstr(err));
splx(s)spllower(s);
return;
}

/* Start up the receive pipe. */
for (i = 0; i < URE_RX_LIST_CNT1; i++) {
c = &sc->ure_cdata.ure_rx_chain[i];
usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_RX0],
    c, c->uc_buf, c->uc_bufmax,
    USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01,
    USBD_NO_TIMEOUT0, ure_rxeof);
usbd_transfer(c->uc_xfer);
}

ure_ifmedia_upd(ifp);

/* Indicate we are up and running. */
sc->ure_flags &= ~URE_FLAG_LINK0x0001;
ifp->if_flags |= IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

timeout_add_sec(&sc->ure_stat_ch, 1);

splx(s)spllower(s);
906}

908void
909ure_start(struct ifnet *ifp)
910{
struct ure_softc	*sc = ifp->if_softc;
struct ure_cdata	*cd = &sc->ure_cdata;
struct ure_chain	*c;
struct mbuf		*m = NULL((void *)0);
uint32_t		new_buflen;
int			s, mlen;

if (!(sc->ure_flags & URE_FLAG_LINK0x0001) ||
(ifp->if_flags & (IFF_RUNNING0x40|IFF_UP0x1)) !=
    (IFF_RUNNING0x40|IFF_UP0x1)) {
return;
}

s = splnet()splraise(0x4);

c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first);
while (c != NULL((void *)0)) {
m = ifq_deq_begin(&ifp->if_snd);
if (m == NULL((void *)0))
	break;

mlen = m->m_pkthdrM_dat.MH.MH_pkthdr.len;

/* Discard packet larger than buffer. */
if (mlen + sizeof(struct ure_txpkt) >= c->uc_bufmax) {
	ifq_deq_commit(&ifp->if_snd, m);
	m_freem(m);
	ifp->if_oerrorsif_data.ifi_oerrors++;
	continue;
}

/*
 * If packet larger than remaining space, send buffer and
 * continue.
 */
new_buflen = roundup(c->uc_buflen, URE_TX_BUF_ALIGN)((((c->uc_buflen)+((4)-1))/(4))*(4));
if (new_buflen + sizeof(struct ure_txpkt) + mlen >=
    c->uc_bufmax) {
	ifq_deq_rollback(&ifp->if_snd, m);
	SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list)do { (&cd->ure_tx_free)->slh_first = (&cd->ure_tx_free
)->slh_first->uc_list.sle_next; } while (0);
	if (ure_encap_xfer(ifp, sc, c)) {
		SLIST_INSERT_HEAD(&cd->ure_tx_free, c,do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
 (0)
		    uc_list)do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
 (0);
		break;
	}
	c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first);
	continue;
}

/* Append packet to current buffer. */
mlen = ure_encap_txpkt(m, c->uc_buf + new_buflen,
    c->uc_bufmax - new_buflen);
if (mlen <= 0) {
	ifq_deq_rollback(&ifp->if_snd, m);
	break;
}

ifq_deq_commit(&ifp->if_snd, m);
c->uc_cnt += 1;
c->uc_buflen = new_buflen + mlen;

972#if NBPFILTER1 > 0
if (ifp->if_bpf)
	bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
975#endif

m_freem(m);
}

if (c != NULL((void *)0)) {
/* Send current buffer unless empty */
if (c->uc_buflen > 0 && c->uc_cnt > 0) {
	SLIST_REMOVE_HEAD(&cd->ure_tx_free, uc_list)do { (&cd->ure_tx_free)->slh_first = (&cd->ure_tx_free
)->slh_first->uc_list.sle_next; } while (0);
	if (ure_encap_xfer(ifp, sc, c)) {
		SLIST_INSERT_HEAD(&cd->ure_tx_free, c,do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
 (0)
		    uc_list)do { (c)->uc_list.sle_next = (&cd->ure_tx_free)->
slh_first; (&cd->ure_tx_free)->slh_first = (c); } while
 (0);
	}
	c = SLIST_FIRST(&cd->ure_tx_free)((&cd->ure_tx_free)->slh_first);
}
}

ifp->if_timer = 5;
if (c == NULL((void *)0))
ifq_set_oactive(&ifp->if_snd);
splx(s)spllower(s);
996}

998void
999ure_tick(void *xsc)
1000{
struct ure_softc	*sc = xsc;

if (sc == NULL((void *)0))
return;

if (usbd_is_dying(sc->ure_udev))
return;

usb_add_task(sc->ure_udev, &sc->ure_tick_task);
1010}

1012void
1013ure_stop(struct ure_softc *sc)
1014{
struct ure_cdata	*cd;
struct ifnet		*ifp;
usbd_status		err;

ure_reset(sc);

ifp = &sc->ure_ac.ac_if;
ifp->if_timer = 0;
ifp->if_flags &= ~IFF_RUNNING0x40;
ifq_clr_oactive(&ifp->if_snd);

timeout_del(&sc->ure_stat_ch);
sc->ure_flags &= ~URE_FLAG_LINK0x0001;

if (sc->ure_ep[URE_ENDPT_RX0] != NULL((void *)0)) {
err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_RX0]);
if (err) {
	printf("%s: close rx pipe failed: %s\n",
	    sc->ure_dev.dv_xname, usbd_errstr(err));
}
sc->ure_ep[URE_ENDPT_RX0] = NULL((void *)0);
}

if (sc->ure_ep[URE_ENDPT_TX1] != NULL((void *)0)) {
err = usbd_close_pipe(sc->ure_ep[URE_ENDPT_TX1]);
if (err) {
	printf("%s: close tx pipe failed: %s\n",
	    sc->ure_dev.dv_xname, usbd_errstr(err));
}
sc->ure_ep[URE_ENDPT_TX1] = NULL((void *)0);
}

cd = &sc->ure_cdata;
ure_xfer_list_free(sc, cd->ure_rx_chain, URE_RX_LIST_CNT1);
ure_xfer_list_free(sc, cd->ure_tx_chain, URE_TX_LIST_CNT1);
1050}

1052int
1053ure_xfer_list_init(struct ure_softc *sc, struct ure_chain *ch,
  uint32_t bufsize, int listlen)
1055{
struct ure_chain	*c;
int			i;

for (i = 0; i < listlen; i++) {
c = &ch[i];
c->uc_sc = sc;
c->uc_idx = i;
c->uc_buflen = 0;
c->uc_bufmax = bufsize;
c->uc_cnt = 0;
if (c->uc_xfer == NULL((void *)0)) {
	c->uc_xfer = usbd_alloc_xfer(sc->ure_udev);
	if (c->uc_xfer == NULL((void *)0))
		return (ENOBUFS55);
	c->uc_buf = usbd_alloc_buffer(c->uc_xfer, c->uc_bufmax);
	if (c->uc_buf == NULL((void *)0)) {
		usbd_free_xfer(c->uc_xfer);
		c->uc_xfer = NULL((void *)0);
		return (ENOBUFS55);
	}
}
}

return (0);
1080}

1082void
1083ure_xfer_list_free(struct ure_softc *sc, struct ure_chain *ch, int listlen)
1084{
int	i;

for (i = 0; i < listlen; i++) {
if (ch[i].uc_buf != NULL((void *)0)) {
	ch[i].uc_buf = NULL((void *)0);
}
ch[i].uc_cnt = 0;
if (ch[i].uc_xfer != NULL((void *)0)) {
	usbd_free_xfer(ch[i].uc_xfer);
	ch[i].uc_xfer = NULL((void *)0);
}
}
1097}

1099void
1100ure_rtl8152_init(struct ure_softc *sc)
1101{
uint32_t	pwrctrl;

/* Disable ALDPS. */
ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, URE_ENPDNPS0x0200 | URE_LINKENA0x0100 |
   URE_DIS_SDSAVE0x0010);
usbd_delay_ms(sc->ure_udev, 20);

if (sc->ure_chip & URE_CHIP_VER_4C000x01)
URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700))
    URE_LED_MODE_MASK)ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700));

URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT)ure_write_2(sc, 0xd800, 0x0000, ure_read_2(sc, 0xd800, 0x0000
) & ~(0x0100));
URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd432, 0x0000, ure_read_2(sc, 0xd432, 0x0000
) & ~(0x0001))
   URE_RESUME_INDICATE)ure_write_2(sc, 0xd432, 0x0000, ure_read_2(sc, 0xd432, 0x0000
) & ~(0x0001));

URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe84c, 0x0100, ure_read_2(sc, 0xe84c, 0x0100
) | (0x0080 | 0x0040))
   URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH)ure_write_2(sc, 0xe84c, 0x0100, ure_read_2(sc, 0xe84c, 0x0100
) | (0x0080 | 0x0040));
pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100);
pwrctrl &= ~URE_MCU_CLK_RATIO_MASK0x0f0f0f0f;
pwrctrl |= URE_MCU_CLK_RATIO0x07010f07 | URE_D3_CLK_GATED_EN0x00004000;
ure_write_4(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, pwrctrl);
ure_write_2(sc, URE_PLA_GPHY_INTR_IMR0xe022, URE_MCU_TYPE_PLA0x0100,
   URE_GPHY_STS_MSK0x0001 | URE_SPEED_DOWN_MSK0x0002 | URE_SPDWN_RXDV_MSK0x0004 |
   URE_SPDWN_LINKCHG_MSK0x0008);

URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100
) | (0x0001));

/* Enable Rx aggregation. */
URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
   URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080));
1132}

1134void
1135ure_rtl8153_init(struct ure_softc *sc)
1136{
uint16_t	reg;
uint8_t		u1u2[8];
int		i;

memset(u1u2, 0x00, sizeof(u1u2))__builtin_memset((u1u2), (0x00), (sizeof(u1u2)));
ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, u1u2,
   sizeof(u1u2));

      for (i = 0; i < 500; i++) {
if (ure_read_2(sc, URE_PLA_BOOT_CTRL0xe004, URE_MCU_TYPE_PLA0x0100) &
    URE_AUTOLOAD_DONE0x0002)
	break;
usbd_delay_ms(sc->ure_udev, 20);
}
if (i == 500)
printf("%s: timeout waiting for chip autoload\n",
    sc->ure_dev.dv_xname);

ure_rtl8153_phy_status(sc, 0);

if (sc->ure_chip & (URE_CHIP_VER_5C000x04 | URE_CHIP_VER_5C100x08 |
   URE_CHIP_VER_5C200x10)) {
ure_ocp_reg_write(sc, URE_OCP_ADC_CFG0xbc06,
    URE_CKADSEL_L0x0100 | URE_ADC_EN0x0080 | URE_EN_EMI_L0x0040);
}

ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON3);

URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) & ~(0x0001));

if (sc->ure_chip & URE_CHIP_VER_5C100x08) {
reg = ure_read_2(sc, URE_USB_SSPHYLINK20xb428, URE_MCU_TYPE_USB0x0000);
reg &= ~URE_PWD_DN_SCALE_MASK0x3ffe;
reg |= URE_PWD_DN_SCALE(96)((96) << 1);
ure_write_2(sc, URE_USB_SSPHYLINK20xb428, URE_MCU_TYPE_USB0x0000, reg);

URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb41e, 0x0000, ure_read_1(sc, 0xb41e, 0x0000
) | (0x0002 | 0x0001))
    URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND)ure_write_1(sc, 0xb41e, 0x0000, ure_read_1(sc, 0xb41e, 0x0000
) | (0x0002 | 0x0001));
} else if (sc->ure_chip & URE_CHIP_VER_5C200x10) {
URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xc0b0, 0x0100, ure_read_1(sc, 0xc0b0, 0x0100
) & ~(0x0002))
    URE_ECM_ALDPS)ure_write_1(sc, 0xc0b0, 0x0100, ure_read_1(sc, 0xc0b0, 0x0100
) & ~(0x0002));
}
if (sc->ure_chip & (URE_CHIP_VER_5C200x10 | URE_CHIP_VER_5C300x20)) {
if (ure_read_2(sc, URE_USB_BURST_SIZE0xcfc0, URE_MCU_TYPE_USB0x0000))
	URE_SETBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) | (0x0001))
	    URE_DYNAMIC_BURST)ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) | (0x0001));
else
	URE_CLRBIT_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB,ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) & ~(0x0001))
	    URE_DYNAMIC_BURST)ure_write_1(sc, 0xb464, 0x0000, ure_read_1(sc, 0xb464, 0x0000
) & ~(0x0001));
}

URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC)ure_write_1(sc, 0xb466, 0x0000, ure_read_1(sc, 0xb466, 0x0000
) | (0x0001));

URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN)ure_write_2(sc, 0xe43c, 0x0000, ure_read_2(sc, 0xe43c, 0x0000
) & ~(0x0001));

URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700))
   URE_LED_MODE_MASK)ure_write_2(sc, 0xdd92, 0x0100, ure_read_2(sc, 0xdd92, 0x0100
) & ~(0x0700));

if ((sc->ure_chip & URE_CHIP_VER_5C100x08) &&
   sc->ure_udev->speed != USB_SPEED_SUPER4)
reg = URE_LPM_TIMER_500MS0x04;
else
reg = URE_LPM_TIMER_500US0x0c;
ure_write_1(sc, URE_USB_LPM_CTRL0xd41a, URE_MCU_TYPE_USB0x0000,
   URE_FIFO_EMPTY_1FB0x30 | URE_ROK_EXIT_LPM0x02 | reg);

reg = ure_read_2(sc, URE_USB_AFE_CTRL20xd824, URE_MCU_TYPE_USB0x0000);
reg &= ~URE_SEN_VAL_MASK0xf800;
reg |= URE_SEN_VAL_NORMAL0xa000 | URE_SEL_RXIDLE0x0100;
ure_write_2(sc, URE_USB_AFE_CTRL20xd824, URE_MCU_TYPE_USB0x0000, reg);

ure_write_2(sc, URE_USB_CONNECT_TIMER0xcbf8, URE_MCU_TYPE_USB0x0000, 0x0001);

URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000
) & ~(0x0001 | 0x0008))
   URE_PWR_EN | URE_PHASE2_EN)ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000
) & ~(0x0001 | 0x0008));
URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000
) & ~(0x0001));

memset(u1u2, 0xff, sizeof(u1u2))__builtin_memset((u1u2), (0xff), (sizeof(u1u2)));
ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f, u1u2,
   sizeof(u1u2));

ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0);
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, 0);
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL30xe0cc, URE_MCU_TYPE_PLA0x0100, 0);
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL40xe0ce, URE_MCU_TYPE_PLA0x0100, 0);

/* Enable Rx aggregation. */
URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
   URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080));

URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100
) | (0x0001));
1228}

1230void
1231ure_rtl8153b_init(struct ure_softc *sc)
1232{
uint16_t	reg;
int		i;

if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
URE_CLRBIT_1(sc, URE_USB_ECM_OP, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd26b, 0x0000, ure_read_1(sc, 0xd26b, 0x0000
) & ~(0x0001))
    URE_EN_ALL_SPEED)ure_write_1(sc, 0xd26b, 0x0000, ure_read_1(sc, 0xd26b, 0x0000
) & ~(0x0001));
ure_write_2(sc, URE_USB_SPEED_OPTION0xd32a, URE_MCU_TYPE_USB0x0000, 0);
URE_SETBIT_2(sc, URE_USB_ECM_OPTION, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfee, 0x0000, ure_read_2(sc, 0xcfee, 0x0000
) | (0x0020))
    URE_BYPASS_MAC_RESET)ure_write_2(sc, 0xcfee, 0x0000, ure_read_2(sc, 0xcfee, 0x0000
) | (0x0020));

if (sc->ure_flags & URE_FLAG_8156B0x8000)
	URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0008))
	    URE_RX_DETECT8)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0008));
}

URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) & ~(0x0001));

if (sc->ure_flags & URE_FLAG_8156B0x8000)
ure_wait_for_flash(sc);

      for (i = 0; i < 500; i++) {
if (ure_read_2(sc, URE_PLA_BOOT_CTRL0xe004, URE_MCU_TYPE_PLA0x0100) &
    URE_AUTOLOAD_DONE0x0002)
	break;
usbd_delay_ms(sc->ure_udev, 20);
}
if (i == 500)
printf("%s: timeout waiting for chip autoload\n",
    sc->ure_dev.dv_xname);

ure_rtl8153_phy_status(sc, 0);
ure_rtl8153_phy_status(sc, URE_PHY_STAT_LAN_ON3);

URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) & ~(0x0001));

/* MSC timer, 32760 ms. */
ure_write_2(sc, URE_USB_MSC_TIMER0xcbfc, URE_MCU_TYPE_USB0x0000, 4095);

if (!(sc->ure_flags & URE_FLAG_8153B0x2000)) {
/* U1/U2/L1 idle timer, 500 us. */
ure_write_2(sc, URE_USB_U1U2_TIMER0xd4da, URE_MCU_TYPE_USB0x0000, 500);
}

URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN)ure_write_2(sc, 0xd80a, 0x0000, ure_read_2(sc, 0xd80a, 0x0000
) & ~(0x0001));
URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS)ure_write_2(sc, 0xd81a, 0x0000, ure_read_2(sc, 0xd81a, 0x0000
) & ~(0x0001));

URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd80a, 0x0000, ure_read_1(sc, 0xd80a, 0x0000
) & ~(0x0010 | 0x0020))
   URE_UPS_EN | URE_USP_PREWAKE)ure_write_1(sc, 0xd80a, 0x0000, ure_read_1(sc, 0xd80a, 0x0000
) & ~(0x0010 | 0x0020));
URE_CLRBIT_1(sc, URE_USB_MISC_2, URE_MCU_TYPE_USB,ure_write_1(sc, 0xcfff, 0x0000, ure_read_1(sc, 0xcfff, 0x0000
) & ~(0x01 | 0x80))
   URE_UPS_FORCE_PWR_DOWN | URE_UPS_NO_UPS)ure_write_1(sc, 0xcfff, 0x0000, ure_read_1(sc, 0xcfff, 0x0000
) & ~(0x01 | 0x80));

URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xd38c, 0x0100, ure_read_1(sc, 0xd38c, 0x0100
) & ~(0x01))
   URE_UPCOMING_RUNTIME_D3)ure_write_1(sc, 0xd38c, 0x0100, ure_read_1(sc, 0xd38c, 0x0100
) & ~(0x01));
URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xd38a, 0x0100, ure_read_1(sc, 0xd38a, 0x0100
) & ~(0x01))
   URE_LINK_CHG_EVENT)ure_write_1(sc, 0xd38a, 0x0100, ure_read_1(sc, 0xd38a, 0x0100
) & ~(0x01));
URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xd398, 0x0100, ure_read_2(sc, 0xd398, 0x0100
) & ~(0x0100))
   URE_LINK_CHANGE_FLAG)ure_write_2(sc, 0xd398, 0x0100, ure_read_2(sc, 0xd398, 0x0100
) & ~(0x0100));

ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_CONFIG0xc0);
URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe820, 0x0100, ure_read_2(sc, 0xe820, 0x0100
) & ~(0x0008))
   URE_LINK_OFF_WAKE_EN)ure_write_2(sc, 0xe820, 0x0100, ure_read_2(sc, 0xe820, 0x0100
) & ~(0x0008));
ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00);

if (sc->ure_flags & URE_FLAG_8153B0x2000) {
reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100);
if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) &
    URE_PHYSTATUS_LINK0x0002)
	reg |= URE_CUR_LINK_OK0x8000;
else
	reg &= ~URE_CUR_LINK_OK0x8000;
ure_write_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100,
    reg | URE_POLL_LINK_CHG0x0001);
}

if (sc->ure_udev->speed == USB_SPEED_SUPER4) {
URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001))
    LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001));
}

if (sc->ure_flags & URE_FLAG_8156B0x8000) {
URE_CLRBIT_2(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_SLOT_EN)ure_write_2(sc, 0xc010, 0x0100, ure_read_2(sc, 0xc010, 0x0100
) & ~(0x00000800));
URE_SETBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe854, 0x0100, ure_read_2(sc, 0xe854, 0x0100
) | (0x0001))
    URE_FLOW_CTRL_EN)ure_write_2(sc, 0xe854, 0x0100, ure_read_2(sc, 0xe854, 0x0100
) | (0x0001));

/* Enable fc timer and set timer to 600 ms. */
ure_write_2(sc, URE_USB_FC_TIMER0xd340, URE_MCU_TYPE_USB0x0000,
    URE_CTRL_TIMER_EN0x8000 | 75);

reg = ure_read_2(sc, URE_USB_FW_CTRL0xd334, URE_MCU_TYPE_USB0x0000);
if (!(ure_read_2(sc, URE_PLA_POL_GPIO_CTRL0xdc6a, URE_MCU_TYPE_PLA0x0100) &
    URE_DACK_DET_EN0x8000))
	reg |= URE_FLOW_CTRL_PATCH_20x0100;
reg &= ~URE_AUTO_SPEEDUP0x0008;
ure_write_2(sc, URE_USB_FW_CTRL0xd334, URE_MCU_TYPE_USB0x0000, reg);

URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002))
    URE_FC_PATCH_TASK)ure_write_2(sc, 0xd4e8, 0x0000, ure_read_2(sc, 0xd4e8, 0x0000
) | (0x0002));
}

/* MAC clock speed down. */
if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL0xe0c0, URE_MCU_TYPE_PLA0x0100, 0x0403);
reg = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100);
reg &= ~URE_EEE_SPDWN_RATIO_MASK0x00ff;
reg |= URE_MAC_CLK_SPDWN_EN0x8000 | 0x0003;
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL20xe0ca, URE_MCU_TYPE_PLA0x0100, reg);

URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
    URE_PLA_MCU_SPDWN_EN)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000));

reg = ure_read_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100);
if (ure_read_2(sc, URE_PLA_PHYSTATUS0xe908, URE_MCU_TYPE_PLA0x0100) &
    URE_PHYSTATUS_LINK0x0002)
	reg |= URE_CUR_LINK_OK0x8000;
else
	reg &= ~URE_CUR_LINK_OK0x8000;
ure_write_2(sc, URE_PLA_EXTRA_STATUS0xd398, URE_MCU_TYPE_PLA0x0100,
    reg | URE_POLL_LINK_CHG0x0001);
} else
URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0ca, 0x0100, ure_read_2(sc, 0xe0ca, 0x0100
) | (0x8000))
    URE_MAC_CLK_SPDWN_EN)ure_write_2(sc, 0xe0ca, 0x0100, ure_read_2(sc, 0xe0ca, 0x0100
) | (0x8000));

/* Enable Rx aggregation. */
URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080))
   URE_RX_AGG_DISABLE | URE_RX_ZERO_EN)ure_write_2(sc, 0xd406, 0x0000, ure_read_2(sc, 0xd406, 0x0000
) & ~(0x0010 | 0x0080));

if (sc->ure_flags & URE_FLAG_81560x4000)
URE_SETBIT_1(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,ure_write_1(sc, 0xd4b4, 0x0000, ure_read_1(sc, 0xd4b4, 0x0000
) | (0x02))
    URE_ACT_ODMA)ure_write_1(sc, 0xd4b4, 0x0000, ure_read_1(sc, 0xd4b4, 0x0000
) | (0x02));

if (!(sc->ure_flags & URE_FLAG_8153B0x2000)) {
/*
 * Select force mode through 0xa5b4 bit 15
 * 0: MDIO force mode
 * 1: MMD force mode
 */
reg = ure_ocp_reg_read(sc, 0xa5b4);
if (reg & 0x8000)
	ure_ocp_reg_write(sc, 0xa5b4, reg & ~0x8000);
}

URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_PLA, URE_TALLY_RESET)ure_write_2(sc, 0xe800, 0x0100, ure_read_2(sc, 0xe800, 0x0100
) | (0x0001));
1375}

1377void
1378ure_rtl8152_nic_reset(struct ure_softc *sc)
1379{
uint32_t	rx_fifo1, rx_fifo2;
int		i;

/* Disable ALDPS. */
ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010, URE_ENPDNPS0x0200 | URE_LINKENA0x0100 |
   URE_DIS_SDSAVE0x0010);
usbd_delay_ms(sc->ure_udev, 20);

URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL)ure_write_4(sc, 0xc010, 0x0100, ure_read_4(sc, 0xc010, 0x0100
) & ~((0x00000001 | 0x00000002 | 0x00000004 | 0x00000008)
));

URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100
) | (0x0008));
ure_disable_teredo(sc);
ure_write_1(sc, URE_PLA_CRWECR0xe81c, URE_MCU_TYPE_PLA0x0100, URE_CRWECR_NORAML0x00);
ure_write_1(sc, URE_PLA_CR0xe813, URE_MCU_TYPE_PLA0x0100, 0);

URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB)ure_write_1(sc, 0xe84f, 0x0100, ure_read_1(sc, 0xe84f, 0x0100
) & ~(0x80));
URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) & ~(0x4000));
for (i = 0; i < URE_TIMEOUT1000; i++) {
if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
    URE_LINK_LIST_READY0x02)
	break;
usbd_delay_ms(sc->ure_udev, 1);
}
if (i == URE_TIMEOUT1000)
printf("%s: timeout waiting for OOB control\n",
    sc->ure_dev.dv_xname);
URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) | (0x8000));
for (i = 0; i < URE_TIMEOUT1000; i++) {
if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
    URE_LINK_LIST_READY0x02)
	break;
usbd_delay_ms(sc->ure_udev, 1);
}
if (i == URE_TIMEOUT1000)
printf("%s: timeout waiting for OOB control\n",
    sc->ure_dev.dv_xname);

ure_reset(sc);

/* Configure Rx FIFO threshold. */
ure_write_4(sc, URE_PLA_RXFIFO_CTRL00xc0a0, URE_MCU_TYPE_PLA0x0100,
   URE_RXFIFO_THR1_NORMAL0x00080002);
if (sc->ure_udev->speed == USB_SPEED_FULL2) {
rx_fifo1 = URE_RXFIFO_THR2_FULL0x00000060;
rx_fifo2 = URE_RXFIFO_THR3_FULL0x00000078;
} else {
rx_fifo1 = URE_RXFIFO_THR2_HIGH0x00000038;
rx_fifo2 = URE_RXFIFO_THR3_HIGH0x00000048;
}
ure_write_4(sc, URE_PLA_RXFIFO_CTRL10xc0a4, URE_MCU_TYPE_PLA0x0100, rx_fifo1);
ure_write_4(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100, rx_fifo2);

/* Configure Tx FIFO threshold. */
ure_write_4(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100,
   URE_TXFIFO_THR_NORMAL0x00400008);

ure_write_1(sc, URE_USB_TX_AGG0xd40a, URE_MCU_TYPE_USB0x0000,
   URE_TX_AGG_MAX_THRESHOLD0x03);
ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000, URE_RX_THR_HIGH0x7a120180);
ure_write_4(sc, URE_USB_TX_DMA0xd434, URE_MCU_TYPE_USB0x0000,
   URE_TEST_MODE_DISABLE0x00000001 | URE_TX_SIZE_ADJUST10x00000100);

ure_rxvlan(sc);
      ure_write_2(sc, URE_PLA_RMS0xc016, URE_MCU_TYPE_PLA0x0100,
   ETHER_MAX_LEN1518 + ETHER_VLAN_ENCAP_LEN4);
URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO)ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100
) | (0x0080));

/* Enable ALDPS. */
ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG0x2010,
   URE_ENPWRSAVE0x8000 | URE_ENPDNPS0x0200 | URE_LINKENA0x0100 | URE_DIS_SDSAVE0x0010);
1450}

1452void
1453ure_rtl8153_nic_reset(struct ure_softc *sc)
1454{
struct ifnet	*ifp = &sc->ure_ac.ac_if;
uint32_t	reg = 0;
uint8_t		u1u2[8] = { 0 };
int		i;

if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) & ~(0x0001))
    LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) & ~(0x0001));
} else {
memset(u1u2, 0x00, sizeof(u1u2))__builtin_memset((u1u2), (0x00), (sizeof(u1u2)));
ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f,
    u1u2, sizeof(u1u2));
}
URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) & ~(0x0001));

/* Disable ALDPS. */
ure_ocp_reg_write(sc, URE_OCP_POWER_CFG0xa430,
   ure_ocp_reg_read(sc, URE_OCP_POWER_CFG0xa430) & ~URE_EN_ALDPS0x0004);
for (i = 0; i < 20; i++) {
usbd_delay_ms(sc->ure_udev, 1);
if (ure_read_2(sc, 0xe000, URE_MCU_TYPE_PLA0x0100) & 0x0100)
	break;
}

URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN)ure_write_2(sc, 0xe85a, 0x0100, ure_read_2(sc, 0xe85a, 0x0100
) | (0x0008));
ure_disable_teredo(sc);

URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL)ure_write_4(sc, 0xc010, 0x0100, ure_read_4(sc, 0xc010, 0x0100
) & ~((0x00000001 | 0x00000002 | 0x00000004 | 0x00000008)
));

ure_reset(sc);
ure_reset_bmu(sc);

URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB)ure_write_1(sc, 0xe84f, 0x0100, ure_read_1(sc, 0xe84f, 0x0100
) & ~(0x80));
URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) & ~(0x4000));

if (!(sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))) {
for (i = 0; i < URE_TIMEOUT1000; i++) {
	if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
	    URE_LINK_LIST_READY0x02)
		break;
	usbd_delay_ms(sc->ure_udev, 1);
}
if (i == URE_TIMEOUT1000)
	printf("%s: timeout waiting for OOB control\n",
	    sc->ure_dev.dv_xname);
URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) | (0x8000))
    URE_RE_INIT_LL)ure_write_2(sc, 0xe8de, 0x0100, ure_read_2(sc, 0xe8de, 0x0100
) | (0x8000));
for (i = 0; i < URE_TIMEOUT1000; i++) {
	if (ure_read_1(sc, URE_PLA_OOB_CTRL0xe84f, URE_MCU_TYPE_PLA0x0100) &
	    URE_LINK_LIST_READY0x02)
		break;
	usbd_delay_ms(sc->ure_udev, 1);
}
if (i == URE_TIMEOUT1000)
	printf("%s: timeout waiting for OOB control\n",
	    sc->ure_dev.dv_xname);
}

ure_rxvlan(sc);

ure_write_2(sc, URE_PLA_RMS0xc016, URE_MCU_TYPE_PLA0x0100,
   URE_FRAMELEN(ifp->if_mtu)(ifp->if_data.ifi_mtu + ((6 * 2) + 2) + 4 + 4));
ure_write_1(sc, URE_PLA_MTPS0xe615, URE_MCU_TYPE_PLA0x0100, MTPS_JUMBO192);

if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
ure_write_2(sc, URE_PLA_RX_FIFO_FULL0xc0a6, URE_MCU_TYPE_PLA0x0100,
    (sc->ure_flags & URE_FLAG_81560x4000) ? 1024 : 512);
ure_write_2(sc, URE_PLA_RX_FIFO_EMPTY0xc0aa, URE_MCU_TYPE_PLA0x0100,
    (sc->ure_flags & URE_FLAG_81560x4000) ? 2048 : 1024);

/* Tx share fifo free credit full threshold. */
ure_write_2(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100, 8);
ure_write_2(sc, URE_PLA_TXFIFO_FULL0xe61a, URE_MCU_TYPE_PLA0x0100, 128);

if (sc->ure_flags & URE_FLAG_81560x4000)
	URE_SETBIT_2(sc, URE_USB_BMU_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd4b4, 0x0000, ure_read_2(sc, 0xd4b4, 0x0000
) | (0x02))
	    URE_ACT_ODMA)ure_write_2(sc, 0xd4b4, 0x0000, ure_read_2(sc, 0xd4b4, 0x0000
) | (0x02));

/* FIFO settings */
reg = ure_read_2(sc, URE_PLA_RXFIFO_FULL0xc0a2, URE_MCU_TYPE_PLA0x0100);
reg &= ~URE_RXFIFO_FULL_MASK0x0fff;
ure_write_2(sc, URE_PLA_RXFIFO_FULL0xc0a2, URE_MCU_TYPE_PLA0x0100,
    reg | 0x0008);

URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
    URE_PLA_MCU_SPDWN_EN)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000));

URE_CLRBIT_2(sc, URE_USB_SPEED_OPTION, URE_MCU_TYPE_USB,ure_write_2(sc, 0xd32a, 0x0000, ure_read_2(sc, 0xd32a, 0x0000
) & ~(0x0100 | 0x0200))
    URE_RG_PWRDN_EN | URE_ALL_SPEED_OFF)ure_write_2(sc, 0xd32a, 0x0000, ure_read_2(sc, 0xd32a, 0x0000
) & ~(0x0100 | 0x0200));

ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000,
    0x00600400);
} else {
URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100
) | (0x0080))
    URE_TCR0_AUTO_FIFO)ure_write_2(sc, 0xe610, 0x0100, ure_read_2(sc, 0xe610, 0x0100
) | (0x0080));
ure_reset(sc);

/* Configure Rx FIFO threshold. */
ure_write_4(sc, URE_PLA_RXFIFO_CTRL00xc0a0, URE_MCU_TYPE_PLA0x0100,
    URE_RXFIFO_THR1_NORMAL0x00080002);
ure_write_2(sc, URE_PLA_RXFIFO_CTRL10xc0a4, URE_MCU_TYPE_PLA0x0100,
    URE_RXFIFO_THR2_NORMAL0x00a0);
ure_write_2(sc, URE_PLA_RXFIFO_CTRL20xc0a8, URE_MCU_TYPE_PLA0x0100,
    URE_RXFIFO_THR3_NORMAL0x0110);

/* Configure Tx FIFO threshold. */
ure_write_4(sc, URE_PLA_TXFIFO_CTRL0xe618, URE_MCU_TYPE_PLA0x0100,
    URE_TXFIFO_THR_NORMAL20x01000008);

if (sc->ure_flags & URE_FLAG_8153B0x2000) {
	ure_write_4(sc, URE_USB_RX_BUF_TH0xd40c, URE_MCU_TYPE_USB0x0000,
	    URE_RX_THR_B0x00010001);

	URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3,ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000))
	    URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN)ure_write_2(sc, 0xe0cc, 0x0100, ure_read_2(sc, 0xe0cc, 0x0100
) & ~(0x4000));
} else {
	URE_SETBIT_1(sc, URE_PLA_CONFIG6, URE_MCU_TYPE_PLA,ure_write_1(sc, 0xe90a, 0x0100, ure_read_1(sc, 0xe90a, 0x0100
) | (0x01))
	    URE_LANWAKE_CLR_EN)ure_write_1(sc, 0xe90a, 0x0100, ure_read_1(sc, 0xe90a, 0x0100
) | (0x01));
	URE_CLRBIT_1(sc, URE_PLA_LWAKE_CTRL_REG,ure_write_1(sc, 0xe007, 0x0100, ure_read_1(sc, 0xe007, 0x0100
) & ~(0x80))
	    URE_MCU_TYPE_PLA, URE_LANWAKE_PIN)ure_write_1(sc, 0xe007, 0x0100, ure_read_1(sc, 0xe007, 0x0100
) & ~(0x80));
	URE_CLRBIT_2(sc, URE_USB_SSPHYLINK1, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb426, 0x0000, ure_read_2(sc, 0xb426, 0x0000
) & ~(0x0002))
	    URE_DELAY_PHY_PWR_CHG)ure_write_2(sc, 0xb426, 0x0000, ure_read_2(sc, 0xb426, 0x0000
) & ~(0x0002));
}
}

/* Enable ALDPS. */
ure_ocp_reg_write(sc, URE_OCP_POWER_CFG0xa430,
   ure_ocp_reg_read(sc, URE_OCP_POWER_CFG0xa430) | URE_EN_ALDPS0x0004);

if ((sc->ure_chip & (URE_CHIP_VER_5C200x10 | URE_CHIP_VER_5C300x20)) ||
   (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)))
URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0001))
    URE_U2P3_ENABLE)ure_write_2(sc, 0xb460, 0x0000, ure_read_2(sc, 0xb460, 0x0000
) | (0x0001));

if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
if (sc->ure_udev->speed == USB_SPEED_SUPER4)
	URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB,ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001))
	    LPM_U1U2_EN)ure_write_2(sc, 0xcfd8, 0x0000, ure_read_2(sc, 0xcfd8, 0x0000
) | (0x0001));
} else {
memset(u1u2, 0xff, sizeof(u1u2))__builtin_memset((u1u2), (0xff), (sizeof(u1u2)));
ure_write_mem(sc, URE_USB_TOLERANCE0xd490, URE_BYTE_EN_SIX_BYTES0x3f,
    u1u2, sizeof(u1u2));
}
1598}

1600uint16_t
1601ure_rtl8153_phy_status(struct ure_softc *sc, int desired)
1602{
uint16_t	reg;
int		i;

for (i = 0; i < 500; i++) {
reg = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS0xa420) &
    URE_PHY_STAT_MASK0x0007;
if (desired) {
	if (reg == desired)
		break;
} else {
	if (reg == URE_PHY_STAT_LAN_ON3 ||
	    reg == URE_PHY_STAT_PWRDN5 ||
	    reg == URE_PHY_STAT_EXT_INIT2)
		break;
}
usbd_delay_ms(sc->ure_udev, 20);
}
if (i == 500)
printf("%s: timeout waiting for phy to stabilize\n",
    sc->ure_dev.dv_xname);

return reg;
1625}

1627void
1628ure_wait_for_flash(struct ure_softc *sc)
1629{
int i;

if ((ure_read_2(sc, URE_PLA_GPHY_CTRL0xd3ae, URE_MCU_TYPE_PLA0x0100) &
   URE_GPHY_FLASH0x0002) &&
   !(ure_read_2(sc, URE_USB_GPHY_CTRL0xd284, URE_MCU_TYPE_USB0x0000) &
   URE_BYPASS_FLASH0x0020)) {
   	for (i = 0; i < 100; i++) {
	if (ure_read_2(sc, URE_USB_GPHY_CTRL0xd284,
	    URE_MCU_TYPE_USB0x0000) & URE_GPHY_PATCH_DONE0x0004)
		break;
	DELAY(1000)(*delay_func)(1000);
}
if (i == 100)
	printf("%s: timeout waiting for loading flash\n",
	    sc->ure_dev.dv_xname);
}
1646}

1648void
1649ure_reset_bmu(struct ure_softc *sc)
1650{
uint8_t	reg;

reg = ure_read_1(sc, URE_USB_BMU_RESET0xd4b0, URE_MCU_TYPE_USB0x0000);
reg &= ~(BMU_RESET_EP_IN0x01 | BMU_RESET_EP_OUT0x02);
ure_write_1(sc, URE_USB_BMU_RESET0xd4b0, URE_MCU_TYPE_USB0x0000, reg);
reg |= BMU_RESET_EP_IN0x01 | BMU_RESET_EP_OUT0x02;
ure_write_1(sc, URE_USB_BMU_RESET0xd4b0, URE_MCU_TYPE_USB0x0000, reg);
1658}

1660void
1661ure_disable_teredo(struct ure_softc *sc)
1662{
if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))
ure_write_1(sc, URE_PLA_TEREDO_CFG0xc0bc, URE_MCU_TYPE_PLA0x0100, 0xff);
else {
URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA,ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100
) & ~(0x8000 | 0x00fe | 0x0001))
    URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK |ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100
) & ~(0x8000 | 0x00fe | 0x0001))
    URE_OOB_TEREDO_EN)ure_write_2(sc, 0xc0bc, 0x0100, ure_read_2(sc, 0xc0bc, 0x0100
) & ~(0x8000 | 0x00fe | 0x0001));
}
ure_write_2(sc, URE_PLA_WDT6_CTRL0xe428, URE_MCU_TYPE_PLA0x0100, URE_WDT6_SET_MODE0x0010);
ure_write_2(sc, URE_PLA_REALWOW_TIMER0xd2e8, URE_MCU_TYPE_PLA0x0100, 0);
ure_write_4(sc, URE_PLA_TEREDO_TIMER0xd2cc, URE_MCU_TYPE_PLA0x0100, 0);
1673}

1675int
1676ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1677{
struct ure_softc	*sc = ifp->if_softc;
struct ifreq		*ifr = (struct ifreq *)data;
int			s, error = 0;

s = splnet()splraise(0x4);

switch (cmd) {
case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
ifp->if_flags |= IFF_UP0x1;
if (!(ifp->if_flags & IFF_RUNNING0x40))
	ure_init(sc);
break;

case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
if (ifp->if_flags & IFF_UP0x1) {
	if (ifp->if_flags & IFF_RUNNING0x40)
		error = ENETRESET52;
	else
		ure_init(sc);
} else {
	if (ifp->if_flags & IFF_RUNNING0x40)
		ure_stop(sc);
}
break;

case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((56))):
case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
 8) | ((55))):
if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))
	error = ifmedia_ioctl(ifp, ifr, &sc->ure_ifmedia, cmd);
else
	error = ifmedia_ioctl(ifp, ifr, &sc->ure_mii.mii_media,
	    cmd);
break;

default:
error = ether_ioctl(ifp, &sc->ure_ac, cmd, data);
}

if (error == ENETRESET52) {
if (ifp->if_flags & IFF_RUNNING0x40)
	ure_iff(sc);
error = 0;
}

splx(s)spllower(s);

return (error);
1725}

1727int
1728ure_match(struct device *parent, void *match, void *aux)
1729{
struct usb_attach_arg	*uaa = aux;

if (uaa->iface == NULL((void *)0) || uaa->configno != 1)
return (UMATCH_NONE0);

return (usb_lookup(ure_devs, uaa->vendor, uaa->product)usbd_match_device((const struct usb_devno *)(ure_devs), sizeof
 (ure_devs) / sizeof ((ure_devs)[0]), sizeof ((ure_devs)[0]),
 (uaa->vendor), (uaa->product)) != NULL((void *)0) ?
   UMATCH_VENDOR_PRODUCT_CONF_IFACE8 : UMATCH_NONE0);
1737}

1739void
1740ure_attach(struct device *parent, struct device *self, void *aux)
1741{
struct ure_softc		*sc = (struct ure_softc *)self;
struct usb_attach_arg		*uaa = aux;
usb_interface_descriptor_t	*id;
usb_endpoint_descriptor_t	*ed;
u_char				eaddr[8]; /* 4byte padded */
struct ifnet			*ifp;
int				i, mii_flags = 0, s;
uint16_t			ver;

sc->ure_udev = uaa->device;
sc->ure_iface = uaa->iface;

usb_init_task(&sc->ure_tick_task, ure_tick_task, sc,((&sc->ure_tick_task)->fun = (ure_tick_task), (&
sc->ure_tick_task)->arg = (sc), (&sc->ure_tick_task
)->type = (0), (&sc->ure_tick_task)->state = 0x0
)
   USB_TASK_TYPE_GENERIC)((&sc->ure_tick_task)->fun = (ure_tick_task), (&
sc->ure_tick_task)->arg = (sc), (&sc->ure_tick_task
)->type = (0), (&sc->ure_tick_task)->state = 0x0
);

id = usbd_get_interface_descriptor(sc->ure_iface);

for (i = 0; i < id->bNumEndpoints; i++) {
1
Assuming 'i' is >= field 'bNumEndpoints'→
2
←
Loop condition is false. Execution continues on line 1775→
ed = usbd_interface2endpoint_descriptor(sc->ure_iface, i);
if (!ed) {
	printf("%s: couldn't get ep %d\n",
	    sc->ure_dev.dv_xname, i);
	return;
}
if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_IN0x80 &&
    UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) == UE_BULK0x02) {
	sc->ure_ed[URE_ENDPT_RX0] = ed->bEndpointAddress;
} else if (UE_GET_DIR(ed->bEndpointAddress)((ed->bEndpointAddress) & 0x80) == UE_DIR_OUT0x00 &&
    UE_GET_XFERTYPE(ed->bmAttributes)((ed->bmAttributes) & 0x03) == UE_BULK0x02) {
	sc->ure_ed[URE_ENDPT_TX1] = ed->bEndpointAddress;
}
}

sc->ure_txbufsz = URE_TX_BUFSZ16384;
sc->ure_rxbufsz = URE_8153_RX_BUFSZ32768;

s = splnet()splraise(0x4);

sc->ure_phyno = 0;
printf("%s: ", sc->ure_dev.dv_xname);

ver = ure_read_2(sc, URE_PLA_TCR10xe612, URE_MCU_TYPE_PLA0x0100) & URE_VERSION_MASK0x7cf0;
3
←
Calling 'ure_read_2'→
switch (ver) {
case 0x4c00:
sc->ure_flags = URE_FLAG_81520x1000;
sc->ure_rxbufsz = URE_8152_RX_BUFSZ16384;
sc->ure_chip |= URE_CHIP_VER_4C000x01;
printf("RTL8152 (0x4c00)");
break;
case 0x4c10:
sc->ure_flags = URE_FLAG_81520x1000;
sc->ure_rxbufsz = URE_8152_RX_BUFSZ16384;
sc->ure_chip |= URE_CHIP_VER_4C100x02;
printf("RTL8152 (0x4c10)");
break;
case 0x5c00:
sc->ure_chip |= URE_CHIP_VER_5C000x04;
printf("RTL8153 (0x5c00)");
break;
case 0x5c10:
sc->ure_chip |= URE_CHIP_VER_5C100x08;
printf("RTL8153 (0x5c10)");
break;
case 0x5c20:
sc->ure_chip |= URE_CHIP_VER_5C200x10;
printf("RTL8153 (0x5c20)");
break;
case 0x5c30:
sc->ure_chip |= URE_CHIP_VER_5C300x20;
printf("RTL8153 (0x5c30)");
break;
case 0x6000:
sc->ure_flags = URE_FLAG_8153B0x2000;
printf("RTL8153B (0x6000)");
break;
case 0x6010:
sc->ure_flags = URE_FLAG_8153B0x2000;
printf("RTL8153B (0x6010)");
break;
case 0x7020:
sc->ure_flags = URE_FLAG_81560x4000;
printf("RTL8156 (0x7020)");
break;
case 0x7030:
sc->ure_flags = URE_FLAG_81560x4000;
printf("RTL8156 (0x7030)");
break;
case 0x7410:
sc->ure_flags = URE_FLAG_8156B0x8000;
printf("RTL8156B (0x7410)");
break;
case 0x7420:
sc->ure_flags = URE_FLAG_8156B0x8000;
sc->ure_chip = URE_CHIP_VER_74200x80;
printf("RTL8153D (0x7420)");
break;
default:
printf(", unknown ver %02x", ver);
break;
}

if (sc->ure_flags & URE_FLAG_81520x1000)
ure_rtl8152_init(sc);
else if (sc->ure_flags & (URE_FLAG_8153B0x2000 | URE_FLAG_81560x4000 |
   URE_FLAG_8156B0x8000))
ure_rtl8153b_init(sc);
else
ure_rtl8153_init(sc);

if (sc->ure_chip & URE_CHIP_VER_4C000x01)
ure_read_mem(sc, URE_PLA_IDR0xc000, URE_MCU_TYPE_PLA0x0100, eaddr,
    sizeof(eaddr));
else
ure_read_mem(sc, URE_PLA_BACKUP0xd000, URE_MCU_TYPE_PLA0x0100, eaddr,
    sizeof(eaddr));

printf(", address %s\n", ether_sprintf(eaddr));

bcopy(eaddr, (char *)&sc->ure_ac.ac_enaddr, ETHER_ADDR_LEN6);

ifp = &sc->ure_ac.ac_if;
ifp->if_softc = sc;
strlcpy(ifp->if_xname, sc->ure_dev.dv_xname, IFNAMSIZ16);
ifp->if_flags = IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
ifp->if_ioctl = ure_ioctl;
ifp->if_start = ure_start;
ifp->if_watchdog = ure_watchdog;

ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010 | IFCAP_CSUM_IPv40x00000001 |
   IFCAP_CSUM_TCPv40x00000002 | IFCAP_CSUM_UDPv40x00000004;

1873#if NVLAN1 > 0
ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
1875#endif

if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000)) {
ifmedia_init(&sc->ure_ifmedia, IFM_IMASK0xff00000000000000ULL, ure_ifmedia_upd,
    ure_ifmedia_sts);
ure_add_media_types(sc);
ifmedia_add(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0));
ifmedia_set(&sc->ure_ifmedia, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);
sc->ure_ifmedia.ifm_media = sc->ure_ifmedia.ifm_cur->ifm_media;
} else {
rw_init(&sc->ure_mii_lock, "uremii")_rw_init_flags(&sc->ure_mii_lock, "uremii", 0, ((void *
)0));

sc->ure_mii.mii_ifp = ifp;
sc->ure_mii.mii_readreg = ure_miibus_readreg;
sc->ure_mii.mii_writereg = ure_miibus_writereg;
sc->ure_mii.mii_statchg = ure_miibus_statchg;
sc->ure_mii.mii_flags = MIIF_AUTOTSLEEP0x0010;

ifmedia_init(&sc->ure_mii.mii_media, 0, ure_ifmedia_upd,
    ure_ifmedia_sts);
if (!(sc->ure_flags & URE_FLAG_81520x1000))
	mii_flags |= MIIF_DOPAUSE0x0100;
mii_attach(self, &sc->ure_mii, 0xffffffff, sc->ure_phyno,
    MII_OFFSET_ANY-1, mii_flags);
if (LIST_FIRST(&sc->ure_mii.mii_phys)((&sc->ure_mii.mii_phys)->lh_first) == NULL((void *)0)) {
	ifmedia_add(&sc->ure_mii.mii_media,
	    IFM_ETHER0x0000000000000100ULL | IFM_NONE2ULL, 0, NULL((void *)0));
	ifmedia_set(&sc->ure_mii.mii_media,
	    IFM_ETHER0x0000000000000100ULL | IFM_NONE2ULL);
} else
	ifmedia_set(&sc->ure_mii.mii_media,
	    IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);
}

if_attach(ifp);
ether_ifattach(ifp);

timeout_set(&sc->ure_stat_ch, ure_tick, sc);

splx(s)spllower(s);
1915}

1917int
1918ure_detach(struct device *self, int flags)
1919{
struct ure_softc	*sc = (struct ure_softc *)self;
struct ifnet		*ifp = &sc->ure_ac.ac_if;
int			s;

if (timeout_initialized(&sc->ure_stat_ch)((&sc->ure_stat_ch)->to_flags & 0x04))
timeout_del(&sc->ure_stat_ch);

if (sc->ure_ep[URE_ENDPT_TX1] != NULL((void *)0))
usbd_abort_pipe(sc->ure_ep[URE_ENDPT_TX1]);
if (sc->ure_ep[URE_ENDPT_RX0] != NULL((void *)0))
usbd_abort_pipe(sc->ure_ep[URE_ENDPT_RX0]);

usb_rem_task(sc->ure_udev, &sc->ure_tick_task);

s = splusb()splraise(0x2);

if (--sc->ure_refcnt >= 0) {
usb_detach_wait(&sc->ure_dev);
}

if (ifp->if_flags & IFF_RUNNING0x40)
ure_stop(sc);

mii_detach(&sc->ure_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1);
ifmedia_delete_instance(&sc->ure_mii.mii_media, IFM_INST_ANY((uint64_t) -1));
if (ifp->if_softc != NULL((void *)0)) {
ether_ifdetach(ifp);
if_detach(ifp);
}

splx(s)spllower(s);

return 0;
1953}

1955void
1956ure_tick_task(void *xsc)
1957{
struct ure_softc	*sc = xsc;
struct mii_data		*mii;
int			s;

if (sc == NULL((void *)0))
return;

if (usbd_is_dying(sc->ure_udev))
return;
mii = &sc->ure_mii;

s = splnet()splraise(0x4);
if (sc->ure_flags & (URE_FLAG_81560x4000 | URE_FLAG_8156B0x8000))
ure_link_state(sc);
else {
mii_tick(mii);
if ((sc->ure_flags & URE_FLAG_LINK0x0001) == 0)
	ure_miibus_statchg(&sc->ure_dev);
}
timeout_add_sec(&sc->ure_stat_ch, 1);
splx(s)spllower(s);
1979}

1981void
1982ure_lock_mii(struct ure_softc *sc)
1983{
sc->ure_refcnt++;
rw_enter_write(&sc->ure_mii_lock);
1986}

1988void
1989ure_unlock_mii(struct ure_softc *sc)
1990{
rw_exit_write(&sc->ure_mii_lock);
if (--sc->ure_refcnt < 0)
usb_detach_wakeup(&sc->ure_dev);
1994}

1996void
1997ure_rxeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
1998{
struct ure_chain	*c = (struct ure_chain *)priv;
struct ure_softc	*sc = c->uc_sc;
struct ifnet		*ifp = &sc->ure_ac.ac_if;
u_char			*buf = c->uc_buf;
uint32_t		cflags, rxvlan, total_len;
struct mbuf_list	ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
struct mbuf		*m;
int			pktlen = 0, s;
struct ure_rxpkt	rxhdr;

if (usbd_is_dying(sc->ure_udev))
return;

if (!(ifp->if_flags & IFF_RUNNING0x40))
return;

if (status != USBD_NORMAL_COMPLETION) {
if (status == USBD_NOT_STARTED || status == USBD_CANCELLED)
	return;
if (usbd_ratecheck(&sc->ure_rx_notice)) {
	printf("%s: usb errors on rx: %s\n",
		sc->ure_dev.dv_xname, usbd_errstr(status));
}
if (status == USBD_STALLED)
	usbd_clear_endpoint_stall_async(
	    sc->ure_ep[URE_ENDPT_RX0]);
goto done;
}

usbd_get_xfer_status(xfer, NULL((void *)0), NULL((void *)0), &total_len, NULL((void *)0));
DPRINTFN(3, ("received %d bytes\n", total_len));

do {
if (total_len < sizeof(rxhdr)) {
	DPRINTF(("too few bytes left for a packet header\n"));
	ifp->if_ierrorsif_data.ifi_ierrors++;
	goto done;
}

buf += roundup(pktlen, URE_RX_BUF_ALIGN)((((pktlen)+((8)-1))/(8))*(8));

memcpy(&rxhdr, buf, sizeof(rxhdr))__builtin_memcpy((&rxhdr), (buf), (sizeof(rxhdr)));
total_len -= sizeof(rxhdr);

pktlen = letoh32(rxhdr.ure_pktlen)((__uint32_t)(rxhdr.ure_pktlen)) & URE_RXPKT_LEN_MASK0x7fff;
DPRINTFN(4, ("next packet is %d bytes\n", pktlen));
if (pktlen > total_len) {
	DPRINTF(("not enough bytes left for next packet\n"));
	ifp->if_ierrorsif_data.ifi_ierrors++;
	goto done;
}

total_len -= roundup(pktlen, URE_RX_BUF_ALIGN)((((pktlen)+((8)-1))/(8))*(8));
buf += sizeof(rxhdr);

m = m_devget(buf, pktlen - ETHER_CRC_LEN4, ETHER_ALIGN2);
if (m == NULL((void *)0)) {
	DPRINTF(("unable to allocate mbuf for next packet\n"));
	ifp->if_ierrorsif_data.ifi_ierrors++;
	goto done;
}

cflags = letoh32(rxhdr.ure_csum)((__uint32_t)(rxhdr.ure_csum));
rxvlan = letoh32(rxhdr.ure_vlan)((__uint32_t)(rxhdr.ure_vlan));

/* Check IP header checksum. */
if ((rxvlan & URE_RXPKT_IPV4(1 << 19)) &&
    !(cflags & URE_RXPKT_IPSUMBAD(1 << 23)))
	m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;

/* Check TCP/UDP checksum. */
if ((rxvlan & (URE_RXPKT_IPV4(1 << 19) | URE_RXPKT_IPV6(1 << 20))) &&
    (((rxvlan & URE_RXPKT_TCP(1 << 22)) &&
    !(cflags & URE_RXPKT_TCPSUMBAD(1 << 21))) ||
    ((rxvlan & URE_RXPKT_UDP(1 << 23)) &&
    !(cflags & URE_RXPKT_UDPSUMBAD(1 << 22)))))
	 m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK0x0020 |
	     M_UDP_CSUM_IN_OK0x0080;
2077#if NVLAN1 > 0
if (rxvlan & URE_RXPKT_VLAN_TAG(1 << 16)) {
	m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag =
	    swap16(rxvlan & URE_RXPKT_VLAN_DATA)(__uint16_t)(__builtin_constant_p(rxvlan & 0xffff) ? (__uint16_t
)(((__uint16_t)(rxvlan & 0xffff) & 0xffU) << 8 |
 ((__uint16_t)(rxvlan & 0xffff) & 0xff00U) >> 8
) : __swap16md(rxvlan & 0xffff));
	 m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
}
2083#endif

ml_enqueue(&ml, m);
} while (total_len > 0);

2088done:
s = splnet()splraise(0x4);
if_input(ifp, &ml);
splx(s)spllower(s);
memset(c->uc_buf, 0, sc->ure_rxbufsz)__builtin_memset((c->uc_buf), (0), (sc->ure_rxbufsz));

usbd_setup_xfer(xfer, sc->ure_ep[URE_ENDPT_RX0], c, c->uc_buf,
   sc->ure_rxbufsz, USBD_SHORT_XFER_OK0x04 | USBD_NO_COPY0x01,
   USBD_NO_TIMEOUT0, ure_rxeof);
usbd_transfer(xfer);
2098}


2101void
2102ure_txeof(struct usbd_xfer *xfer, void *priv, usbd_status status)
2103{
struct ure_softc	*sc;
struct ure_chain	*c;
struct ifnet		*ifp;
int			s;

c = priv;
sc = c->uc_sc;
ifp = &sc->ure_ac.ac_if;

if (usbd_is_dying(sc->ure_udev))
return;

if (status != USBD_NORMAL_COMPLETION)
DPRINTF(("%s: %s uc_idx=%u : %s\n", sc->ure_dev.dv_xname,
	__func__, c->uc_idx, usbd_errstr(status)));

s = splnet()splraise(0x4);

c->uc_cnt = 0;
c->uc_buflen = 0;

SLIST_INSERT_HEAD(&sc->ure_cdata.ure_tx_free, c, uc_list)do { (c)->uc_list.sle_next = (&sc->ure_cdata.ure_tx_free
)->slh_first; (&sc->ure_cdata.ure_tx_free)->slh_first
 = (c); } while (0);

if (status != USBD_NORMAL_COMPLETION) {
if (status == USBD_NOT_STARTED || status == USBD_CANCELLED) {
	splx(s)spllower(s);
	return;
}

ifp->if_oerrorsif_data.ifi_oerrors++;
printf("%s: usb error on tx: %s\n", sc->ure_dev.dv_xname,
    usbd_errstr(status));

if (status == USBD_STALLED)
	usbd_clear_endpoint_stall_async(
	    sc->ure_ep[URE_ENDPT_TX1]);
splx(s)spllower(s);
return;
}

ifp->if_timer = 0;
if (ifq_is_oactive(&ifp->if_snd))
ifq_restart(&ifp->if_snd);
splx(s)spllower(s);
2148}

2150int
2151ure_encap_txpkt(struct mbuf *m, char *buf, uint32_t maxlen)
2152{
struct ure_txpkt	txhdr;
uint32_t		len = sizeof(txhdr), cflags = 0;

if (len + m->m_pkthdrM_dat.MH.MH_pkthdr.len > maxlen)
return (-1);

if ((m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags &
   (M_IPV4_CSUM_OUT0x0001 | M_TCP_CSUM_OUT0x0002 | M_UDP_CSUM_OUT0x0004)) != 0) {
cflags |= URE_TXPKT_IPV4(1 << 29);
if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_TCP_CSUM_OUT0x0002)
	cflags |= URE_TXPKT_TCP(1 << 30);
if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_UDP_CSUM_OUT0x0004)
	cflags |= URE_TXPKT_UDP(1U << 31);
}

2168#if NVLAN1 > 0
if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020)
cflags |= URE_TXPKT_VLAN_TAG(1 << 16) | swap16(m->m_pkthdr.ether_vtag)(__uint16_t)(__builtin_constant_p(m->M_dat.MH.MH_pkthdr.ether_vtag
) ? (__uint16_t)(((__uint16_t)(m->M_dat.MH.MH_pkthdr.ether_vtag
) & 0xffU) << 8 | ((__uint16_t)(m->M_dat.MH.MH_pkthdr
.ether_vtag) & 0xff00U) >> 8) : __swap16md(m->M_dat
.MH.MH_pkthdr.ether_vtag));
2171#endif

txhdr.ure_pktlen = htole32(m->m_pkthdr.len | URE_TXPKT_TX_FS |((__uint32_t)(m->M_dat.MH.MH_pkthdr.len | (1U << 31)
 | (1 << 30)))
   URE_TXPKT_TX_LS)((__uint32_t)(m->M_dat.MH.MH_pkthdr.len | (1U << 31)
 | (1 << 30)));
txhdr.ure_vlan = htole32(cflags)((__uint32_t)(cflags));
memcpy(buf, &txhdr, len)__builtin_memcpy((buf), (&txhdr), (len));

m_copydata(m, 0, m->m_pkthdrM_dat.MH.MH_pkthdr.len, buf + len);
len += m->m_pkthdrM_dat.MH.MH_pkthdr.len;

return (len);
2182}

2184int
2185ure_encap_xfer(struct ifnet *ifp, struct ure_softc *sc, struct ure_chain *c)
2186{
usbd_status	err;

usbd_setup_xfer(c->uc_xfer, sc->ure_ep[URE_ENDPT_TX1], c, c->uc_buf,
   c->uc_buflen, USBD_FORCE_SHORT_XFER0x08 | USBD_NO_COPY0x01, 10000,
   ure_txeof);

err = usbd_transfer(c->uc_xfer);
if (err != USBD_IN_PROGRESS) {
c->uc_cnt = 0;
c->uc_buflen = 0;
ure_stop(sc);
return (EIO5);
}

return (0);
2202}