File: | dev/pci/drm/i915/i915_driver.c |
Warning: | line 2623, column 20 Value stored to 'psc' during its initialization is never read |
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1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ |
3 | /* |
4 | * |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the |
10 | * "Software"), to deal in the Software without restriction, including |
11 | * without limitation the rights to use, copy, modify, merge, publish, |
12 | * distribute, sub license, and/or sell copies of the Software, and to |
13 | * permit persons to whom the Software is furnished to do so, subject to |
14 | * the following conditions: |
15 | * |
16 | * The above copyright notice and this permission notice (including the |
17 | * next paragraph) shall be included in all copies or substantial portions |
18 | * of the Software. |
19 | * |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
27 | * |
28 | */ |
29 | |
30 | #include <linux/acpi.h> |
31 | #include <linux/device.h> |
32 | #include <linux/module.h> |
33 | #include <linux/oom.h> |
34 | #include <linux/pci.h> |
35 | #include <linux/pm.h> |
36 | #include <linux/pm_runtime.h> |
37 | #include <linux/pnp.h> |
38 | #include <linux/slab.h> |
39 | #include <linux/string_helpers.h> |
40 | #include <linux/vga_switcheroo.h> |
41 | #include <linux/vt.h> |
42 | |
43 | #include <drm/drm_aperture.h> |
44 | #include <drm/drm_atomic_helper.h> |
45 | #include <drm/drm_ioctl.h> |
46 | #include <drm/drm_managed.h> |
47 | #include <drm/drm_probe_helper.h> |
48 | |
49 | #include "display/intel_acpi.h" |
50 | #include "display/intel_bw.h" |
51 | #include "display/intel_cdclk.h" |
52 | #include "display/intel_display_types.h" |
53 | #include "display/intel_dmc.h" |
54 | #include "display/intel_dp.h" |
55 | #include "display/intel_dpt.h" |
56 | #include "display/intel_fbdev.h" |
57 | #include "display/intel_hotplug.h" |
58 | #include "display/intel_overlay.h" |
59 | #include "display/intel_pch_refclk.h" |
60 | #include "display/intel_pipe_crc.h" |
61 | #include "display/intel_pps.h" |
62 | #include "display/intel_sprite.h" |
63 | #include "display/intel_vga.h" |
64 | #include "display/skl_watermark.h" |
65 | |
66 | #include "gem/i915_gem_context.h" |
67 | #include "gem/i915_gem_create.h" |
68 | #include "gem/i915_gem_dmabuf.h" |
69 | #include "gem/i915_gem_ioctls.h" |
70 | #include "gem/i915_gem_mman.h" |
71 | #include "gem/i915_gem_pm.h" |
72 | #include "gt/intel_gt.h" |
73 | #include "gt/intel_gt_pm.h" |
74 | #include "gt/intel_rc6.h" |
75 | |
76 | #include "pxp/intel_pxp_pm.h" |
77 | |
78 | #include "i915_file_private.h" |
79 | #include "i915_debugfs.h" |
80 | #include "i915_driver.h" |
81 | #include "i915_drm_client.h" |
82 | #include "i915_drv.h" |
83 | #include "i915_getparam.h" |
84 | #include "i915_ioc32.h" |
85 | #include "i915_ioctl.h" |
86 | #include "i915_irq.h" |
87 | #include "i915_memcpy.h" |
88 | #include "i915_perf.h" |
89 | #include "i915_query.h" |
90 | #include "i915_suspend.h" |
91 | #include "i915_switcheroo.h" |
92 | #include "i915_sysfs.h" |
93 | #include "i915_utils.h" |
94 | #include "i915_vgpu.h" |
95 | #include "intel_dram.h" |
96 | #include "intel_gvt.h" |
97 | #include "intel_memory_region.h" |
98 | #include "intel_pci_config.h" |
99 | #include "intel_pcode.h" |
100 | #include "intel_pm.h" |
101 | #include "intel_region_ttm.h" |
102 | #include "vlv_suspend.h" |
103 | |
104 | /* Intel Rapid Start Technology ACPI device name */ |
105 | static const char irst_name[] = "INT3392"; |
106 | |
107 | static const struct drm_driver i915_drm_driver; |
108 | |
109 | static void i915_release_bridge_dev(struct drm_device *dev, |
110 | void *bridge) |
111 | { |
112 | pci_dev_put(bridge); |
113 | } |
114 | |
115 | #ifdef __linux__ |
116 | static int i915_get_bridge_dev(struct drm_i915_privateinteldrm_softc *dev_priv) |
117 | { |
118 | int domain = pci_domain_nr(to_pci_dev(dev_priv->drm.dev)->bus); |
119 | |
120 | dev_priv->bridge_dev = |
121 | pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0)((0) << 3 | (0))); |
122 | if (!dev_priv->bridge_dev) { |
123 | drm_err(&dev_priv->drm, "bridge device not found\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "bridge device not found\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
124 | return -EIO5; |
125 | } |
126 | |
127 | return drmm_add_action_or_reset(&dev_priv->drm, i915_release_bridge_dev, |
128 | dev_priv->bridge_dev); |
129 | } |
130 | #else |
131 | int i915_get_bridge_dev(struct drm_i915_privateinteldrm_softc *dev_priv) |
132 | { |
133 | struct drm_device *dev = &dev_priv->drm; |
134 | |
135 | /* may be already called from attach */ |
136 | if (dev_priv->bridge_dev != NULL((void *)0)) |
137 | return 0; |
138 | |
139 | dev_priv->bridge_dev = malloc(sizeof(*dev_priv->bridge_dev), |
140 | M_DEVBUF2, M_WAITOK0x0001); |
141 | dev_priv->bridge_dev->pc = dev->pdev->pc; |
142 | dev_priv->bridge_dev->tag = pci_make_tag(dev->pdev->pc, 0, 0, 0); |
143 | return 0; |
144 | } |
145 | #endif |
146 | |
147 | /* Allocate space for the MCH regs if needed, return nonzero on error */ |
148 | static int |
149 | intel_alloc_mchbar_resource(struct drm_i915_privateinteldrm_softc *dev_priv) |
150 | { |
151 | int reg = GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) >= 4 ? MCHBAR_I9650x48 : MCHBAR_I9150x44; |
152 | u32 temp_lo, temp_hi = 0; |
153 | u64 mchbar_addr; |
154 | int ret; |
155 | |
156 | if (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) >= 4) |
157 | pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); |
158 | pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); |
159 | mchbar_addr = ((u64)temp_hi << 32) | temp_lo; |
160 | |
161 | /* If ACPI doesn't have it, assume we need to allocate it ourselves */ |
162 | #ifdef CONFIG_PNP |
163 | if (mchbar_addr && |
164 | pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE(4 * 4096))) |
165 | return 0; |
166 | #endif |
167 | |
168 | #ifdef __linux__ |
169 | /* Get some space for it */ |
170 | dev_priv->mch_res.name = "i915 MCHBAR"; |
171 | dev_priv->mch_res.flags = IORESOURCE_MEM0x0001; |
172 | ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, |
173 | &dev_priv->mch_res, |
174 | MCHBAR_SIZE(4 * 4096), MCHBAR_SIZE(4 * 4096), |
175 | PCIBIOS_MIN_MEM, |
176 | 0, pcibios_align_resource, |
177 | dev_priv->bridge_dev); |
178 | if (ret) { |
179 | drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "failed bus alloc: %d\n" , ret); |
180 | dev_priv->mch_res.start = 0; |
181 | return ret; |
182 | } |
183 | #else |
184 | if (dev_priv->memex == NULL((void *)0) || extent_alloc(dev_priv->memex,extent_alloc_subregion((dev_priv->memex), (dev_priv->memex )->ex_start, (dev_priv->memex)->ex_end, ((4 * 4096)) , ((4 * 4096)), (0), (0), (0), (&dev_priv->mch_res.start )) |
185 | MCHBAR_SIZE, MCHBAR_SIZE, 0, 0, 0, &dev_priv->mch_res.start)extent_alloc_subregion((dev_priv->memex), (dev_priv->memex )->ex_start, (dev_priv->memex)->ex_end, ((4 * 4096)) , ((4 * 4096)), (0), (0), (0), (&dev_priv->mch_res.start ))) { |
186 | return -ENOMEM12; |
187 | } |
188 | #endif |
189 | |
190 | if (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) >= 4) |
191 | pci_write_config_dword(dev_priv->bridge_dev, reg + 4, |
192 | upper_32_bits(dev_priv->mch_res.start)((u32)(((dev_priv->mch_res.start) >> 16) >> 16 ))); |
193 | |
194 | pci_write_config_dword(dev_priv->bridge_dev, reg, |
195 | lower_32_bits(dev_priv->mch_res.start)((u32)(dev_priv->mch_res.start))); |
196 | return 0; |
197 | } |
198 | |
199 | /* Setup MCHBAR if possible, return true if we should disable it again */ |
200 | static void |
201 | intel_setup_mchbar(struct drm_i915_privateinteldrm_softc *dev_priv) |
202 | { |
203 | int mchbar_reg = GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) >= 4 ? MCHBAR_I9650x48 : MCHBAR_I9150x44; |
204 | u32 temp; |
205 | bool_Bool enabled; |
206 | |
207 | if (IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) || IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
208 | return; |
209 | |
210 | dev_priv->mchbar_need_disable = false0; |
211 | |
212 | if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) { |
213 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN0x54, &temp); |
214 | enabled = !!(temp & DEVEN_MCHBAR_EN(1 << 28)); |
215 | } else { |
216 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
217 | enabled = temp & 1; |
218 | } |
219 | |
220 | /* If it's already enabled, don't have to do anything */ |
221 | if (enabled) |
222 | return; |
223 | |
224 | if (intel_alloc_mchbar_resource(dev_priv)) |
225 | return; |
226 | |
227 | dev_priv->mchbar_need_disable = true1; |
228 | |
229 | /* Space is allocated or reserved, so enable it. */ |
230 | if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) { |
231 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN0x54, |
232 | temp | DEVEN_MCHBAR_EN(1 << 28)); |
233 | } else { |
234 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp); |
235 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1); |
236 | } |
237 | } |
238 | |
239 | static void |
240 | intel_teardown_mchbar(struct drm_i915_privateinteldrm_softc *dev_priv) |
241 | { |
242 | int mchbar_reg = GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) >= 4 ? MCHBAR_I9650x48 : MCHBAR_I9150x44; |
243 | |
244 | if (dev_priv->mchbar_need_disable) { |
245 | if (IS_I915G(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915G) || IS_I915GM(dev_priv)IS_PLATFORM(dev_priv, INTEL_I915GM)) { |
246 | u32 deven_val; |
247 | |
248 | pci_read_config_dword(dev_priv->bridge_dev, DEVEN0x54, |
249 | &deven_val); |
250 | deven_val &= ~DEVEN_MCHBAR_EN(1 << 28); |
251 | pci_write_config_dword(dev_priv->bridge_dev, DEVEN0x54, |
252 | deven_val); |
253 | } else { |
254 | u32 mchbar_val; |
255 | |
256 | pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, |
257 | &mchbar_val); |
258 | mchbar_val &= ~1; |
259 | pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, |
260 | mchbar_val); |
261 | } |
262 | } |
263 | |
264 | if (dev_priv->mch_res.start) |
265 | #ifdef __linux__ |
266 | release_resource(&dev_priv->mch_res); |
267 | #else |
268 | extent_free(dev_priv->memex, dev_priv->mch_res.start, |
269 | MCHBAR_SIZE(4 * 4096), 0); |
270 | #endif |
271 | } |
272 | |
273 | static int i915_workqueues_init(struct drm_i915_privateinteldrm_softc *dev_priv) |
274 | { |
275 | /* |
276 | * The i915 workqueue is primarily used for batched retirement of |
277 | * requests (and thus managing bo) once the task has been completed |
278 | * by the GPU. i915_retire_requests() is called directly when we |
279 | * need high-priority retirement, such as waiting for an explicit |
280 | * bo. |
281 | * |
282 | * It is also used for periodic low-priority events, such as |
283 | * idle-timers and recording error state. |
284 | * |
285 | * All tasks on the workqueue are expected to acquire the dev mutex |
286 | * so there is no point in running more than one instance of the |
287 | * workqueue at any time. Use an ordered one. |
288 | */ |
289 | dev_priv->wq = alloc_ordered_workqueue("i915", 0); |
290 | if (dev_priv->wq == NULL((void *)0)) |
291 | goto out_err; |
292 | |
293 | dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0); |
294 | if (dev_priv->display.hotplug.dp_wq == NULL((void *)0)) |
295 | goto out_free_wq; |
296 | |
297 | return 0; |
298 | |
299 | out_free_wq: |
300 | destroy_workqueue(dev_priv->wq); |
301 | out_err: |
302 | drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to allocate workqueues.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
303 | |
304 | return -ENOMEM12; |
305 | } |
306 | |
307 | static void i915_workqueues_cleanup(struct drm_i915_privateinteldrm_softc *dev_priv) |
308 | { |
309 | destroy_workqueue(dev_priv->display.hotplug.dp_wq); |
310 | destroy_workqueue(dev_priv->wq); |
311 | } |
312 | |
313 | /* |
314 | * We don't keep the workarounds for pre-production hardware, so we expect our |
315 | * driver to fail on these machines in one way or another. A little warning on |
316 | * dmesg may help both the user and the bug triagers. |
317 | * |
318 | * Our policy for removing pre-production workarounds is to keep the |
319 | * current gen workarounds as a guide to the bring-up of the next gen |
320 | * (workarounds have a habit of persisting!). Anything older than that |
321 | * should be removed along with the complications they introduce. |
322 | */ |
323 | static void intel_detect_preproduction_hw(struct drm_i915_privateinteldrm_softc *dev_priv) |
324 | { |
325 | bool_Bool pre = false0; |
326 | |
327 | pre |= IS_HSW_EARLY_SDV(dev_priv)(IS_PLATFORM(dev_priv, INTEL_HASWELL) && (((&(dev_priv )->__runtime)->device_id) & 0xFF00) == 0x0C00); |
328 | pre |= IS_SKYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_SKYLAKE) && INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) < 0x6; |
329 | pre |= IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON) && INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) < 0xA; |
330 | pre |= IS_KABYLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_KABYLAKE) && INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) < 0x1; |
331 | pre |= IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) && INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) < 0x3; |
332 | pre |= IS_ICELAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ICELAKE) && INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision) < 0x7; |
333 | |
334 | if (pre) { |
335 | drm_err(&dev_priv->drm, "This is a pre-production stepping. "printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "This is a pre-production stepping. " "It may not be fully functional.\n", ({struct cpu_info *__ci ; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p-> ps_pid, __func__) |
336 | "It may not be fully functional.\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "This is a pre-production stepping. " "It may not be fully functional.\n", ({struct cpu_info *__ci ; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p-> ps_pid, __func__); |
337 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); |
338 | } |
339 | } |
340 | |
341 | static void sanitize_gpu(struct drm_i915_privateinteldrm_softc *i915) |
342 | { |
343 | if (!INTEL_INFO(i915)(&(i915)->__info)->gpu_reset_clobbers_display) { |
344 | struct intel_gt *gt; |
345 | unsigned int i; |
346 | |
347 | for_each_gt(gt, i915, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (i915)->gt[ (i)]))) {} else |
348 | __intel_gt_reset(gt, ALL_ENGINES((intel_engine_mask_t)~0ul)); |
349 | } |
350 | } |
351 | |
352 | /** |
353 | * i915_driver_early_probe - setup state not requiring device access |
354 | * @dev_priv: device private |
355 | * |
356 | * Initialize everything that is a "SW-only" state, that is state not |
357 | * requiring accessing the device or exposing the driver via kernel internal |
358 | * or userspace interfaces. Example steps belonging here: lock initialization, |
359 | * system memory allocation, setting up device specific attributes and |
360 | * function hooks not requiring accessing the device. |
361 | */ |
362 | static int i915_driver_early_probe(struct drm_i915_privateinteldrm_softc *dev_priv) |
363 | { |
364 | int ret = 0; |
365 | |
366 | if (i915_inject_probe_failure(dev_priv)({ ((void)0); 0; })) |
367 | return -ENODEV19; |
368 | |
369 | intel_device_info_subplatform_init(dev_priv); |
370 | intel_step_init(dev_priv); |
371 | |
372 | intel_uncore_mmio_debug_init_early(dev_priv); |
373 | |
374 | mtx_init(&dev_priv->irq_lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&dev_priv ->irq_lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9 ) ? 0x9 : ((0x9)))); } while (0); |
375 | mtx_init(&dev_priv->gpu_error.lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&dev_priv ->gpu_error.lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9) ? 0x9 : ((0x9)))); } while (0); |
376 | rw_init(&dev_priv->display.backlight.lock, "blight")_rw_init_flags(&dev_priv->display.backlight.lock, "blight" , 0, ((void *)0)); |
377 | |
378 | rw_init(&dev_priv->sb_lock, "sb")_rw_init_flags(&dev_priv->sb_lock, "sb", 0, ((void *)0 )); |
379 | cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE-1); |
380 | |
381 | rw_init(&dev_priv->display.audio.mutex, "daud")_rw_init_flags(&dev_priv->display.audio.mutex, "daud", 0, ((void *)0)); |
382 | rw_init(&dev_priv->display.wm.wm_mutex, "wmm")_rw_init_flags(&dev_priv->display.wm.wm_mutex, "wmm", 0 , ((void *)0)); |
383 | rw_init(&dev_priv->display.pps.mutex, "ppsm")_rw_init_flags(&dev_priv->display.pps.mutex, "ppsm", 0 , ((void *)0)); |
384 | rw_init(&dev_priv->display.hdcp.comp_mutex, "hdcpc")_rw_init_flags(&dev_priv->display.hdcp.comp_mutex, "hdcpc" , 0, ((void *)0)); |
385 | mtx_init(&dev_priv->display.dkl.phy_lock, IPL_NONE)do { (void)(((void *)0)); (void)(0); __mtx_init((&dev_priv ->display.dkl.phy_lock), ((((0x0)) > 0x0 && ((0x0 )) < 0x9) ? 0x9 : ((0x0)))); } while (0); |
386 | |
387 | i915_memcpy_init_early(dev_priv); |
388 | intel_runtime_pm_init_early(&dev_priv->runtime_pm); |
389 | |
390 | ret = i915_workqueues_init(dev_priv); |
391 | if (ret < 0) |
392 | return ret; |
393 | |
394 | ret = vlv_suspend_init(dev_priv); |
395 | if (ret < 0) |
396 | goto err_workqueues; |
397 | |
398 | ret = intel_region_ttm_device_init(dev_priv); |
399 | if (ret) |
400 | goto err_ttm; |
401 | |
402 | intel_wopcm_init_early(&dev_priv->wopcm); |
403 | |
404 | ret = intel_root_gt_init_early(dev_priv); |
405 | if (ret < 0) |
406 | goto err_rootgt; |
407 | |
408 | i915_drm_clients_init(&dev_priv->clients, dev_priv); |
409 | |
410 | i915_gem_init_early(dev_priv); |
411 | |
412 | /* This must be called before any calls to HAS_PCH_* */ |
413 | intel_detect_pch(dev_priv); |
414 | |
415 | intel_pm_setup(dev_priv); |
416 | ret = intel_power_domains_init(dev_priv); |
417 | if (ret < 0) |
418 | goto err_gem; |
419 | intel_irq_init(dev_priv); |
420 | intel_init_display_hooks(dev_priv); |
421 | intel_init_clock_gating_hooks(dev_priv); |
422 | |
423 | intel_detect_preproduction_hw(dev_priv); |
424 | |
425 | return 0; |
426 | |
427 | err_gem: |
428 | i915_gem_cleanup_early(dev_priv); |
429 | intel_gt_driver_late_release_all(dev_priv); |
430 | i915_drm_clients_fini(&dev_priv->clients); |
431 | err_rootgt: |
432 | intel_region_ttm_device_fini(dev_priv); |
433 | err_ttm: |
434 | vlv_suspend_cleanup(dev_priv); |
435 | err_workqueues: |
436 | i915_workqueues_cleanup(dev_priv); |
437 | return ret; |
438 | } |
439 | |
440 | /** |
441 | * i915_driver_late_release - cleanup the setup done in |
442 | * i915_driver_early_probe() |
443 | * @dev_priv: device private |
444 | */ |
445 | static void i915_driver_late_release(struct drm_i915_privateinteldrm_softc *dev_priv) |
446 | { |
447 | intel_irq_fini(dev_priv); |
448 | intel_power_domains_cleanup(dev_priv); |
449 | i915_gem_cleanup_early(dev_priv); |
450 | intel_gt_driver_late_release_all(dev_priv); |
451 | i915_drm_clients_fini(&dev_priv->clients); |
452 | intel_region_ttm_device_fini(dev_priv); |
453 | vlv_suspend_cleanup(dev_priv); |
454 | i915_workqueues_cleanup(dev_priv); |
455 | |
456 | cpu_latency_qos_remove_request(&dev_priv->sb_qos); |
457 | mutex_destroy(&dev_priv->sb_lock); |
458 | |
459 | i915_params_free(&dev_priv->params); |
460 | } |
461 | |
462 | /** |
463 | * i915_driver_mmio_probe - setup device MMIO |
464 | * @dev_priv: device private |
465 | * |
466 | * Setup minimal device state necessary for MMIO accesses later in the |
467 | * initialization sequence. The setup here should avoid any other device-wide |
468 | * side effects or exposing the driver via kernel internal or user space |
469 | * interfaces. |
470 | */ |
471 | static int i915_driver_mmio_probe(struct drm_i915_privateinteldrm_softc *dev_priv) |
472 | { |
473 | struct intel_gt *gt; |
474 | int ret, i; |
475 | |
476 | if (i915_inject_probe_failure(dev_priv)({ ((void)0); 0; })) |
477 | return -ENODEV19; |
478 | |
479 | ret = i915_get_bridge_dev(dev_priv); |
480 | if (ret < 0) |
481 | return ret; |
482 | |
483 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else { |
484 | ret = intel_uncore_init_mmio(gt->uncore); |
485 | if (ret) |
486 | return ret; |
487 | |
488 | ret = drmm_add_action_or_reset(&dev_priv->drm, |
489 | intel_uncore_fini_mmio, |
490 | gt->uncore); |
491 | if (ret) |
492 | return ret; |
493 | } |
494 | |
495 | /* Try to make sure MCHBAR is enabled before poking at it */ |
496 | intel_setup_mchbar(dev_priv); |
497 | intel_device_info_runtime_init(dev_priv); |
498 | |
499 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else { |
500 | ret = intel_gt_init_mmio(gt); |
501 | if (ret) |
502 | goto err_uncore; |
503 | } |
504 | |
505 | /* As early as possible, scrub existing GPU state before clobbering */ |
506 | sanitize_gpu(dev_priv); |
507 | |
508 | return 0; |
509 | |
510 | err_uncore: |
511 | intel_teardown_mchbar(dev_priv); |
512 | |
513 | return ret; |
514 | } |
515 | |
516 | /** |
517 | * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe() |
518 | * @dev_priv: device private |
519 | */ |
520 | static void i915_driver_mmio_release(struct drm_i915_privateinteldrm_softc *dev_priv) |
521 | { |
522 | intel_teardown_mchbar(dev_priv); |
523 | } |
524 | |
525 | /** |
526 | * i915_set_dma_info - set all relevant PCI dma info as configured for the |
527 | * platform |
528 | * @i915: valid i915 instance |
529 | * |
530 | * Set the dma max segment size, device and coherent masks. The dma mask set |
531 | * needs to occur before i915_ggtt_probe_hw. |
532 | * |
533 | * A couple of platforms have special needs. Address them as well. |
534 | * |
535 | */ |
536 | static int i915_set_dma_info(struct drm_i915_privateinteldrm_softc *i915) |
537 | { |
538 | unsigned int mask_size = INTEL_INFO(i915)(&(i915)->__info)->dma_mask_size; |
539 | int ret; |
540 | |
541 | GEM_BUG_ON(!mask_size)((void)0); |
542 | |
543 | /* |
544 | * We don't have a max segment size, so set it to the max so sg's |
545 | * debugging layer doesn't complain |
546 | */ |
547 | dma_set_max_seg_size(i915->drm.dev, UINT_MAX0xffffffffU); |
548 | |
549 | ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)(((mask_size) == 64) ? ~0ULL : (1ULL<<(mask_size)) -1)); |
550 | if (ret) |
551 | goto mask_err; |
552 | |
553 | /* overlay on gen2 is broken and can't address above 1G */ |
554 | if (GRAPHICS_VER(i915)((&(i915)->__runtime)->graphics.ip.ver) == 2) |
555 | mask_size = 30; |
556 | |
557 | /* |
558 | * 965GM sometimes incorrectly writes to hardware status page (HWS) |
559 | * using 32bit addressing, overwriting memory if HWS is located |
560 | * above 4GB. |
561 | * |
562 | * The documentation also mentions an issue with undefined |
563 | * behaviour if any general state is accessed within a page above 4GB, |
564 | * which also needs to be handled carefully. |
565 | */ |
566 | if (IS_I965G(i915)IS_PLATFORM(i915, INTEL_I965G) || IS_I965GM(i915)IS_PLATFORM(i915, INTEL_I965GM)) |
567 | mask_size = 32; |
568 | |
569 | ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size)(((mask_size) == 64) ? ~0ULL : (1ULL<<(mask_size)) -1)); |
570 | if (ret) |
571 | goto mask_err; |
572 | |
573 | return 0; |
574 | |
575 | mask_err: |
576 | drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Can't set DMA mask/consistent mask (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
577 | return ret; |
578 | } |
579 | |
580 | static int i915_pcode_init(struct drm_i915_privateinteldrm_softc *i915) |
581 | { |
582 | struct intel_gt *gt; |
583 | int id, ret; |
584 | |
585 | for_each_gt(gt, i915, id)for ((id) = 0; (id) < 4; (id)++) if (!(((gt) = (i915)-> gt[(id)]))) {} else { |
586 | ret = intel_pcode_init(gt->uncore); |
587 | if (ret) { |
588 | drm_err(>->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "gt%d: intel_pcode_init failed %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , id, ret ); |
589 | return ret; |
590 | } |
591 | } |
592 | |
593 | return 0; |
594 | } |
595 | |
596 | /** |
597 | * i915_driver_hw_probe - setup state requiring device access |
598 | * @dev_priv: device private |
599 | * |
600 | * Setup state that requires accessing the device, but doesn't require |
601 | * exposing the driver via kernel internal or userspace interfaces. |
602 | */ |
603 | static int i915_driver_hw_probe(struct drm_i915_privateinteldrm_softc *dev_priv) |
604 | { |
605 | struct pci_dev *pdev = dev_priv->drm.pdev; |
606 | int ret; |
607 | |
608 | if (i915_inject_probe_failure(dev_priv)({ ((void)0); 0; })) |
609 | return -ENODEV19; |
610 | |
611 | if (HAS_PPGTT(dev_priv)(((&(dev_priv)->__runtime)->ppgtt_type) != INTEL_PPGTT_NONE )) { |
612 | if (intel_vgpu_active(dev_priv) && |
613 | !intel_vgpu_has_full_ppgtt(dev_priv)) { |
614 | i915_report_error(dev_priv,__i915_printk(dev_priv, "\0013", "incompatible vGPU found, support for isolated ppGTT required\n" ) |
615 | "incompatible vGPU found, support for isolated ppGTT required\n")__i915_printk(dev_priv, "\0013", "incompatible vGPU found, support for isolated ppGTT required\n" ); |
616 | return -ENXIO6; |
617 | } |
618 | } |
619 | |
620 | if (HAS_EXECLISTS(dev_priv)((&(dev_priv)->__info)->has_logical_ring_contexts)) { |
621 | /* |
622 | * Older GVT emulation depends upon intercepting CSB mmio, |
623 | * which we no longer use, preferring to use the HWSP cache |
624 | * instead. |
625 | */ |
626 | if (intel_vgpu_active(dev_priv) && |
627 | !intel_vgpu_has_hwsp_emulation(dev_priv)) { |
628 | i915_report_error(dev_priv,__i915_printk(dev_priv, "\0013", "old vGPU host found, support for HWSP emulation required\n" ) |
629 | "old vGPU host found, support for HWSP emulation required\n")__i915_printk(dev_priv, "\0013", "old vGPU host found, support for HWSP emulation required\n" ); |
630 | return -ENXIO6; |
631 | } |
632 | } |
633 | |
634 | /* needs to be done before ggtt probe */ |
635 | intel_dram_edram_detect(dev_priv); |
636 | |
637 | ret = i915_set_dma_info(dev_priv); |
638 | if (ret) |
639 | return ret; |
640 | |
641 | i915_perf_init(dev_priv); |
642 | |
643 | ret = intel_gt_assign_ggtt(to_gt(dev_priv)); |
644 | if (ret) |
645 | goto err_perf; |
646 | |
647 | ret = i915_ggtt_probe_hw(dev_priv); |
648 | if (ret) |
649 | goto err_perf; |
650 | |
651 | ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver); |
652 | if (ret) |
653 | goto err_ggtt; |
654 | |
655 | ret = i915_ggtt_init_hw(dev_priv); |
656 | if (ret) |
657 | goto err_ggtt; |
658 | |
659 | ret = intel_memory_regions_hw_probe(dev_priv); |
660 | if (ret) |
661 | goto err_ggtt; |
662 | |
663 | ret = intel_gt_tiles_init(dev_priv); |
664 | if (ret) |
665 | goto err_mem_regions; |
666 | |
667 | ret = i915_ggtt_enable_hw(dev_priv); |
668 | if (ret) { |
669 | drm_err(&dev_priv->drm, "failed to enable GGTT\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to enable GGTT\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
670 | goto err_mem_regions; |
671 | } |
672 | |
673 | pci_set_master(pdev); |
674 | |
675 | /* On the 945G/GM, the chipset reports the MSI capability on the |
676 | * integrated graphics even though the support isn't actually there |
677 | * according to the published specs. It doesn't appear to function |
678 | * correctly in testing on 945G. |
679 | * This may be a side effect of MSI having been made available for PEG |
680 | * and the registers being closely associated. |
681 | * |
682 | * According to chipset errata, on the 965GM, MSI interrupts may |
683 | * be lost or delayed, and was defeatured. MSI interrupts seem to |
684 | * get lost on g4x as well, and interrupt delivery seems to stay |
685 | * properly dead afterwards. So we'll just disable them for all |
686 | * pre-gen5 chipsets. |
687 | * |
688 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy |
689 | * interrupts even when in MSI mode. This results in spurious |
690 | * interrupt warnings if the legacy irq no. is shared with another |
691 | * device. The kernel then disables that interrupt source and so |
692 | * prevents the other device from working properly. |
693 | */ |
694 | if (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) >= 5) { |
695 | if (pci_enable_msi(pdev) < 0) |
696 | drm_dbg(&dev_priv->drm, "can't enable MSI")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "can't enable MSI" ); |
697 | } |
698 | |
699 | ret = intel_gvt_init(dev_priv); |
700 | if (ret) |
701 | goto err_msi; |
702 | |
703 | intel_opregion_setup(dev_priv); |
704 | |
705 | ret = i915_pcode_init(dev_priv); |
706 | if (ret) |
707 | goto err_msi; |
708 | |
709 | /* |
710 | * Fill the dram structure to get the system dram info. This will be |
711 | * used for memory latency calculation. |
712 | */ |
713 | intel_dram_detect(dev_priv); |
714 | |
715 | intel_bw_init_hw(dev_priv); |
716 | |
717 | return 0; |
718 | |
719 | err_msi: |
720 | if (pdev->msi_enabled) |
721 | pci_disable_msi(pdev); |
722 | err_mem_regions: |
723 | intel_memory_regions_driver_release(dev_priv); |
724 | err_ggtt: |
725 | i915_ggtt_driver_release(dev_priv); |
726 | i915_gem_drain_freed_objects(dev_priv); |
727 | i915_ggtt_driver_late_release(dev_priv); |
728 | err_perf: |
729 | i915_perf_fini(dev_priv); |
730 | return ret; |
731 | } |
732 | |
733 | /** |
734 | * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe() |
735 | * @dev_priv: device private |
736 | */ |
737 | static void i915_driver_hw_remove(struct drm_i915_privateinteldrm_softc *dev_priv) |
738 | { |
739 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
740 | #ifdef notyet |
741 | struct pci_dev *pdev = dev_priv->drm.pdev; |
742 | |
743 | i915_perf_fini(dev_priv); |
744 | |
745 | if (pdev->msi_enabled) |
746 | pci_disable_msi(pdev); |
747 | #endif |
748 | } |
749 | |
750 | /** |
751 | * i915_driver_register - register the driver with the rest of the system |
752 | * @dev_priv: device private |
753 | * |
754 | * Perform any steps necessary to make the driver available via kernel |
755 | * internal or userspace interfaces. |
756 | */ |
757 | static void i915_driver_register(struct drm_i915_privateinteldrm_softc *dev_priv) |
758 | { |
759 | struct drm_device *dev = &dev_priv->drm; |
760 | struct intel_gt *gt; |
761 | unsigned int i; |
762 | |
763 | i915_gem_driver_register(dev_priv); |
764 | i915_pmu_register(dev_priv); |
765 | |
766 | intel_vgpu_register(dev_priv); |
767 | |
768 | /* Reveal our presence to userspace */ |
769 | if (drm_dev_register(dev, 0)) { |
770 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register driver for userspace access!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
771 | "Failed to register driver for userspace access!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register driver for userspace access!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
772 | return; |
773 | } |
774 | |
775 | i915_debugfs_register(dev_priv); |
776 | i915_setup_sysfs(dev_priv); |
777 | |
778 | /* Depends on sysfs having been initialized */ |
779 | i915_perf_register(dev_priv); |
780 | |
781 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
782 | intel_gt_driver_register(gt); |
783 | |
784 | intel_display_driver_register(dev_priv); |
785 | |
786 | intel_power_domains_enable(dev_priv); |
787 | intel_runtime_pm_enable(&dev_priv->runtime_pm); |
788 | |
789 | intel_register_dsm_handler(); |
790 | |
791 | if (i915_switcheroo_register(dev_priv)) |
792 | drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to register vga switcheroo!\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
793 | } |
794 | |
795 | /** |
796 | * i915_driver_unregister - cleanup the registration done in i915_driver_regiser() |
797 | * @dev_priv: device private |
798 | */ |
799 | static void i915_driver_unregister(struct drm_i915_privateinteldrm_softc *dev_priv) |
800 | { |
801 | struct intel_gt *gt; |
802 | unsigned int i; |
803 | |
804 | i915_switcheroo_unregister(dev_priv); |
805 | |
806 | intel_unregister_dsm_handler(); |
807 | |
808 | intel_runtime_pm_disable(&dev_priv->runtime_pm); |
809 | intel_power_domains_disable(dev_priv); |
810 | |
811 | intel_display_driver_unregister(dev_priv); |
812 | |
813 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
814 | intel_gt_driver_unregister(gt); |
815 | |
816 | i915_perf_unregister(dev_priv); |
817 | i915_pmu_unregister(dev_priv); |
818 | |
819 | i915_teardown_sysfs(dev_priv); |
820 | drm_dev_unplug(&dev_priv->drm); |
821 | |
822 | i915_gem_driver_unregister(dev_priv); |
823 | } |
824 | |
825 | void |
826 | i915_print_iommu_status(struct drm_i915_privateinteldrm_softc *i915, struct drm_printer *p) |
827 | { |
828 | drm_printf(p, "iommu: %s\n", |
829 | str_enabled_disabled(i915_vtd_active(i915))); |
830 | } |
831 | |
832 | static void i915_welcome_messages(struct drm_i915_privateinteldrm_softc *dev_priv) |
833 | { |
834 | if (drm_debug_enabled(DRM_UT_DRIVER)drm_debug_enabled_raw(DRM_UT_DRIVER)) { |
835 | struct drm_printer p = drm_debug_printer("i915 device info:"); |
836 | struct intel_gt *gt; |
837 | unsigned int i; |
838 | |
839 | drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n", |
840 | INTEL_DEVID(dev_priv)((&(dev_priv)->__runtime)->device_id), |
841 | INTEL_REVID(dev_priv)((dev_priv)->drm.pdev->revision), |
842 | intel_platform_name(INTEL_INFO(dev_priv)(&(dev_priv)->__info)->platform), |
843 | intel_subplatform(RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime), |
844 | INTEL_INFO(dev_priv)(&(dev_priv)->__info)->platform), |
845 | GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver)); |
846 | |
847 | intel_device_info_print(INTEL_INFO(dev_priv)(&(dev_priv)->__info), |
848 | RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime), &p); |
849 | i915_print_iommu_status(dev_priv, &p); |
850 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
851 | intel_gt_info_print(>->info, &p); |
852 | } |
853 | |
854 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG)0) |
855 | drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n")do { } while(0); |
856 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)0) |
857 | drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n")do { } while(0); |
858 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)0) |
859 | drm_info(&dev_priv->drm,do { } while(0) |
860 | "DRM_I915_DEBUG_RUNTIME_PM enabled\n")do { } while(0); |
861 | } |
862 | |
863 | #ifdef __linux__ |
864 | |
865 | static struct drm_i915_privateinteldrm_softc * |
866 | i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent) |
867 | { |
868 | const struct intel_device_info *match_info = |
869 | (struct intel_device_info *)ent->driver_data; |
870 | struct intel_device_info *device_info; |
871 | struct intel_runtime_info *runtime; |
872 | struct drm_i915_privateinteldrm_softc *i915; |
873 | |
874 | i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,((struct inteldrm_softc *) __devm_drm_dev_alloc(&pdev-> dev, &i915_drm_driver, sizeof(struct inteldrm_softc), __builtin_offsetof (struct inteldrm_softc, drm))) |
875 | struct drm_i915_private, drm)((struct inteldrm_softc *) __devm_drm_dev_alloc(&pdev-> dev, &i915_drm_driver, sizeof(struct inteldrm_softc), __builtin_offsetof (struct inteldrm_softc, drm))); |
876 | if (IS_ERR(i915)) |
877 | return i915; |
878 | |
879 | pci_set_drvdata(pdev, i915); |
880 | |
881 | /* Device parameters start as a copy of module parameters. */ |
882 | i915_params_copy(&i915->params, &i915_modparams); |
883 | |
884 | /* Setup the write-once "constant" device info */ |
885 | device_info = mkwrite_device_info(i915); |
886 | memcpy(device_info, match_info, sizeof(*device_info))__builtin_memcpy((device_info), (match_info), (sizeof(*device_info ))); |
887 | |
888 | /* Initialize initial runtime info from static const data and pdev. */ |
889 | runtime = RUNTIME_INFO(i915)(&(i915)->__runtime); |
890 | memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime))__builtin_memcpy((runtime), (&(&(i915)->__info)-> __runtime), (sizeof(*runtime))); |
891 | runtime->device_id = pdev->device; |
892 | |
893 | return i915; |
894 | } |
895 | |
896 | /** |
897 | * i915_driver_probe - setup chip and create an initial config |
898 | * @pdev: PCI device |
899 | * @ent: matching PCI ID entry |
900 | * |
901 | * The driver probe routine has to do several things: |
902 | * - drive output discovery via intel_modeset_init() |
903 | * - initialize the memory manager |
904 | * - allocate initial config memory |
905 | * - setup the DRM framebuffer with the allocated memory |
906 | */ |
907 | int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
908 | { |
909 | struct drm_i915_privateinteldrm_softc *i915; |
910 | int ret; |
911 | |
912 | i915 = i915_driver_create(pdev, ent); |
913 | if (IS_ERR(i915)) |
914 | return PTR_ERR(i915); |
915 | |
916 | /* Disable nuclear pageflip by default on pre-ILK */ |
917 | if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) < 5) |
918 | i915->drm.driver_features &= ~DRIVER_ATOMIC; |
919 | |
920 | ret = pci_enable_device(pdev); |
921 | if (ret) |
922 | goto out_fini; |
923 | |
924 | ret = i915_driver_early_probe(i915); |
925 | if (ret < 0) |
926 | goto out_pci_disable; |
927 | |
928 | disable_rpm_wakeref_asserts(&i915->runtime_pm); |
929 | |
930 | intel_vgpu_detect(i915); |
931 | |
932 | ret = intel_gt_probe_all(i915); |
933 | if (ret < 0) |
934 | goto out_runtime_pm_put; |
935 | |
936 | ret = i915_driver_mmio_probe(i915); |
937 | if (ret < 0) |
938 | goto out_runtime_pm_put; |
939 | |
940 | ret = i915_driver_hw_probe(i915); |
941 | if (ret < 0) |
942 | goto out_cleanup_mmio; |
943 | |
944 | ret = intel_modeset_init_noirq(i915); |
945 | if (ret < 0) |
946 | goto out_cleanup_hw; |
947 | |
948 | ret = intel_irq_install(i915); |
949 | if (ret) |
950 | goto out_cleanup_modeset; |
951 | |
952 | ret = intel_modeset_init_nogem(i915); |
953 | if (ret) |
954 | goto out_cleanup_irq; |
955 | |
956 | ret = i915_gem_init(i915); |
957 | if (ret) |
958 | goto out_cleanup_modeset2; |
959 | |
960 | ret = intel_modeset_init(i915); |
961 | if (ret) |
962 | goto out_cleanup_gem; |
963 | |
964 | i915_driver_register(i915); |
965 | |
966 | enable_rpm_wakeref_asserts(&i915->runtime_pm); |
967 | |
968 | i915_welcome_messages(i915); |
969 | |
970 | i915->do_release = true1; |
971 | |
972 | return 0; |
973 | |
974 | out_cleanup_gem: |
975 | i915_gem_suspend(i915); |
976 | i915_gem_driver_remove(i915); |
977 | i915_gem_driver_release(i915); |
978 | out_cleanup_modeset2: |
979 | /* FIXME clean up the error path */ |
980 | intel_modeset_driver_remove(i915); |
981 | intel_irq_uninstall(i915); |
982 | intel_modeset_driver_remove_noirq(i915); |
983 | goto out_cleanup_modeset; |
984 | out_cleanup_irq: |
985 | intel_irq_uninstall(i915); |
986 | out_cleanup_modeset: |
987 | intel_modeset_driver_remove_nogem(i915); |
988 | out_cleanup_hw: |
989 | i915_driver_hw_remove(i915); |
990 | intel_memory_regions_driver_release(i915); |
991 | i915_ggtt_driver_release(i915); |
992 | i915_gem_drain_freed_objects(i915); |
993 | i915_ggtt_driver_late_release(i915); |
994 | out_cleanup_mmio: |
995 | i915_driver_mmio_release(i915); |
996 | out_runtime_pm_put: |
997 | enable_rpm_wakeref_asserts(&i915->runtime_pm); |
998 | i915_driver_late_release(i915); |
999 | out_pci_disable: |
1000 | pci_disable_device(pdev); |
1001 | out_fini: |
1002 | i915_probe_error(i915, "Device initialization failed (%d)\n", ret)__i915_printk(i915, 0 ? "\0017" : "\0013", "Device initialization failed (%d)\n" , ret); |
1003 | return ret; |
1004 | } |
1005 | |
1006 | #else /* !__linux__ */ |
1007 | |
1008 | void inteldrm_init_backlight(struct inteldrm_softc *); |
1009 | |
1010 | /** |
1011 | * i915_driver_probe - setup chip and create an initial config |
1012 | * @pdev: PCI device |
1013 | * @ent: matching PCI ID entry |
1014 | * |
1015 | * The driver probe routine has to do several things: |
1016 | * - drive output discovery via intel_modeset_init() |
1017 | * - initialize the memory manager |
1018 | * - allocate initial config memory |
1019 | * - setup the DRM framebuffer with the allocated memory |
1020 | */ |
1021 | int i915_driver_probe(struct drm_i915_privateinteldrm_softc *i915, const struct pci_device_id *ent) |
1022 | { |
1023 | struct pci_dev *pdev = i915->drm.pdev; |
1024 | int ret; |
1025 | |
1026 | /* Disable nuclear pageflip by default on pre-ILK */ |
1027 | if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) < 5) |
1028 | i915->drm.driver_features &= ~DRIVER_ATOMIC; |
1029 | |
1030 | ret = pci_enable_device(pdev); |
1031 | if (ret) |
1032 | goto out_fini; |
1033 | |
1034 | ret = i915_driver_early_probe(i915); |
1035 | if (ret < 0) |
1036 | goto out_pci_disable; |
1037 | |
1038 | disable_rpm_wakeref_asserts(&i915->runtime_pm); |
1039 | |
1040 | intel_vgpu_detect(i915); |
1041 | |
1042 | ret = intel_gt_probe_all(i915); |
1043 | if (ret < 0) |
1044 | goto out_runtime_pm_put; |
1045 | |
1046 | ret = i915_driver_mmio_probe(i915); |
1047 | if (ret < 0) |
1048 | goto out_runtime_pm_put; |
1049 | |
1050 | ret = i915_driver_hw_probe(i915); |
1051 | if (ret < 0) |
1052 | goto out_cleanup_mmio; |
1053 | |
1054 | ret = intel_modeset_init_noirq(i915); |
1055 | if (ret < 0) |
1056 | goto out_cleanup_hw; |
1057 | |
1058 | ret = intel_irq_install(i915); |
1059 | if (ret) |
1060 | goto out_cleanup_modeset; |
1061 | |
1062 | ret = intel_modeset_init_nogem(i915); |
1063 | if (ret) |
1064 | goto out_cleanup_irq; |
1065 | |
1066 | ret = i915_gem_init(i915); |
1067 | if (ret) |
1068 | goto out_cleanup_modeset2; |
1069 | |
1070 | ret = intel_modeset_init(i915); |
1071 | if (ret) |
1072 | goto out_cleanup_gem; |
1073 | |
1074 | i915_driver_register(i915); |
1075 | |
1076 | inteldrm_init_backlight(i915); |
1077 | |
1078 | enable_rpm_wakeref_asserts(&i915->runtime_pm); |
1079 | |
1080 | i915_welcome_messages(i915); |
1081 | |
1082 | i915->do_release = true1; |
1083 | |
1084 | return 0; |
1085 | |
1086 | out_cleanup_gem: |
1087 | i915_gem_suspend(i915); |
1088 | i915_gem_driver_remove(i915); |
1089 | i915_gem_driver_release(i915); |
1090 | out_cleanup_modeset2: |
1091 | /* FIXME clean up the error path */ |
1092 | intel_modeset_driver_remove(i915); |
1093 | intel_irq_uninstall(i915); |
1094 | intel_modeset_driver_remove_noirq(i915); |
1095 | goto out_cleanup_modeset; |
1096 | out_cleanup_irq: |
1097 | intel_irq_uninstall(i915); |
1098 | out_cleanup_modeset: |
1099 | intel_modeset_driver_remove_nogem(i915); |
1100 | out_cleanup_hw: |
1101 | i915_driver_hw_remove(i915); |
1102 | intel_memory_regions_driver_release(i915); |
1103 | i915_ggtt_driver_release(i915); |
1104 | i915_gem_drain_freed_objects(i915); |
1105 | i915_ggtt_driver_late_release(i915); |
1106 | out_cleanup_mmio: |
1107 | i915_driver_mmio_release(i915); |
1108 | out_runtime_pm_put: |
1109 | enable_rpm_wakeref_asserts(&i915->runtime_pm); |
1110 | i915_driver_late_release(i915); |
1111 | out_pci_disable: |
1112 | pci_disable_device(pdev); |
1113 | out_fini: |
1114 | i915_probe_error(i915, "Device initialization failed (%d)\n", ret)__i915_printk(i915, 0 ? "\0017" : "\0013", "Device initialization failed (%d)\n" , ret); |
1115 | return ret; |
1116 | } |
1117 | |
1118 | #endif |
1119 | |
1120 | void i915_driver_remove(struct drm_i915_privateinteldrm_softc *i915) |
1121 | { |
1122 | intel_wakeref_t wakeref; |
1123 | |
1124 | wakeref = intel_runtime_pm_get(&i915->runtime_pm); |
1125 | |
1126 | i915_driver_unregister(i915); |
1127 | |
1128 | /* Flush any external code that still may be under the RCU lock */ |
1129 | synchronize_rcu(); |
1130 | |
1131 | i915_gem_suspend(i915); |
1132 | |
1133 | intel_gvt_driver_remove(i915); |
1134 | |
1135 | intel_modeset_driver_remove(i915); |
1136 | |
1137 | intel_irq_uninstall(i915); |
1138 | |
1139 | intel_modeset_driver_remove_noirq(i915); |
1140 | |
1141 | i915_reset_error_state(i915); |
1142 | i915_gem_driver_remove(i915); |
1143 | |
1144 | intel_modeset_driver_remove_nogem(i915); |
1145 | |
1146 | i915_driver_hw_remove(i915); |
1147 | |
1148 | intel_runtime_pm_put(&i915->runtime_pm, wakeref); |
1149 | } |
1150 | |
1151 | static void i915_driver_release(struct drm_device *dev) |
1152 | { |
1153 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
1154 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1155 | intel_wakeref_t wakeref; |
1156 | |
1157 | if (!dev_priv->do_release) |
1158 | return; |
1159 | |
1160 | wakeref = intel_runtime_pm_get(rpm); |
1161 | |
1162 | i915_gem_driver_release(dev_priv); |
1163 | |
1164 | intel_memory_regions_driver_release(dev_priv); |
1165 | i915_ggtt_driver_release(dev_priv); |
1166 | i915_gem_drain_freed_objects(dev_priv); |
1167 | i915_ggtt_driver_late_release(dev_priv); |
1168 | |
1169 | i915_driver_mmio_release(dev_priv); |
1170 | |
1171 | intel_runtime_pm_put(rpm, wakeref); |
1172 | |
1173 | intel_runtime_pm_driver_release(rpm); |
1174 | |
1175 | i915_driver_late_release(dev_priv); |
1176 | } |
1177 | |
1178 | static int i915_driver_open(struct drm_device *dev, struct drm_file *file) |
1179 | { |
1180 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(dev); |
1181 | int ret; |
1182 | |
1183 | ret = i915_gem_open(i915, file); |
1184 | if (ret) |
1185 | return ret; |
1186 | |
1187 | return 0; |
1188 | } |
1189 | |
1190 | /** |
1191 | * i915_driver_lastclose - clean up after all DRM clients have exited |
1192 | * @dev: DRM device |
1193 | * |
1194 | * Take care of cleaning up after all DRM clients have exited. In the |
1195 | * mode setting case, we want to restore the kernel's initial mode (just |
1196 | * in case the last client left us in a bad state). |
1197 | * |
1198 | * Additionally, in the non-mode setting case, we'll tear down the GTT |
1199 | * and DMA structures, since the kernel won't be using them, and clea |
1200 | * up any GEM state. |
1201 | */ |
1202 | static void i915_driver_lastclose(struct drm_device *dev) |
1203 | { |
1204 | intel_fbdev_restore_mode(dev); |
1205 | |
1206 | vga_switcheroo_process_delayed_switch(); |
1207 | } |
1208 | |
1209 | static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) |
1210 | { |
1211 | struct drm_i915_file_private *file_priv = file->driver_priv; |
1212 | |
1213 | i915_gem_context_close(file); |
1214 | i915_drm_client_put(file_priv->client); |
1215 | |
1216 | kfree_rcu(file_priv, rcu)do { free((void *)file_priv, 145, 0); } while(0); |
1217 | |
1218 | /* Catch up with all the deferred frees from "this" client */ |
1219 | i915_gem_flush_free_objects(to_i915(dev)); |
1220 | } |
1221 | |
1222 | static void intel_suspend_encoders(struct drm_i915_privateinteldrm_softc *dev_priv) |
1223 | { |
1224 | struct drm_device *dev = &dev_priv->drm; |
1225 | struct intel_encoder *encoder; |
1226 | |
1227 | if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0)) |
1228 | return; |
1229 | |
1230 | drm_modeset_lock_all(dev); |
1231 | for_each_intel_encoder(dev, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );}); &encoder->base.head != (&(dev)->mode_config.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->base.head ) *__mptr = (encoder->base.head.next); (__typeof(*encoder) *)( (char * )__mptr - __builtin_offsetof(__typeof(*encoder), base.head) ) ;})) |
1232 | if (encoder->suspend) |
1233 | encoder->suspend(encoder); |
1234 | drm_modeset_unlock_all(dev); |
1235 | } |
1236 | |
1237 | static void intel_shutdown_encoders(struct drm_i915_privateinteldrm_softc *dev_priv) |
1238 | { |
1239 | struct drm_device *dev = &dev_priv->drm; |
1240 | struct intel_encoder *encoder; |
1241 | |
1242 | if (!HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0)) |
1243 | return; |
1244 | |
1245 | drm_modeset_lock_all(dev); |
1246 | for_each_intel_encoder(dev, encoder)for (encoder = ({ const __typeof( ((__typeof(*encoder) *)0)-> base.head ) *__mptr = ((&(dev)->mode_config.encoder_list )->next); (__typeof(*encoder) *)( (char *)__mptr - __builtin_offsetof (__typeof(*encoder), base.head) );}); &encoder->base.head != (&(dev)->mode_config.encoder_list); encoder = ({ const __typeof( ((__typeof(*encoder) *)0)->base.head ) *__mptr = (encoder->base.head.next); (__typeof(*encoder) *)( (char * )__mptr - __builtin_offsetof(__typeof(*encoder), base.head) ) ;})) |
1247 | if (encoder->shutdown) |
1248 | encoder->shutdown(encoder); |
1249 | drm_modeset_unlock_all(dev); |
1250 | } |
1251 | |
1252 | void i915_driver_shutdown(struct drm_i915_privateinteldrm_softc *i915) |
1253 | { |
1254 | disable_rpm_wakeref_asserts(&i915->runtime_pm); |
1255 | intel_runtime_pm_disable(&i915->runtime_pm); |
1256 | intel_power_domains_disable(i915); |
1257 | |
1258 | if (HAS_DISPLAY(i915)((&(i915)->__runtime)->pipe_mask != 0)) { |
1259 | drm_kms_helper_poll_disable(&i915->drm); |
1260 | |
1261 | drm_atomic_helper_shutdown(&i915->drm); |
1262 | } |
1263 | |
1264 | intel_dp_mst_suspend(i915); |
1265 | |
1266 | intel_runtime_pm_disable_interrupts(i915); |
1267 | intel_hpd_cancel_work(i915); |
1268 | |
1269 | intel_suspend_encoders(i915); |
1270 | intel_shutdown_encoders(i915); |
1271 | |
1272 | intel_dmc_ucode_suspend(i915); |
1273 | |
1274 | i915_gem_suspend(i915); |
1275 | |
1276 | /* |
1277 | * The only requirement is to reboot with display DC states disabled, |
1278 | * for now leaving all display power wells in the INIT power domain |
1279 | * enabled. |
1280 | * |
1281 | * TODO: |
1282 | * - unify the pci_driver::shutdown sequence here with the |
1283 | * pci_driver.driver.pm.poweroff,poweroff_late sequence. |
1284 | * - unify the driver remove and system/runtime suspend sequences with |
1285 | * the above unified shutdown/poweroff sequence. |
1286 | */ |
1287 | intel_power_domains_driver_remove(i915); |
1288 | enable_rpm_wakeref_asserts(&i915->runtime_pm); |
1289 | |
1290 | intel_runtime_pm_driver_release(&i915->runtime_pm); |
1291 | } |
1292 | |
1293 | static bool_Bool suspend_to_idle(struct drm_i915_privateinteldrm_softc *dev_priv) |
1294 | { |
1295 | #if IS_ENABLED(CONFIG_ACPI_SLEEP)0 |
1296 | if (acpi_target_system_state() < ACPI_STATE_S33) |
1297 | return true1; |
1298 | #endif |
1299 | return false0; |
1300 | } |
1301 | |
1302 | static int i915_drm_prepare(struct drm_device *dev) |
1303 | { |
1304 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(dev); |
1305 | |
1306 | /* |
1307 | * NB intel_display_suspend() may issue new requests after we've |
1308 | * ostensibly marked the GPU as ready-to-sleep here. We need to |
1309 | * split out that work and pull it forward so that after point, |
1310 | * the GPU is not woken again. |
1311 | */ |
1312 | return i915_gem_backup_suspend(i915); |
1313 | } |
1314 | |
1315 | static int i915_drm_suspend(struct drm_device *dev) |
1316 | { |
1317 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
1318 | struct pci_dev *pdev = dev_priv->drm.pdev; |
1319 | pci_power_t opregion_target_state; |
1320 | |
1321 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1322 | |
1323 | /* We do a lot of poking in a lot of registers, make sure they work |
1324 | * properly. */ |
1325 | intel_power_domains_disable(dev_priv); |
1326 | if (HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0)) |
1327 | drm_kms_helper_poll_disable(dev); |
1328 | |
1329 | pci_save_state(pdev); |
1330 | |
1331 | intel_display_suspend(dev); |
1332 | |
1333 | intel_dp_mst_suspend(dev_priv); |
1334 | |
1335 | intel_runtime_pm_disable_interrupts(dev_priv); |
1336 | intel_hpd_cancel_work(dev_priv); |
1337 | |
1338 | intel_suspend_encoders(dev_priv); |
1339 | |
1340 | intel_suspend_hw(dev_priv); |
1341 | |
1342 | /* Must be called before GGTT is suspended. */ |
1343 | intel_dpt_suspend(dev_priv); |
1344 | i915_ggtt_suspend(to_gt(dev_priv)->ggtt); |
1345 | |
1346 | i915_save_display(dev_priv); |
1347 | |
1348 | opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; |
1349 | intel_opregion_suspend(dev_priv, opregion_target_state); |
1350 | |
1351 | intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED1, true1); |
1352 | |
1353 | dev_priv->suspend_count++; |
1354 | |
1355 | intel_dmc_ucode_suspend(dev_priv); |
1356 | |
1357 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1358 | |
1359 | i915_gem_drain_freed_objects(dev_priv); |
1360 | |
1361 | return 0; |
1362 | } |
1363 | |
1364 | static enum i915_drm_suspend_mode |
1365 | get_suspend_mode(struct drm_i915_privateinteldrm_softc *dev_priv, bool_Bool hibernate) |
1366 | { |
1367 | if (hibernate) |
1368 | return I915_DRM_SUSPEND_HIBERNATE; |
1369 | |
1370 | if (suspend_to_idle(dev_priv)) |
1371 | return I915_DRM_SUSPEND_IDLE; |
1372 | |
1373 | return I915_DRM_SUSPEND_MEM; |
1374 | } |
1375 | |
1376 | static int i915_drm_suspend_late(struct drm_device *dev, bool_Bool hibernation) |
1377 | { |
1378 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
1379 | struct pci_dev *pdev = dev_priv->drm.pdev; |
1380 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1381 | struct intel_gt *gt; |
1382 | int ret, i; |
1383 | |
1384 | disable_rpm_wakeref_asserts(rpm); |
1385 | |
1386 | i915_gem_suspend_late(dev_priv); |
1387 | |
1388 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
1389 | intel_uncore_suspend(gt->uncore); |
1390 | |
1391 | intel_power_domains_suspend(dev_priv, |
1392 | get_suspend_mode(dev_priv, hibernation)); |
1393 | |
1394 | intel_display_power_suspend_late(dev_priv); |
1395 | |
1396 | ret = vlv_suspend_complete(dev_priv); |
1397 | if (ret) { |
1398 | drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Suspend complete failed: %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
1399 | intel_power_domains_resume(dev_priv); |
1400 | |
1401 | goto out; |
1402 | } |
1403 | |
1404 | pci_disable_device(pdev); |
1405 | /* |
1406 | * During hibernation on some platforms the BIOS may try to access |
1407 | * the device even though it's already in D3 and hang the machine. So |
1408 | * leave the device in D0 on those platforms and hope the BIOS will |
1409 | * power down the device properly. The issue was seen on multiple old |
1410 | * GENs with different BIOS vendors, so having an explicit blacklist |
1411 | * is inpractical; apply the workaround on everything pre GEN6. The |
1412 | * platforms where the issue was seen: |
1413 | * Lenovo Thinkpad X301, X61s, X60, T60, X41 |
1414 | * Fujitsu FSC S7110 |
1415 | * Acer Aspire 1830T |
1416 | */ |
1417 | if (!(hibernation && GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) < 6)) |
1418 | pci_set_power_state(pdev, PCI_D3hot); |
1419 | |
1420 | out: |
1421 | enable_rpm_wakeref_asserts(rpm); |
1422 | if (!dev_priv->uncore.user_forcewake_count) |
1423 | intel_runtime_pm_driver_release(rpm); |
1424 | |
1425 | return ret; |
1426 | } |
1427 | |
1428 | #ifdef __linux__ |
1429 | int i915_driver_suspend_switcheroo(struct drm_i915_privateinteldrm_softc *i915, |
1430 | pm_message_t state) |
1431 | { |
1432 | int error; |
1433 | |
1434 | if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&({ static int __warned; int __ret = !!((state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& i915->drm))->dev), "", "drm_WARN_ON_ONCE(" "state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); }) |
1435 | state.event != PM_EVENT_FREEZE)({ static int __warned; int __ret = !!((state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& i915->drm))->dev), "", "drm_WARN_ON_ONCE(" "state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1436 | return -EINVAL22; |
1437 | |
1438 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1439 | return 0; |
1440 | |
1441 | error = i915_drm_suspend(&i915->drm); |
1442 | if (error) |
1443 | return error; |
1444 | |
1445 | return i915_drm_suspend_late(&i915->drm, false0); |
1446 | } |
1447 | #endif |
1448 | |
1449 | static int i915_drm_resume(struct drm_device *dev) |
1450 | { |
1451 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
1452 | int ret; |
1453 | |
1454 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1455 | |
1456 | ret = i915_pcode_init(dev_priv); |
1457 | if (ret) |
1458 | return ret; |
1459 | |
1460 | sanitize_gpu(dev_priv); |
1461 | |
1462 | ret = i915_ggtt_enable_hw(dev_priv); |
1463 | if (ret) |
1464 | drm_err(&dev_priv->drm, "failed to re-enable GGTT\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to re-enable GGTT\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1465 | |
1466 | i915_ggtt_resume(to_gt(dev_priv)->ggtt); |
1467 | /* Must be called after GGTT is resumed. */ |
1468 | intel_dpt_resume(dev_priv); |
1469 | |
1470 | intel_dmc_ucode_resume(dev_priv); |
1471 | |
1472 | i915_restore_display(dev_priv); |
1473 | intel_pps_unlock_regs_wa(dev_priv); |
1474 | |
1475 | intel_init_pch_refclk(dev_priv); |
1476 | |
1477 | /* |
1478 | * Interrupts have to be enabled before any batches are run. If not the |
1479 | * GPU will hang. i915_gem_init_hw() will initiate batches to |
1480 | * update/restore the context. |
1481 | * |
1482 | * drm_mode_config_reset() needs AUX interrupts. |
1483 | * |
1484 | * Modeset enabling in intel_modeset_init_hw() also needs working |
1485 | * interrupts. |
1486 | */ |
1487 | intel_runtime_pm_enable_interrupts(dev_priv); |
1488 | |
1489 | if (HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0)) |
1490 | drm_mode_config_reset(dev); |
1491 | |
1492 | i915_gem_resume(dev_priv); |
1493 | |
1494 | intel_modeset_init_hw(dev_priv); |
1495 | intel_init_clock_gating(dev_priv); |
1496 | intel_hpd_init(dev_priv); |
1497 | |
1498 | /* MST sideband requires HPD interrupts enabled */ |
1499 | intel_dp_mst_resume(dev_priv); |
1500 | intel_display_resume(dev); |
1501 | |
1502 | intel_hpd_poll_disable(dev_priv); |
1503 | if (HAS_DISPLAY(dev_priv)((&(dev_priv)->__runtime)->pipe_mask != 0)) |
1504 | drm_kms_helper_poll_enable(dev); |
1505 | |
1506 | intel_opregion_resume(dev_priv); |
1507 | |
1508 | intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING0, false0); |
1509 | |
1510 | intel_power_domains_enable(dev_priv); |
1511 | |
1512 | intel_gvt_resume(dev_priv); |
1513 | |
1514 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1515 | |
1516 | return 0; |
1517 | } |
1518 | |
1519 | static int i915_drm_resume_early(struct drm_device *dev) |
1520 | { |
1521 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
1522 | struct pci_dev *pdev = dev_priv->drm.pdev; |
1523 | struct intel_gt *gt; |
1524 | int ret, i; |
1525 | |
1526 | /* |
1527 | * We have a resume ordering issue with the snd-hda driver also |
1528 | * requiring our device to be power up. Due to the lack of a |
1529 | * parent/child relationship we currently solve this with an early |
1530 | * resume hook. |
1531 | * |
1532 | * FIXME: This should be solved with a special hdmi sink device or |
1533 | * similar so that power domains can be employed. |
1534 | */ |
1535 | |
1536 | /* |
1537 | * Note that we need to set the power state explicitly, since we |
1538 | * powered off the device during freeze and the PCI core won't power |
1539 | * it back up for us during thaw. Powering off the device during |
1540 | * freeze is not a hard requirement though, and during the |
1541 | * suspend/resume phases the PCI core makes sure we get here with the |
1542 | * device powered on. So in case we change our freeze logic and keep |
1543 | * the device powered we can also remove the following set power state |
1544 | * call. |
1545 | */ |
1546 | ret = pci_set_power_state(pdev, PCI_D0); |
1547 | if (ret) { |
1548 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to set PCI D0 power state (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
1549 | "failed to set PCI D0 power state (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "failed to set PCI D0 power state (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
1550 | return ret; |
1551 | } |
1552 | |
1553 | /* |
1554 | * Note that pci_enable_device() first enables any parent bridge |
1555 | * device and only then sets the power state for this device. The |
1556 | * bridge enabling is a nop though, since bridge devices are resumed |
1557 | * first. The order of enabling power and enabling the device is |
1558 | * imposed by the PCI core as described above, so here we preserve the |
1559 | * same order for the freeze/thaw phases. |
1560 | * |
1561 | * TODO: eventually we should remove pci_disable_device() / |
1562 | * pci_enable_enable_device() from suspend/resume. Due to how they |
1563 | * depend on the device enable refcount we can't anyway depend on them |
1564 | * disabling/enabling the device. |
1565 | */ |
1566 | if (pci_enable_device(pdev)) |
1567 | return -EIO5; |
1568 | |
1569 | pci_set_master(pdev); |
1570 | |
1571 | disable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1572 | |
1573 | ret = vlv_resume_prepare(dev_priv, false0); |
1574 | if (ret) |
1575 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Resume prepare failed: %d, continuing anyway\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
1576 | "Resume prepare failed: %d, continuing anyway\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Resume prepare failed: %d, continuing anyway\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
1577 | |
1578 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else { |
1579 | intel_uncore_resume_early(gt->uncore); |
1580 | intel_gt_check_and_clear_faults(gt); |
1581 | } |
1582 | |
1583 | intel_display_power_resume_early(dev_priv); |
1584 | |
1585 | intel_power_domains_resume(dev_priv); |
1586 | |
1587 | enable_rpm_wakeref_asserts(&dev_priv->runtime_pm); |
1588 | |
1589 | return ret; |
1590 | } |
1591 | |
1592 | int i915_driver_resume_switcheroo(struct drm_i915_privateinteldrm_softc *i915) |
1593 | { |
1594 | int ret; |
1595 | |
1596 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1597 | return 0; |
1598 | |
1599 | ret = i915_drm_resume_early(&i915->drm); |
1600 | if (ret) |
1601 | return ret; |
1602 | |
1603 | return i915_drm_resume(&i915->drm); |
1604 | } |
1605 | |
1606 | #ifdef __linux__ |
1607 | |
1608 | static int i915_pm_prepare(struct device *kdev) |
1609 | { |
1610 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1611 | |
1612 | if (!i915) { |
1613 | dev_err(kdev, "DRM not initialized, aborting suspend.\n")printf("drm:pid%d:%s *ERROR* " "DRM not initialized, aborting suspend.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1614 | return -ENODEV19; |
1615 | } |
1616 | |
1617 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1618 | return 0; |
1619 | |
1620 | return i915_drm_prepare(&i915->drm); |
1621 | } |
1622 | |
1623 | static int i915_pm_suspend(struct device *kdev) |
1624 | { |
1625 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1626 | |
1627 | if (!i915) { |
1628 | dev_err(kdev, "DRM not initialized, aborting suspend.\n")printf("drm:pid%d:%s *ERROR* " "DRM not initialized, aborting suspend.\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1629 | return -ENODEV19; |
1630 | } |
1631 | |
1632 | i915_ggtt_mark_pte_lost(i915, false0); |
1633 | |
1634 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1635 | return 0; |
1636 | |
1637 | return i915_drm_suspend(&i915->drm); |
1638 | } |
1639 | |
1640 | static int i915_pm_suspend_late(struct device *kdev) |
1641 | { |
1642 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1643 | |
1644 | /* |
1645 | * We have a suspend ordering issue with the snd-hda driver also |
1646 | * requiring our device to be power up. Due to the lack of a |
1647 | * parent/child relationship we currently solve this with an late |
1648 | * suspend hook. |
1649 | * |
1650 | * FIXME: This should be solved with a special hdmi sink device or |
1651 | * similar so that power domains can be employed. |
1652 | */ |
1653 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1654 | return 0; |
1655 | |
1656 | return i915_drm_suspend_late(&i915->drm, false0); |
1657 | } |
1658 | |
1659 | static int i915_pm_poweroff_late(struct device *kdev) |
1660 | { |
1661 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1662 | |
1663 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1664 | return 0; |
1665 | |
1666 | return i915_drm_suspend_late(&i915->drm, true1); |
1667 | } |
1668 | |
1669 | static int i915_pm_resume_early(struct device *kdev) |
1670 | { |
1671 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1672 | |
1673 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1674 | return 0; |
1675 | |
1676 | return i915_drm_resume_early(&i915->drm); |
1677 | } |
1678 | |
1679 | static int i915_pm_resume(struct device *kdev) |
1680 | { |
1681 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1682 | |
1683 | if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF) |
1684 | return 0; |
1685 | |
1686 | /* |
1687 | * If IRST is enabled, or if we can't detect whether it's enabled, |
1688 | * then we must assume we lost the GGTT page table entries, since |
1689 | * they are not retained if IRST decided to enter S4. |
1690 | */ |
1691 | #ifdef notyet |
1692 | if (!IS_ENABLED(CONFIG_ACPI)1 || acpi_dev_present(irst_name, NULL((void *)0), -1)) |
1693 | i915_ggtt_mark_pte_lost(i915, true1); |
1694 | #else |
1695 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
1696 | #endif |
1697 | |
1698 | return i915_drm_resume(&i915->drm); |
1699 | } |
1700 | |
1701 | /* freeze: before creating the hibernation_image */ |
1702 | static int i915_pm_freeze(struct device *kdev) |
1703 | { |
1704 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1705 | int ret; |
1706 | |
1707 | if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { |
1708 | ret = i915_drm_suspend(&i915->drm); |
1709 | if (ret) |
1710 | return ret; |
1711 | } |
1712 | |
1713 | ret = i915_gem_freeze(i915); |
1714 | if (ret) |
1715 | return ret; |
1716 | |
1717 | return 0; |
1718 | } |
1719 | |
1720 | static int i915_pm_freeze_late(struct device *kdev) |
1721 | { |
1722 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1723 | int ret; |
1724 | |
1725 | if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) { |
1726 | ret = i915_drm_suspend_late(&i915->drm, true1); |
1727 | if (ret) |
1728 | return ret; |
1729 | } |
1730 | |
1731 | ret = i915_gem_freeze_late(i915); |
1732 | if (ret) |
1733 | return ret; |
1734 | |
1735 | return 0; |
1736 | } |
1737 | |
1738 | /* thaw: called after creating the hibernation image, but before turning off. */ |
1739 | static int i915_pm_thaw_early(struct device *kdev) |
1740 | { |
1741 | return i915_pm_resume_early(kdev); |
1742 | } |
1743 | |
1744 | static int i915_pm_thaw(struct device *kdev) |
1745 | { |
1746 | return i915_pm_resume(kdev); |
1747 | } |
1748 | |
1749 | /* restore: called after loading the hibernation image. */ |
1750 | static int i915_pm_restore_early(struct device *kdev) |
1751 | { |
1752 | return i915_pm_resume_early(kdev); |
1753 | } |
1754 | |
1755 | static int i915_pm_restore(struct device *kdev) |
1756 | { |
1757 | struct drm_i915_privateinteldrm_softc *i915 = kdev_to_i915(kdev); |
1758 | |
1759 | i915_ggtt_mark_pte_lost(i915, true1); |
1760 | return i915_pm_resume(kdev); |
1761 | } |
1762 | |
1763 | static int intel_runtime_suspend(struct device *kdev) |
1764 | { |
1765 | struct drm_i915_privateinteldrm_softc *dev_priv = kdev_to_i915(kdev); |
1766 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1767 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1768 | struct pci_dev *root_pdev; |
1769 | struct intel_gt *gt; |
1770 | int ret, i; |
1771 | |
1772 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))({ static int __warned; int __ret = !!((!((&(dev_priv)-> __info)->has_runtime_pm))); if (__ret && !__warned ) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON_ONCE(" "!((&(dev_priv)->__info)->has_runtime_pm)" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1773 | return -ENODEV19; |
1774 | |
1775 | drm_dbg(&dev_priv->drm, "Suspending device\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Suspending device\n" ); |
1776 | |
1777 | disable_rpm_wakeref_asserts(rpm); |
1778 | |
1779 | /* |
1780 | * We are safe here against re-faults, since the fault handler takes |
1781 | * an RPM reference. |
1782 | */ |
1783 | i915_gem_runtime_suspend(dev_priv); |
1784 | |
1785 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
1786 | intel_gt_runtime_suspend(gt); |
1787 | |
1788 | intel_runtime_pm_disable_interrupts(dev_priv); |
1789 | |
1790 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
1791 | intel_uncore_suspend(gt->uncore); |
1792 | |
1793 | intel_display_power_suspend(dev_priv); |
1794 | |
1795 | ret = vlv_suspend_complete(dev_priv); |
1796 | if (ret) { |
1797 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime suspend failed, disabling it (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
1798 | "Runtime suspend failed, disabling it (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime suspend failed, disabling it (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
1799 | intel_uncore_runtime_resume(&dev_priv->uncore); |
1800 | |
1801 | intel_runtime_pm_enable_interrupts(dev_priv); |
1802 | |
1803 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
1804 | intel_gt_runtime_resume(gt); |
1805 | |
1806 | enable_rpm_wakeref_asserts(rpm); |
1807 | |
1808 | return ret; |
1809 | } |
1810 | |
1811 | enable_rpm_wakeref_asserts(rpm); |
1812 | intel_runtime_pm_driver_release(rpm); |
1813 | |
1814 | if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore)) |
1815 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unclaimed access detected prior to suspending\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
1816 | "Unclaimed access detected prior to suspending\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Unclaimed access detected prior to suspending\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
1817 | |
1818 | /* |
1819 | * FIXME: Temporary hammer to avoid freezing the machine on our DGFX |
1820 | * This should be totally removed when we handle the pci states properly |
1821 | * on runtime PM. |
1822 | */ |
1823 | root_pdev = pcie_find_root_port(pdev); |
1824 | if (root_pdev) |
1825 | pci_d3cold_disable(root_pdev); |
1826 | |
1827 | rpm->suspended = true1; |
1828 | |
1829 | /* |
1830 | * FIXME: We really should find a document that references the arguments |
1831 | * used below! |
1832 | */ |
1833 | if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL)) { |
1834 | /* |
1835 | * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop |
1836 | * being detected, and the call we do at intel_runtime_resume() |
1837 | * won't be able to restore them. Since PCI_D3hot matches the |
1838 | * actual specification and appears to be working, use it. |
1839 | */ |
1840 | intel_opregion_notify_adapter(dev_priv, PCI_D3hot); |
1841 | } else { |
1842 | /* |
1843 | * current versions of firmware which depend on this opregion |
1844 | * notification have repurposed the D1 definition to mean |
1845 | * "runtime suspended" vs. what you would normally expect (D3) |
1846 | * to distinguish it from notifications that might be sent via |
1847 | * the suspend path. |
1848 | */ |
1849 | intel_opregion_notify_adapter(dev_priv, PCI_D1); |
1850 | } |
1851 | |
1852 | assert_forcewakes_inactive(&dev_priv->uncore); |
1853 | |
1854 | if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) |
1855 | intel_hpd_poll_enable(dev_priv); |
1856 | |
1857 | drm_dbg(&dev_priv->drm, "Device suspended\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Device suspended\n" ); |
1858 | return 0; |
1859 | } |
1860 | |
1861 | static int intel_runtime_resume(struct device *kdev) |
1862 | { |
1863 | struct drm_i915_privateinteldrm_softc *dev_priv = kdev_to_i915(kdev); |
1864 | struct intel_runtime_pm *rpm = &dev_priv->runtime_pm; |
1865 | struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); |
1866 | struct pci_dev *root_pdev; |
1867 | struct intel_gt *gt; |
1868 | int ret, i; |
1869 | |
1870 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv))({ static int __warned; int __ret = !!((!((&(dev_priv)-> __info)->has_runtime_pm))); if (__ret && !__warned ) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON_ONCE(" "!((&(dev_priv)->__info)->has_runtime_pm)" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1871 | return -ENODEV19; |
1872 | |
1873 | drm_dbg(&dev_priv->drm, "Resuming device\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Resuming device\n" ); |
1874 | |
1875 | drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count))({ static int __warned; int __ret = !!((({ typeof(*(&rpm-> wakeref_count)) __tmp = *(volatile typeof(*(&rpm->wakeref_count )) *)&(*(&rpm->wakeref_count)); membar_datadep_consumer (); __tmp; }))); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON_ONCE(" "({ typeof(*(&rpm->wakeref_count)) __tmp = *(volatile typeof(*(&rpm->wakeref_count)) *)&(*(&rpm->wakeref_count)); membar_datadep_consumer(); __tmp; })" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); }); |
1876 | disable_rpm_wakeref_asserts(rpm); |
1877 | |
1878 | intel_opregion_notify_adapter(dev_priv, PCI_D0); |
1879 | rpm->suspended = false0; |
1880 | |
1881 | root_pdev = pcie_find_root_port(pdev); |
1882 | if (root_pdev) |
1883 | pci_d3cold_enable(root_pdev); |
1884 | |
1885 | if (intel_uncore_unclaimed_mmio(&dev_priv->uncore)) |
1886 | drm_dbg(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Unclaimed access during suspend, bios?\n" ) |
1887 | "Unclaimed access during suspend, bios?\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Unclaimed access during suspend, bios?\n" ); |
1888 | |
1889 | intel_display_power_resume(dev_priv); |
1890 | |
1891 | ret = vlv_resume_prepare(dev_priv, true1); |
1892 | |
1893 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
1894 | intel_uncore_runtime_resume(gt->uncore); |
1895 | |
1896 | intel_runtime_pm_enable_interrupts(dev_priv); |
1897 | |
1898 | /* |
1899 | * No point of rolling back things in case of an error, as the best |
1900 | * we can do is to hope that things will still work (and disable RPM). |
1901 | */ |
1902 | for_each_gt(gt, dev_priv, i)for ((i) = 0; (i) < 4; (i)++) if (!(((gt) = (dev_priv)-> gt[(i)]))) {} else |
1903 | intel_gt_runtime_resume(gt); |
1904 | |
1905 | /* |
1906 | * On VLV/CHV display interrupts are part of the display |
1907 | * power well, so hpd is reinitialized from there. For |
1908 | * everyone else do it here. |
1909 | */ |
1910 | if (!IS_VALLEYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) && !IS_CHERRYVIEW(dev_priv)IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)) { |
1911 | intel_hpd_init(dev_priv); |
1912 | intel_hpd_poll_disable(dev_priv); |
1913 | } |
1914 | |
1915 | skl_watermark_ipc_update(dev_priv); |
1916 | |
1917 | enable_rpm_wakeref_asserts(rpm); |
1918 | |
1919 | if (ret) |
1920 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime resume failed, disabling it (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
1921 | "Runtime resume failed, disabling it (%d)\n", ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Runtime resume failed, disabling it (%d)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
1922 | else |
1923 | drm_dbg(&dev_priv->drm, "Device resumed\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_DRIVER, "Device resumed\n" ); |
1924 | |
1925 | return ret; |
1926 | } |
1927 | |
1928 | const struct dev_pm_ops i915_pm_ops = { |
1929 | /* |
1930 | * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND, |
1931 | * PMSG_RESUME] |
1932 | */ |
1933 | .prepare = i915_pm_prepare, |
1934 | .suspend = i915_pm_suspend, |
1935 | .suspend_late = i915_pm_suspend_late, |
1936 | .resume_early = i915_pm_resume_early, |
1937 | .resume = i915_pm_resume, |
1938 | |
1939 | /* |
1940 | * S4 event handlers |
1941 | * @freeze, @freeze_late : called (1) before creating the |
1942 | * hibernation image [PMSG_FREEZE] and |
1943 | * (2) after rebooting, before restoring |
1944 | * the image [PMSG_QUIESCE] |
1945 | * @thaw, @thaw_early : called (1) after creating the hibernation |
1946 | * image, before writing it [PMSG_THAW] |
1947 | * and (2) after failing to create or |
1948 | * restore the image [PMSG_RECOVER] |
1949 | * @poweroff, @poweroff_late: called after writing the hibernation |
1950 | * image, before rebooting [PMSG_HIBERNATE] |
1951 | * @restore, @restore_early : called after rebooting and restoring the |
1952 | * hibernation image [PMSG_RESTORE] |
1953 | */ |
1954 | .freeze = i915_pm_freeze, |
1955 | .freeze_late = i915_pm_freeze_late, |
1956 | .thaw_early = i915_pm_thaw_early, |
1957 | .thaw = i915_pm_thaw, |
1958 | .poweroff = i915_pm_suspend, |
1959 | .poweroff_late = i915_pm_poweroff_late, |
1960 | .restore_early = i915_pm_restore_early, |
1961 | .restore = i915_pm_restore, |
1962 | |
1963 | /* S0ix (via runtime suspend) event handlers */ |
1964 | .runtime_suspend = intel_runtime_suspend, |
1965 | .runtime_resume = intel_runtime_resume, |
1966 | }; |
1967 | |
1968 | static const struct file_operations i915_driver_fops = { |
1969 | .owner = THIS_MODULE((void *)0), |
1970 | .open = drm_open, |
1971 | .release = drm_release_noglobal, |
1972 | .unlocked_ioctl = drm_ioctl, |
1973 | .mmap = i915_gem_mmap, |
1974 | .poll = drm_poll, |
1975 | .read = drm_read, |
1976 | .compat_ioctl = i915_ioc32_compat_ioctl((void *)0), |
1977 | .llseek = noop_llseek, |
1978 | #ifdef CONFIG_PROC_FS |
1979 | .show_fdinfo = i915_drm_client_fdinfo, |
1980 | #endif |
1981 | }; |
1982 | |
1983 | #endif /* __linux__ */ |
1984 | |
1985 | static int |
1986 | i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data, |
1987 | struct drm_file *file) |
1988 | { |
1989 | return -ENODEV19; |
1990 | } |
1991 | |
1992 | static const struct drm_ioctl_desc i915_ioctls[] = { |
1993 | DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_init_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x00) ))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_init_t) & 0x1fff) << 16) | ((( 'd')) << 8) | ((0x40 + 0x00))), .func = drm_noop, .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_INIT" }, |
1994 | DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x01)))) & 0xff) - 0x40 ] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x01))), .func = drm_noop , .flags = DRM_AUTH, .name = "I915_FLUSH" }, |
1995 | DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x02)))) & 0xff) - 0x40 ] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x02))), .func = drm_noop , .flags = DRM_AUTH, .name = "I915_FLIP" }, |
1996 | DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_batchbuffer_t ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x03)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_batchbuffer_t) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x03))), .func = drm_noop , .flags = DRM_AUTH, .name = "I915_BATCHBUFFER" }, |
1997 | DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(drm_i915_irq_emit_t) & 0x1fff) << 16) | ((( 'd')) << 8) | ((0x40 + 0x04)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(drm_i915_irq_emit_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x04))), .func = drm_noop, . flags = DRM_AUTH, .name = "I915_IRQ_EMIT" }, |
1998 | DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_irq_wait_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x05)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_irq_wait_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x05))), .func = drm_noop, . flags = DRM_AUTH, .name = "I915_IRQ_WAIT" }, |
1999 | DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(drm_i915_getparam_t) & 0x1fff) << 16) | ((( 'd')) << 8) | ((0x40 + 0x06)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(drm_i915_getparam_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x06))), .func = i915_getparam_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GETPARAM" }, |
2000 | DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_setparam_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x07)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_setparam_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x07))), .func = drm_noop, . flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_SETPARAM" }, |
2001 | DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(drm_i915_mem_alloc_t) & 0x1fff) << 16) | (( ('d')) << 8) | ((0x40 + 0x08)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(drm_i915_mem_alloc_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x08))), .func = drm_noop, .flags = DRM_AUTH, .name = "I915_ALLOC" }, |
2002 | DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_free_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x09)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_free_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x09))), .func = drm_noop, . flags = DRM_AUTH, .name = "I915_FREE" }, |
2003 | DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_init_heap_t ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0a)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_init_heap_t) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x0a))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_INIT_HEAP" }, |
2004 | DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_cmdbuffer_t ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0b)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_cmdbuffer_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0b))), .func = drm_noop, . flags = DRM_AUTH, .name = "I915_CMDBUFFER" }, |
2005 | DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_destroy_heap_t ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0c)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_mem_destroy_heap_t) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0c))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_DESTROY_HEAP" }, |
2006 | DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(drm_i915_vblank_pipe_t ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0d)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(drm_i915_vblank_pipe_t) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x0d))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_SET_VBLANK_PIPE" }, |
2007 | DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH)[((((unsigned long)0x40000000 | ((sizeof(drm_i915_vblank_pipe_t ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x0e)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x40000000 | ((sizeof(drm_i915_vblank_pipe_t) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x0e))), .func = drm_noop , .flags = DRM_AUTH, .name = "I915_GET_VBLANK_PIPE" }, |
2008 | DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(drm_i915_vblank_swap_t) & 0x1fff) << 16) | ( (('d')) << 8) | ((0x40 + 0x0f)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(drm_i915_vblank_swap_t) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x0f))), .func = drm_noop , .flags = DRM_AUTH, .name = "I915_VBLANK_SWAP" }, |
2009 | DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_init ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x11)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_init) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x11))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_HWS_ADDR" }, |
2010 | DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_init ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x13)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_init) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x13))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_GEM_INIT" }, |
2011 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_execbuffer ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x14)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_execbuffer) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x14))), .func = drm_invalid_op , .flags = DRM_AUTH, .name = "I915_GEM_EXECBUFFER" }, |
2012 | DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_execbuffer2) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x29)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_execbuffer2) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x29) )), .func = i915_gem_execbuffer2_ioctl, .flags = DRM_RENDER_ALLOW , .name = "I915_GEM_EXECBUFFER2_WR" }, |
2013 | DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_pin) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x15)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_pin) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x15))), .func = i915_gem_reject_pin_ioctl , .flags = DRM_AUTH|DRM_ROOT_ONLY, .name = "I915_GEM_PIN" }, |
2014 | DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_unpin ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x16)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_unpin) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x16))), .func = i915_gem_reject_pin_ioctl , .flags = DRM_AUTH|DRM_ROOT_ONLY, .name = "I915_GEM_UNPIN" }, |
2015 | DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_busy) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x17)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_busy) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x17))), .func = i915_gem_busy_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_BUSY" }, |
2016 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_caching ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2f)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_caching) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2f))), .func = i915_gem_set_caching_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SET_CACHING" }, |
2017 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_caching) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x30)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_caching) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x30))), .func = i915_gem_get_caching_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_GET_CACHING" }, |
2018 | DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x18)))) & 0xff) - 0x40 ] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x18))), .func = i915_gem_throttle_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_THROTTLE" }, |
2019 | DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x19)))) & 0xff) - 0x40 ] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x19))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_GEM_ENTERVT" }, |
2020 | DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY)[((((unsigned long)0x20000000 | ((0 & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x1a)))) & 0xff) - 0x40 ] = { .cmd = ((unsigned long)0x20000000 | ((0 & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1a))), .func = drm_noop , .flags = DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY, .name = "I915_GEM_LEAVEVT" }, |
2021 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_create) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x1b)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_create) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1b))), .func = i915_gem_create_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_CREATE" }, |
2022 | DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_create_ext) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x3c)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_create_ext) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x3c))), .func = i915_gem_create_ext_ioctl, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_CREATE_EXT" }, |
2023 | DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_pread ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1c)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_pread) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1c))), .func = i915_gem_pread_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_PREAD" }, |
2024 | DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_pwrite ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1d)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_pwrite) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1d))), .func = i915_gem_pwrite_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_PWRITE" }, |
2025 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_mmap) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1e)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_mmap) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1e))), .func = i915_gem_mmap_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_MMAP" }, |
2026 | DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_mmap_offset) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x24)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_mmap_offset) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x24) )), .func = i915_gem_mmap_offset_ioctl, .flags = DRM_RENDER_ALLOW , .name = "I915_GEM_MMAP_OFFSET" }, |
2027 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_set_domain ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1f)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_set_domain) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x1f))), .func = i915_gem_set_domain_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SET_DOMAIN" }, |
2028 | DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_sw_finish ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x20)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_sw_finish) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x20))), .func = i915_gem_sw_finish_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SW_FINISH" }, |
2029 | DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_set_tiling) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x21)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_set_tiling) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x21))), .func = i915_gem_set_tiling_ioctl, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_SET_TILING" }, |
2030 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_get_tiling) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x22)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_get_tiling) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x22))), .func = i915_gem_get_tiling_ioctl, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_GET_TILING" }, |
2031 | DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x40000000 | ((sizeof(struct drm_i915_gem_get_aperture ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x23)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x40000000 | ((sizeof(struct drm_i915_gem_get_aperture) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x23))), .func = i915_gem_get_aperture_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_GET_APERTURE" }, |
2032 | DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_get_pipe_from_crtc_id) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x25)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_get_pipe_from_crtc_id) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x25))), .func = intel_get_pipe_from_crtc_id_ioctl, .flags = 0, .name = "I915_GET_PIPE_FROM_CRTC_ID" }, |
2033 | DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_madvise) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x26)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_madvise) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x26))), .func = i915_gem_madvise_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_MADVISE" }, |
2034 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER)[((((unsigned long)0x80000000 | ((sizeof(struct drm_intel_overlay_put_image ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x27)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_intel_overlay_put_image) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x27))), .func = intel_overlay_put_image_ioctl, .flags = DRM_MASTER, .name = "I915_OVERLAY_PUT_IMAGE" }, |
2035 | DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_intel_overlay_attrs) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x28)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_intel_overlay_attrs) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x28))), .func = intel_overlay_attrs_ioctl, .flags = DRM_MASTER, .name = "I915_OVERLAY_ATTRS" }, |
2036 | DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_intel_sprite_colorkey) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2b)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_intel_sprite_colorkey) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2b) )), .func = intel_sprite_set_colorkey_ioctl, .flags = DRM_MASTER , .name = "I915_SET_SPRITE_COLORKEY" }, |
2037 | DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_intel_sprite_colorkey) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2a)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_intel_sprite_colorkey) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2a) )), .func = drm_noop, .flags = DRM_MASTER, .name = "I915_GET_SPRITE_COLORKEY" }, |
2038 | DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_wait) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2c)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_wait) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2c))), .func = i915_gem_wait_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_WAIT" }, |
2039 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_context_create_ext) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2d)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof(struct drm_i915_gem_context_create_ext ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2d))), .func = i915_gem_context_create_ioctl, .flags = DRM_RENDER_ALLOW , .name = "I915_GEM_CONTEXT_CREATE_EXT" }, |
2040 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_context_destroy ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x2e)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_context_destroy) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x2e))), .func = i915_gem_context_destroy_ioctl, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_CONTEXT_DESTROY" }, |
2041 | DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_reg_read) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x31)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_reg_read) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x31))), .func = i915_reg_read_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_REG_READ" }, |
2042 | DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_reset_stats) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x32)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_reset_stats) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x32))), .func = i915_gem_context_reset_stats_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GET_RESET_STATS" }, |
2043 | DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_userptr) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x33)))) & 0xff) - 0x40 ] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_gem_userptr) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x33))), .func = i915_gem_userptr_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_USERPTR" }, |
2044 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_context_param) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x34)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_context_param) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x34) )), .func = i915_gem_context_getparam_ioctl, .flags = DRM_RENDER_ALLOW , .name = "I915_GEM_CONTEXT_GETPARAM" }, |
2045 | DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_context_param) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x35)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_context_param) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x35) )), .func = i915_gem_context_setparam_ioctl, .flags = DRM_RENDER_ALLOW , .name = "I915_GEM_CONTEXT_SETPARAM" }, |
2046 | DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_perf_open_param ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x36)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_perf_open_param) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x36))), .func = i915_perf_open_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_PERF_OPEN" }, |
2047 | DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_perf_oa_config ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x37)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_perf_oa_config) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x37))), .func = i915_perf_add_config_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_PERF_ADD_CONFIG" }, |
2048 | DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(__u64) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x38)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof (__u64) & 0x1fff) << 16) | ((('d')) << 8) | ( (0x40 + 0x38))), .func = i915_perf_remove_config_ioctl, .flags = DRM_RENDER_ALLOW, .name = "I915_PERF_REMOVE_CONFIG" }, |
2049 | DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_query) & 0x1fff) << 16) | ( (('d')) << 8) | ((0x40 + 0x39)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long)0x40000000 ) | ((sizeof(struct drm_i915_query) & 0x1fff) << 16 ) | ((('d')) << 8) | ((0x40 + 0x39))), .func = i915_query_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_QUERY" }, |
2050 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW)[(((((unsigned long)0x80000000|(unsigned long)0x40000000) | ( (sizeof(struct drm_i915_gem_vm_control) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x3a)))) & 0xff) - 0x40] = { .cmd = (((unsigned long)0x80000000|(unsigned long) 0x40000000) | ((sizeof(struct drm_i915_gem_vm_control) & 0x1fff ) << 16) | ((('d')) << 8) | ((0x40 + 0x3a))), .func = i915_gem_vm_create_ioctl, .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_VM_CREATE" }, |
2051 | DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW)[((((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_vm_control ) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x3b)))) & 0xff) - 0x40] = { .cmd = ((unsigned long)0x80000000 | ((sizeof(struct drm_i915_gem_vm_control) & 0x1fff) << 16) | ((('d')) << 8) | ((0x40 + 0x3b))), .func = i915_gem_vm_destroy_ioctl , .flags = DRM_RENDER_ALLOW, .name = "I915_GEM_VM_DESTROY" }, |
2052 | }; |
2053 | |
2054 | /* |
2055 | * Interface history: |
2056 | * |
2057 | * 1.1: Original. |
2058 | * 1.2: Add Power Management |
2059 | * 1.3: Add vblank support |
2060 | * 1.4: Fix cmdbuffer path, add heap destroy |
2061 | * 1.5: Add vblank pipe configuration |
2062 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
2063 | * - Support vertical blank on secondary display pipe |
2064 | */ |
2065 | #define DRIVER_MAJOR1 1 |
2066 | #define DRIVER_MINOR6 6 |
2067 | #define DRIVER_PATCHLEVEL0 0 |
2068 | |
2069 | static const struct drm_driver i915_drm_driver = { |
2070 | /* Don't use MTRRs here; the Xserver or userspace app should |
2071 | * deal with them for Intel hardware. |
2072 | */ |
2073 | .driver_features = |
2074 | DRIVER_GEM | |
2075 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ | |
2076 | DRIVER_SYNCOBJ_TIMELINE, |
2077 | .release = i915_driver_release, |
2078 | .open = i915_driver_open, |
2079 | .lastclose = i915_driver_lastclose, |
2080 | .postclose = i915_driver_postclose, |
2081 | |
2082 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
2083 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
2084 | .gem_prime_import = i915_gem_prime_import, |
2085 | |
2086 | .dumb_create = i915_gem_dumb_create, |
2087 | .dumb_map_offset = i915_gem_dumb_mmap_offset, |
2088 | |
2089 | #ifdef __OpenBSD__1 |
2090 | .mmap = i915_gem_mmap, |
2091 | .gem_fault = i915_gem_fault, |
2092 | #endif |
2093 | |
2094 | .ioctls = i915_ioctls, |
2095 | .num_ioctls = ARRAY_SIZE(i915_ioctls)(sizeof((i915_ioctls)) / sizeof((i915_ioctls)[0])), |
2096 | #ifdef __linux__ |
2097 | .fops = &i915_driver_fops, |
2098 | #endif |
2099 | .name = DRIVER_NAME"i915", |
2100 | .desc = DRIVER_DESC"Intel Graphics", |
2101 | .date = DRIVER_DATE"20201103", |
2102 | .major = DRIVER_MAJOR1, |
2103 | .minor = DRIVER_MINOR6, |
2104 | .patchlevel = DRIVER_PATCHLEVEL0, |
2105 | }; |
2106 | |
2107 | #ifdef __OpenBSD__1 |
2108 | |
2109 | #include <drm/drm_legacy.h> /* for agp */ |
2110 | #include <drm/drm_utils.h> |
2111 | #include <drm/drm_fb_helper.h> |
2112 | |
2113 | #ifdef __amd64__1 |
2114 | #include "efifb.h" |
2115 | #include <machine/biosvar.h> |
2116 | #endif |
2117 | |
2118 | #if NEFIFB1 > 0 |
2119 | #include <machine/efifbvar.h> |
2120 | #endif |
2121 | |
2122 | #include "intagp.h" |
2123 | |
2124 | /* |
2125 | * some functions are only called once on init regardless of how many times |
2126 | * inteldrm attaches in linux this is handled via module_init()/module_exit() |
2127 | */ |
2128 | int inteldrm_refcnt; |
2129 | |
2130 | #if NINTAGP1 > 0 |
2131 | int intagpsubmatch(struct device *, void *, void *); |
2132 | int intagp_print(void *, const char *); |
2133 | |
2134 | int |
2135 | intagpsubmatch(struct device *parent, void *match, void *aux) |
2136 | { |
2137 | extern struct cfdriver intagp_cd; |
2138 | struct cfdata *cf = match; |
2139 | |
2140 | /* only allow intagp to attach */ |
2141 | if (cf->cf_driver == &intagp_cd) |
2142 | return ((*cf->cf_attach->ca_match)(parent, match, aux)); |
2143 | return (0); |
2144 | } |
2145 | |
2146 | int |
2147 | intagp_print(void *vaa, const char *pnp) |
2148 | { |
2149 | if (pnp) |
2150 | printf("intagp at %s", pnp); |
2151 | return (UNCONF1); |
2152 | } |
2153 | #endif |
2154 | |
2155 | int inteldrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); |
2156 | paddr_t inteldrm_wsmmap(void *, off_t, int); |
2157 | int inteldrm_alloc_screen(void *, const struct wsscreen_descr *, |
2158 | void **, int *, int *, uint32_t *); |
2159 | void inteldrm_free_screen(void *, void *); |
2160 | int inteldrm_show_screen(void *, void *, int, |
2161 | void (*)(void *, int, int), void *); |
2162 | void inteldrm_doswitch(void *); |
2163 | void inteldrm_enter_ddb(void *, void *); |
2164 | int inteldrm_load_font(void *, void *, struct wsdisplay_font *); |
2165 | int inteldrm_list_font(void *, struct wsdisplay_font *); |
2166 | int inteldrm_getchar(void *, int, int, struct wsdisplay_charcell *); |
2167 | void inteldrm_burner(void *, u_int, u_int); |
2168 | void inteldrm_burner_cb(void *); |
2169 | void inteldrm_scrollback(void *, void *, int lines); |
2170 | extern const struct pci_device_id pciidlist[]; |
2171 | |
2172 | struct wsscreen_descr inteldrm_stdscreen = { |
2173 | "std", |
2174 | 0, 0, |
2175 | 0, |
2176 | 0, 0, |
2177 | WSSCREEN_UNDERLINE16 | WSSCREEN_HILIT4 | |
2178 | WSSCREEN_REVERSE2 | WSSCREEN_WSCOLORS1 |
2179 | }; |
2180 | |
2181 | const struct wsscreen_descr *inteldrm_scrlist[] = { |
2182 | &inteldrm_stdscreen, |
2183 | }; |
2184 | |
2185 | struct wsscreen_list inteldrm_screenlist = { |
2186 | nitems(inteldrm_scrlist)(sizeof((inteldrm_scrlist)) / sizeof((inteldrm_scrlist)[0])), inteldrm_scrlist |
2187 | }; |
2188 | |
2189 | struct wsdisplay_accessops inteldrm_accessops = { |
2190 | .ioctl = inteldrm_wsioctl, |
2191 | .mmap = inteldrm_wsmmap, |
2192 | .alloc_screen = inteldrm_alloc_screen, |
2193 | .free_screen = inteldrm_free_screen, |
2194 | .show_screen = inteldrm_show_screen, |
2195 | .enter_ddb = inteldrm_enter_ddb, |
2196 | .getchar = inteldrm_getchar, |
2197 | .load_font = inteldrm_load_font, |
2198 | .list_font = inteldrm_list_font, |
2199 | .scrollback = inteldrm_scrollback, |
2200 | .burn_screen = inteldrm_burner |
2201 | }; |
2202 | |
2203 | int |
2204 | inteldrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) |
2205 | { |
2206 | struct inteldrm_softc *dev_priv = v; |
2207 | struct backlight_device *bd = dev_priv->backlight; |
2208 | struct rasops_info *ri = &dev_priv->ro; |
2209 | struct wsdisplay_fbinfo *wdf; |
2210 | struct wsdisplay_param *dp = (struct wsdisplay_param *)data; |
2211 | |
2212 | switch (cmd) { |
2213 | case WSDISPLAYIO_GTYPE((unsigned long)0x40000000 | ((sizeof(u_int) & 0x1fff) << 16) | ((('W')) << 8) | ((64))): |
2214 | *(u_int *)data = WSDISPLAY_TYPE_INTELDRM69; |
2215 | return 0; |
2216 | case WSDISPLAYIO_GINFO((unsigned long)0x40000000 | ((sizeof(struct wsdisplay_fbinfo ) & 0x1fff) << 16) | ((('W')) << 8) | ((65))): |
2217 | wdf = (struct wsdisplay_fbinfo *)data; |
2218 | wdf->width = ri->ri_width; |
2219 | wdf->height = ri->ri_height; |
2220 | wdf->depth = ri->ri_depth; |
2221 | wdf->stride = ri->ri_stride; |
2222 | wdf->offset = 0; |
2223 | wdf->cmsize = 0; |
2224 | return 0; |
2225 | case WSDISPLAYIO_GETPARAM(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct wsdisplay_param) & 0x1fff) << 16) | ((('W') ) << 8) | ((89))): |
2226 | if (ws_get_param && ws_get_param(dp) == 0) |
2227 | return 0; |
2228 | |
2229 | if (bd == NULL((void *)0)) |
2230 | return -1; |
2231 | |
2232 | switch (dp->param) { |
2233 | case WSDISPLAYIO_PARAM_BRIGHTNESS2: |
2234 | dp->min = 0; |
2235 | dp->max = bd->props.max_brightness; |
2236 | dp->curval = bd->ops->get_brightness(bd); |
2237 | return (dp->max > dp->min) ? 0 : -1; |
2238 | } |
2239 | break; |
2240 | case WSDISPLAYIO_SETPARAM(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof (struct wsdisplay_param) & 0x1fff) << 16) | ((('W') ) << 8) | ((90))): |
2241 | if (ws_set_param && ws_set_param(dp) == 0) |
2242 | return 0; |
2243 | |
2244 | if (bd == NULL((void *)0) || dp->curval > bd->props.max_brightness) |
2245 | return -1; |
2246 | |
2247 | switch (dp->param) { |
2248 | case WSDISPLAYIO_PARAM_BRIGHTNESS2: |
2249 | bd->props.brightness = dp->curval; |
2250 | backlight_update_status(bd); |
2251 | knote_locked(&dev_priv->drm.note, NOTE_CHANGE0x00000001); |
2252 | return 0; |
2253 | } |
2254 | break; |
2255 | case WSDISPLAYIO_SVIDEO((unsigned long)0x80000000 | ((sizeof(u_int) & 0x1fff) << 16) | ((('W')) << 8) | ((69))): |
2256 | case WSDISPLAYIO_GVIDEO((unsigned long)0x40000000 | ((sizeof(u_int) & 0x1fff) << 16) | ((('W')) << 8) | ((68))): |
2257 | return 0; |
2258 | } |
2259 | |
2260 | return (-1); |
2261 | } |
2262 | |
2263 | paddr_t |
2264 | inteldrm_wsmmap(void *v, off_t off, int prot) |
2265 | { |
2266 | return (-1); |
2267 | } |
2268 | |
2269 | int |
2270 | inteldrm_alloc_screen(void *v, const struct wsscreen_descr *type, |
2271 | void **cookiep, int *curxp, int *curyp, uint32_t *attrp) |
2272 | { |
2273 | struct inteldrm_softc *dev_priv = v; |
2274 | struct rasops_info *ri = &dev_priv->ro; |
2275 | |
2276 | return rasops_alloc_screen(ri, cookiep, curxp, curyp, attrp); |
2277 | } |
2278 | |
2279 | void |
2280 | inteldrm_free_screen(void *v, void *cookie) |
2281 | { |
2282 | struct inteldrm_softc *dev_priv = v; |
2283 | struct rasops_info *ri = &dev_priv->ro; |
2284 | |
2285 | return rasops_free_screen(ri, cookie); |
2286 | } |
2287 | |
2288 | int |
2289 | inteldrm_show_screen(void *v, void *cookie, int waitok, |
2290 | void (*cb)(void *, int, int), void *cbarg) |
2291 | { |
2292 | struct inteldrm_softc *dev_priv = v; |
2293 | struct rasops_info *ri = &dev_priv->ro; |
2294 | |
2295 | if (cookie == ri->ri_active) |
2296 | return (0); |
2297 | |
2298 | dev_priv->switchcb = cb; |
2299 | dev_priv->switchcbarg = cbarg; |
2300 | dev_priv->switchcookie = cookie; |
2301 | if (cb) { |
2302 | task_add(systq, &dev_priv->switchtask); |
2303 | return (EAGAIN35); |
2304 | } |
2305 | |
2306 | inteldrm_doswitch(v); |
2307 | |
2308 | return (0); |
2309 | } |
2310 | |
2311 | void |
2312 | inteldrm_doswitch(void *v) |
2313 | { |
2314 | struct inteldrm_softc *dev_priv = v; |
2315 | struct rasops_info *ri = &dev_priv->ro; |
2316 | struct drm_device *dev = &dev_priv->drm; |
2317 | |
2318 | rasops_show_screen(ri, dev_priv->switchcookie, 0, NULL((void *)0), NULL((void *)0)); |
2319 | intel_fbdev_restore_mode(dev); |
2320 | |
2321 | if (dev_priv->switchcb) |
2322 | (*dev_priv->switchcb)(dev_priv->switchcbarg, 0, 0); |
2323 | } |
2324 | |
2325 | void |
2326 | inteldrm_enter_ddb(void *v, void *cookie) |
2327 | { |
2328 | struct inteldrm_softc *dev_priv = v; |
2329 | struct rasops_info *ri = &dev_priv->ro; |
2330 | struct drm_device *dev = &dev_priv->drm; |
2331 | |
2332 | if (cookie == ri->ri_active) |
2333 | return; |
2334 | |
2335 | rasops_show_screen(ri, cookie, 0, NULL((void *)0), NULL((void *)0)); |
2336 | intel_fbdev_restore_mode(dev); |
2337 | } |
2338 | |
2339 | int |
2340 | inteldrm_getchar(void *v, int row, int col, struct wsdisplay_charcell *cell) |
2341 | { |
2342 | struct inteldrm_softc *dev_priv = v; |
2343 | struct rasops_info *ri = &dev_priv->ro; |
2344 | |
2345 | return rasops_getchar(ri, row, col, cell); |
2346 | } |
2347 | |
2348 | int |
2349 | inteldrm_load_font(void *v, void *cookie, struct wsdisplay_font *font) |
2350 | { |
2351 | struct inteldrm_softc *dev_priv = v; |
2352 | struct rasops_info *ri = &dev_priv->ro; |
2353 | |
2354 | return rasops_load_font(ri, cookie, font); |
2355 | } |
2356 | |
2357 | int |
2358 | inteldrm_list_font(void *v, struct wsdisplay_font *font) |
2359 | { |
2360 | struct inteldrm_softc *dev_priv = v; |
2361 | struct rasops_info *ri = &dev_priv->ro; |
2362 | |
2363 | return rasops_list_font(ri, font); |
2364 | } |
2365 | |
2366 | void |
2367 | inteldrm_burner(void *v, u_int on, u_int flags) |
2368 | { |
2369 | struct inteldrm_softc *dev_priv = v; |
2370 | |
2371 | task_del(systq, &dev_priv->burner_task); |
2372 | |
2373 | if (on) |
2374 | dev_priv->burner_fblank = FB_BLANK_UNBLANK0; |
2375 | else { |
2376 | if (flags & WSDISPLAY_BURN_VBLANK0x0001) |
2377 | dev_priv->burner_fblank = FB_BLANK_VSYNC_SUSPEND3; |
2378 | else |
2379 | dev_priv->burner_fblank = FB_BLANK_NORMAL1; |
2380 | } |
2381 | |
2382 | /* |
2383 | * Setting the DPMS mode may sleep while waiting for the display |
2384 | * to come back on so hand things off to a taskq. |
2385 | */ |
2386 | task_add(systq, &dev_priv->burner_task); |
2387 | } |
2388 | |
2389 | void |
2390 | inteldrm_burner_cb(void *arg1) |
2391 | { |
2392 | struct inteldrm_softc *dev_priv = arg1; |
2393 | struct drm_device *dev = &dev_priv->drm; |
2394 | struct drm_fb_helper *helper = dev->fb_helper; |
2395 | |
2396 | drm_fb_helper_blank(dev_priv->burner_fblank, helper->fbdev); |
2397 | } |
2398 | |
2399 | int |
2400 | inteldrm_backlight_update_status(struct backlight_device *bd) |
2401 | { |
2402 | struct wsdisplay_param dp; |
2403 | |
2404 | dp.param = WSDISPLAYIO_PARAM_BRIGHTNESS2; |
2405 | dp.curval = bd->props.brightness; |
2406 | ws_set_param(&dp); |
2407 | return 0; |
2408 | } |
2409 | |
2410 | int |
2411 | inteldrm_backlight_get_brightness(struct backlight_device *bd) |
2412 | { |
2413 | struct wsdisplay_param dp; |
2414 | |
2415 | dp.param = WSDISPLAYIO_PARAM_BRIGHTNESS2; |
2416 | ws_get_param(&dp); |
2417 | return dp.curval; |
2418 | } |
2419 | |
2420 | const struct backlight_ops inteldrm_backlight_ops = { |
2421 | .update_status = inteldrm_backlight_update_status, |
2422 | .get_brightness = inteldrm_backlight_get_brightness |
2423 | }; |
2424 | |
2425 | void |
2426 | inteldrm_scrollback(void *v, void *cookie, int lines) |
2427 | { |
2428 | struct inteldrm_softc *dev_priv = v; |
2429 | struct rasops_info *ri = &dev_priv->ro; |
2430 | |
2431 | rasops_scrollback(ri, cookie, lines); |
2432 | } |
2433 | |
2434 | int inteldrm_match(struct device *, void *, void *); |
2435 | void inteldrm_attach(struct device *, struct device *, void *); |
2436 | int inteldrm_detach(struct device *, int); |
2437 | int inteldrm_activate(struct device *, int); |
2438 | void inteldrm_attachhook(struct device *); |
2439 | |
2440 | const struct cfattach inteldrm_ca = { |
2441 | sizeof(struct inteldrm_softc), inteldrm_match, inteldrm_attach, |
2442 | inteldrm_detach, inteldrm_activate |
2443 | }; |
2444 | |
2445 | struct cfdriver inteldrm_cd = { |
2446 | 0, "inteldrm", DV_DULL |
2447 | }; |
2448 | |
2449 | int inteldrm_intr(void *); |
2450 | |
2451 | /* |
2452 | * Set if the mountroot hook has a fatal error. |
2453 | */ |
2454 | int inteldrm_fatal_error; |
2455 | |
2456 | int |
2457 | inteldrm_match(struct device *parent, void *match, void *aux) |
2458 | { |
2459 | struct pci_attach_args *pa = aux; |
2460 | const struct pci_device_id *id; |
2461 | struct intel_device_info *info; |
2462 | |
2463 | if (inteldrm_fatal_error) |
2464 | return 0; |
2465 | |
2466 | id = drm_find_description(PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff), |
2467 | PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff), pciidlist); |
2468 | if (id != NULL((void *)0)) { |
2469 | info = (struct intel_device_info *)id->driver_data; |
2470 | if (info->require_force_probe == 0 && |
2471 | pa->pa_function == 0) |
2472 | return 20; |
2473 | } |
2474 | |
2475 | return 0; |
2476 | } |
2477 | |
2478 | int drm_gem_init(struct drm_device *); |
2479 | void intel_init_stolen_res(struct inteldrm_softc *); |
2480 | |
2481 | void |
2482 | inteldrm_attach(struct device *parent, struct device *self, void *aux) |
2483 | { |
2484 | struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self; |
2485 | struct drm_device *dev; |
2486 | struct pci_attach_args *pa = aux; |
2487 | const struct pci_device_id *id; |
2488 | struct intel_device_info *info, *device_info; |
2489 | struct intel_runtime_info *runtime; |
2490 | extern int vga_console_attached; |
2491 | int mmio_bar, mmio_size, mmio_type; |
2492 | int ret; |
2493 | |
2494 | dev_priv->pc = pa->pa_pc; |
2495 | dev_priv->tag = pa->pa_tag; |
2496 | dev_priv->dmat = pa->pa_dmat; |
2497 | dev_priv->bst = pa->pa_memt; |
2498 | dev_priv->memex = pa->pa_memex; |
2499 | dev_priv->vga_regs = &dev_priv->bar; |
2500 | |
2501 | if (PCI_CLASS(pa->pa_class)(((pa->pa_class) >> 24) & 0xff) == PCI_CLASS_DISPLAY0x03 && |
2502 | PCI_SUBCLASS(pa->pa_class)(((pa->pa_class) >> 16) & 0xff) == PCI_SUBCLASS_DISPLAY_VGA0x00 && |
2503 | (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG0x04) |
2504 | & (PCI_COMMAND_IO_ENABLE0x00000001 | PCI_COMMAND_MEM_ENABLE0x00000002)) |
2505 | == (PCI_COMMAND_IO_ENABLE0x00000001 | PCI_COMMAND_MEM_ENABLE0x00000002)) { |
2506 | dev_priv->primary = 1; |
2507 | dev_priv->console = vga_is_console(pa->pa_iot, -1);; |
2508 | vga_console_attached = 1; |
2509 | } |
2510 | |
2511 | #if NEFIFB1 > 0 |
2512 | if (efifb_is_primary(pa)) { |
2513 | dev_priv->primary = 1; |
2514 | dev_priv->console = efifb_is_console(pa); |
2515 | efifb_detach(); |
2516 | } |
2517 | #endif |
2518 | |
2519 | printf("\n"); |
2520 | |
2521 | dev = drm_attach_pci(&i915_drm_driver, pa, 0, dev_priv->primary, |
2522 | self, &dev_priv->drm); |
2523 | if (dev == NULL((void *)0)) { |
2524 | printf("%s: drm attach failed\n", dev_priv->sc_dev.dv_xname); |
2525 | return; |
2526 | } |
2527 | |
2528 | id = drm_find_description(PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff), |
2529 | PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff), pciidlist); |
2530 | dev_priv->id = id; |
2531 | info = (struct intel_device_info *)id->driver_data; |
2532 | |
2533 | /* Device parameters start as a copy of module parameters. */ |
2534 | i915_params_copy(&dev_priv->params, &i915_modparams); |
2535 | dev_priv->params.enable_guc = 0; |
2536 | dev_priv->params.request_timeout_ms = 0; |
2537 | dev_priv->params.enable_psr = 0; |
2538 | |
2539 | /* Setup the write-once "constant" device info */ |
2540 | device_info = mkwrite_device_info(dev_priv); |
2541 | memcpy(device_info, info, sizeof(*device_info))__builtin_memcpy((device_info), (info), (sizeof(*device_info) )); |
2542 | |
2543 | /* Initialize initial runtime info from static const data and pdev. */ |
2544 | runtime = RUNTIME_INFO(dev_priv)(&(dev_priv)->__runtime); |
2545 | memcpy(runtime, &INTEL_INFO(dev_priv)->__runtime, sizeof(*runtime))__builtin_memcpy((runtime), (&(&(dev_priv)->__info )->__runtime), (sizeof(*runtime))); |
2546 | runtime->device_id = dev->pdev->device; |
2547 | |
2548 | mmio_bar = (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) == 2) ? 0x14 : 0x10; |
2549 | /* Before gen4, the registers and the GTT are behind different BARs. |
2550 | * However, from gen4 onwards, the registers and the GTT are shared |
2551 | * in the same BAR, so we want to restrict this ioremap from |
2552 | * clobbering the GTT which we want ioremap_wc instead. Fortunately, |
2553 | * the register BAR remains the same size for all the earlier |
2554 | * generations up to Ironlake. |
2555 | */ |
2556 | if (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) < 5) |
2557 | mmio_size = 512 * 1024; |
2558 | else if (IS_DGFX(dev_priv)((&(dev_priv)->__info)->is_dgfx)) |
2559 | mmio_size = 4 * 1024 * 1024; |
2560 | else |
2561 | mmio_size = 2 * 1024 * 1024; |
2562 | |
2563 | mmio_type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, mmio_bar); |
2564 | if (pci_mapreg_map(pa, mmio_bar, mmio_type, BUS_SPACE_MAP_LINEAR0x0002, |
2565 | &dev_priv->vga_regs->bst, &dev_priv->vga_regs->bsh, |
2566 | &dev_priv->vga_regs->base, &dev_priv->vga_regs->size, mmio_size)) { |
2567 | printf("%s: can't map registers\n", |
2568 | dev_priv->sc_dev.dv_xname); |
2569 | return; |
2570 | } |
2571 | dev_priv->uncore.regs = bus_space_vaddr(dev_priv->vga_regs->bst,((dev_priv->vga_regs->bst)->vaddr((dev_priv->vga_regs ->bsh))) |
2572 | dev_priv->vga_regs->bsh)((dev_priv->vga_regs->bst)->vaddr((dev_priv->vga_regs ->bsh))); |
2573 | if (dev_priv->uncore.regs == NULL((void *)0)) { |
2574 | printf("%s: bus_space_vaddr registers failed\n", |
2575 | dev_priv->sc_dev.dv_xname); |
2576 | return; |
2577 | } |
2578 | |
2579 | #if NINTAGP1 > 0 |
2580 | if (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) <= 5) { |
2581 | config_found_sm(self, aux, intagp_print, intagpsubmatch); |
2582 | dev->agp = drm_legacy_agp_init(dev); |
2583 | if (dev->agp) { |
2584 | if (drm_mtrr_add(dev->agp->info.ai_aperture_base, |
2585 | dev->agp->info.ai_aperture_size, DRM_MTRR_WC(1<<1)) == 0) |
2586 | dev->agp->mtrr = 1; |
2587 | } |
2588 | } |
2589 | #endif |
2590 | |
2591 | if (GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver) < 5) |
2592 | pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED0x20; |
2593 | |
2594 | if (pci_intr_map_msi(pa, &dev_priv->ih) != 0 && |
2595 | pci_intr_map(pa, &dev_priv->ih) != 0) { |
2596 | printf("%s: couldn't map interrupt\n", |
2597 | dev_priv->sc_dev.dv_xname); |
2598 | return; |
2599 | } |
2600 | |
2601 | printf("%s: %s, %s, gen %d\n", dev_priv->sc_dev.dv_xname, |
2602 | pci_intr_string(dev_priv->pc, dev_priv->ih), |
2603 | intel_platform_name(INTEL_INFO(dev_priv)(&(dev_priv)->__info)->platform), |
2604 | GRAPHICS_VER(dev_priv)((&(dev_priv)->__runtime)->graphics.ip.ver)); |
2605 | |
2606 | dev_priv->irqh = pci_intr_establish(dev_priv->pc, dev_priv->ih, |
2607 | IPL_TTY0x9, inteldrm_intr, dev_priv, dev_priv->sc_dev.dv_xname); |
2608 | if (dev_priv->irqh == NULL((void *)0)) { |
2609 | printf("%s: couldn't establish interrupt\n", |
2610 | dev_priv->sc_dev.dv_xname); |
2611 | return; |
2612 | } |
2613 | dev->pdev->irq = -1; |
2614 | i915_get_bridge_dev(dev_priv); |
2615 | intel_init_stolen_res(dev_priv); |
2616 | |
2617 | config_mountroot(self, inteldrm_attachhook); |
2618 | } |
2619 | |
2620 | void |
2621 | inteldrm_forcedetach(struct inteldrm_softc *dev_priv) |
2622 | { |
2623 | struct pci_softc *psc = (struct pci_softc *)dev_priv->sc_dev.dv_parent; |
Value stored to 'psc' during its initialization is never read | |
2624 | pcitag_t tag = dev_priv->tag; |
2625 | extern int vga_console_attached; |
2626 | |
2627 | if (dev_priv->primary) { |
2628 | vga_console_attached = 0; |
2629 | #if NEFIFB1 > 0 |
2630 | efifb_reattach(); |
2631 | #endif |
2632 | } |
2633 | |
2634 | #ifdef notyet |
2635 | config_detach(&dev_priv->sc_dev, 0); |
2636 | pci_probe_device(psc, tag, NULL((void *)0), NULL((void *)0)); |
2637 | #endif |
2638 | } |
2639 | |
2640 | extern int __init i915_init(void); |
2641 | |
2642 | void |
2643 | inteldrm_attachhook(struct device *self) |
2644 | { |
2645 | struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self; |
2646 | struct rasops_info *ri = &dev_priv->ro; |
2647 | struct wsemuldisplaydev_attach_args aa; |
2648 | const struct pci_device_id *id = dev_priv->id; |
2649 | struct drm_device *dev = &dev_priv->drm; |
2650 | int orientation_quirk; |
2651 | |
2652 | if (inteldrm_refcnt == 0) { |
2653 | i915_init(); |
2654 | } |
2655 | inteldrm_refcnt++; |
2656 | |
2657 | if (i915_driver_probe(dev_priv, id)) |
2658 | goto fail; |
2659 | |
2660 | if (ri->ri_bits == NULL((void *)0)) |
2661 | goto fail; |
2662 | |
2663 | printf("%s: %dx%d, %dbpp\n", dev_priv->sc_dev.dv_xname, |
2664 | ri->ri_width, ri->ri_height, ri->ri_depth); |
2665 | |
2666 | ri->ri_flg = RI_CENTER0x0040 | RI_WRONLY0x1000 | RI_VCONS0x0800 | RI_CLEAR0x0010; |
2667 | |
2668 | orientation_quirk = drm_get_panel_orientation_quirk(ri->ri_width, |
2669 | ri->ri_height); |
2670 | if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_LEFT_UP) |
2671 | ri->ri_flg |= RI_ROTATE_CCW0x0200; |
2672 | else if (orientation_quirk == DRM_MODE_PANEL_ORIENTATION_RIGHT_UP) |
2673 | ri->ri_flg |= RI_ROTATE_CW0x0100; |
2674 | |
2675 | ri->ri_hw = dev_priv; |
2676 | rasops_init(ri, 160, 160); |
2677 | |
2678 | task_set(&dev_priv->switchtask, inteldrm_doswitch, dev_priv); |
2679 | task_set(&dev_priv->burner_task, inteldrm_burner_cb, dev_priv); |
2680 | |
2681 | inteldrm_stdscreen.capabilities = ri->ri_caps; |
2682 | inteldrm_stdscreen.nrows = ri->ri_rows; |
2683 | inteldrm_stdscreen.ncols = ri->ri_cols; |
2684 | inteldrm_stdscreen.textops = &ri->ri_ops; |
2685 | inteldrm_stdscreen.fontwidth = ri->ri_font->fontwidth; |
2686 | inteldrm_stdscreen.fontheight = ri->ri_font->fontheight; |
2687 | |
2688 | aa.console = dev_priv->console; |
2689 | aa.primary = dev_priv->primary; |
2690 | aa.scrdata = &inteldrm_screenlist; |
2691 | aa.accessops = &inteldrm_accessops; |
2692 | aa.accesscookie = dev_priv; |
2693 | aa.defaultscreens = 0; |
2694 | |
2695 | if (dev_priv->console) { |
2696 | uint32_t defattr; |
2697 | |
2698 | /* |
2699 | * Clear the entire screen if we're doing rotation to |
2700 | * make sure no unrotated content survives. |
2701 | */ |
2702 | if (ri->ri_flg & (RI_ROTATE_CW0x0100 | RI_ROTATE_CCW0x0200)) |
2703 | memset(ri->ri_bits, 0, ri->ri_height * ri->ri_stride)__builtin_memset((ri->ri_bits), (0), (ri->ri_height * ri ->ri_stride)); |
2704 | |
2705 | ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); |
2706 | wsdisplay_cnattach(&inteldrm_stdscreen, ri->ri_active, |
2707 | 0, 0, defattr); |
2708 | } |
2709 | |
2710 | config_found_sm(self, &aa, wsemuldisplaydevprint, |
2711 | wsemuldisplaydevsubmatch); |
2712 | return; |
2713 | |
2714 | fail: |
2715 | inteldrm_fatal_error = 1; |
2716 | inteldrm_forcedetach(dev_priv); |
2717 | } |
2718 | |
2719 | int |
2720 | inteldrm_detach(struct device *self, int flags) |
2721 | { |
2722 | return 0; |
2723 | } |
2724 | |
2725 | int |
2726 | inteldrm_activate(struct device *self, int act) |
2727 | { |
2728 | struct inteldrm_softc *dev_priv = (struct inteldrm_softc *)self; |
2729 | struct drm_device *dev = &dev_priv->drm; |
2730 | int rv = 0; |
2731 | |
2732 | if (dev->dev == NULL((void *)0) || inteldrm_fatal_error) |
2733 | return (0); |
2734 | |
2735 | /* |
2736 | * On hibernate resume activate is called before inteldrm_attachhook(). |
2737 | * Do not try to call i915_drm_suspend() when |
2738 | * i915_load_modeset_init()/i915_gem_init() have not been called. |
2739 | */ |
2740 | if (dev_priv->display.wq.modeset == NULL((void *)0)) |
2741 | return 0; |
2742 | |
2743 | switch (act) { |
2744 | case DVACT_QUIESCE2: |
2745 | rv = config_suspend(dev->dev, act); |
2746 | i915_drm_prepare(dev); |
2747 | i915_drm_suspend(dev); |
2748 | i915_drm_suspend_late(dev, false0); |
2749 | break; |
2750 | case DVACT_SUSPEND3: |
2751 | if (dev->agp) |
2752 | config_suspend(dev->agp->agpdev->sc_chipc, act); |
2753 | break; |
2754 | case DVACT_RESUME4: |
2755 | if (dev->agp) |
2756 | config_suspend(dev->agp->agpdev->sc_chipc, act); |
2757 | break; |
2758 | case DVACT_WAKEUP5: |
2759 | i915_drm_resume_early(dev); |
2760 | i915_drm_resume(dev); |
2761 | intel_fbdev_restore_mode(dev); |
2762 | rv = config_suspend(dev->dev, act); |
2763 | break; |
2764 | } |
2765 | |
2766 | return (rv); |
2767 | } |
2768 | |
2769 | void |
2770 | inteldrm_native_backlight(struct inteldrm_softc *dev_priv) |
2771 | { |
2772 | struct drm_device *dev = &dev_priv->drm; |
2773 | struct drm_connector_list_iter conn_iter; |
2774 | struct drm_connector *connector; |
2775 | |
2776 | drm_connector_list_iter_begin(dev, &conn_iter); |
2777 | drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter ))) { |
2778 | struct intel_connector *intel_connector; |
2779 | struct intel_panel *panel; |
2780 | struct backlight_device *bd; |
2781 | |
2782 | if (connector->registration_state != DRM_CONNECTOR_REGISTERED) |
2783 | continue; |
2784 | |
2785 | intel_connector = to_intel_connector(connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector, base) );}); |
2786 | panel = &intel_connector->panel; |
2787 | bd = panel->backlight.device; |
2788 | |
2789 | if (!panel->backlight.present || bd == NULL((void *)0)) |
2790 | continue; |
2791 | |
2792 | dev->registered = false0; |
2793 | connector->registration_state = DRM_CONNECTOR_UNREGISTERED; |
2794 | |
2795 | connector->backlight_device = bd; |
2796 | connector->backlight_property = drm_property_create_range(dev, |
2797 | 0, "Backlight", 0, bd->props.max_brightness); |
2798 | drm_object_attach_property(&connector->base, |
2799 | connector->backlight_property, bd->props.brightness); |
2800 | |
2801 | connector->registration_state = DRM_CONNECTOR_REGISTERED; |
2802 | dev->registered = true1; |
2803 | |
2804 | /* |
2805 | * Use backlight from the first connector that has one |
2806 | * for wscons(4). |
2807 | */ |
2808 | if (dev_priv->backlight == NULL((void *)0)) |
2809 | dev_priv->backlight = bd; |
2810 | } |
2811 | drm_connector_list_iter_end(&conn_iter); |
2812 | } |
2813 | |
2814 | void |
2815 | inteldrm_firmware_backlight(struct inteldrm_softc *dev_priv, |
2816 | struct wsdisplay_param *dp) |
2817 | { |
2818 | struct drm_device *dev = &dev_priv->drm; |
2819 | struct drm_connector_list_iter conn_iter; |
2820 | struct drm_connector *connector; |
2821 | struct backlight_properties props; |
2822 | struct backlight_device *bd; |
2823 | |
2824 | memset(&props, 0, sizeof(props))__builtin_memset((&props), (0), (sizeof(props))); |
2825 | props.type = BACKLIGHT_FIRMWARE1; |
2826 | props.brightness = dp->curval; |
2827 | bd = backlight_device_register(dev->dev->dv_xname, NULL((void *)0), NULL((void *)0), |
2828 | &inteldrm_backlight_ops, &props); |
2829 | |
2830 | drm_connector_list_iter_begin(dev, &conn_iter); |
2831 | drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter ))) { |
2832 | if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS7 && |
2833 | connector->connector_type != DRM_MODE_CONNECTOR_eDP14 && |
2834 | connector->connector_type != DRM_MODE_CONNECTOR_DSI16) |
2835 | continue; |
2836 | |
2837 | if (connector->registration_state != DRM_CONNECTOR_REGISTERED) |
2838 | continue; |
2839 | |
2840 | dev->registered = false0; |
2841 | connector->registration_state = DRM_CONNECTOR_UNREGISTERED; |
2842 | |
2843 | connector->backlight_device = bd; |
2844 | connector->backlight_property = drm_property_create_range(dev, |
2845 | 0, "Backlight", dp->min, dp->max); |
2846 | drm_object_attach_property(&connector->base, |
2847 | connector->backlight_property, dp->curval); |
2848 | |
2849 | connector->registration_state = DRM_CONNECTOR_REGISTERED; |
2850 | dev->registered = true1; |
2851 | } |
2852 | drm_connector_list_iter_end(&conn_iter); |
2853 | } |
2854 | |
2855 | void |
2856 | inteldrm_init_backlight(struct inteldrm_softc *dev_priv) |
2857 | { |
2858 | struct drm_device *dev = &dev_priv->drm; |
2859 | struct wsdisplay_param dp; |
2860 | |
2861 | dp.param = WSDISPLAYIO_PARAM_BRIGHTNESS2; |
2862 | if (ws_get_param && ws_get_param(&dp) == 0) |
2863 | inteldrm_firmware_backlight(dev_priv, &dp); |
2864 | else |
2865 | inteldrm_native_backlight(dev_priv); |
2866 | } |
2867 | |
2868 | int |
2869 | inteldrm_intr(void *arg) |
2870 | { |
2871 | struct inteldrm_softc *dev_priv = arg; |
2872 | |
2873 | if (dev_priv->irq_handler) |
2874 | return dev_priv->irq_handler(0, dev_priv); |
2875 | |
2876 | return 0; |
2877 | } |
2878 | |
2879 | #endif |