| File: | dev/pci/drm/i915/gt/intel_region_lmem.c |
| Warning: | line 210, column 18 Value stored to 'pdev' during its initialization is never read |
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| 1 | // SPDX-License-Identifier: MIT |
| 2 | /* |
| 3 | * Copyright © 2019 Intel Corporation |
| 4 | */ |
| 5 | |
| 6 | #include "i915_drv.h" |
| 7 | #include "i915_pci.h" |
| 8 | #include "i915_reg.h" |
| 9 | #include "intel_memory_region.h" |
| 10 | #include "intel_pci_config.h" |
| 11 | #include "intel_region_lmem.h" |
| 12 | #include "intel_region_ttm.h" |
| 13 | #include "gem/i915_gem_lmem.h" |
| 14 | #include "gem/i915_gem_region.h" |
| 15 | #include "gem/i915_gem_ttm.h" |
| 16 | #include "gt/intel_gt.h" |
| 17 | #include "gt/intel_gt_mcr.h" |
| 18 | #include "gt/intel_gt_regs.h" |
| 19 | |
| 20 | #ifdef CONFIG_64BIT1 |
| 21 | static void _release_bars(struct pci_dev *pdev) |
| 22 | { |
| 23 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 24 | #ifdef notyet |
| 25 | int resno; |
| 26 | |
| 27 | for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) { |
| 28 | if (pci_resource_len(pdev, resno)) |
| 29 | pci_release_resource(pdev, resno); |
| 30 | } |
| 31 | #endif |
| 32 | } |
| 33 | |
| 34 | static void |
| 35 | _resize_bar(struct drm_i915_privateinteldrm_softc *i915, int resno, resource_size_t size) |
| 36 | { |
| 37 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 38 | #ifdef notyet |
| 39 | struct pci_dev *pdev = i915->drm.pdev; |
| 40 | int bar_size = pci_rebar_bytes_to_size(size); |
| 41 | int ret; |
| 42 | |
| 43 | _release_bars(pdev); |
| 44 | |
| 45 | ret = pci_resize_resource(pdev, resno, bar_size); |
| 46 | if (ret) { |
| 47 | drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",do { } while(0) |
| 48 | resno, 1 << bar_size, ERR_PTR(ret))do { } while(0); |
| 49 | return; |
| 50 | } |
| 51 | |
| 52 | drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size)do { } while(0); |
| 53 | #endif |
| 54 | } |
| 55 | |
| 56 | static void i915_resize_lmem_bar(struct drm_i915_privateinteldrm_softc *i915, resource_size_t lmem_size) |
| 57 | { |
| 58 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 59 | #ifdef notyet |
| 60 | struct pci_dev *pdev = i915->drm.pdev; |
| 61 | struct pci_bus *root = pdev->bus; |
| 62 | struct resource *root_res; |
| 63 | resource_size_t rebar_size; |
| 64 | resource_size_t current_size; |
| 65 | u32 pci_cmd; |
| 66 | int i; |
| 67 | |
| 68 | current_size = roundup_pow_of_two(pci_resource_len(pdev, GEN12_LMEM_BAR2)); |
| 69 | |
| 70 | if (i915->params.lmem_bar_size) { |
| 71 | u32 bar_sizes; |
| 72 | |
| 73 | rebar_size = i915->params.lmem_bar_size * |
| 74 | (resource_size_t)SZ_1M(1 << 20); |
| 75 | bar_sizes = pci_rebar_get_possible_sizes(pdev, GEN12_LMEM_BAR2); |
| 76 | |
| 77 | if (rebar_size == current_size) |
| 78 | return; |
| 79 | |
| 80 | if (!(bar_sizes & BIT(pci_rebar_bytes_to_size(rebar_size))(1UL << (pci_rebar_bytes_to_size(rebar_size)))) || |
| 81 | rebar_size >= roundup_pow_of_two(lmem_size)) { |
| 82 | rebar_size = lmem_size; |
| 83 | |
| 84 | drm_info(&i915->drm,do { } while(0) |
| 85 | "Given bar size is not within supported size, setting it to default: %llu\n",do { } while(0) |
| 86 | (u64)lmem_size >> 20)do { } while(0); |
| 87 | } |
| 88 | } else { |
| 89 | rebar_size = current_size; |
| 90 | |
| 91 | if (rebar_size != roundup_pow_of_two(lmem_size)) |
| 92 | rebar_size = lmem_size; |
| 93 | else |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | /* Find out if root bus contains 64bit memory addressing */ |
| 98 | while (root->parent) |
| 99 | root = root->parent; |
| 100 | |
| 101 | pci_bus_for_each_resource(root, root_res, i) { |
| 102 | if (root_res && root_res->flags & (IORESOURCE_MEM0x0001 | IORESOURCE_MEM_64) && |
| 103 | root_res->start > 0x100000000ull) |
| 104 | break; |
| 105 | } |
| 106 | |
| 107 | /* pci_resize_resource will fail anyways */ |
| 108 | if (!root_res) { |
| 109 | drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n")do { } while(0); |
| 110 | return; |
| 111 | } |
| 112 | |
| 113 | /* First disable PCI memory decoding references */ |
| 114 | pci_read_config_dword(pdev, PCI_COMMAND0x04, &pci_cmd); |
| 115 | pci_write_config_dword(pdev, PCI_COMMAND0x04, |
| 116 | pci_cmd & ~PCI_COMMAND_MEMORY0x00000002); |
| 117 | |
| 118 | _resize_bar(i915, GEN12_LMEM_BAR2, rebar_size); |
| 119 | |
| 120 | pci_assign_unassigned_bus_resources(pdev->bus); |
| 121 | pci_write_config_dword(pdev, PCI_COMMAND0x04, pci_cmd); |
| 122 | #endif |
| 123 | } |
| 124 | #else |
| 125 | static void i915_resize_lmem_bar(struct drm_i915_privateinteldrm_softc *i915, resource_size_t lmem_size) {} |
| 126 | #endif |
| 127 | |
| 128 | static int |
| 129 | region_lmem_release(struct intel_memory_region *mem) |
| 130 | { |
| 131 | int ret; |
| 132 | |
| 133 | ret = intel_region_ttm_fini(mem); |
| 134 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 135 | #ifdef notyet |
| 136 | io_mapping_fini(&mem->iomap); |
| 137 | #endif |
| 138 | |
| 139 | return ret; |
| 140 | } |
| 141 | |
| 142 | static int |
| 143 | region_lmem_init(struct intel_memory_region *mem) |
| 144 | { |
| 145 | STUB()do { printf("%s: stub\n", __func__); } while(0); |
| 146 | return -ENOSYS78; |
| 147 | #ifdef notyet |
| 148 | int ret; |
| 149 | |
| 150 | if (!io_mapping_init_wc(&mem->iomap, |
| 151 | mem->io_start, |
| 152 | mem->io_size)) |
| 153 | return -EIO5; |
| 154 | |
| 155 | ret = intel_region_ttm_init(mem); |
| 156 | if (ret) |
| 157 | goto out_no_buddy; |
| 158 | |
| 159 | return 0; |
| 160 | |
| 161 | out_no_buddy: |
| 162 | io_mapping_fini(&mem->iomap); |
| 163 | |
| 164 | return ret; |
| 165 | #endif |
| 166 | } |
| 167 | |
| 168 | static const struct intel_memory_region_ops intel_region_lmem_ops = { |
| 169 | .init = region_lmem_init, |
| 170 | .release = region_lmem_release, |
| 171 | .init_object = __i915_gem_ttm_object_init, |
| 172 | }; |
| 173 | |
| 174 | static bool_Bool get_legacy_lowmem_region(struct intel_uncore *uncore, |
| 175 | u64 *start, u32 *size) |
| 176 | { |
| 177 | if (!IS_DG1_GRAPHICS_STEP(uncore->i915, STEP_A0, STEP_C0)(IS_PLATFORM(uncore->i915, INTEL_DG1) && (({ int __ret = !!((((&(uncore->i915)->__runtime)->step.graphics_step ) == STEP_NONE)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&(uncore->i915)->drm))->dev), "", "drm_WARN_ON(" "((&(uncore->i915)->__runtime)->step.graphics_step) == STEP_NONE" ")"); __builtin_expect(!!(__ret), 0); }), ((&(uncore-> i915)->__runtime)->step.graphics_step) >= (STEP_A0) && ((&(uncore->i915)->__runtime)->step.graphics_step ) < (STEP_C0)))) |
| 178 | return false0; |
| 179 | |
| 180 | *start = 0; |
| 181 | *size = SZ_1M(1 << 20); |
| 182 | |
| 183 | drm_dbg(&uncore->i915->drm, "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n",__drm_dev_dbg(((void *)0), (&uncore->i915->drm) ? ( &uncore->i915->drm)->dev : ((void *)0), DRM_UT_DRIVER , "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n", *start , *start + *size) |
| 184 | *start, *start + *size)__drm_dev_dbg(((void *)0), (&uncore->i915->drm) ? ( &uncore->i915->drm)->dev : ((void *)0), DRM_UT_DRIVER , "LMEM: reserved legacy low-memory [0x%llx-0x%llx]\n", *start , *start + *size); |
| 185 | |
| 186 | return true1; |
| 187 | } |
| 188 | |
| 189 | static int reserve_lowmem_region(struct intel_uncore *uncore, |
| 190 | struct intel_memory_region *mem) |
| 191 | { |
| 192 | u64 reserve_start; |
| 193 | u32 reserve_size; |
| 194 | int ret; |
| 195 | |
| 196 | if (!get_legacy_lowmem_region(uncore, &reserve_start, &reserve_size)) |
| 197 | return 0; |
| 198 | |
| 199 | ret = intel_memory_region_reserve(mem, reserve_start, reserve_size); |
| 200 | if (ret) |
| 201 | drm_err(&uncore->i915->drm, "LMEM: reserving low memory region failed\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "LMEM: reserving low memory region failed\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 202 | |
| 203 | return ret; |
| 204 | } |
| 205 | |
| 206 | static struct intel_memory_region *setup_lmem(struct intel_gt *gt) |
| 207 | { |
| 208 | struct drm_i915_privateinteldrm_softc *i915 = gt->i915; |
| 209 | struct intel_uncore *uncore = gt->uncore; |
| 210 | struct pci_dev *pdev = i915->drm.pdev; |
Value stored to 'pdev' during its initialization is never read | |
| 211 | struct intel_memory_region *mem; |
| 212 | resource_size_t min_page_size; |
| 213 | resource_size_t io_start; |
| 214 | resource_size_t io_size; |
| 215 | resource_size_t lmem_size; |
| 216 | int err; |
| 217 | |
| 218 | if (!IS_DGFX(i915)((&(i915)->__info)->is_dgfx)) |
| 219 | return ERR_PTR(-ENODEV19); |
| 220 | |
| 221 | #ifdef notyet |
| 222 | if (!i915_pci_resource_valid(pdev, GEN12_LMEM_BAR2)) |
| 223 | return ERR_PTR(-ENXIO6); |
| 224 | #endif |
| 225 | |
| 226 | if (HAS_FLAT_CCS(i915)((&(i915)->__info)->has_flat_ccs)) { |
| 227 | resource_size_t lmem_range; |
| 228 | u64 tile_stolen, flat_ccs_base; |
| 229 | |
| 230 | lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE((const i915_reg_t){ .reg = (0x4900) })) & 0xFFFF; |
| 231 | lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT8; |
| 232 | lmem_size *= SZ_1G(1 << 30); |
| 233 | |
| 234 | flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR((const i915_reg_t){ .reg = (0x4910) })); |
| 235 | flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT8) * SZ_64K(64 << 10); |
| 236 | |
| 237 | if (GEM_WARN_ON(lmem_size < flat_ccs_base)({ __builtin_expect(!!(!!(lmem_size < flat_ccs_base)), 0); })) |
| 238 | return ERR_PTR(-EIO5); |
| 239 | |
| 240 | tile_stolen = lmem_size - flat_ccs_base; |
| 241 | |
| 242 | /* If the FLAT_CCS_BASE_ADDR register is not populated, flag an error */ |
| 243 | if (tile_stolen == lmem_size) |
| 244 | drm_err(&i915->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "CCS_BASE_ADDR register did not have expected value\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
| 245 | "CCS_BASE_ADDR register did not have expected value\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "CCS_BASE_ADDR register did not have expected value\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
| 246 | |
| 247 | lmem_size -= tile_stolen; |
| 248 | } else { |
| 249 | /* Stolen starts from GSMBASE without CCS */ |
| 250 | lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE((const i915_reg_t){ .reg = (0x108100) })); |
| 251 | } |
| 252 | |
| 253 | i915_resize_lmem_bar(i915, lmem_size); |
| 254 | |
| 255 | if (i915->params.lmem_size > 0) { |
| 256 | lmem_size = min_t(resource_size_t, lmem_size,({ resource_size_t __min_a = (lmem_size); resource_size_t __min_b = (mul_u32_u32(i915->params.lmem_size, (1 << 20))); __min_a < __min_b ? __min_a : __min_b; }) |
| 257 | mul_u32_u32(i915->params.lmem_size, SZ_1M))({ resource_size_t __min_a = (lmem_size); resource_size_t __min_b = (mul_u32_u32(i915->params.lmem_size, (1 << 20))); __min_a < __min_b ? __min_a : __min_b; }); |
| 258 | } |
| 259 | |
| 260 | #ifdef __linux__ |
| 261 | io_start = pci_resource_start(pdev, GEN12_LMEM_BAR2); |
| 262 | io_size = min(pci_resource_len(pdev, GEN12_LMEM_BAR), lmem_size)(((pci_resource_len(pdev, 2))<(lmem_size))?(pci_resource_len (pdev, 2)):(lmem_size)); |
| 263 | #else |
| 264 | { |
| 265 | pcireg_t type; |
| 266 | bus_size_t len; |
| 267 | |
| 268 | type = pci_mapreg_type(i915->pc, i915->tag, |
| 269 | 0x10 + (4 * GEN12_LMEM_BAR2)); |
| 270 | err = -pci_mapreg_info(i915->pc, i915->tag, |
| 271 | 0x10 + (4 * GEN12_LMEM_BAR2), type, &io_start, &len, NULL((void *)0)); |
| 272 | io_size = min(len, lmem_size)(((len)<(lmem_size))?(len):(lmem_size)); |
| 273 | } |
| 274 | #endif |
| 275 | if (!io_size) |
| 276 | return ERR_PTR(-EIO5); |
| 277 | |
| 278 | min_page_size = HAS_64K_PAGES(i915)((&(i915)->__info)->has_64k_pages) ? I915_GTT_PAGE_SIZE_64K(1ULL << (16)) : |
| 279 | I915_GTT_PAGE_SIZE_4K(1ULL << (12)); |
| 280 | mem = intel_memory_region_create(i915, |
| 281 | 0, |
| 282 | lmem_size, |
| 283 | min_page_size, |
| 284 | io_start, |
| 285 | io_size, |
| 286 | INTEL_MEMORY_LOCAL, |
| 287 | 0, |
| 288 | &intel_region_lmem_ops); |
| 289 | if (IS_ERR(mem)) |
| 290 | return mem; |
| 291 | |
| 292 | err = reserve_lowmem_region(uncore, mem); |
| 293 | if (err) |
| 294 | goto err_region_put; |
| 295 | |
| 296 | drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_DRIVER, "Local memory: %pR\n" , &mem->region); |
| 297 | drm_dbg(&i915->drm, "Local memory IO start: %pa\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_DRIVER, "Local memory IO start: %pa\n" , &mem->io_start) |
| 298 | &mem->io_start)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_DRIVER, "Local memory IO start: %pa\n" , &mem->io_start); |
| 299 | drm_info(&i915->drm, "Local memory IO size: %pa\n",do { } while(0) |
| 300 | &mem->io_size)do { } while(0); |
| 301 | drm_info(&i915->drm, "Local memory available: %pa\n",do { } while(0) |
| 302 | &lmem_size)do { } while(0); |
| 303 | |
| 304 | if (io_size < lmem_size) |
| 305 | drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",do { } while(0) |
| 306 | (u64)io_size >> 20)do { } while(0); |
| 307 | |
| 308 | return mem; |
| 309 | |
| 310 | err_region_put: |
| 311 | intel_memory_region_destroy(mem); |
| 312 | return ERR_PTR(err); |
| 313 | } |
| 314 | |
| 315 | struct intel_memory_region *intel_gt_setup_lmem(struct intel_gt *gt) |
| 316 | { |
| 317 | return setup_lmem(gt); |
| 318 | } |