/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu

Bug Summary

File:	dev/pci/drm/amd/amdgpu/amdgpu_ras.c
Warning:	line 763, column 3 1st function call argument is an uninitialized value
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_ras.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c
1/*
* Copyright 2018 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*
*/
24#include <linux/debugfs.h>
25#include <linux/list.h>
26#include <linux/module.h>
27#include <linux/uaccess.h>
28#include <linux/reboot.h>
29#include <linux/syscalls.h>
30#include <linux/pm_runtime.h>

32#include "amdgpu.h"
33#include "amdgpu_ras.h"
34#include "amdgpu_atomfirmware.h"
35#include "amdgpu_xgmi.h"
36#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
37#include "atom.h"
38#include "amdgpu_reset.h"

40#ifdef CONFIG_X86_MCE_AMD
41#include <asm/mce.h>

43static bool_Bool notifier_registered;
44#endif
45static const char *RAS_FS_NAME = "ras";

47const char *ras_error_string[] = {
"none",
"parity",
"single_correctable",
"multi_uncorrectable",
"poison",
53};

55const char *ras_block_string[] = {
"umc",
"sdma",
"gfx",
"mmhub",
"athub",
"pcie_bif",
"hdp",
"xgmi_wafl",
"df",
"smn",
"sem",
"mp0",
"mp1",
"fuse",
"mca",
"vcn",
"jpeg",
73};

75const char *ras_mca_block_string[] = {
"mca_mp0",
"mca_mp1",
"mca_mpio",
"mca_iohc",
80};

82struct amdgpu_ras_block_list {
/* ras block link */
struct list_head node;

struct amdgpu_ras_block_object *ras_obj;
87};

89const char *get_ras_block_str(struct ras_common_if *ras_block)
90{
if (!ras_block)
return "NULL";

if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST)
return "OUT OF RANGE";

if (ras_block->block == AMDGPU_RAS_BLOCK__MCA)
return ras_mca_block_string[ras_block->sub_block_index];

return ras_block_string[ras_block->block];
101}

103#define ras_block_str(_BLOCK_)(((_BLOCK_) < (sizeof((ras_block_string)) / sizeof((ras_block_string
)[0]))) ? ras_block_string[_BLOCK_] : "Out Of Range") \
(((_BLOCK_) < ARRAY_SIZE(ras_block_string)(sizeof((ras_block_string)) / sizeof((ras_block_string)[0]))) ? ras_block_string[_BLOCK_] : "Out Of Range")

106#define ras_err_str(i)(ras_error_string[ffs(i)]) (ras_error_string[ffs(i)])

108#define RAS_DEFAULT_FLAGS((0x1 << 0)) (AMDGPU_RAS_FLAG_INIT_BY_VBIOS(0x1 << 0))

110/* inject address is 52 bits */
111#define	RAS_UMC_INJECT_ADDR_LIMIT(0x1ULL << 52)	(0x1ULL << 52)

113/* typical ECC bad page rate is 1 bad page per 100MB VRAM */
114#define RAS_BAD_PAGE_COVER(100 * 1024 * 1024ULL)              (100 * 1024 * 1024ULL)

116enum amdgpu_ras_retire_page_reservation {
AMDGPU_RAS_RETIRE_PAGE_RESERVED,
AMDGPU_RAS_RETIRE_PAGE_PENDING,
AMDGPU_RAS_RETIRE_PAGE_FAULT,
120};

122atomic_t amdgpu_ras_in_intr = ATOMIC_INIT(0)(0);

124static bool_Bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
		uint64_t addr);
126static bool_Bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
		uint64_t addr);
128#ifdef CONFIG_X86_MCE_AMD
129static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);
130struct mce_notifier_adev_list {
struct amdgpu_device *devs[MAX_GPU_INSTANCE16];
int num_gpu;
133};
134static struct mce_notifier_adev_list mce_adev_list;
135#endif

137void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool_Bool ready)
138{
if (adev && amdgpu_ras_get_context(adev))
amdgpu_ras_get_context(adev)->error_query_ready = ready;
141}

143static bool_Bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
144{
if (adev && amdgpu_ras_get_context(adev))
return amdgpu_ras_get_context(adev)->error_query_ready;

return false0;
149}

151static int amdgpu_reserve_page_direct(struct amdgpu_device *adev, uint64_t address)
152{
struct ras_err_data err_data = {0, 0, 0, NULL((void *)0)};
struct eeprom_table_record err_rec;

if ((address >= adev->gmc.mc_vram_size) ||
   (address >= RAS_UMC_INJECT_ADDR_LIMIT(0x1ULL << 52))) {
dev_warn(adev->dev,printf("drm:pid%d:%s *WARNING* " "RAS WARN: input address 0x%llx is invalid.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , address
)
         "RAS WARN: input address 0x%llx is invalid.\n",printf("drm:pid%d:%s *WARNING* " "RAS WARN: input address 0x%llx is invalid.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , address
)
         address)printf("drm:pid%d:%s *WARNING* " "RAS WARN: input address 0x%llx is invalid.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , address
);
return -EINVAL22;
}

if (amdgpu_ras_check_bad_page(adev, address)) {
dev_warn(adev->dev,printf("drm:pid%d:%s *WARNING* " "RAS WARN: 0x%llx has already been marked as bad page!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , address
)
	 "RAS WARN: 0x%llx has already been marked as bad page!\n",printf("drm:pid%d:%s *WARNING* " "RAS WARN: 0x%llx has already been marked as bad page!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , address
)
	 address)printf("drm:pid%d:%s *WARNING* " "RAS WARN: 0x%llx has already been marked as bad page!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , address
);
return 0;
}

memset(&err_rec, 0x0, sizeof(struct eeprom_table_record))__builtin_memset((&err_rec), (0x0), (sizeof(struct eeprom_table_record
)));
err_data.err_addr = &err_rec;
amdgpu_umc_fill_error_record(&err_data, address, address, 0, 0);

if (amdgpu_bad_page_threshold != 0) {
amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
			 err_data.err_addr_cnt);
amdgpu_ras_save_bad_pages(adev);
}

dev_warn(adev->dev, "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n")printf("drm:pid%d:%s *WARNING* " "WARNING: THIS IS ONLY FOR TEST PURPOSES AND WILL CORRUPT RAS EEPROM\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
dev_warn(adev->dev, "Clear EEPROM:\n")printf("drm:pid%d:%s *WARNING* " "Clear EEPROM:\n", ({struct cpu_info
 *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__);
dev_warn(adev->dev, "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n")printf("drm:pid%d:%s *WARNING* " "    echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);

return 0;
186}

188#ifdef __linux__

190static ssize_t amdgpu_ras_debugfs_read(struct file *f, char __user *buf,
			size_t size, loff_t *pos)
192{
struct ras_manager *obj = (struct ras_manager *)file_inode(f)->i_private;
struct ras_query_if info = {
.head = obj->head,
};
ssize_t s;
char val[128];

if (amdgpu_ras_query_error_status(obj->adev, &info))
return -EINVAL22;

/* Hardware counter will be reset automatically after the query on Vega20 and Arcturus */
if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2)(((11) << 16) | ((0) << 8) | (2)) &&
   obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)(((11) << 16) | ((0) << 8) | (4))) {
if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
	dev_warn(obj->adev->dev, "Failed to reset error counter and error status")printf("drm:pid%d:%s *WARNING* " "Failed to reset error counter and error status"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

s = snprintf(val, sizeof(val), "%s: %lu\n%s: %lu\n",
	"ue", info.ue_count,
	"ce", info.ce_count);
if (*pos >= s)
return 0;

s -= *pos;
s = min_t(u64, s, size)({ u64 __min_a = (s); u64 __min_b = (size); __min_a < __min_b
 ? __min_a : __min_b; });


if (copy_to_user(buf, &val[*pos], s))
return -EINVAL22;

*pos += s;

return s;
226}

228static const struct file_operations amdgpu_ras_debugfs_ops = {
.owner = THIS_MODULE((void *)0),
.read = amdgpu_ras_debugfs_read,
.write = NULL((void *)0),
.llseek = default_llseek
233};

235static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
236{
int i;

for (i = 0; i < ARRAY_SIZE(ras_block_string)(sizeof((ras_block_string)) / sizeof((ras_block_string)[0])); i++) {
*block_id = i;
if (strcmp(name, ras_block_string[i]) == 0)
	return 0;
}
return -EINVAL22;
245}

247static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
const char __user *buf, size_t size,
loff_t *pos, struct ras_debug_if *data)
250{
ssize_t s = min_t(u64, 64, size)({ u64 __min_a = (64); u64 __min_b = (size); __min_a < __min_b
 ? __min_a : __min_b; });
char str[65];
char block_name[33];
char err[9] = "ue";
int op = -1;
int block_id;
uint32_t sub_block;
u64 address, value;

if (*pos)
return -EINVAL22;
*pos = size;

memset(str, 0, sizeof(str))__builtin_memset((str), (0), (sizeof(str)));
memset(data, 0, sizeof(*data))__builtin_memset((data), (0), (sizeof(*data)));

if (copy_from_user(str, buf, s))
return -EINVAL22;

if (sscanf(str, "disable %32s", block_name) == 1)
op = 0;
else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
op = 1;
else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
op = 2;
else if (strstr(str, "retire_page") != NULL((void *)0))
op = 3;
else if (str[0] && str[1] && str[2] && str[3])
/* ascii string, but commands are not matched. */
return -EINVAL22;

if (op != -1) {
if (op == 3) {
	if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
	    sscanf(str, "%*s %llu", &address) != 1)
		return -EINVAL22;

	data->op = op;
	data->inject.address = address;

	return 0;
}

if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
	return -EINVAL22;

data->head.block = block_id;
/* only ue and ce errors are supported */
if (!memcmp("ue", err, 2)__builtin_memcmp(("ue"), (err), (2)))
	data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
else if (!memcmp("ce", err, 2)__builtin_memcmp(("ce"), (err), (2)))
	data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
else
	return -EINVAL22;

data->op = op;

if (op == 2) {
	if (sscanf(str, "%*s %*s %*s 0x%x 0x%llx 0x%llx",
		   &sub_block, &address, &value) != 3 &&
	    sscanf(str, "%*s %*s %*s %u %llu %llu",
		   &sub_block, &address, &value) != 3)
		return -EINVAL22;
	data->head.sub_block_index = sub_block;
	data->inject.address = address;
	data->inject.value = value;
}
} else {
if (size < sizeof(*data))
	return -EINVAL22;

if (copy_from_user(data, buf, sizeof(*data)))
	return -EINVAL22;
}

return 0;
327}

329/**
* DOC: AMDGPU RAS debugfs control interface
*
* The control interface accepts struct ras_debug_if which has two members.
*
* First member: ras_debug_if::head or ras_debug_if::inject.
*
* head is used to indicate which IP block will be under control.
*
* head has four members, they are block, type, sub_block_index, name.
* block: which IP will be under control.
* type: what kind of error will be enabled/disabled/injected.
* sub_block_index: some IPs have subcomponets. say, GFX, sDMA.
* name: the name of IP.
*
* inject has two more members than head, they are address, value.
* As their names indicate, inject operation will write the
* value to the address.
*
* The second member: struct ras_debug_if::op.
* It has three kinds of operations.
*
* - 0: disable RAS on the block. Take ::head as its data.
* - 1: enable RAS on the block. Take ::head as its data.
* - 2: inject errors on the block. Take ::inject as its data.
*
* How to use the interface?
*
* In a program
*
* Copy the struct ras_debug_if in your code and initialize it.
* Write the struct to the control interface.
*
* From shell
*
* .. code-block:: bash
*
*	echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
*	echo "enable  <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
*	echo "inject  <block> <error> <sub-block> <address> <value> > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
*
* Where N, is the card which you want to affect.
*
* "disable" requires only the block.
* "enable" requires the block and error type.
* "inject" requires the block, error type, address, and value.
*
* The block is one of: umc, sdma, gfx, etc.
*	see ras_block_string[] for details
*
* The error type is one of: ue, ce, where,
*	ue is multi-uncorrectable
*	ce is single-correctable
*
* The sub-block is a the sub-block index, pass 0 if there is no sub-block.
* The address and value are hexadecimal numbers, leading 0x is optional.
*
* For instance,
*
* .. code-block:: bash
*
*	echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
*	echo inject umc ce 0 0 0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
*	echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
*
* How to check the result of the operation?
*
* To check disable/enable, see "ras" features at,
* /sys/class/drm/card[0/1/2...]/device/ras/features
*
* To check inject, see the corresponding error count at,
* /sys/class/drm/card[0/1/2...]/device/ras/[gfx|sdma|umc|...]_err_count
*
* .. note::
*	Operations are only allowed on blocks which are supported.
*	Check the "ras" mask at /sys/module/amdgpu/parameters/ras_mask
*	to see which blocks support RAS on a particular asic.
*
*/
408static ssize_t amdgpu_ras_debugfs_ctrl_write(struct file *f,
			     const char __user *buf,
			     size_t size, loff_t *pos)
411{
struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
struct ras_debug_if data;
int ret = 0;

if (!amdgpu_ras_get_error_query_ready(adev)) {
dev_warn(adev->dev, "RAS WARN: error injection "printf("drm:pid%d:%s *WARNING* " "RAS WARN: error injection "
 "currently inaccessible\n", ({struct cpu_info *__ci; asm volatile
("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct
 cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid
, __func__)
		"currently inaccessible\n")printf("drm:pid%d:%s *WARNING* " "RAS WARN: error injection "
 "currently inaccessible\n", ({struct cpu_info *__ci; asm volatile
("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct
 cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid
, __func__);
return size;
}

ret = amdgpu_ras_debugfs_ctrl_parse_data(f, buf, size, pos, &data);
if (ret)
return ret;

if (data.op == 3) {
ret = amdgpu_reserve_page_direct(adev, data.inject.address);
if (!ret)
	return size;
else
	return ret;
}

if (!amdgpu_ras_is_supported(adev, data.head.block))
return -EINVAL22;

switch (data.op) {
case 0:
ret = amdgpu_ras_feature_enable(adev, &data.head, 0);
break;
case 1:
ret = amdgpu_ras_feature_enable(adev, &data.head, 1);
break;
case 2:
if ((data.inject.address >= adev->gmc.mc_vram_size) ||
    (data.inject.address >= RAS_UMC_INJECT_ADDR_LIMIT(0x1ULL << 52))) {
	dev_warn(adev->dev, "RAS WARN: input address "printf("drm:pid%d:%s *WARNING* " "RAS WARN: input address " "0x%llx is invalid."
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , data.inject
.address)
			"0x%llx is invalid.",printf("drm:pid%d:%s *WARNING* " "RAS WARN: input address " "0x%llx is invalid."
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , data.inject
.address)
			data.inject.address)printf("drm:pid%d:%s *WARNING* " "RAS WARN: input address " "0x%llx is invalid."
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , data.inject
.address);
	ret = -EINVAL22;
	break;
}

/* umc ce/ue error injection for a bad page is not allowed */
if ((data.head.block == AMDGPU_RAS_BLOCK__UMC) &&
    amdgpu_ras_check_bad_page(adev, data.inject.address)) {
	dev_warn(adev->dev, "RAS WARN: inject: 0x%llx has "printf("drm:pid%d:%s *WARNING* " "RAS WARN: inject: 0x%llx has "
 "already been marked as bad!\n", ({struct cpu_info *__ci; asm
 volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__ , data.inject.address)
		 "already been marked as bad!\n",printf("drm:pid%d:%s *WARNING* " "RAS WARN: inject: 0x%llx has "
 "already been marked as bad!\n", ({struct cpu_info *__ci; asm
 volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__ , data.inject.address)
		 data.inject.address)printf("drm:pid%d:%s *WARNING* " "RAS WARN: inject: 0x%llx has "
 "already been marked as bad!\n", ({struct cpu_info *__ci; asm
 volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__ , data.inject.address);
	break;
}

/* data.inject.address is offset instead of absolute gpu address */
ret = amdgpu_ras_error_inject(adev, &data.inject);
break;
default:
ret = -EINVAL22;
break;
}

if (ret)
return ret;

return size;
475}

477/**
* DOC: AMDGPU RAS debugfs EEPROM table reset interface
*
* Some boards contain an EEPROM which is used to persistently store a list of
* bad pages which experiences ECC errors in vram.  This interface provides
* a way to reset the EEPROM, e.g., after testing error injection.
*
* Usage:
*
* .. code-block:: bash
*
*	echo 1 > ../ras/ras_eeprom_reset
*
* will reset EEPROM table to 0 entries.
*
*/
493static ssize_t amdgpu_ras_debugfs_eeprom_write(struct file *f,
			       const char __user *buf,
			       size_t size, loff_t *pos)
496{
struct amdgpu_device *adev =
(struct amdgpu_device *)file_inode(f)->i_private;
int ret;

ret = amdgpu_ras_eeprom_reset_table(
&(amdgpu_ras_get_context(adev)->eeprom_control));

if (!ret) {
/* Something was written to EEPROM.
 */
amdgpu_ras_get_context(adev)->flags = RAS_DEFAULT_FLAGS((0x1 << 0));
return size;
} else {
return ret;
}
512}

514static const struct file_operations amdgpu_ras_debugfs_ctrl_ops = {
.owner = THIS_MODULE((void *)0),
.read = NULL((void *)0),
.write = amdgpu_ras_debugfs_ctrl_write,
.llseek = default_llseek
519};

521static const struct file_operations amdgpu_ras_debugfs_eeprom_ops = {
.owner = THIS_MODULE((void *)0),
.read = NULL((void *)0),
.write = amdgpu_ras_debugfs_eeprom_write,
.llseek = default_llseek
526};

528/**
* DOC: AMDGPU RAS sysfs Error Count Interface
*
* It allows the user to read the error count for each IP block on the gpu through
* /sys/class/drm/card[0/1/2...]/device/ras/[gfx/sdma/...]_err_count
*
* It outputs the multiple lines which report the uncorrected (ue) and corrected
* (ce) error counts.
*
* The format of one line is below,
*
* [ce|ue]: count
*
* Example:
*
* .. code-block:: bash
*
*	ue: 0
*	ce: 1
*
*/
549static ssize_t amdgpu_ras_sysfs_read(struct device *dev,
struct device_attribute *attr, char *buf)
551{
struct ras_manager *obj = container_of(attr, struct ras_manager, sysfs_attr)({ const __typeof( ((struct ras_manager *)0)->sysfs_attr )
 *__mptr = (attr); (struct ras_manager *)( (char *)__mptr - __builtin_offsetof
(struct ras_manager, sysfs_attr) );});
struct ras_query_if info = {
.head = obj->head,
};

if (!amdgpu_ras_get_error_query_ready(obj->adev))
return sysfs_emit(buf, "Query currently inaccessible\n");

if (amdgpu_ras_query_error_status(obj->adev, &info))
return -EINVAL22;

if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2)(((11) << 16) | ((0) << 8) | (2)) &&
   obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)(((11) << 16) | ((0) << 8) | (4))) {
if (amdgpu_ras_reset_error_status(obj->adev, info.head.block))
	dev_warn(obj->adev->dev, "Failed to reset error counter and error status")printf("drm:pid%d:%s *WARNING* " "Failed to reset error counter and error status"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

return sysfs_emit(buf, "%s: %lu\n%s: %lu\n", "ue", info.ue_count,
	  "ce", info.ce_count);
571}

573#endif /* __linux__ */

575/* obj begin */

577#define get_obj(obj)do { (obj)->use++; } while (0) do { (obj)->use++; } while (0)
578#define alive_obj(obj)((obj)->use) ((obj)->use)

580static inline void put_obj(struct ras_manager *obj)
581{
if (obj && (--obj->use == 0))
list_del(&obj->node);
if (obj && (obj->use < 0))
DRM_ERROR("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str(&obj->head))__drm_err("RAS ERROR: Unbalance obj(%s) use\n", get_ras_block_str
(&obj->head));
586}

588/* make one obj and return it. */
589static struct ras_manager *amdgpu_ras_create_obj(struct amdgpu_device *adev,
struct ras_common_if *head)
591{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;

if (!adev->ras_enabled || !con)
return NULL((void *)0);

if (head->block >= AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST)
return NULL((void *)0);

if (head->block == AMDGPU_RAS_BLOCK__MCA) {
if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
	return NULL((void *)0);

obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
} else
obj = &con->objs[head->block];

/* already exist. return obj? */
if (alive_obj(obj)((obj)->use))
return NULL((void *)0);

obj->head = *head;
obj->adev = adev;
list_add(&obj->node, &con->head);
get_obj(obj)do { (obj)->use++; } while (0);

return obj;
619}

621/* return an obj equal to head, or the first when head is NULL */
622struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
struct ras_common_if *head)
624{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;
int i;

if (!adev->ras_enabled || !con)
return NULL((void *)0);

if (head) {
if (head->block >= AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST)
	return NULL((void *)0);

if (head->block == AMDGPU_RAS_BLOCK__MCA) {
	if (head->sub_block_index >= AMDGPU_RAS_MCA_BLOCK__LAST)
		return NULL((void *)0);

	obj = &con->objs[AMDGPU_RAS_BLOCK__LAST + head->sub_block_index];
} else
	obj = &con->objs[head->block];

if (alive_obj(obj)((obj)->use))
	return obj;
} else {
for (i = 0; i < AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST + AMDGPU_RAS_MCA_BLOCK_COUNTAMDGPU_RAS_MCA_BLOCK__LAST; i++) {
	obj = &con->objs[i];
	if (alive_obj(obj)((obj)->use))
		return obj;
}
}

return NULL((void *)0);
655}
656/* obj end */

658/* feature ctl begin */
659static int amdgpu_ras_is_feature_allowed(struct amdgpu_device *adev,
			 struct ras_common_if *head)
661{
return adev->ras_hw_enabled & BIT(head->block)(1UL << (head->block));
663}

665static int amdgpu_ras_is_feature_enabled(struct amdgpu_device *adev,
struct ras_common_if *head)
667{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

return con->features & BIT(head->block)(1UL << (head->block));
671}

673/*
* if obj is not created, then create one.
* set feature enable flag.
*/
677static int __amdgpu_ras_feature_enable(struct amdgpu_device *adev,
struct ras_common_if *head, int enable)
679{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);

/* If hardware does not support ras, then do not create obj.
* But if hardware support ras, we can create the obj.
* Ras framework checks con->hw_supported to see if it need do
* corresponding initialization.
* IP checks con->support to see if it need disable ras.
*/
if (!amdgpu_ras_is_feature_allowed(adev, head))
return 0;

if (enable) {
if (!obj) {
	obj = amdgpu_ras_create_obj(adev, head);
	if (!obj)
		return -EINVAL22;
} else {
	/* In case we create obj somewhere else */
	get_obj(obj)do { (obj)->use++; } while (0);
}
con->features |= BIT(head->block)(1UL << (head->block));
} else {
if (obj && amdgpu_ras_is_feature_enabled(adev, head)) {
	con->features &= ~BIT(head->block)(1UL << (head->block));
	put_obj(obj);
}
}

return 0;
710}

712/* wrapper of psp_ras_enable_features */
713int amdgpu_ras_feature_enable(struct amdgpu_device *adev,
struct ras_common_if *head, bool_Bool enable)
715{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
15
←
Calling 'amdgpu_ras_get_context'→
18
←
Returning from 'amdgpu_ras_get_context'→
union ta_ras_cmd_input *info;
19
←
'info' declared without an initial value→
int ret;

if (!con19.1
'con' is non-null
)
20
←
Taking false branch→
return -EINVAL22;

if (head->block == AMDGPU_RAS_BLOCK__GFX) {
21
←
Assuming field 'block' is not equal to AMDGPU_RAS_BLOCK__GFX→
info = kzalloc(sizeof(union ta_ras_cmd_input), GFP_KERNEL(0x0001 | 0x0004));
if (!info)
	return -ENOMEM12;

if (!enable) {
	info->disable_features = (struct ta_ras_disable_features_input) {
		.block_id =  amdgpu_ras_block_to_ta(head->block),
		.error_type = amdgpu_ras_error_to_ta(head->type),
	};
} else {
	info->enable_features = (struct ta_ras_enable_features_input) {
		.block_id =  amdgpu_ras_block_to_ta(head->block),
		.error_type = amdgpu_ras_error_to_ta(head->type),
	};
}
}

/* Do not enable if it is not allowed. */
WARN_ON(enable && !amdgpu_ras_is_feature_allowed(adev, head))({ int __ret = !!(enable && !amdgpu_ras_is_feature_allowed
(adev, head)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "enable && !amdgpu_ras_is_feature_allowed(adev, head)"
, "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c", 742); __builtin_expect
(!!(__ret), 0); });
22
←
Taking false branch→
23
←
Taking false branch→

/* Only enable ras feature operation handle on host side */
if (head->block23.1
Field 'block' is not equal to AMDGPU_RAS_BLOCK__GFX
 == AMDGPU_RAS_BLOCK__GFX &&
!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) &&
!amdgpu_ras_intr_triggered()) {
ret = psp_ras_enable_features(&adev->psp, info, enable);
if (ret) {
	dev_err(adev->dev, "ras %s %s failed poison:%d ret:%d\n",printf("drm:pid%d:%s *ERROR* " "ras %s %s failed poison:%d ret:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , enable
 ? "enable":"disable", get_ras_block_str(head), amdgpu_ras_is_poison_mode_supported
(adev), ret)
		enable ? "enable":"disable",printf("drm:pid%d:%s *ERROR* " "ras %s %s failed poison:%d ret:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , enable
 ? "enable":"disable", get_ras_block_str(head), amdgpu_ras_is_poison_mode_supported
(adev), ret)
		get_ras_block_str(head),printf("drm:pid%d:%s *ERROR* " "ras %s %s failed poison:%d ret:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , enable
 ? "enable":"disable", get_ras_block_str(head), amdgpu_ras_is_poison_mode_supported
(adev), ret)
		amdgpu_ras_is_poison_mode_supported(adev), ret)printf("drm:pid%d:%s *ERROR* " "ras %s %s failed poison:%d ret:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , enable
 ? "enable":"disable", get_ras_block_str(head), amdgpu_ras_is_poison_mode_supported
(adev), ret);
	goto out;
}
}

/* setup the obj */
__amdgpu_ras_feature_enable(adev, head, enable);
ret = 0;
761out:
if (head->block == AMDGPU_RAS_BLOCK__GFX)
24
←
Assuming field 'block' is equal to AMDGPU_RAS_BLOCK__GFX→
25
←
Taking true branch→
kfree(info);
26
←
1st function call argument is an uninitialized value
return ret;
765}

767/* Only used in device probe stage and called only once. */
768int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev,
struct ras_common_if *head, bool_Bool enable)
770{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int ret;

if (!con)
return -EINVAL22;

if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS(0x1 << 0)) {
if (enable) {
	/* There is no harm to issue a ras TA cmd regardless of
	 * the currecnt ras state.
	 * If current state == target state, it will do nothing
	 * But sometimes it requests driver to reset and repost
	 * with error code -EAGAIN.
	 */
	ret = amdgpu_ras_feature_enable(adev, head, 1);
	/* With old ras TA, we might fail to enable ras.
	 * Log it and just setup the object.
	 * TODO need remove this WA in the future.
	 */
	if (ret == -EINVAL22) {
		ret = __amdgpu_ras_feature_enable(adev, head, 1);
		if (!ret)
			dev_info(adev->dev,do { } while(0)
				"RAS INFO: %s setup object\n",do { } while(0)
				get_ras_block_str(head))do { } while(0);
	}
} else {
	/* setup the object then issue a ras TA disable cmd.*/
	ret = __amdgpu_ras_feature_enable(adev, head, 1);
	if (ret)
		return ret;

	/* gfx block ras dsiable cmd must send to ras-ta */
	if (head->block == AMDGPU_RAS_BLOCK__GFX)
		con->features |= BIT(head->block)(1UL << (head->block));

	ret = amdgpu_ras_feature_enable(adev, head, 0);

	/* clean gfx block ras features flag */
	if (adev->ras_enabled && head->block == AMDGPU_RAS_BLOCK__GFX)
		con->features &= ~BIT(head->block)(1UL << (head->block));
}
} else
ret = amdgpu_ras_feature_enable(adev, head, enable);

return ret;
817}

819static int amdgpu_ras_disable_all_features(struct amdgpu_device *adev,
bool_Bool bypass)
821{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj, *tmp;

list_for_each_entry_safe(obj, tmp, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}), tmp = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = (obj->node.next); (__typeof(*obj) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*obj), node) );}); &obj->
node != (&con->head); obj = tmp, tmp = ({ const __typeof
( ((__typeof(*tmp) *)0)->node ) *__mptr = (tmp->node.next
); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*tmp), node) );})) {
12
←
Loop condition is true.  Entering loop body→
/* bypass psp.
 * aka just release the obj and corresponding flags
 */
if (bypass12.1
'bypass' is false
) {
13
←
Taking false branch→
	if (__amdgpu_ras_feature_enable(adev, &obj->head, 0))
		break;
} else {
	if (amdgpu_ras_feature_enable(adev, &obj->head, 0))
14
←
Calling 'amdgpu_ras_feature_enable'→
		break;
}
}

return con->features;
839}

841static int amdgpu_ras_enable_all_features(struct amdgpu_device *adev,
bool_Bool bypass)
843{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int i;
const enum amdgpu_ras_error_type default_ras_type = AMDGPU_RAS_ERROR__NONE;

for (i = 0; i < AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST; i++) {
struct ras_common_if head = {
	.block = i,
	.type = default_ras_type,
	.sub_block_index = 0,
};

if (i == AMDGPU_RAS_BLOCK__MCA)
	continue;

if (bypass) {
	/*
	 * bypass psp. vbios enable ras for us.
	 * so just create the obj
	 */
	if (__amdgpu_ras_feature_enable(adev, &head, 1))
		break;
} else {
	if (amdgpu_ras_feature_enable(adev, &head, 1))
		break;
}
}

for (i = 0; i < AMDGPU_RAS_MCA_BLOCK_COUNTAMDGPU_RAS_MCA_BLOCK__LAST; i++) {
struct ras_common_if head = {
	.block = AMDGPU_RAS_BLOCK__MCA,
	.type = default_ras_type,
	.sub_block_index = i,
};

if (bypass) {
	/*
	 * bypass psp. vbios enable ras for us.
	 * so just create the obj
	 */
	if (__amdgpu_ras_feature_enable(adev, &head, 1))
		break;
} else {
	if (amdgpu_ras_feature_enable(adev, &head, 1))
		break;
}
}

return con->features;
892}
893/* feature ctl end */

895static int amdgpu_ras_block_match_default(struct amdgpu_ras_block_object *block_obj,
enum amdgpu_ras_block block)
897{
if (!block_obj)
return -EINVAL22;

if (block_obj->ras_comm.block == block)
return 0;

return -EINVAL22;
905}

907static struct amdgpu_ras_block_object *amdgpu_ras_get_ras_block(struct amdgpu_device *adev,
			enum amdgpu_ras_block block, uint32_t sub_block_index)
909{
struct amdgpu_ras_block_list *node, *tmp;
struct amdgpu_ras_block_object *obj;

if (block >= AMDGPU_RAS_BLOCK__LAST)
return NULL((void *)0);

if (!amdgpu_ras_is_supported(adev, block))
return NULL((void *)0);

list_for_each_entry_safe(node, tmp, &adev->ras_list, node)for (node = ({ const __typeof( ((__typeof(*node) *)0)->node
 ) *__mptr = ((&adev->ras_list)->next); (__typeof(*
node) *)( (char *)__mptr - __builtin_offsetof(__typeof(*node)
, node) );}), tmp = ({ const __typeof( ((__typeof(*node) *)0)
->node ) *__mptr = (node->node.next); (__typeof(*node) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*node), node)
 );}); &node->node != (&adev->ras_list); node =
 tmp, tmp = ({ const __typeof( ((__typeof(*tmp) *)0)->node
 ) *__mptr = (tmp->node.next); (__typeof(*tmp) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*tmp), node) );})) {
if (!node->ras_obj) {
	dev_warn(adev->dev, "Warning: abnormal ras list node.\n")printf("drm:pid%d:%s *WARNING* " "Warning: abnormal ras list node.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
	continue;
}

obj = node->ras_obj;
if (obj->ras_block_match) {
	if (obj->ras_block_match(obj, block, sub_block_index) == 0)
		return obj;
} else {
	if (amdgpu_ras_block_match_default(obj, block) == 0)
		return obj;
}
}

return NULL((void *)0);
936}

938static void amdgpu_ras_get_ecc_info(struct amdgpu_device *adev, struct ras_err_data *err_data)
939{
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
int ret = 0;

/*
* choosing right query method according to
* whether smu support query error information
*/
ret = amdgpu_dpm_get_ecc_info(adev, (void *)&(ras->umc_ecc));
if (ret == -EOPNOTSUPP45) {
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
	adev->umc.ras->ras_block.hw_ops->query_ras_error_count)
	adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data);

/* umc query_ras_error_address is also responsible for clearing
 * error status
 */
if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops &&
    adev->umc.ras->ras_block.hw_ops->query_ras_error_address)
	adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, err_data);
} else if (!ret) {
if (adev->umc.ras &&
	adev->umc.ras->ecc_info_query_ras_error_count)
	adev->umc.ras->ecc_info_query_ras_error_count(adev, err_data);

if (adev->umc.ras &&
	adev->umc.ras->ecc_info_query_ras_error_address)
	adev->umc.ras->ecc_info_query_ras_error_address(adev, err_data);
}
968}

970/* query/inject/cure begin */
971int amdgpu_ras_query_error_status(struct amdgpu_device *adev,
		  struct ras_query_if *info)
973{
struct amdgpu_ras_block_object *block_obj = NULL((void *)0);
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
struct ras_err_data err_data = {0, 0, 0, NULL((void *)0)};

if (!obj)
return -EINVAL22;

if (info->head.block == AMDGPU_RAS_BLOCK__UMC) {
amdgpu_ras_get_ecc_info(adev, &err_data);
} else {
block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, 0);
if (!block_obj || !block_obj->hw_ops)   {
	dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",do { } while(0)
		     get_ras_block_str(&info->head))do { } while(0);
	return -EINVAL22;
}

if (block_obj->hw_ops->query_ras_error_count)
	block_obj->hw_ops->query_ras_error_count(adev, &err_data);

if ((info->head.block == AMDGPU_RAS_BLOCK__SDMA) ||
    (info->head.block == AMDGPU_RAS_BLOCK__GFX) ||
    (info->head.block == AMDGPU_RAS_BLOCK__MMHUB)) {
		if (block_obj->hw_ops->query_ras_error_status)
			block_obj->hw_ops->query_ras_error_status(adev);
	}
}

obj->err_data.ue_count += err_data.ue_count;
obj->err_data.ce_count += err_data.ce_count;

info->ue_count = obj->err_data.ue_count;
info->ce_count = obj->err_data.ce_count;

if (err_data.ce_count) {
if (adev->smuio.funcs &&
    adev->smuio.funcs->get_socket_id &&
    adev->smuio.funcs->get_die_id) {
	dev_info(adev->dev, "socket: %d, die: %d "do { } while(0)
			"%ld correctable hardware errors "do { } while(0)
			"detected in %s block, no user "do { } while(0)
			"action is needed.\n",do { } while(0)
			adev->smuio.funcs->get_socket_id(adev),do { } while(0)
			adev->smuio.funcs->get_die_id(adev),do { } while(0)
			obj->err_data.ce_count,do { } while(0)
			get_ras_block_str(&info->head))do { } while(0);
} else {
	dev_info(adev->dev, "%ld correctable hardware errors "do { } while(0)
			"detected in %s block, no user "do { } while(0)
			"action is needed.\n",do { } while(0)
			obj->err_data.ce_count,do { } while(0)
			get_ras_block_str(&info->head))do { } while(0);
}
}
if (err_data.ue_count) {
if (adev->smuio.funcs &&
    adev->smuio.funcs->get_socket_id &&
    adev->smuio.funcs->get_die_id) {
	dev_info(adev->dev, "socket: %d, die: %d "do { } while(0)
			"%ld uncorrectable hardware errors "do { } while(0)
			"detected in %s block\n",do { } while(0)
			adev->smuio.funcs->get_socket_id(adev),do { } while(0)
			adev->smuio.funcs->get_die_id(adev),do { } while(0)
			obj->err_data.ue_count,do { } while(0)
			get_ras_block_str(&info->head))do { } while(0);
} else {
	dev_info(adev->dev, "%ld uncorrectable hardware errors "do { } while(0)
			"detected in %s block\n",do { } while(0)
			obj->err_data.ue_count,do { } while(0)
			get_ras_block_str(&info->head))do { } while(0);
}
}

return 0;
1048}

1050int amdgpu_ras_reset_error_status(struct amdgpu_device *adev,
enum amdgpu_ras_block block)
1052{
struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev, block, 0);

if (!amdgpu_ras_is_supported(adev, block))
return -EINVAL22;

if (!block_obj || !block_obj->hw_ops)   {
dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",do { } while(0)
	     ras_block_str(block))do { } while(0);
return -EINVAL22;
}

if (block_obj->hw_ops->reset_ras_error_count)
block_obj->hw_ops->reset_ras_error_count(adev);

if ((block == AMDGPU_RAS_BLOCK__GFX) ||
   (block == AMDGPU_RAS_BLOCK__MMHUB)) {
if (block_obj->hw_ops->reset_ras_error_status)
	block_obj->hw_ops->reset_ras_error_status(adev);
}

return 0;
1074}

1076/* wrapper of psp_ras_trigger_error */
1077int amdgpu_ras_error_inject(struct amdgpu_device *adev,
struct ras_inject_if *info)
1079{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
struct ta_ras_trigger_error_input block_info = {
.block_id =  amdgpu_ras_block_to_ta(info->head.block),
.inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
.sub_block_index = info->head.sub_block_index,
.address = info->address,
.value = info->value,
};
int ret = -EINVAL22;
struct amdgpu_ras_block_object *block_obj = amdgpu_ras_get_ras_block(adev,
					info->head.block,
					info->head.sub_block_index);

if (!obj)
return -EINVAL22;

if (!block_obj || !block_obj->hw_ops)	{
dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",do { } while(0)
	     get_ras_block_str(&info->head))do { } while(0);
return -EINVAL22;
}

/* Calculate XGMI relative offset */
if (adev->gmc.xgmi.num_physical_nodes > 1) {
block_info.address =
	amdgpu_xgmi_get_relative_phy_addr(adev,
					  block_info.address);
}

if (info->head.block == AMDGPU_RAS_BLOCK__GFX) {
if (block_obj->hw_ops->ras_error_inject)
	ret = block_obj->hw_ops->ras_error_inject(adev, info);
} else {
/* If defined special ras_error_inject(e.g: xgmi), implement special ras_error_inject */
if (block_obj->hw_ops->ras_error_inject)
	ret = block_obj->hw_ops->ras_error_inject(adev, &block_info);
else  /*If not defined .ras_error_inject, use default ras_error_inject*/
	ret = psp_ras_trigger_error(&adev->psp, &block_info);
}

if (ret)
dev_err(adev->dev, "ras inject %s failed %d\n",printf("drm:pid%d:%s *ERROR* " "ras inject %s failed %d\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , get_ras_block_str
(&info->head), ret)
	get_ras_block_str(&info->head), ret)printf("drm:pid%d:%s *ERROR* " "ras inject %s failed %d\n", (
{struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , get_ras_block_str
(&info->head), ret);

return ret;
1125}

1127/**
* amdgpu_ras_query_error_count -- Get error counts of all IPs
* @adev: pointer to AMD GPU device
* @ce_count: pointer to an integer to be set to the count of correctible errors.
* @ue_count: pointer to an integer to be set to the count of uncorrectible
* errors.
*
* If set, @ce_count or @ue_count, count and return the corresponding
* error counts in those integer pointers. Return 0 if the device
* supports RAS. Return -EOPNOTSUPP if the device doesn't support RAS.
*/
1138int amdgpu_ras_query_error_count(struct amdgpu_device *adev,
		 unsigned long *ce_count,
		 unsigned long *ue_count)
1141{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;
unsigned long ce, ue;

if (!adev->ras_enabled || !con)
return -EOPNOTSUPP45;

/* Don't count since no reporting.
*/
if (!ce_count && !ue_count)
return 0;

ce = 0;
ue = 0;
list_for_each_entry(obj, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}); &obj->node != (&con->head); obj = ({ const
 __typeof( ((__typeof(*obj) *)0)->node ) *__mptr = (obj->
node.next); (__typeof(*obj) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*obj), node) );})) {
struct ras_query_if info = {
	.head = obj->head,
};
int res;

res = amdgpu_ras_query_error_status(adev, &info);
if (res)
	return res;

if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2)(((11) << 16) | ((0) << 8) | (2)) &&
    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)(((11) << 16) | ((0) << 8) | (4))) {
	if (amdgpu_ras_reset_error_status(adev, info.head.block))
		dev_warn(adev->dev, "Failed to reset error counter and error status")printf("drm:pid%d:%s *WARNING* " "Failed to reset error counter and error status"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}

ce += info.ce_count;
ue += info.ue_count;
}

if (ce_count)
*ce_count = ce;

if (ue_count)
*ue_count = ue;

return 0;
1183}
1184/* query/inject/cure end */

1186#ifdef __linux__

1188/* sysfs begin */

1190static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
struct ras_badpage **bps, unsigned int *count);

1193static char *amdgpu_ras_badpage_flags_str(unsigned int flags)
1194{
switch (flags) {
case AMDGPU_RAS_RETIRE_PAGE_RESERVED:
return "R";
case AMDGPU_RAS_RETIRE_PAGE_PENDING:
return "P";
case AMDGPU_RAS_RETIRE_PAGE_FAULT:
default:
return "F";
}
1204}

1206/**
* DOC: AMDGPU RAS sysfs gpu_vram_bad_pages Interface
*
* It allows user to read the bad pages of vram on the gpu through
* /sys/class/drm/card[0/1/2...]/device/ras/gpu_vram_bad_pages
*
* It outputs multiple lines, and each line stands for one gpu page.
*
* The format of one line is below,
* gpu pfn : gpu page size : flags
*
* gpu pfn and gpu page size are printed in hex format.
* flags can be one of below character,
*
* R: reserved, this gpu page is reserved and not able to use.
*
* P: pending for reserve, this gpu page is marked as bad, will be reserved
* in next window of page_reserve.
*
* F: unable to reserve. this gpu page can't be reserved due to some reasons.
*
* Examples:
*
* .. code-block:: bash
*
*	0x00000001 : 0x00001000 : R
*	0x00000002 : 0x00001000 : P
*
*/

1236static ssize_t amdgpu_ras_sysfs_badpages_read(struct file *f,
struct kobject *kobj, struct bin_attribute *attr,
char *buf, loff_t ppos, size_t count)
1239{
struct amdgpu_ras *con =
container_of(attr, struct amdgpu_ras, badpages_attr)({ const __typeof( ((struct amdgpu_ras *)0)->badpages_attr
 ) *__mptr = (attr); (struct amdgpu_ras *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_ras, badpages_attr) );});
struct amdgpu_device *adev = con->adev;
const unsigned int element_size =
sizeof("0xabcdabcd : 0x12345678 : R\n") - 1;
unsigned int start = div64_ul(ppos + element_size - 1, element_size);
unsigned int end = div64_ul(ppos + count - 1, element_size);
ssize_t s = 0;
struct ras_badpage *bps = NULL((void *)0);
unsigned int bps_count = 0;

memset(buf, 0, count)__builtin_memset((buf), (0), (count));

if (amdgpu_ras_badpages_read(adev, &bps, &bps_count))
return 0;

for (; start < end && start < bps_count; start++)
s += scnprintf(&buf[s], element_size + 1,snprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n"
, bps[start].bp, bps[start].size, amdgpu_ras_badpage_flags_str
(bps[start].flags))
		"0x%08x : 0x%08x : %1s\n",snprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n"
, bps[start].bp, bps[start].size, amdgpu_ras_badpage_flags_str
(bps[start].flags))
		bps[start].bp,snprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n"
, bps[start].bp, bps[start].size, amdgpu_ras_badpage_flags_str
(bps[start].flags))
		bps[start].size,snprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n"
, bps[start].bp, bps[start].size, amdgpu_ras_badpage_flags_str
(bps[start].flags))
		amdgpu_ras_badpage_flags_str(bps[start].flags))snprintf(&buf[s], element_size + 1, "0x%08x : 0x%08x : %1s\n"
, bps[start].bp, bps[start].size, amdgpu_ras_badpage_flags_str
(bps[start].flags));

kfree(bps);

return s;
1266}

1268static ssize_t amdgpu_ras_sysfs_features_read(struct device *dev,
struct device_attribute *attr, char *buf)
1270{
struct amdgpu_ras *con =
container_of(attr, struct amdgpu_ras, features_attr)({ const __typeof( ((struct amdgpu_ras *)0)->features_attr
 ) *__mptr = (attr); (struct amdgpu_ras *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_ras, features_attr) );});

return scnprintf(buf, PAGE_SIZE, "feature mask: 0x%x\n", con->features)snprintf(buf, (1 << 12), "feature mask: 0x%x\n", con->
features);
1275}

1277static void amdgpu_ras_sysfs_remove_bad_page_node(struct amdgpu_device *adev)
1278{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

if (adev->dev->kobj.sd)
sysfs_remove_file_from_group(&adev->dev->kobj,
		&con->badpages_attr.attr,
		RAS_FS_NAME);
1285}

1287static int amdgpu_ras_sysfs_remove_feature_node(struct amdgpu_device *adev)
1288{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct attribute *attrs[] = {
&con->features_attr.attr,
NULL((void *)0)
};
struct attribute_group group = {
.name = RAS_FS_NAME,
.attrs = attrs,
};

if (adev->dev->kobj.sd)
sysfs_remove_group(&adev->dev->kobj, &group);

return 0;
1303}

1305#endif /* __linux__ */

1307int amdgpu_ras_sysfs_create(struct amdgpu_device *adev,
struct ras_common_if *head)
1309{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);

if (!obj || obj->attr_inuse)
return -EINVAL22;

STUB()do { printf("%s: stub\n", __func__); } while(0);
return -ENOSYS78;
1317#ifdef notyet
get_obj(obj)do { (obj)->use++; } while (0);

snprintf(obj->fs_data.sysfs_name, sizeof(obj->fs_data.sysfs_name),
"%s_err_count", head->name);

obj->sysfs_attr = (struct device_attribute){
.attr = {
	.name = obj->fs_data.sysfs_name,
	.mode = S_IRUGO,
},
	.show = amdgpu_ras_sysfs_read,
};
sysfs_attr_init(&obj->sysfs_attr.attr);

if (sysfs_add_file_to_group(&adev->dev->kobj,
		&obj->sysfs_attr.attr,
		RAS_FS_NAME)) {
put_obj(obj);
return -EINVAL22;
}

obj->attr_inuse = 1;

return 0;
1342#endif
1343}

1345int amdgpu_ras_sysfs_remove(struct amdgpu_device *adev,
struct ras_common_if *head)
1347{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);

if (!obj || !obj->attr_inuse)
return -EINVAL22;

1353#ifdef __linux__
if (adev->dev->kobj.sd)
sysfs_remove_file_from_group(&adev->dev->kobj,
		&obj->sysfs_attr.attr,
		RAS_FS_NAME);
1358#endif
obj->attr_inuse = 0;
put_obj(obj);

return 0;
1363}

1365#ifdef __linux__

1367static int amdgpu_ras_sysfs_remove_all(struct amdgpu_device *adev)
1368{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj, *tmp;

list_for_each_entry_safe(obj, tmp, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}), tmp = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = (obj->node.next); (__typeof(*obj) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*obj), node) );}); &obj->
node != (&con->head); obj = tmp, tmp = ({ const __typeof
( ((__typeof(*tmp) *)0)->node ) *__mptr = (tmp->node.next
); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*tmp), node) );})) {
amdgpu_ras_sysfs_remove(adev, &obj->head);
}

if (amdgpu_bad_page_threshold != 0)
amdgpu_ras_sysfs_remove_bad_page_node(adev);

amdgpu_ras_sysfs_remove_feature_node(adev);

return 0;
1382}
1383/* sysfs end */

1385/**
* DOC: AMDGPU RAS Reboot Behavior for Unrecoverable Errors
*
* Normally when there is an uncorrectable error, the driver will reset
* the GPU to recover.  However, in the event of an unrecoverable error,
* the driver provides an interface to reboot the system automatically
* in that event.
*
* The following file in debugfs provides that interface:
* /sys/kernel/debug/dri/[0/1/2...]/ras/auto_reboot
*
* Usage:
*
* .. code-block:: bash
*
*	echo true > .../ras/auto_reboot
*
*/
1403/* debugfs begin */
1404static struct dentry *amdgpu_ras_debugfs_create_ctrl_node(struct amdgpu_device *adev)
1405{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct drm_minor  *minor = adev_to_drm(adev)->primary;
struct dentry     *dir;

dir = debugfs_create_dir(RAS_FS_NAME, minor->debugfs_root)ERR_PTR(-78);
debugfs_create_file("ras_ctrl", S_IWUGO | S_IRUGO, dir, adev,ERR_PTR(-78)
	    &amdgpu_ras_debugfs_ctrl_ops)ERR_PTR(-78);
debugfs_create_file("ras_eeprom_reset", S_IWUGO | S_IRUGO, dir, adev,ERR_PTR(-78)
	    &amdgpu_ras_debugfs_eeprom_ops)ERR_PTR(-78);
debugfs_create_u32("bad_page_cnt_threshold", 0444, dir,
	   &con->bad_page_cnt_threshold);
debugfs_create_x32("ras_hw_enabled", 0444, dir, &adev->ras_hw_enabled);
debugfs_create_x32("ras_enabled", 0444, dir, &adev->ras_enabled);
debugfs_create_file("ras_eeprom_size", S_IRUGO, dir, adev,ERR_PTR(-78)
	    &amdgpu_ras_debugfs_eeprom_size_ops)ERR_PTR(-78);
con->de_ras_eeprom_table = debugfs_create_file("ras_eeprom_table",ERR_PTR(-78)
				       S_IRUGO, dir, adev,ERR_PTR(-78)
				       &amdgpu_ras_debugfs_eeprom_table_ops)ERR_PTR(-78);
amdgpu_ras_debugfs_set_ret_size(&con->eeprom_control);

/*
* After one uncorrectable error happens, usually GPU recovery will
* be scheduled. But due to the known problem in GPU recovery failing
* to bring GPU back, below interface provides one direct way to
* user to reboot system automatically in such case within
* ERREVENT_ATHUB_INTERRUPT generated. Normal GPU recovery routine
* will never be called.
*/
debugfs_create_bool("auto_reboot", S_IWUGO | S_IRUGO, dir, &con->reboot);

/*
* User could set this not to clean up hardware's error count register
* of RAS IPs during ras recovery.
*/
debugfs_create_bool("disable_ras_err_cnt_harvest", 0644, dir,
	    &con->disable_ras_err_cnt_harvest);
return dir;
1443}

1445static void amdgpu_ras_debugfs_create(struct amdgpu_device *adev,
		      struct ras_fs_if *head,
		      struct dentry *dir)
1448{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &head->head);

if (!obj || !dir)
return;

get_obj(obj)do { (obj)->use++; } while (0);

memcpy(obj->fs_data.debugfs_name,__builtin_memcpy((obj->fs_data.debugfs_name), (head->debugfs_name
), (sizeof(obj->fs_data.debugfs_name)))
	head->debugfs_name,__builtin_memcpy((obj->fs_data.debugfs_name), (head->debugfs_name
), (sizeof(obj->fs_data.debugfs_name)))
	sizeof(obj->fs_data.debugfs_name))__builtin_memcpy((obj->fs_data.debugfs_name), (head->debugfs_name
), (sizeof(obj->fs_data.debugfs_name)));

debugfs_create_file(obj->fs_data.debugfs_name, S_IWUGO | S_IRUGO, dir,ERR_PTR(-78)
	    obj, &amdgpu_ras_debugfs_ops)ERR_PTR(-78);
1462}

1464void amdgpu_ras_debugfs_create_all(struct amdgpu_device *adev)
1465{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct dentry *dir;
struct ras_manager *obj;
struct ras_fs_if fs_info;

/*
* it won't be called in resume path, no need to check
* suspend and gpu reset status
*/
if (!IS_ENABLED(CONFIG_DEBUG_FS)0 || !con)
return;

dir = amdgpu_ras_debugfs_create_ctrl_node(adev);

list_for_each_entry(obj, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}); &obj->node != (&con->head); obj = ({ const
 __typeof( ((__typeof(*obj) *)0)->node ) *__mptr = (obj->
node.next); (__typeof(*obj) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*obj), node) );})) {
if (amdgpu_ras_is_supported(adev, obj->head.block) &&
	(obj->attr_inuse == 1)) {
	sprintf(fs_info.debugfs_name, "%s_err_inject",
			get_ras_block_str(&obj->head));
	fs_info.head = obj->head;
	amdgpu_ras_debugfs_create(adev, &fs_info, dir);
}
}
1489}

1491/* debugfs end */

1493/* ras fs */
1494static BIN_ATTR(gpu_vram_bad_pages, S_IRUGO,
amdgpu_ras_sysfs_badpages_read, NULL((void *)0), 0);
1496#endif /* __linux__ */
1497static DEVICE_ATTR(features, S_IRUGO,struct device_attribute dev_attr_features
amdgpu_ras_sysfs_features_read, NULL)struct device_attribute dev_attr_features;
1499static int amdgpu_ras_fs_init(struct amdgpu_device *adev)
1500{
1501#ifdef __linux__
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct attribute_group group = {
.name = RAS_FS_NAME,
};
struct attribute *attrs[] = {
&con->features_attr.attr,
NULL((void *)0)
};
struct bin_attribute *bin_attrs[] = {
NULL((void *)0),
NULL((void *)0),
};
int r;

/* add features entry */
con->features_attr = dev_attr_features;
group.attrs = attrs;
sysfs_attr_init(attrs[0]);

if (amdgpu_bad_page_threshold != 0) {
/* add bad_page_features entry */
bin_attr_gpu_vram_bad_pages.private = NULL((void *)0);
con->badpages_attr = bin_attr_gpu_vram_bad_pages;
bin_attrs[0] = &con->badpages_attr;
group.bin_attrs = bin_attrs;
sysfs_bin_attr_init(bin_attrs[0]);
}

r = sysfs_create_group(&adev->dev->kobj, &group)0;
if (r)
dev_err(adev->dev, "Failed to create RAS sysfs group!")printf("drm:pid%d:%s *ERROR* " "Failed to create RAS sysfs group!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
1533#endif

return 0;
1536}

1538static int amdgpu_ras_fs_fini(struct amdgpu_device *adev)
1539{
1540#ifdef __linux__
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *con_obj, *ip_obj, *tmp;

if (IS_ENABLED(CONFIG_DEBUG_FS)0) {
list_for_each_entry_safe(con_obj, tmp, &con->head, node)for (con_obj = ({ const __typeof( ((__typeof(*con_obj) *)0)->
node ) *__mptr = ((&con->head)->next); (__typeof(*con_obj
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*con_obj),
 node) );}), tmp = ({ const __typeof( ((__typeof(*con_obj) *)
0)->node ) *__mptr = (con_obj->node.next); (__typeof(*con_obj
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*con_obj),
 node) );}); &con_obj->node != (&con->head); con_obj
 = tmp, tmp = ({ const __typeof( ((__typeof(*tmp) *)0)->node
 ) *__mptr = (tmp->node.next); (__typeof(*tmp) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*tmp), node) );})) {
	ip_obj = amdgpu_ras_find_obj(adev, &con_obj->head);
	if (ip_obj)
		put_obj(ip_obj);
}
}

amdgpu_ras_sysfs_remove_all(adev);
1553#endif
return 0;
1555}
1556/* ras fs end */

1558/* ih begin */

1560/* For the hardware that cannot enable bif ring for both ras_controller_irq
* and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
* register to check whether the interrupt is triggered or not, and properly
* ack the interrupt if it is there
*/
1565void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev)
1566{
/* Fatal error events are handled on host side */
if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) ||
!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF))
return;

if (adev->nbio.ras &&
   adev->nbio.ras->handle_ras_controller_intr_no_bifring)
adev->nbio.ras->handle_ras_controller_intr_no_bifring(adev);

if (adev->nbio.ras &&
   adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring)
adev->nbio.ras->handle_ras_err_event_athub_intr_no_bifring(adev);
1579}

1581static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager *obj,
		struct amdgpu_iv_entry *entry)
1583{
bool_Bool poison_stat = false0;
struct amdgpu_device *adev = obj->adev;
struct ras_err_data err_data = {0, 0, 0, NULL((void *)0)};
struct amdgpu_ras_block_object *block_obj =
amdgpu_ras_get_ras_block(adev, obj->head.block, 0);

if (!block_obj || !block_obj->hw_ops)
return;

/* both query_poison_status and handle_poison_consumption are optional,
* but at least one of them should be implemented if we need poison
* consumption handler
*/
if (block_obj->hw_ops->query_poison_status) {
poison_stat = block_obj->hw_ops->query_poison_status(adev);
if (!poison_stat) {
	/* Not poison consumption interrupt, no need to handle it */
	dev_info(adev->dev, "No RAS poison status in %s poison IH.\n",do { } while(0)
			block_obj->ras_comm.name)do { } while(0);

	return;
}
}

if (!adev->gmc.xgmi.connected_to_cpu)
amdgpu_umc_poison_handler(adev, &err_data, false0);

if (block_obj->hw_ops->handle_poison_consumption)
poison_stat = block_obj->hw_ops->handle_poison_consumption(adev);

/* gpu reset is fallback for failed and default cases */
if (poison_stat) {
dev_info(adev->dev, "GPU reset for %s RAS poison consumption is issued!\n",do { } while(0)
		block_obj->ras_comm.name)do { } while(0);
amdgpu_ras_reset_gpu(adev);
}
1620}

1622static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj,
		struct amdgpu_iv_entry *entry)
1624{
dev_info(obj->adev->dev,do { } while(0)
"Poison is created, no user action is needed.\n")do { } while(0);
1627}

1629static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj,
		struct amdgpu_iv_entry *entry)
1631{
struct ras_ih_data *data = &obj->ih_data;
struct ras_err_data err_data = {0, 0, 0, NULL((void *)0)};
int ret;

if (!data->cb)
return;

/* Let IP handle its data, maybe we need get the output
* from the callback to update the error type/count, etc
*/
ret = data->cb(obj->adev, &err_data, entry);
/* ue will trigger an interrupt, and in that case
* we need do a reset to recovery the whole system.
* But leave IP do that recovery, here we just dispatch
* the error.
*/
if (ret == AMDGPU_RAS_SUCCESS) {
/* these counts could be left as 0 if
 * some blocks do not count error number
 */
obj->err_data.ue_count += err_data.ue_count;
obj->err_data.ce_count += err_data.ce_count;
}
1655}

1657static void amdgpu_ras_interrupt_handler(struct ras_manager *obj)
1658{
struct ras_ih_data *data = &obj->ih_data;
struct amdgpu_iv_entry entry;

while (data->rptr != data->wptr) {
rmb()do { __asm volatile("lfence" ::: "memory"); } while (0);
memcpy(&entry, &data->ring[data->rptr],__builtin_memcpy((&entry), (&data->ring[data->rptr
]), (data->element_size))
		data->element_size)__builtin_memcpy((&entry), (&data->ring[data->rptr
]), (data->element_size));

wmb()do { __asm volatile("sfence" ::: "memory"); } while (0);
data->rptr = (data->aligned_element_size +
		data->rptr) % data->ring_size;

if (amdgpu_ras_is_poison_mode_supported(obj->adev)) {
	if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
		amdgpu_ras_interrupt_poison_creation_handler(obj, &entry);
	else
		amdgpu_ras_interrupt_poison_consumption_handler(obj, &entry);
} else {
	if (obj->head.block == AMDGPU_RAS_BLOCK__UMC)
		amdgpu_ras_interrupt_umc_handler(obj, &entry);
	else
		dev_warn(obj->adev->dev,printf("drm:pid%d:%s *WARNING* " "No RAS interrupt handler for non-UMC block with poison disabled.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
			"No RAS interrupt handler for non-UMC block with poison disabled.\n")printf("drm:pid%d:%s *WARNING* " "No RAS interrupt handler for non-UMC block with poison disabled.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}
}
1684}

1686static void amdgpu_ras_interrupt_process_handler(struct work_struct *work)
1687{
struct ras_ih_data *data =
container_of(work, struct ras_ih_data, ih_work)({ const __typeof( ((struct ras_ih_data *)0)->ih_work ) *__mptr
 = (work); (struct ras_ih_data *)( (char *)__mptr - __builtin_offsetof
(struct ras_ih_data, ih_work) );});
struct ras_manager *obj =
container_of(data, struct ras_manager, ih_data)({ const __typeof( ((struct ras_manager *)0)->ih_data ) *__mptr
 = (data); (struct ras_manager *)( (char *)__mptr - __builtin_offsetof
(struct ras_manager, ih_data) );});

amdgpu_ras_interrupt_handler(obj);
1694}

1696int amdgpu_ras_interrupt_dispatch(struct amdgpu_device *adev,
struct ras_dispatch_if *info)
1698{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
struct ras_ih_data *data = &obj->ih_data;

if (!obj)
return -EINVAL22;

if (data->inuse == 0)
return 0;

/* Might be overflow... */
memcpy(&data->ring[data->wptr], info->entry,__builtin_memcpy((&data->ring[data->wptr]), (info->
entry), (data->element_size))
	data->element_size)__builtin_memcpy((&data->ring[data->wptr]), (info->
entry), (data->element_size));

wmb()do { __asm volatile("sfence" ::: "memory"); } while (0);
data->wptr = (data->aligned_element_size +
	data->wptr) % data->ring_size;

schedule_work(&data->ih_work);

return 0;
1719}

1721int amdgpu_ras_interrupt_remove_handler(struct amdgpu_device *adev,
struct ras_common_if *head)
1723{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
struct ras_ih_data *data;

if (!obj)
return -EINVAL22;

data = &obj->ih_data;
if (data->inuse == 0)
return 0;

cancel_work_sync(&data->ih_work);

kfree(data->ring);
memset(data, 0, sizeof(*data))__builtin_memset((data), (0), (sizeof(*data)));
put_obj(obj);

return 0;
1741}

1743int amdgpu_ras_interrupt_add_handler(struct amdgpu_device *adev,
struct ras_common_if *head)
1745{
struct ras_manager *obj = amdgpu_ras_find_obj(adev, head);
struct ras_ih_data *data;
struct amdgpu_ras_block_object *ras_obj;

if (!obj) {
/* in case we registe the IH before enable ras feature */
obj = amdgpu_ras_create_obj(adev, head);
if (!obj)
	return -EINVAL22;
} else
get_obj(obj)do { (obj)->use++; } while (0);

ras_obj = container_of(head, struct amdgpu_ras_block_object, ras_comm)({ const __typeof( ((struct amdgpu_ras_block_object *)0)->
ras_comm ) *__mptr = (head); (struct amdgpu_ras_block_object *
)( (char *)__mptr - __builtin_offsetof(struct amdgpu_ras_block_object
, ras_comm) );});

data = &obj->ih_data;
/* add the callback.etc */
*data = (struct ras_ih_data) {
.inuse = 0,
.cb = ras_obj->ras_cb,
.element_size = sizeof(struct amdgpu_iv_entry),
.rptr = 0,
.wptr = 0,
};

INIT_WORK(&data->ih_work, amdgpu_ras_interrupt_process_handler);

data->aligned_element_size = roundup2(data->element_size, 8)(((data->element_size) + ((8) - 1)) & (~((__typeof(data
->element_size))(8) - 1)));
/* the ring can store 64 iv entries. */
data->ring_size = 64 * data->aligned_element_size;
data->ring = kmalloc(data->ring_size, GFP_KERNEL(0x0001 | 0x0004));
if (!data->ring) {
put_obj(obj);
return -ENOMEM12;
}

/* IH is ready */
data->inuse = 1;

return 0;
1785}

1787static int amdgpu_ras_interrupt_remove_all(struct amdgpu_device *adev)
1788{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj, *tmp;

list_for_each_entry_safe(obj, tmp, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}), tmp = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = (obj->node.next); (__typeof(*obj) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*obj), node) );}); &obj->
node != (&con->head); obj = tmp, tmp = ({ const __typeof
( ((__typeof(*tmp) *)0)->node ) *__mptr = (tmp->node.next
); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*tmp), node) );})) {
amdgpu_ras_interrupt_remove_handler(adev, &obj->head);
}

return 0;
1797}
1798/* ih end */

1800/* traversal all IPs except NBIO to query error counter */
1801static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
1802{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;

if (!adev->ras_enabled || !con)
return;

list_for_each_entry(obj, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}); &obj->node != (&con->head); obj = ({ const
 __typeof( ((__typeof(*obj) *)0)->node ) *__mptr = (obj->
node.next); (__typeof(*obj) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*obj), node) );})) {
struct ras_query_if info = {
	.head = obj->head,
};

/*
 * PCIE_BIF IP has one different isr by ras controller
 * interrupt, the specific ras counter query will be
 * done in that isr. So skip such block from common
 * sync flood interrupt isr calling.
 */
if (info.head.block == AMDGPU_RAS_BLOCK__PCIE_BIF)
	continue;

/*
 * this is a workaround for aldebaran, skip send msg to
 * smu to get ecc_info table due to smu handle get ecc
 * info table failed temporarily.
 * should be removed until smu fix handle ecc_info table.
 */
if ((info.head.block == AMDGPU_RAS_BLOCK__UMC) &&
	(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2))))
	continue;

amdgpu_ras_query_error_status(adev, &info);

if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2)(((11) << 16) | ((0) << 8) | (2)) &&
    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)(((11) << 16) | ((0) << 8) | (4)) &&
    adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)(((13) << 16) | ((0) << 8) | (0))) {
	if (amdgpu_ras_reset_error_status(adev, info.head.block))
		dev_warn(adev->dev, "Failed to reset error counter and error status")printf("drm:pid%d:%s *WARNING* " "Failed to reset error counter and error status"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
}
}
1842}

1844/* Parse RdRspStatus and WrRspStatus */
1845static void amdgpu_ras_error_status_query(struct amdgpu_device *adev,
			  struct ras_query_if *info)
1847{
struct amdgpu_ras_block_object *block_obj;
/*
* Only two block need to query read/write
* RspStatus at current state
*/
if ((info->head.block != AMDGPU_RAS_BLOCK__GFX) &&
(info->head.block != AMDGPU_RAS_BLOCK__MMHUB))
return;

block_obj = amdgpu_ras_get_ras_block(adev,
			info->head.block,
			info->head.sub_block_index);

if (!block_obj || !block_obj->hw_ops) {
dev_dbg_once(adev->dev, "%s doesn't config RAS function\n",do { } while(0)
	     get_ras_block_str(&info->head))do { } while(0);
return;
}

if (block_obj->hw_ops->query_ras_error_status)
block_obj->hw_ops->query_ras_error_status(adev);

1870}

1872static void amdgpu_ras_query_err_status(struct amdgpu_device *adev)
1873{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj;

if (!adev->ras_enabled || !con)
return;

list_for_each_entry(obj, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}); &obj->node != (&con->head); obj = ({ const
 __typeof( ((__typeof(*obj) *)0)->node ) *__mptr = (obj->
node.next); (__typeof(*obj) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*obj), node) );})) {
struct ras_query_if info = {
	.head = obj->head,
};

amdgpu_ras_error_status_query(adev, &info);
}
1887}

1889/* recovery begin */

1891/* return 0 on success.
* caller need free bps.
*/
1894static int amdgpu_ras_badpages_read(struct amdgpu_device *adev,
struct ras_badpage **bps, unsigned int *count)
1896{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
int i = 0;
int ret = 0, status;

if (!con || !con->eh_data || !bps || !count)
return -EINVAL22;

mutex_lock(&con->recovery_lock)rw_enter_write(&con->recovery_lock);
data = con->eh_data;
if (!data || data->count == 0) {
*bps = NULL((void *)0);
ret = -EINVAL22;
goto out;
}

*bps = kmalloc(sizeof(struct ras_badpage) * data->count, GFP_KERNEL(0x0001 | 0x0004));
if (!*bps) {
ret = -ENOMEM12;
goto out;
}

for (; i < data->count; i++) {
(*bps)[i] = (struct ras_badpage){
	.bp = data->bps[i].retired_page,
	.size = AMDGPU_GPU_PAGE_SIZE4096,
	.flags = AMDGPU_RAS_RETIRE_PAGE_RESERVED,
};
status = amdgpu_vram_mgr_query_page_status(&adev->mman.vram_mgr,
		data->bps[i].retired_page);
if (status == -EBUSY16)
	(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_PENDING;
else if (status == -ENOENT2)
	(*bps)[i].flags = AMDGPU_RAS_RETIRE_PAGE_FAULT;
}

*count = data->count;
1934out:
mutex_unlock(&con->recovery_lock)rw_exit_write(&con->recovery_lock);
return ret;
1937}

1939static void amdgpu_ras_do_recovery(struct work_struct *work)
1940{
struct amdgpu_ras *ras =
container_of(work, struct amdgpu_ras, recovery_work)({ const __typeof( ((struct amdgpu_ras *)0)->recovery_work
 ) *__mptr = (work); (struct amdgpu_ras *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_ras, recovery_work) );});
struct amdgpu_device *remote_adev = NULL((void *)0);
struct amdgpu_device *adev = ras->adev;
struct list_head device_list, *device_list_handle =  NULL((void *)0);

if (!ras->disable_ras_err_cnt_harvest) {
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);

/* Build list of devices to query RAS related errors */
if  (hive && adev->gmc.xgmi.num_physical_nodes > 1) {
	device_list_handle = &hive->device_list;
} else {
	INIT_LIST_HEAD(&device_list);
	list_add_tail(&adev->gmc.xgmi.head, &device_list);
	device_list_handle = &device_list;
}

list_for_each_entry(remote_adev,for (remote_adev = ({ const __typeof( ((__typeof(*remote_adev
) *)0)->gmc.xgmi.head ) *__mptr = ((device_list_handle)->
next); (__typeof(*remote_adev) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*remote_adev), gmc.xgmi.head) );}); &remote_adev
->gmc.xgmi.head != (device_list_handle); remote_adev = ({ const
 __typeof( ((__typeof(*remote_adev) *)0)->gmc.xgmi.head ) *
__mptr = (remote_adev->gmc.xgmi.head.next); (__typeof(*remote_adev
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*remote_adev
), gmc.xgmi.head) );}))
		device_list_handle, gmc.xgmi.head)for (remote_adev = ({ const __typeof( ((__typeof(*remote_adev
) *)0)->gmc.xgmi.head ) *__mptr = ((device_list_handle)->
next); (__typeof(*remote_adev) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*remote_adev), gmc.xgmi.head) );}); &remote_adev
->gmc.xgmi.head != (device_list_handle); remote_adev = ({ const
 __typeof( ((__typeof(*remote_adev) *)0)->gmc.xgmi.head ) *
__mptr = (remote_adev->gmc.xgmi.head.next); (__typeof(*remote_adev
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*remote_adev
), gmc.xgmi.head) );})) {
	amdgpu_ras_query_err_status(remote_adev);
	amdgpu_ras_log_on_err_counter(remote_adev);
}

amdgpu_put_xgmi_hive(hive);
}

if (amdgpu_device_should_recover_gpu(ras->adev)) {
struct amdgpu_reset_context reset_context;
memset(&reset_context, 0, sizeof(reset_context))__builtin_memset((&reset_context), (0), (sizeof(reset_context
)));

reset_context.method = AMD_RESET_METHOD_NONE;
reset_context.reset_req_dev = adev;
clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);

amdgpu_device_gpu_recover(ras->adev, NULL((void *)0), &reset_context);
}
atomic_set(&ras->in_recovery, 0)({ typeof(*(&ras->in_recovery)) __tmp = ((0)); *(volatile
 typeof(*(&ras->in_recovery)) *)&(*(&ras->in_recovery
)) = __tmp; __tmp; });
1979}

1981/* alloc/realloc bps array */
1982static int amdgpu_ras_realloc_eh_data_space(struct amdgpu_device *adev,
struct ras_err_handler_data *data, int pages)
1984{
unsigned int old_space = data->count + data->space_left;
unsigned int new_space = old_space + pages;
unsigned int align_space = roundup2(new_space, 512)(((new_space) + ((512) - 1)) & (~((__typeof(new_space))(512
) - 1)));
void *bps = kmalloc(align_space * sizeof(*data->bps), GFP_KERNEL(0x0001 | 0x0004));

if (!bps) {
return -ENOMEM12;
}

if (data->bps) {
memcpy(bps, data->bps,__builtin_memcpy((bps), (data->bps), (data->count * sizeof
(*data->bps)))
		data->count * sizeof(*data->bps))__builtin_memcpy((bps), (data->bps), (data->count * sizeof
(*data->bps)));
kfree(data->bps);
}

data->bps = bps;
data->space_left += align_space - old_space;
return 0;
2003}

2005/* it deal with vram only. */
2006int amdgpu_ras_add_bad_pages(struct amdgpu_device *adev,
struct eeprom_table_record *bps, int pages)
2008{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
int ret = 0;
uint32_t i;

if (!con || !con->eh_data || !bps || pages <= 0)
return 0;

mutex_lock(&con->recovery_lock)rw_enter_write(&con->recovery_lock);
data = con->eh_data;
if (!data)
goto out;

for (i = 0; i < pages; i++) {
if (amdgpu_ras_check_bad_page_unlock(con,
	bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT12))
	continue;

if (!data->space_left &&
	amdgpu_ras_realloc_eh_data_space(adev, data, 256)) {
	ret = -ENOMEM12;
	goto out;
}

amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr,
	bps[i].retired_page << AMDGPU_GPU_PAGE_SHIFT12,
	AMDGPU_GPU_PAGE_SIZE4096);

memcpy(&data->bps[data->count], &bps[i], sizeof(*data->bps))__builtin_memcpy((&data->bps[data->count]), (&bps
[i]), (sizeof(*data->bps)));
data->count++;
data->space_left--;
}
2041out:
mutex_unlock(&con->recovery_lock)rw_exit_write(&con->recovery_lock);

return ret;
2045}

2047/*
* write error record array to eeprom, the function should be
* protected by recovery_lock
*/
2051int amdgpu_ras_save_bad_pages(struct amdgpu_device *adev)
2052{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data;
struct amdgpu_ras_eeprom_control *control;
int save_count;

if (!con || !con->eh_data)
return 0;

mutex_lock(&con->recovery_lock)rw_enter_write(&con->recovery_lock);
control = &con->eeprom_control;
data = con->eh_data;
save_count = data->count - control->ras_num_recs;
mutex_unlock(&con->recovery_lock)rw_exit_write(&con->recovery_lock);
/* only new entries are saved */
if (save_count > 0) {
if (amdgpu_ras_eeprom_append(control,
			     &data->bps[control->ras_num_recs],
			     save_count)) {
	dev_err(adev->dev, "Failed to save EEPROM table data!")printf("drm:pid%d:%s *ERROR* " "Failed to save EEPROM table data!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
	return -EIO5;
}

dev_info(adev->dev, "Saved %d pages to EEPROM table.\n", save_count)do { } while(0);
}

return 0;
2079}

2081/*
* read error record array in eeprom and reserve enough space for
* storing new bad pages
*/
2085static int amdgpu_ras_load_bad_pages(struct amdgpu_device *adev)
2086{
struct amdgpu_ras_eeprom_control *control =
&adev->psp.ras_context.ras->eeprom_control;
struct eeprom_table_record *bps;
int ret;

/* no bad page record, skip eeprom access */
if (control->ras_num_recs == 0 || amdgpu_bad_page_threshold == 0)
return 0;

bps = kcalloc(control->ras_num_recs, sizeof(*bps), GFP_KERNEL(0x0001 | 0x0004));
if (!bps)
return -ENOMEM12;

ret = amdgpu_ras_eeprom_read(control, bps, control->ras_num_recs);
if (ret)
dev_err(adev->dev, "Failed to load EEPROM table records!")printf("drm:pid%d:%s *ERROR* " "Failed to load EEPROM table records!"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
else
ret = amdgpu_ras_add_bad_pages(adev, bps, control->ras_num_recs);

kfree(bps);
return ret;
2108}

2110static bool_Bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
		uint64_t addr)
2112{
struct ras_err_handler_data *data = con->eh_data;
int i;

addr >>= AMDGPU_GPU_PAGE_SHIFT12;
for (i = 0; i < data->count; i++)
if (addr == data->bps[i].retired_page)
	return true1;

return false0;
2122}

2124/*
* check if an address belongs to bad page
*
* Note: this check is only for umc block
*/
2129static bool_Bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
		uint64_t addr)
2131{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
bool_Bool ret = false0;

if (!con || !con->eh_data)
return ret;

mutex_lock(&con->recovery_lock)rw_enter_write(&con->recovery_lock);
ret = amdgpu_ras_check_bad_page_unlock(con, addr);
mutex_unlock(&con->recovery_lock)rw_exit_write(&con->recovery_lock);
return ret;
2142}

2144static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev,
			  uint32_t max_count)
2146{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

/*
* Justification of value bad_page_cnt_threshold in ras structure
*
* Generally, -1 <= amdgpu_bad_page_threshold <= max record length
* in eeprom, and introduce two scenarios accordingly.
*
* Bad page retirement enablement:
*    - If amdgpu_bad_page_threshold = -1,
*      bad_page_cnt_threshold = typical value by formula.
*
*    - When the value from user is 0 < amdgpu_bad_page_threshold <
*      max record length in eeprom, use it directly.
*
* Bad page retirement disablement:
*    - If amdgpu_bad_page_threshold = 0, bad page retirement
*      functionality is disabled, and bad_page_cnt_threshold will
*      take no effect.
*/

if (amdgpu_bad_page_threshold < 0) {
u64 val = adev->gmc.mc_vram_size;

do_div(val, RAS_BAD_PAGE_COVER)({ uint32_t __base = ((100 * 1024 * 1024ULL)); uint32_t __rem
 = ((uint64_t)(val)) % __base; (val) = ((uint64_t)(val)) / __base
; __rem; });
con->bad_page_cnt_threshold = min(lower_32_bits(val),(((((u32)(val)))<(max_count))?(((u32)(val))):(max_count))
				  max_count)(((((u32)(val)))<(max_count))?(((u32)(val))):(max_count));
} else {
con->bad_page_cnt_threshold = min_t(int, max_count,({ int __min_a = (max_count); int __min_b = (amdgpu_bad_page_threshold
); __min_a < __min_b ? __min_a : __min_b; })
				    amdgpu_bad_page_threshold)({ int __min_a = (max_count); int __min_b = (amdgpu_bad_page_threshold
); __min_a < __min_b ? __min_a : __min_b; });
}
2178}

2180int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
2181{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data **data;
u32  max_eeprom_records_count = 0;
bool_Bool exc_err_limit = false0;
int ret;

if (!con || amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
return 0;

/* Allow access to RAS EEPROM via debugfs, when the ASIC
* supports RAS and debugfs is enabled, but when
* adev->ras_enabled is unset, i.e. when "ras_enable"
* module parameter is set to 0.
*/
con->adev = adev;

if (!adev->ras_enabled)
return 0;

data = &con->eh_data;
*data = kmalloc(sizeof(**data), GFP_KERNEL(0x0001 | 0x0004) | __GFP_ZERO0x0008);
if (!*data) {
ret = -ENOMEM12;
goto out;
}

rw_init(&con->recovery_lock, "rasrec")_rw_init_flags(&con->recovery_lock, "rasrec", 0, ((void
 *)0));
INIT_WORK(&con->recovery_work, amdgpu_ras_do_recovery);
atomic_set(&con->in_recovery, 0)({ typeof(*(&con->in_recovery)) __tmp = ((0)); *(volatile
 typeof(*(&con->in_recovery)) *)&(*(&con->in_recovery
)) = __tmp; __tmp; });
con->eeprom_control.bad_channel_bitmap = 0;

max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count();
amdgpu_ras_validate_threshold(adev, max_eeprom_records_count);

/* Todo: During test the SMU might fail to read the eeprom through I2C
* when the GPU is pending on XGMI reset during probe time
* (Mostly after second bus reset), skip it now
*/
if (adev->gmc.xgmi.pending_reset)
return 0;
ret = amdgpu_ras_eeprom_init(&con->eeprom_control, &exc_err_limit);
/*
* This calling fails when exc_err_limit is true or
* ret != 0.
*/
if (exc_err_limit || ret)
goto free;

if (con->eeprom_control.ras_num_recs) {
ret = amdgpu_ras_load_bad_pages(adev);
if (ret)
	goto free;

amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs);

if (con->update_channel_flag == true1) {
	amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap);
	con->update_channel_flag = false0;
}
}

2243#ifdef CONFIG_X86_MCE_AMD
if ((adev->asic_type == CHIP_ALDEBARAN) &&
   (adev->gmc.xgmi.connected_to_cpu))
amdgpu_register_bad_pages_mca_notifier(adev);
2247#endif
return 0;

2250free:
kfree((*data)->bps);
kfree(*data);
con->eh_data = NULL((void *)0);
2254out:
dev_warn(adev->dev, "Failed to initialize ras recovery! (%d)\n", ret)printf("drm:pid%d:%s *WARNING* " "Failed to initialize ras recovery! (%d)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret);

/*
* Except error threshold exceeding case, other failure cases in this
* function would not fail amdgpu driver init.
*/
if (!exc_err_limit)
ret = 0;
else
ret = -EINVAL22;

return ret;
2267}

2269static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev)
2270{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_err_handler_data *data = con->eh_data;

/* recovery_init failed to init it, fini is useless */
if (!data)
return 0;

cancel_work_sync(&con->recovery_work);

mutex_lock(&con->recovery_lock)rw_enter_write(&con->recovery_lock);
con->eh_data = NULL((void *)0);
kfree(data->bps);
kfree(data);
mutex_unlock(&con->recovery_lock)rw_exit_write(&con->recovery_lock);

return 0;
2287}
2288/* recovery end */

2290static bool_Bool amdgpu_ras_asic_supported(struct amdgpu_device *adev)
2291{
if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 2)(((13) << 16) | ((0) << 8) | (2)):
	return true1;
default:
	return false0;
}
}

if (adev->asic_type == CHIP_IP_DISCOVERY) {
switch (adev->ip_versions[MP0_HWIP][0]) {
case IP_VERSION(13, 0, 0)(((13) << 16) | ((0) << 8) | (0)):
case IP_VERSION(13, 0, 10)(((13) << 16) | ((0) << 8) | (10)):
	return true1;
default:
	return false0;
}
}

return adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS ||
adev->asic_type == CHIP_ALDEBARAN ||
adev->asic_type == CHIP_SIENNA_CICHLID;
2316}

2318/*
* this is workaround for vega20 workstation sku,
* force enable gfx ras, ignore vbios gfx ras flag
* due to GC EDC can not write
*/
2323static void amdgpu_ras_get_quirks(struct amdgpu_device *adev)
2324{
struct atom_context *ctx = adev->mode_info.atom_context;

if (!ctx)
return;

if (strnstr(ctx->vbios_version, "D16406",
    sizeof(ctx->vbios_version)) ||
strnstr(ctx->vbios_version, "D36002",
	sizeof(ctx->vbios_version)))
adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX);
2335}

2337/*
* check hardware's ras ability which will be saved in hw_supported.
* if hardware does not support ras, we can skip some ras initializtion and
* forbid some ras operations from IP.
* if software itself, say boot parameter, limit the ras ability. We still
* need allow IP do some limited operations, like disable. In such case,
* we have to initialize ras as normal. but need check if operation is
* allowed or not in each function.
*/
2346static void amdgpu_ras_check_supported(struct amdgpu_device *adev)
2347{
adev->ras_hw_enabled = adev->ras_enabled = 0;

if (!adev->is_atom_fw ||
   !amdgpu_ras_asic_supported(adev))
return;

if (!adev->gmc.xgmi.connected_to_cpu) {
if (amdgpu_atomfirmware_mem_ecc_supported(adev)) {
	dev_info(adev->dev, "MEM ECC is active.\n")do { } while(0);
	adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__UMC |
				   1 << AMDGPU_RAS_BLOCK__DF);
} else {
	dev_info(adev->dev, "MEM ECC is not presented.\n")do { } while(0);
}

if (amdgpu_atomfirmware_sram_ecc_supported(adev)) {
	dev_info(adev->dev, "SRAM ECC is active.\n")do { } while(0);
	if (!amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
		adev->ras_hw_enabled |= ~(1 << AMDGPU_RAS_BLOCK__UMC |
					    1 << AMDGPU_RAS_BLOCK__DF);

		if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(2, 6, 0)(((2) << 16) | ((6) << 8) | (0)))
			adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__VCN |
					1 << AMDGPU_RAS_BLOCK__JPEG);
		else
			adev->ras_hw_enabled &= ~(1 << AMDGPU_RAS_BLOCK__VCN |
					1 << AMDGPU_RAS_BLOCK__JPEG);
	} else {
		adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__PCIE_BIF |
						1 << AMDGPU_RAS_BLOCK__SDMA |
						1 << AMDGPU_RAS_BLOCK__GFX);
	}
} else {
	dev_info(adev->dev, "SRAM ECC is not presented.\n")do { } while(0);
}
} else {
/* driver only manages a few IP blocks RAS feature
 * when GPU is connected cpu through XGMI */
adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX |
			   1 << AMDGPU_RAS_BLOCK__SDMA |
			   1 << AMDGPU_RAS_BLOCK__MMHUB);
}

amdgpu_ras_get_quirks(adev);

/* hw_supported needs to be aligned with RAS block mask. */
adev->ras_hw_enabled &= AMDGPU_RAS_BLOCK_MASK((1ULL << AMDGPU_RAS_BLOCK__LAST) - 1);

adev->ras_enabled = amdgpu_ras_enable == 0 ? 0 :
adev->ras_hw_enabled & amdgpu_ras_mask;
2398}

2400static void amdgpu_ras_counte_dw(struct work_struct *work)
2401{
struct amdgpu_ras *con = container_of(work, struct amdgpu_ras,({ const __typeof( ((struct amdgpu_ras *)0)->ras_counte_delay_work
.work ) *__mptr = (work); (struct amdgpu_ras *)( (char *)__mptr
 - __builtin_offsetof(struct amdgpu_ras, ras_counte_delay_work
.work) );})
			      ras_counte_delay_work.work)({ const __typeof( ((struct amdgpu_ras *)0)->ras_counte_delay_work
.work ) *__mptr = (work); (struct amdgpu_ras *)( (char *)__mptr
 - __builtin_offsetof(struct amdgpu_ras, ras_counte_delay_work
.work) );});
struct amdgpu_device *adev = con->adev;
struct drm_device *dev = adev_to_drm(adev);
unsigned long ce_count, ue_count;
int res;

res = pm_runtime_get_sync(dev->dev);
if (res < 0)
goto Out;

/* Cache new values.
*/
if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
atomic_set(&con->ras_ce_count, ce_count)({ typeof(*(&con->ras_ce_count)) __tmp = ((ce_count));
 *(volatile typeof(*(&con->ras_ce_count)) *)&(*(&
con->ras_ce_count)) = __tmp; __tmp; });
atomic_set(&con->ras_ue_count, ue_count)({ typeof(*(&con->ras_ue_count)) __tmp = ((ue_count));
 *(volatile typeof(*(&con->ras_ue_count)) *)&(*(&
con->ras_ue_count)) = __tmp; __tmp; });
}

pm_runtime_mark_last_busy(dev->dev);
2421Out:
pm_runtime_put_autosuspend(dev->dev);
2423}

2425int amdgpu_ras_init(struct amdgpu_device *adev)
2426{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
int r;
bool_Bool df_poison, umc_poison;

if (con)
return 0;

con = kmalloc(sizeof(struct amdgpu_ras) +
	sizeof(struct ras_manager) * AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST +
	sizeof(struct ras_manager) * AMDGPU_RAS_MCA_BLOCK_COUNTAMDGPU_RAS_MCA_BLOCK__LAST,
	GFP_KERNEL(0x0001 | 0x0004)|__GFP_ZERO0x0008);
if (!con)
return -ENOMEM12;

con->adev = adev;
INIT_DELAYED_WORK(&con->ras_counte_delay_work, amdgpu_ras_counte_dw);
atomic_set(&con->ras_ce_count, 0)({ typeof(*(&con->ras_ce_count)) __tmp = ((0)); *(volatile
 typeof(*(&con->ras_ce_count)) *)&(*(&con->
ras_ce_count)) = __tmp; __tmp; });
atomic_set(&con->ras_ue_count, 0)({ typeof(*(&con->ras_ue_count)) __tmp = ((0)); *(volatile
 typeof(*(&con->ras_ue_count)) *)&(*(&con->
ras_ue_count)) = __tmp; __tmp; });

con->objs = (struct ras_manager *)(con + 1);

amdgpu_ras_set_context(adev, con);

amdgpu_ras_check_supported(adev);

if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) {
/* set gfx block ras context feature for VEGA20 Gaming
 * send ras disable cmd to ras ta during ras late init.
 */
if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) {
	con->features |= BIT(AMDGPU_RAS_BLOCK__GFX)(1UL << (AMDGPU_RAS_BLOCK__GFX));

	return 0;
}

r = 0;
goto release_con;
}

con->update_channel_flag = false0;
con->features = 0;
INIT_LIST_HEAD(&con->head);
/* Might need get this flag from vbios. */
con->flags = RAS_DEFAULT_FLAGS((0x1 << 0));

/* initialize nbio ras function ahead of any other
* ras functions so hardware fatal error interrupt
* can be enabled as early as possible */
switch (adev->asic_type) {
case CHIP_VEGA20:
case CHIP_ARCTURUS:
case CHIP_ALDEBARAN:
if (!adev->gmc.xgmi.connected_to_cpu) {
	adev->nbio.ras = &nbio_v7_4_ras;
	amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);
	adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;
}
break;
default:
/* nbio ras is not available */
break;
}

if (adev->nbio.ras &&
   adev->nbio.ras->init_ras_controller_interrupt) {
r = adev->nbio.ras->init_ras_controller_interrupt(adev);
if (r)
	goto release_con;
}

if (adev->nbio.ras &&
   adev->nbio.ras->init_ras_err_event_athub_interrupt) {
r = adev->nbio.ras->init_ras_err_event_athub_interrupt(adev);
if (r)
	goto release_con;
}

/* Init poison supported flag, the default value is false */
if (adev->gmc.xgmi.connected_to_cpu) {
/* enabled by default when GPU is connected to CPU */
con->poison_supported = true1;
}
else if (adev->df.funcs &&
   adev->df.funcs->query_ras_poison_mode &&
   adev->umc.ras &&
   adev->umc.ras->query_ras_poison_mode) {
df_poison =
	adev->df.funcs->query_ras_poison_mode(adev);
umc_poison =
	adev->umc.ras->query_ras_poison_mode(adev);
/* Only poison is set in both DF and UMC, we can support it */
if (df_poison && umc_poison)
	con->poison_supported = true1;
else if (df_poison != umc_poison)
	dev_warn(adev->dev, "Poison setting is inconsistent in DF/UMC(%d:%d)!\n",printf("drm:pid%d:%s *WARNING* " "Poison setting is inconsistent in DF/UMC(%d:%d)!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , df_poison
, umc_poison)
			df_poison, umc_poison)printf("drm:pid%d:%s *WARNING* " "Poison setting is inconsistent in DF/UMC(%d:%d)!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , df_poison
, umc_poison);
}

if (amdgpu_ras_fs_init(adev)) {
r = -EINVAL22;
goto release_con;
}

dev_info(adev->dev, "RAS INFO: ras initialized successfully, "do { } while(0)
 "hardware ability[%x] ras_mask[%x]\n",do { } while(0)
 adev->ras_hw_enabled, adev->ras_enabled)do { } while(0);

return 0;
2535release_con:
amdgpu_ras_set_context(adev, NULL((void *)0));
kfree(con);

return r;
2540}

2542int amdgpu_persistent_edc_harvesting_supported(struct amdgpu_device *adev)
2543{
if (adev->gmc.xgmi.connected_to_cpu)
return 1;
return 0;
2547}

2549static int amdgpu_persistent_edc_harvesting(struct amdgpu_device *adev,
			struct ras_common_if *ras_block)
2551{
struct ras_query_if info = {
.head = *ras_block,
};

if (!amdgpu_persistent_edc_harvesting_supported(adev))
return 0;

if (amdgpu_ras_query_error_status(adev, &info) != 0)
DRM_WARN("RAS init harvest failure")printk("\0014" "[" "drm" "] " "RAS init harvest failure");

if (amdgpu_ras_reset_error_status(adev, ras_block->block) != 0)
DRM_WARN("RAS init harvest reset failure")printk("\0014" "[" "drm" "] " "RAS init harvest reset failure"
);

return 0;
2566}

2568bool_Bool amdgpu_ras_is_poison_mode_supported(struct amdgpu_device *adev)
2569{
     struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

     if (!con)
             return false0;

     return con->poison_supported;
2576}

2578/* helper function to handle common stuff in ip late init phase */
2579int amdgpu_ras_block_late_init(struct amdgpu_device *adev,
	 struct ras_common_if *ras_block)
2581{
struct amdgpu_ras_block_object *ras_obj = NULL((void *)0);
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
unsigned long ue_count, ce_count;
int r;

/* disable RAS feature per IP block if it is not supported */
if (!amdgpu_ras_is_supported(adev, ras_block->block)) {
amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0);
return 0;
}

r = amdgpu_ras_feature_enable_on_boot(adev, ras_block, 1);
if (r) {
if (adev->in_suspend || amdgpu_in_reset(adev)) {
	/* in resume phase, if fail to enable ras,
	 * clean up all ras fs nodes, and disable ras */
	goto cleanup;
} else
	return r;
}

/* check for errors on warm reset edc persisant supported ASIC */
amdgpu_persistent_edc_harvesting(adev, ras_block);

/* in resume phase, no need to create ras fs node */
if (adev->in_suspend || amdgpu_in_reset(adev))
return 0;

ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm)({ const __typeof( ((struct amdgpu_ras_block_object *)0)->
ras_comm ) *__mptr = (ras_block); (struct amdgpu_ras_block_object
 *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_ras_block_object
, ras_comm) );});
if (ras_obj->ras_cb || (ras_obj->hw_ops &&
   (ras_obj->hw_ops->query_poison_status ||
   ras_obj->hw_ops->handle_poison_consumption))) {
r = amdgpu_ras_interrupt_add_handler(adev, ras_block);
if (r)
	goto cleanup;
}

r = amdgpu_ras_sysfs_create(adev, ras_block);
if (r)
goto interrupt;

/* Those are the cached values at init.
*/
if (amdgpu_ras_query_error_count(adev, &ce_count, &ue_count) == 0) {
atomic_set(&con->ras_ce_count, ce_count)({ typeof(*(&con->ras_ce_count)) __tmp = ((ce_count));
 *(volatile typeof(*(&con->ras_ce_count)) *)&(*(&
con->ras_ce_count)) = __tmp; __tmp; });
atomic_set(&con->ras_ue_count, ue_count)({ typeof(*(&con->ras_ue_count)) __tmp = ((ue_count));
 *(volatile typeof(*(&con->ras_ue_count)) *)&(*(&
con->ras_ue_count)) = __tmp; __tmp; });
}

return 0;

2632interrupt:
if (ras_obj->ras_cb)
amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2635cleanup:
amdgpu_ras_feature_enable(adev, ras_block, 0);
return r;
2638}

2640static int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
	 struct ras_common_if *ras_block)
2642{
return amdgpu_ras_block_late_init(adev, ras_block);
2644}

2646/* helper function to remove ras fs node and interrupt handler */
2647void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
	  struct ras_common_if *ras_block)
2649{
struct amdgpu_ras_block_object *ras_obj;
if (!ras_block)
return;

amdgpu_ras_sysfs_remove(adev, ras_block);

ras_obj = container_of(ras_block, struct amdgpu_ras_block_object, ras_comm)({ const __typeof( ((struct amdgpu_ras_block_object *)0)->
ras_comm ) *__mptr = (ras_block); (struct amdgpu_ras_block_object
 *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_ras_block_object
, ras_comm) );});
if (ras_obj->ras_cb)
amdgpu_ras_interrupt_remove_handler(adev, ras_block);
2659}

2661static void amdgpu_ras_block_late_fini_default(struct amdgpu_device *adev,
	  struct ras_common_if *ras_block)
2663{
return amdgpu_ras_block_late_fini(adev, ras_block);
2665}

2667/* do some init work after IP late init as dependence.
* and it runs in resume/gpu reset/booting up cases.
*/
2670void amdgpu_ras_resume(struct amdgpu_device *adev)
2671{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
struct ras_manager *obj, *tmp;

if (!adev->ras_enabled || !con) {
/* clean ras context for VEGA20 Gaming after send ras disable cmd */
amdgpu_release_ras_context(adev);

return;
}

if (con->flags & AMDGPU_RAS_FLAG_INIT_BY_VBIOS(0x1 << 0)) {
/* Set up all other IPs which are not implemented. There is a
 * tricky thing that IP's actual ras error type should be
 * MULTI_UNCORRECTABLE, but as driver does not handle it, so
 * ERROR_NONE make sense anyway.
 */
amdgpu_ras_enable_all_features(adev, 1);

/* We enable ras on all hw_supported block, but as boot
 * parameter might disable some of them and one or more IP has
 * not implemented yet. So we disable them on behalf.
 */
list_for_each_entry_safe(obj, tmp, &con->head, node)for (obj = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = ((&con->head)->next); (__typeof(*obj) *)
( (char *)__mptr - __builtin_offsetof(__typeof(*obj), node) )
;}), tmp = ({ const __typeof( ((__typeof(*obj) *)0)->node )
 *__mptr = (obj->node.next); (__typeof(*obj) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*obj), node) );}); &obj->
node != (&con->head); obj = tmp, tmp = ({ const __typeof
( ((__typeof(*tmp) *)0)->node ) *__mptr = (tmp->node.next
); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*tmp), node) );})) {
	if (!amdgpu_ras_is_supported(adev, obj->head.block)) {
		amdgpu_ras_feature_enable(adev, &obj->head, 0);
		/* there should be no any reference. */
		WARN_ON(alive_obj(obj))({ int __ret = !!(((obj)->use)); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "((obj)->use)", "/usr/src/sys/dev/pci/drm/amd/amdgpu/amdgpu_ras.c"
, 2698); __builtin_expect(!!(__ret), 0); });
	}
}
}
2702}

2704void amdgpu_ras_suspend(struct amdgpu_device *adev)
2705{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

if (!adev->ras_enabled || !con)
return;

amdgpu_ras_disable_all_features(adev, 0);
/* Make sure all ras objects are disabled. */
if (con->features)
amdgpu_ras_disable_all_features(adev, 1);
2715}

2717int amdgpu_ras_late_init(struct amdgpu_device *adev)
2718{
struct amdgpu_ras_block_list *node, *tmp;
struct amdgpu_ras_block_object *obj;
int r;

/* Guest side doesn't need init ras feature */
if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
return 0;

list_for_each_entry_safe(node, tmp, &adev->ras_list, node)for (node = ({ const __typeof( ((__typeof(*node) *)0)->node
 ) *__mptr = ((&adev->ras_list)->next); (__typeof(*
node) *)( (char *)__mptr - __builtin_offsetof(__typeof(*node)
, node) );}), tmp = ({ const __typeof( ((__typeof(*node) *)0)
->node ) *__mptr = (node->node.next); (__typeof(*node) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*node), node)
 );}); &node->node != (&adev->ras_list); node =
 tmp, tmp = ({ const __typeof( ((__typeof(*tmp) *)0)->node
 ) *__mptr = (tmp->node.next); (__typeof(*tmp) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*tmp), node) );})) {
if (!node->ras_obj) {
	dev_warn(adev->dev, "Warning: abnormal ras list node.\n")printf("drm:pid%d:%s *WARNING* " "Warning: abnormal ras list node.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
	continue;
}

obj = node->ras_obj;
if (obj->ras_late_init) {
	r = obj->ras_late_init(adev, &obj->ras_comm);
	if (r) {
		dev_err(adev->dev, "%s failed to execute ras_late_init! ret:%d\n",printf("drm:pid%d:%s *ERROR* " "%s failed to execute ras_late_init! ret:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , obj->
ras_comm.name, r)
			obj->ras_comm.name, r)printf("drm:pid%d:%s *ERROR* " "%s failed to execute ras_late_init! ret:%d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , obj->
ras_comm.name, r);
		return r;
	}
} else
	amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
}

return 0;
2746}

2748/* do some fini work before IP fini as dependence */
2749int amdgpu_ras_pre_fini(struct amdgpu_device *adev)
2750{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
1
Calling 'amdgpu_ras_get_context'→
5
←
Returning from 'amdgpu_ras_get_context'→

if (!adev->ras_enabled || !con)
6
←
Assuming field 'ras_enabled' is not equal to 0→
7
←
Assuming 'con' is non-null→
8
←
Taking false branch→
return 0;


/* Need disable ras on all IPs here before ip [hw/sw]fini */
if (con->features)
9
←
Assuming field 'features' is not equal to 0→
10
←
Taking true branch→
amdgpu_ras_disable_all_features(adev, 0);
11
←
Calling 'amdgpu_ras_disable_all_features'→
amdgpu_ras_recovery_fini(adev);
return 0;
2762}

2764int amdgpu_ras_fini(struct amdgpu_device *adev)
2765{
struct amdgpu_ras_block_list *ras_node, *tmp;
struct amdgpu_ras_block_object *obj = NULL((void *)0);
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

if (!adev->ras_enabled || !con)
return 0;

list_for_each_entry_safe(ras_node, tmp, &adev->ras_list, node)for (ras_node = ({ const __typeof( ((__typeof(*ras_node) *)0)
->node ) *__mptr = ((&adev->ras_list)->next); (__typeof
(*ras_node) *)( (char *)__mptr - __builtin_offsetof(__typeof(
*ras_node), node) );}), tmp = ({ const __typeof( ((__typeof(*
ras_node) *)0)->node ) *__mptr = (ras_node->node.next);
 (__typeof(*ras_node) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*ras_node), node) );}); &ras_node->node != (
&adev->ras_list); ras_node = tmp, tmp = ({ const __typeof
( ((__typeof(*tmp) *)0)->node ) *__mptr = (tmp->node.next
); (__typeof(*tmp) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*tmp), node) );})) {
if (ras_node->ras_obj) {
	obj = ras_node->ras_obj;
	if (amdgpu_ras_is_supported(adev, obj->ras_comm.block) &&
	    obj->ras_fini)
		obj->ras_fini(adev, &obj->ras_comm);
	else
		amdgpu_ras_block_late_fini_default(adev, &obj->ras_comm);
}

/* Clear ras blocks from ras_list and free ras block list node */
list_del(&ras_node->node);
kfree(ras_node);
}

amdgpu_ras_fs_fini(adev);
amdgpu_ras_interrupt_remove_all(adev);

WARN(con->features, "Feature mask is not cleared")({ int __ret = !!(con->features); if (__ret) printf("Feature mask is not cleared"
); __builtin_expect(!!(__ret), 0); });

if (con->features)
amdgpu_ras_disable_all_features(adev, 1);

cancel_delayed_work_sync(&con->ras_counte_delay_work);

amdgpu_ras_set_context(adev, NULL((void *)0));
kfree(con);

return 0;
2802}

2804void amdgpu_ras_global_ras_isr(struct amdgpu_device *adev)
2805{
amdgpu_ras_check_supported(adev);
if (!adev->ras_hw_enabled)
return;

if (atomic_cmpxchg(&amdgpu_ras_in_intr, 0, 1)__sync_val_compare_and_swap(&amdgpu_ras_in_intr, 0, 1) == 0) {
dev_info(adev->dev, "uncorrectable hardware error"do { } while(0)
	"(ERREVENT_ATHUB_INTERRUPT) detected!\n")do { } while(0);

amdgpu_ras_reset_gpu(adev);
}
2816}

2818bool_Bool amdgpu_ras_need_emergency_restart(struct amdgpu_device *adev)
2819{
if (adev->asic_type == CHIP_VEGA20 &&
   adev->pm.fw_version <= 0x283400) {
return !(amdgpu_asic_reset_method(adev)(adev)->asic_funcs->reset_method((adev)) == AMD_RESET_METHOD_BACO) &&
		amdgpu_ras_intr_triggered();
}

return false0;
2827}

2829void amdgpu_release_ras_context(struct amdgpu_device *adev)
2830{
struct amdgpu_ras *con = amdgpu_ras_get_context(adev);

if (!con)
return;

if (!adev->ras_enabled && con->features & BIT(AMDGPU_RAS_BLOCK__GFX)(1UL << (AMDGPU_RAS_BLOCK__GFX))) {
con->features &= ~BIT(AMDGPU_RAS_BLOCK__GFX)(1UL << (AMDGPU_RAS_BLOCK__GFX));
amdgpu_ras_set_context(adev, NULL((void *)0));
kfree(con);
}
2841}

2843#ifdef CONFIG_X86_MCE_AMD
2844static struct amdgpu_device *find_adev(uint32_t node_id)
2845{
int i;
struct amdgpu_device *adev = NULL((void *)0);

for (i = 0; i < mce_adev_list.num_gpu; i++) {
adev = mce_adev_list.devs[i];

if (adev && adev->gmc.xgmi.connected_to_cpu &&
    adev->gmc.xgmi.physical_node_id == node_id)
	break;
adev = NULL((void *)0);
}

return adev;
2859}

2861#define GET_MCA_IPID_GPUID(m)	(((m) >> 44) & 0xF)
2862#define GET_UMC_INST(m)		(((m) >> 21) & 0x7)
2863#define GET_CHAN_INDEX(m)	((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
2864#define GPU_ID_OFFSET		8

2866static int amdgpu_bad_page_notifier(struct notifier_block *nb,
		    unsigned long val, void *data)
2868{
struct mce *m = (struct mce *)data;
struct amdgpu_device *adev = NULL((void *)0);
uint32_t gpu_id = 0;
uint32_t umc_inst = 0, ch_inst = 0;
struct ras_err_data err_data = {0, 0, 0, NULL((void *)0)};

/*
* If the error was generated in UMC_V2, which belongs to GPU UMCs,
* and error occurred in DramECC (Extended error code = 0) then only
* process the error, else bail out.
*/
if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) &&
    (XEC(m->status, 0x3f) == 0x0)))
return NOTIFY_DONE0;

/*
* If it is correctable error, return.
*/
if (mce_is_correctable(m))
return NOTIFY_OK1;

/*
* GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
*/
gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;

adev = find_adev(gpu_id);
if (!adev) {
DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,printk("\0014" "[" "drm" "] " "%s: Unable to find adev for gpu_id: %d\n"
, __func__, gpu_id)
						gpu_id)printk("\0014" "[" "drm" "] " "%s: Unable to find adev for gpu_id: %d\n"
, __func__, gpu_id);
return NOTIFY_DONE0;
}

/*
* If it is uncorrectable error, then find out UMC instance and
* channel index.
*/
umc_inst = GET_UMC_INST(m->ipid);
ch_inst = GET_CHAN_INDEX(m->ipid);

dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",do { } while(0)
	     umc_inst, ch_inst)do { } while(0);

err_data.err_addr =
kcalloc(adev->umc.max_ras_err_cnt_per_query,
	sizeof(struct eeprom_table_record), GFP_KERNEL(0x0001 | 0x0004));
if (!err_data.err_addr) {
dev_warn(adev->dev,printf("drm:pid%d:%s *WARNING* " "Failed to alloc memory for umc error record in mca notifier!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__)
	"Failed to alloc memory for umc error record in mca notifier!\n")printf("drm:pid%d:%s *WARNING* " "Failed to alloc memory for umc error record in mca notifier!\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return NOTIFY_DONE0;
}

/*
* Translate UMC channel address to Physical address
*/
if (adev->umc.ras &&
   adev->umc.ras->convert_ras_error_address)
adev->umc.ras->convert_ras_error_address(adev,
	&err_data, m->addr, ch_inst, umc_inst);

if (amdgpu_bad_page_threshold != 0) {
amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
				err_data.err_addr_cnt);
amdgpu_ras_save_bad_pages(adev);
}

kfree(err_data.err_addr);
return NOTIFY_OK1;
2937}

2939static struct notifier_block amdgpu_bad_page_nb = {
.notifier_call  = amdgpu_bad_page_notifier,
.priority       = MCE_PRIO_UC,
2942};

2944static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)
2945{
/*
* Add the adev to the mce_adev_list.
* During mode2 reset, amdgpu device is temporarily
* removed from the mgpu_info list which can cause
* page retirement to fail.
* Use this list instead of mgpu_info to find the amdgpu
* device on which the UMC error was reported.
*/
mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;

/*
* Register the x86 notifier only once
* with MCE subsystem.
*/
if (notifier_registered == false0) {
mce_register_decode_chain(&amdgpu_bad_page_nb);
notifier_registered = true1;
}
2964}
2965#endif

2967struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev)
2968{
if (!adev15.1
'adev' is non-null, which participates in a condition later
)
2
←
Assuming 'adev' is non-null→
3
←
Taking false branch→
16
←
Taking false branch→
return NULL((void *)0);

return adev->psp.ras_context.ras;
4
←
Returning pointer, which participates in a condition later→
17
←
Returning pointer, which participates in a condition later→
2973}

2975int amdgpu_ras_set_context(struct amdgpu_device *adev, struct amdgpu_ras *ras_con)
2976{
if (!adev)
return -EINVAL22;

adev->psp.ras_context.ras = ras_con;
return 0;
2982}

2984/* check if ras is supported on block, say, sdma, gfx */
2985int amdgpu_ras_is_supported(struct amdgpu_device *adev,
unsigned int block)
2987{
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

if (block >= AMDGPU_RAS_BLOCK_COUNTAMDGPU_RAS_BLOCK__LAST)
return 0;
return ras && (adev->ras_enabled & (1 << block));
2993}

2995int amdgpu_ras_reset_gpu(struct amdgpu_device *adev)
2996{
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);

if (atomic_cmpxchg(&ras->in_recovery, 0, 1)__sync_val_compare_and_swap(&ras->in_recovery, 0, 1) == 0)
amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work);
return 0;
3002}


3005/* Register each ip ras block into amdgpu ras */
3006int amdgpu_ras_register_ras_block(struct amdgpu_device *adev,
struct amdgpu_ras_block_object *ras_block_obj)
3008{
struct amdgpu_ras_block_list *ras_node;
if (!adev || !ras_block_obj)
return -EINVAL22;

if (!amdgpu_ras_asic_supported(adev))
return 0;

ras_node = kzalloc(sizeof(*ras_node), GFP_KERNEL(0x0001 | 0x0004));
if (!ras_node)
return -ENOMEM12;

INIT_LIST_HEAD(&ras_node->node);
ras_node->ras_obj = ras_block_obj;
list_add_tail(&ras_node->node, &adev->ras_list);

return 0;
3025}