Bug Summary

File:dev/pci/if_em_hw.c
Warning:line 351, column 3
3rd function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name if_em_hw.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/if_em_hw.c
1/*******************************************************************************
2
3 Copyright (c) 2001-2005, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33
34/* $OpenBSD: if_em_hw.c,v 1.119 2023/12/03 00:19:25 jsg Exp $ */
35/*
36 * if_em_hw.c Shared functions for accessing and configuring the MAC
37 */
38
39#include <sys/param.h>
40#include <sys/systm.h>
41#include <sys/sockio.h>
42#include <sys/mbuf.h>
43#include <sys/malloc.h>
44#include <sys/kernel.h>
45#include <sys/device.h>
46#include <sys/socket.h>
47#include <sys/kstat.h>
48
49#include <net/if.h>
50#include <net/if_media.h>
51
52#include <netinet/in.h>
53#include <netinet/if_ether.h>
54
55#include <uvm/uvm_extern.h>
56
57#include <dev/pci/pcireg.h>
58#include <dev/pci/pcivar.h>
59
60#include <dev/pci/if_em.h>
61#include <dev/pci/if_em_hw.h>
62#include <dev/pci/if_em_soc.h>
63
64#include <dev/mii/rgephyreg.h>
65
66#define STATIC
67
68static int32_t em_swfw_sync_acquire(struct em_hw *, uint16_t);
69static void em_swfw_sync_release(struct em_hw *, uint16_t);
70static int32_t em_read_kmrn_reg(struct em_hw *, uint32_t, uint16_t *);
71static int32_t em_write_kmrn_reg(struct em_hw *hw, uint32_t, uint16_t);
72static int32_t em_get_software_semaphore(struct em_hw *);
73static void em_release_software_semaphore(struct em_hw *);
74
75static int32_t em_check_downshift(struct em_hw *);
76static void em_clear_vfta(struct em_hw *);
77void em_clear_vfta_i350(struct em_hw *);
78static int32_t em_commit_shadow_ram(struct em_hw *);
79static int32_t em_config_dsp_after_link_change(struct em_hw *, boolean_t);
80static int32_t em_config_fc_after_link_up(struct em_hw *);
81static int32_t em_match_gig_phy(struct em_hw *);
82static int32_t em_detect_gig_phy(struct em_hw *);
83static int32_t em_erase_ich8_4k_segment(struct em_hw *, uint32_t);
84static int32_t em_get_auto_rd_done(struct em_hw *);
85static int32_t em_get_cable_length(struct em_hw *, uint16_t *, uint16_t *);
86static int32_t em_get_hw_eeprom_semaphore(struct em_hw *);
87static int32_t em_get_phy_cfg_done(struct em_hw *);
88static int32_t em_get_software_flag(struct em_hw *);
89static int32_t em_ich8_cycle_init(struct em_hw *);
90static int32_t em_ich8_flash_cycle(struct em_hw *, uint32_t);
91static int32_t em_id_led_init(struct em_hw *);
92static int32_t em_init_lcd_from_nvm_config_region(struct em_hw *, uint32_t,
93 uint32_t);
94static int32_t em_init_lcd_from_nvm(struct em_hw *);
95static int32_t em_phy_no_cable_workaround(struct em_hw *);
96static void em_init_rx_addrs(struct em_hw *);
97static void em_initialize_hardware_bits(struct em_softc *);
98static void em_toggle_lanphypc_pch_lpt(struct em_hw *);
99static int em_disable_ulp_lpt_lp(struct em_hw *hw, bool_Bool force);
100static boolean_t em_is_onboard_nvm_eeprom(struct em_hw *);
101static int32_t em_kumeran_lock_loss_workaround(struct em_hw *);
102static int32_t em_mng_enable_host_if(struct em_hw *);
103static int32_t em_read_eeprom_eerd(struct em_hw *, uint16_t, uint16_t,
104 uint16_t *);
105static int32_t em_write_eeprom_eewr(struct em_hw *, uint16_t, uint16_t,
106 uint16_t *data);
107static int32_t em_poll_eerd_eewr_done(struct em_hw *, int);
108static void em_put_hw_eeprom_semaphore(struct em_hw *);
109static int32_t em_read_ich8_byte(struct em_hw *, uint32_t, uint8_t *);
110static int32_t em_verify_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
111static int32_t em_write_ich8_byte(struct em_hw *, uint32_t, uint8_t);
112static int32_t em_read_ich8_word(struct em_hw *, uint32_t, uint16_t *);
113static int32_t em_read_ich8_dword(struct em_hw *, uint32_t, uint32_t *);
114static int32_t em_read_ich8_data(struct em_hw *, uint32_t, uint32_t,
115 uint16_t *);
116static int32_t em_write_ich8_data(struct em_hw *, uint32_t, uint32_t,
117 uint16_t);
118static int32_t em_read_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
119 uint16_t *);
120static int32_t em_write_eeprom_ich8(struct em_hw *, uint16_t, uint16_t,
121 uint16_t *);
122static int32_t em_read_invm_i210(struct em_hw *, uint16_t, uint16_t,
123 uint16_t *);
124static int32_t em_read_invm_word_i210(struct em_hw *, uint16_t, uint16_t *);
125static void em_release_software_flag(struct em_hw *);
126static int32_t em_set_d3_lplu_state(struct em_hw *, boolean_t);
127static int32_t em_set_d0_lplu_state(struct em_hw *, boolean_t);
128static int32_t em_set_lplu_state_pchlan(struct em_hw *, boolean_t);
129static int32_t em_set_pci_ex_no_snoop(struct em_hw *, uint32_t);
130static void em_set_pci_express_master_disable(struct em_hw *);
131static int32_t em_wait_autoneg(struct em_hw *);
132static void em_write_reg_io(struct em_hw *, uint32_t, uint32_t);
133static int32_t em_set_phy_type(struct em_hw *);
134static void em_phy_init_script(struct em_hw *);
135static int32_t em_setup_copper_link(struct em_hw *);
136static int32_t em_setup_fiber_serdes_link(struct em_hw *);
137static int32_t em_adjust_serdes_amplitude(struct em_hw *);
138static int32_t em_phy_force_speed_duplex(struct em_hw *);
139static int32_t em_config_mac_to_phy(struct em_hw *);
140static void em_raise_mdi_clk(struct em_hw *, uint32_t *);
141static void em_lower_mdi_clk(struct em_hw *, uint32_t *);
142static void em_shift_out_mdi_bits(struct em_hw *, uint32_t, uint16_t);
143static uint16_t em_shift_in_mdi_bits(struct em_hw *);
144static int32_t em_phy_reset_dsp(struct em_hw *);
145static int32_t em_write_eeprom_spi(struct em_hw *, uint16_t, uint16_t,
146 uint16_t *);
147static int32_t em_write_eeprom_microwire(struct em_hw *, uint16_t, uint16_t,
148 uint16_t *);
149static int32_t em_spi_eeprom_ready(struct em_hw *);
150static void em_raise_ee_clk(struct em_hw *, uint32_t *);
151static void em_lower_ee_clk(struct em_hw *, uint32_t *);
152static void em_shift_out_ee_bits(struct em_hw *, uint16_t, uint16_t);
153static int32_t em_write_phy_reg_ex(struct em_hw *, uint32_t, uint16_t);
154static int32_t em_read_phy_reg_ex(struct em_hw *, uint32_t, uint16_t *);
155static uint16_t em_shift_in_ee_bits(struct em_hw *, uint16_t);
156static int32_t em_acquire_eeprom(struct em_hw *);
157static void em_release_eeprom(struct em_hw *);
158static void em_standby_eeprom(struct em_hw *);
159static int32_t em_set_vco_speed(struct em_hw *);
160static int32_t em_polarity_reversal_workaround(struct em_hw *);
161static int32_t em_set_phy_mode(struct em_hw *);
162static int32_t em_host_if_read_cookie(struct em_hw *, uint8_t *);
163static uint8_t em_calculate_mng_checksum(char *, uint32_t);
164static int32_t em_configure_kmrn_for_10_100(struct em_hw *, uint16_t);
165static int32_t em_configure_kmrn_for_1000(struct em_hw *);
166static int32_t em_set_pciex_completion_timeout(struct em_hw *hw);
167static int32_t em_set_mdio_slow_mode_hv(struct em_hw *);
168int32_t em_hv_phy_workarounds_ich8lan(struct em_hw *);
169int32_t em_lv_phy_workarounds_ich8lan(struct em_hw *);
170int32_t em_link_stall_workaround_hv(struct em_hw *);
171int32_t em_k1_gig_workaround_hv(struct em_hw *, boolean_t);
172int32_t em_k1_workaround_lv(struct em_hw *);
173int32_t em_k1_workaround_lpt_lp(struct em_hw *, boolean_t);
174int32_t em_configure_k1_ich8lan(struct em_hw *, boolean_t);
175void em_gate_hw_phy_config_ich8lan(struct em_hw *, boolean_t);
176int32_t em_access_phy_wakeup_reg_bm(struct em_hw *, uint32_t,
177 uint16_t *, boolean_t);
178int32_t em_access_phy_debug_regs_hv(struct em_hw *, uint32_t,
179 uint16_t *, boolean_t);
180int32_t em_access_phy_reg_hv(struct em_hw *, uint32_t, uint16_t *,
181 boolean_t);
182int32_t em_oem_bits_config_pchlan(struct em_hw *, boolean_t);
183void em_power_up_serdes_link_82575(struct em_hw *);
184int32_t em_get_pcs_speed_and_duplex_82575(struct em_hw *, uint16_t *,
185 uint16_t *);
186int32_t em_set_eee_i350(struct em_hw *);
187int32_t em_set_eee_pchlan(struct em_hw *);
188int32_t em_valid_nvm_bank_detect_ich8lan(struct em_hw *, uint32_t *);
189int32_t em_initialize_M88E1512_phy(struct em_hw *);
190
191/* IGP cable length table */
192static const uint16_t
193em_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE128] =
194 {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
195 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
196 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
197 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
198 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
199 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
200 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
201 110,
202 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120,
203 120};
204
205static const uint16_t
206em_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE113] =
207 {0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
208 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
209 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
210 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
211 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
212 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
213 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118,
214 121, 124};
215
216/******************************************************************************
217 * Set the phy type member in the hw struct.
218 *
219 * hw - Struct containing variables accessed by shared code
220 *****************************************************************************/
221STATIC int32_t
222em_set_phy_type(struct em_hw *hw)
223{
224 DEBUGFUNC("em_set_phy_type");;
225
226 if (hw->mac_type == em_undefined)
227 return -E1000_ERR_PHY_TYPE6;
228
229 switch (hw->phy_id) {
230 case M88E1000_E_PHY_ID0x01410C50:
231 case M88E1000_I_PHY_ID0x01410C30:
232 case M88E1011_I_PHY_ID0x01410C20:
233 case M88E1111_I_PHY_ID0x01410CC0:
234 case M88E1112_E_PHY_ID0x01410C90:
235 case M88E1543_E_PHY_ID0x01410EA0:
236 case M88E1512_E_PHY_ID0x01410DD0:
237 case I210_I_PHY_ID0x01410C00:
238 case I347AT4_E_PHY_ID0x01410DC0:
239 hw->phy_type = em_phy_m88;
240 break;
241 case IGP01E1000_I_PHY_ID0x02A80380:
242 if (hw->mac_type == em_82541 ||
243 hw->mac_type == em_82541_rev_2 ||
244 hw->mac_type == em_82547 ||
245 hw->mac_type == em_82547_rev_2) {
246 hw->phy_type = em_phy_igp;
247 break;
248 }
249 case IGP03E1000_E_PHY_ID0x02A80390:
250 case IGP04E1000_E_PHY_ID0x02A80391:
251 hw->phy_type = em_phy_igp_3;
252 break;
253 case IFE_E_PHY_ID0x02A80330:
254 case IFE_PLUS_E_PHY_ID0x02A80320:
255 case IFE_C_E_PHY_ID0x02A80310:
256 hw->phy_type = em_phy_ife;
257 break;
258 case M88E1141_E_PHY_ID0x01410CD0:
259 hw->phy_type = em_phy_oem;
260 break;
261 case I82577_E_PHY_ID0x01540050:
262 hw->phy_type = em_phy_82577;
263 break;
264 case I82578_E_PHY_ID0x004DD040:
265 hw->phy_type = em_phy_82578;
266 break;
267 case I82579_E_PHY_ID0x01540090:
268 hw->phy_type = em_phy_82579;
269 break;
270 case I217_E_PHY_ID0x015400A0:
271 hw->phy_type = em_phy_i217;
272 break;
273 case I82580_I_PHY_ID0x015403A0:
274 case I350_I_PHY_ID0x015403B0:
275 hw->phy_type = em_phy_82580;
276 break;
277 case RTL8211_E_PHY_ID0x001CC912:
278 hw->phy_type = em_phy_rtl8211;
279 break;
280 case BME1000_E_PHY_ID0x01410CB0:
281 if (hw->phy_revision == 1) {
282 hw->phy_type = em_phy_bm;
283 break;
284 }
285 /* FALLTHROUGH */
286 case GG82563_E_PHY_ID0x01410CA0:
287 if (hw->mac_type == em_80003es2lan) {
288 hw->phy_type = em_phy_gg82563;
289 break;
290 }
291 /* FALLTHROUGH */
292 default:
293 /* Should never have loaded on this device */
294 hw->phy_type = em_phy_undefined;
295 return -E1000_ERR_PHY_TYPE6;
296 }
297
298 return E1000_SUCCESS0;
299}
300
301/******************************************************************************
302 * IGP phy init script - initializes the GbE PHY
303 *
304 * hw - Struct containing variables accessed by shared code
305 *****************************************************************************/
306static void
307em_phy_init_script(struct em_hw *hw)
308{
309 uint16_t phy_saved_data;
172
←
'phy_saved_data' declared without an initial value
→
310 DEBUGFUNC("em_phy_init_script");;
311
312 if (hw->phy_init_script) {
173
←
Assuming field 'phy_init_script' is not equal to 0
→
174
←
Taking true branch
→
313 msec_delay(20)(*delay_func)(1000*(20));
314 /*
315 * Save off the current value of register 0x2F5B to be
316 * restored at the end of this routine.
317 */
318 em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
175
←
Calling 'em_read_phy_reg'
→
189
←
Returning from 'em_read_phy_reg'
→
319
320 /* Disabled the PHY transmitter */
321 em_write_phy_reg(hw, 0x2F5B, 0x0003);
322 msec_delay(20)(*delay_func)(1000*(20));
323 em_write_phy_reg(hw, 0x0000, 0x0140);
324 msec_delay(5)(*delay_func)(1000*(5));
325
326 switch (hw->mac_type) {
190
←
Control jumps to the 'default' case at line 343
→
327 case em_82541:
328 case em_82547:
329 em_write_phy_reg(hw, 0x1F95, 0x0001);
330 em_write_phy_reg(hw, 0x1F71, 0xBD21);
331 em_write_phy_reg(hw, 0x1F79, 0x0018);
332 em_write_phy_reg(hw, 0x1F30, 0x1600);
333 em_write_phy_reg(hw, 0x1F31, 0x0014);
334 em_write_phy_reg(hw, 0x1F32, 0x161C);
335 em_write_phy_reg(hw, 0x1F94, 0x0003);
336 em_write_phy_reg(hw, 0x1F96, 0x003F);
337 em_write_phy_reg(hw, 0x2010, 0x0008);
338 break;
339 case em_82541_rev_2:
340 case em_82547_rev_2:
341 em_write_phy_reg(hw, 0x1F73, 0x0099);
342 break;
343 default:
344 break;
345 }
346
347 em_write_phy_reg(hw, 0x0000, 0x3300);
348 msec_delay(20)(*delay_func)(1000*(20));
349
350 /* Now enable the transmitter */
351 em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
191
←
3rd function call argument is an uninitialized value
352
353 if (hw->mac_type == em_82547) {
354 uint16_t fused, fine, coarse;
355 /* Move to analog registers page */
356 em_read_phy_reg(hw,
357 IGP01E1000_ANALOG_SPARE_FUSE_STATUS0x20D1, &fused);
358
359 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED0x0100)) {
360 em_read_phy_reg(hw,
361 IGP01E1000_ANALOG_FUSE_STATUS0x20D0, &fused);
362
363 fine = fused &
364 IGP01E1000_ANALOG_FUSE_FINE_MASK0x0F80;
365 coarse = fused &
366 IGP01E1000_ANALOG_FUSE_COARSE_MASK0x0070;
367
368 if (coarse >
369 IGP01E1000_ANALOG_FUSE_COARSE_THRESH0x0040) {
370 coarse -=
371 IGP01E1000_ANALOG_FUSE_COARSE_100x0010;
372 fine -=
373 IGP01E1000_ANALOG_FUSE_FINE_10x0080;
374 } else if (coarse ==
375 IGP01E1000_ANALOG_FUSE_COARSE_THRESH0x0040)
376 fine -= IGP01E1000_ANALOG_FUSE_FINE_100x0500;
377
378 fused = (fused &
379 IGP01E1000_ANALOG_FUSE_POLY_MASK0xF000) |
380 (fine &
381 IGP01E1000_ANALOG_FUSE_FINE_MASK0x0F80) |
382 (coarse &
383 IGP01E1000_ANALOG_FUSE_COARSE_MASK0x0070);
384
385 em_write_phy_reg(hw,
386 IGP01E1000_ANALOG_FUSE_CONTROL0x20DC,
387 fused);
388
389 em_write_phy_reg(hw,
390 IGP01E1000_ANALOG_FUSE_BYPASS0x20DE,
391 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL0x0002);
392 }
393 }
394 }
395}
396
397/******************************************************************************
398 * Set the mac type member in the hw struct.
399 *
400 * hw - Struct containing variables accessed by shared code
401 *****************************************************************************/
402int32_t
403em_set_mac_type(struct em_hw *hw)
404{
405 DEBUGFUNC("em_set_mac_type");;
406
407 switch (hw->device_id) {
408 case E1000_DEV_ID_825420x1000:
409 switch (hw->revision_id) {
410 case E1000_82542_2_0_REV_ID2:
411 hw->mac_type = em_82542_rev2_0;
412 break;
413 case E1000_82542_2_1_REV_ID3:
414 hw->mac_type = em_82542_rev2_1;
415 break;
416 default:
417 /* Invalid 82542 revision ID */
418 return -E1000_ERR_MAC_TYPE5;
419 }
420 break;
421 case E1000_DEV_ID_82543GC_FIBER0x1001:
422 case E1000_DEV_ID_82543GC_COPPER0x1004:
423 hw->mac_type = em_82543;
424 break;
425 case E1000_DEV_ID_82544EI_COPPER0x1008:
426 case E1000_DEV_ID_82544EI_FIBER0x1009:
427 case E1000_DEV_ID_82544GC_COPPER0x100C:
428 case E1000_DEV_ID_82544GC_LOM0x100D:
429 hw->mac_type = em_82544;
430 break;
431 case E1000_DEV_ID_82540EM0x100E:
432 case E1000_DEV_ID_82540EM_LOM0x1015:
433 case E1000_DEV_ID_82540EP0x1017:
434 case E1000_DEV_ID_82540EP_LOM0x1016:
435 case E1000_DEV_ID_82540EP_LP0x101E:
436 hw->mac_type = em_82540;
437 break;
438 case E1000_DEV_ID_82545EM_COPPER0x100F:
439 case E1000_DEV_ID_82545EM_FIBER0x1011:
440 hw->mac_type = em_82545;
441 break;
442 case E1000_DEV_ID_82545GM_COPPER0x1026:
443 case E1000_DEV_ID_82545GM_FIBER0x1027:
444 case E1000_DEV_ID_82545GM_SERDES0x1028:
445 hw->mac_type = em_82545_rev_3;
446 break;
447 case E1000_DEV_ID_82546EB_COPPER0x1010:
448 case E1000_DEV_ID_82546EB_FIBER0x1012:
449 case E1000_DEV_ID_82546EB_QUAD_COPPER0x101D:
450 hw->mac_type = em_82546;
451 break;
452 case E1000_DEV_ID_82546GB_COPPER0x1079:
453 case E1000_DEV_ID_82546GB_FIBER0x107A:
454 case E1000_DEV_ID_82546GB_SERDES0x107B:
455 case E1000_DEV_ID_82546GB_PCIE0x108A:
456 case E1000_DEV_ID_82546GB_QUAD_COPPER0x1099:
457 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP30x10B5:
458 case E1000_DEV_ID_82546GB_20x109B:
459 hw->mac_type = em_82546_rev_3;
460 break;
461 case E1000_DEV_ID_82541EI0x1013:
462 case E1000_DEV_ID_82541EI_MOBILE0x1018:
463 case E1000_DEV_ID_82541ER_LOM0x1014:
464 hw->mac_type = em_82541;
465 break;
466 case E1000_DEV_ID_82541ER0x1078:
467 case E1000_DEV_ID_82541GI0x1076:
468 case E1000_DEV_ID_82541GI_LF0x107C:
469 case E1000_DEV_ID_82541GI_MOBILE0x1077:
470 hw->mac_type = em_82541_rev_2;
471 break;
472 case E1000_DEV_ID_82547EI0x1019:
473 case E1000_DEV_ID_82547EI_MOBILE0x101A:
474 hw->mac_type = em_82547;
475 break;
476 case E1000_DEV_ID_82547GI0x1075:
477 hw->mac_type = em_82547_rev_2;
478 break;
479 case E1000_DEV_ID_82571EB_AF0x10A1:
480 case E1000_DEV_ID_82571EB_AT0x10A0:
481 case E1000_DEV_ID_82571EB_COPPER0x105E:
482 case E1000_DEV_ID_82571EB_FIBER0x105F:
483 case E1000_DEV_ID_82571EB_SERDES0x1060:
484 case E1000_DEV_ID_82571EB_QUAD_COPPER0x10A4:
485 case E1000_DEV_ID_82571EB_QUAD_FIBER0x10A5:
486 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP0x10BC:
487 case E1000_DEV_ID_82571EB_SERDES_DUAL0x10D9:
488 case E1000_DEV_ID_82571EB_SERDES_QUAD0x10DA:
489 case E1000_DEV_ID_82571PT_QUAD_COPPER0x10D5:
490 hw->mac_type = em_82571;
491 break;
492 case E1000_DEV_ID_82572EI_COPPER0x107D:
493 case E1000_DEV_ID_82572EI_FIBER0x107E:
494 case E1000_DEV_ID_82572EI_SERDES0x107F:
495 case E1000_DEV_ID_82572EI0x10B9:
496 hw->mac_type = em_82572;
497 break;
498 case E1000_DEV_ID_82573E0x108B:
499 case E1000_DEV_ID_82573E_IAMT0x108C:
500 case E1000_DEV_ID_82573E_PM0x10B3:
501 case E1000_DEV_ID_82573L0x109A:
502 case E1000_DEV_ID_82573L_PL_10x10B0:
503 case E1000_DEV_ID_82573L_PL_20x10B4:
504 case E1000_DEV_ID_82573V_PM0x10B2:
505 hw->mac_type = em_82573;
506 break;
507 case E1000_DEV_ID_82574L0x10D3:
508 case E1000_DEV_ID_82574LA0x10F6:
509 case E1000_DEV_ID_82583V0x150C:
510 hw->mac_type = em_82574;
511 break;
512 case E1000_DEV_ID_82575EB_PT0x10A7:
513 case E1000_DEV_ID_82575EB_PF0x10A9:
514 case E1000_DEV_ID_82575GB_QP0x10D6:
515 case E1000_DEV_ID_82575GB_QP_PM0x10E2:
516 hw->mac_type = em_82575;
517 hw->initialize_hw_bits_disable = 1;
518 break;
519 case E1000_DEV_ID_825760x10C9:
520 case E1000_DEV_ID_82576_FIBER0x10E6:
521 case E1000_DEV_ID_82576_SERDES0x10E7:
522 case E1000_DEV_ID_82576_QUAD_COPPER0x10E8:
523 case E1000_DEV_ID_82576_QUAD_CU_ET20x1526:
524 case E1000_DEV_ID_82576_NS0x150A:
525 case E1000_DEV_ID_82576_NS_SERDES0x1518:
526 case E1000_DEV_ID_82576_SERDES_QUAD0x150D:
527 hw->mac_type = em_82576;
528 hw->initialize_hw_bits_disable = 1;
529 break;
530 case E1000_DEV_ID_82580_COPPER0x150E:
531 case E1000_DEV_ID_82580_FIBER0x150F:
532 case E1000_DEV_ID_82580_QUAD_FIBER0x1527:
533 case E1000_DEV_ID_82580_SERDES0x1510:
534 case E1000_DEV_ID_82580_SGMII0x1511:
535 case E1000_DEV_ID_82580_COPPER_DUAL0x1516:
536 case E1000_DEV_ID_DH89XXCC_SGMII0x0438:
537 case E1000_DEV_ID_DH89XXCC_SERDES0x043A:
538 case E1000_DEV_ID_DH89XXCC_BACKPLANE0x043C:
539 case E1000_DEV_ID_DH89XXCC_SFP0x0440:
540 hw->mac_type = em_82580;
541 hw->initialize_hw_bits_disable = 1;
542 break;
543 case E1000_DEV_ID_I210_COPPER0x1533:
544 case E1000_DEV_ID_I210_COPPER_OEM10x1534:
545 case E1000_DEV_ID_I210_COPPER_IT0x1535:
546 case E1000_DEV_ID_I210_FIBER0x1536:
547 case E1000_DEV_ID_I210_SERDES0x1537:
548 case E1000_DEV_ID_I210_SGMII0x1538:
549 case E1000_DEV_ID_I210_COPPER_FLASHLESS0x157B:
550 case E1000_DEV_ID_I210_SERDES_FLASHLESS0x157C:
551 case E1000_DEV_ID_I211_COPPER0x1539:
552 hw->mac_type = em_i210;
553 hw->initialize_hw_bits_disable = 1;
554 hw->eee_enable = 1;
555 break;
556 case E1000_DEV_ID_I350_COPPER0x1521:
557 case E1000_DEV_ID_I350_FIBER0x1522:
558 case E1000_DEV_ID_I350_SERDES0x1523:
559 case E1000_DEV_ID_I350_SGMII0x1524:
560 case E1000_DEV_ID_I350_DA40x1546:
561 case E1000_DEV_ID_I354_BACKPLANE_1GBPS0x1F40:
562 case E1000_DEV_ID_I354_SGMII0x1F41:
563 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS0x1F45:
564 hw->mac_type = em_i350;
565 hw->initialize_hw_bits_disable = 1;
566 hw->eee_enable = 1;
567 break;
568 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT0x10BA:
569 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT0x10BB:
570 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT0x1096:
571 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT0x1098:
572 hw->mac_type = em_80003es2lan;
573 break;
574 case E1000_DEV_ID_ICH8_IFE0x104C:
575 case E1000_DEV_ID_ICH8_IFE_G0x10C5:
576 case E1000_DEV_ID_ICH8_IFE_GT0x10C4:
577 case E1000_DEV_ID_ICH8_IGP_AMT0x104A:
578 case E1000_DEV_ID_ICH8_IGP_C0x104B:
579 case E1000_DEV_ID_ICH8_IGP_M0x104D:
580 case E1000_DEV_ID_ICH8_IGP_M_AMT0x1049:
581 case E1000_DEV_ID_ICH8_82567V_30x1501:
582 hw->mac_type = em_ich8lan;
583 break;
584 case E1000_DEV_ID_ICH9_BM0x10E5:
585 case E1000_DEV_ID_ICH9_IFE0x10C0:
586 case E1000_DEV_ID_ICH9_IFE_G0x10C2:
587 case E1000_DEV_ID_ICH9_IFE_GT0x10C3:
588 case E1000_DEV_ID_ICH9_IGP_AMT0x10BD:
589 case E1000_DEV_ID_ICH9_IGP_C0x294C:
590 case E1000_DEV_ID_ICH9_IGP_M0x10BF:
591 case E1000_DEV_ID_ICH9_IGP_M_AMT0x10F5:
592 case E1000_DEV_ID_ICH9_IGP_M_V0x10CB:
593 case E1000_DEV_ID_ICH10_R_BM_LF0x10CD:
594 case E1000_DEV_ID_ICH10_R_BM_LM0x10CC:
595 case E1000_DEV_ID_ICH10_R_BM_V0x10CE:
596 hw->mac_type = em_ich9lan;
597 break;
598 case E1000_DEV_ID_ICH10_D_BM_LF0x10DF:
599 case E1000_DEV_ID_ICH10_D_BM_LM0x10DE:
600 case E1000_DEV_ID_ICH10_D_BM_V0x1525:
601 hw->mac_type = em_ich10lan;
602 break;
603 case E1000_DEV_ID_PCH_M_HV_LC0x10EB:
604 case E1000_DEV_ID_PCH_M_HV_LM0x10EA:
605 case E1000_DEV_ID_PCH_D_HV_DC0x10F0:
606 case E1000_DEV_ID_PCH_D_HV_DM0x10EF:
607 hw->mac_type = em_pchlan;
608 hw->eee_enable = 1;
609 break;
610 case E1000_DEV_ID_PCH2_LV_LM0x1502:
611 case E1000_DEV_ID_PCH2_LV_V0x1503:
612 hw->mac_type = em_pch2lan;
613 break;
614 case E1000_DEV_ID_PCH_LPT_I217_LM0x153A:
615 case E1000_DEV_ID_PCH_LPT_I217_V0x153B:
616 case E1000_DEV_ID_PCH_LPTLP_I218_LM0x155A:
617 case E1000_DEV_ID_PCH_LPTLP_I218_V0x1559:
618 case E1000_DEV_ID_PCH_I218_LM20x15A0:
619 case E1000_DEV_ID_PCH_I218_V20x15A1:
620 case E1000_DEV_ID_PCH_I218_LM30x15A2:
621 case E1000_DEV_ID_PCH_I218_V30x15A3:
622 hw->mac_type = em_pch_lpt;
623 break;
624 case E1000_DEV_ID_PCH_SPT_I219_LM0x156F:
625 case E1000_DEV_ID_PCH_SPT_I219_V0x1570:
626 case E1000_DEV_ID_PCH_SPT_I219_LM20x15B7:
627 case E1000_DEV_ID_PCH_SPT_I219_V20x15B8:
628 case E1000_DEV_ID_PCH_LBG_I219_LM30x15B9:
629 case E1000_DEV_ID_PCH_SPT_I219_LM40x15D7:
630 case E1000_DEV_ID_PCH_SPT_I219_V40x15D8:
631 case E1000_DEV_ID_PCH_SPT_I219_LM50x15E3:
632 case E1000_DEV_ID_PCH_SPT_I219_V50x15D6:
633 case E1000_DEV_ID_PCH_CMP_I219_LM120x0D53:
634 case E1000_DEV_ID_PCH_CMP_I219_V120x0D55:
635 hw->mac_type = em_pch_spt;
636 break;
637 case E1000_DEV_ID_PCH_CNP_I219_LM60x15BD:
638 case E1000_DEV_ID_PCH_CNP_I219_V60x15BE:
639 case E1000_DEV_ID_PCH_CNP_I219_LM70x15BB:
640 case E1000_DEV_ID_PCH_CNP_I219_V70x15BC:
641 case E1000_DEV_ID_PCH_ICP_I219_LM80x15DF:
642 case E1000_DEV_ID_PCH_ICP_I219_V80x15E0:
643 case E1000_DEV_ID_PCH_ICP_I219_LM90x15E1:
644 case E1000_DEV_ID_PCH_ICP_I219_V90x15E2:
645 case E1000_DEV_ID_PCH_CMP_I219_LM100x0D4E:
646 case E1000_DEV_ID_PCH_CMP_I219_V100x0D4F:
647 case E1000_DEV_ID_PCH_CMP_I219_LM110x0D4C:
648 case E1000_DEV_ID_PCH_CMP_I219_V110x0D4D:
649 hw->mac_type = em_pch_cnp;
650 break;
651 case E1000_DEV_ID_PCH_TGP_I219_LM130x15FB:
652 case E1000_DEV_ID_PCH_TGP_I219_V130x15FC:
653 case E1000_DEV_ID_PCH_TGP_I219_LM140x15F9:
654 case E1000_DEV_ID_PCH_TGP_I219_V140x15FA:
655 case E1000_DEV_ID_PCH_TGP_I219_LM150x15F4:
656 case E1000_DEV_ID_PCH_TGP_I219_V150x15F5:
657 hw->mac_type = em_pch_tgp;
658 break;
659 case E1000_DEV_ID_PCH_ADP_I219_LM160x1A1E:
660 case E1000_DEV_ID_PCH_ADP_I219_V160x1A1F:
661 case E1000_DEV_ID_PCH_ADP_I219_LM170x1A1C:
662 case E1000_DEV_ID_PCH_ADP_I219_V170x1A1D:
663 case E1000_DEV_ID_PCH_RPL_I219_LM220x0DC7:
664 case E1000_DEV_ID_PCH_RPL_I219_V220x0DC8:
665 case E1000_DEV_ID_PCH_RPL_I219_LM230x0DC5:
666 case E1000_DEV_ID_PCH_RPL_I219_V230x0DC6:
667 hw->mac_type = em_pch_adp;
668 break;
669 case E1000_DEV_ID_PCH_MTP_I219_LM180x550A:
670 case E1000_DEV_ID_PCH_MTP_I219_V180x550B:
671 case E1000_DEV_ID_PCH_MTP_I219_LM190x550C:
672 case E1000_DEV_ID_PCH_MTP_I219_V190x550D:
673 case E1000_DEV_ID_PCH_LNP_I219_LM200x550E:
674 case E1000_DEV_ID_PCH_LNP_I219_V200x550F:
675 case E1000_DEV_ID_PCH_LNP_I219_LM210x5510:
676 case E1000_DEV_ID_PCH_LNP_I219_V210x5511:
677 case E1000_DEV_ID_PCH_ARL_I219_LM240x57A0:
678 case E1000_DEV_ID_PCH_ARL_I219_V240x57A1:
679 hw->mac_type = em_pch_adp; /* pch_mtp */
680 break;
681 case E1000_DEV_ID_EP80579_LAN_10x5040:
682 hw->mac_type = em_icp_xxxx;
683 hw->icp_xxxx_port_num = 0;
684 break;
685 case E1000_DEV_ID_EP80579_LAN_20x5044:
686 case E1000_DEV_ID_EP80579_LAN_40x5041:
687 hw->mac_type = em_icp_xxxx;
688 hw->icp_xxxx_port_num = 1;
689 break;
690 case E1000_DEV_ID_EP80579_LAN_30x5048:
691 case E1000_DEV_ID_EP80579_LAN_50x5045:
692 hw->mac_type = em_icp_xxxx;
693 hw->icp_xxxx_port_num = 2;
694 break;
695 case E1000_DEV_ID_EP80579_LAN_60x5049:
696 hw->mac_type = em_icp_xxxx;
697 hw->icp_xxxx_port_num = 3;
698 break;
699 default:
700 /* Should never have loaded on this device */
701 return -E1000_ERR_MAC_TYPE5;
702 }
703
704 switch (hw->mac_type) {
705 case em_ich8lan:
706 case em_ich9lan:
707 case em_ich10lan:
708 case em_pchlan:
709 case em_pch2lan:
710 case em_pch_lpt:
711 case em_pch_spt:
712 case em_pch_cnp:
713 case em_pch_tgp:
714 case em_pch_adp:
715 hw->swfwhw_semaphore_present = TRUE1;
716 hw->asf_firmware_present = TRUE1;
717 break;
718 case em_80003es2lan:
719 case em_82575:
720 case em_82576:
721 case em_82580:
722 case em_i210:
723 case em_i350:
724 hw->swfw_sync_present = TRUE1;
725 /* FALLTHROUGH */
726 case em_82571:
727 case em_82572:
728 case em_82573:
729 case em_82574:
730 hw->eeprom_semaphore_present = TRUE1;
731 /* FALLTHROUGH */
732 case em_82541:
733 case em_82547:
734 case em_82541_rev_2:
735 case em_82547_rev_2:
736 hw->asf_firmware_present = TRUE1;
737 break;
738 default:
739 break;
740 }
741
742 return E1000_SUCCESS0;
743}
744
745/**
746 * em_set_sfp_media_type_82575 - derives SFP module media type.
747 * @hw: pointer to the HW structure
748 *
749 * The media type is chosen based on SFP module.
750 * compatibility flags retrieved from SFP ID EEPROM.
751 **/
752STATIC int32_t em_set_sfp_media_type_82575(struct em_hw *hw)
753{
754 struct sfp_e1000_flags eth_flags;
755 int32_t ret_val = E1000_ERR_CONFIG3;
756 uint32_t ctrl_ext = 0;
757 uint8_t transceiver_type = 0;
758 int32_t timeout = 3;
759
760 /* Turn I2C interface ON and power on sfp cage */
761 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
762 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA0x00000080;
763 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext | 0x02000000)));
764
765 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
766
767 /* Read SFP module data */
768 while (timeout) {
769 ret_val = em_read_sfp_data_byte(hw,
770 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET)(0x0000 + (0x00)),
771 &transceiver_type);
772 if (ret_val == E1000_SUCCESS0)
773 break;
774 msec_delay(100)(*delay_func)(1000*(100));
775 timeout--;
776 }
777 if (ret_val != E1000_SUCCESS0)
778 goto out;
779
780 ret_val = em_read_sfp_data_byte(hw,
781 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET)(0x0000 + (0x06)),
782 (uint8_t *)&eth_flags);
783 if (ret_val != E1000_SUCCESS0)
784 goto out;
785
786 /* Check if there is some SFP module plugged and powered */
787 if ((transceiver_type == E1000_SFF_IDENTIFIER_SFP0x03) ||
788 (transceiver_type == E1000_SFF_IDENTIFIER_SFF0x02)) {
789 if (eth_flags.e1000_base_lx || eth_flags.e1000_base_sx) {
790 hw->media_type = em_media_type_internal_serdes;
791 } else if (eth_flags.e100_base_fx || eth_flags.e100_base_lx) {
792 hw->media_type = em_media_type_internal_serdes;
793 hw->sgmii_active = TRUE1;
794 } else if (eth_flags.e1000_base_t) {
795 hw->media_type = em_media_type_copper;
796 hw->sgmii_active = TRUE1;
797 } else {
798 DEBUGOUT("PHY module has not been recognized\n");
799 ret_val = E1000_ERR_CONFIG3;
800 goto out;
801 }
802 } else {
803 ret_val = E1000_ERR_CONFIG3;
804 goto out;
805 }
806 ret_val = E1000_SUCCESS0;
807out:
808 /* Restore I2C interface setting */
809 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
810 return ret_val;
811}
812
813
814/*****************************************************************************
815 * Set media type and TBI compatibility.
816 *
817 * hw - Struct containing variables accessed by shared code
818 * **************************************************************************/
819void
820em_set_media_type(struct em_hw *hw)
821{
822 uint32_t status, ctrl_ext, mdic;
823 DEBUGFUNC("em_set_media_type");;
824
825 if (hw->mac_type != em_82543) {
826 /* tbi_compatibility is only valid on 82543 */
827 hw->tbi_compatibility_en = FALSE0;
828 }
829
830 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
831 hw->mac_type == em_82576 ||
832 hw->mac_type == em_i210 || hw->mac_type == em_i350) {
833 hw->media_type = em_media_type_copper;
834 hw->sgmii_active = FALSE0;
835
836 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
837 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) {
838 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX0x00400000:
839 hw->media_type = em_media_type_internal_serdes;
840 ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000;
841 break;
842 case E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000:
843 mdic = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04)));
844 ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000;
845 if (mdic & E1000_MDICNFG_EXT_MDIO0x80000000) {
846 hw->media_type = em_media_type_copper;
847 hw->sgmii_active = TRUE1;
848 break;
849 }
850 /* FALLTHROUGH */
851 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000:
852 ctrl_ext |= E1000_CTRL_I2C_ENA0x02000000;
853 if (em_set_sfp_media_type_82575(hw) != 0) {
854 hw->media_type = em_media_type_internal_serdes;
855 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) ==
856 E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000) {
857 hw->media_type = em_media_type_copper;
858 hw->sgmii_active = TRUE1;
859 }
860 }
861
862 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000;
863 if (hw->sgmii_active)
864 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII0x00800000;
865 else
866 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000;
867 break;
868 default:
869 ctrl_ext &= ~E1000_CTRL_I2C_ENA0x02000000;
870 break;
871 }
872 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
873 return;
874 }
875
876 switch (hw->device_id) {
877 case E1000_DEV_ID_82545GM_SERDES0x1028:
878 case E1000_DEV_ID_82546GB_SERDES0x107B:
879 case E1000_DEV_ID_82571EB_SERDES0x1060:
880 case E1000_DEV_ID_82571EB_SERDES_DUAL0x10D9:
881 case E1000_DEV_ID_82571EB_SERDES_QUAD0x10DA:
882 case E1000_DEV_ID_82572EI_SERDES0x107F:
883 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT0x1098:
884 hw->media_type = em_media_type_internal_serdes;
885 break;
886 case E1000_DEV_ID_EP80579_LAN_10x5040:
887 case E1000_DEV_ID_EP80579_LAN_20x5044:
888 case E1000_DEV_ID_EP80579_LAN_30x5048:
889 case E1000_DEV_ID_EP80579_LAN_40x5041:
890 case E1000_DEV_ID_EP80579_LAN_50x5045:
891 case E1000_DEV_ID_EP80579_LAN_60x5049:
892 hw->media_type = em_media_type_copper;
893 break;
894 default:
895 switch (hw->mac_type) {
896 case em_82542_rev2_0:
897 case em_82542_rev2_1:
898 hw->media_type = em_media_type_fiber;
899 break;
900 case em_ich8lan:
901 case em_ich9lan:
902 case em_ich10lan:
903 case em_pchlan:
904 case em_pch2lan:
905 case em_pch_lpt:
906 case em_pch_spt:
907 case em_pch_cnp:
908 case em_pch_tgp:
909 case em_pch_adp:
910 case em_82573:
911 case em_82574:
912 /*
913 * The STATUS_TBIMODE bit is reserved or reused for
914 * the this device.
915 */
916 hw->media_type = em_media_type_copper;
917 break;
918 default:
919 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
920 if (status & E1000_STATUS_TBIMODE0x00000020) {
921 hw->media_type = em_media_type_fiber;
922 /* tbi_compatibility not valid on fiber */
923 hw->tbi_compatibility_en = FALSE0;
924 } else {
925 hw->media_type = em_media_type_copper;
926 }
927 break;
928 }
929 }
930}
931/******************************************************************************
932 * Reset the transmit and receive units; mask and clear all interrupts.
933 *
934 * hw - Struct containing variables accessed by shared code
935 *****************************************************************************/
936int32_t
937em_reset_hw(struct em_hw *hw)
938{
939 uint32_t ctrl;
940 uint32_t ctrl_ext;
941 uint32_t icr;
942 uint32_t manc;
943 uint32_t led_ctrl;
944 uint32_t timeout;
945 uint32_t extcnf_ctrl;
946 int32_t ret_val;
947 DEBUGFUNC("em_reset_hw");;
948
949 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
950 if (hw->mac_type == em_82542_rev2_0) {
951 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
952 em_pci_clear_mwi(hw);
953 }
954 if (hw->bus_type == em_bus_type_pci_express) {
955 /*
956 * Prevent the PCI-E bus from sticking if there is no TLP
957 * connection on the last TLP read/write transaction when MAC
958 * is reset.
959 */
960 if (em_disable_pciex_master(hw) != E1000_SUCCESS0) {
961 DEBUGOUT("PCI-E Master disable polling has failed.\n");
962 }
963 }
964
965 /* Set the completion timeout for 82575 chips */
966 if (hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
967 hw->mac_type == em_82576 ||
968 hw->mac_type == em_i210 || hw->mac_type == em_i350) {
969 ret_val = em_set_pciex_completion_timeout(hw);
970 if (ret_val) {
971 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
972 }
973 }
974
975 /* Clear interrupt mask to stop board from generating interrupts */
976 DEBUGOUT("Masking off all interrupts\n");
977 E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register
(0x000D8))), (0xffffffff)));
978 /*
979 * Disable the Transmit and Receive units. Then delay to allow any
980 * pending transactions to complete before we hit the MAC with the
981 * global reset.
982 */
983 E1000_WRITE_REG(hw, RCTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (0)));
984 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400))), (0x00000008)));
985 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
986 /*
987 * The tbi_compatibility_on Flag must be cleared when Rctl is
988 * cleared.
989 */
990 hw->tbi_compatibility_on = FALSE0;
991 /*
992 * Delay to allow any outstanding PCI transactions to complete before
993 * resetting the device
994 */
995 msec_delay(10)(*delay_func)(1000*(10));
996
997 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
998
999 /* Must reset the PHY before resetting the MAC */
1000 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1001 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl | 0x80000000))));
1002 msec_delay(5)(*delay_func)(1000*(5));
1003 }
1004 /*
1005 * Must acquire the MDIO ownership before MAC reset. Ownership
1006 * defaults to firmware after a reset.
1007 */
1008 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1009 timeout = 10;
1010
1011 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
1012 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020;
1013
1014 do {
1015 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00))), (extcnf_ctrl)));
1016 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
1017
1018 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020)
1019 break;
1020 else
1021 extcnf_ctrl |=
1022 E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP0x00000020;
1023
1024 msec_delay(2)(*delay_func)(1000*(2));
1025 timeout--;
1026 } while (timeout);
1027 }
1028 /* Workaround for ICH8 bit corruption issue in FIFO memory */
1029 if (hw->mac_type == em_ich8lan) {
1030 /* Set Tx and Rx buffer allocation to 8k apiece. */
1031 E1000_WRITE_REG(hw, PBA, E1000_PBA_8K)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01000 : em_translate_82542_register
(0x01000))), (0x0008)));
1032 /* Set Packet Buffer Size to 16k. */
1033 E1000_WRITE_REG(hw, PBS, E1000_PBS_16K)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01008 : em_translate_82542_register
(0x01008))), (0x0010)));
1034 }
1035 /*
1036 * Issue a global reset to the MAC. This will reset the chip's
1037 * transmit, receive, DMA, and link units. It will not effect the
1038 * current PCI configuration. The global reset bit is self-
1039 * clearing, and should clear within a microsecond.
1040 */
1041 DEBUGOUT("Issuing a global reset to MAC\n");
1042
1043 switch (hw->mac_type) {
1044 case em_82544:
1045 case em_82540:
1046 case em_82545:
1047 case em_82546:
1048 case em_82541:
1049 case em_82541_rev_2:
1050 /*
1051 * These controllers can't ack the 64-bit write when issuing
1052 * the reset, so use IO-mapping as a workaround to issue the
1053 * reset
1054 */
1055 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST))em_write_reg_io((hw), 0x00000, (ctrl | 0x04000000));
1056 break;
1057 case em_82545_rev_3:
1058 case em_82546_rev_3:
1059 /* Reset is performed on a shadow of the control register */
1060 E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00004 : em_translate_82542_register
(0x00004))), ((ctrl | 0x04000000))));
1061 break;
1062 case em_ich8lan:
1063 case em_ich9lan:
1064 case em_ich10lan:
1065 case em_pchlan:
1066 case em_pch2lan:
1067 case em_pch_lpt:
1068 case em_pch_spt:
1069 case em_pch_cnp:
1070 case em_pch_tgp:
1071 case em_pch_adp:
1072 if (!hw->phy_reset_disable &&
1073 em_check_phy_reset_block(hw) == E1000_SUCCESS0) {
1074 /*
1075 * PHY HW reset requires MAC CORE reset at the same
1076 * time to make sure the interface between MAC and
1077 * the external PHY is reset.
1078 */
1079 ctrl |= E1000_CTRL_PHY_RST0x80000000;
1080 /*
1081 * Gate automatic PHY configuration by hardware on
1082 * non-managed 82579
1083 */
1084 if ((hw->mac_type == em_pch2lan) &&
1085 !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54))))) & E1000_FWSM_FW_VALID0x00008000)) {
1086 em_gate_hw_phy_config_ich8lan(hw, TRUE1);
1087 }
1088 }
1089 em_get_software_flag(hw);
1090 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl | 0x04000000))));
1091 /* HW reset releases software_flag */
1092 hw->sw_flag = 0;
1093 msec_delay(20)(*delay_func)(1000*(20));
1094
1095 /* Ungate automatic PHY configuration on non-managed 82579 */
1096 if (hw->mac_type == em_pch2lan && !hw->phy_reset_disable &&
1097 !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54))))) & E1000_FWSM_FW_VALID0x00008000)) {
1098 msec_delay(10)(*delay_func)(1000*(10));
1099 em_gate_hw_phy_config_ich8lan(hw, FALSE0);
1100 }
1101 break;
1102 default:
1103 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl | 0x04000000))));
1104 break;
1105 }
1106
1107 if (em_check_phy_reset_block(hw) == E1000_SUCCESS0) {
1108 if (hw->mac_type == em_pchlan) {
1109 ret_val = em_hv_phy_workarounds_ich8lan(hw);
1110 if (ret_val)
1111 return ret_val;
1112 }
1113 else if (hw->mac_type == em_pch2lan) {
1114 ret_val = em_lv_phy_workarounds_ich8lan(hw);
1115 if (ret_val)
1116 return ret_val;
1117 }
1118 }
1119
1120 /*
1121 * After MAC reset, force reload of EEPROM to restore power-on
1122 * settings to device. Later controllers reload the EEPROM
1123 * automatically, so just wait for reload to complete.
1124 */
1125 switch (hw->mac_type) {
1126 case em_82542_rev2_0:
1127 case em_82542_rev2_1:
1128 case em_82543:
1129 case em_82544:
1130 /* Wait for reset to complete */
1131 usec_delay(10)(*delay_func)(10);
1132 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
1133 ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000;
1134 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
1135 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
1136 /* Wait for EEPROM reload */
1137 msec_delay(2)(*delay_func)(1000*(2));
1138 break;
1139 case em_82541:
1140 case em_82541_rev_2:
1141 case em_82547:
1142 case em_82547_rev_2:
1143 /* Wait for EEPROM reload */
1144 msec_delay(20)(*delay_func)(1000*(20));
1145 break;
1146 case em_82573:
1147 case em_82574:
1148 if (em_is_onboard_nvm_eeprom(hw) == FALSE0) {
1149 usec_delay(10)(*delay_func)(10);
1150 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
1151 ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000;
1152 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
1153 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
1154 }
1155 /* FALLTHROUGH */
1156
1157 /* Auto read done will delay 5ms or poll based on mac type */
1158 ret_val = em_get_auto_rd_done(hw);
1159 if (ret_val)
1160 return ret_val;
1161 break;
1162 default:
1163 /* Wait for EEPROM reload (it happens automatically) */
1164 msec_delay(5)(*delay_func)(1000*(5));
1165 break;
1166 }
1167
1168 /* Disable HW ARPs on ASF enabled adapters */
1169 if (hw->mac_type >= em_82540 && hw->mac_type <= em_82547_rev_2 &&
1170 hw->mac_type != em_icp_xxxx) {
1171 manc = E1000_READ_REG(hw, MANC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register
(0x05820)))));
1172 manc &= ~(E1000_MANC_ARP_EN0x00002000);
1173 E1000_WRITE_REG(hw, MANC, manc)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register
(0x05820))), (manc)));
1174 }
1175 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
1176 em_phy_init_script(hw);
1177
1178 /* Configure activity LED after PHY reset */
1179 led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00)))));
1180 led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF;
1181 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000);
1182 E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctrl)));
1183 }
1184
1185 /*
1186 * For PCH, this write will make sure that any noise
1187 * will be detected as a CRC error and be dropped rather than show up
1188 * as a bad packet to the DMA engine.
1189 */
1190 if (hw->mac_type == em_pchlan)
1191 E1000_WRITE_REG(hw, CRC_OFFSET, 0x65656565)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F50 : em_translate_82542_register
(0x05F50))), (0x65656565)));
1192
1193 /* Clear interrupt mask to stop board from generating interrupts */
1194 DEBUGOUT("Masking off all interrupts\n");
1195 E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register
(0x000D8))), (0xffffffff)));
1196
1197 /* Clear any pending interrupt events. */
1198 icr = E1000_READ_REG(hw, ICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C0 : em_translate_82542_register
(0x000C0)))));
1199
1200 /* If MWI was previously enabled, reenable it. */
1201 if (hw->mac_type == em_82542_rev2_0) {
1202 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010)
1203 em_pci_set_mwi(hw);
1204 }
1205 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
1206 uint32_t kab = E1000_READ_REG(hw, KABGTXD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03004 : em_translate_82542_register
(0x03004)))));
1207 kab |= E1000_KABGTXD_BGSQLBIAS0x00050000;
1208 E1000_WRITE_REG(hw, KABGTXD, kab)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03004 : em_translate_82542_register
(0x03004))), (kab)));
1209 }
1210
1211 if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
1212 uint32_t mdicnfg;
1213 uint16_t nvm_data;
1214
1215 /* clear global device reset status bit */
1216 EM_WRITE_REG(hw, E1000_STATUS, E1000_STATUS_DEV_RST_SET)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00008), (0x00100000)));
1217
1218 em_read_eeprom(hw, EEPROM_INIT_CONTROL3_PORT_A0x0024 +
1219 NVM_82580_LAN_FUNC_OFFSET(hw->bus_func)(hw->bus_func ? (0x40 + (0x40 * hw->bus_func)) : 0), 1,
1220 &nvm_data);
1221
1222 mdicnfg = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04)));
1223 if (nvm_data & NVM_WORD24_EXT_MDIO0x0004)
1224 mdicnfg |= E1000_MDICNFG_EXT_MDIO0x80000000;
1225 if (nvm_data & NVM_WORD24_COM_MDIO0x0008)
1226 mdicnfg |= E1000_MDICNFG_COM_MDIO0x40000000;
1227 EM_WRITE_REG(hw, E1000_MDICNFG, mdicnfg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04), (mdicnfg)));
1228 }
1229
1230 if (hw->mac_type == em_i210 || hw->mac_type == em_i350)
1231 em_set_eee_i350(hw);
1232
1233 return E1000_SUCCESS0;
1234}
1235
1236/******************************************************************************
1237 *
1238 * Initialize a number of hardware-dependent bits
1239 *
1240 * hw: Struct containing variables accessed by shared code
1241 *
1242 *****************************************************************************/
1243STATIC void
1244em_initialize_hardware_bits(struct em_softc *sc)
1245{
1246 struct em_hw *hw = &sc->hw;
1247 struct em_queue *que;
1248
1249 DEBUGFUNC("em_initialize_hardware_bits");;
1250
1251 if ((hw->mac_type >= em_82571) && (!hw->initialize_hw_bits_disable)) {
1252 /* Settings common to all silicon */
1253 uint32_t reg_ctrl, reg_ctrl_ext;
1254 uint32_t reg_tarc0, reg_tarc1;
1255 uint32_t reg_tctl;
1256 uint32_t reg_txdctl;
1257 reg_tarc0 = E1000_READ_REG(hw, TARC0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03840 : em_translate_82542_register
(0x03840)))));
1258 reg_tarc0 &= ~0x78000000; /* Clear bits 30, 29, 28, and
1259 * 27 */
1260 FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
1261 reg_txdctl = E1000_READ_REG(hw, TXDCTL(que->me))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40))))))));
1262 reg_txdctl |= E1000_TXDCTL_COUNT_DESC0x00400000; /* Set bit 22 */
1263 E1000_WRITE_REG(hw, TXDCTL(que->me), reg_txdctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40)))))), (reg_txdctl)));
1264 }
1265
1266 /*
1267 * Old code always initialized queue 1,
1268 * even when unused, keep behaviour
1269 */
1270 if (sc->num_queues == 1) {
1271 reg_txdctl = E1000_READ_REG(hw, TXDCTL(1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
))))))));
1272 reg_txdctl |= E1000_TXDCTL_COUNT_DESC0x00400000;
1273 E1000_WRITE_REG(hw, TXDCTL(1), reg_txdctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
)))))), (reg_txdctl)));
1274 }
1275
1276 switch (hw->mac_type) {
1277 case em_82571:
1278 case em_82572:
1279 reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940)))));
1280 reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))));
1281
1282 /* Set the phy Tx compatible mode bits */
1283 reg_tarc1 &= ~0x60000000; /* Clear bits 30 and 29 */
1284
1285 reg_tarc0 |= 0x07800000; /* Set TARC0 bits 23-26 */
1286 reg_tarc1 |= 0x07000000; /* Set TARC1 bits 24-26 */
1287
1288 if (reg_tctl & E1000_TCTL_MULR0x10000000)
1289 /* Clear bit 28 if MULR is 1b */
1290 reg_tarc1 &= ~0x10000000;
1291 else
1292 /* Set bit 28 if MULR is 0b */
1293 reg_tarc1 |= 0x10000000;
1294
1295 E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940))), (reg_tarc1)));
1296 break;
1297 case em_82573:
1298 case em_82574:
1299 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
1300 reg_ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
1301
1302 reg_ctrl_ext &= ~0x00800000; /* Clear bit 23 */
1303 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
1304 reg_ctrl &= ~0x20000000; /* Clear bit 29 */
1305
1306 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg_ctrl_ext)));
1307 E1000_WRITE_REG(hw, CTRL, reg_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (reg_ctrl)));
1308 break;
1309 case em_80003es2lan:
1310 if ((hw->media_type == em_media_type_fiber) ||
1311 (hw->media_type == em_media_type_internal_serdes)) {
1312 /* Clear bit 20 */
1313 reg_tarc0 &= ~0x00100000;
1314 }
1315 reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))));
1316 reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940)))));
1317 if (reg_tctl & E1000_TCTL_MULR0x10000000)
1318 /* Clear bit 28 if MULR is 1b */
1319 reg_tarc1 &= ~0x10000000;
1320 else
1321 /* Set bit 28 if MULR is 0b */
1322 reg_tarc1 |= 0x10000000;
1323
1324 E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940))), (reg_tarc1)));
1325 break;
1326 case em_ich8lan:
1327 case em_ich9lan:
1328 case em_ich10lan:
1329 case em_pchlan:
1330 case em_pch2lan:
1331 case em_pch_lpt:
1332 case em_pch_spt:
1333 case em_pch_cnp:
1334 case em_pch_tgp:
1335 case em_pch_adp:
1336 if (hw->mac_type == em_ich8lan)
1337 /* Set TARC0 bits 29 and 28 */
1338 reg_tarc0 |= 0x30000000;
1339
1340 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
1341 reg_ctrl_ext |= 0x00400000; /* Set bit 22 */
1342 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
1343 if (hw->mac_type >= em_pchlan)
1344 reg_ctrl_ext |= E1000_CTRL_EXT_PHYPDEN0x00100000;
1345 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg_ctrl_ext)));
1346
1347 reg_tarc0 |= 0x0d800000; /* Set TARC0 bits 23,
1348 * 24, 26, 27 */
1349
1350 reg_tarc1 = E1000_READ_REG(hw, TARC1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940)))));
1351 reg_tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))));
1352
1353 if (reg_tctl & E1000_TCTL_MULR0x10000000)
1354 /* Clear bit 28 if MULR is 1b */
1355 reg_tarc1 &= ~0x10000000;
1356 else
1357 /* Set bit 28 if MULR is 0b */
1358 reg_tarc1 |= 0x10000000;
1359
1360 reg_tarc1 |= 0x45000000; /* Set bit 24, 26 and
1361 * 30 */
1362
1363 E1000_WRITE_REG(hw, TARC1, reg_tarc1)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03940 : em_translate_82542_register
(0x03940))), (reg_tarc1)));
1364 break;
1365 default:
1366 break;
1367 }
1368
1369 E1000_WRITE_REG(hw, TARC0, reg_tarc0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x03840 : em_translate_82542_register
(0x03840))), (reg_tarc0)));
1370 }
1371}
1372
1373/**
1374 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
1375 * @hw: pointer to the HW structure
1376 *
1377 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
1378 * used to reset the PHY to a quiescent state when necessary.
1379 **/
1380static void
1381em_toggle_lanphypc_pch_lpt(struct em_hw *hw)
1382{
1383 uint32_t mac_reg;
1384
1385 DEBUGFUNC("e1000_toggle_lanphypc_pch_lpt");;
1386
1387 /* Set Phy Config Counter to 50msec */
1388 mac_reg = E1000_READ_REG(hw, FEXTNVM3)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0003C : em_translate_82542_register
(0x0003C)))));
27
←
Assuming field 'mac_type' is < em_82543
→
28
←
'?' condition is false
→
1389 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK0x0C000000;
1390 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC0x08000000;
1391 E1000_WRITE_REG(hw, FEXTNVM3, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0003C : em_translate_82542_register
(0x0003C))), (mac_reg)));
29
←
'?' condition is false
→
1392
1393 /* Toggle LANPHYPC Value bit */
1394 mac_reg = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
30
←
'?' condition is false
→
1395 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1396 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE0x00020000;
1397 E1000_WRITE_REG(hw, CTRL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (mac_reg)));
31
←
'?' condition is false
→
1398 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
32
←
'?' condition is false
→
1399 msec_delay(1)(*delay_func)(1000*(1));
1400 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1401 E1000_WRITE_REG(hw, CTRL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (mac_reg)));
33
←
'?' condition is false
→
1402 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
34
←
'?' condition is false
→
1403
1404 if (hw->mac_type
34.1
Field 'mac_type' is < em_pch_lpt
 < em_pch_lpt) {
35
←
Taking true branch
→
1405 msec_delay(50)(*delay_func)(1000*(50));
1406 } else {
1407 uint16_t count = 20;
1408
1409 do {
1410 msec_delay(5)(*delay_func)(1000*(5));
1411 } while (!(E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))))) &
1412 E1000_CTRL_EXT_LPCD0x00000004) && count--);
1413
1414 msec_delay(30)(*delay_func)(1000*(30));
1415 }
1416}
36
←
Returning without writing to 'hw->phy_init_script', which participates in a condition later
→
1417
1418/**
1419 * em_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1420 * @hw: pointer to the HW structure
1421 * @force: boolean indicating whether or not to force disabling ULP
1422 *
1423 * Un-configure ULP mode when link is up, the system is transitioned from
1424 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1425 * system, poll for an indication from ME that ULP has been un-configured.
1426 * If not on an ME enabled system, un-configure the ULP mode by software.
1427 *
1428 * During nominal operation, this function is called when link is acquired
1429 * to disable ULP mode (force=FALSE); otherwise, for example when unloading
1430 * the driver or during Sx->S0 transitions, this is called with force=TRUE
1431 * to forcibly disable ULP.
1432 */
1433static int
1434em_disable_ulp_lpt_lp(struct em_hw *hw, bool_Bool force)
1435{
1436 int ret_val = E1000_SUCCESS0;
1437 uint32_t mac_reg;
1438 uint16_t phy_reg;
1439 int i = 0;
1440
1441 if ((hw->mac_type
14.1
Field 'mac_type' is >= em_pch_lpt
 < em_pch_lpt) ||
19
←
Taking false branch
→
1442 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_LM0x153A) ||
15
←
Assuming field 'device_id' is not equal to E1000_DEV_ID_PCH_LPT_I217_LM
→
1443 (hw->device_id == E1000_DEV_ID_PCH_LPT_I217_V0x153B) ||
16
←
Assuming field 'device_id' is not equal to E1000_DEV_ID_PCH_LPT_I217_V
→
1444 (hw->device_id == E1000_DEV_ID_PCH_I218_LM20x15A0) ||
17
←
Assuming field 'device_id' is not equal to E1000_DEV_ID_PCH_I218_LM2
→
1445 (hw->device_id == E1000_DEV_ID_PCH_I218_V20x15A1))
18
←
Assuming field 'device_id' is not equal to E1000_DEV_ID_PCH_I218_V2
→
1446 return 0;
1447
1448 if (E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54))))) & E1000_FWSM_FW_VALID0x00008000) {
20
←
'?' condition is true
→
21
←
Assuming the condition is false
→
22
←
Taking false branch
→
1449 if (force) {
1450 /* Request ME un-configure ULP mode in the PHY */
1451 mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
1452 mac_reg &= ~E1000_H2ME_ULP0x00000800;
1453 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS0x00001000;
1454 E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (mac_reg)));
1455 }
1456
1457 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1458 while (E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54))))) & E1000_FWSM_ULP_CFG_DONE0x00000400) {
1459 if (i++ == 30) {
1460 ret_val = -E1000_ERR_PHY2;
1461 goto out;
1462 }
1463
1464 msec_delay(10)(*delay_func)(1000*(10));
1465 }
1466 DEBUGOUT1("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1467
1468 if (force) {
1469 mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
1470 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS0x00001000;
1471 E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (mac_reg)));
1472 } else {
1473 /* Clear H2ME.ULP after ME ULP configuration */
1474 mac_reg = E1000_READ_REG(hw, H2ME)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
1475 mac_reg &= ~E1000_H2ME_ULP0x00000800;
1476 E1000_WRITE_REG(hw, H2ME, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (mac_reg)));
1477 }
1478
1479 goto out;
1480 }
1481
1482 ret_val = em_get_software_flag(hw);
1483 if (ret_val)
23
←
Assuming 'ret_val' is 0
→
24
←
Taking false branch
→
1484 goto out;
1485
1486 if (force
24.1
'force' is true
)
25
←
Taking true branch
→
1487 /* Toggle LANPHYPC Value bit */
1488 em_toggle_lanphypc_pch_lpt(hw);
26
←
Calling 'em_toggle_lanphypc_pch_lpt'
→
37
←
Returning from 'em_toggle_lanphypc_pch_lpt'
→
1489
1490 /* Unforce SMBus mode in PHY */
1491 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), &phy_reg);
38
←
Calling 'em_read_phy_reg'
→
67
←
Returning from 'em_read_phy_reg'
→
1492 if (ret_val
67.1
'ret_val' is 0
) {
68
←
Taking false branch
→
1493 /* The MAC might be in PCIe mode, so temporarily force to
1494 * SMBus mode in order to access the PHY.
1495 */
1496 mac_reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
1497 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS0x00000800;
1498 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (mac_reg)));
1499
1500 msec_delay(50)(*delay_func)(1000*(50));
1501
1502 ret_val = em_read_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), &phy_reg);
1503 if (ret_val)
1504 goto release;
1505 }
1506 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS0x0001;
1507 em_write_phy_reg(hw, CV_SMB_CTRL(((769) << 5) | ((23) & 0x1F)), phy_reg);
1508
1509 /* Unforce SMBus mode in MAC */
1510 mac_reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
69
←
Assuming field 'mac_type' is < em_82543
→
70
←
'?' condition is false
→
1511 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS0x00000800;
1512 E1000_WRITE_REG(hw, CTRL_EXT, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (mac_reg)));
71
←
'?' condition is false
→
1513
1514 /* When ULP mode was previously entered, K1 was disabled by the
1515 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1516 */
1517 ret_val = em_read_phy_reg(hw, HV_PM_CTRL(((770) << 5) | ((17) & 0x1F)), &phy_reg);
72
←
Calling 'em_read_phy_reg'
→
101
←
Returning from 'em_read_phy_reg'
→
1518 if (ret_val
101.1
'ret_val' is 0
)
102
←
Taking false branch
→
1519 goto release;
1520 phy_reg |= HV_PM_CTRL_K1_ENABLE0x4000;
1521 em_write_phy_reg(hw, HV_PM_CTRL(((770) << 5) | ((17) & 0x1F)), phy_reg);
1522
1523 /* Clear ULP enabled configuration */
1524 ret_val = em_read_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), &phy_reg);
103
←
Calling 'em_read_phy_reg'
→
142
←
Returning from 'em_read_phy_reg'
→
1525 if (ret_val
142.1
'ret_val' is 0
)
143
←
Taking false branch
→
1526 goto release;
1527 phy_reg &= ~(I218_ULP_CONFIG1_IND0x0004 |
1528 I218_ULP_CONFIG1_STICKY_ULP0x0010 |
1529 I218_ULP_CONFIG1_RESET_TO_SMBUS0x0100 |
1530 I218_ULP_CONFIG1_WOL_HOST0x0040 |
1531 I218_ULP_CONFIG1_INBAND_EXIT0x0020 |
1532 I218_ULP_CONFIG1_EN_ULP_LANPHYPC0x0400 |
1533 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST0x0800 |
1534 I218_ULP_CONFIG1_DISABLE_SMB_PERST0x1000);
1535 em_write_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), phy_reg);
1536
1537 /* Commit ULP changes by starting auto ULP configuration */
1538 phy_reg |= I218_ULP_CONFIG1_START0x0001;
1539 em_write_phy_reg(hw, I218_ULP_CONFIG1(((779) << 5) | ((16) & 0x1F)), phy_reg);
1540
1541 /* Clear Disable SMBus Release on PERST# in MAC */
1542 mac_reg = E1000_READ_REG(hw, FEXTNVM7)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0xe4UL : em_translate_82542_register
(0xe4UL)))));
144
←
Assuming field 'mac_type' is < em_82543
→
145
←
'?' condition is false
→
1543 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST0x00000020;
1544 E1000_WRITE_REG(hw, FEXTNVM7, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0xe4UL : em_translate_82542_register
(0xe4UL))), (mac_reg)));
146
←
'?' condition is false
→
1545
1546release:
1547 em_release_software_flag(hw);
1548 if (force
146.1
'force' is true
) {
147
←
Taking true branch
→
1549 em_phy_reset(hw);
148
←
Calling 'em_phy_reset'
→
1550 msec_delay(50)(*delay_func)(1000*(50));
1551 }
1552out:
1553 if (ret_val)
1554 DEBUGOUT1("Error in ULP disable flow: %d\n", ret_val);
1555
1556 return ret_val;
1557}
1558
1559/******************************************************************************
1560 * Performs basic configuration of the adapter.
1561 *
1562 * hw - Struct containing variables accessed by shared code
1563 *
1564 * Assumes that the controller has previously been reset and is in a
1565 * post-reset uninitialized state. Initializes the receive address registers,
1566 * multicast table, and VLAN filter table. Calls routines to setup link
1567 * configuration and flow control settings. Clears all on-chip counters. Leaves
1568 * the transmit and receive units disabled and uninitialized.
1569 *****************************************************************************/
1570int32_t
1571em_init_hw(struct em_softc *sc)
1572{
1573 struct em_hw *hw = &sc->hw;
1574 struct em_queue *que;
1575 uint32_t ctrl;
1576 uint32_t i;
1577 int32_t ret_val;
1578 uint16_t pcix_cmd_word;
1579 uint16_t pcix_stat_hi_word;
1580 uint16_t cmd_mmrbc;
1581 uint16_t stat_mmrbc;
1582 uint32_t mta_size;
1583 uint32_t reg_data;
1584 uint32_t ctrl_ext;
1585 uint32_t snoop;
1586 uint32_t fwsm;
1587 DEBUGFUNC("em_init_hw");;
1588
1589 /* force full DMA clock frequency for ICH8 */
1590 if (hw->mac_type == em_ich8lan) {
1
Assuming field 'mac_type' is not equal to em_ich8lan
→
1591 reg_data = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
1592 reg_data &= ~0x80000000;
1593 E1000_WRITE_REG(hw, STATUS, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))), (reg_data)));
1594 }
1595
1596 if (hw->mac_type == em_pchlan ||
2
←
Assuming field 'mac_type' is not equal to em_pchlan
→
9
←
Taking true branch
→
1597 hw->mac_type == em_pch2lan ||
3
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
1598 hw->mac_type == em_pch_lpt ||
4
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
1599 hw->mac_type == em_pch_spt ||
5
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
1600 hw->mac_type == em_pch_cnp ||
6
←
Assuming field 'mac_type' is not equal to em_pch_cnp
→
1601 hw->mac_type == em_pch_tgp ||
7
←
Assuming field 'mac_type' is not equal to em_pch_tgp
→
1602 hw->mac_type == em_pch_adp) {
8
←
Assuming field 'mac_type' is equal to em_pch_adp
→
1603 /*
1604 * The MAC-PHY interconnect may still be in SMBus mode
1605 * after Sx->S0. Toggle the LANPHYPC Value bit to force
1606 * the interconnect to PCIe mode, but only if there is no
1607 * firmware present otherwise firmware will have done it.
1608 */
1609 fwsm = E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))));
10
←
'?' condition is true
→
1610 if ((fwsm & E1000_FWSM_FW_VALID0x00008000) == 0) {
11
←
Assuming the condition is false
→
12
←
Taking false branch
→
1611 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
1612 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1613 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE0x00020000;
1614 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
1615 usec_delay(10)(*delay_func)(10);
1616 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE0x00010000;
1617 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
1618 msec_delay(50)(*delay_func)(1000*(50));
1619 }
1620
1621 /* Gate automatic PHY configuration on non-managed 82579 */
1622 if (hw->mac_type
12.1
Field 'mac_type' is not equal to em_pch2lan
 == em_pch2lan)
13
←
Taking false branch
→
1623 em_gate_hw_phy_config_ich8lan(hw, TRUE1);
1624
1625 em_disable_ulp_lpt_lp(hw, TRUE1);
14
←
Calling 'em_disable_ulp_lpt_lp'
→
1626 /*
1627 * Reset the PHY before any access to it. Doing so,
1628 * ensures that the PHY is in a known good state before
1629 * we read/write PHY registers. The generic reset is
1630 * sufficient here, because we haven't determined
1631 * the PHY type yet.
1632 */
1633 em_phy_reset(hw);
1634
1635 /* Ungate automatic PHY configuration on non-managed 82579 */
1636 if (hw->mac_type == em_pch2lan &&
1637 (fwsm & E1000_FWSM_FW_VALID0x00008000) == 0)
1638 em_gate_hw_phy_config_ich8lan(hw, FALSE0);
1639
1640 /* Set MDIO slow mode before any other MDIO access */
1641 ret_val = em_set_mdio_slow_mode_hv(hw);
1642 if (ret_val)
1643 return ret_val;
1644 }
1645
1646 /* Initialize Identification LED */
1647 ret_val = em_id_led_init(hw);
1648 if (ret_val) {
1649 DEBUGOUT("Error Initializing Identification LED\n");
1650 return ret_val;
1651 }
1652 /* Set the media type and TBI compatibility */
1653 em_set_media_type(hw);
1654
1655 /* Magic delay that improves problems with i219LM on HP Elitebook */
1656 msec_delay(1)(*delay_func)(1000*(1));
1657 /* Must be called after em_set_media_type because media_type is used */
1658 em_initialize_hardware_bits(sc);
1659
1660 /* Disabling VLAN filtering. */
1661 DEBUGOUT("Initializing the IEEE VLAN\n");
1662 /* VET hardcoded to standard value and VFTA removed in ICH8/ICH9 LAN */
1663 if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
1664 if (hw->mac_type < em_82545_rev_3)
1665 E1000_WRITE_REG(hw, VET, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00038 : em_translate_82542_register
(0x00038))), (0)));
1666 if (hw->mac_type == em_i350)
1667 em_clear_vfta_i350(hw);
1668 else
1669 em_clear_vfta(hw);
1670 }
1671 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1672 if (hw->mac_type == em_82542_rev2_0) {
1673 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1674 em_pci_clear_mwi(hw);
1675 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (0x00000001)));
1676 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
1677 msec_delay(5)(*delay_func)(1000*(5));
1678 }
1679 /*
1680 * Setup the receive address. This involves initializing all of the
1681 * Receive Address Registers (RARs 0 - 15).
1682 */
1683 em_init_rx_addrs(hw);
1684
1685 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI*/
1686 if (hw->mac_type == em_82542_rev2_0) {
1687 E1000_WRITE_REG(hw, RCTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (0)));
1688 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
1689 msec_delay(1)(*delay_func)(1000*(1));
1690 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE0x0010)
1691 em_pci_set_mwi(hw);
1692 }
1693 /* Zero out the Multicast HASH table */
1694 DEBUGOUT("Zeroing the MTA\n");
1695 mta_size = E1000_MC_TBL_SIZE128;
1696 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
1697 mta_size = E1000_MC_TBL_SIZE_ICH8LAN32;
1698 for (i = 0; i < mta_size; i++) {
1699 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + ((i) << 2)), (0)));
1700 /*
1701 * use write flush to prevent Memory Write Block (MWB) from
1702 * occurring when accessing our register space
1703 */
1704 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
1705 }
1706 /*
1707 * Set the PCI priority bit correctly in the CTRL register. This
1708 * determines if the adapter gives priority to receives, or if it
1709 * gives equal priority to transmits and receives. Valid only on
1710 * 82542 and 82543 silicon.
1711 */
1712 if (hw->dma_fairness && hw->mac_type <= em_82543) {
1713 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
1714 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl | 0x00000004)));
1715 }
1716 switch (hw->mac_type) {
1717 case em_82545_rev_3:
1718 case em_82546_rev_3:
1719 break;
1720 default:
1721 /*
1722 * Workaround for PCI-X problem when BIOS sets MMRBC
1723 * incorrectly.
1724 */
1725 if (hw->bus_type == em_bus_type_pcix) {
1726 em_read_pci_cfg(hw, PCIX_COMMAND_REGISTER0xE6,
1727 &pcix_cmd_word);
1728 em_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI0xEA,
1729 &pcix_stat_hi_word);
1730 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK0x000C)
1731 >> PCIX_COMMAND_MMRBC_SHIFT0x2;
1732 stat_mmrbc = (pcix_stat_hi_word &
1733 PCIX_STATUS_HI_MMRBC_MASK0x0060) >>
1734 PCIX_STATUS_HI_MMRBC_SHIFT0x5;
1735
1736 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K0x3)
1737 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K0x2;
1738 if (cmd_mmrbc > stat_mmrbc) {
1739 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK0x000C;
1740 pcix_cmd_word |= stat_mmrbc <<
1741 PCIX_COMMAND_MMRBC_SHIFT0x2;
1742 em_write_pci_cfg(hw, PCIX_COMMAND_REGISTER0xE6,
1743 &pcix_cmd_word);
1744 }
1745 }
1746 break;
1747 }
1748
1749 /* More time needed for PHY to initialize */
1750 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
1751 msec_delay(15)(*delay_func)(1000*(15));
1752
1753 /*
1754 * The 82578 Rx buffer will stall if wakeup is enabled in host and
1755 * the ME. Reading the BM_WUC register will clear the host wakeup bit.
1756 * Reset the phy after disabling host wakeup to reset the Rx buffer.
1757 */
1758 if (hw->phy_type == em_phy_82578) {
1759 em_read_phy_reg(hw, PHY_REG(BM_WUC_PAGE, 1)(((800) << 5) | ((1) & 0x1F)),
1760 (uint16_t *)&reg_data);
1761 ret_val = em_phy_reset(hw);
1762 if (ret_val)
1763 return ret_val;
1764 }
1765
1766 /* Call a subroutine to configure the link and setup flow control. */
1767 ret_val = em_setup_link(hw);
1768
1769 /* Set the transmit descriptor write-back policy */
1770 if (hw->mac_type > em_82544) {
1771 FOREACH_QUEUE(sc, que)for ((que) = (sc)->queues; (que) < ((sc)->queues + (
sc)->num_queues); (que)++) {
1772 ctrl = E1000_READ_REG(hw, TXDCTL(que->me))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40))))))));
1773 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH0x00FF0000) |
1774 E1000_TXDCTL_FULL_TX_DESC_WB0x01010000;
1775 E1000_WRITE_REG(hw, TXDCTL(que->me), ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((que->me) < 4 ?
(0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->me
) * 0x40))) : em_translate_82542_register(((que->me) < 4
? (0x03828 + ((que->me) * 0x100)) : (0x0E028 + ((que->
me) * 0x40)))))), (ctrl)));
1776 }
1777 }
1778 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1779 em_enable_tx_pkt_filtering(hw);
1780 }
1781 switch (hw->mac_type) {
1782 default:
1783 break;
1784 case em_80003es2lan:
1785 /* Enable retransmit on late collisions */
1786 reg_data = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))));
1787 reg_data |= E1000_TCTL_RTLC0x01000000;
1788 E1000_WRITE_REG(hw, TCTL, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400))), (reg_data)));
1789
1790 /* Configure Gigabit Carry Extend Padding */
1791 reg_data = E1000_READ_REG(hw, TCTL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00404 : em_translate_82542_register
(0x00404)))));
1792 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK0x000FFC00;
1793 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX0x00010000;
1794 E1000_WRITE_REG(hw, TCTL_EXT, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00404 : em_translate_82542_register
(0x00404))), (reg_data)));
1795
1796 /* Configure Transmit Inter-Packet Gap */
1797 reg_data = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410)))));
1798 reg_data &= ~E1000_TIPG_IPGT_MASK0x000003FF;
1799 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_10000x00000008;
1800 E1000_WRITE_REG(hw, TIPG, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410))), (reg_data)));
1801
1802 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F00 : em_translate_82542_register
(0x05F00)) + ((0x0001) << 2))));
1803 reg_data &= ~0x00100000;
1804 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F00 : em_translate_82542_register
(0x05F00)) + ((0x0001) << 2)), (reg_data)));
1805 /* FALLTHROUGH */
1806 case em_82571:
1807 case em_82572:
1808 case em_82575:
1809 case em_82576:
1810 case em_82580:
1811 case em_i210:
1812 case em_i350:
1813 case em_ich8lan:
1814 case em_ich9lan:
1815 case em_ich10lan:
1816 case em_pchlan:
1817 case em_pch2lan:
1818 case em_pch_lpt:
1819 case em_pch_spt:
1820 case em_pch_cnp:
1821 case em_pch_tgp:
1822 case em_pch_adp:
1823 /*
1824 * Old code always initialized queue 1,
1825 * even when unused, keep behaviour
1826 */
1827 if (sc->num_queues == 1) {
1828 ctrl = E1000_READ_REG(hw, TXDCTL(1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
))))))));
1829 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH0x00FF0000) |
1830 E1000_TXDCTL_FULL_TX_DESC_WB0x01010000;
1831 E1000_WRITE_REG(hw, TXDCTL(1), ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? ((1) < 4 ? (0x03828
+ ((1) * 0x100)) : (0x0E028 + ((1) * 0x40))) : em_translate_82542_register
(((1) < 4 ? (0x03828 + ((1) * 0x100)) : (0x0E028 + ((1) * 0x40
)))))), (ctrl)));
1832 }
1833 break;
1834 }
1835
1836 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
1837 uint32_t gcr = E1000_READ_REG(hw, GCR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00)))));
1838 gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX0x08000000;
1839 E1000_WRITE_REG(hw, GCR, gcr)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00))), (gcr)));
1840 }
1841 /*
1842 * Clear all of the statistics registers (clear on read). It is
1843 * important that we do this after we have tried to establish link
1844 * because the symbol error count will increment wildly if there is
1845 * no link.
1846 */
1847 em_clear_hw_cntrs(hw);
1848 /*
1849 * ICH8 No-snoop bits are opposite polarity. Set to snoop by default
1850 * after reset.
1851 */
1852 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
1853 if (hw->mac_type == em_ich8lan)
1854 snoop = PCI_EX_82566_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010
| 0x00000020);
1855 else
1856 snoop = (u_int32_t) ~ (PCI_EX_NO_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010
| 0x00000020));
1857
1858 em_set_pci_ex_no_snoop(hw, snoop);
1859 }
1860
1861 /* ungate DMA clock to avoid packet loss */
1862 if (hw->mac_type >= em_pch_tgp) {
1863 uint32_t fflt_dbg = E1000_READ_REG(hw, FFLT_DBG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F04 : em_translate_82542_register
(0x05F04)))));
1864 fflt_dbg |= (1 << 12);
1865 E1000_WRITE_REG(hw, FFLT_DBG, fflt_dbg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F04 : em_translate_82542_register
(0x05F04))), (fflt_dbg)));
1866 }
1867
1868 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER0x1099 ||
1869 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP30x10B5) {
1870 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
1871 /*
1872 * Relaxed ordering must be disabled to avoid a parity error
1873 * crash in a PCI slot.
1874 */
1875 ctrl_ext |= E1000_CTRL_EXT_RO_DIS0x00020000;
1876 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
1877 }
1878 return ret_val;
1879}
1880
1881/******************************************************************************
1882 * Adjust SERDES output amplitude based on EEPROM setting.
1883 *
1884 * hw - Struct containing variables accessed by shared code.
1885 *****************************************************************************/
1886static int32_t
1887em_adjust_serdes_amplitude(struct em_hw *hw)
1888{
1889 uint16_t eeprom_data;
1890 int32_t ret_val;
1891 DEBUGFUNC("em_adjust_serdes_amplitude");;
1892
1893 if (hw->media_type != em_media_type_internal_serdes ||
1894 hw->mac_type >= em_82575)
1895 return E1000_SUCCESS0;
1896
1897 switch (hw->mac_type) {
1898 case em_82545_rev_3:
1899 case em_82546_rev_3:
1900 break;
1901 default:
1902 return E1000_SUCCESS0;
1903 }
1904
1905 ret_val = em_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE0x0006, 1, &eeprom_data);
1906 if (ret_val) {
1907 return ret_val;
1908 }
1909 if (eeprom_data != EEPROM_RESERVED_WORD0xFFFF) {
1910 /* Adjust SERDES output amplitude only. */
1911 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK0x000F;
1912 ret_val = em_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL0x1A,
1913 eeprom_data);
1914 if (ret_val)
1915 return ret_val;
1916 }
1917 return E1000_SUCCESS0;
1918}
1919
1920/******************************************************************************
1921 * Configures flow control and link settings.
1922 *
1923 * hw - Struct containing variables accessed by shared code
1924 *
1925 * Determines which flow control settings to use. Calls the appropriate media-
1926 * specific link configuration function. Configures the flow control settings.
1927 * Assuming the adapter has a valid link partner, a valid link should be
1928 * established. Assumes the hardware has previously been reset and the
1929 * transmitter and receiver are not enabled.
1930 *****************************************************************************/
1931int32_t
1932em_setup_link(struct em_hw *hw)
1933{
1934 uint32_t ctrl_ext;
1935 int32_t ret_val;
1936 uint16_t eeprom_data;
1937 uint16_t eeprom_control2_reg_offset;
1938 DEBUGFUNC("em_setup_link");;
1939
1940 eeprom_control2_reg_offset =
1941 (hw->mac_type != em_icp_xxxx)
1942 ? EEPROM_INIT_CONTROL2_REG0x000F
1943 : EEPROM_INIT_CONTROL3_ICP_xxxx(hw->icp_xxxx_port_num)((((hw->icp_xxxx_port_num) + 1) << 4) + 1);
1944 /*
1945 * In the case of the phy reset being blocked, we already have a
1946 * link. We do not have to set it up again.
1947 */
1948 if (em_check_phy_reset_block(hw))
1949 return E1000_SUCCESS0;
1950 /*
1951 * Read and store word 0x0F of the EEPROM. This word contains bits
1952 * that determine the hardware's default PAUSE (flow control) mode, a
1953 * bit that determines whether the HW defaults to enabling or
1954 * disabling auto-negotiation, and the direction of the SW defined
1955 * pins. If there is no SW over-ride of the flow control setting,
1956 * then the variable hw->fc will be initialized based on a value in
1957 * the EEPROM.
1958 */
1959 if (hw->fc == E1000_FC_DEFAULT0xFF) {
1960 switch (hw->mac_type) {
1961 case em_ich8lan:
1962 case em_ich9lan:
1963 case em_ich10lan:
1964 case em_pchlan:
1965 case em_pch2lan:
1966 case em_pch_lpt:
1967 case em_pch_spt:
1968 case em_pch_cnp:
1969 case em_pch_tgp:
1970 case em_pch_adp:
1971 case em_82573:
1972 case em_82574:
1973 hw->fc = E1000_FC_FULL3;
1974 break;
1975 default:
1976 ret_val = em_read_eeprom(hw,
1977 eeprom_control2_reg_offset, 1, &eeprom_data);
1978 if (ret_val) {
1979 DEBUGOUT("EEPROM Read Error\n");
1980 return -E1000_ERR_EEPROM1;
1981 }
1982 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK0x3000) == 0)
1983 hw->fc = E1000_FC_NONE0;
1984 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK0x3000) ==
1985 EEPROM_WORD0F_ASM_DIR0x2000)
1986 hw->fc = E1000_FC_TX_PAUSE2;
1987 else
1988 hw->fc = E1000_FC_FULL3;
1989 break;
1990 }
1991 }
1992 /*
1993 * We want to save off the original Flow Control configuration just
1994 * in case we get disconnected and then reconnected into a different
1995 * hub or switch with different Flow Control capabilities.
1996 */
1997 if (hw->mac_type == em_82542_rev2_0)
1998 hw->fc &= (~E1000_FC_TX_PAUSE2);
1999
2000 if ((hw->mac_type < em_82543) && (hw->report_tx_early == 1))
2001 hw->fc &= (~E1000_FC_RX_PAUSE1);
2002
2003 hw->original_fc = hw->fc;
2004
2005 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
2006 /*
2007 * Take the 4 bits from EEPROM word 0x0F that determine the initial
2008 * polarity value for the SW controlled pins, and setup the Extended
2009 * Device Control reg with that info. This is needed because one of
2010 * the SW controlled pins is used for signal detection. So this
2011 * should be done before em_setup_pcs_link() or em_phy_setup() is
2012 * called.
2013 */
2014 if (hw->mac_type == em_82543) {
2015 ret_val = em_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG0x000F,
2016 1, &eeprom_data);
2017 if (ret_val) {
2018 DEBUGOUT("EEPROM Read Error\n");
2019 return -E1000_ERR_EEPROM1;
2020 }
2021 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT0x00F0) <<
2022 SWDPIO__EXT_SHIFT4);
2023 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
2024 }
2025 /* Make sure we have a valid PHY */
2026 ret_val = em_detect_gig_phy(hw);
2027 if (ret_val) {
2028 DEBUGOUT("Error, did not detect valid phy.\n");
2029 if (hw->mac_type == em_icp_xxxx)
2030 return E1000_DEFER_INIT15;
2031 else
2032 return ret_val;
2033 }
2034 DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
2035
2036 /* Call the necessary subroutine to configure the link. */
2037 switch (hw->media_type) {
2038 case em_media_type_copper:
2039 case em_media_type_oem:
2040 ret_val = em_setup_copper_link(hw);
2041 break;
2042 default:
2043 ret_val = em_setup_fiber_serdes_link(hw);
2044 break;
2045 }
2046 /*
2047 * Initialize the flow control address, type, and PAUSE timer
2048 * registers to their default values. This is done even if flow
2049 * control is disabled, because it does not hurt anything to
2050 * initialize these registers.
2051 */
2052 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"
2053 );
2054
2055 /*
2056 * FCAL/H and FCT are hardcoded to standard values in
2057 * em_ich8lan / em_ich9lan / em_ich10lan.
2058 */
2059 if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
2060 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00030 : em_translate_82542_register
(0x00030))), (0x8808)));
2061 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0002C : em_translate_82542_register
(0x0002C))), (0x00000100)));
2062 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00028 : em_translate_82542_register
(0x00028))), (0x00C28001)));
2063 }
2064 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00170 : em_translate_82542_register
(0x00170))), (hw->fc_pause_time)));
2065
2066 if (hw->phy_type == em_phy_82577 ||
2067 hw->phy_type == em_phy_82578 ||
2068 hw->phy_type == em_phy_82579 ||
2069 hw->phy_type == em_phy_i217) {
2070 E1000_WRITE_REG(hw, FCRTV_PCH, 0x1000)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F40 : em_translate_82542_register
(0x05F40))), (0x1000)));
2071 em_write_phy_reg(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27)(((769) << 5) | ((27) & 0x1F)),
2072 hw->fc_pause_time);
2073 }
2074
2075 /*
2076 * Set the flow control receive threshold registers. Normally, these
2077 * registers will be set to a default threshold that may be adjusted
2078 * later by the driver's runtime code. However, if the ability to
2079 * transmit pause frames in not enabled, then these registers will be
2080 * set to 0.
2081 */
2082 if (!(hw->fc & E1000_FC_TX_PAUSE2)) {
2083 E1000_WRITE_REG(hw, FCRTL, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), (0)));
2084 E1000_WRITE_REG(hw, FCRTH, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register
(0x02168))), (0)));
2085 } else {
2086 /*
2087 * We need to set up the Receive Threshold high and low water
2088 * marks as well as (optionally) enabling the transmission of
2089 * XON frames.
2090 */
2091 if (hw->fc_send_xon) {
2092 E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), ((hw->fc_low_water | 0x80000000))))
2093 | E1000_FCRTL_XONE))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), ((hw->fc_low_water | 0x80000000))));
2094 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register
(0x02168))), (hw->fc_high_water)));
2095 } else {
2096 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02160 : em_translate_82542_register
(0x02160))), (hw->fc_low_water)));
2097 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x02168 : em_translate_82542_register
(0x02168))), (hw->fc_high_water)));
2098 }
2099 }
2100 return ret_val;
2101}
2102
2103void
2104em_power_up_serdes_link_82575(struct em_hw *hw)
2105{
2106 uint32_t reg;
2107
2108 if (hw->media_type != em_media_type_internal_serdes &&
2109 hw->sgmii_active == FALSE0)
2110 return;
2111
2112 /* Enable PCS to turn on link */
2113 reg = E1000_READ_REG(hw, PCS_CFG0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04200 : em_translate_82542_register
(0x04200)))));
2114 reg |= E1000_PCS_CFG_PCS_EN8;
2115 E1000_WRITE_REG(hw, PCS_CFG0, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04200 : em_translate_82542_register
(0x04200))), (reg)));
2116
2117 /* Power up the laser */
2118 reg = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
2119 reg &= ~E1000_CTRL_EXT_SDP3_DATA0x00000080;
2120 E1000_WRITE_REG(hw, CTRL_EXT, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg)));
2121
2122 /* flush the write to verify completion */
2123 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
2124 delay(5)(*delay_func)(5);
2125}
2126
2127/******************************************************************************
2128 * Sets up link for a fiber based or serdes based adapter
2129 *
2130 * hw - Struct containing variables accessed by shared code
2131 *
2132 * Manipulates Physical Coding Sublayer functions in order to configure
2133 * link. Assumes the hardware has been previously reset and the transmitter
2134 * and receiver are not enabled.
2135 *****************************************************************************/
2136static int32_t
2137em_setup_fiber_serdes_link(struct em_hw *hw)
2138{
2139 uint32_t ctrl, ctrl_ext, reg;
2140 uint32_t status;
2141 uint32_t txcw = 0;
2142 uint32_t i;
2143 uint32_t signal = 0;
2144 int32_t ret_val;
2145 DEBUGFUNC("em_setup_fiber_serdes_link");;
2146
2147 if (hw->media_type != em_media_type_internal_serdes &&
2148 hw->sgmii_active == FALSE0)
2149 return -E1000_ERR_CONFIG3;
2150
2151 /*
2152 * On 82571 and 82572 Fiber connections, SerDes loopback mode
2153 * persists until explicitly turned off or a power cycle is
2154 * performed. A read to the register does not indicate its status.
2155 * Therefore, we ensure loopback mode is disabled during
2156 * initialization.
2157 */
2158 if (hw->mac_type == em_82571 || hw->mac_type == em_82572 ||
2159 hw->mac_type >= em_82575)
2160 E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00024 : em_translate_82542_register
(0x00024))), (0x0400)));
2161
2162 if (hw->mac_type >= em_82575)
2163 em_power_up_serdes_link_82575(hw);
2164
2165 /*
2166 * On adapters with a MAC newer than 82544, SWDP 1 will be set when
2167 * the optics detect a signal. On older adapters, it will be cleared
2168 * when there is a signal. This applies to fiber media only. If
2169 * we're on serdes media, adjust the output amplitude to value set in
2170 * the EEPROM.
2171 */
2172 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
2173 if (hw->media_type == em_media_type_fiber)
2174 signal = (hw->mac_type > em_82544) ? E1000_CTRL_SWDPIN10x00080000 : 0;
2175
2176 ret_val = em_adjust_serdes_amplitude(hw);
2177 if (ret_val)
2178 return ret_val;
2179
2180 /* Take the link out of reset */
2181 ctrl &= ~(E1000_CTRL_LRST0x00000008);
2182
2183 if (hw->mac_type >= em_82575) {
2184 /* set both sw defined pins on 82575/82576*/
2185 ctrl |= E1000_CTRL_SWDPIN00x00040000 | E1000_CTRL_SWDPIN10x00080000;
2186
2187 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
2188 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000) {
2189 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX0x00400000:
2190 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES0x00C00000:
2191 /* the backplane is always connected */
2192 reg = E1000_READ_REG(hw, PCS_LCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04208 : em_translate_82542_register
(0x04208)))));
2193 reg |= E1000_PCS_LCTL_FORCE_FCTRL0x80;
2194 reg |= E1000_PCS_LCTL_FSV_10004 | E1000_PCS_LCTL_FDV_FULL8;
2195 reg |= E1000_PCS_LCTL_FSD0x10; /* Force Speed */
2196 DEBUGOUT("Configuring Forced Link\n");
2197 E1000_WRITE_REG(hw, PCS_LCTL, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04208 : em_translate_82542_register
(0x04208))), (reg)));
2198 em_force_mac_fc(hw);
2199 hw->autoneg_failed = 0;
2200 return E1000_SUCCESS0;
2201 break;
2202 default:
2203 /* Set switch control to serdes energy detect */
2204 reg = E1000_READ_REG(hw, CONNSW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034)))));
2205 reg |= E1000_CONNSW_ENRGSRC0x4;
2206 E1000_WRITE_REG(hw, CONNSW, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034))), (reg)));
2207 break;
2208 }
2209 }
2210
2211 /* Adjust VCO speed to improve BER performance */
2212 ret_val = em_set_vco_speed(hw);
2213 if (ret_val)
2214 return ret_val;
2215
2216 em_config_collision_dist(hw);
2217 /*
2218 * Check for a software override of the flow control settings, and
2219 * setup the device accordingly. If auto-negotiation is enabled,
2220 * then software will have to set the "PAUSE" bits to the correct
2221 * value in the Tranmsit Config Word Register (TXCW) and re-start
2222 * auto-negotiation. However, if auto-negotiation is disabled, then
2223 * software will have to manually configure the two flow control
2224 * enable bits in the CTRL register.
2225 *
2226 * The possible values of the "fc" parameter are: 0: Flow control is
2227 * completely disabled 1: Rx flow control is enabled (we can receive
2228 * pause frames, but not send pause frames). 2: Tx flow control is
2229 * enabled (we can send pause frames but we do not support receiving
2230 * pause frames). 3: Both Rx and TX flow control (symmetric) are
2231 * enabled.
2232 */
2233 switch (hw->fc) {
2234 case E1000_FC_NONE0:
2235 /*
2236 * Flow control is completely disabled by a software
2237 * over-ride.
2238 */
2239 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020);
2240 break;
2241 case E1000_FC_RX_PAUSE1:
2242 /*
2243 * RX Flow control is enabled and TX Flow control is disabled
2244 * by a software over-ride. Since there really isn't a way to
2245 * advertise that we are capable of RX Pause ONLY, we will
2246 * advertise that we support both symmetric and asymmetric RX
2247 * PAUSE. Later, we will disable the adapter's ability to
2248 * send PAUSE frames.
2249 */
2250 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 |
2251 E1000_TXCW_PAUSE_MASK0x00000180);
2252 break;
2253 case E1000_FC_TX_PAUSE2:
2254 /*
2255 * TX Flow control is enabled, and RX Flow control is
2256 * disabled, by a software over-ride.
2257 */
2258 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 | E1000_TXCW_ASM_DIR0x00000100);
2259 break;
2260 case E1000_FC_FULL3:
2261 /*
2262 * Flow control (both RX and TX) is enabled by a software
2263 * over-ride.
2264 */
2265 txcw = (E1000_TXCW_ANE0x80000000 | E1000_TXCW_FD0x00000020 |
2266 E1000_TXCW_PAUSE_MASK0x00000180);
2267 break;
2268 default:
2269 DEBUGOUT("Flow control param set incorrectly\n");
2270 return -E1000_ERR_CONFIG3;
2271 break;
2272 }
2273 /*
2274 * Since auto-negotiation is enabled, take the link out of reset (the
2275 * link will be in reset, because we previously reset the chip). This
2276 * will restart auto-negotiation. If auto-negotiation is successful
2277 * then the link-up status bit will be set and the flow control
2278 * enable bits (RFCE and TFCE) will be set according to their
2279 * negotiated value.
2280 */
2281 DEBUGOUT("Auto-negotiation enabled\n");
2282
2283 E1000_WRITE_REG(hw, TXCW, txcw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))), (txcw)));
2284 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
2285 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
2286
2287 hw->txcw = txcw;
2288 msec_delay(1)(*delay_func)(1000*(1));
2289 /*
2290 * If we have a signal (the cable is plugged in) then poll for a
2291 * "Link-Up" indication in the Device Status Register. Time-out if a
2292 * link isn't seen in 500 milliseconds seconds (Auto-negotiation
2293 * should complete in less than 500 milliseconds even if the other
2294 * end is doing it in SW). For internal serdes, we just assume a
2295 * signal is present, then poll.
2296 */
2297 if (hw->media_type == em_media_type_internal_serdes ||
2298 (E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))))) & E1000_CTRL_SWDPIN10x00080000) == signal) {
2299 DEBUGOUT("Looking for Link\n");
2300 for (i = 0; i < (LINK_UP_TIMEOUT500 / 10); i++) {
2301 msec_delay(10)(*delay_func)(1000*(10));
2302 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
2303 if (status & E1000_STATUS_LU0x00000002)
2304 break;
2305 }
2306 if (i == (LINK_UP_TIMEOUT500 / 10)) {
2307 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2308 hw->autoneg_failed = 1;
2309 /*
2310 * AutoNeg failed to achieve a link, so we'll call
2311 * em_check_for_link. This routine will force the
2312 * link up if we detect a signal. This will allow us
2313 * to communicate with non-autonegotiating link
2314 * partners.
2315 */
2316 ret_val = em_check_for_link(hw);
2317 if (ret_val) {
2318 DEBUGOUT("Error while checking for link\n");
2319 return ret_val;
2320 }
2321 hw->autoneg_failed = 0;
2322 } else {
2323 hw->autoneg_failed = 0;
2324 DEBUGOUT("Valid Link Found\n");
2325 }
2326 } else {
2327 DEBUGOUT("No Signal Detected\n");
2328 }
2329 return E1000_SUCCESS0;
2330}
2331
2332/******************************************************************************
2333 * Make sure we have a valid PHY and change PHY mode before link setup.
2334 *
2335 * hw - Struct containing variables accessed by shared code
2336 *****************************************************************************/
2337static int32_t
2338em_copper_link_preconfig(struct em_hw *hw)
2339{
2340 uint32_t ctrl;
2341 int32_t ret_val;
2342 uint16_t phy_data;
2343 DEBUGFUNC("em_copper_link_preconfig");;
2344
2345 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
2346 /*
2347 * With 82543, we need to force speed and duplex on the MAC equal to
2348 * what the PHY speed and duplex configuration is. In addition, we
2349 * need to perform a hardware reset on the PHY to take it out of
2350 * reset.
2351 */
2352 if (hw->mac_type > em_82543) {
2353 ctrl |= E1000_CTRL_SLU0x00000040;
2354 ctrl &= ~(E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000);
2355 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
2356 } else {
2357 ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000 |
2358 E1000_CTRL_SLU0x00000040);
2359 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
2360 ret_val = em_phy_hw_reset(hw);
2361 if (ret_val)
2362 return ret_val;
2363 }
2364
2365 /* Set PHY to class A mode (if necessary) */
2366 ret_val = em_set_phy_mode(hw);
2367 if (ret_val)
2368 return ret_val;
2369
2370 if ((hw->mac_type == em_82545_rev_3) ||
2371 (hw->mac_type == em_82546_rev_3)) {
2372 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2373 &phy_data);
2374 phy_data |= 0x00000008;
2375 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2376 phy_data);
2377 }
2378 if (hw->mac_type <= em_82543 ||
2379 hw->mac_type == em_82541 || hw->mac_type == em_82547 ||
2380 hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2)
2381 hw->phy_reset_disable = FALSE0;
2382 if ((hw->mac_type == em_82575 || hw->mac_type == em_82580 ||
2383 hw->mac_type == em_82576 ||
2384 hw->mac_type == em_i210 || hw->mac_type == em_i350) &&
2385 hw->sgmii_active) {
2386 /* allow time for SFP cage time to power up phy */
2387 msec_delay(300)(*delay_func)(1000*(300));
2388
2389 /*
2390 * SFP documentation requires the following to configure the SFP module
2391 * to work on SGMII. No further documentation is given.
2392 */
2393 em_write_phy_reg(hw, 0x1B, 0x8084);
2394 em_phy_hw_reset(hw);
2395 }
2396
2397 return E1000_SUCCESS0;
2398}
2399
2400/******************************************************************************
2401 * Copper link setup for em_phy_igp series.
2402 *
2403 * hw - Struct containing variables accessed by shared code
2404 *****************************************************************************/
2405static int32_t
2406em_copper_link_igp_setup(struct em_hw *hw)
2407{
2408 uint32_t led_ctrl;
2409 int32_t ret_val;
2410 uint16_t phy_data;
2411 DEBUGFUNC("em_copper_link_igp_setup");;
2412
2413 if (hw->phy_reset_disable)
2414 return E1000_SUCCESS0;
2415
2416 ret_val = em_phy_reset(hw);
2417 if (ret_val) {
2418 DEBUGOUT("Error Resetting the PHY\n");
2419 return ret_val;
2420 }
2421 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2422 msec_delay(15)(*delay_func)(1000*(15));
2423 if (hw->mac_type != em_ich8lan &&
2424 hw->mac_type != em_ich9lan &&
2425 hw->mac_type != em_ich10lan) {
2426 /* Configure activity LED after PHY reset */
2427 led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00)))));
2428 led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF;
2429 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000);
2430 E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctrl)));
2431 }
2432 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2433 if (hw->phy_type == em_phy_igp) {
2434 /* disable lplu d3 during driver init */
2435 ret_val = em_set_d3_lplu_state(hw, FALSE0);
2436 if (ret_val) {
2437 DEBUGOUT("Error Disabling LPLU D3\n");
2438 return ret_val;
2439 }
2440 }
2441 /* disable lplu d0 during driver init */
2442 if (hw->mac_type == em_pchlan ||
2443 hw->mac_type == em_pch2lan ||
2444 hw->mac_type == em_pch_lpt ||
2445 hw->mac_type == em_pch_spt ||
2446 hw->mac_type == em_pch_cnp ||
2447 hw->mac_type == em_pch_tgp ||
2448 hw->mac_type == em_pch_adp)
2449 ret_val = em_set_lplu_state_pchlan(hw, FALSE0);
2450 else
2451 ret_val = em_set_d0_lplu_state(hw, FALSE0);
2452 if (ret_val) {
2453 DEBUGOUT("Error Disabling LPLU D0\n");
2454 return ret_val;
2455 }
2456 /* Configure mdi-mdix settings */
2457 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, &phy_data);
2458 if (ret_val)
2459 return ret_val;
2460
2461 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
2462 hw->dsp_config_state = em_dsp_config_disabled;
2463 /* Force MDI for earlier revs of the IGP PHY */
2464 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX0x1000 |
2465 IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000);
2466 hw->mdix = 1;
2467
2468 } else {
2469 hw->dsp_config_state = em_dsp_config_enabled;
2470 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX0x1000;
2471
2472 switch (hw->mdix) {
2473 case 1:
2474 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000;
2475 break;
2476 case 2:
2477 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000;
2478 break;
2479 case 0:
2480 default:
2481 phy_data |= IGP01E1000_PSCR_AUTO_MDIX0x1000;
2482 break;
2483 }
2484 }
2485 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12, phy_data);
2486 if (ret_val)
2487 return ret_val;
2488
2489 /* set auto-master slave resolution settings */
2490 if (hw->autoneg) {
2491 em_ms_type phy_ms_setting = hw->master_slave;
2492 if (hw->ffe_config_state == em_ffe_config_active)
2493 hw->ffe_config_state = em_ffe_config_enabled;
2494
2495 if (hw->dsp_config_state == em_dsp_config_activated)
2496 hw->dsp_config_state = em_dsp_config_enabled;
2497 /*
2498 * when autonegotiation advertisement is only 1000Mbps then
2499 * we should disable SmartSpeed and enable Auto MasterSlave
2500 * resolution as hardware default.
2501 */
2502 if (hw->autoneg_advertised == ADVERTISE_1000_FULL0x0020) {
2503 /* Disable SmartSpeed */
2504 ret_val = em_read_phy_reg(hw,
2505 IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data);
2506 if (ret_val)
2507 return ret_val;
2508
2509 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080;
2510 ret_val = em_write_phy_reg(hw,
2511 IGP01E1000_PHY_PORT_CONFIG0x10, phy_data);
2512 if (ret_val)
2513 return ret_val;
2514 /* Set auto Master/Slave resolution process */
2515 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09,
2516 &phy_data);
2517 if (ret_val)
2518 return ret_val;
2519
2520 phy_data &= ~CR_1000T_MS_ENABLE0x1000;
2521 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09,
2522 phy_data);
2523 if (ret_val)
2524 return ret_val;
2525 }
2526 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09, &phy_data);
2527 if (ret_val)
2528 return ret_val;
2529
2530 /* load defaults for future use */
2531 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE0x1000) ?
2532 ((phy_data & CR_1000T_MS_VALUE0x0800) ? em_ms_force_master :
2533 em_ms_force_slave) : em_ms_auto;
2534
2535 switch (phy_ms_setting) {
2536 case em_ms_force_master:
2537 phy_data |= (CR_1000T_MS_ENABLE0x1000 | CR_1000T_MS_VALUE0x0800);
2538 break;
2539 case em_ms_force_slave:
2540 phy_data |= CR_1000T_MS_ENABLE0x1000;
2541 phy_data &= ~(CR_1000T_MS_VALUE0x0800);
2542 break;
2543 case em_ms_auto:
2544 phy_data &= ~CR_1000T_MS_ENABLE0x1000;
2545 break;
2546 default:
2547 break;
2548 }
2549 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09, phy_data);
2550 if (ret_val)
2551 return ret_val;
2552 }
2553 return E1000_SUCCESS0;
2554}
2555
2556/******************************************************************************
2557 * Copper link setup for em_phy_gg82563 series.
2558 *
2559 * hw - Struct containing variables accessed by shared code
2560 *****************************************************************************/
2561static int32_t
2562em_copper_link_ggp_setup(struct em_hw *hw)
2563{
2564 int32_t ret_val;
2565 uint16_t phy_data;
2566 uint32_t reg_data;
2567 DEBUGFUNC("em_copper_link_ggp_setup");;
2568
2569 if (!hw->phy_reset_disable) {
2570
2571 /* Enable CRS on TX for half-duplex operation. */
2572 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
2573 &phy_data);
2574 if (ret_val)
2575 return ret_val;
2576
2577 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX0x0010;
2578 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2579 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ0x0007;
2580
2581 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
2582 phy_data);
2583 if (ret_val)
2584 return ret_val;
2585 /*
2586 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1
2587 * - MDI mode 2 - MDI-X mode 3 - Auto for 1000Base-T only
2588 * (MDI-X for 10/100Base-T modes)
2589 */
2590 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL(((0) << 5) | ((16) & 0x1F)),
2591 &phy_data);
2592
2593 if (ret_val)
2594 return ret_val;
2595
2596 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK0x0060;
2597
2598 switch (hw->mdix) {
2599 case 1:
2600 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI0x0000;
2601 break;
2602 case 2:
2603 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX0x0020;
2604 break;
2605 case 0:
2606 default:
2607 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO0x0060;
2608 break;
2609 }
2610 /*
2611 * Options: disable_polarity_correction = 0 (default)
2612 * Automatic Correction for Reversed Cable Polarity 0 -
2613 * Disabled 1 - Enabled
2614 */
2615 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE0x0002;
2616 if (hw->disable_polarity_correction == 1)
2617 phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE0x0002;
2618 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL(((0) << 5) | ((16) & 0x1F)),
2619 phy_data);
2620
2621 if (ret_val)
2622 return ret_val;
2623
2624 /* SW Reset the PHY so all changes take effect */
2625 ret_val = em_phy_reset(hw);
2626 if (ret_val) {
2627 DEBUGOUT("Error Resetting the PHY\n");
2628 return ret_val;
2629 }
2630 } /* phy_reset_disable */
2631 if (hw->mac_type == em_80003es2lan) {
2632 /* Bypass RX and TX FIFO's */
2633 ret_val = em_write_kmrn_reg(hw,
2634 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL0x00000000,
2635 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS0x00000008 |
2636 E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS0x00000800);
2637 if (ret_val)
2638 return ret_val;
2639
2640 ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2(((0) << 5) | ((26) & 0x1F)),
2641 &phy_data);
2642 if (ret_val)
2643 return ret_val;
2644
2645 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG0x2000;
2646 ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2(((0) << 5) | ((26) & 0x1F)),
2647 phy_data);
2648
2649 if (ret_val)
2650 return ret_val;
2651
2652 reg_data = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
2653 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK0x00C00000);
2654 E1000_WRITE_REG(hw, CTRL_EXT, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (reg_data)));
2655
2656 ret_val = em_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL(((193) << 5) | ((20) & 0x1F)),
2657 &phy_data);
2658 if (ret_val)
2659 return ret_val;
2660 /*
2661 * Do not init these registers when the HW is in IAMT mode,
2662 * since the firmware will have already initialized them. We
2663 * only initialize them if the HW is not in IAMT mode.
2664 */
2665 if (em_check_mng_mode(hw) == FALSE0) {
2666 /* Enable Electrical Idle on the PHY */
2667 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE0x0001;
2668 ret_val = em_write_phy_reg(hw,
2669 GG82563_PHY_PWR_MGMT_CTRL(((193) << 5) | ((20) & 0x1F)), phy_data);
2670 if (ret_val)
2671 return ret_val;
2672
2673 ret_val = em_read_phy_reg(hw,
2674 GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &phy_data);
2675 if (ret_val)
2676 return ret_val;
2677
2678 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
2679 ret_val = em_write_phy_reg(hw,
2680 GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), phy_data);
2681
2682 if (ret_val)
2683 return ret_val;
2684 }
2685 /*
2686 * Workaround: Disable padding in Kumeran interface in the
2687 * MAC and in the PHY to avoid CRC errors.
2688 */
2689 ret_val = em_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL(((194) << 5) | ((18) & 0x1F)),
2690 &phy_data);
2691 if (ret_val)
2692 return ret_val;
2693 phy_data |= GG82563_ICR_DIS_PADDING0x0010;
2694 ret_val = em_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL(((194) << 5) | ((18) & 0x1F)),
2695 phy_data);
2696 if (ret_val)
2697 return ret_val;
2698 }
2699 return E1000_SUCCESS0;
2700}
2701
2702/******************************************************************************
2703 * Copper link setup for em_phy_m88 series.
2704 *
2705 * hw - Struct containing variables accessed by shared code
2706 *****************************************************************************/
2707static int32_t
2708em_copper_link_mgp_setup(struct em_hw *hw)
2709{
2710 int32_t ret_val;
2711 uint16_t phy_data;
2712 DEBUGFUNC("em_copper_link_mgp_setup");;
2713
2714 if (hw->phy_reset_disable)
2715 return E1000_SUCCESS0;
2716
2717 /* disable lplu d0 during driver init */
2718 if (hw->mac_type == em_pchlan ||
2719 hw->mac_type == em_pch2lan ||
2720 hw->mac_type == em_pch_lpt ||
2721 hw->mac_type == em_pch_spt ||
2722 hw->mac_type == em_pch_cnp ||
2723 hw->mac_type == em_pch_tgp ||
2724 hw->mac_type == em_pch_adp)
2725 ret_val = em_set_lplu_state_pchlan(hw, FALSE0);
2726
2727 /* Enable CRS on TX. This must be set for half-duplex operation. */
2728 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, &phy_data);
2729 if (ret_val)
2730 return ret_val;
2731
2732 if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0) {
2733 phy_data |= 0x00000008;
2734 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2735 phy_data);
2736 if (ret_val)
2737 return ret_val;
2738
2739 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
2740 &phy_data);
2741 if (ret_val)
2742 return ret_val;
2743
2744 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
2745
2746 }
2747 /* For BM PHY this bit is downshift enable */
2748 else if (hw->phy_type != em_phy_bm)
2749 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
2750 /*
2751 * Options: MDI/MDI-X = 0 (default) 0 - Auto for all speeds 1 - MDI
2752 * mode 2 - MDI-X mode 3 - Auto for 1000Base-T only (MDI-X for
2753 * 10/100Base-T modes)
2754 */
2755 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE0x0060;
2756
2757 switch (hw->mdix) {
2758 case 1:
2759 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE0x0000;
2760 break;
2761 case 2:
2762 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE0x0020;
2763 break;
2764 case 3:
2765 phy_data |= M88E1000_PSCR_AUTO_X_1000T0x0040;
2766 break;
2767 case 0:
2768 default:
2769 phy_data |= M88E1000_PSCR_AUTO_X_MODE0x0060;
2770 break;
2771 }
2772 /*
2773 * Options: disable_polarity_correction = 0 (default) Automatic
2774 * Correction for Reversed Cable Polarity 0 - Disabled 1 - Enabled
2775 */
2776 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL0x0002;
2777 if (hw->disable_polarity_correction == 1)
2778 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL0x0002;
2779
2780 /* Enable downshift on BM (disabled by default) */
2781 if (hw->phy_type == em_phy_bm)
2782 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT0x0800;
2783
2784 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10, phy_data);
2785 if (ret_val)
2786 return ret_val;
2787
2788 if (((hw->phy_type == em_phy_m88) &&
2789 (hw->phy_revision < M88E1011_I_REV_40x04) &&
2790 (hw->phy_id != BME1000_E_PHY_ID0x01410CB0)) ||
2791 (hw->phy_type == em_phy_oem)) {
2792 /*
2793 * Force TX_CLK in the Extended PHY Specific Control Register
2794 * to 25MHz clock.
2795 */
2796 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
2797 &phy_data);
2798 if (ret_val)
2799 return ret_val;
2800
2801 if (hw->phy_type == em_phy_oem) {
2802 phy_data |= M88E1000_EPSCR_TX_TIME_CTRL0x0002;
2803 phy_data |= M88E1000_EPSCR_RX_TIME_CTRL0x0080;
2804 }
2805 phy_data |= M88E1000_EPSCR_TX_CLK_250x0070;
2806
2807 if ((hw->phy_revision == E1000_REVISION_22) &&
2808 (hw->phy_id == M88E1111_I_PHY_ID0x01410CC0)) {
2809 /* Vidalia Phy, set the downshift counter to 5x */
2810 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK0x0E00);
2811 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X0x0800;
2812 ret_val = em_write_phy_reg(hw,
2813 M88E1000_EXT_PHY_SPEC_CTRL0x14, phy_data);
2814 if (ret_val)
2815 return ret_val;
2816 } else {
2817 /* Configure Master and Slave downshift values */
2818 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK0x0C00 |
2819 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK0x0300);
2820 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X0x0000 |
2821 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X0x0100);
2822 ret_val = em_write_phy_reg(hw,
2823 M88E1000_EXT_PHY_SPEC_CTRL0x14, phy_data);
2824 if (ret_val)
2825 return ret_val;
2826 }
2827 }
2828 if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
2829 /*
2830 * Set PHY page 0, register 29 to 0x0003
2831 * The next two writes are supposed to lower BER for gig
2832 * connection
2833 */
2834 ret_val = em_write_phy_reg(hw, BM_REG_BIAS129, 0x0003);
2835 if (ret_val)
2836 return ret_val;
2837
2838 /* Set PHY page 0, register 30 to 0x0000 */
2839 ret_val = em_write_phy_reg(hw, BM_REG_BIAS230, 0x0000);
2840 if (ret_val)
2841 return ret_val;
2842 }
2843 if (hw->phy_type == em_phy_82578) {
2844 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
2845 &phy_data);
2846 if (ret_val)
2847 return ret_val;
2848
2849 /* 82578 PHY - set the downshift count to 1x. */
2850 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE0x0020;
2851 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK0x001C;
2852 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
2853 phy_data);
2854 if (ret_val)
2855 return ret_val;
2856 }
2857 /* SW Reset the PHY so all changes take effect */
2858 ret_val = em_phy_reset(hw);
2859 if (ret_val) {
2860 DEBUGOUT("Error Resetting the PHY\n");
2861 return ret_val;
2862 }
2863 return E1000_SUCCESS0;
2864}
2865
2866/******************************************************************************
2867 * Copper link setup for em_phy_82577 series.
2868 *
2869 * hw - Struct containing variables accessed by shared code
2870 *****************************************************************************/
2871static int32_t
2872em_copper_link_82577_setup(struct em_hw *hw)
2873{
2874 int32_t ret_val;
2875 uint16_t phy_data;
2876 uint32_t led_ctl;
2877 DEBUGFUNC("em_copper_link_82577_setup");;
2878
2879 if (hw->phy_reset_disable)
2880 return E1000_SUCCESS0;
2881
2882 /* Enable CRS on TX for half-duplex operation. */
2883 ret_val = em_read_phy_reg(hw, I82577_PHY_CFG_REG22, &phy_data);
2884 if (ret_val)
2885 return ret_val;
2886
2887 phy_data |= I82577_PHY_CFG_ENABLE_CRS_ON_TX(1 << 15) |
2888 I82577_PHY_CFG_ENABLE_DOWNSHIFT((1 << 10) + (1 << 11));
2889
2890 ret_val = em_write_phy_reg(hw, I82577_PHY_CFG_REG22, phy_data);
2891 if (ret_val)
2892 return ret_val;
2893
2894 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2895 msec_delay(15)(*delay_func)(1000*(15));
2896 led_ctl = hw->ledctl_mode1;
2897
2898 /* disable lplu d0 during driver init */
2899 ret_val = em_set_lplu_state_pchlan(hw, FALSE0);
2900 if (ret_val) {
2901 DEBUGOUT("Error Disabling LPLU D0\n");
2902 return ret_val;
2903 }
2904
2905 E1000_WRITE_REG(hw, LEDCTL, led_ctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctl)));
2906
2907 return E1000_SUCCESS0;
2908}
2909
2910static int32_t
2911em_copper_link_82580_setup(struct em_hw *hw)
2912{
2913 int32_t ret_val;
2914 uint16_t phy_data;
2915
2916 if (hw->phy_reset_disable)
2917 return E1000_SUCCESS0;
2918
2919 ret_val = em_phy_reset(hw);
2920 if (ret_val)
2921 goto out;
2922
2923 /* Enable CRS on TX. This must be set for half-duplex operation. */
2924 ret_val = em_read_phy_reg(hw, I82580_CFG_REG22, &phy_data);
2925 if (ret_val)
2926 goto out;
2927
2928 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX(1 << 15) |
2929 I82580_CFG_ENABLE_DOWNSHIFT(3 << 10);
2930
2931 ret_val = em_write_phy_reg(hw, I82580_CFG_REG22, phy_data);
2932
2933out:
2934 return ret_val;
2935}
2936
2937static int32_t
2938em_copper_link_rtl8211_setup(struct em_hw *hw)
2939{
2940 int32_t ret_val;
2941 uint16_t phy_data;
2942
2943 DEBUGFUNC("em_copper_link_rtl8211_setup: begin");;
2944
2945 if (!hw) {
2946 return -1;
2947 }
2948 /* SW Reset the PHY so all changes take effect */
2949 em_phy_hw_reset(hw);
2950
2951 /* Enable CRS on TX. This must be set for half-duplex operation. */
2952 phy_data = 0;
2953
2954 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data);
2955 if (ret_val) {
2956 printf("Unable to read RGEPHY_CR register\n");
2957 return ret_val;
2958 }
2959 DEBUGOUT3("RTL8211: Rx phy_id=%X addr=%X SPEC_CTRL=%X\n", hw->phy_id,
2960 hw->phy_addr, phy_data);
2961 phy_data |= RGEPHY_CR_ASSERT_CRS0x0800;
2962
2963 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data);
2964 if (ret_val) {
2965 printf("Unable to write RGEPHY_CR register\n");
2966 return ret_val;
2967 }
2968
2969 phy_data = 0; /* LED Control Register 0x18 */
2970 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC0x18, &phy_data);
2971 if (ret_val) {
2972 printf("Unable to read RGEPHY_LC register\n");
2973 return ret_val;
2974 }
2975
2976 phy_data &= 0x80FF; /* bit-15=0 disable, clear bit 8-10 */
2977 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC0x18, phy_data);
2978 if (ret_val) {
2979 printf("Unable to write RGEPHY_LC register\n");
2980 return ret_val;
2981 }
2982 /* LED Control and Definition Register 0x11, PHY spec status reg */
2983 phy_data = 0;
2984 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR0x11, &phy_data);
2985 if (ret_val) {
2986 printf("Unable to read RGEPHY_SR register\n");
2987 return ret_val;
2988 }
2989
2990 phy_data |= 0x0010; /* LED active Low */
2991 ret_val = em_write_phy_reg_ex(hw, RGEPHY_SR0x11, phy_data);
2992 if (ret_val) {
2993 printf("Unable to write RGEPHY_SR register\n");
2994 return ret_val;
2995 }
2996
2997 phy_data = 0;
2998 ret_val = em_read_phy_reg_ex(hw, RGEPHY_SR0x11, &phy_data);
2999 if (ret_val) {
3000 printf("Unable to read RGEPHY_SR register\n");
3001 return ret_val;
3002 }
3003
3004 /* Switch to Page2 */
3005 phy_data = RGEPHY_PS_PAGE_20x0002;
3006 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS0x1F, phy_data);
3007 if (ret_val) {
3008 printf("Unable to write PHY RGEPHY_PS register\n");
3009 return ret_val;
3010 }
3011
3012 phy_data = 0x0000;
3013 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P20x1A, phy_data);
3014 if (ret_val) {
3015 printf("Unable to write RGEPHY_LC_P2 register\n");
3016 return ret_val;
3017 }
3018 usec_delay(5)(*delay_func)(5);
3019
3020
3021 /* LED Configuration Control Reg for setting for 0x1A Register */
3022 phy_data = 0;
3023 ret_val = em_read_phy_reg_ex(hw, RGEPHY_LC_P20x1A, &phy_data);
3024 if (ret_val) {
3025 printf("Unable to read RGEPHY_LC_P2 register\n");
3026 return ret_val;
3027 }
3028
3029 phy_data &= 0xF000;
3030 phy_data |= 0x0F24;
3031 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC_P20x1A, phy_data);
3032 if (ret_val) {
3033 printf("Unable to write RGEPHY_LC_P2 register\n");
3034 return ret_val;
3035 }
3036 phy_data = 0;
3037 ret_val= em_read_phy_reg_ex(hw, RGEPHY_LC_P20x1A, &phy_data);
3038 if (ret_val) {
3039 printf("Unable to read RGEPHY_LC_P2 register\n");
3040 return ret_val;
3041 }
3042 DEBUGOUT1("RTL8211:ReadBack for check, LED_CFG->data=%X\n", phy_data);
3043
3044
3045 /* After setting Page2, go back to Page 0 */
3046 phy_data = 0;
3047 ret_val = em_write_phy_reg_ex(hw, RGEPHY_PS0x1F, phy_data);
3048 if (ret_val) {
3049 printf("Unable to write PHY RGEPHY_PS register\n");
3050 return ret_val;
3051 }
3052
3053 /* pulse streching= 42-84ms, blink rate=84mm */
3054 phy_data = 0x140 | RGEPHY_LC_PULSE_42MS0x2000 | RGEPHY_LC_LINK0x0008 |
3055 RGEPHY_LC_DUPLEX0x0004 | RGEPHY_LC_RX0x0002;
3056
3057 ret_val = em_write_phy_reg_ex(hw, RGEPHY_LC0x18, phy_data);
3058 if (ret_val) {
3059 printf("Unable to write RGEPHY_LC register\n");
3060 return ret_val;
3061 }
3062 return E1000_SUCCESS0;
3063}
3064
3065/******************************************************************************
3066 * Setup auto-negotiation and flow control advertisements,
3067 * and then perform auto-negotiation.
3068 *
3069 * hw - Struct containing variables accessed by shared code
3070 *****************************************************************************/
3071int32_t
3072em_copper_link_autoneg(struct em_hw *hw)
3073{
3074 int32_t ret_val;
3075 uint16_t phy_data;
3076 DEBUGFUNC("em_copper_link_autoneg");;
3077 /*
3078 * Perform some bounds checking on the hw->autoneg_advertised
3079 * parameter. If this variable is zero, then set it to the default.
3080 */
3081 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F;
3082 /*
3083 * If autoneg_advertised is zero, we assume it was not defaulted by
3084 * the calling code so we set to advertise full capability.
3085 */
3086 if (hw->autoneg_advertised == 0)
3087 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F;
3088
3089 /* IFE phy only supports 10/100 */
3090 if (hw->phy_type == em_phy_ife)
3091 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL0x000F;
3092
3093 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
3094 ret_val = em_phy_setup_autoneg(hw);
3095 if (ret_val) {
3096 DEBUGOUT("Error Setting up Auto-Negotiation\n");
3097 return ret_val;
3098 }
3099 DEBUGOUT("Restarting Auto-Neg\n");
3100 /*
3101 * Restart auto-negotiation by setting the Auto Neg Enable bit and
3102 * the Auto Neg Restart bit in the PHY control register.
3103 */
3104 ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &phy_data);
3105 if (ret_val)
3106 return ret_val;
3107
3108 phy_data |= (MII_CR_AUTO_NEG_EN0x1000 | MII_CR_RESTART_AUTO_NEG0x0200);
3109 ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, phy_data);
3110 if (ret_val)
3111 return ret_val;
3112 /*
3113 * Does the user want to wait for Auto-Neg to complete here, or check
3114 * at a later time (for example, callback routine).
3115 */
3116 if (hw->wait_autoneg_complete) {
3117 ret_val = em_wait_autoneg(hw);
3118 if (ret_val) {
3119 DEBUGOUT("Error while waiting for autoneg to complete\n"
3120 );
3121 return ret_val;
3122 }
3123 }
3124 hw->get_link_status = TRUE1;
3125
3126 return E1000_SUCCESS0;
3127}
3128
3129/******************************************************************************
3130 * Config the MAC and the PHY after link is up.
3131 * 1) Set up the MAC to the current PHY speed/duplex
3132 * if we are on 82543. If we
3133 * are on newer silicon, we only need to configure
3134 * collision distance in the Transmit Control Register.
3135 * 2) Set up flow control on the MAC to that established with
3136 * the link partner.
3137 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3138 *
3139 * hw - Struct containing variables accessed by shared code
3140 *****************************************************************************/
3141int32_t
3142em_copper_link_postconfig(struct em_hw *hw)
3143{
3144 int32_t ret_val;
3145 DEBUGFUNC("em_copper_link_postconfig");;
3146
3147 if (hw->mac_type >= em_82544 &&
3148 hw->mac_type != em_icp_xxxx) {
3149 em_config_collision_dist(hw);
3150 } else {
3151 ret_val = em_config_mac_to_phy(hw);
3152 if (ret_val) {
3153 DEBUGOUT("Error configuring MAC to PHY settings\n");
3154 return ret_val;
3155 }
3156 }
3157 ret_val = em_config_fc_after_link_up(hw);
3158 if (ret_val) {
3159 DEBUGOUT("Error Configuring Flow Control\n");
3160 return ret_val;
3161 }
3162 /* Config DSP to improve Giga link quality */
3163 if (hw->phy_type == em_phy_igp) {
3164 ret_val = em_config_dsp_after_link_change(hw, TRUE1);
3165 if (ret_val) {
3166 DEBUGOUT("Error Configuring DSP after link up\n");
3167 return ret_val;
3168 }
3169 }
3170 return E1000_SUCCESS0;
3171}
3172
3173/******************************************************************************
3174 * Detects which PHY is present and setup the speed and duplex
3175 *
3176 * hw - Struct containing variables accessed by shared code
3177 *****************************************************************************/
3178static int32_t
3179em_setup_copper_link(struct em_hw *hw)
3180{
3181 int32_t ret_val;
3182 uint16_t i;
3183 uint16_t phy_data;
3184 uint16_t reg_data;
3185 DEBUGFUNC("em_setup_copper_link");;
3186
3187 switch (hw->mac_type) {
3188 case em_80003es2lan:
3189 case em_ich8lan:
3190 case em_ich9lan:
3191 case em_ich10lan:
3192 case em_pchlan:
3193 case em_pch2lan:
3194 case em_pch_lpt:
3195 case em_pch_spt:
3196 case em_pch_cnp:
3197 case em_pch_tgp:
3198 case em_pch_adp:
3199 /*
3200 * Set the mac to wait the maximum time between each
3201 * iteration and increase the max iterations when polling the
3202 * phy; this fixes erroneous timeouts at 10Mbps.
3203 */
3204 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 4)(((0x34) << 5) | ((4) & 0x1F)), 0xFFFF);
3205 if (ret_val)
3206 return ret_val;
3207 ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9)(((0x34) << 5) | ((9) & 0x1F)),
3208 &reg_data);
3209 if (ret_val)
3210 return ret_val;
3211 reg_data |= 0x3F;
3212 ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9)(((0x34) << 5) | ((9) & 0x1F)),
3213 reg_data);
3214 if (ret_val)
3215 return ret_val;
3216 default:
3217 break;
3218 }
3219
3220 /* Check if it is a valid PHY and set PHY mode if necessary. */
3221 ret_val = em_copper_link_preconfig(hw);
3222 if (ret_val)
3223 return ret_val;
3224
3225 switch (hw->mac_type) {
3226 case em_80003es2lan:
3227 /* Kumeran registers are written-only */
3228 reg_data =
3229 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT0x00000500;
3230 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING0x00000010;
3231 ret_val = em_write_kmrn_reg(hw,
3232 E1000_KUMCTRLSTA_OFFSET_INB_CTRL0x00000002, reg_data);
3233 if (ret_val)
3234 return ret_val;
3235 break;
3236 default:
3237 break;
3238 }
3239
3240 if (hw->phy_type == em_phy_igp ||
3241 hw->phy_type == em_phy_igp_3 ||
3242 hw->phy_type == em_phy_igp_2) {
3243 ret_val = em_copper_link_igp_setup(hw);
3244 if (ret_val)
3245 return ret_val;
3246 } else if (hw->phy_type == em_phy_m88 ||
3247 hw->phy_type == em_phy_bm ||
3248 hw->phy_type == em_phy_oem ||
3249 hw->phy_type == em_phy_82578) {
3250 ret_val = em_copper_link_mgp_setup(hw);
3251 if (ret_val)
3252 return ret_val;
3253 } else if (hw->phy_type == em_phy_gg82563) {
3254 ret_val = em_copper_link_ggp_setup(hw);
3255 if (ret_val)
3256 return ret_val;
3257 } else if (hw->phy_type == em_phy_82577 ||
3258 hw->phy_type == em_phy_82579 ||
3259 hw->phy_type == em_phy_i217) {
3260 ret_val = em_copper_link_82577_setup(hw);
3261 if (ret_val)
3262 return ret_val;
3263 } else if (hw->phy_type == em_phy_82580) {
3264 ret_val = em_copper_link_82580_setup(hw);
3265 if (ret_val)
3266 return ret_val;
3267 } else if (hw->phy_type == em_phy_rtl8211) {
3268 ret_val = em_copper_link_rtl8211_setup(hw);
3269 if (ret_val)
3270 return ret_val;
3271 }
3272 if (hw->autoneg) {
3273 /*
3274 * Setup autoneg and flow control advertisement and perform
3275 * autonegotiation
3276 */
3277 ret_val = em_copper_link_autoneg(hw);
3278 if (ret_val)
3279 return ret_val;
3280 } else {
3281 /*
3282 * PHY will be set to 10H, 10F, 100H,or 100F depending on
3283 * value from forced_speed_duplex.
3284 */
3285 DEBUGOUT("Forcing speed and duplex\n");
3286 ret_val = em_phy_force_speed_duplex(hw);
3287 if (ret_val) {
3288 DEBUGOUT("Error Forcing Speed and Duplex\n");
3289 return ret_val;
3290 }
3291 }
3292 /*
3293 * Check link status. Wait up to 100 microseconds for link to become
3294 * valid.
3295 */
3296 for (i = 0; i < 10; i++) {
3297 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
3298 if (ret_val)
3299 return ret_val;
3300 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
3301 if (ret_val)
3302 return ret_val;
3303
3304 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS0x0004) != 0;
3305
3306 if (phy_data & MII_SR_LINK_STATUS0x0004) {
3307 /* Config the MAC and PHY after link is up */
3308 ret_val = em_copper_link_postconfig(hw);
3309 if (ret_val)
3310 return ret_val;
3311
3312 DEBUGOUT("Valid link established!!!\n");
3313 return E1000_SUCCESS0;
3314 }
3315 usec_delay(10)(*delay_func)(10);
3316 }
3317
3318 DEBUGOUT("Unable to establish link!!!\n");
3319 return E1000_SUCCESS0;
3320}
3321
3322/******************************************************************************
3323 * Configure the MAC-to-PHY interface for 10/100Mbps
3324 *
3325 * hw - Struct containing variables accessed by shared code
3326 *****************************************************************************/
3327static int32_t
3328em_configure_kmrn_for_10_100(struct em_hw *hw, uint16_t duplex)
3329{
3330 int32_t ret_val = E1000_SUCCESS0;
3331 uint32_t tipg;
3332 uint16_t reg_data;
3333 DEBUGFUNC("em_configure_kmrn_for_10_100");;
3334
3335 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT0x00000004;
3336 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010,
3337 reg_data);
3338 if (ret_val)
3339 return ret_val;
3340
3341 /* Configure Transmit Inter-Packet Gap */
3342 tipg = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410)))));
3343 tipg &= ~E1000_TIPG_IPGT_MASK0x000003FF;
3344 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_1000x00000009;
3345 E1000_WRITE_REG(hw, TIPG, tipg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410))), (tipg)));
3346
3347 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &reg_data);
3348
3349 if (ret_val)
3350 return ret_val;
3351
3352 if (duplex == HALF_DUPLEX1)
3353 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
3354 else
3355 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
3356
3357 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), reg_data);
3358
3359 return ret_val;
3360}
3361
3362static int32_t
3363em_configure_kmrn_for_1000(struct em_hw *hw)
3364{
3365 int32_t ret_val = E1000_SUCCESS0;
3366 uint16_t reg_data;
3367 uint32_t tipg;
3368 DEBUGFUNC("em_configure_kmrn_for_1000");;
3369
3370 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT0x00000000;
3371 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010,
3372 reg_data);
3373 if (ret_val)
3374 return ret_val;
3375
3376 /* Configure Transmit Inter-Packet Gap */
3377 tipg = E1000_READ_REG(hw, TIPG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410)))));
3378 tipg &= ~E1000_TIPG_IPGT_MASK0x000003FF;
3379 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10000x00000008;
3380 E1000_WRITE_REG(hw, TIPG, tipg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00410 : em_translate_82542_register
(0x00410))), (tipg)));
3381
3382 ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), &reg_data);
3383
3384 if (ret_val)
3385 return ret_val;
3386
3387 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER0x0800;
3388 ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL(((193) << 5) | ((16) & 0x1F)), reg_data);
3389
3390 return ret_val;
3391}
3392
3393/******************************************************************************
3394 * Configures PHY autoneg and flow control advertisement settings
3395 *
3396 * hw - Struct containing variables accessed by shared code
3397 *****************************************************************************/
3398int32_t
3399em_phy_setup_autoneg(struct em_hw *hw)
3400{
3401 int32_t ret_val;
3402 uint16_t mii_autoneg_adv_reg;
3403 uint16_t mii_1000t_ctrl_reg;
3404 DEBUGFUNC("em_phy_setup_autoneg");;
3405
3406 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
3407 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV0x04, &mii_autoneg_adv_reg);
3408 if (ret_val)
3409 return ret_val;
3410
3411 if (hw->phy_type != em_phy_ife) {
3412 /* Read the MII 1000Base-T Control Register (Address 9). */
3413 ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL0x09,
3414 &mii_1000t_ctrl_reg);
3415 if (ret_val)
3416 return ret_val;
3417 } else
3418 mii_1000t_ctrl_reg = 0;
3419 /*
3420 * Need to parse both autoneg_advertised and fc and set up the
3421 * appropriate PHY registers. First we will parse for
3422 * autoneg_advertised software override. Since we can advertise a
3423 * plethora of combinations, we need to check each bit individually.
3424 */
3425 /*
3426 * First we clear all the 10/100 mb speed bits in the Auto-Neg
3427 * Advertisement Register (Address 4) and the 1000 mb speed bits in
3428 * the 1000Base-T Control Register (Address 9).
3429 */
3430 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK0x01E0;
3431 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK0x0300;
3432
3433 DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
3434
3435 /* Do we want to advertise 10 Mb Half Duplex? */
3436 if (hw->autoneg_advertised & ADVERTISE_10_HALF0x0001) {
3437 DEBUGOUT("Advertise 10mb Half duplex\n");
3438 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS0x0020;
3439 }
3440 /* Do we want to advertise 10 Mb Full Duplex? */
3441 if (hw->autoneg_advertised & ADVERTISE_10_FULL0x0002) {
3442 DEBUGOUT("Advertise 10mb Full duplex\n");
3443 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS0x0040;
3444 }
3445 /* Do we want to advertise 100 Mb Half Duplex? */
3446 if (hw->autoneg_advertised & ADVERTISE_100_HALF0x0004) {
3447 DEBUGOUT("Advertise 100mb Half duplex\n");
3448 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS0x0080;
3449 }
3450 /* Do we want to advertise 100 Mb Full Duplex? */
3451 if (hw->autoneg_advertised & ADVERTISE_100_FULL0x0008) {
3452 DEBUGOUT("Advertise 100mb Full duplex\n");
3453 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS0x0100;
3454 }
3455 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3456 if (hw->autoneg_advertised & ADVERTISE_1000_HALF0x0010) {
3457 DEBUGOUT("Advertise 1000mb Half duplex requested, request"
3458 " denied!\n");
3459 }
3460 /* Do we want to advertise 1000 Mb Full Duplex? */
3461 if (hw->autoneg_advertised & ADVERTISE_1000_FULL0x0020) {
3462 DEBUGOUT("Advertise 1000mb Full duplex\n");
3463 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS0x0200;
3464 if (hw->phy_type == em_phy_ife) {
3465 DEBUGOUT("em_phy_ife is a 10/100 PHY. Gigabit speed is"
3466 " not supported.\n");
3467 }
3468 }
3469 /*
3470 * Check for a software override of the flow control settings, and
3471 * setup the PHY advertisement registers accordingly. If
3472 * auto-negotiation is enabled, then software will have to set the
3473 * "PAUSE" bits to the correct value in the Auto-Negotiation
3474 * Advertisement Register (PHY_AUTONEG_ADV) and re-start
3475 * auto-negotiation.
3476 *
3477 * The possible values of the "fc" parameter are: 0: Flow control is
3478 * completely disabled 1: Rx flow control is enabled (we can receive
3479 * pause frames but not send pause frames). 2: Tx flow control is
3480 * enabled (we can send pause frames but we do not support receiving
3481 * pause frames). 3: Both Rx and TX flow control (symmetric) are
3482 * enabled. other: No software override. The flow control
3483 * configuration in the EEPROM is used.
3484 */
3485 switch (hw->fc) {
3486 case E1000_FC_NONE0: /* 0 */
3487 /*
3488 * Flow control (RX & TX) is completely disabled by a
3489 * software over-ride.
3490 */
3491 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
3492 break;
3493 case E1000_FC_RX_PAUSE1:/* 1 */
3494 /*
3495 * RX Flow control is enabled, and TX Flow control is
3496 * disabled, by a software over-ride.
3497 */
3498 /*
3499 * Since there really isn't a way to advertise that we are
3500 * capable of RX Pause ONLY, we will advertise that we
3501 * support both symmetric and asymmetric RX PAUSE. Later (in
3502 * em_config_fc_after_link_up) we will disable the hw's
3503 * ability to send PAUSE frames.
3504 */
3505 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
3506 break;
3507 case E1000_FC_TX_PAUSE2:/* 2 */
3508 /*
3509 * TX Flow control is enabled, and RX Flow control is
3510 * disabled, by a software over-ride.
3511 */
3512 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR0x0800;
3513 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE0x0400;
3514 break;
3515 case E1000_FC_FULL3: /* 3 */
3516 /*
3517 * Flow control (both RX and TX) is enabled by a software
3518 * over-ride.
3519 */
3520 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR0x0800 | NWAY_AR_PAUSE0x0400);
3521 break;
3522 default:
3523 DEBUGOUT("Flow control param set incorrectly\n");
3524 return -E1000_ERR_CONFIG3;
3525 }
3526
3527 ret_val = em_write_phy_reg(hw, PHY_AUTONEG_ADV0x04, mii_autoneg_adv_reg);
3528 if (ret_val)
3529 return ret_val;
3530
3531 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3532
3533 if (hw->phy_type != em_phy_ife) {
3534 ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL0x09,
3535 mii_1000t_ctrl_reg);
3536 if (ret_val)
3537 return ret_val;
3538 }
3539 return E1000_SUCCESS0;
3540}
3541/******************************************************************************
3542 * Force PHY speed and duplex settings to hw->forced_speed_duplex
3543 *
3544 * hw - Struct containing variables accessed by shared code
3545 *****************************************************************************/
3546static int32_t
3547em_phy_force_speed_duplex(struct em_hw *hw)
3548{
3549 uint32_t ctrl;
3550 int32_t ret_val;
3551 uint16_t mii_ctrl_reg;
3552 uint16_t mii_status_reg;
3553 uint16_t phy_data;
3554 uint16_t i;
3555 DEBUGFUNC("em_phy_force_speed_duplex");;
3556
3557 /* Turn off Flow control if we are forcing speed and duplex. */
3558 hw->fc = E1000_FC_NONE0;
3559
3560 DEBUGOUT1("hw->fc = %d\n", hw->fc);
3561
3562 /* Read the Device Control Register. */
3563 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
3564
3565 /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
3566 ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000);
3567 ctrl &= ~(DEVICE_SPEED_MASK0x00000300);
3568
3569 /* Clear the Auto Speed Detect Enable bit. */
3570 ctrl &= ~E1000_CTRL_ASDE0x00000020;
3571
3572 /* Read the MII Control Register. */
3573 ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &mii_ctrl_reg);
3574 if (ret_val)
3575 return ret_val;
3576
3577 /* We need to disable autoneg in order to force link and duplex. */
3578
3579 mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN0x1000;
3580
3581 /* Are we forcing Full or Half Duplex? */
3582 if (hw->forced_speed_duplex == em_100_full ||
3583 hw->forced_speed_duplex == em_10_full) {
3584 /*
3585 * We want to force full duplex so we SET the full duplex
3586 * bits in the Device and MII Control Registers.
3587 */
3588 ctrl |= E1000_CTRL_FD0x00000001;
3589 mii_ctrl_reg |= MII_CR_FULL_DUPLEX0x0100;
3590 DEBUGOUT("Full Duplex\n");
3591 } else {
3592 /*
3593 * We want to force half duplex so we CLEAR the full duplex
3594 * bits in the Device and MII Control Registers.
3595 */
3596 ctrl &= ~E1000_CTRL_FD0x00000001;
3597 mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX0x0100;
3598 DEBUGOUT("Half Duplex\n");
3599 }
3600
3601 /* Are we forcing 100Mbps??? */
3602 if (hw->forced_speed_duplex == em_100_full ||
3603 hw->forced_speed_duplex == em_100_half) {
3604 /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
3605 ctrl |= E1000_CTRL_SPD_1000x00000100;
3606 mii_ctrl_reg |= MII_CR_SPEED_1000x2000;
3607 mii_ctrl_reg &= ~(MII_CR_SPEED_10000x0040 | MII_CR_SPEED_100x0000);
3608 DEBUGOUT("Forcing 100mb ");
3609 } else {
3610 /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
3611 ctrl &= ~(E1000_CTRL_SPD_10000x00000200 | E1000_CTRL_SPD_1000x00000100);
3612 mii_ctrl_reg |= MII_CR_SPEED_100x0000;
3613 mii_ctrl_reg &= ~(MII_CR_SPEED_10000x0040 | MII_CR_SPEED_1000x2000);
3614 DEBUGOUT("Forcing 10mb ");
3615 }
3616
3617 em_config_collision_dist(hw);
3618
3619 /* Write the configured values back to the Device Control Reg. */
3620 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
3621
3622 if ((hw->phy_type == em_phy_m88) ||
3623 (hw->phy_type == em_phy_gg82563) ||
3624 (hw->phy_type == em_phy_bm) ||
3625 (hw->phy_type == em_phy_oem ||
3626 (hw->phy_type == em_phy_82578))) {
3627 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3628 &phy_data);
3629 if (ret_val)
3630 return ret_val;
3631 /*
3632 * Clear Auto-Crossover to force MDI manually. M88E1000
3633 * requires MDI forced whenever speed are duplex are forced.
3634 */
3635 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE0x0060;
3636 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3637 phy_data);
3638 if (ret_val)
3639 return ret_val;
3640
3641 DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
3642
3643 /* Need to reset the PHY or these changes will be ignored */
3644 mii_ctrl_reg |= MII_CR_RESET0x8000;
3645
3646 }
3647 else if (hw->phy_type == em_phy_rtl8211) {
3648 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data);
3649 if(ret_val) {
3650 printf("Unable to read RGEPHY_CR register\n"
3651 );
3652 return ret_val;
3653 }
3654
3655 /*
3656 * Clear Auto-Crossover to force MDI manually. RTL8211 requires
3657 * MDI forced whenever speed are duplex are forced.
3658 */
3659
3660 phy_data |= RGEPHY_CR_MDI_MASK0x0060; // enable MDIX
3661 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data);
3662 if(ret_val) {
3663 printf("Unable to write RGEPHY_CR register\n");
3664 return ret_val;
3665 }
3666 mii_ctrl_reg |= MII_CR_RESET0x8000;
3667
3668 }
3669 /* Disable MDI-X support for 10/100 */
3670 else if (hw->phy_type == em_phy_ife) {
3671 ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL0x1C, &phy_data);
3672 if (ret_val)
3673 return ret_val;
3674
3675 phy_data &= ~IFE_PMC_AUTO_MDIX0x0080;
3676 phy_data &= ~IFE_PMC_FORCE_MDIX0x0040;
3677
3678 ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL0x1C, phy_data);
3679 if (ret_val)
3680 return ret_val;
3681 } else {
3682 /*
3683 * Clear Auto-Crossover to force MDI manually. IGP requires
3684 * MDI forced whenever speed or duplex are forced.
3685 */
3686 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12,
3687 &phy_data);
3688 if (ret_val)
3689 return ret_val;
3690
3691 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX0x1000;
3692 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX0x2000;
3693
3694 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL0x12,
3695 phy_data);
3696 if (ret_val)
3697 return ret_val;
3698 }
3699
3700 /* Write back the modified PHY MII control register. */
3701 ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, mii_ctrl_reg);
3702 if (ret_val)
3703 return ret_val;
3704
3705 usec_delay(1)(*delay_func)(1);
3706 /*
3707 * The wait_autoneg_complete flag may be a little misleading here.
3708 * Since we are forcing speed and duplex, Auto-Neg is not enabled.
3709 * But we do want to delay for a period while forcing only so we
3710 * don't generate false No Link messages. So we will wait here only
3711 * if the user has set wait_autoneg_complete to 1, which is the
3712 * default.
3713 */
3714 if (hw->wait_autoneg_complete) {
3715 /* We will wait for autoneg to complete. */
3716 DEBUGOUT("Waiting for forced speed/duplex link.\n");
3717 mii_status_reg = 0;
3718 /*
3719 * We will wait for autoneg to complete or 4.5 seconds to
3720 * expire.
3721 */
3722 for (i = PHY_FORCE_TIME20; i > 0; i--) {
3723 /*
3724 * Read the MII Status Register and wait for Auto-Neg
3725 * Complete bit to be set.
3726 */
3727 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3728 &mii_status_reg);
3729 if (ret_val)
3730 return ret_val;
3731
3732 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3733 &mii_status_reg);
3734 if (ret_val)
3735 return ret_val;
3736
3737 if (mii_status_reg & MII_SR_LINK_STATUS0x0004)
3738 break;
3739 msec_delay(100)(*delay_func)(1000*(100));
3740 }
3741 if ((i == 0) &&
3742 ((hw->phy_type == em_phy_m88) ||
3743 (hw->phy_type == em_phy_gg82563) ||
3744 (hw->phy_type == em_phy_bm))) {
3745 /*
3746 * We didn't get link. Reset the DSP and wait again
3747 * for link.
3748 */
3749 ret_val = em_phy_reset_dsp(hw);
3750 if (ret_val) {
3751 DEBUGOUT("Error Resetting PHY DSP\n");
3752 return ret_val;
3753 }
3754 }
3755 /*
3756 * This loop will early-out if the link condition has been
3757 * met.
3758 */
3759 for (i = PHY_FORCE_TIME20; i > 0; i--) {
3760 if (mii_status_reg & MII_SR_LINK_STATUS0x0004)
3761 break;
3762 msec_delay(100)(*delay_func)(1000*(100));
3763 /*
3764 * Read the MII Status Register and wait for Auto-Neg
3765 * Complete bit to be set.
3766 */
3767 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3768 &mii_status_reg);
3769 if (ret_val)
3770 return ret_val;
3771
3772 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01,
3773 &mii_status_reg);
3774 if (ret_val)
3775 return ret_val;
3776 }
3777 }
3778 if (hw->phy_type == em_phy_m88 ||
3779 hw->phy_type == em_phy_bm ||
3780 hw->phy_type == em_phy_oem) {
3781 /*
3782 * Because we reset the PHY above, we need to re-force TX_CLK
3783 * in the Extended PHY Specific Control Register to 25MHz
3784 * clock. This value defaults back to a 2.5MHz clock when
3785 * the PHY is reset.
3786 */
3787 ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
3788 &phy_data);
3789 if (ret_val)
3790 return ret_val;
3791
3792 phy_data |= M88E1000_EPSCR_TX_CLK_250x0070;
3793 ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL0x14,
3794 phy_data);
3795 if (ret_val)
3796 return ret_val;
3797 /*
3798 * In addition, because of the s/w reset above, we need to
3799 * enable CRS on TX. This must be set for both full and half
3800 * duplex operation.
3801 */
3802 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3803 &phy_data);
3804 if (ret_val)
3805 return ret_val;
3806
3807 if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0)
3808 phy_data &= ~M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
3809 else
3810 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX0x0800;
3811
3812 ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL0x10,
3813 phy_data);
3814 if (ret_val)
3815 return ret_val;
3816
3817 if ((hw->mac_type == em_82544 || hw->mac_type == em_82543) &&
3818 (!hw->autoneg) && (hw->forced_speed_duplex == em_10_full ||
3819 hw->forced_speed_duplex == em_10_half)) {
3820 ret_val = em_polarity_reversal_workaround(hw);
3821 if (ret_val)
3822 return ret_val;
3823 }
3824 } else if (hw->phy_type == em_phy_rtl8211) {
3825 /*
3826 * In addition, because of the s/w reset above, we need to enable
3827 * CRX on TX. This must be set for both full and half duplex
3828 * operation.
3829 */
3830
3831 ret_val = em_read_phy_reg_ex(hw, RGEPHY_CR0x10, &phy_data);
3832 if(ret_val) {
3833 printf("Unable to read RGEPHY_CR register\n");
3834 return ret_val;
3835 }
3836
3837 phy_data &= ~RGEPHY_CR_ASSERT_CRS0x0800;
3838 ret_val = em_write_phy_reg_ex(hw, RGEPHY_CR0x10, phy_data);
3839 if(ret_val) {
3840 printf("Unable to write RGEPHY_CR register\n");
3841 return ret_val;
3842 }
3843 } else if (hw->phy_type == em_phy_gg82563) {
3844 /*
3845 * The TX_CLK of the Extended PHY Specific Control Register
3846 * defaults to 2.5MHz on a reset. We need to re-force it
3847 * back to 25MHz, if we're not in a forced 10/duplex
3848 * configuration.
3849 */
3850 ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
3851 &phy_data);
3852 if (ret_val)
3853 return ret_val;
3854
3855 phy_data &= ~GG82563_MSCR_TX_CLK_MASK0x0007;
3856 if ((hw->forced_speed_duplex == em_10_full) ||
3857 (hw->forced_speed_duplex == em_10_half))
3858 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ0x0004;
3859 else
3860 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ0x0005;
3861
3862 /* Also due to the reset, we need to enable CRS on Tx. */
3863 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX0x0010;
3864
3865 ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL(((2) << 5) | ((21) & 0x1F)),
3866 phy_data);
3867 if (ret_val)
3868 return ret_val;
3869 }
3870 return E1000_SUCCESS0;
3871}
3872
3873/******************************************************************************
3874 * Sets the collision distance in the Transmit Control register
3875 *
3876 * hw - Struct containing variables accessed by shared code
3877 *
3878 * Link should have been established previously. Reads the speed and duplex
3879 * information from the Device Status register.
3880 *****************************************************************************/
3881void
3882em_config_collision_dist(struct em_hw *hw)
3883{
3884 uint32_t tctl, coll_dist;
3885 DEBUGFUNC("em_config_collision_dist");;
3886
3887 if (hw->mac_type < em_82543)
3888 coll_dist = E1000_COLLISION_DISTANCE_8254264;
3889 else
3890 coll_dist = E1000_COLLISION_DISTANCE63;
3891
3892 tctl = E1000_READ_REG(hw, TCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400)))));
3893
3894 tctl &= ~E1000_TCTL_COLD0x003ff000;
3895 tctl |= coll_dist << E1000_COLD_SHIFT12;
3896
3897 E1000_WRITE_REG(hw, TCTL, tctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00400 : em_translate_82542_register
(0x00400))), (tctl)));
3898 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
3899}
3900
3901/******************************************************************************
3902 * Sets MAC speed and duplex settings to reflect the those in the PHY
3903 *
3904 * hw - Struct containing variables accessed by shared code
3905 * mii_reg - data to write to the MII control register
3906 *
3907 * The contents of the PHY register containing the needed information need to
3908 * be passed in.
3909 *****************************************************************************/
3910static int32_t
3911em_config_mac_to_phy(struct em_hw *hw)
3912{
3913 uint32_t ctrl;
3914 int32_t ret_val;
3915 uint16_t phy_data;
3916 DEBUGFUNC("em_config_mac_to_phy");;
3917 /*
3918 * 82544 or newer MAC, Auto Speed Detection takes care of MAC
3919 * speed/duplex configuration.
3920 */
3921 if (hw->mac_type >= em_82544
3922 && hw->mac_type != em_icp_xxxx)
3923 return E1000_SUCCESS0;
3924 /*
3925 * Read the Device Control Register and set the bits to Force Speed
3926 * and Duplex.
3927 */
3928 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
3929 ctrl |= (E1000_CTRL_FRCSPD0x00000800 | E1000_CTRL_FRCDPX0x00001000);
3930 ctrl &= ~(E1000_CTRL_SPD_SEL0x00000300 | E1000_CTRL_ILOS0x00000080);
3931 /*
3932 * Set up duplex in the Device Control and Transmit Control registers
3933 * depending on negotiated values.
3934 */
3935 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS0x11, &phy_data);
3936 if (ret_val)
3937 return ret_val;
3938
3939 if (phy_data & M88E1000_PSSR_DPLX0x2000)
3940 ctrl |= E1000_CTRL_FD0x00000001;
3941 else
3942 ctrl &= ~E1000_CTRL_FD0x00000001;
3943
3944 em_config_collision_dist(hw);
3945 /*
3946 * Set up speed in the Device Control register depending on
3947 * negotiated values.
3948 */
3949 if ((phy_data & M88E1000_PSSR_SPEED0xC000) == M88E1000_PSSR_1000MBS0x8000)
3950 ctrl |= E1000_CTRL_SPD_10000x00000200;
3951 else if ((phy_data & M88E1000_PSSR_SPEED0xC000) == M88E1000_PSSR_100MBS0x4000)
3952 ctrl |= E1000_CTRL_SPD_1000x00000100;
3953
3954 /* Write the configured values back to the Device Control Reg. */
3955 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
3956 return E1000_SUCCESS0;
3957}
3958
3959/******************************************************************************
3960 * Forces the MAC's flow control settings.
3961 *
3962 * hw - Struct containing variables accessed by shared code
3963 *
3964 * Sets the TFCE and RFCE bits in the device control register to reflect
3965 * the adapter settings. TFCE and RFCE need to be explicitly set by
3966 * software when a Copper PHY is used because autonegotiation is managed
3967 * by the PHY rather than the MAC. Software must also configure these
3968 * bits when link is forced on a fiber connection.
3969 *****************************************************************************/
3970int32_t
3971em_force_mac_fc(struct em_hw *hw)
3972{
3973 uint32_t ctrl;
3974 DEBUGFUNC("em_force_mac_fc");;
3975
3976 /* Get the current configuration of the Device Control Register */
3977 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
3978 /*
3979 * Because we didn't get link via the internal auto-negotiation
3980 * mechanism (we either forced link or we got link via PHY auto-neg),
3981 * we have to manually enable/disable transmit an receive flow
3982 * control.
3983 *
3984 * The "Case" statement below enables/disable flow control according to
3985 * the "hw->fc" parameter.
3986 *
3987 * The possible values of the "fc" parameter are: 0: Flow control is
3988 * completely disabled 1: Rx flow control is enabled (we can receive
3989 * pause frames but not send pause frames). 2: Tx flow control is
3990 * enabled (we can send pause frames but we do not receive
3991 * pause frames). 3: Both Rx and TX flow control (symmetric) is
3992 * enabled. other: No other values should be possible at this point.
3993 */
3994
3995 switch (hw->fc) {
3996 case E1000_FC_NONE0:
3997 ctrl &= (~(E1000_CTRL_TFCE0x10000000 | E1000_CTRL_RFCE0x08000000));
3998 break;
3999 case E1000_FC_RX_PAUSE1:
4000 ctrl &= (~E1000_CTRL_TFCE0x10000000);
4001 ctrl |= E1000_CTRL_RFCE0x08000000;
4002 break;
4003 case E1000_FC_TX_PAUSE2:
4004 ctrl &= (~E1000_CTRL_RFCE0x08000000);
4005 ctrl |= E1000_CTRL_TFCE0x10000000;
4006 break;
4007 case E1000_FC_FULL3:
4008 ctrl |= (E1000_CTRL_TFCE0x10000000 | E1000_CTRL_RFCE0x08000000);
4009 break;
4010 default:
4011 DEBUGOUT("Flow control param set incorrectly\n");
4012 return -E1000_ERR_CONFIG3;
4013 }
4014
4015 /* Disable TX Flow Control for 82542 (rev 2.0) */
4016 if (hw->mac_type == em_82542_rev2_0)
4017 ctrl &= (~E1000_CTRL_TFCE0x10000000);
4018
4019 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
4020 return E1000_SUCCESS0;
4021}
4022/******************************************************************************
4023 * Configures flow control settings after link is established
4024 *
4025 * hw - Struct containing variables accessed by shared code
4026 *
4027 * Should be called immediately after a valid link has been established.
4028 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
4029 * and autonegotiation is enabled, the MAC flow control settings will be set
4030 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
4031 * and RFCE bits will be automatically set to the negotiated flow control mode.
4032 *****************************************************************************/
4033STATIC int32_t
4034em_config_fc_after_link_up(struct em_hw *hw)
4035{
4036 int32_t ret_val;
4037 uint16_t mii_status_reg;
4038 uint16_t mii_nway_adv_reg;
4039 uint16_t mii_nway_lp_ability_reg;
4040 uint16_t speed;
4041 uint16_t duplex;
4042 DEBUGFUNC("em_config_fc_after_link_up");;
4043 /*
4044 * Check for the case where we have fiber media and auto-neg failed
4045 * so we had to force link. In this case, we need to force the
4046 * configuration of the MAC to match the "fc" parameter.
4047 */
4048 if (((hw->media_type == em_media_type_fiber) && (hw->autoneg_failed))
4049 || ((hw->media_type == em_media_type_internal_serdes) &&
4050 (hw->autoneg_failed)) ||
4051 ((hw->media_type == em_media_type_copper) && (!hw->autoneg)) ||
4052 ((hw->media_type == em_media_type_oem) && (!hw->autoneg))) {
4053 ret_val = em_force_mac_fc(hw);
4054 if (ret_val) {
4055 DEBUGOUT("Error forcing flow control settings\n");
4056 return ret_val;
4057 }
4058 }
4059 /*
4060 * Check for the case where we have copper media and auto-neg is
4061 * enabled. In this case, we need to check and see if Auto-Neg has
4062 * completed, and if so, how the PHY and link partner has flow
4063 * control configured.
4064 */
4065 if ((hw->media_type == em_media_type_copper ||
4066 (hw->media_type == em_media_type_oem)) &&
4067 hw->autoneg) {
4068 /*
4069 * Read the MII Status Register and check to see if AutoNeg
4070 * has completed. We read this twice because this reg has
4071 * some "sticky" (latched) bits.
4072 */
4073 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
4074 if (ret_val)
4075 return ret_val;
4076 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
4077 if (ret_val)
4078 return ret_val;
4079
4080 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE0x0020) {
4081 /*
4082 * The AutoNeg process has completed, so we now need
4083 * to read both the Auto Negotiation Advertisement
4084 * Register (Address 4) and the Auto_Negotiation Base
4085 * Page Ability Register (Address 5) to determine how
4086 * flow control was negotiated.
4087 */
4088 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_ADV0x04,
4089 &mii_nway_adv_reg);
4090 if (ret_val)
4091 return ret_val;
4092 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY0x05,
4093 &mii_nway_lp_ability_reg);
4094 if (ret_val)
4095 return ret_val;
4096 /*
4097 * Two bits in the Auto Negotiation Advertisement
4098 * Register (Address 4) and two bits in the Auto
4099 * Negotiation Base Page Ability Register (Address 5)
4100 * determine flow control for both the PHY and the
4101 * link partner. The following table, taken out of
4102 * the IEEE 802.3ab/D6.0 dated March 25, 1999,
4103 * describes these PAUSE resolution bits and how flow
4104 * control is determined based upon these settings.
4105 * NOTE: DC = Don't Care
4106 *
4107 * LOCAL DEVICE | LINK PARTNER |
4108 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
4109 * -------|---------|-------|---------|---------------
4110 * 0 | 0 | DC | DC | em_fc_none
4111 * 0 | 1 | 0 | DC | em_fc_none
4112 * 0 | 1 | 1 | 0 | em_fc_none
4113 * 0 | 1 | 1 | 1 | em_fc_tx_pause
4114 * 1 | 0 | 0 | DC | em_fc_none
4115 * 1 | DC | 1 | DC | em_fc_full
4116 * 1 | 1 | 0 | 0 | em_fc_none
4117 * 1 | 1 | 0 | 1 | em_fc_rx_pause
4118 *
4119 */
4120 /*
4121 * Are both PAUSE bits set to 1? If so, this implies
4122 * Symmetric Flow Control is enabled at both ends.
4123 * The ASM_DIR bits are irrelevant per the spec.
4124 *
4125 * For Symmetric Flow Control:
4126 *
4127 * LOCAL DEVICE | LINK PARTNER
4128 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
4129 * -------|---------|-------|---------|---------------
4130 * 1 | DC | 1 | DC | em_fc_full
4131 *
4132 */
4133 if ((mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) &&
4134 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400)) {
4135 /*
4136 * Now we need to check if the user selected
4137 * RX ONLY of pause frames. In this case, we
4138 * had to advertise FULL flow control because
4139 * we could not advertise RX ONLY. Hence, we
4140 * must now check to see if we need to turn
4141 * OFF the TRANSMISSION of PAUSE frames.
4142 */
4143 if (hw->original_fc == E1000_FC_FULL3) {
4144 hw->fc = E1000_FC_FULL3;
4145 DEBUGOUT("Flow Control = FULL.\n");
4146 } else {
4147 hw->fc = E1000_FC_RX_PAUSE1;
4148 DEBUGOUT("Flow Control = RX PAUSE"
4149 " frames only.\n");
4150 }
4151 }
4152 /*
4153 * For receiving PAUSE frames ONLY.
4154 *
4155 * LOCAL DEVICE | LINK PARTNER PAUSE | ASM_DIR |
4156 * PAUSE | ASM_DIR | Result
4157 * -------|---------|-------|---------|---------------
4158 * ----- 0 | 1 | 1 | 1 |
4159 * em_fc_tx_pause
4160 *
4161 */
4162 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) &&
4163 (mii_nway_adv_reg & NWAY_AR_ASM_DIR0x0800) &&
4164 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400) &&
4165 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR0x0800)) {
4166 hw->fc = E1000_FC_TX_PAUSE2;
4167 DEBUGOUT("Flow Control = TX PAUSE frames only."
4168 "\n");
4169 }
4170 /*
4171 * For transmitting PAUSE frames ONLY.
4172 *
4173 * LOCAL DEVICE | LINK PARTNER
4174 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
4175 * -------|---------|-------|---------|---------------
4176 * 1 | 1 | 0 | 1 | em_fc_rx_pause
4177 *
4178 */
4179 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE0x0400) &&
4180 (mii_nway_adv_reg & NWAY_AR_ASM_DIR0x0800) &&
4181 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE0x0400) &&
4182 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR0x0800)) {
4183 hw->fc = E1000_FC_RX_PAUSE1;
4184 DEBUGOUT("Flow Control = RX PAUSE frames only."
4185 "\n");
4186 }
4187 /*
4188 * Per the IEEE spec, at this point flow control
4189 * should be disabled. However, we want to consider
4190 * that we could be connected to a legacy switch that
4191 * doesn't advertise desired flow control, but can be
4192 * forced on the link partner. So if we advertised
4193 * no flow control, that is what we will resolve to.
4194 * If we advertised some kind of receive capability
4195 * (Rx Pause Only or Full Flow Control) and the link
4196 * partner advertised none, we will configure
4197 * ourselves to enable Rx Flow Control only. We can
4198 * do this safely for two reasons: If the link
4199 * partner really didn't want flow control enabled,
4200 * and we enable Rx, no harm done since we won't be
4201 * receiving any PAUSE frames anyway. If the intent
4202 * on the link partner was to have flow control
4203 * enabled, then by us enabling RX only, we can at
4204 * least receive pause frames and process them. This
4205 * is a good idea because in most cases, since we are
4206 * predominantly a server NIC, more times than not we
4207 * will be asked to delay transmission of packets
4208 * than asking our link partner to pause transmission
4209 * of frames.
4210 */
4211 else if ((hw->original_fc == E1000_FC_NONE0 ||
4212 hw->original_fc == E1000_FC_TX_PAUSE2) ||
4213 hw->fc_strict_ieee) {
4214 hw->fc = E1000_FC_NONE0;
4215 DEBUGOUT("Flow Control = NONE.\n");
4216 } else {
4217 hw->fc = E1000_FC_RX_PAUSE1;
4218 DEBUGOUT("Flow Control = RX PAUSE frames only."
4219 "\n");
4220 }
4221 /*
4222 * Now we need to do one last check... If we auto-
4223 * negotiated to HALF DUPLEX, flow control should not
4224 * be enabled per IEEE 802.3 spec.
4225 */
4226 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4227 if (ret_val) {
4228 DEBUGOUT("Error getting link speed and duplex"
4229 "\n");
4230 return ret_val;
4231 }
4232 if (duplex == HALF_DUPLEX1)
4233 hw->fc = E1000_FC_NONE0;
4234 /*
4235 * Now we call a subroutine to actually force the MAC
4236 * controller to use the correct flow control
4237 * settings.
4238 */
4239 ret_val = em_force_mac_fc(hw);
4240 if (ret_val) {
4241 DEBUGOUT("Error forcing flow control settings"
4242 "\n");
4243 return ret_val;
4244 }
4245 } else {
4246 DEBUGOUT("Copper PHY and Auto Neg has not completed."
4247 "\n");
4248 }
4249 }
4250 return E1000_SUCCESS0;
4251}
4252/******************************************************************************
4253 * Checks to see if the link status of the hardware has changed.
4254 *
4255 * hw - Struct containing variables accessed by shared code
4256 *
4257 * Called by any function that needs to check the link status of the adapter.
4258 *****************************************************************************/
4259int32_t
4260em_check_for_link(struct em_hw *hw)
4261{
4262 uint32_t rxcw = 0;
4263 uint32_t ctrl;
4264 uint32_t status;
4265 uint32_t rctl;
4266 uint32_t icr;
4267 uint32_t signal = 0;
4268 int32_t ret_val;
4269 uint16_t phy_data;
4270 DEBUGFUNC("em_check_for_link");;
4271 uint16_t speed, duplex;
4272
4273 if (hw->mac_type >= em_82575 &&
4274 hw->media_type != em_media_type_copper) {
4275 ret_val = em_get_pcs_speed_and_duplex_82575(hw, &speed,
4276 &duplex);
4277 hw->get_link_status = hw->serdes_link_down;
4278
4279 return (ret_val);
4280 }
4281
4282 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
4283 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
4284 /*
4285 * On adapters with a MAC newer than 82544, SW Defineable pin 1 will
4286 * be set when the optics detect a signal. On older adapters, it will
4287 * be cleared when there is a signal. This applies to fiber media
4288 * only.
4289 */
4290 if ((hw->media_type == em_media_type_fiber) ||
4291 (hw->media_type == em_media_type_internal_serdes)) {
4292 rxcw = E1000_READ_REG(hw, RXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00180 : em_translate_82542_register
(0x00180)))));
4293
4294 if (hw->media_type == em_media_type_fiber) {
4295 signal = (hw->mac_type > em_82544) ?
4296 E1000_CTRL_SWDPIN10x00080000 : 0;
4297 if (status & E1000_STATUS_LU0x00000002)
4298 hw->get_link_status = FALSE0;
4299 }
4300 }
4301 /*
4302 * If we have a copper PHY then we only want to go out to the PHY
4303 * registers to see if Auto-Neg has completed and/or if our link
4304 * status has changed. The get_link_status flag will be set if we
4305 * receive a Link Status Change interrupt or we have Rx Sequence
4306 * Errors.
4307 */
4308 if ((hw->media_type == em_media_type_copper ||
4309 (hw->media_type == em_media_type_oem)) &&
4310 hw->get_link_status) {
4311 /*
4312 * First we want to see if the MII Status Register reports
4313 * link. If so, then we want to get the current speed/duplex
4314 * of the PHY. Read the register twice since the link bit is
4315 * sticky.
4316 */
4317 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4318 if (ret_val)
4319 return ret_val;
4320 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4321 if (ret_val)
4322 return ret_val;
4323
4324 hw->icp_xxxx_is_link_up = (phy_data & MII_SR_LINK_STATUS0x0004) != 0;
4325
4326 if (hw->mac_type == em_pchlan) {
4327 ret_val = em_k1_gig_workaround_hv(hw,
4328 hw->icp_xxxx_is_link_up);
4329 if (ret_val)
4330 return ret_val;
4331 }
4332
4333 if (phy_data & MII_SR_LINK_STATUS0x0004) {
4334 hw->get_link_status = FALSE0;
4335
4336 if (hw->phy_type == em_phy_82578) {
4337 ret_val = em_link_stall_workaround_hv(hw);
4338 if (ret_val)
4339 return ret_val;
4340 }
4341
4342 if (hw->mac_type == em_pch2lan) {
4343 ret_val = em_k1_workaround_lv(hw);
4344 if (ret_val)
4345 return ret_val;
4346 }
4347 /* Work-around I218 hang issue */
4348 if ((hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM0x155A) ||
4349 (hw->device_id == E1000_DEV_ID_PCH_LPTLP_I218_V0x1559) ||
4350 (hw->device_id == E1000_DEV_ID_PCH_I218_LM30x15A2) ||
4351 (hw->device_id == E1000_DEV_ID_PCH_I218_V30x15A3)) {
4352 ret_val = em_k1_workaround_lpt_lp(hw,
4353 hw->icp_xxxx_is_link_up);
4354 if (ret_val)
4355 return ret_val;
4356 }
4357
4358 /*
4359 * Check if there was DownShift, must be checked
4360 * immediately after link-up
4361 */
4362 em_check_downshift(hw);
4363
4364 /* Enable/Disable EEE after link up */
4365 if (hw->mac_type == em_pch2lan ||
4366 hw->mac_type == em_pch_lpt ||
4367 hw->mac_type == em_pch_spt ||
4368 hw->mac_type == em_pch_cnp ||
4369 hw->mac_type == em_pch_tgp ||
4370 hw->mac_type == em_pch_adp) {
4371 ret_val = em_set_eee_pchlan(hw);
4372 if (ret_val)
4373 return ret_val;
4374 }
4375
4376 /*
4377 * If we are on 82544 or 82543 silicon and
4378 * speed/duplex are forced to 10H or 10F, then we
4379 * will implement the polarity reversal workaround.
4380 * We disable interrupts first, and upon returning,
4381 * place the devices interrupt state to its previous
4382 * value except for the link status change interrupt
4383 * which will happen due to the execution of this
4384 * workaround.
4385 */
4386 if ((hw->mac_type == em_82544 ||
4387 hw->mac_type == em_82543) && (!hw->autoneg) &&
4388 (hw->forced_speed_duplex == em_10_full ||
4389 hw->forced_speed_duplex == em_10_half)) {
4390 E1000_WRITE_REG(hw, IMC, 0xffffffff)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D8 : em_translate_82542_register
(0x000D8))), (0xffffffff)));
4391 ret_val = em_polarity_reversal_workaround(hw);
4392 icr = E1000_READ_REG(hw, ICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C0 : em_translate_82542_register
(0x000C0)))));
4393 E1000_WRITE_REG(hw, ICS,((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C8 : em_translate_82542_register
(0x000C8))), ((icr & ~0x00000004))))
4394 (icr & ~E1000_ICS_LSC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000C8 : em_translate_82542_register
(0x000C8))), ((icr & ~0x00000004))));
4395 E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x000D0 : em_translate_82542_register
(0x000D0))), (( 0x00000080 | 0x00000001 | 0x00000010 | 0x00000008
| 0x00000040 | 0x00000004))));
4396 }
4397 } else {
4398 /* No link detected */
4399 em_config_dsp_after_link_change(hw, FALSE0);
4400 return 0;
4401 }
4402 /*
4403 * If we are forcing speed/duplex, then we simply return
4404 * since we have already determined whether we have link or
4405 * not.
4406 */
4407 if (!hw->autoneg)
4408 return -E1000_ERR_CONFIG3;
4409
4410 /* optimize the dsp settings for the igp phy */
4411 em_config_dsp_after_link_change(hw, TRUE1);
4412 /*
4413 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
4414 * have Si on board that is 82544 or newer, Auto Speed
4415 * Detection takes care of MAC speed/duplex configuration.
4416 * So we only need to configure Collision Distance in the
4417 * MAC. Otherwise, we need to force speed/duplex on the MAC
4418 * to the current PHY speed/duplex settings.
4419 */
4420 if (hw->mac_type >= em_82544 && hw->mac_type != em_icp_xxxx) {
4421 em_config_collision_dist(hw);
4422 } else {
4423 ret_val = em_config_mac_to_phy(hw);
4424 if (ret_val) {
4425 DEBUGOUT("Error configuring MAC to PHY"
4426 " settings\n");
4427 return ret_val;
4428 }
4429 }
4430 /*
4431 * Configure Flow Control now that Auto-Neg has completed.
4432 * First, we need to restore the desired flow control
4433 * settings because we may have had to re-autoneg with a
4434 * different link partner.
4435 */
4436 ret_val = em_config_fc_after_link_up(hw);
4437 if (ret_val) {
4438 DEBUGOUT("Error configuring flow control\n");
4439 return ret_val;
4440 }
4441 /*
4442 * At this point we know that we are on copper and we have
4443 * auto-negotiated link. These are conditions for checking
4444 * the link partner capability register. We use the link
4445 * speed to determine if TBI compatibility needs to be turned
4446 * on or off. If the link is not at gigabit speed, then TBI
4447 * compatibility is not needed. If we are at gigabit speed,
4448 * we turn on TBI compatibility.
4449 */
4450 if (hw->tbi_compatibility_en) {
4451 uint16_t speed, duplex;
4452 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
4453 if (ret_val) {
4454 DEBUGOUT("Error getting link speed and duplex"
4455 "\n");
4456 return ret_val;
4457 }
4458 if (speed != SPEED_10001000) {
4459 /*
4460 * If link speed is not set to gigabit speed,
4461 * we do not need to enable TBI
4462 * compatibility.
4463 */
4464 if (hw->tbi_compatibility_on) {
4465 /*
4466 * If we previously were in the mode,
4467 * turn it off.
4468 */
4469 rctl = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100)))));
4470 rctl &= ~E1000_RCTL_SBP0x00000004;
4471 E1000_WRITE_REG(hw, RCTL, rctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (rctl)));
4472 hw->tbi_compatibility_on = FALSE0;
4473 }
4474 } else {
4475 /*
4476 * If TBI compatibility is was previously
4477 * off, turn it on. For compatibility with a
4478 * TBI link partner, we will store bad
4479 * packets. Some frames have an additional
4480 * byte on the end and will look like CRC
4481 * errors to the hardware.
4482 */
4483 if (!hw->tbi_compatibility_on) {
4484 hw->tbi_compatibility_on = TRUE1;
4485 rctl = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100)))));
4486 rctl |= E1000_RCTL_SBP0x00000004;
4487 E1000_WRITE_REG(hw, RCTL, rctl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (rctl)));
4488 }
4489 }
4490 }
4491 }
4492 /*
4493 * If we don't have link (auto-negotiation failed or link partner
4494 * cannot auto-negotiate), the cable is plugged in (we have signal),
4495 * and our link partner is not trying to auto-negotiate with us (we
4496 * are receiving idles or data), we need to force link up. We also
4497 * need to give auto-negotiation time to complete, in case the cable
4498 * was just plugged in. The autoneg_failed flag does this.
4499 */
4500 else if ((((hw->media_type == em_media_type_fiber) &&
4501 ((ctrl & E1000_CTRL_SWDPIN10x00080000) == signal)) ||
4502 (hw->media_type == em_media_type_internal_serdes)) &&
4503 (!(status & E1000_STATUS_LU0x00000002)) && (!(rxcw & E1000_RXCW_C0x20000000))) {
4504 if (hw->autoneg_failed == 0) {
4505 hw->autoneg_failed = 1;
4506 return 0;
4507 }
4508 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
4509
4510 /* Disable auto-negotiation in the TXCW register */
4511 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))), ((hw->txcw & ~0x80000000))));
4512
4513 /* Force link-up and also force full-duplex. */
4514 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
4515 ctrl |= (E1000_CTRL_SLU0x00000040 | E1000_CTRL_FD0x00000001);
4516 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
4517
4518 /* Configure Flow Control after forcing link up. */
4519 ret_val = em_config_fc_after_link_up(hw);
4520 if (ret_val) {
4521 DEBUGOUT("Error configuring flow control\n");
4522 return ret_val;
4523 }
4524 }
4525 /*
4526 * If we are forcing link and we are receiving /C/ ordered sets,
4527 * re-enable auto-negotiation in the TXCW register and disable forced
4528 * link in the Device Control register in an attempt to
4529 * auto-negotiate with our link partner.
4530 */
4531 else if (((hw->media_type == em_media_type_fiber) ||
4532 (hw->media_type == em_media_type_internal_serdes)) &&
4533 (ctrl & E1000_CTRL_SLU0x00000040) && (rxcw & E1000_RXCW_C0x20000000)) {
4534 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
4535 E1000_WRITE_REG(hw, TXCW, hw->txcw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))), (hw->txcw)));
4536 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((ctrl & ~0x00000040))));
4537
4538 hw->serdes_link_down = FALSE0;
4539 }
4540 /*
4541 * If we force link for non-auto-negotiation switch, check link
4542 * status based on MAC synchronization for internal serdes media
4543 * type.
4544 */
4545 else if ((hw->media_type == em_media_type_internal_serdes) &&
4546 !(E1000_TXCW_ANE0x80000000 & E1000_READ_REG(hw, TXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))))))) {
4547 /* SYNCH bit and IV bit are sticky. */
4548 usec_delay(10)(*delay_func)(10);
4549 if (E1000_RXCW_SYNCH0x40000000 & E1000_READ_REG(hw, RXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00180 : em_translate_82542_register
(0x00180)))))) {
4550 if (!(rxcw & E1000_RXCW_IV0x08000000)) {
4551 hw->serdes_link_down = FALSE0;
4552 DEBUGOUT("SERDES: Link is up.\n");
4553 }
4554 } else {
4555 hw->serdes_link_down = TRUE1;
4556 DEBUGOUT("SERDES: Link is down.\n");
4557 }
4558 }
4559 if ((hw->media_type == em_media_type_internal_serdes) &&
4560 (E1000_TXCW_ANE0x80000000 & E1000_READ_REG(hw, TXCW)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00178 : em_translate_82542_register
(0x00178))))))) {
4561 hw->serdes_link_down = !(E1000_STATUS_LU0x00000002 &
4562 E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))))));
4563 }
4564 return E1000_SUCCESS0;
4565}
4566
4567int32_t
4568em_get_pcs_speed_and_duplex_82575(struct em_hw *hw, uint16_t *speed,
4569 uint16_t *duplex)
4570{
4571 uint32_t pcs;
4572
4573 hw->serdes_link_down = TRUE1;
4574 *speed = 0;
4575 *duplex = 0;
4576
4577 /*
4578 * Read the PCS Status register for link state. For non-copper mode,
4579 * the status register is not accurate. The PCS status register is
4580 * used instead.
4581 */
4582 pcs = E1000_READ_REG(hw, PCS_LSTAT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0420C : em_translate_82542_register
(0x0420C)))));
4583
4584 /*
4585 * The link up bit determines when link is up on autoneg. The sync ok
4586 * gets set once both sides sync up and agree upon link. Stable link
4587 * can be determined by checking for both link up and link sync ok
4588 */
4589 if ((pcs & E1000_PCS_LSTS_LINK_OK0x01) && (pcs & E1000_PCS_LSTS_SYNK_OK0x10)) {
4590 hw->serdes_link_down = FALSE0;
4591
4592 /* Detect and store PCS speed */
4593 if (pcs & E1000_PCS_LSTS_SPEED_10000x04) {
4594 *speed = SPEED_10001000;
4595 } else if (pcs & E1000_PCS_LSTS_SPEED_1000x02) {
4596 *speed = SPEED_100100;
4597 } else {
4598 *speed = SPEED_1010;
4599 }
4600
4601 /* Detect and store PCS duplex */
4602 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL0x08) {
4603 *duplex = FULL_DUPLEX2;
4604 } else {
4605 *duplex = HALF_DUPLEX1;
4606 }
4607 }
4608
4609 return (0);
4610}
4611
4612
4613/******************************************************************************
4614 * Detects the current speed and duplex settings of the hardware.
4615 *
4616 * hw - Struct containing variables accessed by shared code
4617 * speed - Speed of the connection
4618 * duplex - Duplex setting of the connection
4619 *****************************************************************************/
4620int32_t
4621em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex)
4622{
4623 uint32_t status;
4624 int32_t ret_val;
4625 uint16_t phy_data;
4626 DEBUGFUNC("em_get_speed_and_duplex");;
4627
4628 if (hw->mac_type >= em_82575 && hw->media_type != em_media_type_copper)
4629 return em_get_pcs_speed_and_duplex_82575(hw, speed, duplex);
4630
4631 if (hw->mac_type >= em_82543) {
4632 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
4633 if (status & E1000_STATUS_SPEED_10000x00000080) {
4634 *speed = SPEED_10001000;
4635 DEBUGOUT("1000 Mbs, ");
4636 } else if (status & E1000_STATUS_SPEED_1000x00000040) {
4637 *speed = SPEED_100100;
4638 DEBUGOUT("100 Mbs, ");
4639 } else {
4640 *speed = SPEED_1010;
4641 DEBUGOUT("10 Mbs, ");
4642 }
4643
4644 if (status & E1000_STATUS_FD0x00000001) {
4645 *duplex = FULL_DUPLEX2;
4646 DEBUGOUT("Full Duplex\n");
4647 } else {
4648 *duplex = HALF_DUPLEX1;
4649 DEBUGOUT(" Half Duplex\n");
4650 }
4651 } else {
4652 DEBUGOUT("1000 Mbs, Full Duplex\n");
4653 *speed = SPEED_10001000;
4654 *duplex = FULL_DUPLEX2;
4655 }
4656 /*
4657 * IGP01 PHY may advertise full duplex operation after speed
4658 * downgrade even if it is operating at half duplex. Here we set the
4659 * duplex settings to match the duplex in the link partner's
4660 * capabilities.
4661 */
4662 if (hw->phy_type == em_phy_igp && hw->speed_downgraded) {
4663 ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP0x06, &phy_data);
4664 if (ret_val)
4665 return ret_val;
4666
4667 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS0x0001))
4668 *duplex = HALF_DUPLEX1;
4669 else {
4670 ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY0x05,
4671 &phy_data);
4672 if (ret_val)
4673 return ret_val;
4674 if ((*speed == SPEED_100100 &&
4675 !(phy_data & NWAY_LPAR_100TX_FD_CAPS0x0100)) ||
4676 (*speed == SPEED_1010 &&
4677 !(phy_data & NWAY_LPAR_10T_FD_CAPS0x0040)))
4678 *duplex = HALF_DUPLEX1;
4679 }
4680 }
4681 if ((hw->mac_type == em_80003es2lan) &&
4682 (hw->media_type == em_media_type_copper)) {
4683 if (*speed == SPEED_10001000)
4684 ret_val = em_configure_kmrn_for_1000(hw);
4685 else
4686 ret_val = em_configure_kmrn_for_10_100(hw, *duplex);
4687 if (ret_val)
4688 return ret_val;
4689 }
4690 if ((hw->mac_type == em_ich8lan) &&
4691 (hw->phy_type == em_phy_igp_3) &&
4692 (*speed == SPEED_10001000)) {
4693 ret_val = em_kumeran_lock_loss_workaround(hw);
4694 if (ret_val)
4695 return ret_val;
4696 }
4697 return E1000_SUCCESS0;
4698}
4699
4700/******************************************************************************
4701 * Blocks until autoneg completes or times out (~4.5 seconds)
4702 *
4703 * hw - Struct containing variables accessed by shared code
4704 *****************************************************************************/
4705STATIC int32_t
4706em_wait_autoneg(struct em_hw *hw)
4707{
4708 int32_t ret_val;
4709 uint16_t i;
4710 uint16_t phy_data;
4711 DEBUGFUNC("em_wait_autoneg");;
4712 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
4713
4714 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
4715 for (i = PHY_AUTO_NEG_TIME45; i > 0; i--) {
4716 /*
4717 * Read the MII Status Register and wait for Auto-Neg
4718 * Complete bit to be set.
4719 */
4720 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4721 if (ret_val)
4722 return ret_val;
4723 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
4724 if (ret_val)
4725 return ret_val;
4726 if (phy_data & MII_SR_AUTONEG_COMPLETE0x0020) {
4727 return E1000_SUCCESS0;
4728 }
4729 msec_delay(100)(*delay_func)(1000*(100));
4730 }
4731 return E1000_SUCCESS0;
4732}
4733
4734/******************************************************************************
4735 * Raises the Management Data Clock
4736 *
4737 * hw - Struct containing variables accessed by shared code
4738 * ctrl - Device control register's current value
4739 *****************************************************************************/
4740static void
4741em_raise_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4742{
4743 /*
4744 * Raise the clock input to the Management Data Clock (by setting the
4745 * MDC bit), and then delay 10 microseconds.
4746 */
4747 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((*ctrl | 0x00200000))));
4748 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
4749 usec_delay(10)(*delay_func)(10);
4750}
4751
4752/******************************************************************************
4753 * Lowers the Management Data Clock
4754 *
4755 * hw - Struct containing variables accessed by shared code
4756 * ctrl - Device control register's current value
4757 *****************************************************************************/
4758static void
4759em_lower_mdi_clk(struct em_hw *hw, uint32_t *ctrl)
4760{
4761 /*
4762 * Lower the clock input to the Management Data Clock (by clearing
4763 * the MDC bit), and then delay 10 microseconds.
4764 */
4765 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), ((*ctrl & ~0x00200000))));
4766 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
4767 usec_delay(10)(*delay_func)(10);
4768}
4769
4770/******************************************************************************
4771 * Shifts data bits out to the PHY
4772 *
4773 * hw - Struct containing variables accessed by shared code
4774 * data - Data to send out to the PHY
4775 * count - Number of bits to shift out
4776 *
4777 * Bits are shifted out in MSB to LSB order.
4778 *****************************************************************************/
4779static void
4780em_shift_out_mdi_bits(struct em_hw *hw, uint32_t data, uint16_t count)
4781{
4782 uint32_t ctrl;
4783 uint32_t mask;
4784 /*
4785 * We need to shift "count" number of bits out to the PHY. So, the
4786 * value in the "data" parameter will be shifted out to the PHY one
4787 * bit at a time. In order to do this, "data" must be broken down
4788 * into bits.
4789 */
4790 mask = 0x01;
4791 mask <<= (count - 1);
4792
4793 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
4794
4795 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output
4796 * pins.
4797 */
4798 ctrl |= (E1000_CTRL_MDIO_DIR0x01000000 | E1000_CTRL_MDC_DIR0x02000000);
4799
4800 while (mask) {
4801 /*
4802 * A "1" is shifted out to the PHY by setting the MDIO bit to
4803 * "1" and then raising and lowering the Management Data
4804 * Clock. A "0" is shifted out to the PHY by setting the MDIO
4805 * bit to "0" and then raising and lowering the clock.
4806 */
4807 if (data & mask)
4808 ctrl |= E1000_CTRL_MDIO0x00100000;
4809 else
4810 ctrl &= ~E1000_CTRL_MDIO0x00100000;
4811
4812 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
4813 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
4814
4815 usec_delay(10)(*delay_func)(10);
4816
4817 em_raise_mdi_clk(hw, &ctrl);
4818 em_lower_mdi_clk(hw, &ctrl);
4819
4820 mask = mask >> 1;
4821 }
4822}
4823
4824/******************************************************************************
4825 * Shifts data bits in from the PHY
4826 *
4827 * hw - Struct containing variables accessed by shared code
4828 *
4829 * Bits are shifted in in MSB to LSB order.
4830 *****************************************************************************/
4831static uint16_t
4832em_shift_in_mdi_bits(struct em_hw *hw)
4833{
4834 uint32_t ctrl;
4835 uint16_t data = 0;
4836 uint8_t i;
4837 /*
4838 * In order to read a register from the PHY, we need to shift in a
4839 * total of 18 bits from the PHY. The first two bit (turnaround)
4840 * times are used to avoid contention on the MDIO pin when a read
4841 * operation is performed. These two bits are ignored by us and
4842 * thrown away. Bits are "shifted in" by raising the input to the
4843 * Management Data Clock (setting the MDC bit), and then reading the
4844 * value of the MDIO bit.
4845 */
4846 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
4847 /*
4848 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
4849 * input.
4850 */
4851 ctrl &= ~E1000_CTRL_MDIO_DIR0x01000000;
4852 ctrl &= ~E1000_CTRL_MDIO0x00100000;
4853
4854 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
4855 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
4856 /*
4857 * Raise and Lower the clock before reading in the data. This
4858 * accounts for the turnaround bits. The first clock occurred when we
4859 * clocked out the last bit of the Register Address.
4860 */
4861 em_raise_mdi_clk(hw, &ctrl);
4862 em_lower_mdi_clk(hw, &ctrl);
4863
4864 for (data = 0, i = 0; i < 16; i++) {
4865 data = data << 1;
4866 em_raise_mdi_clk(hw, &ctrl);
4867 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
4868 /* Check to see if we shifted in a "1". */
4869 if (ctrl & E1000_CTRL_MDIO0x00100000)
4870 data |= 1;
4871 em_lower_mdi_clk(hw, &ctrl);
4872 }
4873
4874 em_raise_mdi_clk(hw, &ctrl);
4875 em_lower_mdi_clk(hw, &ctrl);
4876
4877 return data;
4878}
4879
4880STATIC int32_t
4881em_swfw_sync_acquire(struct em_hw *hw, uint16_t mask)
4882{
4883 uint32_t swfw_sync = 0;
4884 uint32_t swmask = mask;
4885 uint32_t fwmask = mask << 16;
4886 int32_t timeout = 200;
4887 DEBUGFUNC("em_swfw_sync_acquire");;
4888
4889 if (hw->swfwhw_semaphore_present)
4890 return em_get_software_flag(hw);
4891
4892 if (!hw->swfw_sync_present)
4893 return em_get_hw_eeprom_semaphore(hw);
4894
4895 while (timeout) {
4896 if (em_get_hw_eeprom_semaphore(hw))
4897 return -E1000_ERR_SWFW_SYNC13;
4898
4899 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C)))));
4900 if (!(swfw_sync & (fwmask | swmask))) {
4901 break;
4902 }
4903 /*
4904 * firmware currently using resource (fwmask)
4905 * or other software thread currently using resource (swmask)
4906 */
4907 em_put_hw_eeprom_semaphore(hw);
4908 msec_delay_irq(5)(*delay_func)(1000*(5));
4909 timeout--;
4910 }
4911
4912 if (!timeout) {
4913 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout."
4914 "\n");
4915 return -E1000_ERR_SWFW_SYNC13;
4916 }
4917 swfw_sync |= swmask;
4918 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C))), (swfw_sync)));
4919
4920 em_put_hw_eeprom_semaphore(hw);
4921 return E1000_SUCCESS0;
4922}
4923
4924STATIC void
4925em_swfw_sync_release(struct em_hw *hw, uint16_t mask)
4926{
4927 uint32_t swfw_sync;
4928 uint32_t swmask = mask;
4929 DEBUGFUNC("em_swfw_sync_release");;
4930
4931 if (hw->swfwhw_semaphore_present) {
4932 em_release_software_flag(hw);
4933 return;
4934 }
4935 if (!hw->swfw_sync_present) {
4936 em_put_hw_eeprom_semaphore(hw);
4937 return;
4938 }
4939 /*
4940 * if (em_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC;
4941 */
4942 while (em_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS0);
4943 /* empty */
4944
4945 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C)))));
4946 swfw_sync &= ~swmask;
4947 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B5C : em_translate_82542_register
(0x05B5C))), (swfw_sync)));
4948
4949 em_put_hw_eeprom_semaphore(hw);
4950}
4951
4952/****************************************************************************
4953 * Read BM PHY wakeup register. It works as such:
4954 * 1) Set page 769, register 17, bit 2 = 1
4955 * 2) Set page to 800 for host (801 if we were manageability)
4956 * 3) Write the address using the address opcode (0x11)
4957 * 4) Read or write the data using the data opcode (0x12)
4958 * 5) Restore 769_17.2 to its original value
4959 ****************************************************************************/
4960int32_t
4961em_access_phy_wakeup_reg_bm(struct em_hw *hw, uint32_t reg_addr,
4962 uint16_t *phy_data, boolean_t read)
4963{
4964 int32_t ret_val;
4965 uint16_t reg = BM_PHY_REG_NUM(reg_addr)((uint16_t)(((reg_addr) & 0x1F) | (((reg_addr) >> (
21 - 5)) & ~0x1F)));
4966 uint16_t phy_reg = 0;
4967
4968 /* All operations in this function are phy address 1 */
4969 hw->phy_addr = 1;
4970
4971 /* Set page 769 */
4972 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
4973 (BM_WUC_ENABLE_PAGE769 << PHY_PAGE_SHIFT5));
4974
4975 ret_val = em_read_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, &phy_reg);
4976 if (ret_val)
4977 goto out;
4978
4979 /* First clear bit 4 to avoid a power state change */
4980 phy_reg &= ~(BM_WUC_HOST_WU_BIT(1 << 4));
4981 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, phy_reg);
4982 if (ret_val)
4983 goto out;
4984
4985 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
4986 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17,
4987 phy_reg | BM_WUC_ENABLE_BIT(1 << 2));
4988 if (ret_val)
4989 goto out;
4990
4991 /* Select page 800 */
4992 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
4993 (BM_WUC_PAGE800 << PHY_PAGE_SHIFT5));
4994
4995 /* Write the page 800 offset value using opcode 0x11 */
4996 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ADDRESS_OPCODE0x11, reg);
4997 if (ret_val)
4998 goto out;
4999
5000 if (read)
5001 /* Read the page 800 value using opcode 0x12 */
5002 ret_val = em_read_phy_reg_ex(hw, BM_WUC_DATA_OPCODE0x12,
5003 phy_data);
5004 else
5005 /* Write the page 800 value using opcode 0x12 */
5006 ret_val = em_write_phy_reg_ex(hw, BM_WUC_DATA_OPCODE0x12,
5007 *phy_data);
5008
5009 if (ret_val)
5010 goto out;
5011
5012 /*
5013 * Restore 769_17.2 to its original value
5014 * Set page 769
5015 */
5016 em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5017 (BM_WUC_ENABLE_PAGE769 << PHY_PAGE_SHIFT5));
5018
5019 /* Clear 769_17.2 */
5020 ret_val = em_write_phy_reg_ex(hw, BM_WUC_ENABLE_REG17, phy_reg);
5021 if (ret_val)
5022 goto out;
5023
5024out:
5025 return ret_val;
5026}
5027
5028/***************************************************************************
5029 * Read HV PHY vendor specific high registers
5030 ***************************************************************************/
5031int32_t
5032em_access_phy_debug_regs_hv(struct em_hw *hw, uint32_t reg_addr,
5033 uint16_t *phy_data, boolean_t read)
5034{
5035 int32_t ret_val;
5036 uint32_t addr_reg = 0;
5037 uint32_t data_reg = 0;
5038
5039 /* This takes care of the difference with desktop vs mobile phy */
5040 addr_reg = (hw->phy_type == em_phy_82578) ?
5041 I82578_PHY_ADDR_REG29 : I82577_PHY_ADDR_REG16;
5042 data_reg = addr_reg + 1;
5043
5044 /* All operations in this function are phy address 2 */
5045 hw->phy_addr = 2;
5046
5047 /* masking with 0x3F to remove the page from offset */
5048 ret_val = em_write_phy_reg_ex(hw, addr_reg, (uint16_t)reg_addr & 0x3F);
5049 if (ret_val) {
5050 printf("Could not write PHY the HV address register\n");
5051 goto out;
5052 }
5053
5054 /* Read or write the data value next */
5055 if (read)
5056 ret_val = em_read_phy_reg_ex(hw, data_reg, phy_data);
5057 else
5058 ret_val = em_write_phy_reg_ex(hw, data_reg, *phy_data);
5059
5060 if (ret_val) {
5061 printf("Could not read data value from HV data register\n");
5062 goto out;
5063 }
5064
5065out:
5066 return ret_val;
5067}
5068
5069/******************************************************************************
5070 * Reads or writes the value from a PHY register, if the value is on a specific
5071 * non zero page, sets the page first.
5072 * hw - Struct containing variables accessed by shared code
5073 * reg_addr - address of the PHY register to read
5074 *****************************************************************************/
5075int32_t
5076em_access_phy_reg_hv(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data,
5077 boolean_t read)
5078{
5079 uint32_t ret_val;
5080 uint16_t swfw;
5081 uint16_t page = BM_PHY_REG_PAGE(reg_addr)((uint16_t)(((reg_addr) >> 5) & 0xFFFF));
5082 uint16_t reg = BM_PHY_REG_NUM(reg_addr)((uint16_t)(((reg_addr) & 0x1F) | (((reg_addr) >> (
21 - 5)) & ~0x1F)));
5083
5084 DEBUGFUNC("em_access_phy_reg_hv");;
5085
5086 swfw = E1000_SWFW_PHY0_SM0x0002;
5087
5088 if (em_swfw_sync_acquire(hw, swfw))
5089 return -E1000_ERR_SWFW_SYNC13;
5090
5091 if (page == BM_WUC_PAGE800) {
5092 ret_val = em_access_phy_wakeup_reg_bm(hw, reg_addr,
5093 phy_data, read);
5094 goto release;
5095 }
5096
5097 if (page >= HV_INTC_FC_PAGE_START768)
5098 hw->phy_addr = 1;
5099 else
5100 hw->phy_addr = 2;
5101
5102 if (page == HV_INTC_FC_PAGE_START768)
5103 page = 0;
5104
5105 /*
5106 * Workaround MDIO accesses being disabled after entering IEEE Power
5107 * Down (whenever bit 11 of the PHY Control register is set)
5108 */
5109 if (!read &&
5110 (hw->phy_type == em_phy_82578) &&
5111 (hw->phy_revision >= 1) &&
5112 (hw->phy_addr == 2) &&
5113 ((MAX_PHY_REG_ADDRESS0x1F & reg) == 0) &&
5114 (*phy_data & (1 << 11))) {
5115 uint16_t data2 = 0x7EFF;
5116
5117 ret_val = em_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
5118 &data2, FALSE0);
5119 if (ret_val)
5120 return ret_val;
5121 }
5122
5123 if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) {
5124 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5125 (page << PHY_PAGE_SHIFT5));
5126 if (ret_val)
5127 return ret_val;
5128 }
5129 if (read)
5130 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg,
5131 phy_data);
5132 else
5133 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg,
5134 *phy_data);
5135release:
5136 em_swfw_sync_release(hw, swfw);
5137 return ret_val;
5138}
5139
5140/******************************************************************************
5141 * Reads the value from a PHY register, if the value is on a specific non zero
5142 * page, sets the page first.
5143 * hw - Struct containing variables accessed by shared code
5144 * reg_addr - address of the PHY register to read
5145 *****************************************************************************/
5146int32_t
5147em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5148{
5149 uint32_t ret_val;
5150 uint16_t swfw;
5151 DEBUGFUNC("em_read_phy_reg");;
5152
5153 if (hw->mac_type
38.1
Field 'mac_type' is not equal to em_pchlan
72.1
Field 'mac_type' is not equal to em_pchlan
 == em_pchlan ||
104
←
Assuming field 'mac_type' is not equal to em_pchlan
→
176
←
Assuming field 'mac_type' is not equal to em_pchlan
→
5154 hw->mac_type
38.2
Field 'mac_type' is not equal to em_pch2lan
72.2
Field 'mac_type' is not equal to em_pch2lan
 == em_pch2lan ||
105
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
177
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
5155 hw->mac_type
38.3
Field 'mac_type' is not equal to em_pch_lpt
72.3
Field 'mac_type' is not equal to em_pch_lpt
 == em_pch_lpt ||
106
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
178
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
5156 hw->mac_type
38.4
Field 'mac_type' is not equal to em_pch_spt
72.4
Field 'mac_type' is not equal to em_pch_spt
 == em_pch_spt ||
107
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
179
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
5157 hw->mac_type
38.5
Field 'mac_type' is not equal to em_pch_cnp
72.5
Field 'mac_type' is not equal to em_pch_cnp
 == em_pch_cnp ||
108
←
Assuming field 'mac_type' is not equal to em_pch_cnp
→
180
←
Assuming field 'mac_type' is not equal to em_pch_cnp
→
5158 hw->mac_type
38.6
Field 'mac_type' is not equal to em_pch_tgp
72.6
Field 'mac_type' is not equal to em_pch_tgp
 == em_pch_tgp ||
109
←
Assuming field 'mac_type' is not equal to em_pch_tgp
→
181
←
Assuming field 'mac_type' is not equal to em_pch_tgp
→
5159 hw->mac_type
38.7
Field 'mac_type' is not equal to em_pch_adp
72.7
Field 'mac_type' is not equal to em_pch_adp
 == em_pch_adp)
110
←
Assuming field 'mac_type' is not equal to em_pch_adp
→
182
←
Assuming field 'mac_type' is not equal to em_pch_adp
→
5160 return (em_access_phy_reg_hv(hw, reg_addr, phy_data, TRUE1));
5161
5162 if (((hw->mac_type
38.8
Field 'mac_type' is not equal to em_80003es2lan
72.8
Field 'mac_type' is not equal to em_80003es2lan
 == em_80003es2lan) || (hw->mac_type
38.9
Field 'mac_type' is not equal to em_82575
72.9
Field 'mac_type' is not equal to em_82575
 == em_82575) ||
111
←
Assuming field 'mac_type' is not equal to em_80003es2lan
→
112
←
Assuming field 'mac_type' is not equal to em_82575
→
183
←
Assuming field 'mac_type' is not equal to em_80003es2lan
→
184
←
Assuming field 'mac_type' is not equal to em_82575
→
5163 (hw->mac_type
38.10
Field 'mac_type' is not equal to em_82576
72.10
Field 'mac_type' is not equal to em_82576
 == em_82576)) &&
113
←
Assuming field 'mac_type' is not equal to em_82576
→
185
←
Assuming field 'mac_type' is not equal to em_82576
→
5164 (E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))))) & E1000_STATUS_FUNC_10x00000004)) {
5165 swfw = E1000_SWFW_PHY1_SM0x0004;
5166 } else {
5167 swfw = E1000_SWFW_PHY0_SM0x0002;
5168 }
5169 if (em_swfw_sync_acquire(hw, swfw))
39
←
Assuming the condition is false
→
73
←
Assuming the condition is false
→
114
←
Assuming the condition is false
→
186
←
Assuming the condition is true
→
187
←
Taking true branch
→
5170 return -E1000_ERR_SWFW_SYNC13;
188
←
Returning without writing to '*phy_data'
→
5171
5172 if ((hw->phy_type == em_phy_igp ||
40
←
Assuming field 'phy_type' is not equal to em_phy_igp
→
74
←
Assuming field 'phy_type' is not equal to em_phy_igp
→
115
←
Assuming field 'phy_type' is not equal to em_phy_igp
→
5173 hw->phy_type == em_phy_igp_3 ||
41
←
Assuming field 'phy_type' is not equal to em_phy_igp_3
→
75
←
Assuming field 'phy_type' is not equal to em_phy_igp_3
→
116
←
Assuming field 'phy_type' is not equal to em_phy_igp_3
→
5174 hw->phy_type == em_phy_igp_2) &&
42
←
Assuming field 'phy_type' is not equal to em_phy_igp_2
→
76
←
Assuming field 'phy_type' is not equal to em_phy_igp_2
→
117
←
Assuming field 'phy_type' is not equal to em_phy_igp_2
→
5175 (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF)) {
5176 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5177 (uint16_t) reg_addr);
5178 if (ret_val) {
5179 em_swfw_sync_release(hw, swfw);
5180 return ret_val;
5181 }
5182 } else if (hw->phy_type == em_phy_gg82563) {
43
←
Assuming field 'phy_type' is not equal to em_phy_gg82563
→
77
←
Assuming field 'phy_type' is not equal to em_phy_gg82563
→
118
←
Assuming field 'phy_type' is not equal to em_phy_gg82563
→
5183 if (((reg_addr & MAX_PHY_REG_ADDRESS0x1F) > MAX_PHY_MULTI_PAGE_REG0xF) ||
5184 (hw->mac_type == em_80003es2lan)) {
5185 /* Select Configuration Page */
5186 if ((reg_addr & MAX_PHY_REG_ADDRESS0x1F) <
5187 GG82563_MIN_ALT_REG30) {
5188 ret_val = em_write_phy_reg_ex(hw,
5189 GG82563_PHY_PAGE_SELECT(((0) << 5) | ((22) & 0x1F)),
5190 (uint16_t) ((uint16_t) reg_addr >>
5191 GG82563_PAGE_SHIFT5));
5192 } else {
5193 /*
5194 * Use Alternative Page Select register to
5195 * access registers 30 and 31
5196 */
5197 ret_val = em_write_phy_reg_ex(hw,
5198 GG82563_PHY_PAGE_SELECT_ALT(((0) << 5) | ((29) & 0x1F)),
5199 (uint16_t) ((uint16_t) reg_addr >>
5200 GG82563_PAGE_SHIFT5));
5201 }
5202
5203 if (ret_val) {
5204 em_swfw_sync_release(hw, swfw);
5205 return ret_val;
5206 }
5207 }
5208 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
44
←
Assuming field 'phy_type' is not equal to em_phy_bm
→
78
←
Assuming field 'phy_type' is not equal to em_phy_bm
→
119
←
Assuming field 'phy_type' is not equal to em_phy_bm
→
5209 if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) {
5210 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT22,
5211 (uint16_t) ((uint16_t) reg_addr >>
5212 PHY_PAGE_SHIFT5));
5213 if (ret_val)
5214 return ret_val;
5215 }
5216 }
5217 ret_val = em_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg_addr,
45
←
Calling 'em_read_phy_reg_ex'
→
66
←
Returning from 'em_read_phy_reg_ex'
→
79
←
Calling 'em_read_phy_reg_ex'
→
100
←
Returning from 'em_read_phy_reg_ex'
→
120
←
Calling 'em_read_phy_reg_ex'
→
141
←
Returning from 'em_read_phy_reg_ex'
→
5218 phy_data);
5219
5220 em_swfw_sync_release(hw, swfw);
5221 return ret_val;
5222}
5223
5224STATIC int32_t
5225em_read_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data)
5226{
5227 uint32_t i;
5228 uint32_t mdic = 0;
5229 DEBUGFUNC("em_read_phy_reg_ex");;
5230
5231 /* SGMII active is only set on some specific chips */
5232 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) {
46
←
Assuming field 'sgmii_active' is 0
→
80
←
Assuming field 'sgmii_active' is 0
→
121
←
Assuming field 'sgmii_active' is 0
→
5233 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR255) {
5234 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5235 return -E1000_ERR_PARAM4;
5236 }
5237 return em_read_phy_reg_i2c(hw, reg_addr, phy_data);
5238 }
5239 if (reg_addr
46.1
'reg_addr' is <= MAX_PHY_REG_ADDRESS
80.1
'reg_addr' is <= MAX_PHY_REG_ADDRESS
121.1
'reg_addr' is <= MAX_PHY_REG_ADDRESS
 > MAX_PHY_REG_ADDRESS0x1F) {
47
←
Taking false branch
→
81
←
Taking false branch
→
122
←
Taking false branch
→
5240 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5241 return -E1000_ERR_PARAM4;
5242 }
5243 if (hw->mac_type == em_icp_xxxx) {
48
←
Assuming field 'mac_type' is not equal to em_icp_xxxx
→
49
←
Taking false branch
→
82
←
Assuming field 'mac_type' is not equal to em_icp_xxxx
→
83
←
Taking false branch
→
123
←
Assuming field 'mac_type' is not equal to em_icp_xxxx
→
124
←
Taking false branch
→
5244 *phy_data = gcu_miibus_readreg(hw, hw->icp_xxxx_port_num,
5245 reg_addr);
5246 return E1000_SUCCESS0;
5247 }
5248 if (hw->mac_type > em_82543) {
50
←
Assuming field 'mac_type' is > em_82543
→
51
←
Taking true branch
→
84
←
Assuming field 'mac_type' is > em_82543
→
85
←
Taking true branch
→
125
←
Assuming field 'mac_type' is > em_82543
→
126
←
Taking true branch
→
5249 /*
5250 * Set up Op-code, Phy Address, and register address in the
5251 * MDI Control register. The MAC will take care of
5252 * interfacing with the PHY to retrieve the desired data.
5253 */
5254 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT16) |
5255 (hw->phy_addr << E1000_MDIC_PHY_SHIFT21) |
5256 (E1000_MDIC_OP_READ0x08000000));
5257
5258 E1000_WRITE_REG(hw, MDIC, mdic)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020))), (mdic)));
52
←
'?' condition is true
→
86
←
'?' condition is true
→
127
←
'?' condition is true
→
5259
5260 /*
5261 * Poll the ready bit to see if the MDI read completed
5262 * Increasing the time out as testing showed failures with
5263 * the lower time out (from FreeBSD driver)
5264 */
5265 for (i = 0; i < 1960; i++) {
53
←
Loop condition is true. Entering loop body
→
87
←
Loop condition is true. Entering loop body
→
128
←
Loop condition is true. Entering loop body
→
5266 usec_delay(50)(*delay_func)(50);
5267 mdic = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020)))));
54
←
'?' condition is true
→
88
←
'?' condition is true
→
129
←
'?' condition is true
→
5268 if (mdic & E1000_MDIC_READY0x10000000)
55
←
Assuming the condition is true
→
56
←
Taking true branch
→
89
←
Assuming the condition is true
→
90
←
Taking true branch
→
130
←
Assuming the condition is true
→
131
←
Taking true branch
→
5269 break;
5270 }
5271 if (!(mdic & E1000_MDIC_READY0x10000000)) {
57
←
 Execution continues on line 5271
→
58
←
Taking false branch
→
91
←
 Execution continues on line 5271
→
92
←
Taking false branch
→
132
←
 Execution continues on line 5271
→
133
←
Taking false branch
→
5272 DEBUGOUT("MDI Read did not complete\n");
5273 return -E1000_ERR_PHY2;
5274 }
5275 if (mdic & E1000_MDIC_ERROR0x40000000) {
59
←
Assuming the condition is false
→
60
←
Taking false branch
→
93
←
Assuming the condition is false
→
94
←
Taking false branch
→
134
←
Assuming the condition is false
→
135
←
Taking false branch
→
5276 DEBUGOUT("MDI Error\n");
5277 return -E1000_ERR_PHY2;
5278 }
5279 *phy_data = (uint16_t) mdic;
5280
5281 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
61
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
62
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
95
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
96
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
136
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
137
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
5282 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp ||
63
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
64
←
Assuming field 'mac_type' is equal to em_pch_cnp
→
97
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
98
←
Assuming field 'mac_type' is equal to em_pch_cnp
→
138
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
139
←
Assuming field 'mac_type' is equal to em_pch_cnp
→
5283 hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp)
5284 usec_delay(100)(*delay_func)(100);
5285 } else {
5286 /*
5287 * We must first send a preamble through the MDIO pin to
5288 * signal the beginning of an MII instruction. This is done
5289 * by sending 32 consecutive "1" bits.
5290 */
5291 em_shift_out_mdi_bits(hw, PHY_PREAMBLE0xFFFFFFFF, PHY_PREAMBLE_SIZE32);
5292 /*
5293 * Now combine the next few fields that are required for a
5294 * read operation. We use this method instead of calling the
5295 * em_shift_out_mdi_bits routine five different times. The
5296 * format of a MII read instruction consists of a shift out
5297 * of 14 bits and is defined as follows: <Preamble><SOF><Op
5298 * Code><Phy Addr><Reg Addr> followed by a shift in of 18
5299 * bits. This first two bits shifted in are TurnAround bits
5300 * used to avoid contention on the MDIO pin when a READ
5301 * operation is performed. These two bits are thrown away
5302 * followed by a shift in of 16 bits which contains the
5303 * desired data.
5304 */
5305 mdic = ((reg_addr) | (hw->phy_addr << 5) |
5306 (PHY_OP_READ0x02 << 10) | (PHY_SOF0x01 << 12));
5307
5308 em_shift_out_mdi_bits(hw, mdic, 14);
5309 /*
5310 * Now that we've shifted out the read command to the MII, we
5311 * need to "shift in" the 16-bit value (18 total bits) of the
5312 * requested PHY register address.
5313 */
5314 *phy_data = em_shift_in_mdi_bits(hw);
5315 }
5316 return E1000_SUCCESS0;
65
←
Returning without writing to '->phy_init_script', which participates in a condition later
→
99
←
Returning without writing to '->phy_init_script', which participates in a condition later
→
140
←
Returning without writing to '->phy_init_script', which participates in a condition later
→
5317}
5318
5319/******************************************************************************
5320 * Writes a value to a PHY register
5321 *
5322 * hw - Struct containing variables accessed by shared code
5323 * reg_addr - address of the PHY register to write
5324 * data - data to write to the PHY
5325 *****************************************************************************/
5326int32_t
5327em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5328{
5329 uint32_t ret_val;
5330 DEBUGFUNC("em_write_phy_reg");;
5331
5332 if (hw->mac_type == em_pchlan ||
5333 hw->mac_type == em_pch2lan ||
5334 hw->mac_type == em_pch_lpt ||
5335 hw->mac_type == em_pch_spt ||
5336 hw->mac_type == em_pch_cnp ||
5337 hw->mac_type == em_pch_tgp ||
5338 hw->mac_type == em_pch_adp)
5339 return (em_access_phy_reg_hv(hw, reg_addr, &phy_data, FALSE0));
5340
5341 if (em_swfw_sync_acquire(hw, hw->swfw))
5342 return -E1000_ERR_SWFW_SYNC13;
5343
5344 if ((hw->phy_type == em_phy_igp ||
5345 hw->phy_type == em_phy_igp_3 ||
5346 hw->phy_type == em_phy_igp_2) &&
5347 (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF)) {
5348 ret_val = em_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT0x1F,
5349 (uint16_t) reg_addr);
5350 if (ret_val) {
5351 em_swfw_sync_release(hw, hw->swfw);
5352 return ret_val;
5353 }
5354 } else if (hw->phy_type == em_phy_gg82563) {
5355 if (((reg_addr & MAX_PHY_REG_ADDRESS0x1F) > MAX_PHY_MULTI_PAGE_REG0xF) ||
5356 (hw->mac_type == em_80003es2lan)) {
5357 /* Select Configuration Page */
5358 if ((reg_addr & MAX_PHY_REG_ADDRESS0x1F) <
5359 GG82563_MIN_ALT_REG30) {
5360 ret_val = em_write_phy_reg_ex(hw,
5361 GG82563_PHY_PAGE_SELECT(((0) << 5) | ((22) & 0x1F)),
5362 (uint16_t) ((uint16_t) reg_addr >>
5363 GG82563_PAGE_SHIFT5));
5364 } else {
5365 /*
5366 * Use Alternative Page Select register to
5367 * access registers 30 and 31
5368 */
5369 ret_val = em_write_phy_reg_ex(hw,
5370 GG82563_PHY_PAGE_SELECT_ALT(((0) << 5) | ((29) & 0x1F)),
5371 (uint16_t) ((uint16_t) reg_addr >>
5372 GG82563_PAGE_SHIFT5));
5373 }
5374
5375 if (ret_val) {
5376 em_swfw_sync_release(hw, hw->swfw);
5377 return ret_val;
5378 }
5379 }
5380 } else if ((hw->phy_type == em_phy_bm) && (hw->phy_revision == 1)) {
5381 if (reg_addr > MAX_PHY_MULTI_PAGE_REG0xF) {
5382 ret_val = em_write_phy_reg_ex(hw, BM_PHY_PAGE_SELECT22,
5383 (uint16_t) ((uint16_t) reg_addr >>
5384 PHY_PAGE_SHIFT5));
5385 if (ret_val)
5386 return ret_val;
5387 }
5388 }
5389 ret_val = em_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS0x1F & reg_addr,
5390 phy_data);
5391
5392 em_swfw_sync_release(hw, hw->swfw);
5393 return ret_val;
5394}
5395
5396STATIC int32_t
5397em_write_phy_reg_ex(struct em_hw *hw, uint32_t reg_addr, uint16_t phy_data)
5398{
5399 uint32_t i;
5400 uint32_t mdic = 0;
5401 DEBUGFUNC("em_write_phy_reg_ex");;
5402
5403 /* SGMII active is only set on some specific chips */
5404 if (hw->sgmii_active && !em_sgmii_uses_mdio_82575(hw)) {
5405 if (reg_addr > E1000_MAX_SGMII_PHY_REG_ADDR255) {
5406 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5407 return -E1000_ERR_PARAM4;
5408 }
5409 return em_write_phy_reg_i2c(hw, reg_addr, phy_data);
5410 }
5411 if (reg_addr > MAX_PHY_REG_ADDRESS0x1F) {
5412 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
5413 return -E1000_ERR_PARAM4;
5414 }
5415 if (hw->mac_type == em_icp_xxxx) {
5416 gcu_miibus_writereg(hw, hw->icp_xxxx_port_num,
5417 reg_addr, phy_data);
5418 return E1000_SUCCESS0;
5419 }
5420 if (hw->mac_type > em_82543) {
5421 /*
5422 * Set up Op-code, Phy Address, register address, and data
5423 * intended for the PHY register in the MDI Control register.
5424 * The MAC will take care of interfacing with the PHY to send
5425 * the desired data.
5426 */
5427 mdic = (((uint32_t) phy_data) |
5428 (reg_addr << E1000_MDIC_REG_SHIFT16) |
5429 (hw->phy_addr << E1000_MDIC_PHY_SHIFT21) |
5430 (E1000_MDIC_OP_WRITE0x04000000));
5431
5432 E1000_WRITE_REG(hw, MDIC, mdic)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020))), (mdic)));
5433
5434 /* Poll the ready bit to see if the MDI read completed */
5435 for (i = 0; i < 641; i++) {
5436 usec_delay(5)(*delay_func)(5);
5437 mdic = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020)))));
5438 if (mdic & E1000_MDIC_READY0x10000000)
5439 break;
5440 }
5441 if (!(mdic & E1000_MDIC_READY0x10000000)) {
5442 DEBUGOUT("MDI Write did not complete\n");
5443 return -E1000_ERR_PHY2;
5444 }
5445
5446 if (hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt ||
5447 hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp ||
5448 hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp)
5449 usec_delay(100)(*delay_func)(100);
5450 } else {
5451 /*
5452 * We'll need to use the SW defined pins to shift the write
5453 * command out to the PHY. We first send a preamble to the
5454 * PHY to signal the beginning of the MII instruction. This
5455 * is done by sending 32 consecutive "1" bits.
5456 */
5457 em_shift_out_mdi_bits(hw, PHY_PREAMBLE0xFFFFFFFF, PHY_PREAMBLE_SIZE32);
5458 /*
5459 * Now combine the remaining required fields that will
5460 * indicate a write operation. We use this method instead of
5461 * calling the em_shift_out_mdi_bits routine for each field
5462 * in the command. The format of a MII write instruction is
5463 * as follows: <Preamble><SOF><Op Code><Phy Addr><Reg
5464 * Addr><Turnaround><Data>.
5465 */
5466 mdic = ((PHY_TURNAROUND0x02) | (reg_addr << 2) |
5467 (hw->phy_addr << 7) | (PHY_OP_WRITE0x01 << 12) |
5468 (PHY_SOF0x01 << 14));
5469 mdic <<= 16;
5470 mdic |= (uint32_t) phy_data;
5471
5472 em_shift_out_mdi_bits(hw, mdic, 32);
5473 }
5474
5475 return E1000_SUCCESS0;
5476}
5477
5478STATIC int32_t
5479em_read_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *data)
5480{
5481 uint32_t reg_val;
5482 DEBUGFUNC("em_read_kmrn_reg");;
5483
5484 if (em_swfw_sync_acquire(hw, hw->swfw))
5485 return -E1000_ERR_SWFW_SYNC13;
5486
5487 /* Write register address */
5488 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT16) &
5489 E1000_KUMCTRLSTA_OFFSET0x001F0000) |
5490 E1000_KUMCTRLSTA_REN0x00200000;
5491
5492 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034))), (reg_val)));
5493 usec_delay(2)(*delay_func)(2);
5494
5495 /* Read the data returned */
5496 reg_val = E1000_READ_REG(hw, KUMCTRLSTA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034)))));
5497 *data = (uint16_t) reg_val;
5498
5499 em_swfw_sync_release(hw, hw->swfw);
5500 return E1000_SUCCESS0;
5501}
5502
5503STATIC int32_t
5504em_write_kmrn_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data)
5505{
5506 uint32_t reg_val;
5507 DEBUGFUNC("em_write_kmrn_reg");;
5508
5509 if (em_swfw_sync_acquire(hw, hw->swfw))
5510 return -E1000_ERR_SWFW_SYNC13;
5511
5512 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT16) &
5513 E1000_KUMCTRLSTA_OFFSET0x001F0000) | data;
5514
5515 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00034 : em_translate_82542_register
(0x00034))), (reg_val)));
5516 usec_delay(2)(*delay_func)(2);
5517
5518 em_swfw_sync_release(hw, hw->swfw);
5519 return E1000_SUCCESS0;
5520}
5521
5522/**
5523 * em_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
5524 * @hw: pointer to the HW structure
5525 *
5526 * Called to determine if the I2C pins are being used for I2C or as an
5527 * external MDIO interface since the two options are mutually exclusive.
5528 **/
5529int em_sgmii_uses_mdio_82575(struct em_hw *hw)
5530{
5531 uint32_t reg = 0;
5532 int ext_mdio = 0;
5533
5534 DEBUGFUNC("em_sgmii_uses_mdio_82575");;
5535
5536 switch (hw->mac_type) {
5537 case em_82575:
5538 case em_82576:
5539 reg = E1000_READ_REG(hw, MDIC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00020 : em_translate_82542_register
(0x00020)))));
5540 ext_mdio = !!(reg & E1000_MDIC_DEST0x80000000);
5541 break;
5542 case em_82580:
5543 case em_i350:
5544 case em_i210:
5545 reg = E1000_READ_REG(hw, MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E04 : em_translate_82542_register
(0x00E04)))));
5546 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO0x80000000);
5547 break;
5548 default:
5549 break;
5550 }
5551 return ext_mdio;
5552}
5553
5554/**
5555 * em_read_phy_reg_i2c - Read PHY register using i2c
5556 * @hw: pointer to the HW structure
5557 * @offset: register offset to be read
5558 * @data: pointer to the read data
5559 *
5560 * Reads the PHY register at offset using the i2c interface and stores the
5561 * retrieved information in data.
5562 **/
5563int32_t em_read_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t *data)
5564{
5565 uint32_t i, i2ccmd = 0;
5566
5567 DEBUGFUNC("em_read_phy_reg_i2c");;
5568
5569 /* Set up Op-code, Phy Address, and register address in the I2CCMD
5570 * register. The MAC will take care of interfacing with the
5571 * PHY to retrieve the desired data.
5572 */
5573 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) |
5574 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT24) |
5575 (E1000_I2CCMD_OPCODE_READ0x08000000));
5576
5577 E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028))), (i2ccmd)));
5578
5579 /* Poll the ready bit to see if the I2C read completed */
5580 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) {
5581 usec_delay(50)(*delay_func)(50);
5582 i2ccmd = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028)))));
5583 if (i2ccmd & E1000_I2CCMD_READY0x20000000)
5584 break;
5585 }
5586 if (!(i2ccmd & E1000_I2CCMD_READY0x20000000)) {
5587 DEBUGOUT("I2CCMD Read did not complete\n");
5588 return -E1000_ERR_PHY2;
5589 }
5590 if (i2ccmd & E1000_I2CCMD_ERROR0x80000000) {
5591 DEBUGOUT("I2CCMD Error bit set\n");
5592 return -E1000_ERR_PHY2;
5593 }
5594
5595 /* Need to byte-swap the 16-bit value. */
5596 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
5597
5598 return E1000_SUCCESS0;
5599}
5600
5601/**
5602 * em_write_phy_reg_i2c - Write PHY register using i2c
5603 * @hw: pointer to the HW structure
5604 * @offset: register offset to write to
5605 * @data: data to write at register offset
5606 *
5607 * Writes the data to PHY register at the offset using the i2c interface.
5608 **/
5609int32_t em_write_phy_reg_i2c(struct em_hw *hw, uint32_t offset, uint16_t data)
5610{
5611 uint32_t i, i2ccmd = 0;
5612 uint16_t phy_data_swapped;
5613
5614 DEBUGFUNC("em_write_phy_reg_i2c");;
5615
5616 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
5617 if ((hw->phy_addr == 0) || (hw->phy_addr > 7)) {
5618 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
5619 hw->phy_addr);
5620 return -E1000_ERR_CONFIG3;
5621 }
5622
5623 /* Swap the data bytes for the I2C interface */
5624 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
5625
5626 /* Set up Op-code, Phy Address, and register address in the I2CCMD
5627 * register. The MAC will take care of interfacing with the
5628 * PHY to retrieve the desired data.
5629 */
5630 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) |
5631 (hw->phy_addr << E1000_I2CCMD_PHY_ADDR_SHIFT24) |
5632 E1000_I2CCMD_OPCODE_WRITE0x00000000 |
5633 phy_data_swapped);
5634
5635 E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028))), (i2ccmd)));
5636
5637 /* Poll the ready bit to see if the I2C read completed */
5638 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) {
5639 usec_delay(50)(*delay_func)(50);
5640 i2ccmd = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028)))));
5641 if (i2ccmd & E1000_I2CCMD_READY0x20000000)
5642 break;
5643 }
5644 if (!(i2ccmd & E1000_I2CCMD_READY0x20000000)) {
5645 DEBUGOUT("I2CCMD Write did not complete\n");
5646 return -E1000_ERR_PHY2;
5647 }
5648 if (i2ccmd & E1000_I2CCMD_ERROR0x80000000) {
5649 DEBUGOUT("I2CCMD Error bit set\n");
5650 return -E1000_ERR_PHY2;
5651 }
5652
5653 return E1000_SUCCESS0;
5654}
5655
5656/**
5657 * em_read_sfp_data_byte - Reads SFP module data.
5658 * @hw: pointer to the HW structure
5659 * @offset: byte location offset to be read
5660 * @data: read data buffer pointer
5661 *
5662 * Reads one byte from SFP module data stored
5663 * in SFP resided EEPROM memory or SFP diagnostic area.
5664 * Function should be called with
5665 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
5666 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
5667 * access
5668 **/
5669int32_t em_read_sfp_data_byte(struct em_hw *hw, uint16_t offset, uint8_t *data)
5670{
5671 uint32_t i = 0;
5672 uint32_t i2ccmd = 0;
5673 uint32_t data_local = 0;
5674
5675 DEBUGFUNC("em_read_sfp_data_byte");;
5676
5677 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)(0x0100 + (255))) {
5678 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
5679 return -E1000_ERR_PHY2;
5680 }
5681
5682 /* Set up Op-code, EEPROM Address,in the I2CCMD
5683 * register. The MAC will take care of interfacing with the
5684 * EEPROM to retrieve the desired data.
5685 */
5686 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT16) |
5687 E1000_I2CCMD_OPCODE_READ0x08000000);
5688
5689 E1000_WRITE_REG(hw, I2CCMD, i2ccmd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028))), (i2ccmd)));
5690
5691 /* Poll the ready bit to see if the I2C read completed */
5692 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT200; i++) {
5693 usec_delay(50)(*delay_func)(50);
5694 data_local = E1000_READ_REG(hw, I2CCMD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01028 : em_translate_82542_register
(0x01028)))));
5695 if (data_local & E1000_I2CCMD_READY0x20000000)
5696 break;
5697 }
5698 if (!(data_local & E1000_I2CCMD_READY0x20000000)) {
5699 DEBUGOUT("I2CCMD Read did not complete\n");
5700 return -E1000_ERR_PHY2;
5701 }
5702 if (data_local & E1000_I2CCMD_ERROR0x80000000) {
5703 DEBUGOUT("I2CCMD Error bit set\n");
5704 return -E1000_ERR_PHY2;
5705 }
5706 *data = (uint8_t) data_local & 0xFF;
5707
5708 return E1000_SUCCESS0;
5709}
5710
5711/******************************************************************************
5712 * Returns the PHY to the power-on reset state
5713 *
5714 * hw - Struct containing variables accessed by shared code
5715 *****************************************************************************/
5716int32_t
5717em_phy_hw_reset(struct em_hw *hw)
5718{
5719 uint32_t ctrl, ctrl_ext;
5720 uint32_t led_ctrl;
5721 int32_t ret_val;
5722 DEBUGFUNC("em_phy_hw_reset");;
5723 /*
5724 * In the case of the phy reset being blocked, it's not an error, we
5725 * simply return success without performing the reset.
5726 */
5727 ret_val = em_check_phy_reset_block(hw);
5728 if (ret_val)
5729 return E1000_SUCCESS0;
5730
5731 DEBUGOUT("Resetting Phy...\n");
5732
5733 if (hw->mac_type > em_82543 && hw->mac_type != em_icp_xxxx) {
5734 if (em_swfw_sync_acquire(hw, hw->swfw)) {
5735 DEBUGOUT("Unable to acquire swfw sync\n");
5736 return -E1000_ERR_SWFW_SYNC13;
5737 }
5738 /*
5739 * Read the device control register and assert the
5740 * E1000_CTRL_PHY_RST bit. Then, take it out of reset. For
5741 * pre-em_82571 hardware, we delay for 10ms between the
5742 * assert and deassert. For em_82571 hardware and later, we
5743 * instead delay for 50us between and 10ms after the
5744 * deassertion.
5745 */
5746 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
5747 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl | 0x80000000)));
5748 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
5749
5750 if (hw->mac_type < em_82571)
5751 msec_delay(10)(*delay_func)(1000*(10));
5752 else
5753 usec_delay(100)(*delay_func)(100);
5754
5755 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
5756 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
5757
5758 if (hw->mac_type >= em_82571)
5759 msec_delay_irq(10)(*delay_func)(1000*(10));
5760 em_swfw_sync_release(hw, hw->swfw);
5761 /*
5762 * the M88E1141_E_PHY_ID might need reset here, but nothing
5763 * proves it
5764 */
5765 } else {
5766 /*
5767 * Read the Extended Device Control Register, assert the
5768 * PHY_RESET_DIR bit to put the PHY into reset. Then, take it
5769 * out of reset.
5770 */
5771 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
5772 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR0x00000100;
5773 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA0x00000010;
5774 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
5775 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
5776 msec_delay(10)(*delay_func)(1000*(10));
5777 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA0x00000010;
5778 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
5779 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
5780 }
5781 usec_delay(150)(*delay_func)(150);
5782
5783 if ((hw->mac_type == em_82541) || (hw->mac_type == em_82547)) {
5784 /* Configure activity LED after PHY reset */
5785 led_ctrl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00)))));
5786 led_ctrl &= IGP_ACTIVITY_LED_MASK0xFFFFF0FF;
5787 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE0x0300 | IGP_LED3_MODE0x07000000);
5788 E1000_WRITE_REG(hw, LEDCTL, led_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00))), (led_ctrl)));
5789 }
5790 /* Wait for FW to finish PHY configuration. */
5791 ret_val = em_get_phy_cfg_done(hw);
5792 if (ret_val != E1000_SUCCESS0)
5793 return ret_val;
5794 em_release_software_semaphore(hw);
5795
5796 if ((hw->mac_type == em_ich8lan) && (hw->phy_type == em_phy_igp_3))
5797 ret_val = em_init_lcd_from_nvm(hw);
5798
5799 return ret_val;
5800}
5801
5802/*****************************************************************************
5803 * SW-based LCD Configuration.
5804 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
5805 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
5806 * in NVM determines whether HW should configure LPLU and Gbe Disable.
5807 *****************************************************************************/
5808int32_t
5809em_oem_bits_config_pchlan(struct em_hw *hw, boolean_t d0_state)
5810{
5811 int32_t ret_val = E1000_SUCCESS0;
5812 uint32_t mac_reg;
5813 uint16_t oem_reg;
5814 uint16_t swfw = E1000_SWFW_PHY0_SM0x0002;
5815
5816 if (hw->mac_type < em_pchlan)
5817 return ret_val;
5818
5819 ret_val = em_swfw_sync_acquire(hw, swfw);
5820 if (ret_val)
5821 return ret_val;
5822
5823 if (hw->mac_type == em_pchlan) {
5824 mac_reg = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
5825 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE0x00000008)
5826 goto out;
5827 }
5828
5829 mac_reg = E1000_READ_REG(hw, FEXTNVM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00028 : em_translate_82542_register
(0x00028)))));
5830 if (!(mac_reg & FEXTNVM_SW_CONFIG_ICH8M(1 << 27)))
5831 goto out;
5832
5833 mac_reg = E1000_READ_REG(hw, PHY_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10)))));
5834
5835 ret_val = em_read_phy_reg(hw, HV_OEM_BITS(((768) << 5) | ((25) & 0x1F)), &oem_reg);
5836 if (ret_val)
5837 goto out;
5838
5839 oem_reg &= ~(HV_OEM_BITS_GBE_DIS0x0040 | HV_OEM_BITS_LPLU0x0004);
5840
5841 if (d0_state) {
5842 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE0x00000040)
5843 oem_reg |= HV_OEM_BITS_GBE_DIS0x0040;
5844
5845 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU0x00000002)
5846 oem_reg |= HV_OEM_BITS_LPLU0x0004;
5847 /* Restart auto-neg to activate the bits */
5848 if (!em_check_phy_reset_block(hw))
5849 oem_reg |= HV_OEM_BITS_RESTART_AN0x0400;
5850
5851 } else {
5852 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE0x00000040 |
5853 E1000_PHY_CTRL_NOND0A_GBE_DISABLE0x00000008))
5854 oem_reg |= HV_OEM_BITS_GBE_DIS0x0040;
5855
5856 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU0x00000002 |
5857 E1000_PHY_CTRL_NOND0A_LPLU0x00000004))
5858 oem_reg |= HV_OEM_BITS_LPLU0x0004;
5859 }
5860
5861 ret_val = em_write_phy_reg(hw, HV_OEM_BITS(((768) << 5) | ((25) & 0x1F)), oem_reg);
5862
5863out:
5864 em_swfw_sync_release(hw, swfw);
5865
5866 return ret_val;
5867}
5868
5869
5870/******************************************************************************
5871 * Resets the PHY
5872 *
5873 * hw - Struct containing variables accessed by shared code
5874 *
5875 * Sets bit 15 of the MII Control register
5876 *****************************************************************************/
5877int32_t
5878em_phy_reset(struct em_hw *hw)
5879{
5880 int32_t ret_val;
5881 uint16_t phy_data;
5882 DEBUGFUNC("em_phy_reset");;
5883 /*
5884 * In the case of the phy reset being blocked, it's not an error, we
5885 * simply return success without performing the reset.
5886 */
5887 ret_val = em_check_phy_reset_block(hw);
149
←
Calling 'em_check_phy_reset_block'
→
164
←
Returning from 'em_check_phy_reset_block'
→
5888 if (ret_val
164.1
'ret_val' is 0
)
165
←
Taking false branch
→
5889 return E1000_SUCCESS0;
5890
5891 switch (hw->phy_type) {
166
←
Control jumps to the 'default' case at line 5900
→
5892 case em_phy_igp:
5893 case em_phy_igp_2:
5894 case em_phy_igp_3:
5895 case em_phy_ife:
5896 ret_val = em_phy_hw_reset(hw);
5897 if (ret_val)
5898 return ret_val;
5899 break;
5900 default:
5901 ret_val = em_read_phy_reg(hw, PHY_CTRL0x00, &phy_data);
5902 if (ret_val
166.1
'ret_val' is 0
)
167
←
Taking false branch
→
5903 return ret_val;
5904
5905 phy_data |= MII_CR_RESET0x8000;
5906 ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, phy_data);
5907 if (ret_val
167.1
'ret_val' is 0
)
168
←
Taking false branch
→
5908 return ret_val;
5909
5910 usec_delay(1)(*delay_func)(1);
5911 break;
169
←
 Execution continues on line 5915
→
5912 }
5913
5914 /* Allow time for h/w to get to a quiescent state after reset */
5915 msec_delay(10)(*delay_func)(1000*(10));
5916
5917 if (hw->phy_type == em_phy_igp || hw->phy_type == em_phy_igp_2)
170
←
Assuming field 'phy_type' is equal to em_phy_igp
→
5918 em_phy_init_script(hw);
171
←
Calling 'em_phy_init_script'
→
5919
5920 if (hw->mac_type == em_pchlan) {
5921 ret_val = em_hv_phy_workarounds_ich8lan(hw);
5922 if (ret_val)
5923 return ret_val;
5924 } else if (hw->mac_type == em_pch2lan) {
5925 ret_val = em_lv_phy_workarounds_ich8lan(hw);
5926 if (ret_val)
5927 return ret_val;
5928 }
5929
5930 if (hw->mac_type >= em_pchlan) {
5931 ret_val = em_oem_bits_config_pchlan(hw, TRUE1);
5932 if (ret_val)
5933 return ret_val;
5934 }
5935
5936 /* Ungate automatic PHY configuration on non-managed 82579 */
5937 if ((hw->mac_type == em_pch2lan) &&
5938 !(E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54))))) & E1000_FWSM_FW_VALID0x00008000)) {
5939 msec_delay(10)(*delay_func)(1000*(10));
5940 em_gate_hw_phy_config_ich8lan(hw, FALSE0);
5941 }
5942
5943 if (hw->phy_id == M88E1512_E_PHY_ID0x01410DD0) {
5944 ret_val = em_initialize_M88E1512_phy(hw);
5945 if (ret_val)
5946 return ret_val;
5947 }
5948
5949 return E1000_SUCCESS0;
5950}
5951
5952/******************************************************************************
5953 * Work-around for 82566 Kumeran PCS lock loss:
5954 * On link status change (i.e. PCI reset, speed change) and link is up and
5955 * speed is gigabit-
5956 * 0) if workaround is optionally disabled do nothing
5957 * 1) wait 1ms for Kumeran link to come up
5958 * 2) check Kumeran Diagnostic register PCS lock loss bit
5959 * 3) if not set the link is locked (all is good), otherwise...
5960 * 4) reset the PHY
5961 * 5) repeat up to 10 times
5962 * Note: this is only called for IGP3 copper when speed is 1gb.
5963 *
5964 * hw - struct containing variables accessed by shared code
5965 *****************************************************************************/
5966STATIC int32_t
5967em_kumeran_lock_loss_workaround(struct em_hw *hw)
5968{
5969 int32_t ret_val;
5970 int32_t reg;
5971 int32_t cnt;
5972 uint16_t phy_data;
5973 if (hw->kmrn_lock_loss_workaround_disabled)
5974 return E1000_SUCCESS0;
5975 /*
5976 * Make sure link is up before proceeding. If not just return.
5977 * Attempting this while link is negotiating fouled up link stability
5978 */
5979 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
5980 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &phy_data);
5981
5982 if (phy_data & MII_SR_LINK_STATUS0x0004) {
5983 for (cnt = 0; cnt < 10; cnt++) {
5984 /* read once to clear */
5985 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG(((770) << 5) | ((19) & 0x1F)),
5986 &phy_data);
5987 if (ret_val)
5988 return ret_val;
5989 /* and again to get new status */
5990 ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG(((770) << 5) | ((19) & 0x1F)), &phy_data);
5991 if (ret_val)
5992 return ret_val;
5993
5994 /* check for PCS lock */
5995 if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS0x0002))
5996 return E1000_SUCCESS0;
5997
5998 /* Issue PHY reset */
5999 em_phy_hw_reset(hw);
6000 msec_delay_irq(5)(*delay_func)(1000*(5));
6001 }
6002 /* Disable GigE link negotiation */
6003 reg = E1000_READ_REG(hw, PHY_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10)))));
6004 E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10))), (reg | 0x00000040 | 0x00000008)))
6005 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10))), (reg | 0x00000040 | 0x00000008)));
6006
6007 /* unable to acquire PCS lock */
6008 return E1000_ERR_PHY2;
6009 }
6010 return E1000_SUCCESS0;
6011}
6012
6013/******************************************************************************
6014 * Reads and matches the expected PHY address for known PHY IDs
6015 *
6016 * hw - Struct containing variables accessed by shared code
6017 *****************************************************************************/
6018STATIC int32_t
6019em_match_gig_phy(struct em_hw *hw)
6020{
6021 int32_t phy_init_status, ret_val;
6022 uint16_t phy_id_high, phy_id_low;
6023 boolean_t match = FALSE0;
6024 DEBUGFUNC("em_match_gig_phy");;
6025
6026 ret_val = em_read_phy_reg(hw, PHY_ID10x02, &phy_id_high);
6027 if (ret_val)
6028 return ret_val;
6029
6030 hw->phy_id = (uint32_t) (phy_id_high << 16);
6031 usec_delay(20)(*delay_func)(20);
6032 ret_val = em_read_phy_reg(hw, PHY_ID20x03, &phy_id_low);
6033 if (ret_val)
6034 return ret_val;
6035
6036 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK0xFFFFFFF0);
6037 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK0xFFFFFFF0;
6038
6039 switch (hw->mac_type) {
6040 case em_82543:
6041 if (hw->phy_id == M88E1000_E_PHY_ID0x01410C50)
6042 match = TRUE1;
6043 break;
6044 case em_82544:
6045 if (hw->phy_id == M88E1000_I_PHY_ID0x01410C30)
6046 match = TRUE1;
6047 break;
6048 case em_82540:
6049 case em_82545:
6050 case em_82545_rev_3:
6051 case em_82546:
6052 case em_82546_rev_3:
6053 if (hw->phy_id == M88E1011_I_PHY_ID0x01410C20)
6054 match = TRUE1;
6055 break;
6056 case em_82541:
6057 case em_82541_rev_2:
6058 case em_82547:
6059 case em_82547_rev_2:
6060 if (hw->phy_id == IGP01E1000_I_PHY_ID0x02A80380)
6061 match = TRUE1;
6062 break;
6063 case em_82573:
6064 if (hw->phy_id == M88E1111_I_PHY_ID0x01410CC0)
6065 match = TRUE1;
6066 break;
6067 case em_82574:
6068 if (hw->phy_id == BME1000_E_PHY_ID0x01410CB0)
6069 match = TRUE1;
6070 break;
6071 case em_82575:
6072 case em_82576:
6073 if (hw->phy_id == M88E1000_E_PHY_ID0x01410C50)
6074 match = TRUE1;
6075 if (hw->phy_id == IGP01E1000_I_PHY_ID0x02A80380)
6076 match = TRUE1;
6077 if (hw->phy_id == IGP03E1000_E_PHY_ID0x02A80390)
6078 match = TRUE1;
6079 break;
6080 case em_82580:
6081 case em_i210:
6082 case em_i350:
6083 if (hw->phy_id == I82580_I_PHY_ID0x015403A0 ||
6084 hw->phy_id == I210_I_PHY_ID0x01410C00 ||
6085 hw->phy_id == I347AT4_E_PHY_ID0x01410DC0 ||
6086 hw->phy_id == I350_I_PHY_ID0x015403B0 ||
6087 hw->phy_id == M88E1111_I_PHY_ID0x01410CC0 ||
6088 hw->phy_id == M88E1112_E_PHY_ID0x01410C90 ||
6089 hw->phy_id == M88E1543_E_PHY_ID0x01410EA0 ||
6090 hw->phy_id == M88E1512_E_PHY_ID0x01410DD0) {
6091 uint32_t mdic;
6092
6093 mdic = EM_READ_REG(hw, E1000_MDICNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00E04)));
6094 if (mdic & E1000_MDICNFG_EXT_MDIO0x80000000) {
6095 mdic &= E1000_MDICNFG_PHY_MASK0x03E00000;
6096 hw->phy_addr = mdic >> E1000_MDICNFG_PHY_SHIFT21;
6097 DEBUGOUT1("MDICNFG PHY ADDR %d",
6098 mdic >> E1000_MDICNFG_PHY_SHIFT);
6099 }
6100 match = TRUE1;
6101 }
6102 break;
6103 case em_80003es2lan:
6104 if (hw->phy_id == GG82563_E_PHY_ID0x01410CA0)
6105 match = TRUE1;
6106 break;
6107 case em_ich8lan:
6108 case em_ich9lan:
6109 case em_ich10lan:
6110 case em_pchlan:
6111 case em_pch2lan:
6112 if (hw->phy_id == IGP03E1000_E_PHY_ID0x02A80390)
6113 match = TRUE1;
6114 if (hw->phy_id == IFE_E_PHY_ID0x02A80330)
6115 match = TRUE1;
6116 if (hw->phy_id == IFE_PLUS_E_PHY_ID0x02A80320)
6117 match = TRUE1;
6118 if (hw->phy_id == IFE_C_E_PHY_ID0x02A80310)
6119 match = TRUE1;
6120 if (hw->phy_id == BME1000_E_PHY_ID0x01410CB0)
6121 match = TRUE1;
6122 if (hw->phy_id == I82577_E_PHY_ID0x01540050)
6123 match = TRUE1;
6124 if (hw->phy_id == I82578_E_PHY_ID0x004DD040)
6125 match = TRUE1;
6126 if (hw->phy_id == I82579_E_PHY_ID0x01540090)
6127 match = TRUE1;
6128 break;
6129 case em_pch_lpt:
6130 case em_pch_spt:
6131 case em_pch_cnp:
6132 case em_pch_tgp:
6133 case em_pch_adp:
6134 if (hw->phy_id == I217_E_PHY_ID0x015400A0)
6135 match = TRUE1;
6136 break;
6137 case em_icp_xxxx:
6138 if (hw->phy_id == M88E1141_E_PHY_ID0x01410CD0)
6139 match = TRUE1;
6140 if (hw->phy_id == RTL8211_E_PHY_ID0x001CC912)
6141 match = TRUE1;
6142 break;
6143 default:
6144 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
6145 return -E1000_ERR_CONFIG3;
6146 }
6147 phy_init_status = em_set_phy_type(hw);
6148
6149 if ((match) && (phy_init_status == E1000_SUCCESS0)) {
6150 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
6151 return E1000_SUCCESS0;
6152 }
6153 DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
6154 return -E1000_ERR_PHY2;
6155}
6156
6157/******************************************************************************
6158 * Probes the expected PHY address for known PHY IDs
6159 *
6160 * hw - Struct containing variables accessed by shared code
6161 *****************************************************************************/
6162STATIC int32_t
6163em_detect_gig_phy(struct em_hw *hw)
6164{
6165 int32_t ret_val, i;
6166 DEBUGFUNC("em_detect_gig_phy");;
6167
6168 if (hw->phy_id != 0)
6169 return E1000_SUCCESS0;
6170
6171 /* default phy address, most phys reside here, but not all (ICH10) */
6172 if (hw->mac_type != em_icp_xxxx)
6173 hw->phy_addr = 1;
6174 else
6175 hw->phy_addr = 0; /* There is a phy at phy_addr 0 on EP80579 */
6176
6177 /*
6178 * The 82571 firmware may still be configuring the PHY. In this
6179 * case, we cannot access the PHY until the configuration is done.
6180 * So we explicitly set the PHY values.
6181 */
6182 if (hw->mac_type == em_82571 ||
6183 hw->mac_type == em_82572) {
6184 hw->phy_id = IGP01E1000_I_PHY_ID0x02A80380;
6185 hw->phy_type = em_phy_igp_2;
6186 return E1000_SUCCESS0;
6187 }
6188
6189 /*
6190 * Some of the fiber cards dont have a phy, so we must exit cleanly
6191 * here
6192 */
6193 if ((hw->media_type == em_media_type_fiber) &&
6194 (hw->mac_type == em_82542_rev2_0 ||
6195 hw->mac_type == em_82542_rev2_1 ||
6196 hw->mac_type == em_82543 ||
6197 hw->mac_type == em_82573 ||
6198 hw->mac_type == em_82574 ||
6199 hw->mac_type == em_80003es2lan)) {
6200 hw->phy_type = em_phy_undefined;
6201 return E1000_SUCCESS0;
6202 }
6203
6204 if ((hw->media_type == em_media_type_internal_serdes ||
6205 hw->media_type == em_media_type_fiber) &&
6206 hw->mac_type >= em_82575) {
6207 hw->phy_type = em_phy_undefined;
6208 return E1000_SUCCESS0;
6209 }
6210
6211 /*
6212 * Up to 82543 (incl), we need reset the phy, or it might not get
6213 * detected
6214 */
6215 if (hw->mac_type <= em_82543) {
6216 ret_val = em_phy_hw_reset(hw);
6217 if (ret_val)
6218 return ret_val;
6219 }
6220 /*
6221 * ESB-2 PHY reads require em_phy_gg82563 to be set because of a
6222 * work- around that forces PHY page 0 to be set or the reads fail.
6223 * The rest of the code in this routine uses em_read_phy_reg to read
6224 * the PHY ID. So for ESB-2 we need to have this set so our reads
6225 * won't fail. If the attached PHY is not a em_phy_gg82563, the
6226 * routines below will figure this out as well.
6227 */
6228 if (hw->mac_type == em_80003es2lan)
6229 hw->phy_type = em_phy_gg82563;
6230
6231 /* Power on SGMII phy if it is disabled */
6232 if (hw->mac_type == em_82580 || hw->mac_type == em_i210 ||
6233 hw->mac_type == em_i350) {
6234 uint32_t ctrl_ext = EM_READ_REG(hw, E1000_CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00018)));
6235 EM_WRITE_REG(hw, E1000_CTRL_EXT,((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00018), (ctrl_ext & ~0x00000080)))
6236 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x00018), (ctrl_ext & ~0x00000080)));
6237 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6238 msec_delay(300)(*delay_func)(1000*(300));
6239 }
6240
6241 /* Read the PHY ID Registers to identify which PHY is onboard. */
6242 for (i = 1; i < 8; i++) {
6243 /*
6244 * hw->phy_addr may be modified down in the call stack,
6245 * we can't use it as loop variable.
6246 */
6247 hw->phy_addr = i;
6248 ret_val = em_match_gig_phy(hw);
6249 if (ret_val == E1000_SUCCESS0)
6250 return E1000_SUCCESS0;
6251 }
6252 return -E1000_ERR_PHY2;
6253}
6254
6255/******************************************************************************
6256 * Resets the PHY's DSP
6257 *
6258 * hw - Struct containing variables accessed by shared code
6259 *****************************************************************************/
6260static int32_t
6261em_phy_reset_dsp(struct em_hw *hw)
6262{
6263 int32_t ret_val;
6264 DEBUGFUNC("em_phy_reset_dsp");;
6265
6266 do {
6267 if (hw->phy_type != em_phy_gg82563) {
6268 ret_val = em_write_phy_reg(hw, 29, 0x001d);
6269 if (ret_val)
6270 break;
6271 }
6272 ret_val = em_write_phy_reg(hw, 30, 0x00c1);
6273 if (ret_val)
6274 break;
6275 ret_val = em_write_phy_reg(hw, 30, 0x0000);
6276 if (ret_val)
6277 break;
6278 ret_val = E1000_SUCCESS0;
6279 } while (0);
6280
6281 return ret_val;
6282}
6283
6284/******************************************************************************
6285 * Sets up eeprom variables in the hw struct. Must be called after mac_type
6286 * is configured. Additionally, if this is ICH8, the flash controller GbE
6287 * registers must be mapped, or this will crash.
6288 *
6289 * hw - Struct containing variables accessed by shared code
6290 *****************************************************************************/
6291int32_t
6292em_init_eeprom_params(struct em_hw *hw)
6293{
6294 struct em_eeprom_info *eeprom = &hw->eeprom;
6295 uint32_t eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6296 int32_t ret_val = E1000_SUCCESS0;
6297 uint16_t eeprom_size;
6298 DEBUGFUNC("em_init_eeprom_params");;
6299
6300 switch (hw->mac_type) {
6301 case em_82542_rev2_0:
6302 case em_82542_rev2_1:
6303 case em_82543:
6304 case em_82544:
6305 eeprom->type = em_eeprom_microwire;
6306 eeprom->word_size = 64;
6307 eeprom->opcode_bits = 3;
6308 eeprom->address_bits = 6;
6309 eeprom->delay_usec = 50;
6310 eeprom->use_eerd = FALSE0;
6311 eeprom->use_eewr = FALSE0;
6312 break;
6313 case em_82540:
6314 case em_82545:
6315 case em_82545_rev_3:
6316 case em_icp_xxxx:
6317 case em_82546:
6318 case em_82546_rev_3:
6319 eeprom->type = em_eeprom_microwire;
6320 eeprom->opcode_bits = 3;
6321 eeprom->delay_usec = 50;
6322 if (eecd & E1000_EECD_SIZE0x00000200) {
6323 eeprom->word_size = 256;
6324 eeprom->address_bits = 8;
6325 } else {
6326 eeprom->word_size = 64;
6327 eeprom->address_bits = 6;
6328 }
6329 eeprom->use_eerd = FALSE0;
6330 eeprom->use_eewr = FALSE0;
6331 break;
6332 case em_82541:
6333 case em_82541_rev_2:
6334 case em_82547:
6335 case em_82547_rev_2:
6336 if (eecd & E1000_EECD_TYPE0x00002000) {
6337 eeprom->type = em_eeprom_spi;
6338 eeprom->opcode_bits = 8;
6339 eeprom->delay_usec = 1;
6340 if (eecd & E1000_EECD_ADDR_BITS0x00000400) {
6341 eeprom->page_size = 32;
6342 eeprom->address_bits = 16;
6343 } else {
6344 eeprom->page_size = 8;
6345 eeprom->address_bits = 8;
6346 }
6347 } else {
6348 eeprom->type = em_eeprom_microwire;
6349 eeprom->opcode_bits = 3;
6350 eeprom->delay_usec = 50;
6351 if (eecd & E1000_EECD_ADDR_BITS0x00000400) {
6352 eeprom->word_size = 256;
6353 eeprom->address_bits = 8;
6354 } else {
6355 eeprom->word_size = 64;
6356 eeprom->address_bits = 6;
6357 }
6358 }
6359 eeprom->use_eerd = FALSE0;
6360 eeprom->use_eewr = FALSE0;
6361 break;
6362 case em_82571:
6363 case em_82572:
6364 eeprom->type = em_eeprom_spi;
6365 eeprom->opcode_bits = 8;
6366 eeprom->delay_usec = 1;
6367 if (eecd & E1000_EECD_ADDR_BITS0x00000400) {
6368 eeprom->page_size = 32;
6369 eeprom->address_bits = 16;
6370 } else {
6371 eeprom->page_size = 8;
6372 eeprom->address_bits = 8;
6373 }
6374 eeprom->use_eerd = FALSE0;
6375 eeprom->use_eewr = FALSE0;
6376 break;
6377 case em_82573:
6378 case em_82574:
6379 case em_82575:
6380 case em_82576:
6381 case em_82580:
6382 case em_i210:
6383 case em_i350:
6384 eeprom->type = em_eeprom_spi;
6385 eeprom->opcode_bits = 8;
6386 eeprom->delay_usec = 1;
6387 if (eecd & E1000_EECD_ADDR_BITS0x00000400) {
6388 eeprom->page_size = 32;
6389 eeprom->address_bits = 16;
6390 } else {
6391 eeprom->page_size = 8;
6392 eeprom->address_bits = 8;
6393 }
6394 eeprom->use_eerd = TRUE1;
6395 eeprom->use_eewr = TRUE1;
6396 if (em_is_onboard_nvm_eeprom(hw) == FALSE0) {
6397 eeprom->type = em_eeprom_flash;
6398 eeprom->word_size = 2048;
6399 /*
6400 * Ensure that the Autonomous FLASH update bit is
6401 * cleared due to Flash update issue on parts which
6402 * use a FLASH for NVM.
6403 */
6404 eecd &= ~E1000_EECD_AUPDEN0x00100000;
6405 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6406 }
6407 if (em_get_flash_presence_i210(hw) == FALSE0) {
6408 eeprom->type = em_eeprom_invm;
6409 eeprom->word_size = INVM_SIZE64;
6410 eeprom->use_eerd = FALSE0;
6411 eeprom->use_eewr = FALSE0;
6412 }
6413 break;
6414 case em_80003es2lan:
6415 eeprom->type = em_eeprom_spi;
6416 eeprom->opcode_bits = 8;
6417 eeprom->delay_usec = 1;
6418 if (eecd & E1000_EECD_ADDR_BITS0x00000400) {
6419 eeprom->page_size = 32;
6420 eeprom->address_bits = 16;
6421 } else {
6422 eeprom->page_size = 8;
6423 eeprom->address_bits = 8;
6424 }
6425 eeprom->use_eerd = TRUE1;
6426 eeprom->use_eewr = FALSE0;
6427 break;
6428 case em_ich8lan:
6429 case em_ich9lan:
6430 case em_ich10lan:
6431 case em_pchlan:
6432 case em_pch2lan:
6433 case em_pch_lpt:
6434 {
6435 int32_t i = 0;
6436 uint32_t flash_size =
6437 E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0000
)));
6438 eeprom->type = em_eeprom_ich8;
6439 eeprom->use_eerd = FALSE0;
6440 eeprom->use_eewr = FALSE0;
6441 eeprom->word_size = E1000_SHADOW_RAM_WORDS2048;
6442 /*
6443 * Zero the shadow RAM structure. But don't load it
6444 * from NVM so as to save time for driver init
6445 */
6446 if (hw->eeprom_shadow_ram != NULL((void *)0)) {
6447 for (i = 0; i < E1000_SHADOW_RAM_WORDS2048; i++) {
6448 hw->eeprom_shadow_ram[i].modified =
6449 FALSE0;
6450 hw->eeprom_shadow_ram[i].eeprom_word =
6451 0xFFFF;
6452 }
6453 }
6454 hw->flash_base_addr = (flash_size &
6455 ICH_GFPREG_BASE_MASK0x1FFF) * ICH_FLASH_SECTOR_SIZE4096;
6456
6457 hw->flash_bank_size = ((flash_size >> 16) &
6458 ICH_GFPREG_BASE_MASK0x1FFF) + 1;
6459 hw->flash_bank_size -= (flash_size &
6460 ICH_GFPREG_BASE_MASK0x1FFF);
6461
6462 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE4096;
6463
6464 hw->flash_bank_size /= 2 * sizeof(uint16_t);
6465
6466 break;
6467 }
6468 case em_pch_spt:
6469 case em_pch_cnp:
6470 case em_pch_tgp:
6471 case em_pch_adp:
6472 {
6473 int32_t i = 0;
6474 uint32_t flash_size = EM_READ_REG(hw, 0xc /* STRAP */)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0xc)));
6475
6476 eeprom->type = em_eeprom_ich8;
6477 eeprom->use_eerd = FALSE0;
6478 eeprom->use_eewr = FALSE0;
6479 eeprom->word_size = E1000_SHADOW_RAM_WORDS2048;
6480 /*
6481 * Zero the shadow RAM structure. But don't load it
6482 * from NVM so as to save time for driver init
6483 */
6484 if (hw->eeprom_shadow_ram != NULL((void *)0)) {
6485 for (i = 0; i < E1000_SHADOW_RAM_WORDS2048; i++) {
6486 hw->eeprom_shadow_ram[i].modified =
6487 FALSE0;
6488 hw->eeprom_shadow_ram[i].eeprom_word =
6489 0xFFFF;
6490 }
6491 }
6492 hw->flash_base_addr = 0;
6493 flash_size = ((flash_size >> 1) & 0x1f) + 1;
6494 flash_size *= 4096;
6495 hw->flash_bank_size = flash_size / 4;
6496 }
6497 break;
6498 default:
6499 break;
6500 }
6501
6502 if (eeprom->type == em_eeprom_spi) {
6503 /*
6504 * eeprom_size will be an enum [0..8] that maps to eeprom
6505 * sizes 128B to 32KB (incremented by powers of 2).
6506 */
6507 if (hw->mac_type <= em_82547_rev_2) {
6508 /* Set to default value for initial eeprom read. */
6509 eeprom->word_size = 64;
6510 ret_val = em_read_eeprom(hw, EEPROM_CFG0x0012, 1,
6511 &eeprom_size);
6512 if (ret_val)
6513 return ret_val;
6514 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK0x1C00) >>
6515 EEPROM_SIZE_SHIFT10;
6516 /*
6517 * 256B eeprom size was not supported in earlier
6518 * hardware, so we bump eeprom_size up one to ensure
6519 * that "1" (which maps to 256B) is never the result
6520 * used in the shifting logic below.
6521 */
6522 if (eeprom_size)
6523 eeprom_size++;
6524 } else {
6525 eeprom_size = (uint16_t) (
6526 (eecd & E1000_EECD_SIZE_EX_MASK0x00007800) >>
6527 E1000_EECD_SIZE_EX_SHIFT11);
6528 }
6529
6530 /* EEPROM access above 16k is unsupported */
6531 if (eeprom_size + EEPROM_WORD_SIZE_SHIFT6 >
6532 EEPROM_WORD_SIZE_SHIFT_MAX14) {
6533 eeprom->word_size = 1 << EEPROM_WORD_SIZE_SHIFT_MAX14;
6534 } else {
6535 eeprom->word_size = 1 <<
6536 (eeprom_size + EEPROM_WORD_SIZE_SHIFT6);
6537 }
6538 }
6539 return ret_val;
6540}
6541
6542/******************************************************************************
6543 * Raises the EEPROM's clock input.
6544 *
6545 * hw - Struct containing variables accessed by shared code
6546 * eecd - EECD's current value
6547 *****************************************************************************/
6548static void
6549em_raise_ee_clk(struct em_hw *hw, uint32_t *eecd)
6550{
6551 /*
6552 * Raise the clock input to the EEPROM (by setting the SK bit), and
6553 * then wait <delay> microseconds.
6554 */
6555 *eecd = *eecd | E1000_EECD_SK0x00000001;
6556 E1000_WRITE_REG(hw, EECD, *eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (*eecd)));
6557 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6558 usec_delay(hw->eeprom.delay_usec)(*delay_func)(hw->eeprom.delay_usec);
6559}
6560
6561/******************************************************************************
6562 * Lowers the EEPROM's clock input.
6563 *
6564 * hw - Struct containing variables accessed by shared code
6565 * eecd - EECD's current value
6566 *****************************************************************************/
6567static void
6568em_lower_ee_clk(struct em_hw *hw, uint32_t *eecd)
6569{
6570 /*
6571 * Lower the clock input to the EEPROM (by clearing the SK bit), and
6572 * then wait 50 microseconds.
6573 */
6574 *eecd = *eecd & ~E1000_EECD_SK0x00000001;
6575 E1000_WRITE_REG(hw, EECD, *eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (*eecd)));
6576 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6577 usec_delay(hw->eeprom.delay_usec)(*delay_func)(hw->eeprom.delay_usec);
6578}
6579
6580/******************************************************************************
6581 * Shift data bits out to the EEPROM.
6582 *
6583 * hw - Struct containing variables accessed by shared code
6584 * data - data to send to the EEPROM
6585 * count - number of bits to shift out
6586 *****************************************************************************/
6587static void
6588em_shift_out_ee_bits(struct em_hw *hw, uint16_t data, uint16_t count)
6589{
6590 struct em_eeprom_info *eeprom = &hw->eeprom;
6591 uint32_t eecd;
6592 uint32_t mask;
6593 /*
6594 * We need to shift "count" bits out to the EEPROM. So, value in the
6595 * "data" parameter will be shifted out to the EEPROM one bit at a
6596 * time. In order to do this, "data" must be broken down into bits.
6597 */
6598 mask = 0x01 << (count - 1);
6599 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6600 if (eeprom->type == em_eeprom_microwire) {
6601 eecd &= ~E1000_EECD_DO0x00000008;
6602 } else if (eeprom->type == em_eeprom_spi) {
6603 eecd |= E1000_EECD_DO0x00000008;
6604 }
6605 do {
6606 /*
6607 * A "1" is shifted out to the EEPROM by setting bit "DI" to
6608 * a "1", and then raising and then lowering the clock (the
6609 * SK bit controls the clock input to the EEPROM). A "0" is
6610 * shifted out to the EEPROM by setting "DI" to "0" and then
6611 * raising and then lowering the clock.
6612 */
6613 eecd &= ~E1000_EECD_DI0x00000004;
6614
6615 if (data & mask)
6616 eecd |= E1000_EECD_DI0x00000004;
6617
6618 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6619 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6620
6621 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6622
6623 em_raise_ee_clk(hw, &eecd);
6624 em_lower_ee_clk(hw, &eecd);
6625
6626 mask = mask >> 1;
6627
6628 } while (mask);
6629
6630 /* We leave the "DI" bit set to "0" when we leave this routine. */
6631 eecd &= ~E1000_EECD_DI0x00000004;
6632 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6633}
6634
6635/******************************************************************************
6636 * Shift data bits in from the EEPROM
6637 *
6638 * hw - Struct containing variables accessed by shared code
6639 *****************************************************************************/
6640static uint16_t
6641em_shift_in_ee_bits(struct em_hw *hw, uint16_t count)
6642{
6643 uint32_t eecd;
6644 uint32_t i;
6645 uint16_t data;
6646 /*
6647 * In order to read a register from the EEPROM, we need to shift
6648 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
6649 * the clock input to the EEPROM (setting the SK bit), and then
6650 * reading the value of the "DO" bit. During this "shifting in"
6651 * process the "DI" bit should always be clear.
6652 */
6653
6654 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6655
6656 eecd &= ~(E1000_EECD_DO0x00000008 | E1000_EECD_DI0x00000004);
6657 data = 0;
6658
6659 for (i = 0; i < count; i++) {
6660 data = data << 1;
6661 em_raise_ee_clk(hw, &eecd);
6662
6663 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6664
6665 eecd &= ~(E1000_EECD_DI0x00000004);
6666 if (eecd & E1000_EECD_DO0x00000008)
6667 data |= 1;
6668
6669 em_lower_ee_clk(hw, &eecd);
6670 }
6671
6672 return data;
6673}
6674/******************************************************************************
6675 * Prepares EEPROM for access
6676 *
6677 * hw - Struct containing variables accessed by shared code
6678 *
6679 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
6680 * function should be called before issuing a command to the EEPROM.
6681 *****************************************************************************/
6682static int32_t
6683em_acquire_eeprom(struct em_hw *hw)
6684{
6685 struct em_eeprom_info *eeprom = &hw->eeprom;
6686 uint32_t eecd, i = 0;
6687 DEBUGFUNC("em_acquire_eeprom");;
6688
6689 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM0x0001))
6690 return -E1000_ERR_SWFW_SYNC13;
6691 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6692
6693 if ((hw->mac_type != em_82573) && (hw->mac_type != em_82574)) {
6694 /* Request EEPROM Access */
6695 if (hw->mac_type > em_82544) {
6696 eecd |= E1000_EECD_REQ0x00000040;
6697 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6698 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6699 while ((!(eecd & E1000_EECD_GNT0x00000080)) &&
6700 (i < E1000_EEPROM_GRANT_ATTEMPTS1000)) {
6701 i++;
6702 usec_delay(5)(*delay_func)(5);
6703 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6704 }
6705 if (!(eecd & E1000_EECD_GNT0x00000080)) {
6706 eecd &= ~E1000_EECD_REQ0x00000040;
6707 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6708 DEBUGOUT("Could not acquire EEPROM grant\n");
6709 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM0x0001);
6710 return -E1000_ERR_EEPROM1;
6711 }
6712 }
6713 }
6714
6715 /* Setup EEPROM for Read/Write */
6716 if (eeprom->type == em_eeprom_microwire) {
6717 /* Clear SK and DI */
6718 eecd &= ~(E1000_EECD_DI0x00000004 | E1000_EECD_SK0x00000001);
6719 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6720
6721 /* Set CS */
6722 eecd |= E1000_EECD_CS0x00000002;
6723 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6724 } else if (eeprom->type == em_eeprom_spi) {
6725 /* Clear SK and CS */
6726 eecd &= ~(E1000_EECD_CS0x00000002 | E1000_EECD_SK0x00000001);
6727 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6728 usec_delay(1)(*delay_func)(1);
6729 }
6730 return E1000_SUCCESS0;
6731}
6732
6733/******************************************************************************
6734 * Returns EEPROM to a "standby" state
6735 *
6736 * hw - Struct containing variables accessed by shared code
6737 *****************************************************************************/
6738static void
6739em_standby_eeprom(struct em_hw *hw)
6740{
6741 struct em_eeprom_info *eeprom = &hw->eeprom;
6742 uint32_t eecd;
6743 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6744
6745 if (eeprom->type == em_eeprom_microwire) {
6746 eecd &= ~(E1000_EECD_CS0x00000002 | E1000_EECD_SK0x00000001);
6747 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6748 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6749 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6750
6751 /* Clock high */
6752 eecd |= E1000_EECD_SK0x00000001;
6753 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6754 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6755 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6756
6757 /* Select EEPROM */
6758 eecd |= E1000_EECD_CS0x00000002;
6759 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6760 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6761 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6762
6763 /* Clock low */
6764 eecd &= ~E1000_EECD_SK0x00000001;
6765 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6766 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6767 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6768 } else if (eeprom->type == em_eeprom_spi) {
6769 /* Toggle CS to flush commands */
6770 eecd |= E1000_EECD_CS0x00000002;
6771 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6772 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6773 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6774 eecd &= ~E1000_EECD_CS0x00000002;
6775 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6776 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6777 usec_delay(eeprom->delay_usec)(*delay_func)(eeprom->delay_usec);
6778 }
6779}
6780
6781/******************************************************************************
6782 * Terminates a command by inverting the EEPROM's chip select pin
6783 *
6784 * hw - Struct containing variables accessed by shared code
6785 *****************************************************************************/
6786static void
6787em_release_eeprom(struct em_hw *hw)
6788{
6789 uint32_t eecd;
6790 DEBUGFUNC("em_release_eeprom");;
6791
6792 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
6793
6794 if (hw->eeprom.type == em_eeprom_spi) {
6795 eecd |= E1000_EECD_CS0x00000002; /* Pull CS high */
6796 eecd &= ~E1000_EECD_SK0x00000001; /* Lower SCK */
6797
6798 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6799
6800 usec_delay(hw->eeprom.delay_usec)(*delay_func)(hw->eeprom.delay_usec);
6801 } else if (hw->eeprom.type == em_eeprom_microwire) {
6802 /* cleanup eeprom */
6803
6804 /* CS on Microwire is active-high */
6805 eecd &= ~(E1000_EECD_CS0x00000002 | E1000_EECD_DI0x00000004);
6806
6807 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6808
6809 /* Rising edge of clock */
6810 eecd |= E1000_EECD_SK0x00000001;
6811 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6812 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6813 usec_delay(hw->eeprom.delay_usec)(*delay_func)(hw->eeprom.delay_usec);
6814
6815 /* Falling edge of clock */
6816 eecd &= ~E1000_EECD_SK0x00000001;
6817 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6818 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
6819 usec_delay(hw->eeprom.delay_usec)(*delay_func)(hw->eeprom.delay_usec);
6820 }
6821 /* Stop requesting EEPROM access */
6822 if (hw->mac_type > em_82544) {
6823 eecd &= ~E1000_EECD_REQ0x00000040;
6824 E1000_WRITE_REG(hw, EECD, eecd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd)));
6825 }
6826 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM0x0001);
6827}
6828
6829/******************************************************************************
6830 * Reads a 16 bit word from the EEPROM.
6831 *
6832 * hw - Struct containing variables accessed by shared code
6833 *****************************************************************************/
6834STATIC int32_t
6835em_spi_eeprom_ready(struct em_hw *hw)
6836{
6837 uint16_t retry_count = 0;
6838 uint8_t spi_stat_reg;
6839 DEBUGFUNC("em_spi_eeprom_ready");;
6840 /*
6841 * Read "Status Register" repeatedly until the LSB is cleared. The
6842 * EEPROM will signal that the command has been completed by clearing
6843 * bit 0 of the internal status register. If it's not cleared within
6844 * 5 milliseconds, then error out.
6845 */
6846 retry_count = 0;
6847 do {
6848 em_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI0x05,
6849 hw->eeprom.opcode_bits);
6850 spi_stat_reg = (uint8_t) em_shift_in_ee_bits(hw, 8);
6851 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI0x01))
6852 break;
6853
6854 usec_delay(5)(*delay_func)(5);
6855 retry_count += 5;
6856
6857 em_standby_eeprom(hw);
6858 } while (retry_count < EEPROM_MAX_RETRY_SPI5000);
6859 /*
6860 * ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
6861 * only 0-5mSec on 5V devices)
6862 */
6863 if (retry_count >= EEPROM_MAX_RETRY_SPI5000) {
6864 DEBUGOUT("SPI EEPROM Status error\n");
6865 return -E1000_ERR_EEPROM1;
6866 }
6867 return E1000_SUCCESS0;
6868}
6869
6870/******************************************************************************
6871 * Reads a 16 bit word from the EEPROM.
6872 *
6873 * hw - Struct containing variables accessed by shared code
6874 * offset - offset of word in the EEPROM to read
6875 * data - word read from the EEPROM
6876 * words - number of words to read
6877 *****************************************************************************/
6878int32_t
6879em_read_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words,
6880 uint16_t *data)
6881{
6882 struct em_eeprom_info *eeprom = &hw->eeprom;
6883 uint32_t i = 0;
6884 DEBUGFUNC("em_read_eeprom");;
6885
6886 /* If eeprom is not yet detected, do so now */
6887 if (eeprom->word_size == 0)
6888 em_init_eeprom_params(hw);
6889 /*
6890 * A check for invalid values: offset too large, too many words, and
6891 * not enough words.
6892 */
6893 if ((offset >= eeprom->word_size) ||
6894 (words > eeprom->word_size - offset) ||
6895 (words == 0)) {
6896 DEBUGOUT2("\"words\" parameter out of bounds. Words = %d,"
6897 " size = %d\n", offset, eeprom->word_size);
6898 return -E1000_ERR_EEPROM1;
6899 }
6900 /*
6901 * EEPROM's that don't use EERD to read require us to bit-bang the
6902 * SPI directly. In this case, we need to acquire the EEPROM so that
6903 * FW or other port software does not interrupt.
6904 */
6905 if (em_is_onboard_nvm_eeprom(hw) == TRUE1 &&
6906 em_get_flash_presence_i210(hw) == TRUE1 &&
6907 hw->eeprom.use_eerd == FALSE0) {
6908 /* Prepare the EEPROM for bit-bang reading */
6909 if (em_acquire_eeprom(hw) != E1000_SUCCESS0)
6910 return -E1000_ERR_EEPROM1;
6911 }
6912 /* Eerd register EEPROM access requires no eeprom acquire/release */
6913 if (eeprom->use_eerd == TRUE1)
6914 return em_read_eeprom_eerd(hw, offset, words, data);
6915
6916 /* ICH EEPROM access is done via the ICH flash controller */
6917 if (eeprom->type == em_eeprom_ich8)
6918 return em_read_eeprom_ich8(hw, offset, words, data);
6919
6920 /* Some i210/i211 have a special OTP chip */
6921 if (eeprom->type == em_eeprom_invm)
6922 return em_read_invm_i210(hw, offset, words, data);
6923
6924 /*
6925 * Set up the SPI or Microwire EEPROM for bit-bang reading. We have
6926 * acquired the EEPROM at this point, so any returns should release it
6927 */
6928 if (eeprom->type == em_eeprom_spi) {
6929 uint16_t word_in;
6930 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI0x03;
6931 if (em_spi_eeprom_ready(hw)) {
6932 em_release_eeprom(hw);
6933 return -E1000_ERR_EEPROM1;
6934 }
6935 em_standby_eeprom(hw);
6936 /*
6937 * Some SPI eeproms use the 8th address bit embedded in the
6938 * opcode
6939 */
6940 if ((eeprom->address_bits == 8) && (offset >= 128))
6941 read_opcode |= EEPROM_A8_OPCODE_SPI0x08;
6942
6943 /* Send the READ command (opcode + addr) */
6944 em_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
6945 em_shift_out_ee_bits(hw, (uint16_t) (offset * 2),
6946 eeprom->address_bits);
6947 /*
6948 * Read the data. The address of the eeprom internally
6949 * increments with each byte (spi) being read, saving on the
6950 * overhead of eeprom setup and tear-down. The address
6951 * counter will roll over if reading beyond the size of the
6952 * eeprom, thus allowing the entire memory to be read
6953 * starting from any offset.
6954 */
6955 for (i = 0; i < words; i++) {
6956 word_in = em_shift_in_ee_bits(hw, 16);
6957 data[i] = (word_in >> 8) | (word_in << 8);
6958 }
6959 } else if (eeprom->type == em_eeprom_microwire) {
6960 for (i = 0; i < words; i++) {
6961 /* Send the READ command (opcode + addr) */
6962 em_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE0x6,
6963 eeprom->opcode_bits);
6964 em_shift_out_ee_bits(hw, (uint16_t) (offset + i),
6965 eeprom->address_bits);
6966 /*
6967 * Read the data. For microwire, each word requires
6968 * the overhead of eeprom setup and tear-down.
6969 */
6970 data[i] = em_shift_in_ee_bits(hw, 16);
6971 em_standby_eeprom(hw);
6972 }
6973 }
6974 /* End this read operation */
6975 em_release_eeprom(hw);
6976
6977 return E1000_SUCCESS0;
6978}
6979
6980/******************************************************************************
6981 * Reads a 16 bit word from the EEPROM using the EERD register.
6982 *
6983 * hw - Struct containing variables accessed by shared code
6984 * offset - offset of word in the EEPROM to read
6985 * data - word read from the EEPROM
6986 * words - number of words to read
6987 *****************************************************************************/
6988STATIC int32_t
6989em_read_eeprom_eerd(struct em_hw *hw, uint16_t offset, uint16_t words,
6990 uint16_t *data)
6991{
6992 uint32_t i, eerd = 0;
6993 int32_t error = 0;
6994 for (i = 0; i < words; i++) {
6995 eerd = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT2) +
6996 E1000_EEPROM_RW_REG_START1;
6997
6998 E1000_WRITE_REG(hw, EERD, eerd)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00014 : em_translate_82542_register
(0x00014))), (eerd)));
6999 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ0);
7000
7001 if (error) {
7002 break;
7003 }
7004 data[i] = (E1000_READ_REG(hw, EERD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00014 : em_translate_82542_register
(0x00014))))) >>
7005 E1000_EEPROM_RW_REG_DATA16);
7006
7007 }
7008
7009 return error;
7010}
7011
7012/******************************************************************************
7013 * Writes a 16 bit word from the EEPROM using the EEWR register.
7014 *
7015 * hw - Struct containing variables accessed by shared code
7016 * offset - offset of word in the EEPROM to read
7017 * data - word read from the EEPROM
7018 * words - number of words to read
7019 *****************************************************************************/
7020STATIC int32_t
7021em_write_eeprom_eewr(struct em_hw *hw, uint16_t offset, uint16_t words,
7022 uint16_t *data)
7023{
7024 uint32_t register_value = 0;
7025 uint32_t i = 0;
7026 int32_t error = 0;
7027 if (em_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM0x0001))
7028 return -E1000_ERR_SWFW_SYNC13;
7029
7030 for (i = 0; i < words; i++) {
7031 register_value = (data[i] << E1000_EEPROM_RW_REG_DATA16) |
7032 ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT2) |
7033 E1000_EEPROM_RW_REG_START1;
7034
7035 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE1);
7036 if (error) {
7037 break;
7038 }
7039 E1000_WRITE_REG(hw, EEWR, register_value)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0102C : em_translate_82542_register
(0x0102C))), (register_value)));
7040
7041 error = em_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE1);
7042
7043 if (error) {
7044 break;
7045 }
7046 }
7047
7048 em_swfw_sync_release(hw, E1000_SWFW_EEP_SM0x0001);
7049 return error;
7050}
7051
7052/******************************************************************************
7053 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
7054 *
7055 * hw - Struct containing variables accessed by shared code
7056 *****************************************************************************/
7057STATIC int32_t
7058em_poll_eerd_eewr_done(struct em_hw *hw, int eerd)
7059{
7060 uint32_t attempts = 100000;
7061 uint32_t i, reg = 0;
7062 int32_t done = E1000_ERR_EEPROM1;
7063 for (i = 0; i < attempts; i++) {
7064 if (eerd == E1000_EEPROM_POLL_READ0)
7065 reg = E1000_READ_REG(hw, EERD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00014 : em_translate_82542_register
(0x00014)))));
7066 else
7067 reg = E1000_READ_REG(hw, EEWR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0102C : em_translate_82542_register
(0x0102C)))));
7068
7069 if (reg & E1000_EEPROM_RW_REG_DONE2) {
7070 done = E1000_SUCCESS0;
7071 break;
7072 }
7073 usec_delay(5)(*delay_func)(5);
7074 }
7075
7076 return done;
7077}
7078
7079/******************************************************************************
7080 * Description: Determines if the onboard NVM is FLASH or EEPROM.
7081 *
7082 * hw - Struct containing variables accessed by shared code
7083 *****************************************************************************/
7084STATIC boolean_t
7085em_is_onboard_nvm_eeprom(struct em_hw *hw)
7086{
7087 uint32_t eecd = 0;
7088 DEBUGFUNC("em_is_onboard_nvm_eeprom");;
7089
7090 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
7091 return FALSE0;
7092
7093 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
7094 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
7095
7096 /* Isolate bits 15 & 16 */
7097 eecd = ((eecd >> 15) & 0x03);
7098
7099 /* If both bits are set, device is Flash type */
7100 if (eecd == 0x03) {
7101 return FALSE0;
7102 }
7103 }
7104 return TRUE1;
7105}
7106
7107/******************************************************************************
7108 * Check if flash device is detected.
7109 *
7110 * hw - Struct containing variables accessed by shared code
7111 *****************************************************************************/
7112boolean_t
7113em_get_flash_presence_i210(struct em_hw *hw)
7114{
7115 uint32_t eecd;
7116 DEBUGFUNC("em_get_flash_presence_i210");;
7117
7118 if (hw->mac_type != em_i210)
7119 return TRUE1;
7120
7121 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
7122
7123 if (eecd & E1000_EECD_FLUPD0x00080000)
7124 return TRUE1;
7125
7126 return FALSE0;
7127}
7128
7129/******************************************************************************
7130 * Verifies that the EEPROM has a valid checksum
7131 *
7132 * hw - Struct containing variables accessed by shared code
7133 *
7134 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
7135 * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
7136 * valid.
7137 *****************************************************************************/
7138int32_t
7139em_validate_eeprom_checksum(struct em_hw *hw)
7140{
7141 uint16_t checksum = 0;
7142 uint16_t i, eeprom_data;
7143 uint16_t checksum_reg;
7144 DEBUGFUNC("em_validate_eeprom_checksum");;
7145
7146 checksum_reg = hw->mac_type != em_icp_xxxx ?
7147 EEPROM_CHECKSUM_REG0x003F :
7148 EEPROM_CHECKSUM_REG_ICP_xxxx0x003F;
7149
7150 if (((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) &&
7151 (em_is_onboard_nvm_eeprom(hw) == FALSE0)) {
7152 /*
7153 * Check bit 4 of word 10h. If it is 0, firmware is done
7154 * updating 10h-12h. Checksum may need to be fixed.
7155 */
7156 em_read_eeprom(hw, 0x10, 1, &eeprom_data);
7157 if ((eeprom_data & 0x10) == 0) {
7158 /*
7159 * Read 0x23 and check bit 15. This bit is a 1 when
7160 * the checksum has already been fixed. If the
7161 * checksum is still wrong and this bit is a 1, we
7162 * need to return bad checksum. Otherwise, we need
7163 * to set this bit to a 1 and update the checksum.
7164 */
7165 em_read_eeprom(hw, 0x23, 1, &eeprom_data);
7166 if ((eeprom_data & 0x8000) == 0) {
7167 eeprom_data |= 0x8000;
7168 em_write_eeprom(hw, 0x23, 1, &eeprom_data);
7169 em_update_eeprom_checksum(hw);
7170 }
7171 }
7172 }
7173 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
7174 uint16_t word;
7175 uint16_t valid_csum_mask;
7176
7177 /*
7178 * Drivers must allocate the shadow ram structure for the
7179 * EEPROM checksum to be updated. Otherwise, this bit as
7180 * well as the checksum must both be set correctly for this
7181 * validation to pass.
7182 */
7183 switch (hw->mac_type) {
7184 case em_pch_lpt:
7185 case em_pch_spt:
7186 case em_pch_cnp:
7187 case em_pch_tgp:
7188 case em_pch_adp:
7189 word = EEPROM_COMPAT0x0003;
7190 valid_csum_mask = EEPROM_COMPAT_VALID_CSUM0x0001;
7191 break;
7192 default:
7193 word = EEPROM_FUTURE_INIT_WORD10x0019;
7194 valid_csum_mask = EEPROM_FUTURE_INIT_WORD1_VALID_CSUM0x0040;
7195 break;
7196 }
7197 em_read_eeprom(hw, word, 1, &eeprom_data);
7198 if ((eeprom_data & valid_csum_mask) == 0) {
7199 eeprom_data |= valid_csum_mask;
7200 em_write_eeprom(hw, word, 1, &eeprom_data);
7201 em_update_eeprom_checksum(hw);
7202 }
7203 }
7204 for (i = 0; i < (checksum_reg + 1); i++) {
7205 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
7206 DEBUGOUT("EEPROM Read Error\n");
7207 return -E1000_ERR_EEPROM1;
7208 }
7209 checksum += eeprom_data;
7210 }
7211
7212 if (checksum == (uint16_t) EEPROM_SUM0xBABA)
7213 return E1000_SUCCESS0;
7214 else {
7215 DEBUGOUT("EEPROM Checksum Invalid\n");
7216 return -E1000_ERR_EEPROM1;
7217 }
7218}
7219
7220/******************************************************************************
7221 * Calculates the EEPROM checksum and writes it to the EEPROM
7222 *
7223 * hw - Struct containing variables accessed by shared code
7224 *
7225 * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
7226 * Writes the difference to word offset 63 of the EEPROM.
7227 *****************************************************************************/
7228int32_t
7229em_update_eeprom_checksum(struct em_hw *hw)
7230{
7231 uint32_t ctrl_ext;
7232 uint16_t checksum = 0;
7233 uint16_t i, eeprom_data;
7234 DEBUGFUNC("em_update_eeprom_checksum");;
7235
7236 for (i = 0; i < EEPROM_CHECKSUM_REG0x003F; i++) {
7237 if (em_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
7238 DEBUGOUT("EEPROM Read Error\n");
7239 return -E1000_ERR_EEPROM1;
7240 }
7241 checksum += eeprom_data;
7242 }
7243 checksum = (uint16_t) EEPROM_SUM0xBABA - checksum;
7244 if (em_write_eeprom(hw, EEPROM_CHECKSUM_REG0x003F, 1, &checksum) < 0) {
7245 DEBUGOUT("EEPROM Write Error\n");
7246 return -E1000_ERR_EEPROM1;
7247 } else if (hw->eeprom.type == em_eeprom_flash) {
7248 em_commit_shadow_ram(hw);
7249 } else if (hw->eeprom.type == em_eeprom_ich8) {
7250 em_commit_shadow_ram(hw);
7251 /*
7252 * Reload the EEPROM, or else modifications will not appear
7253 * until after next adapter reset.
7254 */
7255 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
7256 ctrl_ext |= E1000_CTRL_EXT_EE_RST0x00002000;
7257 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
7258 msec_delay(10)(*delay_func)(1000*(10));
7259 }
7260 return E1000_SUCCESS0;
7261}
7262
7263/******************************************************************************
7264 * Parent function for writing words to the different EEPROM types.
7265 *
7266 * hw - Struct containing variables accessed by shared code
7267 * offset - offset within the EEPROM to be written to
7268 * words - number of words to write
7269 * data - 16 bit word to be written to the EEPROM
7270 *
7271 * If em_update_eeprom_checksum is not called after this function, the
7272 * EEPROM will most likely contain an invalid checksum.
7273 *****************************************************************************/
7274int32_t
7275em_write_eeprom(struct em_hw *hw, uint16_t offset, uint16_t words,
7276 uint16_t *data)
7277{
7278 struct em_eeprom_info *eeprom = &hw->eeprom;
7279 int32_t status = 0;
7280 DEBUGFUNC("em_write_eeprom");;
7281
7282 /* If eeprom is not yet detected, do so now */
7283 if (eeprom->word_size == 0)
7284 em_init_eeprom_params(hw);
7285 /*
7286 * A check for invalid values: offset too large, too many words, and
7287 * not enough words.
7288 */
7289 if ((offset >= eeprom->word_size) ||
7290 (words > eeprom->word_size - offset) ||
7291 (words == 0)) {
7292 DEBUGOUT("\"words\" parameter out of bounds\n");
7293 return -E1000_ERR_EEPROM1;
7294 }
7295 /* 82573/4 writes only through eewr */
7296 if (eeprom->use_eewr == TRUE1)
7297 return em_write_eeprom_eewr(hw, offset, words, data);
7298
7299 if (eeprom->type == em_eeprom_ich8)
7300 return em_write_eeprom_ich8(hw, offset, words, data);
7301
7302 /* Prepare the EEPROM for writing */
7303 if (em_acquire_eeprom(hw) != E1000_SUCCESS0)
7304 return -E1000_ERR_EEPROM1;
7305
7306 if (eeprom->type == em_eeprom_microwire) {
7307 status = em_write_eeprom_microwire(hw, offset, words, data);
7308 } else {
7309 status = em_write_eeprom_spi(hw, offset, words, data);
7310 msec_delay(10)(*delay_func)(1000*(10));
7311 }
7312
7313 /* Done with writing */
7314 em_release_eeprom(hw);
7315
7316 return status;
7317}
7318
7319/******************************************************************************
7320 * Writes a 16 bit word to a given offset in an SPI EEPROM.
7321 *
7322 * hw - Struct containing variables accessed by shared code
7323 * offset - offset within the EEPROM to be written to
7324 * words - number of words to write
7325 * data - pointer to array of 8 bit words to be written to the EEPROM
7326 *
7327 *****************************************************************************/
7328STATIC int32_t
7329em_write_eeprom_spi(struct em_hw *hw, uint16_t offset, uint16_t words,
7330 uint16_t *data)
7331{
7332 struct em_eeprom_info *eeprom = &hw->eeprom;
7333 uint16_t widx = 0;
7334 DEBUGFUNC("em_write_eeprom_spi");;
7335
7336 while (widx < words) {
7337 uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI0x02;
7338 if (em_spi_eeprom_ready(hw))
7339 return -E1000_ERR_EEPROM1;
7340
7341 em_standby_eeprom(hw);
7342
7343 /* Send the WRITE ENABLE command (8 bit opcode ) */
7344 em_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI0x06,
7345 eeprom->opcode_bits);
7346
7347 em_standby_eeprom(hw);
7348 /*
7349 * Some SPI eeproms use the 8th address bit embedded in the
7350 * opcode
7351 */
7352 if ((eeprom->address_bits == 8) && (offset >= 128))
7353 write_opcode |= EEPROM_A8_OPCODE_SPI0x08;
7354
7355 /* Send the Write command (8-bit opcode + addr) */
7356 em_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
7357
7358 em_shift_out_ee_bits(hw, (uint16_t) ((offset + widx) * 2),
7359 eeprom->address_bits);
7360
7361 /* Send the data */
7362 /*
7363 * Loop to allow for up to whole page write (32 bytes) of
7364 * eeprom
7365 */
7366 while (widx < words) {
7367 uint16_t word_out = data[widx];
7368 word_out = (word_out >> 8) | (word_out << 8);
7369 em_shift_out_ee_bits(hw, word_out, 16);
7370 widx++;
7371 /*
7372 * Some larger eeprom sizes are capable of a 32-byte
7373 * PAGE WRITE operation, while the smaller eeproms
7374 * are capable of an 8-byte PAGE WRITE operation.
7375 * Break the inner loop to pass new address
7376 */
7377 if ((((offset + widx) * 2) % eeprom->page_size) == 0) {
7378 em_standby_eeprom(hw);
7379 break;
7380 }
7381 }
7382 }
7383
7384 return E1000_SUCCESS0;
7385}
7386
7387/******************************************************************************
7388 * Writes a 16 bit word to a given offset in a Microwire EEPROM.
7389 *
7390 * hw - Struct containing variables accessed by shared code
7391 * offset - offset within the EEPROM to be written to
7392 * words - number of words to write
7393 * data - pointer to array of 16 bit words to be written to the EEPROM
7394 *
7395 *****************************************************************************/
7396STATIC int32_t
7397em_write_eeprom_microwire(struct em_hw *hw, uint16_t offset, uint16_t words,
7398 uint16_t *data)
7399{
7400 struct em_eeprom_info *eeprom = &hw->eeprom;
7401 uint32_t eecd;
7402 uint16_t words_written = 0;
7403 uint16_t i = 0;
7404 DEBUGFUNC("em_write_eeprom_microwire");;
7405 /*
7406 * Send the write enable command to the EEPROM (3-bit opcode plus
7407 * 6/8-bit dummy address beginning with 11). It's less work to
7408 * include the 11 of the dummy address as part of the opcode than it
7409 * is to shift it over the correct number of bits for the address.
7410 * This puts the EEPROM into write/erase mode.
7411 */
7412 em_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE0x13,
7413 (uint16_t) (eeprom->opcode_bits + 2));
7414
7415 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2));
7416
7417 /* Prepare the EEPROM */
7418 em_standby_eeprom(hw);
7419
7420 while (words_written < words) {
7421 /* Send the Write command (3-bit opcode + addr) */
7422 em_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE0x5,
7423 eeprom->opcode_bits);
7424
7425 em_shift_out_ee_bits(hw, (uint16_t) (offset + words_written),
7426 eeprom->address_bits);
7427
7428 /* Send the data */
7429 em_shift_out_ee_bits(hw, data[words_written], 16);
7430 /*
7431 * Toggle the CS line. This in effect tells the EEPROM to
7432 * execute the previous command.
7433 */
7434 em_standby_eeprom(hw);
7435 /*
7436 * Read DO repeatedly until it is high (equal to '1'). The
7437 * EEPROM will signal that the command has been completed by
7438 * raising the DO signal. If DO does not go high in 10
7439 * milliseconds, then error out.
7440 */
7441 for (i = 0; i < 200; i++) {
7442 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
7443 if (eecd & E1000_EECD_DO0x00000008)
7444 break;
7445 usec_delay(50)(*delay_func)(50);
7446 }
7447 if (i == 200) {
7448 DEBUGOUT("EEPROM Write did not complete\n");
7449 return -E1000_ERR_EEPROM1;
7450 }
7451 /* Recover from write */
7452 em_standby_eeprom(hw);
7453
7454 words_written++;
7455 }
7456 /*
7457 * Send the write disable command to the EEPROM (3-bit opcode plus
7458 * 6/8-bit dummy address beginning with 10). It's less work to
7459 * include the 10 of the dummy address as part of the opcode than it
7460 * is to shift it over the correct number of bits for the address.
7461 * This takes the EEPROM out of write/erase mode.
7462 */
7463 em_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE0x10,
7464 (uint16_t) (eeprom->opcode_bits + 2));
7465
7466 em_shift_out_ee_bits(hw, 0, (uint16_t) (eeprom->address_bits - 2));
7467
7468 return E1000_SUCCESS0;
7469}
7470
7471/******************************************************************************
7472 * Flushes the cached eeprom to NVM. This is done by saving the modified values
7473 * in the eeprom cache and the non modified values in the currently active bank
7474 * to the new bank.
7475 *
7476 * hw - Struct containing variables accessed by shared code
7477 * offset - offset of word in the EEPROM to read
7478 * data - word read from the EEPROM
7479 * words - number of words to read
7480 *****************************************************************************/
7481STATIC int32_t
7482em_commit_shadow_ram(struct em_hw *hw)
7483{
7484 uint32_t attempts = 100000;
7485 uint32_t eecd = 0;
7486 uint32_t flop = 0;
7487 uint32_t i = 0;
7488 int32_t error = E1000_SUCCESS0;
7489 uint32_t old_bank_offset = 0;
7490 uint32_t new_bank_offset = 0;
7491 uint8_t low_byte = 0;
7492 uint8_t high_byte = 0;
7493 boolean_t sector_write_failed = FALSE0;
7494 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
7495 /*
7496 * The flop register will be used to determine if flash type
7497 * is STM
7498 */
7499 flop = E1000_READ_REG(hw, FLOP)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0103C : em_translate_82542_register
(0x0103C)))));
7500 for (i = 0; i < attempts; i++) {
7501 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
7502 if ((eecd & E1000_EECD_FLUPD0x00080000) == 0) {
7503 break;
7504 }
7505 usec_delay(5)(*delay_func)(5);
7506 }
7507
7508 if (i == attempts) {
7509 return -E1000_ERR_EEPROM1;
7510 }
7511 /*
7512 * If STM opcode located in bits 15:8 of flop, reset firmware
7513 */
7514 if ((flop & 0xFF00) == E1000_STM_OPCODE0xDB00) {
7515 E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x08F00 : em_translate_82542_register
(0x08F00))), (0xC0)));
7516 }
7517 /* Perform the flash update */
7518 E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (eecd | 0x00080000)));
7519
7520 for (i = 0; i < attempts; i++) {
7521 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
7522 if ((eecd & E1000_EECD_FLUPD0x00080000) == 0) {
7523 break;
7524 }
7525 usec_delay(5)(*delay_func)(5);
7526 }
7527
7528 if (i == attempts) {
7529 return -E1000_ERR_EEPROM1;
7530 }
7531 }
7532 if ((hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan) &&
7533 hw->eeprom_shadow_ram != NULL((void *)0)) {
7534 /*
7535 * We're writing to the opposite bank so if we're on bank 1,
7536 * write to bank 0 etc. We also need to erase the segment
7537 * that is going to be written
7538 */
7539 if (!(E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))))) & E1000_EECD_SEC1VAL0x00400000)) {
7540 new_bank_offset = hw->flash_bank_size * 2;
7541 old_bank_offset = 0;
7542 em_erase_ich8_4k_segment(hw, 1);
7543 } else {
7544 old_bank_offset = hw->flash_bank_size * 2;
7545 new_bank_offset = 0;
7546 em_erase_ich8_4k_segment(hw, 0);
7547 }
7548
7549 sector_write_failed = FALSE0;
7550 /*
7551 * Loop for every byte in the shadow RAM, which is in units
7552 * of words.
7553 */
7554 for (i = 0; i < E1000_SHADOW_RAM_WORDS2048; i++) {
7555 /*
7556 * Determine whether to write the value stored in the
7557 * other NVM bank or a modified value stored in the
7558 * shadow RAM
7559 */
7560 if (hw->eeprom_shadow_ram[i].modified == TRUE1) {
7561 low_byte = (uint8_t)
7562 hw->eeprom_shadow_ram[i].eeprom_word;
7563 usec_delay(100)(*delay_func)(100);
7564 error = em_verify_write_ich8_byte(hw,
7565 (i << 1) + new_bank_offset, low_byte);
7566
7567 if (error != E1000_SUCCESS0)
7568 sector_write_failed = TRUE1;
7569 else {
7570 high_byte = (uint8_t)
7571 (hw->eeprom_shadow_ram
7572 [i].eeprom_word >> 8);
7573 usec_delay(100)(*delay_func)(100);
7574 }
7575 } else {
7576 em_read_ich8_byte(hw, (i << 1) +
7577 old_bank_offset, &low_byte);
7578 usec_delay(100)(*delay_func)(100);
7579 error = em_verify_write_ich8_byte(hw,
7580 (i << 1) + new_bank_offset, low_byte);
7581
7582 if (error != E1000_SUCCESS0)
7583 sector_write_failed = TRUE1;
7584 else {
7585 em_read_ich8_byte(hw, (i << 1) +
7586 old_bank_offset + 1, &high_byte);
7587 usec_delay(100)(*delay_func)(100);
7588 }
7589 }
7590 /*
7591 * If the write of the low byte was successful, go
7592 * ahread and write the high byte while checking to
7593 * make sure that if it is the signature byte, then
7594 * it is handled properly
7595 */
7596 if (sector_write_failed == FALSE0) {
7597 /*
7598 * If the word is 0x13, then make sure the
7599 * signature bits (15:14) are 11b until the
7600 * commit has completed. This will allow us
7601 * to write 10b which indicates the signature
7602 * is valid. We want to do this after the
7603 * write has completed so that we don't mark
7604 * the segment valid while the write is still
7605 * in progress
7606 */
7607 if (i == E1000_ICH_NVM_SIG_WORD0x13)
7608 high_byte = E1000_ICH_NVM_VALID_SIG_MASK0xC0 |
7609 high_byte;
7610
7611 error = em_verify_write_ich8_byte(hw, (i << 1)
7612 + new_bank_offset + 1, high_byte);
7613 if (error != E1000_SUCCESS0)
7614 sector_write_failed = TRUE1;
7615
7616 } else {
7617 /*
7618 * If the write failed then break from the
7619 * loop and return an error
7620 */
7621 break;
7622 }
7623 }
7624 /*
7625 * Don't bother writing the segment valid bits if sector
7626 * programming failed.
7627 */
7628 if (sector_write_failed == FALSE0) {
7629 /*
7630 * Finally validate the new segment by setting bit
7631 * 15:14 to 10b in word 0x13 , this can be done
7632 * without an erase as well since these bits are 11
7633 * to start with and we need to change bit 14 to 0b
7634 */
7635 em_read_ich8_byte(hw, E1000_ICH_NVM_SIG_WORD0x13 * 2 + 1 +
7636 new_bank_offset, &high_byte);
7637 high_byte &= 0xBF;
7638 error = em_verify_write_ich8_byte(hw,
7639 E1000_ICH_NVM_SIG_WORD0x13 * 2 + 1 + new_bank_offset,
7640 high_byte);
7641 /*
7642 * And invalidate the previously valid segment by
7643 * setting its signature word (0x13) high_byte to 0b.
7644 * This can be done without an erase because flash
7645 * erase sets all bits to 1's. We can write 1's to
7646 * 0's without an erase
7647 */
7648 if (error == E1000_SUCCESS0) {
7649 error = em_verify_write_ich8_byte(hw,
7650 E1000_ICH_NVM_SIG_WORD0x13 * 2 + 1 +
7651 old_bank_offset, 0);
7652 }
7653 /* Clear the now not used entry in the cache */
7654 for (i = 0; i < E1000_SHADOW_RAM_WORDS2048; i++) {
7655 hw->eeprom_shadow_ram[i].modified = FALSE0;
7656 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
7657 }
7658 }
7659 }
7660 return error;
7661}
7662
7663/******************************************************************************
7664 * Reads the adapter's part number from the EEPROM
7665 *
7666 * hw - Struct containing variables accessed by shared code
7667 * part_num - Adapter's part number
7668 *****************************************************************************/
7669int32_t
7670em_read_part_num(struct em_hw *hw, uint32_t *part_num)
7671{
7672 uint16_t offset = EEPROM_PBA_BYTE_18;
7673 uint16_t eeprom_data;
7674 DEBUGFUNC("em_read_part_num");;
7675
7676 /* Get word 0 from EEPROM */
7677 if (em_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
7678 DEBUGOUT("EEPROM Read Error\n");
7679 return -E1000_ERR_EEPROM1;
7680 }
7681 /* Save word 0 in upper half of part_num */
7682 *part_num = (uint32_t)eeprom_data << 16;
7683
7684 /* Get word 1 from EEPROM */
7685 if (em_read_eeprom(hw, ++offset, 1, &eeprom_data) < 0) {
7686 DEBUGOUT("EEPROM Read Error\n");
7687 return -E1000_ERR_EEPROM1;
7688 }
7689 /* Save word 1 in lower half of part_num */
7690 *part_num |= eeprom_data;
7691
7692 return E1000_SUCCESS0;
7693}
7694
7695/******************************************************************************
7696 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
7697 * second function of dual function devices
7698 *
7699 * hw - Struct containing variables accessed by shared code
7700 *****************************************************************************/
7701int32_t
7702em_read_mac_addr(struct em_hw *hw)
7703{
7704 uint16_t offset;
7705 uint16_t eeprom_data, i;
7706 uint16_t ia_base_addr = 0;
7707 DEBUGFUNC("em_read_mac_addr");;
7708
7709 if (hw->mac_type == em_icp_xxxx) {
7710 ia_base_addr = (uint16_t)
7711 EEPROM_IA_START_ICP_xxxx(hw->icp_xxxx_port_num)((((hw->icp_xxxx_port_num) + 1) << 4) + 2);
7712 } else if (hw->mac_type == em_82580 || hw->mac_type == em_i350) {
7713 ia_base_addr = NVM_82580_LAN_FUNC_OFFSET(hw->bus_func)(hw->bus_func ? (0x40 + (0x40 * hw->bus_func)) : 0);
7714 }
7715 for (i = 0; i < NODE_ADDRESS_SIZE6; i += 2) {
7716 offset = i >> 1;
7717 if (em_read_eeprom(hw, offset + ia_base_addr, 1, &eeprom_data)
7718 < 0) {
7719 DEBUGOUT("EEPROM Read Error\n");
7720 return -E1000_ERR_EEPROM1;
7721 }
7722 hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
7723 hw->perm_mac_addr[i + 1] = (uint8_t) (eeprom_data >> 8);
7724 }
7725
7726 switch (hw->mac_type) {
7727 default:
7728 break;
7729 case em_82546:
7730 case em_82546_rev_3:
7731 case em_82571:
7732 case em_82575:
7733 case em_82576:
7734 case em_80003es2lan:
7735 if (E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))))) & E1000_STATUS_FUNC_10x00000004)
7736 hw->perm_mac_addr[5] ^= 0x01;
7737 break;
7738 }
7739
7740 for (i = 0; i < NODE_ADDRESS_SIZE6; i++)
7741 hw->mac_addr[i] = hw->perm_mac_addr[i];
7742 return E1000_SUCCESS0;
7743}
7744
7745/******************************************************************************
7746 * Explicitly disables jumbo frames and resets some PHY registers back to hw-
7747 * defaults. This is necessary in case the ethernet cable was inserted AFTER
7748 * the firmware initialized the PHY. Otherwise it is left in a state where
7749 * it is possible to transmit but not receive packets. Observed on I217-LM and
7750 * fixed in FreeBSD's sys/dev/e1000/e1000_ich8lan.c.
7751 *
7752 * hw - Struct containing variables accessed by shared code
7753 *****************************************************************************/
7754STATIC int32_t
7755em_phy_no_cable_workaround(struct em_hw *hw) {
7756 int32_t ret_val, dft_ret_val;
7757 uint32_t mac_reg;
7758 uint16_t data, phy_reg;
7759
7760 /* disable Rx path while enabling workaround */
7761 em_read_phy_reg(hw, I2_DFT_CTRL(((769) << 5) | ((20) & 0x1F)), &phy_reg);
7762 ret_val = em_write_phy_reg(hw, I2_DFT_CTRL(((769) << 5) | ((20) & 0x1F)), phy_reg | (1 << 14));
7763 if (ret_val)
7764 return ret_val;
7765
7766 /* Write MAC register values back to h/w defaults */
7767 mac_reg = E1000_READ_REG(hw, FFLT_DBG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F04 : em_translate_82542_register
(0x05F04)))));
7768 mac_reg &= ~(0xF << 14);
7769 E1000_WRITE_REG(hw, FFLT_DBG, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05F04 : em_translate_82542_register
(0x05F04))), (mac_reg)));
7770
7771 mac_reg = E1000_READ_REG(hw, RCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100)))));
7772 mac_reg &= ~E1000_RCTL_SECRC0x04000000;
7773 E1000_WRITE_REG(hw, RCTL, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00100 : em_translate_82542_register
(0x00100))), (mac_reg)));
7774
7775 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL0x00000001, &data);
7776 if (ret_val)
7777 goto out;
7778 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_CTRL0x00000001,
7779 data & ~(1 << 0));
7780 if (ret_val)
7781 goto out;
7782
7783 ret_val = em_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010, &data);
7784 if (ret_val)
7785 goto out;
7786
7787 data &= ~(0xF << 8);
7788 data |= (0xB << 8);
7789 ret_val = em_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL0x00000010, data);
7790 if (ret_val)
7791 goto out;
7792
7793 /* Write PHY register values back to h/w defaults */
7794 em_read_phy_reg(hw, I2_SMBUS_CTRL(((769) << 5) | ((23) & 0x1F)), &data);
7795 data &= ~(0x7F << 5);
7796 ret_val = em_write_phy_reg(hw, I2_SMBUS_CTRL(((769) << 5) | ((23) & 0x1F)), data);
7797 if (ret_val)
7798 goto out;
7799
7800 em_read_phy_reg(hw, I2_MODE_CTRL(((769) << 5) | ((16) & 0x1F)), &data);
7801 data |= (1 << 13);
7802 ret_val = em_write_phy_reg(hw, I2_MODE_CTRL(((769) << 5) | ((16) & 0x1F)), data);
7803 if (ret_val)
7804 goto out;
7805
7806 /*
7807 * 776.20 and 776.23 are not documented in
7808 * i217-ethernet-controller-datasheet.pdf...
7809 */
7810 em_read_phy_reg(hw, PHY_REG(776, 20)(((776) << 5) | ((20) & 0x1F)), &data);
7811 data &= ~(0x3FF << 2);
7812 data |= (0x8 << 2);
7813 ret_val = em_write_phy_reg(hw, PHY_REG(776, 20)(((776) << 5) | ((20) & 0x1F)), data);
7814 if (ret_val)
7815 goto out;
7816
7817 ret_val = em_write_phy_reg(hw, PHY_REG(776, 23)(((776) << 5) | ((23) & 0x1F)), 0x7E00);
7818 if (ret_val)
7819 goto out;
7820
7821 em_read_phy_reg(hw, I2_PCIE_POWER_CTRL(((770) << 5) | ((17) & 0x1F)), &data);
7822 ret_val = em_write_phy_reg(hw, I2_PCIE_POWER_CTRL(((770) << 5) | ((17) & 0x1F)), data & ~(1 << 10));
7823 if (ret_val)
7824 goto out;
7825
7826out:
7827 /* re-enable Rx path after enabling workaround */
7828 dft_ret_val = em_write_phy_reg(hw, I2_DFT_CTRL(((769) << 5) | ((20) & 0x1F)), phy_reg & ~(1 << 14));
7829 if (ret_val)
7830 return ret_val;
7831 else
7832 return dft_ret_val;
7833}
7834
7835/******************************************************************************
7836 * Initializes receive address filters.
7837 *
7838 * hw - Struct containing variables accessed by shared code
7839 *
7840 * Places the MAC address in receive address register 0 and clears the rest
7841 * of the receive address registers. Clears the multicast table. Assumes
7842 * the receiver is in reset when the routine is called.
7843 *****************************************************************************/
7844STATIC void
7845em_init_rx_addrs(struct em_hw *hw)
7846{
7847 uint32_t i;
7848 uint32_t rar_num;
7849 DEBUGFUNC("em_init_rx_addrs");;
7850
7851 if (hw->mac_type == em_pch_lpt || hw->mac_type == em_pch_spt ||
7852 hw->mac_type == em_pch_cnp || hw->mac_type == em_pch_tgp ||
7853 hw->mac_type == em_pch_adp || hw->mac_type == em_pch2lan)
7854 if (em_phy_no_cable_workaround(hw))
7855 printf(" ...failed to apply em_phy_no_cable_"
7856 "workaround.\n");
7857
7858 /* Setup the receive address. */
7859 DEBUGOUT("Programming MAC Address into RAR[0]\n");
7860
7861 em_rar_set(hw, hw->mac_addr, 0);
7862
7863 rar_num = E1000_RAR_ENTRIES15;
7864 /*
7865 * Reserve a spot for the Locally Administered Address to work around
7866 * an 82571 issue in which a reset on one port will reload the MAC on
7867 * the other port.
7868 */
7869 if ((hw->mac_type == em_82571) && (hw->laa_is_present == TRUE1))
7870 rar_num -= 1;
7871 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
7872 rar_num = E1000_RAR_ENTRIES_ICH8LAN7;
7873 if (hw->mac_type == em_ich8lan)
7874 rar_num -= 1;
7875 if (hw->mac_type == em_82580)
7876 rar_num = E1000_RAR_ENTRIES_8258024;
7877 if (hw->mac_type == em_i210)
7878 rar_num = E1000_RAR_ENTRIES_8257516;
7879 if (hw->mac_type == em_i350)
7880 rar_num = E1000_RAR_ENTRIES_I35032;
7881
7882 /* Zero out the other 15 receive addresses. */
7883 DEBUGOUT("Clearing RAR[1-15]\n");
7884 for (i = 1; i < rar_num; i++) {
7885 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05400 : em_translate_82542_register
(0x05400)) + (((i << 1)) << 2)), (0)));
7886 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
7887 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05400 : em_translate_82542_register
(0x05400)) + ((((i << 1) + 1)) << 2)), (0)));
7888 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
7889 }
7890}
7891
7892/******************************************************************************
7893 * Updates the MAC's list of multicast addresses.
7894 *
7895 * hw - Struct containing variables accessed by shared code
7896 * mc_addr_list - the list of new multicast addresses
7897 * mc_addr_count - number of addresses
7898 * pad - number of bytes between addresses in the list
7899 *
7900 * The given list replaces any existing list and hashes the addresses into the
7901 * multicast table.
7902 *****************************************************************************/
7903void
7904em_mc_addr_list_update(struct em_hw *hw, uint8_t *mc_addr_list,
7905 uint32_t mc_addr_count, uint32_t pad)
7906{
7907 uint32_t hash_value;
7908 uint32_t i;
7909 uint32_t num_mta_entry;
7910 DEBUGFUNC("em_mc_addr_list_update");;
7911 /*
7912 * Set the new number of MC addresses that we are being requested to
7913 * use.
7914 */
7915 hw->num_mc_addrs = mc_addr_count;
7916
7917 /* Clear the MTA */
7918 DEBUGOUT(" Clearing MTA\n");
7919 num_mta_entry = E1000_NUM_MTA_REGISTERS128;
7920 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
7921 num_mta_entry = E1000_NUM_MTA_REGISTERS_ICH8LAN32;
7922
7923 for (i = 0; i < num_mta_entry; i++) {
7924 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + ((i) << 2)), (0)));
7925 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
7926 }
7927
7928 /* Add the new addresses */
7929 for (i = 0; i < mc_addr_count; i++) {
7930 DEBUGOUT(" Adding the multicast addresses:\n");
7931 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i,
7932 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad)],
7933 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 1],
7934 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 2],
7935 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 3],
7936 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 4],
7937 mc_addr_list[i * (ETH_LENGTH_OF_ADDRESS + pad) + 5]);
7938
7939 hash_value = em_hash_mc_addr(hw, mc_addr_list +
7940 (i * (ETH_LENGTH_OF_ADDRESS6 + pad)));
7941
7942 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value);
7943 em_mta_set(hw, hash_value);
7944 }
7945 DEBUGOUT("MC Update Complete\n");
7946}
7947
7948/******************************************************************************
7949 * Hashes an address to determine its location in the multicast table
7950 *
7951 * hw - Struct containing variables accessed by shared code
7952 * mc_addr - the multicast address to hash
7953 *****************************************************************************/
7954uint32_t
7955em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr)
7956{
7957 uint32_t hash_value = 0;
7958 /*
7959 * The portion of the address that is used for the hash table is
7960 * determined by the mc_filter_type setting.
7961 */
7962 switch (hw->mc_filter_type) {
7963 /*
7964 * [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB
7965 * MSB
7966 */
7967 case 0:
7968 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
7969 /* [47:38] i.e. 0x158 for above example address */
7970 hash_value = ((mc_addr[4] >> 6) |
7971 (((uint16_t) mc_addr[5]) << 2));
7972 } else {
7973 /* [47:36] i.e. 0x563 for above example address */
7974 hash_value = ((mc_addr[4] >> 4) |
7975 (((uint16_t) mc_addr[5]) << 4));
7976 }
7977 break;
7978 case 1:
7979 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
7980 /* [46:37] i.e. 0x2B1 for above example address */
7981 hash_value = ((mc_addr[4] >> 5) |
7982 (((uint16_t) mc_addr[5]) << 3));
7983 } else {
7984 /* [46:35] i.e. 0xAC6 for above example address */
7985 hash_value = ((mc_addr[4] >> 3) |
7986 (((uint16_t) mc_addr[5]) << 5));
7987 }
7988 break;
7989 case 2:
7990 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
7991 /* [45:36] i.e. 0x163 for above example address */
7992 hash_value = ((mc_addr[4] >> 4) |
7993 (((uint16_t) mc_addr[5]) << 4));
7994 } else {
7995 /* [45:34] i.e. 0x5D8 for above example address */
7996 hash_value = ((mc_addr[4] >> 2) |
7997 (((uint16_t) mc_addr[5]) << 6));
7998 }
7999 break;
8000 case 3:
8001 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
8002 /* [43:34] i.e. 0x18D for above example address */
8003 hash_value = ((mc_addr[4] >> 2) |
8004 (((uint16_t) mc_addr[5]) << 6));
8005 } else {
8006 /* [43:32] i.e. 0x634 for above example address */
8007 hash_value = ((mc_addr[4]) |
8008 (((uint16_t) mc_addr[5]) << 8));
8009 }
8010 break;
8011 }
8012
8013 hash_value &= 0xFFF;
8014 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
8015 hash_value &= 0x3FF;
8016
8017 return hash_value;
8018}
8019
8020/******************************************************************************
8021 * Sets the bit in the multicast table corresponding to the hash value.
8022 *
8023 * hw - Struct containing variables accessed by shared code
8024 * hash_value - Multicast address hash value
8025 *****************************************************************************/
8026void
8027em_mta_set(struct em_hw *hw, uint32_t hash_value)
8028{
8029 uint32_t hash_bit, hash_reg;
8030 uint32_t mta;
8031 uint32_t temp;
8032 /*
8033 * The MTA is a register array of 128 32-bit registers. It is treated
8034 * like an array of 4096 bits. We want to set bit
8035 * BitArray[hash_value]. So we figure out what register the bit is
8036 * in, read it, OR in the new bit, then write back the new value.
8037 * The register is determined by the upper 7 bits of the hash value
8038 * and the bit within that register are determined by the lower 5
8039 * bits of the value.
8040 */
8041 hash_reg = (hash_value >> 5) & 0x7F;
8042 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
8043 hash_reg &= 0x1F;
8044
8045 hash_bit = hash_value & 0x1F;
8046
8047 mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + ((hash_reg) << 2))));
8048
8049 mta |= (1 << hash_bit);
8050 /*
8051 * If we are on an 82544 and we are trying to write an odd offset in
8052 * the MTA, save off the previous entry before writing and restore
8053 * the old value after writing.
8054 */
8055 if ((hw->mac_type == em_82544) && ((hash_reg & 0x1) == 1)) {
8056 temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + (((hash_reg - 1)) << 2))));
8057 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + ((hash_reg) << 2)), (mta)));
8058 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8059 E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + (((hash_reg - 1)) << 2)), (temp)));
8060 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8061 } else {
8062 E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05200 : em_translate_82542_register
(0x05200)) + ((hash_reg) << 2)), (mta)));
8063 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8064 }
8065}
8066
8067/******************************************************************************
8068 * Puts an ethernet address into a receive address register.
8069 *
8070 * hw - Struct containing variables accessed by shared code
8071 * addr - Address to put into receive address register
8072 * index - Receive address register to write
8073 *****************************************************************************/
8074void
8075em_rar_set(struct em_hw *hw, uint8_t *addr, uint32_t index)
8076{
8077 uint32_t rar_low, rar_high;
8078 /*
8079 * HW expects these in little endian so we reverse the byte order
8080 * from network order (big endian) to little endian
8081 */
8082 rar_low = ((uint32_t) addr[0] | ((uint32_t) addr[1] << 8) |
8083 ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24));
8084 rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8));
8085 /*
8086 * Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
8087 * unit hang.
8088 *
8089 * Description: If there are any Rx frames queued up or otherwise
8090 * present in the HW before RSS is enabled, and then we enable RSS,
8091 * the HW Rx unit will hang. To work around this issue, we have to
8092 * disable receives and flush out all Rx frames before we enable RSS.
8093 * To do so, we modify we redirect all Rx traffic to manageability
8094 * and then reset the HW. This flushes away Rx frames, and (since the
8095 * redirections to manageability persists across resets) keeps new
8096 * ones from coming in while we work. Then, we clear the Address
8097 * Valid AV bit for all MAC addresses and undo the re-direction to
8098 * manageability. Now, frames are coming in again, but the MAC won't
8099 * accept them, so far so good. We now proceed to initialize RSS (if
8100 * necessary) and configure the Rx unit. Last, we re-enable the AV
8101 * bits and continue on our merry way.
8102 */
8103 switch (hw->mac_type) {
8104 case em_82571:
8105 case em_82572:
8106 case em_80003es2lan:
8107 if (hw->leave_av_bit_off == TRUE1)
8108 break;
8109 default:
8110 /* Indicate to hardware the Address is Valid. */
8111 rar_high |= E1000_RAH_AV0x80000000;
8112 break;
8113 }
8114
8115 E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05400 : em_translate_82542_register
(0x05400)) + (((index << 1)) << 2)), (rar_low)));
8116 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8117 E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05400 : em_translate_82542_register
(0x05400)) + ((((index << 1) + 1)) << 2)), (rar_high
)));
8118 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8119}
8120
8121/******************************************************************************
8122 * Clears the VLAN filer table
8123 *
8124 * hw - Struct containing variables accessed by shared code
8125 *****************************************************************************/
8126STATIC void
8127em_clear_vfta(struct em_hw *hw)
8128{
8129 uint32_t offset;
8130 uint32_t vfta_value = 0;
8131 uint32_t vfta_offset = 0;
8132 uint32_t vfta_bit_in_reg = 0;
8133 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
))
8134 return;
8135
8136 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574)) {
8137 if (hw->mng_cookie.vlan_id != 0) {
8138 /*
8139 * The VFTA is a 4096b bit-field, each identifying a
8140 * single VLAN ID. The following operations
8141 * determine which 32b entry (i.e. offset) into the
8142 * array we want to set the VLAN ID (i.e. bit) of the
8143 * manageability unit.
8144 */
8145 vfta_offset = (hw->mng_cookie.vlan_id >>
8146 E1000_VFTA_ENTRY_SHIFT0x5) & E1000_VFTA_ENTRY_MASK0x7F;
8147
8148 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
8149 E1000_VFTA_ENTRY_BIT_SHIFT_MASK0x1F);
8150 }
8151 }
8152 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE128; offset++) {
8153 /*
8154 * If the offset we want to clear is the same offset of the
8155 * manageability VLAN ID, then clear all bits except that of
8156 * the manageability unit
8157 */
8158 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
8159 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05600 : em_translate_82542_register
(0x05600)) + ((offset) << 2)), (vfta_value)));
8160 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8161 }
8162}
8163
8164/*
8165 * Due to hw errata, if the host tries to configure the VFTA register
8166 * while performing queries from the BMC or DMA, then the VFTA in some
8167 * cases won't be written.
8168 */
8169void
8170em_clear_vfta_i350(struct em_hw *hw)
8171{
8172 uint32_t offset;
8173 int i;
8174
8175 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE128; offset++) {
8176 for (i = 0; i < 10; i++)
8177 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05600 : em_translate_82542_register
(0x05600)) + ((offset) << 2)), (0)));
8178 E1000_WRITE_FLUSH(hw)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8179 }
8180}
8181
8182STATIC int32_t
8183em_id_led_init(struct em_hw *hw)
8184{
8185 uint32_t ledctl;
8186 const uint32_t ledctl_mask = 0x000000FF;
8187 const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON0xE;
8188 const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF0xF;
8189 uint16_t eeprom_data, i, temp;
8190 const uint16_t led_mask = 0x0F;
8191 DEBUGFUNC("em_id_led_init");;
8192
8193 if (hw->mac_type < em_82540 || hw->mac_type == em_icp_xxxx) {
8194 /* Nothing to do */
8195 return E1000_SUCCESS0;
8196 }
8197 ledctl = E1000_READ_REG(hw, LEDCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00E00 : em_translate_82542_register
(0x00E00)))));
8198 hw->ledctl_default = ledctl;
8199 hw->ledctl_mode1 = hw->ledctl_default;
8200 hw->ledctl_mode2 = hw->ledctl_default;
8201
8202 if (em_read_eeprom(hw, EEPROM_ID_LED_SETTINGS0x0004, 1, &eeprom_data) < 0) {
8203 DEBUGOUT("EEPROM Read Error\n");
8204 return -E1000_ERR_EEPROM1;
8205 }
8206 if ((hw->mac_type == em_82573) &&
8207 (eeprom_data == ID_LED_RESERVED_825730xF746))
8208 eeprom_data = ID_LED_DEFAULT_825730x1811;
8209 else if ((eeprom_data == ID_LED_RESERVED_00000x0000) ||
8210 (eeprom_data == ID_LED_RESERVED_FFFF0xFFFF)) {
8211 if (hw->mac_type == em_ich8lan ||
8212 hw->mac_type == em_ich9lan ||
8213 hw->mac_type == em_ich10lan) // XXX
8214 eeprom_data = ID_LED_DEFAULT_ICH8LAN((0x1 << 12) | (0x3 << 8) | (0x2 << 4) | (0x1
));
8215 else
8216 eeprom_data = ID_LED_DEFAULT((0x8 << 12) | (0x9 << 8) | (0x1 << 4) | (0x1
));
8217 }
8218 for (i = 0; i < 4; i++) {
8219 temp = (eeprom_data >> (i << 2)) & led_mask;
8220 switch (temp) {
8221 case ID_LED_ON1_DEF20x4:
8222 case ID_LED_ON1_ON20x5:
8223 case ID_LED_ON1_OFF20x6:
8224 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
8225 hw->ledctl_mode1 |= ledctl_on << (i << 3);
8226 break;
8227 case ID_LED_OFF1_DEF20x7:
8228 case ID_LED_OFF1_ON20x8:
8229 case ID_LED_OFF1_OFF20x9:
8230 hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
8231 hw->ledctl_mode1 |= ledctl_off << (i << 3);
8232 break;
8233 default:
8234 /* Do nothing */
8235 break;
8236 }
8237 switch (temp) {
8238 case ID_LED_DEF1_ON20x2:
8239 case ID_LED_ON1_ON20x5:
8240 case ID_LED_OFF1_ON20x8:
8241 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
8242 hw->ledctl_mode2 |= ledctl_on << (i << 3);
8243 break;
8244 case ID_LED_DEF1_OFF20x3:
8245 case ID_LED_ON1_OFF20x6:
8246 case ID_LED_OFF1_OFF20x9:
8247 hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
8248 hw->ledctl_mode2 |= ledctl_off << (i << 3);
8249 break;
8250 default:
8251 /* Do nothing */
8252 break;
8253 }
8254 }
8255 return E1000_SUCCESS0;
8256}
8257
8258/******************************************************************************
8259 * Clears all hardware statistics counters.
8260 *
8261 * hw - Struct containing variables accessed by shared code
8262 *****************************************************************************/
8263void
8264em_clear_hw_cntrs(struct em_hw *hw)
8265{
8266 volatile uint32_t temp;
8267 temp = E1000_READ_REG(hw, CRCERRS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04000 : em_translate_82542_register
(0x04000)))));
8268 temp = E1000_READ_REG(hw, SYMERRS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04008 : em_translate_82542_register
(0x04008)))));
8269 temp = E1000_READ_REG(hw, MPC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04010 : em_translate_82542_register
(0x04010)))));
8270 temp = E1000_READ_REG(hw, SCC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04014 : em_translate_82542_register
(0x04014)))));
8271 temp = E1000_READ_REG(hw, ECOL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04018 : em_translate_82542_register
(0x04018)))));
8272 temp = E1000_READ_REG(hw, MCC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0401C : em_translate_82542_register
(0x0401C)))));
8273 temp = E1000_READ_REG(hw, LATECOL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04020 : em_translate_82542_register
(0x04020)))));
8274 temp = E1000_READ_REG(hw, COLC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04028 : em_translate_82542_register
(0x04028)))));
8275 temp = E1000_READ_REG(hw, DC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04030 : em_translate_82542_register
(0x04030)))));
8276 temp = E1000_READ_REG(hw, SEC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04038 : em_translate_82542_register
(0x04038)))));
8277 temp = E1000_READ_REG(hw, RLEC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04040 : em_translate_82542_register
(0x04040)))));
8278 temp = E1000_READ_REG(hw, XONRXC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04048 : em_translate_82542_register
(0x04048)))));
8279 temp = E1000_READ_REG(hw, XONTXC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0404C : em_translate_82542_register
(0x0404C)))));
8280 temp = E1000_READ_REG(hw, XOFFRXC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04050 : em_translate_82542_register
(0x04050)))));
8281 temp = E1000_READ_REG(hw, XOFFTXC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04054 : em_translate_82542_register
(0x04054)))));
8282 temp = E1000_READ_REG(hw, FCRUC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04058 : em_translate_82542_register
(0x04058)))));
8283
8284 if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
8285 temp = E1000_READ_REG(hw, PRC64)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0405C : em_translate_82542_register
(0x0405C)))));
8286 temp = E1000_READ_REG(hw, PRC127)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04060 : em_translate_82542_register
(0x04060)))));
8287 temp = E1000_READ_REG(hw, PRC255)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04064 : em_translate_82542_register
(0x04064)))));
8288 temp = E1000_READ_REG(hw, PRC511)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04068 : em_translate_82542_register
(0x04068)))));
8289 temp = E1000_READ_REG(hw, PRC1023)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0406C : em_translate_82542_register
(0x0406C)))));
8290 temp = E1000_READ_REG(hw, PRC1522)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04070 : em_translate_82542_register
(0x04070)))));
8291 }
8292 temp = E1000_READ_REG(hw, GPRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04074 : em_translate_82542_register
(0x04074)))));
8293 temp = E1000_READ_REG(hw, BPRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04078 : em_translate_82542_register
(0x04078)))));
8294 temp = E1000_READ_REG(hw, MPRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0407C : em_translate_82542_register
(0x0407C)))));
8295 temp = E1000_READ_REG(hw, GPTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04080 : em_translate_82542_register
(0x04080)))));
8296 temp = E1000_READ_REG(hw, GORCL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04088 : em_translate_82542_register
(0x04088)))));
8297 temp = E1000_READ_REG(hw, GORCH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0408C : em_translate_82542_register
(0x0408C)))));
8298 temp = E1000_READ_REG(hw, GOTCL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04090 : em_translate_82542_register
(0x04090)))));
8299 temp = E1000_READ_REG(hw, GOTCH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04094 : em_translate_82542_register
(0x04094)))));
8300 temp = E1000_READ_REG(hw, RNBC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040A0 : em_translate_82542_register
(0x040A0)))));
8301 temp = E1000_READ_REG(hw, RUC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040A4 : em_translate_82542_register
(0x040A4)))));
8302 temp = E1000_READ_REG(hw, RFC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040A8 : em_translate_82542_register
(0x040A8)))));
8303 temp = E1000_READ_REG(hw, ROC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040AC : em_translate_82542_register
(0x040AC)))));
8304 temp = E1000_READ_REG(hw, RJC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040B0 : em_translate_82542_register
(0x040B0)))));
8305 temp = E1000_READ_REG(hw, TORL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040C0 : em_translate_82542_register
(0x040C0)))));
8306 temp = E1000_READ_REG(hw, TORH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040C4 : em_translate_82542_register
(0x040C4)))));
8307 temp = E1000_READ_REG(hw, TOTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040C8 : em_translate_82542_register
(0x040C8)))));
8308 temp = E1000_READ_REG(hw, TOTH)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040CC : em_translate_82542_register
(0x040CC)))));
8309 temp = E1000_READ_REG(hw, TPR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040D0 : em_translate_82542_register
(0x040D0)))));
8310 temp = E1000_READ_REG(hw, TPT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040D4 : em_translate_82542_register
(0x040D4)))));
8311
8312 if (!IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
8313 temp = E1000_READ_REG(hw, PTC64)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040D8 : em_translate_82542_register
(0x040D8)))));
8314 temp = E1000_READ_REG(hw, PTC127)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040DC : em_translate_82542_register
(0x040DC)))));
8315 temp = E1000_READ_REG(hw, PTC255)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040E0 : em_translate_82542_register
(0x040E0)))));
8316 temp = E1000_READ_REG(hw, PTC511)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040E4 : em_translate_82542_register
(0x040E4)))));
8317 temp = E1000_READ_REG(hw, PTC1023)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040E8 : em_translate_82542_register
(0x040E8)))));
8318 temp = E1000_READ_REG(hw, PTC1522)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040EC : em_translate_82542_register
(0x040EC)))));
8319 }
8320 temp = E1000_READ_REG(hw, MPTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040F0 : em_translate_82542_register
(0x040F0)))));
8321 temp = E1000_READ_REG(hw, BPTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040F4 : em_translate_82542_register
(0x040F4)))));
8322
8323 if (hw->mac_type < em_82543)
8324 return;
8325
8326 temp = E1000_READ_REG(hw, ALGNERRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04004 : em_translate_82542_register
(0x04004)))));
8327 temp = E1000_READ_REG(hw, RXERRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0400C : em_translate_82542_register
(0x0400C)))));
8328 temp = E1000_READ_REG(hw, TNCRS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04034 : em_translate_82542_register
(0x04034)))));
8329 temp = E1000_READ_REG(hw, CEXTERR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0403C : em_translate_82542_register
(0x0403C)))));
8330 temp = E1000_READ_REG(hw, TSCTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040F8 : em_translate_82542_register
(0x040F8)))));
8331 temp = E1000_READ_REG(hw, TSCTFC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040FC : em_translate_82542_register
(0x040FC)))));
8332
8333 if (hw->mac_type <= em_82544
8334 || hw->mac_type == em_icp_xxxx)
8335 return;
8336
8337 temp = E1000_READ_REG(hw, MGTPRC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040B4 : em_translate_82542_register
(0x040B4)))));
8338 temp = E1000_READ_REG(hw, MGTPDC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040B8 : em_translate_82542_register
(0x040B8)))));
8339 temp = E1000_READ_REG(hw, MGTPTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x040BC : em_translate_82542_register
(0x040BC)))));
8340
8341 if (hw->mac_type <= em_82547_rev_2)
8342 return;
8343
8344 temp = E1000_READ_REG(hw, IAC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04100 : em_translate_82542_register
(0x04100)))));
8345 temp = E1000_READ_REG(hw, ICRXOC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04124 : em_translate_82542_register
(0x04124)))));
8346
8347 if (hw->phy_type == em_phy_82577 ||
8348 hw->phy_type == em_phy_82578 ||
8349 hw->phy_type == em_phy_82579 ||
8350 hw->phy_type == em_phy_i217) {
8351 uint16_t phy_data;
8352
8353 em_read_phy_reg(hw, HV_SCC_UPPER(((778) << 5) | ((16) & 0x1F)), &phy_data);
8354 em_read_phy_reg(hw, HV_SCC_LOWER(((778) << 5) | ((17) & 0x1F)), &phy_data);
8355 em_read_phy_reg(hw, HV_ECOL_UPPER(((778) << 5) | ((18) & 0x1F)), &phy_data);
8356 em_read_phy_reg(hw, HV_ECOL_LOWER(((778) << 5) | ((19) & 0x1F)), &phy_data);
8357 em_read_phy_reg(hw, HV_MCC_UPPER(((778) << 5) | ((20) & 0x1F)), &phy_data);
8358 em_read_phy_reg(hw, HV_MCC_LOWER(((778) << 5) | ((21) & 0x1F)), &phy_data);
8359 em_read_phy_reg(hw, HV_LATECOL_UPPER(((778) << 5) | ((23) & 0x1F)), &phy_data);
8360 em_read_phy_reg(hw, HV_LATECOL_LOWER(((778) << 5) | ((24) & 0x1F)), &phy_data);
8361 em_read_phy_reg(hw, HV_COLC_UPPER(((778) << 5) | ((25) & 0x1F)), &phy_data);
8362 em_read_phy_reg(hw, HV_COLC_LOWER(((778) << 5) | ((26) & 0x1F)), &phy_data);
8363 em_read_phy_reg(hw, HV_DC_UPPER(((778) << 5) | ((27) & 0x1F)), &phy_data);
8364 em_read_phy_reg(hw, HV_DC_LOWER(((778) << 5) | ((28) & 0x1F)), &phy_data);
8365 em_read_phy_reg(hw, HV_TNCRS_UPPER(((778) << 5) | ((29) & 0x1F)), &phy_data);
8366 em_read_phy_reg(hw, HV_TNCRS_LOWER(((778) << 5) | ((30) & 0x1F)), &phy_data);
8367 }
8368
8369 if (hw->mac_type == em_ich8lan ||
8370 hw->mac_type == em_ich9lan ||
8371 hw->mac_type == em_ich10lan ||
8372 hw->mac_type == em_pchlan ||
8373 (hw->mac_type != em_pch2lan && hw->mac_type != em_pch_lpt &&
8374 hw->mac_type != em_pch_spt && hw->mac_type != em_pch_cnp &&
8375 hw->mac_type != em_pch_tgp && hw->mac_type != em_pch_adp))
8376 return;
8377
8378 temp = E1000_READ_REG(hw, ICRXPTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04104 : em_translate_82542_register
(0x04104)))));
8379 temp = E1000_READ_REG(hw, ICRXATC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04108 : em_translate_82542_register
(0x04108)))));
8380 temp = E1000_READ_REG(hw, ICTXPTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0410C : em_translate_82542_register
(0x0410C)))));
8381 temp = E1000_READ_REG(hw, ICTXATC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04110 : em_translate_82542_register
(0x04110)))));
8382 temp = E1000_READ_REG(hw, ICTXQEC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04118 : em_translate_82542_register
(0x04118)))));
8383 temp = E1000_READ_REG(hw, ICTXQMTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x0411C : em_translate_82542_register
(0x0411C)))));
8384 temp = E1000_READ_REG(hw, ICRXDMTC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x04120 : em_translate_82542_register
(0x04120)))));
8385}
8386
8387/******************************************************************************
8388 * Gets the current PCI bus type, speed, and width of the hardware
8389 *
8390 * hw - Struct containing variables accessed by shared code
8391 *****************************************************************************/
8392void
8393em_get_bus_info(struct em_hw *hw)
8394{
8395 int32_t ret_val;
8396 uint16_t pci_ex_link_status;
8397 uint32_t status;
8398 switch (hw->mac_type) {
8399 case em_82542_rev2_0:
8400 case em_82542_rev2_1:
8401 hw->bus_type = em_bus_type_unknown;
8402 hw->bus_speed = em_bus_speed_unknown;
8403 hw->bus_width = em_bus_width_unknown;
8404 break;
8405 case em_icp_xxxx:
8406 hw->bus_type = em_bus_type_cpp;
8407 hw->bus_speed = em_bus_speed_unknown;
8408 hw->bus_width = em_bus_width_unknown;
8409 break;
8410 case em_82571:
8411 case em_82572:
8412 case em_82573:
8413 case em_82574:
8414 case em_82575:
8415 case em_82576:
8416 case em_82580:
8417 case em_80003es2lan:
8418 case em_i210:
8419 case em_i350:
8420 hw->bus_type = em_bus_type_pci_express;
8421 hw->bus_speed = em_bus_speed_2500;
8422 ret_val = em_read_pcie_cap_reg(hw, PCI_EX_LINK_STATUS0x12,
8423 &pci_ex_link_status);
8424 if (ret_val)
8425 hw->bus_width = em_bus_width_unknown;
8426 else
8427 hw->bus_width = (pci_ex_link_status &
8428 PCI_EX_LINK_WIDTH_MASK0x3F0) >> PCI_EX_LINK_WIDTH_SHIFT4;
8429 break;
8430 case em_ich8lan:
8431 case em_ich9lan:
8432 case em_ich10lan:
8433 case em_pchlan:
8434 case em_pch2lan:
8435 case em_pch_lpt:
8436 case em_pch_spt:
8437 case em_pch_cnp:
8438 case em_pch_tgp:
8439 case em_pch_adp:
8440 hw->bus_type = em_bus_type_pci_express;
8441 hw->bus_speed = em_bus_speed_2500;
8442 hw->bus_width = em_bus_width_pciex_1;
8443 break;
8444 default:
8445 status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
8446 hw->bus_type = (status & E1000_STATUS_PCIX_MODE0x00002000) ?
8447 em_bus_type_pcix : em_bus_type_pci;
8448
8449 if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER0x101D) {
8450 hw->bus_speed = (hw->bus_type == em_bus_type_pci) ?
8451 em_bus_speed_66 : em_bus_speed_120;
8452 } else if (hw->bus_type == em_bus_type_pci) {
8453 hw->bus_speed = (status & E1000_STATUS_PCI660x00000800) ?
8454 em_bus_speed_66 : em_bus_speed_33;
8455 } else {
8456 switch (status & E1000_STATUS_PCIX_SPEED0x0000C000) {
8457 case E1000_STATUS_PCIX_SPEED_660x00000000:
8458 hw->bus_speed = em_bus_speed_66;
8459 break;
8460 case E1000_STATUS_PCIX_SPEED_1000x00004000:
8461 hw->bus_speed = em_bus_speed_100;
8462 break;
8463 case E1000_STATUS_PCIX_SPEED_1330x00008000:
8464 hw->bus_speed = em_bus_speed_133;
8465 break;
8466 default:
8467 hw->bus_speed = em_bus_speed_reserved;
8468 break;
8469 }
8470 }
8471 hw->bus_width = (status & E1000_STATUS_BUS640x00001000) ?
8472 em_bus_width_64 : em_bus_width_32;
8473 break;
8474 }
8475}
8476
8477/******************************************************************************
8478 * Writes a value to one of the devices registers using port I/O (as opposed to
8479 * memory mapped I/O). Only 82544 and newer devices support port I/O.
8480 *
8481 * hw - Struct containing variables accessed by shared code
8482 * offset - offset to write to
8483 * value - value to write
8484 *****************************************************************************/
8485STATIC void
8486em_write_reg_io(struct em_hw *hw, uint32_t offset, uint32_t value)
8487{
8488 unsigned long io_addr = hw->io_base;
8489 unsigned long io_data = hw->io_base + 4;
8490 em_io_write(hw, io_addr, offset)((((struct em_osdep *)(hw)->back)->io_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->io_bus_space_handle
), ((io_addr)), ((offset))));
8491 em_io_write(hw, io_data, value)((((struct em_osdep *)(hw)->back)->io_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->io_bus_space_handle
), ((io_data)), ((value))));
8492}
8493
8494/******************************************************************************
8495 * Estimates the cable length.
8496 *
8497 * hw - Struct containing variables accessed by shared code
8498 * min_length - The estimated minimum length
8499 * max_length - The estimated maximum length
8500 *
8501 * returns: - E1000_ERR_XXX
8502 * E1000_SUCCESS
8503 *
8504 * This function always returns a ranged length (minimum & maximum).
8505 * So for M88 phy's, this function interprets the one value returned from the
8506 * register to the minimum and maximum range.
8507 * For IGP phy's, the function calculates the range by the AGC registers.
8508 *****************************************************************************/
8509STATIC int32_t
8510em_get_cable_length(struct em_hw *hw, uint16_t *min_length,
8511 uint16_t *max_length)
8512{
8513 int32_t ret_val;
8514 uint16_t agc_value = 0;
8515 uint16_t i, phy_data;
8516 uint16_t cable_length;
8517 DEBUGFUNC("em_get_cable_length");;
8518
8519 *min_length = *max_length = 0;
8520
8521 /* Use old method for Phy older than IGP */
8522 if (hw->phy_type == em_phy_m88 ||
8523 hw->phy_type == em_phy_oem ||
8524 hw->phy_type == em_phy_82578) {
8525
8526 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS0x11,
8527 &phy_data);
8528 if (ret_val)
8529 return ret_val;
8530 cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH0x0380) >>
8531 M88E1000_PSSR_CABLE_LENGTH_SHIFT7;
8532
8533 /* Convert the enum value to ranged values */
8534 switch (cable_length) {
8535 case em_cable_length_50:
8536 *min_length = 0;
8537 *max_length = em_igp_cable_length_50;
8538 break;
8539 case em_cable_length_50_80:
8540 *min_length = em_igp_cable_length_50;
8541 *max_length = em_igp_cable_length_80;
8542 break;
8543 case em_cable_length_80_110:
8544 *min_length = em_igp_cable_length_80;
8545 *max_length = em_igp_cable_length_110;
8546 break;
8547 case em_cable_length_110_140:
8548 *min_length = em_igp_cable_length_110;
8549 *max_length = em_igp_cable_length_140;
8550 break;
8551 case em_cable_length_140:
8552 *min_length = em_igp_cable_length_140;
8553 *max_length = em_igp_cable_length_170;
8554 break;
8555 default:
8556 return -E1000_ERR_PHY2;
8557 break;
8558 }
8559 } else if (hw->phy_type == em_phy_rtl8211) {
8560 /* no cable length info on RTL8211, fake */
8561 *min_length = 0;
8562 *max_length = em_igp_cable_length_50;
8563 } else if (hw->phy_type == em_phy_gg82563) {
8564 ret_val = em_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE(((5) << 5) | ((26) & 0x1F)),
8565 &phy_data);
8566 if (ret_val)
8567 return ret_val;
8568 cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH0x0007;
8569
8570 switch (cable_length) {
8571 case em_gg_cable_length_60:
8572 *min_length = 0;
8573 *max_length = em_igp_cable_length_60;
8574 break;
8575 case em_gg_cable_length_60_115:
8576 *min_length = em_igp_cable_length_60;
8577 *max_length = em_igp_cable_length_115;
8578 break;
8579 case em_gg_cable_length_115_150:
8580 *min_length = em_igp_cable_length_115;
8581 *max_length = em_igp_cable_length_150;
8582 break;
8583 case em_gg_cable_length_150:
8584 *min_length = em_igp_cable_length_150;
8585 *max_length = em_igp_cable_length_180;
8586 break;
8587 default:
8588 return -E1000_ERR_PHY2;
8589 break;
8590 }
8591 } else if (hw->phy_type == em_phy_igp) { /* For IGP PHY */
8592 uint16_t cur_agc_value;
8593 uint16_t min_agc_value =
8594 IGP01E1000_AGC_LENGTH_TABLE_SIZE128;
8595 uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM4] =
8596 {IGP01E1000_PHY_AGC_A0x1172, IGP01E1000_PHY_AGC_B0x1272,
8597 IGP01E1000_PHY_AGC_C0x1472, IGP01E1000_PHY_AGC_D0x1872};
8598
8599 /* Read the AGC registers for all channels */
8600 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM4; i++) {
8601 ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8602 &phy_data);
8603 if (ret_val)
8604 return ret_val;
8605
8606 cur_agc_value = phy_data >>
8607 IGP01E1000_AGC_LENGTH_SHIFT7;
8608
8609 /* Value bound check. */
8610 if ((cur_agc_value >=
8611 IGP01E1000_AGC_LENGTH_TABLE_SIZE128 - 1) ||
8612 (cur_agc_value == 0))
8613 return -E1000_ERR_PHY2;
8614
8615 agc_value += cur_agc_value;
8616
8617 /* Update minimal AGC value. */
8618 if (min_agc_value > cur_agc_value)
8619 min_agc_value = cur_agc_value;
8620 }
8621
8622 /* Remove the minimal AGC result for length < 50m */
8623 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM4 *
8624 em_igp_cable_length_50) {
8625 agc_value -= min_agc_value;
8626
8627 /*
8628 * Get the average length of the remaining 3 channels
8629 */
8630 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM4 - 1);
8631 } else {
8632 /* Get the average length of all the 4 channels. */
8633 agc_value /= IGP01E1000_PHY_CHANNEL_NUM4;
8634 }
8635
8636 /* Set the range of the calculated length. */
8637 *min_length = ((em_igp_cable_length_table[agc_value] -
8638 IGP01E1000_AGC_RANGE10) > 0) ?
8639 (em_igp_cable_length_table[agc_value] -
8640 IGP01E1000_AGC_RANGE10) : 0;
8641 *max_length = em_igp_cable_length_table[agc_value] +
8642 IGP01E1000_AGC_RANGE10;
8643 } else if (hw->phy_type == em_phy_igp_2 ||
8644 hw->phy_type == em_phy_igp_3) {
8645 uint16_t cur_agc_index, max_agc_index = 0;
8646 uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE113 - 1;
8647 uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM4] =
8648 {IGP02E1000_PHY_AGC_A0x11B1, IGP02E1000_PHY_AGC_B0x12B1,
8649 IGP02E1000_PHY_AGC_C0x14B1, IGP02E1000_PHY_AGC_D0x18B1};
8650 /* Read the AGC registers for all channels */
8651 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM4; i++) {
8652 ret_val = em_read_phy_reg(hw, agc_reg_array[i],
8653 &phy_data);
8654 if (ret_val)
8655 return ret_val;
8656 /*
8657 * Getting bits 15:9, which represent the combination
8658 * of course and fine gain values. The result is a
8659 * number that can be put into the lookup table to
8660 * obtain the approximate cable length.
8661 */
8662 cur_agc_index = (phy_data >>
8663 IGP02E1000_AGC_LENGTH_SHIFT9) &
8664 IGP02E1000_AGC_LENGTH_MASK0x7F;
8665
8666 /* Array index bound check. */
8667 if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE113)
8668 || (cur_agc_index == 0))
8669 return -E1000_ERR_PHY2;
8670
8671 /* Remove min & max AGC values from calculation. */
8672 if (em_igp_2_cable_length_table[min_agc_index] >
8673 em_igp_2_cable_length_table[cur_agc_index])
8674 min_agc_index = cur_agc_index;
8675 if (em_igp_2_cable_length_table[max_agc_index] <
8676 em_igp_2_cable_length_table[cur_agc_index])
8677 max_agc_index = cur_agc_index;
8678
8679 agc_value += em_igp_2_cable_length_table
8680 [cur_agc_index];
8681 }
8682
8683 agc_value -= (em_igp_2_cable_length_table[min_agc_index] +
8684 em_igp_2_cable_length_table[max_agc_index]);
8685 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM4 - 2);
8686 /*
8687 * Calculate cable length with the error range of +/- 10
8688 * meters.
8689 */
8690 *min_length = ((agc_value - IGP02E1000_AGC_RANGE15) > 0) ?
8691 (agc_value - IGP02E1000_AGC_RANGE15) : 0;
8692 *max_length = agc_value + IGP02E1000_AGC_RANGE15;
8693 }
8694 return E1000_SUCCESS0;
8695}
8696
8697/******************************************************************************
8698 * Check if Downshift occurred
8699 *
8700 * hw - Struct containing variables accessed by shared code
8701 * downshift - output parameter : 0 - No Downshift occurred.
8702 * 1 - Downshift occurred.
8703 *
8704 * returns: - E1000_ERR_XXX
8705 * E1000_SUCCESS
8706 *
8707 * For phy's older then IGP, this function reads the Downshift bit in the Phy
8708 * Specific Status register. For IGP phy's, it reads the Downgrade bit in the
8709 * Link Health register. In IGP this bit is latched high, so the driver must
8710 * read it immediately after link is established.
8711 *****************************************************************************/
8712STATIC int32_t
8713em_check_downshift(struct em_hw *hw)
8714{
8715 int32_t ret_val;
8716 uint16_t phy_data;
8717 DEBUGFUNC("em_check_downshift");;
8718
8719 if (hw->phy_type == em_phy_igp ||
8720 hw->phy_type == em_phy_igp_3 ||
8721 hw->phy_type == em_phy_igp_2) {
8722 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH0x13,
8723 &phy_data);
8724 if (ret_val)
8725 return ret_val;
8726
8727 hw->speed_downgraded = (phy_data &
8728 IGP01E1000_PLHR_SS_DOWNGRADE0x8000) ? 1 : 0;
8729 } else if ((hw->phy_type == em_phy_m88) ||
8730 (hw->phy_type == em_phy_gg82563) ||
8731 (hw->phy_type == em_phy_oem) ||
8732 (hw->phy_type == em_phy_82578)) {
8733 ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS0x11,
8734 &phy_data);
8735 if (ret_val)
8736 return ret_val;
8737
8738 hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT0x0020) >>
8739 M88E1000_PSSR_DOWNSHIFT_SHIFT5;
8740 } else if (hw->phy_type == em_phy_ife) {
8741 /* em_phy_ife supports 10/100 speed only */
8742 hw->speed_downgraded = FALSE0;
8743 }
8744 return E1000_SUCCESS0;
8745}
8746
8747/*****************************************************************************
8748 *
8749 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
8750 * gigabit link is achieved to improve link quality.
8751 *
8752 * hw: Struct containing variables accessed by shared code
8753 *
8754 * returns: - E1000_ERR_PHY if fail to read/write the PHY
8755 * E1000_SUCCESS at any other case.
8756 *
8757 ****************************************************************************/
8758STATIC int32_t
8759em_config_dsp_after_link_change(struct em_hw *hw, boolean_t link_up)
8760{
8761 int32_t ret_val;
8762 uint16_t phy_data, phy_saved_data, speed, duplex, i;
8763 uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM4] =
8764 {IGP01E1000_PHY_AGC_PARAM_A0x1171, IGP01E1000_PHY_AGC_PARAM_B0x1271,
8765 IGP01E1000_PHY_AGC_PARAM_C0x1471, IGP01E1000_PHY_AGC_PARAM_D0x1871};
8766 uint16_t min_length, max_length;
8767 DEBUGFUNC("em_config_dsp_after_link_change");;
8768
8769 if (hw->phy_type != em_phy_igp)
8770 return E1000_SUCCESS0;
8771
8772 if (link_up) {
8773 ret_val = em_get_speed_and_duplex(hw, &speed, &duplex);
8774 if (ret_val) {
8775 DEBUGOUT("Error getting link speed and duplex\n");
8776 return ret_val;
8777 }
8778 if (speed == SPEED_10001000) {
8779
8780 ret_val = em_get_cable_length(hw, &min_length, &max_length);
8781 if (ret_val)
8782 return ret_val;
8783
8784 if ((hw->dsp_config_state == em_dsp_config_enabled) &&
8785 min_length >= em_igp_cable_length_50) {
8786
8787 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM4;
8788 i++) {
8789 ret_val = em_read_phy_reg(hw,
8790 dsp_reg_array[i], &phy_data);
8791 if (ret_val)
8792 return ret_val;
8793
8794 phy_data &=
8795 ~IGP01E1000_PHY_EDAC_MU_INDEX0xC000;
8796
8797 ret_val = em_write_phy_reg(hw,
8798 dsp_reg_array[i], phy_data);
8799 if (ret_val)
8800 return ret_val;
8801 }
8802 hw->dsp_config_state = em_dsp_config_activated;
8803 }
8804 if ((hw->ffe_config_state == em_ffe_config_enabled) &&
8805 (min_length < em_igp_cable_length_50)) {
8806
8807 uint16_t ffe_idle_err_timeout =
8808 FFE_IDLE_ERR_COUNT_TIMEOUT_2020;
8809 uint32_t idle_errs = 0;
8810 /* clear previous idle error counts */
8811 ret_val = em_read_phy_reg(hw, PHY_1000T_STATUS0x0A,
8812 &phy_data);
8813 if (ret_val)
8814 return ret_val;
8815
8816 for (i = 0; i < ffe_idle_err_timeout; i++) {
8817 usec_delay(1000)(*delay_func)(1000);
8818 ret_val = em_read_phy_reg(hw,
8819 PHY_1000T_STATUS0x0A, &phy_data);
8820 if (ret_val)
8821 return ret_val;
8822
8823 idle_errs += (phy_data &
8824 SR_1000T_IDLE_ERROR_CNT0x00FF);
8825 if (idle_errs >
8826 SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT5) {
8827 hw->ffe_config_state =
8828 em_ffe_config_active;
8829
8830 ret_val = em_write_phy_reg(hw,
8831 IGP01E1000_PHY_DSP_FFE0x1F35,
8832 IGP01E1000_PHY_DSP_FFE_CM_CP0x0069);
8833 if (ret_val)
8834 return ret_val;
8835 break;
8836 }
8837 if (idle_errs)
8838 ffe_idle_err_timeout =
8839 FFE_IDLE_ERR_COUNT_TIMEOUT_100100;
8840 }
8841 }
8842 }
8843 } else {
8844 if (hw->dsp_config_state == em_dsp_config_activated) {
8845 /*
8846 * Save off the current value of register 0x2F5B to
8847 * be restored at the end of the routines.
8848 */
8849 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8850
8851 if (ret_val)
8852 return ret_val;
8853
8854 /* Disable the PHY transmitter */
8855 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8856
8857 if (ret_val)
8858 return ret_val;
8859
8860 msec_delay_irq(20)(*delay_func)(1000*(20));
8861
8862 ret_val = em_write_phy_reg(hw, 0x0000,
8863 IGP01E1000_IEEE_FORCE_GIGA0x0140);
8864 if (ret_val)
8865 return ret_val;
8866 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM4; i++) {
8867 ret_val = em_read_phy_reg(hw, dsp_reg_array[i],
8868 &phy_data);
8869 if (ret_val)
8870 return ret_val;
8871
8872 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX0xC000;
8873 phy_data |=
8874 IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS0x8000;
8875
8876 ret_val = em_write_phy_reg(hw,
8877 dsp_reg_array[i], phy_data);
8878 if (ret_val)
8879 return ret_val;
8880 }
8881
8882 ret_val = em_write_phy_reg(hw, 0x0000,
8883 IGP01E1000_IEEE_RESTART_AUTONEG0x3300);
8884 if (ret_val)
8885 return ret_val;
8886
8887 msec_delay_irq(20)(*delay_func)(1000*(20));
8888
8889 /* Now enable the transmitter */
8890 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8891
8892 if (ret_val)
8893 return ret_val;
8894
8895 hw->dsp_config_state = em_dsp_config_enabled;
8896 }
8897 if (hw->ffe_config_state == em_ffe_config_active) {
8898 /*
8899 * Save off the current value of register 0x2F5B to
8900 * be restored at the end of the routines.
8901 */
8902 ret_val = em_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
8903
8904 if (ret_val)
8905 return ret_val;
8906
8907 /* Disable the PHY transmitter */
8908 ret_val = em_write_phy_reg(hw, 0x2F5B, 0x0003);
8909
8910 if (ret_val)
8911 return ret_val;
8912
8913 msec_delay_irq(20)(*delay_func)(1000*(20));
8914
8915 ret_val = em_write_phy_reg(hw, 0x0000,
8916 IGP01E1000_IEEE_FORCE_GIGA0x0140);
8917 if (ret_val)
8918 return ret_val;
8919 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE0x1F35,
8920 IGP01E1000_PHY_DSP_FFE_DEFAULT0x002A);
8921 if (ret_val)
8922 return ret_val;
8923
8924 ret_val = em_write_phy_reg(hw, 0x0000,
8925 IGP01E1000_IEEE_RESTART_AUTONEG0x3300);
8926 if (ret_val)
8927 return ret_val;
8928
8929 msec_delay_irq(20)(*delay_func)(1000*(20));
8930
8931 /* Now enable the transmitter */
8932 ret_val = em_write_phy_reg(hw, 0x2F5B, phy_saved_data);
8933
8934 if (ret_val)
8935 return ret_val;
8936
8937 hw->ffe_config_state = em_ffe_config_enabled;
8938 }
8939 }
8940 return E1000_SUCCESS0;
8941}
8942
8943/*****************************************************************************
8944 * Set PHY to class A mode
8945 * Assumes the following operations will follow to enable the new class mode.
8946 * 1. Do a PHY soft reset
8947 * 2. Restart auto-negotiation or force link.
8948 *
8949 * hw - Struct containing variables accessed by shared code
8950 ****************************************************************************/
8951static int32_t
8952em_set_phy_mode(struct em_hw *hw)
8953{
8954 int32_t ret_val;
8955 uint16_t eeprom_data;
8956 DEBUGFUNC("em_set_phy_mode");;
8957
8958 if ((hw->mac_type == em_82545_rev_3) &&
8959 (hw->media_type == em_media_type_copper)) {
8960 ret_val = em_read_eeprom(hw, EEPROM_PHY_CLASS_WORD0x0007, 1,
8961 &eeprom_data);
8962 if (ret_val) {
8963 return ret_val;
8964 }
8965 if ((eeprom_data != EEPROM_RESERVED_WORD0xFFFF) &&
8966 (eeprom_data & EEPROM_PHY_CLASS_A0x8000)) {
8967 ret_val = em_write_phy_reg(hw,
8968 M88E1000_PHY_PAGE_SELECT0x1D, 0x000B);
8969 if (ret_val)
8970 return ret_val;
8971 ret_val = em_write_phy_reg(hw,
8972 M88E1000_PHY_GEN_CONTROL0x1E, 0x8104);
8973 if (ret_val)
8974 return ret_val;
8975
8976 hw->phy_reset_disable = FALSE0;
8977 }
8978 }
8979 return E1000_SUCCESS0;
8980}
8981
8982/*****************************************************************************
8983 *
8984 * This function sets the lplu state according to the active flag. When
8985 * activating lplu this function also disables smart speed and vise versa.
8986 * lplu will not be activated unless the device autonegotiation advertisement
8987 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
8988 * hw: Struct containing variables accessed by shared code
8989 * active - true to enable lplu false to disable lplu.
8990 *
8991 * returns: - E1000_ERR_PHY if fail to read/write the PHY
8992 * E1000_SUCCESS at any other case.
8993 *
8994 ****************************************************************************/
8995STATIC int32_t
8996em_set_d3_lplu_state(struct em_hw *hw, boolean_t active)
8997{
8998 uint32_t phy_ctrl = 0;
8999 int32_t ret_val;
9000 uint16_t phy_data;
9001 DEBUGFUNC("em_set_d3_lplu_state");;
9002
9003 if (hw->phy_type != em_phy_igp && hw->phy_type != em_phy_igp_2
9004 && hw->phy_type != em_phy_igp_3)
9005 return E1000_SUCCESS0;
9006 /*
9007 * During driver activity LPLU should not be used or it will attain
9008 * link from the lowest speeds starting from 10Mbps. The capability
9009 * is used for Dx transitions and states
9010 */
9011 if (hw->mac_type == em_82541_rev_2 || hw->mac_type == em_82547_rev_2) {
9012 ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO0x14, &phy_data);
9013 if (ret_val)
9014 return ret_val;
9015 } else if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9016 /*
9017 * MAC writes into PHY register based on the state transition
9018 * and start auto-negotiation. SW driver can overwrite the
9019 * settings in CSR PHY power control E1000_PHY_CTRL register.
9020 */
9021 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10)))));
9022 } else {
9023 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT0x19,
9024 &phy_data);
9025 if (ret_val)
9026 return ret_val;
9027 }
9028
9029 if (!active) {
9030 if (hw->mac_type == em_82541_rev_2 ||
9031 hw->mac_type == em_82547_rev_2) {
9032 phy_data &= ~IGP01E1000_GMII_FLEX_SPD0x10;
9033 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO0x14,
9034 phy_data);
9035 if (ret_val)
9036 return ret_val;
9037 } else {
9038 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9039 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU0x00000004;
9040 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10))), (phy_ctrl)));
9041 } else {
9042 phy_data &= ~IGP02E1000_PM_D3_LPLU0x0004;
9043 ret_val = em_write_phy_reg(hw,
9044 IGP02E1000_PHY_POWER_MGMT0x19, phy_data);
9045 if (ret_val)
9046 return ret_val;
9047 }
9048 }
9049 /*
9050 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
9051 * during Dx states where the power conservation is most
9052 * important. During driver activity we should enable
9053 * SmartSpeed, so performance is maintained.
9054 */
9055 if (hw->smart_speed == em_smart_speed_on) {
9056 ret_val = em_read_phy_reg(hw,
9057 IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data);
9058 if (ret_val)
9059 return ret_val;
9060
9061 phy_data |= IGP01E1000_PSCFR_SMART_SPEED0x0080;
9062 ret_val = em_write_phy_reg(hw,
9063 IGP01E1000_PHY_PORT_CONFIG0x10, phy_data);
9064 if (ret_val)
9065 return ret_val;
9066 } else if (hw->smart_speed == em_smart_speed_off) {
9067 ret_val = em_read_phy_reg(hw,
9068 IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data);
9069 if (ret_val)
9070 return ret_val;
9071
9072 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080;
9073 ret_val = em_write_phy_reg(hw,
9074 IGP01E1000_PHY_PORT_CONFIG0x10, phy_data);
9075 if (ret_val)
9076 return ret_val;
9077 }
9078 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT0x002F)
9079 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL0x0003) ||
9080 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL0x000F)) {
9081
9082 if (hw->mac_type == em_82541_rev_2 ||
9083 hw->mac_type == em_82547_rev_2) {
9084 phy_data |= IGP01E1000_GMII_FLEX_SPD0x10;
9085 ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO0x14,
9086 phy_data);
9087 if (ret_val)
9088 return ret_val;
9089 } else {
9090 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9091 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU0x00000004;
9092 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10))), (phy_ctrl)));
9093 } else {
9094 phy_data |= IGP02E1000_PM_D3_LPLU0x0004;
9095 ret_val = em_write_phy_reg(hw,
9096 IGP02E1000_PHY_POWER_MGMT0x19, phy_data);
9097 if (ret_val)
9098 return ret_val;
9099 }
9100 }
9101
9102 /* When LPLU is enabled we should disable SmartSpeed */
9103 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG0x10,
9104 &phy_data);
9105 if (ret_val)
9106 return ret_val;
9107
9108 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080;
9109 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG0x10,
9110 phy_data);
9111 if (ret_val)
9112 return ret_val;
9113
9114 }
9115 return E1000_SUCCESS0;
9116}
9117
9118/*****************************************************************************
9119 *
9120 * This function sets the lplu d0 state according to the active flag. When
9121 * activating lplu this function also disables smart speed and vise versa.
9122 * lplu will not be activated unless the device autonegotiation advertisement
9123 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
9124 * hw: Struct containing variables accessed by shared code
9125 * active - true to enable lplu false to disable lplu.
9126 *
9127 * returns: - E1000_ERR_PHY if fail to read/write the PHY
9128 * E1000_SUCCESS at any other case.
9129 *
9130 ****************************************************************************/
9131STATIC int32_t
9132em_set_d0_lplu_state(struct em_hw *hw, boolean_t active)
9133{
9134 uint32_t phy_ctrl = 0;
9135 int32_t ret_val;
9136 uint16_t phy_data;
9137 DEBUGFUNC("em_set_d0_lplu_state");;
9138
9139 if (hw->mac_type <= em_82547_rev_2)
9140 return E1000_SUCCESS0;
9141
9142 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9143 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10)))));
9144 } else {
9145 ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT0x19,
9146 &phy_data);
9147 if (ret_val)
9148 return ret_val;
9149 }
9150
9151 if (!active) {
9152 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9153 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU0x00000002;
9154 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10))), (phy_ctrl)));
9155 } else {
9156 phy_data &= ~IGP02E1000_PM_D0_LPLU0x0002;
9157 ret_val = em_write_phy_reg(hw,
9158 IGP02E1000_PHY_POWER_MGMT0x19, phy_data);
9159 if (ret_val)
9160 return ret_val;
9161 }
9162 /*
9163 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
9164 * during Dx states where the power conservation is most
9165 * important. During driver activity we should enable
9166 * SmartSpeed, so performance is maintained.
9167 */
9168 if (hw->smart_speed == em_smart_speed_on) {
9169 ret_val = em_read_phy_reg(hw,
9170 IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data);
9171 if (ret_val)
9172 return ret_val;
9173
9174 phy_data |= IGP01E1000_PSCFR_SMART_SPEED0x0080;
9175 ret_val = em_write_phy_reg(hw,
9176 IGP01E1000_PHY_PORT_CONFIG0x10, phy_data);
9177 if (ret_val)
9178 return ret_val;
9179 } else if (hw->smart_speed == em_smart_speed_off) {
9180 ret_val = em_read_phy_reg(hw,
9181 IGP01E1000_PHY_PORT_CONFIG0x10, &phy_data);
9182 if (ret_val)
9183 return ret_val;
9184
9185 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080;
9186 ret_val = em_write_phy_reg(hw,
9187 IGP01E1000_PHY_PORT_CONFIG0x10, phy_data);
9188 if (ret_val)
9189 return ret_val;
9190 }
9191 } else {
9192 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9193 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU0x00000002;
9194 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F10 : em_translate_82542_register
(0x00F10))), (phy_ctrl)));
9195 } else {
9196 phy_data |= IGP02E1000_PM_D0_LPLU0x0002;
9197 ret_val = em_write_phy_reg(hw,
9198 IGP02E1000_PHY_POWER_MGMT0x19, phy_data);
9199 if (ret_val)
9200 return ret_val;
9201 }
9202
9203 /* When LPLU is enabled we should disable SmartSpeed */
9204 ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG0x10,
9205 &phy_data);
9206 if (ret_val)
9207 return ret_val;
9208
9209 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED0x0080;
9210 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG0x10,
9211 phy_data);
9212 if (ret_val)
9213 return ret_val;
9214
9215 }
9216 return E1000_SUCCESS0;
9217}
9218
9219/***************************************************************************
9220 * Set Low Power Link Up state
9221 *
9222 * Sets the LPLU state according to the active flag. For PCH, if OEM write
9223 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
9224 * the phy speed. This function will manually set the LPLU bit and restart
9225 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
9226 * since it configures the same bit.
9227 ***************************************************************************/
9228int32_t
9229em_set_lplu_state_pchlan(struct em_hw *hw, boolean_t active)
9230{
9231 int32_t ret_val = E1000_SUCCESS0;
9232 uint16_t oem_reg;
9233
9234 DEBUGFUNC("e1000_set_lplu_state_pchlan");;
9235
9236 ret_val = em_read_phy_reg(hw, HV_OEM_BITS(((768) << 5) | ((25) & 0x1F)), &oem_reg);
9237 if (ret_val)
9238 goto out;
9239
9240 if (active)
9241 oem_reg |= HV_OEM_BITS_LPLU0x0004;
9242 else
9243 oem_reg &= ~HV_OEM_BITS_LPLU0x0004;
9244
9245 oem_reg |= HV_OEM_BITS_RESTART_AN0x0400;
9246 ret_val = em_write_phy_reg(hw, HV_OEM_BITS(((768) << 5) | ((25) & 0x1F)), oem_reg);
9247
9248out:
9249 return ret_val;
9250}
9251
9252/******************************************************************************
9253 * Change VCO speed register to improve Bit Error Rate performance of SERDES.
9254 *
9255 * hw - Struct containing variables accessed by shared code
9256 *****************************************************************************/
9257static int32_t
9258em_set_vco_speed(struct em_hw *hw)
9259{
9260 int32_t ret_val;
9261 uint16_t default_page = 0;
9262 uint16_t phy_data;
9263 DEBUGFUNC("em_set_vco_speed");;
9264
9265 switch (hw->mac_type) {
9266 case em_82545_rev_3:
9267 case em_82546_rev_3:
9268 break;
9269 default:
9270 return E1000_SUCCESS0;
9271 }
9272
9273 /* Set PHY register 30, page 5, bit 8 to 0 */
9274
9275 ret_val = em_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, &default_page);
9276 if (ret_val)
9277 return ret_val;
9278
9279 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, 0x0005);
9280 if (ret_val)
9281 return ret_val;
9282
9283 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, &phy_data);
9284 if (ret_val)
9285 return ret_val;
9286
9287 phy_data &= ~M88E1000_PHY_VCO_REG_BIT80x100;
9288 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, phy_data);
9289 if (ret_val)
9290 return ret_val;
9291
9292 /* Set PHY register 30, page 4, bit 11 to 1 */
9293
9294 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, 0x0004);
9295 if (ret_val)
9296 return ret_val;
9297
9298 ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, &phy_data);
9299 if (ret_val)
9300 return ret_val;
9301
9302 phy_data |= M88E1000_PHY_VCO_REG_BIT110x800;
9303 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, phy_data);
9304 if (ret_val)
9305 return ret_val;
9306
9307 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, default_page);
9308 if (ret_val)
9309 return ret_val;
9310
9311 return E1000_SUCCESS0;
9312}
9313
9314/*****************************************************************************
9315 * This function reads the cookie from ARC ram.
9316 *
9317 * returns: - E1000_SUCCESS .
9318 ****************************************************************************/
9319STATIC int32_t
9320em_host_if_read_cookie(struct em_hw *hw, uint8_t *buffer)
9321{
9322 uint8_t i;
9323 uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET0x6F0;
9324 uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH0x10;
9325 length = (length >> 2);
9326 offset = (offset >> 2);
9327
9328 for (i = 0; i < length; i++) {
9329 *((uint32_t *) buffer + i) =
9330 E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x08800 : em_translate_82542_register
(0x08800)) + ((offset + i) << 2))));
9331 }
9332 return E1000_SUCCESS0;
9333}
9334
9335/*****************************************************************************
9336 * This function checks whether the HOST IF is enabled for command operation
9337 * and also checks whether the previous command is completed.
9338 * It busy waits in case of previous command is not completed.
9339 *
9340 * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
9341 * timeout
9342 * - E1000_SUCCESS for success.
9343 ****************************************************************************/
9344STATIC int32_t
9345em_mng_enable_host_if(struct em_hw *hw)
9346{
9347 uint32_t hicr;
9348 uint8_t i;
9349 /* Check that the host interface is enabled. */
9350 hicr = E1000_READ_REG(hw, HICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x08F00 : em_translate_82542_register
(0x08F00)))));
9351 if ((hicr & E1000_HICR_EN0x00000001) == 0) {
9352 DEBUGOUT("E1000_HOST_EN bit disabled.\n");
9353 return -E1000_ERR_HOST_INTERFACE_COMMAND11;
9354 }
9355 /* check the previous command is completed */
9356 for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT10; i++) {
9357 hicr = E1000_READ_REG(hw, HICR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x08F00 : em_translate_82542_register
(0x08F00)))));
9358 if (!(hicr & E1000_HICR_C0x00000002))
9359 break;
9360 msec_delay_irq(1)(*delay_func)(1000*(1));
9361 }
9362
9363 if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT10) {
9364 DEBUGOUT("Previous command timeout failed .\n");
9365 return -E1000_ERR_HOST_INTERFACE_COMMAND11;
9366 }
9367 return E1000_SUCCESS0;
9368}
9369
9370/*****************************************************************************
9371 * This function checks the mode of the firmware.
9372 *
9373 * returns - TRUE when the mode is IAMT or FALSE.
9374 ****************************************************************************/
9375boolean_t
9376em_check_mng_mode(struct em_hw *hw)
9377{
9378 uint32_t fwsm;
9379 fwsm = E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))));
9380
9381 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9382 if ((fwsm & E1000_FWSM_MODE_MASK0x0000000E) ==
9383 (E1000_MNG_ICH_IAMT_MODE0x2 << E1000_FWSM_MODE_SHIFT1))
9384 return TRUE1;
9385 } else if ((fwsm & E1000_FWSM_MODE_MASK0x0000000E) ==
9386 (E1000_MNG_IAMT_MODE0x3 << E1000_FWSM_MODE_SHIFT1))
9387 return TRUE1;
9388
9389 return FALSE0;
9390}
9391
9392/*****************************************************************************
9393 * This function calculates the checksum.
9394 *
9395 * returns - checksum of buffer contents.
9396 ****************************************************************************/
9397STATIC uint8_t
9398em_calculate_mng_checksum(char *buffer, uint32_t length)
9399{
9400 uint8_t sum = 0;
9401 uint32_t i;
9402 if (!buffer)
9403 return 0;
9404
9405 for (i = 0; i < length; i++)
9406 sum += buffer[i];
9407
9408 return (uint8_t) (0 - sum);
9409}
9410
9411/*****************************************************************************
9412 * This function checks whether tx pkt filtering needs to be enabled or not.
9413 *
9414 * returns - TRUE for packet filtering or FALSE.
9415 ****************************************************************************/
9416boolean_t
9417em_enable_tx_pkt_filtering(struct em_hw *hw)
9418{
9419 /* called in init as well as watchdog timer functions */
9420 int32_t ret_val, checksum;
9421 boolean_t tx_filter = FALSE0;
9422 struct em_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
9423 uint8_t *buffer = (uint8_t *) & (hw->mng_cookie);
9424 if (em_check_mng_mode(hw)) {
9425 ret_val = em_mng_enable_host_if(hw);
9426 if (ret_val == E1000_SUCCESS0) {
9427 ret_val = em_host_if_read_cookie(hw, buffer);
9428 if (ret_val == E1000_SUCCESS0) {
9429 checksum = hdr->checksum;
9430 hdr->checksum = 0;
9431 if ((hdr->signature == E1000_IAMT_SIGNATURE0x544D4149) &&
9432 checksum == em_calculate_mng_checksum(
9433 (char *) buffer,
9434 E1000_MNG_DHCP_COOKIE_LENGTH0x10)) {
9435 if (hdr->status &
9436 E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT0x1)
9437 tx_filter = TRUE1;
9438 } else
9439 tx_filter = TRUE1;
9440 } else
9441 tx_filter = TRUE1;
9442 }
9443 }
9444 hw->tx_pkt_filtering = tx_filter;
9445 return tx_filter;
9446}
9447
9448static int32_t
9449em_polarity_reversal_workaround(struct em_hw *hw)
9450{
9451 int32_t ret_val;
9452 uint16_t mii_status_reg;
9453 uint16_t i;
9454 /* Polarity reversal workaround for forced 10F/10H links. */
9455
9456 /* Disable the transmitter on the PHY */
9457 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, 0x0019);
9458 if (ret_val)
9459 return ret_val;
9460 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, 0xFFFF);
9461 if (ret_val)
9462 return ret_val;
9463
9464 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, 0x0000);
9465 if (ret_val)
9466 return ret_val;
9467
9468 /* This loop will early-out if the NO link condition has been met. */
9469 for (i = PHY_FORCE_TIME20; i > 0; i--) {
9470 /*
9471 * Read the MII Status Register and wait for Link Status bit
9472 * to be clear.
9473 */
9474
9475 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
9476 if (ret_val)
9477 return ret_val;
9478
9479 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
9480 if (ret_val)
9481 return ret_val;
9482
9483 if ((mii_status_reg & ~MII_SR_LINK_STATUS0x0004) == 0)
9484 break;
9485 msec_delay_irq(100)(*delay_func)(1000*(100));
9486 }
9487
9488 /* Recommended delay time after link has been lost */
9489 msec_delay_irq(1000)(*delay_func)(1000*(1000));
9490
9491 /* Now we will re-enable the transmitter on the PHY */
9492
9493 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, 0x0019);
9494 if (ret_val)
9495 return ret_val;
9496 msec_delay_irq(50)(*delay_func)(1000*(50));
9497 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, 0xFFF0);
9498 if (ret_val)
9499 return ret_val;
9500 msec_delay_irq(50)(*delay_func)(1000*(50));
9501 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, 0xFF00);
9502 if (ret_val)
9503 return ret_val;
9504 msec_delay_irq(50)(*delay_func)(1000*(50));
9505 ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL0x1E, 0x0000);
9506 if (ret_val)
9507 return ret_val;
9508
9509 ret_val = em_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT0x1D, 0x0000);
9510 if (ret_val)
9511 return ret_val;
9512
9513 /* This loop will early-out if the link condition has been met. */
9514 for (i = PHY_FORCE_TIME20; i > 0; i--) {
9515 /*
9516 * Read the MII Status Register and wait for Link Status bit
9517 * to be set.
9518 */
9519
9520 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
9521 if (ret_val)
9522 return ret_val;
9523
9524 ret_val = em_read_phy_reg(hw, PHY_STATUS0x01, &mii_status_reg);
9525 if (ret_val)
9526 return ret_val;
9527
9528 if (mii_status_reg & MII_SR_LINK_STATUS0x0004)
9529 break;
9530 msec_delay_irq(100)(*delay_func)(1000*(100));
9531 }
9532 return E1000_SUCCESS0;
9533}
9534
9535/******************************************************************************
9536 *
9537 * Disables PCI-Express master access.
9538 *
9539 * hw: Struct containing variables accessed by shared code
9540 *
9541 * returns: - none.
9542 *
9543 *****************************************************************************/
9544STATIC void
9545em_set_pci_express_master_disable(struct em_hw *hw)
9546{
9547 uint32_t ctrl;
9548 DEBUGFUNC("em_set_pci_express_master_disable");;
9549
9550 if (hw->bus_type != em_bus_type_pci_express)
9551 return;
9552
9553 ctrl = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
9554 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE0x00000004;
9555 E1000_WRITE_REG(hw, CTRL, ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl)));
9556}
9557
9558/******************************************************************************
9559 *
9560 * Disables PCI-Express master access and verifies there are no pending
9561 * requests
9562 *
9563 * hw: Struct containing variables accessed by shared code
9564 *
9565 * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
9566 * caused the master requests to be disabled.
9567 * E1000_SUCCESS master requests disabled.
9568 *
9569 ******************************************************************************/
9570int32_t
9571em_disable_pciex_master(struct em_hw *hw)
9572{
9573 int32_t timeout = MASTER_DISABLE_TIMEOUT800; /* 80ms */
9574 DEBUGFUNC("em_disable_pciex_master");;
9575
9576 if (hw->bus_type != em_bus_type_pci_express)
9577 return E1000_SUCCESS0;
9578
9579 em_set_pci_express_master_disable(hw);
9580
9581 while (timeout) {
9582 if (!(E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))))) &
9583 E1000_STATUS_GIO_MASTER_ENABLE0x00080000))
9584 break;
9585 else
9586 usec_delay(100)(*delay_func)(100);
9587 timeout--;
9588 }
9589
9590 if (!timeout) {
9591 DEBUGOUT("Master requests are pending.\n");
9592 return -E1000_ERR_MASTER_REQUESTS_PENDING10;
9593 }
9594 return E1000_SUCCESS0;
9595}
9596
9597/******************************************************************************
9598 *
9599 * Check for EEPROM Auto Read bit done.
9600 *
9601 * hw: Struct containing variables accessed by shared code
9602 *
9603 * returns: - E1000_ERR_RESET if fail to reset MAC
9604 * E1000_SUCCESS at any other case.
9605 *
9606 ******************************************************************************/
9607STATIC int32_t
9608em_get_auto_rd_done(struct em_hw *hw)
9609{
9610 int32_t timeout = AUTO_READ_DONE_TIMEOUT10;
9611 DEBUGFUNC("em_get_auto_rd_done");;
9612
9613 switch (hw->mac_type) {
9614 default:
9615 msec_delay(5)(*delay_func)(1000*(5));
9616 break;
9617 case em_82571:
9618 case em_82572:
9619 case em_82573:
9620 case em_82574:
9621 case em_82575:
9622 case em_82576:
9623 case em_82580:
9624 case em_80003es2lan:
9625 case em_i210:
9626 case em_i350:
9627 case em_ich8lan:
9628 case em_ich9lan:
9629 case em_ich10lan:
9630 case em_pchlan:
9631 case em_pch2lan:
9632 case em_pch_lpt:
9633 case em_pch_spt:
9634 case em_pch_cnp:
9635 case em_pch_tgp:
9636 case em_pch_adp:
9637 while (timeout) {
9638 if (E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))))) & E1000_EECD_AUTO_RD0x00000200)
9639 break;
9640 else
9641 msec_delay(1)(*delay_func)(1000*(1));
9642 timeout--;
9643 }
9644
9645 if (!timeout) {
9646 DEBUGOUT("Auto read by HW from EEPROM has not"
9647 " completed.\n");
9648 return -E1000_ERR_RESET9;
9649 }
9650 break;
9651 }
9652 /*
9653 * PHY configuration from NVM just starts after EECD_AUTO_RD sets to
9654 * high. Need to wait for PHY configuration completion before
9655 * accessing NVM and PHY.
9656 */
9657 if ((hw->mac_type == em_82573) || (hw->mac_type == em_82574))
9658 msec_delay(25)(*delay_func)(1000*(25));
9659
9660 return E1000_SUCCESS0;
9661}
9662
9663/***************************************************************************
9664 * Checks if the PHY configuration is done
9665 *
9666 * hw: Struct containing variables accessed by shared code
9667 *
9668 * returns: - E1000_ERR_RESET if fail to reset MAC
9669 * E1000_SUCCESS at any other case.
9670 *
9671 ***************************************************************************/
9672STATIC int32_t
9673em_get_phy_cfg_done(struct em_hw *hw)
9674{
9675 int32_t timeout = PHY_CFG_TIMEOUT100;
9676 uint32_t cfg_mask = E1000_NVM_CFG_DONE_PORT_00x040000;
9677 DEBUGFUNC("em_get_phy_cfg_done");;
9678
9679 switch (hw->mac_type) {
9680 default:
9681 msec_delay_irq(10)(*delay_func)(1000*(10));
9682 break;
9683 case em_80003es2lan:
9684 case em_82575:
9685 case em_82576:
9686 case em_82580:
9687 case em_i350:
9688 switch (hw->bus_func) {
9689 case 1:
9690 cfg_mask = E1000_NVM_CFG_DONE_PORT_10x080000;
9691 break;
9692 case 2:
9693 cfg_mask = E1000_NVM_CFG_DONE_PORT_20x100000;
9694 break;
9695 case 3:
9696 cfg_mask = E1000_NVM_CFG_DONE_PORT_30x200000;
9697 break;
9698 }
9699 /* FALLTHROUGH */
9700 case em_82571:
9701 case em_82572:
9702 while (timeout) {
9703 if (E1000_READ_REG(hw, EEMNGCTL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x01010 : em_translate_82542_register
(0x01010))))) & cfg_mask)
9704 break;
9705 else
9706 msec_delay(1)(*delay_func)(1000*(1));
9707 timeout--;
9708 }
9709 if (!timeout) {
9710 DEBUGOUT("MNG configuration cycle has not completed."
9711 "\n");
9712 }
9713 break;
9714 }
9715
9716 return E1000_SUCCESS0;
9717}
9718
9719/***************************************************************************
9720 *
9721 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
9722 * adapter or Eeprom access.
9723 *
9724 * hw: Struct containing variables accessed by shared code
9725 *
9726 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
9727 * E1000_SUCCESS at any other case.
9728 *
9729 ***************************************************************************/
9730STATIC int32_t
9731em_get_hw_eeprom_semaphore(struct em_hw *hw)
9732{
9733 int32_t timeout;
9734 uint32_t swsm;
9735 DEBUGFUNC("em_get_hw_eeprom_semaphore");;
9736
9737 if (!hw->eeprom_semaphore_present)
9738 return E1000_SUCCESS0;
9739
9740 if (hw->mac_type == em_80003es2lan) {
9741 /* Get the SW semaphore. */
9742 if (em_get_software_semaphore(hw) != E1000_SUCCESS0)
9743 return -E1000_ERR_EEPROM1;
9744 }
9745 /* Get the FW semaphore. */
9746 timeout = hw->eeprom.word_size + 1;
9747 while (timeout) {
9748 swsm = E1000_READ_REG(hw, SWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
9749 swsm |= E1000_SWSM_SWESMBI0x00000002;
9750 E1000_WRITE_REG(hw, SWSM, swsm)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (swsm)));
9751 /* if we managed to set the bit we got the semaphore. */
9752 swsm = E1000_READ_REG(hw, SWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
9753 if (swsm & E1000_SWSM_SWESMBI0x00000002)
9754 break;
9755
9756 usec_delay(50)(*delay_func)(50);
9757 timeout--;
9758 }
9759
9760 if (!timeout) {
9761 /* Release semaphores */
9762 em_put_hw_eeprom_semaphore(hw);
9763 DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set."
9764 "\n");
9765 return -E1000_ERR_EEPROM1;
9766 }
9767 return E1000_SUCCESS0;
9768}
9769
9770/***************************************************************************
9771 * This function clears HW semaphore bits.
9772 *
9773 * hw: Struct containing variables accessed by shared code
9774 *
9775 * returns: - None.
9776 *
9777 ***************************************************************************/
9778STATIC void
9779em_put_hw_eeprom_semaphore(struct em_hw *hw)
9780{
9781 uint32_t swsm;
9782 DEBUGFUNC("em_put_hw_eeprom_semaphore");;
9783
9784 if (!hw->eeprom_semaphore_present)
9785 return;
9786
9787 swsm = E1000_READ_REG(hw, SWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
9788 if (hw->mac_type == em_80003es2lan) {
9789 /* Release both semaphores. */
9790 swsm &= ~(E1000_SWSM_SMBI0x00000001 | E1000_SWSM_SWESMBI0x00000002);
9791 } else
9792 swsm &= ~(E1000_SWSM_SWESMBI0x00000002);
9793 E1000_WRITE_REG(hw, SWSM, swsm)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (swsm)));
9794}
9795
9796/***************************************************************************
9797 *
9798 * Obtaining software semaphore bit (SMBI) before resetting PHY.
9799 *
9800 * hw: Struct containing variables accessed by shared code
9801 *
9802 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
9803 * E1000_SUCCESS at any other case.
9804 *
9805 ***************************************************************************/
9806STATIC int32_t
9807em_get_software_semaphore(struct em_hw *hw)
9808{
9809 int32_t timeout = hw->eeprom.word_size + 1;
9810 uint32_t swsm;
9811 DEBUGFUNC("em_get_software_semaphore");;
9812
9813 if (hw->mac_type != em_80003es2lan)
9814 return E1000_SUCCESS0;
9815
9816 while (timeout) {
9817 swsm = E1000_READ_REG(hw, SWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
9818 /*
9819 * If SMBI bit cleared, it is now set and we hold the
9820 * semaphore
9821 */
9822 if (!(swsm & E1000_SWSM_SMBI0x00000001))
9823 break;
9824 msec_delay_irq(1)(*delay_func)(1000*(1));
9825 timeout--;
9826 }
9827
9828 if (!timeout) {
9829 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
9830 return -E1000_ERR_RESET9;
9831 }
9832 return E1000_SUCCESS0;
9833}
9834
9835/***************************************************************************
9836 *
9837 * Release semaphore bit (SMBI).
9838 *
9839 * hw: Struct containing variables accessed by shared code
9840 *
9841 ***************************************************************************/
9842STATIC void
9843em_release_software_semaphore(struct em_hw *hw)
9844{
9845 uint32_t swsm;
9846 DEBUGFUNC("em_release_software_semaphore");;
9847
9848 if (hw->mac_type != em_80003es2lan)
9849 return;
9850
9851 swsm = E1000_READ_REG(hw, SWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50)))));
9852 /* Release the SW semaphores. */
9853 swsm &= ~E1000_SWSM_SMBI0x00000001;
9854 E1000_WRITE_REG(hw, SWSM, swsm)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B50 : em_translate_82542_register
(0x05B50))), (swsm)));
9855}
9856
9857/******************************************************************************
9858 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
9859 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
9860 * the caller to figure out how to deal with it.
9861 *
9862 * hw - Struct containing variables accessed by shared code
9863 *
9864 * returns: - E1000_BLK_PHY_RESET
9865 * E1000_SUCCESS
9866 *
9867 *****************************************************************************/
9868int32_t
9869em_check_phy_reset_block(struct em_hw *hw)
9870{
9871 uint32_t manc = 0;
9872 uint32_t fwsm = 0;
9873 DEBUGFUNC("em_check_phy_reset_block\n");;
9874
9875 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
150
←
Assuming field 'mac_type' is not equal to em_ich8lan
→
151
←
Assuming field 'mac_type' is not equal to em_ich9lan
→
152
←
Assuming field 'mac_type' is not equal to em_ich10lan
→
153
←
Assuming field 'mac_type' is not equal to em_pchlan
→
154
←
Assuming field 'mac_type' is not equal to em_pch2lan
→
155
←
Assuming field 'mac_type' is not equal to em_pch_lpt
→
156
←
Assuming field 'mac_type' is not equal to em_pch_spt
→
157
←
Assuming field 'mac_type' is not equal to em_pch_cnp
→
158
←
Assuming field 'mac_type' is not equal to em_pch_tgp
→
159
←
Assuming field 'mac_type' is not equal to em_pch_adp
→
160
←
Taking false branch
→
9876 int i = 0;
9877 int blocked = 0;
9878 do {
9879 fwsm = E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54)))));
9880 if (!(fwsm & E1000_FWSM_RSPCIPHY0x00000040)) {
9881 blocked = 1;
9882 msec_delay(10)(*delay_func)(1000*(10));
9883 continue;
9884 }
9885 blocked = 0;
9886 } while (blocked && (i++ < 30));
9887 return blocked ? E1000_BLK_PHY_RESET12 : E1000_SUCCESS0;
9888 }
9889 if (hw->mac_type > em_82547_rev_2)
161
←
Assuming field 'mac_type' is <= em_82547_rev_2
→
9890 manc = E1000_READ_REG(hw, MANC)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05820 : em_translate_82542_register
(0x05820)))));
9891 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE0x00040000) ?
162
←
'?' condition is false
→
163
←
Returning without writing to 'hw->phy_init_script', which participates in a condition later
→
9892 E1000_BLK_PHY_RESET12 : E1000_SUCCESS0;
9893}
9894
9895/******************************************************************************
9896 * Configure PCI-Ex no-snoop
9897 *
9898 * hw - Struct containing variables accessed by shared code.
9899 * no_snoop - Bitmap of no-snoop events.
9900 *
9901 * returns: E1000_SUCCESS
9902 *
9903 *****************************************************************************/
9904STATIC int32_t
9905em_set_pci_ex_no_snoop(struct em_hw *hw, uint32_t no_snoop)
9906{
9907 uint32_t gcr_reg = 0;
9908 DEBUGFUNC("em_set_pci_ex_no_snoop");;
9909
9910 if (hw->bus_type == em_bus_type_unknown)
9911 em_get_bus_info(hw);
9912
9913 if (hw->bus_type != em_bus_type_pci_express)
9914 return E1000_SUCCESS0;
9915
9916 if (no_snoop) {
9917 gcr_reg = E1000_READ_REG(hw, GCR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00)))));
9918 gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL(0x00000001 | 0x00000002 | 0x00000004 | 0x00000008 | 0x00000010
| 0x00000020));
9919 gcr_reg |= no_snoop;
9920 E1000_WRITE_REG(hw, GCR, gcr_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00))), (gcr_reg)));
9921 }
9922 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9923 uint32_t ctrl_ext;
9924 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
9925 ctrl_ext |= E1000_CTRL_EXT_RO_DIS0x00020000;
9926 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
9927 }
9928 return E1000_SUCCESS0;
9929}
9930
9931/***************************************************************************
9932 *
9933 * Get software semaphore FLAG bit (SWFLAG).
9934 * SWFLAG is used to synchronize the access to all shared resource between
9935 * SW, FW and HW.
9936 *
9937 * hw: Struct containing variables accessed by shared code
9938 *
9939 ***************************************************************************/
9940STATIC int32_t
9941em_get_software_flag(struct em_hw *hw)
9942{
9943 int32_t timeout = PHY_CFG_TIMEOUT100;
9944 uint32_t extcnf_ctrl;
9945 DEBUGFUNC("em_get_software_flag");;
9946
9947 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
9948 if (hw->sw_flag) {
9949 hw->sw_flag++;
9950 return E1000_SUCCESS0;
9951 }
9952 while (timeout) {
9953 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
9954 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG0x00000020))
9955 break;
9956 msec_delay_irq(1)(*delay_func)(1000*(1));
9957 timeout--;
9958 }
9959 if (!timeout) {
9960 printf("%s: SW has already locked the resource?\n",
9961 __func__);
9962 return -E1000_ERR_CONFIG3;
9963 }
9964 timeout = SW_FLAG_TIMEOUT1000;
9965 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG0x00000020;
9966 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00))), (extcnf_ctrl)));
9967
9968 while (timeout) {
9969 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
9970 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG0x00000020)
9971 break;
9972 msec_delay_irq(1)(*delay_func)(1000*(1));
9973 timeout--;
9974 }
9975
9976 if (!timeout) {
9977 printf("Failed to acquire the semaphore, FW or HW "
9978 "has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
9979 E1000_READ_REG(hw, FWSM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B54 : em_translate_82542_register
(0x05B54))))), extcnf_ctrl);
9980 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG0x00000020;
9981 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00))), (extcnf_ctrl)));
9982 return -E1000_ERR_CONFIG3;
9983 }
9984 }
9985 hw->sw_flag++;
9986 return E1000_SUCCESS0;
9987}
9988
9989/***************************************************************************
9990 *
9991 * Release software semaphore FLAG bit (SWFLAG).
9992 * SWFLAG is used to synchronize the access to all shared resource between
9993 * SW, FW and HW.
9994 *
9995 * hw: Struct containing variables accessed by shared code
9996 *
9997 ***************************************************************************/
9998STATIC void
9999em_release_software_flag(struct em_hw *hw)
10000{
10001 uint32_t extcnf_ctrl;
10002 DEBUGFUNC("em_release_software_flag");;
10003
10004 if (IS_ICH8(hw->mac_type)(hw->mac_type == em_ich8lan || hw->mac_type == em_ich9lan
|| hw->mac_type == em_ich10lan || hw->mac_type == em_pchlan
|| hw->mac_type == em_pch2lan || hw->mac_type == em_pch_lpt
|| hw->mac_type == em_pch_spt || hw->mac_type == em_pch_cnp
|| hw->mac_type == em_pch_tgp || hw->mac_type == em_pch_adp
)) {
10005 KASSERT(hw->sw_flag > 0)((hw->sw_flag > 0) ? (void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_em_hw.c"
, 10005, "hw->sw_flag > 0"));
10006 if (--hw->sw_flag > 0)
10007 return;
10008 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
10009 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG0x00000020;
10010 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00))), (extcnf_ctrl)));
10011 }
10012 return;
10013}
10014
10015/**
10016 * em_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
10017 * @hw: pointer to the HW structure
10018 * @bank: pointer to the variable that returns the active bank
10019 *
10020 * Reads signature byte from the NVM using the flash access registers.
10021 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
10022 **/
10023int32_t
10024em_valid_nvm_bank_detect_ich8lan(struct em_hw *hw, uint32_t *bank)
10025{
10026 uint32_t eecd;
10027 uint32_t bank1_offset = hw->flash_bank_size * sizeof(uint16_t);
10028 uint32_t act_offset = E1000_ICH_NVM_SIG_WORD0x13 * 2 + 1;
10029 uint32_t nvm_dword = 0;
10030 uint8_t sig_byte = 0;
10031 int32_t ret_val;
10032
10033 DEBUGFUNC("em_valid_nvm_bank_detect_ich8lan");;
10034
10035 switch (hw->mac_type) {
10036 case em_pch_spt:
10037 case em_pch_cnp:
10038 case em_pch_tgp:
10039 case em_pch_adp:
10040 bank1_offset = hw->flash_bank_size * 2;
10041 act_offset = E1000_ICH_NVM_SIG_WORD0x13 * 2;
10042
10043 /* set bank to 0 in case flash read fails. */
10044 *bank = 0;
10045
10046 /* Check bank 0 */
10047 ret_val = em_read_ich8_dword(hw, act_offset, &nvm_dword);
10048 if (ret_val)
10049 return ret_val;
10050 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
10051 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK0xC0) ==
10052 E1000_ICH_NVM_SIG_VALUE0x80) {
10053 *bank = 0;
10054 return 0;
10055 }
10056
10057 /* Check bank 1 */
10058 ret_val = em_read_ich8_dword(hw, act_offset + bank1_offset,
10059 &nvm_dword);
10060 if (ret_val)
10061 return ret_val;
10062 sig_byte = (uint8_t)((nvm_dword & 0xFF00) >> 8);
10063 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK0xC0) ==
10064 E1000_ICH_NVM_SIG_VALUE0x80) {
10065 *bank = 1;
10066 return 0;
10067 }
10068
10069 DEBUGOUT("ERROR: No valid NVM bank present\n");
10070 return -1;
10071 case em_ich8lan:
10072 case em_ich9lan:
10073 eecd = E1000_READ_REG(hw, EECD)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
10074 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK(0x00000200 | 0x00000100)) ==
10075 E1000_EECD_SEC1VAL_VALID_MASK(0x00000200 | 0x00000100)) {
10076 if (eecd & E1000_EECD_SEC1VAL0x00400000)
10077 *bank = 1;
10078 else
10079 *bank = 0;
10080
10081 return E1000_SUCCESS0;
10082 }
10083 DEBUGOUT("Unable to determine valid NVM bank via EEC - reading flash signature\n");
10084 /* fall-thru */
10085 default:
10086 /* set bank to 0 in case flash read fails */
10087 *bank = 0;
10088
10089 /* Check bank 0 */
10090 ret_val = em_read_ich8_byte(hw, act_offset,
10091 &sig_byte);
10092 if (ret_val)
10093 return ret_val;
10094 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK0xC0) ==
10095 E1000_ICH_NVM_SIG_VALUE0x80) {
10096 *bank = 0;
10097 return E1000_SUCCESS0;
10098 }
10099
10100 /* Check bank 1 */
10101 ret_val = em_read_ich8_byte(hw, act_offset +
10102 bank1_offset,
10103 &sig_byte);
10104 if (ret_val)
10105 return ret_val;
10106 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK0xC0) ==
10107 E1000_ICH_NVM_SIG_VALUE0x80) {
10108 *bank = 1;
10109 return E1000_SUCCESS0;
10110 }
10111
10112 DEBUGOUT("ERROR: No valid NVM bank present\n");
10113 return -1;
10114 }
10115}
10116
10117STATIC int32_t
10118em_read_eeprom_spt(struct em_hw *hw, uint16_t offset, uint16_t words,
10119 uint16_t *data)
10120{
10121 int32_t error = E1000_SUCCESS0;
10122 uint32_t flash_bank = 0;
10123 uint32_t act_offset = 0;
10124 uint32_t bank_offset = 0;
10125 uint32_t dword = 0;
10126 uint16_t i = 0, add;
10127
10128 /*
10129 * We need to know which is the valid flash bank. In the event that
10130 * we didn't allocate eeprom_shadow_ram, we may not be managing
10131 * flash_bank. So it cannot be trusted and needs to be updated with
10132 * each read.
10133 */
10134
10135 if (hw->mac_type < em_pch_spt)
10136 return -E1000_ERR_EEPROM1;
10137
10138 error = em_get_software_flag(hw);
10139 if (error != E1000_SUCCESS0)
10140 return error;
10141
10142 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank);
10143 if (error != E1000_SUCCESS0) {
10144 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
10145 flash_bank = 0;
10146 }
10147
10148 /*
10149 * Adjust offset appropriately if we're on bank 1 - adjust for word
10150 * size
10151 */
10152 bank_offset = flash_bank * (hw->flash_bank_size * 2);
10153
10154 for (i = add = 0; i < words; i += add) {
10155 if ((offset + i) % 2) {
10156 add = 1;
10157 if (hw->eeprom_shadow_ram != NULL((void *)0)
10158 && hw->eeprom_shadow_ram[offset + i].modified) {
10159 data[i] =
10160 hw->eeprom_shadow_ram[offset+i].eeprom_word;
10161 continue;
10162 }
10163 act_offset = bank_offset + (offset + i - 1) * 2;
10164 } else {
10165 add = 2;
10166 if (hw->eeprom_shadow_ram != NULL((void *)0)
10167 && hw->eeprom_shadow_ram[offset+i].modified
10168 && hw->eeprom_shadow_ram[offset+i+1].modified) {
10169 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
10170 data[i+1] = hw->eeprom_shadow_ram[offset+i+1].eeprom_word;
10171 continue;
10172 }
10173 act_offset = bank_offset + (offset + i) * 2;
10174 }
10175 error = em_read_ich8_dword(hw, act_offset, &dword);
10176 if (error != E1000_SUCCESS0)
10177 break;
10178 if (hw->eeprom_shadow_ram != NULL((void *)0)
10179 && hw->eeprom_shadow_ram[offset+i].modified) {
10180 data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
10181 } else {
10182 if (add == 1)
10183 data[i] = dword >> 16;
10184 else
10185 data[i] = dword & 0xFFFFUL;
10186 }
10187 if (add == 1 || words-i == 1)
10188 continue;
10189 if (hw->eeprom_shadow_ram != NULL((void *)0)
10190 && hw->eeprom_shadow_ram[offset+i+1].modified) {
10191 data[i+1] =
10192 hw->eeprom_shadow_ram[offset+i+1].eeprom_word;
10193 } else {
10194 data[i+1] = dword >> 16;
10195 }
10196 }
10197
10198 em_release_software_flag(hw);
10199
10200 return error;
10201}
10202
10203/******************************************************************************
10204 * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
10205 * register.
10206 *
10207 * hw - Struct containing variables accessed by shared code
10208 * offset - offset of word in the EEPROM to read
10209 * data - word read from the EEPROM
10210 * words - number of words to read
10211 *****************************************************************************/
10212STATIC int32_t
10213em_read_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
10214 uint16_t *data)
10215{
10216 int32_t error = E1000_SUCCESS0;
10217 uint32_t flash_bank = 0;
10218 uint32_t act_offset = 0;
10219 uint32_t bank_offset = 0;
10220 uint16_t word = 0;
10221 uint16_t i = 0;
10222 /*
10223 * We need to know which is the valid flash bank. In the event that
10224 * we didn't allocate eeprom_shadow_ram, we may not be managing
10225 * flash_bank. So it cannot be trusted and needs to be updated with
10226 * each read.
10227 */
10228
10229 if (hw->mac_type >= em_pch_spt)
10230 return em_read_eeprom_spt(hw, offset, words, data);
10231
10232 error = em_get_software_flag(hw);
10233 if (error != E1000_SUCCESS0)
10234 return error;
10235
10236 error = em_valid_nvm_bank_detect_ich8lan(hw, &flash_bank);
10237 if (error != E1000_SUCCESS0) {
10238 DEBUGOUT("Could not detect valid bank, assuming bank 0\n");
10239 flash_bank = 0;
10240 }
10241
10242 /*
10243 * Adjust offset appropriately if we're on bank 1 - adjust for word
10244 * size
10245 */
10246 bank_offset = flash_bank * (hw->flash_bank_size * 2);
10247
10248 for (i = 0; i < words; i++) {
10249 if (hw->eeprom_shadow_ram != NULL((void *)0) &&
10250 hw->eeprom_shadow_ram[offset + i].modified == TRUE1) {
10251 data[i] =
10252 hw->eeprom_shadow_ram[offset + i].eeprom_word;
10253 } else {
10254 /* The NVM part needs a byte offset, hence * 2 */
10255 act_offset = bank_offset + ((offset + i) * 2);
10256 error = em_read_ich8_word(hw, act_offset, &word);
10257 if (error != E1000_SUCCESS0)
10258 break;
10259 data[i] = word;
10260 }
10261 }
10262
10263 em_release_software_flag(hw);
10264
10265 return error;
10266}
10267
10268/******************************************************************************
10269 * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
10270 * register. Actually, writes are written to the shadow ram cache in the hw
10271 * structure hw->em_shadow_ram. em_commit_shadow_ram flushes this to
10272 * the NVM, which occurs when the NVM checksum is updated.
10273 *
10274 * hw - Struct containing variables accessed by shared code
10275 * offset - offset of word in the EEPROM to write
10276 * words - number of words to write
10277 * data - words to write to the EEPROM
10278 *****************************************************************************/
10279STATIC int32_t
10280em_write_eeprom_ich8(struct em_hw *hw, uint16_t offset, uint16_t words,
10281 uint16_t *data)
10282{
10283 uint32_t i = 0;
10284 int32_t error = E1000_SUCCESS0;
10285 error = em_get_software_flag(hw);
10286 if (error != E1000_SUCCESS0)
10287 return error;
10288 /*
10289 * A driver can write to the NVM only if it has eeprom_shadow_ram
10290 * allocated. Subsequent reads to the modified words are read from
10291 * this cached structure as well. Writes will only go into this
10292 * cached structure unless it's followed by a call to
10293 * em_update_eeprom_checksum() where it will commit the changes and
10294 * clear the "modified" field.
10295 */
10296 if (hw->eeprom_shadow_ram != NULL((void *)0)) {
10297 for (i = 0; i < words; i++) {
10298 if ((offset + i) < E1000_SHADOW_RAM_WORDS2048) {
10299 hw->eeprom_shadow_ram[offset + i].modified =
10300 TRUE1;
10301 hw->eeprom_shadow_ram[offset + i].eeprom_word =
10302 data[i];
10303 } else {
10304 error = -E1000_ERR_EEPROM1;
10305 break;
10306 }
10307 }
10308 } else {
10309 /*
10310 * Drivers have the option to not allocate eeprom_shadow_ram
10311 * as long as they don't perform any NVM writes. An attempt
10312 * in doing so will result in this error.
10313 */
10314 error = -E1000_ERR_EEPROM1;
10315 }
10316
10317 em_release_software_flag(hw);
10318
10319 return error;
10320}
10321
10322/******************************************************************************
10323 * This function does initial flash setup so that a new read/write/erase cycle
10324 * can be started.
10325 *
10326 * hw - The pointer to the hw structure
10327 ****************************************************************************/
10328STATIC int32_t
10329em_ich8_cycle_init(struct em_hw *hw)
10330{
10331 union ich8_hws_flash_status hsfsts;
10332 int32_t error = E1000_ERR_EEPROM1;
10333 int32_t i = 0;
10334 DEBUGFUNC("em_ich8_cycle_init");;
10335
10336 if (hw->mac_type >= em_pch_spt)
10337 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10338 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
))) & 0xFFFFUL;
10339 else
10340 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10341 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10342
10343 /* May be check the Flash Des Valid bit in Hw status */
10344 if (hsfsts.hsf_status.fldesvalid == 0) {
10345 DEBUGOUT("Flash descriptor invalid. SW Sequencing must be"
10346 " used.");
10347 return error;
10348 }
10349 /* Clear FCERR in Hw status by writing 1 */
10350 /* Clear DAEL in Hw status by writing a 1 */
10351 hsfsts.hsf_status.flcerr = 1;
10352 hsfsts.hsf_status.dael = 1;
10353 if (hw->mac_type >= em_pch_spt)
10354 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval & 0xFFFFUL)))
10355 hsfsts.regval & 0xFFFFUL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval & 0xFFFFUL)));
10356 else
10357 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval)))
10358 hsfsts.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval)));
10359 /*
10360 * Either we should have a hardware SPI cycle in progress bit to
10361 * check against, in order to start a new cycle or FDONE bit should
10362 * be changed in the hardware so that it is 1 after hardware reset,
10363 * which can then be used as an indication whether a cycle is in
10364 * progress or has been completed .. we should also have some
10365 * software semaphore mechanism to guard FDONE or the cycle in
10366 * progress bit so that two threads access to those bits can be
10367 * sequentiallized or a way so that 2 threads dont start the cycle at
10368 * the same time
10369 */
10370
10371 if (hsfsts.hsf_status.flcinprog == 0) {
10372 /*
10373 * There is no cycle running at present, so we can start a
10374 * cycle
10375 */
10376 /* Begin by setting Flash Cycle Done. */
10377 hsfsts.hsf_status.flcdone = 1;
10378 if (hw->mac_type >= em_pch_spt)
10379 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval & 0xFFFFUL)))
10380 hsfsts.regval & 0xFFFFUL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval & 0xFFFFUL)));
10381 else
10382 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval)))
10383 hsfsts.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval)));
10384 error = E1000_SUCCESS0;
10385 } else {
10386 /*
10387 * otherwise poll for sometime so the current cycle has a
10388 * chance to end before giving up.
10389 */
10390 for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT5000; i++) {
10391 if (hw->mac_type >= em_pch_spt)
10392 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10393 hw, ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
))) & 0xFFFFUL;
10394 else
10395 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10396 hw, ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10397 if (hsfsts.hsf_status.flcinprog == 0) {
10398 error = E1000_SUCCESS0;
10399 break;
10400 }
10401 usec_delay(1)(*delay_func)(1);
10402 }
10403 if (error == E1000_SUCCESS0) {
10404 /*
10405 * Successful in waiting for previous cycle to
10406 * timeout, now set the Flash Cycle Done.
10407 */
10408 hsfsts.hsf_status.flcdone = 1;
10409 if (hw->mac_type >= em_pch_spt)
10410 E1000_WRITE_ICH_FLASH_REG32(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval & 0xFFFFUL)))
10411 ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFFUL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval & 0xFFFFUL)));
10412 else
10413 E1000_WRITE_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval)))
10414 ICH_FLASH_HSFSTS, hsfsts.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), (hsfsts.regval)));
10415 } else {
10416 DEBUGOUT("Flash controller busy, cannot get access");
10417 }
10418 }
10419 return error;
10420}
10421
10422/******************************************************************************
10423 * This function starts a flash cycle and waits for its completion
10424 *
10425 * hw - The pointer to the hw structure
10426 *****************************************************************************/
10427STATIC int32_t
10428em_ich8_flash_cycle(struct em_hw *hw, uint32_t timeout)
10429{
10430 union ich8_hws_flash_ctrl hsflctl;
10431 union ich8_hws_flash_status hsfsts;
10432 int32_t error = E1000_ERR_EEPROM1;
10433 uint32_t i = 0;
10434
10435 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
10436 if (hw->mac_type >= em_pch_spt)
10437 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10438 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
))) >> 16;
10439 else
10440 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)))
10441 ICH_FLASH_HSFCTL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)));
10442 hsflctl.hsf_ctrl.flcgo = 1;
10443
10444 if (hw->mac_type >= em_pch_spt)
10445 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), ((uint32_t)hsflctl.regval << 16)))
10446 (uint32_t)hsflctl.regval << 16)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), ((uint32_t)hsflctl.regval << 16)));
10447 else
10448 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)))
10449 hsflctl.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)));
10450
10451 /* wait till FDONE bit is set to 1 */
10452 do {
10453 if (hw->mac_type >= em_pch_spt)
10454 hsfsts.regval = E1000_READ_ICH_FLASH_REG32(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10455 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
))) & 0xFFFFUL;
10456 else
10457 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10458 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10459 if (hsfsts.hsf_status.flcdone == 1)
10460 break;
10461 usec_delay(1)(*delay_func)(1);
10462 i++;
10463 } while (i < timeout);
10464 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
10465 error = E1000_SUCCESS0;
10466 }
10467 return error;
10468}
10469
10470/******************************************************************************
10471 * Reads a byte or word from the NVM using the ICH8 flash access registers.
10472 *
10473 * hw - The pointer to the hw structure
10474 * index - The index of the byte or word to read.
10475 * size - Size of data to read, 1=byte 2=word
10476 * data - Pointer to the word to store the value read.
10477 *****************************************************************************/
10478STATIC int32_t
10479em_read_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
10480 uint16_t *data)
10481{
10482 union ich8_hws_flash_status hsfsts;
10483 union ich8_hws_flash_ctrl hsflctl;
10484 uint32_t flash_linear_address;
10485 uint32_t flash_data = 0;
10486 int32_t error = -E1000_ERR_EEPROM1;
10487 int32_t count = 0;
10488 DEBUGFUNC("em_read_ich8_data");;
10489
10490 if (size < 1 || size > 2 || data == 0x0 ||
10491 index > ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF)
10492 return error;
10493
10494 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF & index) +
10495 hw->flash_base_addr;
10496
10497 do {
10498 usec_delay(1)(*delay_func)(1);
10499 /* Steps */
10500 error = em_ich8_cycle_init(hw);
10501 if (error != E1000_SUCCESS0)
10502 break;
10503
10504 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)))
10505 ICH_FLASH_HSFCTL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)));
10506 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
10507 hsflctl.hsf_ctrl.fldbcount = size - 1;
10508 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ0x0;
10509 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)))
10510 hsflctl.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)));
10511 /*
10512 * Write the last 24 bits of index into Flash Linear address
10513 * field in Flash Address
10514 */
10515 /* TODO: TBD maybe check the index against the size of flash */
10516
10517 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)))
10518 flash_linear_address)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)));
10519
10520 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT5000);
10521 /*
10522 * Check if FCERR is set to 1, if set to 1, clear it and try
10523 * the whole sequence a few more times, else read in (shift
10524 * in) the Flash Data0, the order is least significant byte
10525 * first msb to lsb
10526 */
10527 if (error == E1000_SUCCESS0) {
10528 flash_data = E1000_READ_ICH_FLASH_REG(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0010
)))
10529 ICH_FLASH_FDATA0)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0010
)));
10530 if (size == 1) {
10531 *data = (uint8_t) (flash_data & 0x000000FF);
10532 } else if (size == 2) {
10533 *data = (uint16_t) (flash_data & 0x0000FFFF);
10534 }
10535 break;
10536 } else {
10537 /*
10538 * If we've gotten here, then things are probably
10539 * completely hosed, but if the error condition is
10540 * detected, it won't hurt to give it another
10541 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10542 */
10543 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10544 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10545 if (hsfsts.hsf_status.flcerr == 1) {
10546 /* Repeat for some time before giving up. */
10547 continue;
10548 } else if (hsfsts.hsf_status.flcdone == 0) {
10549 DEBUGOUT("Timeout error - flash cycle did not"
10550 " complete.");
10551 break;
10552 }
10553 }
10554 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT10);
10555
10556 return error;
10557}
10558
10559STATIC int32_t
10560em_read_ich8_data32(struct em_hw *hw, uint32_t offset, uint32_t *data)
10561{
10562 union ich8_hws_flash_status hsfsts;
10563 union ich8_hws_flash_ctrl hsflctl;
10564 uint32_t flash_linear_address;
10565 int32_t error = -E1000_ERR_EEPROM1;
10566 uint32_t count = 0;
10567 DEBUGFUNC("em_read_ich8_data32");;
10568
10569 if (hw->mac_type < em_pch_spt)
10570 return error;
10571 if (offset > ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF)
10572 return error;
10573 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF & offset) +
10574 hw->flash_base_addr;
10575
10576 do {
10577 usec_delay(1)(*delay_func)(1);
10578 /* Steps */
10579 error = em_ich8_cycle_init(hw);
10580 if (error != E1000_SUCCESS0)
10581 break;
10582
10583 /* 32 bit accesses in SPT. */
10584 hsflctl.regval = E1000_READ_ICH_FLASH_REG32(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10585 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
))) >> 16;
10586
10587 hsflctl.hsf_ctrl.fldbcount = sizeof(uint32_t) - 1;
10588 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ0x0;
10589
10590 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_HSFSTS,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), ((uint32_t)hsflctl.regval << 16)))
10591 (uint32_t)hsflctl.regval << 16)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
), ((uint32_t)hsflctl.regval << 16)));
10592 /*
10593 * Write the last 24 bits of offset into Flash Linear address
10594 * field in Flash Address
10595 */
10596 /* TODO: TBD maybe check the offset against the size of flash */
10597
10598 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)))
10599 flash_linear_address)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)));
10600
10601 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT5000);
10602 /*
10603 * Check if FCERR is set to 1, if set to 1, clear it and try
10604 * the whole sequence a few more times, else read in (shift
10605 * in) the Flash Data0, the order is least significant byte
10606 * first msb to lsb
10607 */
10608 if (error == E1000_SUCCESS0) {
10609 (*data) = (uint32_t)E1000_READ_ICH_FLASH_REG32(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0010
)))
10610 ICH_FLASH_FDATA0)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0010
)));
10611 break;
10612 } else {
10613 /*
10614 * If we've gotten here, then things are probably
10615 * completely hosed, but if the error condition is
10616 * detected, it won't hurt to give it another
10617 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10618 */
10619 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10620 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10621 if (hsfsts.hsf_status.flcerr == 1) {
10622 /* Repeat for some time before giving up. */
10623 continue;
10624 } else if (hsfsts.hsf_status.flcdone == 0) {
10625 DEBUGOUT("Timeout error - flash cycle did not"
10626 " complete.");
10627 break;
10628 }
10629 }
10630 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT10);
10631
10632 return error;
10633}
10634
10635
10636/******************************************************************************
10637 * Writes One /two bytes to the NVM using the ICH8 flash access registers.
10638 *
10639 * hw - The pointer to the hw structure
10640 * index - The index of the byte/word to write.
10641 * size - Size of data to read, 1=byte 2=word
10642 * data - The byte(s) to write to the NVM.
10643 *****************************************************************************/
10644STATIC int32_t
10645em_write_ich8_data(struct em_hw *hw, uint32_t index, uint32_t size,
10646 uint16_t data)
10647{
10648 union ich8_hws_flash_status hsfsts;
10649 union ich8_hws_flash_ctrl hsflctl;
10650 uint32_t flash_linear_address;
10651 uint32_t flash_data = 0;
10652 int32_t error = -E1000_ERR_EEPROM1;
10653 int32_t count = 0;
10654 DEBUGFUNC("em_write_ich8_data");;
10655
10656 if (hw->mac_type >= em_pch_spt)
10657 return -E1000_ERR_EEPROM1;
10658 if (size < 1 || size > 2 || data > size * 0xff ||
10659 index > ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF)
10660 return error;
10661
10662 flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF & index) +
10663 hw->flash_base_addr;
10664
10665 do {
10666 usec_delay(1)(*delay_func)(1);
10667 /* Steps */
10668 error = em_ich8_cycle_init(hw);
10669 if (error != E1000_SUCCESS0)
10670 break;
10671
10672 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)))
10673 ICH_FLASH_HSFCTL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)));
10674 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
10675 hsflctl.hsf_ctrl.fldbcount = size - 1;
10676 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE0x2;
10677 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)))
10678 hsflctl.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)));
10679 /*
10680 * Write the last 24 bits of index into Flash Linear address
10681 * field in Flash Address
10682 */
10683 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)))
10684 flash_linear_address)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)));
10685
10686 if (size == 1)
10687 flash_data = (uint32_t) data & 0x00FF;
10688 else
10689 flash_data = (uint32_t) data;
10690
10691 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FDATA0, flash_data)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0010
), (flash_data)));
10692 /*
10693 * check if FCERR is set to 1 , if set to 1, clear it and try
10694 * the whole sequence a few more times else done
10695 */
10696 error = em_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT5000);
10697 if (error == E1000_SUCCESS0) {
10698 break;
10699 } else {
10700 /*
10701 * If we're here, then things are most likely
10702 * completely hosed, but if the error condition is
10703 * detected, it won't hurt to give it another
10704 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
10705 */
10706 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10707 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10708 if (hsfsts.hsf_status.flcerr == 1) {
10709 /* Repeat for some time before giving up. */
10710 continue;
10711 } else if (hsfsts.hsf_status.flcdone == 0) {
10712 DEBUGOUT("Timeout error - flash cycle did not"
10713 " complete.");
10714 break;
10715 }
10716 }
10717 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT10);
10718
10719 return error;
10720}
10721
10722/******************************************************************************
10723 * Reads a single byte from the NVM using the ICH8 flash access registers.
10724 *
10725 * hw - pointer to em_hw structure
10726 * index - The index of the byte to read.
10727 * data - Pointer to a byte to store the value read.
10728 *****************************************************************************/
10729STATIC int32_t
10730em_read_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t *data)
10731{
10732 int32_t status = E1000_SUCCESS0;
10733 uint16_t word = 0;
10734
10735 if (hw->mac_type >= em_pch_spt)
10736 return -E1000_ERR_EEPROM1;
10737 else
10738 status = em_read_ich8_data(hw, index, 1, &word);
10739 if (status == E1000_SUCCESS0) {
10740 *data = (uint8_t) word;
10741 }
10742 return status;
10743}
10744
10745/******************************************************************************
10746 * Writes a single byte to the NVM using the ICH8 flash access registers.
10747 * Performs verification by reading back the value and then going through
10748 * a retry algorithm before giving up.
10749 *
10750 * hw - pointer to em_hw structure
10751 * index - The index of the byte to write.
10752 * byte - The byte to write to the NVM.
10753 *****************************************************************************/
10754STATIC int32_t
10755em_verify_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t byte)
10756{
10757 int32_t error = E1000_SUCCESS0;
10758 int32_t program_retries = 0;
10759 DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
10760
10761 error = em_write_ich8_byte(hw, index, byte);
10762
10763 if (error != E1000_SUCCESS0) {
10764 for (program_retries = 0; program_retries < 100;
10765 program_retries++) {
10766 DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n",
10767 byte, index);
10768 error = em_write_ich8_byte(hw, index, byte);
10769 usec_delay(100)(*delay_func)(100);
10770 if (error == E1000_SUCCESS0)
10771 break;
10772 }
10773 }
10774 if (program_retries == 100)
10775 error = E1000_ERR_EEPROM1;
10776
10777 return error;
10778}
10779
10780/******************************************************************************
10781 * Writes a single byte to the NVM using the ICH8 flash access registers.
10782 *
10783 * hw - pointer to em_hw structure
10784 * index - The index of the byte to read.
10785 * data - The byte to write to the NVM.
10786 *****************************************************************************/
10787STATIC int32_t
10788em_write_ich8_byte(struct em_hw *hw, uint32_t index, uint8_t data)
10789{
10790 int32_t status = E1000_SUCCESS0;
10791 uint16_t word = (uint16_t) data;
10792 status = em_write_ich8_data(hw, index, 1, word);
10793
10794 return status;
10795}
10796
10797/******************************************************************************
10798 * Reads a dword from the NVM using the ICH8 flash access registers.
10799 *
10800 * hw - pointer to em_hw structure
10801 * index - The starting BYTE index of the word to read.
10802 * data - Pointer to a word to store the value read.
10803 *****************************************************************************/
10804STATIC int32_t
10805em_read_ich8_dword(struct em_hw *hw, uint32_t index, uint32_t *data)
10806{
10807 int32_t status = E1000_SUCCESS0;
10808 status = em_read_ich8_data32(hw, index, data);
10809 return status;
10810}
10811
10812/******************************************************************************
10813 * Reads a word from the NVM using the ICH8 flash access registers.
10814 *
10815 * hw - pointer to em_hw structure
10816 * index - The starting byte index of the word to read.
10817 * data - Pointer to a word to store the value read.
10818 *****************************************************************************/
10819STATIC int32_t
10820em_read_ich8_word(struct em_hw *hw, uint32_t index, uint16_t *data)
10821{
10822 int32_t status = E1000_SUCCESS0;
10823 status = em_read_ich8_data(hw, index, 2, data);
10824 return status;
10825}
10826
10827/******************************************************************************
10828 * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
10829 * based.
10830 *
10831 * hw - pointer to em_hw structure
10832 * bank - 0 for first bank, 1 for second bank
10833 *
10834 * Note that this function may actually erase as much as 8 or 64 KBytes. The
10835 * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the
10836 * bank size may be 4, 8 or 64 KBytes
10837 *****************************************************************************/
10838int32_t
10839em_erase_ich8_4k_segment(struct em_hw *hw, uint32_t bank)
10840{
10841 union ich8_hws_flash_status hsfsts;
10842 union ich8_hws_flash_ctrl hsflctl;
10843 uint32_t flash_linear_address;
10844 int32_t count = 0;
10845 int32_t error = E1000_ERR_EEPROM1;
10846 int32_t iteration;
10847 int32_t sub_sector_size = 0;
10848 int32_t bank_size;
10849 int32_t j = 0;
10850 int32_t error_flag = 0;
10851 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10852 /*
10853 * Determine HW Sector size: Read BERASE bits of Hw flash Status
10854 * register
10855 */
10856 /*
10857 * 00: The Hw sector is 256 bytes, hence we need to erase 16
10858 * consecutive sectors. The start index for the nth Hw sector can be
10859 * calculated as bank * 4096 + n * 256 01: The Hw sector is 4K bytes,
10860 * hence we need to erase 1 sector. The start index for the nth Hw
10861 * sector can be calculated as bank * 4096 10: The HW sector is 8K
10862 * bytes 11: The Hw sector size is 64K bytes
10863 */
10864 if (hsfsts.hsf_status.berasesz == 0x0) {
10865 /* Hw sector size 256 */
10866 sub_sector_size = ICH_FLASH_SEG_SIZE_256256;
10867 bank_size = ICH_FLASH_SECTOR_SIZE4096;
10868 iteration = ICH_FLASH_SECTOR_SIZE4096 / ICH_FLASH_SEG_SIZE_256256;
10869 } else if (hsfsts.hsf_status.berasesz == 0x1) {
10870 bank_size = ICH_FLASH_SEG_SIZE_4K4096;
10871 iteration = 1;
10872 } else if (hsfsts.hsf_status.berasesz == 0x2) {
10873 if (hw->mac_type == em_ich9lan) {
10874 uint32_t gfpreg, sector_base_addr, sector_end_addr;
10875 gfpreg = E1000_READ_ICH_FLASH_REG(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0000
)))
10876 ICH_FLASH_GFPREG)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0000
)));
10877 /*
10878 * sector_X_addr is a "sector"-aligned address (4096 bytes)
10879 * Add 1 to sector_end_addr since this sector is included in
10880 * the overall size.
10881 */
10882 sector_base_addr = gfpreg & ICH_GFPREG_BASE_MASK0x1FFF;
10883 sector_end_addr =
10884 ((gfpreg >> 16) & ICH_GFPREG_BASE_MASK0x1FFF) + 1;
10885
10886 /*
10887 * find total size of the NVM, then cut in half since the total
10888 * size represents two separate NVM banks.
10889 */
10890 bank_size = (sector_end_addr - sector_base_addr)
10891 << ICH_FLASH_SECT_ADDR_SHIFT12;
10892 bank_size /= 2;
10893 /* Word align */
10894 bank_size =
10895 (bank_size / sizeof(uint16_t)) * sizeof(uint16_t);
10896
10897 sub_sector_size = ICH_FLASH_SEG_SIZE_8K8192;
10898 iteration = bank_size / ICH_FLASH_SEG_SIZE_8K8192;
10899 } else {
10900 return error;
10901 }
10902 } else if (hsfsts.hsf_status.berasesz == 0x3) {
10903 bank_size = ICH_FLASH_SEG_SIZE_64K65536;
10904 iteration = 1;
10905 } else {
10906 return error;
10907 }
10908
10909 for (j = 0; j < iteration; j++) {
10910 do {
10911 count++;
10912 /* Steps */
10913 error = em_ich8_cycle_init(hw);
10914 if (error != E1000_SUCCESS0) {
10915 error_flag = 1;
10916 break;
10917 }
10918 /*
10919 * Write a value 11 (block Erase) in Flash Cycle
10920 * field in Hw flash Control
10921 */
10922 hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)))
10923 ICH_FLASH_HSFCTL)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
)));
10924 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE0x3;
10925 E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)))
10926 hsflctl.regval)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0006
), (hsflctl.regval)));
10927 /*
10928 * Write the last 24 bits of an index within the
10929 * block into Flash Linear address field in Flash
10930 * Address. This probably needs to be calculated
10931 * here based off the on-chip erase sector size and
10932 * the software bank size (4, 8 or 64 KBytes)
10933 */
10934 flash_linear_address =
10935 bank * bank_size + j * sub_sector_size;
10936 flash_linear_address += hw->flash_base_addr;
10937 flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK0x00FFFFFF;
10938
10939 E1000_WRITE_ICH_FLASH_REG32(hw, ICH_FLASH_FADDR,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)))
10940 flash_linear_address)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->write_4((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0008
), (flash_linear_address)));
10941
10942 error =
10943 em_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT3000000);
10944 /*
10945 * Check if FCERR is set to 1. If 1, clear it and
10946 * try the whole sequence a few more times else Done
10947 */
10948 if (error == E1000_SUCCESS0) {
10949 break;
10950 } else {
10951 hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw,((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)))
10952 ICH_FLASH_HSFSTS)((((struct em_osdep *)(hw)->back)->flash_bus_space_tag)
->read_2((((struct em_osdep *)(hw)->back)->flash_bus_space_handle
), (((struct em_osdep *)(hw)->back)->em_flashoffset + 0x0004
)));
10953 if (hsfsts.hsf_status.flcerr == 1) {
10954 /*
10955 * repeat for some time before giving
10956 * up
10957 */
10958 continue;
10959 } else if (hsfsts.hsf_status.flcdone == 0) {
10960 error_flag = 1;
10961 break;
10962 }
10963 }
10964 } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT10) && !error_flag);
10965 if (error_flag == 1)
10966 break;
10967 }
10968 if (error_flag != 1)
10969 error = E1000_SUCCESS0;
10970 return error;
10971}
10972
10973/******************************************************************************
10974 * Reads 16-bit words from the OTP. Return error when the word is not
10975 * stored in OTP.
10976 *
10977 * hw - Struct containing variables accessed by shared code
10978 * offset - offset of word in the OTP to read
10979 * data - word read from the OTP
10980 * words - number of words to read
10981 *****************************************************************************/
10982STATIC int32_t
10983em_read_invm_i210(struct em_hw *hw, uint16_t offset, uint16_t words,
10984 uint16_t *data)
10985{
10986 int32_t ret_val = E1000_SUCCESS0;
10987
10988 switch (offset)
10989 {
10990 case EEPROM_MAC_ADDR_WORD00x0000:
10991 case EEPROM_MAC_ADDR_WORD10x0001:
10992 case EEPROM_MAC_ADDR_WORD20x0002:
10993 /* Generate random MAC address if there's none. */
10994 ret_val = em_read_invm_word_i210(hw, offset, data);
10995 if (ret_val != E1000_SUCCESS0) {
10996 DEBUGOUT("MAC Addr not found in iNVM\n");
10997 *data = 0xFFFF;
10998 ret_val = E1000_SUCCESS0;
10999 }
11000 break;
11001 case EEPROM_INIT_CONTROL2_REG0x000F:
11002 ret_val = em_read_invm_word_i210(hw, offset, data);
11003 if (ret_val != E1000_SUCCESS0) {
11004 *data = NVM_INIT_CTRL_2_DEFAULT_I2110x7243;
11005 ret_val = E1000_SUCCESS0;
11006 }
11007 break;
11008 case EEPROM_INIT_CONTROL4_REG0x0013:
11009 ret_val = em_read_invm_word_i210(hw, offset, data);
11010 if (ret_val != E1000_SUCCESS0) {
11011 *data = NVM_INIT_CTRL_4_DEFAULT_I2110x00C1;
11012 ret_val = E1000_SUCCESS0;
11013 }
11014 break;
11015 case EEPROM_LED_1_CFG0x001C:
11016 ret_val = em_read_invm_word_i210(hw, offset, data);
11017 if (ret_val != E1000_SUCCESS0) {
11018 *data = NVM_LED_1_CFG_DEFAULT_I2110x0184;
11019 ret_val = E1000_SUCCESS0;
11020 }
11021 break;
11022 case EEPROM_LED_0_2_CFG0x001F:
11023 ret_val = em_read_invm_word_i210(hw, offset, data);
11024 if (ret_val != E1000_SUCCESS0) {
11025 *data = NVM_LED_0_2_CFG_DEFAULT_I2110x200C;
11026 ret_val = E1000_SUCCESS0;
11027 }
11028 break;
11029 case EEPROM_ID_LED_SETTINGS0x0004:
11030 ret_val = em_read_invm_word_i210(hw, offset, data);
11031 if (ret_val != E1000_SUCCESS0) {
11032 *data = ID_LED_RESERVED_FFFF0xFFFF;
11033 ret_val = E1000_SUCCESS0;
11034 }
11035 break;
11036 default:
11037 DEBUGOUT1("NVM word 0x%02x is not mapped.\n", offset);
11038 *data = NVM_RESERVED_WORD0xFFFF;
11039 break;
11040 }
11041
11042 return ret_val;
11043}
11044
11045/******************************************************************************
11046 * Reads 16-bit words from the OTP. Return error when the word is not
11047 * stored in OTP.
11048 *
11049 * hw - Struct containing variables accessed by shared code
11050 * offset - offset of word in the OTP to read
11051 * data - word read from the OTP
11052 *****************************************************************************/
11053STATIC int32_t
11054em_read_invm_word_i210(struct em_hw *hw, uint16_t address, uint16_t *data)
11055{
11056 int32_t error = -E1000_NOT_IMPLEMENTED14;
11057 uint32_t invm_dword;
11058 uint16_t i;
11059 uint8_t record_type, word_address;
11060
11061 for (i = 0; i < INVM_SIZE64; i++) {
11062 invm_dword = EM_READ_REG(hw, E1000_INVM_DATA_REG(i))((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), ((0x12120 + 4*(i)))));
11063 /* Get record type */
11064 record_type = INVM_DWORD_TO_RECORD_TYPE(invm_dword)((invm_dword) & 0x7);
11065 if (record_type == INVM_UNINITIALIZED_STRUCTURE0x0)
11066 break;
11067 if (record_type == INVM_CSR_AUTOLOAD_STRUCTURE0x2)
11068 i += INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS1;
11069 if (record_type == INVM_RSA_KEY_SHA256_STRUCTURE0x4)
11070 i += INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS8;
11071 if (record_type == INVM_WORD_AUTOLOAD_STRUCTURE0x1) {
11072 word_address = INVM_DWORD_TO_WORD_ADDRESS(invm_dword)(((invm_dword) & 0x0000FE00) >> 9);
11073 if (word_address == address) {
11074 *data = INVM_DWORD_TO_WORD_DATA(invm_dword)(((invm_dword) & 0xFFFF0000) >> 16);
11075 error = E1000_SUCCESS0;
11076 break;
11077 }
11078 }
11079 }
11080
11081 return error;
11082}
11083
11084STATIC int32_t
11085em_init_lcd_from_nvm_config_region(struct em_hw *hw, uint32_t cnf_base_addr,
11086 uint32_t cnf_size)
11087{
11088 uint32_t ret_val = E1000_SUCCESS0;
11089 uint16_t word_addr, reg_data, reg_addr;
11090 uint16_t i;
11091 /* cnf_base_addr is in DWORD */
11092 word_addr = (uint16_t) (cnf_base_addr << 1);
11093
11094 /* cnf_size is returned in size of dwords */
11095 for (i = 0; i < cnf_size; i++) {
11096 ret_val =
11097 em_read_eeprom(hw, (word_addr + i * 2), 1, &reg_data);
11098 if (ret_val)
11099 return ret_val;
11100
11101 ret_val =
11102 em_read_eeprom(hw, (word_addr + i * 2 + 1), 1, &reg_addr);
11103 if (ret_val)
11104 return ret_val;
11105
11106 ret_val = em_get_software_flag(hw);
11107 if (ret_val != E1000_SUCCESS0)
11108 return ret_val;
11109
11110 ret_val =
11111 em_write_phy_reg_ex(hw, (uint32_t) reg_addr, reg_data);
11112
11113 em_release_software_flag(hw);
11114 }
11115
11116 return ret_val;
11117}
11118
11119/******************************************************************************
11120 * This function initializes the PHY from the NVM on ICH8 platforms. This
11121 * is needed due to an issue where the NVM configuration is not properly
11122 * autoloaded after power transitions. Therefore, after each PHY reset, we
11123 * will load the configuration data out of the NVM manually.
11124 *
11125 * hw: Struct containing variables accessed by shared code
11126 *****************************************************************************/
11127STATIC int32_t
11128em_init_lcd_from_nvm(struct em_hw *hw)
11129{
11130 uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop, sw_cfg_mask;
11131 if (hw->phy_type != em_phy_igp_3)
11132 return E1000_SUCCESS0;
11133
11134 /* Check if SW needs configure the PHY */
11135 if (hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT0x1049 ||
11136 hw->device_id == E1000_DEV_ID_ICH8_IGP_M0x104D ||
11137 hw->mac_type == em_pchlan ||
11138 hw->mac_type == em_pch2lan ||
11139 hw->mac_type == em_pch_lpt ||
11140 hw->mac_type == em_pch_spt ||
11141 hw->mac_type == em_pch_cnp ||
11142 hw->mac_type == em_pch_tgp ||
11143 hw->mac_type == em_pch_adp)
11144 sw_cfg_mask = FEXTNVM_SW_CONFIG_ICH8M(1 << 27);
11145 else
11146 sw_cfg_mask = FEXTNVM_SW_CONFIG1;
11147
11148 reg_data = E1000_READ_REG(hw, FEXTNVM)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00028 : em_translate_82542_register
(0x00028)))));
11149 if (!(reg_data & sw_cfg_mask))
11150 return E1000_SUCCESS0;
11151
11152 /* Wait for basic configuration completes before proceeding */
11153 loop = 0;
11154 do {
11155 reg_data =
11156 E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))))) & E1000_STATUS_LAN_INIT_DONE0x00000200;
11157 usec_delay(100)(*delay_func)(100);
11158 loop++;
11159 } while ((!reg_data) && (loop < 50));
11160
11161 /* Clear the Init Done bit for the next init event */
11162 reg_data = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
11163 reg_data &= ~E1000_STATUS_LAN_INIT_DONE0x00000200;
11164 E1000_WRITE_REG(hw, STATUS, reg_data)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008))), (reg_data)));
11165 /*
11166 * Make sure HW does not configure LCD from PHY extended
11167 * configuration before SW configuration
11168 */
11169 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
11170 if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE0x00000001) == 0x0000) {
11171 reg_data = E1000_READ_REG(hw, EXTCNF_SIZE)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F08 : em_translate_82542_register
(0x00F08)))));
11172 cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH0x00FF0000;
11173 cnf_size >>= 16;
11174 if (cnf_size) {
11175 reg_data = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
11176 cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER0x0FFF0000;
11177 /* cnf_base_addr is in DWORD */
11178 cnf_base_addr >>= 16;
11179
11180 /* Configure LCD from extended configuration region. */
11181 ret_val = em_init_lcd_from_nvm_config_region(hw,
11182 cnf_base_addr, cnf_size);
11183 if (ret_val)
11184 return ret_val;
11185 }
11186 }
11187 return E1000_SUCCESS0;
11188}
11189
11190/******************************************************************************
11191 * em_set_pciex_completion_timeout - set pci-e completion timeout
11192 *
11193 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
11194 * however the hardware default for these parts is 500us to 1ms which is less
11195 * than the 10ms recommended by the pci-e spec. To address this we need to
11196 * increase the value to either 10ms to 200ms for capability version 1 config,
11197 * or 16ms to 55ms for version 2.
11198 *
11199 * * hw - pointer to em_hw structure
11200 *****************************************************************************/
11201int32_t
11202em_set_pciex_completion_timeout(struct em_hw *hw)
11203{
11204 uint32_t gcr = E1000_READ_REG(hw, GCR)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00)))));
11205 int32_t ret_val = E1000_SUCCESS0;
11206
11207 /* Only take action if timeout value is not set by system BIOS */
11208 if (gcr & E1000_GCR_CMPL_TMOUT_MASK0x0000F000)
11209 goto out;
11210
11211 DEBUGOUT("PCIe completion timeout not set by system BIOS.");
11212
11213 /*
11214 * If capabilities version is type 1 we can write the
11215 * timeout of 10ms to 200ms through the GCR register
11216 */
11217
11218 if (!(gcr & E1000_GCR_CAP_VER20x00040000)) {
11219 gcr |= E1000_GCR_CMPL_TMOUT_10ms0x00001000;
11220 DEBUGOUT("PCIe capability version 1 detected, setting \
11221 completion timeout to 10ms.");
11222 goto out;
11223 }
11224
11225 /*
11226 * For version 2 capabilities we need to write the config space
11227 * directly in order to set the completion timeout value for
11228 * 16ms to 55ms
11229 *
11230 * XXX: Implement em_*_pcie_cap_reg() first.
11231 */
11232#if 0
11233 ret_val = em_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
11234 &pciex_devctl2);
11235
11236 if (ret_val)
11237 goto out;
11238
11239 pciex_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
11240
11241 ret_val = em_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
11242 &pciex_devctl2);
11243#endif
11244
11245out:
11246
11247 /* Disable completion timeout resend */
11248 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND0x00010000;
11249
11250 DEBUGOUT("PCIe completion timeout resend disabled.");
11251
11252 E1000_WRITE_REG(hw, GCR, gcr)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x05B00 : em_translate_82542_register
(0x05B00))), (gcr)));
11253 return ret_val;
11254}
11255
11256/***************************************************************************
11257 * Set slow MDIO access mode
11258 ***************************************************************************/
11259static int32_t
11260em_set_mdio_slow_mode_hv(struct em_hw *hw)
11261{
11262 int32_t ret_val;
11263 uint16_t data;
11264 DEBUGFUNC("em_set_mdio_slow_mode_hv");;
11265
11266 ret_val = em_read_phy_reg(hw, HV_KMRN_MODE_CTRL(((769) << 5) | ((16) & 0x1F)), &data);
11267 if (ret_val)
11268 return ret_val;
11269
11270 data |= HV_KMRN_MDIO_SLOW0x0400;
11271
11272 ret_val = em_write_phy_reg(hw, HV_KMRN_MODE_CTRL(((769) << 5) | ((16) & 0x1F)), data);
11273
11274 return ret_val;
11275}
11276
11277/***************************************************************************
11278 * A series of Phy workarounds to be done after every PHY reset.
11279 ***************************************************************************/
11280int32_t
11281em_hv_phy_workarounds_ich8lan(struct em_hw *hw)
11282{
11283 int32_t ret_val = E1000_SUCCESS0;
11284 uint16_t phy_data;
11285 uint16_t swfw;
11286 DEBUGFUNC("em_hv_phy_workarounds_ich8lan");;
11287
11288 if (hw->mac_type != em_pchlan)
11289 goto out;
11290
11291 swfw = E1000_SWFW_PHY0_SM0x0002;
11292
11293 /* Set MDIO slow mode before any other MDIO access */
11294 if (hw->phy_type == em_phy_82577 ||
11295 hw->phy_type == em_phy_82578) {
11296 ret_val = em_set_mdio_slow_mode_hv(hw);
11297 if (ret_val)
11298 goto out;
11299 }
11300
11301 /* Hanksville M Phy init for IEEE. */
11302 if ((hw->revision_id == 2) &&
11303 (hw->phy_type == em_phy_82577) &&
11304 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) {
11305 em_write_phy_reg(hw, 0x10, 0x8823);
11306 em_write_phy_reg(hw, 0x11, 0x0018);
11307 em_write_phy_reg(hw, 0x10, 0x8824);
11308 em_write_phy_reg(hw, 0x11, 0x0016);
11309 em_write_phy_reg(hw, 0x10, 0x8825);
11310 em_write_phy_reg(hw, 0x11, 0x001A);
11311 em_write_phy_reg(hw, 0x10, 0x888C);
11312 em_write_phy_reg(hw, 0x11, 0x0007);
11313 em_write_phy_reg(hw, 0x10, 0x888D);
11314 em_write_phy_reg(hw, 0x11, 0x0007);
11315 em_write_phy_reg(hw, 0x10, 0x888E);
11316 em_write_phy_reg(hw, 0x11, 0x0007);
11317 em_write_phy_reg(hw, 0x10, 0x8827);
11318 em_write_phy_reg(hw, 0x11, 0x0001);
11319 em_write_phy_reg(hw, 0x10, 0x8835);
11320 em_write_phy_reg(hw, 0x11, 0x0001);
11321 em_write_phy_reg(hw, 0x10, 0x8834);
11322 em_write_phy_reg(hw, 0x11, 0x0001);
11323 em_write_phy_reg(hw, 0x10, 0x8833);
11324 em_write_phy_reg(hw, 0x11, 0x0002);
11325 }
11326
11327 if (((hw->phy_type == em_phy_82577) &&
11328 ((hw->phy_revision == 1) || (hw->phy_revision == 2))) ||
11329 ((hw->phy_type == em_phy_82578) && (hw->phy_revision == 1))) {
11330 /* Disable generation of early preamble */
11331 ret_val = em_write_phy_reg(hw, PHY_REG(769, 25)(((769) << 5) | ((25) & 0x1F)), 0x4431);
11332 if (ret_val)
11333 goto out;
11334
11335 /* Preamble tuning for SSC */
11336 ret_val = em_write_phy_reg(hw, PHY_REG(770, 16)(((770) << 5) | ((16) & 0x1F)), 0xA204);
11337 if (ret_val)
11338 goto out;
11339 }
11340
11341 if (hw->phy_type == em_phy_82578) {
11342 /*
11343 * Return registers to default by doing a soft reset then
11344 * writing 0x3140 to the control register.
11345 */
11346 if (hw->phy_revision < 2) {
11347 em_phy_reset(hw);
11348 ret_val = em_write_phy_reg(hw, PHY_CTRL0x00, 0x3140);
11349 }
11350 }
11351
11352 if ((hw->revision_id == 2) &&
11353 (hw->phy_type == em_phy_82577) &&
11354 ((hw->phy_revision == 2) || (hw->phy_revision == 3))) {
11355 /*
11356 * Workaround for OEM (GbE) not operating after reset -
11357 * restart AN (twice)
11358 */
11359 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25)(((0) << 5) | ((25) & 0x1F)), 0x0400);
11360 if (ret_val)
11361 goto out;
11362 ret_val = em_write_phy_reg(hw, PHY_REG(0, 25)(((0) << 5) | ((25) & 0x1F)), 0x0400);
11363 if (ret_val)
11364 goto out;
11365 }
11366
11367 /* Select page 0 */
11368 ret_val = em_swfw_sync_acquire(hw, swfw);
11369 if (ret_val)
11370 goto out;
11371
11372 hw->phy_addr = 1;
11373 ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PAGE_SELECT0x1F, 0);
11374 em_swfw_sync_release(hw, swfw);
11375 if (ret_val)
11376 goto out;
11377
11378 /* Workaround for link disconnects on a busy hub in half duplex */
11379 ret_val = em_read_phy_reg(hw,
11380 PHY_REG(BM_PORT_CTRL_PAGE, 17)(((769) << 5) | ((17) & 0x1F)),
11381 &phy_data);
11382 if (ret_val)
11383 goto release;
11384 ret_val = em_write_phy_reg(hw,
11385 PHY_REG(BM_PORT_CTRL_PAGE, 17)(((769) << 5) | ((17) & 0x1F)),
11386 phy_data & 0x00FF);
11387release:
11388out:
11389 return ret_val;
11390}
11391
11392
11393/***************************************************************************
11394 * Si workaround
11395 *
11396 * This function works around a Si bug where the link partner can get
11397 * a link up indication before the PHY does. If small packets are sent
11398 * by the link partner they can be placed in the packet buffer without
11399 * being properly accounted for by the PHY and will stall preventing
11400 * further packets from being received. The workaround is to clear the
11401 * packet buffer after the PHY detects link up.
11402 ***************************************************************************/
11403int32_t
11404em_link_stall_workaround_hv(struct em_hw *hw)
11405{
11406 int32_t ret_val = E1000_SUCCESS0;
11407 uint16_t phy_data;
11408
11409 if (hw->phy_type != em_phy_82578)
11410 goto out;
11411
11412 /* Do not apply workaround if in PHY loopback bit 14 set */
11413 em_read_phy_reg(hw, PHY_CTRL0x00, &phy_data);
11414 if (phy_data & E1000_PHY_CTRL_LOOPBACK0x00004000)
11415 goto out;
11416
11417 /* check if link is up and at 1Gbps */
11418 ret_val = em_read_phy_reg(hw, BM_CS_STATUS17, &phy_data);
11419 if (ret_val)
11420 goto out;
11421
11422 phy_data &= BM_CS_STATUS_LINK_UP0x0400 |
11423 BM_CS_STATUS_RESOLVED0x0800 |
11424 BM_CS_STATUS_SPEED_MASK0xC000;
11425
11426 if (phy_data != (BM_CS_STATUS_LINK_UP0x0400 |
11427 BM_CS_STATUS_RESOLVED0x0800 |
11428 BM_CS_STATUS_SPEED_10000x8000))
11429 goto out;
11430
11431 msec_delay(200)(*delay_func)(1000*(200));
11432
11433 /* flush the packets in the fifo buffer */
11434 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL(((776) << 5) | ((16) & 0x1F)),
11435 HV_MUX_DATA_CTRL_GEN_TO_MAC0x0400 | HV_MUX_DATA_CTRL_FORCE_SPEED0x0004);
11436 if (ret_val)
11437 goto out;
11438
11439 ret_val = em_write_phy_reg(hw, HV_MUX_DATA_CTRL(((776) << 5) | ((16) & 0x1F)),
11440 HV_MUX_DATA_CTRL_GEN_TO_MAC0x0400);
11441
11442out:
11443 return ret_val;
11444}
11445
11446/****************************************************************************
11447 * K1 Si workaround
11448 *
11449 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
11450 * from a lower speed. This workaround disables K1 whenever link is at 1Gig.
11451 * If link is down, the function will restore the default K1 setting located
11452 * in the NVM.
11453 ****************************************************************************/
11454int32_t
11455em_k1_gig_workaround_hv(struct em_hw *hw, boolean_t link)
11456{
11457 int32_t ret_val;
11458 uint16_t phy_data;
11459 boolean_t k1_enable;
11460
11461 DEBUGFUNC("em_k1_gig_workaround_hv");;
11462
11463 if (hw->mac_type != em_pchlan)
11464 return E1000_SUCCESS0;
11465
11466 ret_val = em_read_eeprom_ich8(hw, E1000_NVM_K1_CONFIG0x1B, 1, &phy_data);
11467 if (ret_val)
11468 return ret_val;
11469
11470 k1_enable = phy_data & E1000_NVM_K1_ENABLE0x1 ? TRUE1 : FALSE0;
11471
11472 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
11473 if (link) {
11474 if (hw->phy_type == em_phy_82578) {
11475 ret_val = em_read_phy_reg(hw, BM_CS_STATUS17,
11476 &phy_data);
11477 if (ret_val)
11478 return ret_val;
11479
11480 phy_data &= BM_CS_STATUS_LINK_UP0x0400 |
11481 BM_CS_STATUS_RESOLVED0x0800 |
11482 BM_CS_STATUS_SPEED_MASK0xC000;
11483
11484 if (phy_data == (BM_CS_STATUS_LINK_UP0x0400 |
11485 BM_CS_STATUS_RESOLVED0x0800 |
11486 BM_CS_STATUS_SPEED_10000x8000))
11487 k1_enable = FALSE0;
11488 }
11489
11490 if (hw->phy_type == em_phy_82577) {
11491 ret_val = em_read_phy_reg(hw, HV_M_STATUS26,
11492 &phy_data);
11493 if (ret_val)
11494 return ret_val;
11495
11496 phy_data &= HV_M_STATUS_LINK_UP0x0040 |
11497 HV_M_STATUS_AUTONEG_COMPLETE0x1000 |
11498 HV_M_STATUS_SPEED_MASK0x0300;
11499
11500 if (phy_data == (HV_M_STATUS_LINK_UP0x0040 |
11501 HV_M_STATUS_AUTONEG_COMPLETE0x1000 |
11502 HV_M_STATUS_SPEED_10000x0200))
11503 k1_enable = FALSE0;
11504 }
11505
11506 /* Link stall fix for link up */
11507 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19)(((770) << 5) | ((19) & 0x1F)),
11508 0x0100);
11509 if (ret_val)
11510 return ret_val;
11511
11512 } else {
11513 /* Link stall fix for link down */
11514 ret_val = em_write_phy_reg(hw, PHY_REG(770, 19)(((770) << 5) | ((19) & 0x1F)),
11515 0x4100);
11516 if (ret_val)
11517 return ret_val;
11518 }
11519
11520 ret_val = em_configure_k1_ich8lan(hw, k1_enable);
11521
11522 return ret_val;
11523}
11524
11525/* Workaround to set the K1 beacon duration for 82579 parts */
11526int32_t
11527em_k1_workaround_lv(struct em_hw *hw)
11528{
11529 int32_t ret_val;
11530 uint16_t phy_data;
11531 uint32_t mac_reg;
11532
11533 ret_val = em_read_phy_reg(hw, BM_CS_STATUS17, &phy_data);
11534 if (ret_val)
11535 return ret_val;
11536
11537 if ((phy_data & (HV_M_STATUS_LINK_UP0x0040 | HV_M_STATUS_AUTONEG_COMPLETE0x1000))
11538 == (HV_M_STATUS_LINK_UP0x0040 | HV_M_STATUS_AUTONEG_COMPLETE0x1000)) {
11539 mac_reg = E1000_READ_REG(hw, FEXTNVM4)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00024 : em_translate_82542_register
(0x00024)))));
11540 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK0x7;
11541
11542 if (phy_data & HV_M_STATUS_SPEED_10000x0200)
11543 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC0x7;
11544 else
11545 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC0x3;
11546
11547 E1000_WRITE_REG(hw, FEXTNVM4, mac_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00024 : em_translate_82542_register
(0x00024))), (mac_reg)));
11548 }
11549
11550 return E1000_SUCCESS0;
11551}
11552
11553/**
11554 * em_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
11555 *
11556 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
11557 * preventing further DMA write requests. Workaround the issue by disabling
11558 * the de-assertion of the clock request when in 1Gbps mode.
11559 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
11560 * speeds in order to avoid Tx hangs.
11561 **/
11562int32_t
11563em_k1_workaround_lpt_lp(struct em_hw *hw, boolean_t link)
11564{
11565 uint32_t fextnvm6 = E1000_READ_REG(hw, FEXTNVM6)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010)))));
11566 uint32_t status = E1000_READ_REG(hw, STATUS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00008 : em_translate_82542_register
(0x00008)))));
11567 int32_t ret_val = E1000_SUCCESS0;
11568 uint16_t reg;
11569
11570 if (link && (status & E1000_STATUS_SPEED_10000x00000080)) {
11571 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG0x7,
11572 &reg);
11573 if (ret_val)
11574 return ret_val;
11575
11576 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG0x7,
11577 reg & ~E1000_KMRNCTRLSTA_K1_ENABLE0x0002);
11578 if (ret_val)
11579 return ret_val;
11580
11581 usec_delay(10)(*delay_func)(10);
11582
11583 E1000_WRITE_REG(hw, FEXTNVM6,((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (fextnvm6 | 0x00000100)))
11584 fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (fextnvm6 | 0x00000100)));
11585
11586 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG0x7,
11587 reg);
11588 } else {
11589 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
11590 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK0x00000100;
11591
11592 if (!link || ((status & E1000_STATUS_SPEED_1000x00000040) &&
11593 (status & E1000_STATUS_FD0x00000001)))
11594 goto update_fextnvm6;
11595
11596 ret_val = em_read_phy_reg(hw, I217_INBAND_CTRL(((770) << 5) | ((18) & 0x1F)), &reg);
11597 if (ret_val)
11598 return ret_val;
11599
11600 /* Clear link status transmit timeout */
11601 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK0x3F00;
11602
11603 if (status & E1000_STATUS_SPEED_1000x00000040) {
11604 /* Set inband Tx timeout to 5x10us for 100Half */
11605 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT8;
11606
11607 /* Do not extend the K1 entry latency for 100Half */
11608 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION0x00000200;
11609 } else {
11610 /* Set inband Tx timeout to 50x10us for 10Full/Half */
11611 reg |= 50 <<
11612 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT8;
11613
11614 /* Extend the K1 entry latency for 10 Mbps */
11615 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION0x00000200;
11616 }
11617
11618 ret_val = em_write_phy_reg(hw, I217_INBAND_CTRL(((770) << 5) | ((18) & 0x1F)), reg);
11619 if (ret_val)
11620 return ret_val;
11621
11622update_fextnvm6:
11623 E1000_WRITE_REG(hw, FEXTNVM6, fextnvm6)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00010 : em_translate_82542_register
(0x00010))), (fextnvm6)));
11624 }
11625
11626 return ret_val;
11627
11628}
11629
11630
11631/***************************************************************************
11632 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
11633 * @hw: pointer to the HW structure
11634 * @gate: boolean set to TRUE to gate, FALSE to ungate
11635 *
11636 * Gate/ungate the automatic PHY configuration via hardware; perform
11637 * the configuration via software instead.
11638 ***************************************************************************/
11639void
11640em_gate_hw_phy_config_ich8lan(struct em_hw *hw, boolean_t gate)
11641{
11642 uint32_t extcnf_ctrl;
11643
11644 DEBUGFUNC("em_gate_hw_phy_config_ich8lan");;
11645
11646 if (hw->mac_type != em_pch2lan)
11647 return;
11648
11649 extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00)))));
11650
11651 if (gate)
11652 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG0x00000080;
11653 else
11654 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG0x00000080;
11655
11656 E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00F00 : em_translate_82542_register
(0x00F00))), (extcnf_ctrl)));
11657}
11658
11659/***************************************************************************
11660 * Configure K1 power state
11661 *
11662 * Configure the K1 power state based on the provided parameter.
11663 * Assumes semaphore already acquired.
11664 *
11665 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
11666 ***************************************************************************/
11667int32_t
11668em_configure_k1_ich8lan(struct em_hw *hw, boolean_t k1_enable)
11669{
11670 int32_t ret_val = E1000_SUCCESS0;
11671 uint32_t ctrl_reg = 0;
11672 uint32_t ctrl_ext = 0;
11673 uint32_t reg = 0;
11674 uint16_t kmrn_reg = 0;
11675
11676 ret_val = em_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG0x7,
11677 &kmrn_reg);
11678 if (ret_val)
11679 goto out;
11680
11681 if (k1_enable)
11682 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE0x0002;
11683 else
11684 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE0x0002;
11685
11686 ret_val = em_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_K1_CONFIG0x7,
11687 kmrn_reg);
11688 if (ret_val)
11689 goto out;
11690
11691 usec_delay(20)(*delay_func)(20);
11692 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018)))));
11693 ctrl_reg = E1000_READ_REG(hw, CTRL)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000)))));
11694
11695 reg = ctrl_reg & ~(E1000_CTRL_SPD_10000x00000200 | E1000_CTRL_SPD_1000x00000100);
11696 reg |= E1000_CTRL_FRCSPD0x00000800;
11697 E1000_WRITE_REG(hw, CTRL, reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (reg)));
11698
11699 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext | 0x00008000)));
11700 usec_delay(20)(*delay_func)(20);
11701 E1000_WRITE_REG(hw, CTRL, ctrl_reg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00000 : em_translate_82542_register
(0x00000))), (ctrl_reg)));
11702 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (((hw)->mac_type >= em_82543 ? 0x00018 : em_translate_82542_register
(0x00018))), (ctrl_ext)));
11703 usec_delay(20)(*delay_func)(20);
11704
11705out:
11706 return ret_val;
11707}
11708
11709/***************************************************************************
11710 * em_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
11711 * done after every PHY reset.
11712 ***************************************************************************/
11713int32_t
11714em_lv_phy_workarounds_ich8lan(struct em_hw *hw)
11715{
11716 int32_t ret_val = E1000_SUCCESS0;
11717 uint16_t swfw;
11718
11719 DEBUGFUNC("e1000_lv_phy_workarounds_ich8lan");;
11720
11721 if (hw->mac_type != em_pch2lan)
11722 goto out;
11723
11724 /* Set MDIO slow mode before any other MDIO access */
11725 ret_val = em_set_mdio_slow_mode_hv(hw);
11726
11727 swfw = E1000_SWFW_PHY0_SM0x0002;
11728 ret_val = em_swfw_sync_acquire(hw, swfw);
11729 if (ret_val)
11730 goto out;
11731 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR0x10,
11732 I82579_MSE_THRESHOLD0x084F);
11733 if (ret_val)
11734 goto release;
11735 /* set MSE higher to enable link to stay up when noise is high */
11736 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA0x11,
11737 0x0034);
11738 if (ret_val)
11739 goto release;
11740 ret_val = em_write_phy_reg(hw, I82579_EMI_ADDR0x10,
11741 I82579_MSE_LINK_DOWN0x2411);
11742 if (ret_val)
11743 goto release;
11744 /* drop link after 5 times MSE threshold was reached */
11745 ret_val = em_write_phy_reg(hw, I82579_EMI_DATA0x11,
11746 0x0005);
11747release:
11748 em_swfw_sync_release(hw, swfw);
11749
11750out:
11751 return ret_val;
11752}
11753
11754int32_t
11755em_set_eee_i350(struct em_hw *hw)
11756{
11757 int32_t ret_val = E1000_SUCCESS0;
11758 uint32_t ipcnfg, eeer;
11759
11760 if ((hw->mac_type < em_i350) ||
11761 (hw->media_type != em_media_type_copper))
11762 goto out;
11763 ipcnfg = EM_READ_REG(hw, E1000_IPCNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x0E38)));
11764 eeer = EM_READ_REG(hw, E1000_EEER)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x0E30)));
11765
11766 if (hw->eee_enable) {
11767 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN0x00000008 | E1000_IPCNFG_EEE_100M_AN0x00000004);
11768 eeer |= (E1000_EEER_TX_LPI_EN0x00010000 | E1000_EEER_RX_LPI_EN0x00020000 |
11769 E1000_EEER_LPI_FC0x00040000);
11770 } else {
11771 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN0x00000008 | E1000_IPCNFG_EEE_100M_AN0x00000004);
11772 eeer &= ~(E1000_EEER_TX_LPI_EN0x00010000 | E1000_EEER_RX_LPI_EN0x00020000 |
11773 E1000_EEER_LPI_FC0x00040000);
11774 }
11775 EM_WRITE_REG(hw, E1000_IPCNFG, ipcnfg)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x0E38), (ipcnfg)));
11776 EM_WRITE_REG(hw, E1000_EEER, eeer)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
write_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x0E30), (eeer)));
11777 EM_READ_REG(hw, E1000_IPCNFG)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x0E38)));
11778 EM_READ_REG(hw, E1000_EEER)((((struct em_osdep *)(hw)->back)->mem_bus_space_tag)->
read_4((((struct em_osdep *)(hw)->back)->mem_bus_space_handle
), (0x0E30)));
11779out:
11780 return ret_val;
11781}
11782
11783/***************************************************************************
11784 * em_set_eee_pchlan - Enable/disable EEE support
11785 * @hw: pointer to the HW structure
11786 *
11787 * Enable/disable EEE based on setting in dev_spec structure. The bits in
11788 * the LPI Control register will remain set only if/when link is up.
11789 ***************************************************************************/
11790int32_t
11791em_set_eee_pchlan(struct em_hw *hw)
11792{
11793 int32_t ret_val = E1000_SUCCESS0;
11794 uint16_t phy_reg;
11795
11796 DEBUGFUNC("em_set_eee_pchlan");;
11797
11798 if (hw->phy_type != em_phy_82579 &&
11799 hw->phy_type != em_phy_i217)
11800 goto out;
11801
11802 ret_val = em_read_phy_reg(hw, I82579_LPI_CTRL(((772) << 5) | ((20) & 0x1F)), &phy_reg);
11803 if (ret_val)
11804 goto out;
11805
11806 if (hw->eee_enable)
11807 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK0x6000;
11808 else
11809 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK0x6000;
11810
11811 ret_val = em_write_phy_reg(hw, I82579_LPI_CTRL(((772) << 5) | ((20) & 0x1F)), phy_reg);
11812out:
11813 return ret_val;
11814}
11815
11816/**
11817 * em_initialize_M88E1512_phy - Initialize M88E1512 PHY
11818 * @hw: pointer to the HW structure
11819 *
11820 * Initialize Marvell 1512 to work correctly with Avoton.
11821 **/
11822int32_t
11823em_initialize_M88E1512_phy(struct em_hw *hw)
11824{
11825 int32_t ret_val = E1000_SUCCESS0;
11826
11827 DEBUGFUNC("e1000_initialize_M88E1512_phy");;
11828
11829 /* Check if this is correct PHY. */
11830 if (hw->phy_id != M88E1512_E_PHY_ID0x01410DD0)
11831 goto out;
11832
11833 /* Switch to PHY page 0xFF. */
11834 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR0x16, 0x00FF);
11835 if (ret_val)
11836 goto out;
11837
11838 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_20x0011, 0x214B);
11839 if (ret_val)
11840 goto out;
11841
11842 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_10x0010, 0x2144);
11843 if (ret_val)
11844 goto out;
11845
11846 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_20x0011, 0x0C28);
11847 if (ret_val)
11848 goto out;
11849
11850 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_10x0010, 0x2146);
11851 if (ret_val)
11852 goto out;
11853
11854 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_20x0011, 0xB233);
11855 if (ret_val)
11856 goto out;
11857
11858 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_10x0010, 0x214D);
11859 if (ret_val)
11860 goto out;
11861
11862 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_20x0011, 0xCC0C);
11863 if (ret_val)
11864 goto out;
11865
11866 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_10x0010, 0x2159);
11867 if (ret_val)
11868 goto out;
11869
11870 /* Switch to PHY page 0xFB. */
11871 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR0x16, 0x00FB);
11872 if (ret_val)
11873 goto out;
11874
11875 ret_val = em_write_phy_reg(hw, M88E1512_CFG_REG_30x0007, 0x000D);
11876 if (ret_val)
11877 goto out;
11878
11879 /* Switch to PHY page 0x12. */
11880 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR0x16, 0x12);
11881 if (ret_val)
11882 goto out;
11883
11884 /* Change mode to SGMII-to-Copper */
11885 ret_val = em_write_phy_reg(hw, M88E1512_MODE0x0014, 0x8001);
11886 if (ret_val)
11887 goto out;
11888
11889 /* Return the PHY to page 0. */
11890 ret_val = em_write_phy_reg(hw, M88E1543_PAGE_ADDR0x16, 0);
11891 if (ret_val)
11892 goto out;
11893
11894 ret_val = em_phy_hw_reset(hw);
11895 if (ret_val) {
11896 DEBUGOUT("Error committing the PHY changes\n");
11897 return ret_val;
11898 }
11899
11900 msec_delay(1000)(*delay_func)(1000*(1000));
11901out:
11902 return ret_val;
11903}
11904
11905uint32_t
11906em_translate_82542_register(uint32_t reg)
11907{
11908 /*
11909 * Some of the 82542 registers are located at different
11910 * offsets than they are in newer adapters.
11911 * Despite the difference in location, the registers
11912 * function in the same manner.
11913 */
11914 switch (reg) {
11915 case E1000_RA0x05400:
11916 reg = 0x00040;
11917 break;
11918 case E1000_RDTR0x02820:
11919 reg = 0x00108;
11920 break;
11921 case E1000_RDBAL(0)((0) < 4 ? (0x02800 + ((0) * 0x100)) : (0x0C000 + ((0) * 0x40
))):
11922 reg = 0x00110;
11923 break;
11924 case E1000_RDBAH(0)((0) < 4 ? (0x02804 + ((0) * 0x100)) : (0x0C004 + ((0) * 0x40
))):
11925 reg = 0x00114;
11926 break;
11927 case E1000_RDLEN(0)((0) < 4 ? (0x02808 + ((0) * 0x100)) : (0x0C008 + ((0) * 0x40
))):
11928 reg = 0x00118;
11929 break;
11930 case E1000_RDH(0)((0) < 4 ? (0x02810 + ((0) * 0x100)) : (0x0C010 + ((0) * 0x40
))):
11931 reg = 0x00120;
11932 break;
11933 case E1000_RDT(0)((0) < 4 ? (0x02818 + ((0) * 0x100)) : (0x0C018 + ((0) * 0x40
))):
11934 reg = 0x00128;
11935 break;
11936 case E1000_RDBAL(1)((1) < 4 ? (0x02800 + ((1) * 0x100)) : (0x0C000 + ((1) * 0x40
))):
11937 reg = 0x00138;
11938 break;
11939 case E1000_RDBAH(1)((1) < 4 ? (0x02804 + ((1) * 0x100)) : (0x0C004 + ((1) * 0x40
))):
11940 reg = 0x0013C;
11941 break;
11942 case E1000_RDLEN(1)((1) < 4 ? (0x02808 + ((1) * 0x100)) : (0x0C008 + ((1) * 0x40
))):
11943 reg = 0x00140;
11944 break;
11945 case E1000_RDH(1)((1) < 4 ? (0x02810 + ((1) * 0x100)) : (0x0C010 + ((1) * 0x40
))):
11946 reg = 0x00148;
11947 break;
11948 case E1000_RDT(1)((1) < 4 ? (0x02818 + ((1) * 0x100)) : (0x0C018 + ((1) * 0x40
))):
11949 reg = 0x00150;
11950 break;
11951 case E1000_FCRTH0x02168:
11952 reg = 0x00160;
11953 break;
11954 case E1000_FCRTL0x02160:
11955 reg = 0x00168;
11956 break;
11957 case E1000_MTA0x05200:
11958 reg = 0x00200;
11959 break;
11960 case E1000_TDBAL(0)((0) < 4 ? (0x03800 + ((0) * 0x100)) : (0x0E000 + ((0) * 0x40
))):
11961 reg = 0x00420;
11962 break;
11963 case E1000_TDBAH(0)((0) < 4 ? (0x03804 + ((0) * 0x100)) : (0x0E004 + ((0) * 0x40
))):
11964 reg = 0x00424;
11965 break;
11966 case E1000_TDLEN(0)((0) < 4 ? (0x03808 + ((0) * 0x100)) : (0x0E008 + ((0) * 0x40
))):
11967 reg = 0x00428;
11968 break;
11969 case E1000_TDH(0)((0) < 4 ? (0x03810 + ((0) * 0x100)) : (0x0E010 + ((0) * 0x40
))):
11970 reg = 0x00430;
11971 break;
11972 case E1000_TDT(0)((0) < 4 ? (0x03818 + ((0) * 0x100)) : (0x0E018 + ((0) * 0x40
))):
11973 reg = 0x00438;
11974 break;
11975 case E1000_TIDV0x03820:
11976 reg = 0x00440;
11977 break;
11978 case E1000_VFTA0x05600:
11979 reg = 0x00600;
11980 break;
11981 case E1000_TDFH0x03410:
11982 reg = 0x08010;
11983 break;
11984 case E1000_TDFT0x03418:
11985 reg = 0x08018;
11986 break;
11987 default:
11988 break;
11989 }
11990
11991 return (reg);
11992}