Bug Summary

File:dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
Warning:line 439, column 31
Division by zero

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name dcn10_dpp_dscl.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dm_services.h"
27
28#include "core_types.h"
29
30#include "reg_helper.h"
31#include "dcn10_dpp.h"
32#include "basics/conversion.h"
33
34
35#define NUM_PHASES64 64
36#define HORZ_MAX_TAPS8 8
37#define VERT_MAX_TAPS8 8
38
39#define BLACK_OFFSET_RGB_Y0x0 0x0
40#define BLACK_OFFSET_CBCR0x8000 0x8000
41
42#define VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT3 3
43#define VISUAL_CONFIRM_RECT_HEIGHT_MIN1 1
44#define VISUAL_CONFIRM_RECT_HEIGHT_MAX10 10
45
46#define REG(reg)dpp->tf_regs->reg\
47 dpp->tf_regs->reg
48
49#define CTXdpp->base.ctx \
50 dpp->base.ctx
51
52#undef FN
53#define FN(reg_name, field_name)dpp->tf_shift->field_name, dpp->tf_mask->field_name \
54 dpp->tf_shift->field_name, dpp->tf_mask->field_name
55
56enum dcn10_coef_filter_type_sel {
57 SCL_COEF_LUMA_VERT_FILTER = 0,
58 SCL_COEF_LUMA_HORZ_FILTER = 1,
59 SCL_COEF_CHROMA_VERT_FILTER = 2,
60 SCL_COEF_CHROMA_HORZ_FILTER = 3,
61 SCL_COEF_ALPHA_VERT_FILTER = 4,
62 SCL_COEF_ALPHA_HORZ_FILTER = 5
63};
64
65enum dscl_autocal_mode {
66 AUTOCAL_MODE_OFF = 0,
67
68 /* Autocal calculate the scaling ratio and initial phase and the
69 * DSCL_MODE_SEL must be set to 1
70 */
71 AUTOCAL_MODE_AUTOSCALE = 1,
72 /* Autocal perform auto centering without replication and the
73 * DSCL_MODE_SEL must be set to 0
74 */
75 AUTOCAL_MODE_AUTOCENTER = 2,
76 /* Autocal perform auto centering and auto replication and the
77 * DSCL_MODE_SEL must be set to 0
78 */
79 AUTOCAL_MODE_AUTOREPLICATE = 3
80};
81
82enum dscl_mode_sel {
83 DSCL_MODE_SCALING_444_BYPASS = 0,
84 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
85 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
86 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
87 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
88 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
89 DSCL_MODE_DSCL_BYPASS = 6
90};
91
92static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth)
93{
94 if (depth == LB_PIXEL_DEPTH_30BPP)
95 return 0; /* 10 bpc */
96 else if (depth == LB_PIXEL_DEPTH_24BPP)
97 return 1; /* 8 bpc */
98 else if (depth == LB_PIXEL_DEPTH_18BPP)
99 return 2; /* 6 bpc */
100 else if (depth == LB_PIXEL_DEPTH_36BPP)
101 return 3; /* 12 bpc */
102 else {
103 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c"
, 103); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
104 return -1; /* Unsupported */
105 }
106}
107
108static bool_Bool dpp1_dscl_is_video_format(enum pixel_format format)
109{
110 if (format >= PIXEL_FORMAT_VIDEO_BEGIN
111 && format <= PIXEL_FORMAT_VIDEO_END)
112 return true1;
113 else
114 return false0;
115}
116
117static bool_Bool dpp1_dscl_is_420_format(enum pixel_format format)
118{
119 if (format == PIXEL_FORMAT_420BPP8 ||
120 format == PIXEL_FORMAT_420BPP10)
121 return true1;
122 else
123 return false0;
124}
125
126static enum dscl_mode_sel dpp1_dscl_get_dscl_mode(
127 struct dpp *dpp_base,
128 const struct scaler_data *data,
129 bool_Bool dbg_always_scale)
130{
131 const long long one = dc_fixpt_one.value;
132
133 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
134 /* DSCL is processing data in fixed format */
135 if (data->format == PIXEL_FORMAT_FP16)
136 return DSCL_MODE_DSCL_BYPASS;
137 }
138
139 if (data->ratios.horz.value == one
140 && data->ratios.vert.value == one
141 && data->ratios.horz_c.value == one
142 && data->ratios.vert_c.value == one
143 && !dbg_always_scale)
144 return DSCL_MODE_SCALING_444_BYPASS;
145
146 if (!dpp1_dscl_is_420_format(data->format)) {
147 if (dpp1_dscl_is_video_format(data->format))
148 return DSCL_MODE_SCALING_444_YCBCR_ENABLE;
149 else
150 return DSCL_MODE_SCALING_444_RGB_ENABLE;
151 }
152 if (data->ratios.horz.value == one && data->ratios.vert.value == one)
153 return DSCL_MODE_SCALING_420_LUMA_BYPASS;
154 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one)
155 return DSCL_MODE_SCALING_420_CHROMA_BYPASS;
156
157 return DSCL_MODE_SCALING_420_YCBCR_ENABLE;
158}
159
160static void dpp1_power_on_dscl(
161 struct dpp *dpp_base,
162 bool_Bool power_on)
163{
164 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base)({ const __typeof( ((struct dcn10_dpp *)0)->base ) *__mptr
= (dpp_base); (struct dcn10_dpp *)( (char *)__mptr - __builtin_offsetof
(struct dcn10_dpp, base) );});
165
166 if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {
167 if (power_on) {
168 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 0)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_MEM_PWR_CTRL
, 1, dpp->tf_shift->LUT_MEM_PWR_FORCE, dpp->tf_mask->
LUT_MEM_PWR_FORCE, 0);
169 REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5)generic_reg_wait(dpp->base.ctx, dpp->tf_regs->DSCL_MEM_PWR_STATUS
, dpp->tf_shift->LUT_MEM_PWR_STATE, dpp->tf_mask->
LUT_MEM_PWR_STATE, 0, 1, 5, __func__, 169);
170 } else {
171 if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) {
172 dpp->base.ctx->dc->optimized_required = true1;
173 dpp->base.deferred_reg_writes.bits.disable_dscl = true1;
174 } else {
175 REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, 3)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_MEM_PWR_CTRL
, 1, dpp->tf_shift->LUT_MEM_PWR_FORCE, dpp->tf_mask->
LUT_MEM_PWR_FORCE, 3);
176 }
177 }
178 }
179}
180
181
182static void dpp1_dscl_set_lb(
183 struct dcn10_dpp *dpp,
184 const struct line_buffer_params *lb_params,
185 enum lb_memory_config mem_size_config)
186{
187 uint32_t max_partitions = 63; /* Currently hardcoded on all ASICs before DCN 3.2 */
188
189 /* LB */
190 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) {
191 /* DSCL caps: pixel data processed in fixed format */
192 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth);
193 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth;
194
195 REG_SET_7(LB_DATA_FORMAT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
196 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
197 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
198 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
199 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
200 DITHER_EN, 0, /* Dithering enable: Disabled */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
201 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en)
202 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 7, dpp->tf_shift->PIXEL_DEPTH, dpp->tf_mask->
PIXEL_DEPTH, pixel_depth, dpp->tf_shift->PIXEL_EXPAN_MODE
, dpp->tf_mask->PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode
, dpp->tf_shift->PIXEL_REDUCE_MODE, dpp->tf_mask->
PIXEL_REDUCE_MODE, 1, dpp->tf_shift->DYNAMIC_PIXEL_DEPTH
, dpp->tf_mask->DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, dpp
->tf_shift->DITHER_EN, dpp->tf_mask->DITHER_EN, 0
, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->INTERLEAVE_EN
, lb_params->interleave_en, dpp->tf_shift->LB_DATA_FORMAT__ALPHA_EN
, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN, lb_params->
alpha_en); /* Alpha enable */
203 }
204 else {
205 /* DSCL caps: pixel data processed in float format */
206 REG_SET_2(LB_DATA_FORMAT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 2, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->
INTERLEAVE_EN, lb_params->interleave_en, dpp->tf_shift->
LB_DATA_FORMAT__ALPHA_EN, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN
, lb_params->alpha_en)
207 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 2, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->
INTERLEAVE_EN, lb_params->interleave_en, dpp->tf_shift->
LB_DATA_FORMAT__ALPHA_EN, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN
, lb_params->alpha_en)
208 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_DATA_FORMAT
, 0, 2, dpp->tf_shift->INTERLEAVE_EN, dpp->tf_mask->
INTERLEAVE_EN, lb_params->interleave_en, dpp->tf_shift->
LB_DATA_FORMAT__ALPHA_EN, dpp->tf_mask->LB_DATA_FORMAT__ALPHA_EN
, lb_params->alpha_en); /* Alpha enable */
209 }
210
211 if (dpp->base.caps->max_lb_partitions == 31)
212 max_partitions = 31;
213
214 REG_SET_2(LB_MEMORY_CTRL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_MEMORY_CTRL
, 0, 2, dpp->tf_shift->MEMORY_CONFIG, dpp->tf_mask->
MEMORY_CONFIG, mem_size_config, dpp->tf_shift->LB_MAX_PARTITIONS
, dpp->tf_mask->LB_MAX_PARTITIONS, max_partitions)
215 MEMORY_CONFIG, mem_size_config,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_MEMORY_CTRL
, 0, 2, dpp->tf_shift->MEMORY_CONFIG, dpp->tf_mask->
MEMORY_CONFIG, mem_size_config, dpp->tf_shift->LB_MAX_PARTITIONS
, dpp->tf_mask->LB_MAX_PARTITIONS, max_partitions)
216 LB_MAX_PARTITIONS, max_partitions)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->LB_MEMORY_CTRL
, 0, 2, dpp->tf_shift->MEMORY_CONFIG, dpp->tf_mask->
MEMORY_CONFIG, mem_size_config, dpp->tf_shift->LB_MAX_PARTITIONS
, dpp->tf_mask->LB_MAX_PARTITIONS, max_partitions);
217}
218
219static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio)
220{
221 if (taps == 8)
222 return get_filter_8tap_64p(ratio);
223 else if (taps == 7)
224 return get_filter_7tap_64p(ratio);
225 else if (taps == 6)
226 return get_filter_6tap_64p(ratio);
227 else if (taps == 5)
228 return get_filter_5tap_64p(ratio);
229 else if (taps == 4)
230 return get_filter_4tap_64p(ratio);
231 else if (taps == 3)
232 return get_filter_3tap_64p(ratio);
233 else if (taps == 2)
234 return get_filter_2tap_64p();
235 else if (taps == 1)
236 return NULL((void *)0);
237 else {
238 /* should never happen, bug */
239 BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 239); do {} while (0); } while (0);
240 return NULL((void *)0);
241 }
242}
243
244static void dpp1_dscl_set_scaler_filter(
245 struct dcn10_dpp *dpp,
246 uint32_t taps,
247 enum dcn10_coef_filter_type_sel filter_type,
248 const uint16_t *filter)
249{
250 const int tap_pairs = (taps + 1) / 2;
251 int phase;
252 int pair;
253 uint16_t odd_coef, even_coef;
254
255 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type)
256 SCL_COEF_RAM_TAP_PAIR_IDX, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type)
257 SCL_COEF_RAM_PHASE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type)
258 SCL_COEF_RAM_FILTER_TYPE, filter_type)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_SELECT
, 0, 3, dpp->tf_shift->SCL_COEF_RAM_TAP_PAIR_IDX, dpp->
tf_mask->SCL_COEF_RAM_TAP_PAIR_IDX, 0, dpp->tf_shift->
SCL_COEF_RAM_PHASE, dpp->tf_mask->SCL_COEF_RAM_PHASE, 0
, dpp->tf_shift->SCL_COEF_RAM_FILTER_TYPE, dpp->tf_mask
->SCL_COEF_RAM_FILTER_TYPE, filter_type);
259
260 for (phase = 0; phase < (NUM_PHASES64 / 2 + 1); phase++) {
261 for (pair = 0; pair < tap_pairs; pair++) {
262 even_coef = filter[phase * taps + 2 * pair];
263 if ((pair * 2 + 1) < taps)
264 odd_coef = filter[phase * taps + 2 * pair + 1];
265 else
266 odd_coef = 0;
267
268 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
269 /* Even tap coefficient (bits 1:0 fixed to 0) */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
270 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
271 /* Write/read control for even coefficient */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
272 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
273 /* Odd tap coefficient (bits 1:0 fixed to 0) */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
274 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
275 /* Write/read control for odd coefficient */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1)
276 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_COEF_RAM_TAP_DATA
, 0, 4, dpp->tf_shift->SCL_COEF_RAM_EVEN_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, dpp->tf_shift
->SCL_COEF_RAM_EVEN_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_EVEN_TAP_COEF_EN
, 1, dpp->tf_shift->SCL_COEF_RAM_ODD_TAP_COEF, dpp->
tf_mask->SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, dpp->tf_shift
->SCL_COEF_RAM_ODD_TAP_COEF_EN, dpp->tf_mask->SCL_COEF_RAM_ODD_TAP_COEF_EN
, 1);
277 }
278 }
279
280}
281
282static void dpp1_dscl_set_scl_filter(
283 struct dcn10_dpp *dpp,
284 const struct scaler_data *scl_data,
285 bool_Bool chroma_coef_mode)
286{
287 bool_Bool h_2tap_hardcode_coef_en = false0;
288 bool_Bool v_2tap_hardcode_coef_en = false0;
289 bool_Bool h_2tap_sharp_en = false0;
290 bool_Bool v_2tap_sharp_en = false0;
291 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz;
292 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert;
293 bool_Bool coef_ram_current;
294 const uint16_t *filter_h = NULL((void *)0);
295 const uint16_t *filter_v = NULL((void *)0);
296 const uint16_t *filter_h_c = NULL((void *)0);
297 const uint16_t *filter_v_c = NULL((void *)0);
298
299 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3
300 && scl_data->taps.h_taps_c < 3
301 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1);
302 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3
303 && scl_data->taps.v_taps_c < 3
304 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1);
305
306 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0;
307 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0;
308
309 REG_UPDATE_6(DSCL_2TAP_CONTROL,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
310 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
311 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
312 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
313 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
314 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en,generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
)
315 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->DSCL_2TAP_CONTROL
, 6, dpp->tf_shift->SCL_H_2TAP_HARDCODE_COEF_EN, dpp->
tf_mask->SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en
, dpp->tf_shift->SCL_H_2TAP_SHARP_EN, dpp->tf_mask->
SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, dpp->tf_shift->SCL_H_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor
, dpp->tf_shift->SCL_V_2TAP_HARDCODE_COEF_EN, dpp->tf_mask
->SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, dpp
->tf_shift->SCL_V_2TAP_SHARP_EN, dpp->tf_mask->SCL_V_2TAP_SHARP_EN
, v_2tap_sharp_en, dpp->tf_shift->SCL_V_2TAP_SHARP_FACTOR
, dpp->tf_mask->SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor
);
316
317 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) {
318 bool_Bool filter_updated = false0;
319
320 filter_h = dpp1_dscl_get_filter_coeffs_64p(
321 scl_data->taps.h_taps, scl_data->ratios.horz);
322 filter_v = dpp1_dscl_get_filter_coeffs_64p(
323 scl_data->taps.v_taps, scl_data->ratios.vert);
324
325 filter_updated = (filter_h && (filter_h != dpp->filter_h))
326 || (filter_v && (filter_v != dpp->filter_v));
327
328 if (chroma_coef_mode) {
329 filter_h_c = dpp1_dscl_get_filter_coeffs_64p(
330 scl_data->taps.h_taps_c, scl_data->ratios.horz_c);
331 filter_v_c = dpp1_dscl_get_filter_coeffs_64p(
332 scl_data->taps.v_taps_c, scl_data->ratios.vert_c);
333 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c))
334 || (filter_v_c && (filter_v_c != dpp->filter_v_c));
335 }
336
337 if (filter_updated) {
338 uint32_t scl_mode = REG_READ(SCL_MODE)dm_read_reg_func(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, __func__);
339
340 if (!h_2tap_hardcode_coef_en && filter_h) {
341 dpp1_dscl_set_scaler_filter(
342 dpp, scl_data->taps.h_taps,
343 SCL_COEF_LUMA_HORZ_FILTER, filter_h);
344 }
345 dpp->filter_h = filter_h;
346 if (!v_2tap_hardcode_coef_en && filter_v) {
347 dpp1_dscl_set_scaler_filter(
348 dpp, scl_data->taps.v_taps,
349 SCL_COEF_LUMA_VERT_FILTER, filter_v);
350 }
351 dpp->filter_v = filter_v;
352 if (chroma_coef_mode) {
353 if (!h_2tap_hardcode_coef_en && filter_h_c) {
354 dpp1_dscl_set_scaler_filter(
355 dpp, scl_data->taps.h_taps_c,
356 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c);
357 }
358 if (!v_2tap_hardcode_coef_en && filter_v_c) {
359 dpp1_dscl_set_scaler_filter(
360 dpp, scl_data->taps.v_taps_c,
361 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c);
362 }
363 }
364 dpp->filter_h_c = filter_h_c;
365 dpp->filter_v_c = filter_v_c;
366
367 coef_ram_current = get_reg_field_value_ex(
368 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT,
369 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT);
370
371 /* Swap coefficient RAM and set chroma coefficient mode */
372 REG_SET_2(SCL_MODE, scl_mode,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, scl_mode, 2, dpp->tf_shift->SCL_COEF_RAM_SELECT, dpp->
tf_mask->SCL_COEF_RAM_SELECT, !coef_ram_current, dpp->tf_shift
->SCL_CHROMA_COEF_MODE, dpp->tf_mask->SCL_CHROMA_COEF_MODE
, chroma_coef_mode)
373 SCL_COEF_RAM_SELECT, !coef_ram_current,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, scl_mode, 2, dpp->tf_shift->SCL_COEF_RAM_SELECT, dpp->
tf_mask->SCL_COEF_RAM_SELECT, !coef_ram_current, dpp->tf_shift
->SCL_CHROMA_COEF_MODE, dpp->tf_mask->SCL_CHROMA_COEF_MODE
, chroma_coef_mode)
374 SCL_CHROMA_COEF_MODE, chroma_coef_mode)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, scl_mode, 2, dpp->tf_shift->SCL_COEF_RAM_SELECT, dpp->
tf_mask->SCL_COEF_RAM_SELECT, !coef_ram_current, dpp->tf_shift
->SCL_CHROMA_COEF_MODE, dpp->tf_mask->SCL_CHROMA_COEF_MODE
, chroma_coef_mode);
375 }
376 }
377}
378
379static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth)
380{
381 if (depth == LB_PIXEL_DEPTH_30BPP)
382 return 10;
383 else if (depth == LB_PIXEL_DEPTH_24BPP)
384 return 8;
385 else if (depth == LB_PIXEL_DEPTH_18BPP)
386 return 6;
387 else if (depth == LB_PIXEL_DEPTH_36BPP)
388 return 12;
389 else {
390 BREAK_TO_DEBUGGER()do { ___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__
, 390); do {} while (0); } while (0);
391 return -1; /* Unsupported */
392 }
393}
394
395void dpp1_dscl_calc_lb_num_partitions(
396 const struct scaler_data *scl_data,
397 enum lb_memory_config lb_config,
398 int *num_part_y,
399 int *num_part_c)
400{
401 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a,
402 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a;
403
404 int line_size = scl_data->viewport.width < scl_data->recout.width ?
1
Assuming 'scl_data->viewport.width' is >= 'scl_data->recout.width'
→
2
←
'?' condition is false
→
405 scl_data->viewport.width : scl_data->recout.width;
406 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
3
←
Assuming 'scl_data->viewport_c.width' is < 'scl_data->recout.width'
→
4
←
'?' condition is true
→
407 scl_data->viewport_c.width : scl_data->recout.width;
408
409 if (line_size == 0)
5
←
Assuming 'line_size' is equal to 0
→
6
←
Taking true branch
→
410 line_size = 1;
411
412 if (line_size_c
6.1
'line_size_c' is not equal to 0
 == 0)
7
←
Taking false branch
→
413 line_size_c = 1;
414
415
416 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth);
417 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */
8
←
The value 0 is assigned to 'memory_line_size_y'
→
418 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */
419 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
420
421 if (lb_config == LB_MEMORY_CONFIG_1) {
9
←
Assuming 'lb_config' is equal to LB_MEMORY_CONFIG_1
→
10
←
Taking true branch
→
422 lb_memory_size = 816;
423 lb_memory_size_c = 816;
424 lb_memory_size_a = 984;
425 } else if (lb_config == LB_MEMORY_CONFIG_2) {
426 lb_memory_size = 1088;
427 lb_memory_size_c = 1088;
428 lb_memory_size_a = 1312;
429 } else if (lb_config == LB_MEMORY_CONFIG_3) {
430 /* 420 mode: using 3rd mem from Y, Cr and Cb */
431 lb_memory_size = 816 + 1088 + 848 + 848 + 848;
432 lb_memory_size_c = 816 + 1088;
433 lb_memory_size_a = 984 + 1312 + 456;
434 } else {
435 lb_memory_size = 816 + 1088 + 848;
436 lb_memory_size_c = 816 + 1088 + 848;
437 lb_memory_size_a = 984 + 1312 + 456;
438 }
439 *num_part_y = lb_memory_size / memory_line_size_y;
11
←
Division by zero
440 *num_part_c = lb_memory_size_c / memory_line_size_c;
441 num_partitions_a = lb_memory_size_a / memory_line_size_a;
442
443 if (scl_data->lb_params.alpha_en
444 && (num_partitions_a < *num_part_y))
445 *num_part_y = num_partitions_a;
446
447 if (*num_part_y > 64)
448 *num_part_y = 64;
449 if (*num_part_c > 64)
450 *num_part_c = 64;
451
452}
453
454bool_Bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps)
455{
456 if (ceil_vratio > 2)
457 return vtaps <= (num_partitions - ceil_vratio + 2);
458 else
459 return vtaps <= num_partitions;
460}
461
462/*find first match configuration which meets the min required lb size*/
463static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp,
464 const struct scaler_data *scl_data)
465{
466 int num_part_y, num_part_c;
467 int vtaps = scl_data->taps.v_taps;
468 int vtaps_c = scl_data->taps.v_taps_c;
469 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert);
470 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c);
471
472 if (dpp->base.ctx->dc->debug.use_max_lb) {
473 if (scl_data->format == PIXEL_FORMAT_420BPP8
474 || scl_data->format == PIXEL_FORMAT_420BPP10)
475 return LB_MEMORY_CONFIG_3;
476 return LB_MEMORY_CONFIG_0;
477 }
478
479 dpp->base.caps->dscl_calc_lb_num_partitions(
480 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c);
481
482 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
483 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
484 return LB_MEMORY_CONFIG_1;
485
486 dpp->base.caps->dscl_calc_lb_num_partitions(
487 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c);
488
489 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
490 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
491 return LB_MEMORY_CONFIG_2;
492
493 if (scl_data->format == PIXEL_FORMAT_420BPP8
494 || scl_data->format == PIXEL_FORMAT_420BPP10) {
495 dpp->base.caps->dscl_calc_lb_num_partitions(
496 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c);
497
498 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)
499 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))
500 return LB_MEMORY_CONFIG_3;
501 }
502
503 dpp->base.caps->dscl_calc_lb_num_partitions(
504 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c);
505
506 /*Ensure we can support the requested number of vtaps*/
507 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps)do { if (({ static int __warned; int __ret = !!(!(dpp1_dscl_is_lb_conf_valid
(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid
(ceil_vratio_c, num_part_c, vtaps_c))); if (__ret && !
__warned) { printf("WARNING %s failed at %s:%d\n", "!(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c"
, 508); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0)
508 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))do { if (({ static int __warned; int __ret = !!(!(dpp1_dscl_is_lb_conf_valid
(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid
(ceil_vratio_c, num_part_c, vtaps_c))); if (__ret && !
__warned) { printf("WARNING %s failed at %s:%d\n", "!(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c))"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c"
, 508); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
509
510 return LB_MEMORY_CONFIG_0;
511}
512
513
514static void dpp1_dscl_set_manual_ratio_init(
515 struct dcn10_dpp *dpp, const struct scaler_data *data)
516{
517 uint32_t init_frac = 0;
518 uint32_t init_int = 0;
519
520 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO, dpp->tf_mask
->SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) <<
5)
521 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO, dpp->tf_mask
->SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) <<
5);
522
523 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO, dpp->tf_mask
->SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) <<
5)
524 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO, dpp->tf_mask
->SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) <<
5);
525
526 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO_C, dpp->tf_mask
->SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c
) << 5)
527 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_H_SCALE_RATIO_C, dpp->tf_mask
->SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c
) << 5);
528
529 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO_C, dpp->tf_mask
->SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c
) << 5)
530 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_SCALE_RATIO_C
, 0, 1, dpp->tf_shift->SCL_V_SCALE_RATIO_C, dpp->tf_mask
->SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c
) << 5);
531
532 /*
533 * 0.24 format for fraction, first five bits zeroed
534 */
535 init_frac = dc_fixpt_u0d19(data->inits.h) << 5;
536 init_int = dc_fixpt_floor(data->inits.h);
537 REG_SET_2(SCL_HORZ_FILTER_INIT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC, dpp->tf_mask
->SCL_H_INIT_FRAC, init_frac, dpp->tf_shift->SCL_H_INIT_INT
, dpp->tf_mask->SCL_H_INIT_INT, init_int)
538 SCL_H_INIT_FRAC, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC, dpp->tf_mask
->SCL_H_INIT_FRAC, init_frac, dpp->tf_shift->SCL_H_INIT_INT
, dpp->tf_mask->SCL_H_INIT_INT, init_int)
539 SCL_H_INIT_INT, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC, dpp->tf_mask
->SCL_H_INIT_FRAC, init_frac, dpp->tf_shift->SCL_H_INIT_INT
, dpp->tf_mask->SCL_H_INIT_INT, init_int);
540
541 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5;
542 init_int = dc_fixpt_floor(data->inits.h_c);
543 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC_C, dpp->tf_mask
->SCL_H_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_H_INIT_INT_C
, dpp->tf_mask->SCL_H_INIT_INT_C, init_int)
544 SCL_H_INIT_FRAC_C, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC_C, dpp->tf_mask
->SCL_H_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_H_INIT_INT_C
, dpp->tf_mask->SCL_H_INIT_INT_C, init_int)
545 SCL_H_INIT_INT_C, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_HORZ_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_H_INIT_FRAC_C, dpp->tf_mask
->SCL_H_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_H_INIT_INT_C
, dpp->tf_mask->SCL_H_INIT_INT_C, init_int);
546
547 init_frac = dc_fixpt_u0d19(data->inits.v) << 5;
548 init_int = dc_fixpt_floor(data->inits.v);
549 REG_SET_2(SCL_VERT_FILTER_INIT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC, dpp->tf_mask
->SCL_V_INIT_FRAC, init_frac, dpp->tf_shift->SCL_V_INIT_INT
, dpp->tf_mask->SCL_V_INIT_INT, init_int)
550 SCL_V_INIT_FRAC, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC, dpp->tf_mask
->SCL_V_INIT_FRAC, init_frac, dpp->tf_shift->SCL_V_INIT_INT
, dpp->tf_mask->SCL_V_INIT_INT, init_int)
551 SCL_V_INIT_INT, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC, dpp->tf_mask
->SCL_V_INIT_FRAC, init_frac, dpp->tf_shift->SCL_V_INIT_INT
, dpp->tf_mask->SCL_V_INIT_INT, init_int);
552
553 if (REG(SCL_VERT_FILTER_INIT_BOT)dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT) {
554 struct fixed31_32 bot = dc_fixpt_add(data->inits.v, data->ratios.vert);
555
556 init_frac = dc_fixpt_u0d19(bot) << 5;
557 init_int = dc_fixpt_floor(bot);
558 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT
, dpp->tf_mask->SCL_V_INIT_INT_BOT, init_int)
559 SCL_V_INIT_FRAC_BOT, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT
, dpp->tf_mask->SCL_V_INIT_INT_BOT, init_int)
560 SCL_V_INIT_INT_BOT, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT
, dpp->tf_mask->SCL_V_INIT_INT_BOT, init_int);
561 }
562
563 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5;
564 init_int = dc_fixpt_floor(data->inits.v_c);
565 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_C, dpp->tf_mask
->SCL_V_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_C
, dpp->tf_mask->SCL_V_INIT_INT_C, init_int)
566 SCL_V_INIT_FRAC_C, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_C, dpp->tf_mask
->SCL_V_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_C
, dpp->tf_mask->SCL_V_INIT_INT_C, init_int)
567 SCL_V_INIT_INT_C, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_C, dpp->tf_mask
->SCL_V_INIT_FRAC_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_C
, dpp->tf_mask->SCL_V_INIT_INT_C, init_int);
568
569 if (REG(SCL_VERT_FILTER_INIT_BOT_C)dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C) {
570 struct fixed31_32 bot = dc_fixpt_add(data->inits.v_c, data->ratios.vert_c);
571
572 init_frac = dc_fixpt_u0d19(bot) << 5;
573 init_int = dc_fixpt_floor(bot);
574 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT_C, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT_C
, dpp->tf_mask->SCL_V_INIT_INT_BOT_C, init_int)
575 SCL_V_INIT_FRAC_BOT_C, init_frac,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT_C, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT_C
, dpp->tf_mask->SCL_V_INIT_INT_BOT_C, init_int)
576 SCL_V_INIT_INT_BOT_C, init_int)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_VERT_FILTER_INIT_BOT_C
, 0, 2, dpp->tf_shift->SCL_V_INIT_FRAC_BOT_C, dpp->tf_mask
->SCL_V_INIT_FRAC_BOT_C, init_frac, dpp->tf_shift->SCL_V_INIT_INT_BOT_C
, dpp->tf_mask->SCL_V_INIT_INT_BOT_C, init_int);
577 }
578}
579
580/**
581 * dpp1_dscl_set_recout - Set the first pixel of RECOUT in the OTG active area
582 *
583 * @dpp: DPP data struct
584 * @recount: Rectangle information
585 *
586 * This function sets the MPC RECOUT_START and RECOUT_SIZE registers based on
587 * the values specified in the recount parameter.
588 *
589 * Note: This function only have effect if AutoCal is disabled.
590 */
591static void dpp1_dscl_set_recout(struct dcn10_dpp *dpp,
592 const struct rect *recout)
593{
594 int visual_confirm_on = 0;
595 unsigned short visual_confirm_rect_height = VISUAL_CONFIRM_RECT_HEIGHT_DEFAULT3;
596
597 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE)
598 visual_confirm_on = 1;
599
600 /* Check bounds to ensure the VC bar height was set to a sane value */
601 if ((dpp->base.ctx->dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_RECT_HEIGHT_MIN1) &&
602 (dpp->base.ctx->dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_RECT_HEIGHT_MAX10)) {
603 visual_confirm_rect_height = dpp->base.ctx->dc->debug.visual_confirm_rect_height;
604 }
605
606 REG_SET_2(RECOUT_START, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
607 /* First pixel of RECOUT in the active OTG area */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
608 RECOUT_START_X, recout->x,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
609 /* First line of RECOUT in the active OTG area */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y)
610 RECOUT_START_Y, recout->y)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_START
, 0, 2, dpp->tf_shift->RECOUT_START_X, dpp->tf_mask->
RECOUT_START_X, recout->x, dpp->tf_shift->RECOUT_START_Y
, dpp->tf_mask->RECOUT_START_Y, recout->y);
611
612 REG_SET_2(RECOUT_SIZE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 2 * (dpp->base.inst + visual_confirm_rect_height))
613 /* Number of RECOUT horizontal pixels */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 2 * (dpp->base.inst + visual_confirm_rect_height))
614 RECOUT_WIDTH, recout->width,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 2 * (dpp->base.inst + visual_confirm_rect_height))
615 /* Number of RECOUT vertical lines */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 2 * (dpp->base.inst + visual_confirm_rect_height))
616 RECOUT_HEIGHT, recout->heightgeneric_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 2 * (dpp->base.inst + visual_confirm_rect_height))
617 - visual_confirm_on * 2 * (dpp->base.inst + visual_confirm_rect_height))generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->RECOUT_SIZE
, 0, 2, dpp->tf_shift->RECOUT_WIDTH, dpp->tf_mask->
RECOUT_WIDTH, recout->width, dpp->tf_shift->RECOUT_HEIGHT
, dpp->tf_mask->RECOUT_HEIGHT, recout->height - visual_confirm_on
* 2 * (dpp->base.inst + visual_confirm_rect_height));
618}
619
620/**
621 * dpp1_dscl_set_scaler_manual_scale - Manually program scaler and line buffer
622 *
623 * @dpp_base: High level DPP struct
624 * @scl_data: scalaer_data info
625 *
626 * This is the primary function to program scaler and line buffer in manual
627 * scaling mode. To execute the required operations for manual scale, we need
628 * to disable AutoCal first.
629 */
630void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base,
631 const struct scaler_data *scl_data)
632{
633 enum lb_memory_config lb_config;
634 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base)({ const __typeof( ((struct dcn10_dpp *)0)->base ) *__mptr
= (dpp_base); (struct dcn10_dpp *)( (char *)__mptr - __builtin_offsetof
(struct dcn10_dpp, base) );});
635 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode(
636 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale);
637 bool_Bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN
638 && scl_data->format <= PIXEL_FORMAT_VIDEO_END;
639
640 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data))__builtin_memcmp((&dpp->scl_data), (scl_data), (sizeof
(*scl_data))) == 0)
641 return;
642
643 PERF_TRACE()dm_perf_trace_timestamp(__func__, 643, dpp->base.ctx);
644
645 dpp->scl_data = *scl_data;
646
647 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {
648 if (dscl_mode != DSCL_MODE_DSCL_BYPASS)
649 dpp1_power_on_dscl(dpp_base, true1);
650 }
651
652 /* Autocal off */
653 REG_SET_3(DSCL_AUTOCAL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
654 AUTOCAL_MODE, AUTOCAL_MODE_OFF,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
655 AUTOCAL_NUM_PIPE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0)
656 AUTOCAL_PIPE_ID, 0)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->DSCL_AUTOCAL
, 0, 3, dpp->tf_shift->AUTOCAL_MODE, dpp->tf_mask->
AUTOCAL_MODE, AUTOCAL_MODE_OFF, dpp->tf_shift->AUTOCAL_NUM_PIPE
, dpp->tf_mask->AUTOCAL_NUM_PIPE, 0, dpp->tf_shift->
AUTOCAL_PIPE_ID, dpp->tf_mask->AUTOCAL_PIPE_ID, 0);
657
658 /* Recout */
659 dpp1_dscl_set_recout(dpp, &scl_data->recout);
660
661 /* MPC Size */
662 REG_SET_2(MPC_SIZE, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
663 /* Number of horizontal pixels of MPC */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
664 MPC_WIDTH, scl_data->h_active,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
665 /* Number of vertical lines of MPC */generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active)
666 MPC_HEIGHT, scl_data->v_active)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->MPC_SIZE
, 0, 2, dpp->tf_shift->MPC_WIDTH, dpp->tf_mask->MPC_WIDTH
, scl_data->h_active, dpp->tf_shift->MPC_HEIGHT, dpp
->tf_mask->MPC_HEIGHT, scl_data->v_active);
667
668 /* SCL mode */
669 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode)generic_reg_update_ex(dpp->base.ctx, dpp->tf_regs->SCL_MODE
, 1, dpp->tf_shift->DSCL_MODE, dpp->tf_mask->DSCL_MODE
, dscl_mode);
670
671 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) {
672 if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)
673 dpp1_power_on_dscl(dpp_base, false0);
674 return;
675 }
676
677 /* LB */
678 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data);
679 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config);
680
681 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS)
682 return;
683
684 /* Black offsets */
685 if (REG(SCL_BLACK_OFFSET)dpp->tf_regs->SCL_BLACK_OFFSET) {
686 if (ycbcr)
687 REG_SET_2(SCL_BLACK_OFFSET, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000)
688 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000)
689 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x8000);
690 else
691
692 REG_SET_2(SCL_BLACK_OFFSET, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0)
693 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0)
694 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_BLACK_OFFSET
, 0, 2, dpp->tf_shift->SCL_BLACK_OFFSET_RGB_Y, dpp->
tf_mask->SCL_BLACK_OFFSET_RGB_Y, 0x0, dpp->tf_shift->
SCL_BLACK_OFFSET_CBCR, dpp->tf_mask->SCL_BLACK_OFFSET_CBCR
, 0x0);
695 }
696
697 /* Manually calculate scale ratio and init values */
698 dpp1_dscl_set_manual_ratio_init(dpp, scl_data);
699
700 /* HTaps/VTaps */
701 REG_SET_4(SCL_TAP_CONTROL, 0,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
702 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
703 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
704 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1,generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)
705 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1)generic_reg_set_ex(dpp->base.ctx, dpp->tf_regs->SCL_TAP_CONTROL
, 0, 4, dpp->tf_shift->SCL_V_NUM_TAPS, dpp->tf_mask->
SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, dpp->tf_shift
->SCL_H_NUM_TAPS, dpp->tf_mask->SCL_H_NUM_TAPS, scl_data
->taps.h_taps - 1, dpp->tf_shift->SCL_V_NUM_TAPS_C, dpp
->tf_mask->SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c
- 1, dpp->tf_shift->SCL_H_NUM_TAPS_C, dpp->tf_mask->
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
706
707 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
708 PERF_TRACE()dm_perf_trace_timestamp(__func__, 708, dpp->base.ctx);
709}