Bug Summary

File:dev/pci/if_aq_pci.c
Warning:line 2023, column 2
Value stored to 'efuse_shadow_addr' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name if_aq_pci.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/if_aq_pci.c
1/* $OpenBSD: if_aq_pci.c,v 1.26 2023/11/10 15:51:20 bluhm Exp $ */
2/* $NetBSD: if_aq.c,v 1.27 2021/06/16 00:21:18 riastradh Exp $ */
3
4/*
5 * Copyright (c) 2021 Jonathan Matthew <jonathan@d14n.org>
6 * Copyright (c) 2021 Mike Larkin <mlarkin@openbsd.org>
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/**
22 * aQuantia Corporation Network Driver
23 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
27 * are met:
28 *
29 * (1) Redistributions of source code must retain the above
30 * copyright notice, this list of conditions and the following
31 * disclaimer.
32 *
33 * (2) Redistributions in binary form must reproduce the above
34 * copyright notice, this list of conditions and the following
35 * disclaimer in the documentation and/or other materials provided
36 * with the distribution.
37 *
38 * (3) The name of the author may not be used to endorse or promote
39 * products derived from this software without specific prior
40 * written permission.
41 *
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
43 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
44 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
46 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
48 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
50 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
51 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
52 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53 *
54 */
55
56/*-
57 * Copyright (c) 2020 Ryo Shimizu <ryo@nerv.org>
58 * All rights reserved.
59 *
60 * Redistribution and use in source and binary forms, with or without
61 * modification, are permitted provided that the following conditions
62 * are met:
63 * 1. Redistributions of source code must retain the above copyright
64 * notice, this list of conditions and the following disclaimer.
65 * 2. Redistributions in binary form must reproduce the above copyright
66 * notice, this list of conditions and the following disclaimer in the
67 * documentation and/or other materials provided with the distribution.
68 *
69 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
70 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
71 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
72 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
73 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
74 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
75 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
76 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
77 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
78 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
79 * POSSIBILITY OF SUCH DAMAGE.
80 */
81#include "bpfilter.h"
82#include "vlan.h"
83
84#include <sys/types.h>
85#include <sys/device.h>
86#include <sys/param.h>
87#include <sys/kernel.h>
88#include <sys/sockio.h>
89#include <sys/systm.h>
90#include <sys/intrmap.h>
91
92#include <net/if.h>
93#include <net/if_media.h>
94#include <net/toeplitz.h>
95
96#include <netinet/in.h>
97#include <netinet/if_ether.h>
98
99#ifdef __HAVE_FDT
100#include <dev/ofw/openfirm.h>
101#endif
102
103#include <dev/pci/pcireg.h>
104#include <dev/pci/pcivar.h>
105#include <dev/pci/pcidevs.h>
106
107#if NBPFILTER1 > 0
108#include <net/bpf.h>
109#endif
110
111/* #define AQ_DEBUG 1 */
112#ifdef AQ_DEBUG
113#define DPRINTF(x) printf x
114#else
115#define DPRINTF(x)
116#endif /* AQ_DEBUG */
117
118#define DEVNAME(_s)((_s)->sc_dev.dv_xname) ((_s)->sc_dev.dv_xname)
119
120#define AQ_BAR00x10 0x10
121#define AQ_MAXQ8 8
122#define AQ_RSS_KEYSIZE40 40
123#define AQ_RSS_REDIR_ENTRIES12 12
124
125#define AQ_TXD_NUM2048 2048
126#define AQ_RXD_NUM2048 2048
127
128#define AQ_TX_MAX_SEGMENTS32 32
129
130#define AQ_LINKSTAT_IRQ31 31
131
132#define RPF_ACTION_HOST1 1
133
134#define AQ_FW_SOFTRESET_REG0x0000 0x0000
135#define AQ_FW_SOFTRESET_DIS(1 << 14) (1 << 14)
136#define AQ_FW_SOFTRESET_RESET(1 << 15) (1 << 15)
137#define AQ_FW_VERSION_REG0x0018 0x0018
138#define AQ_HW_REVISION_REG0x001c 0x001c
139#define AQ2_HW_FPGA_VERSION_REG0x00f4 0x00f4
140#define AQ_GLB_NVR_INTERFACE1_REG0x0100 0x0100
141#define AQ_FW_MBOX_CMD_REG0x0200 0x0200
142#define AQ_FW_MBOX_CMD_EXECUTE0x00008000 0x00008000
143#define AQ_FW_MBOX_CMD_BUSY0x00000100 0x00000100
144#define AQ_FW_MBOX_ADDR_REG0x0208 0x0208
145#define AQ_FW_MBOX_VAL_REG0x020C 0x020C
146#define AQ_FW_GLB_CPU_SEM_REG(i)(0x03a0 + (i) * 4) (0x03a0 + (i) * 4)
147#define AQ_FW_SEM_RAM_REG(0x03a0 + (2) * 4) AQ_FW_GLB_CPU_SEM_REG(2)(0x03a0 + (2) * 4)
148#define AQ2_ART_SEM_REG(0x03a0 + (3) * 4) AQ_FW_GLB_CPU_SEM_REG(3)(0x03a0 + (3) * 4)
149#define AQ_FW_GLB_CTL2_REG0x0404 0x0404
150#define AQ_GLB_GENERAL_PROVISIONING9_REG0x0520 0x0520
151#define AQ_GLB_NVR_PROVISIONING2_REG0x0534 0x0534
152#define AQ_INTR_STATUS_REG0x2000 0x2000 /* intr status */
153#define AQ_INTR_STATUS_CLR_REG0x2050 0x2050 /* intr status clear */
154#define AQ_INTR_MASK_REG0x2060 0x2060 /* intr mask set */
155#define AQ_INTR_MASK_CLR_REG0x2070 0x2070 /* intr mask clear */
156#define AQ_INTR_AUTOMASK_REG0x2090 0x2090
157
158/* AQ_INTR_IRQ_MAP_TXRX_REG 0x2100-0x2140 */
159#define AQ_INTR_IRQ_MAP_TXRX_REG(i)(0x2100 + ((i) / 2) * 4) (0x2100 + ((i) / 2) * 4)
160#define AQ_INTR_IRQ_MAP_TX_REG(i)(0x2100 + ((i) / 2) * 4) AQ_INTR_IRQ_MAP_TXRX_REG(i)(0x2100 + ((i) / 2) * 4)
161#define AQ_INTR_IRQ_MAP_TX_IRQMAP(i)(0x1FU << (((i) & 1) ? 16 : 24)) (0x1FU << (((i) & 1) ? 16 : 24))
162#define AQ_INTR_IRQ_MAP_TX_EN(i)(1U << (((i) & 1) ? 23 : 31)) (1U << (((i) & 1) ? 23 : 31))
163#define AQ_INTR_IRQ_MAP_RX_REG(i)(0x2100 + ((i) / 2) * 4) AQ_INTR_IRQ_MAP_TXRX_REG(i)(0x2100 + ((i) / 2) * 4)
164#define AQ_INTR_IRQ_MAP_RX_IRQMAP(i)(0x1FU << (((i) & 1) ? 0 : 8)) (0x1FU << (((i) & 1) ? 0 : 8))
165#define AQ_INTR_IRQ_MAP_RX_EN(i)(1U << (((i) & 1) ? 7 : 15)) (1U << (((i) & 1) ? 7 : 15))
166
167/* AQ_GEN_INTR_MAP_REG[AQ_RINGS_NUM] 0x2180-0x2200 */
168#define AQ_GEN_INTR_MAP_REG(i)(0x2180 + (i) * 4) (0x2180 + (i) * 4)
169#define AQ_B0_ERR_INT8U 8U
170
171#define AQ_INTR_CTRL_REG0x2300 0x2300
172#define AQ_INTR_CTRL_IRQMODE((1 << 0) | (1 << 1)) ((1 << 0) | (1 << 1))
173#define AQ_INTR_CTRL_IRQMODE_LEGACY0 0
174#define AQ_INTR_CTRL_IRQMODE_MSI1 1
175#define AQ_INTR_CTRL_IRQMODE_MSIX2 2
176#define AQ_INTR_CTRL_MULTIVEC(1 << 2) (1 << 2)
177#define AQ_INTR_CTRL_RESET_DIS(1 << 29) (1 << 29)
178#define AQ_INTR_CTRL_RESET_IRQ(1U << 31) (1U << 31)
179#define AQ_MBOXIF_POWER_GATING_CONTROL_REG0x32a8 0x32a8
180
181#define FW_MPI_MBOX_ADDR_REG0x0360 0x0360
182#define FW1X_MPI_INIT1_REG0x0364 0x0364
183#define FW1X_MPI_INIT2_REG0x0370 0x0370
184#define FW1X_MPI_EFUSEADDR_REG0x0374 0x0374
185
186#define FW2X_MPI_EFUSEADDR_REG0x0364 0x0364
187#define FW2X_MPI_CONTROL_REG0x0368 0x0368 /* 64bit */
188#define FW2X_MPI_STATE_REG0x0370 0x0370 /* 64bit */
189#define FW_BOOT_EXIT_CODE_REG0x0388 0x0388
190
191#define FW_BOOT_EXIT_CODE_REG0x0388 0x0388
192#define RBL_STATUS_DEAD0x0000dead 0x0000dead
193#define RBL_STATUS_SUCCESS0x0000abba 0x0000abba
194#define RBL_STATUS_FAILURE0x00000bad 0x00000bad
195#define RBL_STATUS_HOST_BOOT0x0000f1a7 0x0000f1a7
196#define FW_MPI_DAISY_CHAIN_STATUS_REG0x0704 0x0704
197#define AQ_PCI_REG_CONTROL_6_REG0x1014 0x1014
198
199#define FW_MPI_RESETCTRL_REG0x4000 0x4000
200#define FW_MPI_RESETCTRL_RESET_DIS(1 << 29) (1 << 29)
201
202#define RX_SYSCONTROL_REG0x5000 0x5000
203#define RX_SYSCONTROL_RESET_DIS(1 << 29) (1 << 29)
204
205#define RX_TCP_RSS_HASH_REG0x5040 0x5040
206#define RX_TCP_RSS_HASH_RPF2(0xf << 16) (0xf << 16)
207#define RX_TCP_RSS_HASH_TYPE(0xffff) (0xffff)
208
209#define RPF_L2BC_REG0x5100 0x5100
210#define RPF_L2BC_EN(1 << 0) (1 << 0)
211#define RPF_L2BC_PROMISC(1 << 3) (1 << 3)
212#define RPF_L2BC_ACTION0x7000 0x7000
213#define RPF_L2BC_THRESHOLD0xFFFF0000 0xFFFF0000
214
215#define AQ_HW_MAC_OWN0 0
216
217/* RPF_L2UC_*_REG[34] (actual [38]?) */
218#define RPF_L2UC_LSW_REG(i)(0x5110 + (i) * 8) (0x5110 + (i) * 8)
219#define RPF_L2UC_MSW_REG(i)(0x5114 + (i) * 8) (0x5114 + (i) * 8)
220#define RPF_L2UC_MSW_MACADDR_HI0xFFFF 0xFFFF
221#define RPF_L2UC_MSW_ACTION0x70000 0x70000
222#define RPF_L2UC_MSW_TAG0x03c00000 0x03c00000
223#define RPF_L2UC_MSW_EN(1U << 31) (1U << 31)
224#define AQ_HW_MAC_NUM34 34
225
226/* RPF_MCAST_FILTER_REG[8] 0x5250-0x5270 */
227#define RPF_MCAST_FILTER_REG(i)(0x5250 + (i) * 4) (0x5250 + (i) * 4)
228#define RPF_MCAST_FILTER_EN(1U << 31) (1U << 31)
229#define RPF_MCAST_FILTER_MASK_REG0x5270 0x5270
230#define RPF_MCAST_FILTER_MASK_ALLMULTI(1 << 14) (1 << 14)
231
232#define RPF_VLAN_MODE_REG0x5280 0x5280
233#define RPF_VLAN_MODE_PROMISC(1 << 1) (1 << 1)
234#define RPF_VLAN_MODE_ACCEPT_UNTAGGED(1 << 2) (1 << 2)
235#define RPF_VLAN_MODE_UNTAGGED_ACTION0x38 0x38
236
237#define RPF_VLAN_TPID_REG0x5284 0x5284
238#define RPF_VLAN_TPID_OUTER0xFFFF0000 0xFFFF0000
239#define RPF_VLAN_TPID_INNER0xFFFF 0xFFFF
240
241/* RPF_ETHERTYPE_FILTER_REG[AQ_RINGS_NUM] 0x5300-0x5380 */
242#define RPF_ETHERTYPE_FILTER_REG(i)(0x5300 + (i) * 4) (0x5300 + (i) * 4)
243#define RPF_ETHERTYPE_FILTER_EN(1U << 31) (1U << 31)
244
245/* RPF_L3_FILTER_REG[8] 0x5380-0x53a0 */
246#define RPF_L3_FILTER_REG(i)(0x5380 + (i) * 4) (0x5380 + (i) * 4)
247#define RPF_L3_FILTER_L4_EN(1U << 31) (1U << 31)
248
249#define RX_FLR_RSS_CONTROL1_REG0x54c0 0x54c0
250#define RX_FLR_RSS_CONTROL1_EN(1U << 31) (1U << 31)
251
252#define RPF_RPB_RX_TC_UPT_REG0x54c4 0x54c4
253#define RPF_RPB_RX_TC_UPT_MASK(i)(0x00000007 << ((i) * 4)) (0x00000007 << ((i) * 4))
254
255#define RPF_RSS_KEY_ADDR_REG0x54d0 0x54d0
256#define RPF_RSS_KEY_ADDR0x1f 0x1f
257#define RPF_RSS_KEY_WR_EN(1 << 5) (1 << 5)
258#define RPF_RSS_KEY_WR_DATA_REG0x54d4 0x54d4
259#define RPF_RSS_KEY_RD_DATA_REG0x54d8 0x54d8
260
261#define RPF_RSS_REDIR_ADDR_REG0x54e0 0x54e0
262#define RPF_RSS_REDIR_ADDR0xf 0xf
263#define RPF_RSS_REDIR_WR_EN(1 << 4) (1 << 4)
264
265#define RPF_RSS_REDIR_WR_DATA_REG0x54e4 0x54e4
266
267
268#define RPO_HWCSUM_REG0x5580 0x5580
269#define RPO_HWCSUM_L4CSUM_EN(1 << 0) (1 << 0)
270#define RPO_HWCSUM_IP4CSUM_EN(1 << 1) (1 << 1)
271
272#define RPB_RPF_RX_REG0x5700 0x5700
273#define RPB_RPF_RX_TC_MODE(1 << 8) (1 << 8)
274#define RPB_RPF_RX_FC_MODE0x30 0x30
275#define RPB_RPF_RX_BUF_EN(1 << 0) (1 << 0)
276
277/* RPB_RXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x5710-0x5790 */
278#define RPB_RXB_BUFSIZE_REG(i)(0x5710 + (i) * 0x10) (0x5710 + (i) * 0x10)
279#define RPB_RXB_BUFSIZE0x1FF 0x1FF
280#define RPB_RXB_XOFF_REG(i)(0x5714 + (i) * 0x10) (0x5714 + (i) * 0x10)
281#define RPB_RXB_XOFF_EN(1U << 31) (1U << 31)
282#define RPB_RXB_XOFF_THRESH_HI0x3FFF0000 0x3FFF0000
283#define RPB_RXB_XOFF_THRESH_LO0x3FFF 0x3FFF
284
285#define RX_DMA_DESC_CACHE_INIT_REG0x5a00 0x5a00
286#define RX_DMA_DESC_CACHE_INIT(1 << 0) (1 << 0)
287
288#define RX_DMA_INT_DESC_WRWB_EN_REG0x5a30 0x5a30
289#define RX_DMA_INT_DESC_WRWB_EN(1 << 2) (1 << 2)
290#define RX_DMA_INT_DESC_MODERATE_EN(1 << 3) (1 << 3)
291
292#define RX_INTR_MODERATION_CTL_REG(i)(0x5a40 + (i) * 4) (0x5a40 + (i) * 4)
293#define RX_INTR_MODERATION_CTL_EN(1 << 1) (1 << 1)
294#define RX_INTR_MODERATION_CTL_MIN(0xFF << 8) (0xFF << 8)
295#define RX_INTR_MODERATION_CTL_MAX(0x1FF << 16) (0x1FF << 16)
296
297#define RX_DMA_DESC_BASE_ADDRLSW_REG(i)(0x5b00 + (i) * 0x20) (0x5b00 + (i) * 0x20)
298#define RX_DMA_DESC_BASE_ADDRMSW_REG(i)(0x5b04 + (i) * 0x20) (0x5b04 + (i) * 0x20)
299#define RX_DMA_DESC_REG(i)(0x5b08 + (i) * 0x20) (0x5b08 + (i) * 0x20)
300#define RX_DMA_DESC_LEN(0x3FF << 3) (0x3FF << 3)
301#define RX_DMA_DESC_RESET(1 << 25) (1 << 25)
302#define RX_DMA_DESC_HEADER_SPLIT(1 << 28) (1 << 28)
303#define RX_DMA_DESC_VLAN_STRIP(1 << 29) (1 << 29)
304#define RX_DMA_DESC_EN(1U << 31) (1U << 31)
305#define RX_DMA_DESC_HEAD_PTR_REG(i)(0x5b0c + (i) * 0x20) (0x5b0c + (i) * 0x20)
306#define RX_DMA_DESC_HEAD_PTR0xFFF 0xFFF
307#define RX_DMA_DESC_TAIL_PTR_REG(i)(0x5b10 + (i) * 0x20) (0x5b10 + (i) * 0x20)
308#define RX_DMA_DESC_BUFSIZE_REG(i)(0x5b18 + (i) * 0x20) (0x5b18 + (i) * 0x20)
309#define RX_DMA_DESC_BUFSIZE_DATA0x000F 0x000F
310#define RX_DMA_DESC_BUFSIZE_HDR0x0FF0 0x0FF0
311
312#define RX_DMA_DCAD_REG(i)(0x6100 + (i) * 4) (0x6100 + (i) * 4)
313#define RX_DMA_DCAD_CPUID0xFF 0xFF
314#define RX_DMA_DCAD_PAYLOAD_EN(1 << 29) (1 << 29)
315#define RX_DMA_DCAD_HEADER_EN(1 << 30) (1 << 30)
316#define RX_DMA_DCAD_DESC_EN(1U << 31) (1U << 31)
317
318#define RX_DMA_DCA_REG0x6180 0x6180
319#define RX_DMA_DCA_EN(1U << 31) (1U << 31)
320#define RX_DMA_DCA_MODE0xF 0xF
321
322#define TX_SYSCONTROL_REG0x7000 0x7000
323#define TX_SYSCONTROL_RESET_DIS(1 << 29) (1 << 29)
324
325#define TX_TPO2_REG0x7040 0x7040
326#define TX_TPO2_EN(1 << 16) (1 << 16)
327
328#define TPS_DESC_VM_ARB_MODE_REG0x7300 0x7300
329#define TPS_DESC_VM_ARB_MODE(1 << 0) (1 << 0)
330#define TPS_DESC_RATE_REG0x7310 0x7310
331#define TPS_DESC_RATE_TA_RST(1U << 31) (1U << 31)
332#define TPS_DESC_RATE_LIM0x7FF 0x7FF
333#define TPS_DESC_TC_ARB_MODE_REG0x7200 0x7200
334#define TPS_DESC_TC_ARB_MODE0x3 0x3
335#define TPS_DATA_TC_ARB_MODE_REG0x7100 0x7100
336#define TPS_DATA_TC_ARB_MODE(1 << 0) (1 << 0)
337
338/* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7110-0x7130 */
339#define TPS_DATA_TCT_REG(i)(0x7110 + (i) * 4) (0x7110 + (i) * 4)
340#define TPS_DATA_TCT_CREDIT_MAX0xFFF0000 0xFFF0000
341#define TPS_DATA_TCT_WEIGHT0x1FF 0x1FF
342#define TPS2_DATA_TCT_CREDIT_MAX0xFFFF0000 0xFFFF0000
343#define TPS2_DATA_TCT_WEIGHT0x7FFF 0x7FFF
344/* TPS_DATA_TCT_REG[AQ_TRAFFICCLASS_NUM] 0x7210-0x7230 */
345#define TPS_DESC_TCT_REG(i)(0x7210 + (i) * 4) (0x7210 + (i) * 4)
346#define TPS_DESC_TCT_CREDIT_MAX0xFFF0000 0xFFF0000
347#define TPS_DESC_TCT_WEIGHT0x1FF 0x1FF
348
349#define AQ_HW_TXBUF_MAX160 160
350#define AQ_HW_RXBUF_MAX320 320
351#define AQ2_HW_TXBUF_MAX128 128
352#define AQ2_HW_RXBUF_MAX192 192
353
354#define TPO_HWCSUM_REG0x7800 0x7800
355#define TPO_HWCSUM_L4CSUM_EN(1 << 0) (1 << 0)
356#define TPO_HWCSUM_IP4CSUM_EN(1 << 1) (1 << 1)
357
358#define THM_LSO_TCP_FLAG1_REG0x7820 0x7820
359#define THM_LSO_TCP_FLAG1_FIRST0xFFF 0xFFF
360#define THM_LSO_TCP_FLAG1_MID0xFFF0000 0xFFF0000
361#define THM_LSO_TCP_FLAG2_REG0x7824 0x7824
362#define THM_LSO_TCP_FLAG2_LAST0xFFF 0xFFF
363
364#define TPB_TX_BUF_REG0x7900 0x7900
365#define TPB_TX_BUF_EN(1 << 0) (1 << 0)
366#define TPB_TX_BUF_SCP_INS_EN(1 << 2) (1 << 2)
367#define TPB_TX_BUF_CLK_GATE_EN(1 << 5) (1 << 5)
368#define TPB_TX_BUF_TC_MODE_EN(1 << 8) (1 << 8)
369
370
371/* TPB_TXB_BUFSIZE_REG[AQ_TRAFFICCLASS_NUM] 0x7910-7990 */
372#define TPB_TXB_BUFSIZE_REG(i)(0x7910 + (i) * 0x10) (0x7910 + (i) * 0x10)
373#define TPB_TXB_BUFSIZE(0xFF) (0xFF)
374#define TPB_TXB_THRESH_REG(i)(0x7914 + (i) * 0x10) (0x7914 + (i) * 0x10)
375#define TPB_TXB_THRESH_HI0x1FFF0000 0x1FFF0000
376#define TPB_TXB_THRESH_LO0x1FFF 0x1FFF
377
378#define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG0x7b20 0x7b20
379
380#define TX_DMA_INT_DESC_WRWB_EN_REG0x7b40 0x7b40
381#define TX_DMA_INT_DESC_WRWB_EN(1 << 1) (1 << 1)
382#define TX_DMA_INT_DESC_MODERATE_EN(1 << 4) (1 << 4)
383
384#define TX_DMA_DESC_BASE_ADDRLSW_REG(i)(0x7c00 + (i) * 0x40) (0x7c00 + (i) * 0x40)
385#define TX_DMA_DESC_BASE_ADDRMSW_REG(i)(0x7c04 + (i) * 0x40) (0x7c04 + (i) * 0x40)
386#define TX_DMA_DESC_REG(i)(0x7c08 + (i) * 0x40) (0x7c08 + (i) * 0x40)
387#define TX_DMA_DESC_LEN0x00000FF8 0x00000FF8
388#define TX_DMA_DESC_EN0x80000000 0x80000000
389#define TX_DMA_DESC_HEAD_PTR_REG(i)(0x7c0c + (i) * 0x40) (0x7c0c + (i) * 0x40)
390#define TX_DMA_DESC_HEAD_PTR0x00000FFF 0x00000FFF
391#define TX_DMA_DESC_TAIL_PTR_REG(i)(0x7c10 + (i) * 0x40) (0x7c10 + (i) * 0x40)
392#define TX_DMA_DESC_WRWB_THRESH_REG(i)(0x7c18 + (i) * 0x40) (0x7c18 + (i) * 0x40)
393#define TX_DMA_DESC_WRWB_THRESH0x00003F00 0x00003F00
394
395#define TDM_DCAD_REG(i)(0x8400 + (i) * 4) (0x8400 + (i) * 4)
396#define TDM_DCAD_CPUID0x7F 0x7F
397#define TDM_DCAD_CPUID_EN0x80000000 0x80000000
398
399#define TDM_DCA_REG0x8480 0x8480
400#define TDM_DCA_EN(1U << 31) (1U << 31)
401#define TDM_DCA_MODE0xF 0xF
402
403#define TX_INTR_MODERATION_CTL_REG(i)(0x8980 + (i) * 4) (0x8980 + (i) * 4)
404#define TX_INTR_MODERATION_CTL_EN(1 << 1) (1 << 1)
405#define TX_INTR_MODERATION_CTL_MIN(0xFF << 8) (0xFF << 8)
406#define TX_INTR_MODERATION_CTL_MAX(0x1FF << 16) (0x1FF << 16)
407
408/* AQ2 registers */
409
410#define AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG0x0e00 0x0e00
411#define AQ2_MIF_HOST_FINISHED_STATUS_READ_REG0x0e04 0x0e04
412#define AQ2_MIF_HOST_FINISHED_STATUS_ACK(1 << 0) (1 << 0)
413
414#define AQ2_MCP_HOST_REQ_INT_REG0x0f00 0x0f00
415#define AQ2_MCP_HOST_REQ_INT_READY(1 << 0) (1 << 0)
416#define AQ2_MCP_HOST_REQ_INT_SET_REG0x0f04 0x0f04
417#define AQ2_MCP_HOST_REQ_INT_CLR_REG0x0f08 0x0f08
418
419#define AQ2_MIF_BOOT_REG0x3040 0x3040
420#define AQ2_MIF_BOOT_HOST_DATA_LOADED(1 << 16) (1 << 16)
421#define AQ2_MIF_BOOT_BOOT_STARTED(1 << 24) (1 << 24)
422#define AQ2_MIF_BOOT_CRASH_INIT(1 << 27) (1 << 27)
423#define AQ2_MIF_BOOT_BOOT_CODE_FAILED(1 << 28) (1 << 28)
424#define AQ2_MIF_BOOT_FW_INIT_FAILED(1 << 29) (1 << 29)
425#define AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS(1U << 31) (1U << 31)
426
427/* AQ2 action resolver table */
428#define AQ2_ART_ACTION_ACT_SHIFT8 8
429#define AQ2_ART_ACTION_RSS0x0080 0x0080
430#define AQ2_ART_ACTION_INDEX_SHIFT2 2
431#define AQ2_ART_ACTION_ENABLE0x0001 0x0001
432#define AQ2_ART_ACTION(act, rss, idx, en)(((act) << 8) | ((rss) ? 0x0080 : 0) | ((idx) << 2
) | ((en) ? 0x0001 : 0)) \
433 (((act) << AQ2_ART_ACTION_ACT_SHIFT8) | \
434 ((rss) ? AQ2_ART_ACTION_RSS0x0080 : 0) | \
435 ((idx) << AQ2_ART_ACTION_INDEX_SHIFT2) | \
436 ((en) ? AQ2_ART_ACTION_ENABLE0x0001 : 0))
437#define AQ2_ART_ACTION_DROP(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(1) ? 0x0001 : 0)) AQ2_ART_ACTION(0, 0, 0, 1)(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(1) ? 0x0001 : 0))
438#define AQ2_ART_ACTION_DISABLE(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(0) ? 0x0001 : 0)) AQ2_ART_ACTION(0, 0, 0, 0)(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(0) ? 0x0001 : 0))
439#define AQ2_ART_ACTION_ASSIGN_QUEUE(q)(((1) << 8) | ((0) ? 0x0080 : 0) | (((q)) << 2) |
((1) ? 0x0001 : 0)) AQ2_ART_ACTION(1, 0, (q), 1)(((1) << 8) | ((0) ? 0x0080 : 0) | (((q)) << 2) |
((1) ? 0x0001 : 0))
440#define AQ2_ART_ACTION_ASSIGN_TC(tc)(((1) << 8) | ((1) ? 0x0080 : 0) | (((tc)) << 2) |
((1) ? 0x0001 : 0)) AQ2_ART_ACTION(1, 1, (tc), 1)(((1) << 8) | ((1) ? 0x0080 : 0) | (((tc)) << 2) |
((1) ? 0x0001 : 0))
441
442#define AQ2_RPF_TAG_PCP_MASK0xe0000000 0xe0000000
443#define AQ2_RPF_TAG_PCP_SHIFT29 29
444#define AQ2_RPF_TAG_FLEX_MASK0x18000000 0x18000000
445#define AQ2_RPF_TAG_UNKNOWN_MASK0x07000000 0x07000000
446#define AQ2_RPF_TAG_L4_MASK0x00e00000 0x00e00000
447#define AQ2_RPF_TAG_L3_V6_MASK0x001c0000 0x001c0000
448#define AQ2_RPF_TAG_L3_V4_MASK0x00038000 0x00038000
449#define AQ2_RPF_TAG_UNTAG_MASK0x00004000 0x00004000
450#define AQ2_RPF_TAG_VLAN_MASK0x00003c00 0x00003c00
451#define AQ2_RPF_TAG_ET_MASK0x00000380 0x00000380
452#define AQ2_RPF_TAG_ALLMC_MASK0x00000040 0x00000040
453#define AQ2_RPF_TAG_UC_MASK0x0000002f 0x0000002f
454
455/* index of aq2_filter_art_set() */
456#define AQ2_RPF_INDEX_L2_PROMISC_OFF0 0
457#define AQ2_RPF_INDEX_VLAN_PROMISC_OFF1 1
458#define AQ2_RPF_INDEX_L3L4_USER8 8
459#define AQ2_RPF_INDEX_ET_PCP_USER24 24
460#define AQ2_RPF_INDEX_VLAN_USER40 40
461#define AQ2_RPF_INDEX_PCP_TO_TC56 56
462
463#define AQ2_RPF_L2BC_TAG_REG0x50f0 0x50f0
464#define AQ2_RPF_L2BC_TAG_MASK0x0000003f 0x0000003f
465
466#define AQ2_RPF_NEW_CTRL_REG0x5104 0x5104
467#define AQ2_RPF_NEW_CTRL_ENABLE(1 << 11) (1 << 11)
468
469#define AQ2_RPF_REDIR2_REG0x54c8 0x54c8
470#define AQ2_RPF_REDIR2_INDEX(1 << 12) (1 << 12)
471#define AQ2_RPF_REDIR2_HASHTYPE0x00000100 0x00000100
472#define AQ2_RPF_REDIR2_HASHTYPE_NONE0 0
473#define AQ2_RPF_REDIR2_HASHTYPE_IP(1 << 0) (1 << 0)
474#define AQ2_RPF_REDIR2_HASHTYPE_TCP4(1 << 1) (1 << 1)
475#define AQ2_RPF_REDIR2_HASHTYPE_UDP4(1 << 2) (1 << 2)
476#define AQ2_RPF_REDIR2_HASHTYPE_IP6(1 << 3) (1 << 3)
477#define AQ2_RPF_REDIR2_HASHTYPE_TCP6(1 << 4) (1 << 4)
478#define AQ2_RPF_REDIR2_HASHTYPE_UDP6(1 << 5) (1 << 5)
479#define AQ2_RPF_REDIR2_HASHTYPE_IP6EX(1 << 6) (1 << 6)
480#define AQ2_RPF_REDIR2_HASHTYPE_TCP6EX(1 << 7) (1 << 7)
481#define AQ2_RPF_REDIR2_HASHTYPE_UDP6EX(1 << 8) (1 << 8)
482#define AQ2_RPF_REDIR2_HASHTYPE_ALL0x00000100 0x00000100
483
484#define AQ2_RPF_REC_TAB_ENABLE_REG0x6ff0 0x6ff0
485#define AQ2_RPF_REC_TAB_ENABLE_MASK0x0000ffff 0x0000ffff
486
487#define AQ2_LAUNCHTIME_CTRL_REG0x7a1c 0x7a1c
488#define AQ2_LAUNCHTIME_CTRL_RATIO0x0000ff00 0x0000ff00
489#define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUARTER4 4
490#define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF2 2
491#define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL1 1
492
493#define AQ2_TX_INTR_MODERATION_CTL_REG(i)(0x7c28 + (i) * 0x40) (0x7c28 + (i) * 0x40)
494#define AQ2_TX_INTR_MODERATION_CTL_EN(1 << 1) (1 << 1)
495#define AQ2_TX_INTR_MODERATION_CTL_MIN0x0000ff00 0x0000ff00
496#define AQ2_TX_INTR_MODERATION_CTL_MAX0x01ff0000 0x01ff0000
497
498#define AQ2_FW_INTERFACE_IN_MTU_REG0x12000 0x12000
499#define AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG0x12008 0x12008
500
501#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG0x12010 0x12010
502#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE0x0000000f 0x0000000f
503#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_INVALID0 0
504#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE1 1
505#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SLEEP_PROXY2 2
506#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_LOWPOWER3 3
507#define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN4 4
508
509#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG0x12018 0x12018
510#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT(1 << 27) (1 << 27)
511#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX(1 << 25) (1 << 25)
512#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX(1 << 24) (1 << 24)
513#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_10G(1 << 20) (1 << 20)
514#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_5G(1 << 19) (1 << 19)
515#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_2G5(1 << 18) (1 << 18)
516#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_1G(1 << 17) (1 << 17)
517#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_100M(1 << 16) (1 << 16)
518#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G(1 << 15) (1 << 15)
519#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G(1 << 14) (1 << 14)
520#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G(1 << 13) (1 << 13)
521#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5(1 << 12) (1 << 12)
522#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5(1 << 11) (1 << 11)
523#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G(1 << 10) (1 << 10)
524#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M(1 << 9) (1 << 9)
525#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M(1 << 8) (1 << 8)
526#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD(1 << 7) (1 << 7)
527#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD(1 << 6) (1 << 6)
528#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD(1 << 5) (1 << 5)
529#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EXTERNAL_LOOPBACK(1 << 4) (1 << 4)
530#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_INTERNAL_LOOPBACK(1 << 3) (1 << 3)
531#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_MINIMAL_LINK_SPEED(1 << 2) (1 << 2)
532#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_RENEGOTIATE(1 << 1) (1 << 1)
533#define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP(1 << 0) (1 << 0)
534
535#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG0x12a58 0x12a58
536#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC0x00800000 0x00800000
537#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX0x007c0000 0x007c0000
538#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT0x00010000 0x00010000
539#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC0x00008000 0x00008000
540#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX0x00007c00 0x00007c00
541#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT0x00000100 0x00000100
542#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC0x00000080 0x00000080
543#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX0x0000007c 0x0000007c
544#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_MCAST0x00000002 0x00000002
545#define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_ALL0x00000001 0x00000001
546
547#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG0x13000 0x13000
548#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B0xffff0000 0xffff0000
549#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B_S16 16
550#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A0x0000ffff 0x0000ffff
551#define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A_S0 0
552
553#define AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG0x13004 0x13004
554#define AQ2_FW_INTERFACE_OUT_VERSION_MAC_REG0x13008 0x13008
555
556#define AQ2_FW_INTERFACE_OUT_VERSION_PHY_REG0x1300c 0x1300c
557#define AQ2_FW_INTERFACE_OUT_VERSION_BUILD0xffff0000 0xffff0000
558#define AQ2_FW_INTERFACE_OUT_VERSION_BUILD_S16 16
559#define AQ2_FW_INTERFACE_OUT_VERSION_MINOR0x0000ff00 0x0000ff00
560#define AQ2_FW_INTERFACE_OUT_VERSION_MINOR_S8 8
561#define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR0x000000ff 0x000000ff
562#define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR_S0 0
563
564#define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG0x13010 0x13010
565#define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER0x0000000f 0x0000000f
566#define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A00 0
567#define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B01 1
568
569#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG0x13014 0x13014
570#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_DUPLEX(1 << 11) (1 << 11)
571#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE(1 << 10) (1 << 10)
572#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX(1 << 9) (1 << 9)
573#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX(1 << 8) (1 << 8)
574#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE0x000000f0 0x000000f0
575#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_S4 4
576#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G6 6
577#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G5 5
578#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G54 4
579#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G3 3
580#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M2 2
581#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M1 1
582#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID0 0
583#define AQ2_FW_INTERFACE_OUT_LINK_STATUS_STATE0x0000000f 0x0000000f
584
585#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG0x13774 0x13774
586#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX0x00ff0000 0x00ff0000
587#define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX_SHIFT16 16
588
589#define AQ2_RPF_ACT_ART_REQ_TAG_REG(i)(0x14000 + (i) * 0x10) (0x14000 + (i) * 0x10)
590#define AQ2_RPF_ACT_ART_REQ_MASK_REG(i)(0x14004 + (i) * 0x10) (0x14004 + (i) * 0x10)
591#define AQ2_RPF_ACT_ART_REQ_ACTION_REG(i)(0x14008 + (i) * 0x10) (0x14008 + (i) * 0x10)
592
593#define __LOWEST_SET_BIT(__mask)(((((uint32_t)__mask) - 1) & ((uint32_t)__mask)) ^ ((uint32_t
)__mask)) (((((uint32_t)__mask) - 1) & ((uint32_t)__mask)) ^ ((uint32_t)__mask))
594#define __SHIFTIN(__x, __mask)((__x) * (((((uint32_t)__mask) - 1) & ((uint32_t)__mask))
^ ((uint32_t)__mask))) ((__x) * __LOWEST_SET_BIT(__mask)(((((uint32_t)__mask) - 1) & ((uint32_t)__mask)) ^ ((uint32_t
)__mask)))
595
596#define AQ_READ_REG(sc, reg)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((reg)))) \
597 bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((reg))))
598#define AQ_READ_REGS(sc, reg, p, cnt)(((sc)->sc_iot)->read_region_4(((sc)->sc_ioh), ((reg
)), ((p)), ((cnt)))); \
599 bus_space_read_region_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (p), (cnt))(((sc)->sc_iot)->read_region_4(((sc)->sc_ioh), ((reg
)), ((p)), ((cnt))));
600
601#define AQ_WRITE_REG(sc, reg, val)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((reg)), ((
val)))) \
602 bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((reg)), ((
val))))
603
604#define AQ_WRITE_REG_BIT(sc, reg, mask, val)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((reg))))); _v &= ~(mask); if ((val) != 0
) _v |= (((val)) * (((((uint32_t)(mask)) - 1) & ((uint32_t
)(mask))) ^ ((uint32_t)(mask)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((reg))), ((_v)))); } while ( 0) \
605 do { \
606 uint32_t _v; \
607 _v = AQ_READ_REG((sc), (reg))((((sc))->sc_iot)->read_4((((sc))->sc_ioh), (((reg))
))); \
608 _v &= ~(mask); \
609 if ((val) != 0) \
610 _v |= __SHIFTIN((val), (mask))(((val)) * (((((uint32_t)(mask)) - 1) & ((uint32_t)(mask)
)) ^ ((uint32_t)(mask)))); \
611 AQ_WRITE_REG((sc), (reg), _v)((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (((reg)
)), ((_v)))); \
612 } while (/* CONSTCOND */ 0)
613
614#define AQ_READ64_REG(sc, reg)((uint64_t)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (
(reg)))) | (((uint64_t)(((sc)->sc_iot)->read_4(((sc)->
sc_ioh), (((reg) + 4))))) << 32)) \
615 ((uint64_t)AQ_READ_REG(sc, reg)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((reg)))) | \
616 (((uint64_t)AQ_READ_REG(sc, (reg) + 4)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (((reg) + 4)
)))) << 32))
617
618#define AQ_WRITE64_REG(sc, reg, val)do { (((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((reg)
), (((uint32_t)val)))); (((sc)->sc_iot)->write_4(((sc)->
sc_ioh), ((reg + 4)), (((uint32_t)(val >> 32))))); } while
( 0) \
619 do { \
620 AQ_WRITE_REG(sc, reg, (uint32_t)val)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((reg)), ((
(uint32_t)val)))); \
621 AQ_WRITE_REG(sc, reg + 4, (uint32_t)(val >> 32))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((reg + 4))
, (((uint32_t)(val >> 32))))); \
622 } while (/* CONSTCOND */0)
623
624#define WAIT_FOR(expr, us, n, errp)do { unsigned int _n; for (_n = n; (!(expr)) && _n !=
0; --_n) { (*delay_func)((us)); } if ((errp != ((void *)0)))
{ if (_n == 0) *(errp) = 60; else *(errp) = 0; } } while ( 0
) \
625 do { \
626 unsigned int _n; \
627 for (_n = n; (!(expr)) && _n != 0; --_n) { \
628 delay((us))(*delay_func)((us)); \
629 } \
630 if ((errp != NULL((void *)0))) { \
631 if (_n == 0) \
632 *(errp) = ETIMEDOUT60; \
633 else \
634 *(errp) = 0; \
635 } \
636 } while (/* CONSTCOND */ 0)
637
638#define FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff) (((sc)->sc_fw_version >> 24) & 0xff)
639#define FW_VERSION_MINOR(sc)(((sc)->sc_fw_version >> 16) & 0xff) (((sc)->sc_fw_version >> 16) & 0xff)
640#define FW_VERSION_BUILD(sc)((sc)->sc_fw_version & 0xffff) ((sc)->sc_fw_version & 0xffff)
641
642#define FEATURES_MIPS0x00000001 0x00000001
643#define FEATURES_TPO20x00000002 0x00000002
644#define FEATURES_RPF20x00000004 0x00000004
645#define FEATURES_MPI_AQ0x00000008 0x00000008
646#define FEATURES_AQ1_REV_A00x01000000 0x01000000
647#define FEATURES_AQ1_REV_A(0x01000000) (FEATURES_AQ1_REV_A00x01000000)
648#define FEATURES_AQ1_REV_B00x02000000 0x02000000
649#define FEATURES_AQ1_REV_B10x04000000 0x04000000
650#define FEATURES_AQ1_REV_B(0x02000000|0x04000000) (FEATURES_AQ1_REV_B00x02000000|FEATURES_AQ1_REV_B10x04000000)
651#define FEATURES_AQ1((0x01000000)|(0x02000000|0x04000000)) (FEATURES_AQ1_REV_A(0x01000000)|FEATURES_AQ1_REV_B(0x02000000|0x04000000))
652#define FEATURES_AQ20x10000000 0x10000000
653#define FEATURES_AQ2_IFACE_A00x20000000 0x20000000
654#define FEATURES_AQ2_IFACE_B00x40000000 0x40000000
655#define HWTYPE_AQ1_P(sc)(((sc)->sc_features & ((0x01000000)|(0x02000000|0x04000000
))) != 0) (((sc)->sc_features & FEATURES_AQ1((0x01000000)|(0x02000000|0x04000000))) != 0)
656#define HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0) (((sc)->sc_features & FEATURES_AQ20x10000000) != 0)
657
658/* lock for firmware interface */
659#define AQ_MPI_LOCK(sc)mtx_enter(&(sc)->sc_mpi_mutex); mtx_enter(&(sc)->sc_mpi_mutex);
660#define AQ_MPI_UNLOCK(sc)mtx_leave(&(sc)->sc_mpi_mutex); mtx_leave(&(sc)->sc_mpi_mutex);
661
662#define FW2X_CTRL_10BASET_HD(1 << 0) (1 << 0)
663#define FW2X_CTRL_10BASET_FD(1 << 1) (1 << 1)
664#define FW2X_CTRL_100BASETX_HD(1 << 2) (1 << 2)
665#define FW2X_CTRL_100BASET4_HD(1 << 3) (1 << 3)
666#define FW2X_CTRL_100BASET2_HD(1 << 4) (1 << 4)
667#define FW2X_CTRL_100BASETX_FD(1 << 5) (1 << 5)
668#define FW2X_CTRL_100BASET2_FD(1 << 6) (1 << 6)
669#define FW2X_CTRL_1000BASET_HD(1 << 7) (1 << 7)
670#define FW2X_CTRL_1000BASET_FD(1 << 8) (1 << 8)
671#define FW2X_CTRL_2P5GBASET_FD(1 << 9) (1 << 9)
672#define FW2X_CTRL_5GBASET_FD(1 << 10) (1 << 10)
673#define FW2X_CTRL_10GBASET_FD(1 << 11) (1 << 11)
674#define FW2X_CTRL_RESERVED1(1ULL << 32) (1ULL << 32)
675#define FW2X_CTRL_10BASET_EEE(1ULL << 33) (1ULL << 33)
676#define FW2X_CTRL_RESERVED2(1ULL << 34) (1ULL << 34)
677#define FW2X_CTRL_PAUSE(1ULL << 35) (1ULL << 35)
678#define FW2X_CTRL_ASYMMETRIC_PAUSE(1ULL << 36) (1ULL << 36)
679#define FW2X_CTRL_100BASETX_EEE(1ULL << 37) (1ULL << 37)
680#define FW2X_CTRL_RESERVED3(1ULL << 38) (1ULL << 38)
681#define FW2X_CTRL_RESERVED4(1ULL << 39) (1ULL << 39)
682#define FW2X_CTRL_1000BASET_FD_EEE(1ULL << 40) (1ULL << 40)
683#define FW2X_CTRL_2P5GBASET_FD_EEE(1ULL << 41) (1ULL << 41)
684#define FW2X_CTRL_5GBASET_FD_EEE(1ULL << 42) (1ULL << 42)
685#define FW2X_CTRL_10GBASET_FD_EEE(1ULL << 43) (1ULL << 43)
686#define FW2X_CTRL_RESERVED5(1ULL << 44) (1ULL << 44)
687#define FW2X_CTRL_RESERVED6(1ULL << 45) (1ULL << 45)
688#define FW2X_CTRL_RESERVED7(1ULL << 46) (1ULL << 46)
689#define FW2X_CTRL_RESERVED8(1ULL << 47) (1ULL << 47)
690#define FW2X_CTRL_RESERVED9(1ULL << 48) (1ULL << 48)
691#define FW2X_CTRL_CABLE_DIAG(1ULL << 49) (1ULL << 49)
692#define FW2X_CTRL_TEMPERATURE(1ULL << 50) (1ULL << 50)
693#define FW2X_CTRL_DOWNSHIFT(1ULL << 51) (1ULL << 51)
694#define FW2X_CTRL_PTP_AVB_EN(1ULL << 52) (1ULL << 52)
695#define FW2X_CTRL_MEDIA_DETECT(1ULL << 53) (1ULL << 53)
696#define FW2X_CTRL_LINK_DROP(1ULL << 54) (1ULL << 54)
697#define FW2X_CTRL_SLEEP_PROXY(1ULL << 55) (1ULL << 55)
698#define FW2X_CTRL_WOL(1ULL << 56) (1ULL << 56)
699#define FW2X_CTRL_MAC_STOP(1ULL << 57) (1ULL << 57)
700#define FW2X_CTRL_EXT_LOOPBACK(1ULL << 58) (1ULL << 58)
701#define FW2X_CTRL_INT_LOOPBACK(1ULL << 59) (1ULL << 59)
702#define FW2X_CTRL_EFUSE_AGENT(1ULL << 60) (1ULL << 60)
703#define FW2X_CTRL_WOL_TIMER(1ULL << 61) (1ULL << 61)
704#define FW2X_CTRL_STATISTICS(1ULL << 62) (1ULL << 62)
705#define FW2X_CTRL_TRANSACTION_ID(1ULL << 63) (1ULL << 63)
706
707#define FW2X_CTRL_RATE_100M(1 << 5) FW2X_CTRL_100BASETX_FD(1 << 5)
708#define FW2X_CTRL_RATE_1G(1 << 8) FW2X_CTRL_1000BASET_FD(1 << 8)
709#define FW2X_CTRL_RATE_2G5(1 << 9) FW2X_CTRL_2P5GBASET_FD(1 << 9)
710#define FW2X_CTRL_RATE_5G(1 << 10) FW2X_CTRL_5GBASET_FD(1 << 10)
711#define FW2X_CTRL_RATE_10G(1 << 11) FW2X_CTRL_10GBASET_FD(1 << 11)
712#define FW2X_CTRL_RATE_MASK((1 << 5) | (1 << 8) | (1 << 9) | (1 <<
10) | (1 << 11)) \
713 (FW2X_CTRL_RATE_100M(1 << 5) | \
714 FW2X_CTRL_RATE_1G(1 << 8) | \
715 FW2X_CTRL_RATE_2G5(1 << 9) | \
716 FW2X_CTRL_RATE_5G(1 << 10) | \
717 FW2X_CTRL_RATE_10G(1 << 11))
718#define FW2X_CTRL_EEE_MASK((1ULL << 33) | (1ULL << 37) | (1ULL << 40)
| (1ULL << 41) | (1ULL << 42) | (1ULL << 43
)) \
719 (FW2X_CTRL_10BASET_EEE(1ULL << 33) | \
720 FW2X_CTRL_100BASETX_EEE(1ULL << 37) | \
721 FW2X_CTRL_1000BASET_FD_EEE(1ULL << 40) | \
722 FW2X_CTRL_2P5GBASET_FD_EEE(1ULL << 41) | \
723 FW2X_CTRL_5GBASET_FD_EEE(1ULL << 42) | \
724 FW2X_CTRL_10GBASET_FD_EEE(1ULL << 43))
725
726enum aq_hwtype {
727 HWTYPE_AQ1,
728 HWTYPE_AQ2
729};
730
731enum aq_fw_bootloader_mode {
732 FW_BOOT_MODE_UNKNOWN = 0,
733 FW_BOOT_MODE_FLB,
734 FW_BOOT_MODE_RBL_FLASH,
735 FW_BOOT_MODE_RBL_HOST_BOOTLOAD
736};
737
738enum aq_media_type {
739 AQ_MEDIA_TYPE_UNKNOWN = 0,
740 AQ_MEDIA_TYPE_FIBRE,
741 AQ_MEDIA_TYPE_TP
742};
743
744enum aq_link_speed {
745 AQ_LINK_NONE = 0,
746 AQ_LINK_10M = (1 << 0),
747 AQ_LINK_100M = (1 << 1),
748 AQ_LINK_1G = (1 << 2),
749 AQ_LINK_2G5 = (1 << 3),
750 AQ_LINK_5G = (1 << 4),
751 AQ_LINK_10G = (1 << 5)
752};
753
754#define AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
) (AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | \
755 AQ_LINK_5G | AQ_LINK_10G )
756#define AQ_LINK_AUTO(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
) AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
757
758enum aq_link_eee {
759 AQ_EEE_DISABLE = 0,
760 AQ_EEE_ENABLE = 1
761};
762
763enum aq_hw_fw_mpi_state {
764 MPI_DEINIT = 0,
765 MPI_RESET = 1,
766 MPI_INIT = 2,
767 MPI_POWER = 4
768};
769
770enum aq_link_fc {
771 AQ_FC_NONE = 0,
772 AQ_FC_RX = (1 << 0),
773 AQ_FC_TX = (1 << 1),
774 AQ_FC_ALL = (AQ_FC_RX | AQ_FC_TX)
775};
776
777struct aq_dmamem {
778 bus_dmamap_t aqm_map;
779 bus_dma_segment_t aqm_seg;
780 int aqm_nsegs;
781 size_t aqm_size;
782 caddr_t aqm_kva;
783};
784
785#define AQ_DMA_MAP(_aqm)((_aqm)->aqm_map) ((_aqm)->aqm_map)
786#define AQ_DMA_DVA(_aqm)((_aqm)->aqm_map->dm_segs[0].ds_addr) ((_aqm)->aqm_map->dm_segs[0].ds_addr)
787#define AQ_DMA_KVA(_aqm)((void *)(_aqm)->aqm_kva) ((void *)(_aqm)->aqm_kva)
788#define AQ_DMA_LEN(_aqm)((_aqm)->aqm_size) ((_aqm)->aqm_size)
789
790
791struct aq_mailbox_header {
792 uint32_t version;
793 uint32_t transaction_id;
794 int32_t error;
795} __packed__attribute__((__packed__)) __aligned(4)__attribute__((__aligned__(4)));
796
797struct aq_hw_stats_s {
798 uint32_t uprc;
799 uint32_t mprc;
800 uint32_t bprc;
801 uint32_t erpt;
802 uint32_t uptc;
803 uint32_t mptc;
804 uint32_t bptc;
805 uint32_t erpr;
806 uint32_t mbtc;
807 uint32_t bbtc;
808 uint32_t mbrc;
809 uint32_t bbrc;
810 uint32_t ubrc;
811 uint32_t ubtc;
812 uint32_t ptc;
813 uint32_t prc;
814 uint32_t dpc; /* not exists in fw2x_msm_statistics */
815 uint32_t cprc; /* not exists in fw2x_msm_statistics */
816} __packed__attribute__((__packed__)) __aligned(4)__attribute__((__aligned__(4)));
817
818struct aq_fw2x_capabilities {
819 uint32_t caps_lo;
820 uint32_t caps_hi;
821} __packed__attribute__((__packed__)) __aligned(4)__attribute__((__aligned__(4)));
822
823struct aq_fw2x_msm_statistics {
824 uint32_t uprc;
825 uint32_t mprc;
826 uint32_t bprc;
827 uint32_t erpt;
828 uint32_t uptc;
829 uint32_t mptc;
830 uint32_t bptc;
831 uint32_t erpr;
832 uint32_t mbtc;
833 uint32_t bbtc;
834 uint32_t mbrc;
835 uint32_t bbrc;
836 uint32_t ubrc;
837 uint32_t ubtc;
838 uint32_t ptc;
839 uint32_t prc;
840} __packed__attribute__((__packed__)) __aligned(4)__attribute__((__aligned__(4)));
841
842struct aq_fw2x_phy_cable_diag_data {
843 uint32_t lane_data[4];
844} __packed__attribute__((__packed__)) __aligned(4)__attribute__((__aligned__(4)));
845
846struct aq_fw2x_mailbox { /* struct fwHostInterface */
847 struct aq_mailbox_header header;
848 struct aq_fw2x_msm_statistics msm; /* msmStatistics_t msm; */
849
850 uint32_t phy_info1;
851#define PHYINFO1_FAULT_CODE__BITS(31,16) __BITS(31,16)
852#define PHYINFO1_PHY_H_BIT__BITS(0,15) __BITS(0,15)
853 uint32_t phy_info2;
854#define PHYINFO2_TEMPERATURE__BITS(15,0) __BITS(15,0)
855#define PHYINFO2_CABLE_LEN__BITS(23,16) __BITS(23,16)
856
857 struct aq_fw2x_phy_cable_diag_data diag_data;
858 uint32_t reserved[8];
859
860 struct aq_fw2x_capabilities caps;
861
862 /* ... */
863} __packed__attribute__((__packed__)) __aligned(4)__attribute__((__aligned__(4)));
864
865struct aq_rx_desc_read {
866 uint64_t buf_addr;
867 uint64_t hdr_addr;
868} __packed__attribute__((__packed__));
869
870struct aq_rx_desc_wb {
871 uint32_t type;
872#define AQ_RXDESC_TYPE_RSSTYPE0x000f 0x000f
873#define AQ_RXDESC_TYPE_ETHER0x0030 0x0030
874#define AQ_RXDESC_TYPE_PROTO0x01c0 0x01c0
875#define AQ_RXDESC_TYPE_VLAN(1 << 9) (1 << 9)
876#define AQ_RXDESC_TYPE_VLAN2(1 << 10) (1 << 10)
877#define AQ_RXDESC_TYPE_DMA_ERR(1 << 12) (1 << 12)
878#define AQ_RXDESC_TYPE_V4_SUM(1 << 19) (1 << 19)
879#define AQ_RXDESC_TYPE_L4_SUM(1 << 20) (1 << 20)
880 uint32_t rss_hash;
881 uint16_t status;
882#define AQ_RXDESC_STATUS_DD(1 << 0) (1 << 0)
883#define AQ_RXDESC_STATUS_EOP(1 << 1) (1 << 1)
884#define AQ_RXDESC_STATUS_MACERR(1 << 2) (1 << 2)
885#define AQ_RXDESC_STATUS_V4_SUM_NG(1 << 3) (1 << 3)
886#define AQ_RXDESC_STATUS_L4_SUM_ERR(1 << 4) (1 << 4)
887#define AQ_RXDESC_STATUS_L4_SUM_OK(1 << 5) (1 << 5)
888 uint16_t pkt_len;
889 uint16_t next_desc_ptr;
890 uint16_t vlan;
891} __packed__attribute__((__packed__));
892
893struct aq_tx_desc {
894 uint64_t buf_addr;
895 uint32_t ctl1;
896#define AQ_TXDESC_CTL1_TYPE_TXD0x00000001 0x00000001
897#define AQ_TXDESC_CTL1_TYPE_TXC0x00000002 0x00000002
898#define AQ_TXDESC_CTL1_BLEN_SHIFT4 4
899#define AQ_TXDESC_CTL1_VLAN_SHIFT4 4
900#define AQ_TXDESC_CTL1_DD(1 << 20) (1 << 20)
901#define AQ_TXDESC_CTL1_CMD_EOP(1 << 21) (1 << 21)
902#define AQ_TXDESC_CTL1_CMD_VLAN(1 << 22) (1 << 22)
903#define AQ_TXDESC_CTL1_CMD_FCS(1 << 23) (1 << 23)
904#define AQ_TXDESC_CTL1_CMD_IP4CSUM(1 << 24) (1 << 24)
905#define AQ_TXDESC_CTL1_CMD_L4CSUM(1 << 25) (1 << 25)
906#define AQ_TXDESC_CTL1_CMD_WB(1 << 27) (1 << 27)
907
908#define AQ_TXDESC_CTL1_VID_SHIFT4 4
909 uint32_t ctl2;
910#define AQ_TXDESC_CTL2_LEN_SHIFT14 14
911#define AQ_TXDESC_CTL2_CTX_EN(1 << 13) (1 << 13)
912} __packed__attribute__((__packed__));
913
914struct aq_slot {
915 bus_dmamap_t as_map;
916 struct mbuf *as_m;
917};
918
919struct aq_rxring {
920 struct ifiqueue *rx_ifiq;
921 struct aq_dmamem rx_mem;
922 struct aq_slot *rx_slots;
923 int rx_q;
924 int rx_irq;
925
926 struct timeout rx_refill;
927 struct if_rxring rx_rxr;
928 uint32_t rx_prod;
929 uint32_t rx_cons;
930
931 struct mbuf *rx_m_head;
932 struct mbuf **rx_m_tail;
933 int rx_m_error;
934};
935
936struct aq_txring {
937 struct ifqueue *tx_ifq;
938 struct aq_dmamem tx_mem;
939 struct aq_slot *tx_slots;
940 int tx_q;
941 int tx_irq;
942 uint32_t tx_prod;
943 uint32_t tx_cons;
944};
945
946struct aq_queues {
947 char q_name[16];
948 void *q_ihc;
949 struct aq_softc *q_sc;
950 int q_index;
951 struct aq_rxring q_rx;
952 struct aq_txring q_tx;
953};
954
955
956struct aq_softc;
957struct aq_firmware_ops {
958 int (*reset)(struct aq_softc *);
959 int (*get_mac_addr)(struct aq_softc *);
960 int (*set_mode)(struct aq_softc *, enum aq_hw_fw_mpi_state,
961 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee);
962 int (*get_mode)(struct aq_softc *, enum aq_hw_fw_mpi_state *,
963 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *);
964 int (*get_stats)(struct aq_softc *, struct aq_hw_stats_s *);
965};
966
967struct aq_softc {
968 struct device sc_dev;
969 uint16_t sc_product;
970 uint16_t sc_revision;
971 bus_dma_tag_t sc_dmat;
972 pci_chipset_tag_t sc_pc;
973 pcitag_t sc_pcitag;
974 int sc_nqueues;
975 struct aq_queues sc_queues[AQ_MAXQ8];
976 struct intrmap *sc_intrmap;
977 void *sc_ih;
978 bus_space_handle_t sc_ioh;
979 bus_space_tag_t sc_iot;
980
981 uint32_t sc_mbox_addr;
982 int sc_rbl_enabled;
983 int sc_fast_start_enabled;
984 int sc_flash_present;
985 int sc_art_filter_base_index;
986 uint32_t sc_fw_version;
987 const struct aq_firmware_ops *sc_fw_ops;
988 uint64_t sc_fw_caps;
989 enum aq_media_type sc_media_type;
990 enum aq_link_speed sc_available_rates;
991 uint32_t sc_features;
992 int sc_linkstat_irq;
993 struct arpcom sc_arpcom;
994 struct ifmedia sc_media;
995
996 struct ether_addr sc_enaddr;
997 struct mutex sc_mpi_mutex;
998};
999
1000const struct pci_matchid aq_devices[] = {
1001 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1000x00b1 },
1002 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1070x07b1 },
1003 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1080x08b1 },
1004 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1090x09b1 },
1005 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1110x11b1 },
1006 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1120x12b1 },
1007 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1130x04c0 },
1008 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC113C0x14c0 },
1009 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC113CA0x34c0 },
1010 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC113CS0x94c0 },
1011 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC114CS0x93c0 },
1012 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC115C0x12c0 },
1013 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC116C0x11c0 },
1014 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC100S0x80b1 },
1015 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC107S0x87b1 },
1016 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC108S0x88b1 },
1017 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC109S0x89b1 },
1018 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC111S0x91b1 },
1019 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC112S0x92b1 },
1020 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1000xd100 },
1021 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1070xd107 },
1022 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1080xd108 },
1023 { PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1090xd109 },
1024};
1025
1026const struct aq_product {
1027 pci_vendor_id_t aq_vendor;
1028 pci_product_id_t aq_product;
1029 enum aq_hwtype aq_hwtype;
1030 enum aq_media_type aq_media_type;
1031 enum aq_link_speed aq_available_rates;
1032} aq_products[] = {
1033{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1000x00b1, HWTYPE_AQ1,
1034 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
1035},
1036{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1070x07b1, HWTYPE_AQ1,
1037 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
1038},
1039{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1080x08b1, HWTYPE_AQ1,
1040 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1041},
1042{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1090x09b1, HWTYPE_AQ1,
1043 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1044},
1045{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1110x11b1, HWTYPE_AQ1,
1046 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1047},
1048{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1120x12b1, HWTYPE_AQ1,
1049 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1050},
1051{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC100S0x80b1, HWTYPE_AQ1,
1052 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
1053},
1054{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC107S0x87b1, HWTYPE_AQ1,
1055 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
1056},
1057{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC108S0x88b1, HWTYPE_AQ1,
1058 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1059},
1060{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC109S0x89b1, HWTYPE_AQ1,
1061 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1062},
1063{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC111S0x91b1, HWTYPE_AQ1,
1064 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1065},
1066{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC112S0x92b1, HWTYPE_AQ1,
1067 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1068},
1069{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1000xd100, HWTYPE_AQ1,
1070 AQ_MEDIA_TYPE_FIBRE, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
1071},
1072{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1070xd107, HWTYPE_AQ1,
1073 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
)
1074},
1075{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1080xd108, HWTYPE_AQ1,
1076 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1077},
1078{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_D1090xd109, HWTYPE_AQ1,
1079 AQ_MEDIA_TYPE_TP, AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1080},
1081
1082{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC1130x04c0, HWTYPE_AQ2,
1083 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
) | AQ_LINK_10M
1084},
1085{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC113C0x14c0, HWTYPE_AQ2,
1086 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
) | AQ_LINK_10M
1087},
1088{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC113CA0x34c0, HWTYPE_AQ2,
1089 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
) | AQ_LINK_10M
1090},
1091{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC113CS0x94c0, HWTYPE_AQ2,
1092 AQ_MEDIA_TYPE_TP, AQ_LINK_ALL(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
) | AQ_LINK_10M
1093},
1094{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC114CS0x93c0, HWTYPE_AQ2,
1095 AQ_MEDIA_TYPE_TP,
1096 AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G
1097},
1098{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC115C0x12c0, HWTYPE_AQ2,
1099 AQ_MEDIA_TYPE_TP,
1100 AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5
1101},
1102{ PCI_VENDOR_AQUANTIA0x1d6a, PCI_PRODUCT_AQUANTIA_AQC116C0x11c0, HWTYPE_AQ2,
1103 AQ_MEDIA_TYPE_TP, AQ_LINK_10M | AQ_LINK_100M | AQ_LINK_1G
1104},
1105};
1106
1107int aq_match(struct device *, void *, void *);
1108void aq_attach(struct device *, struct device *, void *);
1109int aq_detach(struct device *, int);
1110int aq_activate(struct device *, int);
1111int aq_intr(void *);
1112int aq_intr_link(void *);
1113int aq_intr_queue(void *);
1114int aq_init_rss(struct aq_softc *);
1115int aq_hw_reset(struct aq_softc *);
1116int aq_hw_init(struct aq_softc *, int, int);
1117void aq_hw_qos_set(struct aq_softc *);
1118void aq_l3_filter_set(struct aq_softc *);
1119void aq_hw_init_tx_path(struct aq_softc *);
1120void aq_hw_init_rx_path(struct aq_softc *);
1121int aq_set_mac_addr(struct aq_softc *, int, uint8_t *);
1122int aq_set_linkmode(struct aq_softc *, enum aq_link_speed,
1123 enum aq_link_fc, enum aq_link_eee);
1124void aq_watchdog(struct ifnet *);
1125void aq_enable_intr(struct aq_softc *, int, int);
1126int aq_rxrinfo(struct aq_softc *, struct if_rxrinfo *);
1127int aq_ioctl(struct ifnet *, u_long, caddr_t);
1128int aq_up(struct aq_softc *);
1129void aq_down(struct aq_softc *);
1130void aq_iff(struct aq_softc *);
1131void aq_start(struct ifqueue *);
1132void aq_ifmedia_status(struct ifnet *, struct ifmediareq *);
1133int aq_ifmedia_change(struct ifnet *);
1134void aq_update_link_status(struct aq_softc *);
1135
1136int aq1_fw_reboot(struct aq_softc *);
1137int aq1_fw_read_version(struct aq_softc *);
1138int aq1_fw_version_init(struct aq_softc *);
1139int aq1_hw_init_ucp(struct aq_softc *);
1140void aq1_global_software_reset(struct aq_softc *);
1141int aq1_mac_soft_reset(struct aq_softc *, enum aq_fw_bootloader_mode *);
1142int aq1_mac_soft_reset_rbl(struct aq_softc *, enum aq_fw_bootloader_mode *);
1143int aq1_mac_soft_reset_flb(struct aq_softc *);
1144int aq1_fw_downld_dwords(struct aq_softc *, uint32_t, uint32_t *, uint32_t);
1145
1146int aq2_interface_buffer_read(struct aq_softc *, uint32_t, uint32_t *,
1147 uint32_t);
1148int aq2_fw_reboot(struct aq_softc *);
1149int aq2_filter_art_set(struct aq_softc *, uint32_t, uint32_t, uint32_t,
1150 uint32_t action);
1151
1152void aq_refill(void *);
1153int aq_rx_fill(struct aq_softc *, struct aq_rxring *);
1154static inline unsigned int aq_rx_fill_slots(struct aq_softc *,
1155 struct aq_rxring *, uint);
1156
1157int aq_dmamem_alloc(struct aq_softc *, struct aq_dmamem *,
1158 bus_size_t, u_int);
1159void aq_dmamem_zero(struct aq_dmamem *);
1160void aq_dmamem_free(struct aq_softc *, struct aq_dmamem *);
1161
1162int aq1_get_mac_addr(struct aq_softc *);
1163
1164int aq_fw1x_reset(struct aq_softc *);
1165int aq_fw1x_get_mode(struct aq_softc *, enum aq_hw_fw_mpi_state *,
1166 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *);
1167int aq_fw1x_set_mode(struct aq_softc *, enum aq_hw_fw_mpi_state,
1168 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee);
1169int aq_fw1x_get_stats(struct aq_softc *, struct aq_hw_stats_s *);
1170
1171int aq_fw2x_reset(struct aq_softc *);
1172int aq_fw2x_get_mode(struct aq_softc *, enum aq_hw_fw_mpi_state *,
1173 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *);
1174int aq_fw2x_set_mode(struct aq_softc *, enum aq_hw_fw_mpi_state,
1175 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee);
1176int aq_fw2x_get_stats(struct aq_softc *, struct aq_hw_stats_s *);
1177
1178int aq2_fw_reset(struct aq_softc *);
1179int aq2_get_mac_addr(struct aq_softc *);
1180int aq2_fw_get_mode(struct aq_softc *, enum aq_hw_fw_mpi_state *,
1181 enum aq_link_speed *, enum aq_link_fc *, enum aq_link_eee *);
1182int aq2_fw_set_mode(struct aq_softc *, enum aq_hw_fw_mpi_state,
1183 enum aq_link_speed, enum aq_link_fc, enum aq_link_eee);
1184int aq2_fw_get_stats(struct aq_softc *, struct aq_hw_stats_s *);
1185
1186const struct aq_firmware_ops aq_fw1x_ops = {
1187 .reset = aq_fw1x_reset,
1188 .get_mac_addr = aq1_get_mac_addr,
1189 .set_mode = aq_fw1x_set_mode,
1190 .get_mode = aq_fw1x_get_mode,
1191 .get_stats = aq_fw1x_get_stats,
1192};
1193
1194const struct aq_firmware_ops aq_fw2x_ops = {
1195 .reset = aq_fw2x_reset,
1196 .get_mac_addr = aq1_get_mac_addr,
1197 .set_mode = aq_fw2x_set_mode,
1198 .get_mode = aq_fw2x_get_mode,
1199 .get_stats = aq_fw2x_get_stats,
1200};
1201
1202const struct aq_firmware_ops aq2_fw_ops = {
1203 .reset = aq2_fw_reset,
1204 .get_mac_addr = aq2_get_mac_addr,
1205 .set_mode = aq2_fw_set_mode,
1206 .get_mode = aq2_fw_get_mode,
1207 .get_stats = aq2_fw_get_stats
1208};
1209
1210const struct cfattach aq_ca = {
1211 sizeof(struct aq_softc), aq_match, aq_attach, NULL((void *)0),
1212 aq_activate
1213};
1214
1215struct cfdriver aq_cd = {
1216 NULL((void *)0), "aq", DV_IFNET
1217};
1218
1219int
1220aq_match(struct device *dev, void *match, void *aux)
1221{
1222 return pci_matchbyid((struct pci_attach_args *)aux, aq_devices,
1223 sizeof(aq_devices) / sizeof(aq_devices[0]));
1224}
1225
1226const struct aq_product *
1227aq_lookup(const struct pci_attach_args *pa)
1228{
1229 unsigned int i;
1230
1231 for (i = 0; i < sizeof(aq_products) / sizeof(aq_products[0]); i++) {
1232 if (PCI_VENDOR(pa->pa_id)(((pa->pa_id) >> 0) & 0xffff) == aq_products[i].aq_vendor &&
1233 PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff) == aq_products[i].aq_product) {
1234 return &aq_products[i];
1235 }
1236 }
1237
1238 return NULL((void *)0);
1239}
1240
1241void
1242aq_attach(struct device *parent, struct device *self, void *aux)
1243{
1244 struct aq_softc *sc = (struct aq_softc *)self;
1245 struct pci_attach_args *pa = aux;
1246 const struct aq_product *aqp;
1247 pcireg_t bar, memtype;
1248 pci_chipset_tag_t pc;
1249 pci_intr_handle_t ih;
1250 int (*isr)(void *);
1251 const char *intrstr;
1252 pcitag_t tag;
1253 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1254 int txmin, txmax, rxmin, rxmax;
1255 int irqmode, irqnum;
1256 int i;
1257
1258 mtx_init(&sc->sc_mpi_mutex, IPL_NET)do { (void)(((void *)0)); (void)(0); __mtx_init((&sc->
sc_mpi_mutex), ((((0x4)) > 0x0 && ((0x4)) < 0x9
) ? 0x9 : ((0x4)))); } while (0);
1259
1260 sc->sc_dmat = pa->pa_dmat;
1261 sc->sc_pc = pc = pa->pa_pc;
1262 sc->sc_pcitag = tag = pa->pa_tag;
1263
1264 sc->sc_product = PCI_PRODUCT(pa->pa_id)(((pa->pa_id) >> 16) & 0xffff);
1265 sc->sc_revision = PCI_REVISION(pa->pa_class)(((pa->pa_class) >> 0) & 0xff);
1266
1267 aqp = aq_lookup(pa);
1268
1269 bar = pci_conf_read(pc, tag, AQ_BAR00x10);
1270 if (PCI_MAPREG_TYPE(bar)((bar) & 0x00000001) != PCI_MAPREG_TYPE_MEM0x00000000) {
1271 printf(": wrong BAR type\n");
1272 return;
1273 }
1274
1275 memtype = pci_mapreg_type(pc, tag, AQ_BAR00x10);
1276 if (pci_mapreg_map(pa, AQ_BAR00x10, memtype, 0, &sc->sc_iot, &sc->sc_ioh,
1277 NULL((void *)0), NULL((void *)0), 0)) {
1278 printf(": failed to map BAR0\n");
1279 return;
1280 }
1281
1282 sc->sc_nqueues = 1;
1283 sc->sc_linkstat_irq = AQ_LINKSTAT_IRQ31;
1284 isr = aq_intr;
1285 irqnum = 0;
1286
1287 if (pci_intr_map_msix(pa, 0, &ih) == 0) {
1288 int nmsix = pci_intr_msix_count(pa);
1289 /* don't do rss on aq2 yet */
1290 if (aqp->aq_hwtype == HWTYPE_AQ1 && nmsix > 1) {
1291 nmsix--;
1292 sc->sc_intrmap = intrmap_create(&sc->sc_dev,
1293 nmsix, AQ_MAXQ8, INTRMAP_POWEROF2(1 << 0));
1294 sc->sc_nqueues = intrmap_count(sc->sc_intrmap);
1295 KASSERT(sc->sc_nqueues > 0)((sc->sc_nqueues > 0) ? (void)0 : __assert("diagnostic "
, "/usr/src/sys/dev/pci/if_aq_pci.c", 1295, "sc->sc_nqueues > 0"
));
1296 KASSERT(powerof2(sc->sc_nqueues))((((((sc->sc_nqueues)-1)&(sc->sc_nqueues))==0)) ? (
void)0 : __assert("diagnostic ", "/usr/src/sys/dev/pci/if_aq_pci.c"
, 1296, "powerof2(sc->sc_nqueues)"));
1297
1298 sc->sc_linkstat_irq = 0;
1299 isr = aq_intr_link;
1300 irqnum++;
1301 }
1302 irqmode = AQ_INTR_CTRL_IRQMODE_MSIX2;
1303 } else if (pci_intr_map_msi(pa, &ih) == 0) {
1304 irqmode = AQ_INTR_CTRL_IRQMODE_MSI1;
1305 } else if (pci_intr_map(pa, &ih) == 0) {
1306 irqmode = AQ_INTR_CTRL_IRQMODE_LEGACY0;
1307 } else {
1308 printf(": failed to map interrupt\n");
1309 return;
1310 }
1311
1312 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih,
1313 IPL_NET0x4 | IPL_MPSAFE0x100, isr, sc, self->dv_xname);
1314 intrstr = pci_intr_string(pa->pa_pc, ih);
1315 if (intrstr)
1316 printf(": %s", intrstr);
1317
1318 if (sc->sc_nqueues > 1)
1319 printf(", %d queues", sc->sc_nqueues);
1320
1321 switch (aqp->aq_hwtype) {
1322 case HWTYPE_AQ1:
1323 if (aq1_fw_reboot(sc))
1324 return;
1325 break;
1326 case HWTYPE_AQ2:
1327 if (aq2_fw_reboot(sc))
1328 return;
1329 break;
1330 default:
1331 return;
1332 }
1333
1334 if (aq_hw_reset(sc))
1335 return;
1336
1337 if (sc->sc_fw_ops->get_mac_addr(sc))
1338 return;
1339 printf(", address %s", ether_sprintf(sc->sc_enaddr.ether_addr_octet));
1340
1341 if (aq_init_rss(sc))
1342 return;
1343
1344 if (aq_hw_init(sc, irqmode, (sc->sc_nqueues > 1)))
1345 return;
1346
1347 sc->sc_media_type = aqp->aq_media_type;
1348 sc->sc_available_rates = aqp->aq_available_rates;
1349
1350 ifmedia_init(&sc->sc_media, IFM_IMASK0xff00000000000000ULL, aq_ifmedia_change,
1351 aq_ifmedia_status);
1352
1353 bcopy(sc->sc_enaddr.ether_addr_octet, sc->sc_arpcom.ac_enaddr, 6);
1354 strlcpy(ifp->if_xname, self->dv_xname, IFNAMSIZ16);
1355 ifp->if_softc = sc;
1356 ifp->if_flags = IFF_BROADCAST0x2 | IFF_MULTICAST0x8000 | IFF_SIMPLEX0x800;
1357 ifp->if_xflags = IFXF_MPSAFE0x1;
1358 ifp->if_ioctl = aq_ioctl;
1359 ifp->if_qstart = aq_start;
1360 ifp->if_watchdog = aq_watchdog;
1361 ifp->if_hardmtu = 9000;
1362 ifp->if_capabilitiesif_data.ifi_capabilities = IFCAP_VLAN_MTU0x00000010 | IFCAP_CSUM_IPv40x00000001 |
1363 IFCAP_CSUM_UDPv40x00000004 | IFCAP_CSUM_UDPv60x00000100 | IFCAP_CSUM_TCPv40x00000002 |
1364 IFCAP_CSUM_TCPv60x00000080;
1365#if NVLAN1 > 0
1366 ifp->if_capabilitiesif_data.ifi_capabilities |= IFCAP_VLAN_HWTAGGING0x00000020;
1367#endif
1368 ifq_init_maxlen(&ifp->if_snd, AQ_TXD_NUM2048);
1369
1370 ifmedia_init(&sc->sc_media, IFM_IMASK0xff00000000000000ULL, aq_ifmedia_change,
1371 aq_ifmedia_status);
1372 if (sc->sc_available_rates & AQ_LINK_10M) {
1373 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL|IFM_10_T3, 0, NULL((void *)0));
1374 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL|IFM_10_T3|IFM_FDX0x0000010000000000ULL, 0,
1375 NULL((void *)0));
1376 }
1377
1378 if (sc->sc_available_rates & AQ_LINK_100M) {
1379 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL|IFM_100_TX6, 0, NULL((void *)0));
1380 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL|IFM_100_TX6|IFM_FDX0x0000010000000000ULL, 0,
1381 NULL((void *)0));
1382 }
1383
1384 if (sc->sc_available_rates & AQ_LINK_1G) {
1385 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL|IFM_1000_T16, 0, NULL((void *)0));
1386 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL|IFM_1000_T16|IFM_FDX0x0000010000000000ULL, 0,
1387 NULL((void *)0));
1388 }
1389
1390 if (sc->sc_available_rates & AQ_LINK_2G5) {
1391 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34, 0, NULL((void *)0));
1392 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_2500_T34 | IFM_FDX0x0000010000000000ULL,
1393 0, NULL((void *)0));
1394 }
1395
1396 if (sc->sc_available_rates & AQ_LINK_5G) {
1397 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_5000_T35, 0, NULL((void *)0));
1398 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_5000_T35 | IFM_FDX0x0000010000000000ULL,
1399 0, NULL((void *)0));
1400 }
1401
1402 if (sc->sc_available_rates & AQ_LINK_10G) {
1403 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_10G_T22, 0, NULL((void *)0));
1404 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_10G_T22 | IFM_FDX0x0000010000000000ULL,
1405 0, NULL((void *)0));
1406 }
1407
1408 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL, 0, NULL((void *)0));
1409 ifmedia_add(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL | IFM_FDX0x0000010000000000ULL, 0, NULL((void *)0));
1410 ifmedia_set(&sc->sc_media, IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL);
1411 aq_set_linkmode(sc, AQ_LINK_AUTO(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
), AQ_FC_NONE, AQ_EEE_DISABLE);
1412
1413 if_attach(ifp);
1414 ether_ifattach(ifp);
1415
1416 if_attach_iqueues(ifp, sc->sc_nqueues);
1417 if_attach_queues(ifp, sc->sc_nqueues);
1418
1419 /*
1420 * set interrupt moderation for up to 20k interrupts per second,
1421 * more rx than tx. these values are in units of 2us.
1422 */
1423 txmin = 20;
1424 txmax = 200;
1425 rxmin = 6;
1426 rxmax = 60;
1427
1428 for (i = 0; i < sc->sc_nqueues; i++) {
1429 struct aq_queues *aq = &sc->sc_queues[i];
1430 struct aq_rxring *rx = &aq->q_rx;
1431 struct aq_txring *tx = &aq->q_tx;
1432 pci_intr_handle_t ih;
1433
1434 aq->q_sc = sc;
1435 aq->q_index = i;
1436 rx->rx_q = i;
1437 rx->rx_ifiq = ifp->if_iqs[i];
1438 rx->rx_m_head = NULL((void *)0);
1439 rx->rx_m_tail = &rx->rx_m_head;
1440 rx->rx_m_error = 0;
1441 ifp->if_iqs[i]->ifiq_softc_ifiq_ptr._ifiq_softc = aq;
1442 timeout_set(&rx->rx_refill, aq_refill, rx);
1443
1444 tx->tx_q = i;
1445 tx->tx_ifq = ifp->if_ifqs[i];
1446 ifp->if_ifqs[i]->ifq_softc_ifq_ptr._ifq_softc = aq;
1447
1448 snprintf(aq->q_name, sizeof(aq->q_name), "%s:%u",
1449 DEVNAME(sc)((sc)->sc_dev.dv_xname), i);
1450
1451 if (sc->sc_nqueues > 1) {
1452 if (pci_intr_map_msix(pa, irqnum, &ih)) {
1453 printf(": unable to map msi-x vector %d\n",
1454 irqnum);
1455 return;
1456 }
1457
1458 aq->q_ihc = pci_intr_establish_cpu(sc->sc_pc, ih,
1459 IPL_NET0x4 | IPL_MPSAFE0x100, intrmap_cpu(sc->sc_intrmap, i),
1460 aq_intr_queue, aq, aq->q_name);
1461 if (aq->q_ihc == NULL((void *)0)) {
1462 printf(": unable to establish interrupt %d\n",
1463 irqnum);
1464 return;
1465 }
1466 rx->rx_irq = irqnum;
1467 tx->tx_irq = irqnum;
1468 irqnum++;
1469 } else {
1470 rx->rx_irq = irqnum++;
1471 tx->tx_irq = irqnum++;
1472 }
1473
1474 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
1475 AQ_WRITE_REG_BIT(sc, AQ2_TX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c28 + (i) * 0x40)))))); _v &= ~(0x0000ff00
); if ((txmin) != 0) _v |= (((txmin)) * (((((uint32_t)(0x0000ff00
)) - 1) & ((uint32_t)(0x0000ff00))) ^ ((uint32_t)(0x0000ff00
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7c28 + (i) * 0x40)))), ((_v)))); } while ( 0)
1476 AQ2_TX_INTR_MODERATION_CTL_MIN, txmin)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c28 + (i) * 0x40)))))); _v &= ~(0x0000ff00
); if ((txmin) != 0) _v |= (((txmin)) * (((((uint32_t)(0x0000ff00
)) - 1) & ((uint32_t)(0x0000ff00))) ^ ((uint32_t)(0x0000ff00
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7c28 + (i) * 0x40)))), ((_v)))); } while ( 0);
1477 AQ_WRITE_REG_BIT(sc, AQ2_TX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c28 + (i) * 0x40)))))); _v &= ~(0x01ff0000
); if ((txmax) != 0) _v |= (((txmax)) * (((((uint32_t)(0x01ff0000
)) - 1) & ((uint32_t)(0x01ff0000))) ^ ((uint32_t)(0x01ff0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7c28 + (i) * 0x40)))), ((_v)))); } while ( 0)
1478 AQ2_TX_INTR_MODERATION_CTL_MAX, txmax)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c28 + (i) * 0x40)))))); _v &= ~(0x01ff0000
); if ((txmax) != 0) _v |= (((txmax)) * (((((uint32_t)(0x01ff0000
)) - 1) & ((uint32_t)(0x01ff0000))) ^ ((uint32_t)(0x01ff0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7c28 + (i) * 0x40)))), ((_v)))); } while ( 0);
1479 AQ_WRITE_REG_BIT(sc, AQ2_TX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c28 + (i) * 0x40)))))); _v &= ~((1 <<
1)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1 <<
1))) - 1) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)(
(1 << 1))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), ((((0x7c28 + (i) * 0x40)))), ((_v)))); } while ( 0)
1480 AQ2_TX_INTR_MODERATION_CTL_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c28 + (i) * 0x40)))))); _v &= ~((1 <<
1)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1 <<
1))) - 1) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)(
(1 << 1))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), ((((0x7c28 + (i) * 0x40)))), ((_v)))); } while ( 0);
1481 } else {
1482 AQ_WRITE_REG_BIT(sc, TX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8980 + (i) * 4)))))); _v &= ~((0xFF <<
8)); if ((txmin) != 0) _v |= (((txmin)) * (((((uint32_t)((0xFF
<< 8))) - 1) & ((uint32_t)((0xFF << 8)))) ^ (
(uint32_t)((0xFF << 8))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x8980 + (i) * 4)))), ((_v)))); } while
( 0)
1483 TX_INTR_MODERATION_CTL_MIN, txmin)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8980 + (i) * 4)))))); _v &= ~((0xFF <<
8)); if ((txmin) != 0) _v |= (((txmin)) * (((((uint32_t)((0xFF
<< 8))) - 1) & ((uint32_t)((0xFF << 8)))) ^ (
(uint32_t)((0xFF << 8))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x8980 + (i) * 4)))), ((_v)))); } while
( 0);
1484 AQ_WRITE_REG_BIT(sc, TX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8980 + (i) * 4)))))); _v &= ~((0x1FF
<< 16)); if ((txmax) != 0) _v |= (((txmax)) * (((((uint32_t
)((0x1FF << 16))) - 1) & ((uint32_t)((0x1FF <<
16)))) ^ ((uint32_t)((0x1FF << 16))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x8980 + (i) * 4)))), (
(_v)))); } while ( 0)
1485 TX_INTR_MODERATION_CTL_MAX, txmax)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8980 + (i) * 4)))))); _v &= ~((0x1FF
<< 16)); if ((txmax) != 0) _v |= (((txmax)) * (((((uint32_t
)((0x1FF << 16))) - 1) & ((uint32_t)((0x1FF <<
16)))) ^ ((uint32_t)((0x1FF << 16))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x8980 + (i) * 4)))), (
(_v)))); } while ( 0);
1486 AQ_WRITE_REG_BIT(sc, TX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8980 + (i) * 4)))))); _v &= ~((1 <<
1)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1 <<
1))) - 1) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)(
(1 << 1))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), ((((0x8980 + (i) * 4)))), ((_v)))); } while ( 0)
1487 TX_INTR_MODERATION_CTL_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8980 + (i) * 4)))))); _v &= ~((1 <<
1)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1 <<
1))) - 1) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)(
(1 << 1))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), ((((0x8980 + (i) * 4)))), ((_v)))); } while ( 0);
1488 }
1489 AQ_WRITE_REG_BIT(sc, RX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5a40 + (i) * 4)))))); _v &= ~((0xFF <<
8)); if ((rxmin) != 0) _v |= (((rxmin)) * (((((uint32_t)((0xFF
<< 8))) - 1) & ((uint32_t)((0xFF << 8)))) ^ (
(uint32_t)((0xFF << 8))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5a40 + (i) * 4)))), ((_v)))); } while
( 0)
1490 RX_INTR_MODERATION_CTL_MIN, rxmin)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5a40 + (i) * 4)))))); _v &= ~((0xFF <<
8)); if ((rxmin) != 0) _v |= (((rxmin)) * (((((uint32_t)((0xFF
<< 8))) - 1) & ((uint32_t)((0xFF << 8)))) ^ (
(uint32_t)((0xFF << 8))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5a40 + (i) * 4)))), ((_v)))); } while
( 0);
1491 AQ_WRITE_REG_BIT(sc, RX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5a40 + (i) * 4)))))); _v &= ~((0x1FF
<< 16)); if ((rxmax) != 0) _v |= (((rxmax)) * (((((uint32_t
)((0x1FF << 16))) - 1) & ((uint32_t)((0x1FF <<
16)))) ^ ((uint32_t)((0x1FF << 16))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x5a40 + (i) * 4)))), (
(_v)))); } while ( 0)
1492 RX_INTR_MODERATION_CTL_MAX, rxmax)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5a40 + (i) * 4)))))); _v &= ~((0x1FF
<< 16)); if ((rxmax) != 0) _v |= (((rxmax)) * (((((uint32_t
)((0x1FF << 16))) - 1) & ((uint32_t)((0x1FF <<
16)))) ^ ((uint32_t)((0x1FF << 16))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x5a40 + (i) * 4)))), (
(_v)))); } while ( 0);
1493 AQ_WRITE_REG_BIT(sc, RX_INTR_MODERATION_CTL_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5a40 + (i) * 4)))))); _v &= ~((1 <<
1)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1 <<
1))) - 1) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)(
(1 << 1))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), ((((0x5a40 + (i) * 4)))), ((_v)))); } while ( 0)
1494 RX_INTR_MODERATION_CTL_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5a40 + (i) * 4)))))); _v &= ~((1 <<
1)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1 <<
1))) - 1) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)(
(1 << 1))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), ((((0x5a40 + (i) * 4)))), ((_v)))); } while ( 0);
1495 }
1496
1497 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7b40))))); _v &= ~((1 << 1)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 1))) - 1
) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)((1 <<
1))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7b40))), ((_v)))); } while ( 0)
1498 TX_DMA_INT_DESC_WRWB_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7b40))))); _v &= ~((1 << 1)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 1))) - 1
) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)((1 <<
1))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7b40))), ((_v)))); } while ( 0);
1499 AQ_WRITE_REG_BIT(sc, TX_DMA_INT_DESC_WRWB_EN_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7b40))))); _v &= ~((1 << 4)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 4))) - 1
) & ((uint32_t)((1 << 4)))) ^ ((uint32_t)((1 <<
4))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7b40))), ((_v)))); } while ( 0)
1500 TX_DMA_INT_DESC_MODERATE_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7b40))))); _v &= ~((1 << 4)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 4))) - 1
) & ((uint32_t)((1 << 4)))) ^ ((uint32_t)((1 <<
4))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7b40))), ((_v)))); } while ( 0);
1501 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5a30))))); _v &= ~((1 << 2)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 2))) - 1
) & ((uint32_t)((1 << 2)))) ^ ((uint32_t)((1 <<
2))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5a30))), ((_v)))); } while ( 0)
1502 RX_DMA_INT_DESC_WRWB_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5a30))))); _v &= ~((1 << 2)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 2))) - 1
) & ((uint32_t)((1 << 2)))) ^ ((uint32_t)((1 <<
2))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5a30))), ((_v)))); } while ( 0);
1503 AQ_WRITE_REG_BIT(sc, RX_DMA_INT_DESC_WRWB_EN_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5a30))))); _v &= ~((1 << 3)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 3))) - 1
) & ((uint32_t)((1 << 3)))) ^ ((uint32_t)((1 <<
3))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5a30))), ((_v)))); } while ( 0)
1504 RX_DMA_INT_DESC_MODERATE_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5a30))))); _v &= ~((1 << 3)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 3))) - 1
) & ((uint32_t)((1 << 3)))) ^ ((uint32_t)((1 <<
3))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5a30))), ((_v)))); } while ( 0);
1505
1506 aq_enable_intr(sc, 1, 0);
1507 printf("\n");
1508}
1509
1510int
1511aq1_fw_reboot(struct aq_softc *sc)
1512{
1513 uint32_t ver, v, boot_exit_code;
1514 int i, error;
1515 enum aq_fw_bootloader_mode mode;
1516
1517 mode = FW_BOOT_MODE_UNKNOWN;
1518
1519 ver = AQ_READ_REG(sc, AQ_FW_VERSION_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0018))));
1520
1521 for (i = 1000; i > 0; i--) {
1522 v = AQ_READ_REG(sc, FW_MPI_DAISY_CHAIN_STATUS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0704))));
1523 boot_exit_code = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0388))));
1524 if (v != 0x06000000 || boot_exit_code != 0)
1525 break;
1526 }
1527
1528 if (i <= 0) {
1529 printf(": F/W reset failed. Neither RBL nor FLB started");
1530 return ETIMEDOUT60;
1531 }
1532
1533 sc->sc_rbl_enabled = (boot_exit_code != 0);
1534
1535 /*
1536 * Having FW version 0 is an indicator that cold start
1537 * is in progress. This means two things:
1538 * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
1539 * 2) Driver may skip reset sequence and save time.
1540 */
1541 if (sc->sc_fast_start_enabled && (ver != 0)) {
1542 if (aq1_fw_read_version(sc) == 0)
1543 goto faststart;
1544 }
1545
1546 error = aq1_mac_soft_reset(sc, &mode);
1547 if (error != 0) {
1548 printf("%s: MAC reset failed: %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), error);
1549 return error;
1550 }
1551
1552 switch (mode) {
1553 case FW_BOOT_MODE_FLB:
1554 DPRINTF(("%s: FLB> F/W successfully loaded from flash.",
1555 DEVNAME(sc)));
1556 sc->sc_flash_present = 1;
1557 break;
1558 case FW_BOOT_MODE_RBL_FLASH:
1559 DPRINTF(("%s: RBL> F/W loaded from flash. Host Bootload "
1560 "disabled.", DEVNAME(sc)));
1561 sc->sc_flash_present = 1;
1562 break;
1563 case FW_BOOT_MODE_UNKNOWN:
1564 printf("%s: F/W bootload error: unknown bootloader type",
1565 DEVNAME(sc)((sc)->sc_dev.dv_xname));
1566 return ENOTSUP91;
1567 case FW_BOOT_MODE_RBL_HOST_BOOTLOAD:
1568 printf("%s: RBL> F/W Host Bootload not implemented", DEVNAME(sc)((sc)->sc_dev.dv_xname));
1569 return ENOTSUP91;
1570 }
1571
1572 faststart:
1573 error = aq1_fw_read_version(sc);
1574 if (error != 0)
1575 return error;
1576
1577 error = aq1_fw_version_init(sc);
1578 if (error != 0)
1579 return error;
1580
1581 return aq1_hw_init_ucp(sc);
1582}
1583
1584int
1585aq1_mac_soft_reset_rbl(struct aq_softc *sc, enum aq_fw_bootloader_mode *mode)
1586{
1587 int timo;
1588
1589 DPRINTF(("%s: RBL> MAC reset STARTED!\n", DEVNAME(sc)));
1590
1591 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0404)),
((0x40e1))));
1592 AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x03a0 +
(0) * 4))), ((1))));
1593 AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x32a8)),
((0))));
1594
1595 /* MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone */
1596 AQ_WRITE_REG(sc, FW_BOOT_EXIT_CODE_REG, RBL_STATUS_DEAD)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0388)),
((0x0000dead))));
1597
1598 aq1_global_software_reset(sc);
1599
1600 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0404)),
((0x40e0))));
1601
1602 /* Wait for RBL to finish boot process. */
1603#define RBL_TIMEOUT_MS10000 10000
1604 uint16_t rbl_status;
1605 for (timo = RBL_TIMEOUT_MS10000; timo > 0; timo--) {
1606 rbl_status = AQ_READ_REG(sc, FW_BOOT_EXIT_CODE_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0388)))) & 0xffff;
1607 if (rbl_status != 0 && rbl_status != RBL_STATUS_DEAD0x0000dead)
1608 break;
1609 delay(1000)(*delay_func)(1000);
1610 }
1611
1612 if (timo <= 0) {
1613 printf("%s: RBL> RBL restart failed: timeout\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
1614 return EBUSY16;
1615 }
1616
1617 switch (rbl_status) {
1618 case RBL_STATUS_SUCCESS0x0000abba:
1619 if (mode != NULL((void *)0))
1620 *mode = FW_BOOT_MODE_RBL_FLASH;
1621 DPRINTF(("%s: RBL> reset complete! [Flash]\n", DEVNAME(sc)));
1622 break;
1623 case RBL_STATUS_HOST_BOOT0x0000f1a7:
1624 if (mode != NULL((void *)0))
1625 *mode = FW_BOOT_MODE_RBL_HOST_BOOTLOAD;
1626 DPRINTF(("%s: RBL> reset complete! [Host Bootload]\n",
1627 DEVNAME(sc)));
1628 break;
1629 case RBL_STATUS_FAILURE0x00000bad:
1630 default:
1631 printf("%s: unknown RBL status 0x%x\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
1632 rbl_status);
1633 return EBUSY16;
1634 }
1635
1636 return 0;
1637}
1638
1639int
1640aq1_mac_soft_reset_flb(struct aq_softc *sc)
1641{
1642 uint32_t v;
1643 int timo;
1644
1645 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x40e1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0404)),
((0x40e1))));
1646 /*
1647 * Let Felicity hardware to complete SMBUS transaction before
1648 * Global software reset.
1649 */
1650 delay(50000)(*delay_func)(50000);
1651
1652 /*
1653 * If SPI burst transaction was interrupted(before running the script),
1654 * global software reset may not clear SPI interface.
1655 * Clean it up manually before global reset.
1656 */
1657 AQ_WRITE_REG(sc, AQ_GLB_NVR_PROVISIONING2_REG, 0x00a0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0534)),
((0x00a0))));
1658 AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x009f)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0100)),
((0x009f))));
1659 AQ_WRITE_REG(sc, AQ_GLB_NVR_INTERFACE1_REG, 0x809f)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0100)),
((0x809f))));
1660 delay(50000)(*delay_func)(50000);
1661
1662 v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0000))));
1663 v &= ~AQ_FW_SOFTRESET_DIS(1 << 14);
1664 v |= AQ_FW_SOFTRESET_RESET(1 << 15);
1665 AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0000)),
((v))));
1666
1667 /* Kickstart. */
1668 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0404)),
((0x80e0))));
1669 AQ_WRITE_REG(sc, AQ_MBOXIF_POWER_GATING_CONTROL_REG, 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x32a8)),
((0))));
1670 if (!sc->sc_fast_start_enabled)
1671 AQ_WRITE_REG(sc, AQ_GLB_GENERAL_PROVISIONING9_REG, 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0520)),
((1))));
1672
1673 /*
1674 * For the case SPI burst transaction was interrupted (by MCP reset
1675 * above), wait until it is completed by hardware.
1676 */
1677 delay(50000)(*delay_func)(50000);
1678
1679 /* MAC Kickstart */
1680 if (!sc->sc_fast_start_enabled) {
1681 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x180e0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0404)),
((0x180e0))));
1682
1683 uint32_t flb_status;
1684 for (timo = 0; timo < 1000; timo++) {
1685 flb_status = AQ_READ_REG(sc,(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0704))))
1686 FW_MPI_DAISY_CHAIN_STATUS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0704)))) & 0x10;
1687 if (flb_status != 0)
1688 break;
1689 delay(1000)(*delay_func)(1000);
1690 }
1691 if (flb_status == 0) {
1692 printf("%s: FLB> MAC kickstart failed: timed out\n",
1693 DEVNAME(sc)((sc)->sc_dev.dv_xname));
1694 return ETIMEDOUT60;
1695 }
1696 DPRINTF(("%s: FLB> MAC kickstart done, %d ms\n", DEVNAME(sc),
1697 timo));
1698 /* FW reset */
1699 AQ_WRITE_REG(sc, AQ_FW_GLB_CTL2_REG, 0x80e0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0404)),
((0x80e0))));
1700 /*
1701 * Let Felicity hardware complete SMBUS transaction before
1702 * Global software reset.
1703 */
1704 delay(50000)(*delay_func)(50000);
1705 sc->sc_fast_start_enabled = true1;
1706 }
1707 AQ_WRITE_REG(sc, AQ_FW_GLB_CPU_SEM_REG(0), 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x03a0 +
(0) * 4))), ((1))));
1708
1709 /* PHY Kickstart: #undone */
1710 aq1_global_software_reset(sc);
1711
1712 for (timo = 0; timo < 1000; timo++) {
1713 if (AQ_READ_REG(sc, AQ_FW_VERSION_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0018)))) != 0)
1714 break;
1715 delay(10000)(*delay_func)(10000);
1716 }
1717 if (timo >= 1000) {
1718 printf("%s: FLB> Global Soft Reset failed\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
1719 return ETIMEDOUT60;
1720 }
1721 DPRINTF(("%s: FLB> F/W restart: %d ms\n", DEVNAME(sc), timo * 10));
1722
1723 return 0;
1724
1725}
1726
1727int
1728aq1_mac_soft_reset(struct aq_softc *sc, enum aq_fw_bootloader_mode *mode)
1729{
1730 if (sc->sc_rbl_enabled)
1731 return aq1_mac_soft_reset_rbl(sc, mode);
1732
1733 if (mode != NULL((void *)0))
1734 *mode = FW_BOOT_MODE_FLB;
1735 return aq1_mac_soft_reset_flb(sc);
1736}
1737
1738void
1739aq1_global_software_reset(struct aq_softc *sc)
1740{
1741 uint32_t v;
1742
1743 AQ_WRITE_REG_BIT(sc, RX_SYSCONTROL_REG, RX_SYSCONTROL_RESET_DIS, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5000))))); _v &= ~((1 << 29)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 29))) -
1) & ((uint32_t)((1 << 29)))) ^ ((uint32_t)((1 <<
29))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5000))), ((_v)))); } while ( 0);
1744 AQ_WRITE_REG_BIT(sc, TX_SYSCONTROL_REG, TX_SYSCONTROL_RESET_DIS, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7000))))); _v &= ~((1 << 29)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 29))) -
1) & ((uint32_t)((1 << 29)))) ^ ((uint32_t)((1 <<
29))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x7000))), ((_v)))); } while ( 0);
1745 AQ_WRITE_REG_BIT(sc, FW_MPI_RESETCTRL_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x4000))))); _v &= ~((1 << 29)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 29))) -
1) & ((uint32_t)((1 << 29)))) ^ ((uint32_t)((1 <<
29))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x4000))), ((_v)))); } while ( 0)
1746 FW_MPI_RESETCTRL_RESET_DIS, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x4000))))); _v &= ~((1 << 29)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 29))) -
1) & ((uint32_t)((1 << 29)))) ^ ((uint32_t)((1 <<
29))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x4000))), ((_v)))); } while ( 0);
1747
1748 v = AQ_READ_REG(sc, AQ_FW_SOFTRESET_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0000))));
1749 v &= ~AQ_FW_SOFTRESET_DIS(1 << 14);
1750 v |= AQ_FW_SOFTRESET_RESET(1 << 15);
1751 AQ_WRITE_REG(sc, AQ_FW_SOFTRESET_REG, v)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0000)),
((v))));
1752}
1753
1754int
1755aq1_fw_read_version(struct aq_softc *sc)
1756{
1757 int i, error = EBUSY16;
1758#define MAC_FW_START_TIMEOUT_MS10000 10000
1759 for (i = 0; i < MAC_FW_START_TIMEOUT_MS10000; i++) {
1760 sc->sc_fw_version = AQ_READ_REG(sc, AQ_FW_VERSION_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0018))));
1761 if (sc->sc_fw_version != 0) {
1762 error = 0;
1763 break;
1764 }
1765 delay(1000)(*delay_func)(1000);
1766 }
1767 return error;
1768}
1769
1770int
1771aq1_fw_version_init(struct aq_softc *sc)
1772{
1773 int error = 0;
1774 char fw_vers[sizeof("F/W version xxxxx.xxxxx.xxxxx")];
1775
1776 if (FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff) == 1) {
1777 sc->sc_fw_ops = &aq_fw1x_ops;
1778 } else if ((FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff) == 2) || (FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff) == 3)) {
1779 sc->sc_fw_ops = &aq_fw2x_ops;
1780 } else {
1781 printf(": Unsupported F/W version %d.%d.%d\n",
1782 FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff), FW_VERSION_MINOR(sc)(((sc)->sc_fw_version >> 16) & 0xff),
1783 FW_VERSION_BUILD(sc)((sc)->sc_fw_version & 0xffff));
1784 return ENOTSUP91;
1785 }
1786 snprintf(fw_vers, sizeof(fw_vers), "F/W version %d.%d.%d",
1787 FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff), FW_VERSION_MINOR(sc)(((sc)->sc_fw_version >> 16) & 0xff), FW_VERSION_BUILD(sc)((sc)->sc_fw_version & 0xffff));
1788
1789 /* detect revision */
1790 uint32_t hwrev = AQ_READ_REG(sc, AQ_HW_REVISION_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x001c))));
1791 switch (hwrev & 0x0000000f) {
1792 case 0x01:
1793 printf(", Atlantic A0, %s", fw_vers);
1794 sc->sc_features |= FEATURES_AQ1_REV_A00x01000000 |
1795 FEATURES_MPI_AQ0x00000008 | FEATURES_MIPS0x00000001;
1796 break;
1797 case 0x02:
1798 printf(", Atlantic B0, %s", fw_vers);
1799 sc->sc_features |= FEATURES_AQ1_REV_B00x02000000 |
1800 FEATURES_MPI_AQ0x00000008 | FEATURES_MIPS0x00000001 |
1801 FEATURES_TPO20x00000002 | FEATURES_RPF20x00000004;
1802 break;
1803 case 0x0A:
1804 printf(", Atlantic B1, %s", fw_vers);
1805 sc->sc_features |= FEATURES_AQ1_REV_B10x04000000 |
1806 FEATURES_MPI_AQ0x00000008 | FEATURES_MIPS0x00000001 |
1807 FEATURES_TPO20x00000002 | FEATURES_RPF20x00000004;
1808 break;
1809 default:
1810 printf(": Unknown revision (0x%08x)\n", hwrev);
1811 error = ENOTSUP91;
1812 break;
1813 }
1814 return error;
1815}
1816
1817int
1818aq1_hw_init_ucp(struct aq_softc *sc)
1819{
1820 int timo;
1821
1822 if (FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff) == 1) {
1823 if (AQ_READ_REG(sc, FW1X_MPI_INIT2_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0370)))) == 0) {
1824 uint32_t data;
1825 arc4random_buf(&data, sizeof(data));
1826 data &= 0xfefefefe;
1827 data |= 0x02020202;
1828 AQ_WRITE_REG(sc, FW1X_MPI_INIT2_REG, data)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0370)),
((data))));
1829 }
1830 AQ_WRITE_REG(sc, FW1X_MPI_INIT1_REG, 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0364)),
((0))));
1831 }
1832
1833 for (timo = 100; timo > 0; timo--) {
1834 sc->sc_mbox_addr = AQ_READ_REG(sc, FW_MPI_MBOX_ADDR_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0360))));
1835 if (sc->sc_mbox_addr != 0)
1836 break;
1837 delay(1000)(*delay_func)(1000);
1838 }
1839
1840#define AQ_FW_MIN_VERSION0x01050006 0x01050006
1841#define AQ_FW_MIN_VERSION_STR"1.5.6" "1.5.6"
1842 if (sc->sc_fw_version < AQ_FW_MIN_VERSION0x01050006) {
1843 printf("%s: atlantic: wrong FW version: " AQ_FW_MIN_VERSION_STR"1.5.6"
1844 " or later required, this is %d.%d.%d\n",
1845 DEVNAME(sc)((sc)->sc_dev.dv_xname),
1846 FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff),
1847 FW_VERSION_MINOR(sc)(((sc)->sc_fw_version >> 16) & 0xff),
1848 FW_VERSION_BUILD(sc)((sc)->sc_fw_version & 0xffff));
1849 return ENOTSUP91;
1850 }
1851
1852 if (sc->sc_mbox_addr == 0)
1853 printf("%s: NULL MBOX!!\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
1854
1855 return 0;
1856}
1857
1858int
1859aq2_interface_buffer_read(struct aq_softc *sc, uint32_t reg0, uint32_t *data0,
1860 uint32_t size0)
1861{
1862 uint32_t tid0, tid1, reg, *data, size;
1863 int timo;
1864
1865 for (timo = 10000; timo > 0; timo--) {
1866 tid0 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x13000)))
);
1867 if (((tid0 & AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A0x0000ffff)
1868 >> AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A_S0) !=
1869 ((tid0 & AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B0xffff0000)
1870 >> AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B_S16)) {
1871 delay(10)(*delay_func)(10);
1872 continue;
1873 }
1874
1875 for (reg = reg0, data = data0, size = size0;
1876 size >= 4; reg += 4, data++, size -= 4) {
1877 *data = AQ_READ_REG(sc, reg)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((reg))));
1878 }
1879
1880 tid1 = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x13000)))
);
1881 if (tid0 == tid1)
1882 break;
1883 }
1884 if (timo == 0) {
1885 printf("%s: interface buffer read timeout\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
1886 return ETIMEDOUT60;
1887 }
1888 return 0;
1889}
1890
1891int
1892aq2_fw_reboot(struct aq_softc *sc)
1893{
1894 uint32_t v;
1895 int timo, err;
1896 char buf[32];
1897 uint32_t filter_caps[3];
1898
1899 sc->sc_fw_ops = &aq2_fw_ops;
1900 sc->sc_features = FEATURES_AQ20x10000000;
1901
1902 AQ_WRITE_REG(sc, AQ2_MCP_HOST_REQ_INT_CLR_REG, 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0f08)),
((1))));
1903 AQ_WRITE_REG(sc, AQ2_MIF_BOOT_REG, 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x3040)),
((1)))); /* reboot request */
1904 for (timo = 200000; timo > 0; timo--) {
1905 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x3040))));
1906 if ((v & AQ2_MIF_BOOT_BOOT_STARTED(1 << 24)) && v != 0xffffffff)
1907 break;
1908 delay(10)(*delay_func)(10);
1909 }
1910 if (timo <= 0) {
1911 printf(": FW reboot timeout\n");
1912 return ETIMEDOUT60;
1913 }
1914
1915 for (timo = 2000000; timo > 0; timo--) {
1916 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x3040))));
1917 if ((v & AQ2_MIF_BOOT_FW_INIT_FAILED(1 << 29)) ||
1918 (v & AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS(1U << 31)))
1919 break;
1920 v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0f00))));
1921 if (v & AQ2_MCP_HOST_REQ_INT_READY(1 << 0))
1922 break;
1923 delay(10)(*delay_func)(10);
1924 }
1925 if (timo <= 0) {
1926 printf(": FW restart timeout\n");
1927 return ETIMEDOUT60;
1928 }
1929
1930 v = AQ_READ_REG(sc, AQ2_MIF_BOOT_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x3040))));
1931 if (v & AQ2_MIF_BOOT_FW_INIT_FAILED(1 << 29)) {
1932 printf(": FW restart failed\n");
1933 return ETIMEDOUT60;
1934 }
1935
1936 v = AQ_READ_REG(sc, AQ2_MCP_HOST_REQ_INT_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0f00))));
1937 if (v & AQ2_MCP_HOST_REQ_INT_READY(1 << 0)) {
1938 printf(": firmware required\n");
1939 return ENXIO6;
1940 }
1941
1942 /*
1943 * Get aq2 firmware version.
1944 * Note that the bit layout and its meaning are different from aq1.
1945 */
1946 err = aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG0x13004,
1947 (uint32_t *)&v, sizeof(v));
1948 if (err != 0)
1949 return err;
1950
1951 sc->sc_fw_version =
1952 (((v & AQ2_FW_INTERFACE_OUT_VERSION_MAJOR0x000000ff) >>
1953 AQ2_FW_INTERFACE_OUT_VERSION_MAJOR_S0) << 24) |
1954 (((v & AQ2_FW_INTERFACE_OUT_VERSION_MINOR0x0000ff00) >>
1955 AQ2_FW_INTERFACE_OUT_VERSION_MINOR_S8) << 16) |
1956 (((v & AQ2_FW_INTERFACE_OUT_VERSION_BUILD0xffff0000) >>
1957 AQ2_FW_INTERFACE_OUT_VERSION_BUILD_S16));
1958
1959 err = aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG0x13010,
1960 (uint32_t *)&v, sizeof(v));
1961 if (err != 0)
1962 return err;
1963
1964 switch (v & AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER0x0000000f) {
1965 case AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A00:
1966 sc->sc_features |= FEATURES_AQ2_IFACE_A00x20000000;
1967 strncpy(buf, "A0", sizeof(buf));
1968 break;
1969 case AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B01:
1970 sc->sc_features |= FEATURES_AQ2_IFACE_B00x40000000;
1971 strncpy(buf, "B0", sizeof(buf));
1972 break;
1973 default:
1974 snprintf(buf, sizeof(buf), "(unknown 0x%08x)", v);
1975 break;
1976 }
1977 printf(", Atlantic2 %s, F/W version %d.%d.%d", buf,
1978 FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff), FW_VERSION_MINOR(sc)(((sc)->sc_fw_version >> 16) & 0xff), FW_VERSION_BUILD(sc)((sc)->sc_fw_version & 0xffff));
1979
1980 aq2_interface_buffer_read(sc, AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG0x13774,
1981 filter_caps, sizeof(filter_caps));
1982 sc->sc_art_filter_base_index = ((filter_caps[2] &
1983 AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX0x00ff0000) >>
1984 AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX_SHIFT16) * 8;
1985
1986 /* debug info */
1987 v = AQ_READ_REG(sc, AQ_HW_REVISION_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x001c))));
1988 DPRINTF(("%s: HW Rev: 0x%08x\n", DEVNAME(sc), v));
1989
1990 return 0;
1991}
1992
1993int
1994aq_hw_reset(struct aq_softc *sc)
1995{
1996 int error;
1997
1998 /* disable irq */
1999 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x2300))))); _v &= ~((1 << 29)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 29))) -
1) & ((uint32_t)((1 << 29)))) ^ ((uint32_t)((1 <<
29))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x2300))), ((_v)))); } while ( 0);
2000
2001 /* apply */
2002 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_IRQ, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x2300))))); _v &= ~((1U << 31));
if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1U << 31)
)) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t)((
1U << 31))))); ((((sc))->sc_iot)->write_4((((sc))
->sc_ioh), (((0x2300))), ((_v)))); } while ( 0);
2003
2004 /* wait ack 10 times by 1ms */
2005 WAIT_FOR(do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x2300)))) & (1U << 31)
) == 0)) && _n != 0; --_n) { (*delay_func)((1000)); }
if ((&error != ((void *)0))) { if (_n == 0) *(&error
) = 60; else *(&error) = 0; } } while ( 0)
2006 (AQ_READ_REG(sc, AQ_INTR_CTRL_REG) & AQ_INTR_CTRL_RESET_IRQ) == 0,do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x2300)))) & (1U << 31)
) == 0)) && _n != 0; --_n) { (*delay_func)((1000)); }
if ((&error != ((void *)0))) { if (_n == 0) *(&error
) = 60; else *(&error) = 0; } } while ( 0)
2007 1000, 10, &error)do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x2300)))) & (1U << 31)
) == 0)) && _n != 0; --_n) { (*delay_func)((1000)); }
if ((&error != ((void *)0))) { if (_n == 0) *(&error
) = 60; else *(&error) = 0; } } while ( 0);
2008 if (error != 0) {
2009 printf(": IRQ reset failed: %d\n", error);
2010 return error;
2011 }
2012
2013 return sc->sc_fw_ops->reset(sc);
2014}
2015
2016int
2017aq1_get_mac_addr(struct aq_softc *sc)
2018{
2019 uint32_t mac_addr[2];
2020 uint32_t efuse_shadow_addr;
2021 int err;
2022
2023 efuse_shadow_addr = 0;
Value stored to 'efuse_shadow_addr' is never read
2024 if (FW_VERSION_MAJOR(sc)(((sc)->sc_fw_version >> 24) & 0xff) >= 2)
2025 efuse_shadow_addr = AQ_READ_REG(sc, FW2X_MPI_EFUSEADDR_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0364))));
2026 else
2027 efuse_shadow_addr = AQ_READ_REG(sc, FW1X_MPI_EFUSEADDR_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x0374))));
2028
2029 if (efuse_shadow_addr == 0) {
2030 printf(": cannot get efuse addr\n");
2031 return ENXIO6;
2032 }
2033
2034 DPRINTF(("%s: efuse_shadow_addr = %x\n", DEVNAME(sc), efuse_shadow_addr));
2035
2036 memset(mac_addr, 0, sizeof(mac_addr))__builtin_memset((mac_addr), (0), (sizeof(mac_addr)));
2037 err = aq1_fw_downld_dwords(sc, efuse_shadow_addr + (40 * 4),
2038 mac_addr, 2);
2039 if (err < 0)
2040 return err;
2041
2042 if (mac_addr[0] == 0 && mac_addr[1] == 0) {
2043 printf(": mac address not found\n");
2044 return ENXIO6;
2045 }
2046
2047 DPRINTF(("%s: mac0 %x mac1 %x\n", DEVNAME(sc), mac_addr[0],
2048 mac_addr[1]));
2049
2050 mac_addr[0] = htobe32(mac_addr[0])(__uint32_t)(__builtin_constant_p(mac_addr[0]) ? (__uint32_t)
(((__uint32_t)(mac_addr[0]) & 0xff) << 24 | ((__uint32_t
)(mac_addr[0]) & 0xff00) << 8 | ((__uint32_t)(mac_addr
[0]) & 0xff0000) >> 8 | ((__uint32_t)(mac_addr[0]) &
0xff000000) >> 24) : __swap32md(mac_addr[0]));
2051 mac_addr[1] = htobe32(mac_addr[1])(__uint32_t)(__builtin_constant_p(mac_addr[1]) ? (__uint32_t)
(((__uint32_t)(mac_addr[1]) & 0xff) << 24 | ((__uint32_t
)(mac_addr[1]) & 0xff00) << 8 | ((__uint32_t)(mac_addr
[1]) & 0xff0000) >> 8 | ((__uint32_t)(mac_addr[1]) &
0xff000000) >> 24) : __swap32md(mac_addr[1]));
2052
2053 DPRINTF(("%s: mac0 %x mac1 %x\n", DEVNAME(sc), mac_addr[0],
2054 mac_addr[1]));
2055
2056 memcpy(sc->sc_enaddr.ether_addr_octet,__builtin_memcpy((sc->sc_enaddr.ether_addr_octet), ((uint8_t
*)mac_addr), (6))
2057 (uint8_t *)mac_addr, ETHER_ADDR_LEN)__builtin_memcpy((sc->sc_enaddr.ether_addr_octet), ((uint8_t
*)mac_addr), (6));
2058
2059 return 0;
2060}
2061
2062int
2063aq_activate(struct device *self, int act)
2064{
2065 return 0;
2066}
2067
2068int
2069aq1_fw_downld_dwords(struct aq_softc *sc, uint32_t addr, uint32_t *p,
2070 uint32_t cnt)
2071{
2072 uint32_t v;
2073 int error = 0;
2074
2075 WAIT_FOR(AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG) == 1, 1, 10000, &error)do { unsigned int _n; for (_n = 10000; (!((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), (((0x03a0 + (2) * 4))))) == 1)) &&
_n != 0; --_n) { (*delay_func)((1)); } if ((&error != ((
void *)0))) { if (_n == 0) *(&error) = 60; else *(&error
) = 0; } } while ( 0);
2076 if (error != 0) {
2077 AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x03a0 +
(2) * 4))), ((1))));
2078 v = AQ_READ_REG(sc, AQ_FW_SEM_RAM_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (((0x03a0 + (
2) * 4)))));
2079 if (v == 0) {
2080 printf("%s: %s:%d: timeout\n",
2081 DEVNAME(sc)((sc)->sc_dev.dv_xname), __func__, __LINE__2081);
2082 return ETIMEDOUT60;
2083 }
2084 }
2085
2086 AQ_WRITE_REG(sc, AQ_FW_MBOX_ADDR_REG, addr)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0208)),
((addr))));
2087
2088 error = 0;
2089 for (; cnt > 0 && error == 0; cnt--) {
2090 /* execute mailbox interface */
2091 AQ_WRITE_REG_BIT(sc, AQ_FW_MBOX_CMD_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x0200))))); _v &= ~(0x00008000); if ((
1) != 0) _v |= (((1)) * (((((uint32_t)(0x00008000)) - 1) &
((uint32_t)(0x00008000))) ^ ((uint32_t)(0x00008000)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x0200))
), ((_v)))); } while ( 0)
2092 AQ_FW_MBOX_CMD_EXECUTE, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x0200))))); _v &= ~(0x00008000); if ((
1) != 0) _v |= (((1)) * (((((uint32_t)(0x00008000)) - 1) &
((uint32_t)(0x00008000))) ^ ((uint32_t)(0x00008000)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x0200))
), ((_v)))); } while ( 0);
2093 if (sc->sc_features & FEATURES_AQ1_REV_B10x04000000) {
2094 WAIT_FOR(AQ_READ_REG(sc, AQ_FW_MBOX_ADDR_REG) != addr,do { unsigned int _n; for (_n = 1000; (!((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x0208)))) != addr)) && _n
!= 0; --_n) { (*delay_func)((1)); } if ((&error != ((void
*)0))) { if (_n == 0) *(&error) = 60; else *(&error)
= 0; } } while ( 0)
2095 1, 1000, &error)do { unsigned int _n; for (_n = 1000; (!((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x0208)))) != addr)) && _n
!= 0; --_n) { (*delay_func)((1)); } if ((&error != ((void
*)0))) { if (_n == 0) *(&error) = 60; else *(&error)
= 0; } } while ( 0);
2096 } else {
2097 WAIT_FOR((AQ_READ_REG(sc, AQ_FW_MBOX_CMD_REG) &do { unsigned int _n; for (_n = 1000; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x0200)))) & 0x00000100) == 0
)) && _n != 0; --_n) { (*delay_func)((1)); } if ((&
error != ((void *)0))) { if (_n == 0) *(&error) = 60; else
*(&error) = 0; } } while ( 0)
2098 AQ_FW_MBOX_CMD_BUSY) == 0,do { unsigned int _n; for (_n = 1000; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x0200)))) & 0x00000100) == 0
)) && _n != 0; --_n) { (*delay_func)((1)); } if ((&
error != ((void *)0))) { if (_n == 0) *(&error) = 60; else
*(&error) = 0; } } while ( 0)
2099 1, 1000, &error)do { unsigned int _n; for (_n = 1000; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x0200)))) & 0x00000100) == 0
)) && _n != 0; --_n) { (*delay_func)((1)); } if ((&
error != ((void *)0))) { if (_n == 0) *(&error) = 60; else
*(&error) = 0; } } while ( 0);
2100 }
2101 *p++ = AQ_READ_REG(sc, AQ_FW_MBOX_VAL_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x020C))));
2102 addr += sizeof(uint32_t);
2103 }
2104 AQ_WRITE_REG(sc, AQ_FW_SEM_RAM_REG, 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x03a0 +
(2) * 4))), ((1))));
2105
2106 if (error != 0)
2107 printf("%s: %s:%d: timeout\n",
2108 DEVNAME(sc)((sc)->sc_dev.dv_xname), __func__, __LINE__2108);
2109
2110 return error;
2111}
2112
2113int
2114aq_fw2x_reset(struct aq_softc *sc)
2115{
2116 struct aq_fw2x_capabilities caps = { 0 };
2117 int error;
2118
2119 error = aq1_fw_downld_dwords(sc,
2120 sc->sc_mbox_addr + offsetof(struct aq_fw2x_mailbox, caps)__builtin_offsetof(struct aq_fw2x_mailbox, caps),
2121 (uint32_t *)&caps, sizeof caps / sizeof(uint32_t));
2122 if (error != 0) {
2123 printf("%s: fw2x> can't get F/W capabilities mask, error %d\n",
2124 DEVNAME(sc)((sc)->sc_dev.dv_xname), error);
2125 return error;
2126 }
2127 sc->sc_fw_caps = caps.caps_lo | ((uint64_t)caps.caps_hi << 32);
2128
2129 DPRINTF(("%s: fw2x> F/W capabilities=0x%llx\n", DEVNAME(sc),
2130 sc->sc_fw_caps));
2131
2132 return 0;
2133}
2134
2135int
2136aq_fw1x_reset(struct aq_softc *sc)
2137{
2138 printf("%s: unimplemented %s\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), __func__);
2139 return 0;
2140}
2141
2142int
2143aq_fw1x_set_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state w,
2144 enum aq_link_speed x, enum aq_link_fc y, enum aq_link_eee z)
2145{
2146 return 0;
2147}
2148
2149int
2150aq_fw1x_get_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state *w,
2151 enum aq_link_speed *x, enum aq_link_fc *y, enum aq_link_eee *z)
2152{
2153 return 0;
2154}
2155
2156int
2157aq_fw1x_get_stats(struct aq_softc *sc, struct aq_hw_stats_s *w)
2158{
2159 return 0;
2160}
2161
2162
2163int
2164aq_fw2x_get_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state *modep,
2165 enum aq_link_speed *speedp, enum aq_link_fc *fcp, enum aq_link_eee *eeep)
2166{
2167 uint64_t mpi_state, mpi_ctrl;
2168 enum aq_link_speed speed;
2169 enum aq_link_fc fc;
2170
2171 AQ_MPI_LOCK(sc)mtx_enter(&(sc)->sc_mpi_mutex);;
2172
2173 mpi_state = AQ_READ64_REG(sc, FW2X_MPI_STATE_REG)((uint64_t)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (
(0x0370)))) | (((uint64_t)(((sc)->sc_iot)->read_4(((sc)
->sc_ioh), (((0x0370) + 4))))) << 32));
2174 if (modep != NULL((void *)0)) {
2175 mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG)((uint64_t)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (
(0x0368)))) | (((uint64_t)(((sc)->sc_iot)->read_4(((sc)
->sc_ioh), (((0x0368) + 4))))) << 32));
2176 if (mpi_ctrl & FW2X_CTRL_RATE_MASK((1 << 5) | (1 << 8) | (1 << 9) | (1 <<
10) | (1 << 11)))
2177 *modep = MPI_INIT;
2178 else
2179 *modep = MPI_DEINIT;
2180 }
2181
2182 AQ_MPI_UNLOCK(sc)mtx_leave(&(sc)->sc_mpi_mutex);;
2183
2184 if (mpi_state & FW2X_CTRL_RATE_10G(1 << 11))
2185 speed = AQ_LINK_10G;
2186 else if (mpi_state & FW2X_CTRL_RATE_5G(1 << 10))
2187 speed = AQ_LINK_5G;
2188 else if (mpi_state & FW2X_CTRL_RATE_2G5(1 << 9))
2189 speed = AQ_LINK_2G5;
2190 else if (mpi_state & FW2X_CTRL_RATE_1G(1 << 8))
2191 speed = AQ_LINK_1G;
2192 else if (mpi_state & FW2X_CTRL_RATE_100M(1 << 5))
2193 speed = AQ_LINK_100M;
2194 else
2195 speed = AQ_LINK_NONE;
2196 if (speedp != NULL((void *)0))
2197 *speedp = speed;
2198
2199 fc = AQ_FC_NONE;
2200 if (mpi_state & FW2X_CTRL_PAUSE(1ULL << 35))
2201 fc |= AQ_FC_RX;
2202 if (mpi_state & FW2X_CTRL_ASYMMETRIC_PAUSE(1ULL << 36))
2203 fc |= AQ_FC_TX;
2204 if (fcp != NULL((void *)0))
2205 *fcp = fc;
2206
2207 if (eeep != NULL((void *)0))
2208 *eeep = AQ_EEE_DISABLE;
2209
2210 return 0;
2211}
2212
2213int
2214aq_fw2x_get_stats(struct aq_softc *sc, struct aq_hw_stats_s *w)
2215{
2216 return 0;
2217}
2218
2219static int
2220aq2_fw_wait_shared_ack(struct aq_softc *sc)
2221{
2222 int error;
2223
2224 AQ_WRITE_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0e00)),
(((1 << 0)))))
2225 AQ2_MIF_HOST_FINISHED_STATUS_ACK)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0e00)),
(((1 << 0)))));
2226 WAIT_FOR((AQ_READ_REG(sc, AQ2_MIF_HOST_FINISHED_STATUS_READ_REG) &do { unsigned int _n; for (_n = 100000; (!(((((sc)->sc_iot
)->read_4(((sc)->sc_ioh), ((0x0e04)))) & (1 <<
0)) == 0)) && _n != 0; --_n) { (*delay_func)((100));
} if ((&error != ((void *)0))) { if (_n == 0) *(&error
) = 60; else *(&error) = 0; } } while ( 0)
2227 AQ2_MIF_HOST_FINISHED_STATUS_ACK) == 0, 100, 100000, &error)do { unsigned int _n; for (_n = 100000; (!(((((sc)->sc_iot
)->read_4(((sc)->sc_ioh), ((0x0e04)))) & (1 <<
0)) == 0)) && _n != 0; --_n) { (*delay_func)((100));
} if ((&error != ((void *)0))) { if (_n == 0) *(&error
) = 60; else *(&error) = 0; } } while ( 0);
2228
2229 return error;
2230}
2231
2232int
2233aq2_fw_reset(struct aq_softc *sc)
2234{
2235 uint32_t v;
2236 int error;
2237
2238 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0)
2239 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0)
2240 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0);
2241
2242 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_MTU_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x12000))
, (((1 << 11) + sizeof(struct ether_header)))))
2243 /*AQ2_JUMBO_MTU*/ MCLBYTES + sizeof(struct ether_header))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x12000))
, (((1 << 11) + sizeof(struct ether_header)))));
2244
2245 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x12a58)))
);
2246 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC0x00800000;
2247 v &= ~AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX0x007c0000;
2248 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT0x00010000;
2249 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC0x00008000;
2250 v &= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX0x00007c00;
2251 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT0x00000100;
2252 v |= AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC0x00000080;
2253 v &= ~AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX0x0000007c;
2254 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG, v)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x12a58))
, ((v))));
2255
2256 error = aq2_fw_wait_shared_ack(sc);
2257 if (error != 0)
2258 printf(": reset timed out\n");
2259 return error;
2260}
2261
2262int
2263aq2_get_mac_addr(struct aq_softc *sc)
2264{
2265 uint32_t mac_addr[2];
2266
2267 memset(mac_addr, 0, sizeof(mac_addr))__builtin_memset((mac_addr), (0), (sizeof(mac_addr)));
2268 AQ_READ_REGS(sc, AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG,(((sc)->sc_iot)->read_region_4(((sc)->sc_ioh), ((0x12008
)), ((mac_addr)), (((sizeof((mac_addr)) / sizeof((mac_addr)[0
]))))));
2269 mac_addr, nitems(mac_addr))(((sc)->sc_iot)->read_region_4(((sc)->sc_ioh), ((0x12008
)), ((mac_addr)), (((sizeof((mac_addr)) / sizeof((mac_addr)[0
]))))));;
2270
2271#ifdef __HAVE_FDT
2272 if (mac_addr[0] == 0 && mac_addr[1] == 0 &&
2273 PCITAG_NODE(sc->sc_pcitag)) {
2274 OF_getprop(PCITAG_NODE(sc->sc_pcitag), "local-mac-address",
2275 mac_addr, ETHER_ADDR_LEN6);
2276 }
2277#endif
2278
2279 if (mac_addr[0] == 0 && mac_addr[1] == 0) {
2280 printf(": mac address not found\n");
2281 return ENXIO6;
2282 }
2283
2284 mac_addr[0] = htole32(mac_addr[0])((__uint32_t)(mac_addr[0]));
2285 mac_addr[1] = htole32(mac_addr[1])((__uint32_t)(mac_addr[1]));
2286
2287 memcpy(sc->sc_enaddr.ether_addr_octet,__builtin_memcpy((sc->sc_enaddr.ether_addr_octet), ((uint8_t
*)mac_addr), (6))
2288 (uint8_t *)mac_addr, ETHER_ADDR_LEN)__builtin_memcpy((sc->sc_enaddr.ether_addr_octet), ((uint8_t
*)mac_addr), (6));
2289 return 0;
2290}
2291
2292int
2293aq2_fw_set_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state w,
2294 enum aq_link_speed speed, enum aq_link_fc fc, enum aq_link_eee eee)
2295{
2296 uint32_t v, ov;
2297 int error;
2298
2299 AQ_MPI_LOCK(sc)mtx_enter(&(sc)->sc_mpi_mutex);;
2300
2301 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x12018)))
);
2302 v &= ~(
2303 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G(1 << 15) |
2304 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G(1 << 14) |
2305 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G(1 << 13) |
2306 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5(1 << 12) |
2307 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5(1 << 11) |
2308 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G(1 << 10) |
2309 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M(1 << 9) |
2310 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M(1 << 8) |
2311 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD(1 << 7) |
2312 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD(1 << 6) |
2313 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD(1 << 5));
2314
2315 v &= ~AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP(1 << 0);
2316 ov = v;
2317
2318 if (speed & AQ_LINK_10G)
2319 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G(1 << 15);
2320 if (speed & AQ_LINK_5G)
2321 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G(1 << 14) |
2322 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G(1 << 13);
2323 if (speed & AQ_LINK_2G5)
2324 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5(1 << 12) |
2325 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5(1 << 11);
2326 if (speed & AQ_LINK_1G)
2327 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G(1 << 10) |
2328 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD(1 << 7);
2329 if (speed & AQ_LINK_100M)
2330 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M(1 << 9) |
2331 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD(1 << 6);
2332 if (speed & AQ_LINK_10M) {
2333 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M(1 << 8) |
2334 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD(1 << 5);
2335 }
2336
2337 /* flow control */
2338 v &= ~(AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX(1 << 25) |
2339 AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX(1 << 24));
2340 if (fc & AQ_FC_TX)
2341 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX(1 << 25);
2342 if (fc & AQ_FC_RX)
2343 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX(1 << 24);
2344
2345 if (speed == AQ_LINK_NONE) {
2346 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(4) != 0) _v |= (((4)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0)
2347 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(4) != 0) _v |= (((4)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0)
2348 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(4) != 0) _v |= (((4)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0);
2349 } else {
2350 AQ_WRITE_REG_BIT(sc, AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0)
2351 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0)
2352 AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x12010))))); _v &= ~(0x0000000f); if (
(1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000000f)) - 1) &
((uint32_t)(0x0000000f))) ^ ((uint32_t)(0x0000000f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x12010)
)), ((_v)))); } while ( 0);
2353 v |= AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP(1 << 0);
2354 }
2355
2356 AQ_WRITE_REG(sc, AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG, v)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x12018))
, ((v))));
2357 error = aq2_fw_wait_shared_ack(sc);
2358
2359 AQ_MPI_UNLOCK(sc)mtx_leave(&(sc)->sc_mpi_mutex);;
2360 return error;
2361}
2362
2363int
2364aq2_fw_get_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state *modep,
2365 enum aq_link_speed *speedp, enum aq_link_fc *fcp, enum aq_link_eee *eeep)
2366{
2367 uint32_t v;
2368 enum aq_link_speed speed;
2369 enum aq_link_fc fc = 0;
2370 enum aq_link_eee eee;
2371
2372 if (modep != NULL((void *)0))
2373 *modep = MPI_INIT;
2374
2375 v = AQ_READ_REG(sc, AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x13014)))
);
2376 switch ((v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE0x000000f0) >>
2377 AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_S4) {
2378 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G6:
2379 speed = AQ_LINK_10G;
2380 break;
2381 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G5:
2382 speed = AQ_LINK_5G;
2383 break;
2384 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G54:
2385 speed = AQ_LINK_2G5;
2386 break;
2387 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G3:
2388 speed = AQ_LINK_1G;
2389 break;
2390 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M2:
2391 speed = AQ_LINK_100M;
2392 break;
2393 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M1:
2394 speed = AQ_LINK_10M;
2395 break;
2396 case AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID0:
2397 default:
2398 speed = AQ_LINK_NONE;
2399 break;
2400 }
2401 if (speedp != NULL((void *)0))
2402 *speedp = speed;
2403
2404 if (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX(1 << 8))
2405 fc |= AQ_FC_TX;
2406 if (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX(1 << 9))
2407 fc |= AQ_FC_RX;
2408 if (fcp != NULL((void *)0))
2409 *fcp = fc;
2410
2411 eee = (v & AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE(1 << 10)) ?
2412 AQ_EEE_ENABLE : AQ_EEE_DISABLE;
2413 if (eeep != NULL((void *)0))
2414 *eeep = eee;
2415
2416 return 0;
2417}
2418
2419int
2420aq2_fw_get_stats(struct aq_softc *sc, struct aq_hw_stats_s *w)
2421{
2422 return 0;
2423}
2424
2425void
2426aq_hw_l3_filter_set(struct aq_softc *sc)
2427{
2428 int i;
2429
2430 /* clear all filter */
2431 for (i = 0; i < 8; i++) {
2432 AQ_WRITE_REG_BIT(sc, RPF_L3_FILTER_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5380 + (i) * 4)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5380 + (i) * 4)))), ((_v)))); } while (
0)
2433 RPF_L3_FILTER_L4_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5380 + (i) * 4)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5380 + (i) * 4)))), ((_v)))); } while (
0);
2434 }
2435}
2436
2437int
2438aq_hw_init(struct aq_softc *sc, int irqmode, int multivec)
2439{
2440 uint32_t v;
2441
2442 if (HWTYPE_AQ1_P(sc)(((sc)->sc_features & ((0x01000000)|(0x02000000|0x04000000
))) != 0)) {
2443 /* Force limit MRRS on RDM/TDM to 2K */
2444 v = AQ_READ_REG(sc, AQ_PCI_REG_CONTROL_6_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x1014))));
2445 AQ_WRITE_REG(sc, AQ_PCI_REG_CONTROL_6_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x1014)),
(((v & ~0x0707) | 0x0404))))
2446 (v & ~0x0707) | 0x0404)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x1014)),
(((v & ~0x0707) | 0x0404))));
2447
2448 /*
2449 * TX DMA total request limit. B0 hardware is not capable to
2450 * handle more than (8K-MRRS) incoming DMA data.
2451 * Value 24 in 256byte units
2452 */
2453 AQ_WRITE_REG(sc, AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_REG, 24)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x7b20)),
((24))));
2454 }
2455
2456 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2457 uint32_t fpgaver, speed;
2458 fpgaver = AQ_READ_REG(sc, AQ2_HW_FPGA_VERSION_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x00f4))));
2459 if (fpgaver < 0x01000000)
2460 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL1;
2461 else if (fpgaver >= 0x01008502)
2462 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF2;
2463 else
2464 speed = AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUARTER4;
2465 AQ_WRITE_REG_BIT(sc, AQ2_LAUNCHTIME_CTRL_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7a1c))))); _v &= ~(0x0000ff00); if ((
speed) != 0) _v |= (((speed)) * (((((uint32_t)(0x0000ff00)) -
1) & ((uint32_t)(0x0000ff00))) ^ ((uint32_t)(0x0000ff00)
))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((
(0x7a1c))), ((_v)))); } while ( 0)
2466 AQ2_LAUNCHTIME_CTRL_RATIO, speed)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7a1c))))); _v &= ~(0x0000ff00); if ((
speed) != 0) _v |= (((speed)) * (((((uint32_t)(0x0000ff00)) -
1) & ((uint32_t)(0x0000ff00))) ^ ((uint32_t)(0x0000ff00)
))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((
(0x7a1c))), ((_v)))); } while ( 0);
2467 }
2468
2469 aq_hw_init_tx_path(sc);
2470 aq_hw_init_rx_path(sc);
2471
2472 if (aq_set_mac_addr(sc, AQ_HW_MAC_OWN0, sc->sc_enaddr.ether_addr_octet))
2473 return EINVAL22;
2474
2475 aq_set_linkmode(sc, AQ_LINK_NONE, AQ_FC_NONE, AQ_EEE_DISABLE);
2476
2477 aq_hw_qos_set(sc);
2478
2479 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2480 AQ_WRITE_REG_BIT(sc, AQ2_RPF_NEW_CTRL_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5104))))); _v &= ~((1 << 11)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 11))) -
1) & ((uint32_t)((1 << 11)))) ^ ((uint32_t)((1 <<
11))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5104))), ((_v)))); } while ( 0)
2481 AQ2_RPF_NEW_CTRL_ENABLE, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5104))))); _v &= ~((1 << 11)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 11))) -
1) & ((uint32_t)((1 << 11)))) ^ ((uint32_t)((1 <<
11))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5104))), ((_v)))); } while ( 0);
2482 }
2483
2484 /* Enable interrupt */
2485 AQ_WRITE_REG(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_RESET_DIS)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2300)),
(((1 << 29)))));
2486 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_MULTIVEC, multivec)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x2300))))); _v &= ~((1 << 2)); if
((multivec) != 0) _v |= (((multivec)) * (((((uint32_t)((1 <<
2))) - 1) & ((uint32_t)((1 << 2)))) ^ ((uint32_t)(
(1 << 2))))); ((((sc))->sc_iot)->write_4((((sc))->
sc_ioh), (((0x2300))), ((_v)))); } while ( 0);
2487
2488 AQ_WRITE_REG_BIT(sc, AQ_INTR_CTRL_REG, AQ_INTR_CTRL_IRQMODE, irqmode)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x2300))))); _v &= ~(((1 << 0) | (
1 << 1))); if ((irqmode) != 0) _v |= (((irqmode)) * (((
((uint32_t)(((1 << 0) | (1 << 1)))) - 1) & ((
uint32_t)(((1 << 0) | (1 << 1))))) ^ ((uint32_t)(
((1 << 0) | (1 << 1)))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), (((0x2300))), ((_v)))); } while (
0);
2489
2490 AQ_WRITE_REG(sc, AQ_INTR_AUTOMASK_REG, 0xffffffff)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2090)),
((0xffffffff))));
2491
2492 AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(0),(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x2180 +
(0) * 4))), ((((8U << 24) | (1U << 31)) | ((8U <<
16) | (1 << 23))))))
2493 ((AQ_B0_ERR_INT << 24) | (1U << 31)) |(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x2180 +
(0) * 4))), ((((8U << 24) | (1U << 31)) | ((8U <<
16) | (1 << 23))))))
2494 ((AQ_B0_ERR_INT << 16) | (1 << 23))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x2180 +
(0) * 4))), ((((8U << 24) | (1U << 31)) | ((8U <<
16) | (1 << 23))))))
2495 )(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x2180 +
(0) * 4))), ((((8U << 24) | (1U << 31)) | ((8U <<
16) | (1 << 23))))));
2496
2497 /* link interrupt */
2498 AQ_WRITE_REG(sc, AQ_GEN_INTR_MAP_REG(3),(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x2180 +
(3) * 4))), (((1 << 7) | sc->sc_linkstat_irq))))
2499 (1 << 7) | sc->sc_linkstat_irq)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x2180 +
(3) * 4))), (((1 << 7) | sc->sc_linkstat_irq))));
2500
2501 return 0;
2502}
2503
2504void
2505aq_hw_init_tx_path(struct aq_softc *sc)
2506{
2507 /* Tx TC/RSS number config */
2508 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_TC_MODE_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7900))))); _v &= ~((1 << 8)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 8))) - 1
) & ((uint32_t)((1 << 8)))) ^ ((uint32_t)((1 <<
8))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7900))), ((_v)))); } while ( 0);
2509
2510 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7820))))); _v &= ~(0xFFF); if ((0x0ff6
) != 0) _v |= (((0x0ff6)) * (((((uint32_t)(0xFFF)) - 1) &
((uint32_t)(0xFFF))) ^ ((uint32_t)(0xFFF)))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), (((0x7820))), ((_v)))); } while
( 0)
2511 THM_LSO_TCP_FLAG1_FIRST, 0x0ff6)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7820))))); _v &= ~(0xFFF); if ((0x0ff6
) != 0) _v |= (((0x0ff6)) * (((((uint32_t)(0xFFF)) - 1) &
((uint32_t)(0xFFF))) ^ ((uint32_t)(0xFFF)))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), (((0x7820))), ((_v)))); } while
( 0);
2512 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG1_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7820))))); _v &= ~(0xFFF0000); if ((0x0ff6
) != 0) _v |= (((0x0ff6)) * (((((uint32_t)(0xFFF0000)) - 1) &
((uint32_t)(0xFFF0000))) ^ ((uint32_t)(0xFFF0000)))); ((((sc
))->sc_iot)->write_4((((sc))->sc_ioh), (((0x7820))),
((_v)))); } while ( 0)
2513 THM_LSO_TCP_FLAG1_MID, 0x0ff6)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7820))))); _v &= ~(0xFFF0000); if ((0x0ff6
) != 0) _v |= (((0x0ff6)) * (((((uint32_t)(0xFFF0000)) - 1) &
((uint32_t)(0xFFF0000))) ^ ((uint32_t)(0xFFF0000)))); ((((sc
))->sc_iot)->write_4((((sc))->sc_ioh), (((0x7820))),
((_v)))); } while ( 0);
2514 AQ_WRITE_REG_BIT(sc, THM_LSO_TCP_FLAG2_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7824))))); _v &= ~(0xFFF); if ((0x0f7f
) != 0) _v |= (((0x0f7f)) * (((((uint32_t)(0xFFF)) - 1) &
((uint32_t)(0xFFF))) ^ ((uint32_t)(0xFFF)))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), (((0x7824))), ((_v)))); } while
( 0)
2515 THM_LSO_TCP_FLAG2_LAST, 0x0f7f)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7824))))); _v &= ~(0xFFF); if ((0x0f7f
) != 0) _v |= (((0x0f7f)) * (((((uint32_t)(0xFFF)) - 1) &
((uint32_t)(0xFFF))) ^ ((uint32_t)(0xFFF)))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), (((0x7824))), ((_v)))); } while
( 0);
2516
2517 /* misc */
2518 AQ_WRITE_REG(sc, TX_TPO2_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x7040)),
(((sc->sc_features & 0x00000002) ? (1 << 16) : 0
))))
2519 (sc->sc_features & FEATURES_TPO2) ? TX_TPO2_EN : 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x7040)),
(((sc->sc_features & 0x00000002) ? (1 << 16) : 0
))));
2520 AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x8480))))); _v &= ~((1U << 31));
if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U << 31)
)) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t)((
1U << 31))))); ((((sc))->sc_iot)->write_4((((sc))
->sc_ioh), (((0x8480))), ((_v)))); } while ( 0);
2521 AQ_WRITE_REG_BIT(sc, TDM_DCA_REG, TDM_DCA_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x8480))))); _v &= ~(0xF); if ((0) != 0
) _v |= (((0)) * (((((uint32_t)(0xF)) - 1) & ((uint32_t)(
0xF))) ^ ((uint32_t)(0xF)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x8480))), ((_v)))); } while ( 0);
2522
2523 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_SCP_INS_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7900))))); _v &= ~((1 << 2)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 2))) - 1
) & ((uint32_t)((1 << 2)))) ^ ((uint32_t)((1 <<
2))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7900))), ((_v)))); } while ( 0);
2524
2525 if ((sc->sc_features & FEATURES_AQ1_REV_B(0x02000000|0x04000000)) || HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2526 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_CLK_GATE_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7900))))); _v &= ~((1 << 5)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 5))) - 1
) & ((uint32_t)((1 << 5)))) ^ ((uint32_t)((1 <<
5))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7900))), ((_v)))); } while ( 0);
2527 }
2528}
2529
2530void
2531aq_hw_init_rx_path(struct aq_softc *sc)
2532{
2533 int i;
2534
2535 /* clear setting */
2536 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5700))))); _v &= ~((1 << 8)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 8))) - 1
) & ((uint32_t)((1 << 8)))) ^ ((uint32_t)((1 <<
8))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5700))), ((_v)))); } while ( 0);
2537 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5700))))); _v &= ~(0x30); if ((0) != 0
) _v |= (((0)) * (((((uint32_t)(0x30)) - 1) & ((uint32_t)
(0x30))) ^ ((uint32_t)(0x30)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x5700))), ((_v)))); } while ( 0);
2538
2539 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2540 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REDIR2_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54c8))))); _v &= ~(0x00000100); if ((
0x00000100) != 0) _v |= (((0x00000100)) * (((((uint32_t)(0x00000100
)) - 1) & ((uint32_t)(0x00000100))) ^ ((uint32_t)(0x00000100
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x54c8))), ((_v)))); } while ( 0)
2541 AQ2_RPF_REDIR2_HASHTYPE, AQ2_RPF_REDIR2_HASHTYPE_ALL)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54c8))))); _v &= ~(0x00000100); if ((
0x00000100) != 0) _v |= (((0x00000100)) * (((((uint32_t)(0x00000100
)) - 1) & ((uint32_t)(0x00000100))) ^ ((uint32_t)(0x00000100
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x54c8))), ((_v)))); } while ( 0);
2542 }
2543
2544 if (sc->sc_nqueues > 1) {
2545 uint32_t bits;
2546
2547 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_TC_MODE, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5700))))); _v &= ~((1 << 8)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 8))) - 1
) & ((uint32_t)((1 << 8)))) ^ ((uint32_t)((1 <<
8))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5700))), ((_v)))); } while ( 0);
2548 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_FC_MODE, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5700))))); _v &= ~(0x30); if ((1) != 0
) _v |= (((1)) * (((((uint32_t)(0x30)) - 1) & ((uint32_t)
(0x30))) ^ ((uint32_t)(0x30)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x5700))), ((_v)))); } while ( 0);
2549
2550 switch (sc->sc_nqueues) {
2551 case 2:
2552 bits = 0x11111111;
2553 break;
2554 case 4:
2555 bits = 0x22222222;
2556 break;
2557 case 8:
2558 bits = 0x33333333;
2559 break;
2560 }
2561
2562 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x54c0)),
(((1U << 31) | bits))))
2563 RX_FLR_RSS_CONTROL1_EN | bits)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x54c0)),
(((1U << 31) | bits))));
2564 } else {
2565 AQ_WRITE_REG(sc, RX_FLR_RSS_CONTROL1_REG, 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x54c0)),
((0))));
2566 }
2567
2568 if (HWTYPE_AQ1_P(sc)(((sc)->sc_features & ((0x01000000)|(0x02000000|0x04000000
))) != 0)) {
2569 for (i = 0; i < 32; i++) {
2570 AQ_WRITE_REG_BIT(sc, RPF_ETHERTYPE_FILTER_REG(i),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5300 + (i) * 4)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5300 + (i) * 4)))), ((_v)))); } while (
0)
2571 RPF_ETHERTYPE_FILTER_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5300 + (i) * 4)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5300 + (i) * 4)))), ((_v)))); } while (
0);
2572 }
2573 }
2574
2575 /* L2 and Multicast filters */
2576 for (i = 0; i < AQ_HW_MAC_NUM34; i++) {
2577 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (i) * 8)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5114 + (i) * 8)))), ((_v)))); } while (
0);
2578 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(i), RPF_L2UC_MSW_ACTION,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (i) * 8)))))); _v &= ~(0x70000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x70000)) - 1)
& ((uint32_t)(0x70000))) ^ ((uint32_t)(0x70000)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5114 +
(i) * 8)))), ((_v)))); } while ( 0)
2579 RPF_ACTION_HOST)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (i) * 8)))))); _v &= ~(0x70000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x70000)) - 1)
& ((uint32_t)(0x70000))) ^ ((uint32_t)(0x70000)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5114 +
(i) * 8)))), ((_v)))); } while ( 0);
2580 }
2581 AQ_WRITE_REG(sc, RPF_MCAST_FILTER_MASK_REG, 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x5270)),
((0))));
2582 AQ_WRITE_REG(sc, RPF_MCAST_FILTER_REG(0), 0x00010fff)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5250 +
(0) * 4))), ((0x00010fff))));
2583
2584 /* Vlan filters */
2585 AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_OUTER,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5284))))); _v &= ~(0xFFFF0000); if ((
0x88A8) != 0) _v |= (((0x88A8)) * (((((uint32_t)(0xFFFF0000))
- 1) & ((uint32_t)(0xFFFF0000))) ^ ((uint32_t)(0xFFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x5284))), ((_v)))); } while ( 0)
2586 ETHERTYPE_QINQ)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5284))))); _v &= ~(0xFFFF0000); if ((
0x88A8) != 0) _v |= (((0x88A8)) * (((((uint32_t)(0xFFFF0000))
- 1) & ((uint32_t)(0xFFFF0000))) ^ ((uint32_t)(0xFFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x5284))), ((_v)))); } while ( 0);
2587 AQ_WRITE_REG_BIT(sc, RPF_VLAN_TPID_REG, RPF_VLAN_TPID_INNER,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5284))))); _v &= ~(0xFFFF); if ((0x8100
) != 0) _v |= (((0x8100)) * (((((uint32_t)(0xFFFF)) - 1) &
((uint32_t)(0xFFFF))) ^ ((uint32_t)(0xFFFF)))); ((((sc))->
sc_iot)->write_4((((sc))->sc_ioh), (((0x5284))), ((_v))
)); } while ( 0)
2588 ETHERTYPE_VLAN)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5284))))); _v &= ~(0xFFFF); if ((0x8100
) != 0) _v |= (((0x8100)) * (((((uint32_t)(0xFFFF)) - 1) &
((uint32_t)(0xFFFF))) ^ ((uint32_t)(0xFFFF)))); ((((sc))->
sc_iot)->write_4((((sc))->sc_ioh), (((0x5284))), ((_v))
)); } while ( 0);
2589 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG, RPF_VLAN_MODE_PROMISC, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5280))))); _v &= ~((1 << 1)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 1))) - 1
) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)((1 <<
1))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5280))), ((_v)))); } while ( 0);
2590
2591 if ((sc->sc_features & FEATURES_AQ1_REV_B(0x02000000|0x04000000)) || HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2592 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5280))))); _v &= ~((1 << 2)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 2))) - 1
) & ((uint32_t)((1 << 2)))) ^ ((uint32_t)((1 <<
2))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5280))), ((_v)))); } while ( 0)
2593 RPF_VLAN_MODE_ACCEPT_UNTAGGED, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5280))))); _v &= ~((1 << 2)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 2))) - 1
) & ((uint32_t)((1 << 2)))) ^ ((uint32_t)((1 <<
2))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5280))), ((_v)))); } while ( 0);
2594 AQ_WRITE_REG_BIT(sc, RPF_VLAN_MODE_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5280))))); _v &= ~(0x38); if ((1) != 0
) _v |= (((1)) * (((((uint32_t)(0x38)) - 1) & ((uint32_t)
(0x38))) ^ ((uint32_t)(0x38)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x5280))), ((_v)))); } while ( 0)
2595 RPF_VLAN_MODE_UNTAGGED_ACTION, RPF_ACTION_HOST)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5280))))); _v &= ~(0x38); if ((1) != 0
) _v |= (((1)) * (((((uint32_t)(0x38)) - 1) & ((uint32_t)
(0x38))) ^ ((uint32_t)(0x38)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x5280))), ((_v)))); } while ( 0);
2596 }
2597
2598 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2599 AQ_WRITE_REG_BIT(sc, AQ2_RPF_REC_TAB_ENABLE_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x6ff0))))); _v &= ~(0x0000ffff); if ((
0xffff) != 0) _v |= (((0xffff)) * (((((uint32_t)(0x0000ffff))
- 1) & ((uint32_t)(0x0000ffff))) ^ ((uint32_t)(0x0000ffff
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x6ff0))), ((_v)))); } while ( 0)
2600 AQ2_RPF_REC_TAB_ENABLE_MASK, 0xffff)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x6ff0))))); _v &= ~(0x0000ffff); if ((
0xffff) != 0) _v |= (((0xffff)) * (((((uint32_t)(0x0000ffff))
- 1) & ((uint32_t)(0x0000ffff))) ^ ((uint32_t)(0x0000ffff
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x6ff0))), ((_v)))); } while ( 0);
2601 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(0),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (0) * 8)))))); _v &= ~(0x03c00000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x03c00000)) -
1) & ((uint32_t)(0x03c00000))) ^ ((uint32_t)(0x03c00000)
))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((
((0x5114 + (0) * 8)))), ((_v)))); } while ( 0)
2602 RPF_L2UC_MSW_TAG, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (0) * 8)))))); _v &= ~(0x03c00000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x03c00000)) -
1) & ((uint32_t)(0x03c00000))) ^ ((uint32_t)(0x03c00000)
))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((
((0x5114 + (0) * 8)))), ((_v)))); } while ( 0);
2603 AQ_WRITE_REG_BIT(sc, AQ2_RPF_L2BC_TAG_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x50f0))))); _v &= ~(0x0000003f); if ((
1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000003f)) - 1) &
((uint32_t)(0x0000003f))) ^ ((uint32_t)(0x0000003f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x50f0))
), ((_v)))); } while ( 0)
2604 AQ2_RPF_L2BC_TAG_MASK, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x50f0))))); _v &= ~(0x0000003f); if ((
1) != 0) _v |= (((1)) * (((((uint32_t)(0x0000003f)) - 1) &
((uint32_t)(0x0000003f))) ^ ((uint32_t)(0x0000003f)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x50f0))
), ((_v)))); } while ( 0);
2605
2606 aq2_filter_art_set(sc, AQ2_RPF_INDEX_L2_PROMISC_OFF0,
2607 0, AQ2_RPF_TAG_UC_MASK0x0000002f | AQ2_RPF_TAG_ALLMC_MASK0x00000040,
2608 AQ2_ART_ACTION_DROP(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(1) ? 0x0001 : 0)));
2609 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_PROMISC_OFF1,
2610 0, AQ2_RPF_TAG_VLAN_MASK0x00003c00 | AQ2_RPF_TAG_UNTAG_MASK0x00004000,
2611 AQ2_ART_ACTION_DROP(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(1) ? 0x0001 : 0)));
2612
2613 for (i = 0; i < 8; i++) {
2614 aq2_filter_art_set(sc, AQ2_RPF_INDEX_PCP_TO_TC56 + i,
2615 (i << AQ2_RPF_TAG_PCP_SHIFT29), AQ2_RPF_TAG_PCP_MASK0xe0000000,
2616 AQ2_ART_ACTION_ASSIGN_TC(i % sc->sc_nqueues)(((1) << 8) | ((1) ? 0x0080 : 0) | (((i % sc->sc_nqueues
)) << 2) | ((1) ? 0x0001 : 0)));
2617 }
2618
2619 } else if (HWTYPE_AQ1_P(sc)(((sc)->sc_features & ((0x01000000)|(0x02000000|0x04000000
))) != 0)) {
2620 if (sc->sc_features & FEATURES_RPF20x00000004)
2621 AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x5040)),
(((0xf << 16)))))
2622 RX_TCP_RSS_HASH_RPF2)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x5040)),
(((0xf << 16)))));
2623 else
2624 AQ_WRITE_REG(sc, RX_TCP_RSS_HASH_REG, 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x5040)),
((0))));
2625
2626 /* we might want to figure out what this magic number does */
2627 AQ_WRITE_REG_BIT(sc, RX_TCP_RSS_HASH_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5040))))); _v &= ~((0xffff)); if ((0x001e
) != 0) _v |= (((0x001e)) * (((((uint32_t)((0xffff))) - 1) &
((uint32_t)((0xffff)))) ^ ((uint32_t)((0xffff))))); ((((sc))
->sc_iot)->write_4((((sc))->sc_ioh), (((0x5040))), (
(_v)))); } while ( 0)
2628 RX_TCP_RSS_HASH_TYPE, 0x001e)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5040))))); _v &= ~((0xffff)); if ((0x001e
) != 0) _v |= (((0x001e)) * (((((uint32_t)((0xffff))) - 1) &
((uint32_t)((0xffff)))) ^ ((uint32_t)((0xffff))))); ((((sc))
->sc_iot)->write_4((((sc))->sc_ioh), (((0x5040))), (
(_v)))); } while ( 0);
2629 }
2630
2631 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5100))))); _v &= ~((1 << 0)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5100))), ((_v)))); } while ( 0);
2632 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_ACTION, RPF_ACTION_HOST)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5100))))); _v &= ~(0x7000); if ((1) !=
0) _v |= (((1)) * (((((uint32_t)(0x7000)) - 1) & ((uint32_t
)(0x7000))) ^ ((uint32_t)(0x7000)))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), (((0x5100))), ((_v)))); } while (
0);
2633 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_THRESHOLD, 0xffff)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5100))))); _v &= ~(0xFFFF0000); if ((
0xffff) != 0) _v |= (((0xffff)) * (((((uint32_t)(0xFFFF0000))
- 1) & ((uint32_t)(0xFFFF0000))) ^ ((uint32_t)(0xFFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
((0x5100))), ((_v)))); } while ( 0);
2634
2635 AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x6180))))); _v &= ~((1U << 31));
if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U << 31)
)) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t)((
1U << 31))))); ((((sc))->sc_iot)->write_4((((sc))
->sc_ioh), (((0x6180))), ((_v)))); } while ( 0);
2636 AQ_WRITE_REG_BIT(sc, RX_DMA_DCA_REG, RX_DMA_DCA_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x6180))))); _v &= ~(0xF); if ((0) != 0
) _v |= (((0)) * (((((uint32_t)(0xF)) - 1) & ((uint32_t)(
0xF))) ^ ((uint32_t)(0xF)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x6180))), ((_v)))); } while ( 0);
2637}
2638
2639/* set multicast filter. index 0 for own address */
2640int
2641aq_set_mac_addr(struct aq_softc *sc, int index, uint8_t *enaddr)
2642{
2643 uint32_t h, l;
2644
2645 if (index >= AQ_HW_MAC_NUM34)
2646 return EINVAL22;
2647
2648 if (enaddr == NULL((void *)0)) {
2649 /* disable */
2650 AQ_WRITE_REG_BIT(sc,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~((1U
<< 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((
1U << 31))) - 1) & ((uint32_t)((1U << 31)))) ^
((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5114 + (index) * 8)))), ((_v))));
} while ( 0)
2651 RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~((1U
<< 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((
1U << 31))) - 1) & ((uint32_t)((1U << 31)))) ^
((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5114 + (index) * 8)))), ((_v))));
} while ( 0);
2652 return 0;
2653 }
2654
2655 h = (enaddr[0] << 8) | (enaddr[1]);
2656 l = ((uint32_t)enaddr[2] << 24) | (enaddr[3] << 16) |
2657 (enaddr[4] << 8) | (enaddr[5]);
2658
2659 /* disable, set, and enable */
2660 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~((1U
<< 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((
1U << 31))) - 1) & ((uint32_t)((1U << 31)))) ^
((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5114 + (index) * 8)))), ((_v))));
} while ( 0);
2661 AQ_WRITE_REG(sc, RPF_L2UC_LSW_REG(index), l)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5110 +
(index) * 8))), ((l))));
2662 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~(0xFFFF
); if ((h) != 0) _v |= (((h)) * (((((uint32_t)(0xFFFF)) - 1) &
((uint32_t)(0xFFFF))) ^ ((uint32_t)(0xFFFF)))); ((((sc))->
sc_iot)->write_4((((sc))->sc_ioh), ((((0x5114 + (index)
* 8)))), ((_v)))); } while ( 0)
2663 RPF_L2UC_MSW_MACADDR_HI, h)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~(0xFFFF
); if ((h) != 0) _v |= (((h)) * (((((uint32_t)(0xFFFF)) - 1) &
((uint32_t)(0xFFFF))) ^ ((uint32_t)(0xFFFF)))); ((((sc))->
sc_iot)->write_4((((sc))->sc_ioh), ((((0x5114 + (index)
* 8)))), ((_v)))); } while ( 0);
2664 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~(0x70000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x70000)) - 1)
& ((uint32_t)(0x70000))) ^ ((uint32_t)(0x70000)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5114 +
(index) * 8)))), ((_v)))); } while ( 0)
2665 RPF_L2UC_MSW_ACTION, RPF_ACTION_HOST)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~(0x70000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x70000)) - 1)
& ((uint32_t)(0x70000))) ^ ((uint32_t)(0x70000)))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5114 +
(index) * 8)))), ((_v)))); } while ( 0);
2666 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0))
2667 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~(0x03c00000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x03c00000)) -
1) & ((uint32_t)(0x03c00000))) ^ ((uint32_t)(0x03c00000)
))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((
((0x5114 + (index) * 8)))), ((_v)))); } while ( 0)
2668 RPF_L2UC_MSW_TAG, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~(0x03c00000
); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x03c00000)) -
1) & ((uint32_t)(0x03c00000))) ^ ((uint32_t)(0x03c00000)
))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((
((0x5114 + (index) * 8)))), ((_v)))); } while ( 0);
2669 AQ_WRITE_REG_BIT(sc, RPF_L2UC_MSW_REG(index), RPF_L2UC_MSW_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5114 + (index) * 8)))))); _v &= ~((1U
<< 31)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((
1U << 31))) - 1) & ((uint32_t)((1U << 31)))) ^
((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5114 + (index) * 8)))), ((_v))));
} while ( 0);
2670
2671 return 0;
2672}
2673
2674int
2675aq_get_linkmode(struct aq_softc *sc, enum aq_link_speed *speed,
2676 enum aq_link_fc *fc, enum aq_link_eee *eee)
2677{
2678 enum aq_hw_fw_mpi_state mode;
2679 int error;
2680
2681 error = sc->sc_fw_ops->get_mode(sc, &mode, speed, fc, eee);
2682 if (error != 0)
2683 return error;
2684 if (mode != MPI_INIT)
2685 return ENXIO6;
2686
2687 return 0;
2688}
2689
2690int
2691aq_set_linkmode(struct aq_softc *sc, enum aq_link_speed speed,
2692 enum aq_link_fc fc, enum aq_link_eee eee)
2693{
2694 return sc->sc_fw_ops->set_mode(sc, MPI_INIT, speed, fc, eee);
2695}
2696
2697int
2698aq_fw2x_set_mode(struct aq_softc *sc, enum aq_hw_fw_mpi_state mode,
2699 enum aq_link_speed speed, enum aq_link_fc fc, enum aq_link_eee eee)
2700{
2701 uint64_t mpi_ctrl;
2702 int error = 0;
2703
2704 AQ_MPI_LOCK(sc)mtx_enter(&(sc)->sc_mpi_mutex);;
2705
2706 mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG)((uint64_t)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (
(0x0368)))) | (((uint64_t)(((sc)->sc_iot)->read_4(((sc)
->sc_ioh), (((0x0368) + 4))))) << 32));
2707
2708 switch (mode) {
2709 case MPI_INIT:
2710 mpi_ctrl &= ~FW2X_CTRL_RATE_MASK((1 << 5) | (1 << 8) | (1 << 9) | (1 <<
10) | (1 << 11));
2711 if (speed & AQ_LINK_10G)
2712 mpi_ctrl |= FW2X_CTRL_RATE_10G(1 << 11);
2713 if (speed & AQ_LINK_5G)
2714 mpi_ctrl |= FW2X_CTRL_RATE_5G(1 << 10);
2715 if (speed & AQ_LINK_2G5)
2716 mpi_ctrl |= FW2X_CTRL_RATE_2G5(1 << 9);
2717 if (speed & AQ_LINK_1G)
2718 mpi_ctrl |= FW2X_CTRL_RATE_1G(1 << 8);
2719 if (speed & AQ_LINK_100M)
2720 mpi_ctrl |= FW2X_CTRL_RATE_100M(1 << 5);
2721
2722 mpi_ctrl &= ~FW2X_CTRL_LINK_DROP(1ULL << 54);
2723
2724 mpi_ctrl &= ~FW2X_CTRL_EEE_MASK((1ULL << 33) | (1ULL << 37) | (1ULL << 40)
| (1ULL << 41) | (1ULL << 42) | (1ULL << 43
));
2725 if (eee == AQ_EEE_ENABLE)
2726 mpi_ctrl |= FW2X_CTRL_EEE_MASK((1ULL << 33) | (1ULL << 37) | (1ULL << 40)
| (1ULL << 41) | (1ULL << 42) | (1ULL << 43
));
2727
2728 mpi_ctrl &= ~(FW2X_CTRL_PAUSE(1ULL << 35) | FW2X_CTRL_ASYMMETRIC_PAUSE(1ULL << 36));
2729 if (fc & AQ_FC_RX)
2730 mpi_ctrl |= FW2X_CTRL_PAUSE(1ULL << 35);
2731 if (fc & AQ_FC_TX)
2732 mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE(1ULL << 36);
2733 break;
2734 case MPI_DEINIT:
2735 mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK((1 << 5) | (1 << 8) | (1 << 9) | (1 <<
10) | (1 << 11)) | FW2X_CTRL_EEE_MASK((1ULL << 33) | (1ULL << 37) | (1ULL << 40)
| (1ULL << 41) | (1ULL << 42) | (1ULL << 43
)));
2736 mpi_ctrl &= ~(FW2X_CTRL_PAUSE(1ULL << 35) | FW2X_CTRL_ASYMMETRIC_PAUSE(1ULL << 36));
2737 break;
2738 default:
2739 printf("%s: fw2x> unknown MPI state %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname), mode);
2740 error = EINVAL22;
2741 goto failure;
2742 }
2743 AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl)do { (((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x0368
)), (((uint32_t)mpi_ctrl)))); (((sc)->sc_iot)->write_4(
((sc)->sc_ioh), ((0x0368 + 4)), (((uint32_t)(mpi_ctrl >>
32))))); } while ( 0);
2744
2745 failure:
2746 AQ_MPI_UNLOCK(sc)mtx_leave(&(sc)->sc_mpi_mutex);;
2747 return error;
2748}
2749
2750void
2751aq_hw_qos_set(struct aq_softc *sc)
2752{
2753 uint32_t tc = 0;
2754 uint32_t buff_size;
2755
2756 /* TPS Descriptor rate init */
2757 AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_TA_RST, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7310))))); _v &= ~((1U << 31));
if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U << 31)
)) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t)((
1U << 31))))); ((((sc))->sc_iot)->write_4((((sc))
->sc_ioh), (((0x7310))), ((_v)))); } while ( 0);
2758 AQ_WRITE_REG_BIT(sc, TPS_DESC_RATE_REG, TPS_DESC_RATE_LIM, 0xa)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7310))))); _v &= ~(0x7FF); if ((0xa) !=
0) _v |= (((0xa)) * (((((uint32_t)(0x7FF)) - 1) & ((uint32_t
)(0x7FF))) ^ ((uint32_t)(0x7FF)))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), (((0x7310))), ((_v)))); } while (
0);
2759
2760 /* TPS VM init */
2761 AQ_WRITE_REG_BIT(sc, TPS_DESC_VM_ARB_MODE_REG, TPS_DESC_VM_ARB_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7300))))); _v &= ~((1 << 0)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7300))), ((_v)))); } while ( 0);
2762
2763 /* TPS TC credits init */
2764 AQ_WRITE_REG_BIT(sc, TPS_DESC_TC_ARB_MODE_REG, TPS_DESC_TC_ARB_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7200))))); _v &= ~(0x3); if ((0) != 0
) _v |= (((0)) * (((((uint32_t)(0x3)) - 1) & ((uint32_t)(
0x3))) ^ ((uint32_t)(0x3)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x7200))), ((_v)))); } while ( 0);
2765 AQ_WRITE_REG_BIT(sc, TPS_DATA_TC_ARB_MODE_REG, TPS_DATA_TC_ARB_MODE, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7100))))); _v &= ~((1 << 0)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7100))), ((_v)))); } while ( 0);
2766
2767 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
2768 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0xFFFF0000
); if ((0xfff0) != 0) _v |= (((0xfff0)) * (((((uint32_t)(0xFFFF0000
)) - 1) & ((uint32_t)(0xFFFF0000))) ^ ((uint32_t)(0xFFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7110 + (tc) * 4)))), ((_v)))); } while ( 0)
2769 TPS2_DATA_TCT_CREDIT_MAX, 0xfff0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0xFFFF0000
); if ((0xfff0) != 0) _v |= (((0xfff0)) * (((((uint32_t)(0xFFFF0000
)) - 1) & ((uint32_t)(0xFFFF0000))) ^ ((uint32_t)(0xFFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7110 + (tc) * 4)))), ((_v)))); } while ( 0);
2770 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0x7FFF
); if ((0x640) != 0) _v |= (((0x640)) * (((((uint32_t)(0x7FFF
)) - 1) & ((uint32_t)(0x7FFF))) ^ ((uint32_t)(0x7FFF))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7110
+ (tc) * 4)))), ((_v)))); } while ( 0)
2771 TPS2_DATA_TCT_WEIGHT, 0x640)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0x7FFF
); if ((0x640) != 0) _v |= (((0x640)) * (((((uint32_t)(0x7FFF
)) - 1) & ((uint32_t)(0x7FFF))) ^ ((uint32_t)(0x7FFF))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7110
+ (tc) * 4)))), ((_v)))); } while ( 0);
2772 } else {
2773 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0xFFF0000
); if ((0xfff) != 0) _v |= (((0xfff)) * (((((uint32_t)(0xFFF0000
)) - 1) & ((uint32_t)(0xFFF0000))) ^ ((uint32_t)(0xFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7110 + (tc) * 4)))), ((_v)))); } while ( 0)
2774 TPS_DATA_TCT_CREDIT_MAX, 0xfff)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0xFFF0000
); if ((0xfff) != 0) _v |= (((0xfff)) * (((((uint32_t)(0xFFF0000
)) - 1) & ((uint32_t)(0xFFF0000))) ^ ((uint32_t)(0xFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7110 + (tc) * 4)))), ((_v)))); } while ( 0);
2775 AQ_WRITE_REG_BIT(sc, TPS_DATA_TCT_REG(tc),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0x1FF
); if ((0x64) != 0) _v |= (((0x64)) * (((((uint32_t)(0x1FF)) -
1) & ((uint32_t)(0x1FF))) ^ ((uint32_t)(0x1FF)))); ((((sc
))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7110 + (
tc) * 4)))), ((_v)))); } while ( 0)
2776 TPS_DATA_TCT_WEIGHT, 0x64)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7110 + (tc) * 4)))))); _v &= ~(0x1FF
); if ((0x64) != 0) _v |= (((0x64)) * (((((uint32_t)(0x1FF)) -
1) & ((uint32_t)(0x1FF))) ^ ((uint32_t)(0x1FF)))); ((((sc
))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7110 + (
tc) * 4)))), ((_v)))); } while ( 0);
2777 }
2778 AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7210 + (tc) * 4)))))); _v &= ~(0xFFF0000
); if ((0x50) != 0) _v |= (((0x50)) * (((((uint32_t)(0xFFF0000
)) - 1) & ((uint32_t)(0xFFF0000))) ^ ((uint32_t)(0xFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7210 + (tc) * 4)))), ((_v)))); } while ( 0)
2779 TPS_DESC_TCT_CREDIT_MAX, 0x50)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7210 + (tc) * 4)))))); _v &= ~(0xFFF0000
); if ((0x50) != 0) _v |= (((0x50)) * (((((uint32_t)(0xFFF0000
)) - 1) & ((uint32_t)(0xFFF0000))) ^ ((uint32_t)(0xFFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7210 + (tc) * 4)))), ((_v)))); } while ( 0);
2780 AQ_WRITE_REG_BIT(sc, TPS_DESC_TCT_REG(tc),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7210 + (tc) * 4)))))); _v &= ~(0x1FF
); if ((0x1e) != 0) _v |= (((0x1e)) * (((((uint32_t)(0x1FF)) -
1) & ((uint32_t)(0x1FF))) ^ ((uint32_t)(0x1FF)))); ((((sc
))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7210 + (
tc) * 4)))), ((_v)))); } while ( 0)
2781 TPS_DESC_TCT_WEIGHT, 0x1e)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7210 + (tc) * 4)))))); _v &= ~(0x1FF
); if ((0x1e) != 0) _v |= (((0x1e)) * (((((uint32_t)(0x1FF)) -
1) & ((uint32_t)(0x1FF))) ^ ((uint32_t)(0x1FF)))); ((((sc
))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7210 + (
tc) * 4)))), ((_v)))); } while ( 0);
2782
2783 /* Tx buf size */
2784 tc = 0;
2785 buff_size = HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0) ? AQ2_HW_TXBUF_MAX128 : AQ_HW_TXBUF_MAX160;
2786 AQ_WRITE_REG_BIT(sc, TPB_TXB_BUFSIZE_REG(tc), TPB_TXB_BUFSIZE,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7910 + (tc) * 0x10)))))); _v &= ~((0xFF
)); if ((buff_size) != 0) _v |= (((buff_size)) * (((((uint32_t
)((0xFF))) - 1) & ((uint32_t)((0xFF)))) ^ ((uint32_t)((0xFF
))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7910 + (tc) * 0x10)))), ((_v)))); } while ( 0)
2787 buff_size)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7910 + (tc) * 0x10)))))); _v &= ~((0xFF
)); if ((buff_size) != 0) _v |= (((buff_size)) * (((((uint32_t
)((0xFF))) - 1) & ((uint32_t)((0xFF)))) ^ ((uint32_t)((0xFF
))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7910 + (tc) * 0x10)))), ((_v)))); } while ( 0);
2788 AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_HI,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7914 + (tc) * 0x10)))))); _v &= ~(0x1FFF0000
); if (((buff_size * (1024 / 32) * 66) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 66) / 100)) * (((((uint32_t)(0x1FFF0000
)) - 1) & ((uint32_t)(0x1FFF0000))) ^ ((uint32_t)(0x1FFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7914 + (tc) * 0x10)))), ((_v)))); } while ( 0)
2789 (buff_size * (1024 / 32) * 66) / 100)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7914 + (tc) * 0x10)))))); _v &= ~(0x1FFF0000
); if (((buff_size * (1024 / 32) * 66) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 66) / 100)) * (((((uint32_t)(0x1FFF0000
)) - 1) & ((uint32_t)(0x1FFF0000))) ^ ((uint32_t)(0x1FFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7914 + (tc) * 0x10)))), ((_v)))); } while ( 0);
2790 AQ_WRITE_REG_BIT(sc, TPB_TXB_THRESH_REG(tc), TPB_TXB_THRESH_LO,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7914 + (tc) * 0x10)))))); _v &= ~(0x1FFF
); if (((buff_size * (1024 / 32) * 50) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 50) / 100)) * (((((uint32_t)(0x1FFF
)) - 1) & ((uint32_t)(0x1FFF))) ^ ((uint32_t)(0x1FFF))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7914
+ (tc) * 0x10)))), ((_v)))); } while ( 0)
2791 (buff_size * (1024 / 32) * 50) / 100)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7914 + (tc) * 0x10)))))); _v &= ~(0x1FFF
); if (((buff_size * (1024 / 32) * 50) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 50) / 100)) * (((((uint32_t)(0x1FFF
)) - 1) & ((uint32_t)(0x1FFF))) ^ ((uint32_t)(0x1FFF))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x7914
+ (tc) * 0x10)))), ((_v)))); } while ( 0);
2792
2793 /* QoS Rx buf size per TC */
2794 tc = 0;
2795 buff_size = HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0) ? AQ2_HW_RXBUF_MAX192 : AQ_HW_RXBUF_MAX320;
2796 AQ_WRITE_REG_BIT(sc, RPB_RXB_BUFSIZE_REG(tc), RPB_RXB_BUFSIZE,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5710 + (tc) * 0x10)))))); _v &= ~(0x1FF
); if ((buff_size) != 0) _v |= (((buff_size)) * (((((uint32_t
)(0x1FF)) - 1) & ((uint32_t)(0x1FF))) ^ ((uint32_t)(0x1FF
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x5710 + (tc) * 0x10)))), ((_v)))); } while ( 0)
2797 buff_size)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5710 + (tc) * 0x10)))))); _v &= ~(0x1FF
); if ((buff_size) != 0) _v |= (((buff_size)) * (((((uint32_t
)(0x1FF)) - 1) & ((uint32_t)(0x1FF))) ^ ((uint32_t)(0x1FF
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x5710 + (tc) * 0x10)))), ((_v)))); } while ( 0);
2798 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5714 + (tc) * 0x10)))))); _v &= ~((1U
<< 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((
1U << 31))) - 1) & ((uint32_t)((1U << 31)))) ^
((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x5714 + (tc) * 0x10)))), ((_v))));
} while ( 0);
2799 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_HI,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5714 + (tc) * 0x10)))))); _v &= ~(0x3FFF0000
); if (((buff_size * (1024 / 32) * 66) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 66) / 100)) * (((((uint32_t)(0x3FFF0000
)) - 1) & ((uint32_t)(0x3FFF0000))) ^ ((uint32_t)(0x3FFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x5714 + (tc) * 0x10)))), ((_v)))); } while ( 0)
2800 (buff_size * (1024 / 32) * 66) / 100)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5714 + (tc) * 0x10)))))); _v &= ~(0x3FFF0000
); if (((buff_size * (1024 / 32) * 66) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 66) / 100)) * (((((uint32_t)(0x3FFF0000
)) - 1) & ((uint32_t)(0x3FFF0000))) ^ ((uint32_t)(0x3FFF0000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x5714 + (tc) * 0x10)))), ((_v)))); } while ( 0);
2801 AQ_WRITE_REG_BIT(sc, RPB_RXB_XOFF_REG(tc), RPB_RXB_XOFF_THRESH_LO,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5714 + (tc) * 0x10)))))); _v &= ~(0x3FFF
); if (((buff_size * (1024 / 32) * 50) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 50) / 100)) * (((((uint32_t)(0x3FFF
)) - 1) & ((uint32_t)(0x3FFF))) ^ ((uint32_t)(0x3FFF))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5714
+ (tc) * 0x10)))), ((_v)))); } while ( 0)
2802 (buff_size * (1024 / 32) * 50) / 100)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5714 + (tc) * 0x10)))))); _v &= ~(0x3FFF
); if (((buff_size * (1024 / 32) * 50) / 100) != 0) _v |= (((
(buff_size * (1024 / 32) * 50) / 100)) * (((((uint32_t)(0x3FFF
)) - 1) & ((uint32_t)(0x3FFF))) ^ ((uint32_t)(0x3FFF))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5714
+ (tc) * 0x10)))), ((_v)))); } while ( 0);
2803
2804 /* QoS 802.1p priority -> TC mapping */
2805 int i_priority;
2806 for (i_priority = 0; i_priority < 8; i_priority++) {
2807 AQ_WRITE_REG_BIT(sc, RPF_RPB_RX_TC_UPT_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54c4))))); _v &= ~((0x00000007 <<
((i_priority) * 4))); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((0x00000007 << ((i_priority) * 4)))) - 1) & ((uint32_t
)((0x00000007 << ((i_priority) * 4))))) ^ ((uint32_t)((
0x00000007 << ((i_priority) * 4)))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), (((0x54c4))), ((_v)))); } while
( 0)
2808 RPF_RPB_RX_TC_UPT_MASK(i_priority), 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54c4))))); _v &= ~((0x00000007 <<
((i_priority) * 4))); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((0x00000007 << ((i_priority) * 4)))) - 1) & ((uint32_t
)((0x00000007 << ((i_priority) * 4))))) ^ ((uint32_t)((
0x00000007 << ((i_priority) * 4)))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), (((0x54c4))), ((_v)))); } while
( 0);
2809 }
2810}
2811
2812int
2813aq_init_rss(struct aq_softc *sc)
2814{
2815 uint32_t rss_key[AQ_RSS_KEYSIZE40 / sizeof(uint32_t)];
2816 uint32_t redir;
2817 int bits, queue;
2818 int error;
2819 int i;
2820
2821 if (sc->sc_nqueues == 1)
2822 return 0;
2823
2824 /* rss key is composed of 32 bit registers */
2825 stoeplitz_to_key(rss_key, sizeof(rss_key));
2826 for (i = 0; i < nitems(rss_key)(sizeof((rss_key)) / sizeof((rss_key)[0])); i++) {
2827 AQ_WRITE_REG(sc, RPF_RSS_KEY_WR_DATA_REG, htole32(rss_key[i]))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x54d4)),
((((__uint32_t)(rss_key[i]))))));
2828 AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, RPF_RSS_KEY_ADDR,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54d0))))); _v &= ~(0x1f); if (((sizeof
((rss_key)) / sizeof((rss_key)[0])) - 1 - i) != 0) _v |= ((((
sizeof((rss_key)) / sizeof((rss_key)[0])) - 1 - i)) * (((((uint32_t
)(0x1f)) - 1) & ((uint32_t)(0x1f))) ^ ((uint32_t)(0x1f)))
); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x54d0
))), ((_v)))); } while ( 0)
2829 nitems(rss_key) - 1 - i)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54d0))))); _v &= ~(0x1f); if (((sizeof
((rss_key)) / sizeof((rss_key)[0])) - 1 - i) != 0) _v |= ((((
sizeof((rss_key)) / sizeof((rss_key)[0])) - 1 - i)) * (((((uint32_t
)(0x1f)) - 1) & ((uint32_t)(0x1f))) ^ ((uint32_t)(0x1f)))
); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (((0x54d0
))), ((_v)))); } while ( 0);
2830 AQ_WRITE_REG_BIT(sc, RPF_RSS_KEY_ADDR_REG, RPF_RSS_KEY_WR_EN,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54d0))))); _v &= ~((1 << 5)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 5))) - 1
) & ((uint32_t)((1 << 5)))) ^ ((uint32_t)((1 <<
5))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x54d0))), ((_v)))); } while ( 0)
2831 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54d0))))); _v &= ~((1 << 5)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 5))) - 1
) & ((uint32_t)((1 << 5)))) ^ ((uint32_t)((1 <<
5))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x54d0))), ((_v)))); } while ( 0);
2832 WAIT_FOR((AQ_READ_REG(sc, RPF_RSS_KEY_ADDR_REG) &do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x54d0)))) & (1 << 5)) ==
0)) && _n != 0; --_n) { (*delay_func)((1000)); } if (
(&error != ((void *)0))) { if (_n == 0) *(&error) = 60
; else *(&error) = 0; } } while ( 0)
2833 RPF_RSS_KEY_WR_EN) == 0, 1000, 10, &error)do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x54d0)))) & (1 << 5)) ==
0)) && _n != 0; --_n) { (*delay_func)((1000)); } if (
(&error != ((void *)0))) { if (_n == 0) *(&error) = 60
; else *(&error) = 0; } } while ( 0);
2834 if (error != 0) {
2835 printf(": timed out setting rss key\n");
2836 return error;
2837 }
2838 }
2839
2840 /*
2841 * the redirection table has 64 entries, each entry is a 3 bit
2842 * queue number, packed into a 16 bit register, so there are 12
2843 * registers to program.
2844 */
2845 bits = 0;
2846 redir = 0;
2847 queue = 0;
2848 for (i = 0; i < AQ_RSS_REDIR_ENTRIES12; i++) {
2849 while (bits < 16) {
2850 redir |= (queue << bits);
2851 bits += 3;
2852 queue++;
2853 if (queue == sc->sc_nqueues)
2854 queue = 0;
2855 }
2856
2857 AQ_WRITE_REG(sc, RPF_RSS_REDIR_WR_DATA_REG, htole16(redir))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x54e4)),
((((__uint16_t)(redir))))));
2858 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG, RPF_RSS_REDIR_ADDR,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54e0))))); _v &= ~(0xf); if ((i) != 0
) _v |= (((i)) * (((((uint32_t)(0xf)) - 1) & ((uint32_t)(
0xf))) ^ ((uint32_t)(0xf)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x54e0))), ((_v)))); } while ( 0)
2859 i)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54e0))))); _v &= ~(0xf); if ((i) != 0
) _v |= (((i)) * (((((uint32_t)(0xf)) - 1) & ((uint32_t)(
0xf))) ^ ((uint32_t)(0xf)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x54e0))), ((_v)))); } while ( 0);
2860 AQ_WRITE_REG_BIT(sc, RPF_RSS_REDIR_ADDR_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54e0))))); _v &= ~((1 << 4)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 4))) - 1
) & ((uint32_t)((1 << 4)))) ^ ((uint32_t)((1 <<
4))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x54e0))), ((_v)))); } while ( 0)
2861 RPF_RSS_REDIR_WR_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x54e0))))); _v &= ~((1 << 4)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 4))) - 1
) & ((uint32_t)((1 << 4)))) ^ ((uint32_t)((1 <<
4))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x54e0))), ((_v)))); } while ( 0);
2862 WAIT_FOR((AQ_READ_REG(sc, RPF_RSS_REDIR_ADDR_REG) &do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x54e0)))) & (1 << 4)) ==
0)) && _n != 0; --_n) { (*delay_func)((1000)); } if (
(&error != ((void *)0))) { if (_n == 0) *(&error) = 60
; else *(&error) = 0; } } while ( 0)
2863 RPF_RSS_REDIR_WR_EN) == 0, 1000, 10, &error)do { unsigned int _n; for (_n = 10; (!(((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), ((0x54e0)))) & (1 << 4)) ==
0)) && _n != 0; --_n) { (*delay_func)((1000)); } if (
(&error != ((void *)0))) { if (_n == 0) *(&error) = 60
; else *(&error) = 0; } } while ( 0);
2864 if (error != 0) {
2865 printf(": timed out setting rss table\n");
2866 return error;
2867 }
2868 redir >>= 16;
2869 bits -= 16;
2870 }
2871
2872 return 0;
2873}
2874
2875void
2876aq_txring_reset(struct aq_softc *sc, struct aq_txring *tx, int start)
2877{
2878 daddr_t paddr;
2879
2880 tx->tx_prod = 0;
2881 tx->tx_cons = 0;
2882
2883 /* empty slots? */
2884
2885 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(tx->tx_q), TX_DMA_DESC_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c08 + (tx->tx_q) * 0x40)))))); _v &=
~(0x80000000); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0x80000000
)) - 1) & ((uint32_t)(0x80000000))) ^ ((uint32_t)(0x80000000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7c08 + (tx->tx_q) * 0x40)))), ((_v)))); } while ( 0);
2886
2887 if (start == 0)
2888 return;
2889
2890 paddr = AQ_DMA_DVA(&tx->tx_mem)((&tx->tx_mem)->aqm_map->dm_segs[0].ds_addr);
2891 AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(tx->tx_q), paddr)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x7c00 +
(tx->tx_q) * 0x40))), ((paddr))));
2892 AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(tx->tx_q),(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x7c04 +
(tx->tx_q) * 0x40))), ((paddr >> 32))))
2893 paddr >> 32)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x7c04 +
(tx->tx_q) * 0x40))), ((paddr >> 32))));
2894
2895 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(tx->tx_q), TX_DMA_DESC_LEN,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c08 + (tx->tx_q) * 0x40)))))); _v &=
~(0x00000FF8); if ((2048 / 8) != 0) _v |= (((2048 / 8)) * ((
(((uint32_t)(0x00000FF8)) - 1) & ((uint32_t)(0x00000FF8))
) ^ ((uint32_t)(0x00000FF8)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x7c08 + (tx->tx_q) * 0x40)))), (
(_v)))); } while ( 0)
2896 AQ_TXD_NUM / 8)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c08 + (tx->tx_q) * 0x40)))))); _v &=
~(0x00000FF8); if ((2048 / 8) != 0) _v |= (((2048 / 8)) * ((
(((uint32_t)(0x00000FF8)) - 1) & ((uint32_t)(0x00000FF8))
) ^ ((uint32_t)(0x00000FF8)))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), ((((0x7c08 + (tx->tx_q) * 0x40)))), (
(_v)))); } while ( 0);
2897
2898 tx->tx_prod = AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(tx->tx_q))(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (((0x7c10 + (
tx->tx_q) * 0x40)))));
2899 tx->tx_cons = tx->tx_prod;
2900 AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(tx->tx_q), 0)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x7c18 +
(tx->tx_q) * 0x40))), ((0))));
2901
2902 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(tx->tx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((tx->tx_q) / 2) * 4)))))); _v
&= ~((0x1FU << (((tx->tx_q) & 1) ? 16 : 24)
)); if ((tx->tx_irq) != 0) _v |= (((tx->tx_irq)) * ((((
(uint32_t)((0x1FU << (((tx->tx_q) & 1) ? 16 : 24
)))) - 1) & ((uint32_t)((0x1FU << (((tx->tx_q) &
1) ? 16 : 24))))) ^ ((uint32_t)((0x1FU << (((tx->tx_q
) & 1) ? 16 : 24)))))); ((((sc))->sc_iot)->write_4(
(((sc))->sc_ioh), ((((0x2100 + ((tx->tx_q) / 2) * 4))))
, ((_v)))); } while ( 0)
2903 AQ_INTR_IRQ_MAP_TX_IRQMAP(tx->tx_q), tx->tx_irq)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((tx->tx_q) / 2) * 4)))))); _v
&= ~((0x1FU << (((tx->tx_q) & 1) ? 16 : 24)
)); if ((tx->tx_irq) != 0) _v |= (((tx->tx_irq)) * ((((
(uint32_t)((0x1FU << (((tx->tx_q) & 1) ? 16 : 24
)))) - 1) & ((uint32_t)((0x1FU << (((tx->tx_q) &
1) ? 16 : 24))))) ^ ((uint32_t)((0x1FU << (((tx->tx_q
) & 1) ? 16 : 24)))))); ((((sc))->sc_iot)->write_4(
(((sc))->sc_ioh), ((((0x2100 + ((tx->tx_q) / 2) * 4))))
, ((_v)))); } while ( 0);
2904 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(tx->tx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((tx->tx_q) / 2) * 4)))))); _v
&= ~((1U << (((tx->tx_q) & 1) ? 23 : 31)));
if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1U << (((
tx->tx_q) & 1) ? 23 : 31)))) - 1) & ((uint32_t)((1U
<< (((tx->tx_q) & 1) ? 23 : 31))))) ^ ((uint32_t
)((1U << (((tx->tx_q) & 1) ? 23 : 31)))))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x2100 +
((tx->tx_q) / 2) * 4)))), ((_v)))); } while ( 0)
2905 AQ_INTR_IRQ_MAP_TX_EN(tx->tx_q), 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((tx->tx_q) / 2) * 4)))))); _v
&= ~((1U << (((tx->tx_q) & 1) ? 23 : 31)));
if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1U << (((
tx->tx_q) & 1) ? 23 : 31)))) - 1) & ((uint32_t)((1U
<< (((tx->tx_q) & 1) ? 23 : 31))))) ^ ((uint32_t
)((1U << (((tx->tx_q) & 1) ? 23 : 31)))))); ((((
sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x2100 +
((tx->tx_q) / 2) * 4)))), ((_v)))); } while ( 0);
2906
2907 AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(tx->tx_q), TX_DMA_DESC_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x7c08 + (tx->tx_q) * 0x40)))))); _v &=
~(0x80000000); if ((1) != 0) _v |= (((1)) * (((((uint32_t)(0x80000000
)) - 1) & ((uint32_t)(0x80000000))) ^ ((uint32_t)(0x80000000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x7c08 + (tx->tx_q) * 0x40)))), ((_v)))); } while ( 0);
2908
2909 AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(tx->tx_q), TDM_DCAD_CPUID, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8400 + (tx->tx_q) * 4)))))); _v &=
~(0x7F); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0x7F)) -
1) & ((uint32_t)(0x7F))) ^ ((uint32_t)(0x7F)))); ((((sc)
)->sc_iot)->write_4((((sc))->sc_ioh), ((((0x8400 + (
tx->tx_q) * 4)))), ((_v)))); } while ( 0);
2910 AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(tx->tx_q), TDM_DCAD_CPUID_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x8400 + (tx->tx_q) * 4)))))); _v &=
~(0x80000000); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0x80000000
)) - 1) & ((uint32_t)(0x80000000))) ^ ((uint32_t)(0x80000000
)))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh), (
(((0x8400 + (tx->tx_q) * 4)))), ((_v)))); } while ( 0);
2911}
2912
2913void
2914aq_rxring_reset(struct aq_softc *sc, struct aq_rxring *rx, int start)
2915{
2916 daddr_t paddr;
2917 int strip;
2918
2919 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), RX_DMA_DESC_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((1U << 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1U << 31))) - 1) & ((uint32_t)((1U << 31))
)) ^ ((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20
)))), ((_v)))); } while ( 0);
2920 /* drain */
2921
2922 if (start == 0)
2923 return;
2924
2925 paddr = AQ_DMA_DVA(&rx->rx_mem)((&rx->rx_mem)->aqm_map->dm_segs[0].ds_addr);
2926 AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(rx->rx_q), paddr)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5b00 +
(rx->rx_q) * 0x20))), ((paddr))));
2927 AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(rx->rx_q),(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5b04 +
(rx->rx_q) * 0x20))), ((paddr >> 32))))
2928 paddr >> 32)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5b04 +
(rx->rx_q) * 0x20))), ((paddr >> 32))));
2929
2930 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), RX_DMA_DESC_LEN,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((0x3FF << 3)); if ((2048 / 8) != 0) _v |= (((2048 / 8
)) * (((((uint32_t)((0x3FF << 3))) - 1) & ((uint32_t
)((0x3FF << 3)))) ^ ((uint32_t)((0x3FF << 3)))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5b08
+ (rx->rx_q) * 0x20)))), ((_v)))); } while ( 0)
2931 AQ_RXD_NUM / 8)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((0x3FF << 3)); if ((2048 / 8) != 0) _v |= (((2048 / 8
)) * (((((uint32_t)((0x3FF << 3))) - 1) & ((uint32_t
)((0x3FF << 3)))) ^ ((uint32_t)((0x3FF << 3)))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5b08
+ (rx->rx_q) * 0x20)))), ((_v)))); } while ( 0);
2932
2933 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b18 + (rx->rx_q) * 0x20)))))); _v &=
~(0x000F); if (((1 << 11) / 1024) != 0) _v |= ((((1 <<
11) / 1024)) * (((((uint32_t)(0x000F)) - 1) & ((uint32_t
)(0x000F))) ^ ((uint32_t)(0x000F)))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x5b18 + (rx->rx_q) * 0x20
)))), ((_v)))); } while ( 0)
2934 RX_DMA_DESC_BUFSIZE_DATA, MCLBYTES / 1024)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b18 + (rx->rx_q) * 0x20)))))); _v &=
~(0x000F); if (((1 << 11) / 1024) != 0) _v |= ((((1 <<
11) / 1024)) * (((((uint32_t)(0x000F)) - 1) & ((uint32_t
)(0x000F))) ^ ((uint32_t)(0x000F)))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x5b18 + (rx->rx_q) * 0x20
)))), ((_v)))); } while ( 0);
2935 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b18 + (rx->rx_q) * 0x20)))))); _v &=
~(0x0FF0); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0x0FF0
)) - 1) & ((uint32_t)(0x0FF0))) ^ ((uint32_t)(0x0FF0))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5b18
+ (rx->rx_q) * 0x20)))), ((_v)))); } while ( 0)
2936 RX_DMA_DESC_BUFSIZE_HDR, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b18 + (rx->rx_q) * 0x20)))))); _v &=
~(0x0FF0); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0x0FF0
)) - 1) & ((uint32_t)(0x0FF0))) ^ ((uint32_t)(0x0FF0))));
((((sc))->sc_iot)->write_4((((sc))->sc_ioh), ((((0x5b18
+ (rx->rx_q) * 0x20)))), ((_v)))); } while ( 0);
2937 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((1 << 28)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1 << 28))) - 1) & ((uint32_t)((1 << 28))))
^ ((uint32_t)((1 << 28))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20
)))), ((_v)))); } while ( 0)
2938 RX_DMA_DESC_HEADER_SPLIT, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((1 << 28)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1 << 28))) - 1) & ((uint32_t)((1 << 28))))
^ ((uint32_t)((1 << 28))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20
)))), ((_v)))); } while ( 0);
2939
2940#if NVLAN1 > 0
2941 strip = 1;
2942#else
2943 strip = 0;
2944#endif
2945 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((1 << 29)); if ((strip) != 0) _v |= (((strip)) * (((
((uint32_t)((1 << 29))) - 1) & ((uint32_t)((1 <<
29)))) ^ ((uint32_t)((1 << 29))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x5b08 + (rx->rx_q)
* 0x20)))), ((_v)))); } while ( 0)
2946 RX_DMA_DESC_VLAN_STRIP, strip)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((1 << 29)); if ((strip) != 0) _v |= (((strip)) * (((
((uint32_t)((1 << 29))) - 1) & ((uint32_t)((1 <<
29)))) ^ ((uint32_t)((1 << 29))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x5b08 + (rx->rx_q)
* 0x20)))), ((_v)))); } while ( 0);
2947
2948 rx->rx_cons = AQ_READ_REG(sc, RX_DMA_DESC_HEAD_PTR_REG(rx->rx_q))(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (((0x5b0c + (
rx->rx_q) * 0x20))))) &
2949 RX_DMA_DESC_HEAD_PTR0xFFF;
2950 AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(rx->rx_q), rx->rx_cons)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5b10 +
(rx->rx_q) * 0x20))), ((rx->rx_cons))));
2951 rx->rx_prod = rx->rx_cons;
2952
2953 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((rx->rx_q) / 2) * 4)))))); _v
&= ~((0x1FU << (((rx->rx_q) & 1) ? 0 : 8)))
; if ((rx->rx_irq) != 0) _v |= (((rx->rx_irq)) * (((((uint32_t
)((0x1FU << (((rx->rx_q) & 1) ? 0 : 8)))) - 1) &
((uint32_t)((0x1FU << (((rx->rx_q) & 1) ? 0 : 8
))))) ^ ((uint32_t)((0x1FU << (((rx->rx_q) & 1) ?
0 : 8)))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), ((((0x2100 + ((rx->rx_q) / 2) * 4)))), ((_v)))); } while
( 0)
2954 AQ_INTR_IRQ_MAP_RX_IRQMAP(rx->rx_q), rx->rx_irq)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((rx->rx_q) / 2) * 4)))))); _v
&= ~((0x1FU << (((rx->rx_q) & 1) ? 0 : 8)))
; if ((rx->rx_irq) != 0) _v |= (((rx->rx_irq)) * (((((uint32_t
)((0x1FU << (((rx->rx_q) & 1) ? 0 : 8)))) - 1) &
((uint32_t)((0x1FU << (((rx->rx_q) & 1) ? 0 : 8
))))) ^ ((uint32_t)((0x1FU << (((rx->rx_q) & 1) ?
0 : 8)))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), ((((0x2100 + ((rx->rx_q) / 2) * 4)))), ((_v)))); } while
( 0);
2955 AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((rx->rx_q) / 2) * 4)))))); _v
&= ~((1U << (((rx->rx_q) & 1) ? 7 : 15))); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1U << (((rx->
rx_q) & 1) ? 7 : 15)))) - 1) & ((uint32_t)((1U <<
(((rx->rx_q) & 1) ? 7 : 15))))) ^ ((uint32_t)((1U <<
(((rx->rx_q) & 1) ? 7 : 15)))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x2100 + ((rx->rx_q
) / 2) * 4)))), ((_v)))); } while ( 0)
2956 AQ_INTR_IRQ_MAP_RX_EN(rx->rx_q), 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x2100 + ((rx->rx_q) / 2) * 4)))))); _v
&= ~((1U << (((rx->rx_q) & 1) ? 7 : 15))); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1U << (((rx->
rx_q) & 1) ? 7 : 15)))) - 1) & ((uint32_t)((1U <<
(((rx->rx_q) & 1) ? 7 : 15))))) ^ ((uint32_t)((1U <<
(((rx->rx_q) & 1) ? 7 : 15)))))); ((((sc))->sc_iot
)->write_4((((sc))->sc_ioh), ((((0x2100 + ((rx->rx_q
) / 2) * 4)))), ((_v)))); } while ( 0);
2957
2958 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~(0xFF); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0xFF)) -
1) & ((uint32_t)(0xFF))) ^ ((uint32_t)(0xFF)))); ((((sc)
)->sc_iot)->write_4((((sc))->sc_ioh), ((((0x6100 + (
rx->rx_q) * 4)))), ((_v)))); } while ( 0)
2959 RX_DMA_DCAD_CPUID, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~(0xFF); if ((0) != 0) _v |= (((0)) * (((((uint32_t)(0xFF)) -
1) & ((uint32_t)(0xFF))) ^ ((uint32_t)(0xFF)))); ((((sc)
)->sc_iot)->write_4((((sc))->sc_ioh), ((((0x6100 + (
rx->rx_q) * 4)))), ((_v)))); } while ( 0);
2960 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~((1U << 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1U << 31))) - 1) & ((uint32_t)((1U << 31))
)) ^ ((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x6100 + (rx->rx_q) * 4))
)), ((_v)))); } while ( 0)
2961 RX_DMA_DCAD_DESC_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~((1U << 31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1U << 31))) - 1) & ((uint32_t)((1U << 31))
)) ^ ((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x6100 + (rx->rx_q) * 4))
)), ((_v)))); } while ( 0);
2962 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~((1 << 30)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1 << 30))) - 1) & ((uint32_t)((1 << 30))))
^ ((uint32_t)((1 << 30))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x6100 + (rx->rx_q) * 4))
)), ((_v)))); } while ( 0)
2963 RX_DMA_DCAD_HEADER_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~((1 << 30)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1 << 30))) - 1) & ((uint32_t)((1 << 30))))
^ ((uint32_t)((1 << 30))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x6100 + (rx->rx_q) * 4))
)), ((_v)))); } while ( 0);
2964 AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(rx->rx_q),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~((1 << 29)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1 << 29))) - 1) & ((uint32_t)((1 << 29))))
^ ((uint32_t)((1 << 29))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x6100 + (rx->rx_q) * 4))
)), ((_v)))); } while ( 0)
2965 RX_DMA_DCAD_PAYLOAD_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x6100 + (rx->rx_q) * 4)))))); _v &=
~((1 << 29)); if ((0) != 0) _v |= (((0)) * (((((uint32_t
)((1 << 29))) - 1) & ((uint32_t)((1 << 29))))
^ ((uint32_t)((1 << 29))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x6100 + (rx->rx_q) * 4))
)), ((_v)))); } while ( 0);
2966
2967 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(rx->rx_q), RX_DMA_DESC_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20)))))); _v &=
~((1U << 31)); if ((1) != 0) _v |= (((1)) * (((((uint32_t
)((1U << 31))) - 1) & ((uint32_t)((1U << 31))
)) ^ ((uint32_t)((1U << 31))))); ((((sc))->sc_iot)->
write_4((((sc))->sc_ioh), ((((0x5b08 + (rx->rx_q) * 0x20
)))), ((_v)))); } while ( 0);
2968}
2969
2970static inline unsigned int
2971aq_rx_fill_slots(struct aq_softc *sc, struct aq_rxring *rx, uint nslots)
2972{
2973 struct aq_rx_desc_read *ring, *rd;
2974 struct aq_slot *as;
2975 struct mbuf *m;
2976 uint p, fills;
2977
2978 ring = AQ_DMA_KVA(&rx->rx_mem)((void *)(&rx->rx_mem)->aqm_kva);
2979 p = rx->rx_prod;
2980
2981 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x08))
2982 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x08));
2983
2984 for (fills = 0; fills < nslots; fills++) {
2985 as = &rx->rx_slots[p];
2986 rd = &ring[p];
2987
2988 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES + ETHER_ALIGN)m_clget((((void *)0)), (0x0002), ((1 << 11) + 2));
2989 if (m == NULL((void *)0))
2990 break;
2991
2992 m->m_datam_hdr.mh_data += (m->m_extM_dat.MH.MH_dat.MH_ext.ext_size - (MCLBYTES(1 << 11) + ETHER_ALIGN2));
2993 m->m_datam_hdr.mh_data += ETHER_ALIGN2;
2994 m->m_lenm_hdr.mh_len = m->m_pkthdrM_dat.MH.MH_pkthdr.len = MCLBYTES(1 << 11);
2995
2996 if (bus_dmamap_load_mbuf(sc->sc_dmat, as->as_map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
as->as_map), (m), (0x0001))
2997 BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
as->as_map), (m), (0x0001)) != 0) {
2998 m_freem(m);
2999 break;
3000 }
3001 as->as_m = m;
3002
3003 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x01))
3004 as->as_map->dm_mapsize, BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x01));
3005 htolem64(&rd->buf_addr, as->as_map->dm_segs[0].ds_addr)(*(__uint64_t *)(&rd->buf_addr) = ((__uint64_t)(as->
as_map->dm_segs[0].ds_addr)));
3006 rd->hdr_addr = 0;
3007 p++;
3008 if (p == AQ_RXD_NUM2048)
3009 p = 0;
3010 }
3011
3012 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x04))
3013 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x04));
3014
3015 rx->rx_prod = p;
3016 AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(rx->rx_q), rx->rx_prod)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x5b10 +
(rx->rx_q) * 0x20))), ((rx->rx_prod))));
3017 return (nslots - fills);
3018}
3019
3020int
3021aq_rx_fill(struct aq_softc *sc, struct aq_rxring *rx)
3022{
3023 u_int slots;
3024
3025 slots = if_rxr_get(&rx->rx_rxr, AQ_RXD_NUM2048);
3026 if (slots == 0)
3027 return 1;
3028
3029 slots = aq_rx_fill_slots(sc, rx, slots);
3030 if_rxr_put(&rx->rx_rxr, slots)do { (&rx->rx_rxr)->rxr_alive -= (slots); } while (
0);
3031 return 0;
3032}
3033
3034void
3035aq_refill(void *xq)
3036{
3037 struct aq_queues *q = xq;
3038 struct aq_softc *sc = q->q_sc;
3039
3040 aq_rx_fill(sc, &q->q_rx);
3041
3042 if (if_rxr_inuse(&q->q_rx.rx_rxr)((&q->q_rx.rx_rxr)->rxr_alive) == 0)
3043 timeout_add(&q->q_rx.rx_refill, 1);
3044}
3045
3046void
3047aq_rxeof(struct aq_softc *sc, struct aq_rxring *rx)
3048{
3049 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3050 struct aq_rx_desc_wb *rxd;
3051 struct aq_rx_desc_wb *ring;
3052 struct aq_slot *as;
3053 uint32_t end, idx;
3054 uint16_t pktlen, status;
3055 uint32_t rxd_type;
3056 struct mbuf *m, *mb;
3057 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
3058 int rxfree;
3059
3060 if (!ISSET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) & (0x40)))
3061 return;
3062
3063 end = AQ_READ_REG(sc, RX_DMA_DESC_HEAD_PTR_REG(rx->rx_q))(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (((0x5b0c + (
rx->rx_q) * 0x20))))) &
3064 RX_DMA_DESC_HEAD_PTR0xFFF;
3065
3066 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x02))
3067 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x02));
3068
3069 rxfree = 0;
3070 idx = rx->rx_cons;
3071 ring = AQ_DMA_KVA(&rx->rx_mem)((void *)(&rx->rx_mem)->aqm_kva);
3072 while (idx != end) {
3073 rxd = &ring[idx];
3074 as = &rx->rx_slots[idx];
3075
3076 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x02))
3077 as->as_map->dm_mapsize, BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x02));
3078 bus_dmamap_unload(sc->sc_dmat, as->as_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (as->
as_map));
3079
3080 status = lemtoh16(&rxd->status)((__uint16_t)(*(__uint16_t *)(&rxd->status)));
3081 if ((status & AQ_RXDESC_STATUS_DD(1 << 0)) == 0)
3082 break;
3083
3084 rxfree++;
3085 mb = as->as_m;
3086 as->as_m = NULL((void *)0);
3087
3088 pktlen = lemtoh16(&rxd->pkt_len)((__uint16_t)(*(__uint16_t *)(&rxd->pkt_len)));
3089 rxd_type = lemtoh32(&rxd->type)((__uint32_t)(*(__uint32_t *)(&rxd->type)));
3090 if ((rxd_type & AQ_RXDESC_TYPE_RSSTYPE0x000f) != 0) {
3091 mb->m_pkthdrM_dat.MH.MH_pkthdr.ph_flowid = lemtoh32(&rxd->rss_hash)((__uint32_t)(*(__uint32_t *)(&rxd->rss_hash)));
3092 mb->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_FLOWID0x4000;
3093 }
3094
3095 mb->m_pkthdrM_dat.MH.MH_pkthdr.len = 0;
3096 mb->m_nextm_hdr.mh_next = NULL((void *)0);
3097 *rx->rx_m_tail = mb;
3098 rx->rx_m_tail = &mb->m_nextm_hdr.mh_next;
3099
3100 m = rx->rx_m_head;
3101
3102#if NVLAN1 > 0
3103 if (rxd_type & (AQ_RXDESC_TYPE_VLAN(1 << 9) | AQ_RXDESC_TYPE_VLAN2(1 << 10))) {
3104 m->m_pkthdrM_dat.MH.MH_pkthdr.ether_vtag = lemtoh16(&rxd->vlan)((__uint16_t)(*(__uint16_t *)(&rxd->vlan)));
3105 m->m_flagsm_hdr.mh_flags |= M_VLANTAG0x0020;
3106 }
3107#endif
3108
3109 if ((rxd_type & AQ_RXDESC_TYPE_V4_SUM(1 << 19)) &&
3110 ((status & AQ_RXDESC_STATUS_V4_SUM_NG(1 << 3)) == 0))
3111 m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK0x0008;
3112
3113 if ((rxd_type & AQ_RXDESC_TYPE_L4_SUM(1 << 20)) &&
3114 (status & AQ_RXDESC_STATUS_L4_SUM_OK(1 << 5)))
3115 m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK0x0080 |
3116 M_TCP_CSUM_IN_OK0x0020;
3117
3118 if ((status & AQ_RXDESC_STATUS_MACERR(1 << 2)) ||
3119 (rxd_type & AQ_RXDESC_TYPE_DMA_ERR(1 << 12))) {
3120 printf("%s:rx: rx error (status %x type %x)\n",
3121 DEVNAME(sc)((sc)->sc_dev.dv_xname), status, rxd_type);
3122 rx->rx_m_error = 1;
3123 }
3124
3125 if (status & AQ_RXDESC_STATUS_EOP(1 << 1)) {
3126 mb->m_lenm_hdr.mh_len = pktlen - m->m_pkthdrM_dat.MH.MH_pkthdr.len;
3127 m->m_pkthdrM_dat.MH.MH_pkthdr.len = pktlen;
3128 if (rx->rx_m_error != 0) {
3129 ifp->if_ierrorsif_data.ifi_ierrors++;
3130 m_freem(m);
3131 } else {
3132 ml_enqueue(&ml, m);
3133 }
3134
3135 rx->rx_m_head = NULL((void *)0);
3136 rx->rx_m_tail = &rx->rx_m_head;
3137 rx->rx_m_error = 0;
3138 } else {
3139 mb->m_lenm_hdr.mh_len = MCLBYTES(1 << 11);
3140 m->m_pkthdrM_dat.MH.MH_pkthdr.len += mb->m_lenm_hdr.mh_len;
3141 }
3142
3143 idx++;
3144 if (idx == AQ_RXD_NUM2048)
3145 idx = 0;
3146 }
3147
3148 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x01))
3149 AQ_DMA_LEN(&rx->rx_mem), BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x01));
3150
3151 rx->rx_cons = idx;
3152
3153 if (rxfree > 0) {
3154 if_rxr_put(&rx->rx_rxr, rxfree)do { (&rx->rx_rxr)->rxr_alive -= (rxfree); } while (
0);
3155 if (ifiq_input(rx->rx_ifiq, &ml))
3156 if_rxr_livelocked(&rx->rx_rxr);
3157
3158 aq_rx_fill(sc, rx);
3159 if (if_rxr_inuse(&rx->rx_rxr)((&rx->rx_rxr)->rxr_alive) == 0)
3160 timeout_add(&rx->rx_refill, 1);
3161 }
3162}
3163
3164void
3165aq_txeof(struct aq_softc *sc, struct aq_txring *tx)
3166{
3167 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3168 struct aq_slot *as;
3169 uint32_t idx, end, free;
3170
3171 if (!ISSET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) & (0x40)))
3172 return;
3173
3174 idx = tx->tx_cons;
3175 end = AQ_READ_REG(sc, TX_DMA_DESC_HEAD_PTR_REG(tx->tx_q))(((sc)->sc_iot)->read_4(((sc)->sc_ioh), (((0x7c0c + (
tx->tx_q) * 0x40))))) &
3176 TX_DMA_DESC_HEAD_PTR0x00000FFF;
3177 free = 0;
3178
3179 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x02))
3180 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_POSTREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x02));
3181
3182 while (idx != end) {
3183 as = &tx->tx_slots[idx];
3184
3185 if (as->as_m != NULL((void *)0)) {
3186 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x08))
3187 as->as_map->dm_mapsize, BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x08));
3188 bus_dmamap_unload(sc->sc_dmat, as->as_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (as->
as_map));
3189
3190 m_freem(as->as_m);
3191 as->as_m = NULL((void *)0);
3192 }
3193
3194 idx++;
3195 if (idx == AQ_TXD_NUM2048)
3196 idx = 0;
3197 free++;
3198 }
3199
3200 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x01))
3201 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_PREREAD)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x01));
3202
3203 tx->tx_cons = idx;
3204
3205 if (free != 0) {
3206 if (ifq_is_oactive(tx->tx_ifq))
3207 ifq_restart(tx->tx_ifq);
3208 }
3209}
3210
3211void
3212aq_start(struct ifqueue *ifq)
3213{
3214 struct aq_queues *aq = ifq->ifq_softc_ifq_ptr._ifq_softc;
3215 struct aq_softc *sc = aq->q_sc;
3216 struct aq_txring *tx = &aq->q_tx;
3217 struct aq_tx_desc *ring, *txd;
3218 struct aq_slot *as;
3219 struct mbuf *m;
3220 uint32_t idx, free, used, ctl1, ctl2;
3221 int error, i;
3222
3223 idx = tx->tx_prod;
3224 free = tx->tx_cons + AQ_TXD_NUM2048 - tx->tx_prod;
3225 used = 0;
3226
3227 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x08))
3228 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x08));
3229 ring = (struct aq_tx_desc *)AQ_DMA_KVA(&tx->tx_mem)((void *)(&tx->tx_mem)->aqm_kva);
3230
3231 for (;;) {
3232 if (used + AQ_TX_MAX_SEGMENTS32 + 1 >= free) {
3233 ifq_set_oactive(ifq);
3234 break;
3235 }
3236
3237 m = ifq_dequeue(ifq);
3238 if (m == NULL((void *)0))
3239 break;
3240
3241 as = &tx->tx_slots[idx];
3242
3243 error = bus_dmamap_load_mbuf(sc->sc_dmat, as->as_map, m,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
as->as_map), (m), (0x0100 | 0x0001))
3244 BUS_DMA_STREAMING | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
as->as_map), (m), (0x0100 | 0x0001));
3245 if (error == EFBIG27) {
3246 if (m_defrag(m, M_DONTWAIT0x0002)) {
3247 m_freem(m);
3248 break;
3249 }
3250
3251 error = bus_dmamap_load_mbuf(sc->sc_dmat, as->as_map,(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
as->as_map), (m), (0x0100 | 0x0001))
3252 m, BUS_DMA_STREAMING | BUS_DMA_NOWAIT)(*(sc->sc_dmat)->_dmamap_load_mbuf)((sc->sc_dmat), (
as->as_map), (m), (0x0100 | 0x0001));
3253 }
3254 if (error != 0) {
3255 m_freem(m);
3256 break;
3257 }
3258
3259 as->as_m = m;
3260
3261#if NBPFILTER1 > 0
3262 if (ifq->ifq_if->if_bpf)
3263 bpf_mtap_ether(ifq->ifq_if->if_bpf, m, BPF_DIRECTION_OUT(1 << 1));
3264#endif
3265 bus_dmamap_sync(sc->sc_dmat, as->as_map, 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x04))
3266 as->as_map->dm_mapsize, BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (as->
as_map), (0), (as->as_map->dm_mapsize), (0x04));
3267
3268 ctl2 = m->m_pkthdrM_dat.MH.MH_pkthdr.len << AQ_TXDESC_CTL2_LEN_SHIFT14;
3269 ctl1 = AQ_TXDESC_CTL1_TYPE_TXD0x00000001 | AQ_TXDESC_CTL1_CMD_FCS(1 << 23);
3270#if NVLAN1 > 0
3271 if (m->m_flagsm_hdr.mh_flags & M_VLANTAG0x0020) {
3272 txd = ring + idx;
3273 txd->buf_addr = 0;
3274 txd->ctl1 = htole32(AQ_TXDESC_CTL1_TYPE_TXC |((__uint32_t)(0x00000002 | (m->M_dat.MH.MH_pkthdr.ether_vtag
<< 4)))
3275 (m->m_pkthdr.ether_vtag << AQ_TXDESC_CTL1_VLAN_SHIFT))((__uint32_t)(0x00000002 | (m->M_dat.MH.MH_pkthdr.ether_vtag
<< 4)));
3276 txd->ctl2 = 0;
3277
3278 ctl1 |= AQ_TXDESC_CTL1_CMD_VLAN(1 << 22);
3279 ctl2 |= AQ_TXDESC_CTL2_CTX_EN(1 << 13);
3280
3281 idx++;
3282 if (idx == AQ_TXD_NUM2048)
3283 idx = 0;
3284 used++;
3285 }
3286#endif
3287
3288 if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & M_IPV4_CSUM_OUT0x0001)
3289 ctl1 |= AQ_TXDESC_CTL1_CMD_IP4CSUM(1 << 24);
3290 if (m->m_pkthdrM_dat.MH.MH_pkthdr.csum_flags & (M_TCP_CSUM_OUT0x0002 | M_UDP_CSUM_OUT0x0004))
3291 ctl1 |= AQ_TXDESC_CTL1_CMD_L4CSUM(1 << 25);
3292
3293 for (i = 0; i < as->as_map->dm_nsegs; i++) {
3294
3295 if (i == as->as_map->dm_nsegs - 1)
3296 ctl1 |= AQ_TXDESC_CTL1_CMD_EOP(1 << 21) |
3297 AQ_TXDESC_CTL1_CMD_WB(1 << 27);
3298
3299 txd = ring + idx;
3300 txd->buf_addr = htole64(as->as_map->dm_segs[i].ds_addr)((__uint64_t)(as->as_map->dm_segs[i].ds_addr));
3301 txd->ctl1 = htole32(ctl1 |((__uint32_t)(ctl1 | (as->as_map->dm_segs[i].ds_len <<
4)))
3302 (as->as_map->dm_segs[i].ds_len <<((__uint32_t)(ctl1 | (as->as_map->dm_segs[i].ds_len <<
4)))
3303 AQ_TXDESC_CTL1_BLEN_SHIFT))((__uint32_t)(ctl1 | (as->as_map->dm_segs[i].ds_len <<
4)));
3304 txd->ctl2 = htole32(ctl2)((__uint32_t)(ctl2));
3305
3306 idx++;
3307 if (idx == AQ_TXD_NUM2048)
3308 idx = 0;
3309 used++;
3310 }
3311 }
3312
3313 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem), 0,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x04))
3314 AQ_DMA_LEN(&tx->tx_mem), BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x04));
3315
3316 if (used != 0) {
3317 tx->tx_prod = idx;
3318 AQ_WRITE_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(tx->tx_q),(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x7c10 +
(tx->tx_q) * 0x40))), ((tx->tx_prod))))
3319 tx->tx_prod)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x7c10 +
(tx->tx_q) * 0x40))), ((tx->tx_prod))));
3320 }
3321}
3322
3323int
3324aq_intr_queue(void *arg)
3325{
3326 struct aq_queues *aq = arg;
3327 struct aq_softc *sc = aq->q_sc;
3328 uint32_t status;
3329 uint32_t clear;
3330
3331 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x2000))));
3332 clear = 0;
3333 if (status & (1 << aq->q_tx.tx_irq)) {
3334 clear |= (1 << aq->q_tx.tx_irq);
3335 aq_txeof(sc, &aq->q_tx);
3336 }
3337
3338 if (status & (1 << aq->q_rx.rx_irq)) {
3339 clear |= (1 << aq->q_rx.rx_irq);
3340 aq_rxeof(sc, &aq->q_rx);
3341 }
3342
3343 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, clear)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
((clear))));
3344 return (clear != 0);
3345}
3346
3347int
3348aq_intr_link(void *arg)
3349{
3350 struct aq_softc *sc = arg;
3351 uint32_t status;
3352
3353 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x2000))));
3354 if (status & (1 << sc->sc_linkstat_irq)) {
3355 aq_update_link_status(sc);
3356 AQ_WRITE_REG(sc, AQ_INTR_STATUS_REG, (1 << sc->sc_linkstat_irq))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2000)),
(((1 << sc->sc_linkstat_irq)))));
3357 return 1;
3358 }
3359
3360 return 0;
3361}
3362
3363int
3364aq_intr(void *arg)
3365{
3366 struct aq_softc *sc = arg;
3367 struct aq_queues *aq = &sc->sc_queues[0];
3368 uint32_t status;
3369
3370 status = AQ_READ_REG(sc, AQ_INTR_STATUS_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x2000))));
3371 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
((0xffffffff))));
3372
3373 if (status & (1 << sc->sc_linkstat_irq))
3374 aq_update_link_status(sc);
3375
3376 if (status & (1 << aq->q_tx.tx_irq)) {
3377 aq_txeof(sc, &aq->q_tx);
3378 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
(((1 << aq->q_tx.tx_irq)))))
3379 (1 << aq->q_tx.tx_irq))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
(((1 << aq->q_tx.tx_irq)))));
3380 }
3381 if (status & (1 << aq->q_rx.rx_irq)) {
3382 aq_rxeof(sc, &aq->q_rx);
3383 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG,(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
(((1 << aq->q_rx.rx_irq)))))
3384 (1 << aq->q_rx.rx_irq))(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
(((1 << aq->q_rx.rx_irq)))));
3385 }
3386
3387 return 1;
3388}
3389
3390void
3391aq_watchdog(struct ifnet *ifp)
3392{
3393
3394}
3395
3396void
3397aq_free_slots(struct aq_softc *sc, struct aq_slot *slots, int allocated,
3398 int total)
3399{
3400 struct aq_slot *as;
3401
3402 int i = allocated;
3403 while (i-- > 0) {
3404 as = &slots[i];
3405 bus_dmamap_destroy(sc->sc_dmat, as->as_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (as
->as_map));
3406 if (as->as_m != NULL((void *)0))
3407 m_freem(as->as_m);
3408 }
3409 free(slots, M_DEVBUF2, total * sizeof(*as));
3410}
3411
3412int
3413aq_queue_up(struct aq_softc *sc, struct aq_queues *aq)
3414{
3415 struct aq_rxring *rx;
3416 struct aq_txring *tx;
3417 struct aq_slot *as;
3418 int i, mtu;
3419
3420 rx = &aq->q_rx;
3421 rx->rx_slots = mallocarray(sizeof(*as), AQ_RXD_NUM2048, M_DEVBUF2,
3422 M_WAITOK0x0001 | M_ZERO0x0008);
3423 if (rx->rx_slots == NULL((void *)0)) {
3424 printf("%s: failed to allocate rx slots %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
3425 aq->q_index);
3426 return ENOMEM12;
3427 }
3428
3429 for (i = 0; i < AQ_RXD_NUM2048; i++) {
3430 as = &rx->rx_slots[i];
3431 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (1), ((1 << 11)), (0), (0x0000 | 0x0002 | 0x2000
), (&as->as_map))
3432 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (1), ((1 << 11)), (0), (0x0000 | 0x0002 | 0x2000
), (&as->as_map))
3433 &as->as_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
11)), (1), ((1 << 11)), (0), (0x0000 | 0x0002 | 0x2000
), (&as->as_map)) != 0) {
3434 printf("%s: failed to allocate rx dma maps %d\n",
3435 DEVNAME(sc)((sc)->sc_dev.dv_xname), aq->q_index);
3436 goto destroy_rx_slots;
3437 }
3438 }
3439
3440 if (aq_dmamem_alloc(sc, &rx->rx_mem, AQ_RXD_NUM2048 *
3441 sizeof(struct aq_rx_desc_read), PAGE_SIZE(1 << 12)) != 0) {
3442 printf("%s: unable to allocate rx ring %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
3443 aq->q_index);
3444 goto destroy_rx_slots;
3445 }
3446
3447 tx = &aq->q_tx;
3448 tx->tx_slots = mallocarray(sizeof(*as), AQ_TXD_NUM2048, M_DEVBUF2,
3449 M_WAITOK0x0001 | M_ZERO0x0008);
3450 if (tx->tx_slots == NULL((void *)0)) {
3451 printf("%s: failed to allocate tx slots %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
3452 aq->q_index);
3453 goto destroy_rx_ring;
3454 }
3455
3456 mtu = sc->sc_arpcom.ac_if.if_hardmtu;
3457 for (i = 0; i < AQ_TXD_NUM2048; i++) {
3458 as = &tx->tx_slots[i];
3459 if (bus_dmamap_create(sc->sc_dmat, mtu, AQ_TX_MAX_SEGMENTS,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (mtu
), (32), ((1 << 11)), (0), (0x0000 | 0x0002 | 0x2000), (
&as->as_map))
3460 MCLBYTES, 0, BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (mtu
), (32), ((1 << 11)), (0), (0x0000 | 0x0002 | 0x2000), (
&as->as_map))
3461 &as->as_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (mtu
), (32), ((1 << 11)), (0), (0x0000 | 0x0002 | 0x2000), (
&as->as_map)) != 0) {
3462 printf("%s: failed to allocated tx dma maps %d\n",
3463 DEVNAME(sc)((sc)->sc_dev.dv_xname), aq->q_index);
3464 goto destroy_tx_slots;
3465 }
3466 }
3467
3468 if (aq_dmamem_alloc(sc, &tx->tx_mem, AQ_TXD_NUM2048 *
3469 sizeof(struct aq_tx_desc), PAGE_SIZE(1 << 12)) != 0) {
3470 printf("%s: unable to allocate tx ring %d\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
3471 aq->q_index);
3472 goto destroy_tx_slots;
3473 }
3474
3475 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x01|0x04))
3476 0, AQ_DMA_LEN(&tx->tx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x01|0x04))
3477 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x01|0x04));
3478
3479 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x01|0x04))
3480 0, AQ_DMA_LEN(&rx->rx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x01|0x04))
3481 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x01|0x04));
3482
3483 aq_txring_reset(sc, tx, 1);
3484 aq_rxring_reset(sc, rx, 1);
3485 return 0;
3486
3487destroy_tx_slots:
3488 aq_free_slots(sc, tx->tx_slots, i, AQ_TXD_NUM2048);
3489 tx->tx_slots = NULL((void *)0);
3490 i = AQ_RXD_NUM2048;
3491
3492destroy_rx_ring:
3493 aq_dmamem_free(sc, &rx->rx_mem);
3494destroy_rx_slots:
3495 aq_free_slots(sc, rx->rx_slots, i, AQ_RXD_NUM2048);
3496 rx->rx_slots = NULL((void *)0);
3497 return ENOMEM12;
3498}
3499
3500void
3501aq_queue_down(struct aq_softc *sc, struct aq_queues *aq)
3502{
3503 struct aq_txring *tx;
3504 struct aq_rxring *rx;
3505
3506 tx = &aq->q_tx;
3507 aq_txring_reset(sc, &aq->q_tx, 0);
3508 if (tx->tx_slots != NULL((void *)0)) {
3509 aq_free_slots(sc, tx->tx_slots, AQ_TXD_NUM2048, AQ_TXD_NUM2048);
3510 tx->tx_slots = NULL((void *)0);
3511 }
3512
3513 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&tx->tx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x02|0x08))
3514 0, AQ_DMA_LEN(&tx->tx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x02|0x08))
3515 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
tx->tx_mem)->aqm_map)), (0), (((&tx->tx_mem)->
aqm_size)), (0x02|0x08));
3516
3517 aq_dmamem_free(sc, &tx->tx_mem);
3518
3519 rx = &aq->q_rx;
3520 m_freem(rx->rx_m_head);
3521 rx->rx_m_head = NULL((void *)0);
3522 rx->rx_m_tail = &rx->rx_m_head;
3523 rx->rx_m_error = 0;
3524 aq_rxring_reset(sc, &aq->q_rx, 0);
3525 if (rx->rx_slots != NULL((void *)0)) {
3526 aq_free_slots(sc, rx->rx_slots, AQ_RXD_NUM2048, AQ_RXD_NUM2048);
3527 rx->rx_slots = NULL((void *)0);
3528 }
3529
3530 bus_dmamap_sync(sc->sc_dmat, AQ_DMA_MAP(&rx->rx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x02|0x08))
3531 0, AQ_DMA_LEN(&rx->rx_mem),(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x02|0x08))
3532 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (((&
rx->rx_mem)->aqm_map)), (0), (((&rx->rx_mem)->
aqm_size)), (0x02|0x08));
3533
3534 aq_dmamem_free(sc, &rx->rx_mem);
3535}
3536
3537void
3538aq_invalidate_rx_desc_cache(struct aq_softc *sc)
3539{
3540 uint32_t cache;
3541
3542 cache = AQ_READ_REG(sc, RX_DMA_DESC_CACHE_INIT_REG)(((sc)->sc_iot)->read_4(((sc)->sc_ioh), ((0x5a00))));
3543 AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_CACHE_INIT_REG, RX_DMA_DESC_CACHE_INIT,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5a00))))); _v &= ~((1 << 0)); if
(((cache & (1 << 0)) ^ (1 << 0)) != 0) _v |=
((((cache & (1 << 0)) ^ (1 << 0))) * (((((uint32_t
)((1 << 0))) - 1) & ((uint32_t)((1 << 0)))) ^
((uint32_t)((1 << 0))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x5a00))), ((_v)))); } while ( 0)
3544 (cache & RX_DMA_DESC_CACHE_INIT) ^ RX_DMA_DESC_CACHE_INIT)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5a00))))); _v &= ~((1 << 0)); if
(((cache & (1 << 0)) ^ (1 << 0)) != 0) _v |=
((((cache & (1 << 0)) ^ (1 << 0))) * (((((uint32_t
)((1 << 0))) - 1) & ((uint32_t)((1 << 0)))) ^
((uint32_t)((1 << 0))))); ((((sc))->sc_iot)->write_4
((((sc))->sc_ioh), (((0x5a00))), ((_v)))); } while ( 0);
3545}
3546
3547int
3548aq_up(struct aq_softc *sc)
3549{
3550 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3551 int i;
3552
3553 aq_invalidate_rx_desc_cache(sc);
3554
3555 for (i = 0; i < sc->sc_nqueues; i++) {
3556 if (aq_queue_up(sc, &sc->sc_queues[i]) != 0)
3557 goto downqueues;
3558 }
3559
3560 aq_set_mac_addr(sc, AQ_HW_MAC_OWN0, sc->sc_arpcom.ac_enaddr);
3561
3562 AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_IP4CSUM_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7800))))); _v &= ~((1 << 1)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 1))) - 1
) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)((1 <<
1))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7800))), ((_v)))); } while ( 0);
3563 AQ_WRITE_REG_BIT(sc, TPO_HWCSUM_REG, TPO_HWCSUM_L4CSUM_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7800))))); _v &= ~((1 << 0)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7800))), ((_v)))); } while ( 0);
3564
3565 AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_IP4CSUM_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5580))))); _v &= ~((1 << 1)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 1))) - 1
) & ((uint32_t)((1 << 1)))) ^ ((uint32_t)((1 <<
1))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5580))), ((_v)))); } while ( 0);
3566 AQ_WRITE_REG_BIT(sc, RPO_HWCSUM_REG, RPO_HWCSUM_L4CSUM_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5580))))); _v &= ~((1 << 0)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5580))), ((_v)))); } while ( 0);
3567
3568 SET(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) |= (0x40));
3569 aq_enable_intr(sc, 1, 1);
3570 AQ_WRITE_REG_BIT(sc, TPB_TX_BUF_REG, TPB_TX_BUF_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x7900))))); _v &= ~((1 << 0)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x7900))), ((_v)))); } while ( 0);
3571 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5700))))); _v &= ~((1 << 0)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5700))), ((_v)))); } while ( 0);
3572
3573 for (i = 0; i < sc->sc_nqueues; i++) {
3574 struct aq_queues *aq = &sc->sc_queues[i];
3575
3576 if_rxr_init(&aq->q_rx.rx_rxr, howmany(ifp->if_hardmtu, MCLBYTES)(((ifp->if_hardmtu) + (((1 << 11)) - 1)) / ((1 <<
11))),
3577 AQ_RXD_NUM2048 - 1);
3578 aq_rx_fill(sc, &aq->q_rx);
3579
3580 ifq_clr_oactive(aq->q_tx.tx_ifq);
3581 }
3582
3583 return ENETRESET52;
3584
3585downqueues:
3586 for (i = 0; i < sc->sc_nqueues; i++)
3587 aq_queue_down(sc, &sc->sc_queues[i]);
3588 return ENOMEM12;
3589}
3590
3591void
3592aq_down(struct aq_softc *sc)
3593{
3594 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3595 int i;
3596
3597 CLR(ifp->if_flags, IFF_RUNNING)((ifp->if_flags) &= ~(0x40));
3598
3599 aq_enable_intr(sc, 1, 0);
3600 intr_barrier(sc->sc_ih);
3601
3602 AQ_WRITE_REG_BIT(sc, RPB_RPF_RX_REG, RPB_RPF_RX_BUF_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5700))))); _v &= ~((1 << 0)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 0))) - 1
) & ((uint32_t)((1 << 0)))) ^ ((uint32_t)((1 <<
0))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5700))), ((_v)))); } while ( 0);
3603 for (i = 0; i < sc->sc_nqueues; i++) {
3604 /* queue intr barrier? */
3605 aq_queue_down(sc, &sc->sc_queues[i]);
3606 }
3607
3608 aq_invalidate_rx_desc_cache(sc);
3609}
3610
3611void
3612aq_enable_intr(struct aq_softc *sc, int link, int txrx)
3613{
3614 uint32_t imask = 0;
3615 int i;
3616
3617 if (txrx) {
3618 for (i = 0; i < sc->sc_nqueues; i++) {
3619 imask |= (1 << sc->sc_queues[i].q_tx.tx_irq);
3620 imask |= (1 << sc->sc_queues[i].q_rx.rx_irq);
3621 }
3622 }
3623
3624 if (link)
3625 imask |= (1 << sc->sc_linkstat_irq);
3626
3627 AQ_WRITE_REG(sc, AQ_INTR_MASK_REG, imask)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2060)),
((imask))));
3628 AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, 0xffffffff)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), ((0x2050)),
((0xffffffff))));
3629}
3630
3631void
3632aq_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
3633{
3634 struct aq_softc *aq = ifp->if_softc;
3635 enum aq_link_speed speed;
3636 enum aq_link_fc fc;
3637 int media;
3638 int flow;
3639
3640 if (aq_get_linkmode(aq, &speed, &fc, NULL((void *)0)) != 0)
3641 return;
3642
3643 switch (speed) {
3644 case AQ_LINK_10G:
3645 media = IFM_10G_T22;
3646 break;
3647 case AQ_LINK_5G:
3648 media = IFM_5000_T35;
3649 break;
3650 case AQ_LINK_2G5:
3651 media = IFM_2500_T34;
3652 break;
3653 case AQ_LINK_1G:
3654 media = IFM_1000_T16;
3655 break;
3656 case AQ_LINK_100M:
3657 media = IFM_100_TX6;
3658 break;
3659 case AQ_LINK_10M:
3660 media = IFM_10_T3;
3661 break;
3662 case AQ_LINK_NONE:
3663 media = 0;
3664 break;
3665 }
3666
3667 flow = 0;
3668 if (fc & AQ_FC_RX)
3669 flow |= IFM_ETH_RXPAUSE0x0000000000020000ULL;
3670 if (fc & AQ_FC_TX)
3671 flow |= IFM_ETH_TXPAUSE0x0000000000040000ULL;
3672
3673 ifmr->ifm_status = IFM_AVALID0x0000000000000001ULL;
3674 if (speed != AQ_LINK_NONE) {
3675 ifmr->ifm_status |= IFM_ACTIVE0x0000000000000002ULL;
3676 ifmr->ifm_active = IFM_ETHER0x0000000000000100ULL | IFM_AUTO0ULL | media | flow;
3677 }
3678}
3679
3680int
3681aq_ifmedia_change(struct ifnet *ifp)
3682{
3683 struct aq_softc *sc = ifp->if_softc;
3684 enum aq_link_speed rate = AQ_LINK_NONE;
3685 enum aq_link_fc fc = AQ_FC_NONE;
3686
3687 if (IFM_TYPE(sc->sc_media.ifm_media)((sc->sc_media.ifm_media) & 0x000000000000ff00ULL) != IFM_ETHER0x0000000000000100ULL)
3688 return EINVAL22;
3689
3690 switch (IFM_SUBTYPE(sc->sc_media.ifm_media)((sc->sc_media.ifm_media) & 0x00000000000000ffULL)) {
3691 case IFM_AUTO0ULL:
3692 rate = AQ_LINK_AUTO(AQ_LINK_100M | AQ_LINK_1G | AQ_LINK_2G5 | AQ_LINK_5G | AQ_LINK_10G
);
3693 break;
3694 case IFM_NONE2ULL:
3695 rate = AQ_LINK_NONE;
3696 break;
3697 case IFM_10_T3:
3698 rate = AQ_LINK_10M;
3699 break;
3700 case IFM_100_TX6:
3701 rate = AQ_LINK_100M;
3702 break;
3703 case IFM_1000_T16:
3704 rate = AQ_LINK_1G;
3705 break;
3706 case IFM_2500_T34:
3707 rate = AQ_LINK_2G5;
3708 break;
3709 case IFM_5000_T35:
3710 rate = AQ_LINK_5G;
3711 break;
3712 case IFM_10G_T22:
3713 rate = AQ_LINK_10G;
3714 break;
3715 default:
3716 return ENODEV19;
3717 }
3718
3719 if (sc->sc_media.ifm_media & IFM_FLOW0x0000040000000000ULL)
3720 fc = AQ_FC_ALL;
3721
3722 return aq_set_linkmode(sc, rate, fc, AQ_EEE_DISABLE);
3723}
3724
3725void
3726aq_update_link_status(struct aq_softc *sc)
3727{
3728 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3729 enum aq_link_speed speed;
3730 enum aq_link_fc fc;
3731
3732 if (aq_get_linkmode(sc, &speed, &fc, NULL((void *)0)) != 0)
3733 return;
3734
3735 if (speed == AQ_LINK_NONE) {
3736 if (ifp->if_link_stateif_data.ifi_link_state != LINK_STATE_DOWN2) {
3737 ifp->if_link_stateif_data.ifi_link_state = LINK_STATE_DOWN2;
3738 if_link_state_change(ifp);
3739 }
3740 } else {
3741 if (ifp->if_link_stateif_data.ifi_link_state != LINK_STATE_FULL_DUPLEX6) {
3742 ifp->if_link_stateif_data.ifi_link_state = LINK_STATE_FULL_DUPLEX6;
3743 if_link_state_change(ifp);
3744 }
3745 }
3746}
3747
3748int
3749aq_rxrinfo(struct aq_softc *sc, struct if_rxrinfo *ifri)
3750{
3751 struct if_rxring_info *ifr;
3752 int i;
3753 int error;
3754
3755 ifr = mallocarray(sc->sc_nqueues, sizeof(*ifr), M_TEMP127,
3756 M_WAITOK0x0001 | M_ZERO0x0008 | M_CANFAIL0x0004);
3757 if (ifr == NULL((void *)0))
3758 return (ENOMEM12);
3759
3760 for (i = 0; i < sc->sc_nqueues; i++) {
3761 ifr[i].ifr_size = MCLBYTES(1 << 11);
3762 ifr[i].ifr_info = sc->sc_queues[i].q_rx.rx_rxr;
3763 }
3764
3765 error = if_rxr_info_ioctl(ifri, sc->sc_nqueues, ifr);
3766 free(ifr, M_TEMP127, sc->sc_nqueues * sizeof(*ifr));
3767
3768 return (error);
3769}
3770
3771int
3772aq_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3773{
3774 struct aq_softc *sc = ifp->if_softc;
3775 struct ifreq *ifr = (struct ifreq *)data;
3776 int error = 0, s;
3777
3778 s = splnet()splraise(0x4);
3779
3780 switch (cmd) {
3781 case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
3782 ifp->if_flags |= IFF_UP0x1;
3783 if ((ifp->if_flags & IFF_RUNNING0x40) == 0)
3784 error = aq_up(sc);
3785 break;
3786 case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
3787 if (ifp->if_flags & IFF_UP0x1) {
3788 if (ifp->if_flags & IFF_RUNNING0x40)
3789 error = ENETRESET52;
3790 else
3791 error = aq_up(sc);
3792 } else {
3793 if (ifp->if_flags & IFF_RUNNING0x40)
3794 aq_down(sc);
3795 }
3796 break;
3797 case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
8) | ((55))):
3798 case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
8) | ((56))):
3799 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
3800 break;
3801
3802 case SIOCGIFRXR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((170))):
3803 error = aq_rxrinfo(sc, (struct if_rxrinfo *)ifr->ifr_dataifr_ifru.ifru_data);
3804 break;
3805
3806 default:
3807 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
3808 }
3809
3810 if (error == ENETRESET52) {
3811 if (ifp->if_flags & IFF_RUNNING0x40)
3812 aq_iff(sc);
3813 error = 0;
3814 }
3815
3816 splx(s)spllower(s);
3817 return error;
3818}
3819
3820int
3821aq2_filter_art_set(struct aq_softc *sc, uint32_t idx,
3822 uint32_t tag, uint32_t mask, uint32_t action)
3823{
3824 int error;
3825
3826 AQ_MPI_LOCK(sc)mtx_enter(&(sc)->sc_mpi_mutex);;
3827
3828 WAIT_FOR(AQ_READ_REG(sc, AQ2_ART_SEM_REG) == 1, 10, 1000, &error)do { unsigned int _n; for (_n = 1000; (!((((sc)->sc_iot)->
read_4(((sc)->sc_ioh), (((0x03a0 + (3) * 4))))) == 1)) &&
_n != 0; --_n) { (*delay_func)((10)); } if ((&error != (
(void *)0))) { if (_n == 0) *(&error) = 60; else *(&error
) = 0; } } while ( 0);
3829 if (error != 0) {
3830 printf("%s: AQ2_ART_SEM_REG timeout\n", DEVNAME(sc)((sc)->sc_dev.dv_xname));
3831 goto out;
3832 }
3833
3834 idx += sc->sc_art_filter_base_index;
3835 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_TAG_REG(idx), tag)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x14000 +
(idx) * 0x10))), ((tag))));
3836 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_MASK_REG(idx), mask)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x14004 +
(idx) * 0x10))), ((mask))));
3837 AQ_WRITE_REG(sc, AQ2_RPF_ACT_ART_REQ_ACTION_REG(idx), action)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x14008 +
(idx) * 0x10))), ((action))));
3838
3839 AQ_WRITE_REG(sc, AQ2_ART_SEM_REG, 1)(((sc)->sc_iot)->write_4(((sc)->sc_ioh), (((0x03a0 +
(3) * 4))), ((1))));
3840
3841 out:
3842 AQ_MPI_UNLOCK(sc)mtx_leave(&(sc)->sc_mpi_mutex);;
3843 return error;
3844}
3845
3846void
3847aq_iff(struct aq_softc *sc)
3848{
3849 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3850 struct arpcom *ac = &sc->sc_arpcom;
3851 struct ether_multi *enm;
3852 struct ether_multistep step;
3853 uint32_t action;
3854 int idx;
3855
3856 if (HWTYPE_AQ2_P(sc)(((sc)->sc_features & 0x10000000) != 0)) {
3857 action = (ifp->if_flags & IFF_PROMISC0x100) ?
3858 AQ2_ART_ACTION_DISABLE(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(0) ? 0x0001 : 0)) : AQ2_ART_ACTION_DROP(((0) << 8) | ((0) ? 0x0080 : 0) | ((0) << 2) | (
(1) ? 0x0001 : 0));
3859 aq2_filter_art_set(sc, AQ2_RPF_INDEX_L2_PROMISC_OFF0, 0,
3860 AQ2_RPF_TAG_UC_MASK0x0000002f | AQ2_RPF_TAG_ALLMC_MASK0x00000040, action);
3861 aq2_filter_art_set(sc, AQ2_RPF_INDEX_VLAN_PROMISC_OFF1, 0,
3862 AQ2_RPF_TAG_VLAN_MASK0x00003c00 | AQ2_RPF_TAG_UNTAG_MASK0x00004000, action);
3863 }
3864
3865 if (ifp->if_flags & IFF_PROMISC0x100) {
3866 ifp->if_flags |= IFF_ALLMULTI0x200;
3867 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5100))))); _v &= ~((1 << 3)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 3))) - 1
) & ((uint32_t)((1 << 3)))) ^ ((uint32_t)((1 <<
3))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5100))), ((_v)))); } while ( 0);
3868 } else if (ac->ac_multirangecnt > 0 ||
3869 ac->ac_multicnt >= AQ_HW_MAC_NUM34) {
3870 ifp->if_flags |= IFF_ALLMULTI0x200;
3871 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5100))))); _v &= ~((1 << 3)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 3))) - 1
) & ((uint32_t)((1 << 3)))) ^ ((uint32_t)((1 <<
3))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5100))), ((_v)))); } while ( 0);
3872 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5270))))); _v &= ~((1 << 14)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 14))) -
1) & ((uint32_t)((1 << 14)))) ^ ((uint32_t)((1 <<
14))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5270))), ((_v)))); } while ( 0)
3873 RPF_MCAST_FILTER_MASK_ALLMULTI, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5270))))); _v &= ~((1 << 14)); if
((1) != 0) _v |= (((1)) * (((((uint32_t)((1 << 14))) -
1) & ((uint32_t)((1 << 14)))) ^ ((uint32_t)((1 <<
14))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5270))), ((_v)))); } while ( 0);
3874 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5250 + (0) * 4)))))); _v &= ~((1U <<
31)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5250 + (0) * 4)))), ((_v)))); } while (
0)
3875 RPF_MCAST_FILTER_EN, 1)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5250 + (0) * 4)))))); _v &= ~((1U <<
31)); if ((1) != 0) _v |= (((1)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5250 + (0) * 4)))), ((_v)))); } while (
0);
3876 } else {
3877 ifp->if_flags &= ~IFF_ALLMULTI0x200;
3878 idx = AQ_HW_MAC_OWN0 + 1;
3879
3880 AQ_WRITE_REG_BIT(sc, RPF_L2BC_REG, RPF_L2BC_PROMISC, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5100))))); _v &= ~((1 << 3)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 3))) - 1
) & ((uint32_t)((1 << 3)))) ^ ((uint32_t)((1 <<
3))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh)
, (((0x5100))), ((_v)))); } while ( 0);
3881
3882 ETHER_FIRST_MULTI(step, ac, enm)do { (step).e_enm = ((&(ac)->ac_multiaddrs)->lh_first
); do { if ((((enm)) = ((step)).e_enm) != ((void *)0)) ((step
)).e_enm = ((((enm)))->enm_list.le_next); } while ( 0); } while
( 0);
3883 while (enm != NULL((void *)0)) {
3884 aq_set_mac_addr(sc, idx++, enm->enm_addrlo);
3885 ETHER_NEXT_MULTI(step, enm)do { if (((enm) = (step).e_enm) != ((void *)0)) (step).e_enm =
(((enm))->enm_list.le_next); } while ( 0);
3886 }
3887
3888 for (; idx < AQ_HW_MAC_NUM34; idx++)
3889 aq_set_mac_addr(sc, idx, NULL((void *)0));
3890
3891 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_MASK_REG,do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5270))))); _v &= ~((1 << 14)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 14))) -
1) & ((uint32_t)((1 << 14)))) ^ ((uint32_t)((1 <<
14))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5270))), ((_v)))); } while ( 0)
3892 RPF_MCAST_FILTER_MASK_ALLMULTI, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), (((0x5270))))); _v &= ~((1 << 14)); if
((0) != 0) _v |= (((0)) * (((((uint32_t)((1 << 14))) -
1) & ((uint32_t)((1 << 14)))) ^ ((uint32_t)((1 <<
14))))); ((((sc))->sc_iot)->write_4((((sc))->sc_ioh
), (((0x5270))), ((_v)))); } while ( 0);
3893 AQ_WRITE_REG_BIT(sc, RPF_MCAST_FILTER_REG(0),do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5250 + (0) * 4)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5250 + (0) * 4)))), ((_v)))); } while (
0)
3894 RPF_MCAST_FILTER_EN, 0)do { uint32_t _v; _v = ((((sc))->sc_iot)->read_4((((sc)
)->sc_ioh), ((((0x5250 + (0) * 4)))))); _v &= ~((1U <<
31)); if ((0) != 0) _v |= (((0)) * (((((uint32_t)((1U <<
31))) - 1) & ((uint32_t)((1U << 31)))) ^ ((uint32_t
)((1U << 31))))); ((((sc))->sc_iot)->write_4((((sc
))->sc_ioh), ((((0x5250 + (0) * 4)))), ((_v)))); } while (
0);
3895 }
3896}
3897
3898int
3899aq_dmamem_alloc(struct aq_softc *sc, struct aq_dmamem *aqm,
3900 bus_size_t size, u_int align)
3901{
3902 aqm->aqm_size = size;
3903
3904 if (bus_dmamap_create(sc->sc_dmat, aqm->aqm_size, 1,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (aqm
->aqm_size), (1), (aqm->aqm_size), (0), (0x0000 | 0x0002
| 0x2000), (&aqm->aqm_map))
3905 aqm->aqm_size, 0,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (aqm
->aqm_size), (1), (aqm->aqm_size), (0), (0x0000 | 0x0002
| 0x2000), (&aqm->aqm_map))
3906 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW | BUS_DMA_64BIT,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (aqm
->aqm_size), (1), (aqm->aqm_size), (0), (0x0000 | 0x0002
| 0x2000), (&aqm->aqm_map))
3907 &aqm->aqm_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), (aqm
->aqm_size), (1), (aqm->aqm_size), (0), (0x0000 | 0x0002
| 0x2000), (&aqm->aqm_map)) != 0)
3908 return (1);
3909 if (bus_dmamem_alloc(sc->sc_dmat, aqm->aqm_size,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (aqm->
aqm_size), (align), (0), (&aqm->aqm_seg), (1), (&aqm
->aqm_nsegs), (0x0000 | 0x1000))
3910 align, 0, &aqm->aqm_seg, 1, &aqm->aqm_nsegs,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (aqm->
aqm_size), (align), (0), (&aqm->aqm_seg), (1), (&aqm
->aqm_nsegs), (0x0000 | 0x1000))
3911 BUS_DMA_WAITOK | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), (aqm->
aqm_size), (align), (0), (&aqm->aqm_seg), (1), (&aqm
->aqm_nsegs), (0x0000 | 0x1000)) != 0)
3912 goto destroy;
3913 if (bus_dmamem_map(sc->sc_dmat, &aqm->aqm_seg, aqm->aqm_nsegs,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&aqm
->aqm_seg), (aqm->aqm_nsegs), (aqm->aqm_size), (&
aqm->aqm_kva), (0x0000 | 0x0004))
3914 aqm->aqm_size, &aqm->aqm_kva,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&aqm
->aqm_seg), (aqm->aqm_nsegs), (aqm->aqm_size), (&
aqm->aqm_kva), (0x0000 | 0x0004))
3915 BUS_DMA_WAITOK | BUS_DMA_COHERENT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (&aqm
->aqm_seg), (aqm->aqm_nsegs), (aqm->aqm_size), (&
aqm->aqm_kva), (0x0000 | 0x0004)) != 0)
3916 goto free;
3917 if (bus_dmamap_load(sc->sc_dmat, aqm->aqm_map, aqm->aqm_kva,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (aqm->
aqm_map), (aqm->aqm_kva), (aqm->aqm_size), (((void *)0)
), (0x0000))
3918 aqm->aqm_size, NULL, BUS_DMA_WAITOK)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (aqm->
aqm_map), (aqm->aqm_kva), (aqm->aqm_size), (((void *)0)
), (0x0000)) != 0)
3919 goto unmap;
3920
3921 return (0);
3922unmap:
3923 bus_dmamem_unmap(sc->sc_dmat, aqm->aqm_kva, aqm->aqm_size)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (aqm->
aqm_kva), (aqm->aqm_size));
3924free:
3925 bus_dmamem_free(sc->sc_dmat, &aqm->aqm_seg, 1)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
aqm->aqm_seg), (1));
3926destroy:
3927 bus_dmamap_destroy(sc->sc_dmat, aqm->aqm_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (aqm
->aqm_map));
3928 return (1);
3929}
3930
3931void
3932aq_dmamem_free(struct aq_softc *sc, struct aq_dmamem *aqm)
3933{
3934 bus_dmamap_unload(sc->sc_dmat, aqm->aqm_map)(*(sc->sc_dmat)->_dmamap_unload)((sc->sc_dmat), (aqm
->aqm_map));
3935 bus_dmamem_unmap(sc->sc_dmat, aqm->aqm_kva, aqm->aqm_size)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (aqm->
aqm_kva), (aqm->aqm_size));
3936 bus_dmamem_free(sc->sc_dmat, &aqm->aqm_seg, 1)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (&
aqm->aqm_seg), (1));
3937 bus_dmamap_destroy(sc->sc_dmat, aqm->aqm_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (aqm
->aqm_map));
3938}