File: | dev/pci/drm/i915/display/intel_ddi.c |
Warning: | line 2160, column 2 Value stored to 'intel_dp' is never read |
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1 | /* |
2 | * Copyright © 2012 Intel Corporation |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice (including the next |
12 | * paragraph) shall be included in all copies or substantial portions of the |
13 | * Software. |
14 | * |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
21 | * IN THE SOFTWARE. |
22 | * |
23 | * Authors: |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
25 | * |
26 | */ |
27 | |
28 | #include <linux/string_helpers.h> |
29 | |
30 | #include <drm/display/drm_scdc_helper.h> |
31 | #include <drm/drm_privacy_screen_consumer.h> |
32 | |
33 | #include "i915_drv.h" |
34 | #include "intel_audio.h" |
35 | #include "intel_audio_regs.h" |
36 | #include "intel_backlight.h" |
37 | #include "intel_combo_phy.h" |
38 | #include "intel_combo_phy_regs.h" |
39 | #include "intel_connector.h" |
40 | #include "intel_crtc.h" |
41 | #include "intel_ddi.h" |
42 | #include "intel_ddi_buf_trans.h" |
43 | #include "intel_de.h" |
44 | #include "intel_display_power.h" |
45 | #include "intel_display_types.h" |
46 | #include "intel_dkl_phy.h" |
47 | #include "intel_dp.h" |
48 | #include "intel_dp_link_training.h" |
49 | #include "intel_dp_mst.h" |
50 | #include "intel_dpio_phy.h" |
51 | #include "intel_dsi.h" |
52 | #include "intel_fdi.h" |
53 | #include "intel_fifo_underrun.h" |
54 | #include "intel_gmbus.h" |
55 | #include "intel_hdcp.h" |
56 | #include "intel_hdmi.h" |
57 | #include "intel_hotplug.h" |
58 | #include "intel_lspcon.h" |
59 | #include "intel_pps.h" |
60 | #include "intel_psr.h" |
61 | #include "intel_quirks.h" |
62 | #include "intel_snps_phy.h" |
63 | #include "intel_sprite.h" |
64 | #include "intel_tc.h" |
65 | #include "intel_tc_phy_regs.h" |
66 | #include "intel_vdsc.h" |
67 | #include "intel_vrr.h" |
68 | #include "skl_scaler.h" |
69 | #include "skl_universal_plane.h" |
70 | |
71 | static const u8 index_to_dp_signal_levels[] = { |
72 | [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3), |
73 | [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3), |
74 | [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3), |
75 | [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0(0 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_3(3 << 3), |
76 | [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3), |
77 | [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3), |
78 | [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1(1 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_2(2 << 3), |
79 | [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3), |
80 | [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2(2 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_1(1 << 3), |
81 | [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3(3 << 0) | DP_TRAIN_PRE_EMPH_LEVEL_0(0 << 3), |
82 | }; |
83 | |
84 | static int intel_ddi_hdmi_level(struct intel_encoder *encoder, |
85 | const struct intel_ddi_buf_trans *trans) |
86 | { |
87 | int level; |
88 | |
89 | level = intel_bios_hdmi_level_shift(encoder); |
90 | if (level < 0) |
91 | level = trans->hdmi_default_entry; |
92 | |
93 | return level; |
94 | } |
95 | |
96 | static bool_Bool has_buf_trans_select(struct drm_i915_privateinteldrm_softc *i915) |
97 | { |
98 | return DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) < 10 && !IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON); |
99 | } |
100 | |
101 | static bool_Bool has_iboost(struct drm_i915_privateinteldrm_softc *i915) |
102 | { |
103 | return DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) == 9 && !IS_BROXTON(i915)IS_PLATFORM(i915, INTEL_BROXTON); |
104 | } |
105 | |
106 | /* |
107 | * Starting with Haswell, DDI port buffers must be programmed with correct |
108 | * values in advance. This function programs the correct values for |
109 | * DP/eDP/FDI use cases. |
110 | */ |
111 | void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder, |
112 | const struct intel_crtc_state *crtc_state) |
113 | { |
114 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
115 | u32 iboost_bit = 0; |
116 | int i, n_entries; |
117 | enum port port = encoder->port; |
118 | const struct intel_ddi_buf_trans *trans; |
119 | |
120 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
121 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
122 | return; |
123 | |
124 | /* If we're boosting the current, set bit 31 of trans1 */ |
125 | if (has_iboost(dev_priv) && |
126 | intel_bios_encoder_dp_boost_level(encoder->devdata)) |
127 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE(1 << 31); |
128 | |
129 | for (i = 0; i < n_entries; i++) { |
130 | intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60) - (0x64E00))) + (i) * 8) }), |
131 | trans->entries[i].hsw.trans1 | iboost_bit); |
132 | intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60) - (0x64E00))) + (i) * 8 + 4) }), |
133 | trans->entries[i].hsw.trans2); |
134 | } |
135 | } |
136 | |
137 | /* |
138 | * Starting with Haswell, DDI port buffers must be programmed with correct |
139 | * values in advance. This function programs the correct values for |
140 | * HDMI/DVI use cases. |
141 | */ |
142 | static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, |
143 | const struct intel_crtc_state *crtc_state) |
144 | { |
145 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
146 | int level = intel_ddi_level(encoder, crtc_state, 0); |
147 | u32 iboost_bit = 0; |
148 | int n_entries; |
149 | enum port port = encoder->port; |
150 | const struct intel_ddi_buf_trans *trans; |
151 | |
152 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
153 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
154 | return; |
155 | |
156 | /* If we're boosting the current, set bit 31 of trans1 */ |
157 | if (has_iboost(dev_priv) && |
158 | intel_bios_encoder_hdmi_boost_level(encoder->devdata)) |
159 | iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE(1 << 31); |
160 | |
161 | /* Entry 9 is for HDMI: */ |
162 | intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60) - (0x64E00))) + (9) * 8) }), |
163 | trans->entries[level].hsw.trans1 | iboost_bit); |
164 | intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9)((const i915_reg_t){ .reg = (((0x64E00) + (port) * ((0x64E60) - (0x64E00))) + (9) * 8 + 4) }), |
165 | trans->entries[level].hsw.trans2); |
166 | } |
167 | |
168 | void intel_wait_ddi_buf_idle(struct drm_i915_privateinteldrm_softc *dev_priv, |
169 | enum port port) |
170 | { |
171 | if (IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) { |
172 | udelay(16); |
173 | return; |
174 | } |
175 | |
176 | if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &({ int ret__; extern char _ctassert[(!(!__builtin_constant_p( 8))) ? 1 : -1 ] __attribute__((__unused__)); if ((8) > 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw( ), 1000ll * (((8)))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read (dev_priv, ((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })) & (1 << 7))))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range (wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<= 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((8) ) * 1000; u64 base; do { } while (0); if (!(0)) { preempt_disable (); cpu = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self ))); __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64 now = local_clock(); if (!(0)) preempt_enable(); __asm volatile ("" : : : "memory"); if (((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }) ) & (1 << 7)))) { ret = 0; break; } if (now - base >= timeout) { ret = -60; break; } cpu_relax(); if (!(0)) { preempt_disable (); if (__builtin_expect(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu = (({struct cpu_info *__ci; asm volatile( "movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_cpuid); base = local_clock (); } } } ret; }); ret__; }) |
177 | DDI_BUF_IS_IDLE), 8)({ int ret__; extern char _ctassert[(!(!__builtin_constant_p( 8))) ? 1 : -1 ] __attribute__((__unused__)); if ((8) > 10) ret__ = ({ const ktime_t end__ = ktime_add_ns(ktime_get_raw( ), 1000ll * (((8)))); long wait__ = ((10)); int ret__; assertwaitok (); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw (), end__); ; __asm volatile("" : : : "memory"); if ((((intel_de_read (dev_priv, ((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })) & (1 << 7))))) { ret__ = 0; break; } if (expired__) { ret__ = -60; break; } usleep_range (wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<= 1; } ret__; }); else ret__ = ({ int cpu, ret, timeout = ((8) ) * 1000; u64 base; do { } while (0); if (!(0)) { preempt_disable (); cpu = (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self ))); __ci;})->ci_cpuid); } base = local_clock(); for (;;) { u64 now = local_clock(); if (!(0)) preempt_enable(); __asm volatile ("" : : : "memory"); if (((intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }) ) & (1 << 7)))) { ret = 0; break; } if (now - base >= timeout) { ret = -60; break; } cpu_relax(); if (!(0)) { preempt_disable (); if (__builtin_expect(!!(cpu != (({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof (struct cpu_info, ci_self))); __ci;})->ci_cpuid)), 0)) { timeout -= now - base; cpu = (({struct cpu_info *__ci; asm volatile( "movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_cpuid); base = local_clock (); } } } ret; }); ret__; })) |
178 | drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for DDI BUF %c to get idle\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((port ) + 'A')) |
179 | port_name(port))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for DDI BUF %c to get idle\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((port ) + 'A')); |
180 | } |
181 | |
182 | static void intel_wait_ddi_buf_active(struct drm_i915_privateinteldrm_softc *dev_priv, |
183 | enum port port) |
184 | { |
185 | int ret; |
186 | |
187 | /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */ |
188 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 10) { |
189 | usleep_range(518, 1000); |
190 | return; |
191 | } |
192 | |
193 | ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * ((IS_PLATFORM(dev_priv, INTEL_DG2) ? 1200 : 500))); long wait__ = ((10)); int ret__; assertwaitok(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw(), end__); ; __asm volatile("" : : : "memory"); if ((!(intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }) ) & (1 << 7)))) { ret__ = 0; break; } if (expired__ ) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<= 1; } ret__; }) |
194 | DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10)({ const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * ((IS_PLATFORM(dev_priv, INTEL_DG2) ? 1200 : 500))); long wait__ = ((10)); int ret__; assertwaitok(); for (;;) { const _Bool expired__ = ktime_after(ktime_get_raw(), end__); ; __asm volatile("" : : : "memory"); if ((!(intel_de_read(dev_priv, ((const i915_reg_t ){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }) ) & (1 << 7)))) { ret__ = 0; break; } if (expired__ ) { ret__ = -60; break; } usleep_range(wait__, wait__ * 2); if (wait__ < ((10))) wait__ <<= 1; } ret__; }); |
195 | |
196 | if (ret) |
197 | drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for DDI BUF %c to get active\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((port ) + 'A')) |
198 | port_name(port))printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timeout waiting for DDI BUF %c to get active\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ((port ) + 'A')); |
199 | } |
200 | |
201 | static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) |
202 | { |
203 | switch (pll->info->id) { |
204 | case DPLL_ID_WRPLL1: |
205 | return PORT_CLK_SEL_WRPLL1((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(4) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
206 | case DPLL_ID_WRPLL2: |
207 | return PORT_CLK_SEL_WRPLL2((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(5) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
208 | case DPLL_ID_SPLL: |
209 | return PORT_CLK_SEL_SPLL((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
210 | case DPLL_ID_LCPLL_810: |
211 | return PORT_CLK_SEL_LCPLL_810((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
212 | case DPLL_ID_LCPLL_1350: |
213 | return PORT_CLK_SEL_LCPLL_1350((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
214 | case DPLL_ID_LCPLL_2700: |
215 | return PORT_CLK_SEL_LCPLL_2700((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
216 | default: |
217 | MISSING_CASE(pll->info->id)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "pll->info->id", (long)(pll->info->id)); __builtin_expect (!!(__ret), 0); }); |
218 | return PORT_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(7) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
219 | } |
220 | } |
221 | |
222 | static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder, |
223 | const struct intel_crtc_state *crtc_state) |
224 | { |
225 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
226 | int clock = crtc_state->port_clock; |
227 | const enum intel_dpll_id id = pll->info->id; |
228 | |
229 | switch (id) { |
230 | default: |
231 | /* |
232 | * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used |
233 | * here, so do warn if this get passed in |
234 | */ |
235 | MISSING_CASE(id)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "id", (long)(id)); __builtin_expect(!!(__ret), 0); }); |
236 | return DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
237 | case DPLL_ID_ICL_TBTPLL: |
238 | switch (clock) { |
239 | case 162000: |
240 | return DDI_CLK_SEL_TBT_162((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xC) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
241 | case 270000: |
242 | return DDI_CLK_SEL_TBT_270((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xD) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
243 | case 540000: |
244 | return DDI_CLK_SEL_TBT_540((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xE) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
245 | case 810000: |
246 | return DDI_CLK_SEL_TBT_810((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xF) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
247 | default: |
248 | MISSING_CASE(clock)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "clock", (long)(clock)); __builtin_expect(!!(__ret), 0); }); |
249 | return DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
250 | } |
251 | case DPLL_ID_ICL_MGPLL1: |
252 | case DPLL_ID_ICL_MGPLL2: |
253 | case DPLL_ID_ICL_MGPLL3: |
254 | case DPLL_ID_ICL_MGPLL4: |
255 | case DPLL_ID_TGL_MGPLL5: |
256 | case DPLL_ID_TGL_MGPLL6: |
257 | return DDI_CLK_SEL_MG((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )); |
258 | } |
259 | } |
260 | |
261 | static u32 ddi_buf_phy_link_rate(int port_clock) |
262 | { |
263 | switch (port_clock) { |
264 | case 162000: |
265 | return DDI_BUF_PHY_LINK_RATE(0)((0) << 20); |
266 | case 216000: |
267 | return DDI_BUF_PHY_LINK_RATE(4)((4) << 20); |
268 | case 243000: |
269 | return DDI_BUF_PHY_LINK_RATE(5)((5) << 20); |
270 | case 270000: |
271 | return DDI_BUF_PHY_LINK_RATE(1)((1) << 20); |
272 | case 324000: |
273 | return DDI_BUF_PHY_LINK_RATE(6)((6) << 20); |
274 | case 432000: |
275 | return DDI_BUF_PHY_LINK_RATE(7)((7) << 20); |
276 | case 540000: |
277 | return DDI_BUF_PHY_LINK_RATE(2)((2) << 20); |
278 | case 810000: |
279 | return DDI_BUF_PHY_LINK_RATE(3)((3) << 20); |
280 | default: |
281 | MISSING_CASE(port_clock)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "port_clock", (long)(port_clock)); __builtin_expect(!!(__ret ), 0); }); |
282 | return DDI_BUF_PHY_LINK_RATE(0)((0) << 20); |
283 | } |
284 | } |
285 | |
286 | static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder, |
287 | const struct intel_crtc_state *crtc_state) |
288 | { |
289 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
290 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
291 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
292 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
293 | |
294 | /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */ |
295 | intel_dp->DP = dig_port->saved_port_bits | |
296 | DDI_PORT_WIDTH(crtc_state->lane_count)(((crtc_state->lane_count) - 1) << 1) | |
297 | DDI_BUF_TRANS_SELECT(0)((0) << 24); |
298 | |
299 | if (IS_ALDERLAKE_P(i915)IS_PLATFORM(i915, INTEL_ALDERLAKE_P) && intel_phy_is_tc(i915, phy)) { |
300 | intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); |
301 | if (!intel_tc_port_in_tbt_alt_mode(dig_port)) |
302 | intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP((u32)((1UL << (6)) + 0)); |
303 | } |
304 | } |
305 | |
306 | static int icl_calc_tbt_pll_link(struct drm_i915_privateinteldrm_softc *dev_priv, |
307 | enum port port) |
308 | { |
309 | u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })) & DDI_CLK_SEL_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0)); |
310 | |
311 | switch (val) { |
312 | case DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
313 | return 0; |
314 | case DDI_CLK_SEL_TBT_162((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xC) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
315 | return 162000; |
316 | case DDI_CLK_SEL_TBT_270((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xD) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
317 | return 270000; |
318 | case DDI_CLK_SEL_TBT_540((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xE) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
319 | return 540000; |
320 | case DDI_CLK_SEL_TBT_810((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xF) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
321 | return 810000; |
322 | default: |
323 | MISSING_CASE(val)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "val", (long)(val)); __builtin_expect(!!(__ret), 0); }); |
324 | return 0; |
325 | } |
326 | } |
327 | |
328 | static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) |
329 | { |
330 | /* CRT dotclock is determined via other means */ |
331 | if (pipe_config->has_pch_encoder) |
332 | return; |
333 | |
334 | pipe_config->hw.adjusted_mode.crtc_clock = |
335 | intel_crtc_dotclock(pipe_config); |
336 | } |
337 | |
338 | void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, |
339 | const struct drm_connector_state *conn_state) |
340 | { |
341 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
342 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
343 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
344 | u32 temp; |
345 | |
346 | if (!intel_crtc_has_dp_encoder(crtc_state)) |
347 | return; |
348 | |
349 | drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))({ int __ret = !!((transcoder_is_dsi(cpu_transcoder))); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "transcoder_is_dsi(cpu_transcoder)" ")"); __builtin_expect(!!(__ret), 0); }); |
350 | |
351 | temp = DP_MSA_MISC_SYNC_CLOCK(1 << 0); |
352 | |
353 | switch (crtc_state->pipe_bpp) { |
354 | case 18: |
355 | temp |= DP_MSA_MISC_6_BPC(0 << 5); |
356 | break; |
357 | case 24: |
358 | temp |= DP_MSA_MISC_8_BPC(1 << 5); |
359 | break; |
360 | case 30: |
361 | temp |= DP_MSA_MISC_10_BPC(2 << 5); |
362 | break; |
363 | case 36: |
364 | temp |= DP_MSA_MISC_12_BPC(3 << 5); |
365 | break; |
366 | default: |
367 | MISSING_CASE(crtc_state->pipe_bpp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "crtc_state->pipe_bpp", (long)(crtc_state->pipe_bpp)) ; __builtin_expect(!!(__ret), 0); }); |
368 | break; |
369 | } |
370 | |
371 | /* nonsense combination */ |
372 | drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&({ int __ret = !!((crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB" ")"); __builtin_expect(!!(__ret), 0); }) |
373 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)({ int __ret = !!((crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "crtc_state->limited_color_range && crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB" ")"); __builtin_expect(!!(__ret), 0); }); |
374 | |
375 | if (crtc_state->limited_color_range) |
376 | temp |= DP_MSA_MISC_COLOR_CEA_RGB((0) << 15 | (0) << 4 | (1) << 3 | ((0) << 1)); |
377 | |
378 | /* |
379 | * As per DP 1.2 spec section 2.3.4.3 while sending |
380 | * YCBCR 444 signals we should program MSA MISC1/0 fields with |
381 | * colorspace information. |
382 | */ |
383 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
384 | temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709((0) << 15 | (1) << 4 | (1) << 3 | ((2) << 1)); |
385 | |
386 | /* |
387 | * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication |
388 | * of Color Encoding Format and Content Color Gamut] while sending |
389 | * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields |
390 | * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format. |
391 | */ |
392 | if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) |
393 | temp |= DP_MSA_MISC_COLOR_VSC_SDP(1 << 14); |
394 | |
395 | intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60410)) }), temp); |
396 | } |
397 | |
398 | static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) |
399 | { |
400 | if (master_transcoder == TRANSCODER_EDP) |
401 | return 0; |
402 | else |
403 | return master_transcoder + 1; |
404 | } |
405 | |
406 | static void |
407 | intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder, |
408 | const struct intel_crtc_state *crtc_state) |
409 | { |
410 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
411 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
412 | u32 val = 0; |
413 | |
414 | if (intel_dp_is_uhbr(crtc_state)) |
415 | val = TRANS_DP2_128B132B_CHANNEL_CODING((u32)((1UL << (31)) + 0)); |
416 | |
417 | intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder)((const i915_reg_t){ .reg = (((0x600a0) + (cpu_transcoder) * ( (0x610a0) - (0x600a0)))) }), val); |
418 | } |
419 | |
420 | /* |
421 | * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state. |
422 | * |
423 | * Only intended to be used by intel_ddi_enable_transcoder_func() and |
424 | * intel_ddi_config_transcoder_func(). |
425 | */ |
426 | static u32 |
427 | intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder, |
428 | const struct intel_crtc_state *crtc_state) |
429 | { |
430 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
431 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
432 | enum pipe pipe = crtc->pipe; |
433 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
434 | enum port port = encoder->port; |
435 | u32 temp; |
436 | |
437 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
438 | temp = TRANS_DDI_FUNC_ENABLE(1 << 31); |
439 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
440 | temp |= TGL_TRANS_DDI_SELECT_PORT(port)(((port) + 1) << 27); |
441 | else |
442 | temp |= TRANS_DDI_SELECT_PORT(port)((port) << 28); |
443 | |
444 | switch (crtc_state->pipe_bpp) { |
445 | default: |
446 | MISSING_CASE(crtc_state->pipe_bpp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "crtc_state->pipe_bpp", (long)(crtc_state->pipe_bpp)) ; __builtin_expect(!!(__ret), 0); }); |
447 | fallthroughdo {} while (0); |
448 | case 18: |
449 | temp |= TRANS_DDI_BPC_6(2 << 20); |
450 | break; |
451 | case 24: |
452 | temp |= TRANS_DDI_BPC_8(0 << 20); |
453 | break; |
454 | case 30: |
455 | temp |= TRANS_DDI_BPC_10(1 << 20); |
456 | break; |
457 | case 36: |
458 | temp |= TRANS_DDI_BPC_12(3 << 20); |
459 | break; |
460 | } |
461 | |
462 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC(1<<2)) |
463 | temp |= TRANS_DDI_PVSYNC(1 << 17); |
464 | if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC(1<<0)) |
465 | temp |= TRANS_DDI_PHSYNC(1 << 16); |
466 | |
467 | if (cpu_transcoder == TRANSCODER_EDP) { |
468 | switch (pipe) { |
469 | default: |
470 | MISSING_CASE(pipe)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "pipe", (long)(pipe)); __builtin_expect(!!(__ret), 0); }); |
471 | fallthroughdo {} while (0); |
472 | case PIPE_A: |
473 | /* On Haswell, can only use the always-on power well for |
474 | * eDP when not using the panel fitter, and when not |
475 | * using motion blur mitigation (which we don't |
476 | * support). */ |
477 | if (crtc_state->pch_pfit.force_thru) |
478 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF(4 << 12); |
479 | else |
480 | temp |= TRANS_DDI_EDP_INPUT_A_ON(0 << 12); |
481 | break; |
482 | case PIPE_B: |
483 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF(5 << 12); |
484 | break; |
485 | case PIPE_C: |
486 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF(6 << 12); |
487 | break; |
488 | } |
489 | } |
490 | |
491 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
492 | if (crtc_state->has_hdmi_sink) |
493 | temp |= TRANS_DDI_MODE_SELECT_HDMI(0 << 24); |
494 | else |
495 | temp |= TRANS_DDI_MODE_SELECT_DVI(1 << 24); |
496 | |
497 | if (crtc_state->hdmi_scrambling) |
498 | temp |= TRANS_DDI_HDMI_SCRAMBLING(1 << 0); |
499 | if (crtc_state->hdmi_high_tmds_clock_ratio) |
500 | temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE(1 << 4); |
501 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { |
502 | temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B(4 << 24); |
503 | temp |= (crtc_state->fdi_lanes - 1) << 1; |
504 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { |
505 | if (intel_dp_is_uhbr(crtc_state)) |
506 | temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B(4 << 24); |
507 | else |
508 | temp |= TRANS_DDI_MODE_SELECT_DP_MST(3 << 24); |
509 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count)(((crtc_state->lane_count) - 1) << 1); |
510 | |
511 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
512 | enum transcoder master; |
513 | |
514 | master = crtc_state->mst_master_transcoder; |
515 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((master == INVALID_TRANSCODER)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "master == INVALID_TRANSCODER" ")"); __builtin_expect(!!(__ret), 0); }) |
516 | master == INVALID_TRANSCODER)({ int __ret = !!((master == INVALID_TRANSCODER)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "master == INVALID_TRANSCODER" ")"); __builtin_expect(!!(__ret), 0); }); |
517 | temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master)((u32)((((typeof(((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) << (10))) + 0))))(master) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) << (10))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (11 ) - 1)) & ((~0UL) << (10))) + 0)))) + 0 + 0 + 0 + 0 )); |
518 | } |
519 | } else { |
520 | temp |= TRANS_DDI_MODE_SELECT_DP_SST(2 << 24); |
521 | temp |= DDI_PORT_WIDTH(crtc_state->lane_count)(((crtc_state->lane_count) - 1) << 1); |
522 | } |
523 | |
524 | if (IS_DISPLAY_VER(dev_priv, 8, 10)(((&(dev_priv)->__runtime)->display.ip.ver) >= ( 8) && ((&(dev_priv)->__runtime)->display.ip .ver) <= (10)) && |
525 | crtc_state->master_transcoder != INVALID_TRANSCODER) { |
526 | u8 master_select = |
527 | bdw_trans_port_sync_master_select(crtc_state->master_transcoder); |
528 | |
529 | temp |= TRANS_DDI_PORT_SYNC_ENABLE((u32)((1UL << (15)) + 0)) | |
530 | TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select)((u32)((((typeof(((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) << (18))) + 0))))((master_select)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) << (18))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (19 ) - 1)) & ((~0UL) << (18))) + 0)))) + 0 + 0 + 0 + 0 )); |
531 | } |
532 | |
533 | return temp; |
534 | } |
535 | |
536 | void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, |
537 | const struct intel_crtc_state *crtc_state) |
538 | { |
539 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
540 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
541 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
542 | |
543 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
544 | enum transcoder master_transcoder = crtc_state->master_transcoder; |
545 | u32 ctl2 = 0; |
546 | |
547 | if (master_transcoder != INVALID_TRANSCODER) { |
548 | u8 master_select = |
549 | bdw_trans_port_sync_master_select(master_transcoder); |
550 | |
551 | ctl2 |= PORT_SYNC_MODE_ENABLE((u32)((1UL << (4)) + 0)) | |
552 | PORT_SYNC_MODE_MASTER_SELECT(master_select)((u32)((((typeof(((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) << (0))) + 0))))((master_select)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) << (0))) + 0)))) + 0 + 0 + 0 + 0)); |
553 | } |
554 | |
555 | intel_de_write(dev_priv, |
556 | TRANS_DDI_FUNC_CTL2(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60404)) }), ctl2); |
557 | } |
558 | |
559 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) }), |
560 | intel_ddi_transcoder_func_reg_val_get(encoder, |
561 | crtc_state)); |
562 | } |
563 | |
564 | /* |
565 | * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable |
566 | * bit. |
567 | */ |
568 | static void |
569 | intel_ddi_config_transcoder_func(struct intel_encoder *encoder, |
570 | const struct intel_crtc_state *crtc_state) |
571 | { |
572 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
573 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
574 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
575 | u32 ctl; |
576 | |
577 | ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); |
578 | ctl &= ~TRANS_DDI_FUNC_ENABLE(1 << 31); |
579 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) }), ctl); |
580 | } |
581 | |
582 | void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) |
583 | { |
584 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
585 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
586 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
587 | u32 ctl; |
588 | |
589 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) |
590 | intel_de_write(dev_priv, |
591 | TRANS_DDI_FUNC_CTL2(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60404)) }), 0); |
592 | |
593 | ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
594 | |
595 | drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING)({ int __ret = !!((ctl & (1 << 9))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((crtc->base.dev))-> dev), "", "drm_WARN_ON(" "ctl & (1 << 9)" ")"); __builtin_expect (!!(__ret), 0); }); |
596 | |
597 | ctl &= ~TRANS_DDI_FUNC_ENABLE(1 << 31); |
598 | |
599 | if (IS_DISPLAY_VER(dev_priv, 8, 10)(((&(dev_priv)->__runtime)->display.ip.ver) >= ( 8) && ((&(dev_priv)->__runtime)->display.ip .ver) <= (10))) |
600 | ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE((u32)((1UL << (15)) + 0)) | |
601 | TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) << (18))) + 0))); |
602 | |
603 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
604 | if (!intel_dp_mst_is_master_trans(crtc_state)) { |
605 | ctl &= ~(TGL_TRANS_DDI_PORT_MASK(0xf << 27) | |
606 | TRANS_DDI_MODE_SELECT_MASK(7 << 24)); |
607 | } |
608 | } else { |
609 | ctl &= ~(TRANS_DDI_PORT_MASK(7 << 28) | TRANS_DDI_MODE_SELECT_MASK(7 << 24)); |
610 | } |
611 | |
612 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) }), ctl); |
613 | |
614 | if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) && |
615 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
616 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Quirk Increase DDI disabled time\n" ) |
617 | "Quirk Increase DDI disabled time\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Quirk Increase DDI disabled time\n" ); |
618 | /* Quirk time at 100ms for reliable operation */ |
619 | drm_msleep(100)mdelay(100); |
620 | } |
621 | } |
622 | |
623 | int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, |
624 | enum transcoder cpu_transcoder, |
625 | bool_Bool enable, u32 hdcp_mask) |
626 | { |
627 | struct drm_device *dev = intel_encoder->base.dev; |
628 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
629 | intel_wakeref_t wakeref; |
630 | int ret = 0; |
631 | u32 tmp; |
632 | |
633 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
634 | intel_encoder->power_domain); |
635 | if (drm_WARN_ON(dev, !wakeref)({ int __ret = !!((!wakeref)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((dev))->dev), "", "drm_WARN_ON(" "!wakeref" ")"); __builtin_expect(!!(__ret), 0); })) |
636 | return -ENXIO6; |
637 | |
638 | tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
639 | if (enable) |
640 | tmp |= hdcp_mask; |
641 | else |
642 | tmp &= ~hdcp_mask; |
643 | intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) }), tmp); |
644 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
645 | return ret; |
646 | } |
647 | |
648 | bool_Bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
649 | { |
650 | struct drm_device *dev = intel_connector->base.dev; |
651 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
652 | struct intel_encoder *encoder = intel_attached_encoder(intel_connector); |
653 | int type = intel_connector->base.connector_type; |
654 | enum port port = encoder->port; |
655 | enum transcoder cpu_transcoder; |
656 | intel_wakeref_t wakeref; |
657 | enum pipe pipe = 0; |
658 | u32 tmp; |
659 | bool_Bool ret; |
660 | |
661 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
662 | encoder->power_domain); |
663 | if (!wakeref) |
664 | return false0; |
665 | |
666 | if (!encoder->get_hw_state(encoder, &pipe)) { |
667 | ret = false0; |
668 | goto out; |
669 | } |
670 | |
671 | if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)(((&(dev_priv)->__runtime)->cpu_transcoder_mask & (1UL << (TRANSCODER_EDP))) != 0) && port == PORT_A) |
672 | cpu_transcoder = TRANSCODER_EDP; |
673 | else |
674 | cpu_transcoder = (enum transcoder) pipe; |
675 | |
676 | tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
677 | |
678 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK(7 << 24)) { |
679 | case TRANS_DDI_MODE_SELECT_HDMI(0 << 24): |
680 | case TRANS_DDI_MODE_SELECT_DVI(1 << 24): |
681 | ret = type == DRM_MODE_CONNECTOR_HDMIA11; |
682 | break; |
683 | |
684 | case TRANS_DDI_MODE_SELECT_DP_SST(2 << 24): |
685 | ret = type == DRM_MODE_CONNECTOR_eDP14 || |
686 | type == DRM_MODE_CONNECTOR_DisplayPort10; |
687 | break; |
688 | |
689 | case TRANS_DDI_MODE_SELECT_DP_MST(3 << 24): |
690 | /* if the transcoder is in MST state then |
691 | * connector isn't connected */ |
692 | ret = false0; |
693 | break; |
694 | |
695 | case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B(4 << 24): |
696 | if (HAS_DP20(dev_priv)(IS_PLATFORM(dev_priv, INTEL_DG2) || ((&(dev_priv)->__runtime )->display.ip.ver) >= 14)) |
697 | /* 128b/132b */ |
698 | ret = false0; |
699 | else |
700 | /* FDI */ |
701 | ret = type == DRM_MODE_CONNECTOR_VGA1; |
702 | break; |
703 | |
704 | default: |
705 | ret = false0; |
706 | break; |
707 | } |
708 | |
709 | out: |
710 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
711 | |
712 | return ret; |
713 | } |
714 | |
715 | static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, |
716 | u8 *pipe_mask, bool_Bool *is_dp_mst) |
717 | { |
718 | struct drm_device *dev = encoder->base.dev; |
719 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dev); |
720 | enum port port = encoder->port; |
721 | intel_wakeref_t wakeref; |
722 | enum pipe p; |
723 | u32 tmp; |
724 | u8 mst_pipe_mask; |
725 | |
726 | *pipe_mask = 0; |
727 | *is_dp_mst = false0; |
728 | |
729 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
730 | encoder->power_domain); |
731 | if (!wakeref) |
732 | return; |
733 | |
734 | tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })); |
735 | if (!(tmp & DDI_BUF_CTL_ENABLE(1 << 31))) |
736 | goto out; |
737 | |
738 | if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)(((&(dev_priv)->__runtime)->cpu_transcoder_mask & (1UL << (TRANSCODER_EDP))) != 0) && port == PORT_A) { |
739 | tmp = intel_de_read(dev_priv, |
740 | TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(TRANSCODER_EDP)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
741 | |
742 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK(7 << 12)) { |
743 | default: |
744 | MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "tmp & (7 << 12)", (long)(tmp & (7 << 12 ))); __builtin_expect(!!(__ret), 0); }); |
745 | fallthroughdo {} while (0); |
746 | case TRANS_DDI_EDP_INPUT_A_ON(0 << 12): |
747 | case TRANS_DDI_EDP_INPUT_A_ONOFF(4 << 12): |
748 | *pipe_mask = BIT(PIPE_A)(1UL << (PIPE_A)); |
749 | break; |
750 | case TRANS_DDI_EDP_INPUT_B_ONOFF(5 << 12): |
751 | *pipe_mask = BIT(PIPE_B)(1UL << (PIPE_B)); |
752 | break; |
753 | case TRANS_DDI_EDP_INPUT_C_ONOFF(6 << 12): |
754 | *pipe_mask = BIT(PIPE_C)(1UL << (PIPE_C)); |
755 | break; |
756 | } |
757 | |
758 | goto out; |
759 | } |
760 | |
761 | mst_pipe_mask = 0; |
762 | for_each_pipe(dev_priv, p)for ((p) = 0; (p) < I915_MAX_PIPES; (p)++) if (!((&(dev_priv )->__runtime)->pipe_mask & (1UL << (p)))) {} else { |
763 | enum transcoder cpu_transcoder = (enum transcoder)p; |
764 | unsigned int port_mask, ddi_select; |
765 | intel_wakeref_t trans_wakeref; |
766 | |
767 | trans_wakeref = intel_display_power_get_if_enabled(dev_priv, |
768 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A)); |
769 | if (!trans_wakeref) |
770 | continue; |
771 | |
772 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
773 | port_mask = TGL_TRANS_DDI_PORT_MASK(0xf << 27); |
774 | ddi_select = TGL_TRANS_DDI_SELECT_PORT(port)(((port) + 1) << 27); |
775 | } else { |
776 | port_mask = TRANS_DDI_PORT_MASK(7 << 28); |
777 | ddi_select = TRANS_DDI_SELECT_PORT(port)((port) << 28); |
778 | } |
779 | |
780 | tmp = intel_de_read(dev_priv, |
781 | TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
782 | intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A), |
783 | trans_wakeref); |
784 | |
785 | if ((tmp & port_mask) != ddi_select) |
786 | continue; |
787 | |
788 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK(7 << 24)) == TRANS_DDI_MODE_SELECT_DP_MST(3 << 24) || |
789 | (HAS_DP20(dev_priv)(IS_PLATFORM(dev_priv, INTEL_DG2) || ((&(dev_priv)->__runtime )->display.ip.ver) >= 14) && |
790 | (tmp & TRANS_DDI_MODE_SELECT_MASK(7 << 24)) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B(4 << 24))) |
791 | mst_pipe_mask |= BIT(p)(1UL << (p)); |
792 | |
793 | *pipe_mask |= BIT(p)(1UL << (p)); |
794 | } |
795 | |
796 | if (!*pipe_mask) |
797 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No pipe for [ENCODER:%d:%s] found\n" , encoder->base.base.id, encoder->base.name) |
798 | "No pipe for [ENCODER:%d:%s] found\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No pipe for [ENCODER:%d:%s] found\n" , encoder->base.base.id, encoder->base.name) |
799 | encoder->base.base.id, encoder->base.name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "No pipe for [ENCODER:%d:%s] found\n" , encoder->base.base.id, encoder->base.name); |
800 | |
801 | if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) { |
802 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask ) |
803 | "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask ) |
804 | encoder->base.base.id, encoder->base.name,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask ) |
805 | *pipe_mask)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask ); |
806 | *pipe_mask = BIT(ffs(*pipe_mask) - 1)(1UL << (ffs(*pipe_mask) - 1)); |
807 | } |
808 | |
809 | if (mst_pipe_mask && mst_pipe_mask != *pipe_mask) |
810 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask , mst_pipe_mask) |
811 | "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask , mst_pipe_mask) |
812 | encoder->base.base.id, encoder->base.name,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask , mst_pipe_mask) |
813 | *pipe_mask, mst_pipe_mask)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n" , encoder->base.base.id, encoder->base.name, *pipe_mask , mst_pipe_mask); |
814 | else |
815 | *is_dp_mst = mst_pipe_mask; |
816 | |
817 | out: |
818 | if (*pipe_mask && (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON))) { |
819 | tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port)((const i915_reg_t){ .reg = (((0x64C00) + (port) * ((0x64C10) - (0x64C00)))) })); |
820 | if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK(1 << 10) | |
821 | BXT_PHY_LANE_POWERDOWN_ACK(1 << 9) | |
822 | BXT_PHY_LANE_ENABLED(1 << 8))) != BXT_PHY_LANE_ENABLED(1 << 8)) |
823 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , encoder ->base.base.id, encoder->base.name, tmp) |
824 | "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , encoder ->base.base.id, encoder->base.name, tmp) |
825 | encoder->base.base.id, encoder->base.name, tmp)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , encoder ->base.base.id, encoder->base.name, tmp); |
826 | } |
827 | |
828 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
829 | } |
830 | |
831 | bool_Bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
832 | enum pipe *pipe) |
833 | { |
834 | u8 pipe_mask; |
835 | bool_Bool is_mst; |
836 | |
837 | intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); |
838 | |
839 | if (is_mst || !pipe_mask) |
840 | return false0; |
841 | |
842 | *pipe = ffs(pipe_mask) - 1; |
843 | |
844 | return true1; |
845 | } |
846 | |
847 | static enum intel_display_power_domain |
848 | intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port) |
849 | { |
850 | /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with |
851 | * DC states enabled at the same time, while for driver initiated AUX |
852 | * transfers we need the same AUX IOs to be powered but with DC states |
853 | * disabled. Accordingly use the AUX power domain here which leaves DC |
854 | * states enabled. |
855 | * However, for non-A AUX ports the corresponding non-EDP transcoders |
856 | * would have already enabled power well 2 and DC_OFF. This means we can |
857 | * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a |
858 | * specific AUX_IO reference without powering up any extra wells. |
859 | * Note that PSR is enabled only on Port A even though this function |
860 | * returns the correct domain for other ports too. |
861 | */ |
862 | return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A : |
863 | intel_aux_power_domain(dig_port); |
864 | } |
865 | |
866 | static void intel_ddi_get_power_domains(struct intel_encoder *encoder, |
867 | struct intel_crtc_state *crtc_state) |
868 | { |
869 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
870 | struct intel_digital_port *dig_port; |
871 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
872 | |
873 | /* |
874 | * TODO: Add support for MST encoders. Atm, the following should never |
875 | * happen since fake-MST encoders don't set their get_power_domains() |
876 | * hook. |
877 | */ |
878 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)" ")"); __builtin_expect(!!(__ret), 0); }) |
879 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))({ int __ret = !!((intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)" ")"); __builtin_expect(!!(__ret), 0); })) |
880 | return; |
881 | |
882 | dig_port = enc_to_dig_port(encoder); |
883 | |
884 | if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { |
885 | drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref)({ int __ret = !!((dig_port->ddi_io_wakeref)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "dig_port->ddi_io_wakeref" ")"); __builtin_expect (!!(__ret), 0); }); |
886 | dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, |
887 | dig_port->ddi_io_power_domain); |
888 | } |
889 | |
890 | /* |
891 | * AUX power is only needed for (e)DP mode, and for HDMI mode on TC |
892 | * ports. |
893 | */ |
894 | if (intel_crtc_has_dp_encoder(crtc_state) || |
895 | intel_phy_is_tc(dev_priv, phy)) { |
896 | drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref)({ int __ret = !!((dig_port->aux_wakeref)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "dig_port->aux_wakeref" ")"); __builtin_expect (!!(__ret), 0); }); |
897 | dig_port->aux_wakeref = |
898 | intel_display_power_get(dev_priv, |
899 | intel_ddi_main_link_aux_domain(dig_port)); |
900 | } |
901 | } |
902 | |
903 | void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, |
904 | const struct intel_crtc_state *crtc_state) |
905 | { |
906 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
907 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
908 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
909 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
910 | u32 val; |
911 | |
912 | if (cpu_transcoder != TRANSCODER_EDP) { |
913 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 13) |
914 | val = TGL_TRANS_CLK_SEL_PORT(phy)(((phy) + 1) << 28); |
915 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
916 | val = TGL_TRANS_CLK_SEL_PORT(encoder->port)(((encoder->port) + 1) << 28); |
917 | else |
918 | val = TRANS_CLK_SEL_PORT(encoder->port)(((encoder->port) + 1) << 29); |
919 | |
920 | intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder)((const i915_reg_t){ .reg = (((0x46140) + (cpu_transcoder) * ( (0x46144) - (0x46140)))) }), val); |
921 | } |
922 | } |
923 | |
924 | void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state) |
925 | { |
926 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
927 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
928 | |
929 | if (cpu_transcoder != TRANSCODER_EDP) { |
930 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
931 | intel_de_write(dev_priv, |
932 | TRANS_CLK_SEL(cpu_transcoder)((const i915_reg_t){ .reg = (((0x46140) + (cpu_transcoder) * ( (0x46144) - (0x46140)))) }), |
933 | TGL_TRANS_CLK_SEL_DISABLED(0x0 << 28)); |
934 | else |
935 | intel_de_write(dev_priv, |
936 | TRANS_CLK_SEL(cpu_transcoder)((const i915_reg_t){ .reg = (((0x46140) + (cpu_transcoder) * ( (0x46144) - (0x46140)))) }), |
937 | TRANS_CLK_SEL_DISABLED(0x0 << 29)); |
938 | } |
939 | } |
940 | |
941 | static void _skl_ddi_set_iboost(struct drm_i915_privateinteldrm_softc *dev_priv, |
942 | enum port port, u8 iboost) |
943 | { |
944 | u32 tmp; |
945 | |
946 | tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0((const i915_reg_t){ .reg = (0x6C00C) })); |
947 | tmp &= ~(BALANCE_LEG_MASK(port)(7 << (8 + 3 * (port))) | BALANCE_LEG_DISABLE(port)(1 << (23 + (port)))); |
948 | if (iboost) |
949 | tmp |= iboost << BALANCE_LEG_SHIFT(port)(8 + 3 * (port)); |
950 | else |
951 | tmp |= BALANCE_LEG_DISABLE(port)(1 << (23 + (port))); |
952 | intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0((const i915_reg_t){ .reg = (0x6C00C) }), tmp); |
953 | } |
954 | |
955 | static void skl_ddi_set_iboost(struct intel_encoder *encoder, |
956 | const struct intel_crtc_state *crtc_state, |
957 | int level) |
958 | { |
959 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
960 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
961 | u8 iboost; |
962 | |
963 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
964 | iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata); |
965 | else |
966 | iboost = intel_bios_encoder_dp_boost_level(encoder->devdata); |
967 | |
968 | if (iboost == 0) { |
969 | const struct intel_ddi_buf_trans *trans; |
970 | int n_entries; |
971 | |
972 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
973 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
974 | return; |
975 | |
976 | iboost = trans->entries[level].hsw.i_boost; |
977 | } |
978 | |
979 | /* Make sure that the requested I_boost is valid */ |
980 | if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { |
981 | drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Invalid I_boost value %u\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , iboost ); |
982 | return; |
983 | } |
984 | |
985 | _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); |
986 | |
987 | if (encoder->port == PORT_A && dig_port->max_lanes == 4) |
988 | _skl_ddi_set_iboost(dev_priv, PORT_E, iboost); |
989 | } |
990 | |
991 | static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp, |
992 | const struct intel_crtc_state *crtc_state) |
993 | { |
994 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
995 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
996 | int n_entries; |
997 | |
998 | encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
999 | |
1000 | if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)({ int __ret = !!((n_entries < 1)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "n_entries < 1" ")"); __builtin_expect(!! (__ret), 0); })) |
1001 | n_entries = 1; |
1002 | if (drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((n_entries > (sizeof((index_to_dp_signal_levels )) / sizeof((index_to_dp_signal_levels)[0])))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "n_entries > (sizeof((index_to_dp_signal_levels)) / sizeof((index_to_dp_signal_levels)[0]))" ")"); __builtin_expect(!!(__ret), 0); }) |
1003 | n_entries > ARRAY_SIZE(index_to_dp_signal_levels))({ int __ret = !!((n_entries > (sizeof((index_to_dp_signal_levels )) / sizeof((index_to_dp_signal_levels)[0])))); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "n_entries > (sizeof((index_to_dp_signal_levels)) / sizeof((index_to_dp_signal_levels)[0]))" ")"); __builtin_expect(!!(__ret), 0); })) |
1004 | n_entries = ARRAY_SIZE(index_to_dp_signal_levels)(sizeof((index_to_dp_signal_levels)) / sizeof((index_to_dp_signal_levels )[0])); |
1005 | |
1006 | return index_to_dp_signal_levels[n_entries - 1] & |
1007 | DP_TRAIN_VOLTAGE_SWING_MASK0x3; |
1008 | } |
1009 | |
1010 | /* |
1011 | * We assume that the full set of pre-emphasis values can be |
1012 | * used on all DDI platforms. Should that change we need to |
1013 | * rethink this code. |
1014 | */ |
1015 | static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp) |
1016 | { |
1017 | return DP_TRAIN_PRE_EMPH_LEVEL_3(3 << 3); |
1018 | } |
1019 | |
1020 | static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state, |
1021 | int lane) |
1022 | { |
1023 | if (crtc_state->port_clock > 600000) |
1024 | return 0; |
1025 | |
1026 | if (crtc_state->lane_count == 4) |
1027 | return lane >= 1 ? LOADGEN_SELECT(1 << 31) : 0; |
1028 | else |
1029 | return lane == 1 || lane == 2 ? LOADGEN_SELECT(1 << 31) : 0; |
1030 | } |
1031 | |
1032 | static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder, |
1033 | const struct intel_crtc_state *crtc_state) |
1034 | { |
1035 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
1036 | const struct intel_ddi_buf_trans *trans; |
1037 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
1038 | int n_entries, ln; |
1039 | u32 val; |
1040 | |
1041 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
1042 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1043 | return; |
1044 | |
1045 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) { |
1046 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1047 | |
1048 | val = EDP4K2K_MODE_OVRD_EN(1 << 3) | EDP4K2K_MODE_OVRD_OPTIMIZED(1 << 2); |
1049 | intel_dp->hobl_active = is_hobl_buf_trans(trans); |
1050 | intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + 4 * (10))) }), val, |
1051 | intel_dp->hobl_active ? val : 0); |
1052 | } |
1053 | |
1054 | /* Set PORT_TX_DW5 */ |
1055 | val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (0) * 0x100 ) + 4 * (5))) })); |
1056 | val &= ~(SCALING_MODE_SEL_MASK(0x7 << 18) | RTERM_SELECT_MASK(0x7 << 3) | |
1057 | TAP2_DISABLE(1 << 30) | TAP3_DISABLE(1 << 29)); |
1058 | val |= SCALING_MODE_SEL(0x2)((0x2) << 18); |
1059 | val |= RTERM_SELECT(0x6)((0x6) << 3); |
1060 | val |= TAP3_DISABLE(1 << 29); |
1061 | intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + 0x680 + 4 * (5))) } ), val); |
1062 | |
1063 | /* Program PORT_TX_DW2 */ |
1064 | for (ln = 0; ln < 4; ln++) { |
1065 | int level = intel_ddi_level(encoder, crtc_state, ln); |
1066 | |
1067 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (ln) * 0x100 ) + 4 * (2))) }), |
1068 | SWING_SEL_UPPER_MASK(1 << 15) | SWING_SEL_LOWER_MASK(0x7 << 11) | RCOMP_SCALAR_MASK(0xFF << 0), |
1069 | SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel)(((trans->entries[level].icl.dw2_swing_sel) >> 3) << 15) | |
1070 | SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel)(((trans->entries[level].icl.dw2_swing_sel) & 0x7) << 11) | |
1071 | RCOMP_SCALAR(0x98)((0x98) << 0)); |
1072 | } |
1073 | |
1074 | /* Program PORT_TX_DW4 */ |
1075 | /* We cannot write to GRP. It would overwrite individual loadgen. */ |
1076 | for (ln = 0; ln < 4; ln++) { |
1077 | int level = intel_ddi_level(encoder, crtc_state, ln); |
1078 | |
1079 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (ln) * 0x100 ) + 4 * (4))) }), |
1080 | POST_CURSOR_1_MASK(0x3F << 12) | POST_CURSOR_2_MASK(0x3F << 6) | CURSOR_COEFF_MASK(0x3F << 0), |
1081 | POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1)((trans->entries[level].icl.dw4_post_cursor_1) << 12 ) | |
1082 | POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2)((trans->entries[level].icl.dw4_post_cursor_2) << 6) | |
1083 | CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)((trans->entries[level].icl.dw4_cursor_coeff) << 0)); |
1084 | } |
1085 | |
1086 | /* Program PORT_TX_DW7 */ |
1087 | for (ln = 0; ln < 4; ln++) { |
1088 | int level = intel_ddi_level(encoder, crtc_state, ln); |
1089 | |
1090 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (ln) * 0x100 ) + 4 * (7))) }), |
1091 | N_SCALAR_MASK(0x7F << 24), |
1092 | N_SCALAR(trans->entries[level].icl.dw7_n_scalar)((trans->entries[level].icl.dw7_n_scalar) << 24)); |
1093 | } |
1094 | } |
1095 | |
1096 | static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder, |
1097 | const struct intel_crtc_state *crtc_state) |
1098 | { |
1099 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
1100 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
1101 | u32 val; |
1102 | int ln; |
1103 | |
1104 | /* |
1105 | * 1. If port type is eDP or DP, |
1106 | * set PORT_PCS_DW1 cmnkeeper_enable to 1b, |
1107 | * else clear to 0b. |
1108 | */ |
1109 | val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x800 + (0) * 0x100 ) + 4 * (1))) })); |
1110 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
1111 | val &= ~COMMON_KEEPER_EN(1 << 26); |
1112 | else |
1113 | val |= COMMON_KEEPER_EN(1 << 26); |
1114 | intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + 0x600 + 4 * (1))) } ), val); |
1115 | |
1116 | /* 2. Program loadgen select */ |
1117 | /* |
1118 | * Program PORT_TX_DW4 depending on Bit rate and used lanes |
1119 | * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1) |
1120 | * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0) |
1121 | * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) |
1122 | */ |
1123 | for (ln = 0; ln < 4; ln++) { |
1124 | intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (ln) * 0x100 ) + 4 * (4))) }), |
1125 | LOADGEN_SELECT(1 << 31), |
1126 | icl_combo_phy_loadgen_select(crtc_state, ln)); |
1127 | } |
1128 | |
1129 | /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ |
1130 | intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + 4 * (5))) }), |
1131 | 0, SUS_CLOCK_CONFIG(3 << 0)); |
1132 | |
1133 | /* 4. Clear training enable to change swing values */ |
1134 | val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (0) * 0x100 ) + 4 * (5))) })); |
1135 | val &= ~TX_TRAINING_EN(1 << 31); |
1136 | intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + 0x680 + 4 * (5))) } ), val); |
1137 | |
1138 | /* 5. Program swing and de-emphasis */ |
1139 | icl_ddi_combo_vswing_program(encoder, crtc_state); |
1140 | |
1141 | /* 6. Set training enable to trigger update */ |
1142 | val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + (0x880 + (0) * 0x100 ) + 4 * (5))) })); |
1143 | val |= TX_TRAINING_EN(1 << 31); |
1144 | intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy)((const i915_reg_t){ .reg = (((((const u32 []){ 0x162000, 0x6C000 , 0x160000, 0x161000, 0x16B000 })[phy]) + 0x680 + 4 * (5))) } ), val); |
1145 | } |
1146 | |
1147 | static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder, |
1148 | const struct intel_crtc_state *crtc_state) |
1149 | { |
1150 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
1151 | enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); |
1152 | const struct intel_ddi_buf_trans *trans; |
1153 | int n_entries, ln; |
1154 | |
1155 | if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) |
1156 | return; |
1157 | |
1158 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
1159 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1160 | return; |
1161 | |
1162 | for (ln = 0; ln < 2; ln++) { |
1163 | intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port)((const i915_reg_t){ .reg = (((0x16812C) + (tc_port) * ((0x16912C ) - (0x16812C))) + (ln) * ((0x16852C) - (0x16812C))) }), |
1164 | CRI_USE_FS32(1 << 5), 0); |
1165 | intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680AC) + (tc_port) * ((0x1690AC ) - (0x1680AC))) + (ln) * ((0x1684AC) - (0x1680AC))) }), |
1166 | CRI_USE_FS32(1 << 5), 0); |
1167 | } |
1168 | |
1169 | /* Program MG_TX_SWINGCTRL with values from vswing table */ |
1170 | for (ln = 0; ln < 2; ln++) { |
1171 | int level; |
1172 | |
1173 | level = intel_ddi_level(encoder, crtc_state, 2*ln+0); |
1174 | |
1175 | intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x168148) + (tc_port) * ((0x169148 ) - (0x168148))) + (ln) * ((0x168548) - (0x168148))) }), |
1176 | CRI_TXDEEMPH_OVERRIDE_17_12_MASK(0x3F << 0), |
1177 | CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)((trans->entries[level].mg.cri_txdeemph_override_17_12) << 0)); |
1178 | |
1179 | level = intel_ddi_level(encoder, crtc_state, 2*ln+1); |
1180 | |
1181 | intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680C8) + (tc_port) * ((0x1690C8 ) - (0x1680C8))) + (ln) * ((0x1684C8) - (0x1680C8))) }), |
1182 | CRI_TXDEEMPH_OVERRIDE_17_12_MASK(0x3F << 0), |
1183 | CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)((trans->entries[level].mg.cri_txdeemph_override_17_12) << 0)); |
1184 | } |
1185 | |
1186 | /* Program MG_TX_DRVCTRL with values from vswing table */ |
1187 | for (ln = 0; ln < 2; ln++) { |
1188 | int level; |
1189 | |
1190 | level = intel_ddi_level(encoder, crtc_state, 2*ln+0); |
1191 | |
1192 | intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x168144) + (tc_port) * ((0x169144 ) - (0x168144))) + (ln) * ((0x168544) - (0x168144))) }), |
1193 | CRI_TXDEEMPH_OVERRIDE_11_6_MASK(0x3F << 24) | |
1194 | CRI_TXDEEMPH_OVERRIDE_5_0_MASK(0x3F << 16), |
1195 | CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6)((trans->entries[level].mg.cri_txdeemph_override_11_6) << 24) | |
1196 | CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0)((trans->entries[level].mg.cri_txdeemph_override_5_0) << 16) | |
1197 | CRI_TXDEEMPH_OVERRIDE_EN(1 << 22)); |
1198 | |
1199 | level = intel_ddi_level(encoder, crtc_state, 2*ln+1); |
1200 | |
1201 | intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680C4) + (tc_port) * ((0x1690C4 ) - (0x1680C4))) + (ln) * ((0x1684C4) - (0x1680C4))) }), |
1202 | CRI_TXDEEMPH_OVERRIDE_11_6_MASK(0x3F << 24) | |
1203 | CRI_TXDEEMPH_OVERRIDE_5_0_MASK(0x3F << 16), |
1204 | CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6)((trans->entries[level].mg.cri_txdeemph_override_11_6) << 24) | |
1205 | CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0)((trans->entries[level].mg.cri_txdeemph_override_5_0) << 16) | |
1206 | CRI_TXDEEMPH_OVERRIDE_EN(1 << 22)); |
1207 | |
1208 | /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ |
1209 | } |
1210 | |
1211 | /* |
1212 | * Program MG_CLKHUB<LN, port being used> with value from frequency table |
1213 | * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the |
1214 | * values from table for which TX1 and TX2 enabled. |
1215 | */ |
1216 | for (ln = 0; ln < 2; ln++) { |
1217 | intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port)((const i915_reg_t){ .reg = (((0x16839C) + (tc_port) * ((0x16939C ) - (0x16839C))) + (ln) * ((0x16879C) - (0x16839C))) }), |
1218 | CFG_LOW_RATE_LKREN_EN(1 << 11), |
1219 | crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN(1 << 11) : 0); |
1220 | } |
1221 | |
1222 | /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ |
1223 | for (ln = 0; ln < 2; ln++) { |
1224 | intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port)((const i915_reg_t){ .reg = (((0x168110) + (tc_port) * ((0x169110 ) - (0x168110))) + (ln) * ((0x168510) - (0x168110))) }), |
1225 | CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK(0x3 << 25) | |
1226 | CFG_AMI_CK_DIV_OVERRIDE_EN(1 << 24), |
1227 | crtc_state->port_clock > 500000 ? |
1228 | CFG_AMI_CK_DIV_OVERRIDE_VAL(1)((1) << 25) | |
1229 | CFG_AMI_CK_DIV_OVERRIDE_EN(1 << 24) : 0); |
1230 | |
1231 | intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port)((const i915_reg_t){ .reg = (((0x168090) + (tc_port) * ((0x169090 ) - (0x168090))) + (ln) * ((0x168490) - (0x168090))) }), |
1232 | CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK(0x3 << 25) | |
1233 | CFG_AMI_CK_DIV_OVERRIDE_EN(1 << 24), |
1234 | crtc_state->port_clock > 500000 ? |
1235 | CFG_AMI_CK_DIV_OVERRIDE_VAL(1)((1) << 25) | |
1236 | CFG_AMI_CK_DIV_OVERRIDE_EN(1 << 24) : 0); |
1237 | } |
1238 | |
1239 | /* Program MG_TX_PISO_READLOAD with values from vswing table */ |
1240 | for (ln = 0; ln < 2; ln++) { |
1241 | intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port)((const i915_reg_t){ .reg = (((0x16814C) + (tc_port) * ((0x16914C ) - (0x16814C))) + (ln) * ((0x16854C) - (0x16814C))) }), |
1242 | 0, CRI_CALCINIT(1 << 1)); |
1243 | intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port)((const i915_reg_t){ .reg = (((0x1680CC) + (tc_port) * ((0x1690CC ) - (0x1680CC))) + (ln) * ((0x1684CC) - (0x1680CC))) }), |
1244 | 0, CRI_CALCINIT(1 << 1)); |
1245 | } |
1246 | } |
1247 | |
1248 | static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder, |
1249 | const struct intel_crtc_state *crtc_state) |
1250 | { |
1251 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
1252 | enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port); |
1253 | const struct intel_ddi_buf_trans *trans; |
1254 | int n_entries, ln; |
1255 | |
1256 | if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder))) |
1257 | return; |
1258 | |
1259 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
1260 | if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1261 | return; |
1262 | |
1263 | for (ln = 0; ln < 2; ln++) { |
1264 | int level; |
1265 | |
1266 | intel_dkl_phy_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0xD00) }), ln, 0); |
1267 | |
1268 | level = intel_ddi_level(encoder, crtc_state, 2*ln+0); |
1269 | |
1270 | intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0x2C0) }), ln, |
1271 | DKL_TX_PRESHOOT_COEFF_MASK(0x1f << 13) | |
1272 | DKL_TX_DE_EMPAHSIS_COEFF_MASK(0x1f << 8) | |
1273 | DKL_TX_VSWING_CONTROL_MASK(0x7 << 0), |
1274 | DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot)((trans->entries[level].dkl.preshoot) << 13) | |
1275 | DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis)((trans->entries[level].dkl.de_emphasis) << 8) | |
1276 | DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)((trans->entries[level].dkl.vswing) << 0)); |
1277 | |
1278 | level = intel_ddi_level(encoder, crtc_state, 2*ln+1); |
1279 | |
1280 | intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0x2C4) }), ln, |
1281 | DKL_TX_PRESHOOT_COEFF_MASK(0x1f << 13) | |
1282 | DKL_TX_DE_EMPAHSIS_COEFF_MASK(0x1f << 8) | |
1283 | DKL_TX_VSWING_CONTROL_MASK(0x7 << 0), |
1284 | DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot)((trans->entries[level].dkl.preshoot) << 13) | |
1285 | DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis)((trans->entries[level].dkl.de_emphasis) << 8) | |
1286 | DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)((trans->entries[level].dkl.vswing) << 0)); |
1287 | |
1288 | intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0x2C8) }), ln, |
1289 | DKL_TX_DP20BITMODE((u32)((1UL << (2)) + 0)), 0); |
1290 | |
1291 | if (IS_ALDERLAKE_P(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)) { |
1292 | u32 val; |
1293 | |
1294 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
1295 | if (ln == 0) { |
1296 | val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0))))((0)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0)))) + 0 + 0 + 0 + 0)); |
1297 | val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2)((u32)((((typeof(((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0))))((2)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0)))) + 0 + 0 + 0 + 0)); |
1298 | } else { |
1299 | val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3)((u32)((((typeof(((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0))))((3)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0)))) + 0 + 0 + 0 + 0)); |
1300 | val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3)((u32)((((typeof(((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0))))((3)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0)))) + 0 + 0 + 0 + 0)); |
1301 | } |
1302 | } else { |
1303 | val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0))))((0)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0)))) + 0 + 0 + 0 + 0)); |
1304 | val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0)((u32)((((typeof(((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0))))((0)) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0)))) + 0 + 0 + 0 + 0)); |
1305 | } |
1306 | |
1307 | intel_dkl_phy_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0x2C8) }), ln, |
1308 | DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK((u32)((((~0UL) >> (64 - (4) - 1)) & ((~0UL) << (3))) + 0)) | |
1309 | DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK((u32)((((~0UL) >> (64 - (6) - 1)) & ((~0UL) << (5))) + 0)), |
1310 | val); |
1311 | } |
1312 | } |
1313 | } |
1314 | |
1315 | static int translate_signal_level(struct intel_dp *intel_dp, |
1316 | u8 signal_levels) |
1317 | { |
1318 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
1319 | int i; |
1320 | |
1321 | for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels)(sizeof((index_to_dp_signal_levels)) / sizeof((index_to_dp_signal_levels )[0])); i++) { |
1322 | if (index_to_dp_signal_levels[i] == signal_levels) |
1323 | return i; |
1324 | } |
1325 | |
1326 | drm_WARN(&i915->drm, 1,({ int __ret = !!(1); if (__ret) printf("%s %s: " "Unsupported voltage swing/pre-emphasis level: 0x%x\n" , dev_driver_string((&i915->drm)->dev), "", signal_levels ); __builtin_expect(!!(__ret), 0); }) |
1327 | "Unsupported voltage swing/pre-emphasis level: 0x%x\n",({ int __ret = !!(1); if (__ret) printf("%s %s: " "Unsupported voltage swing/pre-emphasis level: 0x%x\n" , dev_driver_string((&i915->drm)->dev), "", signal_levels ); __builtin_expect(!!(__ret), 0); }) |
1328 | signal_levels)({ int __ret = !!(1); if (__ret) printf("%s %s: " "Unsupported voltage swing/pre-emphasis level: 0x%x\n" , dev_driver_string((&i915->drm)->dev), "", signal_levels ); __builtin_expect(!!(__ret), 0); }); |
1329 | |
1330 | return 0; |
1331 | } |
1332 | |
1333 | static int intel_ddi_dp_level(struct intel_dp *intel_dp, |
1334 | const struct intel_crtc_state *crtc_state, |
1335 | int lane) |
1336 | { |
1337 | u8 train_set = intel_dp->train_set[lane]; |
1338 | |
1339 | if (intel_dp_is_uhbr(crtc_state)) { |
1340 | return train_set & DP_TX_FFE_PRESET_VALUE_MASK(0xf << 0); |
1341 | } else { |
1342 | u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK0x3 | |
1343 | DP_TRAIN_PRE_EMPHASIS_MASK(3 << 3)); |
1344 | |
1345 | return translate_signal_level(intel_dp, signal_levels); |
1346 | } |
1347 | } |
1348 | |
1349 | int intel_ddi_level(struct intel_encoder *encoder, |
1350 | const struct intel_crtc_state *crtc_state, |
1351 | int lane) |
1352 | { |
1353 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1354 | const struct intel_ddi_buf_trans *trans; |
1355 | int level, n_entries; |
1356 | |
1357 | trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); |
1358 | if (drm_WARN_ON_ONCE(&i915->drm, !trans)({ static int __warned; int __ret = !!((!trans)); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string(((& i915->drm))->dev), "", "drm_WARN_ON_ONCE(" "!trans" ")" ); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1359 | return 0; |
1360 | |
1361 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
1362 | level = intel_ddi_hdmi_level(encoder, trans); |
1363 | else |
1364 | level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state, |
1365 | lane); |
1366 | |
1367 | if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)({ static int __warned; int __ret = !!((level >= n_entries )); if (__ret && !__warned) { printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON_ONCE(" "level >= n_entries" ")"); __warned = 1; } __builtin_expect(!!(__ret), 0); })) |
1368 | level = n_entries - 1; |
1369 | |
1370 | return level; |
1371 | } |
1372 | |
1373 | static void |
1374 | hsw_set_signal_levels(struct intel_encoder *encoder, |
1375 | const struct intel_crtc_state *crtc_state) |
1376 | { |
1377 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
1378 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1379 | int level = intel_ddi_level(encoder, crtc_state, 0); |
1380 | enum port port = encoder->port; |
1381 | u32 signal_levels; |
1382 | |
1383 | if (has_iboost(dev_priv)) |
1384 | skl_ddi_set_iboost(encoder, crtc_state, level); |
1385 | |
1386 | /* HDMI ignores the rest */ |
1387 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
1388 | return; |
1389 | |
1390 | signal_levels = DDI_BUF_TRANS_SELECT(level)((level) << 24); |
1391 | |
1392 | drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels) |
1393 | signal_levels)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Using signal levels %08x\n" , signal_levels); |
1394 | |
1395 | intel_dp->DP &= ~DDI_BUF_EMP_MASK(0xf << 24); |
1396 | intel_dp->DP |= signal_levels; |
1397 | |
1398 | intel_de_write(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }), intel_dp->DP); |
1399 | intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })); |
1400 | } |
1401 | |
1402 | static void _icl_ddi_enable_clock(struct drm_i915_privateinteldrm_softc *i915, i915_reg_t reg, |
1403 | u32 clk_sel_mask, u32 clk_sel, u32 clk_off) |
1404 | { |
1405 | mutex_lock(&i915->display.dpll.lock)rw_enter_write(&i915->display.dpll.lock); |
1406 | |
1407 | intel_de_rmw(i915, reg, clk_sel_mask, clk_sel); |
1408 | |
1409 | /* |
1410 | * "This step and the step before must be |
1411 | * done with separate register writes." |
1412 | */ |
1413 | intel_de_rmw(i915, reg, clk_off, 0); |
1414 | |
1415 | mutex_unlock(&i915->display.dpll.lock)rw_exit_write(&i915->display.dpll.lock); |
1416 | } |
1417 | |
1418 | static void _icl_ddi_disable_clock(struct drm_i915_privateinteldrm_softc *i915, i915_reg_t reg, |
1419 | u32 clk_off) |
1420 | { |
1421 | mutex_lock(&i915->display.dpll.lock)rw_enter_write(&i915->display.dpll.lock); |
1422 | |
1423 | intel_de_rmw(i915, reg, 0, clk_off); |
1424 | |
1425 | mutex_unlock(&i915->display.dpll.lock)rw_exit_write(&i915->display.dpll.lock); |
1426 | } |
1427 | |
1428 | static bool_Bool _icl_ddi_is_clock_enabled(struct drm_i915_privateinteldrm_softc *i915, i915_reg_t reg, |
1429 | u32 clk_off) |
1430 | { |
1431 | return !(intel_de_read(i915, reg) & clk_off); |
1432 | } |
1433 | |
1434 | static struct intel_shared_dpll * |
1435 | _icl_ddi_get_pll(struct drm_i915_privateinteldrm_softc *i915, i915_reg_t reg, |
1436 | u32 clk_sel_mask, u32 clk_sel_shift) |
1437 | { |
1438 | enum intel_dpll_id id; |
1439 | |
1440 | id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift; |
1441 | |
1442 | return intel_get_shared_dpll_by_id(i915, id); |
1443 | } |
1444 | |
1445 | static void adls_ddi_enable_clock(struct intel_encoder *encoder, |
1446 | const struct intel_crtc_state *crtc_state) |
1447 | { |
1448 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1449 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1450 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1451 | |
1452 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1453 | return; |
1454 | |
1455 | _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 3) * ((0x1642BC ) - (0x164280)))) }), |
1456 | ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)(((const u32 []){ ((u32)((((~0UL) >> (64 - (1) - 1)) & ((~0UL) << (0))) + 0)), ((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (2))) + 0)), ((u32)((((~0UL ) >> (64 - (5) - 1)) & ((~0UL) << (4))) + 0)) , ((u32)((((~0UL) >> (64 - (1) - 1)) & ((~0UL) << (0))) + 0)), ((u32)((((~0UL) >> (64 - (3) - 1)) & ( (~0UL) << (2))) + 0)) })[(phy)]), |
1457 | pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)(((phy) % 3) * 2), |
1458 | ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24, 4, 5 })[phy]))); |
1459 | } |
1460 | |
1461 | static void adls_ddi_disable_clock(struct intel_encoder *encoder) |
1462 | { |
1463 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1464 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1465 | |
1466 | _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 3) * ((0x1642BC ) - (0x164280)))) }), |
1467 | ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24, 4, 5 })[phy]))); |
1468 | } |
1469 | |
1470 | static bool_Bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) |
1471 | { |
1472 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1473 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1474 | |
1475 | return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 3) * ((0x1642BC ) - (0x164280)))) }), |
1476 | ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24, 4, 5 })[phy]))); |
1477 | } |
1478 | |
1479 | static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder) |
1480 | { |
1481 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1482 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1483 | |
1484 | return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 3) * ((0x1642BC ) - (0x164280)))) }), |
1485 | ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy)(((const u32 []){ ((u32)((((~0UL) >> (64 - (1) - 1)) & ((~0UL) << (0))) + 0)), ((u32)((((~0UL) >> (64 - (3) - 1)) & ((~0UL) << (2))) + 0)), ((u32)((((~0UL ) >> (64 - (5) - 1)) & ((~0UL) << (4))) + 0)) , ((u32)((((~0UL) >> (64 - (1) - 1)) & ((~0UL) << (0))) + 0)), ((u32)((((~0UL) >> (64 - (3) - 1)) & ( (~0UL) << (2))) + 0)) })[(phy)]), |
1486 | ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy)(((phy) % 3) * 2)); |
1487 | } |
1488 | |
1489 | static void rkl_ddi_enable_clock(struct intel_encoder *encoder, |
1490 | const struct intel_crtc_state *crtc_state) |
1491 | { |
1492 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1493 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1494 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1495 | |
1496 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1497 | return; |
1498 | |
1499 | _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1500 | RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << (((const u32 []){ 0, 2, 4, 27 })[phy])), |
1501 | RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy)((pll->info->id) << (((const u32 []){ 0, 2, 4, 27 })[phy])), |
1502 | RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << ((phy) + 10)) + 0))); |
1503 | } |
1504 | |
1505 | static void rkl_ddi_disable_clock(struct intel_encoder *encoder) |
1506 | { |
1507 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1508 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1509 | |
1510 | _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1511 | RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << ((phy) + 10)) + 0))); |
1512 | } |
1513 | |
1514 | static bool_Bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) |
1515 | { |
1516 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1517 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1518 | |
1519 | return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1520 | RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << ((phy) + 10)) + 0))); |
1521 | } |
1522 | |
1523 | static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder) |
1524 | { |
1525 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1526 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1527 | |
1528 | return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1529 | RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << (((const u32 []){ 0, 2, 4, 27 })[phy])), |
1530 | RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)(((const u32 []){ 0, 2, 4, 27 })[phy])); |
1531 | } |
1532 | |
1533 | static void dg1_ddi_enable_clock(struct intel_encoder *encoder, |
1534 | const struct intel_crtc_state *crtc_state) |
1535 | { |
1536 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1537 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1538 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1539 | |
1540 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1541 | return; |
1542 | |
1543 | /* |
1544 | * If we fail this, something went very wrong: first 2 PLLs should be |
1545 | * used by first 2 phys and last 2 PLLs by last phys |
1546 | */ |
1547 | if (drm_WARN_ON(&i915->drm,({ int __ret = !!(((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)" ")"); __builtin_expect(!!(__ret), 0); }) |
1548 | (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||({ int __ret = !!(((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)" ")"); __builtin_expect(!!(__ret), 0); }) |
1549 | (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))({ int __ret = !!(((pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)" ")"); __builtin_expect(!!(__ret), 0); })) |
1550 | return; |
1551 | |
1552 | _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 2) * ((0x16C280 ) - (0x164280)))) }), |
1553 | DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(0x3 << (((phy) % 2) * 2)), |
1554 | DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy)(((pll->info->id) % 2) << (((phy) % 2) * 2)), |
1555 | DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << (((phy) % 2) + 10)) + 0))); |
1556 | } |
1557 | |
1558 | static void dg1_ddi_disable_clock(struct intel_encoder *encoder) |
1559 | { |
1560 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1561 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1562 | |
1563 | _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 2) * ((0x16C280 ) - (0x164280)))) }), |
1564 | DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << (((phy) % 2) + 10)) + 0))); |
1565 | } |
1566 | |
1567 | static bool_Bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) |
1568 | { |
1569 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1570 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1571 | |
1572 | return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 2) * ((0x16C280 ) - (0x164280)))) }), |
1573 | DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)((u32)((1UL << (((phy) % 2) + 10)) + 0))); |
1574 | } |
1575 | |
1576 | static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder) |
1577 | { |
1578 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1579 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1580 | enum intel_dpll_id id; |
1581 | u32 val; |
1582 | |
1583 | val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy)((const i915_reg_t){ .reg = (((0x164280) + ((phy) / 2) * ((0x16C280 ) - (0x164280)))) })); |
1584 | val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(0x3 << (((phy) % 2) * 2)); |
1585 | val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)(((phy) % 2) * 2); |
1586 | id = val; |
1587 | |
1588 | /* |
1589 | * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A |
1590 | * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one |
1591 | * bit for phy C and D. |
1592 | */ |
1593 | if (phy >= PHY_C) |
1594 | id += DPLL_ID_DG1_DPLL2; |
1595 | |
1596 | return intel_get_shared_dpll_by_id(i915, id); |
1597 | } |
1598 | |
1599 | static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, |
1600 | const struct intel_crtc_state *crtc_state) |
1601 | { |
1602 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1603 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1604 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1605 | |
1606 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1607 | return; |
1608 | |
1609 | _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1610 | ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << ((phy) * 2)), |
1611 | ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy)((pll->info->id) << ((phy) * 2)), |
1612 | ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24, 4, 5 })[phy]))); |
1613 | } |
1614 | |
1615 | static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder) |
1616 | { |
1617 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1618 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1619 | |
1620 | _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1621 | ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24, 4, 5 })[phy]))); |
1622 | } |
1623 | |
1624 | static bool_Bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) |
1625 | { |
1626 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1627 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1628 | |
1629 | return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1630 | ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)(1 << (((const u32 []){ 10, 11, 24, 4, 5 })[phy]))); |
1631 | } |
1632 | |
1633 | struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder) |
1634 | { |
1635 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1636 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
1637 | |
1638 | return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1639 | ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)(3 << ((phy) * 2)), |
1640 | ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)((phy) * 2)); |
1641 | } |
1642 | |
1643 | static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, |
1644 | const struct intel_crtc_state *crtc_state) |
1645 | { |
1646 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1647 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1648 | enum port port = encoder->port; |
1649 | |
1650 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1651 | return; |
1652 | |
1653 | /* |
1654 | * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port. |
1655 | * MG does not exist, but the programming is required to ungate DDIC and DDID." |
1656 | */ |
1657 | intel_de_write(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) }), DDI_CLK_SEL_MG((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 ))); |
1658 | |
1659 | icl_ddi_combo_enable_clock(encoder, crtc_state); |
1660 | } |
1661 | |
1662 | static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder) |
1663 | { |
1664 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1665 | enum port port = encoder->port; |
1666 | |
1667 | icl_ddi_combo_disable_clock(encoder); |
1668 | |
1669 | intel_de_write(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) }), DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 ))); |
1670 | } |
1671 | |
1672 | static bool_Bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) |
1673 | { |
1674 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1675 | enum port port = encoder->port; |
1676 | u32 tmp; |
1677 | |
1678 | tmp = intel_de_read(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })); |
1679 | |
1680 | if ((tmp & DDI_CLK_SEL_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) == DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 ))) |
1681 | return false0; |
1682 | |
1683 | return icl_ddi_combo_is_clock_enabled(encoder); |
1684 | } |
1685 | |
1686 | static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, |
1687 | const struct intel_crtc_state *crtc_state) |
1688 | { |
1689 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1690 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1691 | enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); |
1692 | enum port port = encoder->port; |
1693 | |
1694 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1695 | return; |
1696 | |
1697 | intel_de_write(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) }), |
1698 | icl_pll_to_ddi_clk_sel(encoder, crtc_state)); |
1699 | |
1700 | mutex_lock(&i915->display.dpll.lock)rw_enter_write(&i915->display.dpll.lock); |
1701 | |
1702 | intel_de_rmw(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1703 | ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)(1 << ((tc_port) < TC_PORT_4 ? (tc_port) + 12 : (tc_port ) - TC_PORT_4 + 21)), 0); |
1704 | |
1705 | mutex_unlock(&i915->display.dpll.lock)rw_exit_write(&i915->display.dpll.lock); |
1706 | } |
1707 | |
1708 | static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder) |
1709 | { |
1710 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1711 | enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); |
1712 | enum port port = encoder->port; |
1713 | |
1714 | mutex_lock(&i915->display.dpll.lock)rw_enter_write(&i915->display.dpll.lock); |
1715 | |
1716 | intel_de_rmw(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) }), |
1717 | 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)(1 << ((tc_port) < TC_PORT_4 ? (tc_port) + 12 : (tc_port ) - TC_PORT_4 + 21))); |
1718 | |
1719 | mutex_unlock(&i915->display.dpll.lock)rw_exit_write(&i915->display.dpll.lock); |
1720 | |
1721 | intel_de_write(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) }), DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 ))); |
1722 | } |
1723 | |
1724 | static bool_Bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) |
1725 | { |
1726 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1727 | enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); |
1728 | enum port port = encoder->port; |
1729 | u32 tmp; |
1730 | |
1731 | tmp = intel_de_read(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })); |
1732 | |
1733 | if ((tmp & DDI_CLK_SEL_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) == DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 ))) |
1734 | return false0; |
1735 | |
1736 | tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0((const i915_reg_t){ .reg = (0x164280) })); |
1737 | |
1738 | return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port)(1 << ((tc_port) < TC_PORT_4 ? (tc_port) + 12 : (tc_port ) - TC_PORT_4 + 21))); |
1739 | } |
1740 | |
1741 | static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder) |
1742 | { |
1743 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1744 | enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); |
1745 | enum port port = encoder->port; |
1746 | enum intel_dpll_id id; |
1747 | u32 tmp; |
1748 | |
1749 | tmp = intel_de_read(i915, DDI_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })); |
1750 | |
1751 | switch (tmp & DDI_CLK_SEL_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) { |
1752 | case DDI_CLK_SEL_TBT_162((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xC) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
1753 | case DDI_CLK_SEL_TBT_270((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xD) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
1754 | case DDI_CLK_SEL_TBT_540((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xE) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
1755 | case DDI_CLK_SEL_TBT_810((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0xF) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
1756 | id = DPLL_ID_ICL_TBTPLL; |
1757 | break; |
1758 | case DDI_CLK_SEL_MG((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x8) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
1759 | id = icl_tc_port_to_pll_id(tc_port); |
1760 | break; |
1761 | default: |
1762 | MISSING_CASE(tmp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "tmp", (long)(tmp)); __builtin_expect(!!(__ret), 0); }); |
1763 | fallthroughdo {} while (0); |
1764 | case DDI_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))))(0x0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (28))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (28))) + 0)))) + 0 + 0 + 0 + 0 )): |
1765 | return NULL((void *)0); |
1766 | } |
1767 | |
1768 | return intel_get_shared_dpll_by_id(i915, id); |
1769 | } |
1770 | |
1771 | static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder) |
1772 | { |
1773 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1774 | enum intel_dpll_id id; |
1775 | |
1776 | switch (encoder->port) { |
1777 | case PORT_A: |
1778 | id = DPLL_ID_SKL_DPLL0; |
1779 | break; |
1780 | case PORT_B: |
1781 | id = DPLL_ID_SKL_DPLL1; |
1782 | break; |
1783 | case PORT_C: |
1784 | id = DPLL_ID_SKL_DPLL2; |
1785 | break; |
1786 | default: |
1787 | MISSING_CASE(encoder->port)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "encoder->port", (long)(encoder->port)); __builtin_expect (!!(__ret), 0); }); |
1788 | return NULL((void *)0); |
1789 | } |
1790 | |
1791 | return intel_get_shared_dpll_by_id(i915, id); |
1792 | } |
1793 | |
1794 | static void skl_ddi_enable_clock(struct intel_encoder *encoder, |
1795 | const struct intel_crtc_state *crtc_state) |
1796 | { |
1797 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1798 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1799 | enum port port = encoder->port; |
1800 | |
1801 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1802 | return; |
1803 | |
1804 | mutex_lock(&i915->display.dpll.lock)rw_enter_write(&i915->display.dpll.lock); |
1805 | |
1806 | intel_de_rmw(i915, DPLL_CTRL2((const i915_reg_t){ .reg = (0x6C05C) }), |
1807 | DPLL_CTRL2_DDI_CLK_OFF(port)(1 << ((port) + 15)) | |
1808 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)(3 << ((port) * 3 + 1)), |
1809 | DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port)((pll->info->id) << ((port) * 3 + 1)) | |
1810 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)(1 << ((port) * 3))); |
1811 | |
1812 | mutex_unlock(&i915->display.dpll.lock)rw_exit_write(&i915->display.dpll.lock); |
1813 | } |
1814 | |
1815 | static void skl_ddi_disable_clock(struct intel_encoder *encoder) |
1816 | { |
1817 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1818 | enum port port = encoder->port; |
1819 | |
1820 | mutex_lock(&i915->display.dpll.lock)rw_enter_write(&i915->display.dpll.lock); |
1821 | |
1822 | intel_de_rmw(i915, DPLL_CTRL2((const i915_reg_t){ .reg = (0x6C05C) }), |
1823 | 0, DPLL_CTRL2_DDI_CLK_OFF(port)(1 << ((port) + 15))); |
1824 | |
1825 | mutex_unlock(&i915->display.dpll.lock)rw_exit_write(&i915->display.dpll.lock); |
1826 | } |
1827 | |
1828 | static bool_Bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) |
1829 | { |
1830 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1831 | enum port port = encoder->port; |
1832 | |
1833 | /* |
1834 | * FIXME Not sure if the override affects both |
1835 | * the PLL selection and the CLK_OFF bit. |
1836 | */ |
1837 | return !(intel_de_read(i915, DPLL_CTRL2((const i915_reg_t){ .reg = (0x6C05C) })) & DPLL_CTRL2_DDI_CLK_OFF(port)(1 << ((port) + 15))); |
1838 | } |
1839 | |
1840 | static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder) |
1841 | { |
1842 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1843 | enum port port = encoder->port; |
1844 | enum intel_dpll_id id; |
1845 | u32 tmp; |
1846 | |
1847 | tmp = intel_de_read(i915, DPLL_CTRL2((const i915_reg_t){ .reg = (0x6C05C) })); |
1848 | |
1849 | /* |
1850 | * FIXME Not sure if the override affects both |
1851 | * the PLL selection and the CLK_OFF bit. |
1852 | */ |
1853 | if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)(1 << ((port) * 3))) == 0) |
1854 | return NULL((void *)0); |
1855 | |
1856 | id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)(3 << ((port) * 3 + 1))) >> |
1857 | DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port)((port) * 3 + 1); |
1858 | |
1859 | return intel_get_shared_dpll_by_id(i915, id); |
1860 | } |
1861 | |
1862 | void hsw_ddi_enable_clock(struct intel_encoder *encoder, |
1863 | const struct intel_crtc_state *crtc_state) |
1864 | { |
1865 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1866 | const struct intel_shared_dpll *pll = crtc_state->shared_dpll; |
1867 | enum port port = encoder->port; |
1868 | |
1869 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
1870 | return; |
1871 | |
1872 | intel_de_write(i915, PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) }), hsw_pll_to_ddi_pll_sel(pll)); |
1873 | } |
1874 | |
1875 | void hsw_ddi_disable_clock(struct intel_encoder *encoder) |
1876 | { |
1877 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1878 | enum port port = encoder->port; |
1879 | |
1880 | intel_de_write(i915, PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) }), PORT_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(7) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 ))); |
1881 | } |
1882 | |
1883 | bool_Bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) |
1884 | { |
1885 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1886 | enum port port = encoder->port; |
1887 | |
1888 | return intel_de_read(i915, PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })) != PORT_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(7) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )); |
1889 | } |
1890 | |
1891 | static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder) |
1892 | { |
1893 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1894 | enum port port = encoder->port; |
1895 | enum intel_dpll_id id; |
1896 | u32 tmp; |
1897 | |
1898 | tmp = intel_de_read(i915, PORT_CLK_SEL(port)((const i915_reg_t){ .reg = (((0x46100) + (port) * ((0x46104) - (0x46100)))) })); |
1899 | |
1900 | switch (tmp & PORT_CLK_SEL_MASK((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) { |
1901 | case PORT_CLK_SEL_WRPLL1((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(4) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1902 | id = DPLL_ID_WRPLL1; |
1903 | break; |
1904 | case PORT_CLK_SEL_WRPLL2((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(5) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1905 | id = DPLL_ID_WRPLL2; |
1906 | break; |
1907 | case PORT_CLK_SEL_SPLL((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(3) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1908 | id = DPLL_ID_SPLL; |
1909 | break; |
1910 | case PORT_CLK_SEL_LCPLL_810((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(2) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1911 | id = DPLL_ID_LCPLL_810; |
1912 | break; |
1913 | case PORT_CLK_SEL_LCPLL_1350((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1914 | id = DPLL_ID_LCPLL_1350; |
1915 | break; |
1916 | case PORT_CLK_SEL_LCPLL_2700((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1917 | id = DPLL_ID_LCPLL_2700; |
1918 | break; |
1919 | default: |
1920 | MISSING_CASE(tmp)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "tmp", (long)(tmp)); __builtin_expect(!!(__ret), 0); }); |
1921 | fallthroughdo {} while (0); |
1922 | case PORT_CLK_SEL_NONE((u32)((((typeof(((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))))(7) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (31) - 1)) & ((~0UL) << (29))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (31 ) - 1)) & ((~0UL) << (29))) + 0)))) + 0 + 0 + 0 + 0 )): |
1923 | return NULL((void *)0); |
1924 | } |
1925 | |
1926 | return intel_get_shared_dpll_by_id(i915, id); |
1927 | } |
1928 | |
1929 | void intel_ddi_enable_clock(struct intel_encoder *encoder, |
1930 | const struct intel_crtc_state *crtc_state) |
1931 | { |
1932 | if (encoder->enable_clock) |
1933 | encoder->enable_clock(encoder, crtc_state); |
1934 | } |
1935 | |
1936 | void intel_ddi_disable_clock(struct intel_encoder *encoder) |
1937 | { |
1938 | if (encoder->disable_clock) |
1939 | encoder->disable_clock(encoder); |
1940 | } |
1941 | |
1942 | void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) |
1943 | { |
1944 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
1945 | u32 port_mask; |
1946 | bool_Bool ddi_clk_needed; |
1947 | |
1948 | /* |
1949 | * In case of DP MST, we sanitize the primary encoder only, not the |
1950 | * virtual ones. |
1951 | */ |
1952 | if (encoder->type == INTEL_OUTPUT_DP_MST) |
1953 | return; |
1954 | |
1955 | if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { |
1956 | u8 pipe_mask; |
1957 | bool_Bool is_mst; |
1958 | |
1959 | intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst); |
1960 | /* |
1961 | * In the unlikely case that BIOS enables DP in MST mode, just |
1962 | * warn since our MST HW readout is incomplete. |
1963 | */ |
1964 | if (drm_WARN_ON(&i915->drm, is_mst)({ int __ret = !!((is_mst)); if (__ret) printf("%s %s: " "%s" , dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "is_mst" ")"); __builtin_expect(!!(__ret), 0); })) |
1965 | return; |
1966 | } |
1967 | |
1968 | port_mask = BIT(encoder->port)(1UL << (encoder->port)); |
1969 | ddi_clk_needed = encoder->base.crtc; |
1970 | |
1971 | if (encoder->type == INTEL_OUTPUT_DSI) { |
1972 | struct intel_encoder *other_encoder; |
1973 | |
1974 | port_mask = intel_dsi_encoder_ports(encoder); |
1975 | /* |
1976 | * Sanity check that we haven't incorrectly registered another |
1977 | * encoder using any of the ports of this DSI encoder. |
1978 | */ |
1979 | for_each_intel_encoder(&i915->drm, other_encoder)for (other_encoder = ({ const __typeof( ((__typeof(*other_encoder ) *)0)->base.head ) *__mptr = ((&(&i915->drm)-> mode_config.encoder_list)->next); (__typeof(*other_encoder ) *)( (char *)__mptr - __builtin_offsetof(__typeof(*other_encoder ), base.head) );}); &other_encoder->base.head != (& (&i915->drm)->mode_config.encoder_list); other_encoder = ({ const __typeof( ((__typeof(*other_encoder) *)0)->base .head ) *__mptr = (other_encoder->base.head.next); (__typeof (*other_encoder) *)( (char *)__mptr - __builtin_offsetof(__typeof (*other_encoder), base.head) );})) { |
1980 | if (other_encoder == encoder) |
1981 | continue; |
1982 | |
1983 | if (drm_WARN_ON(&i915->drm,({ int __ret = !!((port_mask & (1UL << (other_encoder ->port)))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "port_mask & (1UL << (other_encoder->port))" ")"); __builtin_expect(!!(__ret), 0); }) |
1984 | port_mask & BIT(other_encoder->port))({ int __ret = !!((port_mask & (1UL << (other_encoder ->port)))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "port_mask & (1UL << (other_encoder->port))" ")"); __builtin_expect(!!(__ret), 0); })) |
1985 | return; |
1986 | } |
1987 | /* |
1988 | * For DSI we keep the ddi clocks gated |
1989 | * except during enable/disable sequence. |
1990 | */ |
1991 | ddi_clk_needed = false0; |
1992 | } |
1993 | |
1994 | if (ddi_clk_needed || !encoder->is_clock_enabled || |
1995 | !encoder->is_clock_enabled(encoder)) |
1996 | return; |
1997 | |
1998 | drm_notice(&i915->drm,printf("drm:pid%d:%s *NOTICE* " "[drm] " "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , encoder ->base.base.id, encoder->base.name) |
1999 | "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",printf("drm:pid%d:%s *NOTICE* " "[drm] " "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , encoder ->base.base.id, encoder->base.name) |
2000 | encoder->base.base.id, encoder->base.name)printf("drm:pid%d:%s *NOTICE* " "[drm] " "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , encoder ->base.base.id, encoder->base.name); |
2001 | |
2002 | encoder->disable_clock(encoder); |
2003 | } |
2004 | |
2005 | static void |
2006 | icl_program_mg_dp_mode(struct intel_digital_port *dig_port, |
2007 | const struct intel_crtc_state *crtc_state) |
2008 | { |
2009 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
2010 | enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port); |
2011 | enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); |
2012 | u32 ln0, ln1, pin_assignment; |
2013 | u8 width; |
2014 | |
2015 | if (!intel_phy_is_tc(dev_priv, phy) || |
2016 | intel_tc_port_in_tbt_alt_mode(dig_port)) |
2017 | return; |
2018 | |
2019 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
2020 | ln0 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0xA0) }), 0); |
2021 | ln1 = intel_dkl_phy_read(dev_priv, DKL_DP_MODE(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0xA0) }), 1); |
2022 | } else { |
2023 | ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port)((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0 ) - (0x1683A0))) + (0) * ((0x1687A0) - (0x1683A0))) })); |
2024 | ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port)((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0 ) - (0x1683A0))) + (1) * ((0x1687A0) - (0x1683A0))) })); |
2025 | } |
2026 | |
2027 | ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE(1 << 6) | MG_DP_MODE_CFG_DP_X2_MODE(1 << 7)); |
2028 | ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE(1 << 6) | MG_DP_MODE_CFG_DP_X2_MODE(1 << 7)); |
2029 | |
2030 | /* DPPATC */ |
2031 | pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port); |
2032 | width = crtc_state->lane_count; |
2033 | |
2034 | switch (pin_assignment) { |
2035 | case 0x0: |
2036 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((!intel_tc_port_in_legacy_mode(dig_port))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "!intel_tc_port_in_legacy_mode(dig_port)" ")"); __builtin_expect(!!(__ret), 0); }) |
2037 | !intel_tc_port_in_legacy_mode(dig_port))({ int __ret = !!((!intel_tc_port_in_legacy_mode(dig_port))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "!intel_tc_port_in_legacy_mode(dig_port)" ")"); __builtin_expect(!!(__ret), 0); }); |
2038 | if (width == 1) { |
2039 | ln1 |= MG_DP_MODE_CFG_DP_X1_MODE(1 << 6); |
2040 | } else { |
2041 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2042 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2043 | } |
2044 | break; |
2045 | case 0x1: |
2046 | if (width == 4) { |
2047 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2048 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2049 | } |
2050 | break; |
2051 | case 0x2: |
2052 | if (width == 2) { |
2053 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2054 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2055 | } |
2056 | break; |
2057 | case 0x3: |
2058 | case 0x5: |
2059 | if (width == 1) { |
2060 | ln0 |= MG_DP_MODE_CFG_DP_X1_MODE(1 << 6); |
2061 | ln1 |= MG_DP_MODE_CFG_DP_X1_MODE(1 << 6); |
2062 | } else { |
2063 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2064 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2065 | } |
2066 | break; |
2067 | case 0x4: |
2068 | case 0x6: |
2069 | if (width == 1) { |
2070 | ln0 |= MG_DP_MODE_CFG_DP_X1_MODE(1 << 6); |
2071 | ln1 |= MG_DP_MODE_CFG_DP_X1_MODE(1 << 6); |
2072 | } else { |
2073 | ln0 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2074 | ln1 |= MG_DP_MODE_CFG_DP_X2_MODE(1 << 7); |
2075 | } |
2076 | break; |
2077 | default: |
2078 | MISSING_CASE(pin_assignment)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "pin_assignment", (long)(pin_assignment)); __builtin_expect (!!(__ret), 0); }); |
2079 | } |
2080 | |
2081 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
2082 | intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0xA0) }), 0, ln0); |
2083 | intel_dkl_phy_write(dev_priv, DKL_DP_MODE(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0xA0) }), 1, ln1); |
2084 | } else { |
2085 | intel_de_write(dev_priv, MG_DP_MODE(0, tc_port)((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0 ) - (0x1683A0))) + (0) * ((0x1687A0) - (0x1683A0))) }), ln0); |
2086 | intel_de_write(dev_priv, MG_DP_MODE(1, tc_port)((const i915_reg_t){ .reg = (((0x1683A0) + (tc_port) * ((0x1693A0 ) - (0x1683A0))) + (1) * ((0x1687A0) - (0x1683A0))) }), ln1); |
2087 | } |
2088 | } |
2089 | |
2090 | static enum transcoder |
2091 | tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state) |
2092 | { |
2093 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) |
2094 | return crtc_state->mst_master_transcoder; |
2095 | else |
2096 | return crtc_state->cpu_transcoder; |
2097 | } |
2098 | |
2099 | i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, |
2100 | const struct intel_crtc_state *crtc_state) |
2101 | { |
2102 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2103 | |
2104 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
2105 | return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state))((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[((tgl_dp_tp_transcoder(crtc_state)))] - (&(dev_priv)->__info)->display.trans_offsets[TRANSCODER_A ] + ((&(dev_priv)->__info)->display.mmio_offset) + ( 0x60540)) }); |
2106 | else |
2107 | return DP_TP_CTL(encoder->port)((const i915_reg_t){ .reg = (((0x64040) + (encoder->port) * ((0x64140) - (0x64040)))) }); |
2108 | } |
2109 | |
2110 | i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, |
2111 | const struct intel_crtc_state *crtc_state) |
2112 | { |
2113 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2114 | |
2115 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
2116 | return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state))((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[((tgl_dp_tp_transcoder(crtc_state)))] - (&(dev_priv)->__info)->display.trans_offsets[TRANSCODER_A ] + ((&(dev_priv)->__info)->display.mmio_offset) + ( 0x60544)) }); |
2117 | else |
2118 | return DP_TP_STATUS(encoder->port)((const i915_reg_t){ .reg = (((0x64044) + (encoder->port) * ((0x64144) - (0x64044)))) }); |
2119 | } |
2120 | |
2121 | static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp, |
2122 | const struct intel_crtc_state *crtc_state, |
2123 | bool_Bool enable) |
2124 | { |
2125 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
2126 | |
2127 | if (!crtc_state->vrr.enable) |
2128 | return; |
2129 | |
2130 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL0x107, |
2131 | enable ? DP_MSA_TIMING_PAR_IGNORE_EN(1 << 7) : 0) <= 0) |
2132 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n" , str_enable_disable(enable)) |
2133 | "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n" , str_enable_disable(enable)) |
2134 | str_enable_disable(enable))__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n" , str_enable_disable(enable)); |
2135 | } |
2136 | |
2137 | static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp, |
2138 | const struct intel_crtc_state *crtc_state) |
2139 | { |
2140 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
2141 | |
2142 | if (!crtc_state->fec_enable) |
2143 | return; |
2144 | |
2145 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION0x120, DP_FEC_READY(1 << 0)) <= 0) |
2146 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Failed to set FEC_READY in the sink\n" ) |
2147 | "Failed to set FEC_READY in the sink\n")__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "Failed to set FEC_READY in the sink\n" ); |
2148 | } |
2149 | |
2150 | static void intel_ddi_enable_fec(struct intel_encoder *encoder, |
2151 | const struct intel_crtc_state *crtc_state) |
2152 | { |
2153 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2154 | struct intel_dp *intel_dp; |
2155 | u32 val; |
2156 | |
2157 | if (!crtc_state->fec_enable) |
2158 | return; |
2159 | |
2160 | intel_dp = enc_to_intel_dp(encoder); |
Value stored to 'intel_dp' is never read | |
2161 | val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
2162 | val |= DP_TP_CTL_FEC_ENABLE(1 << 30); |
2163 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); |
2164 | } |
2165 | |
2166 | static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, |
2167 | const struct intel_crtc_state *crtc_state) |
2168 | { |
2169 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2170 | struct intel_dp *intel_dp; |
2171 | u32 val; |
2172 | |
2173 | if (!crtc_state->fec_enable) |
2174 | return; |
2175 | |
2176 | intel_dp = enc_to_intel_dp(encoder); |
2177 | val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
2178 | val &= ~DP_TP_CTL_FEC_ENABLE(1 << 30); |
2179 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); |
2180 | intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
2181 | } |
2182 | |
2183 | static void intel_ddi_power_up_lanes(struct intel_encoder *encoder, |
2184 | const struct intel_crtc_state *crtc_state) |
2185 | { |
2186 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
2187 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2188 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
2189 | |
2190 | if (intel_phy_is_combo(i915, phy)) { |
2191 | bool_Bool lane_reversal = |
2192 | dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL(1 << 16); |
2193 | |
2194 | intel_combo_phy_power_up_lanes(i915, phy, false0, |
2195 | crtc_state->lane_count, |
2196 | lane_reversal); |
2197 | } |
2198 | } |
2199 | |
2200 | /* Splitter enable for eDP MSO is limited to certain pipes. */ |
2201 | static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_privateinteldrm_softc *i915) |
2202 | { |
2203 | if (IS_ALDERLAKE_P(i915)IS_PLATFORM(i915, INTEL_ALDERLAKE_P)) |
2204 | return BIT(PIPE_A)(1UL << (PIPE_A)) | BIT(PIPE_B)(1UL << (PIPE_B)); |
2205 | else |
2206 | return BIT(PIPE_A)(1UL << (PIPE_A)); |
2207 | } |
2208 | |
2209 | static void intel_ddi_mso_get_config(struct intel_encoder *encoder, |
2210 | struct intel_crtc_state *pipe_config) |
2211 | { |
2212 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
2213 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev); |
2214 | enum pipe pipe = crtc->pipe; |
2215 | u32 dss1; |
2216 | |
2217 | if (!HAS_MSO(i915)(((&(i915)->__runtime)->display.ip.ver) >= 12)) |
2218 | return; |
2219 | |
2220 | dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe)((const i915_reg_t){ .reg = (((0x78200) + ((pipe) - PIPE_B) * ((0x78400) - (0x78200)))) })); |
2221 | |
2222 | pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE(1 << 31); |
2223 | if (!pipe_config->splitter.enable) |
2224 | return; |
2225 | |
2226 | if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))({ int __ret = !!((!(intel_ddi_splitter_pipe_mask(i915) & (1UL << (pipe))))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!(intel_ddi_splitter_pipe_mask(i915) & (1UL << (pipe)))" ")"); __builtin_expect(!!(__ret), 0); })) { |
2227 | pipe_config->splitter.enable = false0; |
2228 | return; |
2229 | } |
2230 | |
2231 | switch (dss1 & SPLITTER_CONFIGURATION_MASK((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))) { |
2232 | default: |
2233 | drm_WARN(&i915->drm, true,({ int __ret = !!(1); if (__ret) printf("%s %s: " "Invalid splitter configuration, dss1=0x%08x\n" , dev_driver_string((&i915->drm)->dev), "", dss1); __builtin_expect (!!(__ret), 0); }) |
2234 | "Invalid splitter configuration, dss1=0x%08x\n", dss1)({ int __ret = !!(1); if (__ret) printf("%s %s: " "Invalid splitter configuration, dss1=0x%08x\n" , dev_driver_string((&i915->drm)->dev), "", dss1); __builtin_expect (!!(__ret), 0); }); |
2235 | fallthroughdo {} while (0); |
2236 | case SPLITTER_CONFIGURATION_2_SEGMENT((u32)((((typeof(((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (26 ) - 1)) & ((~0UL) << (25))) + 0)))) + 0 + 0 + 0 + 0 )): |
2237 | pipe_config->splitter.link_count = 2; |
2238 | break; |
2239 | case SPLITTER_CONFIGURATION_4_SEGMENT((u32)((((typeof(((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (26 ) - 1)) & ((~0UL) << (25))) + 0)))) + 0 + 0 + 0 + 0 )): |
2240 | pipe_config->splitter.link_count = 4; |
2241 | break; |
2242 | } |
2243 | |
2244 | pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1)((u32)((typeof((0xf << 16)))(((dss1) & ((0xf << 16))) >> (__builtin_ffsll((0xf << 16)) - 1)))); |
2245 | } |
2246 | |
2247 | static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state) |
2248 | { |
2249 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
2250 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev); |
2251 | enum pipe pipe = crtc->pipe; |
2252 | u32 dss1 = 0; |
2253 | |
2254 | if (!HAS_MSO(i915)(((&(i915)->__runtime)->display.ip.ver) >= 12)) |
2255 | return; |
2256 | |
2257 | if (crtc_state->splitter.enable) { |
2258 | dss1 |= SPLITTER_ENABLE(1 << 31); |
2259 | dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap)((crtc_state->splitter.pixel_overlap) << 16); |
2260 | if (crtc_state->splitter.link_count == 2) |
2261 | dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT((u32)((((typeof(((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))))(0) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (26 ) - 1)) & ((~0UL) << (25))) + 0)))) + 0 + 0 + 0 + 0 )); |
2262 | else |
2263 | dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT((u32)((((typeof(((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))))(1) << (__builtin_ffsll (((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0))) - 1)) & (((u32)((((~0UL) >> (64 - (26 ) - 1)) & ((~0UL) << (25))) + 0)))) + 0 + 0 + 0 + 0 )); |
2264 | } |
2265 | |
2266 | intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe)((const i915_reg_t){ .reg = (((0x78200) + ((pipe) - PIPE_B) * ((0x78400) - (0x78200)))) }), |
2267 | SPLITTER_ENABLE(1 << 31) | SPLITTER_CONFIGURATION_MASK((u32)((((~0UL) >> (64 - (26) - 1)) & ((~0UL) << (25))) + 0)) | |
2268 | OVERLAP_PIXELS_MASK(0xf << 16), dss1); |
2269 | } |
2270 | |
2271 | static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, |
2272 | struct intel_encoder *encoder, |
2273 | const struct intel_crtc_state *crtc_state, |
2274 | const struct drm_connector_state *conn_state) |
2275 | { |
2276 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2277 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2278 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2279 | bool_Bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); |
2280 | |
2281 | intel_dp_set_link_params(intel_dp, |
2282 | crtc_state->port_clock, |
2283 | crtc_state->lane_count); |
2284 | |
2285 | /* |
2286 | * We only configure what the register value will be here. Actual |
2287 | * enabling happens during link training farther down. |
2288 | */ |
2289 | intel_ddi_init_dp_buf_reg(encoder, crtc_state); |
2290 | |
2291 | /* |
2292 | * 1. Enable Power Wells |
2293 | * |
2294 | * This was handled at the beginning of intel_atomic_commit_tail(), |
2295 | * before we called down into this function. |
2296 | */ |
2297 | |
2298 | /* 2. Enable Panel Power if PPS is required */ |
2299 | intel_pps_on(intel_dp); |
2300 | |
2301 | /* |
2302 | * 3. For non-TBT Type-C ports, set FIA lane count |
2303 | * (DFLEXDPSP.DPX4TXLATC) |
2304 | * |
2305 | * This was done before tgl_ddi_pre_enable_dp by |
2306 | * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). |
2307 | */ |
2308 | |
2309 | /* |
2310 | * 4. Enable the port PLL. |
2311 | * |
2312 | * The PLL enabling itself was already done before this function by |
2313 | * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only |
2314 | * configure the PLL to port mapping here. |
2315 | */ |
2316 | intel_ddi_enable_clock(encoder, crtc_state); |
2317 | |
2318 | /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */ |
2319 | if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { |
2320 | drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref)({ int __ret = !!((dig_port->ddi_io_wakeref)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "dig_port->ddi_io_wakeref" ")"); __builtin_expect (!!(__ret), 0); }); |
2321 | dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, |
2322 | dig_port->ddi_io_power_domain); |
2323 | } |
2324 | |
2325 | /* 6. Program DP_MODE */ |
2326 | icl_program_mg_dp_mode(dig_port, crtc_state); |
2327 | |
2328 | /* |
2329 | * 7. The rest of the below are substeps under the bspec's "Enable and |
2330 | * Train Display Port" step. Note that steps that are specific to |
2331 | * MST will be handled by intel_mst_pre_enable_dp() before/after it |
2332 | * calls into this function. Also intel_mst_pre_enable_dp() only calls |
2333 | * us when active_mst_links==0, so any steps designated for "single |
2334 | * stream or multi-stream master transcoder" can just be performed |
2335 | * unconditionally here. |
2336 | */ |
2337 | |
2338 | /* |
2339 | * 7.a Configure Transcoder Clock Select to direct the Port clock to the |
2340 | * Transcoder. |
2341 | */ |
2342 | intel_ddi_enable_pipe_clock(encoder, crtc_state); |
2343 | |
2344 | if (HAS_DP20(dev_priv)(IS_PLATFORM(dev_priv, INTEL_DG2) || ((&(dev_priv)->__runtime )->display.ip.ver) >= 14)) |
2345 | intel_ddi_config_transcoder_dp2(encoder, crtc_state); |
2346 | |
2347 | /* |
2348 | * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST |
2349 | * Transport Select |
2350 | */ |
2351 | intel_ddi_config_transcoder_func(encoder, crtc_state); |
2352 | |
2353 | /* |
2354 | * 7.c Configure & enable DP_TP_CTL with link training pattern 1 |
2355 | * selected |
2356 | * |
2357 | * This will be handled by the intel_dp_start_link_train() farther |
2358 | * down this function. |
2359 | */ |
2360 | |
2361 | /* 7.e Configure voltage swing and related IO settings */ |
2362 | encoder->set_signal_levels(encoder, crtc_state); |
2363 | |
2364 | /* |
2365 | * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up |
2366 | * the used lanes of the DDI. |
2367 | */ |
2368 | intel_ddi_power_up_lanes(encoder, crtc_state); |
2369 | |
2370 | /* |
2371 | * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected. |
2372 | */ |
2373 | intel_ddi_mso_configure(crtc_state); |
2374 | |
2375 | if (!is_mst) |
2376 | intel_dp_set_power(intel_dp, DP_SET_POWER_D00x1); |
2377 | |
2378 | intel_dp_configure_protocol_converter(intel_dp, crtc_state); |
2379 | intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true1); |
2380 | /* |
2381 | * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit |
2382 | * in the FEC_CONFIGURATION register to 1 before initiating link |
2383 | * training |
2384 | */ |
2385 | intel_dp_sink_set_fec_ready(intel_dp, crtc_state); |
2386 | |
2387 | intel_dp_check_frl_training(intel_dp); |
2388 | intel_dp_pcon_dsc_configure(intel_dp, crtc_state); |
2389 | |
2390 | /* |
2391 | * 7.i Follow DisplayPort specification training sequence (see notes for |
2392 | * failure handling) |
2393 | * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle |
2394 | * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) |
2395 | * (timeout after 800 us) |
2396 | */ |
2397 | intel_dp_start_link_train(intel_dp, crtc_state); |
2398 | |
2399 | /* 7.k Set DP_TP_CTL link training to Normal */ |
2400 | if (!is_trans_port_sync_mode(crtc_state)) |
2401 | intel_dp_stop_link_train(intel_dp, crtc_state); |
2402 | |
2403 | /* 7.l Configure and enable FEC if needed */ |
2404 | intel_ddi_enable_fec(encoder, crtc_state); |
2405 | |
2406 | intel_dsc_dp_pps_write(encoder, crtc_state); |
2407 | } |
2408 | |
2409 | static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, |
2410 | struct intel_encoder *encoder, |
2411 | const struct intel_crtc_state *crtc_state, |
2412 | const struct drm_connector_state *conn_state) |
2413 | { |
2414 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2415 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2416 | enum port port = encoder->port; |
2417 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2418 | bool_Bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST); |
2419 | |
2420 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 11) |
2421 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((is_mst && (port == PORT_A || port == PORT_E))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "is_mst && (port == PORT_A || port == PORT_E)" ")"); __builtin_expect(!!(__ret), 0); }) |
2422 | is_mst && (port == PORT_A || port == PORT_E))({ int __ret = !!((is_mst && (port == PORT_A || port == PORT_E))); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "is_mst && (port == PORT_A || port == PORT_E)" ")"); __builtin_expect(!!(__ret), 0); }); |
2423 | else |
2424 | drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A)({ int __ret = !!((is_mst && port == PORT_A)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "is_mst && port == PORT_A" ")"); __builtin_expect(!!(__ret), 0); }); |
2425 | |
2426 | intel_dp_set_link_params(intel_dp, |
2427 | crtc_state->port_clock, |
2428 | crtc_state->lane_count); |
2429 | |
2430 | /* |
2431 | * We only configure what the register value will be here. Actual |
2432 | * enabling happens during link training farther down. |
2433 | */ |
2434 | intel_ddi_init_dp_buf_reg(encoder, crtc_state); |
2435 | |
2436 | intel_pps_on(intel_dp); |
2437 | |
2438 | intel_ddi_enable_clock(encoder, crtc_state); |
2439 | |
2440 | if (!intel_tc_port_in_tbt_alt_mode(dig_port)) { |
2441 | drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref)({ int __ret = !!((dig_port->ddi_io_wakeref)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "dig_port->ddi_io_wakeref" ")"); __builtin_expect (!!(__ret), 0); }); |
2442 | dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, |
2443 | dig_port->ddi_io_power_domain); |
2444 | } |
2445 | |
2446 | icl_program_mg_dp_mode(dig_port, crtc_state); |
2447 | |
2448 | if (has_buf_trans_select(dev_priv)) |
2449 | hsw_prepare_dp_ddi_buffers(encoder, crtc_state); |
2450 | |
2451 | encoder->set_signal_levels(encoder, crtc_state); |
2452 | |
2453 | intel_ddi_power_up_lanes(encoder, crtc_state); |
2454 | |
2455 | if (!is_mst) |
2456 | intel_dp_set_power(intel_dp, DP_SET_POWER_D00x1); |
2457 | intel_dp_configure_protocol_converter(intel_dp, crtc_state); |
2458 | intel_dp_sink_set_decompression_state(intel_dp, crtc_state, |
2459 | true1); |
2460 | intel_dp_sink_set_fec_ready(intel_dp, crtc_state); |
2461 | intel_dp_start_link_train(intel_dp, crtc_state); |
2462 | if ((port != PORT_A || DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 9) && |
2463 | !is_trans_port_sync_mode(crtc_state)) |
2464 | intel_dp_stop_link_train(intel_dp, crtc_state); |
2465 | |
2466 | intel_ddi_enable_fec(encoder, crtc_state); |
2467 | |
2468 | if (!is_mst) |
2469 | intel_ddi_enable_pipe_clock(encoder, crtc_state); |
2470 | |
2471 | intel_dsc_dp_pps_write(encoder, crtc_state); |
2472 | } |
2473 | |
2474 | static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, |
2475 | struct intel_encoder *encoder, |
2476 | const struct intel_crtc_state *crtc_state, |
2477 | const struct drm_connector_state *conn_state) |
2478 | { |
2479 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2480 | |
2481 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
2482 | tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); |
2483 | else |
2484 | hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state); |
2485 | |
2486 | /* MST will call a setting of MSA after an allocating of Virtual Channel |
2487 | * from MST encoder pre_enable callback. |
2488 | */ |
2489 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) |
2490 | intel_ddi_set_dp_msa(crtc_state, conn_state); |
2491 | } |
2492 | |
2493 | static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state, |
2494 | struct intel_encoder *encoder, |
2495 | const struct intel_crtc_state *crtc_state, |
2496 | const struct drm_connector_state *conn_state) |
2497 | { |
2498 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2499 | struct intel_hdmi *intel_hdmi = &dig_port->hdmi; |
2500 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2501 | |
2502 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true1); |
2503 | intel_ddi_enable_clock(encoder, crtc_state); |
2504 | |
2505 | drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref)({ int __ret = !!((dig_port->ddi_io_wakeref)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "dig_port->ddi_io_wakeref" ")"); __builtin_expect (!!(__ret), 0); }); |
2506 | dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, |
2507 | dig_port->ddi_io_power_domain); |
2508 | |
2509 | icl_program_mg_dp_mode(dig_port, crtc_state); |
2510 | |
2511 | intel_ddi_enable_pipe_clock(encoder, crtc_state); |
2512 | |
2513 | dig_port->set_infoframes(encoder, |
2514 | crtc_state->has_infoframe, |
2515 | crtc_state, conn_state); |
2516 | } |
2517 | |
2518 | static void intel_ddi_pre_enable(struct intel_atomic_state *state, |
2519 | struct intel_encoder *encoder, |
2520 | const struct intel_crtc_state *crtc_state, |
2521 | const struct drm_connector_state *conn_state) |
2522 | { |
2523 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (crtc_state->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
2524 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev); |
2525 | enum pipe pipe = crtc->pipe; |
2526 | |
2527 | /* |
2528 | * When called from DP MST code: |
2529 | * - conn_state will be NULL |
2530 | * - encoder will be the main encoder (ie. mst->primary) |
2531 | * - the main connector associated with this port |
2532 | * won't be active or linked to a crtc |
2533 | * - crtc_state will be the state of the first stream to |
2534 | * be activated on this port, and it may not be the same |
2535 | * stream that will be deactivated last, but each stream |
2536 | * should have a state that is identical when it comes to |
2537 | * the DP link parameteres |
2538 | */ |
2539 | |
2540 | drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder)({ int __ret = !!((crtc_state->has_pch_encoder)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "crtc_state->has_pch_encoder" ")"); __builtin_expect(!!(__ret), 0); }); |
2541 | |
2542 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true1); |
2543 | |
2544 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { |
2545 | intel_ddi_pre_enable_hdmi(state, encoder, crtc_state, |
2546 | conn_state); |
2547 | } else { |
2548 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2549 | |
2550 | intel_ddi_pre_enable_dp(state, encoder, crtc_state, |
2551 | conn_state); |
2552 | |
2553 | /* FIXME precompute everything properly */ |
2554 | /* FIXME how do we turn infoframes off again? */ |
2555 | if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) |
2556 | dig_port->set_infoframes(encoder, |
2557 | crtc_state->has_infoframe, |
2558 | crtc_state, conn_state); |
2559 | } |
2560 | } |
2561 | |
2562 | static void intel_disable_ddi_buf(struct intel_encoder *encoder, |
2563 | const struct intel_crtc_state *crtc_state) |
2564 | { |
2565 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2566 | enum port port = encoder->port; |
2567 | bool_Bool wait = false0; |
2568 | u32 val; |
2569 | |
2570 | val = intel_de_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })); |
2571 | if (val & DDI_BUF_CTL_ENABLE(1 << 31)) { |
2572 | val &= ~DDI_BUF_CTL_ENABLE(1 << 31); |
2573 | intel_de_write(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }), val); |
2574 | wait = true1; |
2575 | } |
2576 | |
2577 | if (intel_crtc_has_dp_encoder(crtc_state)) { |
2578 | val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
2579 | val &= ~(DP_TP_CTL_ENABLE(1 << 31) | DP_TP_CTL_LINK_TRAIN_MASK(7 << 8)); |
2580 | val |= DP_TP_CTL_LINK_TRAIN_PAT1(0 << 8); |
2581 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); |
2582 | } |
2583 | |
2584 | /* Disable FEC in DP Sink */ |
2585 | intel_ddi_disable_fec_state(encoder, crtc_state); |
2586 | |
2587 | if (wait) |
2588 | intel_wait_ddi_buf_idle(dev_priv, port); |
2589 | } |
2590 | |
2591 | static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, |
2592 | struct intel_encoder *encoder, |
2593 | const struct intel_crtc_state *old_crtc_state, |
2594 | const struct drm_connector_state *old_conn_state) |
2595 | { |
2596 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2597 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2598 | struct intel_dp *intel_dp = &dig_port->dp; |
2599 | bool_Bool is_mst = intel_crtc_has_type(old_crtc_state, |
2600 | INTEL_OUTPUT_DP_MST); |
2601 | |
2602 | if (!is_mst) |
2603 | intel_dp_set_infoframes(encoder, false0, |
2604 | old_crtc_state, old_conn_state); |
2605 | |
2606 | /* |
2607 | * Power down sink before disabling the port, otherwise we end |
2608 | * up getting interrupts from the sink on detecting link loss. |
2609 | */ |
2610 | intel_dp_set_power(intel_dp, DP_SET_POWER_D30x2); |
2611 | |
2612 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
2613 | if (is_mst) { |
2614 | enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; |
2615 | u32 val; |
2616 | |
2617 | val = intel_de_read(dev_priv, |
2618 | TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
2619 | val &= ~(TGL_TRANS_DDI_PORT_MASK(0xf << 27) | |
2620 | TRANS_DDI_MODE_SELECT_MASK(7 << 24)); |
2621 | intel_de_write(dev_priv, |
2622 | TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) }), |
2623 | val); |
2624 | } |
2625 | } else { |
2626 | if (!is_mst) |
2627 | intel_ddi_disable_pipe_clock(old_crtc_state); |
2628 | } |
2629 | |
2630 | intel_disable_ddi_buf(encoder, old_crtc_state); |
2631 | |
2632 | /* |
2633 | * From TGL spec: "If single stream or multi-stream master transcoder: |
2634 | * Configure Transcoder Clock select to direct no clock to the |
2635 | * transcoder" |
2636 | */ |
2637 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
2638 | intel_ddi_disable_pipe_clock(old_crtc_state); |
2639 | |
2640 | intel_pps_vdd_on(intel_dp); |
2641 | intel_pps_off(intel_dp); |
2642 | |
2643 | if (!intel_tc_port_in_tbt_alt_mode(dig_port)) |
2644 | intel_display_power_put(dev_priv, |
2645 | dig_port->ddi_io_power_domain, |
2646 | fetch_and_zero(&dig_port->ddi_io_wakeref)({ typeof(*&dig_port->ddi_io_wakeref) __T = *(&dig_port ->ddi_io_wakeref); *(&dig_port->ddi_io_wakeref) = ( typeof(*&dig_port->ddi_io_wakeref))0; __T; })); |
2647 | |
2648 | intel_ddi_disable_clock(encoder); |
2649 | } |
2650 | |
2651 | static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state, |
2652 | struct intel_encoder *encoder, |
2653 | const struct intel_crtc_state *old_crtc_state, |
2654 | const struct drm_connector_state *old_conn_state) |
2655 | { |
2656 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2657 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2658 | struct intel_hdmi *intel_hdmi = &dig_port->hdmi; |
2659 | |
2660 | dig_port->set_infoframes(encoder, false0, |
2661 | old_crtc_state, old_conn_state); |
2662 | |
2663 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 12) |
2664 | intel_ddi_disable_pipe_clock(old_crtc_state); |
2665 | |
2666 | intel_disable_ddi_buf(encoder, old_crtc_state); |
2667 | |
2668 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
2669 | intel_ddi_disable_pipe_clock(old_crtc_state); |
2670 | |
2671 | intel_display_power_put(dev_priv, |
2672 | dig_port->ddi_io_power_domain, |
2673 | fetch_and_zero(&dig_port->ddi_io_wakeref)({ typeof(*&dig_port->ddi_io_wakeref) __T = *(&dig_port ->ddi_io_wakeref); *(&dig_port->ddi_io_wakeref) = ( typeof(*&dig_port->ddi_io_wakeref))0; __T; })); |
2674 | |
2675 | intel_ddi_disable_clock(encoder); |
2676 | |
2677 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false0); |
2678 | } |
2679 | |
2680 | static void intel_ddi_post_disable(struct intel_atomic_state *state, |
2681 | struct intel_encoder *encoder, |
2682 | const struct intel_crtc_state *old_crtc_state, |
2683 | const struct drm_connector_state *old_conn_state) |
2684 | { |
2685 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2686 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2687 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
2688 | bool_Bool is_tc_port = intel_phy_is_tc(dev_priv, phy); |
2689 | struct intel_crtc *slave_crtc; |
2690 | |
2691 | if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) { |
2692 | intel_crtc_vblank_off(old_crtc_state); |
2693 | |
2694 | intel_disable_transcoder(old_crtc_state); |
2695 | |
2696 | intel_vrr_disable(old_crtc_state); |
2697 | |
2698 | intel_ddi_disable_transcoder_func(old_crtc_state); |
2699 | |
2700 | intel_dsc_disable(old_crtc_state); |
2701 | |
2702 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 9) |
2703 | skl_scaler_disable(old_crtc_state); |
2704 | else |
2705 | ilk_pfit_disable(old_crtc_state); |
2706 | } |
2707 | |
2708 | for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,for (slave_crtc = ({ const __typeof( ((__typeof(*slave_crtc) * )0)->base.head ) *__mptr = ((&(&dev_priv->drm)-> mode_config.crtc_list)->next); (__typeof(*slave_crtc) *)( ( char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base .head) );}); &slave_crtc->base.head != (&(&dev_priv ->drm)->mode_config.crtc_list); slave_crtc = ({ const __typeof ( ((__typeof(*slave_crtc) *)0)->base.head ) *__mptr = (slave_crtc ->base.head.next); (__typeof(*slave_crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base.head) );})) if (!((intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) & (1UL << (slave_crtc->pipe)))) {} else |
2709 | intel_crtc_bigjoiner_slave_pipes(old_crtc_state))for (slave_crtc = ({ const __typeof( ((__typeof(*slave_crtc) * )0)->base.head ) *__mptr = ((&(&dev_priv->drm)-> mode_config.crtc_list)->next); (__typeof(*slave_crtc) *)( ( char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base .head) );}); &slave_crtc->base.head != (&(&dev_priv ->drm)->mode_config.crtc_list); slave_crtc = ({ const __typeof ( ((__typeof(*slave_crtc) *)0)->base.head ) *__mptr = (slave_crtc ->base.head.next); (__typeof(*slave_crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base.head) );})) if (!((intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) & (1UL << (slave_crtc->pipe)))) {} else { |
2710 | const struct intel_crtc_state *old_slave_crtc_state = |
2711 | intel_atomic_get_old_crtc_state(state, slave_crtc); |
2712 | |
2713 | intel_crtc_vblank_off(old_slave_crtc_state); |
2714 | |
2715 | intel_dsc_disable(old_slave_crtc_state); |
2716 | skl_scaler_disable(old_slave_crtc_state); |
2717 | } |
2718 | |
2719 | /* |
2720 | * When called from DP MST code: |
2721 | * - old_conn_state will be NULL |
2722 | * - encoder will be the main encoder (ie. mst->primary) |
2723 | * - the main connector associated with this port |
2724 | * won't be active or linked to a crtc |
2725 | * - old_crtc_state will be the state of the last stream to |
2726 | * be deactivated on this port, and it may not be the same |
2727 | * stream that was activated last, but each stream |
2728 | * should have a state that is identical when it comes to |
2729 | * the DP link parameteres |
2730 | */ |
2731 | |
2732 | if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) |
2733 | intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state, |
2734 | old_conn_state); |
2735 | else |
2736 | intel_ddi_post_disable_dp(state, encoder, old_crtc_state, |
2737 | old_conn_state); |
2738 | |
2739 | if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port) |
2740 | intel_display_power_put(dev_priv, |
2741 | intel_ddi_main_link_aux_domain(dig_port), |
2742 | fetch_and_zero(&dig_port->aux_wakeref)({ typeof(*&dig_port->aux_wakeref) __T = *(&dig_port ->aux_wakeref); *(&dig_port->aux_wakeref) = (typeof (*&dig_port->aux_wakeref))0; __T; })); |
2743 | |
2744 | if (is_tc_port) |
2745 | intel_tc_port_put_link(dig_port); |
2746 | } |
2747 | |
2748 | static void trans_port_sync_stop_link_train(struct intel_atomic_state *state, |
2749 | struct intel_encoder *encoder, |
2750 | const struct intel_crtc_state *crtc_state) |
2751 | { |
2752 | const struct drm_connector_state *conn_state; |
2753 | struct drm_connector *conn; |
2754 | int i; |
2755 | |
2756 | if (!crtc_state->sync_mode_slaves_mask) |
2757 | return; |
2758 | |
2759 | for_each_new_connector_in_state(&state->base, conn, conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((conn) = (&state->base)->connectors[i].ptr, (void )(conn) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
2760 | struct intel_encoder *slave_encoder = |
2761 | to_intel_encoder(conn_state->best_encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (conn_state->best_encoder); (struct intel_encoder *)( ( char *)__mptr - __builtin_offsetof(struct intel_encoder, base ) );}); |
2762 | struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (conn_state->crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
2763 | const struct intel_crtc_state *slave_crtc_state; |
2764 | |
2765 | if (!slave_crtc) |
2766 | continue; |
2767 | |
2768 | slave_crtc_state = |
2769 | intel_atomic_get_new_crtc_state(state, slave_crtc); |
2770 | |
2771 | if (slave_crtc_state->master_transcoder != |
2772 | crtc_state->cpu_transcoder) |
2773 | continue; |
2774 | |
2775 | intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder), |
2776 | slave_crtc_state); |
2777 | } |
2778 | |
2779 | usleep_range(200, 400); |
2780 | |
2781 | intel_dp_stop_link_train(enc_to_intel_dp(encoder), |
2782 | crtc_state); |
2783 | } |
2784 | |
2785 | static void intel_enable_ddi_dp(struct intel_atomic_state *state, |
2786 | struct intel_encoder *encoder, |
2787 | const struct intel_crtc_state *crtc_state, |
2788 | const struct drm_connector_state *conn_state) |
2789 | { |
2790 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2791 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2792 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2793 | enum port port = encoder->port; |
2794 | |
2795 | if (port == PORT_A && DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 9) |
2796 | intel_dp_stop_link_train(intel_dp, crtc_state); |
2797 | |
2798 | drm_connector_update_privacy_screen(conn_state); |
2799 | intel_edp_backlight_on(crtc_state, conn_state); |
2800 | |
2801 | if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink) |
2802 | intel_dp_set_infoframes(encoder, true1, crtc_state, conn_state); |
2803 | |
2804 | intel_audio_codec_enable(encoder, crtc_state, conn_state); |
2805 | |
2806 | trans_port_sync_stop_link_train(state, encoder, crtc_state); |
2807 | } |
2808 | |
2809 | static i915_reg_t |
2810 | gen9_chicken_trans_reg_by_port(struct drm_i915_privateinteldrm_softc *dev_priv, |
2811 | enum port port) |
2812 | { |
2813 | static const enum transcoder trans[] = { |
2814 | [PORT_A] = TRANSCODER_EDP, |
2815 | [PORT_B] = TRANSCODER_A, |
2816 | [PORT_C] = TRANSCODER_B, |
2817 | [PORT_D] = TRANSCODER_C, |
2818 | [PORT_E] = TRANSCODER_A, |
2819 | }; |
2820 | |
2821 | drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9)({ int __ret = !!((((&(dev_priv)->__runtime)->display .ip.ver) < 9)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&dev_priv->drm))->dev), "", "drm_WARN_ON(" "((&(dev_priv)->__runtime)->display.ip.ver) < 9" ")"); __builtin_expect(!!(__ret), 0); }); |
2822 | |
2823 | if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)({ int __ret = !!((port < PORT_A || port > PORT_E)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "port < PORT_A || port > PORT_E" ")"); __builtin_expect(!!(__ret), 0); })) |
2824 | port = PORT_A; |
2825 | |
2826 | return CHICKEN_TRANS(trans[port])((const i915_reg_t){ .reg = ((((const u32 []){ [TRANSCODER_EDP ] = 0x420cc, [TRANSCODER_A] = 0x420c0, [TRANSCODER_B] = 0x420c4 , [TRANSCODER_C] = 0x420c8, [TRANSCODER_D] = 0x420d8 })[(trans [port])])) }); |
2827 | } |
2828 | |
2829 | static void intel_enable_ddi_hdmi(struct intel_atomic_state *state, |
2830 | struct intel_encoder *encoder, |
2831 | const struct intel_crtc_state *crtc_state, |
2832 | const struct drm_connector_state *conn_state) |
2833 | { |
2834 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
2835 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
2836 | struct drm_connector *connector = conn_state->connector; |
2837 | enum port port = encoder->port; |
2838 | enum phy phy = intel_port_to_phy(dev_priv, port); |
2839 | u32 buf_ctl; |
2840 | |
2841 | if (!intel_hdmi_handle_sink_scrambling(encoder, connector, |
2842 | crtc_state->hdmi_high_tmds_clock_ratio, |
2843 | crtc_state->hdmi_scrambling)) |
2844 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n" , connector->base.id, connector->name) |
2845 | "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n" , connector->base.id, connector->name) |
2846 | connector->base.id, connector->name)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n" , connector->base.id, connector->name); |
2847 | |
2848 | if (has_buf_trans_select(dev_priv)) |
2849 | hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state); |
2850 | |
2851 | encoder->set_signal_levels(encoder, crtc_state); |
2852 | |
2853 | /* Display WA #1143: skl,kbl,cfl */ |
2854 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9 && !IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) { |
2855 | /* |
2856 | * For some reason these chicken bits have been |
2857 | * stuffed into a transcoder register, event though |
2858 | * the bits affect a specific DDI port rather than |
2859 | * a specific transcoder. |
2860 | */ |
2861 | i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port); |
2862 | u32 val; |
2863 | |
2864 | val = intel_de_read(dev_priv, reg); |
2865 | |
2866 | if (port == PORT_E) |
2867 | val |= DDIE_TRAINING_OVERRIDE_ENABLE((u32)((1UL << (17)) + 0)) | |
2868 | DDIE_TRAINING_OVERRIDE_VALUE((u32)((1UL << (16)) + 0)); |
2869 | else |
2870 | val |= DDI_TRAINING_OVERRIDE_ENABLE((u32)((1UL << (19)) + 0)) | |
2871 | DDI_TRAINING_OVERRIDE_VALUE((u32)((1UL << (18)) + 0)); |
2872 | |
2873 | intel_de_write(dev_priv, reg, val); |
2874 | intel_de_posting_read(dev_priv, reg); |
2875 | |
2876 | udelay(1); |
2877 | |
2878 | if (port == PORT_E) |
2879 | val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE((u32)((1UL << (17)) + 0)) | |
2880 | DDIE_TRAINING_OVERRIDE_VALUE((u32)((1UL << (16)) + 0))); |
2881 | else |
2882 | val &= ~(DDI_TRAINING_OVERRIDE_ENABLE((u32)((1UL << (19)) + 0)) | |
2883 | DDI_TRAINING_OVERRIDE_VALUE((u32)((1UL << (18)) + 0))); |
2884 | |
2885 | intel_de_write(dev_priv, reg, val); |
2886 | } |
2887 | |
2888 | intel_ddi_power_up_lanes(encoder, crtc_state); |
2889 | |
2890 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
2891 | * are ignored so nothing special needs to be done besides |
2892 | * enabling the port. |
2893 | * |
2894 | * On ADL_P the PHY link rate and lane count must be programmed but |
2895 | * these are both 0 for HDMI. |
2896 | */ |
2897 | buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE(1 << 31); |
2898 | if (IS_ALDERLAKE_P(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) && intel_phy_is_tc(dev_priv, phy)) { |
2899 | drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port))({ int __ret = !!((!intel_tc_port_in_legacy_mode(dig_port))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv ->drm))->dev), "", "drm_WARN_ON(" "!intel_tc_port_in_legacy_mode(dig_port)" ")"); __builtin_expect(!!(__ret), 0); }); |
2900 | buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP((u32)((1UL << (6)) + 0)); |
2901 | } |
2902 | intel_de_write(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }), buf_ctl); |
2903 | |
2904 | intel_audio_codec_enable(encoder, crtc_state, conn_state); |
2905 | } |
2906 | |
2907 | static void intel_enable_ddi(struct intel_atomic_state *state, |
2908 | struct intel_encoder *encoder, |
2909 | const struct intel_crtc_state *crtc_state, |
2910 | const struct drm_connector_state *conn_state) |
2911 | { |
2912 | drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder)({ int __ret = !!((crtc_state->has_pch_encoder)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((state->base.dev ))->dev), "", "drm_WARN_ON(" "crtc_state->has_pch_encoder" ")"); __builtin_expect(!!(__ret), 0); }); |
2913 | |
2914 | if (!intel_crtc_is_bigjoiner_slave(crtc_state)) |
2915 | intel_ddi_enable_transcoder_func(encoder, crtc_state); |
2916 | |
2917 | intel_vrr_enable(encoder, crtc_state); |
2918 | |
2919 | intel_enable_transcoder(crtc_state); |
2920 | |
2921 | intel_crtc_vblank_on(crtc_state); |
2922 | |
2923 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) |
2924 | intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state); |
2925 | else |
2926 | intel_enable_ddi_dp(state, encoder, crtc_state, conn_state); |
2927 | |
2928 | /* Enable hdcp if it's desired */ |
2929 | if (conn_state->content_protection == |
2930 | DRM_MODE_CONTENT_PROTECTION_DESIRED1) |
2931 | intel_hdcp_enable(to_intel_connector(conn_state->connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (conn_state->connector); (struct intel_connector * )( (char *)__mptr - __builtin_offsetof(struct intel_connector , base) );}), |
2932 | crtc_state, |
2933 | (u8)conn_state->hdcp_content_type); |
2934 | } |
2935 | |
2936 | static void intel_disable_ddi_dp(struct intel_atomic_state *state, |
2937 | struct intel_encoder *encoder, |
2938 | const struct intel_crtc_state *old_crtc_state, |
2939 | const struct drm_connector_state *old_conn_state) |
2940 | { |
2941 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
2942 | |
2943 | intel_dp->link_trained = false0; |
2944 | |
2945 | intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); |
2946 | |
2947 | intel_psr_disable(intel_dp, old_crtc_state); |
2948 | intel_edp_backlight_off(old_conn_state); |
2949 | /* Disable the decompression in DP Sink */ |
2950 | intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state, |
2951 | false0); |
2952 | /* Disable Ignore_MSA bit in DP Sink */ |
2953 | intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state, |
2954 | false0); |
2955 | } |
2956 | |
2957 | static void intel_disable_ddi_hdmi(struct intel_atomic_state *state, |
2958 | struct intel_encoder *encoder, |
2959 | const struct intel_crtc_state *old_crtc_state, |
2960 | const struct drm_connector_state *old_conn_state) |
2961 | { |
2962 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
2963 | struct drm_connector *connector = old_conn_state->connector; |
2964 | |
2965 | intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); |
2966 | |
2967 | if (!intel_hdmi_handle_sink_scrambling(encoder, connector, |
2968 | false0, false0)) |
2969 | drm_dbg_kms(&i915->drm,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n" , connector->base.id, connector->name) |
2970 | "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n" , connector->base.id, connector->name) |
2971 | connector->base.id, connector->name)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n" , connector->base.id, connector->name); |
2972 | } |
2973 | |
2974 | static void intel_disable_ddi(struct intel_atomic_state *state, |
2975 | struct intel_encoder *encoder, |
2976 | const struct intel_crtc_state *old_crtc_state, |
2977 | const struct drm_connector_state *old_conn_state) |
2978 | { |
2979 | intel_hdcp_disable(to_intel_connector(old_conn_state->connector)({ const __typeof( ((struct intel_connector *)0)->base ) * __mptr = (old_conn_state->connector); (struct intel_connector *)( (char *)__mptr - __builtin_offsetof(struct intel_connector , base) );})); |
2980 | |
2981 | if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI)) |
2982 | intel_disable_ddi_hdmi(state, encoder, old_crtc_state, |
2983 | old_conn_state); |
2984 | else |
2985 | intel_disable_ddi_dp(state, encoder, old_crtc_state, |
2986 | old_conn_state); |
2987 | } |
2988 | |
2989 | static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state, |
2990 | struct intel_encoder *encoder, |
2991 | const struct intel_crtc_state *crtc_state, |
2992 | const struct drm_connector_state *conn_state) |
2993 | { |
2994 | intel_ddi_set_dp_msa(crtc_state, conn_state); |
2995 | |
2996 | intel_dp_set_infoframes(encoder, true1, crtc_state, conn_state); |
2997 | |
2998 | intel_backlight_update(state, encoder, crtc_state, conn_state); |
2999 | drm_connector_update_privacy_screen(conn_state); |
3000 | } |
3001 | |
3002 | void intel_ddi_update_pipe(struct intel_atomic_state *state, |
3003 | struct intel_encoder *encoder, |
3004 | const struct intel_crtc_state *crtc_state, |
3005 | const struct drm_connector_state *conn_state) |
3006 | { |
3007 | |
3008 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && |
3009 | !intel_encoder_is_mst(encoder)) |
3010 | intel_ddi_update_pipe_dp(state, encoder, crtc_state, |
3011 | conn_state); |
3012 | |
3013 | intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state); |
3014 | } |
3015 | |
3016 | static void |
3017 | intel_ddi_update_prepare(struct intel_atomic_state *state, |
3018 | struct intel_encoder *encoder, |
3019 | struct intel_crtc *crtc) |
3020 | { |
3021 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(state->base.dev); |
3022 | struct intel_crtc_state *crtc_state = |
3023 | crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL((void *)0); |
3024 | int required_lanes = crtc_state ? crtc_state->lane_count : 1; |
3025 | |
3026 | drm_WARN_ON(state->base.dev, crtc && crtc->active)({ int __ret = !!((crtc && crtc->active)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((state->base.dev ))->dev), "", "drm_WARN_ON(" "crtc && crtc->active" ")"); __builtin_expect(!!(__ret), 0); }); |
3027 | |
3028 | intel_tc_port_get_link(enc_to_dig_port(encoder), |
3029 | required_lanes); |
3030 | if (crtc_state && crtc_state->hw.active) { |
3031 | struct intel_crtc *slave_crtc; |
3032 | |
3033 | intel_update_active_dpll(state, crtc, encoder); |
3034 | |
3035 | for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,for (slave_crtc = ({ const __typeof( ((__typeof(*slave_crtc) * )0)->base.head ) *__mptr = ((&(&i915->drm)-> mode_config.crtc_list)->next); (__typeof(*slave_crtc) *)( ( char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base .head) );}); &slave_crtc->base.head != (&(&i915 ->drm)->mode_config.crtc_list); slave_crtc = ({ const __typeof ( ((__typeof(*slave_crtc) *)0)->base.head ) *__mptr = (slave_crtc ->base.head.next); (__typeof(*slave_crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base.head) );})) if (!((intel_crtc_bigjoiner_slave_pipes(crtc_state)) & ( 1UL << (slave_crtc->pipe)))) {} else |
3036 | intel_crtc_bigjoiner_slave_pipes(crtc_state))for (slave_crtc = ({ const __typeof( ((__typeof(*slave_crtc) * )0)->base.head ) *__mptr = ((&(&i915->drm)-> mode_config.crtc_list)->next); (__typeof(*slave_crtc) *)( ( char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base .head) );}); &slave_crtc->base.head != (&(&i915 ->drm)->mode_config.crtc_list); slave_crtc = ({ const __typeof ( ((__typeof(*slave_crtc) *)0)->base.head ) *__mptr = (slave_crtc ->base.head.next); (__typeof(*slave_crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof(*slave_crtc), base.head) );})) if (!((intel_crtc_bigjoiner_slave_pipes(crtc_state)) & ( 1UL << (slave_crtc->pipe)))) {} else |
3037 | intel_update_active_dpll(state, slave_crtc, encoder); |
3038 | } |
3039 | } |
3040 | |
3041 | static void |
3042 | intel_ddi_update_complete(struct intel_atomic_state *state, |
3043 | struct intel_encoder *encoder, |
3044 | struct intel_crtc *crtc) |
3045 | { |
3046 | intel_tc_port_put_link(enc_to_dig_port(encoder)); |
3047 | } |
3048 | |
3049 | static void |
3050 | intel_ddi_pre_pll_enable(struct intel_atomic_state *state, |
3051 | struct intel_encoder *encoder, |
3052 | const struct intel_crtc_state *crtc_state, |
3053 | const struct drm_connector_state *conn_state) |
3054 | { |
3055 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3056 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
3057 | enum phy phy = intel_port_to_phy(dev_priv, encoder->port); |
3058 | bool_Bool is_tc_port = intel_phy_is_tc(dev_priv, phy); |
3059 | |
3060 | if (is_tc_port) |
3061 | intel_tc_port_get_link(dig_port, crtc_state->lane_count); |
3062 | |
3063 | if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) { |
3064 | drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref)({ int __ret = !!((dig_port->aux_wakeref)); if (__ret) printf ("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))-> dev), "", "drm_WARN_ON(" "dig_port->aux_wakeref" ")"); __builtin_expect (!!(__ret), 0); }); |
3065 | dig_port->aux_wakeref = |
3066 | intel_display_power_get(dev_priv, |
3067 | intel_ddi_main_link_aux_domain(dig_port)); |
3068 | } |
3069 | |
3070 | if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port)) |
3071 | /* |
3072 | * Program the lane count for static/dynamic connections on |
3073 | * Type-C ports. Skip this step for TBT. |
3074 | */ |
3075 | intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); |
3076 | else if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
3077 | bxt_ddi_phy_set_lane_optim_mask(encoder, |
3078 | crtc_state->lane_lat_optim_mask); |
3079 | } |
3080 | |
3081 | static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder) |
3082 | { |
3083 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3084 | enum tc_port tc_port = intel_port_to_tc(i915, encoder->port); |
3085 | int ln; |
3086 | |
3087 | for (ln = 0; ln < 2; ln++) |
3088 | intel_dkl_phy_rmw(i915, DKL_PCS_DW5(tc_port)((const i915_reg_t){ .reg = (((0x168000) + (tc_port) * ((0x169000 ) - (0x168000))) + 0x14) }), ln, DKL_PCS_DW5_CORE_SOFTRESET((u32)((1UL << (11)) + 0)), 0); |
3089 | } |
3090 | |
3091 | static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, |
3092 | const struct intel_crtc_state *crtc_state) |
3093 | { |
3094 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3095 | struct intel_encoder *encoder = &dig_port->base; |
3096 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3097 | enum port port = encoder->port; |
3098 | u32 dp_tp_ctl, ddi_buf_ctl; |
3099 | bool_Bool wait = false0; |
3100 | |
3101 | dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
3102 | |
3103 | if (dp_tp_ctl & DP_TP_CTL_ENABLE(1 << 31)) { |
3104 | ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })); |
3105 | if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE(1 << 31)) { |
3106 | intel_de_write(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }), |
3107 | ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE(1 << 31)); |
3108 | wait = true1; |
3109 | } |
3110 | |
3111 | dp_tp_ctl &= ~(DP_TP_CTL_ENABLE(1 << 31) | DP_TP_CTL_LINK_TRAIN_MASK(7 << 8)); |
3112 | dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1(0 << 8); |
3113 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); |
3114 | intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
3115 | |
3116 | if (wait) |
3117 | intel_wait_ddi_buf_idle(dev_priv, port); |
3118 | } |
3119 | |
3120 | dp_tp_ctl = DP_TP_CTL_ENABLE(1 << 31) | DP_TP_CTL_LINK_TRAIN_PAT1(0 << 8); |
3121 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { |
3122 | dp_tp_ctl |= DP_TP_CTL_MODE_MST(1 << 27); |
3123 | } else { |
3124 | dp_tp_ctl |= DP_TP_CTL_MODE_SST(0 << 27); |
3125 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
3126 | dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE(1 << 18); |
3127 | } |
3128 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl); |
3129 | intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
3130 | |
3131 | if (IS_ALDERLAKE_P(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) && |
3132 | (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port))) |
3133 | adlp_tbt_to_dp_alt_switch_wa(encoder); |
3134 | |
3135 | intel_dp->DP |= DDI_BUF_CTL_ENABLE(1 << 31); |
3136 | intel_de_write(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }), intel_dp->DP); |
3137 | intel_de_posting_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })); |
3138 | |
3139 | intel_wait_ddi_buf_active(dev_priv, port); |
3140 | } |
3141 | |
3142 | static void intel_ddi_set_link_train(struct intel_dp *intel_dp, |
3143 | const struct intel_crtc_state *crtc_state, |
3144 | u8 dp_train_pat) |
3145 | { |
3146 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3147 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3148 | u32 temp; |
3149 | |
3150 | temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
3151 | |
3152 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK(7 << 8); |
3153 | switch (intel_dp_training_pattern_symbol(dp_train_pat)) { |
3154 | case DP_TRAINING_PATTERN_DISABLE0: |
3155 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL(3 << 8); |
3156 | break; |
3157 | case DP_TRAINING_PATTERN_11: |
3158 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1(0 << 8); |
3159 | break; |
3160 | case DP_TRAINING_PATTERN_22: |
3161 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2(1 << 8); |
3162 | break; |
3163 | case DP_TRAINING_PATTERN_33: |
3164 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3(4 << 8); |
3165 | break; |
3166 | case DP_TRAINING_PATTERN_47: |
3167 | temp |= DP_TP_CTL_LINK_TRAIN_PAT4(5 << 8); |
3168 | break; |
3169 | } |
3170 | |
3171 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp); |
3172 | } |
3173 | |
3174 | static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, |
3175 | const struct intel_crtc_state *crtc_state) |
3176 | { |
3177 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3178 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3179 | enum port port = encoder->port; |
3180 | u32 val; |
3181 | |
3182 | val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state)); |
3183 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK(7 << 8); |
3184 | val |= DP_TP_CTL_LINK_TRAIN_IDLE(2 << 8); |
3185 | intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val); |
3186 | |
3187 | /* |
3188 | * Until TGL on PORT_A we can have only eDP in SST mode. There the only |
3189 | * reason we need to set idle transmission mode is to work around a HW |
3190 | * issue where we enable the pipe while not in idle link-training mode. |
3191 | * In this case there is requirement to wait for a minimum number of |
3192 | * idle patterns to be sent. |
3193 | */ |
3194 | if (port == PORT_A && DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 12) |
3195 | return; |
3196 | |
3197 | if (intel_de_wait_for_set(dev_priv, |
3198 | dp_tp_status_reg(encoder, crtc_state), |
3199 | DP_TP_STATUS_IDLE_DONE(1 << 25), 1)) |
3200 | drm_err(&dev_priv->drm,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for DP idle patterns\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__) |
3201 | "Timed out waiting for DP idle patterns\n")printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Timed out waiting for DP idle patterns\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
3202 | } |
3203 | |
3204 | static bool_Bool intel_ddi_is_audio_enabled(struct drm_i915_privateinteldrm_softc *dev_priv, |
3205 | enum transcoder cpu_transcoder) |
3206 | { |
3207 | if (cpu_transcoder == TRANSCODER_EDP) |
3208 | return false0; |
3209 | |
3210 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO)) |
3211 | return false0; |
3212 | |
3213 | return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD((const i915_reg_t){ .reg = (0x650c0) })) & |
3214 | AUDIO_OUTPUT_ENABLE(cpu_transcoder)((1 << 2) << ((cpu_transcoder) * 4)); |
3215 | } |
3216 | |
3217 | void intel_ddi_compute_min_voltage_level(struct drm_i915_privateinteldrm_softc *dev_priv, |
3218 | struct intel_crtc_state *crtc_state) |
3219 | { |
3220 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12 && crtc_state->port_clock > 594000) |
3221 | crtc_state->min_voltage_level = 2; |
3222 | else if (IS_JSL_EHL(dev_priv)(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || IS_PLATFORM(dev_priv , INTEL_ELKHARTLAKE)) && crtc_state->port_clock > 594000) |
3223 | crtc_state->min_voltage_level = 3; |
3224 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11 && crtc_state->port_clock > 594000) |
3225 | crtc_state->min_voltage_level = 1; |
3226 | } |
3227 | |
3228 | static enum transcoder bdw_transcoder_master_readout(struct drm_i915_privateinteldrm_softc *dev_priv, |
3229 | enum transcoder cpu_transcoder) |
3230 | { |
3231 | u32 master_select; |
3232 | |
3233 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
3234 | u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60404)) })); |
3235 | |
3236 | if ((ctl2 & PORT_SYNC_MODE_ENABLE((u32)((1UL << (4)) + 0))) == 0) |
3237 | return INVALID_TRANSCODER; |
3238 | |
3239 | master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2)((u32)((typeof(((u32)((((~0UL) >> (64 - (2) - 1)) & ((~0UL) << (0))) + 0))))(((ctl2) & (((u32)((((~0UL ) >> (64 - (2) - 1)) & ((~0UL) << (0))) + 0)) )) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - ( 2) - 1)) & ((~0UL) << (0))) + 0))) - 1)))); |
3240 | } else { |
3241 | u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
3242 | |
3243 | if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE((u32)((1UL << (15)) + 0))) == 0) |
3244 | return INVALID_TRANSCODER; |
3245 | |
3246 | master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl)((u32)((typeof(((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) << (18))) + 0))))(((ctl) & (((u32)((((~0UL ) >> (64 - (19) - 1)) & ((~0UL) << (18))) + 0 )))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (19) - 1)) & ((~0UL) << (18))) + 0))) - 1)))); |
3247 | } |
3248 | |
3249 | if (master_select == 0) |
3250 | return TRANSCODER_EDP; |
3251 | else |
3252 | return master_select - 1; |
3253 | } |
3254 | |
3255 | static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state) |
3256 | { |
3257 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc_state->uapi.crtc->dev); |
3258 | u32 transcoders = BIT(TRANSCODER_A)(1UL << (TRANSCODER_A)) | BIT(TRANSCODER_B)(1UL << (TRANSCODER_B)) | |
3259 | BIT(TRANSCODER_C)(1UL << (TRANSCODER_C)) | BIT(TRANSCODER_D)(1UL << (TRANSCODER_D)); |
3260 | enum transcoder cpu_transcoder; |
3261 | |
3262 | crtc_state->master_transcoder = |
3263 | bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); |
3264 | |
3265 | for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders)for ((cpu_transcoder) = 0; (cpu_transcoder) < I915_MAX_TRANSCODERS ; (cpu_transcoder)++) if (!((&(dev_priv)->__runtime)-> cpu_transcoder_mask & (1UL << (cpu_transcoder)))) { } else if (!((transcoders) & (1UL << (cpu_transcoder )))) {} else { |
3266 | enum intel_display_power_domain power_domain; |
3267 | intel_wakeref_t trans_wakeref; |
3268 | |
3269 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder)((cpu_transcoder) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : (cpu_transcoder) + POWER_DOMAIN_TRANSCODER_A); |
3270 | trans_wakeref = intel_display_power_get_if_enabled(dev_priv, |
3271 | power_domain); |
3272 | |
3273 | if (!trans_wakeref) |
3274 | continue; |
3275 | |
3276 | if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) == |
3277 | crtc_state->cpu_transcoder) |
3278 | crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder)(1UL << (cpu_transcoder)); |
3279 | |
3280 | intel_display_power_put(dev_priv, power_domain, trans_wakeref); |
3281 | } |
3282 | |
3283 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask" ")"); __builtin_expect(!!(__ret), 0); }) |
3284 | crtc_state->master_transcoder != INVALID_TRANSCODER &&({ int __ret = !!((crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask" ")"); __builtin_expect(!!(__ret), 0); }) |
3285 | crtc_state->sync_mode_slaves_mask)({ int __ret = !!((crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask)); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "crtc_state->master_transcoder != INVALID_TRANSCODER && crtc_state->sync_mode_slaves_mask" ")"); __builtin_expect(!!(__ret), 0); }); |
3286 | } |
3287 | |
3288 | static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, |
3289 | struct intel_crtc_state *pipe_config) |
3290 | { |
3291 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3292 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
3293 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
3294 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
3295 | u32 temp, flags = 0; |
3296 | |
3297 | temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)-> display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)-> __info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv )->__info)->display.mmio_offset) + (0x60400)) })); |
3298 | if (temp & TRANS_DDI_PHSYNC(1 << 16)) |
3299 | flags |= DRM_MODE_FLAG_PHSYNC(1<<0); |
3300 | else |
3301 | flags |= DRM_MODE_FLAG_NHSYNC(1<<1); |
3302 | if (temp & TRANS_DDI_PVSYNC(1 << 17)) |
3303 | flags |= DRM_MODE_FLAG_PVSYNC(1<<2); |
3304 | else |
3305 | flags |= DRM_MODE_FLAG_NVSYNC(1<<3); |
3306 | |
3307 | pipe_config->hw.adjusted_mode.flags |= flags; |
3308 | |
3309 | switch (temp & TRANS_DDI_BPC_MASK(7 << 20)) { |
3310 | case TRANS_DDI_BPC_6(2 << 20): |
3311 | pipe_config->pipe_bpp = 18; |
3312 | break; |
3313 | case TRANS_DDI_BPC_8(0 << 20): |
3314 | pipe_config->pipe_bpp = 24; |
3315 | break; |
3316 | case TRANS_DDI_BPC_10(1 << 20): |
3317 | pipe_config->pipe_bpp = 30; |
3318 | break; |
3319 | case TRANS_DDI_BPC_12(3 << 20): |
3320 | pipe_config->pipe_bpp = 36; |
3321 | break; |
3322 | default: |
3323 | break; |
3324 | } |
3325 | |
3326 | switch (temp & TRANS_DDI_MODE_SELECT_MASK(7 << 24)) { |
3327 | case TRANS_DDI_MODE_SELECT_HDMI(0 << 24): |
3328 | pipe_config->has_hdmi_sink = true1; |
3329 | |
3330 | pipe_config->infoframes.enable |= |
3331 | intel_hdmi_infoframes_enabled(encoder, pipe_config); |
3332 | |
3333 | if (pipe_config->infoframes.enable) |
3334 | pipe_config->has_infoframe = true1; |
3335 | |
3336 | if (temp & TRANS_DDI_HDMI_SCRAMBLING(1 << 0)) |
3337 | pipe_config->hdmi_scrambling = true1; |
3338 | if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE(1 << 4)) |
3339 | pipe_config->hdmi_high_tmds_clock_ratio = true1; |
3340 | fallthroughdo {} while (0); |
3341 | case TRANS_DDI_MODE_SELECT_DVI(1 << 24): |
3342 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI)(1UL << (INTEL_OUTPUT_HDMI)); |
3343 | pipe_config->lane_count = 4; |
3344 | break; |
3345 | case TRANS_DDI_MODE_SELECT_DP_SST(2 << 24): |
3346 | if (encoder->type == INTEL_OUTPUT_EDP) |
3347 | pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP)(1UL << (INTEL_OUTPUT_EDP)); |
3348 | else |
3349 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP)(1UL << (INTEL_OUTPUT_DP)); |
3350 | pipe_config->lane_count = |
3351 | ((temp & DDI_PORT_WIDTH_MASK(7 << 1)) >> DDI_PORT_WIDTH_SHIFT1) + 1; |
3352 | |
3353 | intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, |
3354 | &pipe_config->dp_m_n); |
3355 | intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, |
3356 | &pipe_config->dp_m2_n2); |
3357 | |
3358 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
3359 | i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config); |
3360 | |
3361 | pipe_config->fec_enable = |
3362 | intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE(1 << 30); |
3363 | |
3364 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] Fec status: %u\n" , encoder->base.base.id, encoder->base.name, pipe_config ->fec_enable) |
3365 | "[ENCODER:%d:%s] Fec status: %u\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] Fec status: %u\n" , encoder->base.base.id, encoder->base.name, pipe_config ->fec_enable) |
3366 | encoder->base.base.id, encoder->base.name,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] Fec status: %u\n" , encoder->base.base.id, encoder->base.name, pipe_config ->fec_enable) |
3367 | pipe_config->fec_enable)__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] Fec status: %u\n" , encoder->base.base.id, encoder->base.name, pipe_config ->fec_enable); |
3368 | } |
3369 | |
3370 | if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink) |
3371 | pipe_config->infoframes.enable |= |
3372 | intel_lspcon_infoframes_enabled(encoder, pipe_config); |
3373 | else |
3374 | pipe_config->infoframes.enable |= |
3375 | intel_hdmi_infoframes_enabled(encoder, pipe_config); |
3376 | break; |
3377 | case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B(4 << 24): |
3378 | if (!HAS_DP20(dev_priv)(IS_PLATFORM(dev_priv, INTEL_DG2) || ((&(dev_priv)->__runtime )->display.ip.ver) >= 14)) { |
3379 | /* FDI */ |
3380 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG)(1UL << (INTEL_OUTPUT_ANALOG)); |
3381 | break; |
3382 | } |
3383 | fallthroughdo {} while (0); /* 128b/132b */ |
3384 | case TRANS_DDI_MODE_SELECT_DP_MST(3 << 24): |
3385 | pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST)(1UL << (INTEL_OUTPUT_DP_MST)); |
3386 | pipe_config->lane_count = |
3387 | ((temp & DDI_PORT_WIDTH_MASK(7 << 1)) >> DDI_PORT_WIDTH_SHIFT1) + 1; |
3388 | |
3389 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
3390 | pipe_config->mst_master_transcoder = |
3391 | REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp)((u32)((typeof(((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) << (10))) + 0))))(((temp) & (((u32)((((~0UL ) >> (64 - (11) - 1)) & ((~0UL) << (10))) + 0 )))) >> (__builtin_ffsll(((u32)((((~0UL) >> (64 - (11) - 1)) & ((~0UL) << (10))) + 0))) - 1)))); |
3392 | |
3393 | intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, |
3394 | &pipe_config->dp_m_n); |
3395 | |
3396 | pipe_config->infoframes.enable |= |
3397 | intel_hdmi_infoframes_enabled(encoder, pipe_config); |
3398 | break; |
3399 | default: |
3400 | break; |
3401 | } |
3402 | } |
3403 | |
3404 | static void intel_ddi_get_config(struct intel_encoder *encoder, |
3405 | struct intel_crtc_state *pipe_config) |
3406 | { |
3407 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3408 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
3409 | |
3410 | /* XXX: DSI transcoder paranoia */ |
3411 | if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))({ int __ret = !!((transcoder_is_dsi(cpu_transcoder))); if (__ret ) printf("%s %s: " "%s", dev_driver_string(((&dev_priv-> drm))->dev), "", "drm_WARN_ON(" "transcoder_is_dsi(cpu_transcoder)" ")"); __builtin_expect(!!(__ret), 0); })) |
3412 | return; |
3413 | |
3414 | intel_ddi_read_func_ctl(encoder, pipe_config); |
3415 | |
3416 | intel_ddi_mso_get_config(encoder, pipe_config); |
3417 | |
3418 | pipe_config->has_audio = |
3419 | intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder); |
3420 | |
3421 | if (encoder->type == INTEL_OUTPUT_EDP) |
3422 | intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); |
3423 | |
3424 | ddi_dotclock_get(pipe_config); |
3425 | |
3426 | if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
3427 | pipe_config->lane_lat_optim_mask = |
3428 | bxt_ddi_phy_get_lane_lat_optim_mask(encoder); |
3429 | |
3430 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); |
3431 | |
3432 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); |
3433 | |
3434 | intel_read_infoframe(encoder, pipe_config, |
3435 | HDMI_INFOFRAME_TYPE_AVI, |
3436 | &pipe_config->infoframes.avi); |
3437 | intel_read_infoframe(encoder, pipe_config, |
3438 | HDMI_INFOFRAME_TYPE_SPD, |
3439 | &pipe_config->infoframes.spd); |
3440 | intel_read_infoframe(encoder, pipe_config, |
3441 | HDMI_INFOFRAME_TYPE_VENDOR, |
3442 | &pipe_config->infoframes.hdmi); |
3443 | intel_read_infoframe(encoder, pipe_config, |
3444 | HDMI_INFOFRAME_TYPE_DRM, |
3445 | &pipe_config->infoframes.drm); |
3446 | |
3447 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 8) |
3448 | bdw_get_trans_port_sync_config(pipe_config); |
3449 | |
3450 | intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); |
3451 | intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC0x07); |
3452 | |
3453 | intel_psr_get_config(encoder, pipe_config); |
3454 | } |
3455 | |
3456 | void intel_ddi_get_clock(struct intel_encoder *encoder, |
3457 | struct intel_crtc_state *crtc_state, |
3458 | struct intel_shared_dpll *pll) |
3459 | { |
3460 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3461 | enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
3462 | struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; |
3463 | bool_Bool pll_active; |
3464 | |
3465 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
3466 | return; |
3467 | |
3468 | port_dpll->pll = pll; |
3469 | pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); |
3470 | drm_WARN_ON(&i915->drm, !pll_active)({ int __ret = !!((!pll_active)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll_active" ")"); __builtin_expect(!!(__ret), 0); }); |
3471 | |
3472 | icl_set_active_port_dpll(crtc_state, port_dpll_id); |
3473 | |
3474 | crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, |
3475 | &crtc_state->dpll_hw_state); |
3476 | } |
3477 | |
3478 | static void dg2_ddi_get_config(struct intel_encoder *encoder, |
3479 | struct intel_crtc_state *crtc_state) |
3480 | { |
3481 | intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state); |
3482 | crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state); |
3483 | |
3484 | intel_ddi_get_config(encoder, crtc_state); |
3485 | } |
3486 | |
3487 | static void adls_ddi_get_config(struct intel_encoder *encoder, |
3488 | struct intel_crtc_state *crtc_state) |
3489 | { |
3490 | intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder)); |
3491 | intel_ddi_get_config(encoder, crtc_state); |
3492 | } |
3493 | |
3494 | static void rkl_ddi_get_config(struct intel_encoder *encoder, |
3495 | struct intel_crtc_state *crtc_state) |
3496 | { |
3497 | intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder)); |
3498 | intel_ddi_get_config(encoder, crtc_state); |
3499 | } |
3500 | |
3501 | static void dg1_ddi_get_config(struct intel_encoder *encoder, |
3502 | struct intel_crtc_state *crtc_state) |
3503 | { |
3504 | intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder)); |
3505 | intel_ddi_get_config(encoder, crtc_state); |
3506 | } |
3507 | |
3508 | static void icl_ddi_combo_get_config(struct intel_encoder *encoder, |
3509 | struct intel_crtc_state *crtc_state) |
3510 | { |
3511 | intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder)); |
3512 | intel_ddi_get_config(encoder, crtc_state); |
3513 | } |
3514 | |
3515 | static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, |
3516 | struct intel_crtc_state *crtc_state, |
3517 | struct intel_shared_dpll *pll) |
3518 | { |
3519 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3520 | enum icl_port_dpll_id port_dpll_id; |
3521 | struct icl_port_dpll *port_dpll; |
3522 | bool_Bool pll_active; |
3523 | |
3524 | if (drm_WARN_ON(&i915->drm, !pll)({ int __ret = !!((!pll)); if (__ret) printf("%s %s: " "%s", dev_driver_string (((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll" ")" ); __builtin_expect(!!(__ret), 0); })) |
3525 | return; |
3526 | |
3527 | if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL) |
3528 | port_dpll_id = ICL_PORT_DPLL_DEFAULT; |
3529 | else |
3530 | port_dpll_id = ICL_PORT_DPLL_MG_PHY; |
3531 | |
3532 | port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; |
3533 | |
3534 | port_dpll->pll = pll; |
3535 | pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); |
3536 | drm_WARN_ON(&i915->drm, !pll_active)({ int __ret = !!((!pll_active)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&i915->drm))->dev), "", "drm_WARN_ON(" "!pll_active" ")"); __builtin_expect(!!(__ret), 0); }); |
3537 | |
3538 | icl_set_active_port_dpll(crtc_state, port_dpll_id); |
3539 | |
3540 | if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL) |
3541 | crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); |
3542 | else |
3543 | crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, |
3544 | &crtc_state->dpll_hw_state); |
3545 | } |
3546 | |
3547 | static void icl_ddi_tc_get_config(struct intel_encoder *encoder, |
3548 | struct intel_crtc_state *crtc_state) |
3549 | { |
3550 | icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder)); |
3551 | intel_ddi_get_config(encoder, crtc_state); |
3552 | } |
3553 | |
3554 | static void bxt_ddi_get_config(struct intel_encoder *encoder, |
3555 | struct intel_crtc_state *crtc_state) |
3556 | { |
3557 | intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder)); |
3558 | intel_ddi_get_config(encoder, crtc_state); |
3559 | } |
3560 | |
3561 | static void skl_ddi_get_config(struct intel_encoder *encoder, |
3562 | struct intel_crtc_state *crtc_state) |
3563 | { |
3564 | intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder)); |
3565 | intel_ddi_get_config(encoder, crtc_state); |
3566 | } |
3567 | |
3568 | void hsw_ddi_get_config(struct intel_encoder *encoder, |
3569 | struct intel_crtc_state *crtc_state) |
3570 | { |
3571 | intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder)); |
3572 | intel_ddi_get_config(encoder, crtc_state); |
3573 | } |
3574 | |
3575 | static void intel_ddi_sync_state(struct intel_encoder *encoder, |
3576 | const struct intel_crtc_state *crtc_state) |
3577 | { |
3578 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3579 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
3580 | |
3581 | if (intel_phy_is_tc(i915, phy)) |
3582 | intel_tc_port_sanitize_mode(enc_to_dig_port(encoder)); |
3583 | |
3584 | if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) |
3585 | intel_dp_sync_state(encoder, crtc_state); |
3586 | } |
3587 | |
3588 | static bool_Bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder, |
3589 | struct intel_crtc_state *crtc_state) |
3590 | { |
3591 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3592 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
3593 | bool_Bool fastset = true1; |
3594 | |
3595 | if (intel_phy_is_tc(i915, phy)) { |
3596 | drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n" , encoder->base.base.id, encoder->base.name) |
3597 | encoder->base.base.id, encoder->base.name)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n" , encoder->base.base.id, encoder->base.name); |
3598 | crtc_state->uapi.mode_changed = true1; |
3599 | fastset = false0; |
3600 | } |
3601 | |
3602 | if (intel_crtc_has_dp_encoder(crtc_state) && |
3603 | !intel_dp_initial_fastset_check(encoder, crtc_state)) |
3604 | fastset = false0; |
3605 | |
3606 | return fastset; |
3607 | } |
3608 | |
3609 | static enum intel_output_type |
3610 | intel_ddi_compute_output_type(struct intel_encoder *encoder, |
3611 | struct intel_crtc_state *crtc_state, |
3612 | struct drm_connector_state *conn_state) |
3613 | { |
3614 | switch (conn_state->connector->connector_type) { |
3615 | case DRM_MODE_CONNECTOR_HDMIA11: |
3616 | return INTEL_OUTPUT_HDMI; |
3617 | case DRM_MODE_CONNECTOR_eDP14: |
3618 | return INTEL_OUTPUT_EDP; |
3619 | case DRM_MODE_CONNECTOR_DisplayPort10: |
3620 | return INTEL_OUTPUT_DP; |
3621 | default: |
3622 | MISSING_CASE(conn_state->connector->connector_type)({ int __ret = !!(1); if (__ret) printf("Missing case (%s == %ld)\n" , "conn_state->connector->connector_type", (long)(conn_state ->connector->connector_type)); __builtin_expect(!!(__ret ), 0); }); |
3623 | return INTEL_OUTPUT_UNUSED; |
3624 | } |
3625 | } |
3626 | |
3627 | static int intel_ddi_compute_config(struct intel_encoder *encoder, |
3628 | struct intel_crtc_state *pipe_config, |
3629 | struct drm_connector_state *conn_state) |
3630 | { |
3631 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (pipe_config->uapi.crtc); (struct intel_crtc *)( (char * )__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
3632 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3633 | enum port port = encoder->port; |
3634 | int ret; |
3635 | |
3636 | if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP)(((&(dev_priv)->__runtime)->cpu_transcoder_mask & (1UL << (TRANSCODER_EDP))) != 0) && port == PORT_A) |
3637 | pipe_config->cpu_transcoder = TRANSCODER_EDP; |
3638 | |
3639 | if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) { |
3640 | ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state); |
3641 | } else { |
3642 | ret = intel_dp_compute_config(encoder, pipe_config, conn_state); |
3643 | } |
3644 | |
3645 | if (ret) |
3646 | return ret; |
3647 | |
3648 | if (IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL) && crtc->pipe == PIPE_A && |
3649 | pipe_config->cpu_transcoder == TRANSCODER_EDP) |
3650 | pipe_config->pch_pfit.force_thru = |
3651 | pipe_config->pch_pfit.enabled || |
3652 | pipe_config->crc_enabled; |
3653 | |
3654 | if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
3655 | pipe_config->lane_lat_optim_mask = |
3656 | bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); |
3657 | |
3658 | intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); |
3659 | |
3660 | return 0; |
3661 | } |
3662 | |
3663 | static bool_Bool mode_equal(const struct drm_display_mode *mode1, |
3664 | const struct drm_display_mode *mode2) |
3665 | { |
3666 | return drm_mode_match(mode1, mode2, |
3667 | DRM_MODE_MATCH_TIMINGS(1 << 0) | |
3668 | DRM_MODE_MATCH_FLAGS(1 << 2) | |
3669 | DRM_MODE_MATCH_3D_FLAGS(1 << 3)) && |
3670 | mode1->clock == mode2->clock; /* we want an exact match */ |
3671 | } |
3672 | |
3673 | static bool_Bool m_n_equal(const struct intel_link_m_n *m_n_1, |
3674 | const struct intel_link_m_n *m_n_2) |
3675 | { |
3676 | return m_n_1->tu == m_n_2->tu && |
3677 | m_n_1->data_m == m_n_2->data_m && |
3678 | m_n_1->data_n == m_n_2->data_n && |
3679 | m_n_1->link_m == m_n_2->link_m && |
3680 | m_n_1->link_n == m_n_2->link_n; |
3681 | } |
3682 | |
3683 | static bool_Bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1, |
3684 | const struct intel_crtc_state *crtc_state2) |
3685 | { |
3686 | return crtc_state1->hw.active && crtc_state2->hw.active && |
3687 | crtc_state1->output_types == crtc_state2->output_types && |
3688 | crtc_state1->output_format == crtc_state2->output_format && |
3689 | crtc_state1->lane_count == crtc_state2->lane_count && |
3690 | crtc_state1->port_clock == crtc_state2->port_clock && |
3691 | mode_equal(&crtc_state1->hw.adjusted_mode, |
3692 | &crtc_state2->hw.adjusted_mode) && |
3693 | m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); |
3694 | } |
3695 | |
3696 | static u8 |
3697 | intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state, |
3698 | int tile_group_id) |
3699 | { |
3700 | struct drm_connector *connector; |
3701 | const struct drm_connector_state *conn_state; |
3702 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); |
3703 | struct intel_atomic_state *state = |
3704 | to_intel_atomic_state(ref_crtc_state->uapi.state)({ const __typeof( ((struct intel_atomic_state *)0)->base ) *__mptr = (ref_crtc_state->uapi.state); (struct intel_atomic_state *)( (char *)__mptr - __builtin_offsetof(struct intel_atomic_state , base) );}); |
3705 | u8 transcoders = 0; |
3706 | int i; |
3707 | |
3708 | /* |
3709 | * We don't enable port sync on BDW due to missing w/as and |
3710 | * due to not having adjusted the modeset sequence appropriately. |
3711 | */ |
3712 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) < 9) |
3713 | return 0; |
3714 | |
3715 | if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP)) |
3716 | return 0; |
3717 | |
3718 | for_each_new_connector_in_state(&state->base, connector, conn_state, i)for ((i) = 0; (i) < (&state->base)->num_connector ; (i)++) if (!((&state->base)->connectors[i].ptr && ((connector) = (&state->base)->connectors[i].ptr, ( void)(connector) , (conn_state) = (&state->base)->connectors [i].new_state, (void)(conn_state) , 1))) {} else { |
3719 | struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (conn_state->crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
3720 | const struct intel_crtc_state *crtc_state; |
3721 | |
3722 | if (!crtc) |
3723 | continue; |
3724 | |
3725 | if (!connector->has_tile || |
3726 | connector->tile_group->id != |
3727 | tile_group_id) |
3728 | continue; |
3729 | crtc_state = intel_atomic_get_new_crtc_state(state, |
3730 | crtc); |
3731 | if (!crtcs_port_sync_compatible(ref_crtc_state, |
3732 | crtc_state)) |
3733 | continue; |
3734 | transcoders |= BIT(crtc_state->cpu_transcoder)(1UL << (crtc_state->cpu_transcoder)); |
3735 | } |
3736 | |
3737 | return transcoders; |
3738 | } |
3739 | |
3740 | static int intel_ddi_compute_config_late(struct intel_encoder *encoder, |
3741 | struct intel_crtc_state *crtc_state, |
3742 | struct drm_connector_state *conn_state) |
3743 | { |
3744 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3745 | struct drm_connector *connector = conn_state->connector; |
3746 | u8 port_sync_transcoders = 0; |
3747 | |
3748 | drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] [CRTC:%d:%s]" , encoder->base.base.id, encoder->base.name, crtc_state ->uapi.crtc->base.id, crtc_state->uapi.crtc->name ) |
3749 | encoder->base.base.id, encoder->base.name,__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] [CRTC:%d:%s]" , encoder->base.base.id, encoder->base.name, crtc_state ->uapi.crtc->base.id, crtc_state->uapi.crtc->name ) |
3750 | crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name)__drm_dev_dbg(((void *)0), (&i915->drm) ? (&i915-> drm)->dev : ((void *)0), DRM_UT_KMS, "[ENCODER:%d:%s] [CRTC:%d:%s]" , encoder->base.base.id, encoder->base.name, crtc_state ->uapi.crtc->base.id, crtc_state->uapi.crtc->name ); |
3751 | |
3752 | if (connector->has_tile) |
3753 | port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state, |
3754 | connector->tile_group->id); |
3755 | |
3756 | /* |
3757 | * EDP Transcoders cannot be ensalved |
3758 | * make them a master always when present |
3759 | */ |
3760 | if (port_sync_transcoders & BIT(TRANSCODER_EDP)(1UL << (TRANSCODER_EDP))) |
3761 | crtc_state->master_transcoder = TRANSCODER_EDP; |
3762 | else |
3763 | crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; |
3764 | |
3765 | if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { |
3766 | crtc_state->master_transcoder = INVALID_TRANSCODER; |
3767 | crtc_state->sync_mode_slaves_mask = |
3768 | port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder)(1UL << (crtc_state->cpu_transcoder)); |
3769 | } |
3770 | |
3771 | return 0; |
3772 | } |
3773 | |
3774 | static void intel_ddi_encoder_destroy(struct drm_encoder *encoder) |
3775 | { |
3776 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->dev); |
3777 | struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );})); |
3778 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); |
3779 | |
3780 | intel_dp_encoder_flush_work(encoder); |
3781 | if (intel_phy_is_tc(i915, phy)) |
3782 | intel_tc_port_flush_work(dig_port); |
3783 | intel_display_power_flush_work(i915); |
3784 | |
3785 | drm_encoder_cleanup(encoder); |
3786 | kfree(dig_port->hdcp_port_data.streams); |
3787 | kfree(dig_port); |
3788 | } |
3789 | |
3790 | static void intel_ddi_encoder_reset(struct drm_encoder *encoder) |
3791 | { |
3792 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->dev); |
3793 | struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );})); |
3794 | struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)({ const __typeof( ((struct intel_encoder *)0)->base ) *__mptr = (encoder); (struct intel_encoder *)( (char *)__mptr - __builtin_offsetof (struct intel_encoder, base) );})); |
3795 | enum phy phy = intel_port_to_phy(i915, dig_port->base.port); |
3796 | |
3797 | intel_dp->reset_link_params = true1; |
3798 | |
3799 | intel_pps_encoder_reset(intel_dp); |
3800 | |
3801 | if (intel_phy_is_tc(i915, phy)) |
3802 | intel_tc_port_init_mode(dig_port); |
3803 | } |
3804 | |
3805 | static const struct drm_encoder_funcs intel_ddi_funcs = { |
3806 | .reset = intel_ddi_encoder_reset, |
3807 | .destroy = intel_ddi_encoder_destroy, |
3808 | }; |
3809 | |
3810 | static struct intel_connector * |
3811 | intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) |
3812 | { |
3813 | struct intel_connector *connector; |
3814 | enum port port = dig_port->base.port; |
3815 | |
3816 | connector = intel_connector_alloc(); |
3817 | if (!connector) |
3818 | return NULL((void *)0); |
3819 | |
3820 | dig_port->dp.output_reg = DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }); |
3821 | dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; |
3822 | dig_port->dp.set_link_train = intel_ddi_set_link_train; |
3823 | dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; |
3824 | |
3825 | dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; |
3826 | dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; |
3827 | |
3828 | if (!intel_dp_init_connector(dig_port, connector)) { |
3829 | kfree(connector); |
3830 | return NULL((void *)0); |
3831 | } |
3832 | |
3833 | if (dig_port->base.type == INTEL_OUTPUT_EDP) { |
3834 | struct drm_device *dev = dig_port->base.base.dev; |
3835 | struct drm_privacy_screen *privacy_screen; |
3836 | |
3837 | privacy_screen = drm_privacy_screen_get(dev->dev, NULL((void *)0)); |
3838 | if (!IS_ERR(privacy_screen)) { |
3839 | drm_connector_attach_privacy_screen_provider(&connector->base, |
3840 | privacy_screen); |
3841 | } else if (PTR_ERR(privacy_screen) != -ENODEV19) { |
3842 | drm_warn(dev, "Error getting privacy-screen\n")printf("drm:pid%d:%s *WARNING* " "[drm] " "Error getting privacy-screen\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__); |
3843 | } |
3844 | } |
3845 | |
3846 | return connector; |
3847 | } |
3848 | |
3849 | static int modeset_pipe(struct drm_crtc *crtc, |
3850 | struct drm_modeset_acquire_ctx *ctx) |
3851 | { |
3852 | struct drm_atomic_state *state; |
3853 | struct drm_crtc_state *crtc_state; |
3854 | int ret; |
3855 | |
3856 | state = drm_atomic_state_alloc(crtc->dev); |
3857 | if (!state) |
3858 | return -ENOMEM12; |
3859 | |
3860 | state->acquire_ctx = ctx; |
3861 | |
3862 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
3863 | if (IS_ERR(crtc_state)) { |
3864 | ret = PTR_ERR(crtc_state); |
3865 | goto out; |
3866 | } |
3867 | |
3868 | crtc_state->connectors_changed = true1; |
3869 | |
3870 | ret = drm_atomic_commit(state); |
3871 | out: |
3872 | drm_atomic_state_put(state); |
3873 | |
3874 | return ret; |
3875 | } |
3876 | |
3877 | static int intel_hdmi_reset_link(struct intel_encoder *encoder, |
3878 | struct drm_modeset_acquire_ctx *ctx) |
3879 | { |
3880 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
3881 | struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); |
3882 | struct intel_connector *connector = hdmi->attached_connector; |
3883 | struct i2c_adapter *adapter = |
3884 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); |
3885 | struct drm_connector_state *conn_state; |
3886 | struct intel_crtc_state *crtc_state; |
3887 | struct intel_crtc *crtc; |
3888 | u8 config; |
3889 | int ret; |
3890 | |
3891 | if (!connector || connector->base.status != connector_status_connected) |
3892 | return 0; |
3893 | |
3894 | ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, |
3895 | ctx); |
3896 | if (ret) |
3897 | return ret; |
3898 | |
3899 | conn_state = connector->base.state; |
3900 | |
3901 | crtc = to_intel_crtc(conn_state->crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr = (conn_state->crtc); (struct intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc, base) );}); |
3902 | if (!crtc) |
3903 | return 0; |
3904 | |
3905 | ret = drm_modeset_lock(&crtc->base.mutex, ctx); |
3906 | if (ret) |
3907 | return ret; |
3908 | |
3909 | crtc_state = to_intel_crtc_state(crtc->base.state)({ const __typeof( ((struct intel_crtc_state *)0)->uapi ) * __mptr = (crtc->base.state); (struct intel_crtc_state *)( ( char *)__mptr - __builtin_offsetof(struct intel_crtc_state, uapi ) );}); |
3910 | |
3911 | drm_WARN_ON(&dev_priv->drm,({ int __ret = !!((!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)" ")"); __builtin_expect(!!(__ret), 0); }) |
3912 | !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))({ int __ret = !!((!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI ))); if (__ret) printf("%s %s: " "%s", dev_driver_string(((& dev_priv->drm))->dev), "", "drm_WARN_ON(" "!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)" ")"); __builtin_expect(!!(__ret), 0); }); |
3913 | |
3914 | if (!crtc_state->hw.active) |
3915 | return 0; |
3916 | |
3917 | if (!crtc_state->hdmi_high_tmds_clock_ratio && |
3918 | !crtc_state->hdmi_scrambling) |
3919 | return 0; |
3920 | |
3921 | if (conn_state->commit && |
3922 | !try_wait_for_completion(&conn_state->commit->hw_done)) |
3923 | return 0; |
3924 | |
3925 | ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG0x20, &config); |
3926 | if (ret < 0) { |
3927 | drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read TMDS config: %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret) |
3928 | ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "Failed to read TMDS config: %d\n" , ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->ps_pid, __func__ , ret); |
3929 | return 0; |
3930 | } |
3931 | |
3932 | if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40(1 << 1)) == |
3933 | crtc_state->hdmi_high_tmds_clock_ratio && |
3934 | !!(config & SCDC_SCRAMBLING_ENABLE(1 << 0)) == |
3935 | crtc_state->hdmi_scrambling) |
3936 | return 0; |
3937 | |
3938 | /* |
3939 | * HDMI 2.0 says that one should not send scrambled data |
3940 | * prior to configuring the sink scrambling, and that |
3941 | * TMDS clock/data transmission should be suspended when |
3942 | * changing the TMDS clock rate in the sink. So let's |
3943 | * just do a full modeset here, even though some sinks |
3944 | * would be perfectly happy if were to just reconfigure |
3945 | * the SCDC settings on the fly. |
3946 | */ |
3947 | return modeset_pipe(&crtc->base, ctx); |
3948 | } |
3949 | |
3950 | static enum intel_hotplug_state |
3951 | intel_ddi_hotplug(struct intel_encoder *encoder, |
3952 | struct intel_connector *connector) |
3953 | { |
3954 | struct drm_i915_privateinteldrm_softc *i915 = to_i915(encoder->base.dev); |
3955 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
3956 | struct intel_dp *intel_dp = &dig_port->dp; |
3957 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
3958 | bool_Bool is_tc = intel_phy_is_tc(i915, phy); |
3959 | struct drm_modeset_acquire_ctx ctx; |
3960 | enum intel_hotplug_state state; |
3961 | int ret; |
3962 | |
3963 | if (intel_dp->compliance.test_active && |
3964 | intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN(1 << 3)) { |
3965 | intel_dp_phy_test(encoder); |
3966 | /* just do the PHY test and nothing else */ |
3967 | return INTEL_HOTPLUG_UNCHANGED; |
3968 | } |
3969 | |
3970 | state = intel_encoder_hotplug(encoder, connector); |
3971 | |
3972 | drm_modeset_acquire_init(&ctx, 0); |
3973 | |
3974 | for (;;) { |
3975 | if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA11) |
3976 | ret = intel_hdmi_reset_link(encoder, &ctx); |
3977 | else |
3978 | ret = intel_dp_retrain_link(encoder, &ctx); |
3979 | |
3980 | if (ret == -EDEADLK11) { |
3981 | drm_modeset_backoff(&ctx); |
3982 | continue; |
3983 | } |
3984 | |
3985 | break; |
3986 | } |
3987 | |
3988 | drm_modeset_drop_locks(&ctx); |
3989 | drm_modeset_acquire_fini(&ctx); |
3990 | drm_WARN(encoder->base.dev, ret,({ int __ret = !!(ret); if (__ret) printf("%s %s: " "Acquiring modeset locks failed with %i\n" , dev_driver_string((encoder->base.dev)->dev), "", ret) ; __builtin_expect(!!(__ret), 0); }) |
3991 | "Acquiring modeset locks failed with %i\n", ret)({ int __ret = !!(ret); if (__ret) printf("%s %s: " "Acquiring modeset locks failed with %i\n" , dev_driver_string((encoder->base.dev)->dev), "", ret) ; __builtin_expect(!!(__ret), 0); }); |
3992 | |
3993 | /* |
3994 | * Unpowered type-c dongles can take some time to boot and be |
3995 | * responsible, so here giving some time to those dongles to power up |
3996 | * and then retrying the probe. |
3997 | * |
3998 | * On many platforms the HDMI live state signal is known to be |
3999 | * unreliable, so we can't use it to detect if a sink is connected or |
4000 | * not. Instead we detect if it's connected based on whether we can |
4001 | * read the EDID or not. That in turn has a problem during disconnect, |
4002 | * since the HPD interrupt may be raised before the DDC lines get |
4003 | * disconnected (due to how the required length of DDC vs. HPD |
4004 | * connector pins are specified) and so we'll still be able to get a |
4005 | * valid EDID. To solve this schedule another detection cycle if this |
4006 | * time around we didn't detect any change in the sink's connection |
4007 | * status. |
4008 | * |
4009 | * Type-c connectors which get their HPD signal deasserted then |
4010 | * reasserted, without unplugging/replugging the sink from the |
4011 | * connector, introduce a delay until the AUX channel communication |
4012 | * becomes functional. Retry the detection for 5 seconds on type-c |
4013 | * connectors to account for this delay. |
4014 | */ |
4015 | if (state == INTEL_HOTPLUG_UNCHANGED && |
4016 | connector->hotplug_retries < (is_tc ? 5 : 1) && |
4017 | !dig_port->dp.is_mst) |
4018 | state = INTEL_HOTPLUG_RETRY; |
4019 | |
4020 | return state; |
4021 | } |
4022 | |
4023 | static bool_Bool lpt_digital_port_connected(struct intel_encoder *encoder) |
4024 | { |
4025 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
4026 | u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; |
4027 | |
4028 | return intel_de_read(dev_priv, SDEISR((const i915_reg_t){ .reg = (0xc4000) })) & bit; |
4029 | } |
4030 | |
4031 | static bool_Bool hsw_digital_port_connected(struct intel_encoder *encoder) |
4032 | { |
4033 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
4034 | u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; |
4035 | |
4036 | return intel_de_read(dev_priv, DEISR((const i915_reg_t){ .reg = (0x44000) })) & bit; |
4037 | } |
4038 | |
4039 | static bool_Bool bdw_digital_port_connected(struct intel_encoder *encoder) |
4040 | { |
4041 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev); |
4042 | u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; |
4043 | |
4044 | return intel_de_read(dev_priv, GEN8_DE_PORT_ISR((const i915_reg_t){ .reg = (0x44440) })) & bit; |
4045 | } |
4046 | |
4047 | static struct intel_connector * |
4048 | intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port) |
4049 | { |
4050 | struct intel_connector *connector; |
4051 | enum port port = dig_port->base.port; |
4052 | |
4053 | connector = intel_connector_alloc(); |
4054 | if (!connector) |
4055 | return NULL((void *)0); |
4056 | |
4057 | dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) }); |
4058 | intel_hdmi_init_connector(dig_port, connector); |
4059 | |
4060 | return connector; |
4061 | } |
4062 | |
4063 | static bool_Bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port) |
4064 | { |
4065 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
4066 | |
4067 | if (dig_port->base.port != PORT_A) |
4068 | return false0; |
4069 | |
4070 | if (dig_port->saved_port_bits & DDI_A_4_LANES(1 << 4)) |
4071 | return false0; |
4072 | |
4073 | /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only |
4074 | * supported configuration |
4075 | */ |
4076 | if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
4077 | return true1; |
4078 | |
4079 | return false0; |
4080 | } |
4081 | |
4082 | static int |
4083 | intel_ddi_max_lanes(struct intel_digital_port *dig_port) |
4084 | { |
4085 | struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(dig_port->base.base.dev); |
4086 | enum port port = dig_port->base.port; |
4087 | int max_lanes = 4; |
4088 | |
4089 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) |
4090 | return max_lanes; |
4091 | |
4092 | if (port == PORT_A || port == PORT_E) { |
4093 | if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)((const i915_reg_t){ .reg = (((0x64000) + (PORT_A) * ((0x64100 ) - (0x64000)))) })) & DDI_A_4_LANES(1 << 4)) |
4094 | max_lanes = port == PORT_A ? 4 : 0; |
4095 | else |
4096 | /* Both A and E share 2 lanes */ |
4097 | max_lanes = 2; |
4098 | } |
4099 | |
4100 | /* |
4101 | * Some BIOS might fail to set this bit on port A if eDP |
4102 | * wasn't lit up at boot. Force this bit set when needed |
4103 | * so we use the proper lane count for our calculations. |
4104 | */ |
4105 | if (intel_ddi_a_force_4_lanes(dig_port)) { |
4106 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Forcing DDI_A_4_LANES for port A\n" ) |
4107 | "Forcing DDI_A_4_LANES for port A\n")__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "Forcing DDI_A_4_LANES for port A\n" ); |
4108 | dig_port->saved_port_bits |= DDI_A_4_LANES(1 << 4); |
4109 | max_lanes = 4; |
4110 | } |
4111 | |
4112 | return max_lanes; |
4113 | } |
4114 | |
4115 | static bool_Bool hti_uses_phy(struct drm_i915_privateinteldrm_softc *i915, enum phy phy) |
4116 | { |
4117 | return i915->hti_state & HDPORT_ENABLED((u32)((1UL << (0)) + 0)) && |
4118 | i915->hti_state & HDPORT_DDI_USED(phy)((u32)((1UL << (2 * (phy) + 1)) + 0)); |
4119 | } |
4120 | |
4121 | static enum hpd_pin xelpd_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, |
4122 | enum port port) |
4123 | { |
4124 | if (port >= PORT_D_XELPD) |
4125 | return HPD_PORT_D + port - PORT_D_XELPD; |
4126 | else if (port >= PORT_TC1) |
4127 | return HPD_PORT_TC1 + port - PORT_TC1; |
4128 | else |
4129 | return HPD_PORT_A + port - PORT_A; |
4130 | } |
4131 | |
4132 | static enum hpd_pin dg1_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, |
4133 | enum port port) |
4134 | { |
4135 | if (port >= PORT_TC1) |
4136 | return HPD_PORT_C + port - PORT_TC1; |
4137 | else |
4138 | return HPD_PORT_A + port - PORT_A; |
4139 | } |
4140 | |
4141 | static enum hpd_pin tgl_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, |
4142 | enum port port) |
4143 | { |
4144 | if (port >= PORT_TC1) |
4145 | return HPD_PORT_TC1 + port - PORT_TC1; |
4146 | else |
4147 | return HPD_PORT_A + port - PORT_A; |
4148 | } |
4149 | |
4150 | static enum hpd_pin rkl_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, |
4151 | enum port port) |
4152 | { |
4153 | if (HAS_PCH_TGP(dev_priv)(((dev_priv)->pch_type) == PCH_TGP)) |
4154 | return tgl_hpd_pin(dev_priv, port); |
4155 | |
4156 | if (port >= PORT_TC1) |
4157 | return HPD_PORT_C + port - PORT_TC1; |
4158 | else |
4159 | return HPD_PORT_A + port - PORT_A; |
4160 | } |
4161 | |
4162 | static enum hpd_pin icl_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, |
4163 | enum port port) |
4164 | { |
4165 | if (port >= PORT_C) |
4166 | return HPD_PORT_TC1 + port - PORT_C; |
4167 | else |
4168 | return HPD_PORT_A + port - PORT_A; |
4169 | } |
4170 | |
4171 | static enum hpd_pin ehl_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, |
4172 | enum port port) |
4173 | { |
4174 | if (port == PORT_D) |
4175 | return HPD_PORT_A; |
4176 | |
4177 | if (HAS_PCH_TGP(dev_priv)(((dev_priv)->pch_type) == PCH_TGP)) |
4178 | return icl_hpd_pin(dev_priv, port); |
4179 | |
4180 | return HPD_PORT_A + port - PORT_A; |
4181 | } |
4182 | |
4183 | static enum hpd_pin skl_hpd_pin(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port) |
4184 | { |
4185 | if (HAS_PCH_TGP(dev_priv)(((dev_priv)->pch_type) == PCH_TGP)) |
4186 | return icl_hpd_pin(dev_priv, port); |
4187 | |
4188 | return HPD_PORT_A + port - PORT_A; |
4189 | } |
4190 | |
4191 | static bool_Bool intel_ddi_is_tc(struct drm_i915_privateinteldrm_softc *i915, enum port port) |
4192 | { |
4193 | if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 12) |
4194 | return port >= PORT_TC1; |
4195 | else if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 11) |
4196 | return port >= PORT_C; |
4197 | else |
4198 | return false0; |
4199 | } |
4200 | |
4201 | static void intel_ddi_encoder_suspend(struct intel_encoder *encoder) |
4202 | { |
4203 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4204 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
4205 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4206 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
4207 | |
4208 | intel_dp_encoder_suspend(encoder); |
4209 | |
4210 | if (!intel_phy_is_tc(i915, phy)) |
4211 | return; |
4212 | |
4213 | intel_tc_port_flush_work(dig_port); |
4214 | } |
4215 | |
4216 | static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder) |
4217 | { |
4218 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4219 | struct drm_i915_privateinteldrm_softc *i915 = dp_to_i915(intel_dp)to_i915(dp_to_dig_port(intel_dp)->base.base.dev); |
4220 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
4221 | enum phy phy = intel_port_to_phy(i915, encoder->port); |
4222 | |
4223 | intel_dp_encoder_shutdown(encoder); |
4224 | intel_hdmi_encoder_shutdown(encoder); |
4225 | |
4226 | if (!intel_phy_is_tc(i915, phy)) |
4227 | return; |
4228 | |
4229 | intel_tc_port_flush_work(dig_port); |
4230 | } |
4231 | |
4232 | #define port_tc_name(port)((port) - PORT_TC1 + '1') ((port) - PORT_TC1 + '1') |
4233 | #define tc_port_name(tc_port)((tc_port) - TC_PORT_1 + '1') ((tc_port) - TC_PORT_1 + '1') |
4234 | |
4235 | void intel_ddi_init(struct drm_i915_privateinteldrm_softc *dev_priv, enum port port) |
4236 | { |
4237 | struct intel_digital_port *dig_port; |
4238 | struct intel_encoder *encoder; |
4239 | const struct intel_bios_encoder_data *devdata; |
4240 | bool_Bool init_hdmi, init_dp; |
4241 | enum phy phy = intel_port_to_phy(dev_priv, port); |
4242 | |
4243 | /* |
4244 | * On platforms with HTI (aka HDPORT), if it's enabled at boot it may |
4245 | * have taken over some of the PHYs and made them unavailable to the |
4246 | * driver. In that case we should skip initializing the corresponding |
4247 | * outputs. |
4248 | */ |
4249 | if (hti_uses_phy(dev_priv, phy)) { |
4250 | drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PORT %c / PHY %c reserved by HTI\n" , ((port) + 'A'), ((phy) + 'A')) |
4251 | port_name(port), phy_name(phy))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "PORT %c / PHY %c reserved by HTI\n" , ((port) + 'A'), ((phy) + 'A')); |
4252 | return; |
4253 | } |
4254 | |
4255 | devdata = intel_bios_encoder_data_lookup(dev_priv, port); |
4256 | if (!devdata) { |
4257 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c is not present\n" , ((port) + 'A')) |
4258 | "VBT says port %c is not present\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c is not present\n" , ((port) + 'A')) |
4259 | port_name(port))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c is not present\n" , ((port) + 'A')); |
4260 | return; |
4261 | } |
4262 | |
4263 | init_hdmi = intel_bios_encoder_supports_dvi(devdata) || |
4264 | intel_bios_encoder_supports_hdmi(devdata); |
4265 | init_dp = intel_bios_encoder_supports_dp(devdata); |
4266 | |
4267 | if (intel_bios_is_lspcon_present(dev_priv, port)) { |
4268 | /* |
4269 | * Lspcon device needs to be driven with DP connector |
4270 | * with special detection sequence. So make sure DP |
4271 | * is initialized before lspcon. |
4272 | */ |
4273 | init_dp = true1; |
4274 | init_hdmi = false0; |
4275 | drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c has lspcon\n" , ((port) + 'A')) |
4276 | port_name(port))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c has lspcon\n" , ((port) + 'A')); |
4277 | } |
4278 | |
4279 | if (!init_dp && !init_hdmi) { |
4280 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n" , ((port) + 'A')) |
4281 | "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n" , ((port) + 'A')) |
4282 | port_name(port))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n" , ((port) + 'A')); |
4283 | return; |
4284 | } |
4285 | |
4286 | if (intel_phy_is_snps(dev_priv, phy) && |
4287 | dev_priv->snps_phy_failed_calibration & BIT(phy)(1UL << (phy))) { |
4288 | drm_dbg_kms(&dev_priv->drm,__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "SNPS PHY %c failed to calibrate, proceeding anyway\n" , ((phy) + 'A')) |
4289 | "SNPS PHY %c failed to calibrate, proceeding anyway\n",__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "SNPS PHY %c failed to calibrate, proceeding anyway\n" , ((phy) + 'A')) |
4290 | phy_name(phy))__drm_dev_dbg(((void *)0), (&dev_priv->drm) ? (&dev_priv ->drm)->dev : ((void *)0), DRM_UT_KMS, "SNPS PHY %c failed to calibrate, proceeding anyway\n" , ((phy) + 'A')); |
4291 | } |
4292 | |
4293 | dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL(0x0001 | 0x0004)); |
4294 | if (!dig_port) |
4295 | return; |
4296 | |
4297 | encoder = &dig_port->base; |
4298 | encoder->devdata = devdata; |
4299 | |
4300 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 13 && port >= PORT_D_XELPD) { |
4301 | drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, |
4302 | DRM_MODE_ENCODER_TMDS2, |
4303 | "DDI %c/PHY %c", |
4304 | port_name(port - PORT_D_XELPD + PORT_D)((port - PORT_D_XELPD + PORT_D) + 'A'), |
4305 | phy_name(phy)((phy) + 'A')); |
4306 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
4307 | enum tc_port tc_port = intel_port_to_tc(dev_priv, port); |
4308 | |
4309 | drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, |
4310 | DRM_MODE_ENCODER_TMDS2, |
4311 | "DDI %s%c/PHY %s%c", |
4312 | port >= PORT_TC1 ? "TC" : "", |
4313 | port >= PORT_TC1 ? port_tc_name(port)((port) - PORT_TC1 + '1') : port_name(port)((port) + 'A'), |
4314 | tc_port != TC_PORT_NONE ? "TC" : "", |
4315 | tc_port != TC_PORT_NONE ? tc_port_name(tc_port)((tc_port) - TC_PORT_1 + '1') : phy_name(phy)((phy) + 'A')); |
4316 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
4317 | enum tc_port tc_port = intel_port_to_tc(dev_priv, port); |
4318 | |
4319 | drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, |
4320 | DRM_MODE_ENCODER_TMDS2, |
4321 | "DDI %c%s/PHY %s%c", |
4322 | port_name(port)((port) + 'A'), |
4323 | port >= PORT_C ? " (TC)" : "", |
4324 | tc_port != TC_PORT_NONE ? "TC" : "", |
4325 | tc_port != TC_PORT_NONE ? tc_port_name(tc_port)((tc_port) - TC_PORT_1 + '1') : phy_name(phy)((phy) + 'A')); |
4326 | } else { |
4327 | drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, |
4328 | DRM_MODE_ENCODER_TMDS2, |
4329 | "DDI %c/PHY %c", port_name(port)((port) + 'A'), phy_name(phy)((phy) + 'A')); |
4330 | } |
4331 | |
4332 | rw_init(&dig_port->hdcp_mutex, "dhdcp")_rw_init_flags(&dig_port->hdcp_mutex, "dhdcp", 0, ((void *)0)); |
4333 | dig_port->num_hdcp_streams = 0; |
4334 | |
4335 | encoder->hotplug = intel_ddi_hotplug; |
4336 | encoder->compute_output_type = intel_ddi_compute_output_type; |
4337 | encoder->compute_config = intel_ddi_compute_config; |
4338 | encoder->compute_config_late = intel_ddi_compute_config_late; |
4339 | encoder->enable = intel_enable_ddi; |
4340 | encoder->pre_pll_enable = intel_ddi_pre_pll_enable; |
4341 | encoder->pre_enable = intel_ddi_pre_enable; |
4342 | encoder->disable = intel_disable_ddi; |
4343 | encoder->post_disable = intel_ddi_post_disable; |
4344 | encoder->update_pipe = intel_ddi_update_pipe; |
4345 | encoder->get_hw_state = intel_ddi_get_hw_state; |
4346 | encoder->sync_state = intel_ddi_sync_state; |
4347 | encoder->initial_fastset_check = intel_ddi_initial_fastset_check; |
4348 | encoder->suspend = intel_ddi_encoder_suspend; |
4349 | encoder->shutdown = intel_ddi_encoder_shutdown; |
4350 | encoder->get_power_domains = intel_ddi_get_power_domains; |
4351 | |
4352 | encoder->type = INTEL_OUTPUT_DDI; |
4353 | encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); |
4354 | encoder->port = port; |
4355 | encoder->cloneable = 0; |
4356 | encoder->pipe_mask = ~0; |
4357 | |
4358 | if (IS_DG2(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG2)) { |
4359 | encoder->enable_clock = intel_mpllb_enable; |
4360 | encoder->disable_clock = intel_mpllb_disable; |
4361 | encoder->get_config = dg2_ddi_get_config; |
4362 | } else if (IS_ALDERLAKE_S(dev_priv)IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)) { |
4363 | encoder->enable_clock = adls_ddi_enable_clock; |
4364 | encoder->disable_clock = adls_ddi_disable_clock; |
4365 | encoder->is_clock_enabled = adls_ddi_is_clock_enabled; |
4366 | encoder->get_config = adls_ddi_get_config; |
4367 | } else if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) { |
4368 | encoder->enable_clock = rkl_ddi_enable_clock; |
4369 | encoder->disable_clock = rkl_ddi_disable_clock; |
4370 | encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; |
4371 | encoder->get_config = rkl_ddi_get_config; |
4372 | } else if (IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)) { |
4373 | encoder->enable_clock = dg1_ddi_enable_clock; |
4374 | encoder->disable_clock = dg1_ddi_disable_clock; |
4375 | encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; |
4376 | encoder->get_config = dg1_ddi_get_config; |
4377 | } else if (IS_JSL_EHL(dev_priv)(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || IS_PLATFORM(dev_priv , INTEL_ELKHARTLAKE))) { |
4378 | if (intel_ddi_is_tc(dev_priv, port)) { |
4379 | encoder->enable_clock = jsl_ddi_tc_enable_clock; |
4380 | encoder->disable_clock = jsl_ddi_tc_disable_clock; |
4381 | encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; |
4382 | encoder->get_config = icl_ddi_combo_get_config; |
4383 | } else { |
4384 | encoder->enable_clock = icl_ddi_combo_enable_clock; |
4385 | encoder->disable_clock = icl_ddi_combo_disable_clock; |
4386 | encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; |
4387 | encoder->get_config = icl_ddi_combo_get_config; |
4388 | } |
4389 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
4390 | if (intel_ddi_is_tc(dev_priv, port)) { |
4391 | encoder->enable_clock = icl_ddi_tc_enable_clock; |
4392 | encoder->disable_clock = icl_ddi_tc_disable_clock; |
4393 | encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; |
4394 | encoder->get_config = icl_ddi_tc_get_config; |
4395 | } else { |
4396 | encoder->enable_clock = icl_ddi_combo_enable_clock; |
4397 | encoder->disable_clock = icl_ddi_combo_disable_clock; |
4398 | encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; |
4399 | encoder->get_config = icl_ddi_combo_get_config; |
4400 | } |
4401 | } else if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) { |
4402 | /* BXT/GLK have fixed PLL->port mapping */ |
4403 | encoder->get_config = bxt_ddi_get_config; |
4404 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9) { |
4405 | encoder->enable_clock = skl_ddi_enable_clock; |
4406 | encoder->disable_clock = skl_ddi_disable_clock; |
4407 | encoder->is_clock_enabled = skl_ddi_is_clock_enabled; |
4408 | encoder->get_config = skl_ddi_get_config; |
4409 | } else if (IS_BROADWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROADWELL) || IS_HASWELL(dev_priv)IS_PLATFORM(dev_priv, INTEL_HASWELL)) { |
4410 | encoder->enable_clock = hsw_ddi_enable_clock; |
4411 | encoder->disable_clock = hsw_ddi_disable_clock; |
4412 | encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; |
4413 | encoder->get_config = hsw_ddi_get_config; |
4414 | } |
4415 | |
4416 | if (IS_DG2(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG2)) { |
4417 | encoder->set_signal_levels = intel_snps_phy_set_signal_levels; |
4418 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) { |
4419 | if (intel_phy_is_combo(dev_priv, phy)) |
4420 | encoder->set_signal_levels = icl_combo_phy_set_signal_levels; |
4421 | else |
4422 | encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; |
4423 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
4424 | if (intel_phy_is_combo(dev_priv, phy)) |
4425 | encoder->set_signal_levels = icl_combo_phy_set_signal_levels; |
4426 | else |
4427 | encoder->set_signal_levels = icl_mg_phy_set_signal_levels; |
4428 | } else if (IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) { |
4429 | encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels; |
4430 | } else { |
4431 | encoder->set_signal_levels = hsw_set_signal_levels; |
4432 | } |
4433 | |
4434 | intel_ddi_buf_trans_init(encoder); |
4435 | |
4436 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 13) |
4437 | encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); |
4438 | else if (IS_DG1(dev_priv)IS_PLATFORM(dev_priv, INTEL_DG1)) |
4439 | encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); |
4440 | else if (IS_ROCKETLAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)) |
4441 | encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); |
4442 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 12) |
4443 | encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); |
4444 | else if (IS_JSL_EHL(dev_priv)(IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || IS_PLATFORM(dev_priv , INTEL_ELKHARTLAKE))) |
4445 | encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); |
4446 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 11) |
4447 | encoder->hpd_pin = icl_hpd_pin(dev_priv, port); |
4448 | else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) == 9 && !IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
4449 | encoder->hpd_pin = skl_hpd_pin(dev_priv, port); |
4450 | else |
4451 | encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
4452 | |
4453 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) |
4454 | dig_port->saved_port_bits = |
4455 | intel_de_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })) |
4456 | & DDI_BUF_PORT_REVERSAL(1 << 16); |
4457 | else |
4458 | dig_port->saved_port_bits = |
4459 | intel_de_read(dev_priv, DDI_BUF_CTL(port)((const i915_reg_t){ .reg = (((0x64000) + (port) * ((0x64100) - (0x64000)))) })) |
4460 | & (DDI_BUF_PORT_REVERSAL(1 << 16) | DDI_A_4_LANES(1 << 4)); |
4461 | |
4462 | if (intel_bios_is_lane_reversal_needed(dev_priv, port)) |
4463 | dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL(1 << 16); |
4464 | |
4465 | dig_port->dp.output_reg = INVALID_MMIO_REG((const i915_reg_t){ .reg = (0) }); |
4466 | dig_port->max_lanes = intel_ddi_max_lanes(dig_port); |
4467 | dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
4468 | |
4469 | if (intel_phy_is_tc(dev_priv, phy)) { |
4470 | bool_Bool is_legacy = |
4471 | !intel_bios_encoder_supports_typec_usb(devdata) && |
4472 | !intel_bios_encoder_supports_tbt(devdata); |
4473 | |
4474 | intel_tc_port_init(dig_port, is_legacy); |
4475 | |
4476 | encoder->update_prepare = intel_ddi_update_prepare; |
4477 | encoder->update_complete = intel_ddi_update_complete; |
4478 | } |
4479 | |
4480 | drm_WARN_ON(&dev_priv->drm, port > PORT_I)({ int __ret = !!((port > PORT_I)); if (__ret) printf("%s %s: " "%s", dev_driver_string(((&dev_priv->drm))->dev), "" , "drm_WARN_ON(" "port > PORT_I" ")"); __builtin_expect(!! (__ret), 0); }); |
4481 | dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); |
4482 | |
4483 | if (init_dp) { |
4484 | if (!intel_ddi_init_dp_connector(dig_port)) |
4485 | goto err; |
4486 | |
4487 | dig_port->hpd_pulse = intel_dp_hpd_pulse; |
4488 | |
4489 | if (dig_port->dp.mso_link_count) |
4490 | encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); |
4491 | } |
4492 | |
4493 | /* In theory we don't need the encoder->type check, but leave it just in |
4494 | * case we have some really bad VBTs... */ |
4495 | if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
4496 | if (!intel_ddi_init_hdmi_connector(dig_port)) |
4497 | goto err; |
4498 | } |
4499 | |
4500 | if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 11) { |
4501 | if (intel_phy_is_tc(dev_priv, phy)) |
4502 | dig_port->connected = intel_tc_port_connected; |
4503 | else |
4504 | dig_port->connected = lpt_digital_port_connected; |
4505 | } else if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 8) { |
4506 | if (port == PORT_A || IS_GEMINILAKE(dev_priv)IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) || |
4507 | IS_BROXTON(dev_priv)IS_PLATFORM(dev_priv, INTEL_BROXTON)) |
4508 | dig_port->connected = bdw_digital_port_connected; |
4509 | else |
4510 | dig_port->connected = lpt_digital_port_connected; |
4511 | } else { |
4512 | if (port == PORT_A) |
4513 | dig_port->connected = hsw_digital_port_connected; |
4514 | else |
4515 | dig_port->connected = lpt_digital_port_connected; |
4516 | } |
4517 | |
4518 | intel_infoframe_init(dig_port); |
4519 | |
4520 | return; |
4521 | |
4522 | err: |
4523 | drm_encoder_cleanup(&encoder->base); |
4524 | kfree(dig_port); |
4525 | } |