/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu

Bug Summary

File:	dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
Warning:	line 1895, column 19 Dereference of null pointer
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name amdgpu_dm.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c
1/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/

26/* The caprices of the preprocessor require that this be declared right here */
27#define CREATE_TRACE_POINTS

29#include "dm_services_types.h"
30#include "dc.h"
31#include "dc_link_dp.h"
32#include "link_enc_cfg.h"
33#include "dc/inc/core_types.h"
34#include "dal_asic_id.h"
35#include "dmub/dmub_srv.h"
36#include "dc/inc/hw/dmcu.h"
37#include "dc/inc/hw/abm.h"
38#include "dc/dc_dmub_srv.h"
39#include "dc/dc_edid_parser.h"
40#include "dc/dc_stat.h"
41#include "amdgpu_dm_trace.h"
42#include "dc/inc/dc_link_ddc.h"
43#include "dpcd_defs.h"
44#include "dc/inc/link_dpcd.h"
45#include "link_service_types.h"

47#include "vid.h"
48#include "amdgpu.h"
49#include "amdgpu_display.h"
50#include "amdgpu_ucode.h"
51#include "atom.h"
52#include "amdgpu_dm.h"
53#include "amdgpu_dm_plane.h"
54#include "amdgpu_dm_crtc.h"
55#ifdef CONFIG_DRM_AMD_DC_HDCP
56#include "amdgpu_dm_hdcp.h"
57#include <drm/display/drm_hdcp_helper.h>
58#endif
59#include "amdgpu_pm.h"
60#include "amdgpu_atombios.h"

62#include "amd_shared.h"
63#include "amdgpu_dm_irq.h"
64#include "dm_helpers.h"
65#include "amdgpu_dm_mst_types.h"
66#if defined(CONFIG_DEBUG_FS)
67#include "amdgpu_dm_debugfs.h"
68#endif
69#include "amdgpu_dm_psr.h"

71#include "ivsrcid/ivsrcid_vislands30.h"

73#include "i2caux_interface.h"
74#include <linux/module.h>
75#include <linux/moduleparam.h>
76#include <linux/types.h>
77#include <linux/pm_runtime.h>
78#include <linux/pci.h>
79#include <linux/firmware.h>
80#include <linux/component.h>
81#include <linux/dmi.h>

83#include <drm/display/drm_dp_mst_helper.h>
84#include <drm/display/drm_hdmi_helper.h>
85#include <drm/drm_atomic.h>
86#include <drm/drm_atomic_uapi.h>
87#include <drm/drm_atomic_helper.h>
88#include <drm/drm_blend.h>
89#include <drm/drm_fourcc.h>
90#include <drm/drm_edid.h>
91#include <drm/drm_vblank.h>
92#include <drm/drm_audio_component.h>
93#include <drm/drm_gem_atomic_helper.h>
94#include <drm/drm_plane_helper.h>

96#include <acpi/video.h>

98#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"

100#include "dcn/dcn_1_0_offset.h"
101#include "dcn/dcn_1_0_sh_mask.h"
102#include "soc15_hw_ip.h"
103#include "soc15_common.h"
104#include "vega10_ip_offset.h"

106#include "gc/gc_11_0_0_offset.h"
107#include "gc/gc_11_0_0_sh_mask.h"

109#include "modules/inc/mod_freesync.h"
110#include "modules/power/power_helpers.h"
111#include "modules/inc/mod_info_packet.h"

113#define FIRMWARE_RENOIR_DMUB"amdgpu/renoir_dmcub.bin" "amdgpu/renoir_dmcub.bin"
114MODULE_FIRMWARE(FIRMWARE_RENOIR_DMUB);
115#define FIRMWARE_SIENNA_CICHLID_DMUB"amdgpu/sienna_cichlid_dmcub.bin" "amdgpu/sienna_cichlid_dmcub.bin"
116MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID_DMUB);
117#define FIRMWARE_NAVY_FLOUNDER_DMUB"amdgpu/navy_flounder_dmcub.bin" "amdgpu/navy_flounder_dmcub.bin"
118MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER_DMUB);
119#define FIRMWARE_GREEN_SARDINE_DMUB"amdgpu/green_sardine_dmcub.bin" "amdgpu/green_sardine_dmcub.bin"
120MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE_DMUB);
121#define FIRMWARE_VANGOGH_DMUB"amdgpu/vangogh_dmcub.bin" "amdgpu/vangogh_dmcub.bin"
122MODULE_FIRMWARE(FIRMWARE_VANGOGH_DMUB);
123#define FIRMWARE_DIMGREY_CAVEFISH_DMUB"amdgpu/dimgrey_cavefish_dmcub.bin" "amdgpu/dimgrey_cavefish_dmcub.bin"
124MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH_DMUB);
125#define FIRMWARE_BEIGE_GOBY_DMUB"amdgpu/beige_goby_dmcub.bin" "amdgpu/beige_goby_dmcub.bin"
126MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY_DMUB);
127#define FIRMWARE_YELLOW_CARP_DMUB"amdgpu/yellow_carp_dmcub.bin" "amdgpu/yellow_carp_dmcub.bin"
128MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP_DMUB);
129#define FIRMWARE_DCN_314_DMUB"amdgpu/dcn_3_1_4_dmcub.bin" "amdgpu/dcn_3_1_4_dmcub.bin"
130MODULE_FIRMWARE(FIRMWARE_DCN_314_DMUB);
131#define FIRMWARE_DCN_315_DMUB"amdgpu/dcn_3_1_5_dmcub.bin" "amdgpu/dcn_3_1_5_dmcub.bin"
132MODULE_FIRMWARE(FIRMWARE_DCN_315_DMUB);
133#define FIRMWARE_DCN316_DMUB"amdgpu/dcn_3_1_6_dmcub.bin" "amdgpu/dcn_3_1_6_dmcub.bin"
134MODULE_FIRMWARE(FIRMWARE_DCN316_DMUB);

136#define FIRMWARE_DCN_V3_2_0_DMCUB"amdgpu/dcn_3_2_0_dmcub.bin" "amdgpu/dcn_3_2_0_dmcub.bin"
137MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_0_DMCUB);
138#define FIRMWARE_DCN_V3_2_1_DMCUB"amdgpu/dcn_3_2_1_dmcub.bin" "amdgpu/dcn_3_2_1_dmcub.bin"
139MODULE_FIRMWARE(FIRMWARE_DCN_V3_2_1_DMCUB);

141#define FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin"		"amdgpu/raven_dmcu.bin"
142MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);

144#define FIRMWARE_NAVI12_DMCU"amdgpu/navi12_dmcu.bin"            "amdgpu/navi12_dmcu.bin"
145MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);

147/* Number of bytes in PSP header for firmware. */
148#define PSP_HEADER_BYTES0x100 0x100

150/* Number of bytes in PSP footer for firmware. */
151#define PSP_FOOTER_BYTES0x100 0x100

153/**
* DOC: overview
*
* The AMDgpu display manager, **amdgpu_dm** (or even simpler,
* **dm**) sits between DRM and DC. It acts as a liaison, converting DRM
* requests into DC requests, and DC responses into DRM responses.
*
* The root control structure is &struct amdgpu_display_manager.
*/

163/* basic init/fini API */
164static int amdgpu_dm_init(struct amdgpu_device *adev);
165static void amdgpu_dm_fini(struct amdgpu_device *adev);
166static bool_Bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector);

168static enum drm_mode_subconnector get_subconnector_type(struct dc_link *link)
169{
switch (link->dpcd_caps.dongle_type) {
case DISPLAY_DONGLE_NONE:
return DRM_MODE_SUBCONNECTOR_Native;
case DISPLAY_DONGLE_DP_VGA_CONVERTER:
return DRM_MODE_SUBCONNECTOR_VGA;
case DISPLAY_DONGLE_DP_DVI_CONVERTER:
case DISPLAY_DONGLE_DP_DVI_DONGLE:
return DRM_MODE_SUBCONNECTOR_DVID;
case DISPLAY_DONGLE_DP_HDMI_CONVERTER:
case DISPLAY_DONGLE_DP_HDMI_DONGLE:
return DRM_MODE_SUBCONNECTOR_HDMIA;
case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
default:
return DRM_MODE_SUBCONNECTOR_Unknown;
}
185}

187static void update_subconnector_property(struct amdgpu_dm_connector *aconnector)
188{
struct dc_link *link = aconnector->dc_link;
struct drm_connector *connector = &aconnector->base;
enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;

if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort10)
return;

if (aconnector->dc_sink)
subconnector = get_subconnector_type(link);

drm_object_property_set_value(&connector->base,
	connector->dev->mode_config.dp_subconnector_property,
	subconnector);
202}

204/*
* initializes drm_device display related structures, based on the information
* provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
* drm_encoder, drm_mode_config
*
* Returns 0 on success
*/
211static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
212/* removes and deallocates the drm structures, created by the above function */
213static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);

215static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
		    struct amdgpu_dm_connector *amdgpu_dm_connector,
		    u32 link_index,
		    struct amdgpu_encoder *amdgpu_encoder);
219static int amdgpu_dm_encoder_init(struct drm_device *dev,
		  struct amdgpu_encoder *aencoder,
		  uint32_t link_index);

223static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);

225static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);

227static int amdgpu_dm_atomic_check(struct drm_device *dev,
		  struct drm_atomic_state *state);

230static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector);
231static void handle_hpd_rx_irq(void *param);

233static bool_Bool
234is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
		 struct drm_crtc_state *new_crtc_state);
236/*
* dm_vblank_get_counter
*
* @brief
* Get counter for number of vertical blanks
*
* @param
* struct amdgpu_device *adev - [in] desired amdgpu device
* int disp_idx - [in] which CRTC to get the counter from
*
* @return
* Counter for vertical blanks
*/
249static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
250{
if (crtc >= adev->mode_info.num_crtc)
return 0;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];

if (acrtc->dm_irq_params.stream == NULL((void *)0)) {
	DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc)
		  crtc)__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc);
	return 0;
}

return dc_stream_get_vblank_counter(acrtc->dm_irq_params.stream);
}
264}

266static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
		  u32 *vbl, u32 *position)
268{
u32 v_blank_start, v_blank_end, h_position, v_position;

if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
return -EINVAL22;
else {
struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];

if (acrtc->dm_irq_params.stream ==  NULL((void *)0)) {
	DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc)
		  crtc)__drm_err("dc_stream_state is NULL for crtc '%d'!\n", crtc);
	return 0;
}

/*
 * TODO rework base driver to use values directly.
 * for now parse it back into reg-format
 */
dc_stream_get_scanoutpos(acrtc->dm_irq_params.stream,
			 &v_blank_start,
			 &v_blank_end,
			 &h_position,
			 &v_position);

*position = v_position | (h_position << 16);
*vbl = v_blank_start | (v_blank_end << 16);
}

return 0;
297}

299static bool_Bool dm_is_idle(void *handle)
300{
/* XXX todo */
return true1;
303}

305static int dm_wait_for_idle(void *handle)
306{
/* XXX todo */
return 0;
309}

311static bool_Bool dm_check_soft_reset(void *handle)
312{
return false0;
314}

316static int dm_soft_reset(void *handle)
317{
/* XXX todo */
return 0;
320}

322static struct amdgpu_crtc *
323get_crtc_by_otg_inst(struct amdgpu_device *adev,
     int otg_inst)
325{
struct drm_device *dev = adev_to_drm(adev);
struct drm_crtc *crtc;
struct amdgpu_crtc *amdgpu_crtc;

if (WARN_ON(otg_inst == -1)({ int __ret = !!(otg_inst == -1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "otg_inst == -1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 330); __builtin_expect(!!(__ret), 0); }))
return adev->mode_info.crtcs[0];

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&dev->mode_config.crtc_list)->next);
 (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&dev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
amdgpu_crtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

if (amdgpu_crtc->otg_inst == otg_inst)
	return amdgpu_crtc;
}

return NULL((void *)0);
341}

343static inline bool_Bool is_dc_timing_adjust_needed(struct dm_crtc_state *old_state,
			      struct dm_crtc_state *new_state)
345{
if (new_state->freesync_config.state ==  VRR_STATE_ACTIVE_FIXED)
return true1;
else if (amdgpu_dm_vrr_active(old_state) != amdgpu_dm_vrr_active(new_state))
return true1;
else
return false0;
352}

354static inline void reverse_planes_order(struct dc_surface_update *array_of_surface_update,
			int planes_count)
356{
int i, j;
struct dc_surface_update surface_updates_temp;

for (i = 0, j = planes_count - 1; i < j; i++, j--) {
surface_updates_temp = array_of_surface_update[i];
array_of_surface_update[i] = array_of_surface_update[j];
array_of_surface_update[j] = surface_updates_temp;
}
365}

367/**
* update_planes_and_stream_adapter() - Send planes to be updated in DC
*
* DC has a generic way to update planes and stream via
* dc_update_planes_and_stream function; however, DM might need some
* adjustments and preparation before calling it. This function is a wrapper
* for the dc_update_planes_and_stream that does any required configuration
* before passing control to DC.
*/
376static inline bool_Bool update_planes_and_stream_adapter(struct dc *dc,
				    int update_type,
				    int planes_count,
				    struct dc_stream_state *stream,
				    struct dc_stream_update *stream_update,
				    struct dc_surface_update *array_of_surface_update)
382{
reverse_planes_order(array_of_surface_update, planes_count);

/*
* Previous frame finished and HW is ready for optimization.
*/
if (update_type == UPDATE_TYPE_FAST)
dc_post_update_surfaces_to_stream(dc);

return dc_update_planes_and_stream(dc,
			   array_of_surface_update,
			   planes_count,
			   stream,
			   stream_update);
396}

398/**
* dm_pflip_high_irq() - Handle pageflip interrupt
* @interrupt_params: ignored
*
* Handles the pageflip interrupt by notifying all interested parties
* that the pageflip has been completed.
*/
405static void dm_pflip_high_irq(void *interrupt_params)
406{
struct amdgpu_crtc *amdgpu_crtc;
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
unsigned long flags;
struct drm_pending_vblank_event *e;
u32 vpos, hpos, v_blank_start, v_blank_end;
bool_Bool vrr_active;

amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);

/* IRQ could occur when in initial stage */
/* TODO work and BO cleanup */
if (amdgpu_crtc == NULL((void *)0)) {
DC_LOG_PFLIP("CRTC is null, returning.\n")do { } while(0);
return;
}

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);

if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
DC_LOG_PFLIP("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p]\n",do { } while(0)
	     amdgpu_crtc->pflip_status,do { } while(0)
	     AMDGPU_FLIP_SUBMITTED,do { } while(0)
	     amdgpu_crtc->crtc_id,do { } while(0)
	     amdgpu_crtc)do { } while(0);
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
return;
}

/* page flip completed. */
e = amdgpu_crtc->event;
amdgpu_crtc->event = NULL((void *)0);

WARN_ON(!e)({ int __ret = !!(!e); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!e", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 440); __builtin_expect(!!(__ret), 0); });

vrr_active = amdgpu_dm_vrr_active_irq(amdgpu_crtc);

/* Fixed refresh rate, or VRR scanout position outside front-porch? */
if (!vrr_active ||
   !dc_stream_get_scanoutpos(amdgpu_crtc->dm_irq_params.stream, &v_blank_start,
		      &v_blank_end, &hpos, &vpos) ||
   (vpos < v_blank_start)) {
/* Update to correct count and vblank timestamp if racing with
 * vblank irq. This also updates to the correct vblank timestamp
 * even in VRR mode, as scanout is past the front-porch atm.
 */
drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);

/* Wake up userspace by sending the pageflip event with proper
 * count and timestamp of vblank of flip completion.
 */
if (e) {
	drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);

	/* Event sent, so done with vblank for this flip */
	drm_crtc_vblank_put(&amdgpu_crtc->base);
}
} else if (e) {
/* VRR active and inside front-porch: vblank count and
 * timestamp for pageflip event will only be up to date after
 * drm_crtc_handle_vblank() has been executed from late vblank
 * irq handler after start of back-porch (vline 0). We queue the
 * pageflip event for send-out by drm_crtc_handle_vblank() with
 * updated timestamp and count, once it runs after us.
 *
 * We need to open-code this instead of using the helper
 * drm_crtc_arm_vblank_event(), as that helper would
 * call drm_crtc_accurate_vblank_count(), which we must
 * not call in VRR mode while we are in front-porch!
 */

/* sequence will be replaced by real count during send-out. */
e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
e->pipe = amdgpu_crtc->crtc_id;

list_add_tail(&e->base.link, &adev_to_drm(adev)->vblank_event_list);
e = NULL((void *)0);
}

/* Keep track of vblank of this flip for flip throttling. We use the
* cooked hw counter, as that one incremented at start of this vblank
* of pageflip completion, so last_flip_vblank is the forbidden count
* for queueing new pageflips if vsync + VRR is enabled.
*/
amdgpu_crtc->dm_irq_params.last_flip_vblank =
amdgpu_get_vblank_counter_kms(&amdgpu_crtc->base);

amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);

DC_LOG_PFLIP("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",do { } while(0)
     amdgpu_crtc->crtc_id, amdgpu_crtc,do { } while(0)
     vrr_active, (int) !e)do { } while(0);
500}

502static void dm_vupdate_high_irq(void *interrupt_params)
503{
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
struct amdgpu_crtc *acrtc;
struct drm_device *drm_dev;
struct drm_vblank_crtc *vblank;
ktime_t frame_duration_ns, previous_timestamp;
unsigned long flags;
int vrr_active;

acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);

if (acrtc) {
vrr_active = amdgpu_dm_vrr_active_irq(acrtc);
drm_dev = acrtc->base.dev;
vblank = &drm_dev->vblank[acrtc->base.index];
previous_timestamp = atomic64_read(&irq_params->previous_timestamp)({ typeof(*(&irq_params->previous_timestamp)) __tmp = *
(volatile typeof(*(&irq_params->previous_timestamp)) *
)&(*(&irq_params->previous_timestamp)); membar_datadep_consumer
(); __tmp; });
frame_duration_ns = vblank->time - previous_timestamp;

if (frame_duration_ns > 0) {
	trace_amdgpu_refresh_rate_track(acrtc->base.index,
				frame_duration_ns,
				ktime_divns(NSEC_PER_SEC1000000000L, frame_duration_ns));
	atomic64_set(&irq_params->previous_timestamp, vblank->time)({ typeof(*(&irq_params->previous_timestamp)) __tmp = (
(vblank->time)); *(volatile typeof(*(&irq_params->previous_timestamp
)) *)&(*(&irq_params->previous_timestamp)) = __tmp
; __tmp; });
}

DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d\n",do { } while(0)
	      acrtc->crtc_id,do { } while(0)
	      vrr_active)do { } while(0);

/* Core vblank handling is done here after end of front-porch in
 * vrr mode, as vblank timestamping will give valid results
 * while now done after front-porch. This will also deliver
 * page-flip completion events that have been queued to us
 * if a pageflip happened inside front-porch.
 */
if (vrr_active) {
	dm_crtc_handle_vblank(acrtc);

	/* BTR processing for pre-DCE12 ASICs */
	if (acrtc->dm_irq_params.stream &&
	    adev->family < AMDGPU_FAMILY_AI141) {
		spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
		mod_freesync_handle_v_update(
		    adev->dm.freesync_module,
		    acrtc->dm_irq_params.stream,
		    &acrtc->dm_irq_params.vrr_params);

		dc_stream_adjust_vmin_vmax(
		    adev->dm.dc,
		    acrtc->dm_irq_params.stream,
		    &acrtc->dm_irq_params.vrr_params.adjust);
		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
	}
}
}
559}

561/**
* dm_crtc_high_irq() - Handles CRTC interrupt
* @interrupt_params: used for determining the CRTC instance
*
* Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
* event handler.
*/
568static void dm_crtc_high_irq(void *interrupt_params)
569{
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
struct amdgpu_crtc *acrtc;
unsigned long flags;
int vrr_active;

acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
if (!acrtc)
return;

vrr_active = amdgpu_dm_vrr_active_irq(acrtc);

DC_LOG_VBLANK("crtc:%d, vupdate-vrr:%d, planes:%d\n", acrtc->crtc_id,do { } while(0)
      vrr_active, acrtc->dm_irq_params.active_planes)do { } while(0);

/**
* Core vblank handling at start of front-porch is only possible
* in non-vrr mode, as only there vblank timestamping will give
* valid results while done in front-porch. Otherwise defer it
* to dm_vupdate_high_irq after end of front-porch.
*/
if (!vrr_active)
dm_crtc_handle_vblank(acrtc);

/**
* Following stuff must happen at start of vblank, for crc
* computation and below-the-range btr support in vrr mode.
*/
amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);

/* BTR updates need to happen before VUPDATE on Vega and above. */
if (adev->family < AMDGPU_FAMILY_AI141)
return;

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);

if (acrtc->dm_irq_params.stream &&
   acrtc->dm_irq_params.vrr_params.supported &&
   acrtc->dm_irq_params.freesync_config.state ==
    VRR_STATE_ACTIVE_VARIABLE) {
mod_freesync_handle_v_update(adev->dm.freesync_module,
			     acrtc->dm_irq_params.stream,
			     &acrtc->dm_irq_params.vrr_params);

dc_stream_adjust_vmin_vmax(adev->dm.dc, acrtc->dm_irq_params.stream,
			   &acrtc->dm_irq_params.vrr_params.adjust);
}

/*
* If there aren't any active_planes then DCH HUBP may be clock-gated.
* In that case, pageflip completion interrupts won't fire and pageflip
* completion events won't get delivered. Prevent this by sending
* pending pageflip events from here if a flip is still pending.
*
* If any planes are enabled, use dm_pflip_high_irq() instead, to
* avoid race conditions between flip programming and completion,
* which could cause too early flip completion events.
*/
if (adev->family >= AMDGPU_FAMILY_RV142 &&
   acrtc->pflip_status == AMDGPU_FLIP_SUBMITTED &&
   acrtc->dm_irq_params.active_planes == 0) {
if (acrtc->event) {
	drm_crtc_send_vblank_event(&acrtc->base, acrtc->event);
	acrtc->event = NULL((void *)0);
	drm_crtc_vblank_put(&acrtc->base);
}
acrtc->pflip_status = AMDGPU_FLIP_NONE;
}

spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
640}

642#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
643/**
* dm_dcn_vertical_interrupt0_high_irq() - Handles OTG Vertical interrupt0 for
* DCN generation ASICs
* @interrupt_params: interrupt parameters
*
* Used to set crc window/read out crc value at vertical line 0 position
*/
650static void dm_dcn_vertical_interrupt0_high_irq(void *interrupt_params)
651{
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
struct amdgpu_crtc *acrtc;

acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VLINE0);

if (!acrtc)
return;

amdgpu_dm_crtc_handle_crc_window_irq(&acrtc->base);
662}
663#endif /* CONFIG_DRM_AMD_SECURE_DISPLAY */

665/**
* dmub_aux_setconfig_callback - Callback for AUX or SET_CONFIG command.
* @adev: amdgpu_device pointer
* @notify: dmub notification structure
*
* Dmub AUX or SET_CONFIG command completion processing callback
* Copies dmub notification to DM which is to be read by AUX command.
* issuing thread and also signals the event to wake up the thread.
*/
674static void dmub_aux_setconfig_callback(struct amdgpu_device *adev,
			struct dmub_notification *notify)
676{
if (adev->dm.dmub_notify)
memcpy(adev->dm.dmub_notify, notify, sizeof(struct dmub_notification))__builtin_memcpy((adev->dm.dmub_notify), (notify), (sizeof
(struct dmub_notification)));
if (notify->type == DMUB_NOTIFICATION_AUX_REPLY)
complete(&adev->dm.dmub_aux_transfer_done);
681}

683/**
* dmub_hpd_callback - DMUB HPD interrupt processing callback.
* @adev: amdgpu_device pointer
* @notify: dmub notification structure
*
* Dmub Hpd interrupt processing callback. Gets displayindex through the
* ink index and calls helper to do the processing.
*/
691static void dmub_hpd_callback(struct amdgpu_device *adev,
	      struct dmub_notification *notify)
693{
struct amdgpu_dm_connector *aconnector;
struct amdgpu_dm_connector *hpd_aconnector = NULL((void *)0);
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct dc_link *link;
u8 link_index = 0;
struct drm_device *dev;

if (adev == NULL((void *)0))
return;

if (notify == NULL((void *)0)) {
DRM_ERROR("DMUB HPD callback notification was NULL")__drm_err("DMUB HPD callback notification was NULL");
return;
}

if (notify->link_index > adev->dm.dc->link_count) {
DRM_ERROR("DMUB HPD index (%u)is abnormal", notify->link_index)__drm_err("DMUB HPD index (%u)is abnormal", notify->link_index
);
return;
}

link_index = notify->link_index;
link = adev->dm.dc->links[link_index];
dev = adev->dm.ddev;

drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (link && aconnector->dc_link == link) {
	DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index)printk("\0016" "[" "drm" "] " "DMUB HPD callback: link_index=%u\n"
, link_index);
	hpd_aconnector = aconnector;
	break;
}
}
drm_connector_list_iter_end(&iter);

if (hpd_aconnector) {
if (notify->type == DMUB_NOTIFICATION_HPD)
	handle_hpd_irq_helper(hpd_aconnector);
else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
	handle_hpd_rx_irq(hpd_aconnector);
}
736}

738/**
* register_dmub_notify_callback - Sets callback for DMUB notify
* @adev: amdgpu_device pointer
* @type: Type of dmub notification
* @callback: Dmub interrupt callback function
* @dmub_int_thread_offload: offload indicator
*
* API to register a dmub callback handler for a dmub notification
* Also sets indicator whether callback processing to be offloaded.
* to dmub interrupt handling thread
* Return: true if successfully registered, false if there is existing registration
*/
750static bool_Bool register_dmub_notify_callback(struct amdgpu_device *adev,
			  enum dmub_notification_type type,
			  dmub_notify_interrupt_callback_t callback,
			  bool_Bool dmub_int_thread_offload)
754{
if (callback != NULL((void *)0) && type < ARRAY_SIZE(adev->dm.dmub_thread_offload)(sizeof((adev->dm.dmub_thread_offload)) / sizeof((adev->
dm.dmub_thread_offload)[0]))) {
adev->dm.dmub_callback[type] = callback;
adev->dm.dmub_thread_offload[type] = dmub_int_thread_offload;
} else
return false0;

return true1;
762}

764static void dm_handle_hpd_work(struct work_struct *work)
765{
struct dmub_hpd_work *dmub_hpd_wrk;

dmub_hpd_wrk = container_of(work, struct dmub_hpd_work, handle_hpd_work)({ const __typeof( ((struct dmub_hpd_work *)0)->handle_hpd_work
 ) *__mptr = (work); (struct dmub_hpd_work *)( (char *)__mptr
 - __builtin_offsetof(struct dmub_hpd_work, handle_hpd_work) )
;});

if (!dmub_hpd_wrk->dmub_notify) {
DRM_ERROR("dmub_hpd_wrk dmub_notify is NULL")__drm_err("dmub_hpd_wrk dmub_notify is NULL");
return;
}

if (dmub_hpd_wrk->dmub_notify->type < ARRAY_SIZE(dmub_hpd_wrk->adev->dm.dmub_callback)(sizeof((dmub_hpd_wrk->adev->dm.dmub_callback)) / sizeof
((dmub_hpd_wrk->adev->dm.dmub_callback)[0]))) {
dmub_hpd_wrk->adev->dm.dmub_callback[dmub_hpd_wrk->dmub_notify->type](dmub_hpd_wrk->adev,
dmub_hpd_wrk->dmub_notify);
}

kfree(dmub_hpd_wrk->dmub_notify);
kfree(dmub_hpd_wrk);

783}

785#define DMUB_TRACE_MAX_READ64 64
786/**
* dm_dmub_outbox1_low_irq() - Handles Outbox interrupt
* @interrupt_params: used for determining the Outbox instance
*
* Handles the Outbox Interrupt
* event handler.
*/
793static void dm_dmub_outbox1_low_irq(void *interrupt_params)
794{
struct dmub_notification notify;
struct common_irq_params *irq_params = interrupt_params;
struct amdgpu_device *adev = irq_params->adev;
struct amdgpu_display_manager *dm = &adev->dm;
struct dmcub_trace_buf_entry entry = { 0 };
u32 count = 0;
struct dmub_hpd_work *dmub_hpd_wrk;
struct dc_link *plink = NULL((void *)0);

if (dc_enable_dmub_notifications(adev->dm.dc) &&
irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {

do {
	dc_stat_get_dmub_notification(adev->dm.dc, &notify);
	if (notify.type >= ARRAY_SIZE(dm->dmub_thread_offload)(sizeof((dm->dmub_thread_offload)) / sizeof((dm->dmub_thread_offload
)[0]))) {
		DRM_ERROR("DM: notify type %d invalid!", notify.type)__drm_err("DM: notify type %d invalid!", notify.type);
		continue;
	}
	if (!dm->dmub_callback[notify.type]) {
		DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DMUB notification skipped, no handler: type=%d\n"
, notify.type);
		continue;
	}
	if (dm->dmub_thread_offload[notify.type] == true1) {
		dmub_hpd_wrk = kzalloc(sizeof(*dmub_hpd_wrk), GFP_ATOMIC0x0002);
		if (!dmub_hpd_wrk) {
			DRM_ERROR("Failed to allocate dmub_hpd_wrk")__drm_err("Failed to allocate dmub_hpd_wrk");
			return;
		}
		dmub_hpd_wrk->dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_ATOMIC0x0002);
		if (!dmub_hpd_wrk->dmub_notify) {
			kfree(dmub_hpd_wrk);
			DRM_ERROR("Failed to allocate dmub_hpd_wrk->dmub_notify")__drm_err("Failed to allocate dmub_hpd_wrk->dmub_notify");
			return;
		}
		INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
		if (dmub_hpd_wrk->dmub_notify)
			memcpy(dmub_hpd_wrk->dmub_notify, &notify, sizeof(struct dmub_notification))__builtin_memcpy((dmub_hpd_wrk->dmub_notify), (&notify
), (sizeof(struct dmub_notification)));
		dmub_hpd_wrk->adev = adev;
		if (notify.type == DMUB_NOTIFICATION_HPD) {
			plink = adev->dm.dc->links[notify.link_index];
			if (plink) {
				plink->hpd_status =
					notify.hpd_status == DP_HPD_PLUG;
			}
		}
		queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
	} else {
		dm->dmub_callback[notify.type](adev, &notify);
	}
} while (notify.pending_notification);
}


do {
if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
	trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
					entry.param0, entry.param1);

	DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n"
, entry.trace_code, entry.tick_count, entry.param0, entry.param1
)
		 entry.trace_code, entry.tick_count, entry.param0, entry.param1)___drm_dbg(((void *)0), DRM_UT_DRIVER, "trace_code:%u, tick_count:%u, param0:%u, param1:%u\n"
, entry.trace_code, entry.tick_count, entry.param0, entry.param1
);
} else
	break;

count++;

} while (count <= DMUB_TRACE_MAX_READ64);

if (count > DMUB_TRACE_MAX_READ64)
DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Warning : count > DMUB_TRACE_MAX_READ"
);
864}

866static int dm_set_clockgating_state(void *handle,
  enum amd_clockgating_state state)
868{
return 0;
870}

872static int dm_set_powergating_state(void *handle,
  enum amd_powergating_state state)
874{
return 0;
876}

878/* Prototypes of private functions */
879static int dm_early_init(void *handle);

881/* Allocate memory for FBC compressed data  */
882static void amdgpu_dm_fbc_init(struct drm_connector *connector)
883{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_compressor_info *compressor = &adev->dm.compressor;
struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct drm_display_mode *mode;
unsigned long max_size = 0;

if (adev->dm.dc->fbc_compressor == NULL((void *)0))
return;

if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
return;

if (compressor->bo_ptr)
return;


list_for_each_entry(mode, &connector->modes, head)for (mode = ({ const __typeof( ((__typeof(*mode) *)0)->head
 ) *__mptr = ((&connector->modes)->next); (__typeof
(*mode) *)( (char *)__mptr - __builtin_offsetof(__typeof(*mode
), head) );}); &mode->head != (&connector->modes
); mode = ({ const __typeof( ((__typeof(*mode) *)0)->head )
 *__mptr = (mode->head.next); (__typeof(*mode) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*mode), head) );})) {
if (max_size < mode->htotal * mode->vtotal)
	max_size = mode->htotal * mode->vtotal;
}

if (max_size) {
int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE(1 << 12),
	    AMDGPU_GEM_DOMAIN_GTT0x2, &compressor->bo_ptr,
	    &compressor->gpu_addr, &compressor->cpu_addr);

if (r)
	DRM_ERROR("DM: Failed to initialize FBC\n")__drm_err("DM: Failed to initialize FBC\n");
else {
	adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
	DRM_INFO("DM: FBC alloc %lu\n", max_size*4)printk("\0016" "[" "drm" "] " "DM: FBC alloc %lu\n", max_size
*4);
}

}

920}

922static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
			  int pipe, bool_Bool *enabled,
			  unsigned char *buf, int max_bytes)
925{
struct drm_device *dev = dev_get_drvdata(kdev);
struct amdgpu_device *adev = drm_to_adev(dev);
struct drm_connector *connector;
struct drm_connector_list_iter conn_iter;
struct amdgpu_dm_connector *aconnector;
int ret = 0;

*enabled = false0;

mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock);

drm_connector_list_iter_begin(dev, &conn_iter);
drm_for_each_connector_iter(connector, &conn_iter)while ((connector = drm_connector_list_iter_next(&conn_iter
))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->audio_inst != port)
	continue;

*enabled = true1;
ret = drm_eld_size(connector->eld);
memcpy(buf, connector->eld, min(max_bytes, ret))__builtin_memcpy((buf), (connector->eld), ((((max_bytes)<
(ret))?(max_bytes):(ret))));

break;
}
drm_connector_list_iter_end(&conn_iter);

mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock);

DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled)___drm_dbg(((void *)0), DRM_UT_KMS, "Get ELD : idx=%d ret=%d en=%d\n"
, port, ret, *enabled);

return ret;
956}

958static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
.get_eld = amdgpu_dm_audio_component_get_eld,
960};

962static int amdgpu_dm_audio_component_bind(struct device *kdev,
		       struct device *hda_kdev, void *data)
964{
struct drm_device *dev = dev_get_drvdata(kdev);
struct amdgpu_device *adev = drm_to_adev(dev);
struct drm_audio_component *acomp = data;

acomp->ops = &amdgpu_dm_audio_component_ops;
acomp->dev = kdev;
adev->dm.audio_component = acomp;

return 0;
974}

976static void amdgpu_dm_audio_component_unbind(struct device *kdev,
			  struct device *hda_kdev, void *data)
978{
struct drm_device *dev = dev_get_drvdata(kdev);
struct amdgpu_device *adev = drm_to_adev(dev);
struct drm_audio_component *acomp = data;

acomp->ops = NULL((void *)0);
acomp->dev = NULL((void *)0);
adev->dm.audio_component = NULL((void *)0);
986}

988static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
.bind	= amdgpu_dm_audio_component_bind,
.unbind	= amdgpu_dm_audio_component_unbind,
991};

993static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
994{
int i, ret;

if (!amdgpu_audio)
return 0;

adev->mode_info.audio.enabled = true1;

adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;

for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
adev->mode_info.audio.pin[i].channels = -1;
adev->mode_info.audio.pin[i].rate = -1;
adev->mode_info.audio.pin[i].bits_per_sample = -1;
adev->mode_info.audio.pin[i].status_bits = 0;
adev->mode_info.audio.pin[i].category_code = 0;
adev->mode_info.audio.pin[i].connected = false0;
adev->mode_info.audio.pin[i].id =
	adev->dm.dc->res_pool->audios[i]->inst;
adev->mode_info.audio.pin[i].offset = 0;
}

ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops)0;
if (ret < 0)
return ret;

adev->dm.audio_registered = true1;

return 0;
1023}

1025static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
1026{
if (!amdgpu_audio)
return;

if (!adev->mode_info.audio.enabled)
return;

if (adev->dm.audio_registered) {
component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
adev->dm.audio_registered = false0;
}

/* TODO: Disable audio? */

adev->mode_info.audio.enabled = false0;
1041}

1043static  void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
1044{
struct drm_audio_component *acomp = adev->dm.audio_component;

if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
DRM_DEBUG_KMS("Notify ELD: %d\n", pin)___drm_dbg(((void *)0), DRM_UT_KMS, "Notify ELD: %d\n", pin);

acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
				 pin, -1);
}
1053}

1055static int dm_dmub_hw_init(struct amdgpu_device *adev)
1056{
const struct dmcub_firmware_header_v1_0 *hdr;
struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
const struct firmware *dmub_fw = adev->dm.dmub_fw;
struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
struct abm *abm = adev->dm.dc->res_pool->abm;
struct dmub_srv_hw_params hw_params;
enum dmub_status status;
const unsigned char *fw_inst_const, *fw_bss_data;
u32 i, fw_inst_const_size, fw_bss_data_size;
bool_Bool has_hw_support;

if (!dmub_srv)
/* DMUB isn't supported on the ASIC. */
return 0;

if (!fb_info) {
DRM_ERROR("No framebuffer info for DMUB service.\n")__drm_err("No framebuffer info for DMUB service.\n");
return -EINVAL22;
}

if (!dmub_fw) {
/* Firmware required for DMUB support. */
DRM_ERROR("No firmware provided for DMUB.\n")__drm_err("No firmware provided for DMUB.\n");
return -EINVAL22;
}

status = dmub_srv_has_hw_support(dmub_srv, &has_hw_support);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error checking HW support for DMUB: %d\n", status)__drm_err("Error checking HW support for DMUB: %d\n", status);
return -EINVAL22;
}

if (!has_hw_support) {
DRM_INFO("DMUB unsupported on ASIC\n")printk("\0016" "[" "drm" "] " "DMUB unsupported on ASIC\n");
return 0;
}

/* Reset DMCUB if it was previously running - before we overwrite its memory. */
status = dmub_srv_hw_reset(dmub_srv);
if (status != DMUB_STATUS_OK)
DRM_WARN("Error resetting DMUB HW: %d\n", status)printk("\0014" "[" "drm" "] " "Error resetting DMUB HW: %d\n"
, status);

hdr = (const struct dmcub_firmware_header_v1_0 *)dmub_fw->data;

fw_inst_const = dmub_fw->data +
	le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
	PSP_HEADER_BYTES0x100;

fw_bss_data = dmub_fw->data +
      le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
      le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes));

/* Copy firmware and bios info into FB memory. */
fw_inst_const_size = le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) -
	     PSP_HEADER_BYTES0x100 - PSP_FOOTER_BYTES0x100;

fw_bss_data_size = le32_to_cpu(hdr->bss_data_bytes)((__uint32_t)(hdr->bss_data_bytes));

/* if adev->firmware.load_type == AMDGPU_FW_LOAD_PSP,
* amdgpu_ucode_init_single_fw will load dmub firmware
* fw_inst_const part to cw0; otherwise, the firmware back door load
* will be done by dm_dmub_hw_init
*/
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
memcpy(fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr, fw_inst_const,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr
), (fw_inst_const), (fw_inst_const_size))
		fw_inst_const_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_0_INST_CONST].cpu_addr
), (fw_inst_const), (fw_inst_const_size));
}

if (fw_bss_data_size)
memcpy(fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr
), (fw_bss_data), (fw_bss_data_size))
       fw_bss_data, fw_bss_data_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_2_BSS_DATA].cpu_addr
), (fw_bss_data), (fw_bss_data_size));

/* Copy firmware bios info into FB memory. */
memcpy(fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr, adev->bios,__builtin_memcpy((fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr
), (adev->bios), (adev->bios_size))
      adev->bios_size)__builtin_memcpy((fb_info->fb[DMUB_WINDOW_3_VBIOS].cpu_addr
), (adev->bios), (adev->bios_size));

/* Reset regions that need to be reset. */
memset(fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_4_MAILBOX].size))
fb_info->fb[DMUB_WINDOW_4_MAILBOX].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_4_MAILBOX].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_4_MAILBOX].size));

memset(fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size))
      fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].size));

memset(fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr, 0,__builtin_memset((fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_6_FW_STATE].size))
      fb_info->fb[DMUB_WINDOW_6_FW_STATE].size)__builtin_memset((fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr
), (0), (fb_info->fb[DMUB_WINDOW_6_FW_STATE].size));

/* Initialize hardware. */
memset(&hw_params, 0, sizeof(hw_params))__builtin_memset((&hw_params), (0), (sizeof(hw_params)));
hw_params.fb_base = adev->gmc.fb_start;
hw_params.fb_offset = adev->gmc.aper_base;

/* backdoor load firmware and trigger dmub running */
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
hw_params.load_inst_const = true1;

if (dmcu)
hw_params.psp_version = dmcu->psp_version;

for (i = 0; i < fb_info->num_fb; ++i)
hw_params.fb[i] = &fb_info->fb[i];

switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
hw_params.dpia_supported = true1;
hw_params.disable_dpia = adev->dm.dc->debug.dpia_debug.bits.disable_dpia;
break;
default:
break;
}

status = dmub_srv_hw_init(dmub_srv, &hw_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error initializing DMUB HW: %d\n", status)__drm_err("Error initializing DMUB HW: %d\n", status);
return -EINVAL22;
}

/* Wait for firmware load to finish. */
status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
if (status != DMUB_STATUS_OK)
DRM_WARN("Wait for DMUB auto-load failed: %d\n", status)printk("\0014" "[" "drm" "] " "Wait for DMUB auto-load failed: %d\n"
, status);

/* Init DMCU and ABM if available. */
if (dmcu && abm) {
dmcu->funcs->dmcu_init(dmcu);
abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
}

if (!adev->dm.dc->ctx->dmub_srv)
adev->dm.dc->ctx->dmub_srv = dc_dmub_srv_create(adev->dm.dc, dmub_srv);
if (!adev->dm.dc->ctx->dmub_srv) {
DRM_ERROR("Couldn't allocate DC DMUB server!\n")__drm_err("Couldn't allocate DC DMUB server!\n");
return -ENOMEM12;
}

DRM_INFO("DMUB hardware initialized: version=0x%08X\n",printk("\0016" "[" "drm" "] " "DMUB hardware initialized: version=0x%08X\n"
, adev->dm.dmcub_fw_version)
 adev->dm.dmcub_fw_version)printk("\0016" "[" "drm" "] " "DMUB hardware initialized: version=0x%08X\n"
, adev->dm.dmcub_fw_version);

return 0;
1197}

1199static void dm_dmub_hw_resume(struct amdgpu_device *adev)
1200{
struct dmub_srv *dmub_srv = adev->dm.dmub_srv;
enum dmub_status status;
bool_Bool init;

if (!dmub_srv) {
/* DMUB isn't supported on the ASIC. */
return;
}

status = dmub_srv_is_hw_init(dmub_srv, &init);
if (status != DMUB_STATUS_OK)
DRM_WARN("DMUB hardware init check failed: %d\n", status)printk("\0014" "[" "drm" "] " "DMUB hardware init check failed: %d\n"
, status);

if (status == DMUB_STATUS_OK && init) {
/* Wait for firmware load to finish. */
status = dmub_srv_wait_for_auto_load(dmub_srv, 100000);
if (status != DMUB_STATUS_OK)
	DRM_WARN("Wait for DMUB auto-load failed: %d\n", status)printk("\0014" "[" "drm" "] " "Wait for DMUB auto-load failed: %d\n"
, status);
} else {
/* Perform the full hardware initialization. */
dm_dmub_hw_init(adev);
}
1223}

1225static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_addr_space_config *pa_config)
1226{
u64 pt_base;
u32 logical_addr_low;
u32 logical_addr_high;
u32 agp_base, agp_bot, agp_top;
PHYSICAL_ADDRESS_LOCunion large_integer page_table_start, page_table_end, page_table_base;

memset(pa_config, 0, sizeof(*pa_config))__builtin_memset((pa_config), (0), (sizeof(*pa_config)));

agp_base = 0;
agp_bot = adev->gmc.agp_start >> 24;
agp_top = adev->gmc.agp_end >> 24;

/* AGP aperture is disabled */
if (agp_bot == agp_top) {
logical_addr_low  = adev->gmc.vram_start >> 18;
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
	/*
	 * Raven2 has a HW issue that it is unable to use the vram which
	 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
	 * workaround that increase system aperture high address (add 1)
	 * to get rid of the VM fault and hardware hang.
	 */
	logical_addr_high = (adev->gmc.fb_end >> 18) + 0x1;
else
	logical_addr_high = adev->gmc.vram_end >> 18;
} else {
logical_addr_low  = min(adev->gmc.fb_start, adev->gmc.agp_start)(((adev->gmc.fb_start)<(adev->gmc.agp_start))?(adev->
gmc.fb_start):(adev->gmc.agp_start)) >> 18;
if (adev->apu_flags & AMD_APU_IS_RAVEN2)
	/*
	 * Raven2 has a HW issue that it is unable to use the vram which
	 * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
	 * workaround that increase system aperture high address (add 1)
	 * to get rid of the VM fault and hardware hang.
	 */
	logical_addr_high = max((adev->gmc.fb_end >> 18) + 0x1, adev->gmc.agp_end >> 18)((((adev->gmc.fb_end >> 18) + 0x1)>(adev->gmc.
agp_end >> 18))?((adev->gmc.fb_end >> 18) + 0x1
):(adev->gmc.agp_end >> 18));
else
	logical_addr_high = max(adev->gmc.fb_end, adev->gmc.agp_end)(((adev->gmc.fb_end)>(adev->gmc.agp_end))?(adev->
gmc.fb_end):(adev->gmc.agp_end)) >> 18;
}

pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);

page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >>((u32)(((adev->gmc.gart_start >> 12) >> 16) >>
 16))
				   AMDGPU_GPU_PAGE_SHIFT)((u32)(((adev->gmc.gart_start >> 12) >> 16) >>
 16));
page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >>((u32)(adev->gmc.gart_start >> 12))
				  AMDGPU_GPU_PAGE_SHIFT)((u32)(adev->gmc.gart_start >> 12));
page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >>((u32)(((adev->gmc.gart_end >> 12) >> 16) >>
 16))
				 AMDGPU_GPU_PAGE_SHIFT)((u32)(((adev->gmc.gart_end >> 12) >> 16) >>
 16));
page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >>((u32)(adev->gmc.gart_end >> 12))
				AMDGPU_GPU_PAGE_SHIFT)((u32)(adev->gmc.gart_end >> 12));
page_table_base.high_part = upper_32_bits(pt_base)((u32)(((pt_base) >> 16) >> 16));
page_table_base.low_part = lower_32_bits(pt_base)((u32)(pt_base));

pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;
pa_config->system_aperture.end_addr = (uint64_t)logical_addr_high << 18;

pa_config->system_aperture.agp_base = (uint64_t)agp_base << 24;
pa_config->system_aperture.agp_bot = (uint64_t)agp_bot << 24;
pa_config->system_aperture.agp_top = (uint64_t)agp_top << 24;

pa_config->system_aperture.fb_base = adev->gmc.fb_start;
pa_config->system_aperture.fb_offset = adev->gmc.aper_base;
pa_config->system_aperture.fb_top = adev->gmc.fb_end;

pa_config->gart_config.page_table_start_addr = page_table_start.quad_part << 12;
pa_config->gart_config.page_table_end_addr = page_table_end.quad_part << 12;
pa_config->gart_config.page_table_base_addr = page_table_base.quad_part;

pa_config->is_hvm_enabled = adev->mode_info.gpu_vm_support;

1296}

1298static void force_connector_state(
struct amdgpu_dm_connector *aconnector,
enum drm_connector_force force_state)
1301{
struct drm_connector *connector = &aconnector->base;

mutex_lock(&connector->dev->mode_config.mutex)rw_enter_write(&connector->dev->mode_config.mutex);
aconnector->base.force = force_state;
mutex_unlock(&connector->dev->mode_config.mutex)rw_exit_write(&connector->dev->mode_config.mutex);

mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);
drm_kms_helper_connector_hotplug_event(connector);
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);
1311}

1313static void dm_handle_hpd_rx_offload_work(struct work_struct *work)
1314{
struct hpd_rx_irq_offload_work *offload_work;
struct amdgpu_dm_connector *aconnector;
struct dc_link *dc_link;
struct amdgpu_device *adev;
enum dc_connection_type new_connection_type = dc_connection_none;
unsigned long flags;
union test_response test_response;

memset(&test_response, 0, sizeof(test_response))__builtin_memset((&test_response), (0), (sizeof(test_response
)));

offload_work = container_of(work, struct hpd_rx_irq_offload_work, work)({ const __typeof( ((struct hpd_rx_irq_offload_work *)0)->
work ) *__mptr = (work); (struct hpd_rx_irq_offload_work *)( (
char *)__mptr - __builtin_offsetof(struct hpd_rx_irq_offload_work
, work) );});
aconnector = offload_work->offload_wq->aconnector;

if (!aconnector) {
DRM_ERROR("Can't retrieve aconnector in hpd_rx_irq_offload_work")__drm_err("Can't retrieve aconnector in hpd_rx_irq_offload_work"
);
goto skip;
}

adev = drm_to_adev(aconnector->base.dev);
dc_link = aconnector->dc_link;

mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);
if (!dc_link_detect_sink(dc_link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);

if (new_connection_type == dc_connection_none)
goto skip;

if (amdgpu_in_reset(adev))
goto skip;

if (offload_work->data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
offload_work->data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
dm_handle_mst_sideband_msg_ready_event(&aconnector->mst_mgr, DOWN_OR_UP_MSG_RDY_EVENT);
spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags)do { flags = 0; mtx_enter(&offload_work->offload_wq->
offload_lock); } while (0);
offload_work->offload_wq->is_handling_mst_msg_rdy_event = false0;
spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags)do { (void)(flags); mtx_leave(&offload_work->offload_wq
->offload_lock); } while (0);
goto skip;
}

mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
if (offload_work->data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
dc_link_dp_handle_automated_test(dc_link);

if (aconnector->timing_changed) {
	/* force connector disconnect and reconnect */
	force_connector_state(aconnector, DRM_FORCE_OFF);
	drm_msleep(100)mdelay(100);
	force_connector_state(aconnector, DRM_FORCE_UNSPECIFIED);
}

test_response.bits.ACK = 1;

core_link_write_dpcd(
dc_link,
DP_TEST_RESPONSE0x260,
&test_response.raw,
sizeof(test_response));
} else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&
	hpd_rx_irq_check_link_loss_status(dc_link, &offload_work->data) &&
	dc_link_dp_allow_hpd_rx_irq(dc_link)) {
/* offload_work->data is from handle_hpd_rx_irq->
 * schedule_hpd_rx_offload_work.this is defer handle
 * for hpd short pulse. upon here, link status may be
 * changed, need get latest link status from dpcd
 * registers. if link status is good, skip run link
 * training again.
 */
union hpd_irq_data irq_data;

memset(&irq_data, 0, sizeof(irq_data))__builtin_memset((&irq_data), (0), (sizeof(irq_data)));

/* before dc_link_dp_handle_link_loss, allow new link lost handle
 * request be added to work queue if link lost at end of dc_link_
 * dp_handle_link_loss
 */
spin_lock_irqsave(&offload_work->offload_wq->offload_lock, flags)do { flags = 0; mtx_enter(&offload_work->offload_wq->
offload_lock); } while (0);
offload_work->offload_wq->is_handling_link_loss = false0;
spin_unlock_irqrestore(&offload_work->offload_wq->offload_lock, flags)do { (void)(flags); mtx_leave(&offload_work->offload_wq
->offload_lock); } while (0);

if ((read_hpd_rx_irq_data(dc_link, &irq_data) == DC_OK) &&
	hpd_rx_irq_check_link_loss_status(dc_link, &irq_data))
	dc_link_dp_handle_link_loss(dc_link);
}
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);

1402skip:
kfree(offload_work);

1405}

1407static struct hpd_rx_irq_offload_work_queue *hpd_rx_irq_create_workqueue(struct dc *dc)
1408{
int max_caps = dc->caps.max_links;
int i = 0;
struct hpd_rx_irq_offload_work_queue *hpd_rx_offload_wq = NULL((void *)0);

hpd_rx_offload_wq = kcalloc(max_caps, sizeof(*hpd_rx_offload_wq), GFP_KERNEL(0x0001 | 0x0004));

if (!hpd_rx_offload_wq)
return NULL((void *)0);


for (i = 0; i < max_caps; i++) {
hpd_rx_offload_wq[i].wq =
		    create_singlethread_workqueue("amdgpu_dm_hpd_rx_offload_wq");

if (hpd_rx_offload_wq[i].wq == NULL((void *)0)) {
	DRM_ERROR("create amdgpu_dm_hpd_rx_offload_wq fail!")__drm_err("create amdgpu_dm_hpd_rx_offload_wq fail!");
	goto out_err;
}

mtx_init(&hpd_rx_offload_wq[i].offload_lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&hpd_rx_offload_wq
[i].offload_lock), ((((0x9)) > 0x0 && ((0x9)) <
 0x9) ? 0x9 : ((0x9)))); } while (0);
}

return hpd_rx_offload_wq;

1433out_err:
for (i = 0; i < max_caps; i++) {
if (hpd_rx_offload_wq[i].wq)
	destroy_workqueue(hpd_rx_offload_wq[i].wq);
}
kfree(hpd_rx_offload_wq);
return NULL((void *)0);
1440}

1442struct amdgpu_stutter_quirk {
u16 chip_vendor;
u16 chip_device;
u16 subsys_vendor;
u16 subsys_device;
u8 revision;
1448};

1450static const struct amdgpu_stutter_quirk amdgpu_stutter_quirk_list[] = {
/* https://bugzilla.kernel.org/show_bug.cgi?id=214417 */
{ 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc8 },
{ 0, 0, 0, 0, 0 },
1454};

1456static bool_Bool dm_should_disable_stutter(struct pci_dev *pdev)
1457{
const struct amdgpu_stutter_quirk *p = amdgpu_stutter_quirk_list;

while (p && p->chip_device != 0) {
if (pdev->vendor == p->chip_vendor &&
    pdev->device == p->chip_device &&
    pdev->subsystem_vendor == p->subsys_vendor &&
    pdev->subsystem_device == p->subsys_device &&
    pdev->revision == p->revision) {
	return true1;
}
++p;
}
return false0;
1471}

1473static const struct dmi_system_id hpd_disconnect_quirk_table[] = {
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3660"){(DMI_PRODUCT_NAME), ("Precision 3660")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3260"){(DMI_PRODUCT_NAME), ("Precision 3260")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "Precision 3460"){(DMI_PRODUCT_NAME), ("Precision 3460")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower Plus 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Tower Plus 7010")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Tower 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Tower 7010")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF Plus 7010"){(DMI_PRODUCT_NAME), ("OptiPlex SFF Plus 7010")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex SFF 7010"){(DMI_PRODUCT_NAME), ("OptiPlex SFF 7010")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro Plus 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Micro Plus 7010")},
},
},
{
.matches = {
	DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."){(DMI_SYS_VENDOR), ("Dell Inc.")},
	DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex Micro 7010"){(DMI_PRODUCT_NAME), ("OptiPlex Micro 7010")},
},
},
{}
/* TODO: refactor this from a fixed table to a dynamic option */
1530};

1532static void retrieve_dmi_info(struct amdgpu_display_manager *dm)
1533{
const struct dmi_system_id *dmi_id;

dm->aux_hpd_discon_quirk = false0;

dmi_id = dmi_first_match(hpd_disconnect_quirk_table);
if (dmi_id) {
dm->aux_hpd_discon_quirk = true1;
DRM_INFO("aux_hpd_discon_quirk attached\n")printk("\0016" "[" "drm" "] " "aux_hpd_discon_quirk attached\n"
);
}
1543}

1545static int amdgpu_dm_init(struct amdgpu_device *adev)
1546{
struct dc_init_data init_data;
1548#ifdef CONFIG_DRM_AMD_DC_HDCP
struct dc_callback_init init_params;
1550#endif
int r;

adev->dm.ddev = adev_to_drm(adev);
adev->dm.adev = adev;

/* Zero all the fields */
memset(&init_data, 0, sizeof(init_data))__builtin_memset((&init_data), (0), (sizeof(init_data)));
1558#ifdef CONFIG_DRM_AMD_DC_HDCP
memset(&init_params, 0, sizeof(init_params))__builtin_memset((&init_params), (0), (sizeof(init_params
)));
1560#endif

rw_init(&adev->dm.dpia_aux_lock, "dmdpia")_rw_init_flags(&adev->dm.dpia_aux_lock, "dmdpia", 0, (
(void *)0));
rw_init(&adev->dm.dc_lock, "dmdc")_rw_init_flags(&adev->dm.dc_lock, "dmdc", 0, ((void *)
0));
rw_init(&adev->dm.audio_lock, "dmaud")_rw_init_flags(&adev->dm.audio_lock, "dmaud", 0, ((void
 *)0));
mtx_init(&adev->dm.vblank_lock, IPL_TTY)do { (void)(((void *)0)); (void)(0); __mtx_init((&adev->
dm.vblank_lock), ((((0x9)) > 0x0 && ((0x9)) < 0x9
) ? 0x9 : ((0x9)))); } while (0);

if (amdgpu_dm_irq_init(adev)) {
DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n")__drm_err("amdgpu: failed to initialize DM IRQ support.\n");
goto error;
}

init_data.asic_id.chip_family = adev->family;

init_data.asic_id.pci_revision_id = adev->pdev->revision;
init_data.asic_id.hw_internal_rev = adev->external_rev_id;
init_data.asic_id.chip_id = adev->pdev->device;

init_data.asic_id.vram_width = adev->gmc.vram_width;
/* TODO: initialize init_data.asic_id.vram_type here!!!! */
init_data.asic_id.atombios_base_address =
adev->mode_info.atom_context->bios;

init_data.driver = adev;

adev->dm.cgs_device = amdgpu_cgs_create_device(adev);

if (!adev->dm.cgs_device) {
DRM_ERROR("amdgpu: failed to create cgs device.\n")__drm_err("amdgpu: failed to create cgs device.\n");
goto error;
}

init_data.cgs_device = adev->dm.cgs_device;

init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;

switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
switch (adev->dm.dmcub_fw_version) {
case 0: /* development */
case 0x1: /* linux-firmware.git hash 6d9f399 */
case 0x01000000: /* linux-firmware.git hash 9a0b0f4 */
	init_data.flags.disable_dmcu = false0;
	break;
default:
	init_data.flags.disable_dmcu = true1;
}
break;
case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)):
init_data.flags.disable_dmcu = true1;
break;
default:
break;
}

switch (adev->asic_type) {
case CHIP_CARRIZO:
case CHIP_STONEY:
init_data.flags.gpu_vm_support = true1;
break;
default:
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(1, 0, 0)(((1) << 16) | ((0) << 8) | (0)):
case IP_VERSION(1, 0, 1)(((1) << 16) | ((0) << 8) | (1)):
	/* enable S/G on PCO and RV2 */
	if ((adev->apu_flags & AMD_APU_IS_RAVEN2) ||
	    (adev->apu_flags & AMD_APU_IS_PICASSO))
		init_data.flags.gpu_vm_support = true1;
	break;
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)):
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
	init_data.flags.gpu_vm_support = true1;
	break;
default:
	break;
}
break;
}
if (init_data.flags.gpu_vm_support &&
   (amdgpu_sg_display == 0))
init_data.flags.gpu_vm_support = false0;

if (init_data.flags.gpu_vm_support)
adev->mode_info.gpu_vm_support = true1;

if (amdgpu_dc_feature_mask & DC_FBC_MASK)
init_data.flags.fbc_support = true1;

if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
init_data.flags.multi_mon_pp_mclk_switch = true1;

if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
init_data.flags.disable_fractional_pwm = true1;

if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
init_data.flags.edp_no_power_sequencing = true1;

if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP1_4A)
init_data.flags.allow_lttpr_non_transparent_mode.bits.DP1_4A = true1;
if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true1;

init_data.flags.seamless_boot_edp_requested = false0;

if (check_seamless_boot_capability(adev)) {
init_data.flags.seamless_boot_edp_requested = true1;
init_data.flags.allow_seamless_boot_optimization = true1;
DRM_INFO("Seamless boot condition check passed\n")printk("\0016" "[" "drm" "] " "Seamless boot condition check passed\n"
);
}

init_data.flags.enable_mipi_converter_optimization = true1;

init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0];
init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0];

INIT_LIST_HEAD(&adev->dm.da_list);

retrieve_dmi_info(&adev->dm);

/* Display Core create. */
adev->dm.dc = dc_create(&init_data);

if (adev->dm.dc) {
DRM_INFO("Display Core initialized with v%s!\n", DC_VER)printk("\0016" "[" "drm" "] " "Display Core initialized with v%s!\n"
, "3.2.207");
} else {
DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER)printk("\0016" "[" "drm" "] " "Display Core failed to initialize with v%s!\n"
, "3.2.207");
goto error;
}

if (amdgpu_dc_debug_mask & DC_DISABLE_PIPE_SPLIT) {
adev->dm.dc->debug.force_single_disp_pipe_split = false0;
adev->dm.dc->debug.pipe_split_policy = MPC_SPLIT_AVOID;
}

if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
adev->dm.dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false0 : true1;
if (dm_should_disable_stutter(adev->pdev))
adev->dm.dc->debug.disable_stutter = true1;

if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)
adev->dm.dc->debug.disable_stutter = true1;

if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)
adev->dm.dc->debug.disable_dsc = true1;

if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)
adev->dm.dc->debug.disable_clock_gate = true1;

if (amdgpu_dc_debug_mask & DC_FORCE_SUBVP_MCLK_SWITCH)
adev->dm.dc->debug.force_subvp_mclk_switch = true1;

adev->dm.dc->debug.visual_confirm = amdgpu_dc_visual_confirm;

/* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */
adev->dm.dc->debug.ignore_cable_id = true1;

r = dm_dmub_hw_init(adev);
if (r) {
DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n",
 r);
goto error;
}

dc_hardware_init(adev->dm.dc);

adev->dm.hpd_rx_offload_wq = hpd_rx_irq_create_workqueue(adev->dm.dc);
if (!adev->dm.hpd_rx_offload_wq) {
DRM_ERROR("amdgpu: failed to create hpd rx offload workqueue.\n")__drm_err("amdgpu: failed to create hpd rx offload workqueue.\n"
);
goto error;
}

if ((adev->flags & AMD_IS_APU) && (adev->asic_type >= CHIP_CARRIZO)) {
struct dc_phy_addr_space_config pa_config;

mmhub_read_system_context(adev, &pa_config);

// Call the DC init_memory func
dc_setup_system_context(adev->dm.dc, &pa_config);
}

adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
if (!adev->dm.freesync_module) {
DRM_ERROR(__drm_err("amdgpu: failed to initialize freesync_module.\n")
"amdgpu: failed to initialize freesync_module.\n")__drm_err("amdgpu: failed to initialize freesync_module.\n");
} else
DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu: freesync_module init done %p.\n"
, adev->dm.freesync_module)
		adev->dm.freesync_module)___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu: freesync_module init done %p.\n"
, adev->dm.freesync_module);

amdgpu_dm_init_color_mod();

if (adev->dm.dc->caps.max_links > 0) {
adev->dm.vblank_control_workqueue =
	create_singlethread_workqueue("dm_vblank_control_workqueue");
if (!adev->dm.vblank_control_workqueue)
	DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n")__drm_err("amdgpu: failed to initialize vblank_workqueue.\n");
}

1759#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV142) {
adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);

if (!adev->dm.hdcp_workqueue)
	DRM_ERROR("amdgpu: failed to initialize hdcp_workqueue.\n")__drm_err("amdgpu: failed to initialize hdcp_workqueue.\n");
else
	DRM_DEBUG_DRIVER("amdgpu: hdcp_workqueue init done %p.\n", adev->dm.hdcp_workqueue)___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu: hdcp_workqueue init done %p.\n"
, adev->dm.hdcp_workqueue);

dc_init_callbacks(adev->dm.dc, &init_params);
}
1770#endif
1771#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
adev->dm.crc_rd_wrk = amdgpu_dm_crtc_secure_display_create_work();
1773#endif
if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
init_completion(&adev->dm.dmub_aux_transfer_done);
adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification), GFP_KERNEL(0x0001 | 0x0004));
if (!adev->dm.dmub_notify) {
	DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify")printk("\0016" "[" "drm" "] " "amdgpu: fail to allocate adev->dm.dmub_notify"
);
	goto error;
}

adev->dm.delayed_hpd_wq = create_singlethread_workqueue("amdgpu_dm_hpd_wq");
if (!adev->dm.delayed_hpd_wq) {
	DRM_ERROR("amdgpu: failed to create hpd offload workqueue.\n")__drm_err("amdgpu: failed to create hpd offload workqueue.\n"
);
	goto error;
}

amdgpu_dm_outbox_init(adev);
if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_AUX_REPLY,
	dmub_aux_setconfig_callback, false0)) {
	DRM_ERROR("amdgpu: fail to register dmub aux callback")__drm_err("amdgpu: fail to register dmub aux callback");
	goto error;
}
if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true1)) {
	DRM_ERROR("amdgpu: fail to register dmub hpd callback")__drm_err("amdgpu: fail to register dmub hpd callback");
	goto error;
}
if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_IRQ, dmub_hpd_callback, true1)) {
	DRM_ERROR("amdgpu: fail to register dmub hpd callback")__drm_err("amdgpu: fail to register dmub hpd callback");
	goto error;
}
}

/* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
* It is expected that DMUB will resend any pending notifications at this point, for
* example HPD from DPIA.
*/
if (dc_is_dmub_outbox_supported(adev->dm.dc))
dc_enable_dmub_outbox(adev->dm.dc);

if (amdgpu_dm_initialize_drm_device(adev)) {
DRM_ERROR(__drm_err("amdgpu: failed to initialize sw for display support.\n"
)
"amdgpu: failed to initialize sw for display support.\n")__drm_err("amdgpu: failed to initialize sw for display support.\n"
);
goto error;
}

/* create fake encoders for MST */
dm_dp_create_fake_mst_encoders(adev);

/* TODO: Add_display_info? */

/* TODO use dynamic cursor width */
adev_to_drm(adev)->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
adev_to_drm(adev)->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;

if (drm_vblank_init(adev_to_drm(adev), adev->dm.display_indexes_num)) {
DRM_ERROR(__drm_err("amdgpu: failed to initialize sw for display support.\n"
)
"amdgpu: failed to initialize sw for display support.\n")__drm_err("amdgpu: failed to initialize sw for display support.\n"
);
goto error;
}


DRM_DEBUG_DRIVER("KMS initialized.\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "KMS initialized.\n");

return 0;
1836error:
amdgpu_dm_fini(adev);

return -EINVAL22;
1840}

1842static int amdgpu_dm_early_fini(void *handle)
1843{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

amdgpu_dm_audio_fini(adev);

return 0;
1849}

1851static void amdgpu_dm_fini(struct amdgpu_device *adev)
1852{
int i;

if (adev->dm.vblank_control_workqueue) {
2
←
Assuming field 'vblank_control_workqueue' is null→
3
←
Taking false branch→
destroy_workqueue(adev->dm.vblank_control_workqueue);
adev->dm.vblank_control_workqueue = NULL((void *)0);
}

amdgpu_dm_destroy_drm_device(&adev->dm);
4
←
Calling 'amdgpu_dm_destroy_drm_device'→
7
←
Returning from 'amdgpu_dm_destroy_drm_device'→

1862#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
if (adev->dm.crc_rd_wrk) {
flush_work(&adev->dm.crc_rd_wrk->notify_ta_work);
kfree(adev->dm.crc_rd_wrk);
adev->dm.crc_rd_wrk = NULL((void *)0);
}
1868#endif
1869#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.hdcp_workqueue) {
hdcp_destroy(&adev->dev->kobj, adev->dm.hdcp_workqueue);
adev->dm.hdcp_workqueue = NULL((void *)0);
}

if (adev->dm.dc)
dc_deinit_callbacks(adev->dm.dc);
1877#endif

if (adev->dm.dc)
8
←
Assuming field 'dc' is null→
9
←
Taking false branch→
dc_dmub_srv_destroy(&adev->dm.dc->ctx->dmub_srv);

if (dc_enable_dmub_notifications(adev->dm.dc)) {
10
←
Assuming the condition is false→
11
←
Taking false branch→
kfree(adev->dm.dmub_notify);
adev->dm.dmub_notify = NULL((void *)0);
destroy_workqueue(adev->dm.delayed_hpd_wq);
adev->dm.delayed_hpd_wq = NULL((void *)0);
}

if (adev->dm.dmub_bo)
12
←
Assuming field 'dmub_bo' is null→
13
←
Taking false branch→
amdgpu_bo_free_kernel(&adev->dm.dmub_bo,
		      &adev->dm.dmub_bo_gpu_addr,
		      &adev->dm.dmub_bo_cpu_addr);

if (adev->dm.hpd_rx_offload_wq) {
14
←
Assuming field 'hpd_rx_offload_wq' is non-null→
15
←
Taking true branch→
for (i = 0; i < adev->dm.dc->caps.max_links; i++) {
16
←
Dereference of null pointer
	if (adev->dm.hpd_rx_offload_wq[i].wq) {
		destroy_workqueue(adev->dm.hpd_rx_offload_wq[i].wq);
		adev->dm.hpd_rx_offload_wq[i].wq = NULL((void *)0);
	}
}

kfree(adev->dm.hpd_rx_offload_wq);
adev->dm.hpd_rx_offload_wq = NULL((void *)0);
}

/* DC Destroy TODO: Replace destroy DAL */
if (adev->dm.dc)
dc_destroy(&adev->dm.dc);
/*
* TODO: pageflip, vlank interrupt
*
* amdgpu_dm_irq_fini(adev);
*/

if (adev->dm.cgs_device) {
amdgpu_cgs_destroy_device(adev->dm.cgs_device);
adev->dm.cgs_device = NULL((void *)0);
}
if (adev->dm.freesync_module) {
mod_freesync_destroy(adev->dm.freesync_module);
adev->dm.freesync_module = NULL((void *)0);
}

mutex_destroy(&adev->dm.audio_lock);
mutex_destroy(&adev->dm.dc_lock);
mutex_destroy(&adev->dm.dpia_aux_lock);
1927}

1929static int load_dmcu_fw(struct amdgpu_device *adev)
1930{
const char *fw_name_dmcu = NULL((void *)0);
int r;
const struct dmcu_firmware_header_v1_0 *hdr;

switch (adev->asic_type) {
1936#if defined(CONFIG_DRM_AMD_DC_SI)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
1941#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_TONGA:
case CHIP_FIJI:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
case CHIP_VEGAM:
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
return 0;
case CHIP_NAVI12:
fw_name_dmcu = FIRMWARE_NAVI12_DMCU"amdgpu/navi12_dmcu.bin";
break;
case CHIP_RAVEN:
if (ASICREV_IS_PICASSO(adev->external_rev_id)((adev->external_rev_id >= 0x41) && (adev->external_rev_id
 < 0x81)))
	fw_name_dmcu = FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin";
else if (ASICREV_IS_RAVEN2(adev->external_rev_id)((adev->external_rev_id >= 0x81) && (adev->external_rev_id
 < 0x91)))
	fw_name_dmcu = FIRMWARE_RAVEN_DMCU"amdgpu/raven_dmcu.bin";
else
	return 0;
break;
default:
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)):
case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)):
case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)):
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)):
case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)):
case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)):
case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)):
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)):
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)):
case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)):
	return 0;
default:
	break;
}
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type)__drm_err("Unsupported ASIC type: 0x%X\n", adev->asic_type
);
return -EINVAL22;
}

if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n")___drm_dbg(((void *)0), DRM_UT_KMS, "dm: DMCU firmware not supported on direct or SMU loading\n"
);
return 0;
}

r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
if (r == -ENOENT2) {
/* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
DRM_DEBUG_KMS("dm: DMCU firmware not found\n")___drm_dbg(((void *)0), DRM_UT_KMS, "dm: DMCU firmware not found\n"
);
adev->dm.fw_dmcu = NULL((void *)0);
return 0;
}
if (r) {
dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
)
	fw_name_dmcu)printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't load firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
);
return r;
}

r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
if (r) {
dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't validate firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
)
	fw_name_dmcu)printf("drm:pid%d:%s *ERROR* " "amdgpu_dm: Can't validate firmware \"%s\"\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , fw_name_dmcu
);
release_firmware(adev->dm.fw_dmcu);
adev->dm.fw_dmcu = NULL((void *)0);
return r;
}

hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
adev->firmware.fw_size +=
roundup2(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->header.ucode_size_bytes)) - ((__uint32_t
)(hdr->intv_size_bytes))) + (((1 << 12)) - 1)) &
 (~((__typeof(((__uint32_t)(hdr->header.ucode_size_bytes))
 - ((__uint32_t)(hdr->intv_size_bytes))))((1 << 12))
 - 1)));

adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
adev->firmware.fw_size +=
roundup2(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->intv_size_bytes))) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(hdr->intv_size_bytes
))))((1 << 12)) - 1)));

adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));

DRM_DEBUG_KMS("PSP loading DMCU firmware\n")___drm_dbg(((void *)0), DRM_UT_KMS, "PSP loading DMCU firmware\n"
);

return 0;
2038}

2040static uint32_t amdgpu_dm_dmub_reg_read(void *ctx, uint32_t address)
2041{
struct amdgpu_device *adev = ctx;

return dm_read_reg(adev->dm.dc->ctx, address)dm_read_reg_func(adev->dm.dc->ctx, address, __func__);
2045}

2047static void amdgpu_dm_dmub_reg_write(void *ctx, uint32_t address,
		     uint32_t value)
2049{
struct amdgpu_device *adev = ctx;

return dm_write_reg(adev->dm.dc->ctx, address, value)dm_write_reg_func(adev->dm.dc->ctx, address, value, __func__
);
2053}

2055static int dm_dmub_sw_init(struct amdgpu_device *adev)
2056{
struct dmub_srv_create_params create_params;
struct dmub_srv_region_params region_params;
struct dmub_srv_region_info region_info;
struct dmub_srv_memory_params memory_params;
struct dmub_srv_fb_info *fb_info;
struct dmub_srv *dmub_srv;
const struct dmcub_firmware_header_v1_0 *hdr;
const char *fw_name_dmub;
enum dmub_asic dmub_asic;
enum dmub_status status;
int r;

switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
dmub_asic = DMUB_ASIC_DCN21;
fw_name_dmub = FIRMWARE_RENOIR_DMUB"amdgpu/renoir_dmcub.bin";
if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)((adev->external_rev_id >= 0xA1) && (adev->external_rev_id
 < 0xFF)))
	fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB"amdgpu/green_sardine_dmcub.bin";
break;
case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)):
if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)(((10) << 16) | ((3) << 8) | (0))) {
	dmub_asic = DMUB_ASIC_DCN30;
	fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB"amdgpu/sienna_cichlid_dmcub.bin";
} else {
	dmub_asic = DMUB_ASIC_DCN30;
	fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB"amdgpu/navy_flounder_dmcub.bin";
}
break;
case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)):
dmub_asic = DMUB_ASIC_DCN301;
fw_name_dmub = FIRMWARE_VANGOGH_DMUB"amdgpu/vangogh_dmcub.bin";
break;
case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)):
dmub_asic = DMUB_ASIC_DCN302;
fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB"amdgpu/dimgrey_cavefish_dmcub.bin";
break;
case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)):
dmub_asic = DMUB_ASIC_DCN303;
fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB"amdgpu/beige_goby_dmcub.bin";
break;
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
dmub_asic = (adev->external_rev_id == YELLOW_CARP_B00x20) ? DMUB_ASIC_DCN31B : DMUB_ASIC_DCN31;
fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB"amdgpu/yellow_carp_dmcub.bin";
break;
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
dmub_asic = DMUB_ASIC_DCN314;
fw_name_dmub = FIRMWARE_DCN_314_DMUB"amdgpu/dcn_3_1_4_dmcub.bin";
break;
case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)):
dmub_asic = DMUB_ASIC_DCN315;
fw_name_dmub = FIRMWARE_DCN_315_DMUB"amdgpu/dcn_3_1_5_dmcub.bin";
break;
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
dmub_asic = DMUB_ASIC_DCN316;
fw_name_dmub = FIRMWARE_DCN316_DMUB"amdgpu/dcn_3_1_6_dmcub.bin";
break;
case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)):
dmub_asic = DMUB_ASIC_DCN32;
fw_name_dmub = FIRMWARE_DCN_V3_2_0_DMCUB"amdgpu/dcn_3_2_0_dmcub.bin";
break;
case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)):
dmub_asic = DMUB_ASIC_DCN321;
fw_name_dmub = FIRMWARE_DCN_V3_2_1_DMCUB"amdgpu/dcn_3_2_1_dmcub.bin";
break;
default:
/* ASIC doesn't support DMUB. */
return 0;
}

r = request_firmware_direct(&adev->dm.dmub_fw, fw_name_dmub, adev->dev);
if (r) {
DRM_ERROR("DMUB firmware loading failed: %d\n", r)__drm_err("DMUB firmware loading failed: %d\n", r);
return 0;
}

r = amdgpu_ucode_validate(adev->dm.dmub_fw);
if (r) {
DRM_ERROR("Couldn't validate DMUB firmware: %d\n", r)__drm_err("Couldn't validate DMUB firmware: %d\n", r);
return 0;
}

hdr = (const struct dmcub_firmware_header_v1_0 *)adev->dm.dmub_fw->data;
adev->dm.dmcub_fw_version = le32_to_cpu(hdr->header.ucode_version)((__uint32_t)(hdr->header.ucode_version));

if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].ucode_id =
	AMDGPU_UCODE_ID_DMCUB;
adev->firmware.ucode[AMDGPU_UCODE_ID_DMCUB].fw =
	adev->dm.dmub_fw;
adev->firmware.fw_size +=
	roundup2(le32_to_cpu(hdr->inst_const_bytes), PAGE_SIZE)(((((__uint32_t)(hdr->inst_const_bytes))) + (((1 << 12
)) - 1)) & (~((__typeof(((__uint32_t)(hdr->inst_const_bytes
))))((1 << 12)) - 1)));

DRM_INFO("Loading DMUB firmware via PSP: version=0x%08X\n",printk("\0016" "[" "drm" "] " "Loading DMUB firmware via PSP: version=0x%08X\n"
, adev->dm.dmcub_fw_version)
	 adev->dm.dmcub_fw_version)printk("\0016" "[" "drm" "] " "Loading DMUB firmware via PSP: version=0x%08X\n"
, adev->dm.dmcub_fw_version);
}


adev->dm.dmub_srv = kzalloc(sizeof(*adev->dm.dmub_srv), GFP_KERNEL(0x0001 | 0x0004));
dmub_srv = adev->dm.dmub_srv;

if (!dmub_srv) {
DRM_ERROR("Failed to allocate DMUB service!\n")__drm_err("Failed to allocate DMUB service!\n");
return -ENOMEM12;
}

memset(&create_params, 0, sizeof(create_params))__builtin_memset((&create_params), (0), (sizeof(create_params
)));
create_params.user_ctx = adev;
create_params.funcs.reg_read = amdgpu_dm_dmub_reg_read;
create_params.funcs.reg_write = amdgpu_dm_dmub_reg_write;
create_params.asic = dmub_asic;

/* Create the DMUB service. */
status = dmub_srv_create(dmub_srv, &create_params);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error creating DMUB service: %d\n", status)__drm_err("Error creating DMUB service: %d\n", status);
return -EINVAL22;
}

/* Calculate the size of all the regions for the DMUB service. */
memset(&region_params, 0, sizeof(region_params))__builtin_memset((&region_params), (0), (sizeof(region_params
)));

region_params.inst_const_size = le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) -
			PSP_HEADER_BYTES0x100 - PSP_FOOTER_BYTES0x100;
region_params.bss_data_size = le32_to_cpu(hdr->bss_data_bytes)((__uint32_t)(hdr->bss_data_bytes));
region_params.vbios_size = adev->bios_size;
region_params.fw_bss_data = region_params.bss_data_size ?
adev->dm.dmub_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
le32_to_cpu(hdr->inst_const_bytes)((__uint32_t)(hdr->inst_const_bytes)) : NULL((void *)0);
region_params.fw_inst_const =
adev->dm.dmub_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes)((__uint32_t)(hdr->header.ucode_array_offset_bytes)) +
PSP_HEADER_BYTES0x100;
region_params.is_mailbox_in_inbox = false0;

status = dmub_srv_calc_region_info(dmub_srv, &region_params,
			   &region_info);

if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error calculating DMUB region info: %d\n", status)__drm_err("Error calculating DMUB region info: %d\n", status);
return -EINVAL22;
}

/*
* Allocate a framebuffer based on the total size of all the regions.
* TODO: Move this into GART.
*/
r = amdgpu_bo_create_kernel(adev, region_info.fb_size, PAGE_SIZE(1 << 12),
		    AMDGPU_GEM_DOMAIN_VRAM0x4, &adev->dm.dmub_bo,
		    &adev->dm.dmub_bo_gpu_addr,
		    &adev->dm.dmub_bo_cpu_addr);
if (r)
return r;

/* Rebase the regions on the framebuffer address. */
memset(&memory_params, 0, sizeof(memory_params))__builtin_memset((&memory_params), (0), (sizeof(memory_params
)));
memory_params.cpu_fb_addr = adev->dm.dmub_bo_cpu_addr;
memory_params.gpu_fb_addr = adev->dm.dmub_bo_gpu_addr;
memory_params.region_info = &region_info;

adev->dm.dmub_fb_info =
kzalloc(sizeof(*adev->dm.dmub_fb_info), GFP_KERNEL(0x0001 | 0x0004));
fb_info = adev->dm.dmub_fb_info;

if (!fb_info) {
DRM_ERROR(__drm_err("Failed to allocate framebuffer info for DMUB service!\n"
)
	"Failed to allocate framebuffer info for DMUB service!\n")__drm_err("Failed to allocate framebuffer info for DMUB service!\n"
);
return -ENOMEM12;
}

status = dmub_srv_calc_mem_info(dmub_srv, &memory_params, fb_info);
if (status != DMUB_STATUS_OK) {
DRM_ERROR("Error calculating DMUB FB info: %d\n", status)__drm_err("Error calculating DMUB FB info: %d\n", status);
return -EINVAL22;
}

return 0;
2235}

2237static int dm_sw_init(void *handle)
2238{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;

r = dm_dmub_sw_init(adev);
if (r)
return r;

return load_dmcu_fw(adev);
2247}

2249static int dm_sw_fini(void *handle)
2250{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

kfree(adev->dm.dmub_fb_info);
adev->dm.dmub_fb_info = NULL((void *)0);

if (adev->dm.dmub_srv) {
dmub_srv_destroy(adev->dm.dmub_srv);
adev->dm.dmub_srv = NULL((void *)0);
}

release_firmware(adev->dm.dmub_fw);
adev->dm.dmub_fw = NULL((void *)0);

release_firmware(adev->dm.fw_dmcu);
adev->dm.fw_dmcu = NULL((void *)0);

return 0;
2268}

2270static int detect_mst_link_for_all_connectors(struct drm_device *dev)
2271{
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
int ret = 0;

drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->dc_link->type == dc_connection_mst_branch &&
    aconnector->mst_mgr.aux) {
	DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n"
, aconnector, aconnector->base.base.id)
			 aconnector,___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n"
, aconnector, aconnector->base.base.id)
			 aconnector->base.base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM_MST: starting TM on aconnector: %p [id: %d]\n"
, aconnector, aconnector->base.base.id);

	ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true1);
	if (ret < 0) {
		DRM_ERROR("DM_MST: Failed to start MST\n")__drm_err("DM_MST: Failed to start MST\n");
		aconnector->dc_link->type =
			dc_connection_single;
		ret = dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
						     aconnector->dc_link);
		break;
	}
}
}
drm_connector_list_iter_end(&iter);

return ret;
2300}

2302static int dm_late_init(void *handle)
2303{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

struct dmcu_iram_parameters params;
unsigned int linear_lut[16];
int i;
struct dmcu *dmcu = NULL((void *)0);

dmcu = adev->dm.dc->res_pool->dmcu;

for (i = 0; i < 16; i++)
linear_lut[i] = 0xFFFF * i / 15;

params.set = 0;
params.backlight_ramping_override = false0;
params.backlight_ramping_start = 0xCCCC;
params.backlight_ramping_reduction = 0xCCCCCCCC;
params.backlight_lut_array_size = 16;
params.backlight_lut_array = linear_lut;

/* Min backlight level after ABM reduction,  Don't allow below 1%
* 0xFFFF x 0.01 = 0x28F
*/
params.min_abm_backlight = 0x28F;
/* In the case where abm is implemented on dmcub,
* dmcu object will be null.
* ABM 2.4 and up are implemented on dmcub.
*/
if (dmcu) {
if (!dmcu_load_iram(dmcu, params))
	return -EINVAL22;
} else if (adev->dm.dc->ctx->dmub_srv) {
struct dc_link *edp_links[MAX_NUM_EDP2];
int edp_num;

get_edp_links(adev->dm.dc, edp_links, &edp_num);
for (i = 0; i < edp_num; i++) {
	if (!dmub_init_abm_config(adev->dm.dc->res_pool, params, i))
		return -EINVAL22;
}
}

return detect_mst_link_for_all_connectors(adev_to_drm(adev));
2346}

2348static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
2349{
int ret;
u8 guid[16];
u64 tmp64;

mutex_lock(&mgr->lock)rw_enter_write(&mgr->lock);
if (!mgr->mst_primary)
goto out_fail;

if (drm_dp_read_dpcd_caps(mgr->aux, mgr->dpcd) < 0) {
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)->
dev : ((void *)0), DRM_UT_KMS, "dpcd read failed - undocked during suspend?\n"
);
goto out_fail;
}

ret = drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL0x111,
		 DP_MST_EN(1 << 0) |
		 DP_UP_REQ_EN(1 << 1) |
		 DP_UPSTREAM_IS_SRC(1 << 2));
if (ret < 0) {
drm_dbg_kms(mgr->dev, "mst write failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)->
dev : ((void *)0), DRM_UT_KMS, "mst write failed - undocked during suspend?\n"
);
goto out_fail;
}

/* Some hubs forget their guids after they resume */
ret = drm_dp_dpcd_read(mgr->aux, DP_GUID0x030, guid, 16);
if (ret != 16) {
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)->
dev : ((void *)0), DRM_UT_KMS, "dpcd read failed - undocked during suspend?\n"
);
goto out_fail;
}

if (memchr_inv(guid, 0, 16) == NULL((void *)0)) {
tmp64 = get_jiffies_64();
memcpy(&guid[0], &tmp64, sizeof(u64))__builtin_memcpy((&guid[0]), (&tmp64), (sizeof(u64)));
memcpy(&guid[8], &tmp64, sizeof(u64))__builtin_memcpy((&guid[8]), (&tmp64), (sizeof(u64)));

ret = drm_dp_dpcd_write(mgr->aux, DP_GUID0x030, guid, 16);

if (ret != 16) {
	drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n")__drm_dev_dbg(((void *)0), (mgr->dev) ? (mgr->dev)->
dev : ((void *)0), DRM_UT_KMS, "check mstb guid failed - undocked during suspend?\n"
);
	goto out_fail;
}
}

memcpy(mgr->mst_primary->guid, guid, 16)__builtin_memcpy((mgr->mst_primary->guid), (guid), (16)
);

2394out_fail:
mutex_unlock(&mgr->lock)rw_exit_write(&mgr->lock);
2396}

2398static void s3_handle_mst(struct drm_device *dev, bool_Bool suspend)
2399{
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct drm_dp_mst_topology_mgr *mgr;

drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->dc_link->type != dc_connection_mst_branch ||
    aconnector->mst_port)
	continue;

mgr = &aconnector->mst_mgr;

if (suspend) {
	drm_dp_mst_topology_mgr_suspend(mgr);
} else {
	/* if extended timeout is supported in hardware,
	 * default to LTTPR timeout (3.2ms) first as a W/A for DP link layer
	 * CTS 4.2.1.1 regression introduced by CTS specs requirement update.
	 */
	dc_link_aux_try_to_configure_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD3200);
	if (!dp_is_lttpr_present(aconnector->dc_link))
		dc_link_aux_try_to_configure_timeout(aconnector->dc_link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD552);

	/* TODO: move resume_mst_branch_status() into drm mst resume again
	 * once topology probing work is pulled out from mst resume into mst
	 * resume 2nd step. mst resume 2nd step should be called after old
	 * state getting restored (i.e. drm_atomic_helper_resume()).
	 */
	resume_mst_branch_status(mgr);
}
}
drm_connector_list_iter_end(&iter);
2434}

2436static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
2437{
int ret = 0;

/* This interface is for dGPU Navi1x.Linux dc-pplib interface depends
* on window driver dc implementation.
* For Navi1x, clock settings of dcn watermarks are fixed. the settings
* should be passed to smu during boot up and resume from s3.
* boot up: dc calculate dcn watermark clock settings within dc_create,
* dcn20_resource_construct
* then call pplib functions below to pass the settings to smu:
* smu_set_watermarks_for_clock_ranges
* smu_set_watermarks_table
* navi10_set_watermarks_table
* smu_write_watermarks_table
*
* For Renoir, clock settings of dcn watermark are also fixed values.
* dc has implemented different flow for window driver:
* dc_hardware_init / dc_set_power_state
* dcn10_init_hw
* notify_wm_ranges
* set_wm_ranges
* -- Linux
* smu_set_watermarks_for_clock_ranges
* renoir_set_watermarks_table
* smu_write_watermarks_table
*
* For Linux,
* dc_hardware_init -> amdgpu_dm_init
* dc_set_power_state --> dm_resume
*
* therefore, this function apply to navi10/12/14 but not Renoir
* *
*/
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)):
case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)):
break;
default:
return 0;
}

ret = amdgpu_dpm_write_watermarks_table(adev);
if (ret) {
DRM_ERROR("Failed to update WMTABLE!\n")__drm_err("Failed to update WMTABLE!\n");
return ret;
}

return 0;
2485}

2487/**
* dm_hw_init() - Initialize DC device
* @handle: The base driver device containing the amdgpu_dm device.
*
* Initialize the &struct amdgpu_display_manager device. This involves calling
* the initializers of each DM component, then populating the struct with them.
*
* Although the function implies hardware initialization, both hardware and
* software are initialized here. Splitting them out to their relevant init
* hooks is a future TODO item.
*
* Some notable things that are initialized here:
*
* - Display Core, both software and hardware
* - DC modules that we need (freesync and color management)
* - DRM software states
* - Interrupt sources and handlers
* - Vblank support
* - Debug FS entries, if enabled
*/
2507static int dm_hw_init(void *handle)
2508{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
/* Create DAL display manager */
amdgpu_dm_init(adev);
amdgpu_dm_hpd_init(adev);

return 0;
2515}

2517/**
* dm_hw_fini() - Teardown DC device
* @handle: The base driver device containing the amdgpu_dm device.
*
* Teardown components within &struct amdgpu_display_manager that require
* cleanup. This involves cleaning up the DRM device, DC, and any modules that
* were loaded. Also flush IRQ workqueues and disable them.
*/
2525static int dm_hw_fini(void *handle)
2526{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;

amdgpu_dm_hpd_fini(adev);

amdgpu_dm_irq_fini(adev);
amdgpu_dm_fini(adev);
1
Calling 'amdgpu_dm_fini'→
return 0;
2534}


2537static void dm_gpureset_toggle_interrupts(struct amdgpu_device *adev,
		 struct dc_state *state, bool_Bool enable)
2539{
enum dc_irq_source irq_source;
struct amdgpu_crtc *acrtc;
int rc = -EBUSY16;
int i = 0;

for (i = 0; i < state->stream_count; i++) {
acrtc = get_crtc_by_otg_inst(
		adev, state->stream_status[i].primary_otg_inst);

if (acrtc && state->stream_status[i].plane_count != 0) {
	irq_source = IRQ_TYPE_PFLIP + acrtc->otg_inst;
	rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY16;
	DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",___drm_dbg(((void *)0), DRM_UT_VBL, "crtc %d - vupdate irq %sabling: r=%d\n"
, acrtc->crtc_id, enable ? "en" : "dis", rc)
		      acrtc->crtc_id, enable ? "en" : "dis", rc)___drm_dbg(((void *)0), DRM_UT_VBL, "crtc %d - vupdate irq %sabling: r=%d\n"
, acrtc->crtc_id, enable ? "en" : "dis", rc);
	if (rc)
		DRM_WARN("Failed to %s pflip interrupts\n",printk("\0014" "[" "drm" "] " "Failed to %s pflip interrupts\n"
, enable ? "enable" : "disable")
			 enable ? "enable" : "disable")printk("\0014" "[" "drm" "] " "Failed to %s pflip interrupts\n"
, enable ? "enable" : "disable");

	if (enable) {
		rc = dm_enable_vblank(&acrtc->base);
		if (rc)
			DRM_WARN("Failed to enable vblank interrupts\n")printk("\0014" "[" "drm" "] " "Failed to enable vblank interrupts\n"
);
	} else {
		dm_disable_vblank(&acrtc->base);
	}

}
}

2569}

2571static enum dc_status amdgpu_dm_commit_zero_streams(struct dc *dc)
2572{
struct dc_state *context = NULL((void *)0);
enum dc_status res = DC_ERROR_UNEXPECTED;
int i;
struct dc_stream_state *del_streams[MAX_PIPES6];
int del_streams_count = 0;

memset(del_streams, 0, sizeof(del_streams))__builtin_memset((del_streams), (0), (sizeof(del_streams)));

context = dc_create_state(dc);
if (context == NULL((void *)0))
goto context_alloc_fail;

dc_resource_state_copy_construct_current(dc, context);

/* First remove from context all streams */
for (i = 0; i < context->stream_count; i++) {
struct dc_stream_state *stream = context->streams[i];

del_streams[del_streams_count++] = stream;
}

/* Remove all planes for removed streams and then remove the streams */
for (i = 0; i < del_streams_count; i++) {
if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
	res = DC_FAIL_DETACH_SURFACES;
	goto fail;
}

res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
if (res != DC_OK)
	goto fail;
}

res = dc_commit_state(dc, context);

2608fail:
dc_release_state(context);

2611context_alloc_fail:
return res;
2613}

2615static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm)
2616{
int i;

if (dm->hpd_rx_offload_wq) {
for (i = 0; i < dm->dc->caps.max_links; i++)
	flush_workqueue(dm->hpd_rx_offload_wq[i].wq);
}
2623}

2625static int dm_suspend(void *handle)
2626{
struct amdgpu_device *adev = handle;
struct amdgpu_display_manager *dm = &adev->dm;
int ret = 0;

if (amdgpu_in_reset(adev)) {
mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);

dc_allow_idle_optimizations(adev->dm.dc, false0);

dm->cached_dc_state = dc_copy_state(dm->dc->current_state);

dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, false0);

amdgpu_dm_commit_zero_streams(dm->dc);

amdgpu_dm_irq_suspend(adev);

hpd_rx_irq_work_suspend(dm);

return ret;
}

WARN_ON(adev->dm.cached_state)({ int __ret = !!(adev->dm.cached_state); if (__ret) printf
("WARNING %s failed at %s:%d\n", "adev->dm.cached_state", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 2649); __builtin_expect(!!(__ret), 0); });
adev->dm.cached_state = drm_atomic_helper_suspend(adev_to_drm(adev));

s3_handle_mst(adev_to_drm(adev), true1);

amdgpu_dm_irq_suspend(adev);

hpd_rx_irq_work_suspend(dm);

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);

return 0;
2661}

2663struct amdgpu_dm_connector *
2664amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
			     struct drm_crtc *crtc)
2666{
u32 i;
struct drm_connector_state *new_con_state;
struct drm_connector *connector;
struct drm_crtc *crtc_from_state;

for_each_new_connector_in_state(state, connector, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (new_con_state) =
 (state)->connectors[i].new_state, (void)(new_con_state) ,
 1))) {} else {
crtc_from_state = new_con_state->crtc;

if (crtc_from_state == crtc)
	return to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
}

return NULL((void *)0);
2680}

2682static void emulated_link_detect(struct dc_link *link)
2683{
struct dc_sink_init_data sink_init_data = { 0 };
struct display_sink_capability sink_caps = { 0 };
enum dc_edid_status edid_status;
struct dc_context *dc_ctx = link->ctx;
struct dc_sink *sink = NULL((void *)0);
struct dc_sink *prev_sink = NULL((void *)0);

link->type = dc_connection_none;
prev_sink = link->local_sink;

if (prev_sink)
dc_sink_release(prev_sink);

switch (link->connector_signal) {
case SIGNAL_TYPE_HDMI_TYPE_A: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
break;
}

case SIGNAL_TYPE_DVI_SINGLE_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
break;
}

case SIGNAL_TYPE_DVI_DUAL_LINK: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
break;
}

case SIGNAL_TYPE_LVDS: {
sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
sink_caps.signal = SIGNAL_TYPE_LVDS;
break;
}

case SIGNAL_TYPE_EDP: {
sink_caps.transaction_type =
	DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_EDP;
break;
}

case SIGNAL_TYPE_DISPLAY_PORT: {
sink_caps.transaction_type =
	DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
break;
}

default:
DC_ERROR("Invalid connector type! signal:%d\n",do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n"
, link->connector_signal); } while (0)
	link->connector_signal)do { (void)(dc_ctx); __drm_err("Invalid connector type! signal:%d\n"
, link->connector_signal); } while (0);
return;
}

sink_init_data.link = link;
sink_init_data.sink_signal = sink_caps.signal;

sink = dc_sink_create(&sink_init_data);
if (!sink) {
DC_ERROR("Failed to create sink!\n")do { (void)(dc_ctx); __drm_err("Failed to create sink!\n"); }
 while (0);
return;
}

/* dc_sink_create returns a new reference */
link->local_sink = sink;

edid_status = dm_helpers_read_local_edid(
	link->ctx,
	link,
	sink);

if (edid_status != EDID_OK)
DC_ERROR("Failed to read EDID")do { (void)(dc_ctx); __drm_err("Failed to read EDID"); } while
 (0);

2762}

2764static void dm_gpureset_commit_state(struct dc_state *dc_state,
		     struct amdgpu_display_manager *dm)
2766{
struct {
struct dc_surface_update surface_updates[MAX_SURFACES3];
struct dc_plane_info plane_infos[MAX_SURFACES3];
struct dc_scaling_info scaling_infos[MAX_SURFACES3];
struct dc_flip_addrs flip_addrs[MAX_SURFACES3];
struct dc_stream_update stream_update;
} *bundle;
int k, m;

bundle = kzalloc(sizeof(*bundle), GFP_KERNEL(0x0001 | 0x0004));

if (!bundle) {
dm_error("Failed to allocate update bundle\n")__drm_err("Failed to allocate update bundle\n");
goto cleanup;
}

for (k = 0; k < dc_state->stream_count; k++) {
bundle->stream_update.stream = dc_state->streams[k];

for (m = 0; m < dc_state->stream_status->plane_count; m++) {
	bundle->surface_updates[m].surface =
		dc_state->stream_status->plane_states[m];
	bundle->surface_updates[m].surface->force_full_update =
		true1;
}

update_planes_and_stream_adapter(dm->dc,
			 UPDATE_TYPE_FULL,
			 dc_state->stream_status->plane_count,
			 dc_state->streams[k],
			 &bundle->stream_update,
			 bundle->surface_updates);
}

2801cleanup:
kfree(bundle);
2803}

2805static int dm_resume(void *handle)
2806{
struct amdgpu_device *adev = handle;
struct drm_device *ddev = adev_to_drm(adev);
struct amdgpu_display_manager *dm = &adev->dm;
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
struct drm_crtc *crtc;
struct drm_crtc_state *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state;
struct drm_plane *plane;
struct drm_plane_state *new_plane_state;
struct dm_plane_state *dm_new_plane_state;
struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (dm->atomic_obj.state); (struct dm_atomic_state *
)( (char *)__mptr - __builtin_offsetof(struct dm_atomic_state
, base) );});
enum dc_connection_type new_connection_type = dc_connection_none;
struct dc_state *dc_state;
int i, r, j, ret;
bool_Bool need_hotplug = false0;

if (amdgpu_in_reset(adev)) {
dc_state = dm->cached_dc_state;

/*
 * The dc->current_state is backed up into dm->cached_dc_state
 * before we commit 0 streams.
 *
 * DC will clear link encoder assignments on the real state
 * but the changes won't propagate over to the copy we made
 * before the 0 streams commit.
 *
 * DC expects that link encoder assignments are *not* valid
 * when committing a state, so as a workaround we can copy
 * off of the current state.
 *
 * We lose the previous assignments, but we had already
 * commit 0 streams anyway.
 */
link_enc_cfg_copy(adev->dm.dc->current_state, dc_state);

r = dm_dmub_hw_init(adev);
if (r)
	DRM_ERROR("DMUB interface failed to initialize: status=%d\n", r)__drm_err("DMUB interface failed to initialize: status=%d\n",
 r);

dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
dc_resume(dm->dc);

amdgpu_dm_irq_resume_early(adev);

for (i = 0; i < dc_state->stream_count; i++) {
	dc_state->streams[i]->mode_changed = true1;
	for (j = 0; j < dc_state->stream_status[i].plane_count; j++) {
		dc_state->stream_status[i].plane_states[j]->update_flags.raw
			= 0xffffffff;
	}
}

if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
	amdgpu_dm_outbox_init(adev);
	dc_enable_dmub_outbox(adev->dm.dc);
}

WARN_ON(!dc_commit_state(dm->dc, dc_state))({ int __ret = !!(!dc_commit_state(dm->dc, dc_state)); if (
__ret) printf("WARNING %s failed at %s:%d\n", "!dc_commit_state(dm->dc, dc_state)"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 2867); __builtin_expect(!!(__ret), 0); });

dm_gpureset_commit_state(dm->cached_dc_state, dm);

dm_gpureset_toggle_interrupts(adev, dm->cached_dc_state, true1);

dc_release_state(dm->cached_dc_state);
dm->cached_dc_state = NULL((void *)0);

amdgpu_dm_irq_resume_late(adev);

mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);

return 0;
}
/* Recreate dc_state - DC invalidates it when setting power state to S3. */
dc_release_state(dm_state->context);
dm_state->context = dc_create_state(dm->dc);
/* TODO: Remove dc_state->dccg, use dc->dccg directly. */
dc_resource_state_construct(dm->dc, dm_state->context);

/* Before powering on DC we need to re-initialize DMUB. */
dm_dmub_hw_resume(adev);

/* Re-enable outbox interrupts for DPIA. */
if (dc_is_dmub_outbox_supported(adev->dm.dc)) {
amdgpu_dm_outbox_init(adev);
dc_enable_dmub_outbox(adev->dm.dc);
}

/* power on hardware */
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);

/* program HPD filter */
dc_resume(dm->dc);

/*
* early enable HPD Rx IRQ, should be done before set mode as short
* pulse interrupts are used for MST
*/
amdgpu_dm_irq_resume_early(adev);

/* On resume we need to rewrite the MSTM control bits to enable MST*/
s3_handle_mst(ddev, false0);

/* Do detection*/
drm_connector_list_iter_begin(ddev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (!aconnector->dc_link)
	continue;

/*
 * this is the case when traversing through already created end sink
 * MST connectors, should be skipped
 */
if (aconnector && aconnector->mst_port)
	continue;

mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);
if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
	DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
	emulated_link_detect(aconnector->dc_link);
} else {
	mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
	dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
	mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

if (aconnector->fake_enable && aconnector->dc_link->local_sink)
	aconnector->fake_enable = false0;

if (aconnector->dc_sink)
	dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL((void *)0);
amdgpu_dm_update_connector_after_detect(aconnector);
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);
}
drm_connector_list_iter_end(&iter);

/* Force mode set in atomic commit */
for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config
.num_crtc; (i)++) if (!((dm->cached_state)->crtcs[i].ptr
 && ((crtc) = (dm->cached_state)->crtcs[i].ptr,
 (void)(crtc) , (new_crtc_state) = (dm->cached_state)->
crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else
new_crtc_state->active_changed = true1;

/*
* atomic_check is expected to create the dc states. We need to release
* them here, since they were duplicated as part of the suspend
* procedure.
*/
for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config
.num_crtc; (i)++) if (!((dm->cached_state)->crtcs[i].ptr
 && ((crtc) = (dm->cached_state)->crtcs[i].ptr,
 (void)(crtc) , (new_crtc_state) = (dm->cached_state)->
crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
if (dm_new_crtc_state->stream) {
	WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1)({ int __ret = !!(kref_read(&dm_new_crtc_state->stream
->refcount) > 1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "kref_read(&dm_new_crtc_state->stream->refcount) > 1"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 2962); __builtin_expect(!!(__ret), 0); });
	dc_stream_release(dm_new_crtc_state->stream);
	dm_new_crtc_state->stream = NULL((void *)0);
}
}

for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i)for ((i) = 0; (i) < (dm->cached_state)->dev->mode_config
.num_total_plane; (i)++) if (!((dm->cached_state)->planes
[i].ptr && ((plane) = (dm->cached_state)->planes
[i].ptr, (void)(plane) , (new_plane_state) = (dm->cached_state
)->planes[i].new_state, (void)(new_plane_state) , 1))) {} else {
dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
if (dm_new_plane_state->dc_state) {
	WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1)({ int __ret = !!(kref_read(&dm_new_plane_state->dc_state
->refcount) > 1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "kref_read(&dm_new_plane_state->dc_state->refcount) > 1"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 2971); __builtin_expect(!!(__ret), 0); });
	dc_plane_state_release(dm_new_plane_state->dc_state);
	dm_new_plane_state->dc_state = NULL((void *)0);
}
}

drm_atomic_helper_resume(ddev, dm->cached_state);

dm->cached_state = NULL((void *)0);

/* Do mst topology probing after resuming cached state*/
drm_connector_list_iter_begin(ddev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (aconnector->dc_link->type != dc_connection_mst_branch ||
    aconnector->mst_port)
	continue;

ret = drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr, true1);

if (ret < 0) {
	dm_helpers_dp_mst_stop_top_mgr(aconnector->dc_link->ctx,
			aconnector->dc_link);
	need_hotplug = true1;
}
}
drm_connector_list_iter_end(&iter);

if (need_hotplug)
drm_kms_helper_hotplug_event(ddev);

amdgpu_dm_irq_resume_late(adev);

amdgpu_dm_smu_write_watermarks_table(adev);

return 0;
3007}

3009/**
* DOC: DM Lifecycle
*
* DM (and consequently DC) is registered in the amdgpu base driver as a IP
* block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
* the base driver's device list to be initialized and torn down accordingly.
*
* The functions to do so are provided as hooks in &struct amd_ip_funcs.
*/

3019static const struct amd_ip_funcs amdgpu_dm_funcs = {
.name = "dm",
.early_init = dm_early_init,
.late_init = dm_late_init,
.sw_init = dm_sw_init,
.sw_fini = dm_sw_fini,
.early_fini = amdgpu_dm_early_fini,
.hw_init = dm_hw_init,
.hw_fini = dm_hw_fini,
.suspend = dm_suspend,
.resume = dm_resume,
.is_idle = dm_is_idle,
.wait_for_idle = dm_wait_for_idle,
.check_soft_reset = dm_check_soft_reset,
.soft_reset = dm_soft_reset,
.set_clockgating_state = dm_set_clockgating_state,
.set_powergating_state = dm_set_powergating_state,
3036};

3038const struct amdgpu_ip_block_version dm_ip_block = {
.type = AMD_IP_BLOCK_TYPE_DCE,
.major = 1,
.minor = 0,
.rev = 0,
.funcs = &amdgpu_dm_funcs,
3044};


3047/**
* DOC: atomic
*
* *WIP*
*/

3053static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
.fb_create = amdgpu_display_user_framebuffer_create,
.get_format_info = amd_get_format_info,
.atomic_check = amdgpu_dm_atomic_check,
.atomic_commit = drm_atomic_helper_commit,
3058};

3060static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
.atomic_commit_tail = amdgpu_dm_atomic_commit_tail,
.atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
3063};

3065static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector)
3066{
struct amdgpu_dm_backlight_caps *caps;
struct amdgpu_display_manager *dm;
struct drm_connector *conn_base;
struct amdgpu_device *adev;
struct dc_link *link = NULL((void *)0);
struct drm_luminance_range_info *luminance_range;
int i;

if (!aconnector || !aconnector->dc_link)
return;

link = aconnector->dc_link;
if (link->connector_signal != SIGNAL_TYPE_EDP)
return;

conn_base = &aconnector->base;
adev = drm_to_adev(conn_base->dev);
dm = &adev->dm;
for (i = 0; i < dm->num_of_edps; i++) {
if (link == dm->backlight_link[i])
	break;
}
if (i >= dm->num_of_edps)
return;
caps = &dm->backlight_caps[i];
caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;
caps->aux_support = false0;

if (caps->ext_caps->bits.oled == 1
   /*
    * ||
    * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||
    * caps->ext_caps->bits.hdr_aux_backlight_control == 1
    */)
caps->aux_support = true1;

if (amdgpu_backlight == 0)
caps->aux_support = false0;
else if (amdgpu_backlight == 1)
caps->aux_support = true1;

luminance_range = &conn_base->display_info.luminance_range;
caps->aux_min_input_signal = luminance_range->min_luminance;
caps->aux_max_input_signal = luminance_range->max_luminance;
3111}

3113void amdgpu_dm_update_connector_after_detect(
struct amdgpu_dm_connector *aconnector)
3115{
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
struct dc_sink *sink;

/* MST handled by drm_mst framework */
if (aconnector->mst_mgr.mst_state == true1)
return;

sink = aconnector->dc_link->local_sink;
if (sink)
dc_sink_retain(sink);

/*
* Edid mgmt connector gets first update only in mode_valid hook and then
* the connector sink is set to either fake or physical sink depends on link status.
* Skip if already done during boot.
*/
if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
	&& aconnector->dc_em_sink) {

/*
 * For S3 resume with headless use eml_sink to fake stream
 * because on resume connector->sink is set to NULL
 */
mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex);

if (sink) {
	if (aconnector->dc_sink) {
		amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
		/*
		 * retain and release below are used to
		 * bump up refcount for sink because the link doesn't point
		 * to it anymore after disconnect, so on next crtc to connector
		 * reshuffle by UMD we will get into unwanted dc_sink release
		 */
		dc_sink_release(aconnector->dc_sink);
	}
	aconnector->dc_sink = sink;
	dc_sink_retain(aconnector->dc_sink);
	amdgpu_dm_update_freesync_caps(connector,
			aconnector->edid);
} else {
	amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
	if (!aconnector->dc_sink) {
		aconnector->dc_sink = aconnector->dc_em_sink;
		dc_sink_retain(aconnector->dc_sink);
	}
}

mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex);

if (sink)
	dc_sink_release(sink);
return;
}

/*
* TODO: temporary guard to look for proper fix
* if this sink is MST sink, we should not do anything
*/
if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
dc_sink_release(sink);
return;
}

if (aconnector->dc_sink == sink) {
/*
 * We got a DP short pulse (Link Loss, DP CTS, etc...).
 * Do nothing!!
 */
DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: dc_sink didn't change.\n"
, aconnector->connector_id)
		aconnector->connector_id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: dc_sink didn't change.\n"
, aconnector->connector_id);
if (sink)
	dc_sink_release(sink);
return;
}

DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n"
, aconnector->connector_id, aconnector->dc_sink, sink)
aconnector->connector_id, aconnector->dc_sink, sink)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DCHPD: connector_id=%d: Old sink=%p New sink=%p\n"
, aconnector->connector_id, aconnector->dc_sink, sink);

mutex_lock(&dev->mode_config.mutex)rw_enter_write(&dev->mode_config.mutex);

/*
* 1. Update status of the drm connector
* 2. Send an event and let userspace tell us what to do
*/
if (sink) {
/*
 * TODO: check if we still need the S3 mode update workaround.
 * If yes, put it here.
 */
if (aconnector->dc_sink) {
	amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
	dc_sink_release(aconnector->dc_sink);
}

aconnector->dc_sink = sink;
dc_sink_retain(aconnector->dc_sink);
if (sink->dc_edid.length == 0) {
	aconnector->edid = NULL((void *)0);
	if (aconnector->dc_link->aux_mode) {
		drm_dp_cec_unset_edid(
			&aconnector->dm_dp_aux.aux);
	}
} else {
	aconnector->edid =
		(struct edid *)sink->dc_edid.raw_edid;

	if (aconnector->dc_link->aux_mode)
		drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
				    aconnector->edid);
}

aconnector->timing_requested = kzalloc(sizeof(struct dc_crtc_timing), GFP_KERNEL(0x0001 | 0x0004));
if (!aconnector->timing_requested)
	dm_error("%s: failed to create aconnector->requested_timing\n", __func__)__drm_err("%s: failed to create aconnector->requested_timing\n"
, __func__);

drm_connector_update_edid_property(connector, aconnector->edid);
amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
update_connector_ext_caps(aconnector);
} else {
drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
amdgpu_dm_update_freesync_caps(connector, NULL((void *)0));
drm_connector_update_edid_property(connector, NULL((void *)0));
aconnector->num_modes = 0;
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL((void *)0);
aconnector->edid = NULL((void *)0);
kfree(aconnector->timing_requested);
aconnector->timing_requested = NULL((void *)0);
3246#ifdef CONFIG_DRM_AMD_DC_HDCP
/* Set CP to DESIRED if it was ENABLED, so we can re-enable it again on hotplug */
if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2)
	connector->state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
3250#endif
}

mutex_unlock(&dev->mode_config.mutex)rw_exit_write(&dev->mode_config.mutex);

update_subconnector_property(aconnector);

if (sink)
dc_sink_release(sink);
3259}

3261static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector)
3262{
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
enum dc_connection_type new_connection_type = dc_connection_none;
struct amdgpu_device *adev = drm_to_adev(dev);
3267#ifdef CONFIG_DRM_AMD_DC_HDCP
struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});
3269#endif
bool_Bool ret = false0;

if (adev->dm.disable_hpd_irq)
return;

/*
* In case of failure or MST no need to update connector status or notify the OS
* since (for MST case) MST does this in its own context.
*/
mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);

3281#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.hdcp_workqueue) {
hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
dm_con_state->update_hdcp = true1;
}
3286#endif
if (aconnector->fake_enable)
aconnector->fake_enable = false0;

aconnector->timing_changed = false0;

if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
emulated_link_detect(aconnector->dc_link);

drm_modeset_lock_all(dev);
dm_restore_drm_connector_state(dev, connector);
drm_modeset_unlock_all(dev);

if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
	drm_kms_helper_connector_hotplug_event(connector);
} else {
mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
if (ret) {
	amdgpu_dm_update_connector_after_detect(aconnector);

	drm_modeset_lock_all(dev);
	dm_restore_drm_connector_state(dev, connector);
	drm_modeset_unlock_all(dev);

	if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
		drm_kms_helper_connector_hotplug_event(connector);
}
}
mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);

3321}

3323static void handle_hpd_irq(void *param)
3324{
struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;

handle_hpd_irq_helper(aconnector);

3329}

3331static void schedule_hpd_rx_offload_work(struct hpd_rx_irq_offload_work_queue *offload_wq,
					union hpd_irq_data hpd_irq_data)
3333{
struct hpd_rx_irq_offload_work *offload_work =
		kzalloc(sizeof(*offload_work), GFP_KERNEL(0x0001 | 0x0004));

if (!offload_work) {
DRM_ERROR("Failed to allocate hpd_rx_irq_offload_work.\n")__drm_err("Failed to allocate hpd_rx_irq_offload_work.\n");
return;
}

INIT_WORK(&offload_work->work, dm_handle_hpd_rx_offload_work);
offload_work->data = hpd_irq_data;
offload_work->offload_wq = offload_wq;

queue_work(offload_wq->wq, &offload_work->work);
DRM_DEBUG_KMS("queue work to handle hpd_rx offload work")___drm_dbg(((void *)0), DRM_UT_KMS, "queue work to handle hpd_rx offload work"
);
3348}

3350static void handle_hpd_rx_irq(void *param)
3351{
struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
struct drm_connector *connector = &aconnector->base;
struct drm_device *dev = connector->dev;
struct dc_link *dc_link = aconnector->dc_link;
bool_Bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
bool_Bool result = false0;
enum dc_connection_type new_connection_type = dc_connection_none;
struct amdgpu_device *adev = drm_to_adev(dev);
union hpd_irq_data hpd_irq_data;
bool_Bool link_loss = false0;
bool_Bool has_left_work = false0;
int idx = dc_link->link_index;
struct hpd_rx_irq_offload_work_queue *offload_wq = &adev->dm.hpd_rx_offload_wq[idx];

memset(&hpd_irq_data, 0, sizeof(hpd_irq_data))__builtin_memset((&hpd_irq_data), (0), (sizeof(hpd_irq_data
)));

if (adev->dm.disable_hpd_irq)
return;

/*
* TODO:Temporary add mutex to protect hpd interrupt not have a gpio
* conflict, after implement i2c helper, this mutex should be
* retired.
*/
mutex_lock(&aconnector->hpd_lock)rw_enter_write(&aconnector->hpd_lock);

result = dc_link_handle_hpd_rx_irq(dc_link, &hpd_irq_data,
				&link_loss, true1, &has_left_work);

if (!has_left_work)
goto out;

if (hpd_irq_data.bytes.device_service_irq.bits.AUTOMATED_TEST) {
schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);
goto out;
}

if (dc_link_dp_allow_hpd_rx_irq(dc_link)) {
if (hpd_irq_data.bytes.device_service_irq.bits.UP_REQ_MSG_RDY ||
	hpd_irq_data.bytes.device_service_irq.bits.DOWN_REP_MSG_RDY) {
	bool_Bool skip = false0;

	/*
	 * DOWN_REP_MSG_RDY is also handled by polling method
	 * mgr->cbs->poll_hpd_irq()
	 */
	spin_lock(&offload_wq->offload_lock)mtx_enter(&offload_wq->offload_lock);
	skip = offload_wq->is_handling_mst_msg_rdy_event;

	if (!skip)
		offload_wq->is_handling_mst_msg_rdy_event = true1;

	spin_unlock(&offload_wq->offload_lock)mtx_leave(&offload_wq->offload_lock);

	if (!skip)
		schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);

	goto out;
}

if (link_loss) {
	bool_Bool skip = false0;

	spin_lock(&offload_wq->offload_lock)mtx_enter(&offload_wq->offload_lock);
	skip = offload_wq->is_handling_link_loss;

	if (!skip)
		offload_wq->is_handling_link_loss = true1;

	spin_unlock(&offload_wq->offload_lock)mtx_leave(&offload_wq->offload_lock);

	if (!skip)
		schedule_hpd_rx_offload_work(offload_wq, hpd_irq_data);

	goto out;
}
}

3430out:
if (result && !is_mst_root_connector) {
/* Downstream Port status changed. */
if (!dc_link_detect_sink(dc_link, &new_connection_type))
	DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
	emulated_link_detect(dc_link);

	if (aconnector->fake_enable)
		aconnector->fake_enable = false0;

	amdgpu_dm_update_connector_after_detect(aconnector);


	drm_modeset_lock_all(dev);
	dm_restore_drm_connector_state(dev, connector);
	drm_modeset_unlock_all(dev);

	drm_kms_helper_connector_hotplug_event(connector);
} else {
	bool_Bool ret = false0;

	mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
	ret = dc_link_detect(dc_link, DETECT_REASON_HPDRX);
	mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);

	if (ret) {
		if (aconnector->fake_enable)
			aconnector->fake_enable = false0;

		amdgpu_dm_update_connector_after_detect(aconnector);

		drm_modeset_lock_all(dev);
		dm_restore_drm_connector_state(dev, connector);
		drm_modeset_unlock_all(dev);

		drm_kms_helper_connector_hotplug_event(connector);
	}
}
}
3471#ifdef CONFIG_DRM_AMD_DC_HDCP
if (hpd_irq_data.bytes.device_service_irq.bits.CP_IRQ) {
if (adev->dm.hdcp_workqueue)
	hdcp_handle_cpirq(adev->dm.hdcp_workqueue,  aconnector->base.index);
}
3476#endif

if (dc_link->type != dc_connection_mst_branch)
drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);

mutex_unlock(&aconnector->hpd_lock)rw_exit_write(&aconnector->hpd_lock);
3482}

3484static void register_hpd_handlers(struct amdgpu_device *adev)
3485{
struct drm_device *dev = adev_to_drm(adev);
struct drm_connector *connector;
struct amdgpu_dm_connector *aconnector;
const struct dc_link *dc_link;
struct dc_interrupt_params int_params = {0};

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

list_for_each_entry(connector,for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );}))
	&dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );}))	{

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
dc_link = aconnector->dc_link;

if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
	int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
	int_params.irq_source = dc_link->irq_source_hpd;

	amdgpu_dm_irq_register_interrupt(adev, &int_params,
			handle_hpd_irq,
			(void *) aconnector);
}

if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {

	/* Also register for DP short pulse (hpd_rx). */
	int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
	int_params.irq_source =	dc_link->irq_source_hpd_rx;

	amdgpu_dm_irq_register_interrupt(adev, &int_params,
			handle_hpd_rx_irq,
			(void *) aconnector);
}

if (adev->dm.hpd_rx_offload_wq)
	adev->dm.hpd_rx_offload_wq[connector->index].aconnector =
		aconnector;
}
3525}

3527#if defined(CONFIG_DRM_AMD_DC_SI)
3528/* Register IRQ sources and initialize IRQ callbacks */
3529static int dce60_register_irq_handlers(struct amdgpu_device *adev)
3530{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r;
int i;
unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY0;

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

/*
* Actions of amdgpu_irq_add_id():
* 1. Register a set() function with base driver.
*    Base driver will call set() function to enable/disable an
*    interrupt in DC hardware.
* 2. Register amdgpu_dm_irq_handler().
*    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
*    coming from DC hardware.
*    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
*    for acknowledging and handling.
*/

/* Use VBLANK interrupt */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
r = amdgpu_irq_add_id(adev, client_id, i + 1, &adev->crtc_irq);
if (r) {
	DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i + 1, 0);

c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_crtc_high_irq, c_irq_params);
}

/* Use GRPH_PFLIP interrupt */
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8;
	i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP18; i += 2) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
if (r) {
	DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_pflip_high_irq, c_irq_params);

}

/* HPD */
r = amdgpu_irq_add_id(adev, client_id,
	VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n");
return r;
}

register_hpd_handlers(adev);

return 0;
3608}
3609#endif

3611/* Register IRQ sources and initialize IRQ callbacks */
3612static int dce110_register_irq_handlers(struct amdgpu_device *adev)
3613{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r;
int i;
unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY0;

if (adev->family >= AMDGPU_FAMILY_AI141)
client_id = SOC15_IH_CLIENTID_DCE;

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

/*
* Actions of amdgpu_irq_add_id():
* 1. Register a set() function with base driver.
*    Base driver will call set() function to enable/disable an
*    interrupt in DC hardware.
* 2. Register amdgpu_dm_irq_handler().
*    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
*    coming from DC hardware.
*    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
*    for acknowledging and handling.
*/

/* Use VBLANK interrupt */
for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT019; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT024; i++) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
if (r) {
	DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_crtc_high_irq, c_irq_params);
}

/* Use VUPDATE interrupt */
for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT7; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT17; i += 2) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
if (r) {
	DRM_ERROR("Failed to add vupdate irq id!\n")__drm_err("Failed to add vupdate irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_vupdate_high_irq, c_irq_params);
}

/* Use GRPH_PFLIP interrupt */
for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP8;
	i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP18; i += 2) {
r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
if (r) {
	DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_pflip_high_irq, c_irq_params);

}

/* HPD */
r = amdgpu_irq_add_id(adev, client_id,
	VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A42, &adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n");
return r;
}

register_hpd_handlers(adev);

return 0;
3715}

3717/* Register IRQ sources and initialize IRQ callbacks */
3718static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
3719{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r;
int i;
3725#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
static const unsigned int vrtl_int_srcid[] = {
DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL0x1E,
DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL0x1F,
DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL0x20,
DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL0x21,
DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL0x22,
DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL0x38
};
3734#endif

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

/*
* Actions of amdgpu_irq_add_id():
* 1. Register a set() function with base driver.
*    Base driver will call set() function to enable/disable an
*    interrupt in DC hardware.
* 2. Register amdgpu_dm_irq_handler().
*    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
*    coming from DC hardware.
*    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
*    for acknowledging and handling.
*/

/* Use VSTARTUP interrupt */
for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP0x3C;
	i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP0x3C + adev->mode_info.num_crtc - 1;
	i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);

if (r) {
	DRM_ERROR("Failed to add crtc irq id!\n")__drm_err("Failed to add crtc irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(
	adev, &int_params, dm_crtc_high_irq, c_irq_params);
}

/* Use otg vertical line interrupt */
3776#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
for (i = 0; i <= adev->mode_info.num_crtc - 1; i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE,
		vrtl_int_srcid[i], &adev->vline0_irq);

if (r) {
	DRM_ERROR("Failed to add vline0 irq id!\n")__drm_err("Failed to add vline0 irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, vrtl_int_srcid[i], 0);

if (int_params.irq_source == DC_IRQ_SOURCE_INVALID) {
	DRM_ERROR("Failed to register vline0 irq %d!\n", vrtl_int_srcid[i])__drm_err("Failed to register vline0 irq %d!\n", vrtl_int_srcid
[i]);
	break;
}

c_irq_params = &adev->dm.vline0_params[int_params.irq_source
			- DC_IRQ_SOURCE_DC1_VLINE0];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_dcn_vertical_interrupt0_high_irq, c_irq_params);
}
3804#endif

/* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
* the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
* to trigger at end of each vblank, regardless of state of the lock,
* matching DCE behaviour.
*/
for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT0x57;
    i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT0x57 + adev->mode_info.num_crtc - 1;
    i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);

if (r) {
	DRM_ERROR("Failed to add vupdate irq id!\n")__drm_err("Failed to add vupdate irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_vupdate_high_irq, c_irq_params);
}

/* Use GRPH_PFLIP interrupt */
for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT0x4F;
	i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT0x4F + dc->caps.max_otg_num - 1;
	i++) {
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
if (r) {
	DRM_ERROR("Failed to add page flip irq id!\n")__drm_err("Failed to add page flip irq id!\n");
	return r;
}

int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
int_params.irq_source =
	dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_pflip_high_irq, c_irq_params);

}

/* HPD */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT9,
	&adev->hpd_irq);
if (r) {
DRM_ERROR("Failed to add hpd irq id!\n")__drm_err("Failed to add hpd irq id!\n");
return r;
}

register_hpd_handlers(adev);

return 0;
3869}
3870/* Register Outbox IRQ sources and initialize IRQ callbacks */
3871static int register_outbox_irq_handlers(struct amdgpu_device *adev)
3872{
struct dc *dc = adev->dm.dc;
struct common_irq_params *c_irq_params;
struct dc_interrupt_params int_params = {0};
int r, i;

int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;

r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT0x68,
	&adev->dmub_outbox_irq);
if (r) {
DRM_ERROR("Failed to add outbox irq id!\n")__drm_err("Failed to add outbox irq id!\n");
return r;
}

if (dc->ctx->dmub_srv) {
i = DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT0x68;
int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
int_params.irq_source =
dc_interrupt_to_irq_source(dc, i, 0);

c_irq_params = &adev->dm.dmub_outbox_params[0];

c_irq_params->adev = adev;
c_irq_params->irq_src = int_params.irq_source;

amdgpu_dm_irq_register_interrupt(adev, &int_params,
		dm_dmub_outbox1_low_irq, c_irq_params);
}

return 0;
3904}

3906/*
* Acquires the lock for the atomic state object and returns
* the new atomic state.
*
* This should only be called during atomic check.
*/
3912int dm_atomic_get_state(struct drm_atomic_state *state,
	struct dm_atomic_state **dm_state)
3914{
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_display_manager *dm = &adev->dm;
struct drm_private_state *priv_state;

if (*dm_state)
return 0;

priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
if (IS_ERR(priv_state))
return PTR_ERR(priv_state);

*dm_state = to_dm_atomic_state(priv_state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (priv_state); (struct dm_atomic_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_atomic_state, base) );});

return 0;
3930}

3932static struct dm_atomic_state *
3933dm_atomic_get_new_state(struct drm_atomic_state *state)
3934{
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_display_manager *dm = &adev->dm;
struct drm_private_obj *obj;
struct drm_private_state *new_obj_state;
int i;

for_each_new_private_obj_in_state(state, obj, new_obj_state, i)for ((i) = 0; (i) < (state)->num_private_objs &&
 ((obj) = (state)->private_objs[i].ptr, (void)(obj) , (new_obj_state
) = (state)->private_objs[i].new_state, 1); (i)++) {
if (obj->funcs == dm->atomic_obj.funcs)
	return to_dm_atomic_state(new_obj_state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (new_obj_state); (struct dm_atomic_state *)( (char *
)__mptr - __builtin_offsetof(struct dm_atomic_state, base) );
});
}

return NULL((void *)0);
3948}

3950static struct drm_private_state *
3951dm_atomic_duplicate_state(struct drm_private_obj *obj)
3952{
struct dm_atomic_state *old_state, *new_state;

new_state = kzalloc(sizeof(*new_state), GFP_KERNEL(0x0001 | 0x0004));
if (!new_state)
return NULL((void *)0);

__drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);

old_state = to_dm_atomic_state(obj->state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (obj->state); (struct dm_atomic_state *)( (char *
)__mptr - __builtin_offsetof(struct dm_atomic_state, base) );
});

if (old_state && old_state->context)
new_state->context = dc_copy_state(old_state->context);

if (!new_state->context) {
kfree(new_state);
return NULL((void *)0);
}

return &new_state->base;
3972}

3974static void dm_atomic_destroy_state(struct drm_private_obj *obj,
		    struct drm_private_state *state)
3976{
struct dm_atomic_state *dm_state = to_dm_atomic_state(state)({ const __typeof( ((struct dm_atomic_state *)0)->base ) *
__mptr = (state); (struct dm_atomic_state *)( (char *)__mptr -
 __builtin_offsetof(struct dm_atomic_state, base) );});

if (dm_state && dm_state->context)
dc_release_state(dm_state->context);

kfree(dm_state);
3983}

3985static struct drm_private_state_funcs dm_atomic_state_funcs = {
.atomic_duplicate_state = dm_atomic_duplicate_state,
.atomic_destroy_state = dm_atomic_destroy_state,
3988};

3990static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
3991{
struct dm_atomic_state *state;
int r;

adev->mode_info.mode_config_initialized = true1;

adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;

adev_to_drm(adev)->mode_config.max_width = 16384;
adev_to_drm(adev)->mode_config.max_height = 16384;

adev_to_drm(adev)->mode_config.preferred_depth = 24;
if (adev->asic_type == CHIP_HAWAII)
/* disable prefer shadow for now due to hibernation issues */
adev_to_drm(adev)->mode_config.prefer_shadow = 0;
else
adev_to_drm(adev)->mode_config.prefer_shadow = 1;
/* indicates support for immediate flip */
adev_to_drm(adev)->mode_config.async_page_flip = true1;

adev_to_drm(adev)->mode_config.fb_base = adev->gmc.aper_base;

state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));
if (!state)
return -ENOMEM12;

state->context = dc_create_state(adev->dm.dc);
if (!state->context) {
kfree(state);
return -ENOMEM12;
}

dc_resource_state_copy_construct_current(adev->dm.dc, state->context);

drm_atomic_private_obj_init(adev_to_drm(adev),
		    &adev->dm.atomic_obj,
		    &state->base,
		    &dm_atomic_state_funcs);

r = amdgpu_display_modeset_create_props(adev);
if (r) {
dc_release_state(state->context);
kfree(state);
return r;
}

r = amdgpu_dm_audio_init(adev);
if (r) {
dc_release_state(state->context);
kfree(state);
return r;
}

return 0;
4046}

4048#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12 12
4049#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255 255
4050#define AUX_BL_DEFAULT_TRANSITION_TIME_MS50 50

4052static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
			    int bl_idx)
4054{
4055#if defined(CONFIG_ACPI1)
struct amdgpu_dm_backlight_caps caps;

memset(&caps, 0, sizeof(caps))__builtin_memset((&caps), (0), (sizeof(caps)));

if (dm->backlight_caps[bl_idx].caps_valid)
return;

amdgpu_acpi_get_backlight_caps(&caps);
if (caps.caps_valid) {
dm->backlight_caps[bl_idx].caps_valid = true1;
if (caps.aux_support)
	return;
dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal;
dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal;
} else {
dm->backlight_caps[bl_idx].min_input_signal =
		AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12;
dm->backlight_caps[bl_idx].max_input_signal =
		AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255;
}
4076#else
if (dm->backlight_caps[bl_idx].aux_support)
return;

dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT12;
dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT255;
4082#endif
4083}

4085static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,
		unsigned int *min, unsigned int *max)
4087{
if (!caps)
return 0;

if (caps->aux_support) {
// Firmware limits are in nits, DC API wants millinits.
*max = 1000 * caps->aux_max_input_signal;
*min = 1000 * caps->aux_min_input_signal;
} else {
// Firmware limits are 8-bit, PWM control is 16-bit.
*max = 0x101 * caps->max_input_signal;
*min = 0x101 * caps->min_input_signal;
}
return 1;
4101}

4103static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,
			uint32_t brightness)
4105{
unsigned int min, max;

if (!get_brightness_range(caps, &min, &max))
return brightness;

// Rescale 0..255 to min..max
return min + DIV_ROUND_CLOSEST((max - min) * brightness,((((max - min) * brightness) + ((0xFF) / 2)) / (0xFF))
		       AMDGPU_MAX_BL_LEVEL)((((max - min) * brightness) + ((0xFF) / 2)) / (0xFF));
4114}

4116static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,
		      uint32_t brightness)
4118{
unsigned int min, max;

if (!get_brightness_range(caps, &min, &max))
return brightness;

if (brightness < min)
return 0;
// Rescale min..max to 0..255
return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min),(((0xFF * (brightness - min)) + ((max - min) / 2)) / (max - min
))
		 max - min)(((0xFF * (brightness - min)) + ((max - min) / 2)) / (max - min
));
4129}

4131static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
			 int bl_idx,
			 u32 user_brightness)
4134{
struct amdgpu_dm_backlight_caps caps;
struct dc_link *link;
u32 brightness;
bool_Bool rc;

amdgpu_dm_update_backlight_caps(dm, bl_idx);
caps = dm->backlight_caps[bl_idx];

dm->brightness[bl_idx] = user_brightness;
/* update scratch register */
if (bl_idx == 0)
amdgpu_atombios_scratch_regs_set_backlight_level(dm->adev, dm->brightness[bl_idx]);
brightness = convert_brightness_from_user(&caps, dm->brightness[bl_idx]);
link = (struct dc_link *)dm->backlight_link[bl_idx];

/* Change brightness based on AUX property */
if (caps.aux_support) {
rc = dc_link_set_backlight_level_nits(link, true1, brightness,
				      AUX_BL_DEFAULT_TRANSITION_TIME_MS50);
if (!rc)
	DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx)___drm_dbg(((void *)0), DRM_UT_CORE, "DM: Failed to update backlight via AUX on eDP[%d]\n"
, bl_idx);
} else {
rc = dc_link_set_backlight_level(link, brightness, 0);
if (!rc)
	DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx)___drm_dbg(((void *)0), DRM_UT_CORE, "DM: Failed to update backlight on eDP[%d]\n"
, bl_idx);
}

if (rc)
dm->actual_brightness[bl_idx] = user_brightness;
4164}

4166static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
4167{
struct amdgpu_display_manager *dm = bl_get_data(bd);
int i;

for (i = 0; i < dm->num_of_edps; i++) {
if (bd == dm->backlight_dev[i])
	break;
}
if (i >= AMDGPU_DM_MAX_NUM_EDP2)
i = 0;
amdgpu_dm_backlight_set_level(dm, i, bd->props.brightness);

return 0;
4180}

4182static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm,
			 int bl_idx)
4184{
struct amdgpu_dm_backlight_caps caps;
struct dc_link *link = (struct dc_link *)dm->backlight_link[bl_idx];

amdgpu_dm_update_backlight_caps(dm, bl_idx);
caps = dm->backlight_caps[bl_idx];

if (caps.aux_support) {
u32 avg, peak;
bool_Bool rc;

rc = dc_link_get_backlight_level_nits(link, &avg, &peak);
if (!rc)
	return dm->brightness[bl_idx];
return convert_brightness_to_user(&caps, avg);
} else {
int ret = dc_link_get_backlight_level(link);

if (ret == DC_ERROR_UNEXPECTED)
	return dm->brightness[bl_idx];
return convert_brightness_to_user(&caps, ret);
}
4206}

4208static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
4209{
struct amdgpu_display_manager *dm = bl_get_data(bd);
int i;

for (i = 0; i < dm->num_of_edps; i++) {
if (bd == dm->backlight_dev[i])
	break;
}
if (i >= AMDGPU_DM_MAX_NUM_EDP2)
i = 0;
return amdgpu_dm_backlight_get_level(dm, i);
4220}

4222static const struct backlight_ops amdgpu_dm_backlight_ops = {
.options = BL_CORE_SUSPENDRESUME0x00000001,
.get_brightness = amdgpu_dm_backlight_get_brightness,
.update_status	= amdgpu_dm_backlight_update_status,
4226};

4228static void
4229amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
4230{
char bl_name[16];
struct backlight_properties props = { 0 };

amdgpu_dm_update_backlight_caps(dm, dm->num_of_edps);
dm->brightness[dm->num_of_edps] = AMDGPU_MAX_BL_LEVEL0xFF;

if (!acpi_video_backlight_use_native()) {
drm_info(adev_to_drm(dm->adev), "Skipping amdgpu DM backlight registration\n")do { } while(0);
/* Try registering an ACPI video backlight device instead. */
acpi_video_register_backlight();
return;
}

props.max_brightness = AMDGPU_MAX_BL_LEVEL0xFF;
props.brightness = AMDGPU_MAX_BL_LEVEL0xFF;
props.type = BACKLIGHT_RAW0;

snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
 adev_to_drm(dm->adev)->primary->index + dm->num_of_edps);

dm->backlight_dev[dm->num_of_edps] = backlight_device_register(bl_name,
						       adev_to_drm(dm->adev)->dev,
						       dm,
						       &amdgpu_dm_backlight_ops,
						       &props);

if (IS_ERR(dm->backlight_dev[dm->num_of_edps]))
DRM_ERROR("DM: Backlight registration failed!\n")__drm_err("DM: Backlight registration failed!\n");
else
DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DM: Registered Backlight device: %s\n"
, bl_name);
4261}

4263static int initialize_plane(struct amdgpu_display_manager *dm,
	    struct amdgpu_mode_info *mode_info, int plane_id,
	    enum drm_plane_type plane_type,
	    const struct dc_plane_cap *plane_cap)
4267{
struct drm_plane *plane;
unsigned long possible_crtcs;
int ret = 0;

plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL(0x0001 | 0x0004));
if (!plane) {
DRM_ERROR("KMS: Failed to allocate plane\n")__drm_err("KMS: Failed to allocate plane\n");
return -ENOMEM12;
}
plane->type = plane_type;

/*
* HACK: IGT tests expect that the primary plane for a CRTC
* can only have one possible CRTC. Only expose support for
* any CRTC if they're not going to be used as a primary plane
* for a CRTC - like overlay or underlay planes.
*/
possible_crtcs = 1 << plane_id;
if (plane_id >= dm->dc->caps.max_streams)
possible_crtcs = 0xff;

ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);

if (ret) {
DRM_ERROR("KMS: Failed to initialize plane\n")__drm_err("KMS: Failed to initialize plane\n");
kfree(plane);
return ret;
}

if (mode_info)
mode_info->planes[plane_id] = plane;

return ret;
4301}


4304static void register_backlight_device(struct amdgpu_display_manager *dm,
		      struct dc_link *link)
4306{
if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
   link->type != dc_connection_none) {
/*
 * Event if registration failed, we should continue with
 * DM initialization because not having a backlight control
 * is better then a black screen.
 */
if (!dm->backlight_dev[dm->num_of_edps])
	amdgpu_dm_register_backlight_device(dm);

if (dm->backlight_dev[dm->num_of_edps]) {
	dm->backlight_link[dm->num_of_edps] = link;
	dm->num_of_edps++;
}
}
4322}

4324static void amdgpu_set_panel_orientation(struct drm_connector *connector);

4326/*
* In this architecture, the association
* connector -> encoder -> crtc
* id not really requried. The crtc and connector will hold the
* display_index as an abstraction to use with DAL component
*
* Returns 0 on success
*/
4334static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
4335{
struct amdgpu_display_manager *dm = &adev->dm;
s32 i;
struct amdgpu_dm_connector *aconnector = NULL((void *)0);
struct amdgpu_encoder *aencoder = NULL((void *)0);
struct amdgpu_mode_info *mode_info = &adev->mode_info;
u32 link_cnt;
s32 primary_planes;
enum dc_connection_type new_connection_type = dc_connection_none;
const struct dc_plane_cap *plane;
bool_Bool psr_feature_enabled = false0;

dm->display_indexes_num = dm->dc->caps.max_streams;
/* Update the actual used number of crtc */
adev->mode_info.num_crtc = adev->dm.display_indexes_num;

link_cnt = dm->dc->caps.max_links;
if (amdgpu_dm_mode_config_init(dm->adev)) {
DRM_ERROR("DM: Failed to initialize mode config\n")__drm_err("DM: Failed to initialize mode config\n");
return -EINVAL22;
}

/* There is one primary plane per CRTC */
primary_planes = dm->dc->caps.max_streams;
ASSERT(primary_planes <= AMDGPU_MAX_PLANES)do { if (({ static int __warned; int __ret = !!(!(primary_planes
 <= 6)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(primary_planes <= 6)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 4359); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);

/*
* Initialize primary planes, implicit planes for legacy IOCTLS.
* Order is reversed to match iteration order in atomic check.
*/
for (i = (primary_planes - 1); i >= 0; i--) {
plane = &dm->dc->caps.planes[i];

if (initialize_plane(dm, mode_info, i,
		     DRM_PLANE_TYPE_PRIMARY, plane)) {
	DRM_ERROR("KMS: Failed to initialize primary plane\n")__drm_err("KMS: Failed to initialize primary plane\n");
	goto fail;
}
}

/*
* Initialize overlay planes, index starting after primary planes.
* These planes have a higher DRM index than the primary planes since
* they should be considered as having a higher z-order.
* Order is reversed to match iteration order in atomic check.
*
* Only support DCN for now, and only expose one so we don't encourage
* userspace to use up all the pipes.
*/
for (i = 0; i < dm->dc->caps.max_planes; ++i) {
struct dc_plane_cap *plane = &dm->dc->caps.planes[i];

/* Do not create overlay if MPO disabled */
if (amdgpu_dc_debug_mask & DC_DISABLE_MPO)
	break;

if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
	continue;

if (!plane->blends_with_above || !plane->blends_with_below)
	continue;

if (!plane->pixel_format_support.argb8888)
	continue;

if (initialize_plane(dm, NULL((void *)0), primary_planes + i,
		     DRM_PLANE_TYPE_OVERLAY, plane)) {
	DRM_ERROR("KMS: Failed to initialize overlay plane\n")__drm_err("KMS: Failed to initialize overlay plane\n");
	goto fail;
}

/* Only create one overlay plane. */
break;
}

for (i = 0; i < dm->dc->caps.max_streams; i++)
if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
	DRM_ERROR("KMS: Failed to initialize crtc\n")__drm_err("KMS: Failed to initialize crtc\n");
	goto fail;
}

/* Use Outbox interrupt */
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)):
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)):
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)):
case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)):
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
if (register_outbox_irq_handlers(dm->adev)) {
	DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
	goto fail;
}
break;
default:
DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Unsupported DCN IP version for outbox: 0x%X\n"
, adev->ip_versions[DCE_HWIP][0])
	      adev->ip_versions[DCE_HWIP][0])___drm_dbg(((void *)0), DRM_UT_KMS, "Unsupported DCN IP version for outbox: 0x%X\n"
, adev->ip_versions[DCE_HWIP][0]);
}

/* Determine whether to enable PSR support by default. */
if (!(amdgpu_dc_debug_mask & DC_DISABLE_PSR)) {
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)):
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)):
case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)):
	psr_feature_enabled = true1;
	break;
default:
	psr_feature_enabled = amdgpu_dc_feature_mask & DC_PSR_MASK;
	break;
}
}

/* loops over all connectors on the board */
for (i = 0; i < link_cnt; i++) {
struct dc_link *link = NULL((void *)0);

if (i > AMDGPU_DM_MAX_DISPLAY_INDEX31) {
	DRM_ERROR(__drm_err("KMS: Cannot support more than %d display indexes\n"
, 31)
		"KMS: Cannot support more than %d display indexes\n",__drm_err("KMS: Cannot support more than %d display indexes\n"
, 31)
			AMDGPU_DM_MAX_DISPLAY_INDEX)__drm_err("KMS: Cannot support more than %d display indexes\n"
, 31);
	continue;
}

aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL(0x0001 | 0x0004));
if (!aconnector)
	goto fail;

aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL(0x0001 | 0x0004));
if (!aencoder)
	goto fail;

if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
	DRM_ERROR("KMS: Failed to initialize encoder\n")__drm_err("KMS: Failed to initialize encoder\n");
	goto fail;
}

if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
	DRM_ERROR("KMS: Failed to initialize connector\n")__drm_err("KMS: Failed to initialize connector\n");
	goto fail;
}

link = dc_get_link_at_index(dm->dc, i);

if (!dc_link_detect_sink(link, &new_connection_type))
	DRM_ERROR("KMS: Failed to detect connector\n")__drm_err("KMS: Failed to detect connector\n");

if (aconnector->base.force && new_connection_type == dc_connection_none) {
	emulated_link_detect(link);
	amdgpu_dm_update_connector_after_detect(aconnector);
} else {
	bool_Bool ret = false0;

	mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
	ret = dc_link_detect(link, DETECT_REASON_BOOT);
	mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);

	if (ret) {
		amdgpu_dm_update_connector_after_detect(aconnector);
		register_backlight_device(dm, link);

		if (dm->num_of_edps)
			update_connector_ext_caps(aconnector);

		if (psr_feature_enabled)
			amdgpu_dm_set_psr_caps(link);

		/* TODO: Fix vblank control helpers to delay PSR entry to allow this when
		 * PSR is also supported.
		 */
		if (link->psr_settings.psr_feature_enabled)
			adev_to_drm(adev)->vblank_disable_immediate = false0;
	}
}
amdgpu_set_panel_orientation(&aconnector->base);
}

/* If we didn't find a panel, notify the acpi video detection */
if (dm->adev->flags & AMD_IS_APU && dm->num_of_edps == 0)
acpi_video_report_nolcd();

/* Software is initialized. Now we can register interrupt handlers. */
switch (adev->asic_type) {
4525#if defined(CONFIG_DRM_AMD_DC_SI)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
if (dce60_register_irq_handlers(dm->adev)) {
	DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
	goto fail;
}
break;
4535#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_TONGA:
case CHIP_FIJI:
case CHIP_CARRIZO:
case CHIP_STONEY:
case CHIP_POLARIS11:
case CHIP_POLARIS10:
case CHIP_POLARIS12:
case CHIP_VEGAM:
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
if (dce110_register_irq_handlers(dm->adev)) {
	DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
	goto fail;
}
break;
default:
switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(1, 0, 0)(((1) << 16) | ((0) << 8) | (0)):
case IP_VERSION(1, 0, 1)(((1) << 16) | ((0) << 8) | (1)):
case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)):
case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)):
case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)):
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)):
case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)):
case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)):
case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)):
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)):
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)):
case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)):
	if (dcn10_register_irq_handlers(dm->adev)) {
		DRM_ERROR("DM: Failed to initialize IRQ\n")__drm_err("DM: Failed to initialize IRQ\n");
		goto fail;
	}
	break;
default:
	DRM_ERROR("Unsupported DCE IP versions: 0x%X\n",__drm_err("Unsupported DCE IP versions: 0x%X\n", adev->ip_versions
[DCE_HWIP][0])
			adev->ip_versions[DCE_HWIP][0])__drm_err("Unsupported DCE IP versions: 0x%X\n", adev->ip_versions
[DCE_HWIP][0]);
	goto fail;
}
break;
}

return 0;
4590fail:
kfree(aencoder);
kfree(aconnector);

return -EINVAL22;
4595}

4597static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
4598{
drm_atomic_private_obj_fini(&dm->atomic_obj);
5
←
Value assigned to field 'hpd_rx_offload_wq', which participates in a condition later→
6
←
Value assigned to field 'dc'→
4600}

4602/******************************************************************************
* amdgpu_display_funcs functions
*****************************************************************************/

4606/*
* dm_bandwidth_update - program display watermarks
*
* @adev: amdgpu_device pointer
*
* Calculate and program the display watermarks and line buffer allocation.
*/
4613static void dm_bandwidth_update(struct amdgpu_device *adev)
4614{
/* TODO: implement later */
4616}

4618static const struct amdgpu_display_funcs dm_display_funcs = {
.bandwidth_update = dm_bandwidth_update, /* called unconditionally */
.vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
.backlight_set_level = NULL((void *)0), /* never called for DC */
.backlight_get_level = NULL((void *)0), /* never called for DC */
.hpd_sense = NULL((void *)0),/* called unconditionally */
.hpd_set_polarity = NULL((void *)0), /* called unconditionally */
.hpd_get_gpio_reg = NULL((void *)0), /* VBIOS parsing. DAL does it. */
.page_flip_get_scanoutpos =
dm_crtc_get_scanoutpos,/* called unconditionally */
.add_encoder = NULL((void *)0), /* VBIOS parsing. DAL does it. */
.add_connector = NULL((void *)0), /* VBIOS parsing. DAL does it. */
4630};

4632#if defined(CONFIG_DEBUG_KERNEL_DC)

4634static ssize_t s3_debug_store(struct device *device,
	      struct device_attribute *attr,
	      const char *buf,
	      size_t count)
4638{
int ret;
int s3_state;
struct drm_device *drm_dev = dev_get_drvdata(device);
struct amdgpu_device *adev = drm_to_adev(drm_dev);

ret = kstrtoint(buf, 0, &s3_state);

if (ret == 0) {
if (s3_state) {
	dm_resume(adev);
	drm_kms_helper_hotplug_event(adev_to_drm(adev));
} else
	dm_suspend(adev);
}

return ret == 0 ? count : 0;
4655}

4657DEVICE_ATTR_WO(s3_debug);

4659#endif

4661static int dm_early_init(void *handle)
4662{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
struct amdgpu_mode_info *mode_info = &adev->mode_info;
struct atom_context *ctx = mode_info->atom_context;
int index = GetIndexIntoMasterTable(DATA, Object_Header)(__builtin_offsetof(ATOM_MASTER_LIST_OF_DATA_TABLES, Object_Header
) / sizeof(USHORT));
u16 data_offset;

/* if there is no object header, skip DM */
if (!amdgpu_atom_parse_data_header(ctx, index, NULL((void *)0), NULL((void *)0), NULL((void *)0), &data_offset)) {
adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;
dev_info(adev->dev, "No object header, skipping DM\n")do { } while(0);
return -ENOENT2;
}

switch (adev->asic_type) {
4677#if defined(CONFIG_DRM_AMD_DC_SI)
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_OLAND:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 2;
adev->mode_info.num_dig = 2;
break;
4690#endif
case CHIP_BONAIRE:
case CHIP_HAWAII:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_KAVERI:
adev->mode_info.num_crtc = 4;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 7;
break;
case CHIP_KABINI:
case CHIP_MULLINS:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_FIJI:
case CHIP_TONGA:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 7;
break;
case CHIP_CARRIZO:
adev->mode_info.num_crtc = 3;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
break;
case CHIP_STONEY:
adev->mode_info.num_crtc = 2;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 9;
break;
case CHIP_POLARIS11:
case CHIP_POLARIS12:
adev->mode_info.num_crtc = 5;
adev->mode_info.num_hpd = 5;
adev->mode_info.num_dig = 5;
break;
case CHIP_POLARIS10:
case CHIP_VEGAM:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
adev->mode_info.num_crtc = 6;
adev->mode_info.num_hpd = 6;
adev->mode_info.num_dig = 6;
break;
default:

switch (adev->ip_versions[DCE_HWIP][0]) {
case IP_VERSION(2, 0, 2)(((2) << 16) | ((0) << 8) | (2)):
case IP_VERSION(3, 0, 0)(((3) << 16) | ((0) << 8) | (0)):
	adev->mode_info.num_crtc = 6;
	adev->mode_info.num_hpd = 6;
	adev->mode_info.num_dig = 6;
	break;
case IP_VERSION(2, 0, 0)(((2) << 16) | ((0) << 8) | (0)):
case IP_VERSION(3, 0, 2)(((3) << 16) | ((0) << 8) | (2)):
	adev->mode_info.num_crtc = 5;
	adev->mode_info.num_hpd = 5;
	adev->mode_info.num_dig = 5;
	break;
case IP_VERSION(2, 0, 3)(((2) << 16) | ((0) << 8) | (3)):
case IP_VERSION(3, 0, 3)(((3) << 16) | ((0) << 8) | (3)):
	adev->mode_info.num_crtc = 2;
	adev->mode_info.num_hpd = 2;
	adev->mode_info.num_dig = 2;
	break;
case IP_VERSION(1, 0, 0)(((1) << 16) | ((0) << 8) | (0)):
case IP_VERSION(1, 0, 1)(((1) << 16) | ((0) << 8) | (1)):
case IP_VERSION(3, 0, 1)(((3) << 16) | ((0) << 8) | (1)):
case IP_VERSION(2, 1, 0)(((2) << 16) | ((1) << 8) | (0)):
case IP_VERSION(3, 1, 2)(((3) << 16) | ((1) << 8) | (2)):
case IP_VERSION(3, 1, 3)(((3) << 16) | ((1) << 8) | (3)):
case IP_VERSION(3, 1, 4)(((3) << 16) | ((1) << 8) | (4)):
case IP_VERSION(3, 1, 5)(((3) << 16) | ((1) << 8) | (5)):
case IP_VERSION(3, 1, 6)(((3) << 16) | ((1) << 8) | (6)):
case IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)):
case IP_VERSION(3, 2, 1)(((3) << 16) | ((2) << 8) | (1)):
	adev->mode_info.num_crtc = 4;
	adev->mode_info.num_hpd = 4;
	adev->mode_info.num_dig = 4;
	break;
default:
	DRM_ERROR("Unsupported DCE IP versions: 0x%x\n",__drm_err("Unsupported DCE IP versions: 0x%x\n", adev->ip_versions
[DCE_HWIP][0])
			adev->ip_versions[DCE_HWIP][0])__drm_err("Unsupported DCE IP versions: 0x%x\n", adev->ip_versions
[DCE_HWIP][0]);
	return -EINVAL22;
}
break;
}

amdgpu_dm_set_irq_funcs(adev);

if (adev->mode_info.funcs == NULL((void *)0))
adev->mode_info.funcs = &dm_display_funcs;

/*
* Note: Do NOT change adev->audio_endpt_rreg and
* adev->audio_endpt_wreg because they are initialised in
* amdgpu_device_init()
*/
4797#if defined(CONFIG_DEBUG_KERNEL_DC)
device_create_file(0
adev_to_drm(adev)->dev,0
&dev_attr_s3_debug)0;
4801#endif

return 0;
4804}

4806static bool_Bool modereset_required(struct drm_crtc_state *crtc_state)
4807{
return !crtc_state->active && drm_atomic_crtc_needs_modeset(crtc_state);
4809}

4811static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
4812{
drm_encoder_cleanup(encoder);
kfree(encoder);
4815}

4817static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
.destroy = amdgpu_dm_encoder_destroy,
4819};

4821static int
4822fill_plane_color_attributes(const struct drm_plane_state *plane_state,
	    const enum surface_pixel_format format,
	    enum dc_color_space *color_space)
4825{
bool_Bool full_range;

*color_space = COLOR_SPACE_SRGB;

/* DRM color properties only affect non-RGB formats. */
if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
return 0;

full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);

switch (plane_state->color_encoding) {
case DRM_COLOR_YCBCR_BT601:
if (full_range)
	*color_space = COLOR_SPACE_YCBCR601;
else
	*color_space = COLOR_SPACE_YCBCR601_LIMITED;
break;

case DRM_COLOR_YCBCR_BT709:
if (full_range)
	*color_space = COLOR_SPACE_YCBCR709;
else
	*color_space = COLOR_SPACE_YCBCR709_LIMITED;
break;

case DRM_COLOR_YCBCR_BT2020:
if (full_range)
	*color_space = COLOR_SPACE_2020_YCBCR;
else
	return -EINVAL22;
break;

default:
return -EINVAL22;
}

return 0;
4863}

4865static int
4866fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
	    const struct drm_plane_state *plane_state,
	    const u64 tiling_flags,
	    struct dc_plane_info *plane_info,
	    struct dc_plane_address *address,
	    bool_Bool tmz_surface,
	    bool_Bool force_disable_dcc)
4873{
const struct drm_framebuffer *fb = plane_state->fb;
const struct amdgpu_framebuffer *afb =
to_amdgpu_framebuffer(plane_state->fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base )
 *__mptr = (plane_state->fb); (struct amdgpu_framebuffer *
)( (char *)__mptr - __builtin_offsetof(struct amdgpu_framebuffer
, base) );});
int ret;

memset(plane_info, 0, sizeof(*plane_info))__builtin_memset((plane_info), (0), (sizeof(*plane_info)));

switch (fb->format->format) {
case DRM_FORMAT_C8((__u32)('C') | ((__u32)('8') << 8) | ((__u32)(' ') <<
 16) | ((__u32)(' ') << 24)):
plane_info->format =
	SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
break;
case DRM_FORMAT_RGB565((__u32)('R') | ((__u32)('G') << 8) | ((__u32)('1') <<
 16) | ((__u32)('6') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
break;
case DRM_FORMAT_XRGB8888((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
case DRM_FORMAT_ARGB8888((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
break;
case DRM_FORMAT_XRGB2101010((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
case DRM_FORMAT_ARGB2101010((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
break;
case DRM_FORMAT_XBGR2101010((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
case DRM_FORMAT_ABGR2101010((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('3') <<
 16) | ((__u32)('0') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
case DRM_FORMAT_XBGR8888((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
case DRM_FORMAT_ABGR8888((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('2') <<
 16) | ((__u32)('4') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
break;
case DRM_FORMAT_NV21((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('2') <<
 16) | ((__u32)('1') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
break;
case DRM_FORMAT_NV12((__u32)('N') | ((__u32)('V') << 8) | ((__u32)('1') <<
 16) | ((__u32)('2') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
break;
case DRM_FORMAT_P010((__u32)('P') | ((__u32)('0') << 8) | ((__u32)('1') <<
 16) | ((__u32)('0') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb;
break;
case DRM_FORMAT_XRGB16161616F((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
case DRM_FORMAT_ARGB16161616F((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F;
break;
case DRM_FORMAT_XBGR16161616F((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
case DRM_FORMAT_ABGR16161616F((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('H') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F;
break;
case DRM_FORMAT_XRGB16161616((__u32)('X') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('8') << 24)):
case DRM_FORMAT_ARGB16161616((__u32)('A') | ((__u32)('R') << 8) | ((__u32)('4') <<
 16) | ((__u32)('8') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616;
break;
case DRM_FORMAT_XBGR16161616((__u32)('X') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('8') << 24)):
case DRM_FORMAT_ABGR16161616((__u32)('A') | ((__u32)('B') << 8) | ((__u32)('4') <<
 16) | ((__u32)('8') << 24)):
plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616;
break;
default:
DRM_ERROR(__drm_err("Unsupported screen format %p4cc\n", &fb->format
->format)
	"Unsupported screen format %p4cc\n",__drm_err("Unsupported screen format %p4cc\n", &fb->format
->format)
	&fb->format->format)__drm_err("Unsupported screen format %p4cc\n", &fb->format
->format);
return -EINVAL22;
}

switch (plane_state->rotation & DRM_MODE_ROTATE_MASK( (1<<0) | (1<<1) | (1<<2) | (1<<3))) {
case DRM_MODE_ROTATE_0(1<<0):
plane_info->rotation = ROTATION_ANGLE_0;
break;
case DRM_MODE_ROTATE_90(1<<1):
plane_info->rotation = ROTATION_ANGLE_90;
break;
case DRM_MODE_ROTATE_180(1<<2):
plane_info->rotation = ROTATION_ANGLE_180;
break;
case DRM_MODE_ROTATE_270(1<<3):
plane_info->rotation = ROTATION_ANGLE_270;
break;
default:
plane_info->rotation = ROTATION_ANGLE_0;
break;
}


plane_info->visible = true1;
plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;

plane_info->layer_index = plane_state->normalized_zpos;

ret = fill_plane_color_attributes(plane_state, plane_info->format,
			  &plane_info->color_space);
if (ret)
return ret;

ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
			   plane_info->rotation, tiling_flags,
			   &plane_info->tiling_info,
			   &plane_info->plane_size,
			   &plane_info->dcc, address,
			   tmz_surface, force_disable_dcc);
if (ret)
return ret;

fill_blending_from_plane_state(
plane_state, &plane_info->per_pixel_alpha, &plane_info->pre_multiplied_alpha,
&plane_info->global_alpha, &plane_info->global_alpha_value);

return 0;
4980}

4982static int fill_dc_plane_attributes(struct amdgpu_device *adev,
		    struct dc_plane_state *dc_plane_state,
		    struct drm_plane_state *plane_state,
		    struct drm_crtc_state *crtc_state)
4986{
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_crtc_state, base) );});
struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)plane_state->fb;
struct dc_scaling_info scaling_info;
struct dc_plane_info plane_info;
int ret;
bool_Bool force_disable_dcc = false0;

ret = fill_dc_scaling_info(adev, plane_state, &scaling_info);
if (ret)
return ret;

dc_plane_state->src_rect = scaling_info.src_rect;
dc_plane_state->dst_rect = scaling_info.dst_rect;
dc_plane_state->clip_rect = scaling_info.clip_rect;
dc_plane_state->scaling_quality = scaling_info.scaling_quality;

force_disable_dcc = adev->asic_type == CHIP_RAVEN && adev->in_suspend;
ret = fill_dc_plane_info_and_addr(adev, plane_state,
			  afb->tiling_flags,
			  &plane_info,
			  &dc_plane_state->address,
			  afb->tmz_surface,
			  force_disable_dcc);
if (ret)
return ret;

dc_plane_state->format = plane_info.format;
dc_plane_state->color_space = plane_info.color_space;
dc_plane_state->format = plane_info.format;
dc_plane_state->plane_size = plane_info.plane_size;
dc_plane_state->rotation = plane_info.rotation;
dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
dc_plane_state->stereo_format = plane_info.stereo_format;
dc_plane_state->tiling_info = plane_info.tiling_info;
dc_plane_state->visible = plane_info.visible;
dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
dc_plane_state->pre_multiplied_alpha = plane_info.pre_multiplied_alpha;
dc_plane_state->global_alpha = plane_info.global_alpha;
dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
dc_plane_state->dcc = plane_info.dcc;
dc_plane_state->layer_index = plane_info.layer_index;
dc_plane_state->flip_int_enabled = true1;

/*
* Always set input transfer function, since plane state is refreshed
* every time.
*/
ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
if (ret)
return ret;

return 0;
5039}

5041static inline void fill_dc_dirty_rect(struct drm_plane *plane,
		      struct rect *dirty_rect, int32_t x,
		      int32_t y, int32_t width, int32_t height,
		      int *i, bool_Bool ffu)
5045{
WARN_ON(*i >= DC_MAX_DIRTY_RECTS)({ int __ret = !!(*i >= 3); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "*i >= 3", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 5046); __builtin_expect(!!(__ret), 0); });

dirty_rect->x = x;
dirty_rect->y = y;
dirty_rect->width = width;
dirty_rect->height = height;

if (ffu)
drm_dbg(plane->dev,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n"
, plane->base.id, width, height)
	"[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n",__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n"
, plane->base.id, width, height)
	plane->base.id, width, height)__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR FFU dirty rect size (%d, %d)\n"
, plane->base.id, width, height);
else
drm_dbg(plane->dev,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)"
, plane->base.id, x, y, width, height)
	"[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)",__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)"
, plane->base.id, x, y, width, height)
	plane->base.id, x, y, width, height)__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR SU dirty rect at (%d, %d) size (%d, %d)"
, plane->base.id, x, y, width, height);

(*i)++;
5063}

5065/**
* fill_dc_dirty_rects() - Fill DC dirty regions for PSR selective updates
*
* @plane: DRM plane containing dirty regions that need to be flushed to the eDP
*         remote fb
* @old_plane_state: Old state of @plane
* @new_plane_state: New state of @plane
* @crtc_state: New state of CRTC connected to the @plane
* @flip_addrs: DC flip tracking struct, which also tracts dirty rects
*
* For PSR SU, DC informs the DMUB uController of dirty rectangle regions
* (referred to as "damage clips" in DRM nomenclature) that require updating on
* the eDP remote buffer. The responsibility of specifying the dirty regions is
* amdgpu_dm's.
*
* A damage-aware DRM client should fill the FB_DAMAGE_CLIPS property on the
* plane with regions that require flushing to the eDP remote buffer. In
* addition, certain use cases - such as cursor and multi-plane overlay (MPO) -
* implicitly provide damage clips without any client support via the plane
* bounds.
*/
5086static void fill_dc_dirty_rects(struct drm_plane *plane,
		struct drm_plane_state *old_plane_state,
		struct drm_plane_state *new_plane_state,
		struct drm_crtc_state *crtc_state,
		struct dc_flip_addrs *flip_addrs)
5091{
struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (crtc_state); (struct dm_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct dm_crtc_state, base) );});
struct rect *dirty_rects = flip_addrs->dirty_rects;
uint32_t num_clips;
struct drm_mode_rect *clips;
bool_Bool bb_changed;
bool_Bool fb_changed;
u32 i = 0;

/*
* Cursor plane has it's own dirty rect update interface. See
* dcn10_dmub_update_cursor_data and dmub_cmd_update_cursor_info_data
*/
if (plane->type == DRM_PLANE_TYPE_CURSOR)
return;

if (new_plane_state->rotation != DRM_MODE_ROTATE_0(1<<0))
goto ffu;

num_clips = drm_plane_get_damage_clips_count(new_plane_state);
clips = drm_plane_get_damage_clips(new_plane_state);

if (!dm_crtc_state->mpo_requested) {
if (!num_clips || num_clips > DC_MAX_DIRTY_RECTS3)
	goto ffu;

for (; flip_addrs->dirty_rect_count < num_clips; clips++)
	fill_dc_dirty_rect(new_plane_state->plane,
			   &dirty_rects[flip_addrs->dirty_rect_count],
			   clips->x1, clips->y1,
			   clips->x2 - clips->x1, clips->y2 - clips->y1,
			   &flip_addrs->dirty_rect_count,
			   false0);
return;
}

/*
* MPO is requested. Add entire plane bounding box to dirty rects if
* flipped to or damaged.
*
* If plane is moved or resized, also add old bounding box to dirty
* rects.
*/
fb_changed = old_plane_state->fb->base.id !=
     new_plane_state->fb->base.id;
bb_changed = (old_plane_state->crtc_x != new_plane_state->crtc_x ||
      old_plane_state->crtc_y != new_plane_state->crtc_y ||
      old_plane_state->crtc_w != new_plane_state->crtc_w ||
      old_plane_state->crtc_h != new_plane_state->crtc_h);

drm_dbg(plane->dev,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n"
, new_plane_state->plane->base.id, bb_changed, fb_changed
, num_clips)
"[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n",__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n"
, new_plane_state->plane->base.id, bb_changed, fb_changed
, num_clips)
new_plane_state->plane->base.id,__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n"
, new_plane_state->plane->base.id, bb_changed, fb_changed
, num_clips)
bb_changed, fb_changed, num_clips)__drm_dev_dbg(((void *)0), (plane->dev) ? (plane->dev)->
dev : ((void *)0), DRM_UT_DRIVER, "[PLANE:%d] PSR bb_changed:%d fb_changed:%d num_clips:%d\n"
, new_plane_state->plane->base.id, bb_changed, fb_changed
, num_clips);

if ((num_clips + (bb_changed ? 2 : 0)) > DC_MAX_DIRTY_RECTS3)
goto ffu;

if (bb_changed) {
fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
		   new_plane_state->crtc_x,
		   new_plane_state->crtc_y,
		   new_plane_state->crtc_w,
		   new_plane_state->crtc_h, &i, false0);

/* Add old plane bounding-box if plane is moved or resized */
fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
		   old_plane_state->crtc_x,
		   old_plane_state->crtc_y,
		   old_plane_state->crtc_w,
		   old_plane_state->crtc_h, &i, false0);
}

if (num_clips) {
for (; i < num_clips; clips++)
	fill_dc_dirty_rect(new_plane_state->plane,
			   &dirty_rects[i], clips->x1,
			   clips->y1, clips->x2 - clips->x1,
			   clips->y2 - clips->y1, &i, false0);
} else if (fb_changed && !bb_changed) {
fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[i],
		   new_plane_state->crtc_x,
		   new_plane_state->crtc_y,
		   new_plane_state->crtc_w,
		   new_plane_state->crtc_h, &i, false0);
}

flip_addrs->dirty_rect_count = i;
return;

5181ffu:
fill_dc_dirty_rect(new_plane_state->plane, &dirty_rects[0], 0, 0,
	   dm_crtc_state->base.mode.crtc_hdisplay,
	   dm_crtc_state->base.mode.crtc_vdisplay,
	   &flip_addrs->dirty_rect_count, true1);
5186}

5188static void update_stream_scaling_settings(const struct drm_display_mode *mode,
			   const struct dm_connector_state *dm_state,
			   struct dc_stream_state *stream)
5191{
enum amdgpu_rmx_type rmx_type;

struct rect src = { 0 }; /* viewport in composition space*/
struct rect dst = { 0 }; /* stream addressable area */

/* no mode. nothing to be done */
if (!mode)
return;

/* Full screen scaling by default */
src.width = mode->hdisplay;
src.height = mode->vdisplay;
dst.width = stream->timing.h_addressable;
dst.height = stream->timing.v_addressable;

if (dm_state) {
rmx_type = dm_state->scaling;
if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
	if (src.width * dst.height <
			src.height * dst.width) {
		/* height needs less upscaling/more downscaling */
		dst.width = src.width *
				dst.height / src.height;
	} else {
		/* width needs less upscaling/more downscaling */
		dst.height = src.height *
				dst.width / src.width;
	}
} else if (rmx_type == RMX_CENTER) {
	dst = src;
}

dst.x = (stream->timing.h_addressable - dst.width) / 2;
dst.y = (stream->timing.v_addressable - dst.height) / 2;

if (dm_state->underscan_enable) {
	dst.x += dm_state->underscan_hborder / 2;
	dst.y += dm_state->underscan_vborder / 2;
	dst.width -= dm_state->underscan_hborder;
	dst.height -= dm_state->underscan_vborder;
}
}

stream->src = src;
stream->dst = dst;

DRM_DEBUG_KMS("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Destination Rectangle x:%d  y:%d  width:%d  height:%d\n"
, dst.x, dst.y, dst.width, dst.height)
      dst.x, dst.y, dst.width, dst.height)___drm_dbg(((void *)0), DRM_UT_KMS, "Destination Rectangle x:%d  y:%d  width:%d  height:%d\n"
, dst.x, dst.y, dst.width, dst.height);

5241}

5243static enum dc_color_depth
5244convert_color_depth_from_display_info(const struct drm_connector *connector,
		      bool_Bool is_y420, int requested_bpc)
5246{
u8 bpc;

if (is_y420) {
bpc = 8;

/* Cap display bpc based on HDMI 2.0 HF-VSDB */
if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48(1 << 2))
	bpc = 16;
else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36(1 << 1))
	bpc = 12;
else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30(1 << 0))
	bpc = 10;
} else {
bpc = (uint8_t)connector->display_info.bpc;
/* Assume 8 bpc by default if no bpc is specified. */
bpc = bpc ? bpc : 8;
}

if (requested_bpc > 0) {
/*
 * Cap display bpc based on the user requested value.
 *
 * The value for state->max_bpc may not correctly updated
 * depending on when the connector gets added to the state
 * or if this was called outside of atomic check, so it
 * can't be used directly.
 */
bpc = min_t(u8, bpc, requested_bpc)({ u8 __min_a = (bpc); u8 __min_b = (requested_bpc); __min_a <
 __min_b ? __min_a : __min_b; });

/* Round down to the nearest even number. */
bpc = bpc - (bpc & 1);
}

switch (bpc) {
case 0:
/*
 * Temporary Work around, DRM doesn't parse color depth for
 * EDID revision before 1.4
 * TODO: Fix edid parsing
 */
return COLOR_DEPTH_888;
case 6:
return COLOR_DEPTH_666;
case 8:
return COLOR_DEPTH_888;
case 10:
return COLOR_DEPTH_101010;
case 12:
return COLOR_DEPTH_121212;
case 14:
return COLOR_DEPTH_141414;
case 16:
return COLOR_DEPTH_161616;
default:
return COLOR_DEPTH_UNDEFINED;
}
5303}

5305static enum dc_aspect_ratio
5306get_aspect_ratio(const struct drm_display_mode *mode_in)
5307{
/* 1-1 mapping, since both enums follow the HDMI spec. */
return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
5310}

5312static enum dc_color_space
5313get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
5314{
enum dc_color_space color_space = COLOR_SPACE_SRGB;

switch (dc_crtc_timing->pixel_encoding)	{
case PIXEL_ENCODING_YCBCR422:
case PIXEL_ENCODING_YCBCR444:
case PIXEL_ENCODING_YCBCR420:
{
/*
 * 27030khz is the separation point between HDTV and SDTV
 * according to HDMI spec, we use YCbCr709 and YCbCr601
 * respectively
 */
if (dc_crtc_timing->pix_clk_100hz > 270300) {
	if (dc_crtc_timing->flags.Y_ONLY)
		color_space =
			COLOR_SPACE_YCBCR709_LIMITED;
	else
		color_space = COLOR_SPACE_YCBCR709;
} else {
	if (dc_crtc_timing->flags.Y_ONLY)
		color_space =
			COLOR_SPACE_YCBCR601_LIMITED;
	else
		color_space = COLOR_SPACE_YCBCR601;
}

}
break;
case PIXEL_ENCODING_RGB:
color_space = COLOR_SPACE_SRGB;
break;

default:
WARN_ON(1)({ int __ret = !!(1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "1", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 5348); __builtin_expect(!!(__ret), 0); });
break;
}

return color_space;
5353}

5355static bool_Bool adjust_colour_depth_from_display_info(
struct dc_crtc_timing *timing_out,
const struct drm_display_info *info)
5358{
enum dc_color_depth depth = timing_out->display_color_depth;
int normalized_clk;

do {
normalized_clk = timing_out->pix_clk_100hz / 10;
/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
	normalized_clk /= 2;
/* Adjusting pix clock following on HDMI spec based on colour depth */
switch (depth) {
case COLOR_DEPTH_888:
	break;
case COLOR_DEPTH_101010:
	normalized_clk = (normalized_clk * 30) / 24;
	break;
case COLOR_DEPTH_121212:
	normalized_clk = (normalized_clk * 36) / 24;
	break;
case COLOR_DEPTH_161616:
	normalized_clk = (normalized_clk * 48) / 24;
	break;
default:
	/* The above depths are the only ones valid for HDMI. */
	return false0;
}
if (normalized_clk <= info->max_tmds_clock) {
	timing_out->display_color_depth = depth;
	return true1;
}
} while (--depth > COLOR_DEPTH_666);
return false0;
5390}

5392static void fill_stream_properties_from_drm_display_mode(
struct dc_stream_state *stream,
const struct drm_display_mode *mode_in,
const struct drm_connector *connector,
const struct drm_connector_state *connector_state,
const struct dc_stream_state *old_stream,
int requested_bpc)
5399{
struct dc_crtc_timing *timing_out = &stream->timing;
const struct drm_display_info *info = &connector->display_info;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct hdmi_vendor_infoframe hv_frame;
struct hdmi_avi_infoframe avi_frame;

memset(&hv_frame, 0, sizeof(hv_frame))__builtin_memset((&hv_frame), (0), (sizeof(hv_frame)));
memset(&avi_frame, 0, sizeof(avi_frame))__builtin_memset((&avi_frame), (0), (sizeof(avi_frame)));

timing_out->h_border_left = 0;
timing_out->h_border_right = 0;
timing_out->v_border_top = 0;
timing_out->v_border_bottom = 0;
/* TODO: un-hardcode */
if (drm_mode_is_420_only(info, mode_in)
	&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
else if (drm_mode_is_420_also(info, mode_in)
	&& aconnector->force_yuv420_output)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR444(1<<1))
	&& stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
else
timing_out->pixel_encoding = PIXEL_ENCODING_RGB;

timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
timing_out->display_color_depth = convert_color_depth_from_display_info(
connector,
(timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420),
requested_bpc);
timing_out->scan_type = SCANNING_TYPE_NODATA;
timing_out->hdmi_vic = 0;

if (old_stream) {
timing_out->vic = old_stream->timing.vic;
timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
} else {
timing_out->vic = drm_match_cea_mode(mode_in);
if (mode_in->flags & DRM_MODE_FLAG_PHSYNC(1<<0))
	timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
if (mode_in->flags & DRM_MODE_FLAG_PVSYNC(1<<2))
	timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
}

if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in);
timing_out->vic = avi_frame.video_code;
drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in);
timing_out->hdmi_vic = hv_frame.vic;
}

if (is_freesync_video_mode(mode_in, aconnector)) {
timing_out->h_addressable = mode_in->hdisplay;
timing_out->h_total = mode_in->htotal;
timing_out->h_sync_width = mode_in->hsync_end - mode_in->hsync_start;
timing_out->h_front_porch = mode_in->hsync_start - mode_in->hdisplay;
timing_out->v_total = mode_in->vtotal;
timing_out->v_addressable = mode_in->vdisplay;
timing_out->v_front_porch = mode_in->vsync_start - mode_in->vdisplay;
timing_out->v_sync_width = mode_in->vsync_end - mode_in->vsync_start;
timing_out->pix_clk_100hz = mode_in->clock * 10;
} else {
timing_out->h_addressable = mode_in->crtc_hdisplay;
timing_out->h_total = mode_in->crtc_htotal;
timing_out->h_sync_width = mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
timing_out->h_front_porch = mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
timing_out->v_total = mode_in->crtc_vtotal;
timing_out->v_addressable = mode_in->crtc_vdisplay;
timing_out->v_front_porch = mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
timing_out->v_sync_width = mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
}

timing_out->aspect_ratio = get_aspect_ratio(mode_in);

stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
if (!adjust_colour_depth_from_display_info(timing_out, info) &&
    drm_mode_is_420_also(info, mode_in) &&
    timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) {
	timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
	adjust_colour_depth_from_display_info(timing_out, info);
}
}

stream->output_color_space = get_output_color_space(timing_out);
5489}

5491static void fill_audio_info(struct audio_info *audio_info,
	    const struct drm_connector *drm_connector,
	    const struct dc_sink *dc_sink)
5494{
int i = 0;
int cea_revision = 0;
const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;

audio_info->manufacture_id = edid_caps->manufacturer_id;
audio_info->product_id = edid_caps->product_id;

cea_revision = drm_connector->display_info.cea_rev;

strscpy(audio_info->display_name,
edid_caps->display_name,
AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS20);

if (cea_revision >= 3) {
audio_info->mode_count = edid_caps->audio_mode_count;

for (i = 0; i < audio_info->mode_count; ++i) {
	audio_info->modes[i].format_code =
			(enum audio_format_code)
			(edid_caps->audio_modes[i].format_code);
	audio_info->modes[i].channel_count =
			edid_caps->audio_modes[i].channel_count;
	audio_info->modes[i].sample_rates.all =
			edid_caps->audio_modes[i].sample_rate;
	audio_info->modes[i].sample_size =
			edid_caps->audio_modes[i].sample_size;
}
}

audio_info->flags.all = edid_caps->speaker_flags;

/* TODO: We only check for the progressive mode, check for interlace mode too */
if (drm_connector->latency_present[0]) {
audio_info->video_latency = drm_connector->video_latency[0];
audio_info->audio_latency = drm_connector->audio_latency[0];
}

/* TODO: For DP, video and audio latency should be calculated from DPCD caps */

5534}

5536static void
5537copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
		      struct drm_display_mode *dst_mode)
5539{
dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
dst_mode->crtc_clock = src_mode->crtc_clock;
dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
dst_mode->crtc_htotal = src_mode->crtc_htotal;
dst_mode->crtc_hskew = src_mode->crtc_hskew;
dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
5554}

5556static void
5557decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
			const struct drm_display_mode *native_mode,
			bool_Bool scale_enabled)
5560{
if (scale_enabled) {
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
} else if (native_mode->clock == drm_mode->clock &&
	native_mode->htotal == drm_mode->htotal &&
	native_mode->vtotal == drm_mode->vtotal) {
copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
} else {
/* no scaling nor amdgpu inserted, no need to patch */
}
5570}

5572static struct dc_sink *
5573create_fake_sink(struct amdgpu_dm_connector *aconnector)
5574{
struct dc_sink_init_data sink_init_data = { 0 };
struct dc_sink *sink = NULL((void *)0);

sink_init_data.link = aconnector->dc_link;
sink_init_data.sink_signal = aconnector->dc_link->connector_signal;

sink = dc_sink_create(&sink_init_data);
if (!sink) {
DRM_ERROR("Failed to create sink!\n")__drm_err("Failed to create sink!\n");
return NULL((void *)0);
}
sink->sink_signal = SIGNAL_TYPE_VIRTUAL;

return sink;
5589}

5591static void set_multisync_trigger_params(
struct dc_stream_state *stream)
5593{
struct dc_stream_state *master = NULL((void *)0);

if (stream->triggered_crtc_reset.enabled) {
master = stream->triggered_crtc_reset.event_source;
stream->triggered_crtc_reset.event =
	master->timing.flags.VSYNC_POSITIVE_POLARITY ?
	CRTC_EVENT_VSYNC_RISING : CRTC_EVENT_VSYNC_FALLING;
stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_PIXEL;
}
5603}

5605static void set_master_stream(struct dc_stream_state *stream_set[],
	      int stream_count)
5607{
int j, highest_rfr = 0, master_stream = 0;

for (j = 0;  j < stream_count; j++) {
if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
	int refresh_rate = 0;

	refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
		(stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
	if (refresh_rate > highest_rfr) {
		highest_rfr = refresh_rate;
		master_stream = j;
	}
}
}
for (j = 0;  j < stream_count; j++) {
if (stream_set[j])
	stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
}
5626}

5628static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
5629{
int i = 0;
struct dc_stream_state *stream;

if (context->stream_count < 2)
return;
for (i = 0; i < context->stream_count ; i++) {
if (!context->streams[i])
	continue;
/*
 * TODO: add a function to read AMD VSDB bits and set
 * crtc_sync_master.multi_sync_enabled flag
 * For now it's set to false
 */
}

set_master_stream(context->streams, context->stream_count);

for (i = 0; i < context->stream_count ; i++) {
stream = context->streams[i];

if (!stream)
	continue;

set_multisync_trigger_params(stream);
}
5655}

5657/**
* DOC: FreeSync Video
*
* When a userspace application wants to play a video, the content follows a
* standard format definition that usually specifies the FPS for that format.
* The below list illustrates some video format and the expected FPS,
* respectively:
*
* - TV/NTSC (23.976 FPS)
* - Cinema (24 FPS)
* - TV/PAL (25 FPS)
* - TV/NTSC (29.97 FPS)
* - TV/NTSC (30 FPS)
* - Cinema HFR (48 FPS)
* - TV/PAL (50 FPS)
* - Commonly used (60 FPS)
* - Multiples of 24 (48,72,96 FPS)
*
* The list of standards video format is not huge and can be added to the
* connector modeset list beforehand. With that, userspace can leverage
* FreeSync to extends the front porch in order to attain the target refresh
* rate. Such a switch will happen seamlessly, without screen blanking or
* reprogramming of the output in any other way. If the userspace requests a
* modesetting change compatible with FreeSync modes that only differ in the
* refresh rate, DC will skip the full update and avoid blink during the
* transition. For example, the video player can change the modesetting from
* 60Hz to 30Hz for playing TV/NTSC content when it goes full screen without
* causing any display blink. This same concept can be applied to a mode
* setting change.
*/
5687static struct drm_display_mode *
5688get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector,
bool_Bool use_probed_modes)
5690{
struct drm_display_mode *m, *m_pref = NULL((void *)0);
u16 current_refresh, highest_refresh;
struct list_head *list_head = use_probed_modes ?
&aconnector->base.probed_modes :
&aconnector->base.modes;

if (aconnector->freesync_vid_base.clock != 0)
return &aconnector->freesync_vid_base;

/* Find the preferred mode */
list_for_each_entry(m, list_head, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr
 = ((list_head)->next); (__typeof(*m) *)( (char *)__mptr -
 __builtin_offsetof(__typeof(*m), head) );}); &m->head
 != (list_head); m = ({ const __typeof( ((__typeof(*m) *)0)->
head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*m), head) );})) {
if (m->type & DRM_MODE_TYPE_PREFERRED(1<<3)) {
	m_pref = m;
	break;
}
}

if (!m_pref) {
/* Probably an EDID with no preferred mode. Fallback to first entry */
m_pref = list_first_entry_or_null((list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		&aconnector->base.modes, struct drm_display_mode, head)(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}));
if (!m_pref) {
	DRM_DEBUG_DRIVER("No preferred mode found in EDID\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "No preferred mode found in EDID\n"
);
	return NULL((void *)0);
}
}

highest_refresh = drm_mode_vrefresh(m_pref);

/*
* Find the mode with highest refresh rate with same resolution.
* For some monitors, preferred mode is not the mode with highest
* supported refresh rate.
*/
list_for_each_entry(m, list_head, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr
 = ((list_head)->next); (__typeof(*m) *)( (char *)__mptr -
 __builtin_offsetof(__typeof(*m), head) );}); &m->head
 != (list_head); m = ({ const __typeof( ((__typeof(*m) *)0)->
head ) *__mptr = (m->head.next); (__typeof(*m) *)( (char *
)__mptr - __builtin_offsetof(__typeof(*m), head) );})) {
current_refresh  = drm_mode_vrefresh(m);

if (m->hdisplay == m_pref->hdisplay &&
    m->vdisplay == m_pref->vdisplay &&
    highest_refresh < current_refresh) {
	highest_refresh = current_refresh;
	m_pref = m;
}
}

drm_mode_copy(&aconnector->freesync_vid_base, m_pref);
return m_pref;
5738}

5740static bool_Bool is_freesync_video_mode(const struct drm_display_mode *mode,
struct amdgpu_dm_connector *aconnector)
5742{
struct drm_display_mode *high_mode;
int timing_diff;

high_mode = get_highest_refresh_rate_mode(aconnector, false0);
if (!high_mode || !mode)
return false0;

timing_diff = high_mode->vtotal - mode->vtotal;

if (high_mode->clock == 0 || high_mode->clock != mode->clock ||
   high_mode->hdisplay != mode->hdisplay ||
   high_mode->vdisplay != mode->vdisplay ||
   high_mode->hsync_start != mode->hsync_start ||
   high_mode->hsync_end != mode->hsync_end ||
   high_mode->htotal != mode->htotal ||
   high_mode->hskew != mode->hskew ||
   high_mode->vscan != mode->vscan ||
   high_mode->vsync_start - mode->vsync_start != timing_diff ||
   high_mode->vsync_end - mode->vsync_end != timing_diff)
return false0;
else
return true1;
5765}

5767#if defined(CONFIG_DRM_AMD_DC_DCN1)
5768static void update_dsc_caps(struct amdgpu_dm_connector *aconnector,
	    struct dc_sink *sink, struct dc_stream_state *stream,
	    struct dsc_dec_dpcd_caps *dsc_caps)
5771{
stream->timing.flags.DSC = 0;
dsc_caps->is_dsc_supported = false0;

if (aconnector->dc_link && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT ||
   sink->sink_signal == SIGNAL_TYPE_EDP)) {
if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE ||
	sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
	dc_dsc_parse_dsc_dpcd(aconnector->dc_link->ctx->dc,
		aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
		aconnector->dc_link->dpcd_caps.dsc_caps.dsc_branch_decoder_caps.raw,
		dsc_caps);
}
5784}


5787static void apply_dsc_policy_for_edp(struct amdgpu_dm_connector *aconnector,
		    struct dc_sink *sink, struct dc_stream_state *stream,
		    struct dsc_dec_dpcd_caps *dsc_caps,
		    uint32_t max_dsc_target_bpp_limit_override)
5791{
const struct dc_link_settings *verified_link_cap = NULL((void *)0);
u32 link_bw_in_kbps;
u32 edp_min_bpp_x16, edp_max_bpp_x16;
struct dc *dc = sink->ctx->dc;
struct dc_dsc_bw_range bw_range = {0};
struct dc_dsc_config dsc_cfg = {0};

verified_link_cap = dc_link_get_link_cap(stream->link);
link_bw_in_kbps = dc_link_bandwidth_kbps(stream->link, verified_link_cap);
edp_min_bpp_x16 = 8 * 16;
edp_max_bpp_x16 = 8 * 16;

if (edp_max_bpp_x16 > dsc_caps->edp_max_bits_per_pixel)
edp_max_bpp_x16 = dsc_caps->edp_max_bits_per_pixel;

if (edp_max_bpp_x16 < edp_min_bpp_x16)
edp_min_bpp_x16 = edp_max_bpp_x16;

if (dc_dsc_compute_bandwidth_range(dc->res_pool->dscs[0],
		dc->debug.dsc_min_slice_height_override,
		edp_min_bpp_x16, edp_max_bpp_x16,
		dsc_caps,
		&stream->timing,
		&bw_range)) {

if (bw_range.max_kbps < link_bw_in_kbps) {
	if (dc_dsc_compute_config(dc->res_pool->dscs[0],
			dsc_caps,
			dc->debug.dsc_min_slice_height_override,
			max_dsc_target_bpp_limit_override,
			0,
			&stream->timing,
			&dsc_cfg)) {
		stream->timing.dsc_cfg = dsc_cfg;
		stream->timing.flags.DSC = 1;
		stream->timing.dsc_cfg.bits_per_pixel = edp_max_bpp_x16;
	}
	return;
}
}

if (dc_dsc_compute_config(dc->res_pool->dscs[0],
		dsc_caps,
		dc->debug.dsc_min_slice_height_override,
		max_dsc_target_bpp_limit_override,
		link_bw_in_kbps,
		&stream->timing,
		&dsc_cfg)) {
stream->timing.dsc_cfg = dsc_cfg;
stream->timing.flags.DSC = 1;
}
5843}


5846static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector,
			struct dc_sink *sink, struct dc_stream_state *stream,
			struct dsc_dec_dpcd_caps *dsc_caps)
5849{
struct drm_connector *drm_connector = &aconnector->base;
u32 link_bandwidth_kbps;
struct dc *dc = sink->ctx->dc;
u32 max_supported_bw_in_kbps, timing_bw_in_kbps;
u32 dsc_max_supported_bw_in_kbps;
u32 max_dsc_target_bpp_limit_override =
drm_connector->display_info.max_dsc_bpp;

link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
					dc_link_get_link_cap(aconnector->dc_link));

/* Set DSC policy according to dsc_clock_en */
dc_dsc_policy_set_enable_dsc_when_not_needed(
aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE);

if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_EDP &&
   !aconnector->dc_link->panel_config.dsc.disable_dsc_edp &&
   dc->caps.edp_dsc_support && aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE) {

apply_dsc_policy_for_edp(aconnector, sink, stream, dsc_caps, max_dsc_target_bpp_limit_override);

} else if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) {
	if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
				dsc_caps,
				aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
				max_dsc_target_bpp_limit_override,
				link_bandwidth_kbps,
				&stream->timing,
				&stream->timing.dsc_cfg)) {
		stream->timing.flags.DSC = 1;
		DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: [%s] DSC is selected from SST RX\n"
, __func__, drm_connector->name);
	}
} else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) {
	timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing);
	max_supported_bw_in_kbps = link_bandwidth_kbps;
	dsc_max_supported_bw_in_kbps = link_bandwidth_kbps;

	if (timing_bw_in_kbps > max_supported_bw_in_kbps &&
			max_supported_bw_in_kbps > 0 &&
			dsc_max_supported_bw_in_kbps > 0)
		if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc->res_pool->dscs[0],
				dsc_caps,
				aconnector->dc_link->ctx->dc->debug.dsc_min_slice_height_override,
				max_dsc_target_bpp_limit_override,
				dsc_max_supported_bw_in_kbps,
				&stream->timing,
				&stream->timing.dsc_cfg)) {
			stream->timing.flags.DSC = 1;
			DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: [%s] DSC is selected from DP-HDMI PCON\n"
, __func__, drm_connector->name)
							 __func__, drm_connector->name)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: [%s] DSC is selected from DP-HDMI PCON\n"
, __func__, drm_connector->name);
		}
}
}

/* Overwrite the stream flag if DSC is enabled through debugfs */
if (aconnector->dsc_settings.dsc_force_enable == DSC_CLK_FORCE_ENABLE)
stream->timing.flags.DSC = 1;

if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_h)
stream->timing.dsc_cfg.num_slices_h = aconnector->dsc_settings.dsc_num_slices_h;

if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_num_slices_v)
stream->timing.dsc_cfg.num_slices_v = aconnector->dsc_settings.dsc_num_slices_v;

if (stream->timing.flags.DSC && aconnector->dsc_settings.dsc_bits_per_pixel)
stream->timing.dsc_cfg.bits_per_pixel = aconnector->dsc_settings.dsc_bits_per_pixel;
5917}
5918#endif /* CONFIG_DRM_AMD_DC_DCN */

5920static struct dc_stream_state *
5921create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
       const struct drm_display_mode *drm_mode,
       const struct dm_connector_state *dm_state,
       const struct dc_stream_state *old_stream,
       int requested_bpc)
5926{
struct drm_display_mode *preferred_mode = NULL((void *)0);
struct drm_connector *drm_connector;
const struct drm_connector_state *con_state =
dm_state ? &dm_state->base : NULL((void *)0);
struct dc_stream_state *stream = NULL((void *)0);
struct drm_display_mode mode = *drm_mode;
struct drm_display_mode saved_mode;
struct drm_display_mode *freesync_mode = NULL((void *)0);
bool_Bool native_mode_found = false0;
bool_Bool recalculate_timing = false0;
bool_Bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false0;
int mode_refresh;
int preferred_refresh = 0;
5940#if defined(CONFIG_DRM_AMD_DC_DCN1)
struct dsc_dec_dpcd_caps dsc_caps;
5942#endif

struct dc_sink *sink = NULL((void *)0);

memset(&saved_mode, 0, sizeof(saved_mode))__builtin_memset((&saved_mode), (0), (sizeof(saved_mode))
);

if (aconnector == NULL((void *)0)) {
DRM_ERROR("aconnector is NULL!\n")__drm_err("aconnector is NULL!\n");
return stream;
}

drm_connector = &aconnector->base;

if (!aconnector->dc_sink) {
sink = create_fake_sink(aconnector);
if (!sink)
	return stream;
} else {
sink = aconnector->dc_sink;
dc_sink_retain(sink);
}

stream = dc_create_stream_for_sink(sink);

if (stream == NULL((void *)0)) {
DRM_ERROR("Failed to create stream for sink!\n")__drm_err("Failed to create stream for sink!\n");
goto finish;
}

stream->dm_stream_context = aconnector;

stream->timing.flags.LTE_340MCSC_SCRAMBLE =
drm_connector->display_info.hdmi.scdc.scrambling.low_rates;

list_for_each_entry(preferred_mode, &aconnector->base.modes, head)for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&aconnector->base.modes)
->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&aconnector->base.modes); preferred_mode = ({
 const __typeof( ((__typeof(*preferred_mode) *)0)->head ) *
__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );})) {
/* Search for preferred mode */
if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED(1<<3)) {
	native_mode_found = true1;
	break;
}
}
if (!native_mode_found)
preferred_mode = list_first_entry_or_null((list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		&aconnector->base.modes,(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		struct drm_display_mode,(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}))
		head)(list_empty(&aconnector->base.modes) ? ((void *)0) : (
{ const __typeof( ((struct drm_display_mode *)0)->head ) *
__mptr = ((&aconnector->base.modes)->next); (struct
 drm_display_mode *)( (char *)__mptr - __builtin_offsetof(struct
 drm_display_mode, head) );}));

mode_refresh = drm_mode_vrefresh(&mode);

if (preferred_mode == NULL((void *)0)) {
/*
 * This may not be an error, the use case is when we have no
 * usermode calls to reset and set mode upon hotplug. In this
 * case, we call set mode ourselves to restore the previous mode
 * and the modelist may not be filled in time.
 */
DRM_DEBUG_DRIVER("No preferred mode found\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "No preferred mode found\n"
);
} else {
recalculate_timing = is_freesync_video_mode(&mode, aconnector);
if (recalculate_timing) {
	freesync_mode = get_highest_refresh_rate_mode(aconnector, false0);
	drm_mode_copy(&saved_mode, &mode);
	drm_mode_copy(&mode, freesync_mode);
} else {
	decide_crtc_timing_for_drm_display_mode(
			&mode, preferred_mode, scale);

	preferred_refresh = drm_mode_vrefresh(preferred_mode);
}
}

if (recalculate_timing)
drm_mode_set_crtcinfo(&saved_mode, 0);
else if (!dm_state)
drm_mode_set_crtcinfo(&mode, 0);

/*
* If scaling is enabled and refresh rate didn't change
* we copy the vic and polarities of the old timings
*/
if (!scale || mode_refresh != preferred_refresh)
fill_stream_properties_from_drm_display_mode(
	stream, &mode, &aconnector->base, con_state, NULL((void *)0),
	requested_bpc);
else
fill_stream_properties_from_drm_display_mode(
	stream, &mode, &aconnector->base, con_state, old_stream,
	requested_bpc);

if (aconnector->timing_changed) {
DC_LOG_DEBUG("%s: overriding timing for automated test, bpc %d, changing to %d\n",___drm_dbg(((void *)0), DRM_UT_KMS, "%s: overriding timing for automated test, bpc %d, changing to %d\n"
, __func__, stream->timing.display_color_depth, aconnector
->timing_requested->display_color_depth)
		__func__,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: overriding timing for automated test, bpc %d, changing to %d\n"
, __func__, stream->timing.display_color_depth, aconnector
->timing_requested->display_color_depth)
		stream->timing.display_color_depth,___drm_dbg(((void *)0), DRM_UT_KMS, "%s: overriding timing for automated test, bpc %d, changing to %d\n"
, __func__, stream->timing.display_color_depth, aconnector
->timing_requested->display_color_depth)
		aconnector->timing_requested->display_color_depth)___drm_dbg(((void *)0), DRM_UT_KMS, "%s: overriding timing for automated test, bpc %d, changing to %d\n"
, __func__, stream->timing.display_color_depth, aconnector
->timing_requested->display_color_depth);
stream->timing = *aconnector->timing_requested;
}

6039#if defined(CONFIG_DRM_AMD_DC_DCN1)
/* SST DSC determination policy */
update_dsc_caps(aconnector, sink, stream, &dsc_caps);
if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported)
apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps);
6044#endif

update_stream_scaling_settings(&mode, dm_state, stream);

fill_audio_info(
&stream->audio_info,
drm_connector,
sink);

update_stream_signal(stream, sink);

if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
mod_build_hf_vsif_infopacket(stream, &stream->vsp_infopacket);

if (stream->link->psr_settings.psr_feature_enabled) {
//
// should decide stream support vsc sdp colorimetry capability
// before building vsc info packet
//
stream->use_vsc_sdp_for_colorimetry = false0;
if (aconnector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
	stream->use_vsc_sdp_for_colorimetry =
		aconnector->dc_sink->is_vsc_sdp_colorimetry_supported;
} else {
	if (stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED)
		stream->use_vsc_sdp_for_colorimetry = true1;
}
mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space);
aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY5;

}
6075finish:
dc_sink_release(sink);

return stream;
6079}

6081static enum drm_connector_status
6082amdgpu_dm_connector_detect(struct drm_connector *connector, bool_Bool force)
6083{
bool_Bool connected;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

/*
* Notes:
* 1. This interface is NOT called in context of HPD irq.
* 2. This interface *is called* in context of user-mode ioctl. Which
* makes it a bad place for *any* MST-related activity.
*/

if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
   !aconnector->fake_enable)
connected = (aconnector->dc_sink != NULL((void *)0));
else
connected = (aconnector->base.force == DRM_FORCE_ON ||
		aconnector->base.force == DRM_FORCE_ON_DIGITAL);

update_subconnector_property(aconnector);

return (connected ? connector_status_connected :
	connector_status_disconnected);
6105}

6107int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
			    struct drm_connector_state *connector_state,
			    struct drm_property *property,
			    uint64_t val)
6111{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_connector_state *dm_old_state =
to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});
struct dm_connector_state *dm_new_state =
to_dm_connector_state(connector_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector_state)); (struct dm_connector_state *)
( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

int ret = -EINVAL22;

if (property == dev->mode_config.scaling_mode_property) {
enum amdgpu_rmx_type rmx_type;

switch (val) {
case DRM_MODE_SCALE_CENTER2:
	rmx_type = RMX_CENTER;
	break;
case DRM_MODE_SCALE_ASPECT3:
	rmx_type = RMX_ASPECT;
	break;
case DRM_MODE_SCALE_FULLSCREEN1:
	rmx_type = RMX_FULL;
	break;
case DRM_MODE_SCALE_NONE0:
default:
	rmx_type = RMX_OFF;
	break;
}

if (dm_old_state->scaling == rmx_type)
	return 0;

dm_new_state->scaling = rmx_type;
ret = 0;
} else if (property == adev->mode_info.underscan_hborder_property) {
dm_new_state->underscan_hborder = val;
ret = 0;
} else if (property == adev->mode_info.underscan_vborder_property) {
dm_new_state->underscan_vborder = val;
ret = 0;
} else if (property == adev->mode_info.underscan_property) {
dm_new_state->underscan_enable = val;
ret = 0;
} else if (property == adev->mode_info.abm_level_property) {
dm_new_state->abm_level = val ?: ABM_LEVEL_IMMEDIATE_DISABLE255;
ret = 0;
}

return ret;
6160}

6162int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
			    const struct drm_connector_state *state,
			    struct drm_property *property,
			    uint64_t *val)
6166{
struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_connector_state *dm_state =
to_dm_connector_state(state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((state)); (struct dm_connector_state *)( (char *)
__mptr - __builtin_offsetof(struct dm_connector_state, base) )
;});
int ret = -EINVAL22;

if (property == dev->mode_config.scaling_mode_property) {
switch (dm_state->scaling) {
case RMX_CENTER:
	*val = DRM_MODE_SCALE_CENTER2;
	break;
case RMX_ASPECT:
	*val = DRM_MODE_SCALE_ASPECT3;
	break;
case RMX_FULL:
	*val = DRM_MODE_SCALE_FULLSCREEN1;
	break;
case RMX_OFF:
default:
	*val = DRM_MODE_SCALE_NONE0;
	break;
}
ret = 0;
} else if (property == adev->mode_info.underscan_hborder_property) {
*val = dm_state->underscan_hborder;
ret = 0;
} else if (property == adev->mode_info.underscan_vborder_property) {
*val = dm_state->underscan_vborder;
ret = 0;
} else if (property == adev->mode_info.underscan_property) {
*val = dm_state->underscan_enable;
ret = 0;
} else if (property == adev->mode_info.abm_level_property) {
*val = (dm_state->abm_level != ABM_LEVEL_IMMEDIATE_DISABLE255) ?
	dm_state->abm_level : 0;
ret = 0;
}

return ret;
6206}

6208static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
6209{
struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
6213}

6215static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
6216{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
const struct dc_link *link = aconnector->dc_link;
struct amdgpu_device *adev = drm_to_adev(connector->dev);
struct amdgpu_display_manager *dm = &adev->dm;
int i;

/*
* Call only if mst_mgr was initialized before since it's not done
* for all connector types.
*/
if (aconnector->mst_mgr.dev)
drm_dp_mst_topology_mgr_destroy(&aconnector->mst_mgr);

6230#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE1) ||\
defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
for (i = 0; i < dm->num_of_edps; i++) {
if ((link == dm->backlight_link[i]) && dm->backlight_dev[i]) {
	backlight_device_unregister(dm->backlight_dev[i]);
	dm->backlight_dev[i] = NULL((void *)0);
}
}
6238#endif

if (aconnector->dc_em_sink)
dc_sink_release(aconnector->dc_em_sink);
aconnector->dc_em_sink = NULL((void *)0);
if (aconnector->dc_sink)
dc_sink_release(aconnector->dc_sink);
aconnector->dc_sink = NULL((void *)0);

drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
drm_connector_unregister(connector);
drm_connector_cleanup(connector);
if (aconnector->i2c) {
i2c_del_adapter(&aconnector->i2c->base);
kfree(aconnector->i2c);
}
kfree(aconnector->dm_dp_aux.aux.name);

kfree(connector);
6257}

6259void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
6260{
struct dm_connector_state *state =
to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

if (connector->state)
__drm_atomic_helper_connector_destroy_state(connector->state);

kfree(state);

state = kzalloc(sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));

if (state) {
state->scaling = RMX_OFF;
state->underscan_enable = false0;
state->underscan_hborder = 0;
state->underscan_vborder = 0;
state->base.max_requested_bpc = 8;
state->vcpi_slots = 0;
state->pbn = 0;

if (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)
	state->abm_level = amdgpu_dm_abm_level ?:
		ABM_LEVEL_IMMEDIATE_DISABLE255;

__drm_atomic_helper_connector_reset(connector, &state->base);
}
6286}

6288struct drm_connector_state *
6289amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
6290{
struct dm_connector_state *state =
to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

struct dm_connector_state *new_state =
	kmemdup(state, sizeof(*state), GFP_KERNEL(0x0001 | 0x0004));

if (!new_state)
return NULL((void *)0);

__drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);

new_state->freesync_capable = state->freesync_capable;
new_state->abm_level = state->abm_level;
new_state->scaling = state->scaling;
new_state->underscan_enable = state->underscan_enable;
new_state->underscan_hborder = state->underscan_hborder;
new_state->underscan_vborder = state->underscan_vborder;
new_state->vcpi_slots = state->vcpi_slots;
new_state->pbn = state->pbn;
return &new_state->base;
6311}

6313static int
6314amdgpu_dm_connector_late_register(struct drm_connector *connector)
6315{
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
int r;

if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort10) ||
   (connector->connector_type == DRM_MODE_CONNECTOR_eDP14)) {
amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
if (r)
	return r;
}

6328#if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector);
6330#endif

return 0;
6333}

6335static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
.reset = amdgpu_dm_connector_funcs_reset,
.detect = amdgpu_dm_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = amdgpu_dm_connector_destroy,
.atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
.atomic_set_property = amdgpu_dm_connector_atomic_set_property,
.atomic_get_property = amdgpu_dm_connector_atomic_get_property,
.late_register = amdgpu_dm_connector_late_register,
.early_unregister = amdgpu_dm_connector_unregister
6346};

6348static int get_modes(struct drm_connector *connector)
6349{
return amdgpu_dm_connector_get_modes(connector);
6351}

6353static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
6354{
struct dc_sink_init_data init_params = {
	.link = aconnector->dc_link,
	.sink_signal = SIGNAL_TYPE_VIRTUAL
};
struct edid *edid;

if (!aconnector->base.edid_blob_ptr) {
DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",__drm_err("No EDID firmware found on connector: %s ,forcing to OFF!\n"
, aconnector->base.name)
		aconnector->base.name)__drm_err("No EDID firmware found on connector: %s ,forcing to OFF!\n"
, aconnector->base.name);

aconnector->base.force = DRM_FORCE_OFF;
aconnector->base.override_edid = false0;
return;
}

edid = (struct edid *) aconnector->base.edid_blob_ptr->data;

aconnector->edid = edid;

aconnector->dc_em_sink = dc_link_add_remote_sink(
aconnector->dc_link,
(uint8_t *)edid,
(edid->extensions + 1) * EDID_LENGTH128,
&init_params);

if (aconnector->base.force == DRM_FORCE_ON) {
aconnector->dc_sink = aconnector->dc_link->local_sink ?
aconnector->dc_link->local_sink :
aconnector->dc_em_sink;
dc_sink_retain(aconnector->dc_sink);
}
6386}

6388static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
6389{
struct dc_link *link = (struct dc_link *)aconnector->dc_link;

/*
* In case of headless boot with force on for DP managed connector
* Those settings have to be != 0 to get initial modeset
*/
if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
}


aconnector->base.override_edid = true1;
create_eml_sink(aconnector);
6404}

6406struct dc_stream_state *
6407create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector,
		const struct drm_display_mode *drm_mode,
		const struct dm_connector_state *dm_state,
		const struct dc_stream_state *old_stream)
6411{
struct drm_connector *connector = &aconnector->base;
struct amdgpu_device *adev = drm_to_adev(connector->dev);
struct dc_stream_state *stream;
const struct drm_connector_state *drm_state = dm_state ? &dm_state->base : NULL((void *)0);
int requested_bpc = drm_state ? drm_state->max_requested_bpc : 8;
enum dc_status dc_result = DC_OK;

do {
stream = create_stream_for_sink(aconnector, drm_mode,
				dm_state, old_stream,
				requested_bpc);
if (stream == NULL((void *)0)) {
	DRM_ERROR("Failed to create stream for sink!\n")__drm_err("Failed to create stream for sink!\n");
	break;
}

dc_result = dc_validate_stream(adev->dm.dc, stream);
if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
	dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream);

if (dc_result != DC_OK) {
	DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n",___drm_dbg(((void *)0), DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      drm_mode->hdisplay,___drm_dbg(((void *)0), DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      drm_mode->vdisplay,___drm_dbg(((void *)0), DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      drm_mode->clock,___drm_dbg(((void *)0), DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      dc_result,___drm_dbg(((void *)0), DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result))
		      dc_status_to_str(dc_result))___drm_dbg(((void *)0), DRM_UT_KMS, "Mode %dx%d (clk %d) failed DC validation with error %d (%s)\n"
, drm_mode->hdisplay, drm_mode->vdisplay, drm_mode->
clock, dc_result, dc_status_to_str(dc_result));

	dc_stream_release(stream);
	stream = NULL((void *)0);
	requested_bpc -= 2; /* lower bpc to retry validation */
}

} while (stream == NULL((void *)0) && requested_bpc >= 6);

if (dc_result == DC_FAIL_ENC_VALIDATE && !aconnector->force_yuv420_output) {
DRM_DEBUG_KMS("Retry forcing YCbCr420 encoding\n")___drm_dbg(((void *)0), DRM_UT_KMS, "Retry forcing YCbCr420 encoding\n"
);

aconnector->force_yuv420_output = true1;
stream = create_validate_stream_for_sink(aconnector, drm_mode,
				dm_state, old_stream);
aconnector->force_yuv420_output = false0;
}

return stream;
6457}

6459enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
		   struct drm_display_mode *mode)
6461{
int result = MODE_ERROR;
struct dc_sink *dc_sink;
/* TODO: Unhardcode stream count */
struct dc_stream_state *stream;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if ((mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4)) ||
	(mode->flags & DRM_MODE_FLAG_DBLSCAN(1<<5)))
return result;

/*
* Only run this the first time mode_valid is called to initilialize
* EDID mgmt
*/
if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
!aconnector->dc_em_sink)
handle_edid_mgmt(aconnector);

dc_sink = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );})->dc_sink;

if (dc_sink == NULL((void *)0) && aconnector->base.force != DRM_FORCE_ON_DIGITAL &&
		aconnector->base.force != DRM_FORCE_ON) {
DRM_ERROR("dc_sink is NULL!\n")__drm_err("dc_sink is NULL!\n");
goto fail;
}

stream = create_validate_stream_for_sink(aconnector, mode, NULL((void *)0), NULL((void *)0));
if (stream) {
dc_stream_release(stream);
result = MODE_OK;
}

6494fail:
/* TODO: error handling*/
return result;
6497}

6499static int fill_hdr_info_packet(const struct drm_connector_state *state,
		struct dc_info_packet *out)
6501{
struct hdmi_drm_infoframe frame;
unsigned char buf[30]; /* 26 + 4 */
ssize_t len;
int ret, i;

memset(out, 0, sizeof(*out))__builtin_memset((out), (0), (sizeof(*out)));

if (!state->hdr_output_metadata)
return 0;

ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
if (ret)
return ret;

len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
if (len < 0)
return (int)len;

/* Static metadata is a fixed 26 bytes + 4 byte header. */
if (len != 30)
return -EINVAL22;

/* Prepare the infopacket for DC. */
switch (state->connector->connector_type) {
case DRM_MODE_CONNECTOR_HDMIA11:
out->hb0 = 0x87; /* type */
out->hb1 = 0x01; /* version */
out->hb2 = 0x1A; /* length */
out->sb[0] = buf[3]; /* checksum */
i = 1;
break;

case DRM_MODE_CONNECTOR_DisplayPort10:
case DRM_MODE_CONNECTOR_eDP14:
out->hb0 = 0x00; /* sdp id, zero */
out->hb1 = 0x87; /* type */
out->hb2 = 0x1D; /* payload len - 1 */
out->hb3 = (0x13 << 2); /* sdp version */
out->sb[0] = 0x01; /* version */
out->sb[1] = 0x1A; /* length */
i = 2;
break;

default:
return -EINVAL22;
}

memcpy(&out->sb[i], &buf[4], 26)__builtin_memcpy((&out->sb[i]), (&buf[4]), (26));
out->valid = true1;

print_hex_dump(KERN_DEBUG"\0017", "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
       sizeof(out->sb), false0);

return 0;
6556}

6558static int
6559amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
		 struct drm_atomic_state *state)
6561{
struct drm_connector_state *new_con_state =
drm_atomic_get_new_connector_state(state, conn);
struct drm_connector_state *old_con_state =
drm_atomic_get_old_connector_state(state, conn);
struct drm_crtc *crtc = new_con_state->crtc;
struct drm_crtc_state *new_crtc_state;
struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (conn); (struct amdgpu_dm_connector *)( (char *)
__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base)
 );});
int ret;

trace_amdgpu_dm_connector_atomic_check(new_con_state);

if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort10) {
ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr);
if (ret < 0)
	return ret;
}

if (!crtc)
return 0;

if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) {
struct dc_info_packet hdr_infopacket;

ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
if (ret)
	return ret;

new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
if (IS_ERR(new_crtc_state))
	return PTR_ERR(new_crtc_state);

/*
 * DC considers the stream backends changed if the
 * static metadata changes. Forcing the modeset also
 * gives a simple way for userspace to switch from
 * 8bpc to 10bpc when setting the metadata to enter
 * or exit HDR.
 *
 * Changing the static metadata after it's been
 * set is permissible, however. So only force a
 * modeset if we're entering or exiting HDR.
 */
new_crtc_state->mode_changed =
	!old_con_state->hdr_output_metadata ||
	!new_con_state->hdr_output_metadata;
}

return 0;
6610}

6612static const struct drm_connector_helper_funcs
6613amdgpu_dm_connector_helper_funcs = {
/*
* If hotplugging a second bigger display in FB Con mode, bigger resolution
* modes will be filtered by drm_mode_validate_size(), and those modes
* are missing after user start lightdm. So we need to renew modes list.
* in get_modes call back, not just return the modes count
*/
.get_modes = get_modes,
.mode_valid = amdgpu_dm_connector_mode_valid,
.atomic_check = amdgpu_dm_connector_atomic_check,
6623};

6625static void dm_encoder_helper_disable(struct drm_encoder *encoder)
6626{

6628}

6630int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth)
6631{
switch (display_color_depth) {
case COLOR_DEPTH_666:
return 6;
case COLOR_DEPTH_888:
return 8;
case COLOR_DEPTH_101010:
return 10;
case COLOR_DEPTH_121212:
return 12;
case COLOR_DEPTH_141414:
return 14;
case COLOR_DEPTH_161616:
return 16;
default:
break;
}
return 0;
6649}

6651static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
			  struct drm_crtc_state *crtc_state,
			  struct drm_connector_state *conn_state)
6654{
struct drm_atomic_state *state = crtc_state->state;
struct drm_connector *connector = conn_state->connector;
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct dm_connector_state *dm_new_connector_state = to_dm_connector_state(conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((conn_state)); (struct dm_connector_state *)( (char
 *)__mptr - __builtin_offsetof(struct dm_connector_state, base
) );});
const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
struct drm_dp_mst_topology_mgr *mst_mgr;
struct drm_dp_mst_port *mst_port;
struct drm_dp_mst_topology_state *mst_state;
enum dc_color_depth color_depth;
int clock, bpp = 0;
bool_Bool is_y420 = false0;

if (!aconnector->port)
return 0;

mst_port = aconnector->port;
mst_mgr = &aconnector->mst_port->mst_mgr;

if (!crtc_state->connectors_changed && !crtc_state->mode_changed)
return 0;

mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr);
if (IS_ERR(mst_state))
return PTR_ERR(mst_state);

if (!mst_state->pbn_div)
mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_port->dc_link);

if (!state->duplicated) {
int max_bpc = conn_state->max_requested_bpc;

is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&
	  aconnector->force_yuv420_output;
color_depth = convert_color_depth_from_display_info(connector,
						    is_y420,
						    max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false0);
}

dm_new_connector_state->vcpi_slots =
drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port,
			      dm_new_connector_state->pbn);
if (dm_new_connector_state->vcpi_slots < 0) {
DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "failed finding vcpi slots: %d\n"
, (int)dm_new_connector_state->vcpi_slots);
return dm_new_connector_state->vcpi_slots;
}
return 0;
6704}

6706const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
.disable = dm_encoder_helper_disable,
.atomic_check = dm_encoder_helper_atomic_check
6709};

6711#if defined(CONFIG_DRM_AMD_DC_DCN1)
6712static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
			    struct dc_state *dc_state,
			    struct dsc_mst_fairness_vars *vars)
6715{
struct dc_stream_state *stream = NULL((void *)0);
struct drm_connector *connector;
struct drm_connector_state *new_con_state;
struct amdgpu_dm_connector *aconnector;
struct dm_connector_state *dm_conn_state;
int i, j, ret;
int vcpi, pbn_div, pbn, slot_num = 0;

for_each_new_connector_in_state(state, connector, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (new_con_state) =
 (state)->connectors[i].new_state, (void)(new_con_state) ,
 1))) {} else {

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (!aconnector->port)
	continue;

if (!new_con_state || !new_con_state->crtc)
	continue;

dm_conn_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});

for (j = 0; j < dc_state->stream_count; j++) {
	stream = dc_state->streams[j];
	if (!stream)
		continue;

	if ((struct amdgpu_dm_connector *)stream->dm_stream_context == aconnector)
		break;

	stream = NULL((void *)0);
}

if (!stream)
	continue;

pbn_div = dm_mst_get_pbn_divider(stream->link);
/* pbn is calculated by compute_mst_dsc_configs_for_state*/
for (j = 0; j < dc_state->stream_count; j++) {
	if (vars[j].aconnector == aconnector) {
		pbn = vars[j].pbn;
		break;
	}
}

if (j == dc_state->stream_count)
	continue;

slot_num = DIV_ROUND_UP(pbn, pbn_div)(((pbn) + ((pbn_div) - 1)) / (pbn_div));

if (stream->timing.flags.DSC != 1) {
	dm_conn_state->pbn = pbn;
	dm_conn_state->vcpi_slots = slot_num;

	ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->port,
					   dm_conn_state->pbn, false0);
	if (ret < 0)
		return ret;

	continue;
}

vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->port, pbn, true1);
if (vcpi < 0)
	return vcpi;

dm_conn_state->pbn = pbn;
dm_conn_state->vcpi_slots = vcpi;
}
return 0;
6784}
6785#endif

6787static int to_drm_connector_type(enum amd_signal_type st)
6788{
switch (st) {
case SIGNAL_TYPE_HDMI_TYPE_A:
return DRM_MODE_CONNECTOR_HDMIA11;
case SIGNAL_TYPE_EDP:
return DRM_MODE_CONNECTOR_eDP14;
case SIGNAL_TYPE_LVDS:
return DRM_MODE_CONNECTOR_LVDS7;
case SIGNAL_TYPE_RGB:
return DRM_MODE_CONNECTOR_VGA1;
case SIGNAL_TYPE_DISPLAY_PORT:
case SIGNAL_TYPE_DISPLAY_PORT_MST:
return DRM_MODE_CONNECTOR_DisplayPort10;
case SIGNAL_TYPE_DVI_DUAL_LINK:
case SIGNAL_TYPE_DVI_SINGLE_LINK:
return DRM_MODE_CONNECTOR_DVID3;
case SIGNAL_TYPE_VIRTUAL:
return DRM_MODE_CONNECTOR_VIRTUAL15;

default:
return DRM_MODE_CONNECTOR_Unknown0;
}
6810}

6812static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector)
6813{
struct drm_encoder *encoder;

/* There is only one encoder per connector */
drm_connector_for_each_possible_encoder(connector, encoder)for ((encoder) = ({ const __typeof( ((__typeof(*(encoder)) *)
0)->head ) *__mptr = ((&((connector)->dev)->mode_config
.encoder_list)->next); (__typeof(*(encoder)) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*(encoder)), head) );}); &
(encoder)->head != (&((connector)->dev)->mode_config
.encoder_list); (encoder) = ({ const __typeof( ((__typeof(*(encoder
)) *)0)->head ) *__mptr = ((encoder)->head.next); (__typeof
(*(encoder)) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*(encoder)), head) );})) if (!(((connector)->possible_encoders
) & drm_encoder_mask(encoder))) {} else
return encoder;

return NULL((void *)0);
6821}

6823static void amdgpu_dm_get_native_mode(struct drm_connector *connector)
6824{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;

encoder = amdgpu_dm_connector_to_encoder(connector);

if (encoder == NULL((void *)0))
return;

amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});

amdgpu_encoder->native_mode.clock = 0;

if (!list_empty(&connector->probed_modes)) {
struct drm_display_mode *preferred_mode = NULL((void *)0);

list_for_each_entry(preferred_mode,for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&connector->probed_modes
)->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&connector->probed_modes); preferred_mode = (
{ const __typeof( ((__typeof(*preferred_mode) *)0)->head )
 *__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );}))
		    &connector->probed_modes,for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&connector->probed_modes
)->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&connector->probed_modes); preferred_mode = (
{ const __typeof( ((__typeof(*preferred_mode) *)0)->head )
 *__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );}))
		    head)for (preferred_mode = ({ const __typeof( ((__typeof(*preferred_mode
) *)0)->head ) *__mptr = ((&connector->probed_modes
)->next); (__typeof(*preferred_mode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*preferred_mode), head) );}); &preferred_mode->
head != (&connector->probed_modes); preferred_mode = (
{ const __typeof( ((__typeof(*preferred_mode) *)0)->head )
 *__mptr = (preferred_mode->head.next); (__typeof(*preferred_mode
) *)( (char *)__mptr - __builtin_offsetof(__typeof(*preferred_mode
), head) );})) {
	if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED(1<<3))
		amdgpu_encoder->native_mode = *preferred_mode;

	break;
}

}
6850}

6852static struct drm_display_mode *
6853amdgpu_dm_create_common_mode(struct drm_encoder *encoder,
	     char *name,
	     int hdisplay, int vdisplay)
6856{
struct drm_device *dev = encoder->dev;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
struct drm_display_mode *mode = NULL((void *)0);
struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;

mode = drm_mode_duplicate(dev, native_mode);

if (mode == NULL((void *)0))
return NULL((void *)0);

mode->hdisplay = hdisplay;
mode->vdisplay = vdisplay;
mode->type &= ~DRM_MODE_TYPE_PREFERRED(1<<3);
strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN32);

return mode;

6874}

6876static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder,
				 struct drm_connector *connector)
6878{
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});
struct drm_display_mode *mode = NULL((void *)0);
struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode;
struct amdgpu_dm_connector *amdgpu_dm_connector =
		to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
int i;
int n;
struct mode_size {
char name[DRM_DISPLAY_MODE_LEN32];
int w;
int h;
} common_modes[] = {
{  "640x480",  640,  480},
{  "800x600",  800,  600},
{ "1024x768", 1024,  768},
{ "1280x720", 1280,  720},
{ "1280x800", 1280,  800},
{"1280x1024", 1280, 1024},
{ "1440x900", 1440,  900},
{"1680x1050", 1680, 1050},
{"1600x1200", 1600, 1200},
{"1920x1080", 1920, 1080},
{"1920x1200", 1920, 1200}
};

n = ARRAY_SIZE(common_modes)(sizeof((common_modes)) / sizeof((common_modes)[0]));

for (i = 0; i < n; i++) {
struct drm_display_mode *curmode = NULL((void *)0);
bool_Bool mode_existed = false0;

if (common_modes[i].w > native_mode->hdisplay ||
    common_modes[i].h > native_mode->vdisplay ||
   (common_modes[i].w == native_mode->hdisplay &&
    common_modes[i].h == native_mode->vdisplay))
	continue;

list_for_each_entry(curmode, &connector->probed_modes, head)for (curmode = ({ const __typeof( ((__typeof(*curmode) *)0)->
head ) *__mptr = ((&connector->probed_modes)->next)
; (__typeof(*curmode) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*curmode), head) );}); &curmode->head != (&
connector->probed_modes); curmode = ({ const __typeof( ((__typeof
(*curmode) *)0)->head ) *__mptr = (curmode->head.next);
 (__typeof(*curmode) *)( (char *)__mptr - __builtin_offsetof(
__typeof(*curmode), head) );})) {
	if (common_modes[i].w == curmode->hdisplay &&
	    common_modes[i].h == curmode->vdisplay) {
		mode_existed = true1;
		break;
	}
}

if (mode_existed)
	continue;

mode = amdgpu_dm_create_common_mode(encoder,
		common_modes[i].name, common_modes[i].w,
		common_modes[i].h);
if (!mode)
	continue;

drm_mode_probed_add(connector, mode);
amdgpu_dm_connector->num_modes++;
}
6936}

6938static void amdgpu_set_panel_orientation(struct drm_connector *connector)
6939{
struct drm_encoder *encoder;
struct amdgpu_encoder *amdgpu_encoder;
const struct drm_display_mode *native_mode;

if (connector->connector_type != DRM_MODE_CONNECTOR_eDP14 &&
   connector->connector_type != DRM_MODE_CONNECTOR_LVDS7)
return;

mutex_lock(&connector->dev->mode_config.mutex)rw_enter_write(&connector->dev->mode_config.mutex);
amdgpu_dm_connector_get_modes(connector);
mutex_unlock(&connector->dev->mode_config.mutex)rw_exit_write(&connector->dev->mode_config.mutex);

encoder = amdgpu_dm_connector_to_encoder(connector);
if (!encoder)
return;

amdgpu_encoder = to_amdgpu_encoder(encoder)({ const __typeof( ((struct amdgpu_encoder *)0)->base ) *__mptr
 = (encoder); (struct amdgpu_encoder *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_encoder, base) );});

native_mode = &amdgpu_encoder->native_mode;
if (native_mode->hdisplay == 0 || native_mode->vdisplay == 0)
return;

drm_connector_set_panel_orientation_with_quirk(connector,
				       DRM_MODE_PANEL_ORIENTATION_UNKNOWN,
				       native_mode->hdisplay,
				       native_mode->vdisplay);
6966}

6968static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector,
			      struct edid *edid)
6970{
struct amdgpu_dm_connector *amdgpu_dm_connector =
	to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (edid) {
/* empty probed_modes */
INIT_LIST_HEAD(&connector->probed_modes);
amdgpu_dm_connector->num_modes =
		drm_add_edid_modes(connector, edid);

/* sorting the probed modes before calling function
 * amdgpu_dm_get_native_mode() since EDID can have
 * more than one preferred mode. The modes that are
 * later in the probed mode list could be of higher
 * and preferred resolution. For example, 3840x2160
 * resolution in base EDID preferred timing and 4096x2160
 * preferred resolution in DID extension block later.
 */
drm_mode_sort(&connector->probed_modes);
amdgpu_dm_get_native_mode(connector);

/* Freesync capabilities are reset by calling
 * drm_add_edid_modes() and need to be
 * restored here.
 */
amdgpu_dm_update_freesync_caps(connector, edid);
} else {
amdgpu_dm_connector->num_modes = 0;
}
6999}

7001static bool_Bool is_duplicate_mode(struct amdgpu_dm_connector *aconnector,
	      struct drm_display_mode *mode)
7003{
struct drm_display_mode *m;

list_for_each_entry(m, &aconnector->base.probed_modes, head)for (m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr
 = ((&aconnector->base.probed_modes)->next); (__typeof
(*m) *)( (char *)__mptr - __builtin_offsetof(__typeof(*m), head
) );}); &m->head != (&aconnector->base.probed_modes
); m = ({ const __typeof( ((__typeof(*m) *)0)->head ) *__mptr
 = (m->head.next); (__typeof(*m) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*m), head) );})) {
if (drm_mode_equal(m, mode))
	return true1;
}

return false0;
7012}

7014static uint add_fs_modes(struct amdgpu_dm_connector *aconnector)
7015{
const struct drm_display_mode *m;
struct drm_display_mode *new_mode;
uint i;
u32 new_modes_count = 0;

/* Standard FPS values
*
* 23.976       - TV/NTSC
* 24 	        - Cinema
* 25 	        - TV/PAL
* 29.97        - TV/NTSC
* 30 	        - TV/NTSC
* 48 	        - Cinema HFR
* 50 	        - TV/PAL
* 60 	        - Commonly used
* 48,72,96,120 - Multiples of 24
*/
static const u32 common_rates[] = {
23976, 24000, 25000, 29970, 30000,
48000, 50000, 60000, 72000, 96000, 120000
};

/*
* Find mode with highest refresh rate with the same resolution
* as the preferred mode. Some monitors report a preferred mode
* with lower resolution than the highest refresh rate supported.
*/

m = get_highest_refresh_rate_mode(aconnector, true1);
if (!m)
return 0;

for (i = 0; i < ARRAY_SIZE(common_rates)(sizeof((common_rates)) / sizeof((common_rates)[0])); i++) {
u64 target_vtotal, target_vtotal_diff;
u64 num, den;

if (drm_mode_vrefresh(m) * 1000 < common_rates[i])
	continue;

if (common_rates[i] < aconnector->min_vfreq * 1000 ||
    common_rates[i] > aconnector->max_vfreq * 1000)
	continue;

num = (unsigned long long)m->clock * 1000 * 1000;
den = common_rates[i] * (unsigned long long)m->htotal;
target_vtotal = div_u64(num, den);
target_vtotal_diff = target_vtotal - m->vtotal;

/* Check for illegal modes */
if (m->vsync_start + target_vtotal_diff < m->vdisplay ||
    m->vsync_end + target_vtotal_diff < m->vsync_start ||
    m->vtotal + target_vtotal_diff < m->vsync_end)
	continue;

new_mode = drm_mode_duplicate(aconnector->base.dev, m);
if (!new_mode)
	goto out;

new_mode->vtotal += (u16)target_vtotal_diff;
new_mode->vsync_start += (u16)target_vtotal_diff;
new_mode->vsync_end += (u16)target_vtotal_diff;
new_mode->type &= ~DRM_MODE_TYPE_PREFERRED(1<<3);
new_mode->type |= DRM_MODE_TYPE_DRIVER(1<<6);

if (!is_duplicate_mode(aconnector, new_mode)) {
	drm_mode_probed_add(&aconnector->base, new_mode);
	new_modes_count += 1;
} else
	drm_mode_destroy(aconnector->base.dev, new_mode);
}
out:
return new_modes_count;
7088}

7090static void amdgpu_dm_connector_add_freesync_modes(struct drm_connector *connector,
				   struct edid *edid)
7092{
struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (!edid)
return;

if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
amdgpu_dm_connector->num_modes +=
	add_fs_modes(amdgpu_dm_connector);
7102}

7104static int amdgpu_dm_connector_get_modes(struct drm_connector *connector)
7105{
struct amdgpu_dm_connector *amdgpu_dm_connector =
	to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct drm_encoder *encoder;
struct edid *edid = amdgpu_dm_connector->edid;

encoder = amdgpu_dm_connector_to_encoder(connector);

if (!drm_edid_is_valid(edid)) {
amdgpu_dm_connector->num_modes =
		drm_add_modes_noedid(connector, 640, 480);
} else {
amdgpu_dm_connector_ddc_get_modes(connector, edid);
amdgpu_dm_connector_add_common_modes(encoder, connector);
amdgpu_dm_connector_add_freesync_modes(connector, edid);
}
amdgpu_dm_fbc_init(connector);

return amdgpu_dm_connector->num_modes;
7124}

7126void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm,
		     struct amdgpu_dm_connector *aconnector,
		     int connector_type,
		     struct dc_link *link,
		     int link_index)
7131{
struct amdgpu_device *adev = drm_to_adev(dm->ddev);

/*
* Some of the properties below require access to state, like bpc.
* Allocate some default initial connector state with our reset helper.
*/
if (aconnector->base.funcs->reset)
aconnector->base.funcs->reset(&aconnector->base);

aconnector->connector_id = link_index;
aconnector->dc_link = link;
aconnector->base.interlace_allowed = false0;
aconnector->base.doublescan_allowed = false0;
aconnector->base.stereo_allowed = false0;
aconnector->base.dpms = DRM_MODE_DPMS_OFF3;
aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */
aconnector->audio_inst = -1;
rw_init(&aconnector->hpd_lock, "dmhpd")_rw_init_flags(&aconnector->hpd_lock, "dmhpd", 0, ((void
 *)0));
rw_init(&aconnector->handle_mst_msg_ready, "dmmr")_rw_init_flags(&aconnector->handle_mst_msg_ready, "dmmr"
, 0, ((void *)0));

/*
* configure support HPD hot plug connector_>polled default value is 0
* which means HPD hot plug not supported
*/
switch (connector_type) {
case DRM_MODE_CONNECTOR_HDMIA11:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD(1 << 0);
aconnector->base.ycbcr_420_allowed =
	link->link_enc->features.hdmi_ycbcr420_supported ? true1 : false0;
break;
case DRM_MODE_CONNECTOR_DisplayPort10:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD(1 << 0);
link->link_enc = link_enc_cfg_get_link_enc(link);
ASSERT(link->link_enc)do { if (({ static int __warned; int __ret = !!(!(link->link_enc
)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(link->link_enc)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7165); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
if (link->link_enc)
	aconnector->base.ycbcr_420_allowed =
	link->link_enc->features.dp_ycbcr420_supported ? true1 : false0;
break;
case DRM_MODE_CONNECTOR_DVID3:
aconnector->base.polled = DRM_CONNECTOR_POLL_HPD(1 << 0);
break;
default:
break;
}

drm_object_attach_property(&aconnector->base.base,
		dm->ddev->mode_config.scaling_mode_property,
		DRM_MODE_SCALE_NONE0);

drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.underscan_property,
		UNDERSCAN_OFF);
drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.underscan_hborder_property,
		0);
drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.underscan_vborder_property,
		0);

if (!aconnector->mst_port)
drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16);

/* This defaults to the max in the range, but we want 8bpc for non-edp. */
aconnector->base.state->max_bpc = (connector_type == DRM_MODE_CONNECTOR_eDP14) ? 16 : 8;
aconnector->base.state->max_requested_bpc = aconnector->base.state->max_bpc;

if (connector_type == DRM_MODE_CONNECTOR_eDP14 &&
   (dc_is_dmcu_initialized(adev->dm.dc) || adev->dm.dc->ctx->dmub_srv)) {
drm_object_attach_property(&aconnector->base.base,
		adev->mode_info.abm_level_property, 0);
}

if (connector_type == DRM_MODE_CONNECTOR_HDMIA11 ||
   connector_type == DRM_MODE_CONNECTOR_DisplayPort10 ||
   connector_type == DRM_MODE_CONNECTOR_eDP14) {
drm_connector_attach_hdr_output_metadata_property(&aconnector->base);

if (!aconnector->mst_port)
	drm_connector_attach_vrr_capable_property(&aconnector->base);

7212#ifdef CONFIG_DRM_AMD_DC_HDCP
if (adev->dm.hdcp_workqueue)
	drm_connector_attach_content_protection_property(&aconnector->base, true1);
7215#endif
}
7217}

7219static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap,
	      struct i2c_msg *msgs, int num)
7221{
struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap);
struct ddc_service *ddc_service = i2c->ddc_service;
struct i2c_command cmd;
int i;
int result = -EIO5;

if (!ddc_service->ddc_pin || !ddc_service->ddc_pin->hw_info.hw_supported)
return result;

cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL(0x0001 | 0x0004));

if (!cmd.payloads)
return result;

cmd.number_of_payloads = num;
cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
cmd.speed = 100;

for (i = 0; i < num; i++) {
cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD0x0001);
cmd.payloads[i].address = msgs[i].addr;
cmd.payloads[i].length = msgs[i].len;
cmd.payloads[i].data = msgs[i].buf;
}

if (dc_submit_i2c(
	ddc_service->ctx->dc,
	ddc_service->link->link_index,
	&cmd))
result = num;

kfree(cmd.payloads);
return result;
7255}

7257static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap)
7258{
return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0;
7260}

7262static const struct i2c_algorithm amdgpu_dm_i2c_algo = {
.master_xfer = amdgpu_dm_i2c_xfer,
.functionality = amdgpu_dm_i2c_func,
7265};

7267static struct amdgpu_i2c_adapter *
7268create_i2c(struct ddc_service *ddc_service,
  int link_index,
  int *res)
7271{
struct amdgpu_device *adev = ddc_service->ctx->driver_context;
struct amdgpu_i2c_adapter *i2c;

i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL(0x0001 | 0x0004));
if (!i2c)
return NULL((void *)0);
7278#ifdef notyet
i2c->base.owner = THIS_MODULE((void *)0);
i2c->base.class = I2C_CLASS_DDC;
i2c->base.dev.parent = &adev->pdev->dev;
7282#endif
i2c->base.algo = &amdgpu_dm_i2c_algo;
snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index);
i2c_set_adapdata(&i2c->base, i2c);
i2c->ddc_service = ddc_service;

return i2c;
7289}


7292/*
* Note: this function assumes that dc_link_detect() was called for the
* dc_link which will be represented by this aconnector.
*/
7296static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
		    struct amdgpu_dm_connector *aconnector,
		    u32 link_index,
		    struct amdgpu_encoder *aencoder)
7300{
int res = 0;
int connector_type;
struct dc *dc = dm->dc;
struct dc_link *link = dc_get_link_at_index(dc, link_index);
struct amdgpu_i2c_adapter *i2c;

link->priv = aconnector;


i2c = create_i2c(link->ddc, link->link_index, &res);
if (!i2c) {
DRM_ERROR("Failed to create i2c adapter data\n")__drm_err("Failed to create i2c adapter data\n");
return -ENOMEM12;
}

aconnector->i2c = i2c;
res = i2c_add_adapter(&i2c->base);

if (res) {
DRM_ERROR("Failed to register hw i2c %d\n", link->link_index)__drm_err("Failed to register hw i2c %d\n", link->link_index
);
goto out_free;
}

connector_type = to_drm_connector_type(link->connector_signal);

res = drm_connector_init_with_ddc(
	dm->ddev,
	&aconnector->base,
	&amdgpu_dm_connector_funcs,
	connector_type,
	&i2c->base);

if (res) {
DRM_ERROR("connector_init failed\n")__drm_err("connector_init failed\n");
aconnector->connector_id = -1;
goto out_free;
}

drm_connector_helper_add(
	&aconnector->base,
	&amdgpu_dm_connector_helper_funcs);

amdgpu_dm_connector_init_helper(
dm,
aconnector,
connector_type,
link,
link_index);

drm_connector_attach_encoder(
&aconnector->base, &aencoder->base);

if (connector_type == DRM_MODE_CONNECTOR_DisplayPort10
|| connector_type == DRM_MODE_CONNECTOR_eDP14)
amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);

7357out_free:
if (res) {
kfree(i2c);
aconnector->i2c = NULL((void *)0);
}
return res;
7363}

7365int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev)
7366{
switch (adev->mode_info.num_crtc) {
case 1:
return 0x1;
case 2:
return 0x3;
case 3:
return 0x7;
case 4:
return 0xf;
case 5:
return 0x1f;
case 6:
default:
return 0x3f;
}
7382}

7384static int amdgpu_dm_encoder_init(struct drm_device *dev,
		  struct amdgpu_encoder *aencoder,
		  uint32_t link_index)
7387{
struct amdgpu_device *adev = drm_to_adev(dev);

int res = drm_encoder_init(dev,
		   &aencoder->base,
		   &amdgpu_dm_encoder_funcs,
		   DRM_MODE_ENCODER_TMDS2,
		   NULL((void *)0));

aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev);

if (!res)
aencoder->encoder_id = link_index;
else
aencoder->encoder_id = -1;

drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs);

return res;
7406}

7408static void manage_dm_interrupts(struct amdgpu_device *adev,
		 struct amdgpu_crtc *acrtc,
		 bool_Bool enable)
7411{
/*
* We have no guarantee that the frontend index maps to the same
* backend index - some even map to more than one.
*
* TODO: Use a different interrupt or check DC itself for the mapping.
*/
int irq_type =
amdgpu_display_crtc_idx_to_irq_type(
	adev,
	acrtc->crtc_id);

if (enable) {
drm_crtc_vblank_on(&acrtc->base);
amdgpu_irq_get(
	adev,
	&adev->pageflip_irq,
	irq_type);
7429#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
amdgpu_irq_get(
	adev,
	&adev->vline0_irq,
	irq_type);
7434#endif
} else {
7436#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
amdgpu_irq_put(
	adev,
	&adev->vline0_irq,
	irq_type);
7441#endif
amdgpu_irq_put(
	adev,
	&adev->pageflip_irq,
	irq_type);
drm_crtc_vblank_off(&acrtc->base);
}
7448}

7450static void dm_update_pflip_irq_state(struct amdgpu_device *adev,
		      struct amdgpu_crtc *acrtc)
7452{
int irq_type =
amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);

/**
* This reads the current state for the IRQ and force reapplies
* the setting to hardware.
*/
amdgpu_irq_update(adev, &adev->pageflip_irq, irq_type);
7461}

7463static bool_Bool
7464is_scaling_state_different(const struct dm_connector_state *dm_state,
	   const struct dm_connector_state *old_dm_state)
7466{
if (dm_state->scaling != old_dm_state->scaling)
return true1;
if (!dm_state->underscan_enable && old_dm_state->underscan_enable) {
if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0)
	return true1;
} else  if (dm_state->underscan_enable && !old_dm_state->underscan_enable) {
if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0)
	return true1;
} else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder ||
   dm_state->underscan_vborder != old_dm_state->underscan_vborder)
return true1;
return false0;
7479}

7481#ifdef CONFIG_DRM_AMD_DC_HDCP
7482static bool_Bool is_content_protection_different(struct drm_crtc_state *new_crtc_state,
			    struct drm_crtc_state *old_crtc_state,
			    struct drm_connector_state *new_conn_state,
			    struct drm_connector_state *old_conn_state,
			    const struct drm_connector *connector,
			    struct hdcp_workqueue *hdcp_w)
7488{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct dm_connector_state *dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",do { } while(0)
connector->index, connector->status, connector->dpms)do { } while(0);
pr_debug("[HDCP_DM] state protection old: %x new: %x\n",do { } while(0)
old_conn_state->content_protection, new_conn_state->content_protection)do { } while(0);

if (old_crtc_state)
pr_debug("[HDCP_DM] old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",do { } while(0)
old_crtc_state->enable,do { } while(0)
old_crtc_state->active,do { } while(0)
old_crtc_state->mode_changed,do { } while(0)
old_crtc_state->active_changed,do { } while(0)
old_crtc_state->connectors_changed)do { } while(0);

if (new_crtc_state)
pr_debug("[HDCP_DM] NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",do { } while(0)
new_crtc_state->enable,do { } while(0)
new_crtc_state->active,do { } while(0)
new_crtc_state->mode_changed,do { } while(0)
new_crtc_state->active_changed,do { } while(0)
new_crtc_state->connectors_changed)do { } while(0);

/* hdcp content type change */
if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type &&
   new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED0) {
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__)do { } while(0);
return true1;
}

/* CP is being re enabled, ignore this */
if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2 &&
   new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1) {
if (new_crtc_state && new_crtc_state->mode_changed) {
	new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
	pr_debug("[HDCP_DM] ENABLED->DESIRED & mode_changed %s :true\n", __func__)do { } while(0);
	return true1;
};
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_ENABLED2;
pr_debug("[HDCP_DM] ENABLED -> DESIRED %s :false\n", __func__)do { } while(0);
return false0;
}

/* S3 resume case, since old state will always be 0 (UNDESIRED) and the restored state will be ENABLED
*
* Handles:	UNDESIRED -> ENABLED
*/
if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_UNDESIRED0 &&
   new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2)
new_conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;

/* Stream removed and re-enabled
*
* Can sometimes overlap with the HPD case,
* thus set update_hdcp to false to avoid
* setting HDCP multiple times.
*
* Handles:	DESIRED -> DESIRED (Special case)
*/
if (!(old_conn_state->crtc && old_conn_state->crtc->enabled) &&
new_conn_state->crtc && new_conn_state->crtc->enabled &&
connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1) {
dm_con_state->update_hdcp = false0;
pr_debug("[HDCP_DM] DESIRED->DESIRED (Stream removed and re-enabled) %s :true\n",do { } while(0)
	__func__)do { } while(0);
return true1;
}

/* Hot-plug, headless s3, dpms
*
* Only start HDCP if the display is connected/enabled.
* update_hdcp flag will be set to false until the next
* HPD comes in.
*
* Handles:	DESIRED -> DESIRED (Special case)
*/
if (dm_con_state->update_hdcp &&
new_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1 &&
connector->dpms == DRM_MODE_DPMS_ON0 && aconnector->dc_sink != NULL((void *)0)) {
dm_con_state->update_hdcp = false0;
pr_debug("[HDCP_DM] DESIRED->DESIRED (Hot-plug, headless s3, dpms) %s :true\n",do { } while(0)
	__func__)do { } while(0);
return true1;
}

if (old_conn_state->content_protection == new_conn_state->content_protection) {
if (new_conn_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED1) {
	if (new_crtc_state && new_crtc_state->mode_changed) {
		pr_debug("[HDCP_DM] DESIRED->DESIRED or ENABLE->ENABLE mode_change %s :true\n",do { } while(0)
			__func__)do { } while(0);
		return true1;
	};
	pr_debug("[HDCP_DM] DESIRED->DESIRED & ENABLE->ENABLE %s :false\n",do { } while(0)
		__func__)do { } while(0);
	return false0;
};

pr_debug("[HDCP_DM] UNDESIRED->UNDESIRED %s :false\n", __func__)do { } while(0);
return false0;
}

if (new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_ENABLED2) {
pr_debug("[HDCP_DM] UNDESIRED->DESIRED or DESIRED->UNDESIRED or ENABLED->UNDESIRED %s :true\n",do { } while(0)
	__func__)do { } while(0);
return true1;
}

pr_debug("[HDCP_DM] DESIRED->ENABLED %s :false\n", __func__)do { } while(0);
return false0;
7600}
7601#endif

7603static void remove_stream(struct amdgpu_device *adev,
	  struct amdgpu_crtc *acrtc,
	  struct dc_stream_state *stream)
7606{
/* this is the update mode case */

acrtc->otg_inst = -1;
acrtc->enabled = false0;
7611}

7613static void prepare_flip_isr(struct amdgpu_crtc *acrtc)
7614{

assert_spin_locked(&acrtc->base.dev->event_lock)do { if (((&acrtc->base.dev->event_lock)->mtx_owner
 != ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" :
 "=r" (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self
))); __ci;})) && !(panicstr || db_active)) panic("mutex %p not held in %s"
, (&acrtc->base.dev->event_lock), __func__); } while
 (0);
WARN_ON(acrtc->event)({ int __ret = !!(acrtc->event); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "acrtc->event", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7617); __builtin_expect(!!(__ret), 0); });

acrtc->event = acrtc->base.state->event;

/* Set the flip status */
acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;

/* Mark this event as consumed */
acrtc->base.state->event = NULL((void *)0);

DC_LOG_PFLIP("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n",do { } while(0)
     acrtc->crtc_id)do { } while(0);
7629}

7631static void update_freesync_state_on_stream(
struct amdgpu_display_manager *dm,
struct dm_crtc_state *new_crtc_state,
struct dc_stream_state *new_stream,
struct dc_plane_state *surface,
u32 flip_timestamp_in_us)
7637{
struct mod_vrr_params vrr_params;
struct dc_info_packet vrr_infopacket = {0};
struct amdgpu_device *adev = dm->adev;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (new_crtc_state->base.crtc); (struct amdgpu_crtc *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );});
unsigned long flags;
bool_Bool pack_sdp_v1_3 = false0;

if (!new_stream)
return;

/*
* TODO: Determine why min/max totals and vrefresh can be 0 here.
* For now it's sufficient to just guard against these conditions.
*/

if (!new_stream->timing.h_total || !new_stream->timing.v_total)
return;

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
      vrr_params = acrtc->dm_irq_params.vrr_params;

if (surface) {
mod_freesync_handle_preflip(
	dm->freesync_module,
	surface,
	new_stream,
	flip_timestamp_in_us,
	&vrr_params);

if (adev->family < AMDGPU_FAMILY_AI141 &&
    amdgpu_dm_vrr_active(new_crtc_state)) {
	mod_freesync_handle_v_update(dm->freesync_module,
				     new_stream, &vrr_params);

	/* Need to call this before the frame ends. */
	dc_stream_adjust_vmin_vmax(dm->dc,
				   new_crtc_state->stream,
				   &vrr_params.adjust);
}
}

mod_freesync_build_vrr_infopacket(
dm->freesync_module,
new_stream,
&vrr_params,
PACKET_TYPE_VRR,
TRANSFER_FUNC_UNKNOWN,
&vrr_infopacket,
pack_sdp_v1_3);

new_crtc_state->freesync_vrr_info_changed |=
(memcmp(&new_crtc_state->vrr_infopacket,__builtin_memcmp((&new_crtc_state->vrr_infopacket), (&
vrr_infopacket), (sizeof(vrr_infopacket)))
	&vrr_infopacket,__builtin_memcmp((&new_crtc_state->vrr_infopacket), (&
vrr_infopacket), (sizeof(vrr_infopacket)))
	sizeof(vrr_infopacket))__builtin_memcmp((&new_crtc_state->vrr_infopacket), (&
vrr_infopacket), (sizeof(vrr_infopacket))) != 0);

acrtc->dm_irq_params.vrr_params = vrr_params;
new_crtc_state->vrr_infopacket = vrr_infopacket;

new_stream->vrr_infopacket = vrr_infopacket;

if (new_crtc_state->freesync_vrr_info_changed)
DRM_DEBUG_KMS("VRR packet update: crtc=%u enabled=%d state=%d",___drm_dbg(((void *)0), DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state)
	      new_crtc_state->base.crtc->base.id,___drm_dbg(((void *)0), DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state)
	      (int)new_crtc_state->base.vrr_enabled,___drm_dbg(((void *)0), DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state)
	      (int)vrr_params.state)___drm_dbg(((void *)0), DRM_UT_KMS, "VRR packet update: crtc=%u enabled=%d state=%d"
, new_crtc_state->base.crtc->base.id, (int)new_crtc_state
->base.vrr_enabled, (int)vrr_params.state);

spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
7705}

7707static void update_stream_irq_parameters(
struct amdgpu_display_manager *dm,
struct dm_crtc_state *new_crtc_state)
7710{
struct dc_stream_state *new_stream = new_crtc_state->stream;
struct mod_vrr_params vrr_params;
struct mod_freesync_config config = new_crtc_state->freesync_config;
struct amdgpu_device *adev = dm->adev;
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_crtc_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (new_crtc_state->base.crtc); (struct amdgpu_crtc *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) );});
unsigned long flags;

if (!new_stream)
return;

/*
* TODO: Determine why min/max totals and vrefresh can be 0 here.
* For now it's sufficient to just guard against these conditions.
*/
if (!new_stream->timing.h_total || !new_stream->timing.v_total)
return;

spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
vrr_params = acrtc->dm_irq_params.vrr_params;

if (new_crtc_state->vrr_supported &&
   config.min_refresh_in_uhz &&
   config.max_refresh_in_uhz) {
/*
 * if freesync compatible mode was set, config.state will be set
 * in atomic check
 */
if (config.state == VRR_STATE_ACTIVE_FIXED && config.fixed_refresh_in_uhz &&
    (!drm_atomic_crtc_needs_modeset(&new_crtc_state->base) ||
     new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED)) {
	vrr_params.max_refresh_in_uhz = config.max_refresh_in_uhz;
	vrr_params.min_refresh_in_uhz = config.min_refresh_in_uhz;
	vrr_params.fixed_refresh_in_uhz = config.fixed_refresh_in_uhz;
	vrr_params.state = VRR_STATE_ACTIVE_FIXED;
} else {
	config.state = new_crtc_state->base.vrr_enabled ?
				     VRR_STATE_ACTIVE_VARIABLE :
				     VRR_STATE_INACTIVE;
}
} else {
config.state = VRR_STATE_UNSUPPORTED;
}

mod_freesync_build_vrr_params(dm->freesync_module,
		      new_stream,
		      &config, &vrr_params);

new_crtc_state->freesync_config = config;
/* Copy state for access from DM IRQ handler */
acrtc->dm_irq_params.freesync_config = config;
acrtc->dm_irq_params.active_planes = new_crtc_state->active_planes;
acrtc->dm_irq_params.vrr_params = vrr_params;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
7764}

7766static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
			    struct dm_crtc_state *new_state)
7768{
bool_Bool old_vrr_active = amdgpu_dm_vrr_active(old_state);
bool_Bool new_vrr_active = amdgpu_dm_vrr_active(new_state);

if (!old_vrr_active && new_vrr_active) {
/* Transition VRR inactive -> active:
 * While VRR is active, we must not disable vblank irq, as a
 * reenable after disable would compute bogus vblank/pflip
 * timestamps if it likely happened inside display front-porch.
 *
 * We also need vupdate irq for the actual core vblank handling
 * at end of vblank.
 */
WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, true) != 0)({ int __ret = !!(dm_set_vupdate_irq(new_state->base.crtc,
 1) != 0); if (__ret) printf("WARNING %s failed at %s:%d\n", "dm_set_vupdate_irq(new_state->base.crtc, 1) != 0"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7781); __builtin_expect(!!(__ret), 0); });
WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0)({ int __ret = !!(drm_crtc_vblank_get(new_state->base.crtc
) != 0); if (__ret) printf("WARNING %s failed at %s:%d\n", "drm_crtc_vblank_get(new_state->base.crtc) != 0"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7782); __builtin_expect(!!(__ret), 0); });
DRM_DEBUG_DRIVER("%s: crtc=%u VRR off->on: Get vblank ref\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: crtc=%u VRR off->on: Get vblank ref\n"
, __func__, new_state->base.crtc->base.id)
		 __func__, new_state->base.crtc->base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: crtc=%u VRR off->on: Get vblank ref\n"
, __func__, new_state->base.crtc->base.id);
} else if (old_vrr_active && !new_vrr_active) {
/* Transition VRR active -> inactive:
 * Allow vblank irq disable again for fixed refresh rate.
 */
WARN_ON(dm_set_vupdate_irq(new_state->base.crtc, false) != 0)({ int __ret = !!(dm_set_vupdate_irq(new_state->base.crtc,
 0) != 0); if (__ret) printf("WARNING %s failed at %s:%d\n", "dm_set_vupdate_irq(new_state->base.crtc, 0) != 0"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 7789); __builtin_expect(!!(__ret), 0); });
drm_crtc_vblank_put(new_state->base.crtc);
DRM_DEBUG_DRIVER("%s: crtc=%u VRR on->off: Drop vblank ref\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: crtc=%u VRR on->off: Drop vblank ref\n"
, __func__, new_state->base.crtc->base.id)
		 __func__, new_state->base.crtc->base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: crtc=%u VRR on->off: Drop vblank ref\n"
, __func__, new_state->base.crtc->base.id);
}
7794}

7796static void amdgpu_dm_commit_cursors(struct drm_atomic_state *state)
7797{
struct drm_plane *plane;
struct drm_plane_state *old_plane_state;
int i;

/*
* TODO: Make this per-stream so we don't issue redundant updates for
* commits with multiple streams.
*/
for_each_old_plane_in_state(state, plane, old_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (old_plane_state) = (state)->planes
[i].old_state, 1))) {} else
if (plane->type == DRM_PLANE_TYPE_CURSOR)
	handle_cursor_update(plane, old_plane_state);
7809}

7811static inline uint32_t get_mem_type(struct drm_framebuffer *fb)
7812{
struct amdgpu_bo *abo = gem_to_amdgpu_bo(fb->obj[0])({ const __typeof( ((struct amdgpu_bo *)0)->tbo.base ) *__mptr
 = ((fb->obj[0])); (struct amdgpu_bo *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_bo, tbo.base) );});

return abo->tbo.resource ? abo->tbo.resource->mem_type : 0;
7816}

7818static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
		    struct dc_state *dc_state,
		    struct drm_device *dev,
		    struct amdgpu_display_manager *dm,
		    struct drm_crtc *pcrtc,
		    bool_Bool wait_for_vblank)
7824{
u32 i;
u64 timestamp_ns;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (pcrtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
struct drm_crtc_state *new_pcrtc_state =
	drm_atomic_get_new_crtc_state(state, pcrtc);
struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_pcrtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
struct dm_crtc_state *dm_old_crtc_state =
	to_dm_crtc_state(drm_atomic_get_old_crtc_state(state, pcrtc))({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (drm_atomic_get_old_crtc_state(state, pcrtc)); (struct dm_crtc_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_crtc_state
, base) );});
int planes_count = 0, vpos, hpos;
unsigned long flags;
u32 target_vblank, last_flip_vblank;
bool_Bool vrr_active = amdgpu_dm_vrr_active(acrtc_state);
bool_Bool cursor_update = false0;
bool_Bool pflip_present = false0;
struct {
struct dc_surface_update surface_updates[MAX_SURFACES3];
struct dc_plane_info plane_infos[MAX_SURFACES3];
struct dc_scaling_info scaling_infos[MAX_SURFACES3];
struct dc_flip_addrs flip_addrs[MAX_SURFACES3];
struct dc_stream_update stream_update;
} *bundle;

bundle = kzalloc(sizeof(*bundle), GFP_KERNEL(0x0001 | 0x0004));

if (!bundle) {
dm_error("Failed to allocate update bundle\n")__drm_err("Failed to allocate update bundle\n");
goto cleanup;
}

/*
* Disable the cursor first if we're disabling all the planes.
* It'll remain on the screen after the planes are re-enabled
* if we don't.
*/
if (acrtc_state->active_planes == 0)
amdgpu_dm_commit_cursors(state);

/* update planes when needed */
for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else {
struct drm_crtc *crtc = new_plane_state->crtc;
struct drm_crtc_state *new_crtc_state;
struct drm_framebuffer *fb = new_plane_state->fb;
struct amdgpu_framebuffer *afb = (struct amdgpu_framebuffer *)fb;
bool_Bool plane_needs_flip;
struct dc_plane_state *dc_plane;
struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});

/* Cursor plane is handled after stream updates */
if (plane->type == DRM_PLANE_TYPE_CURSOR) {
	if ((fb && crtc == pcrtc) ||
	    (old_plane_state->fb && old_plane_state->crtc == pcrtc))
		cursor_update = true1;

	continue;
}

if (!fb || !crtc || pcrtc != crtc)
	continue;

new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
if (!new_crtc_state->active)
	continue;

dc_plane = dm_new_plane_state->dc_state;
if (!dc_plane)
	continue;

bundle->surface_updates[planes_count].surface = dc_plane;
if (new_pcrtc_state->color_mgmt_changed) {
	bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
	bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
	bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
}

fill_dc_scaling_info(dm->adev, new_plane_state,
		     &bundle->scaling_infos[planes_count]);

bundle->surface_updates[planes_count].scaling_info =
	&bundle->scaling_infos[planes_count];

plane_needs_flip = old_plane_state->fb && new_plane_state->fb;

pflip_present = pflip_present || plane_needs_flip;

if (!plane_needs_flip) {
	planes_count += 1;
	continue;
}

fill_dc_plane_info_and_addr(
	dm->adev, new_plane_state,
	afb->tiling_flags,
	&bundle->plane_infos[planes_count],
	&bundle->flip_addrs[planes_count].address,
	afb->tmz_surface, false0);

drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n",__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "plane: id=%d dcc_en=%d\n", new_plane_state
->plane->index, bundle->plane_infos[planes_count].dcc
.enable)
		 new_plane_state->plane->index,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "plane: id=%d dcc_en=%d\n", new_plane_state
->plane->index, bundle->plane_infos[planes_count].dcc
.enable)
		 bundle->plane_infos[planes_count].dcc.enable)__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "plane: id=%d dcc_en=%d\n", new_plane_state
->plane->index, bundle->plane_infos[planes_count].dcc
.enable);

bundle->surface_updates[planes_count].plane_info =
	&bundle->plane_infos[planes_count];

if (acrtc_state->stream->link->psr_settings.psr_feature_enabled)
	fill_dc_dirty_rects(plane, old_plane_state,
			    new_plane_state, new_crtc_state,
			    &bundle->flip_addrs[planes_count]);

/*
 * Only allow immediate flips for fast updates that don't
 * change memory domain, FB pitch, DCC state, rotation or
 * mirroring.
 *
 * dm_crtc_helper_atomic_check() only accepts async flips with
 * fast updates.
 */
if (crtc->state->async_flip &&
    (acrtc_state->update_type != UPDATE_TYPE_FAST ||
     get_mem_type(old_plane_state->fb) != get_mem_type(fb)))
	drm_warn_once(state->dev,printf("drm:pid%d:%s *WARNING* " "[drm] " "[PLANE:%d:%s] async flip with non-fast update\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , plane->
base.id, plane->name)
		      "[PLANE:%d:%s] async flip with non-fast update\n",printf("drm:pid%d:%s *WARNING* " "[drm] " "[PLANE:%d:%s] async flip with non-fast update\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , plane->
base.id, plane->name)
		      plane->base.id, plane->name)printf("drm:pid%d:%s *WARNING* " "[drm] " "[PLANE:%d:%s] async flip with non-fast update\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , plane->
base.id, plane->name);

bundle->flip_addrs[planes_count].flip_immediate =
	crtc->state->async_flip &&
	acrtc_state->update_type == UPDATE_TYPE_FAST &&
	get_mem_type(old_plane_state->fb) == get_mem_type(fb);

timestamp_ns = ktime_get_ns();
bundle->flip_addrs[planes_count].flip_timestamp_in_us = div_u64(timestamp_ns, 1000);
bundle->surface_updates[planes_count].flip_addr = &bundle->flip_addrs[planes_count];
bundle->surface_updates[planes_count].surface = dc_plane;

if (!bundle->surface_updates[planes_count].surface) {
	DRM_ERROR("No surface for CRTC: id=%d\n",__drm_err("No surface for CRTC: id=%d\n", acrtc_attach->crtc_id
)
			acrtc_attach->crtc_id)__drm_err("No surface for CRTC: id=%d\n", acrtc_attach->crtc_id
);
	continue;
}

if (plane == pcrtc->primary)
	update_freesync_state_on_stream(
		dm,
		acrtc_state,
		acrtc_state->stream,
		dc_plane,
		bundle->flip_addrs[planes_count].flip_timestamp_in_us);

drm_dbg_state(state->dev, "%s Flipping to hi: 0x%x, low: 0x%x\n",__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part)
		 __func__,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part)
		 bundle->flip_addrs[planes_count].address.grph.addr.high_part,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part)
		 bundle->flip_addrs[planes_count].address.grph.addr.low_part)__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "%s Flipping to hi: 0x%x, low: 0x%x\n"
, __func__, bundle->flip_addrs[planes_count].address.grph.
addr.high_part, bundle->flip_addrs[planes_count].address.grph
.addr.low_part);

planes_count += 1;

}

if (pflip_present) {
if (!vrr_active) {
	/* Use old throttling in non-vrr fixed refresh rate mode
	 * to keep flip scheduling based on target vblank counts
	 * working in a backwards compatible way, e.g., for
	 * clients using the GLX_OML_sync_control extension or
	 * DRI3/Present extension with defined target_msc.
	 */
	last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);
} else {
	/* For variable refresh rate mode only:
	 * Get vblank of last completed flip to avoid > 1 vrr
	 * flips per video frame by use of throttling, but allow
	 * flip programming anywhere in the possibly large
	 * variable vrr vblank interval for fine-grained flip
	 * timing control and more opportunity to avoid stutter
	 * on late submission of flips.
	 */
	spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);
	last_flip_vblank = acrtc_attach->dm_irq_params.last_flip_vblank;
	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}

target_vblank = last_flip_vblank + wait_for_vblank;

/*
 * Wait until we're out of the vertical blank period before the one
 * targeted by the flip
 */
while ((acrtc_attach->enabled &&
	(amdgpu_display_get_crtc_scanoutpos(dm->ddev, acrtc_attach->crtc_id,
					    0, &vpos, &hpos, NULL((void *)0),
					    NULL((void *)0), &pcrtc->hwmode)
	 & (DRM_SCANOUTPOS_VALID(1 << 0) | DRM_SCANOUTPOS_IN_VBLANK(1 << 1))) ==
	(DRM_SCANOUTPOS_VALID(1 << 0) | DRM_SCANOUTPOS_IN_VBLANK(1 << 1)) &&
	(int)(target_vblank -
	  amdgpu_get_vblank_counter_kms(pcrtc)) > 0)) {
	usleep_range(1000, 1100);
}

/**
 * Prepare the flip event for the pageflip interrupt to handle.
 *
 * This only works in the case where we've already turned on the
 * appropriate hardware blocks (eg. HUBP) so in the transition case
 * from 0 -> n planes we have to skip a hardware generated event
 * and rely on sending it from software.
 */
if (acrtc_attach->base.state->event &&
    acrtc_state->active_planes > 0) {
	drm_crtc_vblank_get(pcrtc);

	spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);

	WARN_ON(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE)({ int __ret = !!(acrtc_attach->pflip_status != AMDGPU_FLIP_NONE
); if (__ret) printf("WARNING %s failed at %s:%d\n", "acrtc_attach->pflip_status != AMDGPU_FLIP_NONE"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8037); __builtin_expect(!!(__ret), 0); });
	prepare_flip_isr(acrtc_attach);

	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}

if (acrtc_state->stream) {
	if (acrtc_state->freesync_vrr_info_changed)
		bundle->stream_update.vrr_infopacket =
			&acrtc_state->stream->vrr_infopacket;
}
} else if (cursor_update && acrtc_state->active_planes > 0 &&
   acrtc_attach->base.state->event) {
drm_crtc_vblank_get(pcrtc);

spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);

acrtc_attach->event = acrtc_attach->base.state->event;
acrtc_attach->base.state->event = NULL((void *)0);

spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}

/* Update the planes if changed or disable if we don't have any. */
if ((planes_count || acrtc_state->active_planes == 0) &&
acrtc_state->stream) {
/*
 * If PSR or idle optimizations are enabled then flush out
 * any pending work before hardware programming.
 */
if (dm->vblank_control_workqueue)
	flush_workqueue(dm->vblank_control_workqueue);

bundle->stream_update.stream = acrtc_state->stream;
if (new_pcrtc_state->mode_changed) {
	bundle->stream_update.src = acrtc_state->stream->src;
	bundle->stream_update.dst = acrtc_state->stream->dst;
}

if (new_pcrtc_state->color_mgmt_changed) {
	/*
	 * TODO: This isn't fully correct since we've actually
	 * already modified the stream in place.
	 */
	bundle->stream_update.gamut_remap =
		&acrtc_state->stream->gamut_remap_matrix;
	bundle->stream_update.output_csc_transform =
		&acrtc_state->stream->csc_color_matrix;
	bundle->stream_update.out_transfer_func =
		acrtc_state->stream->out_transfer_func;
}

acrtc_state->stream->abm_level = acrtc_state->abm_level;
if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
	bundle->stream_update.abm_level = &acrtc_state->abm_level;

mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
		acrtc_state->stream->link->psr_settings.psr_allow_active)
	amdgpu_dm_psr_disable(acrtc_state->stream);
mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);

/*
 * If FreeSync state on the stream has changed then we need to
 * re-adjust the min/max bounds now that DC doesn't handle this
 * as part of commit.
 */
if (is_dc_timing_adjust_needed(dm_old_crtc_state, acrtc_state)) {
	spin_lock_irqsave(&pcrtc->dev->event_lock, flags)do { flags = 0; mtx_enter(&pcrtc->dev->event_lock);
 } while (0);
	dc_stream_adjust_vmin_vmax(
		dm->dc, acrtc_state->stream,
		&acrtc_attach->dm_irq_params.vrr_params.adjust);
	spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags)do { (void)(flags); mtx_leave(&pcrtc->dev->event_lock
); } while (0);
}
mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
update_planes_and_stream_adapter(dm->dc,
			 acrtc_state->update_type,
			 planes_count,
			 acrtc_state->stream,
			 &bundle->stream_update,
			 bundle->surface_updates);

/**
 * Enable or disable the interrupts on the backend.
 *
 * Most pipes are put into power gating when unused.
 *
 * When power gating is enabled on a pipe we lose the
 * interrupt enablement state when power gating is disabled.
 *
 * So we need to update the IRQ control state in hardware
 * whenever the pipe turns on (since it could be previously
 * power gated) or off (since some pipes can't be power gated
 * on some ASICs).
 */
if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
	dm_update_pflip_irq_state(drm_to_adev(dev),
				  acrtc_attach);

if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
		acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
		!acrtc_state->stream->link->psr_settings.psr_feature_enabled)
	amdgpu_dm_link_setup_psr(acrtc_state->stream);

/* Decrement skip count when PSR is enabled and we're doing fast updates. */
if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
    acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
	struct amdgpu_dm_connector *aconn =
		(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;

	if (aconn->psr_skip_count > 0)
		aconn->psr_skip_count--;

	/* Allow PSR when skip count is 0. */
	acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;

	/*
	 * If sink supports PSR SU, there is no need to rely on
	 * a vblank event disable request to enable PSR. PSR SU
	 * can be enabled immediately once OS demonstrates an
	 * adequate number of fast atomic commits to notify KMD
	 * of update events. See `vblank_control_worker()`.
	 */
	if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
	    acrtc_attach->dm_irq_params.allow_psr_entry &&
	    !acrtc_state->stream->link->psr_settings.psr_allow_active)
		amdgpu_dm_psr_enable(acrtc_state->stream);
} else {
	acrtc_attach->dm_irq_params.allow_psr_entry = false0;
}

mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

/*
* Update cursor state *after* programming all the planes.
* This avoids redundant programming in the case where we're going
* to be disabling a single plane - those pipes are being disabled.
*/
if (acrtc_state->active_planes)
amdgpu_dm_commit_cursors(state);

8179cleanup:
kfree(bundle);
8181}

8183static void amdgpu_dm_commit_audio(struct drm_device *dev,
		   struct drm_atomic_state *state)
8185{
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct drm_crtc_state *new_crtc_state;
struct dm_crtc_state *new_dm_crtc_state;
const struct dc_stream_status *status;
int i, inst;

/* Notify device removals. */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
if (old_con_state->crtc != new_con_state->crtc) {
	/* CRTC changes require notification. */
	goto notify;
}

if (!new_con_state->crtc)
	continue;

new_crtc_state = drm_atomic_get_new_crtc_state(
	state, new_con_state->crtc);

if (!new_crtc_state)
	continue;

if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
	continue;

notify:
aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock);
inst = aconnector->audio_inst;
aconnector->audio_inst = -1;
mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock);

amdgpu_dm_audio_eld_notify(adev, inst);
}

/* Notify audio device additions. */
for_each_new_connector_in_state(state, connector, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (new_con_state) =
 (state)->connectors[i].new_state, (void)(new_con_state) ,
 1))) {} else {
if (!new_con_state->crtc)
	continue;

new_crtc_state = drm_atomic_get_new_crtc_state(
	state, new_con_state->crtc);

if (!new_crtc_state)
	continue;

if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
	continue;

new_dm_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
if (!new_dm_crtc_state->stream)
	continue;

status = dc_stream_get_status(new_dm_crtc_state->stream);
if (!status)
	continue;

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

mutex_lock(&adev->dm.audio_lock)rw_enter_write(&adev->dm.audio_lock);
inst = status->audio_inst;
aconnector->audio_inst = inst;
mutex_unlock(&adev->dm.audio_lock)rw_exit_write(&adev->dm.audio_lock);

amdgpu_dm_audio_eld_notify(adev, inst);
}
8256}

8258/*
* amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
* @crtc_state: the DRM CRTC state
* @stream_state: the DC stream state.
*
* Copy the mirrored transient state flags from DRM, to DC. It is used to bring
* a dc_stream_state's flags in sync with a drm_crtc_state's flags.
*/
8266static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state *crtc_state,
				struct dc_stream_state *stream_state)
8268{
stream_state->mode_changed = drm_atomic_crtc_needs_modeset(crtc_state);
8270}

8272/**
* amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
* @state: The atomic state to commit
*
* This will tell DC to commit the constructed DC state from atomic_check,
* programming the hardware. Any failures here implies a hardware failure, since
* atomic check should have filtered anything non-kosher.
*/
8280static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
8281{
struct drm_device *dev = state->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_display_manager *dm = &adev->dm;
struct dm_atomic_state *dm_state;
struct dc_state *dc_state = NULL((void *)0), *dc_state_temp = NULL((void *)0);
u32 i, j;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
unsigned long flags;
bool_Bool wait_for_vblank = true1;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
int crtc_disable_count = 0;
bool_Bool mode_set_reset_required = false0;
int r;

trace_amdgpu_dm_atomic_commit_tail_begin(state);

r = drm_atomic_helper_wait_for_fences(dev, state, false0);
if (unlikely(r)__builtin_expect(!!(r), 0))
DRM_ERROR("Waiting for fences timed out!")__drm_err("Waiting for fences timed out!");

drm_atomic_helper_update_legacy_modeset_state(dev, state);
drm_dp_mst_atomic_wait_for_dependencies(state);

dm_state = dm_atomic_get_new_state(state);
if (dm_state && dm_state->context) {
dc_state = dm_state->context;
} else {
/* No state changes, retain current state. */
dc_state_temp = dc_create_state(dm->dc);
ASSERT(dc_state_temp)do { if (({ static int __warned; int __ret = !!(!(dc_state_temp
)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(dc_state_temp)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8314); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
 {} while (0); } while (0);
dc_state = dc_state_temp;
dc_resource_state_copy_construct_current(dm->dc, dc_state);
}

for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else
		      new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (old_crtc_state->active &&
    (!new_crtc_state->active ||
     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
	manage_dm_interrupts(adev, acrtc, false0);
	dc_stream_release(dm_old_crtc_state->stream);
}
}

drm_atomic_helper_calc_timestamping_constants(state);

/* update changed items */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

drm_dbg_state(state->dev,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	acrtc->crtc_id,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->enable,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->active,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->planes_changed,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->mode_changed,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->active_changed,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
	new_crtc_state->connectors_changed)__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed);

/* Disable cursor if disabling crtc */
if (old_crtc_state->active && !new_crtc_state->active) {
	struct dc_cursor_position position;

	memset(&position, 0, sizeof(position))__builtin_memset((&position), (0), (sizeof(position)));
	mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
	dc_stream_set_cursor_position(dm_old_crtc_state->stream, &position);
	mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

/* Copy all transient state flags into dc state */
if (dm_new_crtc_state->stream) {
	amdgpu_dm_crtc_copy_transient_flags(&dm_new_crtc_state->base,
					    dm_new_crtc_state->stream);
}

/* handles headless hotplug case, updating new_state and
 * aconnector as needed
 */

if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) {

	DRM_DEBUG_ATOMIC("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Atomic commit: SET crtc id %d: [%p]\n"
, acrtc->crtc_id, acrtc);

	if (!dm_new_crtc_state->stream) {
		/*
		 * this could happen because of issues with
		 * userspace notifications delivery.
		 * In this case userspace tries to set mode on
		 * display which is disconnected in fact.
		 * dc_sink is NULL in this case on aconnector.
		 * We expect reset mode will come soon.
		 *
		 * This can also happen when unplug is done
		 * during resume sequence ended
		 *
		 * In this case, we want to pretend we still
		 * have a sink to keep the pipe running so that
		 * hw state is consistent with the sw state
		 */
		DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id)
				__func__, acrtc->base.base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id);
		continue;
	}

	if (dm_old_crtc_state->stream)
		remove_stream(adev, acrtc, dm_old_crtc_state->stream);

	pm_runtime_get_noresume(dev->dev);

	acrtc->enabled = true1;
	acrtc->hw_mode = new_crtc_state->mode;
	crtc->hwmode = new_crtc_state->mode;
	mode_set_reset_required = true1;
} else if (modereset_required(new_crtc_state)) {
	DRM_DEBUG_ATOMIC("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Atomic commit: RESET. crtc id %d:[%p]\n"
, acrtc->crtc_id, acrtc);
	/* i.e. reset mode */
	if (dm_old_crtc_state->stream)
		remove_stream(adev, acrtc, dm_old_crtc_state->stream);

	mode_set_reset_required = true1;
}
} /* for_each_crtc_in_state() */

if (dc_state) {
/* if there mode set or reset, disable eDP PSR */
if (mode_set_reset_required) {
	if (dm->vblank_control_workqueue)
		flush_workqueue(dm->vblank_control_workqueue);

	amdgpu_dm_psr_disable_all(dm);
}

dm_enable_per_frame_crtc_master_sync(dc_state);
mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
WARN_ON(!dc_commit_state(dm->dc, dc_state))({ int __ret = !!(!dc_commit_state(dm->dc, dc_state)); if (
__ret) printf("WARNING %s failed at %s:%d\n", "!dc_commit_state(dm->dc, dc_state)"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8427); __builtin_expect(!!(__ret), 0); });

/* Allow idle optimization when vblank count is 0 for display off */
if (dm->active_vblank_irq_count == 0)
	dc_allow_idle_optimizations(dm->dc, true1);
mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (dm_new_crtc_state->stream != NULL((void *)0)) {
	const struct dc_stream_status *status =
			dc_stream_get_status(dm_new_crtc_state->stream);

	if (!status)
		status = dc_stream_get_status_from_state(dc_state,
							 dm_new_crtc_state->stream);
	if (!status)
		DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc)do { __drm_err("got no status for stream %p on acrtc%p\n", dm_new_crtc_state
->stream, acrtc); do { ___drm_dbg(((void *)0), DRM_UT_DRIVER
, "%s():%d\n", __func__, 8448); do {} while (0); } while (0);
 } while (0);
	else
		acrtc->otg_inst = status->primary_otg_inst;
}
}
8453#ifdef CONFIG_DRM_AMD_DC_HDCP
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (!adev->dm.hdcp_workqueue)
	continue;

pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i)do { } while(0);

if (!connector)
	continue;

pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",do { } while(0)
	connector->index, connector->status, connector->dpms)do { } while(0);
pr_debug("[HDCP_DM] state protection old: %x new: %x\n",do { } while(0)
	old_con_state->content_protection, new_con_state->content_protection)do { } while(0);

if (aconnector->dc_sink) {
	if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
		aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
		pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",do { } while(0)
		aconnector->dc_sink->edid_caps.display_name)do { } while(0);
	}
}

new_crtc_state = NULL((void *)0);
old_crtc_state = NULL((void *)0);

if (acrtc) {
	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
	old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
}

if (old_crtc_state)
	pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",do { } while(0)
	old_crtc_state->enable,do { } while(0)
	old_crtc_state->active,do { } while(0)
	old_crtc_state->mode_changed,do { } while(0)
	old_crtc_state->active_changed,do { } while(0)
	old_crtc_state->connectors_changed)do { } while(0);

if (new_crtc_state)
	pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",do { } while(0)
	new_crtc_state->enable,do { } while(0)
	new_crtc_state->active,do { } while(0)
	new_crtc_state->mode_changed,do { } while(0)
	new_crtc_state->active_changed,do { } while(0)
	new_crtc_state->connectors_changed)do { } while(0);
}

for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});

if (!adev->dm.hdcp_workqueue)
	continue;

new_crtc_state = NULL((void *)0);
old_crtc_state = NULL((void *)0);

if (acrtc) {
	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
	old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
}

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL((void *)0) &&
    connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED2) {
	hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
	new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED1;
	dm_new_con_state->update_hdcp = true1;
	continue;
}

if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
									old_con_state, connector, adev->dm.hdcp_workqueue)) {
	/* when display is unplugged from mst hub, connctor will
	 * be destroyed within dm_dp_mst_connector_destroy. connector
	 * hdcp perperties, like type, undesired, desired, enabled,
	 * will be lost. So, save hdcp properties into hdcp_work within
	 * amdgpu_dm_atomic_commit_tail. if the same display is
	 * plugged back with same display index, its hdcp properties
	 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
	 */

	bool_Bool enable_encryption = false0;

	if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED1)
		enable_encryption = true1;

	if (aconnector->dc_link && aconnector->dc_sink &&
		aconnector->dc_link->type == dc_connection_mst_branch) {
		struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
		struct hdcp_workqueue *hdcp_w =
			&hdcp_work[aconnector->dc_link->link_index];

		hdcp_w->hdcp_content_type[connector->index] =
			new_con_state->hdcp_content_type;
		hdcp_w->content_protection[connector->index] =
			new_con_state->content_protection;
	}

	if (new_crtc_state && new_crtc_state->mode_changed &&
		new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED1)
		enable_encryption = true1;

	DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption)printk("\0016" "[" "drm" "] " "[HDCP_DM] hdcp_update_display enable_encryption = %x\n"
, enable_encryption);

	hdcp_update_display(
		adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
		new_con_state->hdcp_content_type, enable_encryption);
}
}
8570#endif

/* Handle connector state changes */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((old_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct dc_surface_update dummy_updates[MAX_SURFACES3];
struct dc_stream_update stream_update;
struct dc_info_packet hdr_packet;
struct dc_stream_status *status = NULL((void *)0);
bool_Bool abm_changed, hdr_changed, scaling_changed;

memset(&dummy_updates, 0, sizeof(dummy_updates))__builtin_memset((&dummy_updates), (0), (sizeof(dummy_updates
)));
memset(&stream_update, 0, sizeof(stream_update))__builtin_memset((&stream_update), (0), (sizeof(stream_update
)));

if (acrtc) {
	new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
	old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
}

/* Skip any modesets/resets */
if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
	continue;

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

scaling_changed = is_scaling_state_different(dm_new_con_state,
					     dm_old_con_state);

abm_changed = dm_new_crtc_state->abm_level !=
	      dm_old_crtc_state->abm_level;

hdr_changed =
	!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);

if (!scaling_changed && !abm_changed && !hdr_changed)
	continue;

stream_update.stream = dm_new_crtc_state->stream;
if (scaling_changed) {
	update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
			dm_new_con_state, dm_new_crtc_state->stream);

	stream_update.src = dm_new_crtc_state->stream->src;
	stream_update.dst = dm_new_crtc_state->stream->dst;
}

if (abm_changed) {
	dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;

	stream_update.abm_level = &dm_new_crtc_state->abm_level;
}

if (hdr_changed) {
	fill_hdr_info_packet(new_con_state, &hdr_packet);
	stream_update.hdr_static_metadata = &hdr_packet;
}

status = dc_stream_get_status(dm_new_crtc_state->stream);

if (WARN_ON(!status)({ int __ret = !!(!status); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!status", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8632); __builtin_expect(!!(__ret), 0); }))
	continue;

WARN_ON(!status->plane_count)({ int __ret = !!(!status->plane_count); if (__ret) printf
("WARNING %s failed at %s:%d\n", "!status->plane_count", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 8635); __builtin_expect(!!(__ret), 0); });

/*
 * TODO: DC refuses to perform stream updates without a dc_surface_update.
 * Here we create an empty update on each plane.
 * To fix this, DC should permit updating only stream properties.
 */
for (j = 0; j < status->plane_count; j++)
	dummy_updates[j].surface = status->plane_states[0];


mutex_lock(&dm->dc_lock)rw_enter_write(&dm->dc_lock);
dc_update_planes_and_stream(dm->dc,
			    dummy_updates,
			    status->plane_count,
			    dm_new_crtc_state->stream,
			    &stream_update);
mutex_unlock(&dm->dc_lock)rw_exit_write(&dm->dc_lock);
}

/**
* Enable interrupts for CRTCs that are newly enabled or went through
* a modeset. It was intentionally deferred until after the front end
* state was modified to wait until the OTG was on and so the IRQ
* handlers didn't access stale or invalid state.
*/
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
8663#ifdef CONFIG_DEBUG_FS
enum amdgpu_dm_pipe_crc_source cur_crc_src;
8665#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
struct crc_rd_work *crc_rd_wrk;
8667#endif
8668#endif
/* Count number of newly disabled CRTCs for dropping PM refs later. */
if (old_crtc_state->active && !new_crtc_state->active)
	crtc_disable_count++;

dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

/* For freesync config update on crtc state and params for irq */
update_stream_irq_parameters(dm, dm_new_crtc_state);

8679#ifdef CONFIG_DEBUG_FS
8680#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
crc_rd_wrk = dm->crc_rd_wrk;
8682#endif
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
cur_crc_src = acrtc->dm_irq_params.crc_src;
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
8686#endif

if (new_crtc_state->active &&
    (!old_crtc_state->active ||
     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
	dc_stream_retain(dm_new_crtc_state->stream);
	acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
	manage_dm_interrupts(adev, acrtc, true1);
}
/* Handle vrr on->off / off->on transitions */
amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);

8698#ifdef CONFIG_DEBUG_FS
if (new_crtc_state->active &&
    (!old_crtc_state->active ||
     drm_atomic_crtc_needs_modeset(new_crtc_state))) {
	/**
	 * Frontend may have changed so reapply the CRC capture
	 * settings for the stream.
	 */
	if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
8707#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
		if (amdgpu_dm_crc_window_is_activated(crtc)) {
			spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
			acrtc->dm_irq_params.crc_window.update_win = true1;
			acrtc->dm_irq_params.crc_window.skip_frame_cnt = 2;
			spin_lock_irq(&crc_rd_wrk->crc_rd_work_lock)mtx_enter(&crc_rd_wrk->crc_rd_work_lock);
			crc_rd_wrk->crtc = crtc;
			spin_unlock_irq(&crc_rd_wrk->crc_rd_work_lock)mtx_leave(&crc_rd_wrk->crc_rd_work_lock);
			spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);
		}
8717#endif
		if (amdgpu_dm_crtc_configure_crc_source(
			crtc, dm_new_crtc_state, cur_crc_src))
			DRM_DEBUG_DRIVER("Failed to configure crc source")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Failed to configure crc source"
);
	}
}
8723#endif
}

for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)for ((j) = 0; (j) < (state)->dev->mode_config.num_crtc
; (j)++) if (!((state)->crtcs[j].ptr && ((crtc) = (
state)->crtcs[j].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[j].new_state, (void)(new_crtc_state) , 1))) {} else
if (new_crtc_state->async_flip)
	wait_for_vblank = false0;

/* update planes when needed per crtc*/
for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)for ((j) = 0; (j) < (state)->dev->mode_config.num_crtc
; (j)++) if (!((state)->crtcs[j].ptr && ((crtc) = (
state)->crtcs[j].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[j].new_state, (void)(new_crtc_state) , 1))) {} else {
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (dm_new_crtc_state->stream)
	amdgpu_dm_commit_planes(state, dc_state, dev,
				dm, crtc, wait_for_vblank);
}

/* Update audio instances for each connector. */
amdgpu_dm_commit_audio(dev, state);

/* restore the backlight level */
for (i = 0; i < dm->num_of_edps; i++) {
if (dm->backlight_dev[i] &&
    (dm->actual_brightness[i] != dm->brightness[i]))
	amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
}

/*
* send vblank event on all events not handled in flip and
* mark consumed event for drm_atomic_helper_commit_hw_done
*/
spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags)do { flags = 0; mtx_enter(&adev_to_drm(adev)->event_lock
); } while (0);
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {

if (new_crtc_state->event)
	drm_send_event_locked(dev, &new_crtc_state->event->base);

new_crtc_state->event = NULL((void *)0);
}
spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags)do { (void)(flags); mtx_leave(&adev_to_drm(adev)->event_lock
); } while (0);

/* Signal HW programming completion */
drm_atomic_helper_commit_hw_done(state);

if (wait_for_vblank)
drm_atomic_helper_wait_for_flip_done(dev, state);

drm_atomic_helper_cleanup_planes(dev, state);

/* return the stolen vga memory back to VRAM */
if (!adev->mman.keep_stolen_vga_memory)
amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL((void *)0), NULL((void *)0));
amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL((void *)0), NULL((void *)0));

/*
* Finally, drop a runtime PM reference for each newly disabled CRTC,
* so we can put the GPU into runtime suspend if we're not driving any
* displays anymore
*/
for (i = 0; i < crtc_disable_count; i++)
pm_runtime_put_autosuspend(dev->dev);
pm_runtime_mark_last_busy(dev->dev);

if (dc_state_temp)
dc_release_state(dc_state_temp);
8787}

8789static int dm_force_atomic_commit(struct drm_connector *connector)
8790{
int ret = 0;
struct drm_device *ddev = connector->dev;
struct drm_atomic_state *state = drm_atomic_state_alloc(ddev);
struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (connector->encoder->crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
struct drm_plane *plane = disconnected_acrtc->base.primary;
struct drm_connector_state *conn_state;
struct drm_crtc_state *crtc_state;
struct drm_plane_state *plane_state;

if (!state)
return -ENOMEM12;

state->acquire_ctx = ddev->mode_config.acquire_ctx;

/* Construct an atomic state to restore previous display setting */

/*
* Attach connectors to drm_atomic_state
*/
conn_state = drm_atomic_get_connector_state(state, connector);

ret = PTR_ERR_OR_ZERO(conn_state);
if (ret)
goto out;

/* Attach crtc to drm_atomic_state*/
crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base);

ret = PTR_ERR_OR_ZERO(crtc_state);
if (ret)
goto out;

/* force a restore */
crtc_state->mode_changed = true1;

/* Attach plane to drm_atomic_state */
plane_state = drm_atomic_get_plane_state(state, plane);

ret = PTR_ERR_OR_ZERO(plane_state);
if (ret)
goto out;

/* Call commit internally with the state we just constructed */
ret = drm_atomic_commit(state);

8836out:
drm_atomic_state_put(state);
if (ret)
DRM_ERROR("Restoring old state failed with %i\n", ret)__drm_err("Restoring old state failed with %i\n", ret);

return ret;
8842}

8844/*
* This function handles all cases when set mode does not come upon hotplug.
* This includes when a display is unplugged then plugged back into the
* same port and when running without usermode desktop manager supprot
*/
8849void dm_restore_drm_connector_state(struct drm_device *dev,
		    struct drm_connector *connector)
8851{
struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct amdgpu_crtc *disconnected_acrtc;
struct dm_crtc_state *acrtc_state;

if (!aconnector->dc_sink || !connector->state || !connector->encoder)
return;

disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (connector->encoder->crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});
if (!disconnected_acrtc)
return;

acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (disconnected_acrtc->base.state); (struct dm_crtc_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_crtc_state
, base) );});
if (!acrtc_state->stream)
return;

/*
* If the previous sink is not released and different from the current,
* we deduce we are in a state where we can not rely on usermode call
* to turn on the display, so we do it here
*/
if (acrtc_state->stream->sink != aconnector->dc_sink)
dm_force_atomic_commit(&aconnector->base);
8874}

8876/*
* Grabs all modesetting locks to serialize against any blocking commits,
* Waits for completion of all non blocking commits.
*/
8880static int do_aquire_global_lock(struct drm_device *dev,
		 struct drm_atomic_state *state)
8882{
struct drm_crtc *crtc;
struct drm_crtc_commit *commit;
long ret;

/*
* Adding all modeset locks to aquire_ctx will
* ensure that when the framework release it the
* extra locks we are locking here will get released to
*/
ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx);
if (ret)
return ret;

list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&dev->mode_config.crtc_list)->next);
 (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&dev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
spin_lock(&crtc->commit_lock)mtx_enter(&crtc->commit_lock);
commit = list_first_entry_or_null(&crtc->commit_list,(list_empty(&crtc->commit_list) ? ((void *)0) : ({ const
 __typeof( ((struct drm_crtc_commit *)0)->commit_entry ) *
__mptr = ((&crtc->commit_list)->next); (struct drm_crtc_commit
 *)( (char *)__mptr - __builtin_offsetof(struct drm_crtc_commit
, commit_entry) );}))
		struct drm_crtc_commit, commit_entry)(list_empty(&crtc->commit_list) ? ((void *)0) : ({ const
 __typeof( ((struct drm_crtc_commit *)0)->commit_entry ) *
__mptr = ((&crtc->commit_list)->next); (struct drm_crtc_commit
 *)( (char *)__mptr - __builtin_offsetof(struct drm_crtc_commit
, commit_entry) );}));
if (commit)
	drm_crtc_commit_get(commit);
spin_unlock(&crtc->commit_lock)mtx_leave(&crtc->commit_lock);

if (!commit)
	continue;

/*
 * Make sure all pending HW programming completed and
 * page flips done
 */
ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZhz);

if (ret > 0)
	ret = wait_for_completion_interruptible_timeout(
			&commit->flip_done, 10*HZhz);

if (ret == 0)
	DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",__drm_err("[CRTC:%d:%s] hw_done or flip_done timed out\n", crtc
->base.id, crtc->name)
		  crtc->base.id, crtc->name)__drm_err("[CRTC:%d:%s] hw_done or flip_done timed out\n", crtc
->base.id, crtc->name);

drm_crtc_commit_put(commit);
}

return ret < 0 ? ret : 0;
8925}

8927static void get_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state,
struct dm_connector_state *new_con_state)
8930{
struct mod_freesync_config config = {0};
struct amdgpu_dm_connector *aconnector =
	to_amdgpu_dm_connector(new_con_state->base.connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (new_con_state->base.connector); (struct amdgpu_dm_connector
 *)( (char *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector
, base) );});
struct drm_display_mode *mode = &new_crtc_state->base.mode;
int vrefresh = drm_mode_vrefresh(mode);
bool_Bool fs_vid_mode = false0;

new_crtc_state->vrr_supported = new_con_state->freesync_capable &&
			vrefresh >= aconnector->min_vfreq &&
			vrefresh <= aconnector->max_vfreq;

if (new_crtc_state->vrr_supported) {
new_crtc_state->stream->ignore_msa_timing_param = true1;
fs_vid_mode = new_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;

config.min_refresh_in_uhz = aconnector->min_vfreq * 1000000;
config.max_refresh_in_uhz = aconnector->max_vfreq * 1000000;
config.vsif_supported = true1;
config.btr = true1;

if (fs_vid_mode) {
	config.state = VRR_STATE_ACTIVE_FIXED;
	config.fixed_refresh_in_uhz = new_crtc_state->freesync_config.fixed_refresh_in_uhz;
	goto out;
} else if (new_crtc_state->base.vrr_enabled) {
	config.state = VRR_STATE_ACTIVE_VARIABLE;
} else {
	config.state = VRR_STATE_INACTIVE;
}
}
8961out:
new_crtc_state->freesync_config = config;
8963}

8965static void reset_freesync_config_for_crtc(
struct dm_crtc_state *new_crtc_state)
8967{
new_crtc_state->vrr_supported = false0;

memset(&new_crtc_state->vrr_infopacket, 0,__builtin_memset((&new_crtc_state->vrr_infopacket), (0
), (sizeof(new_crtc_state->vrr_infopacket)))
      sizeof(new_crtc_state->vrr_infopacket))__builtin_memset((&new_crtc_state->vrr_infopacket), (0
), (sizeof(new_crtc_state->vrr_infopacket)));
8972}

8974static bool_Bool
8975is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state,
		 struct drm_crtc_state *new_crtc_state)
8977{
const struct drm_display_mode *old_mode, *new_mode;

if (!old_crtc_state || !new_crtc_state)
return false0;

old_mode = &old_crtc_state->mode;
new_mode = &new_crtc_state->mode;

if (old_mode->clock       == new_mode->clock &&
   old_mode->hdisplay    == new_mode->hdisplay &&
   old_mode->vdisplay    == new_mode->vdisplay &&
   old_mode->htotal      == new_mode->htotal &&
   old_mode->vtotal      != new_mode->vtotal &&
   old_mode->hsync_start == new_mode->hsync_start &&
   old_mode->vsync_start != new_mode->vsync_start &&
   old_mode->hsync_end   == new_mode->hsync_end &&
   old_mode->vsync_end   != new_mode->vsync_end &&
   old_mode->hskew       == new_mode->hskew &&
   old_mode->vscan       == new_mode->vscan &&
   (old_mode->vsync_end - old_mode->vsync_start) ==
   (new_mode->vsync_end - new_mode->vsync_start))
return true1;

return false0;
9002}

9004static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)
9005{
u64 num, den, res;
struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;

dm_new_crtc_state->freesync_config.state = VRR_STATE_ACTIVE_FIXED;

num = (unsigned long long)new_crtc_state->mode.clock * 1000 * 1000000;
den = (unsigned long long)new_crtc_state->mode.htotal *
     (unsigned long long)new_crtc_state->mode.vtotal;

res = div_u64(num, den);
dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = res;
9017}

9019static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
	 struct drm_atomic_state *state,
	 struct drm_crtc *crtc,
	 struct drm_crtc_state *old_crtc_state,
	 struct drm_crtc_state *new_crtc_state,
	 bool_Bool enable,
	 bool_Bool *lock_and_validation_needed)
9026{
struct dm_atomic_state *dm_state = NULL((void *)0);
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
struct dc_stream_state *new_stream;
int ret = 0;

/*
* TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set
* update changed items
*/
struct amdgpu_crtc *acrtc = NULL((void *)0);
struct amdgpu_dm_connector *aconnector = NULL((void *)0);
struct drm_connector_state *drm_new_conn_state = NULL((void *)0), *drm_old_conn_state = NULL((void *)0);
struct dm_connector_state *dm_new_conn_state = NULL((void *)0), *dm_old_conn_state = NULL((void *)0);

new_stream = NULL((void *)0);

dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
acrtc = to_amdgpu_crtc(crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (crtc); (struct amdgpu_crtc *)( (char *)__mptr - __builtin_offsetof
(struct amdgpu_crtc, base) );});
aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc);

/* TODO This hack should go away */
if (aconnector && enable) {
/* Make sure fake sink is created in plug-in scenario */
drm_new_conn_state = drm_atomic_get_new_connector_state(state,
					    &aconnector->base);
drm_old_conn_state = drm_atomic_get_old_connector_state(state,
					    &aconnector->base);

if (IS_ERR(drm_new_conn_state)) {
	ret = PTR_ERR_OR_ZERO(drm_new_conn_state);
	goto fail;
}

dm_new_conn_state = to_dm_connector_state(drm_new_conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((drm_new_conn_state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});
dm_old_conn_state = to_dm_connector_state(drm_old_conn_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((drm_old_conn_state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
	goto skip_modeset;

new_stream = create_validate_stream_for_sink(aconnector,
					     &new_crtc_state->mode,
					     dm_new_conn_state,
					     dm_old_crtc_state->stream);

/*
 * we can have no stream on ACTION_SET if a display
 * was disconnected during S3, in this case it is not an
 * error, the OS will be updated after detection, and
 * will do the right thing on next atomic commit
 */

if (!new_stream) {
	DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id)
			__func__, acrtc->base.base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "%s: Failed to create new stream for crtc %d\n"
, __func__, acrtc->base.base.id);
	ret = -ENOMEM12;
	goto fail;
}

/*
 * TODO: Check VSDB bits to decide whether this should
 * be enabled or not.
 */
new_stream->triggered_crtc_reset.enabled =
	dm->force_timing_sync;

dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;

ret = fill_hdr_info_packet(drm_new_conn_state,
			   &new_stream->hdr_static_metadata);
if (ret)
	goto fail;

/*
 * If we already removed the old stream from the context
 * (and set the new stream to NULL) then we can't reuse
 * the old stream even if the stream and scaling are unchanged.
 * We'll hit the BUG_ON and black screen.
 *
 * TODO: Refactor this function to allow this check to work
 * in all conditions.
 */
if (dm_new_crtc_state->stream &&
    is_timing_unchanged_for_freesync(new_crtc_state, old_crtc_state))
	goto skip_modeset;

if (dm_new_crtc_state->stream &&
    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) {
	new_crtc_state->mode_changed = false0;
	DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d",___drm_dbg(((void *)0), DRM_UT_DRIVER, "Mode change not required, setting mode_changed to %d"
, new_crtc_state->mode_changed)
			 new_crtc_state->mode_changed)___drm_dbg(((void *)0), DRM_UT_DRIVER, "Mode change not required, setting mode_changed to %d"
, new_crtc_state->mode_changed);
}
}

/* mode_changed flag may get updated above, need to check again */
if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
goto skip_modeset;

drm_dbg_state(state->dev,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
acrtc->crtc_id,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->enable,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->active,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->planes_changed,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->mode_changed,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->active_changed,__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed)
new_crtc_state->connectors_changed)__drm_dev_dbg(((void *)0), (state->dev) ? (state->dev)->
dev : ((void *)0), DRM_UT_STATE, "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n"
, acrtc->crtc_id, new_crtc_state->enable, new_crtc_state
->active, new_crtc_state->planes_changed, new_crtc_state
->mode_changed, new_crtc_state->active_changed, new_crtc_state
->connectors_changed);

/* Remove stream for any changed/disabled CRTC */
if (!enable) {

if (!dm_old_crtc_state->stream)
	goto skip_modeset;

/* Unset freesync video if it was active before */
if (dm_old_crtc_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED) {
	dm_new_crtc_state->freesync_config.state = VRR_STATE_INACTIVE;
	dm_new_crtc_state->freesync_config.fixed_refresh_in_uhz = 0;
}

/* Now check if we should set freesync video mode */
if (dm_new_crtc_state->stream &&
    dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) &&
    dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream) &&
    is_timing_unchanged_for_freesync(new_crtc_state,
				     old_crtc_state)) {
	new_crtc_state->mode_changed = false0;
	DRM_DEBUG_DRIVER(___drm_dbg(((void *)0), DRM_UT_DRIVER, "Mode change not required for front porch change, setting mode_changed to %d"
, new_crtc_state->mode_changed)
		"Mode change not required for front porch change, setting mode_changed to %d",___drm_dbg(((void *)0), DRM_UT_DRIVER, "Mode change not required for front porch change, setting mode_changed to %d"
, new_crtc_state->mode_changed)
		new_crtc_state->mode_changed)___drm_dbg(((void *)0), DRM_UT_DRIVER, "Mode change not required for front porch change, setting mode_changed to %d"
, new_crtc_state->mode_changed);

	set_freesync_fixed_config(dm_new_crtc_state);

	goto skip_modeset;
} else if (aconnector &&
	   is_freesync_video_mode(&new_crtc_state->mode,
				  aconnector)) {
	struct drm_display_mode *high_mode;

	high_mode = get_highest_refresh_rate_mode(aconnector, false0);
	if (!drm_mode_equal(&new_crtc_state->mode, high_mode))
		set_freesync_fixed_config(dm_new_crtc_state);
}

ret = dm_atomic_get_state(state, &dm_state);
if (ret)
	goto fail;

DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "Disabling DRM crtc: %d\n"
, crtc->base.id)
		crtc->base.id)___drm_dbg(((void *)0), DRM_UT_DRIVER, "Disabling DRM crtc: %d\n"
, crtc->base.id);

/* i.e. reset mode */
if (dc_remove_stream_from_ctx(
		dm->dc,
		dm_state->context,
		dm_old_crtc_state->stream) != DC_OK) {
	ret = -EINVAL22;
	goto fail;
}

dc_stream_release(dm_old_crtc_state->stream);
dm_new_crtc_state->stream = NULL((void *)0);

reset_freesync_config_for_crtc(dm_new_crtc_state);

*lock_and_validation_needed = true1;

} else {/* Add stream for any updated/enabled CRTC */
/*
 * Quick fix to prevent NULL pointer on new_stream when
 * added MST connectors not found in existing crtc_state in the chained mode
 * TODO: need to dig out the root cause of that
 */
if (!aconnector)
	goto skip_modeset;

if (modereset_required(new_crtc_state))
	goto skip_modeset;

if (modeset_required(new_crtc_state, new_stream,
		     dm_old_crtc_state->stream)) {

	WARN_ON(dm_new_crtc_state->stream)({ int __ret = !!(dm_new_crtc_state->stream); if (__ret) printf
("WARNING %s failed at %s:%d\n", "dm_new_crtc_state->stream"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 9210); __builtin_expect(!!(__ret), 0); });

	ret = dm_atomic_get_state(state, &dm_state);
	if (ret)
		goto fail;

	dm_new_crtc_state->stream = new_stream;

	dc_stream_retain(new_stream);

	DRM_DEBUG_ATOMIC("Enabling DRM crtc: %d\n",___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Enabling DRM crtc: %d\n"
, crtc->base.id)
			 crtc->base.id)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Enabling DRM crtc: %d\n"
, crtc->base.id);

	if (dc_add_stream_to_ctx(
			dm->dc,
			dm_state->context,
			dm_new_crtc_state->stream) != DC_OK) {
		ret = -EINVAL22;
		goto fail;
	}

	*lock_and_validation_needed = true1;
}
}

9235skip_modeset:
/* Release extra reference */
if (new_stream)
 dc_stream_release(new_stream);

/*
* We want to do dc stream updates that do not require a
* full modeset below.
*/
if (!(enable && aconnector && new_crtc_state->active))
return 0;
/*
* Given above conditions, the dc state cannot be NULL because:
* 1. We're in the process of enabling CRTCs (just been added
*    to the dc context, or already is on the context)
* 2. Has a valid connector attached, and
* 3. Is currently active and enabled.
* => The dc stream state currently exists.
*/
BUG_ON(dm_new_crtc_state->stream == NULL)((!(dm_new_crtc_state->stream == ((void *)0))) ? (void)0 :
 __assert("diagnostic ", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 9254, "!(dm_new_crtc_state->stream == ((void *)0))"));

/* Scaling or underscan settings */
if (is_scaling_state_different(dm_old_conn_state, dm_new_conn_state) ||
		drm_atomic_crtc_needs_modeset(new_crtc_state))
update_stream_scaling_settings(
	&new_crtc_state->mode, dm_new_conn_state, dm_new_crtc_state->stream);

/* ABM settings */
dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level;

/*
* Color management settings. We also update color properties
* when a modeset is needed, to ensure it gets reprogrammed.
*/
if (dm_new_crtc_state->base.color_mgmt_changed ||
   drm_atomic_crtc_needs_modeset(new_crtc_state)) {
ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
if (ret)
	goto fail;
}

/* Update Freesync settings. */
get_freesync_config_for_crtc(dm_new_crtc_state,
		     dm_new_conn_state);

return ret;

9282fail:
if (new_stream)
dc_stream_release(new_stream);
return ret;
9286}

9288static bool_Bool should_reset_plane(struct drm_atomic_state *state,
	       struct drm_plane *plane,
	       struct drm_plane_state *old_plane_state,
	       struct drm_plane_state *new_plane_state)
9292{
struct drm_plane *other;
struct drm_plane_state *old_other_state, *new_other_state;
struct drm_crtc_state *new_crtc_state;
struct amdgpu_device *adev = drm_to_adev(plane->dev);
int i;

/*
* TODO: Remove this hack for all asics once it proves that the
* fast updates works fine on DCN3.2+.
*/
if (adev->ip_versions[DCE_HWIP][0] < IP_VERSION(3, 2, 0)(((3) << 16) | ((2) << 8) | (0)) && state->allow_modeset)
return true1;

/* Exit early if we know that we're adding or removing the plane. */
if (old_plane_state->crtc != new_plane_state->crtc)
return true1;

/* old crtc == new_crtc == NULL, plane not in context. */
if (!new_plane_state->crtc)
return false0;

new_crtc_state =
drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);

if (!new_crtc_state)
return true1;

/* CRTC Degamma changes currently require us to recreate planes. */
if (new_crtc_state->color_mgmt_changed)
return true1;

if (drm_atomic_crtc_needs_modeset(new_crtc_state))
return true1;

/*
* If there are any new primary or overlay planes being added or
* removed then the z-order can potentially change. To ensure
* correct z-order and pipe acquisition the current DC architecture
* requires us to remove and recreate all existing planes.
*
* TODO: Come up with a more elegant solution for this.
*/
for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((other) =
 (state)->planes[i].ptr, (void)(other) , (old_other_state)
 = (state)->planes[i].old_state, (new_other_state) = (state
)->planes[i].new_state, 1))) {} else {
struct amdgpu_framebuffer *old_afb, *new_afb;

if (other->type == DRM_PLANE_TYPE_CURSOR)
	continue;

if (old_other_state->crtc != new_plane_state->crtc &&
    new_other_state->crtc != new_plane_state->crtc)
	continue;

if (old_other_state->crtc != new_other_state->crtc)
	return true1;

/* Src/dst size and scaling updates. */
if (old_other_state->src_w != new_other_state->src_w ||
    old_other_state->src_h != new_other_state->src_h ||
    old_other_state->crtc_w != new_other_state->crtc_w ||
    old_other_state->crtc_h != new_other_state->crtc_h)
	return true1;

/* Rotation / mirroring updates. */
if (old_other_state->rotation != new_other_state->rotation)
	return true1;

/* Blending updates. */
if (old_other_state->pixel_blend_mode !=
    new_other_state->pixel_blend_mode)
	return true1;

/* Alpha updates. */
if (old_other_state->alpha != new_other_state->alpha)
	return true1;

/* Colorspace changes. */
if (old_other_state->color_range != new_other_state->color_range ||
    old_other_state->color_encoding != new_other_state->color_encoding)
	return true1;

/* Framebuffer checks fall at the end. */
if (!old_other_state->fb || !new_other_state->fb)
	continue;

/* Pixel format changes can require bandwidth updates. */
if (old_other_state->fb->format != new_other_state->fb->format)
	return true1;

old_afb = (struct amdgpu_framebuffer *)old_other_state->fb;
new_afb = (struct amdgpu_framebuffer *)new_other_state->fb;

/* Tiling and DCC changes also require bandwidth updates. */
if (old_afb->tiling_flags != new_afb->tiling_flags ||
    old_afb->base.modifier != new_afb->base.modifier)
	return true1;
}

return false0;
9391}

9393static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
	      struct drm_plane_state *new_plane_state,
	      struct drm_framebuffer *fb)
9396{
struct amdgpu_device *adev = drm_to_adev(new_acrtc->base.dev);
struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb)({ const __typeof( ((struct amdgpu_framebuffer *)0)->base )
 *__mptr = (fb); (struct amdgpu_framebuffer *)( (char *)__mptr
 - __builtin_offsetof(struct amdgpu_framebuffer, base) );});
unsigned int pitch;
bool_Bool linear;

if (fb->width > new_acrtc->max_cursor_width ||
   fb->height > new_acrtc->max_cursor_height) {
DRM_DEBUG_ATOMIC("Bad cursor FB size %dx%d\n",___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Bad cursor FB size %dx%d\n"
, new_plane_state->fb->width, new_plane_state->fb->
height)
		 new_plane_state->fb->width,___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Bad cursor FB size %dx%d\n"
, new_plane_state->fb->width, new_plane_state->fb->
height)
		 new_plane_state->fb->height)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Bad cursor FB size %dx%d\n"
, new_plane_state->fb->width, new_plane_state->fb->
height);
return -EINVAL22;
}
if (new_plane_state->src_w != fb->width << 16 ||
   new_plane_state->src_h != fb->height << 16) {
DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n")___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Cropping not supported for cursor plane\n"
);
return -EINVAL22;
}

/* Pitch in pixels */
pitch = fb->pitches[0] / fb->format->cpp[0];

if (fb->width != pitch) {
DRM_DEBUG_ATOMIC("Cursor FB width %d doesn't match pitch %d",___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Cursor FB width %d doesn't match pitch %d"
, fb->width, pitch)
		 fb->width, pitch)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Cursor FB width %d doesn't match pitch %d"
, fb->width, pitch);
return -EINVAL22;
}

switch (pitch) {
case 64:
case 128:
case 256:
/* FB pitch is supported by cursor plane */
break;
default:
DRM_DEBUG_ATOMIC("Bad cursor FB pitch %d px\n", pitch)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Bad cursor FB pitch %d px\n"
, pitch);
return -EINVAL22;
}

/* Core DRM takes care of checking FB modifiers, so we only need to
* check tiling flags when the FB doesn't have a modifier.
*/
if (!(fb->flags & DRM_MODE_FB_MODIFIERS(1<<1))) {
if (adev->family < AMDGPU_FAMILY_AI141) {
	linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE)(((__u64)(afb->tiling_flags) >> 0) & 0xf) != DC_ARRAY_2D_TILED_THIN1 &&
		 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE)(((__u64)(afb->tiling_flags) >> 0) & 0xf) != DC_ARRAY_1D_TILED_THIN1 &&
		 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE)(((__u64)(afb->tiling_flags) >> 12) & 0x7) == 0;
} else {
	linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)(((__u64)(afb->tiling_flags) >> 0) & 0x1f) == 0;
}
if (!linear) {
	DRM_DEBUG_ATOMIC("Cursor FB not linear")___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Cursor FB not linear"
);
	return -EINVAL22;
}
}

return 0;
9453}

9455static int dm_update_plane_state(struct dc *dc,
		 struct drm_atomic_state *state,
		 struct drm_plane *plane,
		 struct drm_plane_state *old_plane_state,
		 struct drm_plane_state *new_plane_state,
		 bool_Bool enable,
		 bool_Bool *lock_and_validation_needed)
9462{

struct dm_atomic_state *dm_state = NULL((void *)0);
struct drm_crtc *new_plane_crtc, *old_plane_crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
struct amdgpu_crtc *new_acrtc;
bool_Bool needs_reset;
int ret = 0;


new_plane_crtc = new_plane_state->crtc;
old_plane_crtc = old_plane_state->crtc;
dm_new_plane_state = to_dm_plane_state(new_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (new_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});
dm_old_plane_state = to_dm_plane_state(old_plane_state)({ const __typeof( ((struct dm_plane_state *)0)->base ) *__mptr
 = (old_plane_state); (struct dm_plane_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_plane_state, base) );});

if (plane->type == DRM_PLANE_TYPE_CURSOR) {
if (!enable || !new_plane_crtc ||
	drm_atomic_plane_disabling(plane->state, new_plane_state))
	return 0;

new_acrtc = to_amdgpu_crtc(new_plane_crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (new_plane_crtc); (struct amdgpu_crtc *)( (char *)__mptr -
 __builtin_offsetof(struct amdgpu_crtc, base) );});

if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
	DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n")___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Cropping not supported for cursor plane\n"
);
	return -EINVAL22;
}

if (new_plane_state->fb) {
	ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
				 new_plane_state->fb);
	if (ret)
		return ret;
}

return 0;
}

needs_reset = should_reset_plane(state, plane, old_plane_state,
			 new_plane_state);

/* Remove any changed/removed planes */
if (!enable) {
if (!needs_reset)
	return 0;

if (!old_plane_crtc)
	return 0;

old_crtc_state = drm_atomic_get_old_crtc_state(
		state, old_plane_crtc);
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (!dm_old_crtc_state->stream)
	return 0;

DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n",___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Disabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, old_plane_crtc->base.id)
		plane->base.id, old_plane_crtc->base.id)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Disabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, old_plane_crtc->base.id);

ret = dm_atomic_get_state(state, &dm_state);
if (ret)
	return ret;

if (!dc_remove_plane_from_context(
		dc,
		dm_old_crtc_state->stream,
		dm_old_plane_state->dc_state,
		dm_state->context)) {

	return -EINVAL22;
}

if (dm_old_plane_state->dc_state)
	dc_plane_state_release(dm_old_plane_state->dc_state);

dm_new_plane_state->dc_state = NULL((void *)0);

*lock_and_validation_needed = true1;

} else { /* Add new planes */
struct dc_plane_state *dc_new_plane_state;

if (drm_atomic_plane_disabling(plane->state, new_plane_state))
	return 0;

if (!new_plane_crtc)
	return 0;

new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc);
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (!dm_new_crtc_state->stream)
	return 0;

if (!needs_reset)
	return 0;

ret = dm_plane_helper_check_state(new_plane_state, new_crtc_state);
if (ret)
	return ret;

WARN_ON(dm_new_plane_state->dc_state)({ int __ret = !!(dm_new_plane_state->dc_state); if (__ret
) printf("WARNING %s failed at %s:%d\n", "dm_new_plane_state->dc_state"
, "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 9564); __builtin_expect(!!(__ret), 0); });

dc_new_plane_state = dc_create_plane_state(dc);
if (!dc_new_plane_state)
	return -ENOMEM12;

DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Enabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, new_plane_crtc->base.id)
		 plane->base.id, new_plane_crtc->base.id)___drm_dbg(((void *)0), DRM_UT_ATOMIC, "Enabling DRM plane: %d on DRM crtc %d\n"
, plane->base.id, new_plane_crtc->base.id);

ret = fill_dc_plane_attributes(
	drm_to_adev(new_plane_crtc->dev),
	dc_new_plane_state,
	new_plane_state,
	new_crtc_state);
if (ret) {
	dc_plane_state_release(dc_new_plane_state);
	return ret;
}

ret = dm_atomic_get_state(state, &dm_state);
if (ret) {
	dc_plane_state_release(dc_new_plane_state);
	return ret;
}

/*
 * Any atomic check errors that occur after this will
 * not need a release. The plane state will be attached
 * to the stream, and therefore part of the atomic
 * state. It'll be released when the atomic state is
 * cleaned.
 */
if (!dc_add_plane_to_context(
		dc,
		dm_new_crtc_state->stream,
		dc_new_plane_state,
		dm_state->context)) {

	dc_plane_state_release(dc_new_plane_state);
	return -EINVAL22;
}

dm_new_plane_state->dc_state = dc_new_plane_state;

dm_new_crtc_state->mpo_requested |= (plane->type == DRM_PLANE_TYPE_OVERLAY);

/* Tell DC to do a full surface update every time there
 * is a plane change. Inefficient, but works for now.
 */
dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;

*lock_and_validation_needed = true1;
}


return ret;
9620}

9622static void dm_get_oriented_plane_size(struct drm_plane_state *plane_state,
		       int *src_w, int *src_h)
9624{
switch (plane_state->rotation & DRM_MODE_ROTATE_MASK( (1<<0) | (1<<1) | (1<<2) | (1<<3))) {
case DRM_MODE_ROTATE_90(1<<1):
case DRM_MODE_ROTATE_270(1<<3):
*src_w = plane_state->src_h >> 16;
*src_h = plane_state->src_w >> 16;
break;
case DRM_MODE_ROTATE_0(1<<0):
case DRM_MODE_ROTATE_180(1<<2):
default:
*src_w = plane_state->src_w >> 16;
*src_h = plane_state->src_h >> 16;
break;
}
9638}

9640static void
9641dm_get_plane_scale(struct drm_plane_state *plane_state,
   int *out_plane_scale_w, int *out_plane_scale_h)
9643{
int plane_src_w, plane_src_h;

dm_get_oriented_plane_size(plane_state, &plane_src_w, &plane_src_h);
*out_plane_scale_w = plane_state->crtc_w * 1000 / plane_src_w;
*out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
9649}

9651static int dm_check_crtc_cursor(struct drm_atomic_state *state,
		struct drm_crtc *crtc,
		struct drm_crtc_state *new_crtc_state)
9654{
struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
struct drm_plane_state *old_plane_state, *new_plane_state;
struct drm_plane_state *new_cursor_state, *new_underlying_state;
int i;
int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
bool_Bool any_relevant_change = false0;

/* On DCE and DCN there is no dedicated hardware cursor plane. We get a
* cursor per pipe but it's going to inherit the scaling and
* positioning from the underlying pipe. Check the cursor plane's
* blending properties match the underlying planes'.
*/

/* If no plane was enabled or changed scaling, no need to check again */
for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else {
int new_scale_w, new_scale_h, old_scale_w, old_scale_h;

if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
	continue;

if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
	any_relevant_change = true1;
	break;
}

if (new_plane_state->fb == old_plane_state->fb &&
    new_plane_state->crtc_w == old_plane_state->crtc_w &&
    new_plane_state->crtc_h == old_plane_state->crtc_h)
	continue;

dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);

if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
	any_relevant_change = true1;
	break;
}
}

if (!any_relevant_change)
return 0;

new_cursor_state = drm_atomic_get_plane_state(state, cursor);
if (IS_ERR(new_cursor_state))
return PTR_ERR(new_cursor_state);

if (!new_cursor_state->fb)
return 0;

dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);

/* Need to check all enabled planes, even if this commit doesn't change
* their state
*/
i = drm_atomic_add_affected_planes(state, crtc);
if (i)
return i;

for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i)for ((i) = ((state)->dev->mode_config.num_total_plane -
 1); (i) >= 0; (i)--) if (!((state)->planes[i].ptr &&
 ((underlying) = (state)->planes[i].ptr, (new_underlying_state
) = (state)->planes[i].new_state, 1))) {} else {
/* Narrow down to non-cursor planes on the same CRTC as the cursor */
if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
	continue;

/* Ignore disabled planes */
if (!new_underlying_state->fb)
	continue;

dm_get_plane_scale(new_underlying_state,
		   &underlying_scale_w, &underlying_scale_h);

if (cursor_scale_w != underlying_scale_w ||
    cursor_scale_h != underlying_scale_h) {
	drm_dbg_atomic(crtc->dev,__drm_dev_dbg(((void *)0), (crtc->dev) ? (crtc->dev)->
dev : ((void *)0), DRM_UT_ATOMIC, "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n"
, cursor->base.id, cursor->name, underlying->base.id
, underlying->name)
		       "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",__drm_dev_dbg(((void *)0), (crtc->dev) ? (crtc->dev)->
dev : ((void *)0), DRM_UT_ATOMIC, "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n"
, cursor->base.id, cursor->name, underlying->base.id
, underlying->name)
		       cursor->base.id, cursor->name, underlying->base.id, underlying->name)__drm_dev_dbg(((void *)0), (crtc->dev) ? (crtc->dev)->
dev : ((void *)0), DRM_UT_ATOMIC, "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n"
, cursor->base.id, cursor->name, underlying->base.id
, underlying->name);
	return -EINVAL22;
}

/* If this plane covers the whole CRTC, no need to check planes underneath */
if (new_underlying_state->crtc_x <= 0 &&
    new_underlying_state->crtc_y <= 0 &&
    new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
    new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
	break;
}

return 0;
9742}

9744#if defined(CONFIG_DRM_AMD_DC_DCN1)
9745static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
9746{
struct drm_connector *connector;
struct drm_connector_state *conn_state, *old_conn_state;
struct amdgpu_dm_connector *aconnector = NULL((void *)0);
int i;

for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_conn_state)
 = (state)->connectors[i].old_state, (conn_state) = (state
)->connectors[i].new_state, 1))) {} else {
if (!conn_state->crtc)
	conn_state = old_conn_state;

if (conn_state->crtc != crtc)
	continue;

aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
if (!aconnector->port || !aconnector->mst_port)
	aconnector = NULL((void *)0);
else
	break;
}

if (!aconnector)
return 0;

return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_port->mst_mgr);
9770}
9771#endif

9773/**
* amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
*
* @dev: The DRM device
* @state: The atomic state to commit
*
* Validate that the given atomic state is programmable by DC into hardware.
* This involves constructing a &struct dc_state reflecting the new hardware
* state we wish to commit, then querying DC to see if it is programmable. It's
* important not to modify the existing DC state. Otherwise, atomic_check
* may unexpectedly commit hardware changes.
*
* When validating the DC state, it's important that the right locks are
* acquired. For full updates case which removes/adds/updates streams on one
* CRTC while flipping on another CRTC, acquiring global lock will guarantee
* that any such full update commit will wait for completion of any outstanding
* flip using DRMs synchronization events.
*
* Note that DM adds the affected connectors for all CRTCs in state, when that
* might not seem necessary. This is because DC stream creation requires the
* DC sink, which is tied to the DRM connector state. Cleaning this up should
* be possible but non-trivial - a possible TODO item.
*
* Return: -Error code if validation failed.
*/
9798static int amdgpu_dm_atomic_check(struct drm_device *dev,
		  struct drm_atomic_state *state)
9800{
struct amdgpu_device *adev = drm_to_adev(dev);
struct dm_atomic_state *dm_state = NULL((void *)0);
struct dc *dc = adev->dm.dc;
struct drm_connector *connector;
struct drm_connector_state *old_con_state, *new_con_state;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
struct drm_plane *plane;
struct drm_plane_state *old_plane_state, *new_plane_state;
enum dc_status status;
int ret, i;
bool_Bool lock_and_validation_needed = false0;
struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
9814#if defined(CONFIG_DRM_AMD_DC_DCN1)
struct drm_dp_mst_topology_mgr *mgr;
struct drm_dp_mst_topology_state *mst_state;
struct dsc_mst_fairness_vars vars[MAX_PIPES6];
9818#endif

trace_amdgpu_dm_atomic_check_begin(state);

ret = drm_atomic_helper_check_modeset(dev, state);
if (ret) {
DRM_DEBUG_DRIVER("drm_atomic_helper_check_modeset() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "drm_atomic_helper_check_modeset() failed\n"
);
goto fail;
}

/* Check connector changes */
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((old_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});

/* Skip connectors that are disabled or part of modeset already. */
if (!new_con_state->crtc)
	continue;

new_crtc_state = drm_atomic_get_crtc_state(state, new_con_state->crtc);
if (IS_ERR(new_crtc_state)) {
	DRM_DEBUG_DRIVER("drm_atomic_get_crtc_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "drm_atomic_get_crtc_state() failed\n"
);
	ret = PTR_ERR(new_crtc_state);
	goto fail;
}

if (dm_old_con_state->abm_level != dm_new_con_state->abm_level ||
    dm_old_con_state->scaling != dm_new_con_state->scaling)
	new_crtc_state->connectors_changed = true1;
}

9849#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (dc_resource_is_dsc_encoding_supported(dc)) {
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
	if (drm_atomic_crtc_needs_modeset(new_crtc_state)) {
		ret = add_affected_mst_dsc_crtcs(state, crtc);
		if (ret) {
			DRM_DEBUG_DRIVER("add_affected_mst_dsc_crtcs() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "add_affected_mst_dsc_crtcs() failed\n"
);
			goto fail;
		}
	}
}
}
9861#endif
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
dm_old_crtc_state = to_dm_crtc_state(old_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (old_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

if (!drm_atomic_crtc_needs_modeset(new_crtc_state) &&
    !new_crtc_state->color_mgmt_changed &&
    old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled &&
	dm_old_crtc_state->dsc_force_changed == false0)
	continue;

ret = amdgpu_dm_verify_lut_sizes(new_crtc_state);
if (ret) {
	DRM_DEBUG_DRIVER("amdgpu_dm_verify_lut_sizes() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "amdgpu_dm_verify_lut_sizes() failed\n"
);
	goto fail;
}

if (!new_crtc_state->enable)
	continue;

ret = drm_atomic_add_affected_connectors(state, crtc);
if (ret) {
	DRM_DEBUG_DRIVER("drm_atomic_add_affected_connectors() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "drm_atomic_add_affected_connectors() failed\n"
);
	goto fail;
}

ret = drm_atomic_add_affected_planes(state, crtc);
if (ret) {
	DRM_DEBUG_DRIVER("drm_atomic_add_affected_planes() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "drm_atomic_add_affected_planes() failed\n"
);
	goto fail;
}

if (dm_old_crtc_state->dsc_force_changed)
	new_crtc_state->mode_changed = true1;
}

/*
* Add all primary and overlay planes on the CRTC to the state
* whenever a plane is enabled to maintain correct z-ordering
* and to enable fast surface updates.
*/
drm_for_each_crtc(crtc, dev)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&(dev)->mode_config.crtc_list)->next
); (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&(dev)->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
bool_Bool modified = false0;

for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_total_plane
; (i)++) if (!((state)->planes[i].ptr && ((plane) =
 (state)->planes[i].ptr, (void)(plane) , (old_plane_state)
 = (state)->planes[i].old_state, (new_plane_state) = (state
)->planes[i].new_state, 1))) {} else {
	if (plane->type == DRM_PLANE_TYPE_CURSOR)
		continue;

	if (new_plane_state->crtc == crtc ||
	    old_plane_state->crtc == crtc) {
		modified = true1;
		break;
	}
}

if (!modified)
	continue;

drm_for_each_plane_mask(plane, state->dev, crtc->state->plane_mask)for ((plane) = ({ const __typeof( ((__typeof(*(plane)) *)0)->
head ) *__mptr = ((&(state->dev)->mode_config.plane_list
)->next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*(plane)), head) );}); &(plane)->head != (&
(state->dev)->mode_config.plane_list); (plane) = ({ const
 __typeof( ((__typeof(*(plane)) *)0)->head ) *__mptr = ((plane
)->head.next); (__typeof(*(plane)) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*(plane)), head) );})) if (!((crtc->state->plane_mask
) & drm_plane_mask(plane))) {} else {
	if (plane->type == DRM_PLANE_TYPE_CURSOR)
		continue;

	new_plane_state =
		drm_atomic_get_plane_state(state, plane);

	if (IS_ERR(new_plane_state)) {
		ret = PTR_ERR(new_plane_state);
		DRM_DEBUG_DRIVER("new_plane_state is BAD\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "new_plane_state is BAD\n"
);
		goto fail;
	}
}
}

/*
* DC consults the zpos (layer_index in DC terminology) to determine the
* hw plane on which to enable the hw cursor (see
* `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
* atomic state, so call drm helper to normalize zpos.
*/
ret = drm_atomic_normalize_zpos(dev, state);
if (ret) {
drm_dbg(dev, "drm_atomic_normalize_zpos() failed\n")__drm_dev_dbg(((void *)0), (dev) ? (dev)->dev : ((void *)0
), DRM_UT_DRIVER, "drm_atomic_normalize_zpos() failed\n");
goto fail;
}

/* Remove exiting planes if they are modified */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i)for ((i) = ((state)->dev->mode_config.num_total_plane -
 1); (i) >= 0; (i)--) if (!((state)->planes[i].ptr &&
 ((plane) = (state)->planes[i].ptr, (old_plane_state) = (state
)->planes[i].old_state, (new_plane_state) = (state)->planes
[i].new_state, 1))) {} else {
if (old_plane_state->fb && new_plane_state->fb &&
    get_mem_type(old_plane_state->fb) !=
    get_mem_type(new_plane_state->fb))
	lock_and_validation_needed = true1;

ret = dm_update_plane_state(dc, state, plane,
			    old_plane_state,
			    new_plane_state,
			    false0,
			    &lock_and_validation_needed);
if (ret) {
	DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "dm_update_plane_state() failed\n"
);
	goto fail;
}
}

/* Disable all crtcs which require disable */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
ret = dm_update_crtc_state(&adev->dm, state, crtc,
			   old_crtc_state,
			   new_crtc_state,
			   false0,
			   &lock_and_validation_needed);
if (ret) {
	DRM_DEBUG_DRIVER("DISABLE: dm_update_crtc_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "DISABLE: dm_update_crtc_state() failed\n"
);
	goto fail;
}
}

/* Enable all crtcs which require enable */
for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (old_crtc_state) = (state
)->crtcs[i].old_state, (void)(old_crtc_state) , (new_crtc_state
) = (state)->crtcs[i].new_state, (void)(new_crtc_state) , 1
))) {} else {
ret = dm_update_crtc_state(&adev->dm, state, crtc,
			   old_crtc_state,
			   new_crtc_state,
			   true1,
			   &lock_and_validation_needed);
if (ret) {
	DRM_DEBUG_DRIVER("ENABLE: dm_update_crtc_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "ENABLE: dm_update_crtc_state() failed\n"
);
	goto fail;
}
}

/* Add new/modified planes */
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i)for ((i) = ((state)->dev->mode_config.num_total_plane -
 1); (i) >= 0; (i)--) if (!((state)->planes[i].ptr &&
 ((plane) = (state)->planes[i].ptr, (old_plane_state) = (state
)->planes[i].old_state, (new_plane_state) = (state)->planes
[i].new_state, 1))) {} else {
ret = dm_update_plane_state(dc, state, plane,
			    old_plane_state,
			    new_plane_state,
			    true1,
			    &lock_and_validation_needed);
if (ret) {
	DRM_DEBUG_DRIVER("dm_update_plane_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "dm_update_plane_state() failed\n"
);
	goto fail;
}
}

10002#if defined(CONFIG_DRM_AMD_DC_DCN1)
if (dc_resource_is_dsc_encoding_supported(dc)) {
ret = pre_validate_dsc(state, &dm_state, vars);
if (ret != 0)
	goto fail;
}
10008#endif

/* Run this here since we want to validate the streams we created */
ret = drm_atomic_helper_check_planes(dev, state);
if (ret) {
DRM_DEBUG_DRIVER("drm_atomic_helper_check_planes() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "drm_atomic_helper_check_planes() failed\n"
);
goto fail;
}

for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
dm_new_crtc_state = to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});
if (dm_new_crtc_state->mpo_requested)
	DRM_DEBUG_DRIVER("MPO enablement requested on crtc:[%p]\n", crtc)___drm_dbg(((void *)0), DRM_UT_DRIVER, "MPO enablement requested on crtc:[%p]\n"
, crtc);
}

/* Check cursor planes scaling */
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
if (ret) {
	DRM_DEBUG_DRIVER("dm_check_crtc_cursor() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "dm_check_crtc_cursor() failed\n"
);
	goto fail;
}
}

if (state->legacy_cursor_update) {
/*
 * This is a fast cursor update coming from the plane update
 * helper, check if it can be done asynchronously for better
 * performance.
 */
state->async_update =
	!drm_atomic_helper_async_check(dev, state);

/*
 * Skip the remaining global validation if this is an async
 * update. Cursor updates can be done without affecting
 * state or bandwidth calcs and this avoids the performance
 * penalty of locking the private state object and
 * allocating a new dc_state.
 */
if (state->async_update)
	return 0;
}

/* Check scaling and underscan changes*/
/* TODO Removed scaling changes validation due to inability to commit
* new stream into context w\o causing full reset. Need to
* decide how to handle.
*/
for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i)for ((i) = 0; (i) < (state)->num_connector; (i)++) if (
!((state)->connectors[i].ptr && ((connector) = (state
)->connectors[i].ptr, (void)(connector) , (old_con_state) =
 (state)->connectors[i].old_state, (new_con_state) = (state
)->connectors[i].new_state, 1))) {} else {
struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((old_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((new_con_state)); (struct dm_connector_state *)( (
char *)__mptr - __builtin_offsetof(struct dm_connector_state,
 base) );});
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc)({ const __typeof( ((struct amdgpu_crtc *)0)->base ) *__mptr
 = (dm_new_con_state->base.crtc); (struct amdgpu_crtc *)( (
char *)__mptr - __builtin_offsetof(struct amdgpu_crtc, base) )
;});

/* Skip any modesets/resets */
if (!acrtc || drm_atomic_crtc_needs_modeset(
		drm_atomic_get_new_crtc_state(state, &acrtc->base)))
	continue;

/* Skip any thing not scale or underscan changes */
if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state))
	continue;

lock_and_validation_needed = true1;
}

10074#if defined(CONFIG_DRM_AMD_DC_DCN1)
/* set the slot info for each mst_state based on the link encoding format */
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i)for ((i) = 0; (i) < (state)->num_private_objs; (i)++) if
 (!(__drm_dp_mst_state_iter_get((state), &(mgr), ((void *
)0), &(mst_state), (i)))) {} else {
struct amdgpu_dm_connector *aconnector;
struct drm_connector *connector;
struct drm_connector_list_iter iter;
u8 link_coding_cap;

drm_connector_list_iter_begin(dev, &iter);
drm_for_each_connector_iter(connector, &iter)while ((connector = drm_connector_list_iter_next(&iter))) {
	if (connector->index == mst_state->mgr->conn_base_id) {
		aconnector = to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
		link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link);
		drm_dp_mst_update_slots(mst_state, link_coding_cap);

		break;
	}
}
drm_connector_list_iter_end(&iter);
}
10094#endif

/**
* Streams and planes are reset when there are changes that affect
* bandwidth. Anything that affects bandwidth needs to go through
* DC global validation to ensure that the configuration can be applied
* to hardware.
*
* We have to currently stall out here in atomic_check for outstanding
* commits to finish in this case because our IRQ handlers reference
* DRM state directly - we can end up disabling interrupts too early
* if we don't.
*
* TODO: Remove this stall and drop DM state private objects.
*/
if (lock_and_validation_needed) {
ret = dm_atomic_get_state(state, &dm_state);
if (ret) {
	DRM_DEBUG_DRIVER("dm_atomic_get_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "dm_atomic_get_state() failed\n"
);
	goto fail;
}

ret = do_aquire_global_lock(dev, state);
if (ret) {
	DRM_DEBUG_DRIVER("do_aquire_global_lock() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "do_aquire_global_lock() failed\n"
);
	goto fail;
}

10122#if defined(CONFIG_DRM_AMD_DC_DCN1)
ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars);
if (ret) {
	DRM_DEBUG_DRIVER("compute_mst_dsc_configs_for_state() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "compute_mst_dsc_configs_for_state() failed\n"
);
	ret = -EINVAL22;
	goto fail;
}

ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
if (ret) {
	DRM_DEBUG_DRIVER("dm_update_mst_vcpi_slots_for_dsc() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "dm_update_mst_vcpi_slots_for_dsc() failed\n"
);
	goto fail;
}
10135#endif

/*
 * Perform validation of MST topology in the state:
 * We need to perform MST atomic check before calling
 * dc_validate_global_state(), or there is a chance
 * to get stuck in an infinite loop and hang eventually.
 */
ret = drm_dp_mst_atomic_check(state);
if (ret) {
	DRM_DEBUG_DRIVER("drm_dp_mst_atomic_check() failed\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "drm_dp_mst_atomic_check() failed\n"
);
	goto fail;
}
status = dc_validate_global_state(dc, dm_state->context, true1);
if (status != DC_OK) {
	DRM_DEBUG_DRIVER("DC global validation failure: %s (%d)",___drm_dbg(((void *)0), DRM_UT_DRIVER, "DC global validation failure: %s (%d)"
, dc_status_to_str(status), status)
		       dc_status_to_str(status), status)___drm_dbg(((void *)0), DRM_UT_DRIVER, "DC global validation failure: %s (%d)"
, dc_status_to_str(status), status);
	ret = -EINVAL22;
	goto fail;
}
} else {
/*
 * The commit is a fast update. Fast updates shouldn't change
 * the DC context, affect global validation, and can have their
 * commit work done in parallel with other commits not touching
 * the same resource. If we have a new DC context as part of
 * the DM atomic state from validation we need to free it and
 * retain the existing one instead.
 *
 * Furthermore, since the DM atomic state only contains the DC
 * context and can safely be annulled, we can free the state
 * and clear the associated private object now to free
 * some memory and avoid a possible use-after-free later.
 */

for (i = 0; i < state->num_private_objs; i++) {
	struct drm_private_obj *obj = state->private_objs[i].ptr;

	if (obj->funcs == adev->dm.atomic_obj.funcs) {
		int j = state->num_private_objs-1;

		dm_atomic_destroy_state(obj,
				state->private_objs[i].state);

		/* If i is not at the end of the array then the
		 * last element needs to be moved to where i was
		 * before the array can safely be truncated.
		 */
		if (i != j)
			state->private_objs[i] =
				state->private_objs[j];

		state->private_objs[j].ptr = NULL((void *)0);
		state->private_objs[j].state = NULL((void *)0);
		state->private_objs[j].old_state = NULL((void *)0);
		state->private_objs[j].new_state = NULL((void *)0);

		state->num_private_objs = j;
		break;
	}
}
}

/* Store the overall update type for use later in atomic check. */
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i)for ((i) = 0; (i) < (state)->dev->mode_config.num_crtc
; (i)++) if (!((state)->crtcs[i].ptr && ((crtc) = (
state)->crtcs[i].ptr, (void)(crtc) , (new_crtc_state) = (state
)->crtcs[i].new_state, (void)(new_crtc_state) , 1))) {} else {
struct dm_crtc_state *dm_new_crtc_state =
	to_dm_crtc_state(new_crtc_state)({ const __typeof( ((struct dm_crtc_state *)0)->base ) *__mptr
 = (new_crtc_state); (struct dm_crtc_state *)( (char *)__mptr
 - __builtin_offsetof(struct dm_crtc_state, base) );});

/*
 * Only allow async flips for fast updates that don't change
 * the FB pitch, the DCC state, rotation, etc.
 */
if (new_crtc_state->async_flip && lock_and_validation_needed) {
	drm_dbg_atomic(crtc->dev,__drm_dev_dbg(((void *)0), (crtc->dev) ? (crtc->dev)->
dev : ((void *)0), DRM_UT_ATOMIC, "[CRTC:%d:%s] async flips are only supported for fast updates\n"
, crtc->base.id, crtc->name)
		       "[CRTC:%d:%s] async flips are only supported for fast updates\n",__drm_dev_dbg(((void *)0), (crtc->dev) ? (crtc->dev)->
dev : ((void *)0), DRM_UT_ATOMIC, "[CRTC:%d:%s] async flips are only supported for fast updates\n"
, crtc->base.id, crtc->name)
		       crtc->base.id, crtc->name)__drm_dev_dbg(((void *)0), (crtc->dev) ? (crtc->dev)->
dev : ((void *)0), DRM_UT_ATOMIC, "[CRTC:%d:%s] async flips are only supported for fast updates\n"
, crtc->base.id, crtc->name);
	ret = -EINVAL22;
	goto fail;
}

dm_new_crtc_state->update_type = lock_and_validation_needed ?
	UPDATE_TYPE_FULL : UPDATE_TYPE_FAST;
}

/* Must be success */
WARN_ON(ret)({ int __ret = !!(ret); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "ret", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 10220); __builtin_expect(!!(__ret), 0); });

trace_amdgpu_dm_atomic_check_finish(state, ret);

return ret;

10226fail:
if (ret == -EDEADLK11)
DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Atomic check stopped to avoid deadlock.\n"
);
else if (ret == -EINTR4 || ret == -EAGAIN35 || ret == -ERESTARTSYS4)
DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n")___drm_dbg(((void *)0), DRM_UT_DRIVER, "Atomic check stopped due to signal.\n"
);
else
DRM_DEBUG_DRIVER("Atomic check failed with err: %d\n", ret)___drm_dbg(((void *)0), DRM_UT_DRIVER, "Atomic check failed with err: %d\n"
, ret);

trace_amdgpu_dm_atomic_check_finish(state, ret);

return ret;
10237}

10239static bool_Bool is_dp_capable_without_timing_msa(struct dc *dc,
			     struct amdgpu_dm_connector *amdgpu_dm_connector)
10241{
u8 dpcd_data;
bool_Bool capable = false0;

if (amdgpu_dm_connector->dc_link &&
dm_helpers_dp_read_dpcd(
		NULL((void *)0),
		amdgpu_dm_connector->dc_link,
		DP_DOWN_STREAM_PORT_COUNT0x007,
		&dpcd_data,
		sizeof(dpcd_data))) {
capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED(1 << 6)) ? true1:false0;
}

return capable;
10256}

10258static bool_Bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
unsigned int offset,
unsigned int total_length,
u8 *data,
unsigned int length,
struct amdgpu_hdmi_vsdb_info *vsdb)
10264{
bool_Bool res;
union dmub_rb_cmd cmd;
struct dmub_cmd_send_edid_cea *input;
struct dmub_cmd_edid_cea_output *output;

if (length > DMUB_EDID_CEA_DATA_CHUNK_BYTES8)
return false0;

memset(&cmd, 0, sizeof(cmd))__builtin_memset((&cmd), (0), (sizeof(cmd)));

input = &cmd.edid_cea.data.input;

cmd.edid_cea.header.type = DMUB_CMD__EDID_CEA;
cmd.edid_cea.header.sub_type = 0;
cmd.edid_cea.header.payload_bytes =
sizeof(cmd.edid_cea) - sizeof(cmd.edid_cea.header);
input->offset = offset;
input->length = length;
input->cea_total_length = total_length;
memcpy(input->payload, data, length)__builtin_memcpy((input->payload), (data), (length));

res = dc_dmub_srv_cmd_with_reply_data(dm->dc->ctx->dmub_srv, &cmd);
if (!res) {
DRM_ERROR("EDID CEA parser failed\n")__drm_err("EDID CEA parser failed\n");
return false0;
}

output = &cmd.edid_cea.data.output;

if (output->type == DMUB_CMD__EDID_CEA_ACK) {
if (!output->ack.success) {
	DRM_ERROR("EDID CEA ack failed at offset %d\n",__drm_err("EDID CEA ack failed at offset %d\n", output->ack
.offset)
			output->ack.offset)__drm_err("EDID CEA ack failed at offset %d\n", output->ack
.offset);
}
} else if (output->type == DMUB_CMD__EDID_CEA_AMD_VSDB) {
if (!output->amd_vsdb.vsdb_found)
	return false0;

vsdb->freesync_supported = output->amd_vsdb.freesync_supported;
vsdb->amd_vsdb_version = output->amd_vsdb.amd_vsdb_version;
vsdb->min_refresh_rate_hz = output->amd_vsdb.min_frame_rate;
vsdb->max_refresh_rate_hz = output->amd_vsdb.max_frame_rate;
} else {
if (output->type != 0)
	DRM_WARN("Unknown EDID CEA parser results\n")printk("\0014" "[" "drm" "] " "Unknown EDID CEA parser results\n"
);
return false0;
}

return true1;
10314}

10316static bool_Bool parse_edid_cea_dmcu(struct amdgpu_display_manager *dm,
u8 *edid_ext, int len,
struct amdgpu_hdmi_vsdb_info *vsdb_info)
10319{
int i;

/* send extension block to DMCU for parsing */
for (i = 0; i < len; i += 8) {
bool_Bool res;
int offset;

/* send 8 bytes a time */
if (!dc_edid_parser_send_cea(dm->dc, i, len, &edid_ext[i], 8))
	return false0;

if (i+8 == len) {
	/* EDID block sent completed, expect result */
	int version, min_rate, max_rate;

	res = dc_edid_parser_recv_amd_vsdb(dm->dc, &version, &min_rate, &max_rate);
	if (res) {
		/* amd vsdb found */
		vsdb_info->freesync_supported = 1;
		vsdb_info->amd_vsdb_version = version;
		vsdb_info->min_refresh_rate_hz = min_rate;
		vsdb_info->max_refresh_rate_hz = max_rate;
		return true1;
	}
	/* not amd vsdb */
	return false0;
}

/* check for ack*/
res = dc_edid_parser_recv_cea_ack(dm->dc, &offset);
if (!res)
	return false0;
}

return false0;
10355}

10357static bool_Bool parse_edid_cea_dmub(struct amdgpu_display_manager *dm,
u8 *edid_ext, int len,
struct amdgpu_hdmi_vsdb_info *vsdb_info)
10360{
int i;

/* send extension block to DMCU for parsing */
for (i = 0; i < len; i += 8) {
/* send 8 bytes a time */
if (!dm_edid_parser_send_cea(dm, i, len, &edid_ext[i], 8, vsdb_info))
	return false0;
}

return vsdb_info->freesync_supported;
10371}

10373static bool_Bool parse_edid_cea(struct amdgpu_dm_connector *aconnector,
u8 *edid_ext, int len,
struct amdgpu_hdmi_vsdb_info *vsdb_info)
10376{
struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev);

if (adev->dm.dmub_srv)
return parse_edid_cea_dmub(&adev->dm, edid_ext, len, vsdb_info);
else
return parse_edid_cea_dmcu(&adev->dm, edid_ext, len, vsdb_info);
10383}

10385static int parse_hdmi_amd_vsdb(struct amdgpu_dm_connector *aconnector,
struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info)
10387{
u8 *edid_ext = NULL((void *)0);
int i;
bool_Bool valid_vsdb_found = false0;

/*----- drm_find_cea_extension() -----*/
/* No EDID or EDID extensions */
if (edid == NULL((void *)0) || edid->extensions == 0)
return -ENODEV19;

/* Find CEA extension */
for (i = 0; i < edid->extensions; i++) {
edid_ext = (uint8_t *)edid + EDID_LENGTH128 * (i + 1);
if (edid_ext[0] == CEA_EXT0x02)
	break;
}

if (i == edid->extensions)
return -ENODEV19;

/*----- cea_db_offsets() -----*/
if (edid_ext[0] != CEA_EXT0x02)
return -ENODEV19;

valid_vsdb_found = parse_edid_cea(aconnector, edid_ext, EDID_LENGTH128, vsdb_info);

return valid_vsdb_found ? i : -ENODEV19;
10414}

10416/**
* amdgpu_dm_update_freesync_caps - Update Freesync capabilities
*
* @connector: Connector to query.
* @edid: EDID from monitor
*
* Amdgpu supports Freesync in DP and HDMI displays, and it is required to keep
* track of some of the display information in the internal data struct used by
* amdgpu_dm. This function checks which type of connector we need to set the
* FreeSync parameters.
*/
10427void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
		    struct edid *edid)
10429{
int i = 0;
struct detailed_timing *timing;
struct detailed_non_pixel *data;
struct detailed_data_monitor_range *range;
struct amdgpu_dm_connector *amdgpu_dm_connector =
	to_amdgpu_dm_connector(connector)({ const __typeof( ((struct amdgpu_dm_connector *)0)->base
 ) *__mptr = (connector); (struct amdgpu_dm_connector *)( (char
 *)__mptr - __builtin_offsetof(struct amdgpu_dm_connector, base
) );});
struct dm_connector_state *dm_con_state = NULL((void *)0);
struct dc_sink *sink;

struct drm_device *dev = connector->dev;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_hdmi_vsdb_info vsdb_info = {0};
bool_Bool freesync_capable = false0;

if (!connector->state) {
DRM_ERROR("%s - Connector has no state", __func__)__drm_err("%s - Connector has no state", __func__);
goto update;
}

sink = amdgpu_dm_connector->dc_sink ?
amdgpu_dm_connector->dc_sink :
amdgpu_dm_connector->dc_em_sink;

if (!edid || !sink) {
dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

amdgpu_dm_connector->min_vfreq = 0;
amdgpu_dm_connector->max_vfreq = 0;
amdgpu_dm_connector->pixel_clock_mhz = 0;
connector->display_info.monitor_range.min_vfreq = 0;
connector->display_info.monitor_range.max_vfreq = 0;
freesync_capable = false0;

goto update;
}

dm_con_state = to_dm_connector_state(connector->state)({ const __typeof( ((struct dm_connector_state *)0)->base )
 *__mptr = ((connector->state)); (struct dm_connector_state
 *)( (char *)__mptr - __builtin_offsetof(struct dm_connector_state
, base) );});

if (!adev->dm.freesync_module)
goto update;

if (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT
|| sink->sink_signal == SIGNAL_TYPE_EDP) {
bool_Bool edid_check_required = false0;

if (edid) {
	edid_check_required = is_dp_capable_without_timing_msa(
				adev->dm.dc,
				amdgpu_dm_connector);
}

if (edid_check_required == true1 && (edid->version > 1 ||
   (edid->version == 1 && edid->revision > 1))) {
	for (i = 0; i < 4; i++) {

		timing	= &edid->detailed_timings[i];
		data	= &timing->data.other_data;
		range	= &data->data.range;
		/*
		 * Check if monitor has continuous frequency mode
		 */
		if (data->type != EDID_DETAIL_MONITOR_RANGE0xfd)
			continue;
		/*
		 * Check for flag range limits only. If flag == 1 then
		 * no additional timing information provided.
		 * Default GTF, GTF Secondary curve and CVT are not
		 * supported
		 */
		if (range->flags != 1)
			continue;

		amdgpu_dm_connector->min_vfreq = range->min_vfreq;
		amdgpu_dm_connector->max_vfreq = range->max_vfreq;
		amdgpu_dm_connector->pixel_clock_mhz =
			range->pixel_clock_mhz * 10;

		connector->display_info.monitor_range.min_vfreq = range->min_vfreq;
		connector->display_info.monitor_range.max_vfreq = range->max_vfreq;

		break;
	}

	if (amdgpu_dm_connector->max_vfreq -
	    amdgpu_dm_connector->min_vfreq > 10) {

		freesync_capable = true1;
	}
}
} else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) {
i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info);
if (i >= 0 && vsdb_info.freesync_supported) {
	timing  = &edid->detailed_timings[i];
	data    = &timing->data.other_data;

	amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz;
	amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz;
	if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10)
		freesync_capable = true1;

	connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz;
	connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz;
}
}

10535update:
if (dm_con_state)
dm_con_state->freesync_capable = freesync_capable;

if (connector->vrr_capable_property)
drm_connector_set_vrr_capable_property(connector,
				       freesync_capable);
10542}

10544void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)
10545{
struct amdgpu_device *adev = drm_to_adev(dev);
struct dc *dc = adev->dm.dc;
int i;

mutex_lock(&adev->dm.dc_lock)rw_enter_write(&adev->dm.dc_lock);
if (dc->current_state) {
for (i = 0; i < dc->current_state->stream_count; ++i)
	dc->current_state->streams[i]
		->triggered_crtc_reset.enabled =
		adev->dm.force_timing_sync;

dm_enable_per_frame_crtc_master_sync(dc->current_state);
dc_trigger_sync(dc, dc->current_state);
}
mutex_unlock(&adev->dm.dc_lock)rw_exit_write(&adev->dm.dc_lock);
10561}

10563void dm_write_reg_func(const struct dc_context *ctx, uint32_t address,
       u32 value, const char *func_name)
10565{
10566#ifdef DM_CHECK_ADDR_0
if (address == 0) {
DC_ERR("invalid register write. address = 0")do { __drm_err("invalid register write. address = 0"); do { ___drm_dbg
(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__, 10568); do
 {} while (0); } while (0); } while (0);
return;
}
10571#endif
cgs_write_register(ctx->cgs_device, address, value)(((struct cgs_device *)ctx->cgs_device)->ops->write_register
(ctx->cgs_device,address,value));
trace_amdgpu_dc_wreg(&ctx->perf_trace->write_count, address, value);
10574}

10576uint32_t dm_read_reg_func(const struct dc_context *ctx, uint32_t address,
	  const char *func_name)
10578{
u32 value;
10580#ifdef DM_CHECK_ADDR_0
if (address == 0) {
DC_ERR("invalid register read; address = 0\n")do { __drm_err("invalid register read; address = 0\n"); do { ___drm_dbg
(((void *)0), DRM_UT_DRIVER, "%s():%d\n", __func__, 10582); do
 {} while (0); } while (0); } while (0);
return 0;
}
10585#endif

if (ctx->dmub_srv &&
   ctx->dmub_srv->reg_helper_offload.gather_in_progress &&
   !ctx->dmub_srv->reg_helper_offload.should_burst_write) {
ASSERT(false)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
 && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm/amdgpu_dm.c"
, 10590); __warned = 1; } __builtin_expect(!!(__ret), 0); }))
 do {} while (0); } while (0);
return 0;
}

value = cgs_read_register(ctx->cgs_device, address)(((struct cgs_device *)ctx->cgs_device)->ops->read_register
(ctx->cgs_device,address));

trace_amdgpu_dc_rreg(&ctx->perf_trace->read_count, address, value);

return value;
10599}

10601int amdgpu_dm_process_dmub_aux_transfer_sync(
struct dc_context *ctx,
unsigned int link_index,
struct aux_payload *payload,
enum aux_return_code_type *operation_result)
10606{
struct amdgpu_device *adev = ctx->driver_context;
struct dmub_notification *p_notify = adev->dm.dmub_notify;
int ret = -1;

mutex_lock(&adev->dm.dpia_aux_lock)rw_enter_write(&adev->dm.dpia_aux_lock);
if (!dc_process_dmub_aux_transfer_async(ctx->dc, link_index, payload)) {
*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
goto out;
}

if (!wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZhz)) {
DRM_ERROR("wait_for_completion_timeout timeout!")__drm_err("wait_for_completion_timeout timeout!");
*operation_result = AUX_RET_ERROR_TIMEOUT;
goto out;
}

if (p_notify->result != AUX_RET_SUCCESS) {
/*
 * Transient states before tunneling is enabled could
 * lead to this error. We can ignore this for now.
 */
if (p_notify->result != AUX_RET_ERROR_PROTOCOL_ERROR) {
	DRM_WARN("DPIA AUX failed on 0x%x(%d), error %d\n",printk("\0014" "[" "drm" "] " "DPIA AUX failed on 0x%x(%d), error %d\n"
, payload->address, payload->length, p_notify->result
)
			payload->address, payload->length,printk("\0014" "[" "drm" "] " "DPIA AUX failed on 0x%x(%d), error %d\n"
, payload->address, payload->length, p_notify->result
)
			p_notify->result)printk("\0014" "[" "drm" "] " "DPIA AUX failed on 0x%x(%d), error %d\n"
, payload->address, payload->length, p_notify->result
);
}
*operation_result = AUX_RET_ERROR_INVALID_REPLY;
goto out;
}


payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
if (!payload->write && p_notify->aux_reply.length &&
	(payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK)) {

if (payload->length != p_notify->aux_reply.length) {
	DRM_WARN("invalid read length %d from DPIA AUX 0x%x(%d)!\n",printk("\0014" "[" "drm" "] " "invalid read length %d from DPIA AUX 0x%x(%d)!\n"
, p_notify->aux_reply.length, payload->address, payload
->length)
		p_notify->aux_reply.length,printk("\0014" "[" "drm" "] " "invalid read length %d from DPIA AUX 0x%x(%d)!\n"
, p_notify->aux_reply.length, payload->address, payload
->length)
			payload->address, payload->length)printk("\0014" "[" "drm" "] " "invalid read length %d from DPIA AUX 0x%x(%d)!\n"
, p_notify->aux_reply.length, payload->address, payload
->length);
	*operation_result = AUX_RET_ERROR_INVALID_REPLY;
	goto out;
}

memcpy(payload->data, p_notify->aux_reply.data,__builtin_memcpy((payload->data), (p_notify->aux_reply.
data), (p_notify->aux_reply.length))
		p_notify->aux_reply.length)__builtin_memcpy((payload->data), (p_notify->aux_reply.
data), (p_notify->aux_reply.length));
}

/* success */
ret = p_notify->aux_reply.length;
*operation_result = p_notify->result;
10657out:
reinit_completion(&adev->dm.dmub_aux_transfer_done);
mutex_unlock(&adev->dm.dpia_aux_lock)rw_exit_write(&adev->dm.dpia_aux_lock);
return ret;
10661}

10663int amdgpu_dm_process_dmub_set_config_sync(
struct dc_context *ctx,
unsigned int link_index,
struct set_config_cmd_payload *payload,
enum set_config_status *operation_result)
10668{
struct amdgpu_device *adev = ctx->driver_context;
bool_Bool is_cmd_complete;
int ret;

mutex_lock(&adev->dm.dpia_aux_lock)rw_enter_write(&adev->dm.dpia_aux_lock);
is_cmd_complete = dc_process_dmub_set_config_async(ctx->dc,
	link_index, payload, adev->dm.dmub_notify);

if (is_cmd_complete || wait_for_completion_timeout(&adev->dm.dmub_aux_transfer_done, 10 * HZhz)) {
ret = 0;
*operation_result = adev->dm.dmub_notify->sc_status;
} else {
DRM_ERROR("wait_for_completion_timeout timeout!")__drm_err("wait_for_completion_timeout timeout!");
ret = -1;
*operation_result = SET_CONFIG_UNKNOWN_ERROR;
}

if (!is_cmd_complete)
reinit_completion(&adev->dm.dmub_aux_transfer_done);
mutex_unlock(&adev->dm.dpia_aux_lock)rw_exit_write(&adev->dm.dpia_aux_lock);
return ret;
10690}

10692/*
* Check whether seamless boot is supported.
*
* So far we only support seamless boot on CHIP_VANGOGH.
* If everything goes well, we may consider expanding
* seamless boot to other ASICs.
*/
10699bool_Bool check_seamless_boot_capability(struct amdgpu_device *adev)
10700{
switch (adev->asic_type) {
case CHIP_VANGOGH:
if (!adev->mman.keep_stolen_vga_memory)
	return true1;
break;
default:
break;
}

return false0;
10711}