/usr/src/sys/dev/pci/drm/radeon/r100.c

Bug Summary

File:	dev/pci/drm/radeon/r100.c
Warning:	line 3822, column 3 3rd function call argument is an uninitialized value
Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name r100.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/radeon/r100.c
1/*
* Copyright 2008 Advanced Micro Devices, Inc.
* Copyright 2008 Red Hat Inc.
* Copyright 2009 Jerome Glisse.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Dave Airlie
*          Alex Deucher
*          Jerome Glisse
*/

29#include <linux/firmware.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/seq_file.h>
33#include <linux/slab.h>

35#include <drm/drm_device.h>
36#include <drm/drm_file.h>
37#include <drm/drm_fourcc.h>
38#include <drm/drm_framebuffer.h>
39#include <drm/drm_vblank.h>
40#include <drm/radeon_drm.h>

42#include "atom.h"
43#include "r100_reg_safe.h"
44#include "r100d.h"
45#include "radeon.h"
46#include "radeon_asic.h"
47#include "radeon_reg.h"
48#include "rn50_reg_safe.h"
49#include "rs100d.h"
50#include "rv200d.h"
51#include "rv250d.h"

53/* Firmware Names */
54#define FIRMWARE_R100"radeon/R100_cp.bin"		"radeon/R100_cp.bin"
55#define FIRMWARE_R200"radeon/R200_cp.bin"		"radeon/R200_cp.bin"
56#define FIRMWARE_R300"radeon/R300_cp.bin"		"radeon/R300_cp.bin"
57#define FIRMWARE_R420"radeon/R420_cp.bin"		"radeon/R420_cp.bin"
58#define FIRMWARE_RS690"radeon/RS690_cp.bin"		"radeon/RS690_cp.bin"
59#define FIRMWARE_RS600"radeon/RS600_cp.bin"		"radeon/RS600_cp.bin"
60#define FIRMWARE_R520"radeon/R520_cp.bin"		"radeon/R520_cp.bin"

62MODULE_FIRMWARE(FIRMWARE_R100);
63MODULE_FIRMWARE(FIRMWARE_R200);
64MODULE_FIRMWARE(FIRMWARE_R300);
65MODULE_FIRMWARE(FIRMWARE_R420);
66MODULE_FIRMWARE(FIRMWARE_RS690);
67MODULE_FIRMWARE(FIRMWARE_RS600);
68MODULE_FIRMWARE(FIRMWARE_R520);

70#include "r100_track.h"

72/* This files gather functions specifics to:
* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
* and others in some cases.
*/

77static bool_Bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
78{
if (crtc == 0) {
if (RREG32(RADEON_CRTC_STATUS)r100_mm_rreg(rdev, (0x005c), 0) & RADEON_CRTC_VBLANK_CUR(1 << 0))
	return true1;
else
	return false0;
} else {
if (RREG32(RADEON_CRTC2_STATUS)r100_mm_rreg(rdev, (0x03fc), 0) & RADEON_CRTC2_VBLANK_CUR(1 << 0))
	return true1;
else
	return false0;
}
90}

92static bool_Bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
93{
u32 vline1, vline2;

if (crtc == 0) {
vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE)r100_mm_rreg(rdev, (0x0210), 0) >> 16) & RADEON_CRTC_V_TOTAL(0x07ff << 0);
vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE)r100_mm_rreg(rdev, (0x0210), 0) >> 16) & RADEON_CRTC_V_TOTAL(0x07ff << 0);
} else {
vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE)r100_mm_rreg(rdev, (0x0310), 0) >> 16) & RADEON_CRTC_V_TOTAL(0x07ff << 0);
vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE)r100_mm_rreg(rdev, (0x0310), 0) >> 16) & RADEON_CRTC_V_TOTAL(0x07ff << 0);
}
if (vline1 != vline2)
return true1;
else
return false0;
107}

109/**
* r100_wait_for_vblank - vblank wait asic callback.
*
* @rdev: radeon_device pointer
* @crtc: crtc to wait for vblank on
*
* Wait for vblank on the requested crtc (r1xx-r4xx).
*/
117void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
118{
unsigned i = 0;

if (crtc >= rdev->num_crtc)
return;

if (crtc == 0) {
if (!(RREG32(RADEON_CRTC_GEN_CNTL)r100_mm_rreg(rdev, (0x0050), 0) & RADEON_CRTC_EN(1 << 25)))
	return;
} else {
if (!(RREG32(RADEON_CRTC2_GEN_CNTL)r100_mm_rreg(rdev, (0x03f8), 0) & RADEON_CRTC2_EN(1 << 25)))
	return;
}

/* depending on when we hit vblank, we may be close to active; if so,
* wait for another frame.
*/
while (r100_is_in_vblank(rdev, crtc)) {
if (i++ % 100 == 0) {
	if (!r100_is_counter_moving(rdev, crtc))
		break;
}
}

while (!r100_is_in_vblank(rdev, crtc)) {
if (i++ % 100 == 0) {
	if (!r100_is_counter_moving(rdev, crtc))
		break;
}
}
148}

150/**
* r100_page_flip - pageflip callback.
*
* @rdev: radeon_device pointer
* @crtc_id: crtc to cleanup pageflip on
* @crtc_base: new address of the crtc (GPU MC address)
* @async: asynchronous flip
*
* Does the actual pageflip (r1xx-r4xx).
* During vblank we take the crtc lock and wait for the update_pending
* bit to go high, when it does, we release the lock, and allow the
* double buffered update to take place.
*/
163void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool_Bool async)
164{
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
uint32_t crtc_pitch, pitch_pixels;
struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK(1<<31);
int i;

/* Lock the graphics update lock */
/* update the scanout addresses */
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x0224 + radeon_crtc->crtc_offset), (tmp
), 0);

/* update pitch */
pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
crtc_pitch = DIV_ROUND_UP(pitch_pixels * fb->format->cpp[0] * 8,(((pitch_pixels * fb->format->cpp[0] * 8) + ((fb->format
->cpp[0] * 8 * 8) - 1)) / (fb->format->cpp[0] * 8 * 8
))
		  fb->format->cpp[0] * 8 * 8)(((pitch_pixels * fb->format->cpp[0] * 8) + ((fb->format
->cpp[0] * 8 * 8) - 1)) / (fb->format->cpp[0] * 8 * 8
));
crtc_pitch |= crtc_pitch << 16;
WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch)r100_mm_wreg(rdev, (0x022c + radeon_crtc->crtc_offset), (crtc_pitch
), 0);

/* Wait for update_pending to go high. */
for (i = 0; i < rdev->usec_timeout; i++) {
if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x0224 + radeon_crtc->crtc_offset), 0) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET(1<<30))
	break;
udelay(1);
}
DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n")___drm_dbg(((void *)0), DRM_UT_CORE, "Update pending now high. Unlocking vupdate_lock.\n"
);

/* Unlock the lock, so double-buffering can take place inside vblank */
tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK(1<<31);
WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp)r100_mm_wreg(rdev, (0x0224 + radeon_crtc->crtc_offset), (tmp
), 0);

194}

196/**
* r100_page_flip_pending - check if page flip is still pending
*
* @rdev: radeon_device pointer
* @crtc_id: crtc to check
*
* Check if the last pagefilp is still pending (r1xx-r4xx).
* Returns the current update pending status.
*/
205bool_Bool r100_page_flip_pending(struct radeon_device *rdev, int crtc_id)
206{
struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];

/* Return current update_pending status: */
return !!(RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset)r100_mm_rreg(rdev, (0x0224 + radeon_crtc->crtc_offset), 0) &
RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET(1<<30));
212}

214/**
* r100_pm_get_dynpm_state - look up dynpm power state callback.
*
* @rdev: radeon_device pointer
*
* Look up the optimal power state based on the
* current state of the GPU (r1xx-r5xx).
* Used for dynpm only.
*/
223void r100_pm_get_dynpm_state(struct radeon_device *rdev)
224{
int i;
rdev->pm.dynpm_can_upclock = true1;
rdev->pm.dynpm_can_downclock = true1;

switch (rdev->pm.dynpm_planned_action) {
case DYNPM_ACTION_MINIMUM:
rdev->pm.requested_power_state_index = 0;
rdev->pm.dynpm_can_downclock = false0;
break;
case DYNPM_ACTION_DOWNCLOCK:
if (rdev->pm.current_power_state_index == 0) {
	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
	rdev->pm.dynpm_can_downclock = false0;
} else {
	if (rdev->pm.active_crtc_count > 1) {
		for (i = 0; i < rdev->pm.num_power_states; i++) {
			if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0))
				continue;
			else if (i >= rdev->pm.current_power_state_index) {
				rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
				break;
			} else {
				rdev->pm.requested_power_state_index = i;
				break;
			}
		}
	} else
		rdev->pm.requested_power_state_index =
			rdev->pm.current_power_state_index - 1;
}
/* don't use the power state if crtcs are active and no display flag is set */
if ((rdev->pm.active_crtc_count > 0) &&
    (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
     RADEON_PM_MODE_NO_DISPLAY(1 << 0))) {
	rdev->pm.requested_power_state_index++;
}
break;
case DYNPM_ACTION_UPCLOCK:
if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
	rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
	rdev->pm.dynpm_can_upclock = false0;
} else {
	if (rdev->pm.active_crtc_count > 1) {
		for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
			if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY(1 << 0))
				continue;
			else if (i <= rdev->pm.current_power_state_index) {
				rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
				break;
			} else {
				rdev->pm.requested_power_state_index = i;
				break;
			}
		}
	} else
		rdev->pm.requested_power_state_index =
			rdev->pm.current_power_state_index + 1;
}
break;
case DYNPM_ACTION_DEFAULT:
rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
rdev->pm.dynpm_can_upclock = false0;
break;
case DYNPM_ACTION_NONE:
default:
DRM_ERROR("Requested mode for not defined action\n")__drm_err("Requested mode for not defined action\n");
return;
}
/* only one clock mode per power state */
rdev->pm.requested_clock_mode_index = 0;

DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes)
  rdev->pm.power_state[rdev->pm.requested_power_state_index].___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes)
  clock_info[rdev->pm.requested_clock_mode_index].sclk,___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes)
  rdev->pm.power_state[rdev->pm.requested_power_state_index].___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes)
  clock_info[rdev->pm.requested_clock_mode_index].mclk,___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes)
  rdev->pm.power_state[rdev->pm.requested_power_state_index].___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes)
  pcie_lanes)___drm_dbg(((void *)0), DRM_UT_DRIVER, "Requested: e: %d m: %d p: %d\n"
, rdev->pm.power_state[rdev->pm.requested_power_state_index
]. clock_info[rdev->pm.requested_clock_mode_index].sclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 clock_info[rdev->pm.requested_clock_mode_index].mclk, rdev
->pm.power_state[rdev->pm.requested_power_state_index].
 pcie_lanes);
303}

305/**
* r100_pm_init_profile - Initialize power profiles callback.
*
* @rdev: radeon_device pointer
*
* Initialize the power states used in profile mode
* (r1xx-r3xx).
* Used for profile mode only.
*/
314void r100_pm_init_profile(struct radeon_device *rdev)
315{
/* default */
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX0].dpms_on_cm_idx = 0;
/* low sh */
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX1].dpms_on_cm_idx = 0;
/* mid sh */
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_SH_IDX2].dpms_on_cm_idx = 0;
/* high sh */
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX3].dpms_on_cm_idx = 0;
/* low mh */
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX4].dpms_on_cm_idx = 0;
/* mid mh */
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_MID_MH_IDX5].dpms_on_cm_idx = 0;
/* high mh */
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_ps_idx = 0;
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_ps_idx = rdev->pm.default_power_state_index;
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_off_cm_idx = 0;
rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX6].dpms_on_cm_idx = 0;
351}

353/**
* r100_pm_misc - set additional pm hw parameters callback.
*
* @rdev: radeon_device pointer
*
* Set non-clock parameters associated with a power state
* (voltage, pcie lanes, etc.) (r1xx-r4xx).
*/
361void r100_pm_misc(struct radeon_device *rdev)
362{
int requested_index = rdev->pm.requested_power_state_index;
struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;

if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT0x00000004L) {
	tmp = RREG32(voltage->gpio.reg)r100_mm_rreg(rdev, (voltage->gpio.reg), 0);
	if (voltage->active_high)
		tmp |= voltage->gpio.mask;
	else
		tmp &= ~(voltage->gpio.mask);
	WREG32(voltage->gpio.reg, tmp)r100_mm_wreg(rdev, (voltage->gpio.reg), (tmp), 0);
	if (voltage->delay)
		udelay(voltage->delay);
} else {
	tmp = RREG32(voltage->gpio.reg)r100_mm_rreg(rdev, (voltage->gpio.reg), 0);
	if (voltage->active_high)
		tmp &= ~voltage->gpio.mask;
	else
		tmp |= voltage->gpio.mask;
	WREG32(voltage->gpio.reg, tmp)r100_mm_wreg(rdev, (voltage->gpio.reg), (tmp), 0);
	if (voltage->delay)
		udelay(voltage->delay);
}
}

sclk_cntl = RREG32_PLL(SCLK_CNTL)rdev->pll_rreg(rdev, (0xd));
sclk_cntl2 = RREG32_PLL(SCLK_CNTL2)rdev->pll_rreg(rdev, (0x1e));
sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3)((3) << 17);
sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL)rdev->pll_rreg(rdev, (0x35));
sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3)((3) << 20);
if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN0x00000100L) {
sclk_more_cntl |= REDUCED_SPEED_SCLK_EN(1 << 16);
if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE0x00400000L)
	sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE(1 << 16);
else
	sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE(1 << 16);
if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_20x00800000L)
	sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0)((0) << 17);
else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_40x01000000L)
	sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2)((2) << 17);
} else
sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN(1 << 16);

if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN0x00000200L) {
sclk_more_cntl |= IO_CG_VOLTAGE_DROP(1 << 17);
if (voltage->delay) {
	sclk_more_cntl |= VOLTAGE_DROP_SYNC(1 << 19);
	switch (voltage->delay) {
	case 33:
		sclk_more_cntl |= VOLTAGE_DELAY_SEL(0)((0) << 20);
		break;
	case 66:
		sclk_more_cntl |= VOLTAGE_DELAY_SEL(1)((1) << 20);
		break;
	case 99:
		sclk_more_cntl |= VOLTAGE_DELAY_SEL(2)((2) << 20);
		break;
	case 132:
		sclk_more_cntl |= VOLTAGE_DELAY_SEL(3)((3) << 20);
		break;
	}
} else
	sclk_more_cntl &= ~VOLTAGE_DROP_SYNC(1 << 19);
} else
sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP(1 << 17);

if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN0x02000000L)
sclk_cntl &= ~FORCE_HDP(1 << 17);
else
sclk_cntl |= FORCE_HDP(1 << 17);

WREG32_PLL(SCLK_CNTL, sclk_cntl)rdev->pll_wreg(rdev, (0xd), (sclk_cntl));
WREG32_PLL(SCLK_CNTL2, sclk_cntl2)rdev->pll_wreg(rdev, (0x1e), (sclk_cntl2));
WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl)rdev->pll_wreg(rdev, (0x35), (sclk_more_cntl));

/* set pcie lanes */
if ((rdev->flags & RADEON_IS_PCIE) &&
   !(rdev->flags & RADEON_IS_IGP) &&
   rdev->asic->pm.set_pcie_lanes &&
   (ps->pcie_lanes !=
    rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
radeon_set_pcie_lanes(rdev,(rdev)->asic->pm.set_pcie_lanes((rdev), (ps->pcie_lanes
))
		      ps->pcie_lanes)(rdev)->asic->pm.set_pcie_lanes((rdev), (ps->pcie_lanes
));
DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes)___drm_dbg(((void *)0), DRM_UT_DRIVER, "Setting: p: %d\n", ps
->pcie_lanes);
}
450}

452/**
* r100_pm_prepare - pre-power state change callback.
*
* @rdev: radeon_device pointer
*
* Prepare for a power state change (r1xx-r4xx).
*/
459void r100_pm_prepare(struct radeon_device *rdev)
460{
struct drm_device *ddev = rdev->ddev;
struct drm_crtc *crtc;
struct radeon_crtc *radeon_crtc;
u32 tmp;

/* disable any active CRTCs */
list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&ddev->mode_config.crtc_list)->next)
; (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&ddev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );});
if (radeon_crtc->enabled) {
	if (radeon_crtc->crtc_id) {
		tmp = RREG32(RADEON_CRTC2_GEN_CNTL)r100_mm_rreg(rdev, (0x03f8), 0);
		tmp |= RADEON_CRTC2_DISP_REQ_EN_B(1 << 26);
		WREG32(RADEON_CRTC2_GEN_CNTL, tmp)r100_mm_wreg(rdev, (0x03f8), (tmp), 0);
	} else {
		tmp = RREG32(RADEON_CRTC_GEN_CNTL)r100_mm_rreg(rdev, (0x0050), 0);
		tmp |= RADEON_CRTC_DISP_REQ_EN_B(1 << 26);
		WREG32(RADEON_CRTC_GEN_CNTL, tmp)r100_mm_wreg(rdev, (0x0050), (tmp), 0);
	}
}
}
481}

483/**
* r100_pm_finish - post-power state change callback.
*
* @rdev: radeon_device pointer
*
* Clean up after a power state change (r1xx-r4xx).
*/
490void r100_pm_finish(struct radeon_device *rdev)
491{
struct drm_device *ddev = rdev->ddev;
struct drm_crtc *crtc;
struct radeon_crtc *radeon_crtc;
u32 tmp;

/* enable any active CRTCs */
list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head)for (crtc = ({ const __typeof( ((__typeof(*crtc) *)0)->head
 ) *__mptr = ((&ddev->mode_config.crtc_list)->next)
; (__typeof(*crtc) *)( (char *)__mptr - __builtin_offsetof(__typeof
(*crtc), head) );}); &crtc->head != (&ddev->mode_config
.crtc_list); crtc = ({ const __typeof( ((__typeof(*crtc) *)0)
->head ) *__mptr = (crtc->head.next); (__typeof(*crtc) *
)( (char *)__mptr - __builtin_offsetof(__typeof(*crtc), head)
 );})) {
radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );});
if (radeon_crtc->enabled) {
	if (radeon_crtc->crtc_id) {
		tmp = RREG32(RADEON_CRTC2_GEN_CNTL)r100_mm_rreg(rdev, (0x03f8), 0);
		tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B(1 << 26);
		WREG32(RADEON_CRTC2_GEN_CNTL, tmp)r100_mm_wreg(rdev, (0x03f8), (tmp), 0);
	} else {
		tmp = RREG32(RADEON_CRTC_GEN_CNTL)r100_mm_rreg(rdev, (0x0050), 0);
		tmp &= ~RADEON_CRTC_DISP_REQ_EN_B(1 << 26);
		WREG32(RADEON_CRTC_GEN_CNTL, tmp)r100_mm_wreg(rdev, (0x0050), (tmp), 0);
	}
}
}
512}

514/**
* r100_gui_idle - gui idle callback.
*
* @rdev: radeon_device pointer
*
* Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
* Returns true if idle, false if not.
*/
522bool_Bool r100_gui_idle(struct radeon_device *rdev)
523{
if (RREG32(RADEON_RBBM_STATUS)r100_mm_rreg(rdev, (0x0e40), 0) & RADEON_RBBM_ACTIVE(1 << 31))
return false0;
else
return true1;
528}

530/* hpd for digital panel detect/disconnect */
531/**
* r100_hpd_sense - hpd sense callback.
*
* @rdev: radeon_device pointer
* @hpd: hpd (hotplug detect) pin
*
* Checks if a digital monitor is connected (r1xx-r4xx).
* Returns true if connected, false if not connected.
*/
540bool_Bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
541{
bool_Bool connected = false0;

switch (hpd) {
case RADEON_HPD_1:
if (RREG32(RADEON_FP_GEN_CNTL)r100_mm_rreg(rdev, (0x0284), 0) & RADEON_FP_DETECT_SENSE(1 << 8))
	connected = true1;
break;
case RADEON_HPD_2:
if (RREG32(RADEON_FP2_GEN_CNTL)r100_mm_rreg(rdev, (0x0288), 0) & RADEON_FP2_DETECT_SENSE(1 << 8))
	connected = true1;
break;
default:
break;
}
return connected;
557}

559/**
* r100_hpd_set_polarity - hpd set polarity callback.
*
* @rdev: radeon_device pointer
* @hpd: hpd (hotplug detect) pin
*
* Set the polarity of the hpd pin (r1xx-r4xx).
*/
567void r100_hpd_set_polarity(struct radeon_device *rdev,
	   enum radeon_hpd_id hpd)
569{
u32 tmp;
bool_Bool connected = r100_hpd_sense(rdev, hpd);

switch (hpd) {
case RADEON_HPD_1:
tmp = RREG32(RADEON_FP_GEN_CNTL)r100_mm_rreg(rdev, (0x0284), 0);
if (connected)
	tmp &= ~RADEON_FP_DETECT_INT_POL(1 << 9);
else
	tmp |= RADEON_FP_DETECT_INT_POL(1 << 9);
WREG32(RADEON_FP_GEN_CNTL, tmp)r100_mm_wreg(rdev, (0x0284), (tmp), 0);
break;
case RADEON_HPD_2:
tmp = RREG32(RADEON_FP2_GEN_CNTL)r100_mm_rreg(rdev, (0x0288), 0);
if (connected)
	tmp &= ~RADEON_FP2_DETECT_INT_POL(1 << 9);
else
	tmp |= RADEON_FP2_DETECT_INT_POL(1 << 9);
WREG32(RADEON_FP2_GEN_CNTL, tmp)r100_mm_wreg(rdev, (0x0288), (tmp), 0);
break;
default:
break;
}
593}

595/**
* r100_hpd_init - hpd setup callback.
*
* @rdev: radeon_device pointer
*
* Setup the hpd pins used by the card (r1xx-r4xx).
* Set the polarity, and enable the hpd interrupts.
*/
603void r100_hpd_init(struct radeon_device *rdev)
604{
struct drm_device *dev = rdev->ddev;
struct drm_connector *connector;
unsigned enable = 0;

list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );})) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
	enable |= 1 << radeon_connector->hpd.hpd;
radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd)(rdev)->asic->hpd.set_polarity((rdev), (radeon_connector
->hpd.hpd));
}
radeon_irq_kms_enable_hpd(rdev, enable);
616}

618/**
* r100_hpd_fini - hpd tear down callback.
*
* @rdev: radeon_device pointer
*
* Tear down the hpd pins used by the card (r1xx-r4xx).
* Disable the hpd interrupts.
*/
626void r100_hpd_fini(struct radeon_device *rdev)
627{
struct drm_device *dev = rdev->ddev;
struct drm_connector *connector;
unsigned disable = 0;

list_for_each_entry(connector, &dev->mode_config.connector_list, head)for (connector = ({ const __typeof( ((__typeof(*connector) *)
0)->head ) *__mptr = ((&dev->mode_config.connector_list
)->next); (__typeof(*connector) *)( (char *)__mptr - __builtin_offsetof
(__typeof(*connector), head) );}); &connector->head !=
 (&dev->mode_config.connector_list); connector = ({ const
 __typeof( ((__typeof(*connector) *)0)->head ) *__mptr = (
connector->head.next); (__typeof(*connector) *)( (char *)__mptr
 - __builtin_offsetof(__typeof(*connector), head) );})) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector)({ const __typeof( ((struct radeon_connector *)0)->base ) *
__mptr = (connector); (struct radeon_connector *)( (char *)__mptr
 - __builtin_offsetof(struct radeon_connector, base) );});
if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
	disable |= 1 << radeon_connector->hpd.hpd;
}
radeon_irq_kms_disable_hpd(rdev, disable);
638}

640/*
* PCI GART
*/
643void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
644{
/* TODO: can we do somethings here ? */
/* It seems hw only cache one entry so we should discard this
* entry otherwise if first GPU GART read hit this entry it
* could end up in wrong address. */
649}

651int r100_pci_gart_init(struct radeon_device *rdev)
652{
int r;

if (rdev->gart.ptr) {
WARN(1, "R100 PCI GART already initialized\n")({ int __ret = !!(1); if (__ret) printf("R100 PCI GART already initialized\n"
); __builtin_expect(!!(__ret), 0); });
return 0;
}
/* Initialize common gart structure */
r = radeon_gart_init(rdev);
if (r)
return r;
rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
rdev->asic->gart.set_page = &r100_pci_gart_set_page;
return radeon_gart_table_ram_alloc(rdev);
668}

670int r100_pci_gart_enable(struct radeon_device *rdev)
671{
uint32_t tmp;

/* discard memory request outside of configured range */
tmp = RREG32(RADEON_AIC_CNTL)r100_mm_rreg(rdev, (0x01d0), 0) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS(1 << 1);
WREG32(RADEON_AIC_CNTL, tmp)r100_mm_wreg(rdev, (0x01d0), (tmp), 0);
/* set address range for PCI address translate */
WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start)r100_mm_wreg(rdev, (0x01dc), (rdev->mc.gtt_start), 0);
WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end)r100_mm_wreg(rdev, (0x01e0), (rdev->mc.gtt_end), 0);
/* set PCI GART page-table base address */
WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr)r100_mm_wreg(rdev, (0x01d8), (rdev->gart.table_addr), 0);
tmp = RREG32(RADEON_AIC_CNTL)r100_mm_rreg(rdev, (0x01d0), 0) | RADEON_PCIGART_TRANSLATE_EN(1 << 0);
WREG32(RADEON_AIC_CNTL, tmp)r100_mm_wreg(rdev, (0x01d0), (tmp), 0);
r100_pci_gart_tlb_flush(rdev);
DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",printk("\0016" "[" "drm" "] " "PCI GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
 long)rdev->gart.table_addr)
 (unsigned)(rdev->mc.gtt_size >> 20),printk("\0016" "[" "drm" "] " "PCI GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
 long)rdev->gart.table_addr)
 (unsigned long long)rdev->gart.table_addr)printk("\0016" "[" "drm" "] " "PCI GART of %uM enabled (table at 0x%016llX).\n"
, (unsigned)(rdev->mc.gtt_size >> 20), (unsigned long
 long)rdev->gart.table_addr);
rdev->gart.ready = true1;
return 0;
690}

692void r100_pci_gart_disable(struct radeon_device *rdev)
693{
uint32_t tmp;

/* discard memory request outside of configured range */
tmp = RREG32(RADEON_AIC_CNTL)r100_mm_rreg(rdev, (0x01d0), 0) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS(1 << 1);
WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN)r100_mm_wreg(rdev, (0x01d0), (tmp & ~(1 << 0)), 0);
WREG32(RADEON_AIC_LO_ADDR, 0)r100_mm_wreg(rdev, (0x01dc), (0), 0);
WREG32(RADEON_AIC_HI_ADDR, 0)r100_mm_wreg(rdev, (0x01e0), (0), 0);
701}

703uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags)
704{
return addr;
706}

708void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
	    uint64_t entry)
710{
u32 *gtt = rdev->gart.ptr;
gtt[i] = cpu_to_le32(lower_32_bits(entry))((__uint32_t)(((u32)(entry))));
713}

715void r100_pci_gart_fini(struct radeon_device *rdev)
716{
radeon_gart_fini(rdev);
r100_pci_gart_disable(rdev);
radeon_gart_table_ram_free(rdev);
720}

722int r100_irq_set(struct radeon_device *rdev)
723{
uint32_t tmp = 0;

if (!rdev->irq.installed) {
WARN(1, "Can't enable IRQ/MSI because no handler is installed\n")({ int __ret = !!(1); if (__ret) printf("Can't enable IRQ/MSI because no handler is installed\n"
); __builtin_expect(!!(__ret), 0); });
WREG32(R_000040_GEN_INT_CNTL, 0)r100_mm_wreg(rdev, (0x000040), (0), 0);
return -EINVAL22;
}
if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])({ typeof(*(&rdev->irq.ring_int[0])) __tmp = *(volatile
 typeof(*(&rdev->irq.ring_int[0])) *)&(*(&rdev
->irq.ring_int[0])); membar_datadep_consumer(); __tmp; })) {
tmp |= RADEON_SW_INT_ENABLE(1 << 25);
}
if (rdev->irq.crtc_vblank_int[0] ||
   atomic_read(&rdev->irq.pflip[0])({ typeof(*(&rdev->irq.pflip[0])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[0])) *)&(*(&rdev->irq.pflip
[0])); membar_datadep_consumer(); __tmp; })) {
tmp |= RADEON_CRTC_VBLANK_MASK(1 << 0);
}
if (rdev->irq.crtc_vblank_int[1] ||
   atomic_read(&rdev->irq.pflip[1])({ typeof(*(&rdev->irq.pflip[1])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[1])) *)&(*(&rdev->irq.pflip
[1])); membar_datadep_consumer(); __tmp; })) {
tmp |= RADEON_CRTC2_VBLANK_MASK(1 << 9);
}
if (rdev->irq.hpd[0]) {
tmp |= RADEON_FP_DETECT_MASK(1 << 4);
}
if (rdev->irq.hpd[1]) {
tmp |= RADEON_FP2_DETECT_MASK(1 << 10);
}
WREG32(RADEON_GEN_INT_CNTL, tmp)r100_mm_wreg(rdev, (0x0040), (tmp), 0);

/* read back to post the write */
RREG32(RADEON_GEN_INT_CNTL)r100_mm_rreg(rdev, (0x0040), 0);

return 0;
754}

756void r100_irq_disable(struct radeon_device *rdev)
757{
u32 tmp;

WREG32(R_000040_GEN_INT_CNTL, 0)r100_mm_wreg(rdev, (0x000040), (0), 0);
/* Wait and acknowledge irq */
mdelay(1);
tmp = RREG32(R_000044_GEN_INT_STATUS)r100_mm_rreg(rdev, (0x000044), 0);
WREG32(R_000044_GEN_INT_STATUS, tmp)r100_mm_wreg(rdev, (0x000044), (tmp), 0);
765}

767static uint32_t r100_irq_ack(struct radeon_device *rdev)
768{
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS)r100_mm_rreg(rdev, (0x0044), 0);
uint32_t irq_mask = RADEON_SW_INT_TEST(1 << 25) |
RADEON_CRTC_VBLANK_STAT(1 << 0) | RADEON_CRTC2_VBLANK_STAT(1 << 9) |
RADEON_FP_DETECT_STAT(1 << 4) | RADEON_FP2_DETECT_STAT(1 << 10);

if (irqs) {
WREG32(RADEON_GEN_INT_STATUS, irqs)r100_mm_wreg(rdev, (0x0044), (irqs), 0);
}
return irqs & irq_mask;
778}

780int r100_irq_process(struct radeon_device *rdev)
781{
uint32_t status, msi_rearm;
bool_Bool queue_hotplug = false0;

status = r100_irq_ack(rdev);
if (!status) {
return IRQ_NONE;
}
if (rdev->shutdown) {
return IRQ_NONE;
}
while (status) {
/* SW interrupt */
if (status & RADEON_SW_INT_TEST(1 << 25)) {
	radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX0);
}
/* Vertical blank interrupts */
if (status & RADEON_CRTC_VBLANK_STAT(1 << 0)) {
	if (rdev->irq.crtc_vblank_int[0]) {
		drm_handle_vblank(rdev->ddev, 0);
		rdev->pm.vblank_sync = true1;
		wake_up(&rdev->irq.vblank_queue);
	}
	if (atomic_read(&rdev->irq.pflip[0])({ typeof(*(&rdev->irq.pflip[0])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[0])) *)&(*(&rdev->irq.pflip
[0])); membar_datadep_consumer(); __tmp; }))
		radeon_crtc_handle_vblank(rdev, 0);
}
if (status & RADEON_CRTC2_VBLANK_STAT(1 << 9)) {
	if (rdev->irq.crtc_vblank_int[1]) {
		drm_handle_vblank(rdev->ddev, 1);
		rdev->pm.vblank_sync = true1;
		wake_up(&rdev->irq.vblank_queue);
	}
	if (atomic_read(&rdev->irq.pflip[1])({ typeof(*(&rdev->irq.pflip[1])) __tmp = *(volatile typeof
(*(&rdev->irq.pflip[1])) *)&(*(&rdev->irq.pflip
[1])); membar_datadep_consumer(); __tmp; }))
		radeon_crtc_handle_vblank(rdev, 1);
}
if (status & RADEON_FP_DETECT_STAT(1 << 4)) {
	queue_hotplug = true1;
	DRM_DEBUG("HPD1\n")___drm_dbg(((void *)0), DRM_UT_CORE, "HPD1\n");
}
if (status & RADEON_FP2_DETECT_STAT(1 << 10)) {
	queue_hotplug = true1;
	DRM_DEBUG("HPD2\n")___drm_dbg(((void *)0), DRM_UT_CORE, "HPD2\n");
}
status = r100_irq_ack(rdev);
}
if (queue_hotplug)
schedule_delayed_work(&rdev->hotplug_work, 0);
if (rdev->msi_enabled) {
switch (rdev->family) {
case CHIP_RS400:
case CHIP_RS480:
	msi_rearm = RREG32(RADEON_AIC_CNTL)r100_mm_rreg(rdev, (0x01d0), 0) & ~RS400_MSI_REARM(1 << 3);
	WREG32(RADEON_AIC_CNTL, msi_rearm)r100_mm_wreg(rdev, (0x01d0), (msi_rearm), 0);
	WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM)r100_mm_wreg(rdev, (0x01d0), (msi_rearm | (1 << 3)), 0);
	break;
default:
	WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN)r100_mm_wreg(rdev, (0x0160), ((1 << 0)), 0);
	break;
}
}
return IRQ_HANDLED;
842}

844u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
845{
if (crtc == 0)
return RREG32(RADEON_CRTC_CRNT_FRAME)r100_mm_rreg(rdev, (0x0214), 0);
else
return RREG32(RADEON_CRTC2_CRNT_FRAME)r100_mm_rreg(rdev, (0x0314), 0);
850}

852/**
* r100_ring_hdp_flush - flush Host Data Path via the ring buffer
* @rdev: radeon device structure
* @ring: ring buffer struct for emitting packets
*/
857static void r100_ring_hdp_flush(struct radeon_device *rdev, struct radeon_ring *ring)
858{
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)(0x00000000 | ((((0x0130) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
		RADEON_HDP_READ_BUFFER_INVALIDATE(1 << 27));
radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0)(0x00000000 | ((((0x0130) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
864}

866/* Who ever call radeon_fence_emit should call ring_lock and ask
* for enough space (today caller are ib schedule and buffer move) */
868void r100_fence_ring_emit(struct radeon_device *rdev,
	  struct radeon_fence *fence)
870{
struct radeon_ring *ring = &rdev->ring[fence->ring];

/* We have to make sure that caches are flushed before
* CPU might read something from VRAM. */
radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)(0x00000000 | ((((0x325C) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL0xf);
radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)(0x00000000 | ((((0x3254) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL0x5);
/* Wait until IDLE & CLEAN */
radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)(0x00000000 | ((((0x1720) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN(1 << 16) | RADEON_WAIT_3D_IDLECLEAN(1 << 17));
r100_ring_hdp_flush(rdev, ring);
/* Emit fence sequence & fire IRQ */
radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)(0x00000000 | ((((rdev->fence_drv[fence->ring].scratch_reg
) >> 2) << 0) & (0x1ffff << 0)) | ((((0
)) << 16) & (0x3fff << 16))));
radeon_ring_write(ring, fence->seq);
radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0)(0x00000000 | ((((0x0044) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, RADEON_SW_INT_FIRE(1 << 26));
888}

890bool_Bool r100_semaphore_ring_emit(struct radeon_device *rdev,
	      struct radeon_ring *ring,
	      struct radeon_semaphore *semaphore,
	      bool_Bool emit_wait)
894{
/* Unused on older asics, since we don't have semaphores or multiple rings */
BUG()do { panic("BUG at %s:%d", "/usr/src/sys/dev/pci/drm/radeon/r100.c"
, 896); } while (0);
return false0;
898}

900struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
		    uint64_t src_offset,
		    uint64_t dst_offset,
		    unsigned num_gpu_pages,
		    struct dma_resv *resv)
905{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
struct radeon_fence *fence;
uint32_t cur_pages;
uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE4096;
uint32_t pitch;
uint32_t stride_pixels;
unsigned ndw;
int num_loops;
int r = 0;

/* radeon limited to 16k stride */
stride_bytes &= 0x3fff;
/* radeon pitch is /64 */
pitch = stride_bytes / 64;
stride_pixels = stride_bytes / 4;
num_loops = DIV_ROUND_UP(num_gpu_pages, 8191)(((num_gpu_pages) + ((8191) - 1)) / (8191));

/* Ask for enough room for blit + flush + fence */
ndw = 64 + (10 * num_loops);
r = radeon_ring_lock(rdev, ring, ndw);
if (r) {
DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw)__drm_err("radeon: moving bo (%d) asking for %u dw.\n", r, ndw
);
return ERR_PTR(-EINVAL22);
}
while (num_gpu_pages > 0) {
cur_pages = num_gpu_pages;
if (cur_pages > 8191) {
	cur_pages = 8191;
}
num_gpu_pages -= cur_pages;

/* pages are in Y direction - height
   page width in X direction - width */
radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)(0xC0000000 | ((((0x9B)) << 8) & (0xff << 8))
 | ((((8)) << 16) & (0x3fff << 16))));
radeon_ring_write(ring,
		  RADEON_GMC_SRC_PITCH_OFFSET_CNTL(1 << 0) |
		  RADEON_GMC_DST_PITCH_OFFSET_CNTL(1 << 1) |
		  RADEON_GMC_SRC_CLIPPING(1 << 2) |
		  RADEON_GMC_DST_CLIPPING(1 << 3) |
		  RADEON_GMC_BRUSH_NONE(15 << 4) |
		  (RADEON_COLOR_FORMAT_ARGB88886 << 8) |
		  RADEON_GMC_SRC_DATATYPE_COLOR(3 << 12) |
		  RADEON_ROP3_S0x00cc0000 |
		  RADEON_DP_SRC_SOURCE_MEMORY(2 << 24) |
		  RADEON_GMC_CLR_CMP_CNTL_DIS(1 << 28) |
		  RADEON_GMC_WR_MSK_DIS(1 << 30));
radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
radeon_ring_write(ring, 0);
radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
radeon_ring_write(ring, num_gpu_pages);
radeon_ring_write(ring, num_gpu_pages);
radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
}
radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)(0x00000000 | ((((0x1714) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL0xf);
radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0)(0x00000000 | ((((0x1720) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring,
	  RADEON_WAIT_2D_IDLECLEAN(1 << 16) |
	  RADEON_WAIT_HOST_IDLECLEAN(1 << 18) |
	  RADEON_WAIT_DMA_GUI_IDLE(1 << 9));
r = radeon_fence_emit(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX0);
if (r) {
radeon_ring_unlock_undo(rdev, ring);
return ERR_PTR(r);
}
radeon_ring_unlock_commit(rdev, ring, false0);
return fence;
975}

977static int r100_cp_wait_for_idle(struct radeon_device *rdev)
978{
unsigned i;
u32 tmp;

for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
if (!G_000E40_CP_CMDSTRM_BUSY(tmp)(((tmp) >> 16) & 0x1)) {
	return 0;
}
udelay(1);
}
return -1;
990}

992void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
993{
int r;

r = radeon_ring_lock(rdev, ring, 2);
if (r) {
return;
}
radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0)(0x00000000 | ((((0x1724) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring,
	  RADEON_ISYNC_ANY2D_IDLE3D(1 << 0) |
	  RADEON_ISYNC_ANY3D_IDLE2D(1 << 1) |
	  RADEON_ISYNC_WAIT_IDLEGUI(1 << 4) |
	  RADEON_ISYNC_CPSCRATCH_IDLEGUI(1 << 5));
radeon_ring_unlock_commit(rdev, ring, false0);
1007}


1010/* Load the microcode for the CP */
1011static int r100_cp_init_microcode(struct radeon_device *rdev)
1012{
const char *fw_name = NULL((void *)0);
int err;

DRM_DEBUG_KMS("\n")___drm_dbg(((void *)0), DRM_UT_KMS, "\n");

if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
   (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
   (rdev->family == CHIP_RS200)) {
DRM_INFO("Loading R100 Microcode\n")printk("\0016" "[" "drm" "] " "Loading R100 Microcode\n");
fw_name = FIRMWARE_R100"radeon/R100_cp.bin";
} else if ((rdev->family == CHIP_R200) ||
   (rdev->family == CHIP_RV250) ||
   (rdev->family == CHIP_RV280) ||
   (rdev->family == CHIP_RS300)) {
DRM_INFO("Loading R200 Microcode\n")printk("\0016" "[" "drm" "] " "Loading R200 Microcode\n");
fw_name = FIRMWARE_R200"radeon/R200_cp.bin";
} else if ((rdev->family == CHIP_R300) ||
   (rdev->family == CHIP_R350) ||
   (rdev->family == CHIP_RV350) ||
   (rdev->family == CHIP_RV380) ||
   (rdev->family == CHIP_RS400) ||
   (rdev->family == CHIP_RS480)) {
DRM_INFO("Loading R300 Microcode\n")printk("\0016" "[" "drm" "] " "Loading R300 Microcode\n");
fw_name = FIRMWARE_R300"radeon/R300_cp.bin";
} else if ((rdev->family == CHIP_R420) ||
   (rdev->family == CHIP_R423) ||
   (rdev->family == CHIP_RV410)) {
DRM_INFO("Loading R400 Microcode\n")printk("\0016" "[" "drm" "] " "Loading R400 Microcode\n");
fw_name = FIRMWARE_R420"radeon/R420_cp.bin";
} else if ((rdev->family == CHIP_RS690) ||
   (rdev->family == CHIP_RS740)) {
DRM_INFO("Loading RS690/RS740 Microcode\n")printk("\0016" "[" "drm" "] " "Loading RS690/RS740 Microcode\n"
);
fw_name = FIRMWARE_RS690"radeon/RS690_cp.bin";
} else if (rdev->family == CHIP_RS600) {
DRM_INFO("Loading RS600 Microcode\n")printk("\0016" "[" "drm" "] " "Loading RS600 Microcode\n");
fw_name = FIRMWARE_RS600"radeon/RS600_cp.bin";
} else if ((rdev->family == CHIP_RV515) ||
   (rdev->family == CHIP_R520) ||
   (rdev->family == CHIP_RV530) ||
   (rdev->family == CHIP_R580) ||
   (rdev->family == CHIP_RV560) ||
   (rdev->family == CHIP_RV570)) {
DRM_INFO("Loading R500 Microcode\n")printk("\0016" "[" "drm" "] " "Loading R500 Microcode\n");
fw_name = FIRMWARE_R520"radeon/R520_cp.bin";
}

err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
if (err) {
pr_err("radeon_cp: Failed to load firmware \"%s\"\n", fw_name)printk("\0013" "radeon_cp: Failed to load firmware \"%s\"\n",
 fw_name);
} else if (rdev->me_fw->size % 8) {
pr_err("radeon_cp: Bogus length %zu in firmware \"%s\"\n",printk("\0013" "radeon_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->me_fw->size, fw_name)
       rdev->me_fw->size, fw_name)printk("\0013" "radeon_cp: Bogus length %zu in firmware \"%s\"\n"
, rdev->me_fw->size, fw_name);
err = -EINVAL22;
release_firmware(rdev->me_fw);
rdev->me_fw = NULL((void *)0);
}
return err;
1070}

1072u32 r100_gfx_get_rptr(struct radeon_device *rdev,
      struct radeon_ring *ring)
1074{
u32 rptr;

if (rdev->wb.enabled)
rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4])((__uint32_t)(rdev->wb.wb[ring->rptr_offs/4]));
else
rptr = RREG32(RADEON_CP_RB_RPTR)r100_mm_rreg(rdev, (0x0710), 0);

return rptr;
1083}

1085u32 r100_gfx_get_wptr(struct radeon_device *rdev,
      struct radeon_ring *ring)
1087{
return RREG32(RADEON_CP_RB_WPTR)r100_mm_rreg(rdev, (0x0714), 0);
1089}

1091void r100_gfx_set_wptr(struct radeon_device *rdev,
       struct radeon_ring *ring)
1093{
WREG32(RADEON_CP_RB_WPTR, ring->wptr)r100_mm_wreg(rdev, (0x0714), (ring->wptr), 0);
(void)RREG32(RADEON_CP_RB_WPTR)r100_mm_rreg(rdev, (0x0714), 0);
1096}

1098static void r100_cp_load_microcode(struct radeon_device *rdev)
1099{
const __be32 *fw_data;
int i, size;

if (r100_gui_wait_for_idle(rdev)) {
pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while programming pipes. Bad things might happen.\n"
);
}

if (rdev->me_fw) {
size = rdev->me_fw->size / 4;
fw_data = (const __be32 *)&rdev->me_fw->data[0];
WREG32(RADEON_CP_ME_RAM_ADDR, 0)r100_mm_wreg(rdev, (0x07d4), (0), 0);
for (i = 0; i < size; i += 2) {
	WREG32(RADEON_CP_ME_RAM_DATAH,r100_mm_wreg(rdev, (0x07dc), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(&fw_data[i])) ? (__uint32_t)(((__uint32_t
)(*(__uint32_t *)(&fw_data[i])) & 0xff) << 24 |
 ((__uint32_t)(*(__uint32_t *)(&fw_data[i])) & 0xff00
) << 8 | ((__uint32_t)(*(__uint32_t *)(&fw_data[i])
) & 0xff0000) >> 8 | ((__uint32_t)(*(__uint32_t *)(
&fw_data[i])) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(&fw_data[i])))), 0)
	       be32_to_cpup(&fw_data[i]))r100_mm_wreg(rdev, (0x07dc), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(&fw_data[i])) ? (__uint32_t)(((__uint32_t
)(*(__uint32_t *)(&fw_data[i])) & 0xff) << 24 |
 ((__uint32_t)(*(__uint32_t *)(&fw_data[i])) & 0xff00
) << 8 | ((__uint32_t)(*(__uint32_t *)(&fw_data[i])
) & 0xff0000) >> 8 | ((__uint32_t)(*(__uint32_t *)(
&fw_data[i])) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(&fw_data[i])))), 0);
	WREG32(RADEON_CP_ME_RAM_DATAL,r100_mm_wreg(rdev, (0x07e0), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(&fw_data[i + 1])) ? (__uint32_t)(((__uint32_t
)(*(__uint32_t *)(&fw_data[i + 1])) & 0xff) << 24
 | ((__uint32_t)(*(__uint32_t *)(&fw_data[i + 1])) & 0xff00
) << 8 | ((__uint32_t)(*(__uint32_t *)(&fw_data[i +
 1])) & 0xff0000) >> 8 | ((__uint32_t)(*(__uint32_t
 *)(&fw_data[i + 1])) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(&fw_data[i + 1])))), 0)
	       be32_to_cpup(&fw_data[i + 1]))r100_mm_wreg(rdev, (0x07e0), ((__uint32_t)(__builtin_constant_p
(*(__uint32_t *)(&fw_data[i + 1])) ? (__uint32_t)(((__uint32_t
)(*(__uint32_t *)(&fw_data[i + 1])) & 0xff) << 24
 | ((__uint32_t)(*(__uint32_t *)(&fw_data[i + 1])) & 0xff00
) << 8 | ((__uint32_t)(*(__uint32_t *)(&fw_data[i +
 1])) & 0xff0000) >> 8 | ((__uint32_t)(*(__uint32_t
 *)(&fw_data[i + 1])) & 0xff000000) >> 24) : __swap32md
(*(__uint32_t *)(&fw_data[i + 1])))), 0);
}
}
1118}

1120int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1121{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
unsigned rb_bufsz;
unsigned rb_blksz;
unsigned max_fetch;
unsigned pre_write_timer;
unsigned pre_write_limit;
unsigned indirect2_start;
unsigned indirect1_start;
uint32_t tmp;
int r;

r100_debugfs_cp_init(rdev);
if (!rdev->me_fw) {
r = r100_cp_init_microcode(rdev);
if (r) {
	DRM_ERROR("Failed to load firmware!\n")__drm_err("Failed to load firmware!\n");
	return r;
}
}

/* Align ring size */
rb_bufsz = order_base_2(ring_size / 8)drm_order(ring_size / 8);
ring_size = (1 << (rb_bufsz + 1)) * 4;
r100_cp_load_microcode(rdev);
r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET1024,
	     RADEON_CP_PACKET20x80000000);
if (r) {
return r;
}
/* Each time the cp read 1024 bytes (16 dword/quadword) update
* the rptr copy in system ram */
rb_blksz = 9;
/* cp will read 128bytes at a time (4 dwords) */
max_fetch = 1;
ring->align_mask = 16 - 1;
/* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
pre_write_timer = 64;
/* Force CP_RB_WPTR write if written more than one time before the
* delay expire
*/
pre_write_limit = 0;
/* Setup the cp cache like this (cache size is 96 dwords) :
*	RING		0  to 15
*	INDIRECT1	16 to 79
*	INDIRECT2	80 to 95
* So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
*    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
*    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
* Idea being that most of the gpu cmd will be through indirect1 buffer
* so it gets the bigger cache.
*/
indirect2_start = 80;
indirect1_start = 16;
/* cp setup */
WREG32(0x718, pre_write_timer | (pre_write_limit << 28))r100_mm_wreg(rdev, (0x718), (pre_write_timer | (pre_write_limit
 << 28)), 0);
tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz)(((rb_bufsz) << 0) & (0x3f << 0)) |
      REG_SET(RADEON_RB_BLKSZ, rb_blksz)(((rb_blksz) << 8) & (0x3f << 8)) |
      REG_SET(RADEON_MAX_FETCH, max_fetch)(((max_fetch) << 18) & (0x3 << 18)));
1180#ifdef __BIG_ENDIAN
tmp |= RADEON_BUF_SWAP_32BIT(2 << 16);
1182#endif
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE)r100_mm_wreg(rdev, (0x0704), (tmp | (1 << 27)), 0);

/* Set ring address */
DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr)printk("\0016" "[" "drm" "] " "radeon: ring at 0x%016lX\n", (
unsigned long)ring->gpu_addr);
WREG32(RADEON_CP_RB_BASE, ring->gpu_addr)r100_mm_wreg(rdev, (0x0700), (ring->gpu_addr), 0);
/* Force read & write ptr to 0 */
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE)r100_mm_wreg(rdev, (0x0704), (tmp | (1 << 31) | (1 <<
 27)), 0);
WREG32(RADEON_CP_RB_RPTR_WR, 0)r100_mm_wreg(rdev, (0x071c), (0), 0);
ring->wptr = 0;
WREG32(RADEON_CP_RB_WPTR, ring->wptr)r100_mm_wreg(rdev, (0x0714), (ring->wptr), 0);

/* set the wb address whether it's enabled or not */
WREG32(R_00070C_CP_RB_RPTR_ADDR,r100_mm_wreg(rdev, (0x00070C), (((((rdev->wb.gpu_addr + 1024
) >> 2) & 0x3FFFFFFF) << 2)), 0)
S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2))r100_mm_wreg(rdev, (0x00070C), (((((rdev->wb.gpu_addr + 1024
) >> 2) & 0x3FFFFFFF) << 2)), 0);
WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET)r100_mm_wreg(rdev, (0x000774), (rdev->wb.gpu_addr + 0), 0);

if (rdev->wb.enabled)
WREG32(R_000770_SCRATCH_UMSK, 0xff)r100_mm_wreg(rdev, (0x000770), (0xff), 0);
else {
tmp |= RADEON_RB_NO_UPDATE(1 << 27);
WREG32(R_000770_SCRATCH_UMSK, 0)r100_mm_wreg(rdev, (0x000770), (0), 0);
}

WREG32(RADEON_CP_RB_CNTL, tmp)r100_mm_wreg(rdev, (0x0704), (tmp), 0);
udelay(10);
/* Set cp mode to bus mastering & enable cp*/
WREG32(RADEON_CP_CSQ_MODE,r100_mm_wreg(rdev, (0x0744), ((((indirect2_start) << 0)
 & (0x7f << 0)) | (((indirect1_start) << 8) &
 (0x7f << 8))), 0)
      REG_SET(RADEON_INDIRECT2_START, indirect2_start) |r100_mm_wreg(rdev, (0x0744), ((((indirect2_start) << 0)
 & (0x7f << 0)) | (((indirect1_start) << 8) &
 (0x7f << 8))), 0)
      REG_SET(RADEON_INDIRECT1_START, indirect1_start))r100_mm_wreg(rdev, (0x0744), ((((indirect2_start) << 0)
 & (0x7f << 0)) | (((indirect1_start) << 8) &
 (0x7f << 8))), 0);
WREG32(RADEON_CP_RB_WPTR_DELAY, 0)r100_mm_wreg(rdev, (0x0718), (0), 0);
WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D)r100_mm_wreg(rdev, (0x0744), (0x00004D4D), 0);
WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM)r100_mm_wreg(rdev, (0x0740), ((4 << 28)), 0);

/* at this point everything should be setup correctly to enable master */
pci_set_master(rdev->pdev);

radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX])(rdev)->asic->ring[(0)]->ring_start((rdev), (&rdev
->ring[0]));
r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring)(rdev)->asic->ring[(0)]->ring_test((rdev), (ring));
if (r) {
DRM_ERROR("radeon: cp isn't working (%d).\n", r)__drm_err("radeon: cp isn't working (%d).\n", r);
return r;
}
ring->ready = true1;
radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);

if (!ring->rptr_save_reg /* not resuming from suspend */
   && radeon_ring_supports_scratch_reg(rdev, ring)) {
r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
if (r) {
	DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r)__drm_err("failed to get scratch reg for rptr save (%d).\n", r
);
	ring->rptr_save_reg = 0;
}
}
return 0;
1237}

1239void r100_cp_fini(struct radeon_device *rdev)
1240{
if (r100_cp_wait_for_idle(rdev)) {
DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n")__drm_err("Wait for CP idle timeout, shutting down CP.\n");
}
/* Disable ring */
r100_cp_disable(rdev);
radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].rptr_save_reg);
radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0]);
DRM_INFO("radeon: cp finalized\n")printk("\0016" "[" "drm" "] " "radeon: cp finalized\n");
1249}

1251void r100_cp_disable(struct radeon_device *rdev)
1252{
/* Disable ring */
radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ready = false0;
WREG32(RADEON_CP_CSQ_MODE, 0)r100_mm_wreg(rdev, (0x0744), (0), 0);
WREG32(RADEON_CP_CSQ_CNTL, 0)r100_mm_wreg(rdev, (0x0740), (0), 0);
WREG32(R_000770_SCRATCH_UMSK, 0)r100_mm_wreg(rdev, (0x000770), (0), 0);
if (r100_gui_wait_for_idle(rdev)) {
pr_warn("Failed to wait GUI idle while programming pipes. Bad things might happen.\n")printk("\0014" "Failed to wait GUI idle while programming pipes. Bad things might happen.\n"
);
}
1262}

1264/*
* CS functions
*/
1267int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
	    struct radeon_cs_packet *pkt,
	    unsigned idx,
	    unsigned reg)
1271{
int r;
u32 tile_flags = 0;
u32 tmp;
struct radeon_bo_list *reloc;
u32 value;

r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
	  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
radeon_cs_dump_packet(p, pkt);
return r;
}

value = radeon_get_ib_value(p, idx);
tmp = value & 0x003fffff;
tmp += (((u32)reloc->gpu_offset) >> 10);

if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS0x01)) {
if (reloc->tiling_flags & RADEON_TILING_MACRO0x1)
	tile_flags |= RADEON_DST_TILE_MACRO(1 << 30);
if (reloc->tiling_flags & RADEON_TILING_MICRO0x2) {
	if (reg == RADEON_SRC_PITCH_OFFSET0x1428) {
		DRM_ERROR("Cannot src blit from microtiled surface\n")__drm_err("Cannot src blit from microtiled surface\n");
		radeon_cs_dump_packet(p, pkt);
		return -EINVAL22;
	}
	tile_flags |= RADEON_DST_TILE_MICRO(2 << 30);
}

tmp |= tile_flags;
p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
} else
p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
return 0;
1307}

1309int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
	     struct radeon_cs_packet *pkt,
	     int idx)
1312{
unsigned c, i;
struct radeon_bo_list *reloc;
struct r100_cs_track *track;
int r = 0;
volatile uint32_t *ib;
u32 idx_value;

ib = p->ib.ptr;
track = (struct r100_cs_track *)p->track;
c = radeon_get_ib_value(p, idx++) & 0x1F;
if (c > 16) {
   DRM_ERROR("Only 16 vertex buffers are allowed %d\n",__drm_err("Only 16 vertex buffers are allowed %d\n", pkt->
opcode)
      pkt->opcode)__drm_err("Only 16 vertex buffers are allowed %d\n", pkt->
opcode);
   radeon_cs_dump_packet(p, pkt);
   return -EINVAL22;
}
track->num_arrays = c;
for (i = 0; i < (c - 1); i+=2, idx+=3) {
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for packet3 %d\n",__drm_err("No reloc for packet3 %d\n", pkt->opcode)
		  pkt->opcode)__drm_err("No reloc for packet3 %d\n", pkt->opcode);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
idx_value = radeon_get_ib_value(p, idx);
ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);

track->arrays[i + 0].esize = idx_value >> 8;
track->arrays[i + 0].robj = reloc->robj;
track->arrays[i + 0].esize &= 0x7F;
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for packet3 %d\n",__drm_err("No reloc for packet3 %d\n", pkt->opcode)
		  pkt->opcode)__drm_err("No reloc for packet3 %d\n", pkt->opcode);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
track->arrays[i + 1].robj = reloc->robj;
track->arrays[i + 1].esize = idx_value >> 24;
track->arrays[i + 1].esize &= 0x7F;
}
if (c & 1) {
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for packet3 %d\n",__drm_err("No reloc for packet3 %d\n", pkt->opcode)
			  pkt->opcode)__drm_err("No reloc for packet3 %d\n", pkt->opcode);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
idx_value = radeon_get_ib_value(p, idx);
ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
track->arrays[i + 0].robj = reloc->robj;
track->arrays[i + 0].esize = idx_value >> 8;
track->arrays[i + 0].esize &= 0x7F;
}
return r;
1371}

1373int r100_cs_parse_packet0(struct radeon_cs_parser *p,
	  struct radeon_cs_packet *pkt,
	  const unsigned *auth, unsigned n,
	  radeon_packet0_check_t check)
1377{
unsigned reg;
unsigned i, j, m;
unsigned idx;
int r;

idx = pkt->idx + 1;
reg = pkt->reg;
/* Check that register fall into register range
* determined by the number of entry (n) in the
* safe register bitmap.
*/
if (pkt->one_reg_wr) {
if ((reg >> 7) > n) {
	return -EINVAL22;
}
} else {
if (((reg + (pkt->count << 2)) >> 7) > n) {
	return -EINVAL22;
}
}
for (i = 0; i <= pkt->count; i++, idx++) {
j = (reg >> 7);
m = 1 << ((reg >> 2) & 31);
if (auth[j] & m) {
	r = check(p, pkt, idx, reg);
	if (r) {
		return r;
	}
}
if (pkt->one_reg_wr) {
	if (!(auth[j] & m)) {
		break;
	}
} else {
	reg += 4;
}
}
return 0;
1416}

1418/**
* r100_cs_packet_parse_vline() - parse userspace VLINE packet
* @p:		parser structure holding parsing context.
*
* Userspace sends a special sequence for VLINE waits.
* PACKET0 - VLINE_START_END + value
* PACKET0 - WAIT_UNTIL +_value
* RELOC (P3) - crtc_id in reloc.
*
* This function parses this and relocates the VLINE START END
* and WAIT UNTIL packets to the correct crtc.
* It also detects a switched off crtc and nulls out the
* wait in that case.
*/
1432int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1433{
struct drm_crtc *crtc;
struct radeon_crtc *radeon_crtc;
struct radeon_cs_packet p3reloc, waitreloc;
int crtc_id;
int r;
uint32_t header, h_idx, reg;
volatile uint32_t *ib;

ib = p->ib.ptr;

/* parse the wait until */
r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
if (r)
return r;

/* check its a wait until and only 1 count */
if (waitreloc.reg != RADEON_WAIT_UNTIL0x1720 ||
   waitreloc.count != 0) {
DRM_ERROR("vline wait had illegal wait until segment\n")__drm_err("vline wait had illegal wait until segment\n");
return -EINVAL22;
}

if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE(1 << 3)) {
DRM_ERROR("vline wait had illegal wait until\n")__drm_err("vline wait had illegal wait until\n");
return -EINVAL22;
}

/* jump over the NOP */
r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
if (r)
return r;

h_idx = p->idx - 2;
p->idx += waitreloc.count + 2;
p->idx += p3reloc.count + 2;

header = radeon_get_ib_value(p, h_idx);
crtc_id = radeon_get_ib_value(p, h_idx + 5);
reg = R100_CP_PACKET0_GET_REG(header)(((header) & 0x1FFF) << 2);
crtc = drm_crtc_find(p->rdev->ddev, p->filp, crtc_id);
if (!crtc) {
DRM_ERROR("cannot find crtc %d\n", crtc_id)__drm_err("cannot find crtc %d\n", crtc_id);
return -ENOENT2;
}
radeon_crtc = to_radeon_crtc(crtc)({ const __typeof( ((struct radeon_crtc *)0)->base ) *__mptr
 = (crtc); (struct radeon_crtc *)( (char *)__mptr - __builtin_offsetof
(struct radeon_crtc, base) );});
crtc_id = radeon_crtc->crtc_id;

if (!crtc->enabled) {
/* if the CRTC isn't enabled - we need to nop out the wait until */
ib[h_idx + 2] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib[h_idx + 3] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
} else if (crtc_id == 1) {
switch (reg) {
case AVIVO_D1MODE_VLINE_START_END0x6538:
	header &= ~R300_CP_PACKET0_REG_MASK0x00001fff;
	header |= AVIVO_D2MODE_VLINE_START_END0x6d38 >> 2;
	break;
case RADEON_CRTC_GUI_TRIG_VLINE0x0218:
	header &= ~R300_CP_PACKET0_REG_MASK0x00001fff;
	header |= RADEON_CRTC2_GUI_TRIG_VLINE0x0318 >> 2;
	break;
default:
	DRM_ERROR("unknown crtc reloc\n")__drm_err("unknown crtc reloc\n");
	return -EINVAL22;
}
ib[h_idx] = header;
ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1(1 << 31);
}

return 0;
1504}

1506static int r100_get_vtx_size(uint32_t vtx_fmt)
1507{
int vtx_size;
vtx_size = 2;
/* ordered according to bits in spec */
if (vtx_fmt & RADEON_SE_VTX_FMT_W00x00000001)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR0x00000002)
vtx_size += 3;
if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA0x00000004)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR0x00000008)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC0x00000010)
vtx_size += 3;
if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG0x00000020)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC0x00000040)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_ST00x00000080)
vtx_size += 2;
if (vtx_fmt & RADEON_SE_VTX_FMT_ST10x00000100)
vtx_size += 2;
if (vtx_fmt & RADEON_SE_VTX_FMT_Q10x00000200)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_ST20x00000400)
vtx_size += 2;
if (vtx_fmt & RADEON_SE_VTX_FMT_Q20x00000800)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_ST30x00001000)
vtx_size += 2;
if (vtx_fmt & RADEON_SE_VTX_FMT_Q30x00002000)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_Q00x00004000)
vtx_size++;
/* blend weight */
if (vtx_fmt & (0x7 << 15))
vtx_size += (vtx_fmt >> 15) & 0x7;
if (vtx_fmt & RADEON_SE_VTX_FMT_N00x00040000)
vtx_size += 3;
if (vtx_fmt & RADEON_SE_VTX_FMT_XY10x08000000)
vtx_size += 2;
if (vtx_fmt & RADEON_SE_VTX_FMT_Z10x10000000)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_W10x20000000)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_N10x40000000)
vtx_size++;
if (vtx_fmt & RADEON_SE_VTX_FMT_Z0x80000000)
vtx_size++;
return vtx_size;
1557}

1559static int r100_packet0_check(struct radeon_cs_parser *p,
	      struct radeon_cs_packet *pkt,
	      unsigned idx, unsigned reg)
1562{
struct radeon_bo_list *reloc;
struct r100_cs_track *track;
volatile uint32_t *ib;
uint32_t tmp;
int r;
int i, face;
u32 tile_flags = 0;
u32 idx_value;

ib = p->ib.ptr;
track = (struct r100_cs_track *)p->track;

idx_value = radeon_get_ib_value(p, idx);

switch (reg) {
case RADEON_CRTC_GUI_TRIG_VLINE0x0218:
r = r100_cs_packet_parse_vline(p);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
break;
/* FIXME: only allow PACKET3 blit? easier to check for out of
 * range access */
case RADEON_DST_PITCH_OFFSET0x142c:
case RADEON_SRC_PITCH_OFFSET0x1428:
r = r100_reloc_pitch_offset(p, pkt, idx, reg);
if (r)
	return r;
break;
case RADEON_RB3D_DEPTHOFFSET0x1c24:
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
track->zb.robj = reloc->robj;
track->zb.offset = idx_value;
track->zb_dirty = true1;
ib[idx] = idx_value + ((u32)reloc->gpu_offset);
break;
case RADEON_RB3D_COLOROFFSET0x1c40:
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
track->cb[0].robj = reloc->robj;
track->cb[0].offset = idx_value;
track->cb_dirty = true1;
ib[idx] = idx_value + ((u32)reloc->gpu_offset);
break;
case RADEON_PP_TXOFFSET_00x1c5c:
case RADEON_PP_TXOFFSET_10x1c74:
case RADEON_PP_TXOFFSET_20x1c8c:
i = (reg - RADEON_PP_TXOFFSET_00x1c5c) / 24;
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS0x01)) {
	if (reloc->tiling_flags & RADEON_TILING_MACRO0x1)
		tile_flags |= RADEON_TXO_MACRO_TILE(1 << 2);
	if (reloc->tiling_flags & RADEON_TILING_MICRO0x2)
		tile_flags |= RADEON_TXO_MICRO_TILE_X2(1 << 3);

	tmp = idx_value & ~(0x7 << 2);
	tmp |= tile_flags;
	ib[idx] = tmp + ((u32)reloc->gpu_offset);
} else
	ib[idx] = idx_value + ((u32)reloc->gpu_offset);
track->textures[i].robj = reloc->robj;
track->tex_dirty = true1;
break;
case RADEON_PP_CUBIC_OFFSET_T0_00x1dd0:
case RADEON_PP_CUBIC_OFFSET_T0_10x1dd4:
case RADEON_PP_CUBIC_OFFSET_T0_20x1dd8:
case RADEON_PP_CUBIC_OFFSET_T0_30x1ddc:
case RADEON_PP_CUBIC_OFFSET_T0_40x1de0:
i = (reg - RADEON_PP_CUBIC_OFFSET_T0_00x1dd0) / 4;
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
track->textures[0].cube_info[i].offset = idx_value;
ib[idx] = idx_value + ((u32)reloc->gpu_offset);
track->textures[0].cube_info[i].robj = reloc->robj;
track->tex_dirty = true1;
break;
case RADEON_PP_CUBIC_OFFSET_T1_00x1e00:
case RADEON_PP_CUBIC_OFFSET_T1_10x1e04:
case RADEON_PP_CUBIC_OFFSET_T1_20x1e08:
case RADEON_PP_CUBIC_OFFSET_T1_30x1e0c:
case RADEON_PP_CUBIC_OFFSET_T1_40x1e10:
i = (reg - RADEON_PP_CUBIC_OFFSET_T1_00x1e00) / 4;
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
track->textures[1].cube_info[i].offset = idx_value;
ib[idx] = idx_value + ((u32)reloc->gpu_offset);
track->textures[1].cube_info[i].robj = reloc->robj;
track->tex_dirty = true1;
break;
case RADEON_PP_CUBIC_OFFSET_T2_00x1e14:
case RADEON_PP_CUBIC_OFFSET_T2_10x1e18:
case RADEON_PP_CUBIC_OFFSET_T2_20x1e1c:
case RADEON_PP_CUBIC_OFFSET_T2_30x1e20:
case RADEON_PP_CUBIC_OFFSET_T2_40x1e24:
i = (reg - RADEON_PP_CUBIC_OFFSET_T2_00x1e14) / 4;
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
track->textures[2].cube_info[i].offset = idx_value;
ib[idx] = idx_value + ((u32)reloc->gpu_offset);
track->textures[2].cube_info[i].robj = reloc->robj;
track->tex_dirty = true1;
break;
case RADEON_RE_WIDTH_HEIGHT0x1c44:
track->maxy = ((idx_value >> 16) & 0x7FF);
track->cb_dirty = true1;
track->zb_dirty = true1;
break;
case RADEON_RB3D_COLORPITCH0x1c48:
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS0x01)) {
	if (reloc->tiling_flags & RADEON_TILING_MACRO0x1)
		tile_flags |= RADEON_COLOR_TILE_ENABLE(1 << 16);
	if (reloc->tiling_flags & RADEON_TILING_MICRO0x2)
		tile_flags |= RADEON_COLOR_MICROTILE_ENABLE(1 << 17);

	tmp = idx_value & ~(0x7 << 16);
	tmp |= tile_flags;
	ib[idx] = tmp;
} else
	ib[idx] = idx_value;

track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK0x000001ff8;
track->cb_dirty = true1;
break;
case RADEON_RB3D_DEPTHPITCH0x1c28:
track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK0x00001ff8;
track->zb_dirty = true1;
break;
case RADEON_RB3D_CNTL0x1c3c:
switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT10) & 0x1f) {
case 7:
case 8:
case 9:
case 11:
case 12:
	track->cb[0].cpp = 1;
	break;
case 3:
case 4:
case 15:
	track->cb[0].cpp = 2;
	break;
case 6:
	track->cb[0].cpp = 4;
	break;
default:
	DRM_ERROR("Invalid color buffer format (%d) !\n",__drm_err("Invalid color buffer format (%d) !\n", ((idx_value
 >> 10) & 0x1f))
		  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f))__drm_err("Invalid color buffer format (%d) !\n", ((idx_value
 >> 10) & 0x1f));
	return -EINVAL22;
}
track->z_enabled = !!(idx_value & RADEON_Z_ENABLE(1 << 8));
track->cb_dirty = true1;
track->zb_dirty = true1;
break;
case RADEON_RB3D_ZSTENCILCNTL0x1c2c:
switch (idx_value & 0xf) {
case 0:
	track->zb.cpp = 2;
	break;
case 2:
case 3:
case 4:
case 5:
case 9:
case 11:
	track->zb.cpp = 4;
	break;
default:
	break;
}
track->zb_dirty = true1;
break;
case RADEON_RB3D_ZPASS_ADDR0x3294:
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for ib[%d]=0x%04X\n",__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg)
		  idx, reg)__drm_err("No reloc for ib[%d]=0x%04X\n", idx, reg);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
ib[idx] = idx_value + ((u32)reloc->gpu_offset);
break;
case RADEON_PP_CNTL0x1c38:
{
	uint32_t temp = idx_value >> 4;
	for (i = 0; i < track->num_texture; i++)
		track->textures[i].enabled = !!(temp & (1 << i));
	track->tex_dirty = true1;
}
break;
case RADEON_SE_VF_CNTL0x2084:
track->vap_vf_cntl = idx_value;
break;
case RADEON_SE_VTX_FMT0x2080:
track->vtx_size = r100_get_vtx_size(idx_value);
break;
case RADEON_PP_TEX_SIZE_00x1d04:
case RADEON_PP_TEX_SIZE_10x1d0c:
case RADEON_PP_TEX_SIZE_20x1d14:
i = (reg - RADEON_PP_TEX_SIZE_00x1d04) / 8;
track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK(0x7ff << 0)) + 1;
track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK(0x7ff << 16)) >> RADEON_TEX_VSIZE_SHIFT16) + 1;
track->tex_dirty = true1;
break;
case RADEON_PP_TEX_PITCH_00x1d08:
case RADEON_PP_TEX_PITCH_10x1d10:
case RADEON_PP_TEX_PITCH_20x1d18:
i = (reg - RADEON_PP_TEX_PITCH_00x1d08) / 8;
track->textures[i].pitch = idx_value + 32;
track->tex_dirty = true1;
break;
case RADEON_PP_TXFILTER_00x1c54:
case RADEON_PP_TXFILTER_10x1c6c:
case RADEON_PP_TXFILTER_20x1c84:
i = (reg - RADEON_PP_TXFILTER_00x1c54) / 24;
track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK(0x0f << 16))
				 >> RADEON_MAX_MIP_LEVEL_SHIFT16);
tmp = (idx_value >> 23) & 0x7;
if (tmp == 2 || tmp == 6)
	track->textures[i].roundup_w = false0;
tmp = (idx_value >> 27) & 0x7;
if (tmp == 2 || tmp == 6)
	track->textures[i].roundup_h = false0;
track->tex_dirty = true1;
break;
case RADEON_PP_TXFORMAT_00x1c58:
case RADEON_PP_TXFORMAT_10x1c70:
case RADEON_PP_TXFORMAT_20x1c88:
i = (reg - RADEON_PP_TXFORMAT_00x1c58) / 24;
if (idx_value & RADEON_TXFORMAT_NON_POWER2(1 << 7)) {
	track->textures[i].use_pitch = true1;
} else {
	track->textures[i].use_pitch = false0;
	track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK(15 << 8)) >> RADEON_TXFORMAT_WIDTH_SHIFT8);
	track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK(15 << 12)) >> RADEON_TXFORMAT_HEIGHT_SHIFT12);
}
if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE(1 << 30))
	track->textures[i].tex_coord_type = 2;
switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK(31 << 0))) {
case RADEON_TXFORMAT_I8(0 << 0):
case RADEON_TXFORMAT_RGB332(2 << 0):
case RADEON_TXFORMAT_Y8(8 << 0):
	track->textures[i].cpp = 1;
	track->textures[i].compress_format = R100_TRACK_COMP_NONE0;
	break;
case RADEON_TXFORMAT_AI88(1 << 0):
case RADEON_TXFORMAT_ARGB1555(3 << 0):
case RADEON_TXFORMAT_RGB565(4 << 0):
case RADEON_TXFORMAT_ARGB4444(5 << 0):
case RADEON_TXFORMAT_VYUY422(10 << 0):
case RADEON_TXFORMAT_YVYU422(11 << 0):
case RADEON_TXFORMAT_SHADOW16(16 << 0):
case RADEON_TXFORMAT_LDUDV655(19 << 0):
case RADEON_TXFORMAT_DUDV88(18 << 0):
	track->textures[i].cpp = 2;
	track->textures[i].compress_format = R100_TRACK_COMP_NONE0;
	break;
case RADEON_TXFORMAT_ARGB8888(6 << 0):
case RADEON_TXFORMAT_RGBA8888(7 << 0):
case RADEON_TXFORMAT_SHADOW32(17 << 0):
case RADEON_TXFORMAT_LDUDUV8888(20 << 0):
	track->textures[i].cpp = 4;
	track->textures[i].compress_format = R100_TRACK_COMP_NONE0;
	break;
case RADEON_TXFORMAT_DXT1(12 << 0):
	track->textures[i].cpp = 1;
	track->textures[i].compress_format = R100_TRACK_COMP_DXT11;
	break;
case RADEON_TXFORMAT_DXT23(14 << 0):
case RADEON_TXFORMAT_DXT45(15 << 0):
	track->textures[i].cpp = 1;
	track->textures[i].compress_format = R100_TRACK_COMP_DXT352;
	break;
}
track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
track->tex_dirty = true1;
break;
case RADEON_PP_CUBIC_FACES_00x1d24:
case RADEON_PP_CUBIC_FACES_10x1d28:
case RADEON_PP_CUBIC_FACES_20x1d2c:
tmp = idx_value;
i = (reg - RADEON_PP_CUBIC_FACES_00x1d24) / 4;
for (face = 0; face < 4; face++) {
	track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
	track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
}
track->tex_dirty = true1;
break;
default:
pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx)printk("\0013" "Forbidden register 0x%04X in cs at %d\n", reg
, idx);
return -EINVAL22;
}
return 0;
1898}

1900int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
			 struct radeon_cs_packet *pkt,
			 struct radeon_bo *robj)
1903{
unsigned idx;
u32 value;
idx = pkt->idx + 1;
value = radeon_get_ib_value(p, idx + 2);
if ((value + 1) > radeon_bo_size(robj)) {
DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "__drm_err("[drm] Buffer too small for PACKET3 INDX_BUFFER " "(need %u have %lu) !\n"
, value + 1, radeon_bo_size(robj))
	  "(need %u have %lu) !\n",__drm_err("[drm] Buffer too small for PACKET3 INDX_BUFFER " "(need %u have %lu) !\n"
, value + 1, radeon_bo_size(robj))
	  value + 1,__drm_err("[drm] Buffer too small for PACKET3 INDX_BUFFER " "(need %u have %lu) !\n"
, value + 1, radeon_bo_size(robj))
	  radeon_bo_size(robj))__drm_err("[drm] Buffer too small for PACKET3 INDX_BUFFER " "(need %u have %lu) !\n"
, value + 1, radeon_bo_size(robj));
return -EINVAL22;
}
return 0;
1916}

1918static int r100_packet3_check(struct radeon_cs_parser *p,
	      struct radeon_cs_packet *pkt)
1920{
struct radeon_bo_list *reloc;
struct r100_cs_track *track;
unsigned idx;
volatile uint32_t *ib;
int r;

ib = p->ib.ptr;
idx = pkt->idx + 1;
track = (struct r100_cs_track *)p->track;
switch (pkt->opcode) {
case PACKET3_3D_LOAD_VBPNTR0x2F:
r = r100_packet3_load_vbpntr(p, pkt, idx);
if (r)
	return r;
break;
case PACKET3_INDX_BUFFER0x33:
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode)__drm_err("No reloc for packet3 %d\n", pkt->opcode);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
if (r) {
	return r;
}
break;
case 0x23:
/* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
r = radeon_cs_packet_next_reloc(p, &reloc, 0);
if (r) {
	DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode)__drm_err("No reloc for packet3 %d\n", pkt->opcode);
	radeon_cs_dump_packet(p, pkt);
	return r;
}
ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
track->num_arrays = 1;
track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));

track->arrays[0].robj = reloc->robj;
track->arrays[0].esize = track->vtx_size;

track->max_indx = radeon_get_ib_value(p, idx+1);

track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
track->immd_dwords = pkt->count - 1;
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
case PACKET3_3D_DRAW_IMMD0x29:
if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n")__drm_err("PRIM_WALK must be 3 for IMMD draw\n");
	return -EINVAL22;
}
track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
track->immd_dwords = pkt->count - 1;
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
/* triggers drawing using in-packet vertex data */
case PACKET3_3D_DRAW_IMMD_20x35:
if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
	DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n")__drm_err("PRIM_WALK must be 3 for IMMD draw\n");
	return -EINVAL22;
}
track->vap_vf_cntl = radeon_get_ib_value(p, idx);
track->immd_dwords = pkt->count;
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
/* triggers drawing using in-packet vertex data */
case PACKET3_3D_DRAW_VBUF_20x34:
track->vap_vf_cntl = radeon_get_ib_value(p, idx);
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
/* triggers drawing of vertex buffers setup elsewhere */
case PACKET3_3D_DRAW_INDX_20x36:
track->vap_vf_cntl = radeon_get_ib_value(p, idx);
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
/* triggers drawing using indices to vertex buffer */
case PACKET3_3D_DRAW_VBUF0x28:
track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
/* triggers drawing of vertex buffers setup elsewhere */
case PACKET3_3D_DRAW_INDX0x2A:
track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
r = r100_cs_track_check(p->rdev, track);
if (r)
	return r;
break;
/* triggers drawing using indices to vertex buffer */
case PACKET3_3D_CLEAR_HIZ0x37:
case PACKET3_3D_CLEAR_ZMASK0x32:
if (p->rdev->hyperz_filp != p->filp)
	return -EINVAL22;
break;
case PACKET3_NOP0x10:
break;
default:
DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode)__drm_err("Packet3 opcode %x not supported\n", pkt->opcode
);
return -EINVAL22;
}
return 0;
2037}

2039int r100_cs_parse(struct radeon_cs_parser *p)
2040{
struct radeon_cs_packet pkt;
struct r100_cs_track *track;
int r;

track = kzalloc(sizeof(*track), GFP_KERNEL(0x0001 | 0x0004));
if (!track)
return -ENOMEM12;
r100_cs_track_clear(p->rdev, track);
p->track = track;
do {
r = radeon_cs_packet_parse(p, &pkt, p->idx);
if (r) {
	return r;
}
p->idx += pkt.count + 2;
switch (pkt.type) {
case RADEON_PACKET_TYPE00:
	if (p->rdev->family >= CHIP_R200)
		r = r100_cs_parse_packet0(p, &pkt,
			p->rdev->config.r100.reg_safe_bm,
			p->rdev->config.r100.reg_safe_bm_size,
			&r200_packet0_check);
	else
		r = r100_cs_parse_packet0(p, &pkt,
			p->rdev->config.r100.reg_safe_bm,
			p->rdev->config.r100.reg_safe_bm_size,
			&r100_packet0_check);
	break;
case RADEON_PACKET_TYPE22:
	break;
case RADEON_PACKET_TYPE33:
	r = r100_packet3_check(p, &pkt);
	break;
default:
	DRM_ERROR("Unknown packet type %d !\n",__drm_err("Unknown packet type %d !\n", pkt.type)
		  pkt.type)__drm_err("Unknown packet type %d !\n", pkt.type);
	return -EINVAL22;
}
if (r)
	return r;
} while (p->idx < p->chunk_ib->length_dw);
return 0;
2083}

2085static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2086{
DRM_ERROR("pitch                      %d\n", t->pitch)__drm_err("pitch                      %d\n", t->pitch);
DRM_ERROR("use_pitch                  %d\n", t->use_pitch)__drm_err("use_pitch                  %d\n", t->use_pitch);
DRM_ERROR("width                      %d\n", t->width)__drm_err("width                      %d\n", t->width);
DRM_ERROR("width_11                   %d\n", t->width_11)__drm_err("width_11                   %d\n", t->width_11);
DRM_ERROR("height                     %d\n", t->height)__drm_err("height                     %d\n", t->height);
DRM_ERROR("height_11                  %d\n", t->height_11)__drm_err("height_11                  %d\n", t->height_11);
DRM_ERROR("num levels                 %d\n", t->num_levels)__drm_err("num levels                 %d\n", t->num_levels
);
DRM_ERROR("depth                      %d\n", t->txdepth)__drm_err("depth                      %d\n", t->txdepth);
DRM_ERROR("bpp                        %d\n", t->cpp)__drm_err("bpp                        %d\n", t->cpp);
DRM_ERROR("coordinate type            %d\n", t->tex_coord_type)__drm_err("coordinate type            %d\n", t->tex_coord_type
);
DRM_ERROR("width round to power of 2  %d\n", t->roundup_w)__drm_err("width round to power of 2  %d\n", t->roundup_w);
DRM_ERROR("height round to power of 2 %d\n", t->roundup_h)__drm_err("height round to power of 2 %d\n", t->roundup_h);
DRM_ERROR("compress format            %d\n", t->compress_format)__drm_err("compress format            %d\n", t->compress_format
);
2100}

2102static int r100_track_compress_size(int compress_format, int w, int h)
2103{
int block_width, block_height, block_bytes;
int wblocks, hblocks;
int min_wblocks;
int sz;

block_width = 4;
block_height = 4;

switch (compress_format) {
case R100_TRACK_COMP_DXT11:
block_bytes = 8;
min_wblocks = 4;
break;
default:
case R100_TRACK_COMP_DXT352:
block_bytes = 16;
min_wblocks = 2;
break;
}

hblocks = (h + block_height - 1) / block_height;
wblocks = (w + block_width - 1) / block_width;
if (wblocks < min_wblocks)
wblocks = min_wblocks;
sz = wblocks * hblocks * block_bytes;
return sz;
2130}

2132static int r100_cs_track_cube(struct radeon_device *rdev,
	      struct r100_cs_track *track, unsigned idx)
2134{
unsigned face, w, h;
struct radeon_bo *cube_robj;
unsigned long size;
unsigned compress_format = track->textures[idx].compress_format;

for (face = 0; face < 5; face++) {
cube_robj = track->textures[idx].cube_info[face].robj;
w = track->textures[idx].cube_info[face].width;
h = track->textures[idx].cube_info[face].height;

if (compress_format) {
	size = r100_track_compress_size(compress_format, w, h);
} else
	size = w * h;
size *= track->textures[idx].cpp;

size += track->textures[idx].cube_info[face].offset;

if (size > radeon_bo_size(cube_robj)) {
	DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",__drm_err("Cube texture offset greater than object size %lu %lu\n"
, size, radeon_bo_size(cube_robj))
		  size, radeon_bo_size(cube_robj))__drm_err("Cube texture offset greater than object size %lu %lu\n"
, size, radeon_bo_size(cube_robj));
	r100_cs_track_texture_print(&track->textures[idx]);
	return -1;
}
}
return 0;
2161}

2163static int r100_cs_track_texture_check(struct radeon_device *rdev,
		       struct r100_cs_track *track)
2165{
struct radeon_bo *robj;
unsigned long size;
unsigned u, i, w, h, d;
int ret;

for (u = 0; u < track->num_texture; u++) {
if (!track->textures[u].enabled)
	continue;
if (track->textures[u].lookup_disable)
	continue;
robj = track->textures[u].robj;
if (robj == NULL((void *)0)) {
	DRM_ERROR("No texture bound to unit %u\n", u)__drm_err("No texture bound to unit %u\n", u);
	return -EINVAL22;
}
size = 0;
for (i = 0; i <= track->textures[u].num_levels; i++) {
	if (track->textures[u].use_pitch) {
		if (rdev->family < CHIP_R300)
			w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
		else
			w = track->textures[u].pitch / (1 << i);
	} else {
		w = track->textures[u].width;
		if (rdev->family >= CHIP_RV515)
			w |= track->textures[u].width_11;
		w = w / (1 << i);
		if (track->textures[u].roundup_w)
			w = roundup_pow_of_two(w);
	}
	h = track->textures[u].height;
	if (rdev->family >= CHIP_RV515)
		h |= track->textures[u].height_11;
	h = h / (1 << i);
	if (track->textures[u].roundup_h)
		h = roundup_pow_of_two(h);
	if (track->textures[u].tex_coord_type == 1) {
		d = (1 << track->textures[u].txdepth) / (1 << i);
		if (!d)
			d = 1;
	} else {
		d = 1;
	}
	if (track->textures[u].compress_format) {

		size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
		/* compressed textures are block based */
	} else
		size += w * h * d;
}
size *= track->textures[u].cpp;

switch (track->textures[u].tex_coord_type) {
case 0:
case 1:
	break;
case 2:
	if (track->separate_cube) {
		ret = r100_cs_track_cube(rdev, track, u);
		if (ret)
			return ret;
	} else
		size *= 6;
	break;
default:
	DRM_ERROR("Invalid texture coordinate type %u for unit "__drm_err("Invalid texture coordinate type %u for unit " "%u\n"
, track->textures[u].tex_coord_type, u)
		  "%u\n", track->textures[u].tex_coord_type, u)__drm_err("Invalid texture coordinate type %u for unit " "%u\n"
, track->textures[u].tex_coord_type, u);
	return -EINVAL22;
}
if (size > radeon_bo_size(robj)) {
	DRM_ERROR("Texture of unit %u needs %lu bytes but is "__drm_err("Texture of unit %u needs %lu bytes but is " "%lu\n"
, u, size, radeon_bo_size(robj))
		  "%lu\n", u, size, radeon_bo_size(robj))__drm_err("Texture of unit %u needs %lu bytes but is " "%lu\n"
, u, size, radeon_bo_size(robj));
	r100_cs_track_texture_print(&track->textures[u]);
	return -EINVAL22;
}
}
return 0;
2243}

2245int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2246{
unsigned i;
unsigned long size;
unsigned prim_walk;
unsigned nverts;
unsigned num_cb = track->cb_dirty ? track->num_cb : 0;

if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
   !track->blend_read_enable)
num_cb = 0;

for (i = 0; i < num_cb; i++) {
if (track->cb[i].robj == NULL((void *)0)) {
	DRM_ERROR("[drm] No buffer for color buffer %d !\n", i)__drm_err("[drm] No buffer for color buffer %d !\n", i);
	return -EINVAL22;
}
size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
size += track->cb[i].offset;
if (size > radeon_bo_size(track->cb[i].robj)) {
	DRM_ERROR("[drm] Buffer too small for color buffer %d "__drm_err("[drm] Buffer too small for color buffer %d " "(need %lu have %lu) !\n"
, i, size, radeon_bo_size(track->cb[i].robj))
		  "(need %lu have %lu) !\n", i, size,__drm_err("[drm] Buffer too small for color buffer %d " "(need %lu have %lu) !\n"
, i, size, radeon_bo_size(track->cb[i].robj))
		  radeon_bo_size(track->cb[i].robj))__drm_err("[drm] Buffer too small for color buffer %d " "(need %lu have %lu) !\n"
, i, size, radeon_bo_size(track->cb[i].robj));
	DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",__drm_err("[drm] color buffer %d (%u %u %u %u)\n", i, track->
cb[i].pitch, track->cb[i].cpp, track->cb[i].offset, track
->maxy)
		  i, track->cb[i].pitch, track->cb[i].cpp,__drm_err("[drm] color buffer %d (%u %u %u %u)\n", i, track->
cb[i].pitch, track->cb[i].cpp, track->cb[i].offset, track
->maxy)
		  track->cb[i].offset, track->maxy)__drm_err("[drm] color buffer %d (%u %u %u %u)\n", i, track->
cb[i].pitch, track->cb[i].cpp, track->cb[i].offset, track
->maxy);
	return -EINVAL22;
}
}
track->cb_dirty = false0;

if (track->zb_dirty && track->z_enabled) {
if (track->zb.robj == NULL((void *)0)) {
	DRM_ERROR("[drm] No buffer for z buffer !\n")__drm_err("[drm] No buffer for z buffer !\n");
	return -EINVAL22;
}
size = track->zb.pitch * track->zb.cpp * track->maxy;
size += track->zb.offset;
if (size > radeon_bo_size(track->zb.robj)) {
	DRM_ERROR("[drm] Buffer too small for z buffer "__drm_err("[drm] Buffer too small for z buffer " "(need %lu have %lu) !\n"
, size, radeon_bo_size(track->zb.robj))
		  "(need %lu have %lu) !\n", size,__drm_err("[drm] Buffer too small for z buffer " "(need %lu have %lu) !\n"
, size, radeon_bo_size(track->zb.robj))
		  radeon_bo_size(track->zb.robj))__drm_err("[drm] Buffer too small for z buffer " "(need %lu have %lu) !\n"
, size, radeon_bo_size(track->zb.robj));
	DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",__drm_err("[drm] zbuffer (%u %u %u %u)\n", track->zb.pitch
, track->zb.cpp, track->zb.offset, track->maxy)
		  track->zb.pitch, track->zb.cpp,__drm_err("[drm] zbuffer (%u %u %u %u)\n", track->zb.pitch
, track->zb.cpp, track->zb.offset, track->maxy)
		  track->zb.offset, track->maxy)__drm_err("[drm] zbuffer (%u %u %u %u)\n", track->zb.pitch
, track->zb.cpp, track->zb.offset, track->maxy);
	return -EINVAL22;
}
}
track->zb_dirty = false0;

if (track->aa_dirty && track->aaresolve) {
if (track->aa.robj == NULL((void *)0)) {
	DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i)__drm_err("[drm] No buffer for AA resolve buffer %d !\n", i);
	return -EINVAL22;
}
/* I believe the format comes from colorbuffer0. */
size = track->aa.pitch * track->cb[0].cpp * track->maxy;
size += track->aa.offset;
if (size > radeon_bo_size(track->aa.robj)) {
	DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "__drm_err("[drm] Buffer too small for AA resolve buffer %d " "(need %lu have %lu) !\n"
, i, size, radeon_bo_size(track->aa.robj))
		  "(need %lu have %lu) !\n", i, size,__drm_err("[drm] Buffer too small for AA resolve buffer %d " "(need %lu have %lu) !\n"
, i, size, radeon_bo_size(track->aa.robj))
		  radeon_bo_size(track->aa.robj))__drm_err("[drm] Buffer too small for AA resolve buffer %d " "(need %lu have %lu) !\n"
, i, size, radeon_bo_size(track->aa.robj));
	DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",__drm_err("[drm] AA resolve buffer %d (%u %u %u %u)\n", i, track
->aa.pitch, track->cb[0].cpp, track->aa.offset, track
->maxy)
		  i, track->aa.pitch, track->cb[0].cpp,__drm_err("[drm] AA resolve buffer %d (%u %u %u %u)\n", i, track
->aa.pitch, track->cb[0].cpp, track->aa.offset, track
->maxy)
		  track->aa.offset, track->maxy)__drm_err("[drm] AA resolve buffer %d (%u %u %u %u)\n", i, track
->aa.pitch, track->cb[0].cpp, track->aa.offset, track
->maxy);
	return -EINVAL22;
}
}
track->aa_dirty = false0;

prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
if (track->vap_vf_cntl & (1 << 14)) {
nverts = track->vap_alt_nverts;
} else {
nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
}
switch (prim_walk) {
case 1:
for (i = 0; i < track->num_arrays; i++) {
	size = track->arrays[i].esize * track->max_indx * 4;
	if (track->arrays[i].robj == NULL((void *)0)) {
		DRM_ERROR("(PW %u) Vertex array %u no buffer "__drm_err("(PW %u) Vertex array %u no buffer " "bound\n", prim_walk
, i)
			  "bound\n", prim_walk, i)__drm_err("(PW %u) Vertex array %u no buffer " "bound\n", prim_walk
, i);
		return -EINVAL22;
	}
	if (size > radeon_bo_size(track->arrays[i].robj)) {
		dev_err(rdev->dev, "(PW %u) Vertex array %u "printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			"need %lu dwords have %lu dwords\n",printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			prim_walk, i, size >> 2,printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			radeon_bo_size(track->arrays[i].robj)printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			>> 2)printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2);
		DRM_ERROR("Max indices %u\n", track->max_indx)__drm_err("Max indices %u\n", track->max_indx);
		return -EINVAL22;
	}
}
break;
case 2:
for (i = 0; i < track->num_arrays; i++) {
	size = track->arrays[i].esize * (nverts - 1) * 4;
	if (track->arrays[i].robj == NULL((void *)0)) {
		DRM_ERROR("(PW %u) Vertex array %u no buffer "__drm_err("(PW %u) Vertex array %u no buffer " "bound\n", prim_walk
, i)
			  "bound\n", prim_walk, i)__drm_err("(PW %u) Vertex array %u no buffer " "bound\n", prim_walk
, i);
		return -EINVAL22;
	}
	if (size > radeon_bo_size(track->arrays[i].robj)) {
		dev_err(rdev->dev, "(PW %u) Vertex array %u "printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			"need %lu dwords have %lu dwords\n",printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			prim_walk, i, size >> 2,printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			radeon_bo_size(track->arrays[i].robj)printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2)
			>> 2)printf("drm:pid%d:%s *ERROR* " "(PW %u) Vertex array %u " "need %lu dwords have %lu dwords\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , prim_walk
, i, size >> 2, radeon_bo_size(track->arrays[i].robj
) >> 2);
		return -EINVAL22;
	}
}
break;
case 3:
size = track->vtx_size * nverts;
if (size != track->immd_dwords) {
	DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",__drm_err("IMMD draw %u dwors but needs %lu dwords\n", track->
immd_dwords, size)
		  track->immd_dwords, size)__drm_err("IMMD draw %u dwors but needs %lu dwords\n", track->
immd_dwords, size);
	DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",__drm_err("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", nverts
, track->vtx_size)
		  nverts, track->vtx_size)__drm_err("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n", nverts
, track->vtx_size);
	return -EINVAL22;
}
break;
default:
DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",__drm_err("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n"
, prim_walk)
	  prim_walk)__drm_err("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n"
, prim_walk);
return -EINVAL22;
}

if (track->tex_dirty) {
track->tex_dirty = false0;
return r100_cs_track_texture_check(rdev, track);
}
return 0;
2380}

2382void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2383{
unsigned i, face;

track->cb_dirty = true1;
track->zb_dirty = true1;
track->tex_dirty = true1;
track->aa_dirty = true1;

if (rdev->family < CHIP_R300) {
track->num_cb = 1;
if (rdev->family <= CHIP_RS200)
	track->num_texture = 3;
else
	track->num_texture = 6;
track->maxy = 2048;
track->separate_cube = true1;
} else {
track->num_cb = 4;
track->num_texture = 16;
track->maxy = 4096;
track->separate_cube = false0;
track->aaresolve = false0;
track->aa.robj = NULL((void *)0);
}

for (i = 0; i < track->num_cb; i++) {
track->cb[i].robj = NULL((void *)0);
track->cb[i].pitch = 8192;
track->cb[i].cpp = 16;
track->cb[i].offset = 0;
}
track->z_enabled = true1;
track->zb.robj = NULL((void *)0);
track->zb.pitch = 8192;
track->zb.cpp = 4;
track->zb.offset = 0;
track->vtx_size = 0x7F;
track->immd_dwords = 0xFFFFFFFFUL;
track->num_arrays = 11;
track->max_indx = 0x00FFFFFFUL;
for (i = 0; i < track->num_arrays; i++) {
track->arrays[i].robj = NULL((void *)0);
track->arrays[i].esize = 0x7F;
}
for (i = 0; i < track->num_texture; i++) {
track->textures[i].compress_format = R100_TRACK_COMP_NONE0;
track->textures[i].pitch = 16536;
track->textures[i].width = 16536;
track->textures[i].height = 16536;
track->textures[i].width_11 = 1 << 11;
track->textures[i].height_11 = 1 << 11;
track->textures[i].num_levels = 12;
if (rdev->family <= CHIP_RS200) {
	track->textures[i].tex_coord_type = 0;
	track->textures[i].txdepth = 0;
} else {
	track->textures[i].txdepth = 16;
	track->textures[i].tex_coord_type = 1;
}
track->textures[i].cpp = 64;
track->textures[i].robj = NULL((void *)0);
/* CS IB emission code makes sure texture unit are disabled */
track->textures[i].enabled = false0;
track->textures[i].lookup_disable = false0;
track->textures[i].roundup_w = true1;
track->textures[i].roundup_h = true1;
if (track->separate_cube)
	for (face = 0; face < 5; face++) {
		track->textures[i].cube_info[face].robj = NULL((void *)0);
		track->textures[i].cube_info[face].width = 16536;
		track->textures[i].cube_info[face].height = 16536;
		track->textures[i].cube_info[face].offset = 0;
	}
}
2457}

2459/*
* Global GPU functions
*/
2462static void r100_errata(struct radeon_device *rdev)
2463{
rdev->pll_errata = 0;

if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
}

if (rdev->family == CHIP_RV100 ||
   rdev->family == CHIP_RS100 ||
   rdev->family == CHIP_RS200) {
rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
}
2475}

2477static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2478{
unsigned i;
uint32_t tmp;

for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(RADEON_RBBM_STATUS)r100_mm_rreg(rdev, (0x0e40), 0) & RADEON_RBBM_FIFOCNT_MASK0x007f;
if (tmp >= n) {
	return 0;
}
udelay(1);
}
return -1;
2490}

2492int r100_gui_wait_for_idle(struct radeon_device *rdev)
2493{
unsigned i;
uint32_t tmp;

if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
pr_warn("radeon: wait for empty RBBM fifo failed! Bad things might happen.\n")printk("\0014" "radeon: wait for empty RBBM fifo failed! Bad things might happen.\n"
);
}
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(RADEON_RBBM_STATUS)r100_mm_rreg(rdev, (0x0e40), 0);
if (!(tmp & RADEON_RBBM_ACTIVE(1 << 31))) {
	return 0;
}
udelay(1);
}
return -1;
2508}

2510int r100_mc_wait_for_idle(struct radeon_device *rdev)
2511{
unsigned i;
uint32_t tmp;

for (i = 0; i < rdev->usec_timeout; i++) {
/* read MC_STATUS */
tmp = RREG32(RADEON_MC_STATUS)r100_mm_rreg(rdev, (0x0150), 0);
if (tmp & RADEON_MC_IDLE(1 << 2)) {
	return 0;
}
udelay(1);
}
return -1;
2524}

2526bool_Bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2527{
u32 rbbm_status;

rbbm_status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
if (!G_000E40_GUI_ACTIVE(rbbm_status)(((rbbm_status) >> 31) & 0x1)) {
radeon_ring_lockup_update(rdev, ring);
return false0;
}
return radeon_ring_test_lockup(rdev, ring);
2536}

2538/* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2539void r100_enable_bm(struct radeon_device *rdev)
2540{
uint32_t tmp;
/* Enable bus mastering */
tmp = RREG32(RADEON_BUS_CNTL)r100_mm_rreg(rdev, (0x0030), 0) & ~RADEON_BUS_MASTER_DIS(1 << 6);
WREG32(RADEON_BUS_CNTL, tmp)r100_mm_wreg(rdev, (0x0030), (tmp), 0);
2545}

2547void r100_bm_disable(struct radeon_device *rdev)
2548{
u32 tmp;

/* disable bus mastering */
tmp = RREG32(R_000030_BUS_CNTL)r100_mm_rreg(rdev, (0x000030), 0);
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044)r100_mm_wreg(rdev, (0x000030), ((tmp & 0xFFFFFFFF) | 0x00000044
), 0);
mdelay(1);
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042)r100_mm_wreg(rdev, (0x000030), ((tmp & 0xFFFFFFFF) | 0x00000042
), 0);
mdelay(1);
WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040)r100_mm_wreg(rdev, (0x000030), ((tmp & 0xFFFFFFFF) | 0x00000040
), 0);
tmp = RREG32(RADEON_BUS_CNTL)r100_mm_rreg(rdev, (0x0030), 0);
mdelay(1);
pci_clear_master(rdev->pdev);
mdelay(1);
2562}

2564int r100_asic_reset(struct radeon_device *rdev, bool_Bool hard)
2565{
struct r100_mc_save save;
u32 status, tmp;
int ret = 0;

status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
if (!G_000E40_GUI_ACTIVE(status)(((status) >> 31) & 0x1)) {
return 0;
}
r100_mc_stop(rdev, &save);
status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
/* stop CP */
WREG32(RADEON_CP_CSQ_CNTL, 0)r100_mm_wreg(rdev, (0x0740), (0), 0);
tmp = RREG32(RADEON_CP_RB_CNTL)r100_mm_rreg(rdev, (0x0704), 0);
WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA)r100_mm_wreg(rdev, (0x0704), (tmp | (1 << 31)), 0);
WREG32(RADEON_CP_RB_RPTR_WR, 0)r100_mm_wreg(rdev, (0x071c), (0), 0);
WREG32(RADEON_CP_RB_WPTR, 0)r100_mm_wreg(rdev, (0x0714), (0), 0);
WREG32(RADEON_CP_RB_CNTL, tmp)r100_mm_wreg(rdev, (0x0704), (tmp), 0);
/* save PCI state */
pci_save_state(rdev->pdev);
/* disable bus mastering */
r100_bm_disable(rdev);
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 2) |
 (((1) & 0x1) << 3) | (((1) & 0x1) << 4) |
 (((1) & 0x1) << 6)), 0)
			S_0000F0_SOFT_RESET_RE(1) |r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 2) |
 (((1) & 0x1) << 3) | (((1) & 0x1) << 4) |
 (((1) & 0x1) << 6)), 0)
			S_0000F0_SOFT_RESET_PP(1) |r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 2) |
 (((1) & 0x1) << 3) | (((1) & 0x1) << 4) |
 (((1) & 0x1) << 6)), 0)
			S_0000F0_SOFT_RESET_RB(1))r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 2) |
 (((1) & 0x1) << 3) | (((1) & 0x1) << 4) |
 (((1) & 0x1) << 6)), 0);
RREG32(R_0000F0_RBBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0000F0), 0);
mdelay(500);
WREG32(R_0000F0_RBBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x0000F0), (0), 0);
mdelay(1);
status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
/* reset CP */
WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1))r100_mm_wreg(rdev, (0x0000F0), ((((1) & 0x1) << 0))
, 0);
RREG32(R_0000F0_RBBM_SOFT_RESET)r100_mm_rreg(rdev, (0x0000F0), 0);
mdelay(500);
WREG32(R_0000F0_RBBM_SOFT_RESET, 0)r100_mm_wreg(rdev, (0x0000F0), (0), 0);
mdelay(1);
status = RREG32(R_000E40_RBBM_STATUS)r100_mm_rreg(rdev, (0x000E40), 0);
dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status)do { } while(0);
/* restore PCI & busmastering */
pci_restore_state(rdev->pdev);
r100_enable_bm(rdev);
/* Check if GPU is idle */
if (G_000E40_SE_BUSY(status)(((status) >> 20) & 0x1) || G_000E40_RE_BUSY(status)(((status) >> 21) & 0x1) ||
G_000E40_TAM_BUSY(status)(((status) >> 22) & 0x1) || G_000E40_PB_BUSY(status)(((status) >> 24) & 0x1)) {
dev_err(rdev->dev, "failed to reset GPU\n")printf("drm:pid%d:%s *ERROR* " "failed to reset GPU\n", ({struct
 cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r" (__ci
) :"n" (__builtin_offsetof(struct cpu_info, ci_self))); __ci;
})->ci_curproc->p_p->ps_pid, __func__);
ret = -1;
} else
dev_info(rdev->dev, "GPU reset succeed\n")do { } while(0);
r100_mc_resume(rdev, &save);
return ret;
2618}

2620void r100_set_common_regs(struct radeon_device *rdev)
2621{
bool_Bool force_dac2 = false0;
u32 tmp;

/* set these so they don't interfere with anything */
WREG32(RADEON_OV0_SCALE_CNTL, 0)r100_mm_wreg(rdev, (0x0420), (0), 0);
WREG32(RADEON_SUBPIC_CNTL, 0)r100_mm_wreg(rdev, (0x0540), (0), 0);
WREG32(RADEON_VIPH_CONTROL, 0)r100_mm_wreg(rdev, (0x0c40), (0), 0);
WREG32(RADEON_I2C_CNTL_1, 0)r100_mm_wreg(rdev, (0x0094), (0), 0);
WREG32(RADEON_DVI_I2C_CNTL_1, 0)r100_mm_wreg(rdev, (0x02e4), (0), 0);
WREG32(RADEON_CAP0_TRIG_CNTL, 0)r100_mm_wreg(rdev, (0x0950), (0), 0);
WREG32(RADEON_CAP1_TRIG_CNTL, 0)r100_mm_wreg(rdev, (0x09C0), (0), 0);

/* always set up dac2 on rn50 and some rv100 as lots
* of servers seem to wire it up to a VGA port but
* don't report it in the bios connector
* table.
*/
switch (rdev->pdev->device) {
/* RN50 */
case 0x515e:
case 0x5969:
force_dac2 = true1;
break;
/* RV100*/
case 0x5159:
case 0x515a:
/* DELL triple head servers */
if ((rdev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
    ((rdev->pdev->subsystem_device == 0x016c) ||
     (rdev->pdev->subsystem_device == 0x016d) ||
     (rdev->pdev->subsystem_device == 0x016e) ||
     (rdev->pdev->subsystem_device == 0x016f) ||
     (rdev->pdev->subsystem_device == 0x0170) ||
     (rdev->pdev->subsystem_device == 0x017d) ||
     (rdev->pdev->subsystem_device == 0x017e) ||
     (rdev->pdev->subsystem_device == 0x0183) ||
     (rdev->pdev->subsystem_device == 0x018a) ||
     (rdev->pdev->subsystem_device == 0x019a)))
	force_dac2 = true1;
break;
}

if (force_dac2) {
u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG)r100_mm_rreg(rdev, (0x0d14), 0);
u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL)r100_mm_rreg(rdev, (0x088c), 0);
u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2)r100_mm_rreg(rdev, (0x007c), 0);

/* For CRT on DAC2, don't turn it on if BIOS didn't
   enable it, even it's detected.
*/

/* force it to crtc0 */
dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL(1 << 0);
dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL(1 << 1);
disp_hw_debug |= RADEON_CRT2_DISP1_SEL(1 << 5);

/* set up the TV DAC */
tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL(1 << 2) |
		 RADEON_TV_DAC_STD_MASK(3 << 8) |
		 RADEON_TV_DAC_RDACPD(1 << 24) |
		 RADEON_TV_DAC_GDACPD(1 << 25) |
		 RADEON_TV_DAC_BDACPD(1 << 26) |
		 RADEON_TV_DAC_BGADJ_MASK(0xf << 16) |
		 RADEON_TV_DAC_DACADJ_MASK(0xf << 20));
tv_dac_cntl |= (RADEON_TV_DAC_NBLANK(1 << 0) |
		RADEON_TV_DAC_NHOLD(1 << 1) |
		RADEON_TV_DAC_STD_PS2(2 << 8) |
		(0x58 << 16));

WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl)r100_mm_wreg(rdev, (0x088c), (tv_dac_cntl), 0);
WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug)r100_mm_wreg(rdev, (0x0d14), (disp_hw_debug), 0);
WREG32(RADEON_DAC_CNTL2, dac2_cntl)r100_mm_wreg(rdev, (0x007c), (dac2_cntl), 0);
}

/* switch PM block to ACPI mode */
tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL)rdev->pll_rreg(rdev, (0x0015));
tmp &= ~RADEON_PM_MODE_SEL(1 << 13);
WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp)rdev->pll_wreg(rdev, (0x0015), (tmp));

2701}

2703/*
* VRAM info
*/
2706static void r100_vram_get_type(struct radeon_device *rdev)
2707{
uint32_t tmp;

rdev->mc.vram_is_ddr = false0;
if (rdev->flags & RADEON_IS_IGP)
rdev->mc.vram_is_ddr = true1;
else if (RREG32(RADEON_MEM_SDRAM_MODE_REG)r100_mm_rreg(rdev, (0x0158), 0) & RADEON_MEM_CFG_TYPE_DDR(1 << 30))
rdev->mc.vram_is_ddr = true1;
if ((rdev->family == CHIP_RV100) ||
   (rdev->family == CHIP_RS100) ||
   (rdev->family == CHIP_RS200)) {
tmp = RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0);
if (tmp & RV100_HALF_MODE(1 << 3)) {
	rdev->mc.vram_width = 32;
} else {
	rdev->mc.vram_width = 64;
}
if (rdev->flags & RADEON_SINGLE_CRTC) {
	rdev->mc.vram_width /= 4;
	rdev->mc.vram_is_ddr = true1;
}
} else if (rdev->family <= CHIP_RV280) {
tmp = RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0);
if (tmp & RADEON_MEM_NUM_CHANNELS_MASK0x01) {
	rdev->mc.vram_width = 128;
} else {
	rdev->mc.vram_width = 64;
}
} else {
/* newer IGPs */
rdev->mc.vram_width = 128;
}
2739}

2741static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2742{
u32 aper_size;
u8 byte;

aper_size = RREG32(RADEON_CONFIG_APER_SIZE)r100_mm_rreg(rdev, (0x0108), 0);

/* Set HDP_APER_CNTL only on cards that are known not to be broken,
* that is has the 2nd generation multifunction PCI interface
*/
if (rdev->family == CHIP_RV280 ||
   rdev->family >= CHIP_RV350) {
WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x0130), 0); tmp_ &=
 (~(1 << 23)); tmp_ |= (((1 << 23)) & ~(~(1 <<
 23))); r100_mm_wreg(rdev, (0x0130), (tmp_), 0); } while (0)
       ~RADEON_HDP_APER_CNTL)do { uint32_t tmp_ = r100_mm_rreg(rdev, (0x0130), 0); tmp_ &=
 (~(1 << 23)); tmp_ |= (((1 << 23)) & ~(~(1 <<
 23))); r100_mm_wreg(rdev, (0x0130), (tmp_), 0); } while (0);
DRM_INFO("Generation 2 PCI interface, using max accessible memory\n")printk("\0016" "[" "drm" "] " "Generation 2 PCI interface, using max accessible memory\n"
);
return aper_size * 2;
}

/* Older cards have all sorts of funny issues to deal with. First
* check if it's a multifunction card by reading the PCI config
* header type... Limit those to one aperture size
*/
pci_read_config_byte(rdev->pdev, 0xe, &byte);
if (byte & 0x80) {
DRM_INFO("Generation 1 PCI interface in multifunction mode\n")printk("\0016" "[" "drm" "] " "Generation 1 PCI interface in multifunction mode\n"
);
DRM_INFO("Limiting VRAM to one aperture\n")printk("\0016" "[" "drm" "] " "Limiting VRAM to one aperture\n"
);
return aper_size;
}

/* Single function older card. We read HDP_APER_CNTL to see how the BIOS
* have set it up. We don't write this as it's broken on some ASICs but
* we expect the BIOS to have done the right thing (might be too optimistic...)
*/
if (RREG32(RADEON_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x0130), 0) & RADEON_HDP_APER_CNTL(1 << 23))
return aper_size * 2;
return aper_size;
2777}

2779void r100_vram_init_sizes(struct radeon_device *rdev)
2780{
u64 config_aper_size;

/* work out accessible VRAM */
rdev->mc.aper_base = rdev->fb_aper_offset;
rdev->mc.aper_size = rdev->fb_aper_size;
rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
/* FIXME we don't use the second aperture yet when we could use it */
if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
rdev->mc.visible_vram_size = rdev->mc.aper_size;
config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE)r100_mm_rreg(rdev, (0x0108), 0);
if (rdev->flags & RADEON_IS_IGP) {
uint32_t tom;
/* read NB_TOM to get the amount of ram stolen for the GPU */
tom = RREG32(RADEON_NB_TOM)r100_mm_rreg(rdev, (0x15c), 0);
rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size)r100_mm_wreg(rdev, (0x00f8), (rdev->mc.real_vram_size), 0);
rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
} else {
rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE)r100_mm_rreg(rdev, (0x00f8), 0);
/* Some production boards of m6 will report 0
 * if it's 8 MB
 */
if (rdev->mc.real_vram_size == 0) {
	rdev->mc.real_vram_size = 8192 * 1024;
	WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size)r100_mm_wreg(rdev, (0x00f8), (rdev->mc.real_vram_size), 0);
}
/* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
 * Novell bug 204882 + along with lots of ubuntu ones
 */
if (rdev->mc.aper_size > config_aper_size)
	config_aper_size = rdev->mc.aper_size;

if (config_aper_size > rdev->mc.real_vram_size)
	rdev->mc.mc_vram_size = config_aper_size;
else
	rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
}
2818}

2820void r100_vga_set_state(struct radeon_device *rdev, bool_Bool state)
2821{
uint32_t temp;

temp = RREG32(RADEON_CONFIG_CNTL)r100_mm_rreg(rdev, (0x00e0), 0);
if (!state) {
temp &= ~RADEON_CFG_VGA_RAM_EN(1 << 8);
temp |= RADEON_CFG_VGA_IO_DIS(1 << 9);
} else {
temp &= ~RADEON_CFG_VGA_IO_DIS(1 << 9);
}
WREG32(RADEON_CONFIG_CNTL, temp)r100_mm_wreg(rdev, (0x00e0), (temp), 0);
2832}

2834static void r100_mc_init(struct radeon_device *rdev)
2835{
u64 base;

r100_vram_get_type(rdev);
r100_vram_init_sizes(rdev);
base = rdev->mc.aper_base;
if (rdev->flags & RADEON_IS_IGP)
base = (RREG32(RADEON_NB_TOM)r100_mm_rreg(rdev, (0x15c), 0) & 0xffff) << 16;
radeon_vram_location(rdev, &rdev->mc, base);
rdev->mc.gtt_base_align = 0;
if (!(rdev->flags & RADEON_IS_AGP))
radeon_gtt_location(rdev, &rdev->mc);
radeon_update_bandwidth_info(rdev);
2848}


2851/*
* Indirect registers accessor
*/
2854void r100_pll_errata_after_index(struct radeon_device *rdev)
2855{
if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
(void)RREG32(RADEON_CLOCK_CNTL_DATA)r100_mm_rreg(rdev, (0x000c), 0);
(void)RREG32(RADEON_CRTC_GEN_CNTL)r100_mm_rreg(rdev, (0x0050), 0);
}
2860}

2862static void r100_pll_errata_after_data(struct radeon_device *rdev)
2863{
/* This workarounds is necessary on RV100, RS100 and RS200 chips
* or the chip could hang on a subsequent access
*/
if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
mdelay(5);
}

/* This function is required to workaround a hardware bug in some (all?)
* revisions of the R300.  This workaround should be called after every
* CLOCK_CNTL_INDEX register access.  If not, register reads afterward
* may not be correct.
*/
if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
uint32_t save, tmp;

save = RREG32(RADEON_CLOCK_CNTL_INDEX)r100_mm_rreg(rdev, (0x0008), 0);
tmp = save & ~(0x3f | RADEON_PLL_WR_EN(1 << 7));
WREG32(RADEON_CLOCK_CNTL_INDEX, tmp)r100_mm_wreg(rdev, (0x0008), (tmp), 0);
tmp = RREG32(RADEON_CLOCK_CNTL_DATA)r100_mm_rreg(rdev, (0x000c), 0);
WREG32(RADEON_CLOCK_CNTL_INDEX, save)r100_mm_wreg(rdev, (0x0008), (save), 0);
}
2885}

2887uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2888{
unsigned long flags;
uint32_t data;

spin_lock_irqsave(&rdev->pll_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->pll_idx_lock); } while
 (0);
WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f)iowrite8(reg & 0x3f, (rdev->rmmio) + (0x0008));
r100_pll_errata_after_index(rdev);
data = RREG32(RADEON_CLOCK_CNTL_DATA)r100_mm_rreg(rdev, (0x000c), 0);
r100_pll_errata_after_data(rdev);
spin_unlock_irqrestore(&rdev->pll_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->pll_idx_lock); } while
 (0);
return data;
2899}

2901void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2902{
unsigned long flags;

spin_lock_irqsave(&rdev->pll_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->pll_idx_lock); } while
 (0);
WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN))iowrite8(((reg & 0x3f) | (1 << 7)), (rdev->rmmio
) + (0x0008));
r100_pll_errata_after_index(rdev);
WREG32(RADEON_CLOCK_CNTL_DATA, v)r100_mm_wreg(rdev, (0x000c), (v), 0);
r100_pll_errata_after_data(rdev);
spin_unlock_irqrestore(&rdev->pll_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->pll_idx_lock); } while
 (0);
2911}

2913static void r100_set_safe_registers(struct radeon_device *rdev)
2914{
if (ASIC_IS_RN50(rdev)((rdev->pdev->device == 0x515e) || (rdev->pdev->device
 == 0x5969))) {
rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm)(sizeof((rn50_reg_safe_bm)) / sizeof((rn50_reg_safe_bm)[0]));
} else if (rdev->family < CHIP_R200) {
rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm)(sizeof((r100_reg_safe_bm)) / sizeof((r100_reg_safe_bm)[0]));
} else {
r200_set_safe_registers(rdev);
}
2924}

2926/*
* Debugfs info
*/
2929#if defined(CONFIG_DEBUG_FS)
2930static int r100_debugfs_rbbm_info_show(struct seq_file *m, void *unused)
2931{
struct radeon_device *rdev = (struct radeon_device *)m->private;
uint32_t reg, value;
unsigned i;

seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS)r100_mm_rreg(rdev, (0x0e40), 0));
seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C)r100_mm_rreg(rdev, (0xE7C), 0));
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)r100_mm_rreg(rdev, (0x7C0), 0));
for (i = 0; i < 64; i++) {
WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100)r100_mm_wreg(rdev, (0xE70), (i | 0x100), 0);
reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA)r100_mm_rreg(rdev, (0xE74), 0) - 1) >> 2;
WREG32(RADEON_RBBM_CMDFIFO_ADDR, i)r100_mm_wreg(rdev, (0xE70), (i), 0);
value = RREG32(RADEON_RBBM_CMDFIFO_DATA)r100_mm_rreg(rdev, (0xE74), 0);
seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
}
return 0;
2947}

2949static int r100_debugfs_cp_ring_info_show(struct seq_file *m, void *unused)
2950{
struct radeon_device *rdev = (struct radeon_device *)m->private;
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];
uint32_t rdp, wdp;
unsigned count, i, j;

radeon_ring_free_size(rdev, ring);
rdp = RREG32(RADEON_CP_RB_RPTR)r100_mm_rreg(rdev, (0x0710), 0);
wdp = RREG32(RADEON_CP_RB_WPTR)r100_mm_rreg(rdev, (0x0714), 0);
count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)r100_mm_rreg(rdev, (0x7C0), 0));
seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
seq_printf(m, "%u dwords in ring\n", count);
if (ring->ready) {
for (j = 0; j <= count; j++) {
	i = (rdp + j) & ring->ptr_mask;
	seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
}
}
return 0;
2972}


2975static int r100_debugfs_cp_csq_fifo_show(struct seq_file *m, void *unused)
2976{
struct radeon_device *rdev = (struct radeon_device *)m->private;
uint32_t csq_stat, csq2_stat, tmp;
unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
unsigned i;

seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)r100_mm_rreg(rdev, (0x7C0), 0));
seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE)r100_mm_rreg(rdev, (0x0744), 0));
csq_stat = RREG32(RADEON_CP_CSQ_STAT)r100_mm_rreg(rdev, (0x07f8), 0);
csq2_stat = RREG32(RADEON_CP_CSQ2_STAT)r100_mm_rreg(rdev, (0x07fc), 0);
r_rptr = (csq_stat >> 0) & 0x3ff;
r_wptr = (csq_stat >> 10) & 0x3ff;
ib1_rptr = (csq_stat >> 20) & 0x3ff;
ib1_wptr = (csq2_stat >> 0) & 0x3ff;
ib2_rptr = (csq2_stat >> 10) & 0x3ff;
ib2_wptr = (csq2_stat >> 20) & 0x3ff;
seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
seq_printf(m, "Ring rptr %u\n", r_rptr);
seq_printf(m, "Ring wptr %u\n", r_wptr);
seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
/* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
* 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
seq_printf(m, "Ring fifo:\n");
for (i = 0; i < 256; i++) {
WREG32(RADEON_CP_CSQ_ADDR, i << 2)r100_mm_wreg(rdev, (0x07f0), (i << 2), 0);
tmp = RREG32(RADEON_CP_CSQ_DATA)r100_mm_rreg(rdev, (0x07f4), 0);
seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
}
seq_printf(m, "Indirect1 fifo:\n");
for (i = 256; i <= 512; i++) {
WREG32(RADEON_CP_CSQ_ADDR, i << 2)r100_mm_wreg(rdev, (0x07f0), (i << 2), 0);
tmp = RREG32(RADEON_CP_CSQ_DATA)r100_mm_rreg(rdev, (0x07f4), 0);
seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
}
seq_printf(m, "Indirect2 fifo:\n");
for (i = 640; i < ib1_wptr; i++) {
WREG32(RADEON_CP_CSQ_ADDR, i << 2)r100_mm_wreg(rdev, (0x07f0), (i << 2), 0);
tmp = RREG32(RADEON_CP_CSQ_DATA)r100_mm_rreg(rdev, (0x07f4), 0);
seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
}
return 0;
3021}

3023static int r100_debugfs_mc_info_show(struct seq_file *m, void *unused)
3024{
struct radeon_device *rdev = (struct radeon_device *)m->private;
uint32_t tmp;

tmp = RREG32(RADEON_CONFIG_MEMSIZE)r100_mm_rreg(rdev, (0x00f8), 0);
seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
tmp = RREG32(RADEON_MC_FB_LOCATION)r100_mm_rreg(rdev, (0x0148), 0);
seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
tmp = RREG32(RADEON_BUS_CNTL)r100_mm_rreg(rdev, (0x0030), 0);
seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
tmp = RREG32(RADEON_MC_AGP_LOCATION)r100_mm_rreg(rdev, (0x014c), 0);
seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
tmp = RREG32(RADEON_AGP_BASE)r100_mm_rreg(rdev, (0x0170), 0);
seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
tmp = RREG32(RADEON_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x0130), 0);
seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
tmp = RREG32(0x01D0)r100_mm_rreg(rdev, (0x01D0), 0);
seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
tmp = RREG32(RADEON_AIC_LO_ADDR)r100_mm_rreg(rdev, (0x01dc), 0);
seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
tmp = RREG32(RADEON_AIC_HI_ADDR)r100_mm_rreg(rdev, (0x01e0), 0);
seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
tmp = RREG32(0x01E4)r100_mm_rreg(rdev, (0x01E4), 0);
seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
return 0;
3049}

3051DEFINE_SHOW_ATTRIBUTE(r100_debugfs_rbbm_info);
3052DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_ring_info);
3053DEFINE_SHOW_ATTRIBUTE(r100_debugfs_cp_csq_fifo);
3054DEFINE_SHOW_ATTRIBUTE(r100_debugfs_mc_info);

3056#endif

3058void  r100_debugfs_rbbm_init(struct radeon_device *rdev)
3059{
3060#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;

debugfs_create_file("r100_rbbm_info", 0444, root, rdev,ERR_PTR(-78)
	    &r100_debugfs_rbbm_info_fops)ERR_PTR(-78);
3065#endif
3066}

3068void r100_debugfs_cp_init(struct radeon_device *rdev)
3069{
3070#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;

debugfs_create_file("r100_cp_ring_info", 0444, root, rdev,ERR_PTR(-78)
	    &r100_debugfs_cp_ring_info_fops)ERR_PTR(-78);
debugfs_create_file("r100_cp_csq_fifo", 0444, root, rdev,ERR_PTR(-78)
	    &r100_debugfs_cp_csq_fifo_fops)ERR_PTR(-78);
3077#endif
3078}

3080void  r100_debugfs_mc_info_init(struct radeon_device *rdev)
3081{
3082#if defined(CONFIG_DEBUG_FS)
struct dentry *root = rdev->ddev->primary->debugfs_root;

debugfs_create_file("r100_mc_info", 0444, root, rdev,ERR_PTR(-78)
	    &r100_debugfs_mc_info_fops)ERR_PTR(-78);
3087#endif
3088}

3090int r100_set_surface_reg(struct radeon_device *rdev, int reg,
	 uint32_t tiling_flags, uint32_t pitch,
	 uint32_t offset, uint32_t obj_size)
3093{
int surf_index = reg * 16;
int flags = 0;

if (rdev->family <= CHIP_RS200) {
if ((tiling_flags & (RADEON_TILING_MACRO0x1|RADEON_TILING_MICRO0x2))
		 == (RADEON_TILING_MACRO0x1|RADEON_TILING_MICRO0x2))
	flags |= RADEON_SURF_TILE_COLOR_BOTH(1 << 16);
if (tiling_flags & RADEON_TILING_MACRO0x1)
	flags |= RADEON_SURF_TILE_COLOR_MACRO(0 << 16);
/* setting pitch to 0 disables tiling */
if ((tiling_flags & (RADEON_TILING_MACRO0x1|RADEON_TILING_MICRO0x2))
		== 0)
	pitch = 0;
} else if (rdev->family <= CHIP_RV280) {
if (tiling_flags & (RADEON_TILING_MACRO0x1))
	flags |= R200_SURF_TILE_COLOR_MACRO(1 << 16);
if (tiling_flags & RADEON_TILING_MICRO0x2)
	flags |= R200_SURF_TILE_COLOR_MICRO(2 << 16);
} else {
if (tiling_flags & RADEON_TILING_MACRO0x1)
	flags |= R300_SURF_TILE_MACRO(1<<16);
if (tiling_flags & RADEON_TILING_MICRO0x2)
	flags |= R300_SURF_TILE_MICRO(2<<16);
}

if (tiling_flags & RADEON_TILING_SWAP_16BIT0x4)
flags |= RADEON_SURF_AP0_SWP_16BPP(1 << 20) | RADEON_SURF_AP1_SWP_16BPP(1 << 22);
if (tiling_flags & RADEON_TILING_SWAP_32BIT0x8)
flags |= RADEON_SURF_AP0_SWP_32BPP(1 << 21) | RADEON_SURF_AP1_SWP_32BPP(1 << 23);

/* r100/r200 divide by 16 */
if (rdev->family < CHIP_R300)
flags |= pitch / 16;
else
flags |= pitch / 8;


DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1)___drm_dbg(((void *)0), DRM_UT_KMS, "writing surface %d %d %x %x\n"
, reg, flags, offset, offset+obj_size-1);
WREG32(RADEON_SURFACE0_INFO + surf_index, flags)r100_mm_wreg(rdev, (0x0b0c + surf_index), (flags), 0);
WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset)r100_mm_wreg(rdev, (0x0b04 + surf_index), (offset), 0);
WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1)r100_mm_wreg(rdev, (0x0b08 + surf_index), (offset + obj_size -
 1), 0);
return 0;
3136}

3138void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3139{
int surf_index = reg * 16;
WREG32(RADEON_SURFACE0_INFO + surf_index, 0)r100_mm_wreg(rdev, (0x0b0c + surf_index), (0), 0);
3142}

3144void r100_bandwidth_update(struct radeon_device *rdev)
3145{
fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
fixed20_12 crit_point_ff = {0};
uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
fixed20_12 memtcas_ff[8] = {
dfixed_init(1){ .full = (u32)((((1)) << 12)) },
dfixed_init(2){ .full = (u32)((((2)) << 12)) },
dfixed_init(3){ .full = (u32)((((3)) << 12)) },
dfixed_init(0){ .full = (u32)((((0)) << 12)) },
dfixed_init_half(1){ .full = (u32)((((1)) << 12) + 2048) },
dfixed_init_half(2){ .full = (u32)((((2)) << 12) + 2048) },
dfixed_init(0){ .full = (u32)((((0)) << 12)) },
};
fixed20_12 memtcas_rs480_ff[8] = {
dfixed_init(0){ .full = (u32)((((0)) << 12)) },
dfixed_init(1){ .full = (u32)((((1)) << 12)) },
dfixed_init(2){ .full = (u32)((((2)) << 12)) },
dfixed_init(3){ .full = (u32)((((3)) << 12)) },
dfixed_init(0){ .full = (u32)((((0)) << 12)) },
dfixed_init_half(1){ .full = (u32)((((1)) << 12) + 2048) },
dfixed_init_half(2){ .full = (u32)((((2)) << 12) + 2048) },
dfixed_init_half(3){ .full = (u32)((((3)) << 12) + 2048) },
};
fixed20_12 memtcas2_ff[8] = {
dfixed_init(0){ .full = (u32)((((0)) << 12)) },
dfixed_init(1){ .full = (u32)((((1)) << 12)) },
dfixed_init(2){ .full = (u32)((((2)) << 12)) },
dfixed_init(3){ .full = (u32)((((3)) << 12)) },
dfixed_init(4){ .full = (u32)((((4)) << 12)) },
dfixed_init(5){ .full = (u32)((((5)) << 12)) },
dfixed_init(6){ .full = (u32)((((6)) << 12)) },
dfixed_init(7){ .full = (u32)((((7)) << 12)) },
};
fixed20_12 memtrbs[8] = {
dfixed_init(1){ .full = (u32)((((1)) << 12)) },
dfixed_init_half(1){ .full = (u32)((((1)) << 12) + 2048) },
dfixed_init(2){ .full = (u32)((((2)) << 12)) },
dfixed_init_half(2){ .full = (u32)((((2)) << 12) + 2048) },
dfixed_init(3){ .full = (u32)((((3)) << 12)) },
dfixed_init_half(3){ .full = (u32)((((3)) << 12) + 2048) },
dfixed_init(4){ .full = (u32)((((4)) << 12)) },
dfixed_init_half(4){ .full = (u32)((((4)) << 12) + 2048) }
};
fixed20_12 memtrbs_r4xx[8] = {
dfixed_init(4){ .full = (u32)((((4)) << 12)) },
dfixed_init(5){ .full = (u32)((((5)) << 12)) },
dfixed_init(6){ .full = (u32)((((6)) << 12)) },
dfixed_init(7){ .full = (u32)((((7)) << 12)) },
dfixed_init(8){ .full = (u32)((((8)) << 12)) },
dfixed_init(9){ .full = (u32)((((9)) << 12)) },
dfixed_init(10){ .full = (u32)((((10)) << 12)) },
dfixed_init(11){ .full = (u32)((((11)) << 12)) }
};
fixed20_12 min_mem_eff;
fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
fixed20_12 cur_latency_mclk, cur_latency_sclk;
fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate = {0},
disp_drain_rate2, read_return_rate;
fixed20_12 time_disp1_drop_priority;
int c;
int cur_size = 16;       /* in octawords */
int critical_point = 0, critical_point2;
3209/* 	uint32_t read_return_rate, time_disp1_drop_priority; */
int stop_req, max_stop_req;
struct drm_display_mode *mode1 = NULL((void *)0);
struct drm_display_mode *mode2 = NULL((void *)0);
uint32_t pixel_bytes1 = 0;
uint32_t pixel_bytes2 = 0;

/* Guess line buffer size to be 8192 pixels */
u32 lb_size = 8192;

if (!rdev->mode_info.mode_config_initialized)
return;

radeon_update_display_priority(rdev);

if (rdev->mode_info.crtcs[0]->base.enabled) {
const struct drm_framebuffer *fb =
	rdev->mode_info.crtcs[0]->base.primary->fb;

mode1 = &rdev->mode_info.crtcs[0]->base.mode;
pixel_bytes1 = fb->format->cpp[0];
}
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
if (rdev->mode_info.crtcs[1]->base.enabled) {
	const struct drm_framebuffer *fb =
		rdev->mode_info.crtcs[1]->base.primary->fb;

	mode2 = &rdev->mode_info.crtcs[1]->base.mode;
	pixel_bytes2 = fb->format->cpp[0];
}
}

min_mem_eff.full = dfixed_const_8(0)(u32)(((0) << 12) + 3277);
/* get modes */
if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480))) {
uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER)r100_mm_rreg(rdev, (0x180), 0);
mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK0xf << R300_MC_DISP1R_INIT_LAT_SHIFT12);
mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK0xf << R300_MC_DISP0R_INIT_LAT_SHIFT8);
/* check crtc enables */
if (mode2)
	mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT12);
if (mode1)
	mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT8);
WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer)r100_mm_wreg(rdev, (0x180), (mc_init_misc_lat_timer), 0);
}

/*
* determine is there is enough bw for current mode
*/
sclk_ff = rdev->pm.sclk;
mclk_ff = rdev->pm.mclk;

temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
temp_ff.full = dfixed_const(temp)(u32)(((temp) << 12));
mem_bw.full = dfixed_mul(mclk_ff, temp_ff)((u64)((u64)(mclk_ff).full * (temp_ff).full + 2048) >> 12
);

pix_clk.full = 0;
pix_clk2.full = 0;
peak_disp_bw.full = 0;
if (mode1) {
temp_ff.full = dfixed_const(1000)(u32)(((1000) << 12));
pix_clk.full = dfixed_const(mode1->clock)(u32)(((mode1->clock) << 12)); /* convert to fixed point */
pix_clk.full = dfixed_div(pix_clk, temp_ff);
temp_ff.full = dfixed_const(pixel_bytes1)(u32)(((pixel_bytes1) << 12));
peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff)((u64)((u64)(pix_clk).full * (temp_ff).full + 2048) >> 12
);
}
if (mode2) {
temp_ff.full = dfixed_const(1000)(u32)(((1000) << 12));
pix_clk2.full = dfixed_const(mode2->clock)(u32)(((mode2->clock) << 12)); /* convert to fixed point */
pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
temp_ff.full = dfixed_const(pixel_bytes2)(u32)(((pixel_bytes2) << 12));
peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff)((u64)((u64)(pix_clk2).full * (temp_ff).full + 2048) >>
 12);
}

mem_bw.full = dfixed_mul(mem_bw, min_mem_eff)((u64)((u64)(mem_bw).full * (min_mem_eff).full + 2048) >>
 12);
if (peak_disp_bw.full >= mem_bw.full) {
DRM_ERROR("You may not have enough display bandwidth for current mode\n"__drm_err("You may not have enough display bandwidth for current mode\n"
 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"
)
	  "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n")__drm_err("You may not have enough display bandwidth for current mode\n"
 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"
);
}

/*  Get values from the EXT_MEM_CNTL register...converting its contents. */
temp = RREG32(RADEON_MEM_TIMING_CNTL)r100_mm_rreg(rdev, (0x0144), 0);
if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
mem_trcd = ((temp >> 2) & 0x3) + 1;
mem_trp  = ((temp & 0x3)) + 1;
mem_tras = ((temp & 0x70) >> 4) + 1;
} else if (rdev->family == CHIP_R300 ||
   rdev->family == CHIP_R350) { /* r300, r350 */
mem_trcd = (temp & 0x7) + 1;
mem_trp = ((temp >> 8) & 0x7) + 1;
mem_tras = ((temp >> 11) & 0xf) + 4;
} else if (rdev->family == CHIP_RV350 ||
   rdev->family == CHIP_RV380) {
/* rv3x0 */
mem_trcd = (temp & 0x7) + 3;
mem_trp = ((temp >> 8) & 0x7) + 3;
mem_tras = ((temp >> 11) & 0xf) + 6;
} else if (rdev->family == CHIP_R420 ||
   rdev->family == CHIP_R423 ||
   rdev->family == CHIP_RV410) {
/* r4xx */
mem_trcd = (temp & 0xf) + 3;
if (mem_trcd > 15)
	mem_trcd = 15;
mem_trp = ((temp >> 8) & 0xf) + 3;
if (mem_trp > 15)
	mem_trp = 15;
mem_tras = ((temp >> 12) & 0x1f) + 6;
if (mem_tras > 31)
	mem_tras = 31;
} else { /* RV200, R200 */
mem_trcd = (temp & 0x7) + 1;
mem_trp = ((temp >> 8) & 0x7) + 1;
mem_tras = ((temp >> 12) & 0xf) + 4;
}
/* convert to FF */
trcd_ff.full = dfixed_const(mem_trcd)(u32)(((mem_trcd) << 12));
trp_ff.full = dfixed_const(mem_trp)(u32)(((mem_trp) << 12));
tras_ff.full = dfixed_const(mem_tras)(u32)(((mem_tras) << 12));

/* Get values from the MEM_SDRAM_MODE_REG register...converting its */
temp = RREG32(RADEON_MEM_SDRAM_MODE_REG)r100_mm_rreg(rdev, (0x0158), 0);
data = (temp & (7 << 20)) >> 20;
if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
if (rdev->family == CHIP_RS480) /* don't think rs400 */
	tcas_ff = memtcas_rs480_ff[data];
else
	tcas_ff = memtcas_ff[data];
} else
tcas_ff = memtcas2_ff[data];

if (rdev->family == CHIP_RS400 ||
   rdev->family == CHIP_RS480) {
/* extra cas latency stored in bits 23-25 0-4 clocks */
data = (temp >> 23) & 0x7;
if (data < 5)
	tcas_ff.full += dfixed_const(data)(u32)(((data) << 12));
}

if (ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480)) && !(rdev->flags & RADEON_IS_IGP)) {
/* on the R300, Tcas is included in Trbs.
 */
temp = RREG32(RADEON_MEM_CNTL)r100_mm_rreg(rdev, (0x0140), 0);
data = (R300_MEM_NUM_CHANNELS_MASK0x03 & temp);
if (data == 1) {
	if (R300_MEM_USE_CD_CH_ONLY(1 << 2) & temp) {
		temp = RREG32(R300_MC_IND_INDEX)r100_mm_rreg(rdev, (0x01f8), 0);
		temp &= ~R300_MC_IND_ADDR_MASK0x3f;
		temp |= R300_MC_READ_CNTL_CD_mcind0x24;
		WREG32(R300_MC_IND_INDEX, temp)r100_mm_wreg(rdev, (0x01f8), (temp), 0);
		temp = RREG32(R300_MC_IND_DATA)r100_mm_rreg(rdev, (0x01fc), 0);
		data = (R300_MEM_RBS_POSITION_C_MASK0x03 & temp);
	} else {
		temp = RREG32(R300_MC_READ_CNTL_AB)r100_mm_rreg(rdev, (0x017c), 0);
		data = (R300_MEM_RBS_POSITION_A_MASK0x03 & temp);
	}
} else {
	temp = RREG32(R300_MC_READ_CNTL_AB)r100_mm_rreg(rdev, (0x017c), 0);
	data = (R300_MEM_RBS_POSITION_A_MASK0x03 & temp);
}
if (rdev->family == CHIP_RV410 ||
    rdev->family == CHIP_R420 ||
    rdev->family == CHIP_R423)
	trbs_ff = memtrbs_r4xx[data];
else
	trbs_ff = memtrbs[data];
tcas_ff.full += trbs_ff.full;
}

sclk_eff_ff.full = sclk_ff.full;

if (rdev->flags & RADEON_IS_AGP) {
fixed20_12 agpmode_ff;
agpmode_ff.full = dfixed_const(radeon_agpmode)(u32)(((radeon_agpmode) << 12));
temp_ff.full = dfixed_const_666(16)(u32)(((16) << 12) + 2731);
sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff)((u64)((u64)(agpmode_ff).full * (temp_ff).full + 2048) >>
 12);
}
/* TODO PCIE lanes may affect this - agpmode == 16?? */

if (ASIC_IS_R300(rdev)((rdev->family == CHIP_R300) || (rdev->family == CHIP_RV350
) || (rdev->family == CHIP_R350) || (rdev->family == CHIP_RV380
) || (rdev->family == CHIP_R420) || (rdev->family == CHIP_R423
) || (rdev->family == CHIP_RV410) || (rdev->family == CHIP_RS400
) || (rdev->family == CHIP_RS480))) {
sclk_delay_ff.full = dfixed_const(250)(u32)(((250) << 12));
} else {
if ((rdev->family == CHIP_RV100) ||
    rdev->flags & RADEON_IS_IGP) {
	if (rdev->mc.vram_is_ddr)
		sclk_delay_ff.full = dfixed_const(41)(u32)(((41) << 12));
	else
		sclk_delay_ff.full = dfixed_const(33)(u32)(((33) << 12));
} else {
	if (rdev->mc.vram_width == 128)
		sclk_delay_ff.full = dfixed_const(57)(u32)(((57) << 12));
	else
		sclk_delay_ff.full = dfixed_const(41)(u32)(((41) << 12));
}
}

mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);

if (rdev->mc.vram_is_ddr) {
if (rdev->mc.vram_width == 32) {
	k1.full = dfixed_const(40)(u32)(((40) << 12));
	c  = 3;
} else {
	k1.full = dfixed_const(20)(u32)(((20) << 12));
	c  = 1;
}
} else {
k1.full = dfixed_const(40)(u32)(((40) << 12));
c  = 3;
}

temp_ff.full = dfixed_const(2)(u32)(((2) << 12));
mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff)((u64)((u64)(trcd_ff).full * (temp_ff).full + 2048) >> 12
);
temp_ff.full = dfixed_const(c)(u32)(((c) << 12));
mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff)((u64)((u64)(tcas_ff).full * (temp_ff).full + 2048) >> 12
);
temp_ff.full = dfixed_const(4)(u32)(((4) << 12));
mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff)((u64)((u64)(tras_ff).full * (temp_ff).full + 2048) >> 12
);
mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff)((u64)((u64)(trp_ff).full * (temp_ff).full + 2048) >> 12
);
mc_latency_mclk.full += k1.full;

mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);

/*
 HW cursor time assuming worst case of full size colour cursor.
*/
temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))))(u32)((((2 * (cur_size - (rdev->mc.vram_is_ddr + 1)))) <<
 12));
temp_ff.full += trcd_ff.full;
if (temp_ff.full < tras_ff.full)
temp_ff.full = tras_ff.full;
cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);

temp_ff.full = dfixed_const(cur_size)(u32)(((cur_size) << 12));
cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
/*
 Find the total latency for the display data.
*/
disp_latency_overhead.full = dfixed_const(8)(u32)(((8) << 12));
disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;

if (mc_latency_mclk.full > mc_latency_sclk.full)
disp_latency.full = mc_latency_mclk.full;
else
disp_latency.full = mc_latency_sclk.full;

/* setup Max GRPH_STOP_REQ default value */
if (ASIC_IS_RV100(rdev)((rdev->family == CHIP_RV100) || (rdev->family == CHIP_RV200
) || (rdev->family == CHIP_RS100) || (rdev->family == CHIP_RS200
) || (rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280
) || (rdev->family == CHIP_RS300)))
max_stop_req = 0x5c;
else
max_stop_req = 0x7c;

if (mode1) {
/*  CRTC1
    Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
    GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
*/
stop_req = mode1->hdisplay * pixel_bytes1 / 16;

if (stop_req > max_stop_req)
	stop_req = max_stop_req;

/*
  Find the drain rate of the display buffer.
*/
temp_ff.full = dfixed_const((16/pixel_bytes1))(u32)((((16/pixel_bytes1)) << 12));
disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);

/*
  Find the critical point of the display buffer.
*/
crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency)((u64)((u64)(disp_drain_rate).full * (disp_latency).full + 2048
) >> 12);
crit_point_ff.full += dfixed_const_half(0)(u32)(((0) << 12) + 2048);

critical_point = dfixed_trunc(crit_point_ff)((crit_point_ff).full >> 12);

if (rdev->disp_priority == 2) {
	critical_point = 0;
}

/*
  The critical point should never be above max_stop_req-4.  Setting
  GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
*/
if (max_stop_req - critical_point < 4)
	critical_point = 0;

if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
	/* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
	critical_point = 0x10;
}

temp = RREG32(RADEON_GRPH_BUFFER_CNTL)r100_mm_rreg(rdev, (0x02f0), 0);
temp &= ~(RADEON_GRPH_STOP_REQ_MASK(0x7f<<8));
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT8);
temp &= ~(RADEON_GRPH_START_REQ_MASK(0x7f));
if ((rdev->family == CHIP_R350) &&
    (stop_req > 0x15)) {
	stop_req -= 0x10;
}
temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT0);
temp |= RADEON_GRPH_BUFFER_SIZE(1<<29);
temp &= ~(RADEON_GRPH_CRITICAL_CNTL(1<<28)   |
	  RADEON_GRPH_CRITICAL_AT_SOF(1<<30) |
	  RADEON_GRPH_STOP_CNTL(1<<31));
/*
  Write the result into the register.
*/
WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |r100_mm_wreg(rdev, (0x02f0), (((temp & ~(0x7f<<16))
 | (critical_point << 16))), 0)
				       (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)))r100_mm_wreg(rdev, (0x02f0), (((temp & ~(0x7f<<16))
 | (critical_point << 16))), 0);

3521#if 0
if ((rdev->family == CHIP_RS400) ||
    (rdev->family == CHIP_RS480)) {
	/* attempt to program RS400 disp regs correctly ??? */
	temp = RREG32(RS400_DISP1_REG_CNTL)r100_mm_rreg(rdev, (RS400_DISP1_REG_CNTL), 0);
	temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK0x3ff |
		  RS400_DISP1_STOP_REQ_LEVEL_MASK0x3ff);
	WREG32(RS400_DISP1_REQ_CNTL1, (temp |r100_mm_wreg(rdev, (0xe3c), ((temp | (critical_point <<
 0) | (critical_point << 12))), 0)
				       (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |r100_mm_wreg(rdev, (0xe3c), ((temp | (critical_point <<
 0) | (critical_point << 12))), 0)
				       (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)))r100_mm_wreg(rdev, (0xe3c), ((temp | (critical_point <<
 0) | (critical_point << 12))), 0);
	temp = RREG32(RS400_DMIF_MEM_CNTL1)r100_mm_rreg(rdev, (0xe38), 0);
	temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK0x3ff |
		  RS400_DISP1_CRITICAL_POINT_STOP_MASK0x3ff);
	WREG32(RS400_DMIF_MEM_CNTL1, (temp |r100_mm_wreg(rdev, (0xe38), ((temp | (critical_point <<
 12) | (critical_point << 22))), 0)
				      (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |r100_mm_wreg(rdev, (0xe38), ((temp | (critical_point <<
 12) | (critical_point << 22))), 0)
				      (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)))r100_mm_wreg(rdev, (0xe38), ((temp | (critical_point <<
 12) | (critical_point << 22))), 0);
}
3538#endif

DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",___drm_dbg(((void *)0), DRM_UT_KMS, "GRPH_BUFFER_CNTL from to %x\n"
, (unsigned int)r100_mm_rreg(rdev, (0x02f0), 0))
	  /* 	  (unsigned int)info->SavedReg->grph_buffer_cntl, */___drm_dbg(((void *)0), DRM_UT_KMS, "GRPH_BUFFER_CNTL from to %x\n"
, (unsigned int)r100_mm_rreg(rdev, (0x02f0), 0))
	  (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL))___drm_dbg(((void *)0), DRM_UT_KMS, "GRPH_BUFFER_CNTL from to %x\n"
, (unsigned int)r100_mm_rreg(rdev, (0x02f0), 0));
}

if (mode2) {
u32 grph2_cntl;
stop_req = mode2->hdisplay * pixel_bytes2 / 16;

if (stop_req > max_stop_req)
	stop_req = max_stop_req;

/*
  Find the drain rate of the display buffer.
*/
temp_ff.full = dfixed_const((16/pixel_bytes2))(u32)((((16/pixel_bytes2)) << 12));
disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);

grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL)r100_mm_rreg(rdev, (0x03f0), 0);
grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK(0x7f<<8));
grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT8);
grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK(0x7f));
if ((rdev->family == CHIP_R350) &&
    (stop_req > 0x15)) {
	stop_req -= 0x10;
}
grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT0);
grph2_cntl |= RADEON_GRPH_BUFFER_SIZE(1<<29);
grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL(1<<28)   |
	  RADEON_GRPH_CRITICAL_AT_SOF(1<<30) |
	  RADEON_GRPH_STOP_CNTL(1<<31));

if ((rdev->family == CHIP_RS100) ||
    (rdev->family == CHIP_RS200))
	critical_point2 = 0;
else {
	temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
	temp_ff.full = dfixed_const(temp)(u32)(((temp) << 12));
	temp_ff.full = dfixed_mul(mclk_ff, temp_ff)((u64)((u64)(mclk_ff).full * (temp_ff).full + 2048) >> 12
);
	if (sclk_ff.full < temp_ff.full)
		temp_ff.full = sclk_ff.full;

	read_return_rate.full = temp_ff.full;

	if (mode1) {
		temp_ff.full = read_return_rate.full - disp_drain_rate.full;
		time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
	} else {
		time_disp1_drop_priority.full = 0;
	}
	crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
	crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2)((u64)((u64)(crit_point_ff).full * (disp_drain_rate2).full + 2048
) >> 12);
	crit_point_ff.full += dfixed_const_half(0)(u32)(((0) << 12) + 2048);

	critical_point2 = dfixed_trunc(crit_point_ff)((crit_point_ff).full >> 12);

	if (rdev->disp_priority == 2) {
		critical_point2 = 0;
	}

	if (max_stop_req - critical_point2 < 4)
		critical_point2 = 0;

}

if (critical_point2 == 0 && rdev->family == CHIP_R300) {
	/* some R300 cards have problem with this set to 0 */
	critical_point2 = 0x10;
}

WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |r100_mm_wreg(rdev, (0x03f0), (((grph2_cntl & ~(0x7f<<
16)) | (critical_point2 << 16))), 0)
				  (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)))r100_mm_wreg(rdev, (0x03f0), (((grph2_cntl & ~(0x7f<<
16)) | (critical_point2 << 16))), 0);

if ((rdev->family == CHIP_RS400) ||
    (rdev->family == CHIP_RS480)) {
3615#if 0
	/* attempt to program RS400 disp2 regs correctly ??? */
	temp = RREG32(RS400_DISP2_REQ_CNTL1)r100_mm_rreg(rdev, (0xe30), 0);
	temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK0x3ff |
		  RS400_DISP2_STOP_REQ_LEVEL_MASK0x3ff);
	WREG32(RS400_DISP2_REQ_CNTL1, (temp |r100_mm_wreg(rdev, (0xe30), ((temp | (critical_point2 <<
 0) | (critical_point2 << 12))), 0)
				       (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |r100_mm_wreg(rdev, (0xe30), ((temp | (critical_point2 <<
 0) | (critical_point2 << 12))), 0)
				       (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)))r100_mm_wreg(rdev, (0xe30), ((temp | (critical_point2 <<
 0) | (critical_point2 << 12))), 0);
	temp = RREG32(RS400_DISP2_REQ_CNTL2)r100_mm_rreg(rdev, (0xe34), 0);
	temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK0x3ff |
		  RS400_DISP2_CRITICAL_POINT_STOP_MASK0x3ff);
	WREG32(RS400_DISP2_REQ_CNTL2, (temp |r100_mm_wreg(rdev, (0xe34), ((temp | (critical_point2 <<
 12) | (critical_point2 << 22))), 0)
				       (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |r100_mm_wreg(rdev, (0xe34), ((temp | (critical_point2 <<
 12) | (critical_point2 << 22))), 0)
				       (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)))r100_mm_wreg(rdev, (0xe34), ((temp | (critical_point2 <<
 12) | (critical_point2 << 22))), 0);
3629#endif
	WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC)r100_mm_wreg(rdev, (0xe30), (0x105DC1CC), 0);
	WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000)r100_mm_wreg(rdev, (0xe34), (0x2749D000), 0);
	WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC)r100_mm_wreg(rdev, (0xe38), (0x29CA71DC), 0);
	WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC)r100_mm_wreg(rdev, (0xe3c), (0x28FBC3AC), 0);
}

DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",___drm_dbg(((void *)0), DRM_UT_KMS, "GRPH2_BUFFER_CNTL from to %x\n"
, (unsigned int)r100_mm_rreg(rdev, (0x03f0), 0))
	  (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL))___drm_dbg(((void *)0), DRM_UT_KMS, "GRPH2_BUFFER_CNTL from to %x\n"
, (unsigned int)r100_mm_rreg(rdev, (0x03f0), 0));
}

/* Save number of lines the linebuffer leads before the scanout */
if (mode1)
   rdev->mode_info.crtcs[0]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode1->crtc_hdisplay)(((lb_size) + ((mode1->crtc_hdisplay) - 1)) / (mode1->crtc_hdisplay
));

if (mode2)
   rdev->mode_info.crtcs[1]->lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode2->crtc_hdisplay)(((lb_size) + ((mode2->crtc_hdisplay) - 1)) / (mode2->crtc_hdisplay
));
3646}

3648int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3649{
uint32_t scratch;
uint32_t tmp = 0;
unsigned i;
int r;

r = radeon_scratch_get(rdev, &scratch);
if (r) {
DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r)__drm_err("radeon: cp failed to get scratch reg (%d).\n", r);
return r;
}
WREG32(scratch, 0xCAFEDEAD)r100_mm_wreg(rdev, (scratch), (0xCAFEDEAD), 0);
r = radeon_ring_lock(rdev, ring, 2);
if (r) {
DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r)__drm_err("radeon: cp failed to lock ring (%d).\n", r);
radeon_scratch_free(rdev, scratch);
return r;
}
radeon_ring_write(ring, PACKET0(scratch, 0)(0x00000000 | ((((scratch) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, 0xDEADBEEF);
radeon_ring_unlock_commit(rdev, ring, false0);
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(scratch)r100_mm_rreg(rdev, (scratch), 0);
if (tmp == 0xDEADBEEF) {
	break;
}
udelay(1);
}
if (i < rdev->usec_timeout) {
DRM_INFO("ring test succeeded in %d usecs\n", i)printk("\0016" "[" "drm" "] " "ring test succeeded in %d usecs\n"
, i);
} else {
DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",__drm_err("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n"
, scratch, tmp)
	  scratch, tmp)__drm_err("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n"
, scratch, tmp);
r = -EINVAL22;
}
radeon_scratch_free(rdev, scratch);
return r;
3686}

3688void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3689{
struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX0];

if (ring->rptr_save_reg) {
u32 next_rptr = ring->wptr + 2 + 3;
radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0)(0x00000000 | ((((ring->rptr_save_reg) >> 2) <<
 0) & (0x1ffff << 0)) | ((((0)) << 16) & (
0x3fff << 16))));
radeon_ring_write(ring, next_rptr);
}

radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1)(0x00000000 | ((((0x0738) >> 2) << 0) & (0x1ffff
 << 0)) | ((((1)) << 16) & (0x3fff << 16
))));
radeon_ring_write(ring, ib->gpu_addr);
radeon_ring_write(ring, ib->length_dw);
3701}

3703int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3704{
struct radeon_ib ib;
uint32_t scratch;
uint32_t tmp = 0;
unsigned i;
int r;

r = radeon_scratch_get(rdev, &scratch);
if (r) {
DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r)__drm_err("radeon: failed to get scratch reg (%d).\n", r);
return r;
}
WREG32(scratch, 0xCAFEDEAD)r100_mm_wreg(rdev, (scratch), (0xCAFEDEAD), 0);
r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX0, &ib, NULL((void *)0), 256);
if (r) {
DRM_ERROR("radeon: failed to get ib (%d).\n", r)__drm_err("radeon: failed to get ib (%d).\n", r);
goto free_scratch;
}
ib.ptr[0] = PACKET0(scratch, 0)(0x00000000 | ((((scratch) >> 2) << 0) & (0x1ffff
 << 0)) | ((((0)) << 16) & (0x3fff << 16
)));
ib.ptr[1] = 0xDEADBEEF;
ib.ptr[2] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib.ptr[3] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib.ptr[4] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib.ptr[5] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib.ptr[6] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib.ptr[7] = PACKET2(0)(0x80000000 | ((((0)) << 0) & (0x3fffffff << 0
)));
ib.length_dw = 8;
r = radeon_ib_schedule(rdev, &ib, NULL((void *)0), false0);
if (r) {
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r)__drm_err("radeon: failed to schedule ib (%d).\n", r);
goto free_ib;
}
r = radeon_fence_wait_timeout(ib.fence, false0, usecs_to_jiffies((((uint64_t)(1000000)) * hz / 1000000)
RADEON_USEC_IB_TEST_TIMEOUT)(((uint64_t)(1000000)) * hz / 1000000));
if (r < 0) {
DRM_ERROR("radeon: fence wait failed (%d).\n", r)__drm_err("radeon: fence wait failed (%d).\n", r);
goto free_ib;
} else if (r == 0) {
DRM_ERROR("radeon: fence wait timed out.\n")__drm_err("radeon: fence wait timed out.\n");
r = -ETIMEDOUT60;
goto free_ib;
}
r = 0;
for (i = 0; i < rdev->usec_timeout; i++) {
tmp = RREG32(scratch)r100_mm_rreg(rdev, (scratch), 0);
if (tmp == 0xDEADBEEF) {
	break;
}
udelay(1);
}
if (i < rdev->usec_timeout) {
DRM_INFO("ib test succeeded in %u usecs\n", i)printk("\0016" "[" "drm" "] " "ib test succeeded in %u usecs\n"
, i);
} else {
DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",__drm_err("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n"
, scratch, tmp)
	  scratch, tmp)__drm_err("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n"
, scratch, tmp);
r = -EINVAL22;
}
3761free_ib:
radeon_ib_free(rdev, &ib);
3763free_scratch:
radeon_scratch_free(rdev, scratch);
return r;
3766}

3768void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3769{
/* Shutdown CP we shouldn't need to do that but better be safe than
* sorry
*/
rdev->ring[RADEON_RING_TYPE_GFX_INDEX0].ready = false0;
WREG32(R_000740_CP_CSQ_CNTL, 0)r100_mm_wreg(rdev, (0x000740), (0), 0);

/* Save few CRTC registers */
save->GENMO_WT = RREG8(R_0003C2_GENMO_WT)ioread8((rdev->rmmio) + (0x0003C2));
save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL)r100_mm_rreg(rdev, (0x000054), 0);
save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL)r100_mm_rreg(rdev, (0x000050), 0);
save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET)r100_mm_rreg(rdev, (0x000260), 0);
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
8
←
Assuming the condition is false→
9
←
Taking false branch→
save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL)r100_mm_rreg(rdev, (0x0003F8), 0);
save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET)r100_mm_rreg(rdev, (0x000360), 0);
}

/* Disable VGA aperture access */
WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT)iowrite8(0xFD & save->GENMO_WT, (rdev->rmmio) + (0x0003C2
));
/* Disable cursor, overlay, crtc */
WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1))r100_mm_wreg(rdev, (0x000260), (save->CUR_OFFSET | (((1) &
 0x1) << 31)), 0);
WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |r100_mm_wreg(rdev, (0x000054), (save->CRTC_EXT_CNTL | (((1
) & 0x1) << 10)), 0)
			S_000054_CRTC_DISPLAY_DIS(1))r100_mm_wreg(rdev, (0x000054), (save->CRTC_EXT_CNTL | (((1
) & 0x1) << 10)), 0);
WREG32(R_000050_CRTC_GEN_CNTL,r100_mm_wreg(rdev, (0x000050), ((0xFFFEFFFF & save->CRTC_GEN_CNTL
) | (((1) & 0x1) << 26)), 0)
	(C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |r100_mm_wreg(rdev, (0x000050), ((0xFFFEFFFF & save->CRTC_GEN_CNTL
) | (((1) & 0x1) << 26)), 0)
	S_000050_CRTC_DISP_REQ_EN_B(1))r100_mm_wreg(rdev, (0x000050), ((0xFFFEFFFF & save->CRTC_GEN_CNTL
) | (((1) & 0x1) << 26)), 0);
WREG32(R_000420_OV0_SCALE_CNTL,r100_mm_wreg(rdev, (0x000420), (0xBFFFFFFF & r100_mm_rreg
(rdev, (0x000420), 0)), 0)
C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL))r100_mm_wreg(rdev, (0x000420), (0xBFFFFFFF & r100_mm_rreg
(rdev, (0x000420), 0)), 0);
WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET)r100_mm_wreg(rdev, (0x000260), (0x7FFFFFFF & save->CUR_OFFSET
), 0);
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
10
←
Taking false branch→
WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |r100_mm_wreg(rdev, (0x000360), (save->CUR2_OFFSET | (((1) &
 0x1) << 31)), 0)
				S_000360_CUR2_LOCK(1))r100_mm_wreg(rdev, (0x000360), (save->CUR2_OFFSET | (((1) &
 0x1) << 31)), 0);
WREG32(R_0003F8_CRTC2_GEN_CNTL,r100_mm_wreg(rdev, (0x0003F8), ((0xFFFEFFFF & save->CRTC2_GEN_CNTL
) | (((1) & 0x1) << 23) | (((1) & 0x1) <<
 26)), 0)
	(C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |r100_mm_wreg(rdev, (0x0003F8), ((0xFFFEFFFF & save->CRTC2_GEN_CNTL
) | (((1) & 0x1) << 23) | (((1) & 0x1) <<
 26)), 0)
	S_0003F8_CRTC2_DISPLAY_DIS(1) |r100_mm_wreg(rdev, (0x0003F8), ((0xFFFEFFFF & save->CRTC2_GEN_CNTL
) | (((1) & 0x1) << 23) | (((1) & 0x1) <<
 26)), 0)
	S_0003F8_CRTC2_DISP_REQ_EN_B(1))r100_mm_wreg(rdev, (0x0003F8), ((0xFFFEFFFF & save->CRTC2_GEN_CNTL
) | (((1) & 0x1) << 23) | (((1) & 0x1) <<
 26)), 0);
WREG32(R_000360_CUR2_OFFSET,r100_mm_wreg(rdev, (0x000360), (0x7FFFFFFF & save->CUR2_OFFSET
), 0)
	C_000360_CUR2_LOCK & save->CUR2_OFFSET)r100_mm_wreg(rdev, (0x000360), (0x7FFFFFFF & save->CUR2_OFFSET
), 0);
}
3808}
11
←
Returning without writing to 'save->CRTC2_GEN_CNTL'→

3810void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3811{
/* Update base address for crtc */
WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start)r100_mm_wreg(rdev, (0x00023C), (rdev->mc.vram_start), 0);
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
20
←
Assuming the condition is true→
21
←
Taking true branch→
WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start)r100_mm_wreg(rdev, (0x00033C), (rdev->mc.vram_start), 0);
}
/* Restore CRTC registers */
WREG8(R_0003C2_GENMO_WT, save->GENMO_WT)iowrite8(save->GENMO_WT, (rdev->rmmio) + (0x0003C2));
WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL)r100_mm_wreg(rdev, (0x000054), (save->CRTC_EXT_CNTL), 0);
WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL)r100_mm_wreg(rdev, (0x000050), (save->CRTC_GEN_CNTL), 0);
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
22
←
Taking true branch→
WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL)r100_mm_wreg(rdev, (0x0003F8), (save->CRTC2_GEN_CNTL), 0);
23
←
3rd function call argument is an uninitialized value
}
3824}

3826void r100_vga_render_disable(struct radeon_device *rdev)
3827{
u32 tmp;

tmp = RREG8(R_0003C2_GENMO_WT)ioread8((rdev->rmmio) + (0x0003C2));
WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp)iowrite8(0xFD & tmp, (rdev->rmmio) + (0x0003C2));
3832}

3834static void r100_mc_program(struct radeon_device *rdev)
3835{
struct r100_mc_save save;

/* Stops all mc clients */
r100_mc_stop(rdev, &save);
7
←
Calling 'r100_mc_stop'→
12
←
Returning from 'r100_mc_stop'→
if (rdev->flags & RADEON_IS_AGP) {
13
←
Assuming the condition is false→
14
←
Taking false branch→
WREG32(R_00014C_MC_AGP_LOCATION,r100_mm_wreg(rdev, (0x00014C), ((((rdev->mc.gtt_start >>
 16) & 0xFFFF) << 0) | (((rdev->mc.gtt_end >>
 16) & 0xFFFF) << 16)), 0)
	S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |r100_mm_wreg(rdev, (0x00014C), ((((rdev->mc.gtt_start >>
 16) & 0xFFFF) << 0) | (((rdev->mc.gtt_end >>
 16) & 0xFFFF) << 16)), 0)
	S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16))r100_mm_wreg(rdev, (0x00014C), ((((rdev->mc.gtt_start >>
 16) & 0xFFFF) << 0) | (((rdev->mc.gtt_end >>
 16) & 0xFFFF) << 16)), 0);
WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base))r100_mm_wreg(rdev, (0x000170), (((u32)(rdev->mc.agp_base))
), 0);
if (rdev->family > CHIP_RV200)
	WREG32(R_00015C_AGP_BASE_2,r100_mm_wreg(rdev, (0x00015C), (((u32)(((rdev->mc.agp_base
) >> 16) >> 16)) & 0xff), 0)
		upper_32_bits(rdev->mc.agp_base) & 0xff)r100_mm_wreg(rdev, (0x00015C), (((u32)(((rdev->mc.agp_base
) >> 16) >> 16)) & 0xff), 0);
} else {
WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF)r100_mm_wreg(rdev, (0x00014C), (0x0FFFFFFF), 0);
WREG32(R_000170_AGP_BASE, 0)r100_mm_wreg(rdev, (0x000170), (0), 0);
if (rdev->family > CHIP_RV200)
15
←
Assuming field 'family' is <= CHIP_RV200→
16
←
Taking false branch→
	WREG32(R_00015C_AGP_BASE_2, 0)r100_mm_wreg(rdev, (0x00015C), (0), 0);
}
/* Wait for mc idle */
if (r100_mc_wait_for_idle(rdev))
17
←
Assuming the condition is false→
18
←
Taking false branch→
dev_warn(rdev->dev, "Wait for MC idle timeout.\n")printf("drm:pid%d:%s *WARNING* " "Wait for MC idle timeout.\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
/* Program MC, should be a 32bits limited address space */
WREG32(R_000148_MC_FB_LOCATION,r100_mm_wreg(rdev, (0x000148), ((((rdev->mc.vram_start >>
 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end >>
 16) & 0xFFFF) << 16)), 0)
S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |r100_mm_wreg(rdev, (0x000148), ((((rdev->mc.vram_start >>
 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end >>
 16) & 0xFFFF) << 16)), 0)
S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16))r100_mm_wreg(rdev, (0x000148), ((((rdev->mc.vram_start >>
 16) & 0xFFFF) << 0) | (((rdev->mc.vram_end >>
 16) & 0xFFFF) << 16)), 0);
r100_mc_resume(rdev, &save);
19
←
Calling 'r100_mc_resume'→
3862}

3864static void r100_clock_startup(struct radeon_device *rdev)
3865{
u32 tmp;

if (radeon_dynclks != -1 && radeon_dynclks)
radeon_legacy_set_clock_gating(rdev, 1);
/* We need to force on some of the block */
tmp = RREG32_PLL(R_00000D_SCLK_CNTL)rdev->pll_rreg(rdev, (0x00000D));
tmp |= S_00000D_FORCE_CP(1)(((1) & 0x1) << 16) | S_00000D_FORCE_VIP(1)(((1) & 0x1) << 23);
if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
tmp |= S_00000D_FORCE_DISP1(1)(((1) & 0x1) << 18) | S_00000D_FORCE_DISP2(1)(((1) & 0x1) << 15);
WREG32_PLL(R_00000D_SCLK_CNTL, tmp)rdev->pll_wreg(rdev, (0x00000D), (tmp));
3876}

3878static int r100_startup(struct radeon_device *rdev)
3879{
int r;

/* set common regs */
r100_set_common_regs(rdev);
/* program mc */
r100_mc_program(rdev);
6
←
Calling 'r100_mc_program'→
/* Resume clock */
r100_clock_startup(rdev);
/* Initialize GART (initialize after TTM so we can allocate
* memory through TTM but finalize after TTM) */
r100_enable_bm(rdev);
if (rdev->flags & RADEON_IS_PCI) {
r = r100_pci_gart_enable(rdev);
if (r)
	return r;
}

/* allocate wb buffer */
r = radeon_wb_init(rdev);
if (r)
return r;

r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX0);
if (r) {
dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP fences (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

/* Enable IRQ */
if (!rdev->irq.installed) {
r = radeon_irq_kms_init(rdev);
if (r)
	return r;
}

r100_irq_set(rdev);
rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL)r100_mm_rreg(rdev, (0x0130), 0);
/* 1M ring buffer */
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
dev_err(rdev->dev, "failed initializing CP (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "failed initializing CP (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

r = radeon_ib_pool_init(rdev);
if (r) {
dev_err(rdev->dev, "IB initialization failed (%d).\n", r)printf("drm:pid%d:%s *ERROR* " "IB initialization failed (%d).\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r);
return r;
}

return 0;
3931}

3933int r100_resume(struct radeon_device *rdev)
3934{
int r;

/* Make sur GART are not working */
if (rdev->flags & RADEON_IS_PCI)
1
Assuming the condition is false→
2
←
Taking false branch→
r100_pci_gart_disable(rdev);
/* Resume clock before doing reset */
r100_clock_startup(rdev);
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) {
3
←
Assuming the condition is false→
4
←
Taking false branch→
dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
	RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
	RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0));
}
/* post */
radeon_combios_asic_init(rdev->ddev);
/* Resume clock after posting */
r100_clock_startup(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);

rdev->accel_working = true1;
r = r100_startup(rdev);
5
←
Calling 'r100_startup'→
if (r) {
rdev->accel_working = false0;
}
return r;
3961}

3963int r100_suspend(struct radeon_device *rdev)
3964{
radeon_pm_suspend(rdev);
r100_cp_disable(rdev);
radeon_wb_disable(rdev);
r100_irq_disable(rdev);
if (rdev->flags & RADEON_IS_PCI)
r100_pci_gart_disable(rdev);
return 0;
3972}

3974void r100_fini(struct radeon_device *rdev)
3975{
radeon_pm_fini(rdev);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_gem_fini(rdev);
if (rdev->flags & RADEON_IS_PCI)
r100_pci_gart_fini(rdev);
radeon_agp_fini(rdev);
radeon_irq_kms_fini(rdev);
radeon_fence_driver_fini(rdev);
radeon_bo_fini(rdev);
radeon_atombios_fini(rdev);
kfree(rdev->bios);
rdev->bios = NULL((void *)0);
3990}

3992/*
* Due to how kexec works, it can leave the hw fully initialised when it
* boots the new kernel. However doing our init sequence with the CP and
* WB stuff setup causes GPU hangs on the RN50 at least. So at startup
* do some quick sanity checks and restore sane values to avoid this
* problem.
*/
3999void r100_restore_sanity(struct radeon_device *rdev)
4000{
u32 tmp;

tmp = RREG32(RADEON_CP_CSQ_CNTL)r100_mm_rreg(rdev, (0x0740), 0);
if (tmp) {
WREG32(RADEON_CP_CSQ_CNTL, 0)r100_mm_wreg(rdev, (0x0740), (0), 0);
}
tmp = RREG32(RADEON_CP_RB_CNTL)r100_mm_rreg(rdev, (0x0704), 0);
if (tmp) {
WREG32(RADEON_CP_RB_CNTL, 0)r100_mm_wreg(rdev, (0x0704), (0), 0);
}
tmp = RREG32(RADEON_SCRATCH_UMSK)r100_mm_rreg(rdev, (0x0770), 0);
if (tmp) {
WREG32(RADEON_SCRATCH_UMSK, 0)r100_mm_wreg(rdev, (0x0770), (0), 0);
}
4015}

4017int r100_init(struct radeon_device *rdev)
4018{
int r;

/* Register debugfs file specific to this group of asics */
r100_debugfs_mc_info_init(rdev);
/* Disable VGA */
r100_vga_render_disable(rdev);
/* Initialize scratch registers */
radeon_scratch_init(rdev);
/* Initialize surface registers */
radeon_surface_init(rdev);
/* sanity check some register to avoid hangs like after kexec */
r100_restore_sanity(rdev);
/* TODO: disable VGA need to use VGA request */
/* BIOS*/
if (!radeon_get_bios(rdev)) {
if (ASIC_IS_AVIVO(rdev)((rdev->family >= CHIP_RS600)))
	return -EINVAL22;
}
if (rdev->is_atom_bios) {
dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n")printf("drm:pid%d:%s *ERROR* " "Expecting combios for RS400/RS480 GPU\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
return -EINVAL22;
} else {
r = radeon_combios_init(rdev);
if (r)
	return r;
}
/* Reset gpu before posting otherwise ATOM will enter infinite loop */
if (radeon_asic_reset(rdev)(rdev)->asic->asic_reset((rdev), 0)) {
dev_warn(rdev->dev,printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
	"GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
	RREG32(R_000E40_RBBM_STATUS),printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0))
	RREG32(R_0007C0_CP_STAT))printf("drm:pid%d:%s *WARNING* " "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , r100_mm_rreg
(rdev, (0x000E40), 0), r100_mm_rreg(rdev, (0x0007C0), 0));
}
/* check if cards are posted or not */
if (radeon_boot_test_post_card(rdev) == false0)
return -EINVAL22;
/* Set asic errata */
r100_errata(rdev);
/* Initialize clocks */
radeon_get_clock_info(rdev->ddev);
/* initialize AGP */
if (rdev->flags & RADEON_IS_AGP) {
r = radeon_agp_init(rdev);
if (r) {
	radeon_agp_disable(rdev);
}
}
/* initialize VRAM */
r100_mc_init(rdev);
/* Fence driver */
radeon_fence_driver_init(rdev);
/* Memory manager */
r = radeon_bo_init(rdev);
if (r)
return r;
if (rdev->flags & RADEON_IS_PCI) {
r = r100_pci_gart_init(rdev);
if (r)
	return r;
}
r100_set_safe_registers(rdev);

/* Initialize power management */
radeon_pm_init(rdev);

rdev->accel_working = true1;
r = r100_startup(rdev);
if (r) {
/* Somethings want wront with the accel init stop accel */
dev_err(rdev->dev, "Disabling GPU acceleration\n")printf("drm:pid%d:%s *ERROR* " "Disabling GPU acceleration\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__);
r100_cp_fini(rdev);
radeon_wb_fini(rdev);
radeon_ib_pool_fini(rdev);
radeon_irq_kms_fini(rdev);
if (rdev->flags & RADEON_IS_PCI)
	r100_pci_gart_fini(rdev);
rdev->accel_working = false0;
}
return 0;
4098}

4100uint32_t r100_mm_rreg_slow(struct radeon_device *rdev, uint32_t reg)
4101{
unsigned long flags;
uint32_t ret;

spin_lock_irqsave(&rdev->mmio_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mmio_idx_lock); } while
 (0);
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX)iowrite32(reg, ((void *)rdev->rmmio) + 0x0000);
ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA)ioread32(((void *)rdev->rmmio) + 0x0004);
spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mmio_idx_lock); }
 while (0);
return ret;
4110}

4112void r100_mm_wreg_slow(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4113{
unsigned long flags;

spin_lock_irqsave(&rdev->mmio_idx_lock, flags)do { flags = 0; mtx_enter(&rdev->mmio_idx_lock); } while
 (0);
writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX)iowrite32(reg, ((void *)rdev->rmmio) + 0x0000);
writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA)iowrite32(v, ((void *)rdev->rmmio) + 0x0004);
spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags)do { (void)(flags); mtx_leave(&rdev->mmio_idx_lock); }
 while (0);
4120}

4122u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4123{
u32 val;

if (reg < rdev->rio_mem_size) {
val = bus_space_read_4(rdev->iot, rdev->rio_mem, reg)((rdev->iot)->read_4((rdev->rio_mem), (reg)));
bus_space_barrier(rdev->iot, rdev->rio_mem, 0,
    rdev->rio_mem_size, BUS_SPACE_BARRIER_READ0x01);
} else {
bus_space_barrier(rdev->iot, rdev->rio_mem, 0,
    rdev->rio_mem_size, BUS_SPACE_BARRIER_WRITE0x02);
bus_space_write_4(rdev->iot, rdev->rio_mem,((rdev->iot)->write_4((rdev->rio_mem), (0x0000), (reg
)))
    RADEON_MM_INDEX, reg)((rdev->iot)->write_4((rdev->rio_mem), (0x0000), (reg
)));
val = bus_space_read_4(rdev->iot, rdev->rio_mem,((rdev->iot)->read_4((rdev->rio_mem), (0x0004)))
    RADEON_MM_DATA)((rdev->iot)->read_4((rdev->rio_mem), (0x0004)));
bus_space_barrier(rdev->iot, rdev->rio_mem, 0,
    rdev->rio_mem_size, BUS_SPACE_BARRIER_READ0x01);
}

return val;
4142}

4144void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4145{
if (reg < rdev->rio_mem_size) {
bus_space_barrier(rdev->iot, rdev->rio_mem, 0,
    rdev->rio_mem_size, BUS_SPACE_BARRIER_WRITE0x02);
bus_space_write_4(rdev->iot, rdev->rio_mem, reg, v)((rdev->iot)->write_4((rdev->rio_mem), (reg), (v)));
} else {
bus_space_barrier(rdev->iot, rdev->rio_mem, 0,
    rdev->rio_mem_size, BUS_SPACE_BARRIER_WRITE0x02);
bus_space_write_4(rdev->iot, rdev->rio_mem,((rdev->iot)->write_4((rdev->rio_mem), (0x0000), (reg
)))
    RADEON_MM_INDEX, reg)((rdev->iot)->write_4((rdev->rio_mem), (0x0000), (reg
)));
bus_space_barrier(rdev->iot, rdev->rio_mem, 0,
    rdev->rio_mem_size, BUS_SPACE_BARRIER_WRITE0x02);
bus_space_write_4(rdev->iot, rdev->rio_mem,((rdev->iot)->write_4((rdev->rio_mem), (0x0004), (v)
))
    RADEON_MM_DATA, v)((rdev->iot)->write_4((rdev->rio_mem), (0x0004), (v)
));
}
4160}