Bug Summary

File:dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
Warning:line 366, column 3
Value stored to 'remaining_buffer' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name vg_clk_mgr.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#include "dccg.h"
27#include "clk_mgr_internal.h"
28
29// For dce12_get_dp_ref_freq_khz
30#include "dce100/dce_clk_mgr.h"
31
32// For dcn20_update_clocks_update_dpp_dto
33#include "dcn20/dcn20_clk_mgr.h"
34
35// For DML FPU code
36#include "dml/dcn20/dcn20_fpu.h"
37
38#include "vg_clk_mgr.h"
39#include "dcn301_smu.h"
40#include "reg_helper.h"
41#include "core_types.h"
42#include "dm_helpers.h"
43
44#include "atomfirmware.h"
45#include "vangogh_ip_offset.h"
46#include "clk/clk_11_5_0_offset.h"
47#include "clk/clk_11_5_0_sh_mask.h"
48
49/* Constants */
50
51#define LPDDR_MEM_RETRAIN_LATENCY4.977 4.977 /* Number obtained from LPDDR4 Training Counter Requirement doc */
52
53/* Macros */
54
55#define TO_CLK_MGR_VGH(clk_mgr)({ const __typeof( ((struct clk_mgr_vgh *)0)->base ) *__mptr
= (clk_mgr); (struct clk_mgr_vgh *)( (char *)__mptr - __builtin_offsetof
(struct clk_mgr_vgh, base) );})\
56 container_of(clk_mgr, struct clk_mgr_vgh, base)({ const __typeof( ((struct clk_mgr_vgh *)0)->base ) *__mptr
= (clk_mgr); (struct clk_mgr_vgh *)( (char *)__mptr - __builtin_offsetof
(struct clk_mgr_vgh, base) );})
57
58#define REG(reg_name)(CLK_BASE.instance[0].segment[mmreg_name_BASE_IDX] + mmreg_name
) \
59 (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
60
61/* TODO: evaluate how to lower or disable all dcn clocks in screen off case */
62static int vg_get_active_display_cnt_wa(
63 struct dc *dc,
64 struct dc_state *context)
65{
66 int i, display_count;
67 bool_Bool tmds_present = false0;
68
69 display_count = 0;
70 for (i = 0; i < context->stream_count; i++) {
71 const struct dc_stream_state *stream = context->streams[i];
72
73 if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
74 stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
75 stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
76 tmds_present = true1;
77 }
78
79 for (i = 0; i < dc->link_count; i++) {
80 const struct dc_link *link = dc->links[i];
81
82 /* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
83 if (link->link_enc->funcs->is_dig_enabled &&
84 link->link_enc->funcs->is_dig_enabled(link->link_enc))
85 display_count++;
86 }
87
88 /* WA for hang on HDMI after display off back back on*/
89 if (display_count == 0 && tmds_present)
90 display_count = 1;
91
92 return display_count;
93}
94
95static void vg_update_clocks(struct clk_mgr *clk_mgr_base,
96 struct dc_state *context,
97 bool_Bool safe_to_lower)
98{
99 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base)({ const __typeof( ((struct clk_mgr_internal *)0)->base ) *
__mptr = (clk_mgr_base); (struct clk_mgr_internal *)( (char *
)__mptr - __builtin_offsetof(struct clk_mgr_internal, base) )
;});
100 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
101 struct dc *dc = clk_mgr_base->ctx->dc;
102 int display_count;
103 bool_Bool update_dppclk = false0;
104 bool_Bool update_dispclk = false0;
105 bool_Bool dpp_clock_lowered = false0;
106
107 if (dc->work_arounds.skip_clock_update)
108 return;
109
110 /*
111 * if it is safe to lower, but we are already in the lower state, we don't have to do anything
112 * also if safe to lower is false, we just go in the higher state
113 */
114 if (safe_to_lower) {
115 /* check that we're not already in lower */
116 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
117
118 display_count = vg_get_active_display_cnt_wa(dc, context);
119 /* if we can go lower, go lower */
120 if (display_count == 0 && !IS_DIAG_DC(dc->ctx->dce_environment)((dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) || (
dc->ctx->dce_environment == DCE_ENV_DIAG))) {
121 union display_idle_optimization_u idle_info = { 0 };
122
123 idle_info.idle_info.df_request_disabled = 1;
124 idle_info.idle_info.phy_ref_clk_off = 1;
125
126 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
127 /* update power state */
128 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
129 }
130 }
131 } else {
132 /* check that we're not already in D0 */
133 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
134 union display_idle_optimization_u idle_info = { 0 };
135
136 dcn301_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
137 /* update power state */
138 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
139 }
140 }
141
142 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) && !dc->debug.disable_min_fclk) {
143 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
144 dcn301_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
145 }
146
147 if (should_set_clock(safe_to_lower,
148 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) && !dc->debug.disable_min_fclk) {
149 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
150 dcn301_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
151 }
152
153 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
154 if (!IS_DIAG_DC(dc->ctx->dce_environment)((dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) || (
dc->ctx->dce_environment == DCE_ENV_DIAG))) {
155 if (new_clocks->dppclk_khz < 100000)
156 new_clocks->dppclk_khz = 100000;
157 }
158
159 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
160 if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
161 dpp_clock_lowered = true1;
162 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
163 update_dppclk = true1;
164 }
165
166 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
167 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
168 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
169
170 update_dispclk = true1;
171 }
172
173 if (dpp_clock_lowered) {
174 // increase per DPP DTO before lowering global dppclk
175 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
176 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
177 } else {
178 // increase global DPPCLK before lowering per DPP DTO
179 if (update_dppclk || update_dispclk)
180 dcn301_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
181 // always update dtos unless clock is lowered and not safe to lower
182 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
183 }
184}
185
186
187static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
188{
189 /* get FbMult value */
190 struct fixed31_32 pll_req;
191 unsigned int fbmult_frac_val = 0;
192 unsigned int fbmult_int_val = 0;
193
194
195 /*
196 * Register value of fbmult is in 8.16 format, we are converting to 31.32
197 * to leverage the fix point operations available in driver
198 */
199
200 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val)generic_reg_get(clk_mgr->base.ctx, (CLK_BASE.instance[0].segment
[0] + 0x0410), 0x10, 0xFFFF0000L, &fbmult_frac_val); /* 16 bit fractional part*/
201 REG_GET(CLK1_0_CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val)generic_reg_get(clk_mgr->base.ctx, (CLK_BASE.instance[0].segment
[0] + 0x0410), 0x0, 0x000001FFL, &fbmult_int_val); /* 8 bit integer part */
202
203 pll_req = dc_fixpt_from_int(fbmult_int_val);
204
205 /*
206 * since fractional part is only 16 bit in register definition but is 32 bit
207 * in our fix point definiton, need to shift left by 16 to obtain correct value
208 */
209 pll_req.value |= fbmult_frac_val << 16;
210
211 /* multiply by REFCLK period */
212 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
213
214 /* integer part is now VCO frequency in kHz */
215 return dc_fixpt_floor(pll_req);
216}
217
218static void vg_dump_clk_registers_internal(struct dcn301_clk_internal *internal, struct clk_mgr *clk_mgr_base)
219{
220 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base)({ const __typeof( ((struct clk_mgr_internal *)0)->base ) *
__mptr = (clk_mgr_base); (struct clk_mgr_internal *)( (char *
)__mptr - __builtin_offsetof(struct clk_mgr_internal, base) )
;});
221
222 internal->CLK1_CLK3_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK3_CURRENT_CNT)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x04aa), __func__);
223 internal->CLK1_CLK3_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_BYPASS_CNTL)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x0468), __func__);
224
225 internal->CLK1_CLK3_DS_CNTL = REG_READ(CLK1_0_CLK1_CLK3_DS_CNTL)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x0461), __func__); //dcf deep sleep divider
226 internal->CLK1_CLK3_ALLOW_DS = REG_READ(CLK1_0_CLK1_CLK3_ALLOW_DS)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x0462), __func__);
227
228 internal->CLK1_CLK1_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK1_CURRENT_CNT)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x04a8), __func__);
229 internal->CLK1_CLK1_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK1_BYPASS_CNTL)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x0454), __func__);
230
231 internal->CLK1_CLK2_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK2_CURRENT_CNT)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x04a9), __func__);
232 internal->CLK1_CLK2_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK2_BYPASS_CNTL)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x045e), __func__);
233
234 internal->CLK1_CLK0_CURRENT_CNT = REG_READ(CLK1_0_CLK1_CLK0_CURRENT_CNT)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x04a7), __func__);
235 internal->CLK1_CLK0_BYPASS_CNTL = REG_READ(CLK1_0_CLK1_CLK0_BYPASS_CNTL)dm_read_reg_func(clk_mgr->base.ctx, (CLK_BASE.instance[0].
segment[0] + 0x044a), __func__);
236}
237
238/* This function collect raw clk register values */
239static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
240 struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
241{
242 struct dcn301_clk_internal internal = {0};
243 char *bypass_clks[5] = {"0x0 DFS", "0x1 REFCLK", "0x2 ERROR", "0x3 400 FCH", "0x4 600 FCH"};
244 unsigned int chars_printed = 0;
245 unsigned int remaining_buffer = log_info->bufSize;
246
247 vg_dump_clk_registers_internal(&internal, clk_mgr_base);
248
249 regs_and_bypass->dcfclk = internal.CLK1_CLK3_CURRENT_CNT / 10;
250 regs_and_bypass->dcf_deep_sleep_divider = internal.CLK1_CLK3_DS_CNTL / 10;
251 regs_and_bypass->dcf_deep_sleep_allow = internal.CLK1_CLK3_ALLOW_DS;
252 regs_and_bypass->dprefclk = internal.CLK1_CLK2_CURRENT_CNT / 10;
253 regs_and_bypass->dispclk = internal.CLK1_CLK0_CURRENT_CNT / 10;
254 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
255
256 regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
257 if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
258 regs_and_bypass->dppclk_bypass = 0;
259 regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
260 if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
261 regs_and_bypass->dcfclk_bypass = 0;
262 regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
263 if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
264 regs_and_bypass->dispclk_bypass = 0;
265 regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
266 if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
267 regs_and_bypass->dprefclk_bypass = 0;
268
269 if (log_info->enabled) {
270 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "clk_type,clk_value,deepsleep_cntl,deepsleep_allow,bypass\n");
271 remaining_buffer -= chars_printed;
272 *log_info->sum_chars_printed += chars_printed;
273 log_info->pBuf += chars_printed;
274
275 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dcfclk,%d,%d,%d,%s\n",
276 regs_and_bypass->dcfclk,
277 regs_and_bypass->dcf_deep_sleep_divider,
278 regs_and_bypass->dcf_deep_sleep_allow,
279 bypass_clks[(int) regs_and_bypass->dcfclk_bypass]);
280 remaining_buffer -= chars_printed;
281 *log_info->sum_chars_printed += chars_printed;
282 log_info->pBuf += chars_printed;
283
284 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dprefclk,%d,N/A,N/A,%s\n",
285 regs_and_bypass->dprefclk,
286 bypass_clks[(int) regs_and_bypass->dprefclk_bypass]);
287 remaining_buffer -= chars_printed;
288 *log_info->sum_chars_printed += chars_printed;
289 log_info->pBuf += chars_printed;
290
291 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "dispclk,%d,N/A,N/A,%s\n",
292 regs_and_bypass->dispclk,
293 bypass_clks[(int) regs_and_bypass->dispclk_bypass]);
294 remaining_buffer -= chars_printed;
295 *log_info->sum_chars_printed += chars_printed;
296 log_info->pBuf += chars_printed;
297
298 //split
299 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "SPLIT\n");
300 remaining_buffer -= chars_printed;
301 *log_info->sum_chars_printed += chars_printed;
302 log_info->pBuf += chars_printed;
303
304 // REGISTER VALUES
305 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "reg_name,value,clk_type\n");
306 remaining_buffer -= chars_printed;
307 *log_info->sum_chars_printed += chars_printed;
308 log_info->pBuf += chars_printed;
309
310 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_CURRENT_CNT,%d,dcfclk\n",
311 internal.CLK1_CLK3_CURRENT_CNT);
312 remaining_buffer -= chars_printed;
313 *log_info->sum_chars_printed += chars_printed;
314 log_info->pBuf += chars_printed;
315
316 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_DS_CNTL,%d,dcf_deep_sleep_divider\n",
317 internal.CLK1_CLK3_DS_CNTL);
318 remaining_buffer -= chars_printed;
319 *log_info->sum_chars_printed += chars_printed;
320 log_info->pBuf += chars_printed;
321
322 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_ALLOW_DS,%d,dcf_deep_sleep_allow\n",
323 internal.CLK1_CLK3_ALLOW_DS);
324 remaining_buffer -= chars_printed;
325 *log_info->sum_chars_printed += chars_printed;
326 log_info->pBuf += chars_printed;
327
328 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_CURRENT_CNT,%d,dprefclk\n",
329 internal.CLK1_CLK2_CURRENT_CNT);
330 remaining_buffer -= chars_printed;
331 *log_info->sum_chars_printed += chars_printed;
332 log_info->pBuf += chars_printed;
333
334 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_CURRENT_CNT,%d,dispclk\n",
335 internal.CLK1_CLK0_CURRENT_CNT);
336 remaining_buffer -= chars_printed;
337 *log_info->sum_chars_printed += chars_printed;
338 log_info->pBuf += chars_printed;
339
340 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n",
341 internal.CLK1_CLK1_CURRENT_CNT);
342 remaining_buffer -= chars_printed;
343 *log_info->sum_chars_printed += chars_printed;
344 log_info->pBuf += chars_printed;
345
346 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK3_BYPASS_CNTL,%d,dcfclk_bypass\n",
347 internal.CLK1_CLK3_BYPASS_CNTL);
348 remaining_buffer -= chars_printed;
349 *log_info->sum_chars_printed += chars_printed;
350 log_info->pBuf += chars_printed;
351
352 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK2_BYPASS_CNTL,%d,dprefclk_bypass\n",
353 internal.CLK1_CLK2_BYPASS_CNTL);
354 remaining_buffer -= chars_printed;
355 *log_info->sum_chars_printed += chars_printed;
356 log_info->pBuf += chars_printed;
357
358 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK0_BYPASS_CNTL,%d,dispclk_bypass\n",
359 internal.CLK1_CLK0_BYPASS_CNTL);
360 remaining_buffer -= chars_printed;
361 *log_info->sum_chars_printed += chars_printed;
362 log_info->pBuf += chars_printed;
363
364 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_BYPASS_CNTL,%d,dppclk_bypass\n",
365 internal.CLK1_CLK1_BYPASS_CNTL);
366 remaining_buffer -= chars_printed;
Value stored to 'remaining_buffer' is never read
367 *log_info->sum_chars_printed += chars_printed;
368 log_info->pBuf += chars_printed;
369 }
370}
371
372static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base)
373{
374 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base)({ const __typeof( ((struct clk_mgr_internal *)0)->base ) *
__mptr = (clk_mgr_base); (struct clk_mgr_internal *)( (char *
)__mptr - __builtin_offsetof(struct clk_mgr_internal, base) )
;});
375
376 dcn301_smu_enable_pme_wa(clk_mgr);
377}
378
379static void vg_init_clocks(struct clk_mgr *clk_mgr)
380{
381 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks))__builtin_memset((&(clk_mgr->clks)), (0), (sizeof(struct
dc_clocks)));
382 // Assumption is that boot state always supports pstate
383 clk_mgr->clks.p_state_change_support = true1;
384 clk_mgr->clks.prev_p_state_change_support = true1;
385 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN;
386}
387
388static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
389{
390 int i, num_valid_sets;
391
392 num_valid_sets = 0;
393
394 for (i = 0; i < WM_SET_COUNT4; i++) {
395 /* skip empty entries, the smu array has no holes*/
396 if (!bw_params->wm_table.entries[i].valid)
397 continue;
398
399 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
400 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
401 /* We will not select WM based on fclk, so leave it as unconstrained */
402 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
403 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
404
405 if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
406 if (i == 0)
407 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
408 else {
409 /* add 1 to make it non-overlapping with next lvl */
410 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
411 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
412 }
413 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
414 bw_params->clk_table.entries[i].dcfclk_mhz;
415
416 } else {
417 /* unconstrained for memory retraining */
418 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
419 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
420
421 /* Modify previous watermark range to cover up to max */
422 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
423 }
424 num_valid_sets++;
425 }
426
427 ASSERT(num_valid_sets != 0)do { if (({ static int __warned; int __ret = !!(!(num_valid_sets
!= 0)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(num_valid_sets != 0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c"
, 427); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0); /* Must have at least one set of valid watermarks */
428
429 /* modify the min and max to make sure we cover the whole range*/
430 table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
431 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
434
435 /* This is for writeback only, does not matter currently as no writeback support*/
436 table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A0;
437 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
438 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
439 table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
440 table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
441}
442
443
444static void vg_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
445{
446 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base)({ const __typeof( ((struct clk_mgr_internal *)0)->base ) *
__mptr = (clk_mgr_base); (struct clk_mgr_internal *)( (char *
)__mptr - __builtin_offsetof(struct clk_mgr_internal, base) )
;});
447 struct clk_mgr_vgh *clk_mgr_vgh = TO_CLK_MGR_VGH(clk_mgr)({ const __typeof( ((struct clk_mgr_vgh *)0)->base ) *__mptr
= (clk_mgr); (struct clk_mgr_vgh *)( (char *)__mptr - __builtin_offsetof
(struct clk_mgr_vgh, base) );});
448 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set;
449
450 if (!clk_mgr->smu_ver)
451 return;
452
453 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0)
454 return;
455
456 memset(table, 0, sizeof(*table))__builtin_memset((table), (0), (sizeof(*table)));
457
458 vg_build_watermark_ranges(clk_mgr_base->bw_params, table);
459
460 dcn301_smu_set_dram_addr_high(clk_mgr,
461 clk_mgr_vgh->smu_wm_set.mc_address.high_part);
462 dcn301_smu_set_dram_addr_low(clk_mgr,
463 clk_mgr_vgh->smu_wm_set.mc_address.low_part);
464 dcn301_smu_transfer_wm_table_dram_2_smu(clk_mgr);
465}
466
467static bool_Bool vg_are_clock_states_equal(struct dc_clocks *a,
468 struct dc_clocks *b)
469{
470 if (a->dispclk_khz != b->dispclk_khz)
471 return false0;
472 else if (a->dppclk_khz != b->dppclk_khz)
473 return false0;
474 else if (a->dcfclk_khz != b->dcfclk_khz)
475 return false0;
476 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
477 return false0;
478
479 return true1;
480}
481
482
483static struct clk_mgr_funcs vg_funcs = {
484 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
485 .update_clocks = vg_update_clocks,
486 .init_clocks = vg_init_clocks,
487 .enable_pme_wa = vg_enable_pme_wa,
488 .are_clock_states_equal = vg_are_clock_states_equal,
489 .notify_wm_ranges = vg_notify_wm_ranges
490};
491
492static struct clk_bw_params vg_bw_params = {
493 .vram_type = Ddr4MemType,
494 .num_channels = 1,
495 .clk_table = {
496 .entries = {
497 {
498 .voltage = 0,
499 .dcfclk_mhz = 400,
500 .fclk_mhz = 400,
501 .memclk_mhz = 800,
502 .socclk_mhz = 0,
503 },
504 {
505 .voltage = 0,
506 .dcfclk_mhz = 483,
507 .fclk_mhz = 800,
508 .memclk_mhz = 1600,
509 .socclk_mhz = 0,
510 },
511 {
512 .voltage = 0,
513 .dcfclk_mhz = 602,
514 .fclk_mhz = 1067,
515 .memclk_mhz = 1067,
516 .socclk_mhz = 0,
517 },
518 {
519 .voltage = 0,
520 .dcfclk_mhz = 738,
521 .fclk_mhz = 1333,
522 .memclk_mhz = 1600,
523 .socclk_mhz = 0,
524 },
525 },
526
527 .num_entries = 4,
528 },
529
530};
531
532static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
533{
534 uint32_t max = 0;
535 int i;
536
537 for (i = 0; i < num_clocks; ++i) {
538 if (clocks[i] > max)
539 max = clocks[i];
540 }
541
542 return max;
543}
544
545static unsigned int find_dcfclk_for_voltage(const struct vg_dpm_clocks *clock_table,
546 unsigned int voltage)
547{
548 int i;
549
550 for (i = 0; i < VG_NUM_SOC_VOLTAGE_LEVELS8; i++) {
551 if (clock_table->SocVoltage[i] == voltage)
552 return clock_table->DcfClocks[i];
553 }
554
555 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c"
, 555); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
556 return 0;
557}
558
559static void vg_clk_mgr_helper_populate_bw_params(
560 struct clk_mgr_internal *clk_mgr,
561 struct integrated_info *bios_info,
562 const struct vg_dpm_clocks *clock_table)
563{
564 int i, j;
565 struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
566
567 j = -1;
568
569 ASSERT(VG_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL)do { if (({ static int __warned; int __ret = !!(!(4 <= 8))
; if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(4 <= 8)", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c"
, 569); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
570
571 /* Find lowest DPM, FCLK is filled in reverse order*/
572
573 for (i = VG_NUM_FCLK_DPM_LEVELS4 - 1; i >= 0; i--) {
574 if (clock_table->DfPstateTable[i].fclk != 0) {
575 j = i;
576 break;
577 }
578 }
579
580 if (j == -1) {
581 /* clock table is all 0s, just use our own hardcode */
582 ASSERT(0)do { if (({ static int __warned; int __ret = !!(!(0)); if (__ret
&& !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(0)", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c"
, 582); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
583 return;
584 }
585
586 bw_params->clk_table.num_entries = j + 1;
587
588 for (i = 0; i < bw_params->clk_table.num_entries - 1; i++, j--) {
589 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
590 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
591 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
592 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
593 }
594 bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].fclk;
595 bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].memclk;
596 bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].voltage;
597 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCFCLK_DPM_LEVELS7);
598
599 bw_params->vram_type = bios_info->memory_type;
600 bw_params->num_channels = bios_info->ma_channel_number;
601
602 for (i = 0; i < WM_SET_COUNT4; i++) {
603 bw_params->wm_table.entries[i].wm_inst = i;
604
605 if (i >= bw_params->clk_table.num_entries) {
606 bw_params->wm_table.entries[i].valid = false0;
607 continue;
608 }
609
610 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
611 bw_params->wm_table.entries[i].valid = true1;
612 }
613
614 if (bw_params->vram_type == LpDdr4MemType) {
615 /*
616 * WM set D will be re-purposed for memory retraining
617 */
618 DC_FP_START()dc_fpu_begin(__func__, 618);
619 dcn21_clk_mgr_set_bw_params_wm_table(bw_params);
620 DC_FP_END()dc_fpu_end(__func__, 620);
621 }
622
623}
624
625/* Temporary Place holder until we can get them from fuse */
626static struct vg_dpm_clocks dummy_clocks = {
627 .DcfClocks = { 201, 403, 403, 403, 403, 403, 403 },
628 .SocClocks = { 400, 600, 600, 600, 600, 600, 600 },
629 .SocVoltage = { 2800, 2860, 2860, 2860, 2860, 2860, 2860, 2860 },
630 .DfPstateTable = {
631 { .fclk = 400, .memclk = 400, .voltage = 2800 },
632 { .fclk = 400, .memclk = 400, .voltage = 2800 },
633 { .fclk = 400, .memclk = 400, .voltage = 2800 },
634 { .fclk = 400, .memclk = 400, .voltage = 2800 }
635 }
636};
637
638static struct watermarks dummy_wms = { 0 };
639
640static void vg_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
641 struct smu_dpm_clks *smu_dpm_clks)
642{
643 struct vg_dpm_clocks *table = smu_dpm_clks->dpm_clks;
644
645 if (!clk_mgr->smu_ver)
646 return;
647
648 if (!table || smu_dpm_clks->mc_address.quad_part == 0)
649 return;
650
651 memset(table, 0, sizeof(*table))__builtin_memset((table), (0), (sizeof(*table)));
652
653 dcn301_smu_set_dram_addr_high(clk_mgr,
654 smu_dpm_clks->mc_address.high_part);
655 dcn301_smu_set_dram_addr_low(clk_mgr,
656 smu_dpm_clks->mc_address.low_part);
657 dcn301_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
658}
659
660void vg_clk_mgr_construct(
661 struct dc_context *ctx,
662 struct clk_mgr_vgh *clk_mgr,
663 struct pp_smu_funcs *pp_smu,
664 struct dccg *dccg)
665{
666 struct smu_dpm_clks smu_dpm_clks = { 0 };
667
668 clk_mgr->base.base.ctx = ctx;
669 clk_mgr->base.base.funcs = &vg_funcs;
670
671 clk_mgr->base.pp_smu = pp_smu;
672
673 clk_mgr->base.dccg = dccg;
674 clk_mgr->base.dfs_bypass_disp_clk = 0;
675
676 clk_mgr->base.dprefclk_ss_percentage = 0;
677 clk_mgr->base.dprefclk_ss_divider = 1000;
678 clk_mgr->base.ss_on_dprefclk = false0;
679 clk_mgr->base.dfs_ref_freq_khz = 48000;
680
681 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem(
682 clk_mgr->base.base.ctx,
683 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
684 sizeof(struct watermarks),
685 &clk_mgr->smu_wm_set.mc_address.quad_part);
686
687 if (!clk_mgr->smu_wm_set.wm_set) {
688 clk_mgr->smu_wm_set.wm_set = &dummy_wms;
689 clk_mgr->smu_wm_set.mc_address.quad_part = 0;
690 }
691 ASSERT(clk_mgr->smu_wm_set.wm_set)do { if (({ static int __warned; int __ret = !!(!(clk_mgr->
smu_wm_set.wm_set)); if (__ret && !__warned) { printf
("WARNING %s failed at %s:%d\n", "!(clk_mgr->smu_wm_set.wm_set)"
, "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c"
, 691); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
692
693 smu_dpm_clks.dpm_clks = (struct vg_dpm_clocks *)dm_helpers_allocate_gpu_mem(
694 clk_mgr->base.base.ctx,
695 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
696 sizeof(struct vg_dpm_clocks),
697 &smu_dpm_clks.mc_address.quad_part);
698
699 if (smu_dpm_clks.dpm_clks == NULL((void *)0)) {
700 smu_dpm_clks.dpm_clks = &dummy_clocks;
701 smu_dpm_clks.mc_address.quad_part = 0;
702 }
703
704 ASSERT(smu_dpm_clks.dpm_clks)do { if (({ static int __warned; int __ret = !!(!(smu_dpm_clks
.dpm_clks)); if (__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!(smu_dpm_clks.dpm_clks)", "/usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c"
, 704); __warned = 1; } __builtin_expect(!!(__ret), 0); })) do
{} while (0); } while (0);
705
706 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)(ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS)) {
707 vg_funcs.update_clocks = dcn2_update_clocks_fpga;
708 clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
709 } else {
710 struct clk_log_info log_info = {0};
711
712 clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base);
713
714 if (clk_mgr->base.smu_ver)
715 clk_mgr->base.smu_present = true1;
716
717 /* TODO: Check we get what we expect during bringup */
718 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
719
720 /* in case we don't get a value from the register, use default */
721 if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
722 clk_mgr->base.base.dentist_vco_freq_khz = 3600000;
723
724 if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
725 vg_bw_params.wm_table = lpddr5_wm_table;
726 } else {
727 vg_bw_params.wm_table = ddr4_wm_table;
728 }
729 /* Saved clocks configured at boot for debug purposes */
730 vg_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
731 }
732
733 clk_mgr->base.base.dprefclk_khz = 600000;
734 dce_clock_read_ss_info(&clk_mgr->base);
735
736 clk_mgr->base.base.bw_params = &vg_bw_params;
737
738 vg_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
739 if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
740 vg_clk_mgr_helper_populate_bw_params(
741 &clk_mgr->base,
742 ctx->dc_bios->integrated_info,
743 smu_dpm_clks.dpm_clks);
744 }
745
746 if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
747 dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
748 smu_dpm_clks.dpm_clks);
749/*
750 if (!IS_FPGA_MAXIMUS_DC(ctx->dce_environment) && clk_mgr->base.smu_ver) {
751 enable powerfeatures when displaycount goes to 0
752 dcn301_smu_enable_phy_refclk_pwrdwn(clk_mgr, !debug->disable_48mhz_pwrdwn);
753 }
754*/
755}
756
757void vg_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
758{
759 struct clk_mgr_vgh *clk_mgr = TO_CLK_MGR_VGH(clk_mgr_int)({ const __typeof( ((struct clk_mgr_vgh *)0)->base ) *__mptr
= (clk_mgr_int); (struct clk_mgr_vgh *)( (char *)__mptr - __builtin_offsetof
(struct clk_mgr_vgh, base) );});
760
761 if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
762 dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
763 clk_mgr->smu_wm_set.wm_set);
764}