Bug Summary

File:dev/ic/elink3.c
Warning:line 1360, column 2
Value stored to 'len' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name elink3.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/ic/elink3.c
1/* $OpenBSD: elink3.c,v 1.101 2023/11/10 15:51:20 bluhm Exp $ */
2/* $NetBSD: elink3.c,v 1.32 1997/05/14 00:22:00 thorpej Exp $ */
3
4/*
5 * Copyright (c) 1996, 1997 Jonathan Stone <jonathan@NetBSD.org>
6 * Copyright (c) 1994 Herb Peyerl <hpeyerl@beer.org>
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by Herb Peyerl.
20 * 4. The name of Herb Peyerl may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include "bpfilter.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/mbuf.h>
40#include <sys/socket.h>
41#include <sys/ioctl.h>
42#include <sys/errno.h>
43#include <sys/syslog.h>
44#include <sys/timeout.h>
45#include <sys/device.h>
46
47#include <net/if.h>
48#include <net/if_media.h>
49
50#include <netinet/in.h>
51#include <netinet/if_ether.h>
52
53#if NBPFILTER1 > 0
54#include <net/bpf.h>
55#endif
56
57#include <machine/cpu.h>
58#include <machine/bus.h>
59
60#include <dev/mii/mii.h>
61#include <dev/mii/miivar.h>
62
63#include <dev/ic/elink3var.h>
64#include <dev/ic/elink3reg.h>
65
66/*
67 * Structure to map media-present bits in boards to
68 * ifmedia codes and printable media names. Used for table-driven
69 * ifmedia initialization.
70 */
71struct ep_media {
72 int epm_eeprom_data; /* bitmask for eeprom config */
73 int epm_conn; /* sc->ep_connectors code for medium */
74 char *epm_name; /* name of medium */
75 uint64_t epm_ifmedia; /* ifmedia word for medium */
76 int epm_ifdata;
77};
78
79/*
80 * ep_media table for Vortex/Demon/Boomerang:
81 * map from media-present bits in register RESET_OPTIONS+2
82 * to ifmedia "media words" and printable names.
83 *
84 * XXX indexed directly by INTERNAL_CONFIG default_media field,
85 * (i.e., EPMEDIA_ constants) forcing order of entries.
86 * Note that 3 is reserved.
87 */
88const struct ep_media ep_vortex_media[] = {
89 { EP_PCI_UTP(1<<3), EPC_UTP0x08, "utp", IFM_ETHER0x0000000000000100ULL|IFM_10_T3,
90 EPMEDIA_10BASE_T(u_short) 0x00 },
91 { EP_PCI_AUI(1<<5), EPC_AUI0x01, "aui", IFM_ETHER0x0000000000000100ULL|IFM_10_55,
92 EPMEDIA_AUI(u_short) 0x01 },
93 { 0, 0, "reserved", IFM_NONE2ULL, EPMEDIA_RESV1(u_short) 0x02 },
94 { EP_PCI_BNC(1<<4), EPC_BNC0x02, "bnc", IFM_ETHER0x0000000000000100ULL|IFM_10_24,
95 EPMEDIA_10BASE_2(u_short) 0x03 },
96 { EP_PCI_100BASE_TX(1<<1), EPC_100TX0x10, "100-TX", IFM_ETHER0x0000000000000100ULL|IFM_100_TX6,
97 EPMEDIA_100BASE_TX(u_short) 0x04 },
98 { EP_PCI_100BASE_FX(1<<2), EPC_100FX0x20, "100-FX", IFM_ETHER0x0000000000000100ULL|IFM_100_FX7,
99 EPMEDIA_100BASE_FX(u_short) 0x05 },
100 { EP_PCI_100BASE_MII(1<<6),EPC_MII0x40, "mii", IFM_ETHER0x0000000000000100ULL|IFM_100_TX6,
101 EPMEDIA_MII(u_short) 0x06 },
102 { EP_PCI_100BASE_T4(1<<0), EPC_100T40x80, "100-T4", IFM_ETHER0x0000000000000100ULL|IFM_100_T48,
103 EPMEDIA_100BASE_T4(u_short) 0x07 }
104};
105
106/*
107 * ep_media table for 3c509/3c509b/3c579/3c589:
108 * map from media-present bits in register CNFG_CNTRL
109 * (window 0, offset ?) to ifmedia "media words" and printable names.
110 */
111struct ep_media ep_isa_media[] = {
112 { EP_W0_CC_UTP(1<<9), EPC_UTP0x08, "utp", IFM_ETHER0x0000000000000100ULL|IFM_10_T3, EPMEDIA_10BASE_T(u_short) 0x00 },
113 { EP_W0_CC_AUI(1<<13), EPC_AUI0x01, "aui", IFM_ETHER0x0000000000000100ULL|IFM_10_55, EPMEDIA_AUI(u_short) 0x01 },
114 { EP_W0_CC_BNC(1<<12), EPC_BNC0x02, "bnc", IFM_ETHER0x0000000000000100ULL|IFM_10_24, EPMEDIA_10BASE_2(u_short) 0x03 },
115};
116
117/* Map vortex reset_options bits to if_media codes. */
118const uint64_t ep_default_to_media[] = {
119 IFM_ETHER0x0000000000000100ULL | IFM_10_T3,
120 IFM_ETHER0x0000000000000100ULL | IFM_10_55,
121 0, /* reserved by 3Com */
122 IFM_ETHER0x0000000000000100ULL | IFM_10_24,
123 IFM_ETHER0x0000000000000100ULL | IFM_100_TX6,
124 IFM_ETHER0x0000000000000100ULL | IFM_100_FX7,
125 IFM_ETHER0x0000000000000100ULL | IFM_100_TX6, /* XXX really MII: need to talk to PHY */
126 IFM_ETHER0x0000000000000100ULL | IFM_100_T48,
127};
128
129struct cfdriver ep_cd = {
130 NULL((void *)0), "ep", DV_IFNET
131};
132
133void ep_vortex_probemedia(struct ep_softc *sc);
134void ep_isa_probemedia(struct ep_softc *sc);
135
136void eptxstat(struct ep_softc *);
137int epstatus(struct ep_softc *);
138int epioctl(struct ifnet *, u_long, caddr_t);
139void epstart(struct ifnet *);
140void epwatchdog(struct ifnet *);
141void epreset(struct ep_softc *);
142void epread(struct ep_softc *);
143struct mbuf *epget(struct ep_softc *, int);
144void epmbuffill(void *);
145void epmbufempty(struct ep_softc *);
146void epsetfilter(struct ep_softc *);
147void ep_roadrunner_mii_enable(struct ep_softc *);
148int epsetmedia(struct ep_softc *, int);
149
150/* ifmedia callbacks */
151int ep_media_change(struct ifnet *);
152void ep_media_status(struct ifnet *, struct ifmediareq *);
153
154/* MII callbacks */
155int ep_mii_readreg(struct device *, int, int);
156void ep_mii_writereg(struct device *, int, int, int);
157void ep_statchg(struct device *);
158
159void ep_mii_setbit(struct ep_softc *, u_int16_t);
160void ep_mii_clrbit(struct ep_softc *, u_int16_t);
161u_int16_t ep_mii_readbit(struct ep_softc *, u_int16_t);
162void ep_mii_sync(struct ep_softc *);
163void ep_mii_sendbits(struct ep_softc *, u_int32_t, int);
164
165int epbusyeeprom(struct ep_softc *);
166u_int16_t ep_read_eeprom(struct ep_softc *, u_int16_t);
167
168static inline void ep_reset_cmd(struct ep_softc *sc, u_int cmd,u_int arg);
169static inline void ep_finish_reset(bus_space_tag_t, bus_space_handle_t);
170static inline void ep_discard_rxtop(bus_space_tag_t, bus_space_handle_t);
171static __inline int ep_w1_reg(struct ep_softc *, int);
172
173/*
174 * Issue a (reset) command, and be sure it has completed.
175 * Used for global reset, TX_RESET, RX_RESET.
176 */
177static inline void
178ep_reset_cmd(struct ep_softc *sc, u_int cmd, u_int arg)
179{
180 bus_space_tag_t iot = sc->sc_iot;
181 bus_space_handle_t ioh = sc->sc_ioh;
182
183 bus_space_write_2(iot, ioh, cmd, arg)((iot)->write_2((ioh), (cmd), (arg)));
184 ep_finish_reset(iot, ioh);
185}
186
187/*
188 * Wait for any pending reset to complete.
189 */
190static inline void
191ep_finish_reset(bus_space_tag_t iot, bus_space_handle_t ioh)
192{
193 int i;
194
195 for (i = 0; i < 10000; i++) {
196 if ((bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e))) &
197 S_COMMAND_IN_PROGRESS(u_short) (0x1000)) == 0)
198 break;
199 DELAY(10)(*delay_func)(10);
200 }
201}
202
203static inline void
204ep_discard_rxtop(bus_space_tag_t iot, bus_space_handle_t ioh)
205{
206 int i;
207
208 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISCARD_TOP_PACK)((iot)->write_2((ioh), (0x0e), ((u_short) (0x8<<11))
));
209
210 /*
211 * Spin for about 1 msec, to avoid forcing a DELAY() between
212 * every received packet (adding latency and limiting pkt-recv rate).
213 * On PCI, at 4 30-nsec PCI bus cycles for a read, 8000 iterations
214 * is about right.
215 */
216 for (i = 0; i < 8000; i++) {
217 if ((bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e))) &
218 S_COMMAND_IN_PROGRESS(u_short) (0x1000)) == 0)
219 return;
220 }
221
222 /* not fast enough, do DELAY()s */
223 ep_finish_reset(iot, ioh);
224}
225
226/*
227 * Some chips (i.e., 3c574 RoadRunner) have Window 1 registers offset.
228 */
229static __inline int
230ep_w1_reg(struct ep_softc *sc, int reg)
231{
232 switch (sc->ep_chipset) {
233 case EP_CHIPSET_ROADRUNNER0x05:
234 switch (reg) {
235 case EP_W1_FREE_TX0x0c:
236 case EP_W1_RUNNER_RDCTL0x16:
237 case EP_W1_RUNNER_WRCTL0x1c:
238 return (reg);
239 }
240 return (reg + 0x10);
241 }
242 return (reg);
243}
244
245/*
246 * Back-end attach and configure.
247 */
248void
249epconfig(struct ep_softc *sc, u_short chipset, u_int8_t *enaddr)
250{
251 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
252 bus_space_tag_t iot = sc->sc_iot;
253 bus_space_handle_t ioh = sc->sc_ioh;
254 u_int16_t i;
255
256 sc->ep_chipset = chipset;
257
258 /*
259 * We could have been groveling around in other register
260 * windows in the front-end; make sure we're in window 0
261 * to read the EEPROM.
262 */
263 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
264
265 if (enaddr == NULL((void *)0)) {
266 /*
267 * Read the station address from the eeprom.
268 */
269 for (i = 0; i < 3; i++) {
270 u_int16_t x = ep_read_eeprom(sc, i);
271
272 sc->sc_arpcom.ac_enaddr[(i << 1)] = x >> 8;
273 sc->sc_arpcom.ac_enaddr[(i << 1) + 1] = x;
274 }
275 } else {
276 bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN6);
277 }
278
279 printf(" address %s", ether_sprintf(sc->sc_arpcom.ac_enaddr));
280 if (sc->ep_flags & EP_FLAGS_MII0x4000)
281 printf("\n");
282 else
283 printf(", ");
284
285 /*
286 * Vortex-based (3c59x pci,eisa) cards allow FDDI-sized (4500) byte
287 * packets. Commands only take an 11-bit parameter, and 11 bits
288 * isn't enough to hold a full-size packet length.
289 * Commands to these cards implicitly upshift a packet size
290 * or threshold by 2 bits.
291 * To detect cards with large-packet support, we probe by setting
292 * the transmit threshold register, then change windows and
293 * read back the threshold register directly, and see if the
294 * threshold value was shifted or not.
295 */
296 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)))
297 SET_TX_AVAIL_THRESH | EP_LARGEWIN_PROBE )((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)));
298 GO_WINDOW(5)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|5)));
299 i = bus_space_read_2(iot, ioh, EP_W5_TX_AVAIL_THRESH)((iot)->read_2((ioh), (0x02)));
300 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)));
301 switch (i) {
302 case EP_LARGEWIN_PROBE2047:
303 case (EP_LARGEWIN_PROBE2047 & EP_LARGEWIN_MASK0xffc):
304 sc->txashift = 0;
305 break;
306
307 case (EP_LARGEWIN_PROBE2047 << 2):
308 sc->txashift = 2;
309 /* XXX does the 3c515 support Vortex-style RESET_OPTIONS? */
310 break;
311
312 default:
313 printf("wrote %x to TX_AVAIL_THRESH, read back %x. "
314 "Interface disabled\n", EP_THRESH_DISABLE2047, (int) i);
315 return;
316 }
317
318 timeout_set(&sc->sc_epmbuffill_tmo, epmbuffill, sc);
319
320 /*
321 * Ensure Tx-available interrupts are enabled for
322 * start the interface.
323 * XXX should be in epinit()?
324 */
325 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))))
326 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift))((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))));
327
328 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ16);
329 ifp->if_softc = sc;
330 ifp->if_start = epstart;
331 ifp->if_ioctl = epioctl;
332 ifp->if_watchdog = epwatchdog;
333 ifp->if_flags =
334 IFF_BROADCAST0x2 | IFF_SIMPLEX0x800 | IFF_MULTICAST0x8000;
335 /* 64 packets are around 100ms on 10Mbps */
336 ifq_init_maxlen(&ifp->if_snd, 64);
337
338 if_attach(ifp);
339 ether_ifattach(ifp);
340
341 /*
342 * Finish configuration:
343 * determine chipset if the front-end couldn't do so,
344 * show board details, set media.
345 */
346
347 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
348
349 ifmedia_init(&sc->sc_mii.mii_media, 0, ep_media_change,
350 ep_media_status);
351 sc->sc_mii.mii_ifp = ifp;
352 sc->sc_mii.mii_readreg = ep_mii_readreg;
353 sc->sc_mii.mii_writereg = ep_mii_writereg;
354 sc->sc_mii.mii_statchg = ep_statchg;
355
356 /*
357 * If we've got an indirect (ISA, PCMCIA?) board, the chipset
358 * is unknown. If the board has large-packet support, it's a
359 * Vortex/Boomerang, otherwise it's a 3c509.
360 * XXX use eeprom capability word instead?
361 */
362 if (sc->ep_chipset == EP_CHIPSET_UNKNOWN0x00 && sc->txashift) {
363 printf("warning: unknown chipset, possibly 3c515?\n");
364#ifdef notyet
365 sc->sc_chipset = EP_CHIPSET_VORTEX0x02;
366#endif /* notyet */
367 }
368
369 /*
370 * Ascertain which media types are present and inform ifmedia.
371 */
372 switch (sc->ep_chipset) {
373 case EP_CHIPSET_ROADRUNNER0x05:
374 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
375 ep_roadrunner_mii_enable(sc);
376 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
377 }
378 /* FALLTHROUGH */
379
380 case EP_CHIPSET_BOOMERANG0x03:
381 /*
382 * If the device has MII, probe it. We won't be using
383 * any `native' media in this case, only PHYs. If
384 * we don't, just treat the Boomerang like the Vortex.
385 */
386 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
387 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
388 MII_PHY_ANY-1, MII_OFFSET_ANY-1, 0);
389 if (LIST_FIRST(&sc->sc_mii.mii_phys)((&sc->sc_mii.mii_phys)->lh_first) == NULL((void *)0)) {
390 ifmedia_add(&sc->sc_mii.mii_media,
391 IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL, 0, NULL((void *)0));
392 ifmedia_set(&sc->sc_mii.mii_media,
393 IFM_ETHER0x0000000000000100ULL|IFM_NONE2ULL);
394 } else {
395 ifmedia_set(&sc->sc_mii.mii_media,
396 IFM_ETHER0x0000000000000100ULL|IFM_AUTO0ULL);
397 }
398 break;
399 }
400 /* FALLTHROUGH */
401
402 /* on a direct bus, the attach routine can tell, but check anyway. */
403 case EP_CHIPSET_VORTEX0x02:
404 case EP_CHIPSET_BOOMERANG20x04:
405 ep_vortex_probemedia(sc);
406 break;
407
408 /* on ISA we can't yet tell 3c509 from 3c515. Assume the former. */
409 case EP_CHIPSET_3C5090x01:
410 default:
411 ep_isa_probemedia(sc);
412 break;
413 }
414
415 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* Window 1 is operating window */
416
417 sc->tx_start_thresh = 20; /* probably a good starting point. */
418
419 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
420 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
421}
422
423int
424ep_detach(struct device *self)
425{
426 struct ep_softc *sc = (struct ep_softc *)self;
427 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
428
429 if (sc->ep_flags & EP_FLAGS_MII0x4000)
430 mii_detach(&sc->sc_mii, MII_PHY_ANY-1, MII_OFFSET_ANY-1);
431
432 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY((uint64_t) -1));
433
434 ether_ifdetach(ifp);
435 if_detach(ifp);
436
437 return (0);
438}
439
440/*
441 * Find supported media on 3c509-generation hardware that doesn't have
442 * a "reset_options" register in window 3.
443 * Use the config_cntrl register in window 0 instead.
444 * Used on original, 10Mbit ISA (3c509), 3c509B, and pre-Demon EISA cards
445 * that implement CONFIG_CTRL. We don't have a good way to set the
446 * default active medium; punt to ifconfig instead.
447 *
448 * XXX what about 3c515, pcmcia 10/100?
449 */
450void
451ep_isa_probemedia(struct ep_softc *sc)
452{
453 bus_space_tag_t iot = sc->sc_iot;
454 bus_space_handle_t ioh = sc->sc_ioh;
455 struct ifmedia *ifm = &sc->sc_mii.mii_media;
456 int conn, i;
457 u_int16_t ep_w0_config, port;
458
459 conn = 0;
460 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
461 ep_w0_config = bus_space_read_2(iot, ioh, EP_W0_CONFIG_CTRL)((iot)->read_2((ioh), (0x04)));
462 for (i = 0; i < nitems(ep_isa_media)(sizeof((ep_isa_media)) / sizeof((ep_isa_media)[0])); i++) {
463 struct ep_media * epm = ep_isa_media + i;
464
465 if ((ep_w0_config & epm->epm_eeprom_data) != 0) {
466 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0);
467 if (conn)
468 printf("/");
469 printf("%s", epm->epm_name);
470 conn |= epm->epm_conn;
471 }
472 }
473 sc->ep_connectors = conn;
474
475 /* get default medium from EEPROM */
476 if (epbusyeeprom(sc))
477 return; /* XXX why is eeprom busy? */
478 bus_space_write_2(iot, ioh, EP_W0_EEPROM_COMMAND,((iot)->write_2((ioh), (0x0a), ((1<<7) | 0x8)))
479 READ_EEPROM | EEPROM_ADDR_CFG)((iot)->write_2((ioh), (0x0a), ((1<<7) | 0x8)));
480 if (epbusyeeprom(sc))
481 return; /* XXX why is eeprom busy? */
482 port = bus_space_read_2(iot, ioh, EP_W0_EEPROM_DATA)((iot)->read_2((ioh), (0x0c)));
483 port = port >> 14;
484
485 printf(" (default %s)\n", ep_vortex_media[port].epm_name);
486
487 /* tell ifconfig what currently-active media is. */
488 ifmedia_set(ifm, ep_default_to_media[port]);
489
490 /* XXX autoselect not yet implemented */
491}
492
493
494/*
495 * Find media present on large-packet-capable elink3 devices.
496 * Show onboard configuration of large-packet-capable elink3 devices
497 * (Demon, Vortex, Boomerang), which do not implement CONFIG_CTRL in window 0.
498 * Use media and card-version info in window 3 instead.
499 *
500 * XXX how much of this works with 3c515, pcmcia 10/100?
501 */
502void
503ep_vortex_probemedia(struct ep_softc *sc)
504{
505 bus_space_tag_t iot = sc->sc_iot;
506 bus_space_handle_t ioh = sc->sc_ioh;
507 struct ifmedia *ifm = &sc->sc_mii.mii_media;
508 u_int config1, conn;
509 int reset_options;
510 int default_media; /* 3-bit encoding of default (EEPROM) media */
511 int autoselect; /* boolean: should default to autoselect */
512 const char *medium_name;
513 register int i;
514
515 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)));
516 config1 = (u_int)bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
517 reset_options = (int)bus_space_read_1(iot, ioh, EP_W3_RESET_OPTIONS)((iot)->read_1((ioh), (0x08)));
518 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
519
520 default_media = (config1 & CONFIG_MEDIAMASK(u_short) 0x0070) >> CONFIG_MEDIAMASK_SHIFT(u_short) 4;
521 autoselect = (config1 & CONFIG_AUTOSELECT(u_short) 0x0100) >> CONFIG_AUTOSELECT_SHIFT(u_short) 8;
522
523 /* set available media options */
524 conn = 0;
525 for (i = 0; i < nitems(ep_vortex_media)(sizeof((ep_vortex_media)) / sizeof((ep_vortex_media)[0])); i++) {
526 const struct ep_media *epm = ep_vortex_media + i;
527
528 if ((reset_options & epm->epm_eeprom_data) != 0) {
529 if (conn)
530 printf("/");
531 printf("%s", epm->epm_name);
532 conn |= epm->epm_conn;
533 ifmedia_add(ifm, epm->epm_ifmedia, epm->epm_ifdata, 0);
534 }
535 }
536
537 sc->ep_connectors = conn;
538
539 /* Show eeprom's idea of default media. */
540 medium_name = (default_media > nitems(ep_vortex_media)(sizeof((ep_vortex_media)) / sizeof((ep_vortex_media)[0])) - 1)
541 ? "(unknown/impossible media)"
542 : ep_vortex_media[default_media].epm_name;
543 printf(" default %s%s",
544 medium_name, (autoselect) ? "/autoselect" : "");
545/* sc->sc_media = ep_vortex_media[default_media].epm_ifdata;*/
546
547#ifdef notyet
548 /*
549 * Set default: either the active interface the card
550 * reads from the EEPROM, or if autoselect is true,
551 * whatever we find is actually connected.
552 *
553 * XXX autoselect not yet implemented.
554 */
555#endif /* notyet */
556
557 /* tell ifconfig what currently-active media is. */
558 ifmedia_set(ifm, ep_default_to_media[default_media]);
559}
560
561/*
562 * Bring device up.
563 *
564 * The order in here seems important. Otherwise we may not receive
565 * interrupts. ?!
566 */
567void
568epinit(struct ep_softc *sc)
569{
570 register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
571 bus_space_tag_t iot = sc->sc_iot;
572 bus_space_handle_t ioh = sc->sc_ioh;
573 int i;
574
575 /* make sure any pending reset has completed before touching board */
576 ep_finish_reset(iot, ioh);
577
578 /* cancel any pending I/O */
579 epstop(sc);
580
581 if (sc->bustype != EP_BUS_PCI0x3) {
582 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
583 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, 0)((iot)->write_2((ioh), (0x04), (0)));
584 bus_space_write_2(iot, ioh, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ)((iot)->write_2((ioh), (0x04), (0x0001)));
585 }
586
587 if (sc->bustype == EP_BUS_PCMCIA0x1) {
588 bus_space_write_2(iot, ioh, EP_W0_RESOURCE_CFG, 0x3f00)((iot)->write_2((ioh), (0x08), (0x3f00)));
589 }
590
591 GO_WINDOW(2)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|2)));
592 for (i = 0; i < 6; i++) /* Reload the ether_addr. */
593 bus_space_write_1(iot, ioh, EP_W2_ADDR_0 + i,((iot)->write_1((ioh), (0x00 + i), (sc->sc_arpcom.ac_enaddr
[i])))
594 sc->sc_arpcom.ac_enaddr[i])((iot)->write_1((ioh), (0x00 + i), (sc->sc_arpcom.ac_enaddr
[i])));
595
596 if (sc->bustype == EP_BUS_PCI0x3 || sc->bustype == EP_BUS_EISA0x2)
597 /*
598 * Reset the station-address receive filter.
599 * A bug workaround for busmastering (Vortex, Demon) cards.
600 */
601 for (i = 0; i < 6; i++)
602 bus_space_write_1(iot, ioh, EP_W2_RECVMASK_0 + i, 0)((iot)->write_1((ioh), (0x06 + i), (0)));
603
604 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
605 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
606
607 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* Window 1 is operating window */
608 for (i = 0; i < 31; i++)
609 bus_space_read_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS))((iot)->read_1((ioh), (ep_w1_reg(sc, 0x0b))));
610
611 /* Set threshold for Tx-space available interrupt. */
612 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))))
613 SET_TX_AVAIL_THRESH | (1600 >> sc->txashift))((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| (1600 >> sc->txashift))));
614
615 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05) {
616 /* Enable options in the PCMCIA LAN COR register, via
617 * RoadRunner Window 1.
618 *
619 * XXX MAGIC CONSTANTS!
620 */
621 u_int16_t cor;
622
623 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, (1 << 11))((iot)->write_2((ioh), (0x16), ((1 << 11))));
624
625 cor = bus_space_read_2(iot, ioh, 0)((iot)->read_2((ioh), (0))) & ~0x30;
626 bus_space_write_2(iot, ioh, 0, cor)((iot)->write_2((ioh), (0), (cor)));
627
628 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0)((iot)->write_2((ioh), (0x1c), (0)));
629 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0)((iot)->write_2((ioh), (0x16), (0)));
630
631 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
632 ep_roadrunner_mii_enable(sc);
633 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)));
634 }
635 }
636
637 /* Enable interrupts. */
638 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK |((iot)->write_2((ioh), (0x0e), ((u_short) (0x0f<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))))
639 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0f<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))));
640 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK |((iot)->write_2((ioh), (0x0e), ((u_short) (0x0e<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))))
641 S_CARD_FAILURE | S_RX_COMPLETE | S_TX_COMPLETE | S_TX_AVAIL)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0e<<11)
| (u_short) (0x0002) | (u_short) (0x0010) | (u_short) (0x0004
) | (u_short) (0x0008))));
642
643 /*
644 * Attempt to get rid of any stray interrupts that occurred during
645 * configuration. On the i386 this isn't possible because one may
646 * already be queued. However, a single stray interrupt is
647 * unimportant.
648 */
649 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | 0xff)((iot)->write_2((ioh), (0x0e), ((u_short) (0x6800) | 0xff)
));
650
651 epsetfilter(sc);
652 epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data);
653
654 bus_space_write_2(iot, ioh, EP_COMMAND, RX_ENABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x4<<11))
));
655 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x9<<11))
));
656
657 epmbuffill(sc);
658
659 /* Interface is now `running', with no output active. */
660 ifp->if_flags |= IFF_RUNNING0x40;
661 ifq_clr_oactive(&ifp->if_snd);
662
663 /* Attempt to start output, if any. */
664 epstart(ifp);
665}
666
667/*
668 * Set multicast receive filter.
669 * elink3 hardware has no selective multicast filter in hardware.
670 * Enable reception of all multicasts and filter in software.
671 */
672void
673epsetfilter(struct ep_softc *sc)
674{
675 register struct ifnet *ifp = &sc->sc_arpcom.ac_if;
676
677 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* Window 1 is operating window */
678 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_COMMAND, SET_RX_FILTER |((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
679 FIL_INDIVIDUAL | FIL_BRDCST |((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
680 ((ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0 ) |((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))))
681 ((ifp->if_flags & IFF_PROMISC) ? FIL_PROMISC : 0 ))((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x10<<11) | (u_short) (0x01) | (u_short) (0x04) | ((
ifp->if_flags & 0x8000) ? (u_short) (0x02) : 0 ) | ((ifp
->if_flags & 0x100) ? (u_short) (0x08) : 0 ))));
682}
683
684
685int
686ep_media_change(struct ifnet *ifp)
687{
688 register struct ep_softc *sc = ifp->if_softc;
689
690 return epsetmedia(sc, sc->sc_mii.mii_media.ifm_cur->ifm_data);
691}
692
693/*
694 * Reset and enable the MII on the RoadRunner.
695 */
696void
697ep_roadrunner_mii_enable(struct ep_softc *sc)
698{
699 bus_space_tag_t iot = sc->sc_iot;
700 bus_space_handle_t ioh = sc->sc_ioh;
701
702 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)));
703 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)))
704 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)));
705 delay(1000)(*delay_func)(1000);
706 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), ((1<<6)|0x4000|0x8000
)))
707 EP_PCI_100BASE_MII|EP_RUNNER_MII_RESET|EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), ((1<<6)|0x4000|0x8000
)));
708 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
709 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
710 delay(1000)(*delay_func)(1000);
711 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)))
712 EP_PCI_100BASE_MII|EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), ((1<<6)|0x8000)));
713}
714
715/*
716 * Set active media to a specific given EPMEDIA_<> value.
717 * For vortex/demon/boomerang cards, update media field in w3_internal_config,
718 * and power on selected transceiver.
719 * For 3c509-generation cards (3c509/3c579/3c589/3c509B),
720 * update media field in w0_address_config, and power on selected xcvr.
721 */
722int
723epsetmedia(struct ep_softc *sc, int medium)
724{
725 bus_space_tag_t iot = sc->sc_iot;
726 bus_space_handle_t ioh = sc->sc_ioh;
727 int w4_media;
728 int config0, config1;
729
730 /*
731 * you can `ifconfig (link0|-link0) ep0' to get the following
732 * behaviour:
733 * -link0 disable AUI/UTP. enable BNC.
734 * link0 disable BNC. enable AUI.
735 * link1 if the card has a UTP connector, and link0 is
736 * set too, then you get the UTP port.
737 */
738
739 /*
740 * First, change the media-control bits in EP_W4_MEDIA_TYPE.
741 */
742
743 /* Turn everything off. First turn off linkbeat and UTP. */
744 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)));
745 w4_media = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE)((iot)->read_2((ioh), (0x0a)));
746 w4_media = w4_media & ~(ENABLE_UTP(0x40|0x80)|SQE_ENABLE0x08);
747 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, w4_media)((iot)->write_2((ioh), (0x0a), (w4_media)));
748
749 /* Turn off coax */
750 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x17<<11)
)));
751 delay(1000)(*delay_func)(1000);
752
753 /* If the device has MII, select it, and then tell the
754 * PHY which media to use.
755 */
756 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
757 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)));
758
759 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05) {
760 int resopt;
761
762 resopt = bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x08)))
763 EP_W3_RESET_OPTIONS)((iot)->read_2((ioh), (0x08)));
764 bus_space_write_2(iot, ioh, EP_W3_RESET_OPTIONS,((iot)->write_2((ioh), (0x08), (resopt | 0x8000)))
765 resopt | EP_RUNNER_ENABLE_MII)((iot)->write_2((ioh), (0x08), (resopt | 0x8000)));
766 }
767
768 config0 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00)))
769 EP_W3_INTERNAL_CONFIG)((iot)->read_2((ioh), (0x00)));
770 config1 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00 + 2)))
771 EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
772
773 config1 = config1 & ~CONFIG_MEDIAMASK(u_short) 0x0070;
774 config1 |= (EPMEDIA_MII(u_short) 0x06 << CONFIG_MEDIAMASK_SHIFT(u_short) 4);
775
776 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0)((iot)->write_2((ioh), (0x00), (config0)));
777 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1)((iot)->write_2((ioh), (0x00 + 2), (config1)));
778 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* back to operating window */
779
780 mii_mediachg(&sc->sc_mii);
781 return (0);
782 }
783
784 /*
785 * Now turn on the selected media/transceiver.
786 */
787 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)));
788 switch (medium) {
789 case EPMEDIA_10BASE_T(u_short) 0x00:
790 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE, (ENABLE_UTP |((iot)->write_2((ioh), (0x0a), (((0x40|0x80) | (sc->bustype
== 0x1 ? 0x0001 : 0)))))
791 (sc->bustype == EP_BUS_PCMCIA ? MEDIA_LED : 0)))((iot)->write_2((ioh), (0x0a), (((0x40|0x80) | (sc->bustype
== 0x1 ? 0x0001 : 0)))));
792 break;
793
794 case EPMEDIA_10BASE_2(u_short) 0x03:
795 bus_space_write_2(iot, ioh, EP_COMMAND, START_TRANSCEIVER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x2<<11))
));
796 DELAY(1000)(*delay_func)(1000); /* 50ms not enough? */
797 break;
798
799 /* XXX following only for new-generation cards */
800 case EPMEDIA_100BASE_TX(u_short) 0x04:
801 case EPMEDIA_100BASE_FX(u_short) 0x05:
802 case EPMEDIA_100BASE_T4(u_short) 0x07: /* XXX check documentation */
803 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,((iot)->write_2((ioh), (0x0a), (w4_media | 0x80)))
804 w4_media | LINKBEAT_ENABLE)((iot)->write_2((ioh), (0x0a), (w4_media | 0x80)));
805 DELAY(1000)(*delay_func)(1000); /* not strictly necessary? */
806 break;
807
808 case EPMEDIA_AUI(u_short) 0x01:
809 bus_space_write_2(iot, ioh, EP_W4_MEDIA_TYPE,((iot)->write_2((ioh), (0x0a), (w4_media | 0x08)))
810 w4_media | SQE_ENABLE)((iot)->write_2((ioh), (0x0a), (w4_media | 0x08)));
811 DELAY(1000)(*delay_func)(1000); /* not strictly necessary? */
812 break;
813 case EPMEDIA_MII(u_short) 0x06:
814 break;
815 default:
816#if defined(EP_DEBUG)
817 printf("%s unknown media 0x%x\n", sc->sc_dev.dv_xname, medium);
818#endif
819 break;
820
821 }
822
823 /*
824 * Tell the chip which PHY [sic] to use.
825 */
826 switch (sc->ep_chipset) {
827 case EP_CHIPSET_VORTEX0x02:
828 case EP_CHIPSET_BOOMERANG20x04:
829 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)));
830 config0 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00)))
831 EP_W3_INTERNAL_CONFIG)((iot)->read_2((ioh), (0x00)));
832 config1 = (u_int)bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (0x00 + 2)))
833 EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
834
835#if defined(EP_DEBUG)
836 printf("%s: read 0x%x, 0x%x from EP_W3_CONFIG register\n",
837 sc->sc_dev.dv_xname, config0, config1);
838#endif
839 config1 = config1 & ~CONFIG_MEDIAMASK(u_short) 0x0070;
840 config1 |= (medium << CONFIG_MEDIAMASK_SHIFT(u_short) 4);
841
842#if defined(EP_DEBUG)
843 printf("epsetmedia: %s: medium 0x%x, 0x%x to EP_W3_CONFIG\n",
844 sc->sc_dev.dv_xname, medium, config1);
845#endif
846 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG, config0)((iot)->write_2((ioh), (0x00), (config0)));
847 bus_space_write_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2, config1)((iot)->write_2((ioh), (0x00 + 2), (config1)));
848 break;
849
850 default:
851 GO_WINDOW(0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|0)));
852 config0 = bus_space_read_2(iot, ioh, EP_W0_ADDRESS_CFG)((iot)->read_2((ioh), (0x06)));
853 config0 &= 0x3fff;
854 bus_space_write_2(iot, ioh, EP_W0_ADDRESS_CFG,((iot)->write_2((ioh), (0x06), (config0 | (medium <<
14))))
855 config0 | (medium << 14))((iot)->write_2((ioh), (0x06), (config0 | (medium <<
14))));
856 DELAY(1000)(*delay_func)(1000);
857 break;
858 }
859
860 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* Window 1 is operating window */
861 return (0);
862}
863
864
865/*
866 * Get currently-selected media from card.
867 * (if_media callback, may be called before interface is brought up).
868 */
869void
870ep_media_status(struct ifnet *ifp, struct ifmediareq *req)
871{
872 register struct ep_softc *sc = ifp->if_softc;
873 bus_space_tag_t iot = sc->sc_iot;
874 bus_space_handle_t ioh = sc->sc_ioh;
875 u_int config1;
876 u_int ep_mediastatus;
877
878 /*
879 * If we have MII, go ask the PHY what's going on.
880 */
881 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
882 mii_pollstat(&sc->sc_mii);
883 req->ifm_active = sc->sc_mii.mii_media_active;
884 req->ifm_status = sc->sc_mii.mii_media_status;
885 return;
886 }
887
888 /* XXX read from softc when we start autosensing media */
889 req->ifm_active = sc->sc_mii.mii_media.ifm_cur->ifm_media;
890
891 switch (sc->ep_chipset) {
892 case EP_CHIPSET_VORTEX0x02:
893 case EP_CHIPSET_BOOMERANG0x03:
894 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)));
895 delay(5000)(*delay_func)(5000);
896
897 config1 = bus_space_read_2(iot, ioh, EP_W3_INTERNAL_CONFIG + 2)((iot)->read_2((ioh), (0x00 + 2)));
898 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)));
899
900 config1 =
901 (config1 & CONFIG_MEDIAMASK(u_short) 0x0070) >> CONFIG_MEDIAMASK_SHIFT(u_short) 4;
902 req->ifm_active = ep_default_to_media[config1];
903
904 /* XXX check full-duplex bits? */
905
906 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)));
907 req->ifm_status = IFM_AVALID0x0000000000000001ULL; /* XXX */
908 ep_mediastatus = bus_space_read_2(iot, ioh, EP_W4_MEDIA_TYPE)((iot)->read_2((ioh), (0x0a)));
909 if (ep_mediastatus & LINKBEAT_DETECT0x800)
910 req->ifm_status |= IFM_ACTIVE0x0000000000000002ULL; /* XXX automedia */
911
912 break;
913
914 case EP_CHIPSET_UNKNOWN0x00:
915 case EP_CHIPSET_3C5090x01:
916 req->ifm_status = 0; /* XXX */
917 break;
918
919 default:
920 printf("%s: media_status on unknown chipset 0x%x\n",
921 ifp->if_xname, sc->ep_chipset);
922 break;
923 }
924
925 /* XXX look for softc heartbeat for other chips or media */
926
927 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)));
928 return;
929}
930
931
932
933/*
934 * Start outputting on the interface.
935 * Always called as splnet().
936 */
937void
938epstart(struct ifnet *ifp)
939{
940 register struct ep_softc *sc = ifp->if_softc;
941 bus_space_tag_t iot = sc->sc_iot;
942 bus_space_handle_t ioh = sc->sc_ioh;
943 struct mbuf *m, *m0;
944 caddr_t data;
945 int sh, len, pad, txreg;
946
947 /* Don't transmit if interface is busy or not running */
948 if (!(ifp->if_flags & IFF_RUNNING0x40) || ifq_is_oactive(&ifp->if_snd))
949 return;
950
951startagain:
952 /* Sneak a peek at the next packet */
953 m0 = ifq_deq_begin(&ifp->if_snd);
954 if (m0 == NULL((void *)0))
955 return;
956
957 /* We need to use m->m_pkthdr.len, so require the header */
958 if ((m0->m_flagsm_hdr.mh_flags & M_PKTHDR0x0002) == 0)
959 panic("epstart: no header mbuf");
960 len = m0->m_pkthdrM_dat.MH.MH_pkthdr.len;
961
962 pad = (4 - len) & 3;
963
964 /*
965 * The 3c509 automatically pads short packets to minimum ethernet
966 * length, but we drop packets that are too large. Perhaps we should
967 * truncate them instead?
968 */
969 if (len + pad > ETHER_MAX_LEN1518) {
970 /* packet is obviously too large: toss it */
971 ++ifp->if_oerrorsif_data.ifi_oerrors;
972 ifq_deq_commit(&ifp->if_snd, m0);
973 m_freem(m0);
974 goto readcheck;
975 }
976
977 if (bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_FREE_TX))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x0c)))) <
978 len + pad + 4) {
979 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| ((len + pad + 4) >> sc->txashift))))
980 SET_TX_AVAIL_THRESH | ((len + pad + 4) >> sc->txashift))((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| ((len + pad + 4) >> sc->txashift))));
981 /* not enough room in FIFO */
982 ifq_deq_rollback(&ifp->if_snd, m0);
983 ifq_set_oactive(&ifp->if_snd);
984 return;
985 } else {
986 bus_space_write_2(iot, ioh, EP_COMMAND,((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)))
987 SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x12<<11)
| 2047)));
988 }
989
990 ifq_deq_commit(&ifp->if_snd, m0);
991 if (m0 == NULL((void *)0))
992 return;
993
994 bus_space_write_2(iot, ioh, EP_COMMAND, SET_TX_START_THRESH |((iot)->write_2((ioh), (0x0e), ((u_short) (0x13<<11)
| ((len / 4 + sc->tx_start_thresh) ))))
995 ((len / 4 + sc->tx_start_thresh) /*>> sc->txashift*/))((iot)->write_2((ioh), (0x0e), ((u_short) (0x13<<11)
| ((len / 4 + sc->tx_start_thresh) ))));
996
997#if NBPFILTER1 > 0
998 if (ifp->if_bpf)
999 bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT(1 << 1));
1000#endif
1001
1002 /*
1003 * Do the output at splhigh() so that an interrupt from another device
1004 * won't cause a FIFO underrun.
1005 */
1006 sh = splhigh()splraise(0xd);
1007
1008 txreg = ep_w1_reg(sc, EP_W1_TX_PIO_WR_10x00);
1009
1010 bus_space_write_2(iot, ioh, txreg, len)((iot)->write_2((ioh), (txreg), (len)));
1011 bus_space_write_2(iot, ioh, txreg, 0xffff)((iot)->write_2((ioh), (txreg), (0xffff))); /* Second is meaningless */
1012 if (EP_IS_BUS_32(sc->bustype)((sc->bustype) & 0x2)) {
1013 for (m = m0; m; ) {
1014 data = mtod(m, u_int8_t *)((u_int8_t *)((m)->m_hdr.mh_data));
1015 if (m->m_lenm_hdr.mh_len > 3 && ALIGNED_POINTER(data, uint32_t)1) {
1016 bus_space_write_raw_multi_4(iot, ioh, txreg,((iot)->write_multi_4((ioh), (txreg), (const u_int32_t *)(
data), (m->m_hdr.mh_len & ~3) >> 2))
1017 data, m->m_len & ~3)((iot)->write_multi_4((ioh), (txreg), (const u_int32_t *)(
data), (m->m_hdr.mh_len & ~3) >> 2));
1018 if (m->m_lenm_hdr.mh_len & 3)
1019 bus_space_write_multi_1(iot, ioh, txreg,((iot)->write_multi_1((ioh), (txreg), (data + (m->m_hdr
.mh_len & ~3)), (m->m_hdr.mh_len & 3)))
1020 data + (m->m_len & ~3),((iot)->write_multi_1((ioh), (txreg), (data + (m->m_hdr
.mh_len & ~3)), (m->m_hdr.mh_len & 3)))
1021 m->m_len & 3)((iot)->write_multi_1((ioh), (txreg), (data + (m->m_hdr
.mh_len & ~3)), (m->m_hdr.mh_len & 3)));
1022 } else
1023 bus_space_write_multi_1(iot, ioh, txreg,((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)))
1024 data, m->m_len)((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)));
1025 m0 = m_free(m);
1026 m = m0;
1027 }
1028 } else {
1029 for (m = m0; m; ) {
1030 data = mtod(m, u_int8_t *)((u_int8_t *)((m)->m_hdr.mh_data));
1031 if (m->m_lenm_hdr.mh_len > 1 && ALIGNED_POINTER(data, uint16_t)1) {
1032 bus_space_write_raw_multi_2(iot, ioh, txreg,((iot)->write_multi_2((ioh), (txreg), (const u_int16_t *)(
data), (m->m_hdr.mh_len & ~1) >> 1))
1033 data, m->m_len & ~1)((iot)->write_multi_2((ioh), (txreg), (const u_int16_t *)(
data), (m->m_hdr.mh_len & ~1) >> 1));
1034 if (m->m_lenm_hdr.mh_len & 1)
1035 bus_space_write_1(iot, ioh, txreg,((iot)->write_1((ioh), (txreg), (*(data + m->m_hdr.mh_len
- 1))))
1036 *(data + m->m_len - 1))((iot)->write_1((ioh), (txreg), (*(data + m->m_hdr.mh_len
- 1))));
1037 } else
1038 bus_space_write_multi_1(iot, ioh, txreg,((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)))
1039 data, m->m_len)((iot)->write_multi_1((ioh), (txreg), (data), (m->m_hdr
.mh_len)));
1040 m0 = m_free(m);
1041 m = m0;
1042 }
1043 }
1044 while (pad--)
1045 bus_space_write_1(iot, ioh, txreg, 0)((iot)->write_1((ioh), (txreg), (0)));
1046
1047 splx(sh)spllower(sh);
1048
1049readcheck:
1050 if ((bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08)))) &
1051 ERR_INCOMPLETE(u_short) (0x8000)) == 0) {
1052 /* We received a complete packet. */
1053 u_int16_t status = bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e)));
1054
1055 if ((status & S_INTR_LATCH(u_short) (0x0001)) == 0) {
1056 /*
1057 * No interrupt, read the packet and continue
1058 * Is this supposed to happen? Is my motherboard
1059 * completely busted?
1060 */
1061 epread(sc);
1062 } else
1063 /* Got an interrupt, return to get it serviced. */
1064 return;
1065 } else {
1066 /* Check if we are stuck and reset [see XXX comment] */
1067 if (epstatus(sc)) {
1068#ifdef EP_DEBUG
1069 if (ifp->if_flags & IFF_DEBUG0x4)
1070 printf("%s: adapter reset\n",
1071 sc->sc_dev.dv_xname);
1072#endif
1073 epreset(sc);
1074 }
1075 }
1076
1077 goto startagain;
1078}
1079
1080
1081/*
1082 * XXX: The 3c509 card can get in a mode where both the fifo status bit
1083 * FIFOS_RX_OVERRUN and the status bit ERR_INCOMPLETE are set
1084 * We detect this situation and we reset the adapter.
1085 * It happens at times when there is a lot of broadcast traffic
1086 * on the cable (once in a blue moon).
1087 */
1088int
1089epstatus(struct ep_softc *sc)
1090{
1091 bus_space_tag_t iot = sc->sc_iot;
1092 bus_space_handle_t ioh = sc->sc_ioh;
1093 u_int16_t fifost;
1094
1095 /*
1096 * Check the FIFO status and act accordingly
1097 */
1098 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)));
1099 fifost = bus_space_read_2(iot, ioh, EP_W4_FIFO_DIAG)((iot)->read_2((ioh), (0x04)));
1100 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1)));
1101
1102 if (fifost & FIFOS_RX_UNDERRUN(u_short) 0x2000) {
1103#ifdef EP_DEBUG
1104 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1105 printf("%s: RX underrun\n", sc->sc_dev.dv_xname);
1106#endif
1107 epreset(sc);
1108 return 0;
1109 }
1110
1111 if (fifost & FIFOS_RX_STATUS_OVERRUN(u_short) 0x1000) {
1112#ifdef EP_DEBUG
1113 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1114 printf("%s: RX Status overrun\n", sc->sc_dev.dv_xname);
1115#endif
1116 return 1;
1117 }
1118
1119 if (fifost & FIFOS_RX_OVERRUN(u_short) 0x0800) {
1120#ifdef EP_DEBUG
1121 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1122 printf("%s: RX overrun\n", sc->sc_dev.dv_xname);
1123#endif
1124 return 1;
1125 }
1126
1127 if (fifost & FIFOS_TX_OVERRUN(u_short) 0x0400) {
1128#ifdef EP_DEBUG
1129 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1130 printf("%s: TX overrun\n", sc->sc_dev.dv_xname);
1131#endif
1132 epreset(sc);
1133 return 0;
1134 }
1135
1136 return 0;
1137}
1138
1139
1140void
1141eptxstat(struct ep_softc *sc)
1142{
1143 bus_space_tag_t iot = sc->sc_iot;
1144 bus_space_handle_t ioh = sc->sc_ioh;
1145 int i;
1146
1147 /*
1148 * We need to read+write TX_STATUS until we get a 0 status
1149 * in order to turn off the interrupt flag.
1150 */
1151 while ((i = bus_space_read_1(iot, ioh,((iot)->read_1((ioh), (ep_w1_reg(sc, 0x0b))))
1152 ep_w1_reg(sc, EP_W1_TX_STATUS))((iot)->read_1((ioh), (ep_w1_reg(sc, 0x0b))))) & TXS_COMPLETE0x80) {
1153 bus_space_write_1(iot, ioh, ep_w1_reg(sc, EP_W1_TX_STATUS),((iot)->write_1((ioh), (ep_w1_reg(sc, 0x0b)), (0x0)))
1154 0x0)((iot)->write_1((ioh), (ep_w1_reg(sc, 0x0b)), (0x0)));
1155
1156 if (i & TXS_JABBER0x20) {
1157 ++sc->sc_arpcom.ac_if.if_oerrorsif_data.ifi_oerrors;
1158#ifdef EP_DEBUG
1159 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1160 printf("%s: jabber (%x)\n",
1161 sc->sc_dev.dv_xname, i);
1162#endif
1163 epreset(sc);
1164 } else if (i & TXS_UNDERRUN0x10) {
1165 ++sc->sc_arpcom.ac_if.if_oerrorsif_data.ifi_oerrors;
1166#ifdef EP_DEBUG
1167 if (sc->sc_arpcom.ac_if.if_flags & IFF_DEBUG0x4)
1168 printf("%s: fifo underrun (%x) @%d\n",
1169 sc->sc_dev.dv_xname, i,
1170 sc->tx_start_thresh);
1171#endif
1172 if (sc->tx_succ_ok < 100)
1173 sc->tx_start_thresh = min(ETHER_MAX_LEN1518,
1174 sc->tx_start_thresh + 20);
1175 sc->tx_succ_ok = 0;
1176 epreset(sc);
1177 } else if (i & TXS_MAX_COLLISION0x08) {
1178 ++sc->sc_arpcom.ac_if.if_collisionsif_data.ifi_collisions;
1179 bus_space_write_2(iot, ioh, EP_COMMAND, TX_ENABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x9<<11))
));
1180 ifq_clr_oactive(&sc->sc_arpcom.ac_if.if_snd);
1181 } else
1182 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
1183 }
1184}
1185
1186int
1187epintr(void *arg)
1188{
1189 register struct ep_softc *sc = arg;
1190 bus_space_tag_t iot = sc->sc_iot;
1191 bus_space_handle_t ioh = sc->sc_ioh;
1192 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1193 u_int16_t status;
1194 int ret = 0;
1195
1196 for (;;) {
1197 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH)((iot)->write_2((ioh), (0x0e), ((u_short) ((u_short) (0x6800
)|0x01))));
1198
1199 status = bus_space_read_2(iot, ioh, EP_STATUS)((iot)->read_2((ioh), (0x0e)));
1200
1201 if ((status & (S_TX_COMPLETE(u_short) (0x0004) | S_TX_AVAIL(u_short) (0x0008) |
1202 S_RX_COMPLETE(u_short) (0x0010) | S_CARD_FAILURE(u_short) (0x0002))) == 0)
1203 break;
1204
1205 ret = 1;
1206
1207 /*
1208 * Acknowledge any interrupts. It's important that we do this
1209 * first, since there would otherwise be a race condition.
1210 * Due to the i386 interrupt queueing, we may get spurious
1211 * interrupts occasionally.
1212 */
1213 bus_space_write_2(iot, ioh, EP_COMMAND, ACK_INTR | status)((iot)->write_2((ioh), (0x0e), ((u_short) (0x6800) | status
)));
1214
1215 if (status & S_RX_COMPLETE(u_short) (0x0010))
1216 epread(sc);
1217 if (status & S_TX_AVAIL(u_short) (0x0008)) {
1218 ifq_clr_oactive(&ifp->if_snd);
1219 epstart(ifp);
1220 }
1221 if (status & S_CARD_FAILURE(u_short) (0x0002)) {
1222 epreset(sc);
1223 return (1);
1224 }
1225 if (status & S_TX_COMPLETE(u_short) (0x0004)) {
1226 eptxstat(sc);
1227 epstart(ifp);
1228 }
1229 }
1230
1231 /* no more interrupts */
1232 return (ret);
1233}
1234
1235void
1236epread(struct ep_softc *sc)
1237{
1238 bus_space_tag_t iot = sc->sc_iot;
1239 bus_space_handle_t ioh = sc->sc_ioh;
1240 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1241 struct mbuf_list ml = MBUF_LIST_INITIALIZER(){ ((void *)0), ((void *)0), 0 };
1242 struct mbuf *m;
1243 int len, error = 0;
1244
1245 len = bus_space_read_2(iot, ioh, ep_w1_reg(sc, EP_W1_RX_STATUS))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08))));
1246
1247again:
1248#ifdef EP_DEBUG
1249 if (ifp->if_flags & IFF_DEBUG0x4) {
1250 int err = len & ERR_MASK(u_short) (0x7800);
1251 char *s = NULL((void *)0);
1252
1253 if (len & ERR_INCOMPLETE(u_short) (0x8000))
1254 s = "incomplete packet";
1255 else if (err == ERR_OVERRUN(u_short) (0x4000))
1256 s = "packet overrun";
1257 else if (err == ERR_RUNT(u_short) (0x5800))
1258 s = "runt packet";
1259 else if (err == ERR_ALIGNMENT(u_short) (0x6000))
1260 s = "bad alignment";
1261 else if (err == ERR_CRC(u_short) (0x6800))
1262 s = "bad crc";
1263 else if (err == ERR_OVERSIZE(u_short) (0x4800))
1264 s = "oversized packet";
1265 else if (err == ERR_DRIBBLE(u_short) (0x1000))
1266 s = "dribble bits";
1267
1268 if (s)
1269 printf("%s: %s\n", sc->sc_dev.dv_xname, s);
1270 }
1271#endif
1272
1273 if (len & ERR_INCOMPLETE(u_short) (0x8000))
1274 goto done;
1275
1276 if (len & ERR_RX(u_short) (0x4000)) {
1277 ++ifp->if_ierrorsif_data.ifi_ierrors;
1278 error = 1;
1279 goto done;
1280 }
1281
1282 len &= RX_BYTES_MASK(u_short) (0x07ff); /* Lower 11 bits = RX bytes. */
1283
1284 /* Pull packet off interface. */
1285 m = epget(sc, len);
1286 if (m == NULL((void *)0)) {
1287 ifp->if_ierrorsif_data.ifi_ierrors++;
1288 error = 1;
1289 goto done;
1290 }
1291
1292 ml_enqueue(&ml, m);
1293
1294 /*
1295 * In periods of high traffic we can actually receive enough
1296 * packets so that the fifo overrun bit will be set at this point,
1297 * even though we just read a packet. In this case we
1298 * are not going to receive any more interrupts. We check for
1299 * this condition and read again until the fifo is not full.
1300 * We could simplify this test by not using epstatus(), but
1301 * rechecking the RX_STATUS register directly. This test could
1302 * result in unnecessary looping in cases where there is a new
1303 * packet but the fifo is not full, but it will not fix the
1304 * stuck behavior.
1305 *
1306 * Even with this improvement, we still get packet overrun errors
1307 * which are hurting performance. Maybe when I get some more time
1308 * I'll modify epread() so that it can handle RX_EARLY interrupts.
1309 */
1310 if (epstatus(sc)) {
1311 len = bus_space_read_2(iot, ioh,((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08))))
1312 ep_w1_reg(sc, EP_W1_RX_STATUS))((iot)->read_2((ioh), (ep_w1_reg(sc, 0x08))));
1313 /* Check if we are stuck and reset [see XXX comment] */
1314 if (len & ERR_INCOMPLETE(u_short) (0x8000)) {
1315#ifdef EP_DEBUG
1316 if (ifp->if_flags & IFF_DEBUG0x4)
1317 printf("%s: adapter reset\n",
1318 sc->sc_dev.dv_xname);
1319#endif
1320 epreset(sc);
1321 goto done;
1322 }
1323 goto again;
1324 }
1325done:
1326 if (error)
1327 ep_discard_rxtop(iot, ioh);
1328 if_input(ifp, &ml);
1329}
1330
1331struct mbuf *
1332epget(struct ep_softc *sc, int totlen)
1333{
1334 bus_space_tag_t iot = sc->sc_iot;
1335 bus_space_handle_t ioh = sc->sc_ioh;
1336 struct mbuf *m;
1337 caddr_t data;
1338 int len, pad, off, sh, rxreg;
1339
1340 splassert(IPL_NET)do { if (splassert_ctl > 0) { splassert_check(0x4, __func__
); } } while (0);
1341
1342 m = sc->mb[sc->next_mb];
1343 sc->mb[sc->next_mb] = NULL((void *)0);
1344 if (m == NULL((void *)0)) {
1345 m = MCLGETL(NULL, M_DONTWAIT, MCLBYTES)m_clget((((void *)0)), (0x0002), ((1 << 11)));
1346 /* If the queue is no longer full, refill. */
1347 if (!timeout_pending(&sc->sc_epmbuffill_tmo)((&sc->sc_epmbuffill_tmo)->to_flags & 0x02))
1348 timeout_add(&sc->sc_epmbuffill_tmo, 1);
1349 }
1350 if (!m)
1351 return (NULL((void *)0));
1352
1353 sc->next_mb = (sc->next_mb + 1) % MAX_MBS8;
1354
1355 len = MCLBYTES(1 << 11);
1356 m->m_pkthdrM_dat.MH.MH_pkthdr.len = totlen;
1357 m->m_lenm_hdr.mh_len = totlen;
1358 pad = ALIGN(sizeof(struct ether_header))(((unsigned long)(sizeof(struct ether_header)) + (sizeof(long
) - 1)) &~(sizeof(long) - 1)) - sizeof(struct ether_header);
1359 m->m_datam_hdr.mh_data += pad;
1360 len -= pad;
Value stored to 'len' is never read
1361
1362 /*
1363 * We read the packet at splhigh() so that an interrupt from another
1364 * device doesn't cause the card's buffer to overflow while we're
1365 * reading it. We may still lose packets at other times.
1366 */
1367 sh = splhigh()splraise(0xd);
1368
1369 rxreg = ep_w1_reg(sc, EP_W1_RX_PIO_RD_10x00);
1370
1371 off = 0;
1372 while (totlen) {
1373 len = min(totlen, m_trailingspace(m));
1374 if (len == 0)
1375 panic("ep_get: packet does not fit in MCLBYTES");
1376
1377 data = mtod(m, u_int8_t *)((u_int8_t *)((m)->m_hdr.mh_data));
1378 if (EP_IS_BUS_32(sc->bustype)((sc->bustype) & 0x2))
1379 pad = 4 - ((u_long)(data + off) & 0x3);
1380 else
1381 pad = (u_long)(data + off) & 0x1;
1382
1383 if (pad) {
1384 if (pad < len)
1385 pad = len;
1386 bus_space_read_multi_1(iot, ioh, rxreg,((iot)->read_multi_1((ioh), (rxreg), (data + off), (pad)))
1387 data + off, pad)((iot)->read_multi_1((ioh), (rxreg), (data + off), (pad)));
1388 len = pad;
1389 } else if (EP_IS_BUS_32(sc->bustype)((sc->bustype) & 0x2) && len > 3 &&
1390 ALIGNED_POINTER(data, uint32_t)1) {
1391 len &= ~3;
1392 bus_space_read_raw_multi_4(iot, ioh, rxreg,((iot)->read_multi_4((ioh), (rxreg), (u_int32_t *)(data + off
), (len) >> 2))
1393 data + off, len)((iot)->read_multi_4((ioh), (rxreg), (u_int32_t *)(data + off
), (len) >> 2));
1394 } else if (len > 1 && ALIGNED_POINTER(data, uint16_t)1) {
1395 len &= ~1;
1396 bus_space_read_raw_multi_2(iot, ioh, rxreg,((iot)->read_multi_2((ioh), (rxreg), (u_int16_t *)(data + off
), (len) >> 1))
1397 data + off, len)((iot)->read_multi_2((ioh), (rxreg), (u_int16_t *)(data + off
), (len) >> 1));
1398 } else
1399 bus_space_read_multi_1(iot, ioh, rxreg,((iot)->read_multi_1((ioh), (rxreg), (data + off), (len)))
1400 data + off, len)((iot)->read_multi_1((ioh), (rxreg), (data + off), (len)));
1401
1402 off += len;
1403 totlen -= len;
1404 }
1405
1406 ep_discard_rxtop(iot, ioh);
1407
1408 splx(sh)spllower(sh);
1409
1410 return m;
1411}
1412
1413int
1414epioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1415{
1416 struct ep_softc *sc = ifp->if_softc;
1417 struct ifreq *ifr = (struct ifreq *)data;
1418 int s, error = 0;
1419
1420 s = splnet()splraise(0x4);
1421
1422 switch (cmd) {
1423 case SIOCSIFADDR((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((12))):
1424 ifp->if_flags |= IFF_UP0x1;
1425 if (!(ifp->if_flags & IFF_RUNNING0x40))
1426 epinit(sc);
1427 break;
1428
1429 case SIOCSIFFLAGS((unsigned long)0x80000000 | ((sizeof(struct ifreq) & 0x1fff
) << 16) | ((('i')) << 8) | ((16))):
1430 if (ifp->if_flags & IFF_UP0x1) {
1431 if (ifp->if_flags & IFF_RUNNING0x40)
1432 error = ENETRESET52;
1433 else
1434 epinit(sc);
1435 } else {
1436 if (ifp->if_flags & IFF_RUNNING0x40)
1437 epstop(sc);
1438 }
1439 break;
1440
1441 case SIOCSIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifreq) & 0x1fff) << 16) | ((('i')) <<
8) | ((55))):
1442 case SIOCGIFMEDIA(((unsigned long)0x80000000|(unsigned long)0x40000000) | ((sizeof
(struct ifmediareq) & 0x1fff) << 16) | ((('i')) <<
8) | ((56))):
1443 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
1444 break;
1445
1446 default:
1447 error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data);
1448 }
1449
1450 if (error == ENETRESET52) {
1451 if (ifp->if_flags & IFF_RUNNING0x40)
1452 epreset(sc);
1453 error = 0;
1454 }
1455
1456 splx(s)spllower(s);
1457 return (error);
1458}
1459
1460void
1461epreset(struct ep_softc *sc)
1462{
1463 int s;
1464
1465 s = splnet()splraise(0x4);
1466 epinit(sc);
1467 splx(s)spllower(s);
1468}
1469
1470void
1471epwatchdog(struct ifnet *ifp)
1472{
1473 struct ep_softc *sc = ifp->if_softc;
1474
1475 log(LOG_ERR3, "%s: device timeout\n", sc->sc_dev.dv_xname);
1476 ++sc->sc_arpcom.ac_if.if_oerrorsif_data.ifi_oerrors;
1477
1478 epreset(sc);
1479}
1480
1481void
1482epstop(struct ep_softc *sc)
1483{
1484 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1485 bus_space_tag_t iot = sc->sc_iot;
1486 bus_space_handle_t ioh = sc->sc_ioh;
1487
1488 ifp->if_flags &= ~IFF_RUNNING0x40;
1489 ifq_clr_oactive(&ifp->if_snd);
1490
1491 if (sc->ep_flags & EP_FLAGS_MII0x4000) {
1492 mii_down(&sc->sc_mii);
1493 }
1494
1495 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05) {
1496 /* Clear the FIFO buffer count, thus halting
1497 * any currently-running transactions.
1498 */
1499 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* sanity */
1500 bus_space_write_2(iot, ioh, EP_W1_RUNNER_WRCTL, 0)((iot)->write_2((ioh), (0x1c), (0)));
1501 bus_space_write_2(iot, ioh, EP_W1_RUNNER_RDCTL, 0)((iot)->write_2((ioh), (0x16), (0)));
1502 }
1503
1504 bus_space_write_2(iot, ioh, EP_COMMAND, RX_DISABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0x3<<11))
));
1505 ep_discard_rxtop(iot, ioh);
1506
1507 bus_space_write_2(iot, ioh, EP_COMMAND, TX_DISABLE)((iot)->write_2((ioh), (0x0e), ((u_short) (0xa<<11))
));
1508 bus_space_write_2(iot, ioh, EP_COMMAND, STOP_TRANSCEIVER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x17<<11)
)));
1509
1510 ep_reset_cmd(sc, EP_COMMAND0x0e, RX_RESET(u_short) (0x5<<11));
1511 ep_reset_cmd(sc, EP_COMMAND0x0e, TX_RESET(u_short) (0xb<<11));
1512
1513 bus_space_write_2(iot, ioh, EP_COMMAND, C_INTR_LATCH)((iot)->write_2((ioh), (0x0e), ((u_short) ((u_short) (0x6800
)|0x01))));
1514 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RD_0_MASK)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0f<<11)
)));
1515 bus_space_write_2(iot, ioh, EP_COMMAND, SET_INTR_MASK)((iot)->write_2((ioh), (0x0e), ((u_short) (0x0e<<11)
)));
1516 bus_space_write_2(iot, ioh, EP_COMMAND, SET_RX_FILTER)((iot)->write_2((ioh), (0x0e), ((u_short) (0x10<<11)
)));
1517
1518 epmbufempty(sc);
1519}
1520
1521/*
1522 * We get eeprom data from the id_port given an offset into the
1523 * eeprom. Basically; after the ID_sequence is sent to all of
1524 * the cards; they enter the ID_CMD state where they will accept
1525 * command requests. 0x80-0xbf loads the eeprom data. We then
1526 * read the port 16 times and with every read; the cards check
1527 * for contention (ie: if one card writes a 0 bit and another
1528 * writes a 1 bit then the host sees a 0. At the end of the cycle;
1529 * each card compares the data on the bus; if there is a difference
1530 * then that card goes into ID_WAIT state again). In the meantime;
1531 * one bit of data is returned in the AX register which is conveniently
1532 * returned to us by bus_space_read_1(). Hence; we read 16 times getting one
1533 * bit of data with each read.
1534 *
1535 * NOTE: the caller must provide an i/o handle for ELINK_ID_PORT!
1536 */
1537u_int16_t
1538epreadeeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int offset)
1539{
1540 u_int16_t data = 0;
1541 int i;
1542
1543 bus_space_write_1(iot, ioh, 0, 0x80 + offset)((iot)->write_1((ioh), (0), (0x80 + offset)));
1544 delay(1000)(*delay_func)(1000);
1545 for (i = 0; i < 16; i++)
1546 data = (data << 1) | (bus_space_read_2(iot, ioh, 0)((iot)->read_2((ioh), (0))) & 1);
1547 return (data);
1548}
1549
1550int
1551epbusyeeprom(struct ep_softc *sc)
1552{
1553 bus_space_tag_t iot = sc->sc_iot;
1554 bus_space_handle_t ioh = sc->sc_ioh;
1555 int i = 100, j;
1556
1557 while (i--) {
1558 j = bus_space_read_2(iot, ioh, EP_W0_EEPROM_COMMAND)((iot)->read_2((ioh), (0x0a)));
1559 if (j & EEPROM_BUSY(1<<15))
1560 delay(100)(*delay_func)(100);
1561 else
1562 break;
1563 }
1564 if (!i) {
1565 printf("\n%s: eeprom failed to come ready\n",
1566 sc->sc_dev.dv_xname);
1567 return (1);
1568 }
1569 if (sc->bustype != EP_BUS_PCMCIA0x1 && sc->bustype != EP_BUS_PCI0x3 &&
1570 (j & EEPROM_TST_MODE(1<<14))) {
1571 printf("\n%s: erase pencil mark, or disable PnP mode!\n",
1572 sc->sc_dev.dv_xname);
1573 return (1);
1574 }
1575 return (0);
1576}
1577
1578u_int16_t
1579ep_read_eeprom(struct ep_softc *sc, u_int16_t offset)
1580{
1581 u_int16_t readcmd;
1582
1583 /*
1584 * RoadRunner has a larger EEPROM, so a different read command
1585 * is required.
1586 */
1587 if (sc->ep_chipset == EP_CHIPSET_ROADRUNNER0x05)
1588 readcmd = READ_EEPROM_RR0x200;
1589 else
1590 readcmd = READ_EEPROM(1<<7);
1591
1592 if (epbusyeeprom(sc))
1593 return (0); /* XXX why is eeprom busy? */
1594 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_COMMAND,((sc->sc_iot)->write_2((sc->sc_ioh), (0x0a), (readcmd
| offset)))
1595 readcmd | offset)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0a), (readcmd
| offset)));
1596 if (epbusyeeprom(sc))
1597 return (0); /* XXX why is eeprom busy? */
1598
1599 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W0_EEPROM_DATA)((sc->sc_iot)->read_2((sc->sc_ioh), (0x0c))));
1600}
1601
1602void
1603epmbuffill(void *v)
1604{
1605 struct ep_softc *sc = v;
1606 int s, i;
1607
1608 s = splnet()splraise(0x4);
1609 for (i = 0; i < MAX_MBS8; i++) {
1610 if (sc->mb[i] == NULL((void *)0)) {
1611 sc->mb[i] = MCLGETL(NULL, M_DONTWAIT, MCLBYTES)m_clget((((void *)0)), (0x0002), ((1 << 11)));
1612 if (sc->mb[i] == NULL((void *)0))
1613 break;
1614 }
1615 }
1616 /* If the queue was not filled, try again. */
1617 if (i < MAX_MBS8)
1618 timeout_add(&sc->sc_epmbuffill_tmo, 1);
1619 splx(s)spllower(s);
1620}
1621
1622void
1623epmbufempty(struct ep_softc *sc)
1624{
1625 int s, i;
1626
1627 s = splnet()splraise(0x4);
1628 for (i = 0; i<MAX_MBS8; i++) {
1629 if (sc->mb[i]) {
1630 m_freem(sc->mb[i]);
1631 sc->mb[i] = NULL((void *)0);
1632 }
1633 }
1634 sc->next_mb = 0;
1635 timeout_del(&sc->sc_epmbuffill_tmo);
1636 splx(s)spllower(s);
1637}
1638
1639void
1640ep_mii_setbit(struct ep_softc *sc, u_int16_t bit)
1641{
1642 u_int16_t val;
1643
1644 /* We assume we're already in Window 4 */
1645 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT)((sc->sc_iot)->read_2((sc->sc_ioh), (0x08)));
1646 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT,((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val | bit
)))
1647 val | bit)((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val | bit
)));
1648}
1649
1650void
1651ep_mii_clrbit(struct ep_softc *sc, u_int16_t bit)
1652{
1653 u_int16_t val;
1654
1655 /* We assume we're already in Window 4 */
1656 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT)((sc->sc_iot)->read_2((sc->sc_ioh), (0x08)));
1657 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT,((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val &
~bit)))
1658 val & ~bit)((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (val &
~bit)));
1659}
1660
1661u_int16_t
1662ep_mii_readbit(struct ep_softc *sc, u_int16_t bit)
1663{
1664
1665 /* We assume we're already in Window 4 */
1666 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT)((sc->sc_iot)->read_2((sc->sc_ioh), (0x08))) &
1667 bit);
1668}
1669
1670void
1671ep_mii_sync(struct ep_softc *sc)
1672{
1673 int i;
1674
1675 /* We assume we're already in Window 4 */
1676 ep_mii_clrbit(sc, PHYSMGMT_DIR0x0004);
1677 for (i = 0; i < 32; i++) {
1678 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1679 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1680 }
1681}
1682
1683void
1684ep_mii_sendbits(struct ep_softc *sc, u_int32_t data, int nbits)
1685{
1686 int i;
1687
1688 /* We assume we're already in Window 4 */
1689 ep_mii_setbit(sc, PHYSMGMT_DIR0x0004);
1690 for (i = 1 << (nbits - 1); i; i = i >> 1) {
1691 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1692 ep_mii_readbit(sc, PHYSMGMT_CLK0x0001);
1693 if (data & i)
1694 ep_mii_setbit(sc, PHYSMGMT_DATA0x0002);
1695 else
1696 ep_mii_clrbit(sc, PHYSMGMT_DATA0x0002);
1697 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1698 ep_mii_readbit(sc, PHYSMGMT_CLK0x0001);
1699 }
1700}
1701
1702int
1703ep_mii_readreg(struct device *self, int phy, int reg)
1704{
1705 struct ep_softc *sc = (struct ep_softc *)self;
1706 int val = 0, i, err;
1707
1708 /*
1709 * Read the PHY register by manually driving the MII control lines.
1710 */
1711
1712 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)));
1713
1714 bus_space_write_2(sc->sc_iot, sc->sc_ioh, EP_W4_BOOM_PHYSMGMT, 0)((sc->sc_iot)->write_2((sc->sc_ioh), (0x08), (0)));
1715
1716 ep_mii_sync(sc);
1717 ep_mii_sendbits(sc, MII_COMMAND_START0x01, 2);
1718 ep_mii_sendbits(sc, MII_COMMAND_READ0x02, 2);
1719 ep_mii_sendbits(sc, phy, 5);
1720 ep_mii_sendbits(sc, reg, 5);
1721
1722 ep_mii_clrbit(sc, PHYSMGMT_DIR0x0004);
1723 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1724 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1725 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1726
1727 err = ep_mii_readbit(sc, PHYSMGMT_DATA0x0002);
1728 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1729
1730 /* Even if an error occurs, must still clock out the cycle. */
1731 for (i = 0; i < 16; i++) {
1732 val <<= 1;
1733 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1734 if (err == 0 && ep_mii_readbit(sc, PHYSMGMT_DATA0x0002))
1735 val |= 1;
1736 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1737 }
1738 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1739 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1740
1741 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* back to operating window */
1742
1743 return (err ? 0 : val);
1744}
1745
1746void
1747ep_mii_writereg(struct device *self, int phy, int reg, int val)
1748{
1749 struct ep_softc *sc = (struct ep_softc *)self;
1750
1751 /*
1752 * Write the PHY register by manually driving the MII control lines.
1753 */
1754
1755 GO_WINDOW(4)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|4)));
1756
1757 ep_mii_sync(sc);
1758 ep_mii_sendbits(sc, MII_COMMAND_START0x01, 2);
1759 ep_mii_sendbits(sc, MII_COMMAND_WRITE0x01, 2);
1760 ep_mii_sendbits(sc, phy, 5);
1761 ep_mii_sendbits(sc, reg, 5);
1762 ep_mii_sendbits(sc, MII_COMMAND_ACK0x02, 2);
1763 ep_mii_sendbits(sc, val, 16);
1764
1765 ep_mii_clrbit(sc, PHYSMGMT_CLK0x0001);
1766 ep_mii_setbit(sc, PHYSMGMT_CLK0x0001);
1767
1768 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* back to operating window */
1769}
1770
1771void
1772ep_statchg(struct device *self)
1773{
1774 struct ep_softc *sc = (struct ep_softc *)self;
1775 bus_space_tag_t iot = sc->sc_iot;
1776 bus_space_handle_t ioh = sc->sc_ioh;
1777 int mctl;
1778
1779 /* XXX Update ifp->if_baudrate */
1780
1781 GO_WINDOW(3)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|3)));
1782 mctl = bus_space_read_2(iot, ioh, EP_W3_MAC_CONTROL)((iot)->read_2((ioh), (0x06)));
1783 if (sc->sc_mii.mii_media_active & IFM_FDX0x0000010000000000ULL)
1784 mctl |= MAC_CONTROL_FDX0x20;
1785 else
1786 mctl &= ~MAC_CONTROL_FDX0x20;
1787 bus_space_write_2(iot, ioh, EP_W3_MAC_CONTROL, mctl)((iot)->write_2((ioh), (0x06), (mctl)));
1788 GO_WINDOW(1)((sc->sc_iot)->write_2((sc->sc_ioh), (0x0e), ((u_short
) (0x1<<11)|1))); /* back to operating window */
1789}