Bug Summary

File:dev/pci/drm/include/drm/display/drm_dp_helper.h
Warning:line 220, column 9
Array access (from variable 'dpcd') results in a null pointer dereference

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name intel_vrr.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/i915/display/intel_vrr.c

/usr/src/sys/dev/pci/drm/i915/display/intel_vrr.c

→
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2020 Intel Corporation
4 *
5 */
6
7#include "i915_drv.h"
8#include "intel_de.h"
9#include "intel_display_types.h"
10#include "intel_vrr.h"
11
12bool_Bool intel_vrr_is_capable(struct intel_connector *connector)
13{
14 const struct drm_display_info *info = &connector->base.display_info;
15 struct drm_i915_privateinteldrm_softc *i915 = to_i915(connector->base.dev);
16 struct intel_dp *intel_dp;
17
18 /*
19 * DP Sink is capable of VRR video timings if
20 * Ignore MSA bit is set in DPCD.
21 * EDID monitor range also should be atleast 10 for reasonable
22 * Adaptive Sync or Variable Refresh Rate end user experience.
23 */
24 switch (connector->base.connector_type) {
2
←
Control jumps to 'case 10:' at line 29
→
25 case DRM_MODE_CONNECTOR_eDP14:
26 if (!connector->panel.vbt.vrr)
27 return false0;
28 fallthroughdo {} while (0);
29 case DRM_MODE_CONNECTOR_DisplayPort10:
30 intel_dp = intel_attached_dp(connector);
31
32 if (!drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd))
3
←
Passing null pointer value via 1st parameter 'dpcd'
→
4
←
Calling 'drm_dp_sink_can_do_video_without_timing_msa'
→
33 return false0;
34
35 break;
36 default:
37 return false0;
38 }
39
40 return HAS_VRR(i915)(((&(i915)->__runtime)->display.ip.ver) >= 11) &&
41 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
42}
43
44void
45intel_vrr_check_modeset(struct intel_atomic_state *state)
46{
47 int i;
48 struct intel_crtc_state *old_crtc_state, *new_crtc_state;
49 struct intel_crtc *crtc;
50
51 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc
&& ((crtc) = ({ const __typeof( ((struct intel_crtc *
)0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct
intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc
, base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state
*)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state
); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const
__typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr =
((state)->base.crtcs[i].new_state); (struct intel_crtc_state
*)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state
, uapi) );}), 1); (i)++) if (!(crtc)) {} else
52 new_crtc_state, i)for ((i) = 0; (i) < (state)->base.dev->mode_config.num_crtc
&& ((crtc) = ({ const __typeof( ((struct intel_crtc *
)0)->base ) *__mptr = ((state)->base.crtcs[i].ptr); (struct
intel_crtc *)( (char *)__mptr - __builtin_offsetof(struct intel_crtc
, base) );}), (old_crtc_state) = ({ const __typeof( ((struct intel_crtc_state
*)0)->uapi ) *__mptr = ((state)->base.crtcs[i].old_state
); (struct intel_crtc_state *)( (char *)__mptr - __builtin_offsetof
(struct intel_crtc_state, uapi) );}), (new_crtc_state) = ({ const
__typeof( ((struct intel_crtc_state *)0)->uapi ) *__mptr =
((state)->base.crtcs[i].new_state); (struct intel_crtc_state
*)( (char *)__mptr - __builtin_offsetof(struct intel_crtc_state
, uapi) );}), 1); (i)++) if (!(crtc)) {} else {
53 if (new_crtc_state->uapi.vrr_enabled !=
54 old_crtc_state->uapi.vrr_enabled)
55 new_crtc_state->uapi.mode_changed = true1;
56 }
57}
58
59/*
60 * Without VRR registers get latched at:
61 * vblank_start
62 *
63 * With VRR the earliest registers can get latched is:
64 * intel_vrr_vmin_vblank_start(), which if we want to maintain
65 * the correct min vtotal is >=vblank_start+1
66 *
67 * The latest point registers can get latched is the vmax decision boundary:
68 * intel_vrr_vmax_vblank_start()
69 *
70 * Between those two points the vblank exit starts (and hence registers get
71 * latched) ASAP after a push is sent.
72 *
73 * framestart_delay is programmable 1-4.
74 */
75static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state)
76{
77 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
78 struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev);
79
80 /* The hw imposes the extra scanline before frame start */
81 if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 13)
82 return crtc_state->vrr.guardband + crtc_state->framestart_delay + 1;
83 else
84 return crtc_state->vrr.pipeline_full + crtc_state->framestart_delay + 1;
85}
86
87int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
88{
89 /* Min vblank actually determined by flipline that is always >=vmin+1 */
90 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state);
91}
92
93int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state)
94{
95 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state);
96}
97
98void
99intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
100 struct drm_connector_state *conn_state)
101{
102 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
103 struct drm_i915_privateinteldrm_softc *i915 = to_i915(crtc->base.dev);
104 struct intel_connector *connector =
105 to_intel_connector(conn_state->connector)({ const __typeof( ((struct intel_connector *)0)->base ) *
__mptr = (conn_state->connector); (struct intel_connector *
)( (char *)__mptr - __builtin_offsetof(struct intel_connector
, base) );});
106 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
107 const struct drm_display_info *info = &connector->base.display_info;
108 int vmin, vmax;
109
110 if (!intel_vrr_is_capable(connector))
1
Calling 'intel_vrr_is_capable'
→
111 return;
112
113 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE(1<<4))
114 return;
115
116 if (!crtc_state->uapi.vrr_enabled)
117 return;
118
119 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000,(((adjusted_mode->crtc_clock * 1000) + ((adjusted_mode->
crtc_htotal * info->monitor_range.max_vfreq) - 1)) / (adjusted_mode
->crtc_htotal * info->monitor_range.max_vfreq))
120 adjusted_mode->crtc_htotal * info->monitor_range.max_vfreq)(((adjusted_mode->crtc_clock * 1000) + ((adjusted_mode->
crtc_htotal * info->monitor_range.max_vfreq) - 1)) / (adjusted_mode
->crtc_htotal * info->monitor_range.max_vfreq));
121 vmax = adjusted_mode->crtc_clock * 1000 /
122 (adjusted_mode->crtc_htotal * info->monitor_range.min_vfreq);
123
124 vmin = max_t(int, vmin, adjusted_mode->crtc_vtotal)({ int __max_a = (vmin); int __max_b = (adjusted_mode->crtc_vtotal
); __max_a > __max_b ? __max_a : __max_b; });
125 vmax = max_t(int, vmax, adjusted_mode->crtc_vtotal)({ int __max_a = (vmax); int __max_b = (adjusted_mode->crtc_vtotal
); __max_a > __max_b ? __max_a : __max_b; });
126
127 if (vmin >= vmax)
128 return;
129
130 /*
131 * flipline determines the min vblank length the hardware will
132 * generate, and flipline>=vmin+1, hence we reduce vmin by one
133 * to make sure we can get the actual min vblank length.
134 */
135 crtc_state->vrr.vmin = vmin - 1;
136 crtc_state->vrr.vmax = vmax;
137 crtc_state->vrr.enable = true1;
138
139 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
140
141 /*
142 * For XE_LPD+, we use guardband and pipeline override
143 * is deprecated.
144 */
145 if (DISPLAY_VER(i915)((&(i915)->__runtime)->display.ip.ver) >= 13) {
146 /*
147 * FIXME: Subtract Window2 delay from below value.
148 *
149 * Window2 specifies time required to program DSB (Window2) in
150 * number of scan lines. Assuming 0 for no DSB.
151 */
152 crtc_state->vrr.guardband =
153 crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
154 } else {
155 /*
156 * FIXME: s/4/framestart_delay/ to get consistent
157 * earliest/latest points for register latching regardless
158 * of the framestart_delay used?
159 *
160 * FIXME: this really needs the extra scanline to provide consistent
161 * behaviour for all framestart_delay values. Otherwise with
162 * framestart_delay==4 we will end up extending the min vblank by
163 * one extra line.
164 */
165 crtc_state->vrr.pipeline_full =
166 min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1)(((255)<(crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay
- 4 - 1))?(255):(crtc_state->vrr.vmin - adjusted_mode->
crtc_vdisplay - 4 - 1));
167 }
168
169 crtc_state->mode_flags |= I915_MODE_FLAG_VRR(1<<6);
170}
171
172void intel_vrr_enable(struct intel_encoder *encoder,
173 const struct intel_crtc_state *crtc_state)
174{
175 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(encoder->base.dev);
176 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
177 u32 trans_vrr_ctl;
178
179 if (!crtc_state->vrr.enable)
180 return;
181
182 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 13)
183 trans_vrr_ctl = VRR_CTL_VRR_ENABLE((u32)((1UL << (31)) + 0)) |
184 VRR_CTL_IGN_MAX_SHIFT((u32)((1UL << (30)) + 0)) | VRR_CTL_FLIP_LINE_EN((u32)((1UL << (29)) + 0)) |
185 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband)((u32)((((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) &
((~0UL) << (0))) + 0))))((crtc_state->vrr.guardband
)) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (
15) - 1)) & ((~0UL) << (0))) + 0))) - 1)) & (((
u32)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) <<
(0))) + 0)))) + 0 + 0 + 0 + 0));
186 else
187 trans_vrr_ctl = VRR_CTL_VRR_ENABLE((u32)((1UL << (31)) + 0)) |
188 VRR_CTL_IGN_MAX_SHIFT((u32)((1UL << (30)) + 0)) | VRR_CTL_FLIP_LINE_EN((u32)((1UL << (29)) + 0)) |
189 VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full)((u32)((((typeof(((u32)((((~0UL) >> (64 - (10) - 1)) &
((~0UL) << (3))) + 0))))((crtc_state->vrr.pipeline_full
)) << (__builtin_ffsll(((u32)((((~0UL) >> (64 - (
10) - 1)) & ((~0UL) << (3))) + 0))) - 1)) & (((
u32)((((~0UL) >> (64 - (10) - 1)) & ((~0UL) <<
(3))) + 0)))) + 0 + 0 + 0 + 0)) |
190 VRR_CTL_PIPELINE_FULL_OVERRIDE((u32)((1UL << (0)) + 0));
191
192 intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60434)) }), crtc_state->vrr.vmin - 1);
193 intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60424)) }), crtc_state->vrr.vmax - 1);
194 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60420)) }), trans_vrr_ctl);
195 intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60438)) }), crtc_state->vrr.flipline - 1);
196 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60A70)) }), TRANS_PUSH_EN((u32)((1UL << (31)) + 0)));
197}
198
199void intel_vrr_send_push(const struct intel_crtc_state *crtc_state)
200{
201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
202 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
203 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
204
205 if (!crtc_state->vrr.enable)
206 return;
207
208 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60A70)) }),
209 TRANS_PUSH_EN((u32)((1UL << (31)) + 0)) | TRANS_PUSH_SEND((u32)((1UL << (30)) + 0)));
210}
211
212bool_Bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state)
213{
214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (crtc_state->uapi.crtc); (struct intel_crtc *)( (char *
)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
215 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
216 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
217
218 if (!crtc_state->vrr.enable)
219 return false0;
220
221 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60A70)) })) & TRANS_PUSH_SEND((u32)((1UL << (30)) + 0));
222}
223
224void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
225{
226 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc)({ const __typeof( ((struct intel_crtc *)0)->base ) *__mptr
= (old_crtc_state->uapi.crtc); (struct intel_crtc *)( (char
*)__mptr - __builtin_offsetof(struct intel_crtc, base) );});
227 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
228 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
229
230 if (!old_crtc_state->vrr.enable)
231 return;
232
233 intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60420)) }), 0);
234 intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60A70)) }), 0);
235}
236
237void intel_vrr_get_config(struct intel_crtc *crtc,
238 struct intel_crtc_state *crtc_state)
239{
240 struct drm_i915_privateinteldrm_softc *dev_priv = to_i915(crtc->base.dev);
241 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
242 u32 trans_vrr_ctl;
243
244 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60420)) }));
245 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE((u32)((1UL << (31)) + 0));
246 if (!crtc_state->vrr.enable)
247 return;
248
249 if (DISPLAY_VER(dev_priv)((&(dev_priv)->__runtime)->display.ip.ver) >= 13)
250 crtc_state->vrr.guardband =
251 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl)((u32)((typeof(((u32)((((~0UL) >> (64 - (15) - 1)) &
((~0UL) << (0))) + 0))))(((trans_vrr_ctl) & (((u32
)((((~0UL) >> (64 - (15) - 1)) & ((~0UL) << (
0))) + 0)))) >> (__builtin_ffsll(((u32)((((~0UL) >>
(64 - (15) - 1)) & ((~0UL) << (0))) + 0))) - 1))));
252 else
253 if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE((u32)((1UL << (0)) + 0)))
254 crtc_state->vrr.pipeline_full =
255 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl)((u32)((typeof(((u32)((((~0UL) >> (64 - (10) - 1)) &
((~0UL) << (3))) + 0))))(((trans_vrr_ctl) & (((u32
)((((~0UL) >> (64 - (10) - 1)) & ((~0UL) << (
3))) + 0)))) >> (__builtin_ffsll(((u32)((((~0UL) >>
(64 - (10) - 1)) & ((~0UL) << (3))) + 0))) - 1))));
256 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN((u32)((1UL << (29)) + 0)))
257 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60438)) })) + 1;
258 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60424)) })) + 1;
259 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)((const i915_reg_t){ .reg = ((&(dev_priv)->__info)->
display.trans_offsets[(cpu_transcoder)] - (&(dev_priv)->
__info)->display.trans_offsets[TRANSCODER_A] + ((&(dev_priv
)->__info)->display.mmio_offset) + (0x60434)) })) + 1;
260
261 crtc_state->mode_flags |= I915_MODE_FLAG_VRR(1<<6);
262}
←

/usr/src/sys/dev/pci/drm/include/drm/display/drm_dp_helper.h

1/*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#ifndef _DRM_DP_HELPER_H_
24#define _DRM_DP_HELPER_H_
25
26#include <linux/delay.h>
27#include <linux/i2c.h>
28
29#include <drm/display/drm_dp.h>
30#include <drm/drm_connector.h>
31
32struct drm_device;
33struct drm_dp_aux;
34struct drm_panel;
35
36bool_Bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE6],
37 int lane_count);
38bool_Bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE6],
39 int lane_count);
40u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE6],
41 int lane);
42u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE6],
43 int lane);
44u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE6],
45 int lane);
46
47int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
48 enum drm_dp_phy dp_phy, bool_Bool uhbr);
49int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
50 enum drm_dp_phy dp_phy, bool_Bool uhbr);
51
52void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf]);
54void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf]);
57void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE3]);
59
60int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61bool_Bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE6],
62 int lane_count);
63bool_Bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE6],
64 int lane_count);
65bool_Bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE6]);
66bool_Bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE6]);
67bool_Bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE6]);
68
69u8 drm_dp_link_rate_to_bw_code(int link_rate);
70int drm_dp_bw_code_to_link_rate(u8 link_bw);
71
72const char *drm_dp_phy_name(enum drm_dp_phy dp_phy);
73
74/**
75 * struct drm_dp_vsc_sdp - drm DP VSC SDP
76 *
77 * This structure represents a DP VSC SDP of drm
78 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
79 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
80 *
81 * @sdp_type: secondary-data packet type
82 * @revision: revision number
83 * @length: number of valid data bytes
84 * @pixelformat: pixel encoding format
85 * @colorimetry: colorimetry format
86 * @bpc: bit per color
87 * @dynamic_range: dynamic range information
88 * @content_type: CTA-861-G defines content types and expected processing by a sink device
89 */
90struct drm_dp_vsc_sdp {
91 unsigned char sdp_type;
92 unsigned char revision;
93 unsigned char length;
94 enum dp_pixelformat pixelformat;
95 enum dp_colorimetry colorimetry;
96 int bpc;
97 enum dp_dynamic_range dynamic_range;
98 enum dp_content_type content_type;
99};
100
101void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
102 const struct drm_dp_vsc_sdp *vsc);
103
104int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE2]);
105
106static inline int
107drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
108{
109 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE0x001]);
110}
111
112static inline u8
113drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
114{
115 return dpcd[DP_MAX_LANE_COUNT0x002] & DP_MAX_LANE_COUNT_MASK0x1f;
116}
117
118static inline bool_Bool
119drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
120{
121 return dpcd[DP_DPCD_REV0x000] >= 0x11 &&
122 (dpcd[DP_MAX_LANE_COUNT0x002] & DP_ENHANCED_FRAME_CAP(1 << 7));
123}
124
125static inline bool_Bool
126drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
127{
128 return dpcd[DP_DPCD_REV0x000] >= 0x11 &&
129 (dpcd[DP_MAX_DOWNSPREAD0x003] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING(1 << 6));
130}
131
132static inline bool_Bool
133drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
134{
135 return dpcd[DP_DPCD_REV0x000] >= 0x12 &&
136 dpcd[DP_MAX_LANE_COUNT0x002] & DP_TPS3_SUPPORTED(1 << 6);
137}
138
139static inline bool_Bool
140drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
141{
142 return dpcd[DP_DPCD_REV0x000] >= 0x11 ||
143 dpcd[DP_MAX_DOWNSPREAD0x003] & DP_MAX_DOWNSPREAD_0_5(1 << 0);
144}
145
146static inline bool_Bool
147drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
148{
149 return dpcd[DP_DPCD_REV0x000] >= 0x14 &&
150 dpcd[DP_MAX_DOWNSPREAD0x003] & DP_TPS4_SUPPORTED(1 << 7);
151}
152
153static inline u8
154drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
155{
156 return (dpcd[DP_DPCD_REV0x000] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_40xf :
157 DP_TRAINING_PATTERN_MASK0x3;
158}
159
160static inline bool_Bool
161drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
162{
163 return dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DWN_STRM_PORT_PRESENT(1 << 0);
164}
165
166/* DP/eDP DSC support */
167u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10],
168 bool_Bool is_edp);
169u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10]);
170int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE0x10],
171 u8 dsc_bpc[3]);
172
173static inline bool_Bool
174drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10])
175{
176 return dsc_dpcd[DP_DSC_SUPPORT0x060 - DP_DSC_SUPPORT0x060] &
177 DP_DSC_DECOMPRESSION_IS_SUPPORTED(1 << 0);
178}
179
180static inline u16
181drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10])
182{
183 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW0x067 - DP_DSC_SUPPORT0x060] |
184 ((dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI0x068 - DP_DSC_SUPPORT0x060] &
185 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK(0x3 << 0)) << 8);
186}
187
188static inline u32
189drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10])
190{
191 /* Max Slicewidth = Number of Pixels * 320 */
192 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH0x06C - DP_DSC_SUPPORT0x060] *
193 DP_DSC_SLICE_WIDTH_MULTIPLIER320;
194}
195
196/* Forward Error Correction Support on DP 1.4 */
197static inline bool_Bool
198drm_dp_sink_supports_fec(const u8 fec_capable)
199{
200 return fec_capable & DP_FEC_CAPABLE(1 << 0);
201}
202
203static inline bool_Bool
204drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
205{
206 return dpcd[DP_MAIN_LINK_CHANNEL_CODING0x006] & DP_CAP_ANSI_8B10B(1 << 0);
207}
208
209static inline bool_Bool
210drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
211{
212 return dpcd[DP_EDP_CONFIGURATION_CAP0x00d] &
213 DP_ALTERNATE_SCRAMBLER_RESET_CAP(1 << 0);
214}
215
216/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
217static inline bool_Bool
218drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
219{
220 return dpcd[DP_DOWN_STREAM_PORT_COUNT0x007] &
5
←
Array access (from variable 'dpcd') results in a null pointer dereference
221 DP_MSA_TIMING_PAR_IGNORED(1 << 6);
222}
223
224/**
225 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
226 * @edp_dpcd: The DPCD to check
227 *
228 * Note that currently this function will return %false for panels which support various DPCD
229 * backlight features but which require the brightness be set through PWM, and don't support setting
230 * the brightness level via the DPCD.
231 *
232 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
233 * otherwise
234 */
235static inline bool_Bool
236drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE3])
237{
238 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP(1 << 0));
239}
240
241/*
242 * DisplayPort AUX channel
243 */
244
245/**
246 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
247 * @address: address of the (first) register to access
248 * @request: contains the type of transaction (see DP_AUX_* macros)
249 * @reply: upon completion, contains the reply type of the transaction
250 * @buffer: pointer to a transmission or reception buffer
251 * @size: size of @buffer
252 */
253struct drm_dp_aux_msg {
254 unsigned int address;
255 u8 request;
256 u8 reply;
257 void *buffer;
258 size_t size;
259};
260
261struct cec_adapter;
262struct edid;
263struct drm_connector;
264
265/**
266 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
267 * @lock: mutex protecting this struct
268 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
269 * @connector: the connector this CEC adapter is associated with
270 * @unregister_work: unregister the CEC adapter
271 */
272struct drm_dp_aux_cec {
273 struct rwlock lock;
274 struct cec_adapter *adap;
275 struct drm_connector *connector;
276 struct delayed_work unregister_work;
277};
278
279/**
280 * struct drm_dp_aux - DisplayPort AUX channel
281 *
282 * An AUX channel can also be used to transport I2C messages to a sink. A
283 * typical application of that is to access an EDID that's present in the sink
284 * device. The @transfer() function can also be used to execute such
285 * transactions. The drm_dp_aux_register() function registers an I2C adapter
286 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
287 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
288 * transfers by default; if a partial response is received, the adapter will
289 * drop down to the size given by the partial response for this transaction
290 * only.
291 */
292struct drm_dp_aux {
293 /**
294 * @name: user-visible name of this AUX channel and the
295 * I2C-over-AUX adapter.
296 *
297 * It's also used to specify the name of the I2C adapter. If set
298 * to %NULL, dev_name() of @dev will be used.
299 */
300 const char *name;
301
302 /**
303 * @ddc: I2C adapter that can be used for I2C-over-AUX
304 * communication
305 */
306 struct i2c_adapter ddc;
307
308 /**
309 * @dev: pointer to struct device that is the parent for this
310 * AUX channel.
311 */
312 struct device *dev;
313
314 /**
315 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
316 * Beware, this may be %NULL before drm_dp_aux_register() has been
317 * called.
318 *
319 * It should be set to the &drm_device that will be using this AUX
320 * channel as early as possible. For many graphics drivers this should
321 * happen before drm_dp_aux_init(), however it's perfectly fine to set
322 * this field later so long as it's assigned before calling
323 * drm_dp_aux_register().
324 */
325 struct drm_device *drm_dev;
326
327 /**
328 * @crtc: backpointer to the crtc that is currently using this
329 * AUX channel
330 */
331 struct drm_crtc *crtc;
332
333 /**
334 * @hw_mutex: internal mutex used for locking transfers.
335 *
336 * Note that if the underlying hardware is shared among multiple
337 * channels, the driver needs to do additional locking to
338 * prevent concurrent access.
339 */
340 struct rwlock hw_mutex;
341
342 /**
343 * @crc_work: worker that captures CRCs for each frame
344 */
345 struct work_struct crc_work;
346
347 /**
348 * @crc_count: counter of captured frame CRCs
349 */
350 u8 crc_count;
351
352 /**
353 * @transfer: transfers a message representing a single AUX
354 * transaction.
355 *
356 * This is a hardware-specific implementation of how
357 * transactions are executed that the drivers must provide.
358 *
359 * A pointer to a &drm_dp_aux_msg structure describing the
360 * transaction is passed into this function. Upon success, the
361 * implementation should return the number of payload bytes that
362 * were transferred, or a negative error-code on failure.
363 *
364 * Helpers will propagate these errors, with the exception of
365 * the %-EBUSY error, which causes a transaction to be retried.
366 * On a short, helpers will return %-EPROTO to make it simpler
367 * to check for failure.
368 *
369 * The @transfer() function must only modify the reply field of
370 * the &drm_dp_aux_msg structure. The retry logic and i2c
371 * helpers assume this is the case.
372 *
373 * Also note that this callback can be called no matter the
374 * state @dev is in and also no matter what state the panel is
375 * in. It's expected:
376 *
377 * - If the @dev providing the AUX bus is currently unpowered then
378 * it will power itself up for the transfer.
379 *
380 * - If we're on eDP (using a drm_panel) and the panel is not in a
381 * state where it can respond (it's not powered or it's in a
382 * low power state) then this function may return an error, but
383 * not crash. It's up to the caller of this code to make sure that
384 * the panel is powered on if getting an error back is not OK. If a
385 * drm_panel driver is initiating a DP AUX transfer it may power
386 * itself up however it wants. All other code should ensure that
387 * the pre_enable() bridge chain (which eventually calls the
388 * drm_panel prepare function) has powered the panel.
389 */
390 ssize_t (*transfer)(struct drm_dp_aux *aux,
391 struct drm_dp_aux_msg *msg);
392
393 /**
394 * @wait_hpd_asserted: wait for HPD to be asserted
395 *
396 * This is mainly useful for eDP panels drivers to wait for an eDP
397 * panel to finish powering on. This is an optional function.
398 *
399 * This function will efficiently wait for the HPD signal to be
400 * asserted. The `wait_us` parameter that is passed in says that we
401 * know that the HPD signal is expected to be asserted within `wait_us`
402 * microseconds. This function could wait for longer than `wait_us` if
403 * the logic in the DP controller has a long debouncing time. The
404 * important thing is that if this function returns success that the
405 * DP controller is ready to send AUX transactions.
406 *
407 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
408 * expired and HPD wasn't asserted. This function should not print
409 * timeout errors to the log.
410 *
411 * The semantics of this function are designed to match the
412 * readx_poll_timeout() function. That means a `wait_us` of 0 means
413 * to wait forever. Like readx_poll_timeout(), this function may sleep.
414 *
415 * NOTE: this function specifically reports the state of the HPD pin
416 * that's associated with the DP AUX channel. This is different from
417 * the HPD concept in much of the rest of DRM which is more about
418 * physical presence of a display. For eDP, for instance, a display is
419 * assumed always present even if the HPD pin is deasserted.
420 */
421 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
422
423 /**
424 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
425 */
426 unsigned i2c_nack_count;
427 /**
428 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
429 */
430 unsigned i2c_defer_count;
431 /**
432 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
433 */
434 struct drm_dp_aux_cec cec;
435 /**
436 * @is_remote: Is this AUX CH actually using sideband messaging.
437 */
438 bool_Bool is_remote;
439};
440
441int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
442ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
443 void *buffer, size_t size);
444ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
445 void *buffer, size_t size);
446
447/**
448 * drm_dp_dpcd_readb() - read a single byte from the DPCD
449 * @aux: DisplayPort AUX channel
450 * @offset: address of the register to read
451 * @valuep: location where the value of the register will be stored
452 *
453 * Returns the number of bytes transferred (1) on success, or a negative
454 * error code on failure.
455 */
456static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
457 unsigned int offset, u8 *valuep)
458{
459 return drm_dp_dpcd_read(aux, offset, valuep, 1);
460}
461
462/**
463 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
464 * @aux: DisplayPort AUX channel
465 * @offset: address of the register to write
466 * @value: value to write to the register
467 *
468 * Returns the number of bytes transferred (1) on success, or a negative
469 * error code on failure.
470 */
471static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
472 unsigned int offset, u8 value)
473{
474 return drm_dp_dpcd_write(aux, offset, &value, 1);
475}
476
477int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
478 u8 dpcd[DP_RECEIVER_CAP_SIZE0xf]);
479
480int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
481 u8 status[DP_LINK_STATUS_SIZE6]);
482
483int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
484 enum drm_dp_phy dp_phy,
485 u8 link_status[DP_LINK_STATUS_SIZE6]);
486
487bool_Bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
488 u8 real_edid_checksum);
489
490int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
491 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
492 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS0x10]);
493bool_Bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
494 const u8 port_cap[4], u8 type);
495bool_Bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
496 const u8 port_cap[4],
497 const struct edid *edid);
498int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
499 const u8 port_cap[4]);
500int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
501 const u8 port_cap[4],
502 const struct edid *edid);
503int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
504 const u8 port_cap[4],
505 const struct edid *edid);
506int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
507 const u8 port_cap[4],
508 const struct edid *edid);
509bool_Bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
510 const u8 port_cap[4]);
511bool_Bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
512 const u8 port_cap[4]);
513struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
514 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
515 const u8 port_cap[4]);
516int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
517void drm_dp_downstream_debug(struct seq_file *m,
518 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
519 const u8 port_cap[4],
520 const struct edid *edid,
521 struct drm_dp_aux *aux);
522enum drm_mode_subconnector
523drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
524 const u8 port_cap[4]);
525void drm_dp_set_subconnector_property(struct drm_connector *connector,
526 enum drm_connector_status status,
527 const u8 *dpcd,
528 const u8 port_cap[4]);
529
530struct drm_dp_desc;
531bool_Bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
532 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
533 const struct drm_dp_desc *desc);
534int drm_dp_read_sink_count(struct drm_dp_aux *aux);
535
536int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
537 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
538 u8 caps[DP_LTTPR_COMMON_CAP_SIZE8]);
539int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
540 const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
541 enum drm_dp_phy dp_phy,
542 u8 caps[DP_LTTPR_PHY_CAP_SIZE3]);
543int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE8]);
544int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE8]);
545int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE8]);
546bool_Bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE3]);
547bool_Bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE3]);
548
549void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
550void drm_dp_aux_init(struct drm_dp_aux *aux);
551int drm_dp_aux_register(struct drm_dp_aux *aux);
552void drm_dp_aux_unregister(struct drm_dp_aux *aux);
553
554int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
555int drm_dp_stop_crc(struct drm_dp_aux *aux);
556
557struct drm_dp_dpcd_ident {
558 u8 oui[3];
559 u8 device_id[6];
560 u8 hw_rev;
561 u8 sw_major_rev;
562 u8 sw_minor_rev;
563} __packed__attribute__((__packed__));
564
565/**
566 * struct drm_dp_desc - DP branch/sink device descriptor
567 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
568 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
569 */
570struct drm_dp_desc {
571 struct drm_dp_dpcd_ident ident;
572 u32 quirks;
573};
574
575int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
576 bool_Bool is_branch);
577
578/**
579 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
580 *
581 * Display Port sink and branch devices in the wild have a variety of bugs, try
582 * to collect them here. The quirks are shared, but it's up to the drivers to
583 * implement workarounds for them.
584 */
585enum drm_dp_quirk {
586 /**
587 * @DP_DPCD_QUIRK_CONSTANT_N:
588 *
589 * The device requires main link attributes Mvid and Nvid to be limited
590 * to 16 bits. So will give a constant value (0x8000) for compatability.
591 */
592 DP_DPCD_QUIRK_CONSTANT_N,
593 /**
594 * @DP_DPCD_QUIRK_NO_PSR:
595 *
596 * The device does not support PSR even if reports that it supports or
597 * driver still need to implement proper handling for such device.
598 */
599 DP_DPCD_QUIRK_NO_PSR,
600 /**
601 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
602 *
603 * The device does not set SINK_COUNT to a non-zero value.
604 * The driver should ignore SINK_COUNT during detection. Note that
605 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
606 */
607 DP_DPCD_QUIRK_NO_SINK_COUNT,
608 /**
609 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
610 *
611 * The device supports MST DSC despite not supporting Virtual DPCD.
612 * The DSC caps can be read from the physical aux instead.
613 */
614 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
615 /**
616 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
617 *
618 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
619 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
620 */
621 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
622};
623
624/**
625 * drm_dp_has_quirk() - does the DP device have a specific quirk
626 * @desc: Device descriptor filled by drm_dp_read_desc()
627 * @quirk: Quirk to query for
628 *
629 * Return true if DP device identified by @desc has @quirk.
630 */
631static inline bool_Bool
632drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
633{
634 return desc->quirks & BIT(quirk)(1UL << (quirk));
635}
636
637/**
638 * struct drm_edp_backlight_info - Probed eDP backlight info struct
639 * @pwmgen_bit_count: The pwmgen bit count
640 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
641 * @max: The maximum backlight level that may be set
642 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
643 * @aux_enable: Does the panel support the AUX enable cap?
644 * @aux_set: Does the panel support setting the brightness through AUX?
645 *
646 * This structure contains various data about an eDP backlight, which can be populated by using
647 * drm_edp_backlight_init().
648 */
649struct drm_edp_backlight_info {
650 u8 pwmgen_bit_count;
651 u8 pwm_freq_pre_divider;
652 u16 max;
653
654 bool_Bool lsb_reg_used : 1;
655 bool_Bool aux_enable : 1;
656 bool_Bool aux_set : 1;
657};
658
659int
660drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
661 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE3],
662 u16 *current_level, u8 *current_mode);
663int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
664 u16 level);
665int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
666 u16 level);
667int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
668
669#if IS_ENABLED(CONFIG_DRM_KMS_HELPER)1 && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE)1 || \
670 (IS_MODULE(CONFIG_DRM_KMS_HELPER)0 && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)0))
671
672int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
673
674#else
675
676static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
677 struct drm_dp_aux *aux)
678{
679 return 0;
680}
681
682#endif
683
684#ifdef CONFIG_DRM_DP_CEC
685void drm_dp_cec_irq(struct drm_dp_aux *aux);
686void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
687 struct drm_connector *connector);
688void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
689void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
690void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
691#else
692static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
693{
694}
695
696static inline void
697drm_dp_cec_register_connector(struct drm_dp_aux *aux,
698 struct drm_connector *connector)
699{
700}
701
702static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
703{
704}
705
706static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
707 const struct edid *edid)
708{
709}
710
711static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
712{
713}
714
715#endif
716
717/**
718 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
719 * @link_rate: Requested Link rate from DPCD 0x219
720 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
721 * @phy_pattern: DP Phy test pattern from DPCD 0x248
722 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
723 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
724 * @enhanced_frame_cap: flag for enhanced frame capability.
725 */
726struct drm_dp_phy_test_params {
727 int link_rate;
728 u8 num_lanes;
729 u8 phy_pattern;
730 u8 hbr2_reset[2];
731 u8 custom80[10];
732 bool_Bool enhanced_frame_cap;
733};
734
735int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
736 struct drm_dp_phy_test_params *data);
737int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
738 struct drm_dp_phy_test_params *data, u8 dp_rev);
739int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
740 const u8 port_cap[4]);
741int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool_Bool enable_frl_ready_hpd);
742bool_Bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
743int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
744 u8 frl_mode);
745int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
746 u8 frl_type);
747int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
748int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
749
750bool_Bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
751int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
752void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
753 struct drm_connector *connector);
754bool_Bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD]);
755int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD]);
756int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD]);
757int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD]);
758int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
759int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
760int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
761bool_Bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
762 const u8 port_cap[4], u8 color_spc);
763int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
764
765#endif /* _DRM_DP_HELPER_H_ */