File: | dev/pci/ixgb_hw.c |
Warning: | line 175, column 2 Value stored to 'icr_reg' is never read |
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1 | /******************************************************************************* |
2 | |
3 | Copyright (c) 2001-2005, Intel Corporation |
4 | All rights reserved. |
5 | |
6 | Redistribution and use in source and binary forms, with or without |
7 | modification, are permitted provided that the following conditions are met: |
8 | |
9 | 1. Redistributions of source code must retain the above copyright notice, |
10 | this list of conditions and the following disclaimer. |
11 | |
12 | 2. Redistributions in binary form must reproduce the above copyright |
13 | notice, this list of conditions and the following disclaimer in the |
14 | documentation and/or other materials provided with the distribution. |
15 | |
16 | 3. Neither the name of the Intel Corporation nor the names of its |
17 | contributors may be used to endorse or promote products derived from |
18 | this software without specific prior written permission. |
19 | |
20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
30 | POSSIBILITY OF SUCH DAMAGE. |
31 | |
32 | *******************************************************************************/ |
33 | |
34 | /* $OpenBSD: ixgb_hw.c,v 1.9 2022/01/09 05:42:56 jsg Exp $ */ |
35 | |
36 | /* ixgb_hw.c |
37 | * Shared functions for accessing and configuring the adapter |
38 | */ |
39 | |
40 | #include <sys/param.h> |
41 | #include <sys/systm.h> |
42 | #include <sys/sockio.h> |
43 | #include <sys/mbuf.h> |
44 | #include <sys/malloc.h> |
45 | #include <sys/kernel.h> |
46 | #include <sys/device.h> |
47 | #include <sys/socket.h> |
48 | |
49 | #include <net/if.h> |
50 | #include <net/if_media.h> |
51 | |
52 | #include <netinet/in.h> |
53 | #include <netinet/if_ether.h> |
54 | |
55 | #include <uvm/uvm_extern.h> |
56 | |
57 | #include <dev/pci/pcireg.h> |
58 | #include <dev/pci/pcivar.h> |
59 | |
60 | #include <dev/pci/ixgb_hw.h> |
61 | #include <dev/pci/ixgb_ids.h> |
62 | |
63 | /* Local function prototypes */ |
64 | |
65 | static uint32_t ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr); |
66 | |
67 | static void ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value); |
68 | |
69 | static void ixgb_get_bus_info(struct ixgb_hw *hw); |
70 | |
71 | static boolean_t ixgb_link_reset(struct ixgb_hw *hw); |
72 | |
73 | static void ixgb_optics_reset(struct ixgb_hw *hw); |
74 | |
75 | static void ixgb_optics_reset_bcm(struct ixgb_hw *hw); |
76 | |
77 | static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw); |
78 | |
79 | uint32_t ixgb_mac_reset(struct ixgb_hw *hw); |
80 | |
81 | uint32_t |
82 | ixgb_mac_reset(struct ixgb_hw *hw) |
83 | { |
84 | uint32_t ctrl_reg; |
85 | |
86 | ctrl_reg = IXGB_CTRL0_RST0x04000000 | |
87 | IXGB_CTRL0_SDP3_DIR0x02000000 | /* All pins are Output=1 */ |
88 | IXGB_CTRL0_SDP2_DIR0x01000000 | |
89 | IXGB_CTRL0_SDP1_DIR0x00800000 | |
90 | IXGB_CTRL0_SDP0_DIR0x00400000 | |
91 | IXGB_CTRL0_SDP30x00200000 | /* Initial value 1101 */ |
92 | IXGB_CTRL0_SDP20x00100000 | |
93 | IXGB_CTRL0_SDP00x00040000; |
94 | |
95 | #ifdef HP_ZX1 |
96 | /* Workaround for 82597EX reset errata */ |
97 | IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); |
98 | #else |
99 | IXGB_WRITE_REG(hw, CTRL0, ctrl_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (ctrl_reg))); |
100 | #endif |
101 | |
102 | /* Delay a few ms just to allow the reset to complete */ |
103 | msec_delay(IXGB_DELAY_AFTER_RESET)(*delay_func)(1000*(1)); |
104 | ctrl_reg = IXGB_READ_REG(hw, CTRL0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))); |
105 | #ifdef DBG0 |
106 | /* Make sure the self-clearing global reset bit did self clear */ |
107 | ASSERT(!(ctrl_reg & IXGB_CTRL0_RST))if(!(!(ctrl_reg & 0x04000000))) panic("IXGB: x"); |
108 | #endif |
109 | |
110 | if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID0x108E) { |
111 | ctrl_reg = /* Enable interrupt from XFP and SerDes */ |
112 | IXGB_CTRL1_GPI0_EN0x00000001 | |
113 | IXGB_CTRL1_SDP6_DIR0x00000400 | |
114 | IXGB_CTRL1_SDP7_DIR0x00000800 | |
115 | IXGB_CTRL1_SDP60x00000040 | |
116 | IXGB_CTRL1_SDP70x00000080; |
117 | IXGB_WRITE_REG(hw, CTRL1, ctrl_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00008), (ctrl_reg))); |
118 | ixgb_optics_reset_bcm(hw); |
119 | } |
120 | |
121 | if (hw->phy_type == ixgb_phy_type_txn17401) |
122 | ixgb_optics_reset(hw); |
123 | |
124 | return ctrl_reg; |
125 | } |
126 | |
127 | /****************************************************************************** |
128 | * Reset the transmit and receive units; mask and clear all interrupts. |
129 | * |
130 | * hw - Struct containing variables accessed by shared code |
131 | *****************************************************************************/ |
132 | boolean_t |
133 | ixgb_adapter_stop(struct ixgb_hw *hw) |
134 | { |
135 | uint32_t ctrl_reg; |
136 | uint32_t icr_reg; |
137 | |
138 | DEBUGFUNC("ixgb_adapter_stop");; |
139 | |
140 | /* If we are stopped or resetting exit gracefully and wait to be |
141 | * started again before accessing the hardware. */ |
142 | if(hw->adapter_stopped) { |
143 | DEBUGOUT("Exiting because the adapter is already stopped!!!\n"); |
144 | return FALSE0; |
145 | } |
146 | |
147 | /* Set the Adapter Stopped flag so other driver functions stop touching |
148 | * the Hardware. */ |
149 | hw->adapter_stopped = TRUE1; |
150 | |
151 | /* Clear interrupt mask to stop board from generating interrupts */ |
152 | DEBUGOUT("Masking off all interrupts\n"); |
153 | IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00098), (0xFFFFFFFF))); |
154 | |
155 | /* Disable the Transmit and Receive units. Then delay to allow any |
156 | * pending transactions to complete before we hit the MAC with the |
157 | * global reset. */ |
158 | IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00100), (((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag )->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00100))) & ~0x00000002))); |
159 | IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00600), (((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag )->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00600))) & ~0x00000002))); |
160 | msec_delay(IXGB_DELAY_BEFORE_RESET)(*delay_func)(1000*(10)); |
161 | |
162 | /* Issue a global reset to the MAC. This will reset the chip's |
163 | * transmit, receive, DMA, and link units. It will not effect the |
164 | * current PCI configuration. The global reset bit is self- clearing, |
165 | * and should clear within a microsecond. */ |
166 | DEBUGOUT("Issuing a global reset to MAC\n"); |
167 | |
168 | ctrl_reg = ixgb_mac_reset(hw); |
169 | |
170 | /* Clear interrupt mask to stop board from generating interrupts */ |
171 | DEBUGOUT("Masking off all interrupts\n"); |
172 | IXGB_WRITE_REG(hw, IMC, 0xffffffff)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00098), (0xffffffff))); |
173 | |
174 | /* Clear any pending interrupt events. */ |
175 | icr_reg = IXGB_READ_REG(hw, ICR)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00080))); |
Value stored to 'icr_reg' is never read | |
176 | |
177 | return (ctrl_reg & IXGB_CTRL0_RST0x04000000); |
178 | } |
179 | |
180 | /****************************************************************************** |
181 | * Identifies the vendor of the optics module on the adapter. The SR adapters |
182 | * support two different types of XPAK optics, so it is necessary to determine |
183 | * which optics are present before applying any optics-specific workarounds. |
184 | * |
185 | * hw - Struct containing variables accessed by shared code. |
186 | * |
187 | * Returns: the vendor of the XPAK optics module. |
188 | *****************************************************************************/ |
189 | static ixgb_xpak_vendor |
190 | ixgb_identify_xpak_vendor(struct ixgb_hw *hw) |
191 | { |
192 | uint32_t i; |
193 | uint16_t vendor_name[5]; |
194 | ixgb_xpak_vendor xpak_vendor; |
195 | |
196 | DEBUGFUNC("ixgb_identify_xpak_vendor");; |
197 | |
198 | /* Read the first few bytes of the vendor string from the XPAK NVR |
199 | * registers. These are standard XENPAK/XPAK registers, so all XPAK |
200 | * devices should implement them. */ |
201 | for(i = 0; i < 5; i++) { |
202 | vendor_name[i] = |
203 | ixgb_read_phy_reg(hw, MDIO_PMA_PMD_XPAK_VENDOR_NAME0x803A + i, |
204 | IXGB_PHY_ADDRESS0x0, MDIO_PMA_PMD_DID0x01); |
205 | } |
206 | |
207 | /* Determine the actual vendor */ |
208 | if (vendor_name[0] == 'I' && |
209 | vendor_name[1] == 'N' && |
210 | vendor_name[2] == 'T' && |
211 | vendor_name[3] == 'E' && |
212 | vendor_name[4] == 'L') { |
213 | xpak_vendor = ixgb_xpak_vendor_intel; |
214 | } |
215 | else { |
216 | xpak_vendor = ixgb_xpak_vendor_infineon; |
217 | } |
218 | return (xpak_vendor); |
219 | } |
220 | |
221 | /****************************************************************************** |
222 | * Determine the physical layer module on the adapter. |
223 | * |
224 | * hw - Struct containing variables accessed by shared code. The device_id |
225 | * field must be (correctly) populated before calling this routine. |
226 | * |
227 | * Returns: the phy type of the adapter. |
228 | *****************************************************************************/ |
229 | static ixgb_phy_type |
230 | ixgb_identify_phy(struct ixgb_hw *hw) |
231 | { |
232 | ixgb_phy_type phy_type; |
233 | ixgb_xpak_vendor xpak_vendor; |
234 | |
235 | DEBUGFUNC("ixgb_identify_phy");; |
236 | |
237 | /* Infer the transceiver/phy type from the device id */ |
238 | switch(hw->device_id) { |
239 | case IXGB_DEVICE_ID_82597EX0x1048: |
240 | DEBUGOUT("Identified TXN17401 optics\n"); |
241 | phy_type = ixgb_phy_type_txn17401; |
242 | break; |
243 | |
244 | case IXGB_DEVICE_ID_82597EX_SR0x1A48: |
245 | /* The SR adapters carry two different types of XPAK optics |
246 | * modules; read the vendor identifier to determine the exact |
247 | * type of optics. */ |
248 | xpak_vendor = ixgb_identify_xpak_vendor(hw); |
249 | if(xpak_vendor == ixgb_xpak_vendor_intel) { |
250 | DEBUGOUT("Identified TXN17201 optics\n"); |
251 | phy_type = ixgb_phy_type_txn17201; |
252 | } else { |
253 | DEBUGOUT("Identified G6005 optics\n"); |
254 | phy_type = ixgb_phy_type_g6005; |
255 | } |
256 | break; |
257 | |
258 | case IXGB_DEVICE_ID_82597EX_LR0x1B48: |
259 | DEBUGOUT("Identified G6104 optics\n"); |
260 | phy_type = ixgb_phy_type_g6104; |
261 | break; |
262 | |
263 | case IXGB_DEVICE_ID_82597EX_CX40x109E: |
264 | DEBUGOUT("Identified CX4\n"); |
265 | xpak_vendor = ixgb_identify_xpak_vendor(hw); |
266 | if(xpak_vendor == ixgb_xpak_vendor_intel) { |
267 | DEBUGOUT("Identified TXN17201 optics\n"); |
268 | phy_type = ixgb_phy_type_txn17201; |
269 | } else { |
270 | DEBUGOUT("Identified G6005 optics\n"); |
271 | phy_type = ixgb_phy_type_g6005; |
272 | } |
273 | break; |
274 | |
275 | default: |
276 | DEBUGOUT("Unknown physical layer module\n"); |
277 | phy_type = ixgb_phy_type_unknown; |
278 | break; |
279 | } |
280 | |
281 | /* update phy type for sun specific board */ |
282 | if (hw->subsystem_vendor_id == SUN_SUBVENDOR_ID0x108E) |
283 | phy_type = ixgb_phy_type_bcm; |
284 | |
285 | return (phy_type); |
286 | } |
287 | |
288 | /****************************************************************************** |
289 | * Performs basic configuration of the adapter. |
290 | * |
291 | * hw - Struct containing variables accessed by shared code |
292 | * |
293 | * Resets the controller. |
294 | * Reads and validates the EEPROM. |
295 | * Initializes the receive address registers. |
296 | * Initializes the multicast table. |
297 | * Clears all on-chip counters. |
298 | * Calls routine to setup flow control settings. |
299 | * Leaves the transmit and receive units disabled and uninitialized. |
300 | * |
301 | * Returns: |
302 | * TRUE if successful, |
303 | * FALSE if unrecoverable problems were encountered. |
304 | *****************************************************************************/ |
305 | boolean_t |
306 | ixgb_init_hw(struct ixgb_hw *hw) |
307 | { |
308 | uint32_t i; |
309 | uint32_t ctrl_reg; |
310 | boolean_t status; |
311 | |
312 | DEBUGFUNC("ixgb_init_hw");; |
313 | |
314 | /* Issue a global reset to the MAC. This will reset the chip's |
315 | * transmit, receive, DMA, and link units. It will not effect the |
316 | * current PCI configuration. The global reset bit is self- clearing, |
317 | * and should clear within a microsecond. */ |
318 | DEBUGOUT("Issuing a global reset to MAC\n"); |
319 | |
320 | ctrl_reg = ixgb_mac_reset(hw); |
321 | |
322 | DEBUGOUT("Issuing an EE reset to MAC\n"); |
323 | #ifdef HP_ZX1 |
324 | /* Workaround for 82597EX reset errata */ |
325 | IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST0x00002000); |
326 | #else |
327 | IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00008), (0x00002000))); |
328 | #endif |
329 | |
330 | /* Delay a few ms just to allow the reset to complete */ |
331 | msec_delay(IXGB_DELAY_AFTER_EE_RESET)(*delay_func)(1000*(10)); |
332 | |
333 | if(ixgb_get_eeprom_data(hw) == FALSE0) { |
334 | return (FALSE0); |
335 | } |
336 | |
337 | /* Use the device id to determine the type of phy/transceiver. */ |
338 | hw->device_id = ixgb_get_ee_device_id(hw); |
339 | hw->phy_type = ixgb_identify_phy(hw); |
340 | |
341 | /* Setup the receive addresses. Receive Address Registers (RARs 0 - |
342 | * 15). */ |
343 | ixgb_init_rx_addrs(hw); |
344 | |
345 | /* |
346 | * Check that a valid MAC address has been set. |
347 | * If it is not valid, we fail hardware init. |
348 | */ |
349 | if(!mac_addr_valid(hw->curr_mac_addr)) { |
350 | DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n"); |
351 | return (FALSE0); |
352 | } |
353 | |
354 | /* tell the routines in this file they can access hardware again */ |
355 | hw->adapter_stopped = FALSE0; |
356 | |
357 | /* Fill in the bus_info structure */ |
358 | ixgb_get_bus_info(hw); |
359 | |
360 | /* Zero out the Multicast HASH table */ |
361 | DEBUGOUT("Zeroing the MTA\n"); |
362 | for(i = 0; i < IXGB_MC_TBL_SIZE128; i++) |
363 | IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00200 + ((i) << 2))), (0))); |
364 | |
365 | /* Zero out the VLAN Filter Table Array */ |
366 | ixgb_clear_vfta(hw); |
367 | |
368 | /* Zero all of the hardware counters */ |
369 | ixgb_clear_hw_cntrs(hw); |
370 | |
371 | /* Call a subroutine to setup flow control. */ |
372 | status = ixgb_setup_fc(hw); |
373 | |
374 | /* 82597EX errata: Call check-for-link in case lane deskew is locked */ |
375 | ixgb_check_for_link(hw); |
376 | |
377 | return (status); |
378 | } |
379 | |
380 | /****************************************************************************** |
381 | * Initializes receive address filters. |
382 | * |
383 | * hw - Struct containing variables accessed by shared code |
384 | * |
385 | * Places the MAC address in receive address register 0 and clears the rest |
386 | * of the receive address registers. Clears the multicast table. Assumes |
387 | * the receiver is in reset when the routine is called. |
388 | *****************************************************************************/ |
389 | void |
390 | ixgb_init_rx_addrs(struct ixgb_hw *hw) |
391 | { |
392 | uint32_t i; |
393 | |
394 | DEBUGFUNC("ixgb_init_rx_addrs");; |
395 | |
396 | /* |
397 | * If the current mac address is valid, assume it is a software override |
398 | * to the permanent address. |
399 | * Otherwise, use the permanent address from the eeprom. |
400 | */ |
401 | if(!mac_addr_valid(hw->curr_mac_addr)) { |
402 | |
403 | /* Get the MAC address from the eeprom for later reference */ |
404 | ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); |
405 | |
406 | DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ", |
407 | hw->curr_mac_addr[0], hw->curr_mac_addr[1], |
408 | hw->curr_mac_addr[2]); |
409 | DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3], |
410 | hw->curr_mac_addr[4], hw->curr_mac_addr[5]); |
411 | } else { |
412 | |
413 | /* Setup the receive address. */ |
414 | DEBUGOUT("Overriding MAC Address in RAR[0]\n"); |
415 | DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", |
416 | hw->curr_mac_addr[0], hw->curr_mac_addr[1], |
417 | hw->curr_mac_addr[2]); |
418 | DEBUGOUT3("%.2X %.2X %.2X\n", hw->curr_mac_addr[3], |
419 | hw->curr_mac_addr[4], hw->curr_mac_addr[5]); |
420 | |
421 | ixgb_rar_set(hw, hw->curr_mac_addr, 0); |
422 | } |
423 | |
424 | /* Zero out the other 15 receive addresses. */ |
425 | DEBUGOUT("Clearing RAR[1-15]\n"); |
426 | for(i = 1; i < IXGB_RAR_ENTRIES3; i++) { |
427 | IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00180 + (((i << 1)) << 2))), (0))); |
428 | IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00180 + ((((i << 1) + 1)) << 2))), (0))); |
429 | } |
430 | |
431 | return; |
432 | } |
433 | |
434 | /****************************************************************************** |
435 | * Updates the MAC's list of multicast addresses. |
436 | * |
437 | * hw - Struct containing variables accessed by shared code |
438 | * mc_addr_list - the list of new multicast addresses |
439 | * mc_addr_count - number of addresses |
440 | * pad - number of bytes between addresses in the list |
441 | * |
442 | * The given list replaces any existing list. Clears the last 15 receive |
443 | * address registers and the multicast table. Uses receive address registers |
444 | * for the first 15 multicast addresses, and hashes the rest into the |
445 | * multicast table. |
446 | *****************************************************************************/ |
447 | void |
448 | ixgb_mc_addr_list_update(struct ixgb_hw *hw, uint8_t *mc_addr_list, |
449 | uint32_t mc_addr_count, uint32_t pad) |
450 | { |
451 | uint32_t hash_value; |
452 | uint32_t i; |
453 | uint32_t rar_used_count = 1; /* RAR[0] is used for our MAC address */ |
454 | |
455 | DEBUGFUNC("ixgb_mc_addr_list_update");; |
456 | |
457 | /* Set the new number of MC addresses that we are being requested to |
458 | * use. */ |
459 | hw->num_mc_addrs = mc_addr_count; |
460 | |
461 | /* Clear RAR[1-15] */ |
462 | DEBUGOUT(" Clearing RAR[1-15]\n"); |
463 | for(i = rar_used_count; i < IXGB_RAR_ENTRIES3; i++) { |
464 | IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00180 + (((i << 1)) << 2))), (0))); |
465 | IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00180 + ((((i << 1) + 1)) << 2))), (0))); |
466 | } |
467 | |
468 | /* Clear the MTA */ |
469 | DEBUGOUT(" Clearing MTA\n"); |
470 | for(i = 0; i < IXGB_MC_TBL_SIZE128; i++) { |
471 | IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00200 + ((i) << 2))), (0))); |
472 | } |
473 | |
474 | /* Add the new addresses */ |
475 | for(i = 0; i < mc_addr_count; i++) { |
476 | DEBUGOUT(" Adding the multicast addresses:\n"); |
477 | DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i, |
478 | mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad)], |
479 | mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 1], |
480 | mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 2], |
481 | mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 3], |
482 | mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 4], |
483 | mc_addr_list[i * (IXGB_ETH_LENGTH_OF_ADDRESS + pad) + 5]); |
484 | |
485 | /* Place this multicast address in the RAR if there is room, * |
486 | * else put it in the MTA */ |
487 | if(rar_used_count < IXGB_RAR_ENTRIES3) { |
488 | ixgb_rar_set(hw, |
489 | mc_addr_list + |
490 | (i * (IXGB_ETH_LENGTH_OF_ADDRESS6 + pad)), |
491 | rar_used_count); |
492 | DEBUGOUT1("Added a multicast address to RAR[%d]\n", i); |
493 | rar_used_count++; |
494 | } else { |
495 | hash_value = |
496 | ixgb_hash_mc_addr(hw, |
497 | mc_addr_list + |
498 | (i * |
499 | (IXGB_ETH_LENGTH_OF_ADDRESS6 + |
500 | pad))); |
501 | |
502 | DEBUGOUT1(" Hash value = 0x%03X\n", hash_value); |
503 | |
504 | ixgb_mta_set(hw, hash_value); |
505 | } |
506 | } |
507 | |
508 | DEBUGOUT("MC Update Complete\n"); |
509 | return; |
510 | } |
511 | |
512 | /****************************************************************************** |
513 | * Hashes an address to determine its location in the multicast table |
514 | * |
515 | * hw - Struct containing variables accessed by shared code |
516 | * mc_addr - the multicast address to hash |
517 | * |
518 | * Returns: |
519 | * The hash value |
520 | *****************************************************************************/ |
521 | static uint32_t |
522 | ixgb_hash_mc_addr(struct ixgb_hw *hw, uint8_t *mc_addr) |
523 | { |
524 | uint32_t hash_value = 0; |
525 | |
526 | DEBUGFUNC("ixgb_hash_mc_addr");; |
527 | |
528 | /* The portion of the address that is used for the hash table is |
529 | * determined by the mc_filter_type setting. */ |
530 | switch(hw->mc_filter_type) { |
531 | /* [0] [1] [2] [3] [4] [5] 01 AA 00 12 34 56 LSB MSB - |
532 | * According to H/W docs */ |
533 | case 0: |
534 | /* [47:36] i.e. 0x563 for above example address */ |
535 | hash_value = |
536 | ((mc_addr[4] >> 4) | (((uint16_t)mc_addr[5]) << 4)); |
537 | break; |
538 | case 1: /* [46:35] i.e. 0xAC6 for above |
539 | * example address */ |
540 | hash_value = |
541 | ((mc_addr[4] >> 3) | (((uint16_t)mc_addr[5]) << 5)); |
542 | break; |
543 | case 2: /* [45:34] i.e. 0x5D8 for above |
544 | * example address */ |
545 | hash_value = |
546 | ((mc_addr[4] >> 2) | (((uint16_t)mc_addr[5]) << 6)); |
547 | break; |
548 | case 3: /* [43:32] i.e. 0x634 for above |
549 | * example address */ |
550 | hash_value = ((mc_addr[4]) | (((uint16_t)mc_addr[5]) << 8)); |
551 | break; |
552 | default: |
553 | /* Invalid mc_filter_type, what should we do? */ |
554 | DEBUGOUT("MC filter type param set incorrectly\n"); |
555 | ASSERT(0)if(!(0)) panic("IXGB: x"); |
556 | break; |
557 | } |
558 | |
559 | hash_value &= 0xFFF; |
560 | return (hash_value); |
561 | } |
562 | |
563 | /****************************************************************************** |
564 | * Sets the bit in the multicast table corresponding to the hash value. |
565 | * |
566 | * hw - Struct containing variables accessed by shared code |
567 | * hash_value - Multicast address hash value |
568 | *****************************************************************************/ |
569 | static void |
570 | ixgb_mta_set(struct ixgb_hw *hw, uint32_t hash_value) |
571 | { |
572 | uint32_t hash_bit, hash_reg; |
573 | uint32_t mta_reg; |
574 | |
575 | /* The MTA is a register array of 128 32-bit registers. It is treated |
576 | * like an array of 4096 bits. We want to set bit |
577 | * BitArray[hash_value]. So we figure out what register the bit is in, |
578 | * read it, OR in the new bit, then write back the new value. The |
579 | * register is determined by the upper 7 bits of the hash value and the |
580 | * bit within that register are determined by the lower 5 bits of the |
581 | * value. */ |
582 | hash_reg = (hash_value >> 5) & 0x7F; |
583 | hash_bit = hash_value & 0x1F; |
584 | mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00200 + ((hash_reg) << 2))))); |
585 | mta_reg |= (1 << hash_bit); |
586 | IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00200 + ((hash_reg) << 2))), (mta_reg))); |
587 | return; |
588 | } |
589 | |
590 | /****************************************************************************** |
591 | * Puts an ethernet address into a receive address register. |
592 | * |
593 | * hw - Struct containing variables accessed by shared code |
594 | * addr - Address to put into receive address register |
595 | * index - Receive address register to write |
596 | *****************************************************************************/ |
597 | void |
598 | ixgb_rar_set(struct ixgb_hw *hw, uint8_t *addr, uint32_t index) |
599 | { |
600 | uint32_t rar_low, rar_high; |
601 | |
602 | DEBUGFUNC("ixgb_rar_set");; |
603 | |
604 | /* HW expects these in little endian so we reverse the byte order from |
605 | * network order (big endian) to little endian */ |
606 | rar_low = ((uint32_t)addr[0] | |
607 | ((uint32_t)addr[1] << 8) | |
608 | ((uint32_t)addr[2] << 16) | |
609 | ((uint32_t)addr[3] << 24)); |
610 | |
611 | rar_high = ((uint32_t)addr[4] | |
612 | ((uint32_t)addr[5] << 8) | |
613 | IXGB_RAH_AV0x80000000); |
614 | |
615 | IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00180 + (((index << 1)) << 2))), (rar_low) )); |
616 | IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00180 + ((((index << 1) + 1)) << 2))), (rar_high ))); |
617 | return; |
618 | } |
619 | |
620 | /****************************************************************************** |
621 | * Writes a value to the specified offset in the VLAN filter table. |
622 | * |
623 | * hw - Struct containing variables accessed by shared code |
624 | * offset - Offset in VLAN filer table to write |
625 | * value - Value to write into VLAN filter table |
626 | *****************************************************************************/ |
627 | void |
628 | ixgb_write_vfta(struct ixgb_hw *hw, uint32_t offset, uint32_t value) |
629 | { |
630 | IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00400 + ((offset) << 2))), (value))); |
631 | return; |
632 | } |
633 | |
634 | /****************************************************************************** |
635 | * Clears the VLAN filer table |
636 | * |
637 | * hw - Struct containing variables accessed by shared code |
638 | *****************************************************************************/ |
639 | void |
640 | ixgb_clear_vfta(struct ixgb_hw *hw) |
641 | { |
642 | uint32_t offset; |
643 | |
644 | for(offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE128; offset++) |
645 | IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), ((0x00400 + ((offset) << 2))), (0))); |
646 | return; |
647 | } |
648 | |
649 | /****************************************************************************** |
650 | * Configures the flow control settings based on SW configuration. |
651 | * |
652 | * hw - Struct containing variables accessed by shared code |
653 | *****************************************************************************/ |
654 | |
655 | boolean_t |
656 | ixgb_setup_fc(struct ixgb_hw *hw) |
657 | { |
658 | uint32_t ctrl_reg; |
659 | uint32_t pap_reg = 0; /* by default, assume no pause time */ |
660 | boolean_t status = TRUE1; |
661 | |
662 | DEBUGFUNC("ixgb_setup_fc");; |
663 | |
664 | /* Get the current control reg 0 settings */ |
665 | ctrl_reg = IXGB_READ_REG(hw, CTRL0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))); |
666 | |
667 | /* Clear the Receive Pause Enable and Transmit Pause Enable bits */ |
668 | ctrl_reg &= ~(IXGB_CTRL0_RPE0x08000000 | IXGB_CTRL0_TPE0x10000000); |
669 | |
670 | /* The possible values of the "flow_control" parameter are: |
671 | * 0: Flow control is completely disabled |
672 | * 1: Rx flow control is enabled (we can receive pause frames but not send |
673 | * pause frames). |
674 | * 2: Tx flow control is enabled (we can send pause frames but we do not |
675 | * support receiving pause frames) |
676 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
677 | * other: Invalid. */ |
678 | switch(hw->fc.type) { |
679 | case ixgb_fc_none: /* 0 */ |
680 | /* Set CMDC bit to disable Rx Flow control */ |
681 | ctrl_reg |= (IXGB_CTRL0_CMDC0x00000080); |
682 | break; |
683 | case ixgb_fc_rx_pause: /* 1 */ |
684 | /* RX Flow control is enabled, and TX Flow control is disabled. */ |
685 | ctrl_reg |= (IXGB_CTRL0_RPE0x08000000); |
686 | break; |
687 | case ixgb_fc_tx_pause: /* 2 */ |
688 | /* TX Flow control is enabled, and RX Flow control is disabled, |
689 | * by a software over-ride. */ |
690 | ctrl_reg |= (IXGB_CTRL0_TPE0x10000000); |
691 | pap_reg = hw->fc.pause_time; |
692 | break; |
693 | case ixgb_fc_full: /* 3 */ |
694 | /* Flow control (both RX and TX) is enabled by a software |
695 | * over-ride. */ |
696 | ctrl_reg |= (IXGB_CTRL0_RPE0x08000000 | IXGB_CTRL0_TPE0x10000000); |
697 | pap_reg = hw->fc.pause_time; |
698 | break; |
699 | default: |
700 | /* We should never get here. The value should be 0-3. */ |
701 | DEBUGOUT("Flow control param set incorrectly\n"); |
702 | ASSERT(0)if(!(0)) panic("IXGB: x"); |
703 | break; |
704 | } |
705 | |
706 | /* Write the new settings */ |
707 | IXGB_WRITE_REG(hw, CTRL0, ctrl_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (ctrl_reg))); |
708 | |
709 | if(pap_reg != 0) { |
710 | IXGB_WRITE_REG(hw, PAP, pap_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00640), (pap_reg))); |
711 | } |
712 | |
713 | /* Set the flow control receive threshold registers. Normally, these |
714 | * registers will be set to a default threshold that may be adjusted |
715 | * later by the driver's runtime code. However, if the ability to |
716 | * transmit pause frames in not enabled, then these registers will be |
717 | * set to 0. */ |
718 | if(!(hw->fc.type & ixgb_fc_tx_pause)) { |
719 | IXGB_WRITE_REG(hw, FCRTL, 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00108), (0))); |
720 | IXGB_WRITE_REG(hw, FCRTH, 0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00110), (0))); |
721 | } else { |
722 | /* We need to set up the Receive Threshold high and low water |
723 | * marks as well as (optionally) enabling the transmission of |
724 | * XON frames. */ |
725 | if(hw->fc.send_xon) { |
726 | IXGB_WRITE_REG(hw, FCRTL,((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00108), ((hw->fc.low_water | 0x80000000)))) |
727 | (hw->fc.low_water | IXGB_FCRTL_XONE))((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00108), ((hw->fc.low_water | 0x80000000)))); |
728 | } else { |
729 | IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00108), (hw->fc.low_water))); |
730 | } |
731 | IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00110), (hw->fc.high_water))); |
732 | } |
733 | return (status); |
734 | } |
735 | |
736 | /****************************************************************************** |
737 | * Reads a word from a device over the Management Data Interface (MDI) bus. |
738 | * This interface is used to manage Physical layer devices. |
739 | * |
740 | * hw - Struct containing variables accessed by hw code |
741 | * reg_address - Offset of device register being read. |
742 | * phy_address - Address of device on MDI. |
743 | * |
744 | * Returns: Data word (16 bits) from MDI device. |
745 | * |
746 | * The 82597EX has support for several MDI access methods. This routine |
747 | * uses the new protocol MDI Single Command and Address Operation. |
748 | * This requires that first an address cycle command is sent, followed by a |
749 | * read command. |
750 | *****************************************************************************/ |
751 | uint16_t |
752 | ixgb_read_phy_reg(struct ixgb_hw *hw, uint32_t reg_address, |
753 | uint32_t phy_address, uint32_t device_type) |
754 | { |
755 | uint32_t i; |
756 | uint32_t data; |
757 | uint32_t command = 0; |
758 | |
759 | ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS)if(!(reg_address <= 0xFFFF)) panic("IXGB: x"); |
760 | ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS)if(!(phy_address <= 31)) panic("IXGB: x"); |
761 | ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE)if(!(device_type <= 31)) panic("IXGB: x"); |
762 | |
763 | /* Setup and write the address cycle command */ |
764 | command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT0) | |
765 | (device_type << IXGB_MSCA_DEV_TYPE_SHIFT16) | |
766 | (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT21) | |
767 | (IXGB_MSCA_ADDR_CYCLE0x00000000 | IXGB_MSCA_MDI_COMMAND0x40000000)); |
768 | |
769 | IXGB_WRITE_REG(hw, MSCA, command)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758), (command))); |
770 | |
771 | /************************************************************** |
772 | ** Check every 10 usec to see if the address cycle completed |
773 | ** The COMMAND bit will clear when the operation is complete. |
774 | ** This may take as long as 64 usecs (we'll wait 100 usecs max) |
775 | ** from the CPU Write to the Ready bit assertion. |
776 | **************************************************************/ |
777 | |
778 | for(i = 0; i < 10; i++) { |
779 | usec_delay(10)(*delay_func)(10); |
780 | |
781 | command = IXGB_READ_REG(hw, MSCA)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758))); |
782 | |
783 | if((command & IXGB_MSCA_MDI_COMMAND0x40000000) == 0) |
784 | break; |
785 | } |
786 | |
787 | ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0)if(!((command & 0x40000000) == 0)) panic("IXGB: x"); |
788 | |
789 | /* Address cycle complete, setup and write the read command */ |
790 | command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT0) | |
791 | (device_type << IXGB_MSCA_DEV_TYPE_SHIFT16) | |
792 | (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT21) | |
793 | (IXGB_MSCA_READ0x08000000 | IXGB_MSCA_MDI_COMMAND0x40000000)); |
794 | |
795 | IXGB_WRITE_REG(hw, MSCA, command)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758), (command))); |
796 | |
797 | /************************************************************** |
798 | ** Check every 10 usec to see if the read command completed |
799 | ** The COMMAND bit will clear when the operation is complete. |
800 | ** The read may take as long as 64 usecs (we'll wait 100 usecs max) |
801 | ** from the CPU Write to the Ready bit assertion. |
802 | **************************************************************/ |
803 | |
804 | for(i = 0; i < 10; i++) { |
805 | usec_delay(10)(*delay_func)(10); |
806 | |
807 | command = IXGB_READ_REG(hw, MSCA)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758))); |
808 | |
809 | if((command & IXGB_MSCA_MDI_COMMAND0x40000000) == 0) |
810 | break; |
811 | } |
812 | |
813 | ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0)if(!((command & 0x40000000) == 0)) panic("IXGB: x"); |
814 | |
815 | /* Operation is complete, get the data from the MDIO Read/Write Data |
816 | * register and return. */ |
817 | data = IXGB_READ_REG(hw, MSRWD)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00760))); |
818 | data >>= IXGB_MSRWD_READ_DATA_SHIFT16; |
819 | return ((uint16_t)data); |
820 | } |
821 | |
822 | /****************************************************************************** |
823 | * Writes a word to a device over the Management Data Interface (MDI) bus. |
824 | * This interface is used to manage Physical layer devices. |
825 | * |
826 | * hw - Struct containing variables accessed by hw code |
827 | * reg_address - Offset of device register being read. |
828 | * phy_address - Address of device on MDI. |
829 | * device_type - Also known as the Device ID or DID. |
830 | * data - 16-bit value to be written |
831 | * |
832 | * Returns: void. |
833 | * |
834 | * The 82597EX has support for several MDI access methods. This routine |
835 | * uses the new protocol MDI Single Command and Address Operation. |
836 | * This requires that first an address cycle command is sent, followed by a |
837 | * write command. |
838 | *****************************************************************************/ |
839 | void |
840 | ixgb_write_phy_reg(struct ixgb_hw *hw, uint32_t reg_address, |
841 | uint32_t phy_address, uint32_t device_type, uint16_t data) |
842 | { |
843 | uint32_t i; |
844 | uint32_t command = 0; |
845 | |
846 | ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS)if(!(reg_address <= 0xFFFF)) panic("IXGB: x"); |
847 | ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS)if(!(phy_address <= 31)) panic("IXGB: x"); |
848 | ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE)if(!(device_type <= 31)) panic("IXGB: x"); |
849 | |
850 | /* Put the data in the MDIO Read/Write Data register */ |
851 | IXGB_WRITE_REG(hw, MSRWD, (uint32_t)data)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00760), ((uint32_t)data))); |
852 | |
853 | /* Setup and write the address cycle command */ |
854 | command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT0) | |
855 | (device_type << IXGB_MSCA_DEV_TYPE_SHIFT16) | |
856 | (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT21) | |
857 | (IXGB_MSCA_ADDR_CYCLE0x00000000 | IXGB_MSCA_MDI_COMMAND0x40000000)); |
858 | |
859 | IXGB_WRITE_REG(hw, MSCA, command)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758), (command))); |
860 | |
861 | /************************************************************** |
862 | ** Check every 10 usec to see if the address cycle completed |
863 | ** The COMMAND bit will clear when the operation is complete. |
864 | ** This may take as long as 64 usecs (we'll wait 100 usecs max) |
865 | ** from the CPU Write to the Ready bit assertion. |
866 | **************************************************************/ |
867 | |
868 | for(i = 0; i < 10; i++) { |
869 | usec_delay(10)(*delay_func)(10); |
870 | |
871 | command = IXGB_READ_REG(hw, MSCA)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758))); |
872 | |
873 | if((command & IXGB_MSCA_MDI_COMMAND0x40000000) == 0) |
874 | break; |
875 | } |
876 | |
877 | ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0)if(!((command & 0x40000000) == 0)) panic("IXGB: x"); |
878 | |
879 | /* Address cycle complete, setup and write the write command */ |
880 | command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT0) | |
881 | (device_type << IXGB_MSCA_DEV_TYPE_SHIFT16) | |
882 | (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT21) | |
883 | (IXGB_MSCA_WRITE0x04000000 | IXGB_MSCA_MDI_COMMAND0x40000000)); |
884 | |
885 | IXGB_WRITE_REG(hw, MSCA, command)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758), (command))); |
886 | |
887 | /************************************************************** |
888 | ** Check every 10 usec to see if the read command completed |
889 | ** The COMMAND bit will clear when the operation is complete. |
890 | ** The write may take as long as 64 usecs (we'll wait 100 usecs max) |
891 | ** from the CPU Write to the Ready bit assertion. |
892 | **************************************************************/ |
893 | |
894 | for(i = 0; i < 10; i++) { |
895 | usec_delay(10)(*delay_func)(10); |
896 | |
897 | command = IXGB_READ_REG(hw, MSCA)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00758))); |
898 | |
899 | if((command & IXGB_MSCA_MDI_COMMAND0x40000000) == 0) |
900 | break; |
901 | } |
902 | |
903 | ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0)if(!((command & 0x40000000) == 0)) panic("IXGB: x"); |
904 | |
905 | /* Operation is complete, return. */ |
906 | } |
907 | |
908 | /****************************************************************************** |
909 | * Checks to see if the link status of the hardware has changed. |
910 | * |
911 | * hw - Struct containing variables accessed by hw code |
912 | * |
913 | * Called by any function that needs to check the link status of the adapter. |
914 | *****************************************************************************/ |
915 | void |
916 | ixgb_check_for_link(struct ixgb_hw *hw) |
917 | { |
918 | uint32_t status_reg; |
919 | uint32_t xpcss_reg; |
920 | |
921 | DEBUGFUNC("ixgb_check_for_link");; |
922 | |
923 | xpcss_reg = IXGB_READ_REG(hw, XPCSS)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00720))); |
924 | status_reg = IXGB_READ_REG(hw, STATUS)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00010))); |
925 | |
926 | if((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS0x00001000) && |
927 | (status_reg & IXGB_STATUS_LU0x00000002)) { |
928 | hw->link_up = TRUE1; |
929 | } else if(!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS0x00001000) && |
930 | (status_reg & IXGB_STATUS_LU0x00000002)) { |
931 | DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n"); |
932 | hw->link_up = ixgb_link_reset(hw); |
933 | } else { |
934 | /* |
935 | * 82597EX errata. Since the lane deskew problem may prevent |
936 | * link, reset the link before reporting link down. |
937 | */ |
938 | hw->link_up = ixgb_link_reset(hw); |
939 | } |
940 | /* Anything else for 10 Gig?? */ |
941 | } |
942 | |
943 | /****************************************************************************** |
944 | * Check for a bad link condition that may have occurred. |
945 | * The indication is that the RFC / LFC registers may be incrementing |
946 | * continually. A full adapter reset is required to recover. |
947 | * |
948 | * hw - Struct containing variables accessed by hw code |
949 | * |
950 | * Called by any function that needs to check the link status of the adapter. |
951 | *****************************************************************************/ |
952 | boolean_t |
953 | ixgb_check_for_bad_link(struct ixgb_hw *hw) |
954 | { |
955 | uint32_t newLFC, newRFC; |
956 | boolean_t bad_link_returncode = FALSE0; |
957 | |
958 | if(hw->phy_type == ixgb_phy_type_txn17401) { |
959 | newLFC = IXGB_READ_REG(hw, LFC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02190))); |
960 | newRFC = IXGB_READ_REG(hw, RFC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02188))); |
961 | if((hw->lastLFC + 250 < newLFC) || (hw->lastRFC + 250 < newRFC)) { |
962 | DEBUGOUT("BAD LINK! too many LFC/RFC since last check\n"); |
963 | bad_link_returncode = TRUE1; |
964 | } |
965 | hw->lastLFC = newLFC; |
966 | hw->lastRFC = newRFC; |
967 | } |
968 | |
969 | return bad_link_returncode; |
970 | } |
971 | |
972 | /****************************************************************************** |
973 | * Clears all hardware statistics counters. |
974 | * |
975 | * hw - Struct containing variables accessed by shared code |
976 | *****************************************************************************/ |
977 | void |
978 | ixgb_clear_hw_cntrs(struct ixgb_hw *hw) |
979 | { |
980 | volatile uint32_t temp_reg; |
981 | |
982 | DEBUGFUNC("ixgb_clear_hw_cntrs");; |
983 | |
984 | /* if we are stopped or resetting exit gracefully */ |
985 | if(hw->adapter_stopped) { |
986 | DEBUGOUT("Exiting because the adapter is stopped!!!\n"); |
987 | return; |
988 | } |
989 | |
990 | temp_reg = IXGB_READ_REG(hw, TPRL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02000))); |
991 | temp_reg = IXGB_READ_REG(hw, TPRH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02004))); |
992 | temp_reg = IXGB_READ_REG(hw, GPRCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02008))); |
993 | temp_reg = IXGB_READ_REG(hw, GPRCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0200C))); |
994 | temp_reg = IXGB_READ_REG(hw, BPRCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02010))); |
995 | temp_reg = IXGB_READ_REG(hw, BPRCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02014))); |
996 | temp_reg = IXGB_READ_REG(hw, MPRCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02018))); |
997 | temp_reg = IXGB_READ_REG(hw, MPRCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0201C))); |
998 | temp_reg = IXGB_READ_REG(hw, UPRCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02020))); |
999 | temp_reg = IXGB_READ_REG(hw, UPRCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02024))); |
1000 | temp_reg = IXGB_READ_REG(hw, VPRCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02028))); |
1001 | temp_reg = IXGB_READ_REG(hw, VPRCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0202C))); |
1002 | temp_reg = IXGB_READ_REG(hw, JPRCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02030))); |
1003 | temp_reg = IXGB_READ_REG(hw, JPRCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02034))); |
1004 | temp_reg = IXGB_READ_REG(hw, GORCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02038))); |
1005 | temp_reg = IXGB_READ_REG(hw, GORCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0203C))); |
1006 | temp_reg = IXGB_READ_REG(hw, TORL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02040))); |
1007 | temp_reg = IXGB_READ_REG(hw, TORH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02044))); |
1008 | temp_reg = IXGB_READ_REG(hw, RNBC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02048))); |
1009 | temp_reg = IXGB_READ_REG(hw, RUC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02050))); |
1010 | temp_reg = IXGB_READ_REG(hw, ROC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02058))); |
1011 | temp_reg = IXGB_READ_REG(hw, RLEC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02060))); |
1012 | temp_reg = IXGB_READ_REG(hw, CRCERRS)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02068))); |
1013 | temp_reg = IXGB_READ_REG(hw, ICBC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02070))); |
1014 | temp_reg = IXGB_READ_REG(hw, ECBC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02078))); |
1015 | temp_reg = IXGB_READ_REG(hw, MPC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02080))); |
1016 | temp_reg = IXGB_READ_REG(hw, TPTL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02100))); |
1017 | temp_reg = IXGB_READ_REG(hw, TPTH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02104))); |
1018 | temp_reg = IXGB_READ_REG(hw, GPTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02108))); |
1019 | temp_reg = IXGB_READ_REG(hw, GPTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0210C))); |
1020 | temp_reg = IXGB_READ_REG(hw, BPTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02110))); |
1021 | temp_reg = IXGB_READ_REG(hw, BPTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02114))); |
1022 | temp_reg = IXGB_READ_REG(hw, MPTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02118))); |
1023 | temp_reg = IXGB_READ_REG(hw, MPTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0211C))); |
1024 | temp_reg = IXGB_READ_REG(hw, UPTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02120))); |
1025 | temp_reg = IXGB_READ_REG(hw, UPTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02124))); |
1026 | temp_reg = IXGB_READ_REG(hw, VPTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02128))); |
1027 | temp_reg = IXGB_READ_REG(hw, VPTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0212C))); |
1028 | temp_reg = IXGB_READ_REG(hw, JPTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02130))); |
1029 | temp_reg = IXGB_READ_REG(hw, JPTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02134))); |
1030 | temp_reg = IXGB_READ_REG(hw, GOTCL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02138))); |
1031 | temp_reg = IXGB_READ_REG(hw, GOTCH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x0213C))); |
1032 | temp_reg = IXGB_READ_REG(hw, TOTL)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02140))); |
1033 | temp_reg = IXGB_READ_REG(hw, TOTH)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02144))); |
1034 | temp_reg = IXGB_READ_REG(hw, DC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02148))); |
1035 | temp_reg = IXGB_READ_REG(hw, PLT64C)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02150))); |
1036 | temp_reg = IXGB_READ_REG(hw, TSCTC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02170))); |
1037 | temp_reg = IXGB_READ_REG(hw, TSCTFC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02178))); |
1038 | temp_reg = IXGB_READ_REG(hw, IBIC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02180))); |
1039 | temp_reg = IXGB_READ_REG(hw, RFC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02188))); |
1040 | temp_reg = IXGB_READ_REG(hw, LFC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02190))); |
1041 | temp_reg = IXGB_READ_REG(hw, PFRC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x02198))); |
1042 | temp_reg = IXGB_READ_REG(hw, PFTC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021A0))); |
1043 | temp_reg = IXGB_READ_REG(hw, MCFRC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021A8))); |
1044 | temp_reg = IXGB_READ_REG(hw, MCFTC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021B0))); |
1045 | temp_reg = IXGB_READ_REG(hw, XONRXC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021B8))); |
1046 | temp_reg = IXGB_READ_REG(hw, XONTXC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021C0))); |
1047 | temp_reg = IXGB_READ_REG(hw, XOFFRXC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021C8))); |
1048 | temp_reg = IXGB_READ_REG(hw, XOFFTXC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021D0))); |
1049 | temp_reg = IXGB_READ_REG(hw, RJC)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x021D8))); |
1050 | return; |
1051 | } |
1052 | |
1053 | /****************************************************************************** |
1054 | * Turns on the software controllable LED |
1055 | * |
1056 | * hw - Struct containing variables accessed by shared code |
1057 | *****************************************************************************/ |
1058 | void |
1059 | ixgb_led_on(struct ixgb_hw *hw) |
1060 | { |
1061 | uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))); |
1062 | |
1063 | /* To turn on the LED, clear software-definable pin 0 (SDP0). */ |
1064 | ctrl0_reg &= ~IXGB_CTRL0_SDP00x00040000; |
1065 | IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (ctrl0_reg))); |
1066 | return; |
1067 | } |
1068 | |
1069 | /****************************************************************************** |
1070 | * Turns off the software controllable LED |
1071 | * |
1072 | * hw - Struct containing variables accessed by shared code |
1073 | *****************************************************************************/ |
1074 | void |
1075 | ixgb_led_off(struct ixgb_hw *hw) |
1076 | { |
1077 | uint32_t ctrl0_reg = IXGB_READ_REG(hw, CTRL0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))); |
1078 | |
1079 | /* To turn off the LED, set software-definable pin 0 (SDP0). */ |
1080 | ctrl0_reg |= IXGB_CTRL0_SDP00x00040000; |
1081 | IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (ctrl0_reg))); |
1082 | return; |
1083 | } |
1084 | |
1085 | /****************************************************************************** |
1086 | * Gets the current PCI bus type, speed, and width of the hardware |
1087 | * |
1088 | * hw - Struct containing variables accessed by shared code |
1089 | *****************************************************************************/ |
1090 | static void |
1091 | ixgb_get_bus_info(struct ixgb_hw *hw) |
1092 | { |
1093 | uint32_t status_reg; |
1094 | |
1095 | status_reg = IXGB_READ_REG(hw, STATUS)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00010))); |
1096 | |
1097 | hw->bus.type = |
1098 | (status_reg & IXGB_STATUS_PCIX_MODE0x00002000) ? ixgb_bus_type_pcix : |
1099 | ixgb_bus_type_pci; |
1100 | |
1101 | if(hw->bus.type == ixgb_bus_type_pci) { |
1102 | hw->bus.speed = |
1103 | (status_reg & IXGB_STATUS_PCI_SPD0x00000800) ? ixgb_bus_speed_66 : |
1104 | ixgb_bus_speed_33; |
1105 | } else { |
1106 | switch(status_reg & IXGB_STATUS_PCIX_SPD_MASK0x0000C000) { |
1107 | case IXGB_STATUS_PCIX_SPD_660x00000000: |
1108 | hw->bus.speed = ixgb_bus_speed_66; |
1109 | break; |
1110 | case IXGB_STATUS_PCIX_SPD_1000x00004000: |
1111 | hw->bus.speed = ixgb_bus_speed_100; |
1112 | break; |
1113 | case IXGB_STATUS_PCIX_SPD_1330x00008000: |
1114 | hw->bus.speed = ixgb_bus_speed_133; |
1115 | break; |
1116 | default: |
1117 | hw->bus.speed = ixgb_bus_speed_reserved; |
1118 | break; |
1119 | } |
1120 | } |
1121 | |
1122 | hw->bus.width = |
1123 | (status_reg & IXGB_STATUS_BUS640x00001000) ? ixgb_bus_width_64 : |
1124 | ixgb_bus_width_32; |
1125 | |
1126 | return; |
1127 | } |
1128 | |
1129 | /****************************************************************************** |
1130 | * Tests a MAC address to ensure it is a valid Individual Address |
1131 | * |
1132 | * mac_addr - pointer to MAC address. |
1133 | * |
1134 | *****************************************************************************/ |
1135 | boolean_t |
1136 | mac_addr_valid(uint8_t *mac_addr) |
1137 | { |
1138 | boolean_t is_valid = TRUE1; |
1139 | |
1140 | DEBUGFUNC("mac_addr_valid");; |
1141 | |
1142 | /* Make sure it is not a multicast address */ |
1143 | if(IS_MULTICAST(mac_addr)(boolean_t)(((uint8_t *)(mac_addr))[0] & ((uint8_t)0x01))) { |
1144 | DEBUGOUT("MAC address is multicast\n"); |
1145 | is_valid = FALSE0; |
1146 | } |
1147 | /* Not a broadcast address */ |
1148 | else if(IS_BROADCAST(mac_addr)((((uint8_t *)(mac_addr))[0] == ((uint8_t)0xff)) && ( ((uint8_t *)(mac_addr))[1] == ((uint8_t)0xff)))) { |
1149 | DEBUGOUT("MAC address is broadcast\n"); |
1150 | is_valid = FALSE0; |
1151 | } |
1152 | /* Reject the zero address */ |
1153 | else if (mac_addr[0] == 0 && |
1154 | mac_addr[1] == 0 && |
1155 | mac_addr[2] == 0 && |
1156 | mac_addr[3] == 0 && |
1157 | mac_addr[4] == 0 && |
1158 | mac_addr[5] == 0) { |
1159 | DEBUGOUT("MAC address is all zeros\n"); |
1160 | is_valid = FALSE0; |
1161 | } |
1162 | return (is_valid); |
1163 | } |
1164 | |
1165 | /****************************************************************************** |
1166 | * Resets the 10GbE link. Waits the settle time and returns the state of |
1167 | * the link. |
1168 | * |
1169 | * hw - Struct containing variables accessed by shared code |
1170 | *****************************************************************************/ |
1171 | boolean_t |
1172 | ixgb_link_reset(struct ixgb_hw *hw) |
1173 | { |
1174 | boolean_t link_status = FALSE0; |
1175 | uint8_t wait_retries = MAX_RESET_ITERATIONS8; |
1176 | uint8_t lrst_retries = MAX_RESET_ITERATIONS8; |
1177 | |
1178 | do { |
1179 | /* Reset the link */ |
1180 | IXGB_WRITE_REG(hw, CTRL0,((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag )->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))) | 0x00000008))) |
1181 | IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag )->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))) | 0x00000008))); |
1182 | |
1183 | /* Wait for link-up and lane re-alignment */ |
1184 | do { |
1185 | usec_delay(IXGB_DELAY_USECS_AFTER_LINK_RESET)(*delay_func)(13); |
1186 | link_status = |
1187 | ((IXGB_READ_REG(hw, STATUS)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00010))) & IXGB_STATUS_LU0x00000002) && |
1188 | (IXGB_READ_REG(hw, XPCSS)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00720))) & |
1189 | IXGB_XPCSS_ALIGN_STATUS0x00001000)) ? TRUE1 : FALSE0; |
1190 | } while(!link_status && --wait_retries); |
1191 | |
1192 | } while(!link_status && --lrst_retries); |
1193 | |
1194 | return link_status; |
1195 | } |
1196 | |
1197 | /****************************************************************************** |
1198 | * Resets the 10GbE optics module. |
1199 | * |
1200 | * hw - Struct containing variables accessed by shared code |
1201 | *****************************************************************************/ |
1202 | void |
1203 | ixgb_optics_reset(struct ixgb_hw *hw) |
1204 | { |
1205 | if(hw->phy_type == ixgb_phy_type_txn17401) { |
1206 | uint16_t mdio_reg; |
1207 | |
1208 | ixgb_write_phy_reg(hw, |
1209 | MDIO_PMA_PMD_CR10x0000, |
1210 | IXGB_PHY_ADDRESS0x0, |
1211 | MDIO_PMA_PMD_DID0x01, |
1212 | MDIO_PMA_PMD_CR1_RESET0x8000); |
1213 | |
1214 | mdio_reg = ixgb_read_phy_reg(hw, |
1215 | MDIO_PMA_PMD_CR10x0000, |
1216 | IXGB_PHY_ADDRESS0x0, |
1217 | MDIO_PMA_PMD_DID0x01); |
1218 | } |
1219 | |
1220 | return; |
1221 | } |
1222 | |
1223 | /****************************************************************************** |
1224 | * Resets the 10GbE optics module for Sun variant NIC. |
1225 | * |
1226 | * hw - Struct containing variables accessed by shared code |
1227 | *****************************************************************************/ |
1228 | |
1229 | #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG0xC803 0xC803 |
1230 | #define IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL0x0164 0x0164 |
1231 | #define IXGB_BCM8704_USER_CTRL_REG0xC800 0xC800 |
1232 | #define IXGB_BCM8704_USER_CTRL_REG_VAL0x7FBF 0x7FBF |
1233 | #define IXGB_BCM8704_USER_DEV3_ADDR0x0003 0x0003 |
1234 | #define IXGB_SUN_PHY_ADDRESS0x0000 0x0000 |
1235 | #define IXGB_SUN_PHY_RESET_DELAY305 305 |
1236 | |
1237 | static void |
1238 | ixgb_optics_reset_bcm(struct ixgb_hw *hw) |
1239 | { |
1240 | uint32_t ctrl = IXGB_READ_REG(hw, CTRL0)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->read_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000))); |
1241 | ctrl &= ~IXGB_CTRL0_SDP20x00100000; |
1242 | ctrl |= IXGB_CTRL0_SDP30x00200000; |
1243 | IXGB_WRITE_REG(hw, CTRL0, ctrl)((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_tag) ->write_4((((struct ixgb_osdep *)(hw)->back)->mem_bus_space_handle ), (0x00000), (ctrl))); |
1244 | |
1245 | /* SerDes needs extra delay */ |
1246 | msec_delay(IXGB_SUN_PHY_RESET_DELAY)(*delay_func)(1000*(305)); |
1247 | |
1248 | /* Broadcom 7408L configuration */ |
1249 | /* Reference clock config */ |
1250 | ixgb_write_phy_reg(hw, |
1251 | IXGB_BCM8704_USER_PMD_TX_CTRL_REG0xC803, |
1252 | IXGB_SUN_PHY_ADDRESS0x0000, |
1253 | IXGB_BCM8704_USER_DEV3_ADDR0x0003, |
1254 | IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL0x0164); |
1255 | /* we must read the registers twice */ |
1256 | ixgb_read_phy_reg(hw, |
1257 | IXGB_BCM8704_USER_PMD_TX_CTRL_REG0xC803, |
1258 | IXGB_SUN_PHY_ADDRESS0x0000, |
1259 | IXGB_BCM8704_USER_DEV3_ADDR0x0003); |
1260 | ixgb_read_phy_reg(hw, |
1261 | IXGB_BCM8704_USER_PMD_TX_CTRL_REG0xC803, |
1262 | IXGB_SUN_PHY_ADDRESS0x0000, |
1263 | IXGB_BCM8704_USER_DEV3_ADDR0x0003); |
1264 | |
1265 | ixgb_write_phy_reg(hw, |
1266 | IXGB_BCM8704_USER_CTRL_REG0xC800, |
1267 | IXGB_SUN_PHY_ADDRESS0x0000, |
1268 | IXGB_BCM8704_USER_DEV3_ADDR0x0003, |
1269 | IXGB_BCM8704_USER_CTRL_REG_VAL0x7FBF); |
1270 | ixgb_read_phy_reg(hw, |
1271 | IXGB_BCM8704_USER_CTRL_REG0xC800, |
1272 | IXGB_SUN_PHY_ADDRESS0x0000, |
1273 | IXGB_BCM8704_USER_DEV3_ADDR0x0003); |
1274 | ixgb_read_phy_reg(hw, |
1275 | IXGB_BCM8704_USER_CTRL_REG0xC800, |
1276 | IXGB_SUN_PHY_ADDRESS0x0000, |
1277 | IXGB_BCM8704_USER_DEV3_ADDR0x0003); |
1278 | |
1279 | /* SerDes needs extra delay */ |
1280 | msec_delay(IXGB_SUN_PHY_RESET_DELAY)(*delay_func)(1000*(305)); |
1281 | |
1282 | return; |
1283 | } |