Bug Summary

File:dev/sdmmc/sdhc.c
Warning:line 854, column 9
Although the value stored to 'state' is used in the enclosing expression, the value is never actually read from 'state'

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name sdhc.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/sdmmc/sdhc.c
1/* $OpenBSD: sdhc.c,v 1.76 2023/10/01 08:56:24 kettenis Exp $ */
2
3/*
4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * SD Host Controller driver based on the SD Host Controller Standard
21 * Simplified Specification Version 1.00 (www.sdcard.org).
22 */
23
24#include <sys/param.h>
25#include <sys/device.h>
26#include <sys/kernel.h>
27#include <sys/malloc.h>
28#include <sys/proc.h>
29#include <sys/systm.h>
30#include <sys/time.h>
31
32#include <dev/sdmmc/sdhcreg.h>
33#include <dev/sdmmc/sdhcvar.h>
34#include <dev/sdmmc/sdmmcchip.h>
35#include <dev/sdmmc/sdmmcreg.h>
36#include <dev/sdmmc/sdmmcvar.h>
37#include <dev/sdmmc/sdmmc_ioreg.h>
38
39/* Timeouts in seconds */
40#define SDHC_COMMAND_TIMEOUT1 1
41#define SDHC_BUFFER_TIMEOUT1 1
42#define SDHC_TRANSFER_TIMEOUT1 1
43#define SDHC_DMA_TIMEOUT3 3
44
45struct sdhc_host {
46 struct sdhc_softc *sc; /* host controller device */
47 struct device *sdmmc; /* generic SD/MMC device */
48 bus_space_tag_t iot; /* host register set tag */
49 bus_space_handle_t ioh; /* host register set handle */
50 u_int16_t version; /* specification version */
51 u_int clkbase; /* base clock frequency in KHz */
52 int maxblklen; /* maximum block length */
53 int flags; /* flags for this host */
54 u_int32_t ocr; /* OCR value from capabilities */
55 u_int8_t regs[14]; /* host controller state */
56 u_int16_t intr_status; /* soft interrupt status */
57 u_int16_t intr_error_status; /* soft error status */
58
59 bus_dmamap_t adma_map;
60 bus_dma_segment_t adma_segs[1];
61 caddr_t adma2;
62
63 uint16_t block_size;
64 uint16_t block_count;
65 uint16_t transfer_mode;
66};
67
68/* flag values */
69#define SHF_USE_DMA0x0001 0x0001
70#define SHF_USE_DMA640x0002 0x0002
71#define SHF_USE_32BIT_ACCESS0x0004 0x0004
72
73#define HREAD1(hp, reg)(sdhc_read_1((hp), (reg))) \
74 (sdhc_read_1((hp), (reg)))
75#define HREAD2(hp, reg)(sdhc_read_2((hp), (reg))) \
76 (sdhc_read_2((hp), (reg)))
77#define HREAD4(hp, reg)((((hp)->iot)->read_4(((hp)->ioh), ((reg))))) \
78 (bus_space_read_4((hp)->iot, (hp)->ioh, (reg))(((hp)->iot)->read_4(((hp)->ioh), ((reg)))))
79#define HWRITE1(hp, reg, val)sdhc_write_1((hp), (reg), (val)) \
80 sdhc_write_1((hp), (reg), (val))
81#define HWRITE2(hp, reg, val)sdhc_write_2((hp), (reg), (val)) \
82 sdhc_write_2((hp), (reg), (val))
83#define HWRITE4(hp, reg, val)(((hp)->iot)->write_4(((hp)->ioh), ((reg)), ((val)))
) \
84 bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))(((hp)->iot)->write_4(((hp)->ioh), ((reg)), ((val)))
)
85#define HCLR1(hp, reg, bits)sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
& ~(bits))) \
86 HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
& ~(bits)))
87#define HCLR2(hp, reg, bits)sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
& ~(bits))) \
88 HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
& ~(bits)))
89#define HSET1(hp, reg, bits)sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
| (bits))) \
90 HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))sdhc_write_1(((hp)), ((reg)), ((sdhc_read_1(((hp)), ((reg))))
| (bits)))
91#define HSET2(hp, reg, bits)sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
| (bits))) \
92 HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))sdhc_write_2(((hp)), ((reg)), ((sdhc_read_2(((hp)), ((reg))))
| (bits)))
93
94int sdhc_host_reset(sdmmc_chipset_handle_t);
95u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t);
96int sdhc_host_maxblklen(sdmmc_chipset_handle_t);
97int sdhc_card_detect(sdmmc_chipset_handle_t);
98int sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t);
99int sdhc_bus_clock(sdmmc_chipset_handle_t, int, int);
100int sdhc_bus_width(sdmmc_chipset_handle_t, int);
101void sdhc_card_intr_mask(sdmmc_chipset_handle_t, int);
102void sdhc_card_intr_ack(sdmmc_chipset_handle_t);
103int sdhc_signal_voltage(sdmmc_chipset_handle_t, int);
104void sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *);
105int sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
106int sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t);
107int sdhc_soft_reset(struct sdhc_host *, int);
108int sdhc_wait_intr_cold(struct sdhc_host *, int, int);
109int sdhc_wait_intr(struct sdhc_host *, int, int);
110void sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
111void sdhc_read_data(struct sdhc_host *, u_char *, int);
112void sdhc_write_data(struct sdhc_host *, u_char *, int);
113int sdhc_hibernate_init(sdmmc_chipset_handle_t, void *);
114
115#ifdef SDHC_DEBUG
116int sdhcdebug = 0;
117#define DPRINTF(n,s)do {} while(0) do { if ((n) <= sdhcdebug) printf s; } while (0)
118void sdhc_dump_regs(struct sdhc_host *);
119#else
120#define DPRINTF(n,s)do {} while(0) do {} while(0)
121#endif
122
123struct sdmmc_chip_functions sdhc_functions = {
124 .host_reset = sdhc_host_reset,
125 .host_ocr = sdhc_host_ocr,
126 .host_maxblklen = sdhc_host_maxblklen,
127 .card_detect = sdhc_card_detect,
128 .bus_power = sdhc_bus_power,
129 .bus_clock = sdhc_bus_clock,
130 .bus_width = sdhc_bus_width,
131 .exec_command = sdhc_exec_command,
132 .card_intr_mask = sdhc_card_intr_mask,
133 .card_intr_ack = sdhc_card_intr_ack,
134 .signal_voltage = sdhc_signal_voltage,
135 .hibernate_init = sdhc_hibernate_init,
136};
137
138struct cfdriver sdhc_cd = {
139 NULL((void *)0), "sdhc", DV_DULL
140};
141
142/*
143 * Some controllers live on a bus that only allows 32-bit
144 * transactions. In that case we use a RMW cycle for 8-bit and 16-bit
145 * register writes. However that doesn't work for the Transfer Mode
146 * register as this register lives in the same 32-bit word as the
147 * Command register and writing the Command register triggers SD
148 * command generation. We avoid this issue by using a shadow variable
149 * for the Transfer Mode register that we write out when we write the
150 * Command register.
151 *
152 * The Arasan controller integrated on the Broadcom SoCs
153 * used in the Raspberry Pi has an interesting bug where writing the
154 * same 32-bit register twice doesn't work. This means that we lose
155 * writes to the Block Sine and/or Block Count register. We work
156 * around that issue by using shadow variables as well.
157 */
158
159uint8_t
160sdhc_read_1(struct sdhc_host *hp, bus_size_t offset)
161{
162 uint32_t reg;
163
164 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
165 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3)((hp->iot)->read_4((hp->ioh), (offset & ~3)));
166 return (reg >> ((offset & 3) * 8)) & 0xff;
167 }
168
169 return bus_space_read_1(hp->iot, hp->ioh, offset)((hp->iot)->read_1((hp->ioh), (offset)));
170}
171
172uint16_t
173sdhc_read_2(struct sdhc_host *hp, bus_size_t offset)
174{
175 uint32_t reg;
176
177 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
178 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2)((hp->iot)->read_4((hp->ioh), (offset & ~2)));
179 return (reg >> ((offset & 2) * 8)) & 0xffff;
180 }
181
182 return bus_space_read_2(hp->iot, hp->ioh, offset)((hp->iot)->read_2((hp->ioh), (offset)));
183}
184
185void
186sdhc_write_1(struct sdhc_host *hp, bus_size_t offset, uint8_t value)
187{
188 uint32_t reg;
189
190 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
191 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~3)((hp->iot)->read_4((hp->ioh), (offset & ~3)));
192 reg &= ~(0xff << ((offset & 3) * 8));
193 reg |= (value << ((offset & 3) * 8));
194 bus_space_write_4(hp->iot, hp->ioh, offset & ~3, reg)((hp->iot)->write_4((hp->ioh), (offset & ~3), (reg
)));
195 return;
196 }
197
198 bus_space_write_1(hp->iot, hp->ioh, offset, value)((hp->iot)->write_1((hp->ioh), (offset), (value)));
199}
200
201void
202sdhc_write_2(struct sdhc_host *hp, bus_size_t offset, uint16_t value)
203{
204 uint32_t reg;
205
206 if (hp->flags & SHF_USE_32BIT_ACCESS0x0004) {
207 switch (offset) {
208 case SDHC_BLOCK_SIZE0x04:
209 hp->block_size = value;
210 return;
211 case SDHC_BLOCK_COUNT0x06:
212 hp->block_count = value;
213 return;
214 case SDHC_TRANSFER_MODE0x0c:
215 hp->transfer_mode = value;
216 return;
217 case SDHC_COMMAND0x0e:
218 bus_space_write_4(hp->iot, hp->ioh, SDHC_BLOCK_SIZE,((hp->iot)->write_4((hp->ioh), (0x04), ((hp->block_count
<< 16) | hp->block_size)))
219 (hp->block_count << 16) | hp->block_size)((hp->iot)->write_4((hp->ioh), (0x04), ((hp->block_count
<< 16) | hp->block_size)));
220 bus_space_write_4(hp->iot, hp->ioh, SDHC_TRANSFER_MODE,((hp->iot)->write_4((hp->ioh), (0x0c), ((value <<
16) | hp->transfer_mode)))
221 (value << 16) | hp->transfer_mode)((hp->iot)->write_4((hp->ioh), (0x0c), ((value <<
16) | hp->transfer_mode)));
222 return;
223 }
224
225 reg = bus_space_read_4(hp->iot, hp->ioh, offset & ~2)((hp->iot)->read_4((hp->ioh), (offset & ~2)));
226 reg &= ~(0xffff << ((offset & 2) * 8));
227 reg |= (value << ((offset & 2) * 8));
228 bus_space_write_4(hp->iot, hp->ioh, offset & ~2, reg)((hp->iot)->write_4((hp->ioh), (offset & ~2), (reg
)));
229 return;
230 }
231
232 bus_space_write_2(hp->iot, hp->ioh, offset, value)((hp->iot)->write_2((hp->ioh), (offset), (value)));
233}
234
235/*
236 * Called by attachment driver. For each SD card slot there is one SD
237 * host controller standard register set. (1.3)
238 */
239int
240sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
241 bus_space_handle_t ioh, bus_size_t iosize, int usedma, uint64_t capmask,
242 uint64_t capset)
243{
244 struct sdmmcbus_attach_args saa;
245 struct sdhc_host *hp;
246 uint32_t caps;
247 int major, minor;
248 int error = 1;
249 int max_clock;
250
251 /* Allocate one more host structure. */
252 sc->sc_nhosts++;
253 hp = malloc(sizeof(*hp), M_DEVBUF2, M_WAITOK0x0001 | M_ZERO0x0008);
254 sc->sc_host[sc->sc_nhosts - 1] = hp;
255
256 if (ISSET(sc->sc_flags, SDHC_F_32BIT_ACCESS)((sc->sc_flags) & ((1 << 2))))
257 SET(hp->flags, SHF_USE_32BIT_ACCESS)((hp->flags) |= (0x0004));
258
259 /* Fill in the new host structure. */
260 hp->sc = sc;
261 hp->iot = iot;
262 hp->ioh = ioh;
263
264 /* Store specification version. */
265 hp->version = HREAD2(hp, SDHC_HOST_CTL_VERSION)(sdhc_read_2((hp), (0xfe)));
266
267 /*
268 * Reset the host controller and enable interrupts.
269 */
270 (void)sdhc_host_reset(hp);
271
272 /* Determine host capabilities. */
273 caps = HREAD4(hp, SDHC_CAPABILITIES)((((hp)->iot)->read_4(((hp)->ioh), ((0x40)))));
274 caps &= ~capmask;
275 caps |= capset;
276
277 /* Use DMA if the host system and the controller support it. */
278 if (usedma && ISSET(caps, SDHC_ADMA2_SUPP)((caps) & ((1<<19)))) {
279 SET(hp->flags, SHF_USE_DMA)((hp->flags) |= (0x0001));
280 if (ISSET(caps, SDHC_64BIT_DMA_SUPP)((caps) & ((1<<28))))
281 SET(hp->flags, SHF_USE_DMA64)((hp->flags) |= (0x0002));
282 }
283
284 /*
285 * Determine the base clock frequency. (2.2.24)
286 */
287 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
288 /* SDHC 3.0 supports 10-255 MHz. */
289 max_clock = 255000;
290 if (SDHC_BASE_FREQ_KHZ_V3(caps)((((caps) >> 8) & 0xff) * 1000) != 0)
291 hp->clkbase = SDHC_BASE_FREQ_KHZ_V3(caps)((((caps) >> 8) & 0xff) * 1000);
292 } else {
293 /* SDHC 1.0/2.0 supports only 10-63 MHz. */
294 max_clock = 63000;
295 if (SDHC_BASE_FREQ_KHZ(caps)((((caps) >> 8) & 0x3f) * 1000) != 0)
296 hp->clkbase = SDHC_BASE_FREQ_KHZ(caps)((((caps) >> 8) & 0x3f) * 1000);
297 }
298 if (hp->clkbase == 0) {
299 /* Make sure we can clock down to 400 kHz. */
300 max_clock = 400 * SDHC_SDCLK_DIV_MAX_V32046;
301 hp->clkbase = sc->sc_clkbase;
302 }
303 if (hp->clkbase == 0) {
304 /* The attachment driver must tell us. */
305 printf("%s: base clock frequency unknown\n",
306 sc->sc_dev.dv_xname);
307 goto err;
308 } else if (hp->clkbase < 10000 || hp->clkbase > max_clock) {
309 printf("%s: base clock frequency out of range: %u MHz\n",
310 sc->sc_dev.dv_xname, hp->clkbase / 1000);
311 goto err;
312 }
313
314 switch (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff)) {
315 case SDHC_SPEC_VERS_4_100x04:
316 major = 4, minor = 10;
317 break;
318 case SDHC_SPEC_VERS_4_200x05:
319 major = 4, minor = 20;
320 break;
321 default:
322 major = SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) + 1, minor = 0;
323 break;
324 }
325
326 printf("%s: SDHC %d.%02d, %d MHz base clock\n", DEVNAME(sc)((sc)->sc_dev.dv_xname),
327 major, minor, hp->clkbase / 1000);
328
329 /*
330 * XXX Set the data timeout counter value according to
331 * capabilities. (2.2.15)
332 */
333
334 /*
335 * Determine SD bus voltage levels supported by the controller.
336 */
337 if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V)((caps) & ((1<<26))))
338 SET(hp->ocr, MMC_OCR_1_65V_1_95V)((hp->ocr) |= ((1<<7)));
339 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V)((caps) & ((1<<25))))
340 SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V)((hp->ocr) |= ((1<<17) | (1<<18)));
341 if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V)((caps) & ((1<<24))))
342 SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V)((hp->ocr) |= ((1<<20) | (1<<21)));
343
344 /*
345 * Determine the maximum block length supported by the host
346 * controller. (2.2.24)
347 */
348 switch((caps >> SDHC_MAX_BLK_LEN_SHIFT16) & SDHC_MAX_BLK_LEN_MASK0x3) {
349 case SDHC_MAX_BLK_LEN_5120:
350 hp->maxblklen = 512;
351 break;
352 case SDHC_MAX_BLK_LEN_10241:
353 hp->maxblklen = 1024;
354 break;
355 case SDHC_MAX_BLK_LEN_20482:
356 hp->maxblklen = 2048;
357 break;
358 default:
359 hp->maxblklen = 1;
360 break;
361 }
362
363 if (ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001))) {
364 int rseg;
365
366 /* Allocate ADMA2 descriptor memory */
367 error = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, PAGE_SIZE,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((1 <<
12)), ((1 << 12)), ((1 << 12)), (hp->adma_segs
), (1), (&rseg), (0x0000 | 0x1000))
368 PAGE_SIZE, hp->adma_segs, 1, &rseg,(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((1 <<
12)), ((1 << 12)), ((1 << 12)), (hp->adma_segs
), (1), (&rseg), (0x0000 | 0x1000))
369 BUS_DMA_WAITOK | BUS_DMA_ZERO)(*(sc->sc_dmat)->_dmamem_alloc)((sc->sc_dmat), ((1 <<
12)), ((1 << 12)), ((1 << 12)), (hp->adma_segs
), (1), (&rseg), (0x0000 | 0x1000));
370 if (error)
371 goto adma_done;
372 error = bus_dmamem_map(sc->sc_dmat, hp->adma_segs, rseg,(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (hp->
adma_segs), (rseg), ((1 << 12)), (&hp->adma2), (
0x0000 | 0x0004))
373 PAGE_SIZE, &hp->adma2, BUS_DMA_WAITOK | BUS_DMA_COHERENT)(*(sc->sc_dmat)->_dmamem_map)((sc->sc_dmat), (hp->
adma_segs), (rseg), ((1 << 12)), (&hp->adma2), (
0x0000 | 0x0004));
374 if (error) {
375 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (hp->
adma_segs), (rseg));
376 goto adma_done;
377 }
378 error = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE,(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
12)), (1), ((1 << 12)), (0), (0x0000), (&hp->adma_map
))
379 0, BUS_DMA_WAITOK, &hp->adma_map)(*(sc->sc_dmat)->_dmamap_create)((sc->sc_dmat), ((1 <<
12)), (1), ((1 << 12)), (0), (0x0000), (&hp->adma_map
));
380 if (error) {
381 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (hp->
adma2), ((1 << 12)));
382 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (hp->
adma_segs), (rseg));
383 goto adma_done;
384 }
385 error = bus_dmamap_load(sc->sc_dmat, hp->adma_map,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (hp->
adma_map), (hp->adma2), ((1 << 12)), (((void *)0)), (
0x0000 | 0x0400))
386 hp->adma2, PAGE_SIZE, NULL,(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (hp->
adma_map), (hp->adma2), ((1 << 12)), (((void *)0)), (
0x0000 | 0x0400))
387 BUS_DMA_WAITOK | BUS_DMA_WRITE)(*(sc->sc_dmat)->_dmamap_load)((sc->sc_dmat), (hp->
adma_map), (hp->adma2), ((1 << 12)), (((void *)0)), (
0x0000 | 0x0400));
388 if (error) {
389 bus_dmamap_destroy(sc->sc_dmat, hp->adma_map)(*(sc->sc_dmat)->_dmamap_destroy)((sc->sc_dmat), (hp
->adma_map));
390 bus_dmamem_unmap(sc->sc_dmat, hp->adma2, PAGE_SIZE)(*(sc->sc_dmat)->_dmamem_unmap)((sc->sc_dmat), (hp->
adma2), ((1 << 12)));
391 bus_dmamem_free(sc->sc_dmat, hp->adma_segs, rseg)(*(sc->sc_dmat)->_dmamem_free)((sc->sc_dmat), (hp->
adma_segs), (rseg));
392 goto adma_done;
393 }
394
395 adma_done:
396 if (error) {
397 printf("%s: can't allocate DMA descriptor table\n",
398 DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname));
399 CLR(hp->flags, SHF_USE_DMA)((hp->flags) &= ~(0x0001));
400 }
401 }
402
403 /*
404 * Attach the generic SD/MMC bus driver. (The bus driver must
405 * not invoke any chipset functions before it is attached.)
406 */
407 bzero(&saa, sizeof(saa))__builtin_bzero((&saa), (sizeof(saa)));
408 saa.saa_busname = "sdmmc";
409 saa.sct = &sdhc_functions;
410 saa.sch = hp;
411 saa.caps = SMC_CAPS_4BIT_MODE0x0002;
412 saa.dmat = sc->sc_dmat;
413 saa.dma_boundary = sc->sc_dma_boundary;
414 if (ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001)))
415 saa.caps |= SMC_CAPS_DMA0x0004;
416
417 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)((caps) & ((1<<21))))
418 saa.caps |= SMC_CAPS_SD_HIGHSPEED0x0100;
419 if (ISSET(caps, SDHC_HIGH_SPEED_SUPP)((caps) & ((1<<21))))
420 saa.caps |= SMC_CAPS_MMC_HIGHSPEED0x0200;
421
422 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
423 uint32_t caps2 = HREAD4(hp, SDHC_CAPABILITIES2)((((hp)->iot)->read_4(((hp)->ioh), ((0x44)))));
424 caps2 &= ~(capmask >> 32);
425 caps2 |= capset >> 32;
426
427 if (ISSET(caps, SDHC_8BIT_MODE_SUPP)((caps) & ((1<<18))))
428 saa.caps |= SMC_CAPS_8BIT_MODE0x0040;
429
430 if (ISSET(caps2, SDHC_DDR50_SUPP)((caps2) & ((1<<2))))
431 saa.caps |= SMC_CAPS_MMC_DDR520x2000;
432 }
433
434 if (ISSET(sc->sc_flags, SDHC_F_NONREMOVABLE)((sc->sc_flags) & ((1 << 1))))
435 saa.caps |= SMC_CAPS_NONREMOVABLE0x10000;
436
437 hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL)config_found_sm((&sc->sc_dev), (&saa), (((void *)0
)), ((void *)0));
438 if (hp->sdmmc == NULL((void *)0)) {
439 error = 0;
440 goto err;
441 }
442
443 return 0;
444
445err:
446 free(hp, M_DEVBUF2, sizeof *hp);
447 sc->sc_host[sc->sc_nhosts - 1] = NULL((void *)0);
448 sc->sc_nhosts--;
449 return (error);
450}
451
452int
453sdhc_activate(struct device *self, int act)
454{
455 struct sdhc_softc *sc = (struct sdhc_softc *)self;
456 struct sdhc_host *hp;
457 int n, i, rv = 0;
458
459 switch (act) {
460 case DVACT_SUSPEND3:
461 rv = config_activate_children(self, act);
462
463 /* Save the host controller state. */
464 for (n = 0; n < sc->sc_nhosts; n++) {
465 hp = sc->sc_host[n];
466 for (i = 0; i < sizeof hp->regs; i++)
467 hp->regs[i] = HREAD1(hp, i)(sdhc_read_1((hp), (i)));
468 }
469 break;
470 case DVACT_RESUME4:
471 /* Restore the host controller state. */
472 for (n = 0; n < sc->sc_nhosts; n++) {
473 hp = sc->sc_host[n];
474 (void)sdhc_host_reset(hp);
475 for (i = 0; i < sizeof hp->regs; i++)
476 HWRITE1(hp, i, hp->regs[i])sdhc_write_1((hp), (i), (hp->regs[i]));
477 }
478 rv = config_activate_children(self, act);
479 break;
480 case DVACT_POWERDOWN6:
481 rv = config_activate_children(self, act);
482 sdhc_shutdown(self);
483 break;
484 default:
485 rv = config_activate_children(self, act);
486 break;
487 }
488 return (rv);
489}
490
491/*
492 * Shutdown hook established by or called from attachment driver.
493 */
494void
495sdhc_shutdown(void *arg)
496{
497 struct sdhc_softc *sc = arg;
498 struct sdhc_host *hp;
499 int i;
500
501 /* XXX chip locks up if we don't disable it before reboot. */
502 for (i = 0; i < sc->sc_nhosts; i++) {
503 hp = sc->sc_host[i];
504 (void)sdhc_host_reset(hp);
505 }
506}
507
508/*
509 * Reset the host controller. Called during initialization, when
510 * cards are removed, upon resume, and during error recovery.
511 */
512int
513sdhc_host_reset(sdmmc_chipset_handle_t sch)
514{
515 struct sdhc_host *hp = sch;
516 u_int16_t imask;
517 int error;
518 int s;
519
520 s = splsdmmc()splraise(0x3);
521
522 /* Disable all interrupts. */
523 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0)sdhc_write_2((hp), (0x38), (0));
524
525 /*
526 * Reset the entire host controller and wait up to 100ms for
527 * the controller to clear the reset bit.
528 */
529 if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL(1<<0))) != 0) {
530 splx(s)spllower(s);
531 return (error);
532 }
533
534 /* Set data timeout counter value to max for now. */
535 HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX)sdhc_write_1((hp), (0x2e), (0x0e));
536
537 /* Enable interrupts. */
538 imask = SDHC_CARD_REMOVAL(1<<7) | SDHC_CARD_INSERTION(1<<6) |
539 SDHC_BUFFER_READ_READY(1<<5) | SDHC_BUFFER_WRITE_READY(1<<4) |
540 SDHC_DMA_INTERRUPT(1<<3) | SDHC_BLOCK_GAP_EVENT(1<<2) |
541 SDHC_TRANSFER_COMPLETE(1<<1) | SDHC_COMMAND_COMPLETE(1<<0);
542
543 HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask)sdhc_write_2((hp), (0x34), (imask));
544 HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK)sdhc_write_2((hp), (0x36), (0x03ff));
545 HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask)sdhc_write_2((hp), (0x38), (imask));
546 HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK)sdhc_write_2((hp), (0x3a), (0x03ff));
547
548 splx(s)spllower(s);
549 return 0;
550}
551
552u_int32_t
553sdhc_host_ocr(sdmmc_chipset_handle_t sch)
554{
555 struct sdhc_host *hp = sch;
556 return hp->ocr;
557}
558
559int
560sdhc_host_maxblklen(sdmmc_chipset_handle_t sch)
561{
562 struct sdhc_host *hp = sch;
563 return hp->maxblklen;
564}
565
566/*
567 * Return non-zero if the card is currently inserted.
568 */
569int
570sdhc_card_detect(sdmmc_chipset_handle_t sch)
571{
572 struct sdhc_host *hp = sch;
573
574 if (hp->sc->sc_card_detect)
575 return hp->sc->sc_card_detect(hp->sc);
576
577 return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED)((((((hp)->iot)->read_4(((hp)->ioh), ((0x24)))))) &
((1<<16))) ?
578 1 : 0;
579}
580
581/*
582 * Set or change SD bus voltage and enable or disable SD bus power.
583 * Return zero on success.
584 */
585int
586sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr)
587{
588 struct sdhc_host *hp = sch;
589 u_int8_t vdd;
590 int s;
591
592 s = splsdmmc()splraise(0x3);
593
594 /*
595 * Disable bus power before voltage change.
596 */
597 if (!(hp->sc->sc_flags & SDHC_F_NOPWR0(1 << 0)))
598 HWRITE1(hp, SDHC_POWER_CTL, 0)sdhc_write_1((hp), (0x29), (0));
599
600 /* If power is disabled, reset the host and return now. */
601 if (ocr == 0) {
602 splx(s)spllower(s);
603 (void)sdhc_host_reset(hp);
604 return 0;
605 }
606
607 /*
608 * Select the maximum voltage according to capabilities.
609 */
610 ocr &= hp->ocr;
611 if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V)((ocr) & ((1<<20)|(1<<21))))
612 vdd = SDHC_VOLTAGE_3_3V0x07;
613 else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V)((ocr) & ((1<<17)|(1<<18))))
614 vdd = SDHC_VOLTAGE_3_0V0x06;
615 else if (ISSET(ocr, MMC_OCR_1_65V_1_95V)((ocr) & ((1<<7))))
616 vdd = SDHC_VOLTAGE_1_8V0x05;
617 else {
618 /* Unsupported voltage level requested. */
619 splx(s)spllower(s);
620 return EINVAL22;
621 }
622
623 /*
624 * Enable bus power. Wait at least 1 ms (or 74 clocks) plus
625 * voltage ramp until power rises.
626 */
627 HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) |sdhc_write_1((hp), (0x29), ((vdd << 1) | (1<<0)))
628 SDHC_BUS_POWER)sdhc_write_1((hp), (0x29), ((vdd << 1) | (1<<0)));
629 sdmmc_delay(10000);
630
631 /*
632 * The host system may not power the bus due to battery low,
633 * etc. In that case, the host controller should clear the
634 * bus power bit.
635 */
636 if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)(((sdhc_read_1((hp), (0x29)))) & ((1<<0)))) {
637 splx(s)spllower(s);
638 return ENXIO6;
639 }
640
641 splx(s)spllower(s);
642 return 0;
643}
644
645/*
646 * Return the smallest possible base clock frequency divisor value
647 * for the CLOCK_CTL register to produce `freq' (KHz).
648 */
649static int
650sdhc_clock_divisor(struct sdhc_host *hp, u_int freq)
651{
652 int div;
653
654 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
655 if (hp->clkbase <= freq)
656 return 0;
657
658 for (div = 2; div <= SDHC_SDCLK_DIV_MAX_V32046; div += 2)
659 if ((hp->clkbase / div) <= freq)
660 return (div / 2);
661 } else {
662 for (div = 1; div <= SDHC_SDCLK_DIV_MAX256; div *= 2)
663 if ((hp->clkbase / div) <= freq)
664 return (div / 2);
665 }
666
667 /* No divisor found. */
668 return -1;
669}
670
671/*
672 * Set or change SDCLK frequency or disable the SD clock.
673 * Return zero on success.
674 */
675int
676sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing)
677{
678 struct sdhc_host *hp = sch;
679 struct sdhc_softc *sc = hp->sc;
680 int s;
681 int div;
682 int sdclk;
683 int timo;
684 int error = 0;
685
686 s = splsdmmc()splraise(0x3);
687
688 if (hp->sc->sc_bus_clock_pre)
689 hp->sc->sc_bus_clock_pre(hp->sc, freq, timing);
690
691#ifdef DIAGNOSTIC1
692 /* Must not stop the clock if commands are in progress. */
693 if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK)((((((hp)->iot)->read_4(((hp)->ioh), ((0x24)))))) &
(0x0003)) &&
694 sdhc_card_detect(hp))
695 printf("sdhc_sdclk_frequency_select: command in progress\n");
696#endif
697
698 /*
699 * Stop SD clock before changing the frequency.
700 */
701 HWRITE2(hp, SDHC_CLOCK_CTL, 0)sdhc_write_2((hp), (0x2c), (0));
702 if (freq == SDMMC_SDCLK_OFF0)
703 goto ret;
704
705 if (!ISSET(sc->sc_flags, SDHC_F_NO_HS_BIT)((sc->sc_flags) & ((1 << 3)))) {
706 if (timing == SDMMC_TIMING_LEGACY0)
707 HCLR1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((1<<2))));
708 else
709 HSET1(hp, SDHC_HOST_CTL, SDHC_HIGH_SPEED)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((1<<2))));
710 }
711
712 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
713 switch (timing) {
714 case SDMMC_TIMING_MMC_DDR524:
715 HCLR2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_MASK)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) & ~(0x7)));
716 HSET2(hp, SDHC_HOST_CTL2, SDHC_UHS_MODE_SELECT_DDR50)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) | (4)));
717 break;
718 }
719 }
720
721 /*
722 * Set the minimum base clock frequency divisor.
723 */
724 if ((div = sdhc_clock_divisor(hp, freq)) < 0) {
725 /* Invalid base clock frequency or `freq' value. */
726 error = EINVAL22;
727 goto ret;
728 }
729 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32)
730 sdclk = SDHC_SDCLK_DIV_V3(div)((((div) & 0xff) << 8) | (((div) & 0x300) >>
2));
731 else
732 sdclk = SDHC_SDCLK_DIV(div)(((div) & 0xff) << 8);
733 HWRITE2(hp, SDHC_CLOCK_CTL, sdclk)sdhc_write_2((hp), (0x2c), (sdclk));
734
735 /*
736 * Start internal clock. Wait 10ms for stabilization.
737 */
738 HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE)sdhc_write_2(((hp)), ((0x2c)), ((sdhc_read_2(((hp)), ((0x2c))
)) | ((1<<0))));
739 for (timo = 1000; timo > 0; timo--) {
740 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE)(((sdhc_read_2((hp), (0x2c)))) & ((1<<1))))
741 break;
742 sdmmc_delay(10);
743 }
744 if (timo == 0) {
745 error = ETIMEDOUT60;
746 goto ret;
747 }
748
749 /*
750 * Enable SD clock.
751 */
752 HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE)sdhc_write_2(((hp)), ((0x2c)), ((sdhc_read_2(((hp)), ((0x2c))
)) | ((1<<2))));
753
754 if (hp->sc->sc_bus_clock_post)
755 hp->sc->sc_bus_clock_post(hp->sc, freq, timing);
756
757ret:
758 splx(s)spllower(s);
759 return error;
760}
761
762int
763sdhc_bus_width(sdmmc_chipset_handle_t sch, int width)
764{
765 struct sdhc_host *hp = (struct sdhc_host *)sch;
766 int reg;
767 int s;
768
769 if (width != 1 && width != 4 && width != 8)
770 return EINVAL22;
771
772 s = splsdmmc()splraise(0x3);
773
774 reg = HREAD1(hp, SDHC_HOST_CTL)(sdhc_read_1((hp), (0x28)));
775 reg &= ~SDHC_4BIT_MODE(1<<1);
776 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) >= SDHC_SPEC_V32) {
777 reg &= ~SDHC_8BIT_MODE(1<<5);
778 }
779 if (width == 4) {
780 reg |= SDHC_4BIT_MODE(1<<1);
781 } else if (width == 8) {
782 KASSERT(SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3)(((((hp->version) >> 0) & 0xff) >= 2) ? (void
)0 : __assert("diagnostic ", "/usr/src/sys/dev/sdmmc/sdhc.c",
782, "SDHC_SPEC_VERSION(hp->version) >= SDHC_SPEC_V3")
);
783 reg |= SDHC_8BIT_MODE(1<<5);
784 }
785 HWRITE1(hp, SDHC_HOST_CTL, reg)sdhc_write_1((hp), (0x28), (reg));
786
787 splx(s)spllower(s);
788
789 return 0;
790}
791
792void
793sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)
794{
795 struct sdhc_host *hp = sch;
796
797 if (enable) {
798 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))));
799 HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x38)), ((sdhc_read_2(((hp)), ((0x38))
)) | ((1<<8))));
800 } else {
801 HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x38)), ((sdhc_read_2(((hp)), ((0x38))
)) & ~((1<<8))));
802 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) & ~((1<<8))));
803 }
804}
805
806void
807sdhc_card_intr_ack(sdmmc_chipset_handle_t sch)
808{
809 struct sdhc_host *hp = sch;
810
811 HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))));
812}
813
814int
815sdhc_signal_voltage(sdmmc_chipset_handle_t sch, int signal_voltage)
816{
817 struct sdhc_host *hp = sch;
818
819 if (hp->sc->sc_signal_voltage)
820 return hp->sc->sc_signal_voltage(hp->sc, signal_voltage);
821
822 if (SDHC_SPEC_VERSION(hp->version)(((hp->version) >> 0) & 0xff) < SDHC_SPEC_V32)
823 return EINVAL22;
824
825 switch (signal_voltage) {
826 case SDMMC_SIGNAL_VOLTAGE_1801:
827 HSET2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) | ((1<<3))));
828 break;
829 case SDMMC_SIGNAL_VOLTAGE_3300:
830 HCLR2(hp, SDHC_HOST_CTL2, SDHC_1_8V_SIGNAL_EN)sdhc_write_2(((hp)), ((0x3e)), ((sdhc_read_2(((hp)), ((0x3e))
)) & ~((1<<3))));
831 break;
832 default:
833 return EINVAL22;
834 }
835
836 /* Regulator output shall be stable within 5 ms. */
837 sdmmc_delay(5000);
838
839 /* Host controller clears this bit if 1.8V signalling fails. */
840 if (signal_voltage == SDMMC_SIGNAL_VOLTAGE_1801 &&
841 !ISSET(HREAD2(hp, SDHC_HOST_CTL2), SDHC_1_8V_SIGNAL_EN)(((sdhc_read_2((hp), (0x3e)))) & ((1<<3))))
842 return EIO5;
843
844 return 0;
845}
846
847int
848sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value)
849{
850 u_int32_t state;
851 int timeout;
852
853 for (timeout = 10; timeout > 0; timeout--) {
854 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)((((hp)->iot)->read_4(((hp)->ioh), ((0x24)))))) & mask)
Although the value stored to 'state' is used in the enclosing expression, the value is never actually read from 'state'
855 == value)
856 return 0;
857 sdmmc_delay(10000);
858 }
859 DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", DEVNAME(hp->sc),do {} while(0)
860 value, state, SDHC_PRESENT_STATE_BITS))do {} while(0);
861 return ETIMEDOUT60;
862}
863
864void
865sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
866{
867 struct sdhc_host *hp = sch;
868 int error;
869
870 /*
871 * Start the MMC command, or mark `cmd' as failed and return.
872 */
873 error = sdhc_start_command(hp, cmd);
874 if (error != 0) {
875 cmd->c_error = error;
876 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
877 return;
878 }
879
880 /*
881 * Wait until the command phase is done, or until the command
882 * is marked done for any other reason.
883 */
884 if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE(1<<0),
885 SDHC_COMMAND_TIMEOUT1)) {
886 cmd->c_error = ETIMEDOUT60;
887 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
888 return;
889 }
890
891 /*
892 * The host controller removes bits [0:7] from the response
893 * data (CRC) and we pass the data up unchanged to the bus
894 * driver (without padding).
895 */
896 if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)((cmd->c_flags) & (0x1000))) {
897 if (ISSET(cmd->c_flags, SCF_RSP_136)((cmd->c_flags) & (0x0200))) {
898 u_char *p = (u_char *)cmd->c_resp;
899 int i;
900
901 for (i = 0; i < 15; i++)
902 *p++ = HREAD1(hp, SDHC_RESPONSE + i)(sdhc_read_1((hp), (0x10 + i)));
903 } else
904 cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE)((((hp)->iot)->read_4(((hp)->ioh), ((0x10)))));
905 }
906
907 /*
908 * If the command has data to transfer in any direction,
909 * execute the transfer now.
910 */
911 if (cmd->c_error == 0 && cmd->c_data != NULL((void *)0))
912 sdhc_transfer_data(hp, cmd);
913
914 /* Turn off the LED. */
915 HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((1<<0))));
916
917 DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n",do {} while(0)
918 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_flags, cmd->c_error))do {} while(0);
919 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
920}
921
922int
923sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
924{
925 struct sdhc_adma2_descriptor32 *desc32 = (void *)hp->adma2;
926 struct sdhc_adma2_descriptor64 *desc64 = (void *)hp->adma2;
927 struct sdhc_softc *sc = hp->sc;
928 u_int16_t blksize = 0;
929 u_int16_t blkcount = 0;
930 u_int16_t mode;
931 u_int16_t command;
932 int error;
933 int seg;
934 int s;
935
936 DPRINTF(1,("%s: start cmd %u arg=%#x data=%p dlen=%d flags=%#x\n",do {} while(0)
937 DEVNAME(hp->sc), cmd->c_opcode, cmd->c_arg, cmd->c_data,do {} while(0)
938 cmd->c_datalen, cmd->c_flags))do {} while(0);
939
940 /*
941 * The maximum block length for commands should be the minimum
942 * of the host buffer size and the card buffer size. (1.7.2)
943 */
944
945 /* Fragment the data into proper blocks. */
946 if (cmd->c_datalen > 0) {
947 blksize = MIN(cmd->c_datalen, cmd->c_blklen)(((cmd->c_datalen)<(cmd->c_blklen))?(cmd->c_datalen
):(cmd->c_blklen));
948 blkcount = cmd->c_datalen / blksize;
949 if (cmd->c_datalen % blksize > 0) {
950 /* XXX: Split this command. (1.7.4) */
951 printf("%s: data not a multiple of %d bytes\n",
952 DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname), blksize);
953 return EINVAL22;
954 }
955 }
956
957 /* Check limit imposed by 9-bit block count. (1.7.2) */
958 if (blkcount > SDHC_BLOCK_COUNT_MAX512) {
959 printf("%s: too much data\n", DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname));
960 return EINVAL22;
961 }
962
963 /* Prepare transfer mode register value. (2.2.5) */
964 mode = 0;
965 if (ISSET(cmd->c_flags, SCF_CMD_READ)((cmd->c_flags) & (0x0040)))
966 mode |= SDHC_READ_MODE(1<<4);
967 if (blkcount > 0) {
968 mode |= SDHC_BLOCK_COUNT_ENABLE(1<<1);
969 if (blkcount > 1) {
970 mode |= SDHC_MULTI_BLOCK_MODE(1<<5);
971 if (cmd->c_opcode != SD_IO_RW_EXTENDED53)
972 mode |= SDHC_AUTO_CMD12_ENABLE(1<<2);
973 }
974 }
975 if (cmd->c_dmamap && cmd->c_datalen > 0 &&
976 ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001)))
977 mode |= SDHC_DMA_ENABLE(1<<0);
978
979 /*
980 * Prepare command register value. (2.2.6)
981 */
982 command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK0x3f) <<
983 SDHC_COMMAND_INDEX_SHIFT8;
984
985 if (ISSET(cmd->c_flags, SCF_RSP_CRC)((cmd->c_flags) & (0x0400)))
986 command |= SDHC_CRC_CHECK_ENABLE(1<<3);
987 if (ISSET(cmd->c_flags, SCF_RSP_IDX)((cmd->c_flags) & (0x0800)))
988 command |= SDHC_INDEX_CHECK_ENABLE(1<<4);
989 if (cmd->c_data != NULL((void *)0))
990 command |= SDHC_DATA_PRESENT_SELECT(1<<5);
991
992 if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT)((cmd->c_flags) & (0x1000)))
993 command |= SDHC_NO_RESPONSE(0<<0);
994 else if (ISSET(cmd->c_flags, SCF_RSP_136)((cmd->c_flags) & (0x0200)))
995 command |= SDHC_RESP_LEN_136(1<<0);
996 else if (ISSET(cmd->c_flags, SCF_RSP_BSY)((cmd->c_flags) & (0x0100)))
997 command |= SDHC_RESP_LEN_48_CHK_BUSY(3<<0);
998 else
999 command |= SDHC_RESP_LEN_48(2<<0);
1000
1001 /* Wait until command and data inhibit bits are clear. (1.5) */
1002 if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK0x0003, 0)) != 0)
1003 return error;
1004
1005 s = splsdmmc()splraise(0x3);
1006
1007 /* Alert the user not to remove the card. */
1008 HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((1<<0))));
1009
1010 /* Set DMA start address if SHF_USE_DMA is set. */
1011 if (cmd->c_dmamap && ISSET(hp->flags, SHF_USE_DMA)((hp->flags) & (0x0001))) {
1012 for (seg = 0; seg < cmd->c_dmamap->dm_nsegs; seg++) {
1013 bus_addr_t paddr =
1014 cmd->c_dmamap->dm_segs[seg].ds_addr;
1015 uint16_t len =
1016 cmd->c_dmamap->dm_segs[seg].ds_len == 65536 ?
1017 0 : cmd->c_dmamap->dm_segs[seg].ds_len;
1018 uint16_t attr;
1019
1020 attr = SDHC_ADMA2_VALID(1<<0) | SDHC_ADMA2_ACT_TRANS(2<<4);
1021 if (seg == cmd->c_dmamap->dm_nsegs - 1)
1022 attr |= SDHC_ADMA2_END(1<<1);
1023
1024 if (ISSET(hp->flags, SHF_USE_DMA64)((hp->flags) & (0x0002))) {
1025 desc64[seg].attribute = htole16(attr)((__uint16_t)(attr));
1026 desc64[seg].length = htole16(len)((__uint16_t)(len));
1027 desc64[seg].address_lo =
1028 htole32((uint64_t)paddr & 0xffffffff)((__uint32_t)((uint64_t)paddr & 0xffffffff));
1029 desc64[seg].address_hi =
1030 htole32((uint64_t)paddr >> 32)((__uint32_t)((uint64_t)paddr >> 32));
1031 } else {
1032 desc32[seg].attribute = htole16(attr)((__uint16_t)(attr));
1033 desc32[seg].length = htole16(len)((__uint16_t)(len));
1034 desc32[seg].address = htole32(paddr)((__uint32_t)(paddr));
1035 }
1036 }
1037
1038 if (ISSET(hp->flags, SHF_USE_DMA64)((hp->flags) & (0x0002)))
1039 desc64[cmd->c_dmamap->dm_nsegs].attribute = htole16(0)((__uint16_t)(0));
1040 else
1041 desc32[cmd->c_dmamap->dm_nsegs].attribute = htole16(0)((__uint16_t)(0));
1042
1043 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x04))
1044 BUS_DMASYNC_PREWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x04));
1045
1046 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((3<<3))));
1047 if (ISSET(hp->flags, SHF_USE_DMA64)((hp->flags) & (0x0002)))
1048 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA64)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((3<<3))));
1049 else
1050 HSET1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT_ADMA32)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) | ((2<<3))));
1051
1052 HWRITE4(hp, SDHC_ADMA_SYSTEM_ADDR,(((hp)->iot)->write_4(((hp)->ioh), ((0x58)), ((hp->
adma_map->dm_segs[0].ds_addr))))
1053 hp->adma_map->dm_segs[0].ds_addr)(((hp)->iot)->write_4(((hp)->ioh), ((0x58)), ((hp->
adma_map->dm_segs[0].ds_addr))));
1054 } else
1055 HCLR1(hp, SDHC_HOST_CTL, SDHC_DMA_SELECT)sdhc_write_1(((hp)), ((0x28)), ((sdhc_read_1(((hp)), ((0x28))
)) & ~((3<<3))));
1056
1057 DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n",do {} while(0)
1058 DEVNAME(hp->sc), command, mode, blksize, blkcount))do {} while(0);
1059
1060 /*
1061 * Start a CPU data transfer. Writing to the high order byte
1062 * of the SDHC_COMMAND register triggers the SD command. (1.5)
1063 */
1064 HWRITE2(hp, SDHC_TRANSFER_MODE, mode)sdhc_write_2((hp), (0x0c), (mode));
1065 HWRITE2(hp, SDHC_BLOCK_SIZE, blksize)sdhc_write_2((hp), (0x04), (blksize));
1066 HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount)sdhc_write_2((hp), (0x06), (blkcount));
1067 HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg)(((hp)->iot)->write_4(((hp)->ioh), ((0x08)), ((cmd->
c_arg))));
1068 HWRITE2(hp, SDHC_COMMAND, command)sdhc_write_2((hp), (0x0e), (command));
1069
1070 splx(s)spllower(s);
1071 return 0;
1072}
1073
1074void
1075sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
1076{
1077 struct sdhc_softc *sc = hp->sc;
1078 u_char *datap = cmd->c_data;
1079 int i, datalen;
1080 int mask;
1081 int error;
1082
1083 if (cmd->c_dmamap) {
1084 int status;
1085
1086 error = 0;
1087 for (;;) {
1088 status = sdhc_wait_intr(hp,
1089 SDHC_DMA_INTERRUPT(1<<3)|SDHC_TRANSFER_COMPLETE(1<<1),
1090 SDHC_DMA_TIMEOUT3);
1091 if (status & SDHC_TRANSFER_COMPLETE(1<<1))
1092 break;
1093 if (!status) {
1094 error = ETIMEDOUT60;
1095 break;
1096 }
1097 }
1098
1099 bus_dmamap_sync(sc->sc_dmat, hp->adma_map, 0, PAGE_SIZE,(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x08))
1100 BUS_DMASYNC_POSTWRITE)(*(sc->sc_dmat)->_dmamap_sync)((sc->sc_dmat), (hp->
adma_map), (0), ((1 << 12)), (0x08));
1101 goto done;
1102 }
1103
1104 mask = ISSET(cmd->c_flags, SCF_CMD_READ)((cmd->c_flags) & (0x0040)) ?
1105 SDHC_BUFFER_READ_ENABLE(1<<11) : SDHC_BUFFER_WRITE_ENABLE(1<<10);
1106 error = 0;
1107 datalen = cmd->c_datalen;
1108
1109 DPRINTF(1,("%s: resp=%#x datalen=%d\n", DEVNAME(hp->sc),do {} while(0)
1110 MMC_R1(cmd->c_resp), datalen))do {} while(0);
1111
1112#ifdef SDHC_DEBUG
1113 /* XXX I forgot why I wanted to know when this happens :-( */
1114 if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) &&
1115 ISSET(MMC_R1(cmd->c_resp), 0xcb00)((((cmd->c_resp)[0])) & (0xcb00)))
1116 printf("%s: CMD52/53 error response flags %#x\n",
1117 DEVNAME(hp->sc)((hp->sc)->sc_dev.dv_xname), MMC_R1(cmd->c_resp)((cmd->c_resp)[0]) & 0xff00);
1118#endif
1119
1120 while (datalen > 0) {
1121 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY(1<<5)|
1122 SDHC_BUFFER_WRITE_READY(1<<4), SDHC_BUFFER_TIMEOUT1)) {
1123 error = ETIMEDOUT60;
1124 break;
1125 }
1126
1127 if ((error = sdhc_wait_state(hp, mask, mask)) != 0)
1128 break;
1129
1130 i = MIN(datalen, cmd->c_blklen)(((datalen)<(cmd->c_blklen))?(datalen):(cmd->c_blklen
));
1131 if (ISSET(cmd->c_flags, SCF_CMD_READ)((cmd->c_flags) & (0x0040)))
1132 sdhc_read_data(hp, datap, i);
1133 else
1134 sdhc_write_data(hp, datap, i);
1135
1136 datap += i;
1137 datalen -= i;
1138 }
1139
1140 if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE(1<<1),
1141 SDHC_TRANSFER_TIMEOUT1))
1142 error = ETIMEDOUT60;
1143
1144done:
1145 if (error != 0)
1146 cmd->c_error = error;
1147 SET(cmd->c_flags, SCF_ITSDONE)((cmd->c_flags) |= (0x0001));
1148
1149 DPRINTF(1,("%s: data transfer done (error=%d)\n",do {} while(0)
1150 DEVNAME(hp->sc), cmd->c_error))do {} while(0);
1151}
1152
1153void
1154sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen)
1155{
1156 while (datalen > 3) {
1157 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA)((((hp)->iot)->read_4(((hp)->ioh), ((0x20)))));
1158 datap += 4;
1159 datalen -= 4;
1160 }
1161 if (datalen > 0) {
1162 u_int32_t rv = HREAD4(hp, SDHC_DATA)((((hp)->iot)->read_4(((hp)->ioh), ((0x20)))));
1163 do {
1164 *datap++ = rv & 0xff;
1165 rv = rv >> 8;
1166 } while (--datalen > 0);
1167 }
1168}
1169
1170void
1171sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen)
1172{
1173 while (datalen > 3) {
1174 DPRINTF(3,("%08x\n", *(u_int32_t *)datap))do {} while(0);
1175 HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap))(((hp)->iot)->write_4(((hp)->ioh), ((0x20)), ((*((u_int32_t
*)datap)))));
1176 datap += 4;
1177 datalen -= 4;
1178 }
1179 if (datalen > 0) {
1180 u_int32_t rv = *datap++;
1181 if (datalen > 1)
1182 rv |= *datap++ << 8;
1183 if (datalen > 2)
1184 rv |= *datap++ << 16;
1185 DPRINTF(3,("rv %08x\n", rv))do {} while(0);
1186 HWRITE4(hp, SDHC_DATA, rv)(((hp)->iot)->write_4(((hp)->ioh), ((0x20)), ((rv)))
);
1187 }
1188}
1189
1190/* Prepare for another command. */
1191int
1192sdhc_soft_reset(struct sdhc_host *hp, int mask)
1193{
1194 int timo;
1195
1196 DPRINTF(1,("%s: software reset reg=%#x\n", DEVNAME(hp->sc), mask))do {} while(0);
1197
1198 HWRITE1(hp, SDHC_SOFTWARE_RESET, mask)sdhc_write_1((hp), (0x2f), (mask));
1199 for (timo = 10; timo > 0; timo--) {
1200 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask)(((sdhc_read_1((hp), (0x2f)))) & (mask)))
1201 break;
1202 sdmmc_delay(10000);
1203 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0)sdhc_write_1((hp), (0x2f), (0));
1204 }
1205 if (timo == 0) {
1206 DPRINTF(1,("%s: timeout reg=%#x\n", DEVNAME(hp->sc),do {} while(0)
1207 HREAD1(hp, SDHC_SOFTWARE_RESET)))do {} while(0);
1208 HWRITE1(hp, SDHC_SOFTWARE_RESET, 0)sdhc_write_1((hp), (0x2f), (0));
1209 return (ETIMEDOUT60);
1210 }
1211
1212 return (0);
1213}
1214
1215int
1216sdhc_wait_intr_cold(struct sdhc_host *hp, int mask, int secs)
1217{
1218 int status, usecs;
1219
1220 mask |= SDHC_ERROR_INTERRUPT(1<<15);
1221 usecs = secs * 1000000;
1222 status = hp->intr_status;
1223 while ((status & mask) == 0) {
1224
1225 status = HREAD2(hp, SDHC_NINTR_STATUS)(sdhc_read_2((hp), (0x30)));
1226 if (ISSET(status, SDHC_NINTR_STATUS_MASK)((status) & (0x91ff))) {
1227 HWRITE2(hp, SDHC_NINTR_STATUS, status)sdhc_write_2((hp), (0x30), (status));
1228 if (ISSET(status, SDHC_ERROR_INTERRUPT)((status) & ((1<<15)))) {
1229 uint16_t error;
1230 error = HREAD2(hp, SDHC_EINTR_STATUS)(sdhc_read_2((hp), (0x32)));
1231 HWRITE2(hp, SDHC_EINTR_STATUS, error)sdhc_write_2((hp), (0x32), (error));
1232 hp->intr_status |= status;
1233
1234 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|((error) & ((1<<0)| (1<<4)))
1235 SDHC_DATA_TIMEOUT_ERROR)((error) & ((1<<0)| (1<<4))))
1236 break;
1237 }
1238
1239 if (ISSET(status, SDHC_BUFFER_READ_READY |((status) & ((1<<5) | (1<<4) | (1<<0) |
(1<<1)))
1240 SDHC_BUFFER_WRITE_READY | SDHC_COMMAND_COMPLETE |((status) & ((1<<5) | (1<<4) | (1<<0) |
(1<<1)))
1241 SDHC_TRANSFER_COMPLETE)((status) & ((1<<5) | (1<<4) | (1<<0) |
(1<<1)))) {
1242 hp->intr_status |= status;
1243 break;
1244 }
1245
1246 if (ISSET(status, SDHC_CARD_INTERRUPT)((status) & ((1<<8)))) {
1247 HSET2(hp, SDHC_NINTR_STATUS_EN,sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))))
1248 SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) | ((1<<8))));
1249 }
1250
1251 continue;
1252 }
1253
1254 delay(1)(*delay_func)(1);
1255 if (usecs-- == 0) {
1256 status |= SDHC_ERROR_INTERRUPT(1<<15);
1257 break;
1258 }
1259 }
1260
1261 hp->intr_status &= ~(status & mask);
1262 return (status & mask);
1263}
1264
1265int
1266sdhc_wait_intr(struct sdhc_host *hp, int mask, int secs)
1267{
1268 int status;
1269 int s;
1270
1271 if (cold)
1272 return (sdhc_wait_intr_cold(hp, mask, secs));
1273
1274 mask |= SDHC_ERROR_INTERRUPT(1<<15);
1275
1276 s = splsdmmc()splraise(0x3);
1277 status = hp->intr_status & mask;
1278 while (status == 0) {
1279 if (tsleep_nsec(&hp->intr_status, PWAIT32, "hcintr",
1280 SEC_TO_NSEC(secs)) == EWOULDBLOCK35) {
1281 status |= SDHC_ERROR_INTERRUPT(1<<15);
1282 break;
1283 }
1284 status = hp->intr_status & mask;
1285 }
1286 hp->intr_status &= ~status;
1287
1288 DPRINTF(2,("%s: intr status %#x error %#x\n", DEVNAME(hp->sc), status,do {} while(0)
1289 hp->intr_error_status))do {} while(0);
1290
1291 /* Command timeout has higher priority than command complete. */
1292 if (ISSET(status, SDHC_ERROR_INTERRUPT)((status) & ((1<<15)))) {
1293 hp->intr_error_status = 0;
1294 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT(1<<2)|SDHC_RESET_CMD(1<<1));
1295 status = 0;
1296 }
1297
1298 splx(s)spllower(s);
1299 return status;
1300}
1301
1302/*
1303 * Established by attachment driver at interrupt priority IPL_SDMMC.
1304 */
1305int
1306sdhc_intr(void *arg)
1307{
1308 struct sdhc_softc *sc = arg;
1309 int host;
1310 int done = 0;
1311
1312 /* We got an interrupt, but we don't know from which slot. */
1313 for (host = 0; host < sc->sc_nhosts; host++) {
1314 struct sdhc_host *hp = sc->sc_host[host];
1315 u_int16_t status;
1316
1317 if (hp == NULL((void *)0))
1318 continue;
1319
1320 /* Find out which interrupts are pending. */
1321 status = HREAD2(hp, SDHC_NINTR_STATUS)(sdhc_read_2((hp), (0x30)));
1322 if (!ISSET(status, SDHC_NINTR_STATUS_MASK)((status) & (0x91ff)))
1323 continue; /* no interrupt for us */
1324
1325 /* Acknowledge the interrupts we are about to handle. */
1326 HWRITE2(hp, SDHC_NINTR_STATUS, status)sdhc_write_2((hp), (0x30), (status));
1327 DPRINTF(2,("%s: interrupt status=%b\n", DEVNAME(hp->sc),do {} while(0)
1328 status, SDHC_NINTR_STATUS_BITS))do {} while(0);
1329
1330 /* Claim this interrupt. */
1331 done = 1;
1332
1333 /*
1334 * Service error interrupts.
1335 */
1336 if (ISSET(status, SDHC_ERROR_INTERRUPT)((status) & ((1<<15)))) {
1337 u_int16_t error;
1338
1339 /* Acknowledge error interrupts. */
1340 error = HREAD2(hp, SDHC_EINTR_STATUS)(sdhc_read_2((hp), (0x32)));
1341 HWRITE2(hp, SDHC_EINTR_STATUS, error)sdhc_write_2((hp), (0x32), (error));
1342 DPRINTF(2,("%s: error interrupt, status=%b\n",do {} while(0)
1343 DEVNAME(hp->sc), error, SDHC_EINTR_STATUS_BITS))do {} while(0);
1344
1345 if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|((error) & ((1<<0)| (1<<4)))
1346 SDHC_DATA_TIMEOUT_ERROR)((error) & ((1<<0)| (1<<4)))) {
1347 hp->intr_error_status |= error;
1348 hp->intr_status |= status;
1349 wakeup(&hp->intr_status);
1350 }
1351 }
1352
1353 /*
1354 * Wake up the sdmmc event thread to scan for cards.
1355 */
1356 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION)((status) & ((1<<7)|(1<<6))))
1357 sdmmc_needs_discover(hp->sdmmc);
1358
1359 /*
1360 * Wake up the blocking process to service command
1361 * related interrupt(s).
1362 */
1363 if (ISSET(status, SDHC_BUFFER_READ_READY|((status) & ((1<<5)| (1<<4)|(1<<0)| (1<<
1)))
1364 SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE|((status) & ((1<<5)| (1<<4)|(1<<0)| (1<<
1)))
1365 SDHC_TRANSFER_COMPLETE)((status) & ((1<<5)| (1<<4)|(1<<0)| (1<<
1)))) {
1366 hp->intr_status |= status;
1367 wakeup(&hp->intr_status);
1368 }
1369
1370 /*
1371 * Service SD card interrupts.
1372 */
1373 if (ISSET(status, SDHC_CARD_INTERRUPT)((status) & ((1<<8)))) {
1374 DPRINTF(0,("%s: card interrupt\n", DEVNAME(hp->sc)))do {} while(0);
1375 HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT)sdhc_write_2(((hp)), ((0x34)), ((sdhc_read_2(((hp)), ((0x34))
)) & ~((1<<8))));
1376 sdmmc_card_intr(hp->sdmmc);
1377 }
1378 }
1379 return done;
1380}
1381
1382void
1383sdhc_needs_discover(struct sdhc_softc *sc)
1384{
1385 int host;
1386
1387 for (host = 0; host < sc->sc_nhosts; host++)
1388 sdmmc_needs_discover(sc->sc_host[host]->sdmmc);
1389}
1390
1391#ifdef SDHC_DEBUG
1392void
1393sdhc_dump_regs(struct sdhc_host *hp)
1394{
1395 printf("0x%02x PRESENT_STATE: %b\n", SDHC_PRESENT_STATE0x24,
1396 HREAD4(hp, SDHC_PRESENT_STATE)((((hp)->iot)->read_4(((hp)->ioh), ((0x24))))), SDHC_PRESENT_STATE_BITS"\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC");
1397 printf("0x%02x POWER_CTL: %x\n", SDHC_POWER_CTL0x29,
1398 HREAD1(hp, SDHC_POWER_CTL)(sdhc_read_1((hp), (0x29))));
1399 printf("0x%02x NINTR_STATUS: %x\n", SDHC_NINTR_STATUS0x30,
1400 HREAD2(hp, SDHC_NINTR_STATUS)(sdhc_read_2((hp), (0x30))));
1401 printf("0x%02x EINTR_STATUS: %x\n", SDHC_EINTR_STATUS0x32,
1402 HREAD2(hp, SDHC_EINTR_STATUS)(sdhc_read_2((hp), (0x32))));
1403 printf("0x%02x NINTR_STATUS_EN: %x\n", SDHC_NINTR_STATUS_EN0x34,
1404 HREAD2(hp, SDHC_NINTR_STATUS_EN)(sdhc_read_2((hp), (0x34))));
1405 printf("0x%02x EINTR_STATUS_EN: %x\n", SDHC_EINTR_STATUS_EN0x36,
1406 HREAD2(hp, SDHC_EINTR_STATUS_EN)(sdhc_read_2((hp), (0x36))));
1407 printf("0x%02x NINTR_SIGNAL_EN: %x\n", SDHC_NINTR_SIGNAL_EN0x38,
1408 HREAD2(hp, SDHC_NINTR_SIGNAL_EN)(sdhc_read_2((hp), (0x38))));
1409 printf("0x%02x EINTR_SIGNAL_EN: %x\n", SDHC_EINTR_SIGNAL_EN0x3a,
1410 HREAD2(hp, SDHC_EINTR_SIGNAL_EN)(sdhc_read_2((hp), (0x3a))));
1411 printf("0x%02x CAPABILITIES: %x\n", SDHC_CAPABILITIES0x40,
1412 HREAD4(hp, SDHC_CAPABILITIES)((((hp)->iot)->read_4(((hp)->ioh), ((0x40))))));
1413 printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES0x48,
1414 HREAD4(hp, SDHC_MAX_CAPABILITIES)((((hp)->iot)->read_4(((hp)->ioh), ((0x48))))));
1415}
1416#endif
1417
1418int
1419sdhc_hibernate_init(sdmmc_chipset_handle_t sch, void *fake_softc)
1420{
1421 struct sdhc_host *hp, *fhp;
1422 fhp = fake_softc;
1423 hp = sch;
1424 *fhp = *hp;
1425
1426 return (0);
1427}